1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
36 #include "basic-block.h"
45 /* This file contains the reload pass of the compiler, which is
46 run after register allocation has been done. It checks that
47 each insn is valid (operands required to be in registers really
48 are in registers of the proper class) and fixes up invalid ones
49 by copying values temporarily into registers for the insns
52 The results of register allocation are described by the vector
53 reg_renumber; the insns still contain pseudo regs, but reg_renumber
54 can be used to find which hard reg, if any, a pseudo reg is in.
56 The technique we always use is to free up a few hard regs that are
57 called ``reload regs'', and for each place where a pseudo reg
58 must be in a hard reg, copy it temporarily into one of the reload regs.
60 Reload regs are allocated locally for every instruction that needs
61 reloads. When there are pseudos which are allocated to a register that
62 has been chosen as a reload reg, such pseudos must be ``spilled''.
63 This means that they go to other hard regs, or to stack slots if no other
64 available hard regs can be found. Spilling can invalidate more
65 insns, requiring additional need for reloads, so we must keep checking
66 until the process stabilizes.
68 For machines with different classes of registers, we must keep track
69 of the register class needed for each reload, and make sure that
70 we allocate enough reload registers of each class.
72 The file reload.c contains the code that checks one insn for
73 validity and reports the reloads that it needs. This file
74 is in charge of scanning the entire rtl code, accumulating the
75 reload needs, spilling, assigning reload registers to use for
76 fixing up each insn, and generating the new insns to copy values
77 into the reload registers. */
79 #ifndef REGISTER_MOVE_COST
80 #define REGISTER_MOVE_COST(m, x, y) 2
84 #define LOCAL_REGNO(REGNO) 0
87 /* During reload_as_needed, element N contains a REG rtx for the hard reg
88 into which reg N has been reloaded (perhaps for a previous insn). */
89 static rtx *reg_last_reload_reg;
91 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
92 for an output reload that stores into reg N. */
93 static char *reg_has_output_reload;
95 /* Indicates which hard regs are reload-registers for an output reload
96 in the current insn. */
97 static HARD_REG_SET reg_is_output_reload;
99 /* Element N is the constant value to which pseudo reg N is equivalent,
100 or zero if pseudo reg N is not equivalent to a constant.
101 find_reloads looks at this in order to replace pseudo reg N
102 with the constant it stands for. */
103 rtx *reg_equiv_constant;
105 /* Element N is a memory location to which pseudo reg N is equivalent,
106 prior to any register elimination (such as frame pointer to stack
107 pointer). Depending on whether or not it is a valid address, this value
108 is transferred to either reg_equiv_address or reg_equiv_mem. */
109 rtx *reg_equiv_memory_loc;
111 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
112 This is used when the address is not valid as a memory address
113 (because its displacement is too big for the machine.) */
114 rtx *reg_equiv_address;
116 /* Element N is the memory slot to which pseudo reg N is equivalent,
117 or zero if pseudo reg N is not equivalent to a memory slot. */
120 /* Widest width in which each pseudo reg is referred to (via subreg). */
121 static unsigned int *reg_max_ref_width;
123 /* Element N is the list of insns that initialized reg N from its equivalent
124 constant or memory slot. */
125 static rtx *reg_equiv_init;
127 /* Vector to remember old contents of reg_renumber before spilling. */
128 static short *reg_old_renumber;
130 /* During reload_as_needed, element N contains the last pseudo regno reloaded
131 into hard register N. If that pseudo reg occupied more than one register,
132 reg_reloaded_contents points to that pseudo for each spill register in
133 use; all of these must remain set for an inheritance to occur. */
134 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
136 /* During reload_as_needed, element N contains the insn for which
137 hard register N was last used. Its contents are significant only
138 when reg_reloaded_valid is set for this register. */
139 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
141 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
142 static HARD_REG_SET reg_reloaded_valid;
143 /* Indicate if the register was dead at the end of the reload.
144 This is only valid if reg_reloaded_contents is set and valid. */
145 static HARD_REG_SET reg_reloaded_dead;
147 /* Number of spill-regs so far; number of valid elements of spill_regs. */
150 /* In parallel with spill_regs, contains REG rtx's for those regs.
151 Holds the last rtx used for any given reg, or 0 if it has never
152 been used for spilling yet. This rtx is reused, provided it has
154 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
156 /* In parallel with spill_regs, contains nonzero for a spill reg
157 that was stored after the last time it was used.
158 The precise value is the insn generated to do the store. */
159 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
161 /* This is the register that was stored with spill_reg_store. This is a
162 copy of reload_out / reload_out_reg when the value was stored; if
163 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
164 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
166 /* This table is the inverse mapping of spill_regs:
167 indexed by hard reg number,
168 it contains the position of that reg in spill_regs,
169 or -1 for something that is not in spill_regs.
171 ?!? This is no longer accurate. */
172 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
174 /* This reg set indicates registers that can't be used as spill registers for
175 the currently processed insn. These are the hard registers which are live
176 during the insn, but not allocated to pseudos, as well as fixed
178 static HARD_REG_SET bad_spill_regs;
180 /* These are the hard registers that can't be used as spill register for any
181 insn. This includes registers used for user variables and registers that
182 we can't eliminate. A register that appears in this set also can't be used
183 to retry register allocation. */
184 static HARD_REG_SET bad_spill_regs_global;
186 /* Describes order of use of registers for reloading
187 of spilled pseudo-registers. `n_spills' is the number of
188 elements that are actually valid; new ones are added at the end.
190 Both spill_regs and spill_reg_order are used on two occasions:
191 once during find_reload_regs, where they keep track of the spill registers
192 for a single insn, but also during reload_as_needed where they show all
193 the registers ever used by reload. For the latter case, the information
194 is calculated during finish_spills. */
195 static short spill_regs[FIRST_PSEUDO_REGISTER];
197 /* This vector of reg sets indicates, for each pseudo, which hard registers
198 may not be used for retrying global allocation because the register was
199 formerly spilled from one of them. If we allowed reallocating a pseudo to
200 a register that it was already allocated to, reload might not
202 static HARD_REG_SET *pseudo_previous_regs;
204 /* This vector of reg sets indicates, for each pseudo, which hard
205 registers may not be used for retrying global allocation because they
206 are used as spill registers during one of the insns in which the
208 static HARD_REG_SET *pseudo_forbidden_regs;
210 /* All hard regs that have been used as spill registers for any insn are
211 marked in this set. */
212 static HARD_REG_SET used_spill_regs;
214 /* Index of last register assigned as a spill register. We allocate in
215 a round-robin fashion. */
216 static int last_spill_reg;
218 /* Nonzero if indirect addressing is supported on the machine; this means
219 that spilling (REG n) does not require reloading it into a register in
220 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
221 value indicates the level of indirect addressing supported, e.g., two
222 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
224 static char spill_indirect_levels;
226 /* Nonzero if indirect addressing is supported when the innermost MEM is
227 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
228 which these are valid is the same as spill_indirect_levels, above. */
229 char indirect_symref_ok;
231 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
232 char double_reg_address_ok;
234 /* Record the stack slot for each spilled hard register. */
235 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
237 /* Width allocated so far for that stack slot. */
238 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
240 /* Record which pseudos needed to be spilled. */
241 static regset_head spilled_pseudos;
243 /* Used for communication between order_regs_for_reload and count_pseudo.
244 Used to avoid counting one pseudo twice. */
245 static regset_head pseudos_counted;
247 /* First uid used by insns created by reload in this function.
248 Used in find_equiv_reg. */
249 int reload_first_uid;
251 /* Flag set by local-alloc or global-alloc if anything is live in
252 a call-clobbered reg across calls. */
253 int caller_save_needed;
255 /* Set to 1 while reload_as_needed is operating.
256 Required by some machines to handle any generated moves differently. */
257 int reload_in_progress = 0;
259 /* These arrays record the insn_code of insns that may be needed to
260 perform input and output reloads of special objects. They provide a
261 place to pass a scratch register. */
262 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
263 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
265 /* This obstack is used for allocation of rtl during register elimination.
266 The allocated storage can be freed once find_reloads has processed the
268 struct obstack reload_obstack;
270 /* Points to the beginning of the reload_obstack. All insn_chain structures
271 are allocated first. */
272 char *reload_startobj;
274 /* The point after all insn_chain structures. Used to quickly deallocate
275 memory allocated in copy_reloads during calculate_needs_all_insns. */
276 char *reload_firstobj;
278 /* This points before all local rtl generated by register elimination.
279 Used to quickly free all memory after processing one insn. */
280 static char *reload_insn_firstobj;
282 #define obstack_chunk_alloc xmalloc
283 #define obstack_chunk_free free
285 /* List of insn_chain instructions, one for every insn that reload needs to
287 struct insn_chain *reload_insn_chain;
290 extern tree current_function_decl;
292 extern union tree_node *current_function_decl;
295 /* List of all insns needing reloads. */
296 static struct insn_chain *insns_need_reload;
298 /* This structure is used to record information about register eliminations.
299 Each array entry describes one possible way of eliminating a register
300 in favor of another. If there is more than one way of eliminating a
301 particular register, the most preferred should be specified first. */
305 int from; /* Register number to be eliminated. */
306 int to; /* Register number used as replacement. */
307 int initial_offset; /* Initial difference between values. */
308 int can_eliminate; /* Non-zero if this elimination can be done. */
309 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
310 insns made by reload. */
311 int offset; /* Current offset between the two regs. */
312 int previous_offset; /* Offset at end of previous insn. */
313 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
314 rtx from_rtx; /* REG rtx for the register to be eliminated.
315 We cannot simply compare the number since
316 we might then spuriously replace a hard
317 register corresponding to a pseudo
318 assigned to the reg to be eliminated. */
319 rtx to_rtx; /* REG rtx for the replacement. */
322 static struct elim_table *reg_eliminate = 0;
324 /* This is an intermediate structure to initialize the table. It has
325 exactly the members provided by ELIMINABLE_REGS. */
326 static struct elim_table_1
330 } reg_eliminate_1[] =
332 /* If a set of eliminable registers was specified, define the table from it.
333 Otherwise, default to the normal case of the frame pointer being
334 replaced by the stack pointer. */
336 #ifdef ELIMINABLE_REGS
339 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
342 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
344 /* Record the number of pending eliminations that have an offset not equal
345 to their initial offset. If non-zero, we use a new copy of each
346 replacement result in any insns encountered. */
347 int num_not_at_initial_offset;
349 /* Count the number of registers that we may be able to eliminate. */
350 static int num_eliminable;
351 /* And the number of registers that are equivalent to a constant that
352 can be eliminated to frame_pointer / arg_pointer + constant. */
353 static int num_eliminable_invariants;
355 /* For each label, we record the offset of each elimination. If we reach
356 a label by more than one path and an offset differs, we cannot do the
357 elimination. This information is indexed by the number of the label.
358 The first table is an array of flags that records whether we have yet
359 encountered a label and the second table is an array of arrays, one
360 entry in the latter array for each elimination. */
362 static char *offsets_known_at;
363 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
365 /* Number of labels in the current function. */
367 static int num_labels;
369 static void replace_pseudos_in_call_usage PARAMS((rtx *,
372 static void maybe_fix_stack_asms PARAMS ((void));
373 static void copy_reloads PARAMS ((struct insn_chain *));
374 static void calculate_needs_all_insns PARAMS ((int));
375 static int find_reg PARAMS ((struct insn_chain *, int));
376 static void find_reload_regs PARAMS ((struct insn_chain *));
377 static void select_reload_regs PARAMS ((void));
378 static void delete_caller_save_insns PARAMS ((void));
380 static void spill_failure PARAMS ((rtx, enum reg_class));
381 static void count_spilled_pseudo PARAMS ((int, int, int));
382 static void delete_dead_insn PARAMS ((rtx));
383 static void alter_reg PARAMS ((int, int));
384 static void set_label_offsets PARAMS ((rtx, rtx, int));
385 static void check_eliminable_occurrences PARAMS ((rtx));
386 static void elimination_effects PARAMS ((rtx, enum machine_mode));
387 static int eliminate_regs_in_insn PARAMS ((rtx, int));
388 static void update_eliminable_offsets PARAMS ((void));
389 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
390 static void set_initial_elim_offsets PARAMS ((void));
391 static void verify_initial_elim_offsets PARAMS ((void));
392 static void set_initial_label_offsets PARAMS ((void));
393 static void set_offsets_for_label PARAMS ((rtx));
394 static void init_elim_table PARAMS ((void));
395 static void update_eliminables PARAMS ((HARD_REG_SET *));
396 static void spill_hard_reg PARAMS ((unsigned int, int));
397 static int finish_spills PARAMS ((int));
398 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
399 static void scan_paradoxical_subregs PARAMS ((rtx));
400 static void count_pseudo PARAMS ((int));
401 static void order_regs_for_reload PARAMS ((struct insn_chain *));
402 static void reload_as_needed PARAMS ((int));
403 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
404 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
405 static void mark_reload_reg_in_use PARAMS ((unsigned int, int,
408 static void clear_reload_reg_in_use PARAMS ((unsigned int, int,
411 static int reload_reg_free_p PARAMS ((unsigned int, int,
413 static int reload_reg_free_for_value_p PARAMS ((int, int, int,
415 rtx, rtx, int, int));
416 static int free_for_value_p PARAMS ((int, enum machine_mode, int,
417 enum reload_type, rtx, rtx,
419 static int reload_reg_reaches_end_p PARAMS ((unsigned int, int,
421 static int allocate_reload_reg PARAMS ((struct insn_chain *, int,
423 static int conflicts_with_override PARAMS ((rtx));
424 static void failed_reload PARAMS ((rtx, int));
425 static int set_reload_reg PARAMS ((int, int));
426 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
427 static void choose_reload_regs PARAMS ((struct insn_chain *));
428 static void merge_assigned_reloads PARAMS ((rtx));
429 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
430 struct reload *, rtx, int));
431 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
432 struct reload *, int));
433 static void do_input_reload PARAMS ((struct insn_chain *,
434 struct reload *, int));
435 static void do_output_reload PARAMS ((struct insn_chain *,
436 struct reload *, int));
437 static void emit_reload_insns PARAMS ((struct insn_chain *));
438 static void delete_output_reload PARAMS ((rtx, int, int));
439 static void delete_address_reloads PARAMS ((rtx, rtx));
440 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
441 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
442 static int constraint_accepts_reg_p PARAMS ((const char *, rtx));
443 static void reload_cse_regs_1 PARAMS ((rtx));
444 static int reload_cse_noop_set_p PARAMS ((rtx));
445 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
446 static int reload_cse_simplify_operands PARAMS ((rtx));
447 static void reload_combine PARAMS ((void));
448 static void reload_combine_note_use PARAMS ((rtx *, rtx));
449 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
450 static void reload_cse_move2add PARAMS ((rtx));
451 static void move2add_note_store PARAMS ((rtx, rtx, void *));
453 static void add_auto_inc_notes PARAMS ((rtx, rtx));
455 static void copy_eh_notes PARAMS ((rtx, rtx));
456 static HOST_WIDE_INT sext_for_mode PARAMS ((enum machine_mode,
458 static void failed_reload PARAMS ((rtx, int));
459 static int set_reload_reg PARAMS ((int, int));
460 static void reload_cse_delete_noop_set PARAMS ((rtx, rtx));
461 static void reload_cse_simplify PARAMS ((rtx));
462 static void fixup_abnormal_edges PARAMS ((void));
463 extern void dump_needs PARAMS ((struct insn_chain *));
465 /* Initialize the reload pass once per compilation. */
472 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
473 Set spill_indirect_levels to the number of levels such addressing is
474 permitted, zero if it is not permitted at all. */
477 = gen_rtx_MEM (Pmode,
480 LAST_VIRTUAL_REGISTER + 1),
482 spill_indirect_levels = 0;
484 while (memory_address_p (QImode, tem))
486 spill_indirect_levels++;
487 tem = gen_rtx_MEM (Pmode, tem);
490 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
492 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
493 indirect_symref_ok = memory_address_p (QImode, tem);
495 /* See if reg+reg is a valid (and offsettable) address. */
497 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
499 tem = gen_rtx_PLUS (Pmode,
500 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
501 gen_rtx_REG (Pmode, i));
503 /* This way, we make sure that reg+reg is an offsettable address. */
504 tem = plus_constant (tem, 4);
506 if (memory_address_p (QImode, tem))
508 double_reg_address_ok = 1;
513 /* Initialize obstack for our rtl allocation. */
514 gcc_obstack_init (&reload_obstack);
515 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
517 INIT_REG_SET (&spilled_pseudos);
518 INIT_REG_SET (&pseudos_counted);
521 /* List of insn chains that are currently unused. */
522 static struct insn_chain *unused_insn_chains = 0;
524 /* Allocate an empty insn_chain structure. */
528 struct insn_chain *c;
530 if (unused_insn_chains == 0)
532 c = (struct insn_chain *)
533 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
534 INIT_REG_SET (&c->live_throughout);
535 INIT_REG_SET (&c->dead_or_set);
539 c = unused_insn_chains;
540 unused_insn_chains = c->next;
542 c->is_caller_save_insn = 0;
543 c->need_operand_change = 0;
549 /* Small utility function to set all regs in hard reg set TO which are
550 allocated to pseudos in regset FROM. */
553 compute_use_by_pseudos (to, from)
559 EXECUTE_IF_SET_IN_REG_SET
560 (from, FIRST_PSEUDO_REGISTER, regno,
562 int r = reg_renumber[regno];
567 /* reload_combine uses the information from
568 BASIC_BLOCK->global_live_at_start, which might still
569 contain registers that have not actually been allocated
570 since they have an equivalence. */
571 if (! reload_completed)
576 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
578 SET_HARD_REG_BIT (*to, r + nregs);
583 /* Replace all pseudos found in LOC with their corresponding
587 replace_pseudos_in_call_usage (loc, mem_mode, usage)
589 enum machine_mode mem_mode;
603 unsigned int regno = REGNO (x);
605 if (regno < FIRST_PSEUDO_REGISTER)
608 x = eliminate_regs (x, mem_mode, usage);
612 replace_pseudos_in_call_usage (loc, mem_mode, usage);
616 if (reg_equiv_constant[regno])
617 *loc = reg_equiv_constant[regno];
618 else if (reg_equiv_mem[regno])
619 *loc = reg_equiv_mem[regno];
620 else if (reg_equiv_address[regno])
621 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
622 else if (GET_CODE (regno_reg_rtx[regno]) != REG
623 || REGNO (regno_reg_rtx[regno]) != regno)
624 *loc = regno_reg_rtx[regno];
630 else if (code == MEM)
632 replace_pseudos_in_call_usage (& XEXP (x, 0), GET_MODE (x), usage);
636 /* Process each of our operands recursively. */
637 fmt = GET_RTX_FORMAT (code);
638 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
640 replace_pseudos_in_call_usage (&XEXP (x, i), mem_mode, usage);
641 else if (*fmt == 'E')
642 for (j = 0; j < XVECLEN (x, i); j++)
643 replace_pseudos_in_call_usage (& XVECEXP (x, i, j), mem_mode, usage);
647 /* Global variables used by reload and its subroutines. */
649 /* Set during calculate_needs if an insn needs register elimination. */
650 static int something_needs_elimination;
651 /* Set during calculate_needs if an insn needs an operand changed. */
652 int something_needs_operands_changed;
654 /* Nonzero means we couldn't get enough spill regs. */
657 /* Main entry point for the reload pass.
659 FIRST is the first insn of the function being compiled.
661 GLOBAL nonzero means we were called from global_alloc
662 and should attempt to reallocate any pseudoregs that we
663 displace from hard regs we will use for reloads.
664 If GLOBAL is zero, we do not have enough information to do that,
665 so any pseudo reg that is spilled must go to the stack.
667 Return value is nonzero if reload failed
668 and we must not do any more for this function. */
671 reload (first, global)
677 struct elim_table *ep;
679 /* The two pointers used to track the true location of the memory used
680 for label offsets. */
681 char *real_known_ptr = NULL;
682 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
684 /* Make sure even insns with volatile mem refs are recognizable. */
689 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
691 /* Make sure that the last insn in the chain
692 is not something that needs reloading. */
693 emit_note (NULL, NOTE_INSN_DELETED);
695 /* Enable find_equiv_reg to distinguish insns made by reload. */
696 reload_first_uid = get_max_uid ();
698 #ifdef SECONDARY_MEMORY_NEEDED
699 /* Initialize the secondary memory table. */
700 clear_secondary_mem ();
703 /* We don't have a stack slot for any spill reg yet. */
704 memset ((char *) spill_stack_slot, 0, sizeof spill_stack_slot);
705 memset ((char *) spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
707 /* Initialize the save area information for caller-save, in case some
711 /* Compute which hard registers are now in use
712 as homes for pseudo registers.
713 This is done here rather than (eg) in global_alloc
714 because this point is reached even if not optimizing. */
715 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
718 /* A function that receives a nonlocal goto must save all call-saved
720 if (current_function_has_nonlocal_label)
721 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
722 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
723 regs_ever_live[i] = 1;
725 /* Find all the pseudo registers that didn't get hard regs
726 but do have known equivalent constants or memory slots.
727 These include parameters (known equivalent to parameter slots)
728 and cse'd or loop-moved constant memory addresses.
730 Record constant equivalents in reg_equiv_constant
731 so they will be substituted by find_reloads.
732 Record memory equivalents in reg_mem_equiv so they can
733 be substituted eventually by altering the REG-rtx's. */
735 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
736 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
737 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
738 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
739 reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int));
740 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
741 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
742 pseudo_forbidden_regs
743 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
745 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
747 CLEAR_HARD_REG_SET (bad_spill_regs_global);
749 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
750 Also find all paradoxical subregs and find largest such for each pseudo.
751 On machines with small register classes, record hard registers that
752 are used for user variables. These can never be used for spills.
753 Also look for a "constant" REG_SETJMP. This means that all
754 caller-saved registers must be marked live. */
756 num_eliminable_invariants = 0;
757 for (insn = first; insn; insn = NEXT_INSN (insn))
759 rtx set = single_set (insn);
761 /* We may introduce USEs that we want to remove at the end, so
762 we'll mark them with QImode. Make sure there are no
763 previously-marked insns left by say regmove. */
764 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
765 && GET_MODE (insn) != VOIDmode)
766 PUT_MODE (insn, VOIDmode);
768 if (GET_CODE (insn) == CALL_INSN
769 && find_reg_note (insn, REG_SETJMP, NULL))
770 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
771 if (! call_used_regs[i])
772 regs_ever_live[i] = 1;
774 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
776 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
778 #ifdef LEGITIMATE_PIC_OPERAND_P
779 && (! function_invariant_p (XEXP (note, 0))
781 /* A function invariant is often CONSTANT_P but may
782 include a register. We promise to only pass
783 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
784 || (CONSTANT_P (XEXP (note, 0))
785 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))))
789 rtx x = XEXP (note, 0);
790 i = REGNO (SET_DEST (set));
791 if (i > LAST_VIRTUAL_REGISTER)
793 if (GET_CODE (x) == MEM)
795 /* Always unshare the equivalence, so we can
796 substitute into this insn without touching the
798 reg_equiv_memory_loc[i] = copy_rtx (x);
800 else if (function_invariant_p (x))
802 if (GET_CODE (x) == PLUS)
804 /* This is PLUS of frame pointer and a constant,
805 and might be shared. Unshare it. */
806 reg_equiv_constant[i] = copy_rtx (x);
807 num_eliminable_invariants++;
809 else if (x == frame_pointer_rtx
810 || x == arg_pointer_rtx)
812 reg_equiv_constant[i] = x;
813 num_eliminable_invariants++;
815 else if (LEGITIMATE_CONSTANT_P (x))
816 reg_equiv_constant[i] = x;
818 reg_equiv_memory_loc[i]
819 = force_const_mem (GET_MODE (SET_DEST (set)), x);
824 /* If this register is being made equivalent to a MEM
825 and the MEM is not SET_SRC, the equivalencing insn
826 is one with the MEM as a SET_DEST and it occurs later.
827 So don't mark this insn now. */
828 if (GET_CODE (x) != MEM
829 || rtx_equal_p (SET_SRC (set), x))
831 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
836 /* If this insn is setting a MEM from a register equivalent to it,
837 this is the equivalencing insn. */
838 else if (set && GET_CODE (SET_DEST (set)) == MEM
839 && GET_CODE (SET_SRC (set)) == REG
840 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
841 && rtx_equal_p (SET_DEST (set),
842 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
843 reg_equiv_init[REGNO (SET_SRC (set))]
844 = gen_rtx_INSN_LIST (VOIDmode, insn,
845 reg_equiv_init[REGNO (SET_SRC (set))]);
848 scan_paradoxical_subregs (PATTERN (insn));
853 num_labels = max_label_num () - get_first_label_num ();
855 /* Allocate the tables used to store offset information at labels. */
856 /* We used to use alloca here, but the size of what it would try to
857 allocate would occasionally cause it to exceed the stack limit and
858 cause a core dump. */
859 real_known_ptr = xmalloc (num_labels);
861 = (int (*)[NUM_ELIMINABLE_REGS])
862 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
864 offsets_known_at = real_known_ptr - get_first_label_num ();
866 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
868 /* Alter each pseudo-reg rtx to contain its hard reg number.
869 Assign stack slots to the pseudos that lack hard regs or equivalents.
870 Do not touch virtual registers. */
872 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
875 /* If we have some registers we think can be eliminated, scan all insns to
876 see if there is an insn that sets one of these registers to something
877 other than itself plus a constant. If so, the register cannot be
878 eliminated. Doing this scan here eliminates an extra pass through the
879 main reload loop in the most common case where register elimination
881 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
882 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
883 || GET_CODE (insn) == CALL_INSN)
884 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
886 maybe_fix_stack_asms ();
888 insns_need_reload = 0;
889 something_needs_elimination = 0;
891 /* Initialize to -1, which means take the first spill register. */
894 /* Spill any hard regs that we know we can't eliminate. */
895 CLEAR_HARD_REG_SET (used_spill_regs);
896 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
897 if (! ep->can_eliminate)
898 spill_hard_reg (ep->from, 1);
900 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
901 if (frame_pointer_needed)
902 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
904 finish_spills (global);
906 /* From now on, we may need to generate moves differently. We may also
907 allow modifications of insns which cause them to not be recognized.
908 Any such modifications will be cleaned up during reload itself. */
909 reload_in_progress = 1;
911 /* This loop scans the entire function each go-round
912 and repeats until one repetition spills no additional hard regs. */
915 int something_changed;
918 HOST_WIDE_INT starting_frame_size;
920 /* Round size of stack frame to stack_alignment_needed. This must be done
921 here because the stack size may be a part of the offset computation
922 for register elimination, and there might have been new stack slots
923 created in the last iteration of this loop. */
924 if (cfun->stack_alignment_needed)
925 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
927 starting_frame_size = get_frame_size ();
929 set_initial_elim_offsets ();
930 set_initial_label_offsets ();
932 /* For each pseudo register that has an equivalent location defined,
933 try to eliminate any eliminable registers (such as the frame pointer)
934 assuming initial offsets for the replacement register, which
937 If the resulting location is directly addressable, substitute
938 the MEM we just got directly for the old REG.
940 If it is not addressable but is a constant or the sum of a hard reg
941 and constant, it is probably not addressable because the constant is
942 out of range, in that case record the address; we will generate
943 hairy code to compute the address in a register each time it is
944 needed. Similarly if it is a hard register, but one that is not
945 valid as an address register.
947 If the location is not addressable, but does not have one of the
948 above forms, assign a stack slot. We have to do this to avoid the
949 potential of producing lots of reloads if, e.g., a location involves
950 a pseudo that didn't get a hard register and has an equivalent memory
951 location that also involves a pseudo that didn't get a hard register.
953 Perhaps at some point we will improve reload_when_needed handling
954 so this problem goes away. But that's very hairy. */
956 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
957 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
959 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
961 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
963 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
964 else if (CONSTANT_P (XEXP (x, 0))
965 || (GET_CODE (XEXP (x, 0)) == REG
966 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
967 || (GET_CODE (XEXP (x, 0)) == PLUS
968 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
969 && (REGNO (XEXP (XEXP (x, 0), 0))
970 < FIRST_PSEUDO_REGISTER)
971 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
972 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
975 /* Make a new stack slot. Then indicate that something
976 changed so we go back and recompute offsets for
977 eliminable registers because the allocation of memory
978 below might change some offset. reg_equiv_{mem,address}
979 will be set up for this pseudo on the next pass around
981 reg_equiv_memory_loc[i] = 0;
982 reg_equiv_init[i] = 0;
987 if (caller_save_needed)
990 /* If we allocated another stack slot, redo elimination bookkeeping. */
991 if (starting_frame_size != get_frame_size ())
994 if (caller_save_needed)
996 save_call_clobbered_regs ();
997 /* That might have allocated new insn_chain structures. */
998 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1001 calculate_needs_all_insns (global);
1003 CLEAR_REG_SET (&spilled_pseudos);
1006 something_changed = 0;
1008 /* If we allocated any new memory locations, make another pass
1009 since it might have changed elimination offsets. */
1010 if (starting_frame_size != get_frame_size ())
1011 something_changed = 1;
1014 HARD_REG_SET to_spill;
1015 CLEAR_HARD_REG_SET (to_spill);
1016 update_eliminables (&to_spill);
1017 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1018 if (TEST_HARD_REG_BIT (to_spill, i))
1020 spill_hard_reg (i, 1);
1023 /* Regardless of the state of spills, if we previously had
1024 a register that we thought we could eliminate, but no can
1025 not eliminate, we must run another pass.
1027 Consider pseudos which have an entry in reg_equiv_* which
1028 reference an eliminable register. We must make another pass
1029 to update reg_equiv_* so that we do not substitute in the
1030 old value from when we thought the elimination could be
1032 something_changed = 1;
1036 select_reload_regs ();
1040 if (insns_need_reload != 0 || did_spill)
1041 something_changed |= finish_spills (global);
1043 if (! something_changed)
1046 if (caller_save_needed)
1047 delete_caller_save_insns ();
1049 obstack_free (&reload_obstack, reload_firstobj);
1052 /* If global-alloc was run, notify it of any register eliminations we have
1055 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1056 if (ep->can_eliminate)
1057 mark_elimination (ep->from, ep->to);
1059 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1060 If that insn didn't set the register (i.e., it copied the register to
1061 memory), just delete that insn instead of the equivalencing insn plus
1062 anything now dead. If we call delete_dead_insn on that insn, we may
1063 delete the insn that actually sets the register if the register dies
1064 there and that is incorrect. */
1066 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1068 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1071 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1073 rtx equiv_insn = XEXP (list, 0);
1074 if (GET_CODE (equiv_insn) == NOTE)
1076 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1077 delete_dead_insn (equiv_insn);
1080 PUT_CODE (equiv_insn, NOTE);
1081 NOTE_SOURCE_FILE (equiv_insn) = 0;
1082 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1088 /* Use the reload registers where necessary
1089 by generating move instructions to move the must-be-register
1090 values into or out of the reload registers. */
1092 if (insns_need_reload != 0 || something_needs_elimination
1093 || something_needs_operands_changed)
1095 HOST_WIDE_INT old_frame_size = get_frame_size ();
1097 reload_as_needed (global);
1099 if (old_frame_size != get_frame_size ())
1103 verify_initial_elim_offsets ();
1106 /* If we were able to eliminate the frame pointer, show that it is no
1107 longer live at the start of any basic block. If it ls live by
1108 virtue of being in a pseudo, that pseudo will be marked live
1109 and hence the frame pointer will be known to be live via that
1112 if (! frame_pointer_needed)
1113 for (i = 0; i < n_basic_blocks; i++)
1114 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
1115 HARD_FRAME_POINTER_REGNUM);
1117 /* Come here (with failure set nonzero) if we can't get enough spill regs
1118 and we decide not to abort about it. */
1121 CLEAR_REG_SET (&spilled_pseudos);
1122 reload_in_progress = 0;
1124 /* Now eliminate all pseudo regs by modifying them into
1125 their equivalent memory references.
1126 The REG-rtx's for the pseudos are modified in place,
1127 so all insns that used to refer to them now refer to memory.
1129 For a reg that has a reg_equiv_address, all those insns
1130 were changed by reloading so that no insns refer to it any longer;
1131 but the DECL_RTL of a variable decl may refer to it,
1132 and if so this causes the debugging info to mention the variable. */
1134 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1138 if (reg_equiv_mem[i])
1139 addr = XEXP (reg_equiv_mem[i], 0);
1141 if (reg_equiv_address[i])
1142 addr = reg_equiv_address[i];
1146 if (reg_renumber[i] < 0)
1148 rtx reg = regno_reg_rtx[i];
1150 PUT_CODE (reg, MEM);
1151 XEXP (reg, 0) = addr;
1152 REG_USERVAR_P (reg) = 0;
1153 if (reg_equiv_memory_loc[i])
1154 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1157 RTX_UNCHANGING_P (reg) = MEM_IN_STRUCT_P (reg)
1158 = MEM_SCALAR_P (reg) = 0;
1159 MEM_ATTRS (reg) = 0;
1162 else if (reg_equiv_mem[i])
1163 XEXP (reg_equiv_mem[i], 0) = addr;
1167 /* We must set reload_completed now since the cleanup_subreg_operands call
1168 below will re-recognize each insn and reload may have generated insns
1169 which are only valid during and after reload. */
1170 reload_completed = 1;
1172 /* Make a pass over all the insns and delete all USEs which we inserted
1173 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1174 notes. Delete all CLOBBER insns that don't refer to the return value
1175 and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1176 REG_LIBCALL notes since they are no longer useful or accurate. Strip
1177 and regenerate REG_INC notes that may have been moved around. */
1179 for (insn = first; insn; insn = NEXT_INSN (insn))
1184 if (GET_CODE (insn) == CALL_INSN)
1185 replace_pseudos_in_call_usage (& CALL_INSN_FUNCTION_USAGE (insn),
1187 CALL_INSN_FUNCTION_USAGE (insn));
1189 if ((GET_CODE (PATTERN (insn)) == USE
1190 /* We mark with QImode USEs introduced by reload itself. */
1191 && (GET_MODE (insn) == QImode
1192 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1193 || (GET_CODE (PATTERN (insn)) == CLOBBER
1194 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1195 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1201 pnote = ®_NOTES (insn);
1204 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1205 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1206 || REG_NOTE_KIND (*pnote) == REG_INC
1207 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1208 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1209 *pnote = XEXP (*pnote, 1);
1211 pnote = &XEXP (*pnote, 1);
1215 add_auto_inc_notes (insn, PATTERN (insn));
1218 /* And simplify (subreg (reg)) if it appears as an operand. */
1219 cleanup_subreg_operands (insn);
1222 /* If we are doing stack checking, give a warning if this function's
1223 frame size is larger than we expect. */
1224 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1226 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1227 static int verbose_warned = 0;
1229 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1230 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1231 size += UNITS_PER_WORD;
1233 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1235 warning ("frame size too large for reliable stack checking");
1236 if (! verbose_warned)
1238 warning ("try reducing the number of local variables");
1244 /* Indicate that we no longer have known memory locations or constants. */
1245 if (reg_equiv_constant)
1246 free (reg_equiv_constant);
1247 reg_equiv_constant = 0;
1248 if (reg_equiv_memory_loc)
1249 free (reg_equiv_memory_loc);
1250 reg_equiv_memory_loc = 0;
1253 free (real_known_ptr);
1257 free (reg_equiv_mem);
1258 free (reg_equiv_init);
1259 free (reg_equiv_address);
1260 free (reg_max_ref_width);
1261 free (reg_old_renumber);
1262 free (pseudo_previous_regs);
1263 free (pseudo_forbidden_regs);
1265 CLEAR_HARD_REG_SET (used_spill_regs);
1266 for (i = 0; i < n_spills; i++)
1267 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1269 /* Free all the insn_chain structures at once. */
1270 obstack_free (&reload_obstack, reload_startobj);
1271 unused_insn_chains = 0;
1272 fixup_abnormal_edges ();
1277 /* Yet another special case. Unfortunately, reg-stack forces people to
1278 write incorrect clobbers in asm statements. These clobbers must not
1279 cause the register to appear in bad_spill_regs, otherwise we'll call
1280 fatal_insn later. We clear the corresponding regnos in the live
1281 register sets to avoid this.
1282 The whole thing is rather sick, I'm afraid. */
1285 maybe_fix_stack_asms ()
1288 const char *constraints[MAX_RECOG_OPERANDS];
1289 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1290 struct insn_chain *chain;
1292 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1295 HARD_REG_SET clobbered, allowed;
1298 if (! INSN_P (chain->insn)
1299 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1301 pat = PATTERN (chain->insn);
1302 if (GET_CODE (pat) != PARALLEL)
1305 CLEAR_HARD_REG_SET (clobbered);
1306 CLEAR_HARD_REG_SET (allowed);
1308 /* First, make a mask of all stack regs that are clobbered. */
1309 for (i = 0; i < XVECLEN (pat, 0); i++)
1311 rtx t = XVECEXP (pat, 0, i);
1312 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1313 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1316 /* Get the operand values and constraints out of the insn. */
1317 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1318 constraints, operand_mode);
1320 /* For every operand, see what registers are allowed. */
1321 for (i = 0; i < noperands; i++)
1323 const char *p = constraints[i];
1324 /* For every alternative, we compute the class of registers allowed
1325 for reloading in CLS, and merge its contents into the reg set
1327 int cls = (int) NO_REGS;
1333 if (c == '\0' || c == ',' || c == '#')
1335 /* End of one alternative - mark the regs in the current
1336 class, and reset the class. */
1337 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1342 } while (c != '\0' && c != ',');
1350 case '=': case '+': case '*': case '%': case '?': case '!':
1351 case '0': case '1': case '2': case '3': case '4': case 'm':
1352 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1353 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1354 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1359 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1364 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1368 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1373 /* Those of the registers which are clobbered, but allowed by the
1374 constraints, must be usable as reload registers. So clear them
1375 out of the life information. */
1376 AND_HARD_REG_SET (allowed, clobbered);
1377 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1378 if (TEST_HARD_REG_BIT (allowed, i))
1380 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1381 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1388 /* Copy the global variables n_reloads and rld into the corresponding elts
1391 copy_reloads (chain)
1392 struct insn_chain *chain;
1394 chain->n_reloads = n_reloads;
1396 = (struct reload *) obstack_alloc (&reload_obstack,
1397 n_reloads * sizeof (struct reload));
1398 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1399 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1402 /* Walk the chain of insns, and determine for each whether it needs reloads
1403 and/or eliminations. Build the corresponding insns_need_reload list, and
1404 set something_needs_elimination as appropriate. */
1406 calculate_needs_all_insns (global)
1409 struct insn_chain **pprev_reload = &insns_need_reload;
1410 struct insn_chain *chain, *next = 0;
1412 something_needs_elimination = 0;
1414 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1415 for (chain = reload_insn_chain; chain != 0; chain = next)
1417 rtx insn = chain->insn;
1421 /* Clear out the shortcuts. */
1422 chain->n_reloads = 0;
1423 chain->need_elim = 0;
1424 chain->need_reload = 0;
1425 chain->need_operand_change = 0;
1427 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1428 include REG_LABEL), we need to see what effects this has on the
1429 known offsets at labels. */
1431 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1432 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1433 set_label_offsets (insn, insn, 0);
1437 rtx old_body = PATTERN (insn);
1438 int old_code = INSN_CODE (insn);
1439 rtx old_notes = REG_NOTES (insn);
1440 int did_elimination = 0;
1441 int operands_changed = 0;
1442 rtx set = single_set (insn);
1444 /* Skip insns that only set an equivalence. */
1445 if (set && GET_CODE (SET_DEST (set)) == REG
1446 && reg_renumber[REGNO (SET_DEST (set))] < 0
1447 && reg_equiv_constant[REGNO (SET_DEST (set))])
1450 /* If needed, eliminate any eliminable registers. */
1451 if (num_eliminable || num_eliminable_invariants)
1452 did_elimination = eliminate_regs_in_insn (insn, 0);
1454 /* Analyze the instruction. */
1455 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1456 global, spill_reg_order);
1458 /* If a no-op set needs more than one reload, this is likely
1459 to be something that needs input address reloads. We
1460 can't get rid of this cleanly later, and it is of no use
1461 anyway, so discard it now.
1462 We only do this when expensive_optimizations is enabled,
1463 since this complements reload inheritance / output
1464 reload deletion, and it can make debugging harder. */
1465 if (flag_expensive_optimizations && n_reloads > 1)
1467 rtx set = single_set (insn);
1469 && SET_SRC (set) == SET_DEST (set)
1470 && GET_CODE (SET_SRC (set)) == REG
1471 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1474 /* Delete it from the reload chain */
1476 chain->prev->next = next;
1478 reload_insn_chain = next;
1480 next->prev = chain->prev;
1481 chain->next = unused_insn_chains;
1482 unused_insn_chains = chain;
1487 update_eliminable_offsets ();
1489 /* Remember for later shortcuts which insns had any reloads or
1490 register eliminations. */
1491 chain->need_elim = did_elimination;
1492 chain->need_reload = n_reloads > 0;
1493 chain->need_operand_change = operands_changed;
1495 /* Discard any register replacements done. */
1496 if (did_elimination)
1498 obstack_free (&reload_obstack, reload_insn_firstobj);
1499 PATTERN (insn) = old_body;
1500 INSN_CODE (insn) = old_code;
1501 REG_NOTES (insn) = old_notes;
1502 something_needs_elimination = 1;
1505 something_needs_operands_changed |= operands_changed;
1509 copy_reloads (chain);
1510 *pprev_reload = chain;
1511 pprev_reload = &chain->next_need_reload;
1518 /* Comparison function for qsort to decide which of two reloads
1519 should be handled first. *P1 and *P2 are the reload numbers. */
1522 reload_reg_class_lower (r1p, r2p)
1526 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1529 /* Consider required reloads before optional ones. */
1530 t = rld[r1].optional - rld[r2].optional;
1534 /* Count all solitary classes before non-solitary ones. */
1535 t = ((reg_class_size[(int) rld[r2].class] == 1)
1536 - (reg_class_size[(int) rld[r1].class] == 1));
1540 /* Aside from solitaires, consider all multi-reg groups first. */
1541 t = rld[r2].nregs - rld[r1].nregs;
1545 /* Consider reloads in order of increasing reg-class number. */
1546 t = (int) rld[r1].class - (int) rld[r2].class;
1550 /* If reloads are equally urgent, sort by reload number,
1551 so that the results of qsort leave nothing to chance. */
1555 /* The cost of spilling each hard reg. */
1556 static int spill_cost[FIRST_PSEUDO_REGISTER];
1558 /* When spilling multiple hard registers, we use SPILL_COST for the first
1559 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1560 only the first hard reg for a multi-reg pseudo. */
1561 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1563 /* Update the spill cost arrays, considering that pseudo REG is live. */
1569 int freq = REG_FREQ (reg);
1570 int r = reg_renumber[reg];
1573 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1574 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1577 SET_REGNO_REG_SET (&pseudos_counted, reg);
1582 spill_add_cost[r] += freq;
1584 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1586 spill_cost[r + nregs] += freq;
1589 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1590 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1593 order_regs_for_reload (chain)
1594 struct insn_chain *chain;
1597 HARD_REG_SET used_by_pseudos;
1598 HARD_REG_SET used_by_pseudos2;
1600 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1602 memset (spill_cost, 0, sizeof spill_cost);
1603 memset (spill_add_cost, 0, sizeof spill_add_cost);
1605 /* Count number of uses of each hard reg by pseudo regs allocated to it
1606 and then order them by decreasing use. First exclude hard registers
1607 that are live in or across this insn. */
1609 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1610 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1611 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1612 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1614 /* Now find out which pseudos are allocated to it, and update
1616 CLEAR_REG_SET (&pseudos_counted);
1618 EXECUTE_IF_SET_IN_REG_SET
1619 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1623 EXECUTE_IF_SET_IN_REG_SET
1624 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1628 CLEAR_REG_SET (&pseudos_counted);
1631 /* Vector of reload-numbers showing the order in which the reloads should
1633 static short reload_order[MAX_RELOADS];
1635 /* This is used to keep track of the spill regs used in one insn. */
1636 static HARD_REG_SET used_spill_regs_local;
1638 /* We decided to spill hard register SPILLED, which has a size of
1639 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1640 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1641 update SPILL_COST/SPILL_ADD_COST. */
1644 count_spilled_pseudo (spilled, spilled_nregs, reg)
1645 int spilled, spilled_nregs, reg;
1647 int r = reg_renumber[reg];
1648 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1650 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1651 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1654 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1656 spill_add_cost[r] -= REG_FREQ (reg);
1658 spill_cost[r + nregs] -= REG_FREQ (reg);
1661 /* Find reload register to use for reload number ORDER. */
1664 find_reg (chain, order)
1665 struct insn_chain *chain;
1668 int rnum = reload_order[order];
1669 struct reload *rl = rld + rnum;
1670 int best_cost = INT_MAX;
1674 HARD_REG_SET not_usable;
1675 HARD_REG_SET used_by_other_reload;
1677 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1678 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1679 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1681 CLEAR_HARD_REG_SET (used_by_other_reload);
1682 for (k = 0; k < order; k++)
1684 int other = reload_order[k];
1686 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1687 for (j = 0; j < rld[other].nregs; j++)
1688 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1691 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1693 unsigned int regno = i;
1695 if (! TEST_HARD_REG_BIT (not_usable, regno)
1696 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1697 && HARD_REGNO_MODE_OK (regno, rl->mode))
1699 int this_cost = spill_cost[regno];
1701 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1703 for (j = 1; j < this_nregs; j++)
1705 this_cost += spill_add_cost[regno + j];
1706 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1707 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1712 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1714 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1716 if (this_cost < best_cost
1717 /* Among registers with equal cost, prefer caller-saved ones, or
1718 use REG_ALLOC_ORDER if it is defined. */
1719 || (this_cost == best_cost
1720 #ifdef REG_ALLOC_ORDER
1721 && (inv_reg_alloc_order[regno]
1722 < inv_reg_alloc_order[best_reg])
1724 && call_used_regs[regno]
1725 && ! call_used_regs[best_reg]
1730 best_cost = this_cost;
1738 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1740 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1741 rl->regno = best_reg;
1743 EXECUTE_IF_SET_IN_REG_SET
1744 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1746 count_spilled_pseudo (best_reg, rl->nregs, j);
1749 EXECUTE_IF_SET_IN_REG_SET
1750 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1752 count_spilled_pseudo (best_reg, rl->nregs, j);
1755 for (i = 0; i < rl->nregs; i++)
1757 if (spill_cost[best_reg + i] != 0
1758 || spill_add_cost[best_reg + i] != 0)
1760 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1765 /* Find more reload regs to satisfy the remaining need of an insn, which
1767 Do it by ascending class number, since otherwise a reg
1768 might be spilled for a big class and might fail to count
1769 for a smaller class even though it belongs to that class. */
1772 find_reload_regs (chain)
1773 struct insn_chain *chain;
1777 /* In order to be certain of getting the registers we need,
1778 we must sort the reloads into order of increasing register class.
1779 Then our grabbing of reload registers will parallel the process
1780 that provided the reload registers. */
1781 for (i = 0; i < chain->n_reloads; i++)
1783 /* Show whether this reload already has a hard reg. */
1784 if (chain->rld[i].reg_rtx)
1786 int regno = REGNO (chain->rld[i].reg_rtx);
1787 chain->rld[i].regno = regno;
1789 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1792 chain->rld[i].regno = -1;
1793 reload_order[i] = i;
1796 n_reloads = chain->n_reloads;
1797 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1799 CLEAR_HARD_REG_SET (used_spill_regs_local);
1802 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1804 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1806 /* Compute the order of preference for hard registers to spill. */
1808 order_regs_for_reload (chain);
1810 for (i = 0; i < n_reloads; i++)
1812 int r = reload_order[i];
1814 /* Ignore reloads that got marked inoperative. */
1815 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1816 && ! rld[r].optional
1817 && rld[r].regno == -1)
1818 if (! find_reg (chain, i))
1820 spill_failure (chain->insn, rld[r].class);
1826 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1827 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1829 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1833 select_reload_regs ()
1835 struct insn_chain *chain;
1837 /* Try to satisfy the needs for each insn. */
1838 for (chain = insns_need_reload; chain != 0;
1839 chain = chain->next_need_reload)
1840 find_reload_regs (chain);
1843 /* Delete all insns that were inserted by emit_caller_save_insns during
1846 delete_caller_save_insns ()
1848 struct insn_chain *c = reload_insn_chain;
1852 while (c != 0 && c->is_caller_save_insn)
1854 struct insn_chain *next = c->next;
1857 if (c == reload_insn_chain)
1858 reload_insn_chain = next;
1862 next->prev = c->prev;
1864 c->prev->next = next;
1865 c->next = unused_insn_chains;
1866 unused_insn_chains = c;
1874 /* Handle the failure to find a register to spill.
1875 INSN should be one of the insns which needed this particular spill reg. */
1878 spill_failure (insn, class)
1880 enum reg_class class;
1882 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1883 if (asm_noperands (PATTERN (insn)) >= 0)
1884 error_for_asm (insn, "Can't find a register in class `%s' while reloading `asm'.",
1885 reg_class_names[class]);
1888 error ("Unable to find a register to spill in class `%s'.",
1889 reg_class_names[class]);
1890 fatal_insn ("This is the insn:", insn);
1894 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1895 data that is dead in INSN. */
1898 delete_dead_insn (insn)
1901 rtx prev = prev_real_insn (insn);
1904 /* If the previous insn sets a register that dies in our insn, delete it
1906 if (prev && GET_CODE (PATTERN (prev)) == SET
1907 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1908 && reg_mentioned_p (prev_dest, PATTERN (insn))
1909 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1910 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1911 delete_dead_insn (prev);
1913 PUT_CODE (insn, NOTE);
1914 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1915 NOTE_SOURCE_FILE (insn) = 0;
1918 /* Modify the home of pseudo-reg I.
1919 The new home is present in reg_renumber[I].
1921 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1922 or it may be -1, meaning there is none or it is not relevant.
1923 This is used so that all pseudos spilled from a given hard reg
1924 can share one stack slot. */
1927 alter_reg (i, from_reg)
1931 /* When outputting an inline function, this can happen
1932 for a reg that isn't actually used. */
1933 if (regno_reg_rtx[i] == 0)
1936 /* If the reg got changed to a MEM at rtl-generation time,
1938 if (GET_CODE (regno_reg_rtx[i]) != REG)
1941 /* Modify the reg-rtx to contain the new hard reg
1942 number or else to contain its pseudo reg number. */
1943 REGNO (regno_reg_rtx[i])
1944 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1946 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1947 allocate a stack slot for it. */
1949 if (reg_renumber[i] < 0
1950 && REG_N_REFS (i) > 0
1951 && reg_equiv_constant[i] == 0
1952 && reg_equiv_memory_loc[i] == 0)
1955 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1956 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1959 /* Each pseudo reg has an inherent size which comes from its own mode,
1960 and a total size which provides room for paradoxical subregs
1961 which refer to the pseudo reg in wider modes.
1963 We can use a slot already allocated if it provides both
1964 enough inherent space and enough total space.
1965 Otherwise, we allocate a new slot, making sure that it has no less
1966 inherent space, and no less total space, then the previous slot. */
1969 /* No known place to spill from => no slot to reuse. */
1970 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1971 inherent_size == total_size ? 0 : -1);
1972 if (BYTES_BIG_ENDIAN)
1973 /* Cancel the big-endian correction done in assign_stack_local.
1974 Get the address of the beginning of the slot.
1975 This is so we can do a big-endian correction unconditionally
1977 adjust = inherent_size - total_size;
1979 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1981 /* Nothing can alias this slot except this pseudo. */
1982 set_mem_alias_set (x, new_alias_set ());
1985 /* Reuse a stack slot if possible. */
1986 else if (spill_stack_slot[from_reg] != 0
1987 && spill_stack_slot_width[from_reg] >= total_size
1988 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1990 x = spill_stack_slot[from_reg];
1992 /* Allocate a bigger slot. */
1995 /* Compute maximum size needed, both for inherent size
1996 and for total size. */
1997 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2000 if (spill_stack_slot[from_reg])
2002 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2004 mode = GET_MODE (spill_stack_slot[from_reg]);
2005 if (spill_stack_slot_width[from_reg] > total_size)
2006 total_size = spill_stack_slot_width[from_reg];
2009 /* Make a slot with that size. */
2010 x = assign_stack_local (mode, total_size,
2011 inherent_size == total_size ? 0 : -1);
2014 /* All pseudos mapped to this slot can alias each other. */
2015 if (spill_stack_slot[from_reg])
2016 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2018 set_mem_alias_set (x, new_alias_set ());
2020 if (BYTES_BIG_ENDIAN)
2022 /* Cancel the big-endian correction done in assign_stack_local.
2023 Get the address of the beginning of the slot.
2024 This is so we can do a big-endian correction unconditionally
2026 adjust = GET_MODE_SIZE (mode) - total_size;
2029 = adjust_address_nv (x, mode_for_size (total_size
2035 spill_stack_slot[from_reg] = stack_slot;
2036 spill_stack_slot_width[from_reg] = total_size;
2039 /* On a big endian machine, the "address" of the slot
2040 is the address of the low part that fits its inherent mode. */
2041 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2042 adjust += (total_size - inherent_size);
2044 /* If we have any adjustment to make, or if the stack slot is the
2045 wrong mode, make a new stack slot. */
2046 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2047 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2049 /* Save the stack slot for later. */
2050 reg_equiv_memory_loc[i] = x;
2054 /* Mark the slots in regs_ever_live for the hard regs
2055 used by pseudo-reg number REGNO. */
2058 mark_home_live (regno)
2063 i = reg_renumber[regno];
2066 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2068 regs_ever_live[i++] = 1;
2071 /* This function handles the tracking of elimination offsets around branches.
2073 X is a piece of RTL being scanned.
2075 INSN is the insn that it came from, if any.
2077 INITIAL_P is non-zero if we are to set the offset to be the initial
2078 offset and zero if we are setting the offset of the label to be the
2082 set_label_offsets (x, insn, initial_p)
2087 enum rtx_code code = GET_CODE (x);
2090 struct elim_table *p;
2095 if (LABEL_REF_NONLOCAL_P (x))
2100 /* ... fall through ... */
2103 /* If we know nothing about this label, set the desired offsets. Note
2104 that this sets the offset at a label to be the offset before a label
2105 if we don't know anything about the label. This is not correct for
2106 the label after a BARRIER, but is the best guess we can make. If
2107 we guessed wrong, we will suppress an elimination that might have
2108 been possible had we been able to guess correctly. */
2110 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2112 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2113 offsets_at[CODE_LABEL_NUMBER (x)][i]
2114 = (initial_p ? reg_eliminate[i].initial_offset
2115 : reg_eliminate[i].offset);
2116 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2119 /* Otherwise, if this is the definition of a label and it is
2120 preceded by a BARRIER, set our offsets to the known offset of
2124 && (tem = prev_nonnote_insn (insn)) != 0
2125 && GET_CODE (tem) == BARRIER)
2126 set_offsets_for_label (insn);
2128 /* If neither of the above cases is true, compare each offset
2129 with those previously recorded and suppress any eliminations
2130 where the offsets disagree. */
2132 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2133 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2134 != (initial_p ? reg_eliminate[i].initial_offset
2135 : reg_eliminate[i].offset))
2136 reg_eliminate[i].can_eliminate = 0;
2141 set_label_offsets (PATTERN (insn), insn, initial_p);
2143 /* ... fall through ... */
2147 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2148 and hence must have all eliminations at their initial offsets. */
2149 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2150 if (REG_NOTE_KIND (tem) == REG_LABEL)
2151 set_label_offsets (XEXP (tem, 0), insn, 1);
2157 /* Each of the labels in the parallel or address vector must be
2158 at their initial offsets. We want the first field for PARALLEL
2159 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2161 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2162 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2167 /* We only care about setting PC. If the source is not RETURN,
2168 IF_THEN_ELSE, or a label, disable any eliminations not at
2169 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2170 isn't one of those possibilities. For branches to a label,
2171 call ourselves recursively.
2173 Note that this can disable elimination unnecessarily when we have
2174 a non-local goto since it will look like a non-constant jump to
2175 someplace in the current function. This isn't a significant
2176 problem since such jumps will normally be when all elimination
2177 pairs are back to their initial offsets. */
2179 if (SET_DEST (x) != pc_rtx)
2182 switch (GET_CODE (SET_SRC (x)))
2189 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2193 tem = XEXP (SET_SRC (x), 1);
2194 if (GET_CODE (tem) == LABEL_REF)
2195 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2196 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2199 tem = XEXP (SET_SRC (x), 2);
2200 if (GET_CODE (tem) == LABEL_REF)
2201 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2202 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2210 /* If we reach here, all eliminations must be at their initial
2211 offset because we are doing a jump to a variable address. */
2212 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2213 if (p->offset != p->initial_offset)
2214 p->can_eliminate = 0;
2222 /* Scan X and replace any eliminable registers (such as fp) with a
2223 replacement (such as sp), plus an offset.
2225 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2226 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2227 MEM, we are allowed to replace a sum of a register and the constant zero
2228 with the register, which we cannot do outside a MEM. In addition, we need
2229 to record the fact that a register is referenced outside a MEM.
2231 If INSN is an insn, it is the insn containing X. If we replace a REG
2232 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2233 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2234 the REG is being modified.
2236 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2237 That's used when we eliminate in expressions stored in notes.
2238 This means, do not set ref_outside_mem even if the reference
2241 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2242 replacements done assuming all offsets are at their initial values. If
2243 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2244 encounter, return the actual location so that find_reloads will do
2245 the proper thing. */
2248 eliminate_regs (x, mem_mode, insn)
2250 enum machine_mode mem_mode;
2253 enum rtx_code code = GET_CODE (x);
2254 struct elim_table *ep;
2261 if (! current_function_decl)
2280 /* This is only for the benefit of the debugging backends, which call
2281 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2282 removed after CSE. */
2283 new = eliminate_regs (XEXP (x, 0), 0, insn);
2284 if (GET_CODE (new) == MEM)
2285 return XEXP (new, 0);
2291 /* First handle the case where we encounter a bare register that
2292 is eliminable. Replace it with a PLUS. */
2293 if (regno < FIRST_PSEUDO_REGISTER)
2295 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2297 if (ep->from_rtx == x && ep->can_eliminate)
2298 return plus_constant (ep->to_rtx, ep->previous_offset);
2301 else if (reg_renumber && reg_renumber[regno] < 0
2302 && reg_equiv_constant && reg_equiv_constant[regno]
2303 && ! CONSTANT_P (reg_equiv_constant[regno]))
2304 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2308 /* You might think handling MINUS in a manner similar to PLUS is a
2309 good idea. It is not. It has been tried multiple times and every
2310 time the change has had to have been reverted.
2312 Other parts of reload know a PLUS is special (gen_reload for example)
2313 and require special code to handle code a reloaded PLUS operand.
2315 Also consider backends where the flags register is clobbered by a
2316 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2317 lea instruction comes to mind). If we try to reload a MINUS, we
2318 may kill the flags register that was holding a useful value.
2320 So, please before trying to handle MINUS, consider reload as a
2321 whole instead of this little section as well as the backend issues. */
2323 /* If this is the sum of an eliminable register and a constant, rework
2325 if (GET_CODE (XEXP (x, 0)) == REG
2326 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2327 && CONSTANT_P (XEXP (x, 1)))
2329 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2331 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2333 /* The only time we want to replace a PLUS with a REG (this
2334 occurs when the constant operand of the PLUS is the negative
2335 of the offset) is when we are inside a MEM. We won't want
2336 to do so at other times because that would change the
2337 structure of the insn in a way that reload can't handle.
2338 We special-case the commonest situation in
2339 eliminate_regs_in_insn, so just replace a PLUS with a
2340 PLUS here, unless inside a MEM. */
2341 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2342 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2345 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2346 plus_constant (XEXP (x, 1),
2347 ep->previous_offset));
2350 /* If the register is not eliminable, we are done since the other
2351 operand is a constant. */
2355 /* If this is part of an address, we want to bring any constant to the
2356 outermost PLUS. We will do this by doing register replacement in
2357 our operands and seeing if a constant shows up in one of them.
2359 Note that there is no risk of modifying the structure of the insn,
2360 since we only get called for its operands, thus we are either
2361 modifying the address inside a MEM, or something like an address
2362 operand of a load-address insn. */
2365 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2366 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2368 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2370 /* If one side is a PLUS and the other side is a pseudo that
2371 didn't get a hard register but has a reg_equiv_constant,
2372 we must replace the constant here since it may no longer
2373 be in the position of any operand. */
2374 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2375 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2376 && reg_renumber[REGNO (new1)] < 0
2377 && reg_equiv_constant != 0
2378 && reg_equiv_constant[REGNO (new1)] != 0)
2379 new1 = reg_equiv_constant[REGNO (new1)];
2380 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2381 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2382 && reg_renumber[REGNO (new0)] < 0
2383 && reg_equiv_constant[REGNO (new0)] != 0)
2384 new0 = reg_equiv_constant[REGNO (new0)];
2386 new = form_sum (new0, new1);
2388 /* As above, if we are not inside a MEM we do not want to
2389 turn a PLUS into something else. We might try to do so here
2390 for an addition of 0 if we aren't optimizing. */
2391 if (! mem_mode && GET_CODE (new) != PLUS)
2392 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2400 /* If this is the product of an eliminable register and a
2401 constant, apply the distribute law and move the constant out
2402 so that we have (plus (mult ..) ..). This is needed in order
2403 to keep load-address insns valid. This case is pathological.
2404 We ignore the possibility of overflow here. */
2405 if (GET_CODE (XEXP (x, 0)) == REG
2406 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2407 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2408 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2410 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2413 /* Refs inside notes don't count for this purpose. */
2414 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2415 || GET_CODE (insn) == INSN_LIST)))
2416 ep->ref_outside_mem = 1;
2419 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2420 ep->previous_offset * INTVAL (XEXP (x, 1)));
2423 /* ... fall through ... */
2427 /* See comments before PLUS about handling MINUS. */
2429 case DIV: case UDIV:
2430 case MOD: case UMOD:
2431 case AND: case IOR: case XOR:
2432 case ROTATERT: case ROTATE:
2433 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2435 case GE: case GT: case GEU: case GTU:
2436 case LE: case LT: case LEU: case LTU:
2438 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2440 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2442 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2443 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2448 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2451 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2452 if (new != XEXP (x, 0))
2454 /* If this is a REG_DEAD note, it is not valid anymore.
2455 Using the eliminated version could result in creating a
2456 REG_DEAD note for the stack or frame pointer. */
2457 if (GET_MODE (x) == REG_DEAD)
2459 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2462 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2466 /* ... fall through ... */
2469 /* Now do eliminations in the rest of the chain. If this was
2470 an EXPR_LIST, this might result in allocating more memory than is
2471 strictly needed, but it simplifies the code. */
2474 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2475 if (new != XEXP (x, 1))
2477 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2485 case STRICT_LOW_PART:
2487 case SIGN_EXTEND: case ZERO_EXTEND:
2488 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2489 case FLOAT: case FIX:
2490 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2494 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2495 if (new != XEXP (x, 0))
2496 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2500 /* Similar to above processing, but preserve SUBREG_BYTE.
2501 Convert (subreg (mem)) to (mem) if not paradoxical.
2502 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2503 pseudo didn't get a hard reg, we must replace this with the
2504 eliminated version of the memory location because push_reloads
2505 may do the replacement in certain circumstances. */
2506 if (GET_CODE (SUBREG_REG (x)) == REG
2507 && (GET_MODE_SIZE (GET_MODE (x))
2508 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2509 && reg_equiv_memory_loc != 0
2510 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2512 new = SUBREG_REG (x);
2515 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2517 if (new != SUBREG_REG (x))
2519 int x_size = GET_MODE_SIZE (GET_MODE (x));
2520 int new_size = GET_MODE_SIZE (GET_MODE (new));
2522 if (GET_CODE (new) == MEM
2523 && ((x_size < new_size
2524 #ifdef WORD_REGISTER_OPERATIONS
2525 /* On these machines, combine can create rtl of the form
2526 (set (subreg:m1 (reg:m2 R) 0) ...)
2527 where m1 < m2, and expects something interesting to
2528 happen to the entire word. Moreover, it will use the
2529 (reg:m2 R) later, expecting all bits to be preserved.
2530 So if the number of words is the same, preserve the
2531 subreg so that push_reloads can see it. */
2532 && ! ((x_size - 1) / UNITS_PER_WORD
2533 == (new_size -1 ) / UNITS_PER_WORD)
2536 || x_size == new_size)
2539 int offset = SUBREG_BYTE (x);
2540 enum machine_mode mode = GET_MODE (x);
2542 PUT_MODE (new, mode);
2543 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2547 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2553 /* This is only for the benefit of the debugging backends, which call
2554 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2555 removed after CSE. */
2556 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2557 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2559 /* Our only special processing is to pass the mode of the MEM to our
2560 recursive call and copy the flags. While we are here, handle this
2561 case more efficiently. */
2563 replace_equiv_address_nv (x,
2564 eliminate_regs (XEXP (x, 0),
2565 GET_MODE (x), insn));
2568 /* Handle insn_list USE that a call to a pure function may generate. */
2569 new = eliminate_regs (XEXP (x, 0), 0, insn);
2570 if (new != XEXP (x, 0))
2571 return gen_rtx_USE (GET_MODE (x), new);
2583 /* Process each of our operands recursively. If any have changed, make a
2585 fmt = GET_RTX_FORMAT (code);
2586 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2590 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2591 if (new != XEXP (x, i) && ! copied)
2593 rtx new_x = rtx_alloc (code);
2595 (sizeof (*new_x) - sizeof (new_x->fld)
2596 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2602 else if (*fmt == 'E')
2605 for (j = 0; j < XVECLEN (x, i); j++)
2607 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2608 if (new != XVECEXP (x, i, j) && ! copied_vec)
2610 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2614 rtx new_x = rtx_alloc (code);
2616 (sizeof (*new_x) - sizeof (new_x->fld)
2617 + (sizeof (new_x->fld[0])
2618 * GET_RTX_LENGTH (code))));
2622 XVEC (x, i) = new_v;
2625 XVECEXP (x, i, j) = new;
2633 /* Scan rtx X for modifications of elimination target registers. Update
2634 the table of eliminables to reflect the changed state. MEM_MODE is
2635 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2638 elimination_effects (x, mem_mode)
2640 enum machine_mode mem_mode;
2643 enum rtx_code code = GET_CODE (x);
2644 struct elim_table *ep;
2670 /* First handle the case where we encounter a bare register that
2671 is eliminable. Replace it with a PLUS. */
2672 if (regno < FIRST_PSEUDO_REGISTER)
2674 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2676 if (ep->from_rtx == x && ep->can_eliminate)
2679 ep->ref_outside_mem = 1;
2684 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2685 && reg_equiv_constant[regno]
2686 && ! CONSTANT_P (reg_equiv_constant[regno]))
2687 elimination_effects (reg_equiv_constant[regno], mem_mode);
2696 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2697 if (ep->to_rtx == XEXP (x, 0))
2699 int size = GET_MODE_SIZE (mem_mode);
2701 /* If more bytes than MEM_MODE are pushed, account for them. */
2702 #ifdef PUSH_ROUNDING
2703 if (ep->to_rtx == stack_pointer_rtx)
2704 size = PUSH_ROUNDING (size);
2706 if (code == PRE_DEC || code == POST_DEC)
2708 else if (code == PRE_INC || code == POST_INC)
2710 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2711 && GET_CODE (XEXP (x, 1)) == PLUS
2712 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2713 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2714 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2717 /* These two aren't unary operators. */
2718 if (code == POST_MODIFY || code == PRE_MODIFY)
2721 /* Fall through to generic unary operation case. */
2722 case STRICT_LOW_PART:
2724 case SIGN_EXTEND: case ZERO_EXTEND:
2725 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2726 case FLOAT: case FIX:
2727 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2731 elimination_effects (XEXP (x, 0), mem_mode);
2735 if (GET_CODE (SUBREG_REG (x)) == REG
2736 && (GET_MODE_SIZE (GET_MODE (x))
2737 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2738 && reg_equiv_memory_loc != 0
2739 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2742 elimination_effects (SUBREG_REG (x), mem_mode);
2746 /* If using a register that is the source of an eliminate we still
2747 think can be performed, note it cannot be performed since we don't
2748 know how this register is used. */
2749 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2750 if (ep->from_rtx == XEXP (x, 0))
2751 ep->can_eliminate = 0;
2753 elimination_effects (XEXP (x, 0), mem_mode);
2757 /* If clobbering a register that is the replacement register for an
2758 elimination we still think can be performed, note that it cannot
2759 be performed. Otherwise, we need not be concerned about it. */
2760 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2761 if (ep->to_rtx == XEXP (x, 0))
2762 ep->can_eliminate = 0;
2764 elimination_effects (XEXP (x, 0), mem_mode);
2768 /* Check for setting a register that we know about. */
2769 if (GET_CODE (SET_DEST (x)) == REG)
2771 /* See if this is setting the replacement register for an
2774 If DEST is the hard frame pointer, we do nothing because we
2775 assume that all assignments to the frame pointer are for
2776 non-local gotos and are being done at a time when they are valid
2777 and do not disturb anything else. Some machines want to
2778 eliminate a fake argument pointer (or even a fake frame pointer)
2779 with either the real frame or the stack pointer. Assignments to
2780 the hard frame pointer must not prevent this elimination. */
2782 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2784 if (ep->to_rtx == SET_DEST (x)
2785 && SET_DEST (x) != hard_frame_pointer_rtx)
2787 /* If it is being incremented, adjust the offset. Otherwise,
2788 this elimination can't be done. */
2789 rtx src = SET_SRC (x);
2791 if (GET_CODE (src) == PLUS
2792 && XEXP (src, 0) == SET_DEST (x)
2793 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2794 ep->offset -= INTVAL (XEXP (src, 1));
2796 ep->can_eliminate = 0;
2800 elimination_effects (SET_DEST (x), 0);
2801 elimination_effects (SET_SRC (x), 0);
2805 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2808 /* Our only special processing is to pass the mode of the MEM to our
2810 elimination_effects (XEXP (x, 0), GET_MODE (x));
2817 fmt = GET_RTX_FORMAT (code);
2818 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2821 elimination_effects (XEXP (x, i), mem_mode);
2822 else if (*fmt == 'E')
2823 for (j = 0; j < XVECLEN (x, i); j++)
2824 elimination_effects (XVECEXP (x, i, j), mem_mode);
2828 /* Descend through rtx X and verify that no references to eliminable registers
2829 remain. If any do remain, mark the involved register as not
2833 check_eliminable_occurrences (x)
2843 code = GET_CODE (x);
2845 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2847 struct elim_table *ep;
2849 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2850 if (ep->from_rtx == x && ep->can_eliminate)
2851 ep->can_eliminate = 0;
2855 fmt = GET_RTX_FORMAT (code);
2856 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2859 check_eliminable_occurrences (XEXP (x, i));
2860 else if (*fmt == 'E')
2863 for (j = 0; j < XVECLEN (x, i); j++)
2864 check_eliminable_occurrences (XVECEXP (x, i, j));
2869 /* Scan INSN and eliminate all eliminable registers in it.
2871 If REPLACE is nonzero, do the replacement destructively. Also
2872 delete the insn as dead it if it is setting an eliminable register.
2874 If REPLACE is zero, do all our allocations in reload_obstack.
2876 If no eliminations were done and this insn doesn't require any elimination
2877 processing (these are not identical conditions: it might be updating sp,
2878 but not referencing fp; this needs to be seen during reload_as_needed so
2879 that the offset between fp and sp can be taken into consideration), zero
2880 is returned. Otherwise, 1 is returned. */
2883 eliminate_regs_in_insn (insn, replace)
2887 int icode = recog_memoized (insn);
2888 rtx old_body = PATTERN (insn);
2889 int insn_is_asm = asm_noperands (old_body) >= 0;
2890 rtx old_set = single_set (insn);
2894 rtx substed_operand[MAX_RECOG_OPERANDS];
2895 rtx orig_operand[MAX_RECOG_OPERANDS];
2896 struct elim_table *ep;
2898 if (! insn_is_asm && icode < 0)
2900 if (GET_CODE (PATTERN (insn)) == USE
2901 || GET_CODE (PATTERN (insn)) == CLOBBER
2902 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2903 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2904 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2909 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2910 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2912 /* Check for setting an eliminable register. */
2913 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2914 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2916 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2917 /* If this is setting the frame pointer register to the
2918 hardware frame pointer register and this is an elimination
2919 that will be done (tested above), this insn is really
2920 adjusting the frame pointer downward to compensate for
2921 the adjustment done before a nonlocal goto. */
2922 if (ep->from == FRAME_POINTER_REGNUM
2923 && ep->to == HARD_FRAME_POINTER_REGNUM)
2925 rtx src = SET_SRC (old_set);
2926 int offset = 0, ok = 0;
2927 rtx prev_insn, prev_set;
2929 if (src == ep->to_rtx)
2931 else if (GET_CODE (src) == PLUS
2932 && GET_CODE (XEXP (src, 0)) == CONST_INT
2933 && XEXP (src, 1) == ep->to_rtx)
2934 offset = INTVAL (XEXP (src, 0)), ok = 1;
2935 else if (GET_CODE (src) == PLUS
2936 && GET_CODE (XEXP (src, 1)) == CONST_INT
2937 && XEXP (src, 0) == ep->to_rtx)
2938 offset = INTVAL (XEXP (src, 1)), ok = 1;
2939 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
2940 && (prev_set = single_set (prev_insn)) != 0
2941 && rtx_equal_p (SET_DEST (prev_set), src))
2943 src = SET_SRC (prev_set);
2944 if (src == ep->to_rtx)
2946 else if (GET_CODE (src) == PLUS
2947 && GET_CODE (XEXP (src, 0)) == CONST_INT
2948 && XEXP (src, 1) == ep->to_rtx)
2949 offset = INTVAL (XEXP (src, 0)), ok = 1;
2950 else if (GET_CODE (src) == PLUS
2951 && GET_CODE (XEXP (src, 1)) == CONST_INT
2952 && XEXP (src, 0) == ep->to_rtx)
2953 offset = INTVAL (XEXP (src, 1)), ok = 1;
2959 = plus_constant (ep->to_rtx, offset - ep->offset);
2961 new_body = old_body;
2964 new_body = copy_insn (old_body);
2965 if (REG_NOTES (insn))
2966 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2968 PATTERN (insn) = new_body;
2969 old_set = single_set (insn);
2971 /* First see if this insn remains valid when we
2972 make the change. If not, keep the INSN_CODE
2973 the same and let reload fit it up. */
2974 validate_change (insn, &SET_SRC (old_set), src, 1);
2975 validate_change (insn, &SET_DEST (old_set),
2977 if (! apply_change_group ())
2979 SET_SRC (old_set) = src;
2980 SET_DEST (old_set) = ep->to_rtx;
2989 /* In this case this insn isn't serving a useful purpose. We
2990 will delete it in reload_as_needed once we know that this
2991 elimination is, in fact, being done.
2993 If REPLACE isn't set, we can't delete this insn, but needn't
2994 process it since it won't be used unless something changes. */
2997 delete_dead_insn (insn);
3005 /* We allow one special case which happens to work on all machines we
3006 currently support: a single set with the source being a PLUS of an
3007 eliminable register and a constant. */
3009 && GET_CODE (SET_DEST (old_set)) == REG
3010 && GET_CODE (SET_SRC (old_set)) == PLUS
3011 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3012 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
3013 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
3015 rtx reg = XEXP (SET_SRC (old_set), 0);
3016 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
3018 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3019 if (ep->from_rtx == reg && ep->can_eliminate)
3021 offset += ep->offset;
3026 /* We assume here that if we need a PARALLEL with
3027 CLOBBERs for this assignment, we can do with the
3028 MATCH_SCRATCHes that add_clobbers allocates.
3029 There's not much we can do if that doesn't work. */
3030 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3034 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3037 rtvec vec = rtvec_alloc (num_clobbers + 1);
3039 vec->elem[0] = PATTERN (insn);
3040 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3041 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3043 if (INSN_CODE (insn) < 0)
3048 new_body = old_body;
3051 new_body = copy_insn (old_body);
3052 if (REG_NOTES (insn))
3053 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3055 PATTERN (insn) = new_body;
3056 old_set = single_set (insn);
3058 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3059 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3062 /* This can't have an effect on elimination offsets, so skip right
3068 /* Determine the effects of this insn on elimination offsets. */
3069 elimination_effects (old_body, 0);
3071 /* Eliminate all eliminable registers occurring in operands that
3072 can be handled by reload. */
3073 extract_insn (insn);
3075 for (i = 0; i < recog_data.n_operands; i++)
3077 orig_operand[i] = recog_data.operand[i];
3078 substed_operand[i] = recog_data.operand[i];
3080 /* For an asm statement, every operand is eliminable. */
3081 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3083 /* Check for setting a register that we know about. */
3084 if (recog_data.operand_type[i] != OP_IN
3085 && GET_CODE (orig_operand[i]) == REG)
3087 /* If we are assigning to a register that can be eliminated, it
3088 must be as part of a PARALLEL, since the code above handles
3089 single SETs. We must indicate that we can no longer
3090 eliminate this reg. */
3091 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3093 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3094 ep->can_eliminate = 0;
3097 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3098 replace ? insn : NULL_RTX);
3099 if (substed_operand[i] != orig_operand[i])
3100 val = any_changes = 1;
3101 /* Terminate the search in check_eliminable_occurrences at
3103 *recog_data.operand_loc[i] = 0;
3105 /* If an output operand changed from a REG to a MEM and INSN is an
3106 insn, write a CLOBBER insn. */
3107 if (recog_data.operand_type[i] != OP_IN
3108 && GET_CODE (orig_operand[i]) == REG
3109 && GET_CODE (substed_operand[i]) == MEM
3111 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3116 for (i = 0; i < recog_data.n_dups; i++)
3117 *recog_data.dup_loc[i]
3118 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3120 /* If any eliminable remain, they aren't eliminable anymore. */
3121 check_eliminable_occurrences (old_body);
3123 /* Substitute the operands; the new values are in the substed_operand
3125 for (i = 0; i < recog_data.n_operands; i++)
3126 *recog_data.operand_loc[i] = substed_operand[i];
3127 for (i = 0; i < recog_data.n_dups; i++)
3128 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3130 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3131 re-recognize the insn. We do this in case we had a simple addition
3132 but now can do this as a load-address. This saves an insn in this
3134 If re-recognition fails, the old insn code number will still be used,
3135 and some register operands may have changed into PLUS expressions.
3136 These will be handled by find_reloads by loading them into a register
3141 /* If we aren't replacing things permanently and we changed something,
3142 make another copy to ensure that all the RTL is new. Otherwise
3143 things can go wrong if find_reload swaps commutative operands
3144 and one is inside RTL that has been copied while the other is not. */
3145 new_body = old_body;
3148 new_body = copy_insn (old_body);
3149 if (REG_NOTES (insn))
3150 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3152 PATTERN (insn) = new_body;
3154 /* If we had a move insn but now we don't, rerecognize it. This will
3155 cause spurious re-recognition if the old move had a PARALLEL since
3156 the new one still will, but we can't call single_set without
3157 having put NEW_BODY into the insn and the re-recognition won't
3158 hurt in this rare case. */
3159 /* ??? Why this huge if statement - why don't we just rerecognize the
3163 && ((GET_CODE (SET_SRC (old_set)) == REG
3164 && (GET_CODE (new_body) != SET
3165 || GET_CODE (SET_SRC (new_body)) != REG))
3166 /* If this was a load from or store to memory, compare
3167 the MEM in recog_data.operand to the one in the insn.
3168 If they are not equal, then rerecognize the insn. */
3170 && ((GET_CODE (SET_SRC (old_set)) == MEM
3171 && SET_SRC (old_set) != recog_data.operand[1])
3172 || (GET_CODE (SET_DEST (old_set)) == MEM
3173 && SET_DEST (old_set) != recog_data.operand[0])))
3174 /* If this was an add insn before, rerecognize. */
3175 || GET_CODE (SET_SRC (old_set)) == PLUS))
3177 int new_icode = recog (PATTERN (insn), insn, 0);
3179 INSN_CODE (insn) = icode;
3183 /* Restore the old body. If there were any changes to it, we made a copy
3184 of it while the changes were still in place, so we'll correctly return
3185 a modified insn below. */
3188 /* Restore the old body. */
3189 for (i = 0; i < recog_data.n_operands; i++)
3190 *recog_data.operand_loc[i] = orig_operand[i];
3191 for (i = 0; i < recog_data.n_dups; i++)
3192 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3195 /* Update all elimination pairs to reflect the status after the current
3196 insn. The changes we make were determined by the earlier call to
3197 elimination_effects.
3199 We also detect a cases where register elimination cannot be done,
3200 namely, if a register would be both changed and referenced outside a MEM
3201 in the resulting insn since such an insn is often undefined and, even if
3202 not, we cannot know what meaning will be given to it. Note that it is
3203 valid to have a register used in an address in an insn that changes it
3204 (presumably with a pre- or post-increment or decrement).
3206 If anything changes, return nonzero. */
3208 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3210 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3211 ep->can_eliminate = 0;
3213 ep->ref_outside_mem = 0;
3215 if (ep->previous_offset != ep->offset)
3220 /* If we changed something, perform elimination in REG_NOTES. This is
3221 needed even when REPLACE is zero because a REG_DEAD note might refer
3222 to a register that we eliminate and could cause a different number
3223 of spill registers to be needed in the final reload pass than in
3225 if (val && REG_NOTES (insn) != 0)
3226 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3231 /* Loop through all elimination pairs.
3232 Recalculate the number not at initial offset.
3234 Compute the maximum offset (minimum offset if the stack does not
3235 grow downward) for each elimination pair. */
3238 update_eliminable_offsets ()
3240 struct elim_table *ep;
3242 num_not_at_initial_offset = 0;
3243 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3245 ep->previous_offset = ep->offset;
3246 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3247 num_not_at_initial_offset++;
3251 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3252 replacement we currently believe is valid, mark it as not eliminable if X
3253 modifies DEST in any way other than by adding a constant integer to it.
3255 If DEST is the frame pointer, we do nothing because we assume that
3256 all assignments to the hard frame pointer are nonlocal gotos and are being
3257 done at a time when they are valid and do not disturb anything else.
3258 Some machines want to eliminate a fake argument pointer with either the
3259 frame or stack pointer. Assignments to the hard frame pointer must not
3260 prevent this elimination.
3262 Called via note_stores from reload before starting its passes to scan
3263 the insns of the function. */
3266 mark_not_eliminable (dest, x, data)
3269 void *data ATTRIBUTE_UNUSED;
3273 /* A SUBREG of a hard register here is just changing its mode. We should
3274 not see a SUBREG of an eliminable hard register, but check just in
3276 if (GET_CODE (dest) == SUBREG)
3277 dest = SUBREG_REG (dest);
3279 if (dest == hard_frame_pointer_rtx)
3282 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3283 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3284 && (GET_CODE (x) != SET
3285 || GET_CODE (SET_SRC (x)) != PLUS
3286 || XEXP (SET_SRC (x), 0) != dest
3287 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3289 reg_eliminate[i].can_eliminate_previous
3290 = reg_eliminate[i].can_eliminate = 0;
3295 /* Verify that the initial elimination offsets did not change since the
3296 last call to set_initial_elim_offsets. This is used to catch cases
3297 where something illegal happened during reload_as_needed that could
3298 cause incorrect code to be generated if we did not check for it. */
3301 verify_initial_elim_offsets ()
3305 #ifdef ELIMINABLE_REGS
3306 struct elim_table *ep;
3308 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3310 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3311 if (t != ep->initial_offset)
3315 INITIAL_FRAME_POINTER_OFFSET (t);
3316 if (t != reg_eliminate[0].initial_offset)
3321 /* Reset all offsets on eliminable registers to their initial values. */
3324 set_initial_elim_offsets ()
3326 struct elim_table *ep = reg_eliminate;
3328 #ifdef ELIMINABLE_REGS
3329 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3331 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3332 ep->previous_offset = ep->offset = ep->initial_offset;
3335 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3336 ep->previous_offset = ep->offset = ep->initial_offset;
3339 num_not_at_initial_offset = 0;
3342 /* Initialize the known label offsets.
3343 Set a known offset for each forced label to be at the initial offset
3344 of each elimination. We do this because we assume that all
3345 computed jumps occur from a location where each elimination is
3346 at its initial offset.
3347 For all other labels, show that we don't know the offsets. */
3350 set_initial_label_offsets ()
3353 memset ((char *) &offsets_known_at[get_first_label_num ()], 0, num_labels);
3355 for (x = forced_labels; x; x = XEXP (x, 1))
3357 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3360 /* Set all elimination offsets to the known values for the code label given
3364 set_offsets_for_label (insn)
3368 int label_nr = CODE_LABEL_NUMBER (insn);
3369 struct elim_table *ep;
3371 num_not_at_initial_offset = 0;
3372 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3374 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3375 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3376 num_not_at_initial_offset++;
3380 /* See if anything that happened changes which eliminations are valid.
3381 For example, on the Sparc, whether or not the frame pointer can
3382 be eliminated can depend on what registers have been used. We need
3383 not check some conditions again (such as flag_omit_frame_pointer)
3384 since they can't have changed. */
3387 update_eliminables (pset)
3390 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3391 int previous_frame_pointer_needed = frame_pointer_needed;
3393 struct elim_table *ep;
3395 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3396 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3397 #ifdef ELIMINABLE_REGS
3398 || ! CAN_ELIMINATE (ep->from, ep->to)
3401 ep->can_eliminate = 0;
3403 /* Look for the case where we have discovered that we can't replace
3404 register A with register B and that means that we will now be
3405 trying to replace register A with register C. This means we can
3406 no longer replace register C with register B and we need to disable
3407 such an elimination, if it exists. This occurs often with A == ap,
3408 B == sp, and C == fp. */
3410 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3412 struct elim_table *op;
3415 if (! ep->can_eliminate && ep->can_eliminate_previous)
3417 /* Find the current elimination for ep->from, if there is a
3419 for (op = reg_eliminate;
3420 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3421 if (op->from == ep->from && op->can_eliminate)
3427 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3429 for (op = reg_eliminate;
3430 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3431 if (op->from == new_to && op->to == ep->to)
3432 op->can_eliminate = 0;
3436 /* See if any registers that we thought we could eliminate the previous
3437 time are no longer eliminable. If so, something has changed and we
3438 must spill the register. Also, recompute the number of eliminable
3439 registers and see if the frame pointer is needed; it is if there is
3440 no elimination of the frame pointer that we can perform. */
3442 frame_pointer_needed = 1;
3443 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3445 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3446 && ep->to != HARD_FRAME_POINTER_REGNUM)
3447 frame_pointer_needed = 0;
3449 if (! ep->can_eliminate && ep->can_eliminate_previous)
3451 ep->can_eliminate_previous = 0;
3452 SET_HARD_REG_BIT (*pset, ep->from);
3457 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3458 /* If we didn't need a frame pointer last time, but we do now, spill
3459 the hard frame pointer. */
3460 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3461 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3465 /* Initialize the table of registers to eliminate. */
3470 struct elim_table *ep;
3471 #ifdef ELIMINABLE_REGS
3472 struct elim_table_1 *ep1;
3476 reg_eliminate = (struct elim_table *)
3477 xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3479 /* Does this function require a frame pointer? */
3481 frame_pointer_needed = (! flag_omit_frame_pointer
3482 #ifdef EXIT_IGNORE_STACK
3483 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3484 and restore sp for alloca. So we can't eliminate
3485 the frame pointer in that case. At some point,
3486 we should improve this by emitting the
3487 sp-adjusting insns for this case. */
3488 || (current_function_calls_alloca
3489 && EXIT_IGNORE_STACK)
3491 || FRAME_POINTER_REQUIRED);
3495 #ifdef ELIMINABLE_REGS
3496 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3497 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3499 ep->from = ep1->from;
3501 ep->can_eliminate = ep->can_eliminate_previous
3502 = (CAN_ELIMINATE (ep->from, ep->to)
3503 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3506 reg_eliminate[0].from = reg_eliminate_1[0].from;
3507 reg_eliminate[0].to = reg_eliminate_1[0].to;
3508 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3509 = ! frame_pointer_needed;
3512 /* Count the number of eliminable registers and build the FROM and TO
3513 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3514 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3515 We depend on this. */
3516 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3518 num_eliminable += ep->can_eliminate;
3519 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3520 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3524 /* Kick all pseudos out of hard register REGNO.
3526 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3527 because we found we can't eliminate some register. In the case, no pseudos
3528 are allowed to be in the register, even if they are only in a block that
3529 doesn't require spill registers, unlike the case when we are spilling this
3530 hard reg to produce another spill register.
3532 Return nonzero if any pseudos needed to be kicked out. */
3535 spill_hard_reg (regno, cant_eliminate)
3543 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3544 regs_ever_live[regno] = 1;
3547 /* Spill every pseudo reg that was allocated to this reg
3548 or to something that overlaps this reg. */
3550 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3551 if (reg_renumber[i] >= 0
3552 && (unsigned int) reg_renumber[i] <= regno
3553 && ((unsigned int) reg_renumber[i]
3554 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3555 PSEUDO_REGNO_MODE (i))
3557 SET_REGNO_REG_SET (&spilled_pseudos, i);
3560 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3561 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3564 ior_hard_reg_set (set1, set2)
3565 HARD_REG_SET *set1, *set2;
3567 IOR_HARD_REG_SET (*set1, *set2);
3570 /* After find_reload_regs has been run for all insn that need reloads,
3571 and/or spill_hard_regs was called, this function is used to actually
3572 spill pseudo registers and try to reallocate them. It also sets up the
3573 spill_regs array for use by choose_reload_regs. */
3576 finish_spills (global)
3579 struct insn_chain *chain;
3580 int something_changed = 0;
3583 /* Build the spill_regs array for the function. */
3584 /* If there are some registers still to eliminate and one of the spill regs
3585 wasn't ever used before, additional stack space may have to be
3586 allocated to store this register. Thus, we may have changed the offset
3587 between the stack and frame pointers, so mark that something has changed.
3589 One might think that we need only set VAL to 1 if this is a call-used
3590 register. However, the set of registers that must be saved by the
3591 prologue is not identical to the call-used set. For example, the
3592 register used by the call insn for the return PC is a call-used register,
3593 but must be saved by the prologue. */
3596 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3597 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3599 spill_reg_order[i] = n_spills;
3600 spill_regs[n_spills++] = i;
3601 if (num_eliminable && ! regs_ever_live[i])
3602 something_changed = 1;
3603 regs_ever_live[i] = 1;
3606 spill_reg_order[i] = -1;
3608 EXECUTE_IF_SET_IN_REG_SET
3609 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3611 /* Record the current hard register the pseudo is allocated to in
3612 pseudo_previous_regs so we avoid reallocating it to the same
3613 hard reg in a later pass. */
3614 if (reg_renumber[i] < 0)
3617 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3618 /* Mark it as no longer having a hard register home. */
3619 reg_renumber[i] = -1;
3620 /* We will need to scan everything again. */
3621 something_changed = 1;
3624 /* Retry global register allocation if possible. */
3627 memset ((char *) pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3628 /* For every insn that needs reloads, set the registers used as spill
3629 regs in pseudo_forbidden_regs for every pseudo live across the
3631 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3633 EXECUTE_IF_SET_IN_REG_SET
3634 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3636 ior_hard_reg_set (pseudo_forbidden_regs + i,
3637 &chain->used_spill_regs);
3639 EXECUTE_IF_SET_IN_REG_SET
3640 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3642 ior_hard_reg_set (pseudo_forbidden_regs + i,
3643 &chain->used_spill_regs);
3647 /* Retry allocating the spilled pseudos. For each reg, merge the
3648 various reg sets that indicate which hard regs can't be used,
3649 and call retry_global_alloc.
3650 We change spill_pseudos here to only contain pseudos that did not
3651 get a new hard register. */
3652 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3653 if (reg_old_renumber[i] != reg_renumber[i])
3655 HARD_REG_SET forbidden;
3656 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3657 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3658 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3659 retry_global_alloc (i, forbidden);
3660 if (reg_renumber[i] >= 0)
3661 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3665 /* Fix up the register information in the insn chain.
3666 This involves deleting those of the spilled pseudos which did not get
3667 a new hard register home from the live_{before,after} sets. */
3668 for (chain = reload_insn_chain; chain; chain = chain->next)
3670 HARD_REG_SET used_by_pseudos;
3671 HARD_REG_SET used_by_pseudos2;
3673 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3674 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3676 /* Mark any unallocated hard regs as available for spills. That
3677 makes inheritance work somewhat better. */
3678 if (chain->need_reload)
3680 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3681 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3682 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3684 /* Save the old value for the sanity test below. */
3685 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3687 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3688 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3689 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3690 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3692 /* Make sure we only enlarge the set. */
3693 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3699 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3700 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3702 int regno = reg_renumber[i];
3703 if (reg_old_renumber[i] == regno)
3706 alter_reg (i, reg_old_renumber[i]);
3707 reg_old_renumber[i] = regno;
3711 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3713 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3714 i, reg_renumber[i]);
3718 return something_changed;
3721 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3722 Also mark any hard registers used to store user variables as
3723 forbidden from being used for spill registers. */
3726 scan_paradoxical_subregs (x)
3731 enum rtx_code code = GET_CODE (x);
3737 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3738 && REG_USERVAR_P (x))
3739 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3755 if (GET_CODE (SUBREG_REG (x)) == REG
3756 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3757 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3758 = GET_MODE_SIZE (GET_MODE (x));
3765 fmt = GET_RTX_FORMAT (code);
3766 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3769 scan_paradoxical_subregs (XEXP (x, i));
3770 else if (fmt[i] == 'E')
3773 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3774 scan_paradoxical_subregs (XVECEXP (x, i, j));
3779 /* Reload pseudo-registers into hard regs around each insn as needed.
3780 Additional register load insns are output before the insn that needs it
3781 and perhaps store insns after insns that modify the reloaded pseudo reg.
3783 reg_last_reload_reg and reg_reloaded_contents keep track of
3784 which registers are already available in reload registers.
3785 We update these for the reloads that we perform,
3786 as the insns are scanned. */
3789 reload_as_needed (live_known)
3792 struct insn_chain *chain;
3793 #if defined (AUTO_INC_DEC)
3798 memset ((char *) spill_reg_rtx, 0, sizeof spill_reg_rtx);
3799 memset ((char *) spill_reg_store, 0, sizeof spill_reg_store);
3800 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3801 reg_has_output_reload = (char *) xmalloc (max_regno);
3802 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3804 set_initial_elim_offsets ();
3806 for (chain = reload_insn_chain; chain; chain = chain->next)
3809 rtx insn = chain->insn;
3810 rtx old_next = NEXT_INSN (insn);
3812 /* If we pass a label, copy the offsets from the label information
3813 into the current offsets of each elimination. */
3814 if (GET_CODE (insn) == CODE_LABEL)
3815 set_offsets_for_label (insn);
3817 else if (INSN_P (insn))
3819 rtx oldpat = PATTERN (insn);
3821 /* If this is a USE and CLOBBER of a MEM, ensure that any
3822 references to eliminable registers have been removed. */
3824 if ((GET_CODE (PATTERN (insn)) == USE
3825 || GET_CODE (PATTERN (insn)) == CLOBBER)
3826 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3827 XEXP (XEXP (PATTERN (insn), 0), 0)
3828 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3829 GET_MODE (XEXP (PATTERN (insn), 0)),
3832 /* If we need to do register elimination processing, do so.
3833 This might delete the insn, in which case we are done. */
3834 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3836 eliminate_regs_in_insn (insn, 1);
3837 if (GET_CODE (insn) == NOTE)
3839 update_eliminable_offsets ();
3844 /* If need_elim is nonzero but need_reload is zero, one might think
3845 that we could simply set n_reloads to 0. However, find_reloads
3846 could have done some manipulation of the insn (such as swapping
3847 commutative operands), and these manipulations are lost during
3848 the first pass for every insn that needs register elimination.
3849 So the actions of find_reloads must be redone here. */
3851 if (! chain->need_elim && ! chain->need_reload
3852 && ! chain->need_operand_change)
3854 /* First find the pseudo regs that must be reloaded for this insn.
3855 This info is returned in the tables reload_... (see reload.h).
3856 Also modify the body of INSN by substituting RELOAD
3857 rtx's for those pseudo regs. */
3860 memset (reg_has_output_reload, 0, max_regno);
3861 CLEAR_HARD_REG_SET (reg_is_output_reload);
3863 find_reloads (insn, 1, spill_indirect_levels, live_known,
3869 rtx next = NEXT_INSN (insn);
3872 prev = PREV_INSN (insn);
3874 /* Now compute which reload regs to reload them into. Perhaps
3875 reusing reload regs from previous insns, or else output
3876 load insns to reload them. Maybe output store insns too.
3877 Record the choices of reload reg in reload_reg_rtx. */
3878 choose_reload_regs (chain);
3880 /* Merge any reloads that we didn't combine for fear of
3881 increasing the number of spill registers needed but now
3882 discover can be safely merged. */
3883 if (SMALL_REGISTER_CLASSES)
3884 merge_assigned_reloads (insn);
3886 /* Generate the insns to reload operands into or out of
3887 their reload regs. */
3888 emit_reload_insns (chain);
3890 /* Substitute the chosen reload regs from reload_reg_rtx
3891 into the insn's body (or perhaps into the bodies of other
3892 load and store insn that we just made for reloading
3893 and that we moved the structure into). */
3894 subst_reloads (insn);
3896 /* If this was an ASM, make sure that all the reload insns
3897 we have generated are valid. If not, give an error
3900 if (asm_noperands (PATTERN (insn)) >= 0)
3901 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3902 if (p != insn && INSN_P (p)
3903 && (recog_memoized (p) < 0
3904 || (extract_insn (p), ! constrain_operands (1))))
3906 error_for_asm (insn,
3907 "`asm' operand requires impossible reload");
3912 if (num_eliminable && chain->need_elim)
3913 update_eliminable_offsets ();
3915 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3916 is no longer validly lying around to save a future reload.
3917 Note that this does not detect pseudos that were reloaded
3918 for this insn in order to be stored in
3919 (obeying register constraints). That is correct; such reload
3920 registers ARE still valid. */
3921 note_stores (oldpat, forget_old_reloads_1, NULL);
3923 /* There may have been CLOBBER insns placed after INSN. So scan
3924 between INSN and NEXT and use them to forget old reloads. */
3925 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3926 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3927 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3930 /* Likewise for regs altered by auto-increment in this insn.
3931 REG_INC notes have been changed by reloading:
3932 find_reloads_address_1 records substitutions for them,
3933 which have been performed by subst_reloads above. */
3934 for (i = n_reloads - 1; i >= 0; i--)
3936 rtx in_reg = rld[i].in_reg;
3939 enum rtx_code code = GET_CODE (in_reg);
3940 /* PRE_INC / PRE_DEC will have the reload register ending up
3941 with the same value as the stack slot, but that doesn't
3942 hold true for POST_INC / POST_DEC. Either we have to
3943 convert the memory access to a true POST_INC / POST_DEC,
3944 or we can't use the reload register for inheritance. */
3945 if ((code == POST_INC || code == POST_DEC)
3946 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3947 REGNO (rld[i].reg_rtx))
3948 /* Make sure it is the inc/dec pseudo, and not
3949 some other (e.g. output operand) pseudo. */
3950 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3951 == REGNO (XEXP (in_reg, 0))))
3954 rtx reload_reg = rld[i].reg_rtx;
3955 enum machine_mode mode = GET_MODE (reload_reg);
3959 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3961 /* We really want to ignore REG_INC notes here, so
3962 use PATTERN (p) as argument to reg_set_p . */
3963 if (reg_set_p (reload_reg, PATTERN (p)))
3965 n = count_occurrences (PATTERN (p), reload_reg, 0);
3970 n = validate_replace_rtx (reload_reg,
3971 gen_rtx (code, mode,
3975 /* We must also verify that the constraints
3976 are met after the replacement. */
3979 n = constrain_operands (1);
3983 /* If the constraints were not met, then
3984 undo the replacement. */
3987 validate_replace_rtx (gen_rtx (code, mode,
3999 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4001 /* Mark this as having an output reload so that the
4002 REG_INC processing code below won't invalidate
4003 the reload for inheritance. */
4004 SET_HARD_REG_BIT (reg_is_output_reload,
4005 REGNO (reload_reg));
4006 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4009 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4012 else if ((code == PRE_INC || code == PRE_DEC)
4013 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4014 REGNO (rld[i].reg_rtx))
4015 /* Make sure it is the inc/dec pseudo, and not
4016 some other (e.g. output operand) pseudo. */
4017 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4018 == REGNO (XEXP (in_reg, 0))))
4020 SET_HARD_REG_BIT (reg_is_output_reload,
4021 REGNO (rld[i].reg_rtx));
4022 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4026 /* If a pseudo that got a hard register is auto-incremented,
4027 we must purge records of copying it into pseudos without
4029 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4030 if (REG_NOTE_KIND (x) == REG_INC)
4032 /* See if this pseudo reg was reloaded in this insn.
4033 If so, its last-reload info is still valid
4034 because it is based on this insn's reload. */
4035 for (i = 0; i < n_reloads; i++)
4036 if (rld[i].out == XEXP (x, 0))
4040 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4044 /* A reload reg's contents are unknown after a label. */
4045 if (GET_CODE (insn) == CODE_LABEL)
4046 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4048 /* Don't assume a reload reg is still good after a call insn
4049 if it is a call-used reg. */
4050 else if (GET_CODE (insn) == CALL_INSN)
4051 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
4055 free (reg_last_reload_reg);
4056 free (reg_has_output_reload);
4059 /* Discard all record of any value reloaded from X,
4060 or reloaded in X from someplace else;
4061 unless X is an output reload reg of the current insn.
4063 X may be a hard reg (the reload reg)
4064 or it may be a pseudo reg that was reloaded from. */
4067 forget_old_reloads_1 (x, ignored, data)
4069 rtx ignored ATTRIBUTE_UNUSED;
4070 void *data ATTRIBUTE_UNUSED;
4076 /* note_stores does give us subregs of hard regs,
4077 subreg_regno_offset will abort if it is not a hard reg. */
4078 while (GET_CODE (x) == SUBREG)
4080 offset += subreg_regno_offset (REGNO (SUBREG_REG (x)),
4081 GET_MODE (SUBREG_REG (x)),
4087 if (GET_CODE (x) != REG)
4090 regno = REGNO (x) + offset;
4092 if (regno >= FIRST_PSEUDO_REGISTER)
4098 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4099 /* Storing into a spilled-reg invalidates its contents.
4100 This can happen if a block-local pseudo is allocated to that reg
4101 and it wasn't spilled because this block's total need is 0.
4102 Then some insn might have an optional reload and use this reg. */
4103 for (i = 0; i < nr; i++)
4104 /* But don't do this if the reg actually serves as an output
4105 reload reg in the current instruction. */
4107 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4109 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4110 spill_reg_store[regno + i] = 0;
4114 /* Since value of X has changed,
4115 forget any value previously copied from it. */
4118 /* But don't forget a copy if this is the output reload
4119 that establishes the copy's validity. */
4120 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4121 reg_last_reload_reg[regno + nr] = 0;
4124 /* The following HARD_REG_SETs indicate when each hard register is
4125 used for a reload of various parts of the current insn. */
4127 /* If reg is unavailable for all reloads. */
4128 static HARD_REG_SET reload_reg_unavailable;
4129 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4130 static HARD_REG_SET reload_reg_used;
4131 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4132 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4133 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4134 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4135 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4136 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4137 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4138 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4139 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4140 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4141 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4142 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4143 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4144 static HARD_REG_SET reload_reg_used_in_op_addr;
4145 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4146 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4147 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4148 static HARD_REG_SET reload_reg_used_in_insn;
4149 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4150 static HARD_REG_SET reload_reg_used_in_other_addr;
4152 /* If reg is in use as a reload reg for any sort of reload. */
4153 static HARD_REG_SET reload_reg_used_at_all;
4155 /* If reg is use as an inherited reload. We just mark the first register
4157 static HARD_REG_SET reload_reg_used_for_inherit;
4159 /* Records which hard regs are used in any way, either as explicit use or
4160 by being allocated to a pseudo during any point of the current insn. */
4161 static HARD_REG_SET reg_used_in_insn;
4163 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4164 TYPE. MODE is used to indicate how many consecutive regs are
4168 mark_reload_reg_in_use (regno, opnum, type, mode)
4171 enum reload_type type;
4172 enum machine_mode mode;
4174 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4177 for (i = regno; i < nregs + regno; i++)
4182 SET_HARD_REG_BIT (reload_reg_used, i);
4185 case RELOAD_FOR_INPUT_ADDRESS:
4186 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4189 case RELOAD_FOR_INPADDR_ADDRESS:
4190 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4193 case RELOAD_FOR_OUTPUT_ADDRESS:
4194 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4197 case RELOAD_FOR_OUTADDR_ADDRESS:
4198 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4201 case RELOAD_FOR_OPERAND_ADDRESS:
4202 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4205 case RELOAD_FOR_OPADDR_ADDR:
4206 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4209 case RELOAD_FOR_OTHER_ADDRESS:
4210 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4213 case RELOAD_FOR_INPUT:
4214 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4217 case RELOAD_FOR_OUTPUT:
4218 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4221 case RELOAD_FOR_INSN:
4222 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4226 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4230 /* Similarly, but show REGNO is no longer in use for a reload. */
4233 clear_reload_reg_in_use (regno, opnum, type, mode)
4236 enum reload_type type;
4237 enum machine_mode mode;
4239 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4240 unsigned int start_regno, end_regno, r;
4242 /* A complication is that for some reload types, inheritance might
4243 allow multiple reloads of the same types to share a reload register.
4244 We set check_opnum if we have to check only reloads with the same
4245 operand number, and check_any if we have to check all reloads. */
4246 int check_opnum = 0;
4248 HARD_REG_SET *used_in_set;
4253 used_in_set = &reload_reg_used;
4256 case RELOAD_FOR_INPUT_ADDRESS:
4257 used_in_set = &reload_reg_used_in_input_addr[opnum];
4260 case RELOAD_FOR_INPADDR_ADDRESS:
4262 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4265 case RELOAD_FOR_OUTPUT_ADDRESS:
4266 used_in_set = &reload_reg_used_in_output_addr[opnum];
4269 case RELOAD_FOR_OUTADDR_ADDRESS:
4271 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4274 case RELOAD_FOR_OPERAND_ADDRESS:
4275 used_in_set = &reload_reg_used_in_op_addr;
4278 case RELOAD_FOR_OPADDR_ADDR:
4280 used_in_set = &reload_reg_used_in_op_addr_reload;
4283 case RELOAD_FOR_OTHER_ADDRESS:
4284 used_in_set = &reload_reg_used_in_other_addr;
4288 case RELOAD_FOR_INPUT:
4289 used_in_set = &reload_reg_used_in_input[opnum];
4292 case RELOAD_FOR_OUTPUT:
4293 used_in_set = &reload_reg_used_in_output[opnum];
4296 case RELOAD_FOR_INSN:
4297 used_in_set = &reload_reg_used_in_insn;
4302 /* We resolve conflicts with remaining reloads of the same type by
4303 excluding the intervals of of reload registers by them from the
4304 interval of freed reload registers. Since we only keep track of
4305 one set of interval bounds, we might have to exclude somewhat
4306 more then what would be necessary if we used a HARD_REG_SET here.
4307 But this should only happen very infrequently, so there should
4308 be no reason to worry about it. */
4310 start_regno = regno;
4311 end_regno = regno + nregs;
4312 if (check_opnum || check_any)
4314 for (i = n_reloads - 1; i >= 0; i--)
4316 if (rld[i].when_needed == type
4317 && (check_any || rld[i].opnum == opnum)
4320 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4321 unsigned int conflict_end
4323 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4325 /* If there is an overlap with the first to-be-freed register,
4326 adjust the interval start. */
4327 if (conflict_start <= start_regno && conflict_end > start_regno)
4328 start_regno = conflict_end;
4329 /* Otherwise, if there is a conflict with one of the other
4330 to-be-freed registers, adjust the interval end. */
4331 if (conflict_start > start_regno && conflict_start < end_regno)
4332 end_regno = conflict_start;
4337 for (r = start_regno; r < end_regno; r++)
4338 CLEAR_HARD_REG_BIT (*used_in_set, r);
4341 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4342 specified by OPNUM and TYPE. */
4345 reload_reg_free_p (regno, opnum, type)
4348 enum reload_type type;
4352 /* In use for a RELOAD_OTHER means it's not available for anything. */
4353 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4354 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4360 /* In use for anything means we can't use it for RELOAD_OTHER. */
4361 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4362 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4363 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4366 for (i = 0; i < reload_n_operands; i++)
4367 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4368 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4369 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4370 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4371 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4372 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4377 case RELOAD_FOR_INPUT:
4378 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4379 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4382 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4385 /* If it is used for some other input, can't use it. */
4386 for (i = 0; i < reload_n_operands; i++)
4387 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4390 /* If it is used in a later operand's address, can't use it. */
4391 for (i = opnum + 1; i < reload_n_operands; i++)
4392 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4393 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4398 case RELOAD_FOR_INPUT_ADDRESS:
4399 /* Can't use a register if it is used for an input address for this
4400 operand or used as an input in an earlier one. */
4401 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4402 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4405 for (i = 0; i < opnum; i++)
4406 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4411 case RELOAD_FOR_INPADDR_ADDRESS:
4412 /* Can't use a register if it is used for an input address
4413 for this operand or used as an input in an earlier
4415 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4418 for (i = 0; i < opnum; i++)
4419 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4424 case RELOAD_FOR_OUTPUT_ADDRESS:
4425 /* Can't use a register if it is used for an output address for this
4426 operand or used as an output in this or a later operand. Note
4427 that multiple output operands are emitted in reverse order, so
4428 the conflicting ones are those with lower indices. */
4429 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4432 for (i = 0; i <= opnum; i++)
4433 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4438 case RELOAD_FOR_OUTADDR_ADDRESS:
4439 /* Can't use a register if it is used for an output address
4440 for this operand or used as an output in this or a
4441 later operand. Note that multiple output operands are
4442 emitted in reverse order, so the conflicting ones are
4443 those with lower indices. */
4444 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4447 for (i = 0; i <= opnum; i++)
4448 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4453 case RELOAD_FOR_OPERAND_ADDRESS:
4454 for (i = 0; i < reload_n_operands; i++)
4455 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4458 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4459 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4461 case RELOAD_FOR_OPADDR_ADDR:
4462 for (i = 0; i < reload_n_operands; i++)
4463 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4466 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4468 case RELOAD_FOR_OUTPUT:
4469 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4470 outputs, or an operand address for this or an earlier output.
4471 Note that multiple output operands are emitted in reverse order,
4472 so the conflicting ones are those with higher indices. */
4473 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4476 for (i = 0; i < reload_n_operands; i++)
4477 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4480 for (i = opnum; i < reload_n_operands; i++)
4481 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4482 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4487 case RELOAD_FOR_INSN:
4488 for (i = 0; i < reload_n_operands; i++)
4489 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4490 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4493 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4494 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4496 case RELOAD_FOR_OTHER_ADDRESS:
4497 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4502 /* Return 1 if the value in reload reg REGNO, as used by a reload
4503 needed for the part of the insn specified by OPNUM and TYPE,
4504 is still available in REGNO at the end of the insn.
4506 We can assume that the reload reg was already tested for availability
4507 at the time it is needed, and we should not check this again,
4508 in case the reg has already been marked in use. */
4511 reload_reg_reaches_end_p (regno, opnum, type)
4514 enum reload_type type;
4521 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4522 its value must reach the end. */
4525 /* If this use is for part of the insn,
4526 its value reaches if no subsequent part uses the same register.
4527 Just like the above function, don't try to do this with lots
4530 case RELOAD_FOR_OTHER_ADDRESS:
4531 /* Here we check for everything else, since these don't conflict
4532 with anything else and everything comes later. */
4534 for (i = 0; i < reload_n_operands; i++)
4535 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4536 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4537 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4538 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4539 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4540 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4543 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4544 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4545 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4547 case RELOAD_FOR_INPUT_ADDRESS:
4548 case RELOAD_FOR_INPADDR_ADDRESS:
4549 /* Similar, except that we check only for this and subsequent inputs
4550 and the address of only subsequent inputs and we do not need
4551 to check for RELOAD_OTHER objects since they are known not to
4554 for (i = opnum; i < reload_n_operands; i++)
4555 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4558 for (i = opnum + 1; i < reload_n_operands; i++)
4559 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4560 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4563 for (i = 0; i < reload_n_operands; i++)
4564 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4565 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4566 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4569 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4572 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4573 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4574 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4576 case RELOAD_FOR_INPUT:
4577 /* Similar to input address, except we start at the next operand for
4578 both input and input address and we do not check for
4579 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4582 for (i = opnum + 1; i < reload_n_operands; i++)
4583 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4584 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4585 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4588 /* ... fall through ... */
4590 case RELOAD_FOR_OPERAND_ADDRESS:
4591 /* Check outputs and their addresses. */
4593 for (i = 0; i < reload_n_operands; i++)
4594 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4595 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4596 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4599 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4601 case RELOAD_FOR_OPADDR_ADDR:
4602 for (i = 0; i < reload_n_operands; i++)
4603 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4604 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4605 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4608 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4609 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4610 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4612 case RELOAD_FOR_INSN:
4613 /* These conflict with other outputs with RELOAD_OTHER. So
4614 we need only check for output addresses. */
4616 opnum = reload_n_operands;
4618 /* ... fall through ... */
4620 case RELOAD_FOR_OUTPUT:
4621 case RELOAD_FOR_OUTPUT_ADDRESS:
4622 case RELOAD_FOR_OUTADDR_ADDRESS:
4623 /* We already know these can't conflict with a later output. So the
4624 only thing to check are later output addresses.
4625 Note that multiple output operands are emitted in reverse order,
4626 so the conflicting ones are those with lower indices. */
4627 for (i = 0; i < opnum; i++)
4628 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4629 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4638 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4641 This function uses the same algorithm as reload_reg_free_p above. */
4644 reloads_conflict (r1, r2)
4647 enum reload_type r1_type = rld[r1].when_needed;
4648 enum reload_type r2_type = rld[r2].when_needed;
4649 int r1_opnum = rld[r1].opnum;
4650 int r2_opnum = rld[r2].opnum;
4652 /* RELOAD_OTHER conflicts with everything. */
4653 if (r2_type == RELOAD_OTHER)
4656 /* Otherwise, check conflicts differently for each type. */
4660 case RELOAD_FOR_INPUT:
4661 return (r2_type == RELOAD_FOR_INSN
4662 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4663 || r2_type == RELOAD_FOR_OPADDR_ADDR
4664 || r2_type == RELOAD_FOR_INPUT
4665 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4666 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4667 && r2_opnum > r1_opnum));
4669 case RELOAD_FOR_INPUT_ADDRESS:
4670 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4671 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4673 case RELOAD_FOR_INPADDR_ADDRESS:
4674 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4675 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4677 case RELOAD_FOR_OUTPUT_ADDRESS:
4678 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4679 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4681 case RELOAD_FOR_OUTADDR_ADDRESS:
4682 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4683 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4685 case RELOAD_FOR_OPERAND_ADDRESS:
4686 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4687 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4689 case RELOAD_FOR_OPADDR_ADDR:
4690 return (r2_type == RELOAD_FOR_INPUT
4691 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4693 case RELOAD_FOR_OUTPUT:
4694 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4695 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4696 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4697 && r2_opnum >= r1_opnum));
4699 case RELOAD_FOR_INSN:
4700 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4701 || r2_type == RELOAD_FOR_INSN
4702 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4704 case RELOAD_FOR_OTHER_ADDRESS:
4705 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4715 /* Indexed by reload number, 1 if incoming value
4716 inherited from previous insns. */
4717 char reload_inherited[MAX_RELOADS];
4719 /* For an inherited reload, this is the insn the reload was inherited from,
4720 if we know it. Otherwise, this is 0. */
4721 rtx reload_inheritance_insn[MAX_RELOADS];
4723 /* If non-zero, this is a place to get the value of the reload,
4724 rather than using reload_in. */
4725 rtx reload_override_in[MAX_RELOADS];
4727 /* For each reload, the hard register number of the register used,
4728 or -1 if we did not need a register for this reload. */
4729 int reload_spill_index[MAX_RELOADS];
4731 /* Subroutine of free_for_value_p, used to check a single register.
4732 START_REGNO is the starting regno of the full reload register
4733 (possibly comprising multiple hard registers) that we are considering. */
4736 reload_reg_free_for_value_p (start_regno, regno, opnum, type, value, out,
4737 reloadnum, ignore_address_reloads)
4738 int start_regno, regno;
4740 enum reload_type type;
4743 int ignore_address_reloads;
4746 /* Set if we see an input reload that must not share its reload register
4747 with any new earlyclobber, but might otherwise share the reload
4748 register with an output or input-output reload. */
4749 int check_earlyclobber = 0;
4753 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4756 if (out == const0_rtx)
4762 /* We use some pseudo 'time' value to check if the lifetimes of the
4763 new register use would overlap with the one of a previous reload
4764 that is not read-only or uses a different value.
4765 The 'time' used doesn't have to be linear in any shape or form, just
4767 Some reload types use different 'buckets' for each operand.
4768 So there are MAX_RECOG_OPERANDS different time values for each
4770 We compute TIME1 as the time when the register for the prospective
4771 new reload ceases to be live, and TIME2 for each existing
4772 reload as the time when that the reload register of that reload
4774 Where there is little to be gained by exact lifetime calculations,
4775 we just make conservative assumptions, i.e. a longer lifetime;
4776 this is done in the 'default:' cases. */
4779 case RELOAD_FOR_OTHER_ADDRESS:
4780 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4781 time1 = copy ? 0 : 1;
4784 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4786 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4787 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4788 respectively, to the time values for these, we get distinct time
4789 values. To get distinct time values for each operand, we have to
4790 multiply opnum by at least three. We round that up to four because
4791 multiply by four is often cheaper. */
4792 case RELOAD_FOR_INPADDR_ADDRESS:
4793 time1 = opnum * 4 + 2;
4795 case RELOAD_FOR_INPUT_ADDRESS:
4796 time1 = opnum * 4 + 3;
4798 case RELOAD_FOR_INPUT:
4799 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4800 executes (inclusive). */
4801 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4803 case RELOAD_FOR_OPADDR_ADDR:
4805 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4806 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4808 case RELOAD_FOR_OPERAND_ADDRESS:
4809 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4811 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4813 case RELOAD_FOR_OUTADDR_ADDRESS:
4814 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4816 case RELOAD_FOR_OUTPUT_ADDRESS:
4817 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4820 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4823 for (i = 0; i < n_reloads; i++)
4825 rtx reg = rld[i].reg_rtx;
4826 if (reg && GET_CODE (reg) == REG
4827 && ((unsigned) regno - true_regnum (reg)
4828 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
4831 rtx other_input = rld[i].in;
4833 /* If the other reload loads the same input value, that
4834 will not cause a conflict only if it's loading it into
4835 the same register. */
4836 if (true_regnum (reg) != start_regno)
4837 other_input = NULL_RTX;
4838 if (! other_input || ! rtx_equal_p (other_input, value)
4839 || rld[i].out || out)
4842 switch (rld[i].when_needed)
4844 case RELOAD_FOR_OTHER_ADDRESS:
4847 case RELOAD_FOR_INPADDR_ADDRESS:
4848 /* find_reloads makes sure that a
4849 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4850 by at most one - the first -
4851 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4852 address reload is inherited, the address address reload
4853 goes away, so we can ignore this conflict. */
4854 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4855 && ignore_address_reloads
4856 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4857 Then the address address is still needed to store
4858 back the new address. */
4859 && ! rld[reloadnum].out)
4861 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4862 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4864 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4865 && ignore_address_reloads
4866 /* Unless we are reloading an auto_inc expression. */
4867 && ! rld[reloadnum].out)
4869 time2 = rld[i].opnum * 4 + 2;
4871 case RELOAD_FOR_INPUT_ADDRESS:
4872 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4873 && ignore_address_reloads
4874 && ! rld[reloadnum].out)
4876 time2 = rld[i].opnum * 4 + 3;
4878 case RELOAD_FOR_INPUT:
4879 time2 = rld[i].opnum * 4 + 4;
4880 check_earlyclobber = 1;
4882 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4883 == MAX_RECOG_OPERAND * 4 */
4884 case RELOAD_FOR_OPADDR_ADDR:
4885 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4886 && ignore_address_reloads
4887 && ! rld[reloadnum].out)
4889 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4891 case RELOAD_FOR_OPERAND_ADDRESS:
4892 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4893 check_earlyclobber = 1;
4895 case RELOAD_FOR_INSN:
4896 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4898 case RELOAD_FOR_OUTPUT:
4899 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4900 instruction is executed. */
4901 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4903 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4904 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4906 case RELOAD_FOR_OUTADDR_ADDRESS:
4907 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4908 && ignore_address_reloads
4909 && ! rld[reloadnum].out)
4911 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4913 case RELOAD_FOR_OUTPUT_ADDRESS:
4914 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4917 /* If there is no conflict in the input part, handle this
4918 like an output reload. */
4919 if (! rld[i].in || rtx_equal_p (other_input, value))
4921 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4922 /* Earlyclobbered outputs must conflict with inputs. */
4923 if (earlyclobber_operand_p (rld[i].out))
4924 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4929 /* RELOAD_OTHER might be live beyond instruction execution,
4930 but this is not obvious when we set time2 = 1. So check
4931 here if there might be a problem with the new reload
4932 clobbering the register used by the RELOAD_OTHER. */
4940 && (! rld[i].in || rld[i].out
4941 || ! rtx_equal_p (other_input, value)))
4942 || (out && rld[reloadnum].out_reg
4943 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4949 /* Earlyclobbered outputs must conflict with inputs. */
4950 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4956 /* Return 1 if the value in reload reg REGNO, as used by a reload
4957 needed for the part of the insn specified by OPNUM and TYPE,
4958 may be used to load VALUE into it.
4960 MODE is the mode in which the register is used, this is needed to
4961 determine how many hard regs to test.
4963 Other read-only reloads with the same value do not conflict
4964 unless OUT is non-zero and these other reloads have to live while
4965 output reloads live.
4966 If OUT is CONST0_RTX, this is a special case: it means that the
4967 test should not be for using register REGNO as reload register, but
4968 for copying from register REGNO into the reload register.
4970 RELOADNUM is the number of the reload we want to load this value for;
4971 a reload does not conflict with itself.
4973 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4974 reloads that load an address for the very reload we are considering.
4976 The caller has to make sure that there is no conflict with the return
4980 free_for_value_p (regno, mode, opnum, type, value, out, reloadnum,
4981 ignore_address_reloads)
4983 enum machine_mode mode;
4985 enum reload_type type;
4988 int ignore_address_reloads;
4990 int nregs = HARD_REGNO_NREGS (regno, mode);
4992 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
4993 value, out, reloadnum,
4994 ignore_address_reloads))
4999 /* Determine whether the reload reg X overlaps any rtx'es used for
5000 overriding inheritance. Return nonzero if so. */
5003 conflicts_with_override (x)
5007 for (i = 0; i < n_reloads; i++)
5008 if (reload_override_in[i]
5009 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5014 /* Give an error message saying we failed to find a reload for INSN,
5015 and clear out reload R. */
5017 failed_reload (insn, r)
5021 if (asm_noperands (PATTERN (insn)) < 0)
5022 /* It's the compiler's fault. */
5023 fatal_insn ("Could not find a spill register", insn);
5025 /* It's the user's fault; the operand's mode and constraint
5026 don't match. Disable this reload so we don't crash in final. */
5027 error_for_asm (insn,
5028 "`asm' operand constraint incompatible with operand size");
5032 rld[r].optional = 1;
5033 rld[r].secondary_p = 1;
5036 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5037 for reload R. If it's valid, get an rtx for it. Return nonzero if
5040 set_reload_reg (i, r)
5044 rtx reg = spill_reg_rtx[i];
5046 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5047 spill_reg_rtx[i] = reg
5048 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5050 regno = true_regnum (reg);
5052 /* Detect when the reload reg can't hold the reload mode.
5053 This used to be one `if', but Sequent compiler can't handle that. */
5054 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5056 enum machine_mode test_mode = VOIDmode;
5058 test_mode = GET_MODE (rld[r].in);
5059 /* If rld[r].in has VOIDmode, it means we will load it
5060 in whatever mode the reload reg has: to wit, rld[r].mode.
5061 We have already tested that for validity. */
5062 /* Aside from that, we need to test that the expressions
5063 to reload from or into have modes which are valid for this
5064 reload register. Otherwise the reload insns would be invalid. */
5065 if (! (rld[r].in != 0 && test_mode != VOIDmode
5066 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5067 if (! (rld[r].out != 0
5068 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5070 /* The reg is OK. */
5073 /* Mark as in use for this insn the reload regs we use
5075 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5076 rld[r].when_needed, rld[r].mode);
5078 rld[r].reg_rtx = reg;
5079 reload_spill_index[r] = spill_regs[i];
5086 /* Find a spill register to use as a reload register for reload R.
5087 LAST_RELOAD is non-zero if this is the last reload for the insn being
5090 Set rld[R].reg_rtx to the register allocated.
5092 We return 1 if successful, or 0 if we couldn't find a spill reg and
5093 we didn't change anything. */
5096 allocate_reload_reg (chain, r, last_reload)
5097 struct insn_chain *chain ATTRIBUTE_UNUSED;
5103 /* If we put this reload ahead, thinking it is a group,
5104 then insist on finding a group. Otherwise we can grab a
5105 reg that some other reload needs.
5106 (That can happen when we have a 68000 DATA_OR_FP_REG
5107 which is a group of data regs or one fp reg.)
5108 We need not be so restrictive if there are no more reloads
5111 ??? Really it would be nicer to have smarter handling
5112 for that kind of reg class, where a problem like this is normal.
5113 Perhaps those classes should be avoided for reloading
5114 by use of more alternatives. */
5116 int force_group = rld[r].nregs > 1 && ! last_reload;
5118 /* If we want a single register and haven't yet found one,
5119 take any reg in the right class and not in use.
5120 If we want a consecutive group, here is where we look for it.
5122 We use two passes so we can first look for reload regs to
5123 reuse, which are already in use for other reloads in this insn,
5124 and only then use additional registers.
5125 I think that maximizing reuse is needed to make sure we don't
5126 run out of reload regs. Suppose we have three reloads, and
5127 reloads A and B can share regs. These need two regs.
5128 Suppose A and B are given different regs.
5129 That leaves none for C. */
5130 for (pass = 0; pass < 2; pass++)
5132 /* I is the index in spill_regs.
5133 We advance it round-robin between insns to use all spill regs
5134 equally, so that inherited reloads have a chance
5135 of leapfrogging each other. */
5139 for (count = 0; count < n_spills; count++)
5141 int class = (int) rld[r].class;
5147 regnum = spill_regs[i];
5149 if ((reload_reg_free_p (regnum, rld[r].opnum,
5152 /* We check reload_reg_used to make sure we
5153 don't clobber the return register. */
5154 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5155 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5156 rld[r].when_needed, rld[r].in,
5158 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5159 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5160 /* Look first for regs to share, then for unshared. But
5161 don't share regs used for inherited reloads; they are
5162 the ones we want to preserve. */
5164 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5166 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5169 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5170 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5171 (on 68000) got us two FP regs. If NR is 1,
5172 we would reject both of them. */
5175 /* If we need only one reg, we have already won. */
5178 /* But reject a single reg if we demand a group. */
5183 /* Otherwise check that as many consecutive regs as we need
5184 are available here. */
5187 int regno = regnum + nr - 1;
5188 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5189 && spill_reg_order[regno] >= 0
5190 && reload_reg_free_p (regno, rld[r].opnum,
5191 rld[r].when_needed)))
5200 /* If we found something on pass 1, omit pass 2. */
5201 if (count < n_spills)
5205 /* We should have found a spill register by now. */
5206 if (count >= n_spills)
5209 /* I is the index in SPILL_REG_RTX of the reload register we are to
5210 allocate. Get an rtx for it and find its register number. */
5212 return set_reload_reg (i, r);
5215 /* Initialize all the tables needed to allocate reload registers.
5216 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5217 is the array we use to restore the reg_rtx field for every reload. */
5220 choose_reload_regs_init (chain, save_reload_reg_rtx)
5221 struct insn_chain *chain;
5222 rtx *save_reload_reg_rtx;
5226 for (i = 0; i < n_reloads; i++)
5227 rld[i].reg_rtx = save_reload_reg_rtx[i];
5229 memset (reload_inherited, 0, MAX_RELOADS);
5230 memset ((char *) reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5231 memset ((char *) reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5233 CLEAR_HARD_REG_SET (reload_reg_used);
5234 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5235 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5236 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5237 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5238 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5240 CLEAR_HARD_REG_SET (reg_used_in_insn);
5243 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5244 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5245 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5246 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5247 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5248 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5251 for (i = 0; i < reload_n_operands; i++)
5253 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5254 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5255 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5256 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5257 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5258 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5261 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5263 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5265 for (i = 0; i < n_reloads; i++)
5266 /* If we have already decided to use a certain register,
5267 don't use it in another way. */
5269 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5270 rld[i].when_needed, rld[i].mode);
5273 /* Assign hard reg targets for the pseudo-registers we must reload
5274 into hard regs for this insn.
5275 Also output the instructions to copy them in and out of the hard regs.
5277 For machines with register classes, we are responsible for
5278 finding a reload reg in the proper class. */
5281 choose_reload_regs (chain)
5282 struct insn_chain *chain;
5284 rtx insn = chain->insn;
5286 unsigned int max_group_size = 1;
5287 enum reg_class group_class = NO_REGS;
5288 int pass, win, inheritance;
5290 rtx save_reload_reg_rtx[MAX_RELOADS];
5292 /* In order to be certain of getting the registers we need,
5293 we must sort the reloads into order of increasing register class.
5294 Then our grabbing of reload registers will parallel the process
5295 that provided the reload registers.
5297 Also note whether any of the reloads wants a consecutive group of regs.
5298 If so, record the maximum size of the group desired and what
5299 register class contains all the groups needed by this insn. */
5301 for (j = 0; j < n_reloads; j++)
5303 reload_order[j] = j;
5304 reload_spill_index[j] = -1;
5306 if (rld[j].nregs > 1)
5308 max_group_size = MAX (rld[j].nregs, max_group_size);
5310 = reg_class_superunion[(int) rld[j].class][(int)group_class];
5313 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5317 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5319 /* If -O, try first with inheritance, then turning it off.
5320 If not -O, don't do inheritance.
5321 Using inheritance when not optimizing leads to paradoxes
5322 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5323 because one side of the comparison might be inherited. */
5325 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5327 choose_reload_regs_init (chain, save_reload_reg_rtx);
5329 /* Process the reloads in order of preference just found.
5330 Beyond this point, subregs can be found in reload_reg_rtx.
5332 This used to look for an existing reloaded home for all of the
5333 reloads, and only then perform any new reloads. But that could lose
5334 if the reloads were done out of reg-class order because a later
5335 reload with a looser constraint might have an old home in a register
5336 needed by an earlier reload with a tighter constraint.
5338 To solve this, we make two passes over the reloads, in the order
5339 described above. In the first pass we try to inherit a reload
5340 from a previous insn. If there is a later reload that needs a
5341 class that is a proper subset of the class being processed, we must
5342 also allocate a spill register during the first pass.
5344 Then make a second pass over the reloads to allocate any reloads
5345 that haven't been given registers yet. */
5347 for (j = 0; j < n_reloads; j++)
5349 int r = reload_order[j];
5350 rtx search_equiv = NULL_RTX;
5352 /* Ignore reloads that got marked inoperative. */
5353 if (rld[r].out == 0 && rld[r].in == 0
5354 && ! rld[r].secondary_p)
5357 /* If find_reloads chose to use reload_in or reload_out as a reload
5358 register, we don't need to chose one. Otherwise, try even if it
5359 found one since we might save an insn if we find the value lying
5361 Try also when reload_in is a pseudo without a hard reg. */
5362 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5363 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5364 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5365 && GET_CODE (rld[r].in) != MEM
5366 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5369 #if 0 /* No longer needed for correct operation.
5370 It might give better code, or might not; worth an experiment? */
5371 /* If this is an optional reload, we can't inherit from earlier insns
5372 until we are sure that any non-optional reloads have been allocated.
5373 The following code takes advantage of the fact that optional reloads
5374 are at the end of reload_order. */
5375 if (rld[r].optional != 0)
5376 for (i = 0; i < j; i++)
5377 if ((rld[reload_order[i]].out != 0
5378 || rld[reload_order[i]].in != 0
5379 || rld[reload_order[i]].secondary_p)
5380 && ! rld[reload_order[i]].optional
5381 && rld[reload_order[i]].reg_rtx == 0)
5382 allocate_reload_reg (chain, reload_order[i], 0);
5385 /* First see if this pseudo is already available as reloaded
5386 for a previous insn. We cannot try to inherit for reloads
5387 that are smaller than the maximum number of registers needed
5388 for groups unless the register we would allocate cannot be used
5391 We could check here to see if this is a secondary reload for
5392 an object that is already in a register of the desired class.
5393 This would avoid the need for the secondary reload register.
5394 But this is complex because we can't easily determine what
5395 objects might want to be loaded via this reload. So let a
5396 register be allocated here. In `emit_reload_insns' we suppress
5397 one of the loads in the case described above. */
5403 enum machine_mode mode = VOIDmode;
5407 else if (GET_CODE (rld[r].in) == REG)
5409 regno = REGNO (rld[r].in);
5410 mode = GET_MODE (rld[r].in);
5412 else if (GET_CODE (rld[r].in_reg) == REG)
5414 regno = REGNO (rld[r].in_reg);
5415 mode = GET_MODE (rld[r].in_reg);
5417 else if (GET_CODE (rld[r].in_reg) == SUBREG
5418 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5420 byte = SUBREG_BYTE (rld[r].in_reg);
5421 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5422 if (regno < FIRST_PSEUDO_REGISTER)
5423 regno = subreg_regno (rld[r].in_reg);
5424 mode = GET_MODE (rld[r].in_reg);
5427 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5428 || GET_CODE (rld[r].in_reg) == PRE_DEC
5429 || GET_CODE (rld[r].in_reg) == POST_INC
5430 || GET_CODE (rld[r].in_reg) == POST_DEC)
5431 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5433 regno = REGNO (XEXP (rld[r].in_reg, 0));
5434 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5435 rld[r].out = rld[r].in;
5439 /* This won't work, since REGNO can be a pseudo reg number.
5440 Also, it takes much more hair to keep track of all the things
5441 that can invalidate an inherited reload of part of a pseudoreg. */
5442 else if (GET_CODE (rld[r].in) == SUBREG
5443 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5444 regno = subreg_regno (rld[r].in);
5447 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5449 enum reg_class class = rld[r].class, last_class;
5450 rtx last_reg = reg_last_reload_reg[regno];
5451 enum machine_mode need_mode;
5453 i = REGNO (last_reg);
5454 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5455 last_class = REGNO_REG_CLASS (i);
5461 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5462 GET_MODE_CLASS (mode));
5465 #ifdef CLASS_CANNOT_CHANGE_MODE
5467 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], i)
5468 ? ! CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (last_reg),
5470 : (GET_MODE_SIZE (GET_MODE (last_reg))
5471 >= GET_MODE_SIZE (need_mode)))
5473 (GET_MODE_SIZE (GET_MODE (last_reg))
5474 >= GET_MODE_SIZE (need_mode))
5476 && reg_reloaded_contents[i] == regno
5477 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5478 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5479 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5480 /* Even if we can't use this register as a reload
5481 register, we might use it for reload_override_in,
5482 if copying it to the desired class is cheap
5484 || ((REGISTER_MOVE_COST (mode, last_class, class)
5485 < MEMORY_MOVE_COST (mode, class, 1))
5486 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5487 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5491 #ifdef SECONDARY_MEMORY_NEEDED
5492 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5497 && (rld[r].nregs == max_group_size
5498 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5500 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5501 rld[r].when_needed, rld[r].in,
5504 /* If a group is needed, verify that all the subsequent
5505 registers still have their values intact. */
5506 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5509 for (k = 1; k < nr; k++)
5510 if (reg_reloaded_contents[i + k] != regno
5511 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5519 last_reg = (GET_MODE (last_reg) == mode
5520 ? last_reg : gen_rtx_REG (mode, i));
5523 for (k = 0; k < nr; k++)
5524 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5527 /* We found a register that contains the
5528 value we need. If this register is the
5529 same as an `earlyclobber' operand of the
5530 current insn, just mark it as a place to
5531 reload from since we can't use it as the
5532 reload register itself. */
5534 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5535 if (reg_overlap_mentioned_for_reload_p
5536 (reg_last_reload_reg[regno],
5537 reload_earlyclobbers[i1]))
5540 if (i1 != n_earlyclobbers
5541 || ! (free_for_value_p (i, rld[r].mode,
5543 rld[r].when_needed, rld[r].in,
5545 /* Don't use it if we'd clobber a pseudo reg. */
5546 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5548 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5549 /* Don't clobber the frame pointer. */
5550 || (i == HARD_FRAME_POINTER_REGNUM
5552 /* Don't really use the inherited spill reg
5553 if we need it wider than we've got it. */
5554 || (GET_MODE_SIZE (rld[r].mode)
5555 > GET_MODE_SIZE (mode))
5558 /* If find_reloads chose reload_out as reload
5559 register, stay with it - that leaves the
5560 inherited register for subsequent reloads. */
5561 || (rld[r].out && rld[r].reg_rtx
5562 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5564 if (! rld[r].optional)
5566 reload_override_in[r] = last_reg;
5567 reload_inheritance_insn[r]
5568 = reg_reloaded_insn[i];
5574 /* We can use this as a reload reg. */
5575 /* Mark the register as in use for this part of
5577 mark_reload_reg_in_use (i,
5581 rld[r].reg_rtx = last_reg;
5582 reload_inherited[r] = 1;
5583 reload_inheritance_insn[r]
5584 = reg_reloaded_insn[i];
5585 reload_spill_index[r] = i;
5586 for (k = 0; k < nr; k++)
5587 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5595 /* Here's another way to see if the value is already lying around. */
5598 && ! reload_inherited[r]
5600 && (CONSTANT_P (rld[r].in)
5601 || GET_CODE (rld[r].in) == PLUS
5602 || GET_CODE (rld[r].in) == REG
5603 || GET_CODE (rld[r].in) == MEM)
5604 && (rld[r].nregs == max_group_size
5605 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5606 search_equiv = rld[r].in;
5607 /* If this is an output reload from a simple move insn, look
5608 if an equivalence for the input is available. */
5609 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5611 rtx set = single_set (insn);
5614 && rtx_equal_p (rld[r].out, SET_DEST (set))
5615 && CONSTANT_P (SET_SRC (set)))
5616 search_equiv = SET_SRC (set);
5622 = find_equiv_reg (search_equiv, insn, rld[r].class,
5623 -1, NULL, 0, rld[r].mode);
5628 if (GET_CODE (equiv) == REG)
5629 regno = REGNO (equiv);
5630 else if (GET_CODE (equiv) == SUBREG)
5632 /* This must be a SUBREG of a hard register.
5633 Make a new REG since this might be used in an
5634 address and not all machines support SUBREGs
5636 regno = subreg_regno (equiv);
5637 equiv = gen_rtx_REG (rld[r].mode, regno);
5643 /* If we found a spill reg, reject it unless it is free
5644 and of the desired class. */
5646 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5647 && ! free_for_value_p (regno, rld[r].mode,
5648 rld[r].opnum, rld[r].when_needed,
5649 rld[r].in, rld[r].out, r, 1))
5650 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5654 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5657 /* We found a register that contains the value we need.
5658 If this register is the same as an `earlyclobber' operand
5659 of the current insn, just mark it as a place to reload from
5660 since we can't use it as the reload register itself. */
5663 for (i = 0; i < n_earlyclobbers; i++)
5664 if (reg_overlap_mentioned_for_reload_p (equiv,
5665 reload_earlyclobbers[i]))
5667 if (! rld[r].optional)
5668 reload_override_in[r] = equiv;
5673 /* If the equiv register we have found is explicitly clobbered
5674 in the current insn, it depends on the reload type if we
5675 can use it, use it for reload_override_in, or not at all.
5676 In particular, we then can't use EQUIV for a
5677 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5681 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5682 switch (rld[r].when_needed)
5684 case RELOAD_FOR_OTHER_ADDRESS:
5685 case RELOAD_FOR_INPADDR_ADDRESS:
5686 case RELOAD_FOR_INPUT_ADDRESS:
5687 case RELOAD_FOR_OPADDR_ADDR:
5690 case RELOAD_FOR_INPUT:
5691 case RELOAD_FOR_OPERAND_ADDRESS:
5692 if (! rld[r].optional)
5693 reload_override_in[r] = equiv;
5699 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5700 switch (rld[r].when_needed)
5702 case RELOAD_FOR_OTHER_ADDRESS:
5703 case RELOAD_FOR_INPADDR_ADDRESS:
5704 case RELOAD_FOR_INPUT_ADDRESS:
5705 case RELOAD_FOR_OPADDR_ADDR:
5706 case RELOAD_FOR_OPERAND_ADDRESS:
5707 case RELOAD_FOR_INPUT:
5710 if (! rld[r].optional)
5711 reload_override_in[r] = equiv;
5719 /* If we found an equivalent reg, say no code need be generated
5720 to load it, and use it as our reload reg. */
5721 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5723 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5725 rld[r].reg_rtx = equiv;
5726 reload_inherited[r] = 1;
5728 /* If reg_reloaded_valid is not set for this register,
5729 there might be a stale spill_reg_store lying around.
5730 We must clear it, since otherwise emit_reload_insns
5731 might delete the store. */
5732 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5733 spill_reg_store[regno] = NULL_RTX;
5734 /* If any of the hard registers in EQUIV are spill
5735 registers, mark them as in use for this insn. */
5736 for (k = 0; k < nr; k++)
5738 i = spill_reg_order[regno + k];
5741 mark_reload_reg_in_use (regno, rld[r].opnum,
5744 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5751 /* If we found a register to use already, or if this is an optional
5752 reload, we are done. */
5753 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5757 /* No longer needed for correct operation. Might or might
5758 not give better code on the average. Want to experiment? */
5760 /* See if there is a later reload that has a class different from our
5761 class that intersects our class or that requires less register
5762 than our reload. If so, we must allocate a register to this
5763 reload now, since that reload might inherit a previous reload
5764 and take the only available register in our class. Don't do this
5765 for optional reloads since they will force all previous reloads
5766 to be allocated. Also don't do this for reloads that have been
5769 for (i = j + 1; i < n_reloads; i++)
5771 int s = reload_order[i];
5773 if ((rld[s].in == 0 && rld[s].out == 0
5774 && ! rld[s].secondary_p)
5778 if ((rld[s].class != rld[r].class
5779 && reg_classes_intersect_p (rld[r].class,
5781 || rld[s].nregs < rld[r].nregs)
5788 allocate_reload_reg (chain, r, j == n_reloads - 1);
5792 /* Now allocate reload registers for anything non-optional that
5793 didn't get one yet. */
5794 for (j = 0; j < n_reloads; j++)
5796 int r = reload_order[j];
5798 /* Ignore reloads that got marked inoperative. */
5799 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5802 /* Skip reloads that already have a register allocated or are
5804 if (rld[r].reg_rtx != 0 || rld[r].optional)
5807 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5811 /* If that loop got all the way, we have won. */
5818 /* Loop around and try without any inheritance. */
5823 /* First undo everything done by the failed attempt
5824 to allocate with inheritance. */
5825 choose_reload_regs_init (chain, save_reload_reg_rtx);
5827 /* Some sanity tests to verify that the reloads found in the first
5828 pass are identical to the ones we have now. */
5829 if (chain->n_reloads != n_reloads)
5832 for (i = 0; i < n_reloads; i++)
5834 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5836 if (chain->rld[i].when_needed != rld[i].when_needed)
5838 for (j = 0; j < n_spills; j++)
5839 if (spill_regs[j] == chain->rld[i].regno)
5840 if (! set_reload_reg (j, i))
5841 failed_reload (chain->insn, i);
5845 /* If we thought we could inherit a reload, because it seemed that
5846 nothing else wanted the same reload register earlier in the insn,
5847 verify that assumption, now that all reloads have been assigned.
5848 Likewise for reloads where reload_override_in has been set. */
5850 /* If doing expensive optimizations, do one preliminary pass that doesn't
5851 cancel any inheritance, but removes reloads that have been needed only
5852 for reloads that we know can be inherited. */
5853 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5855 for (j = 0; j < n_reloads; j++)
5857 int r = reload_order[j];
5859 if (reload_inherited[r] && rld[r].reg_rtx)
5860 check_reg = rld[r].reg_rtx;
5861 else if (reload_override_in[r]
5862 && (GET_CODE (reload_override_in[r]) == REG
5863 || GET_CODE (reload_override_in[r]) == SUBREG))
5864 check_reg = reload_override_in[r];
5867 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5868 rld[r].opnum, rld[r].when_needed, rld[r].in,
5869 (reload_inherited[r]
5870 ? rld[r].out : const0_rtx),
5875 reload_inherited[r] = 0;
5876 reload_override_in[r] = 0;
5878 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5879 reload_override_in, then we do not need its related
5880 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5881 likewise for other reload types.
5882 We handle this by removing a reload when its only replacement
5883 is mentioned in reload_in of the reload we are going to inherit.
5884 A special case are auto_inc expressions; even if the input is
5885 inherited, we still need the address for the output. We can
5886 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5887 If we suceeded removing some reload and we are doing a preliminary
5888 pass just to remove such reloads, make another pass, since the
5889 removal of one reload might allow us to inherit another one. */
5891 && rld[r].out != rld[r].in
5892 && remove_address_replacements (rld[r].in) && pass)
5897 /* Now that reload_override_in is known valid,
5898 actually override reload_in. */
5899 for (j = 0; j < n_reloads; j++)
5900 if (reload_override_in[j])
5901 rld[j].in = reload_override_in[j];
5903 /* If this reload won't be done because it has been cancelled or is
5904 optional and not inherited, clear reload_reg_rtx so other
5905 routines (such as subst_reloads) don't get confused. */
5906 for (j = 0; j < n_reloads; j++)
5907 if (rld[j].reg_rtx != 0
5908 && ((rld[j].optional && ! reload_inherited[j])
5909 || (rld[j].in == 0 && rld[j].out == 0
5910 && ! rld[j].secondary_p)))
5912 int regno = true_regnum (rld[j].reg_rtx);
5914 if (spill_reg_order[regno] >= 0)
5915 clear_reload_reg_in_use (regno, rld[j].opnum,
5916 rld[j].when_needed, rld[j].mode);
5918 reload_spill_index[j] = -1;
5921 /* Record which pseudos and which spill regs have output reloads. */
5922 for (j = 0; j < n_reloads; j++)
5924 int r = reload_order[j];
5926 i = reload_spill_index[r];
5928 /* I is nonneg if this reload uses a register.
5929 If rld[r].reg_rtx is 0, this is an optional reload
5930 that we opted to ignore. */
5931 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5932 && rld[r].reg_rtx != 0)
5934 int nregno = REGNO (rld[r].out_reg);
5937 if (nregno < FIRST_PSEUDO_REGISTER)
5938 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5941 reg_has_output_reload[nregno + nr] = 1;
5945 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5947 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5950 if (rld[r].when_needed != RELOAD_OTHER
5951 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5952 && rld[r].when_needed != RELOAD_FOR_INSN)
5958 /* Deallocate the reload register for reload R. This is called from
5959 remove_address_replacements. */
5962 deallocate_reload_reg (r)
5967 if (! rld[r].reg_rtx)
5969 regno = true_regnum (rld[r].reg_rtx);
5971 if (spill_reg_order[regno] >= 0)
5972 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5974 reload_spill_index[r] = -1;
5977 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
5978 reloads of the same item for fear that we might not have enough reload
5979 registers. However, normally they will get the same reload register
5980 and hence actually need not be loaded twice.
5982 Here we check for the most common case of this phenomenon: when we have
5983 a number of reloads for the same object, each of which were allocated
5984 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5985 reload, and is not modified in the insn itself. If we find such,
5986 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5987 This will not increase the number of spill registers needed and will
5988 prevent redundant code. */
5991 merge_assigned_reloads (insn)
5996 /* Scan all the reloads looking for ones that only load values and
5997 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5998 assigned and not modified by INSN. */
6000 for (i = 0; i < n_reloads; i++)
6002 int conflicting_input = 0;
6003 int max_input_address_opnum = -1;
6004 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6006 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6007 || rld[i].out != 0 || rld[i].reg_rtx == 0
6008 || reg_set_p (rld[i].reg_rtx, insn))
6011 /* Look at all other reloads. Ensure that the only use of this
6012 reload_reg_rtx is in a reload that just loads the same value
6013 as we do. Note that any secondary reloads must be of the identical
6014 class since the values, modes, and result registers are the
6015 same, so we need not do anything with any secondary reloads. */
6017 for (j = 0; j < n_reloads; j++)
6019 if (i == j || rld[j].reg_rtx == 0
6020 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6024 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6025 && rld[j].opnum > max_input_address_opnum)
6026 max_input_address_opnum = rld[j].opnum;
6028 /* If the reload regs aren't exactly the same (e.g, different modes)
6029 or if the values are different, we can't merge this reload.
6030 But if it is an input reload, we might still merge
6031 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6033 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6034 || rld[j].out != 0 || rld[j].in == 0
6035 || ! rtx_equal_p (rld[i].in, rld[j].in))
6037 if (rld[j].when_needed != RELOAD_FOR_INPUT
6038 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6039 || rld[i].opnum > rld[j].opnum)
6040 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6042 conflicting_input = 1;
6043 if (min_conflicting_input_opnum > rld[j].opnum)
6044 min_conflicting_input_opnum = rld[j].opnum;
6048 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6049 we, in fact, found any matching reloads. */
6052 && max_input_address_opnum <= min_conflicting_input_opnum)
6054 for (j = 0; j < n_reloads; j++)
6055 if (i != j && rld[j].reg_rtx != 0
6056 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6057 && (! conflicting_input
6058 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6059 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6061 rld[i].when_needed = RELOAD_OTHER;
6063 reload_spill_index[j] = -1;
6064 transfer_replacements (i, j);
6067 /* If this is now RELOAD_OTHER, look for any reloads that load
6068 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6069 if they were for inputs, RELOAD_OTHER for outputs. Note that
6070 this test is equivalent to looking for reloads for this operand
6073 if (rld[i].when_needed == RELOAD_OTHER)
6074 for (j = 0; j < n_reloads; j++)
6076 && rld[j].when_needed != RELOAD_OTHER
6077 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6080 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6081 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6082 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6087 /* These arrays are filled by emit_reload_insns and its subroutines. */
6088 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6089 static rtx other_input_address_reload_insns = 0;
6090 static rtx other_input_reload_insns = 0;
6091 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6092 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6093 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6094 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6095 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6096 static rtx operand_reload_insns = 0;
6097 static rtx other_operand_reload_insns = 0;
6098 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6100 /* Values to be put in spill_reg_store are put here first. */
6101 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6102 static HARD_REG_SET reg_reloaded_died;
6104 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6105 has the number J. OLD contains the value to be used as input. */
6108 emit_input_reload_insns (chain, rl, old, j)
6109 struct insn_chain *chain;
6114 rtx insn = chain->insn;
6115 rtx reloadreg = rl->reg_rtx;
6116 rtx oldequiv_reg = 0;
6119 enum machine_mode mode;
6122 /* Determine the mode to reload in.
6123 This is very tricky because we have three to choose from.
6124 There is the mode the insn operand wants (rl->inmode).
6125 There is the mode of the reload register RELOADREG.
6126 There is the intrinsic mode of the operand, which we could find
6127 by stripping some SUBREGs.
6128 It turns out that RELOADREG's mode is irrelevant:
6129 we can change that arbitrarily.
6131 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6132 then the reload reg may not support QImode moves, so use SImode.
6133 If foo is in memory due to spilling a pseudo reg, this is safe,
6134 because the QImode value is in the least significant part of a
6135 slot big enough for a SImode. If foo is some other sort of
6136 memory reference, then it is impossible to reload this case,
6137 so previous passes had better make sure this never happens.
6139 Then consider a one-word union which has SImode and one of its
6140 members is a float, being fetched as (SUBREG:SF union:SI).
6141 We must fetch that as SFmode because we could be loading into
6142 a float-only register. In this case OLD's mode is correct.
6144 Consider an immediate integer: it has VOIDmode. Here we need
6145 to get a mode from something else.
6147 In some cases, there is a fourth mode, the operand's
6148 containing mode. If the insn specifies a containing mode for
6149 this operand, it overrides all others.
6151 I am not sure whether the algorithm here is always right,
6152 but it does the right things in those cases. */
6154 mode = GET_MODE (old);
6155 if (mode == VOIDmode)
6158 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6159 /* If we need a secondary register for this operation, see if
6160 the value is already in a register in that class. Don't
6161 do this if the secondary register will be used as a scratch
6164 if (rl->secondary_in_reload >= 0
6165 && rl->secondary_in_icode == CODE_FOR_nothing
6168 = find_equiv_reg (old, insn,
6169 rld[rl->secondary_in_reload].class,
6173 /* If reloading from memory, see if there is a register
6174 that already holds the same value. If so, reload from there.
6175 We can pass 0 as the reload_reg_p argument because
6176 any other reload has either already been emitted,
6177 in which case find_equiv_reg will see the reload-insn,
6178 or has yet to be emitted, in which case it doesn't matter
6179 because we will use this equiv reg right away. */
6181 if (oldequiv == 0 && optimize
6182 && (GET_CODE (old) == MEM
6183 || (GET_CODE (old) == REG
6184 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6185 && reg_renumber[REGNO (old)] < 0)))
6186 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6190 unsigned int regno = true_regnum (oldequiv);
6192 /* Don't use OLDEQUIV if any other reload changes it at an
6193 earlier stage of this insn or at this stage. */
6194 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6195 rl->in, const0_rtx, j, 0))
6198 /* If it is no cheaper to copy from OLDEQUIV into the
6199 reload register than it would be to move from memory,
6200 don't use it. Likewise, if we need a secondary register
6204 && ((REGNO_REG_CLASS (regno) != rl->class
6205 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6207 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6208 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6209 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6213 #ifdef SECONDARY_MEMORY_NEEDED
6214 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6222 /* delete_output_reload is only invoked properly if old contains
6223 the original pseudo register. Since this is replaced with a
6224 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6225 find the pseudo in RELOAD_IN_REG. */
6227 && reload_override_in[j]
6228 && GET_CODE (rl->in_reg) == REG)
6235 else if (GET_CODE (oldequiv) == REG)
6236 oldequiv_reg = oldequiv;
6237 else if (GET_CODE (oldequiv) == SUBREG)
6238 oldequiv_reg = SUBREG_REG (oldequiv);
6240 /* If we are reloading from a register that was recently stored in
6241 with an output-reload, see if we can prove there was
6242 actually no need to store the old value in it. */
6244 if (optimize && GET_CODE (oldequiv) == REG
6245 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6246 && spill_reg_store[REGNO (oldequiv)]
6247 && GET_CODE (old) == REG
6248 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6249 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6251 delete_output_reload (insn, j, REGNO (oldequiv));
6253 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6254 then load RELOADREG from OLDEQUIV. Note that we cannot use
6255 gen_lowpart_common since it can do the wrong thing when
6256 RELOADREG has a multi-word mode. Note that RELOADREG
6257 must always be a REG here. */
6259 if (GET_MODE (reloadreg) != mode)
6260 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6261 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6262 oldequiv = SUBREG_REG (oldequiv);
6263 if (GET_MODE (oldequiv) != VOIDmode
6264 && mode != GET_MODE (oldequiv))
6265 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6267 /* Switch to the right place to emit the reload insns. */
6268 switch (rl->when_needed)
6271 where = &other_input_reload_insns;
6273 case RELOAD_FOR_INPUT:
6274 where = &input_reload_insns[rl->opnum];
6276 case RELOAD_FOR_INPUT_ADDRESS:
6277 where = &input_address_reload_insns[rl->opnum];
6279 case RELOAD_FOR_INPADDR_ADDRESS:
6280 where = &inpaddr_address_reload_insns[rl->opnum];
6282 case RELOAD_FOR_OUTPUT_ADDRESS:
6283 where = &output_address_reload_insns[rl->opnum];
6285 case RELOAD_FOR_OUTADDR_ADDRESS:
6286 where = &outaddr_address_reload_insns[rl->opnum];
6288 case RELOAD_FOR_OPERAND_ADDRESS:
6289 where = &operand_reload_insns;
6291 case RELOAD_FOR_OPADDR_ADDR:
6292 where = &other_operand_reload_insns;
6294 case RELOAD_FOR_OTHER_ADDRESS:
6295 where = &other_input_address_reload_insns;
6301 push_to_sequence (*where);
6303 /* Auto-increment addresses must be reloaded in a special way. */
6304 if (rl->out && ! rl->out_reg)
6306 /* We are not going to bother supporting the case where a
6307 incremented register can't be copied directly from
6308 OLDEQUIV since this seems highly unlikely. */
6309 if (rl->secondary_in_reload >= 0)
6312 if (reload_inherited[j])
6313 oldequiv = reloadreg;
6315 old = XEXP (rl->in_reg, 0);
6317 if (optimize && GET_CODE (oldequiv) == REG
6318 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6319 && spill_reg_store[REGNO (oldequiv)]
6320 && GET_CODE (old) == REG
6321 && (dead_or_set_p (insn,
6322 spill_reg_stored_to[REGNO (oldequiv)])
6323 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6325 delete_output_reload (insn, j, REGNO (oldequiv));
6327 /* Prevent normal processing of this reload. */
6329 /* Output a special code sequence for this case. */
6330 new_spill_reg_store[REGNO (reloadreg)]
6331 = inc_for_reload (reloadreg, oldequiv, rl->out,
6335 /* If we are reloading a pseudo-register that was set by the previous
6336 insn, see if we can get rid of that pseudo-register entirely
6337 by redirecting the previous insn into our reload register. */
6339 else if (optimize && GET_CODE (old) == REG
6340 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6341 && dead_or_set_p (insn, old)
6342 /* This is unsafe if some other reload
6343 uses the same reg first. */
6344 && ! conflicts_with_override (reloadreg)
6345 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6346 rl->when_needed, old, rl->out, j, 0))
6348 rtx temp = PREV_INSN (insn);
6349 while (temp && GET_CODE (temp) == NOTE)
6350 temp = PREV_INSN (temp);
6352 && GET_CODE (temp) == INSN
6353 && GET_CODE (PATTERN (temp)) == SET
6354 && SET_DEST (PATTERN (temp)) == old
6355 /* Make sure we can access insn_operand_constraint. */
6356 && asm_noperands (PATTERN (temp)) < 0
6357 /* This is unsafe if prev insn rejects our reload reg. */
6358 && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint,
6360 /* This is unsafe if operand occurs more than once in current
6361 insn. Perhaps some occurrences aren't reloaded. */
6362 && count_occurrences (PATTERN (insn), old, 0) == 1
6363 /* Don't risk splitting a matching pair of operands. */
6364 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6366 /* Store into the reload register instead of the pseudo. */
6367 SET_DEST (PATTERN (temp)) = reloadreg;
6369 /* If the previous insn is an output reload, the source is
6370 a reload register, and its spill_reg_store entry will
6371 contain the previous destination. This is now
6373 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6374 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6376 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6377 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6380 /* If these are the only uses of the pseudo reg,
6381 pretend for GDB it lives in the reload reg we used. */
6382 if (REG_N_DEATHS (REGNO (old)) == 1
6383 && REG_N_SETS (REGNO (old)) == 1)
6385 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6386 alter_reg (REGNO (old), -1);
6392 /* We can't do that, so output an insn to load RELOADREG. */
6394 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6395 /* If we have a secondary reload, pick up the secondary register
6396 and icode, if any. If OLDEQUIV and OLD are different or
6397 if this is an in-out reload, recompute whether or not we
6398 still need a secondary register and what the icode should
6399 be. If we still need a secondary register and the class or
6400 icode is different, go back to reloading from OLD if using
6401 OLDEQUIV means that we got the wrong type of register. We
6402 cannot have different class or icode due to an in-out reload
6403 because we don't make such reloads when both the input and
6404 output need secondary reload registers. */
6406 if (! special && rl->secondary_in_reload >= 0)
6408 rtx second_reload_reg = 0;
6409 int secondary_reload = rl->secondary_in_reload;
6410 rtx real_oldequiv = oldequiv;
6413 enum insn_code icode;
6415 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6416 and similarly for OLD.
6417 See comments in get_secondary_reload in reload.c. */
6418 /* If it is a pseudo that cannot be replaced with its
6419 equivalent MEM, we must fall back to reload_in, which
6420 will have all the necessary substitutions registered.
6421 Likewise for a pseudo that can't be replaced with its
6422 equivalent constant.
6424 Take extra care for subregs of such pseudos. Note that
6425 we cannot use reg_equiv_mem in this case because it is
6426 not in the right mode. */
6429 if (GET_CODE (tmp) == SUBREG)
6430 tmp = SUBREG_REG (tmp);
6431 if (GET_CODE (tmp) == REG
6432 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6433 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6434 || reg_equiv_constant[REGNO (tmp)] != 0))
6436 if (! reg_equiv_mem[REGNO (tmp)]
6437 || num_not_at_initial_offset
6438 || GET_CODE (oldequiv) == SUBREG)
6439 real_oldequiv = rl->in;
6441 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6445 if (GET_CODE (tmp) == SUBREG)
6446 tmp = SUBREG_REG (tmp);
6447 if (GET_CODE (tmp) == REG
6448 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6449 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6450 || reg_equiv_constant[REGNO (tmp)] != 0))
6452 if (! reg_equiv_mem[REGNO (tmp)]
6453 || num_not_at_initial_offset
6454 || GET_CODE (old) == SUBREG)
6457 real_old = reg_equiv_mem[REGNO (tmp)];
6460 second_reload_reg = rld[secondary_reload].reg_rtx;
6461 icode = rl->secondary_in_icode;
6463 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6464 || (rl->in != 0 && rl->out != 0))
6466 enum reg_class new_class
6467 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6468 mode, real_oldequiv);
6470 if (new_class == NO_REGS)
6471 second_reload_reg = 0;
6474 enum insn_code new_icode;
6475 enum machine_mode new_mode;
6477 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6478 REGNO (second_reload_reg)))
6479 oldequiv = old, real_oldequiv = real_old;
6482 new_icode = reload_in_optab[(int) mode];
6483 if (new_icode != CODE_FOR_nothing
6484 && ((insn_data[(int) new_icode].operand[0].predicate
6485 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6487 || (insn_data[(int) new_icode].operand[1].predicate
6488 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6489 (real_oldequiv, mode)))))
6490 new_icode = CODE_FOR_nothing;
6492 if (new_icode == CODE_FOR_nothing)
6495 new_mode = insn_data[(int) new_icode].operand[2].mode;
6497 if (GET_MODE (second_reload_reg) != new_mode)
6499 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6501 oldequiv = old, real_oldequiv = real_old;
6504 = gen_rtx_REG (new_mode,
6505 REGNO (second_reload_reg));
6511 /* If we still need a secondary reload register, check
6512 to see if it is being used as a scratch or intermediate
6513 register and generate code appropriately. If we need
6514 a scratch register, use REAL_OLDEQUIV since the form of
6515 the insn may depend on the actual address if it is
6518 if (second_reload_reg)
6520 if (icode != CODE_FOR_nothing)
6522 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6523 second_reload_reg));
6528 /* See if we need a scratch register to load the
6529 intermediate register (a tertiary reload). */
6530 enum insn_code tertiary_icode
6531 = rld[secondary_reload].secondary_in_icode;
6533 if (tertiary_icode != CODE_FOR_nothing)
6535 rtx third_reload_reg
6536 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6538 emit_insn ((GEN_FCN (tertiary_icode)
6539 (second_reload_reg, real_oldequiv,
6540 third_reload_reg)));
6543 gen_reload (second_reload_reg, real_oldequiv,
6547 oldequiv = second_reload_reg;
6553 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6555 rtx real_oldequiv = oldequiv;
6557 if ((GET_CODE (oldequiv) == REG
6558 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6559 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6560 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6561 || (GET_CODE (oldequiv) == SUBREG
6562 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6563 && (REGNO (SUBREG_REG (oldequiv))
6564 >= FIRST_PSEUDO_REGISTER)
6565 && ((reg_equiv_memory_loc
6566 [REGNO (SUBREG_REG (oldequiv))] != 0)
6567 || (reg_equiv_constant
6568 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6569 || (CONSTANT_P (oldequiv)
6570 && (PREFERRED_RELOAD_CLASS (oldequiv,
6571 REGNO_REG_CLASS (REGNO (reloadreg)))
6573 real_oldequiv = rl->in;
6574 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6578 if (flag_non_call_exceptions)
6579 copy_eh_notes (insn, get_insns ());
6581 /* End this sequence. */
6582 *where = get_insns ();
6585 /* Update reload_override_in so that delete_address_reloads_1
6586 can see the actual register usage. */
6588 reload_override_in[j] = oldequiv;
6591 /* Generate insns to for the output reload RL, which is for the insn described
6592 by CHAIN and has the number J. */
6594 emit_output_reload_insns (chain, rl, j)
6595 struct insn_chain *chain;
6599 rtx reloadreg = rl->reg_rtx;
6600 rtx insn = chain->insn;
6603 enum machine_mode mode = GET_MODE (old);
6606 if (rl->when_needed == RELOAD_OTHER)
6609 push_to_sequence (output_reload_insns[rl->opnum]);
6611 /* Determine the mode to reload in.
6612 See comments above (for input reloading). */
6614 if (mode == VOIDmode)
6616 /* VOIDmode should never happen for an output. */
6617 if (asm_noperands (PATTERN (insn)) < 0)
6618 /* It's the compiler's fault. */
6619 fatal_insn ("VOIDmode on an output", insn);
6620 error_for_asm (insn, "output operand is constant in `asm'");
6621 /* Prevent crash--use something we know is valid. */
6623 old = gen_rtx_REG (mode, REGNO (reloadreg));
6626 if (GET_MODE (reloadreg) != mode)
6627 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6629 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6631 /* If we need two reload regs, set RELOADREG to the intermediate
6632 one, since it will be stored into OLD. We might need a secondary
6633 register only for an input reload, so check again here. */
6635 if (rl->secondary_out_reload >= 0)
6639 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6640 && reg_equiv_mem[REGNO (old)] != 0)
6641 real_old = reg_equiv_mem[REGNO (old)];
6643 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6647 rtx second_reloadreg = reloadreg;
6648 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6650 /* See if RELOADREG is to be used as a scratch register
6651 or as an intermediate register. */
6652 if (rl->secondary_out_icode != CODE_FOR_nothing)
6654 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6655 (real_old, second_reloadreg, reloadreg)));
6660 /* See if we need both a scratch and intermediate reload
6663 int secondary_reload = rl->secondary_out_reload;
6664 enum insn_code tertiary_icode
6665 = rld[secondary_reload].secondary_out_icode;
6667 if (GET_MODE (reloadreg) != mode)
6668 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6670 if (tertiary_icode != CODE_FOR_nothing)
6673 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6676 /* Copy primary reload reg to secondary reload reg.
6677 (Note that these have been swapped above, then
6678 secondary reload reg to OLD using our insn.) */
6680 /* If REAL_OLD is a paradoxical SUBREG, remove it
6681 and try to put the opposite SUBREG on
6683 if (GET_CODE (real_old) == SUBREG
6684 && (GET_MODE_SIZE (GET_MODE (real_old))
6685 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6686 && 0 != (tem = gen_lowpart_common
6687 (GET_MODE (SUBREG_REG (real_old)),
6689 real_old = SUBREG_REG (real_old), reloadreg = tem;
6691 gen_reload (reloadreg, second_reloadreg,
6692 rl->opnum, rl->when_needed);
6693 emit_insn ((GEN_FCN (tertiary_icode)
6694 (real_old, reloadreg, third_reloadreg)));
6699 /* Copy between the reload regs here and then to
6702 gen_reload (reloadreg, second_reloadreg,
6703 rl->opnum, rl->when_needed);
6709 /* Output the last reload insn. */
6714 /* Don't output the last reload if OLD is not the dest of
6715 INSN and is in the src and is clobbered by INSN. */
6716 if (! flag_expensive_optimizations
6717 || GET_CODE (old) != REG
6718 || !(set = single_set (insn))
6719 || rtx_equal_p (old, SET_DEST (set))
6720 || !reg_mentioned_p (old, SET_SRC (set))
6721 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6722 gen_reload (old, reloadreg, rl->opnum,
6726 /* Look at all insns we emitted, just to be safe. */
6727 for (p = get_insns (); p; p = NEXT_INSN (p))
6730 rtx pat = PATTERN (p);
6732 /* If this output reload doesn't come from a spill reg,
6733 clear any memory of reloaded copies of the pseudo reg.
6734 If this output reload comes from a spill reg,
6735 reg_has_output_reload will make this do nothing. */
6736 note_stores (pat, forget_old_reloads_1, NULL);
6738 if (reg_mentioned_p (rl->reg_rtx, pat))
6740 rtx set = single_set (insn);
6741 if (reload_spill_index[j] < 0
6743 && SET_SRC (set) == rl->reg_rtx)
6745 int src = REGNO (SET_SRC (set));
6747 reload_spill_index[j] = src;
6748 SET_HARD_REG_BIT (reg_is_output_reload, src);
6749 if (find_regno_note (insn, REG_DEAD, src))
6750 SET_HARD_REG_BIT (reg_reloaded_died, src);
6752 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6754 int s = rl->secondary_out_reload;
6755 set = single_set (p);
6756 /* If this reload copies only to the secondary reload
6757 register, the secondary reload does the actual
6759 if (s >= 0 && set == NULL_RTX)
6760 /* We can't tell what function the secondary reload
6761 has and where the actual store to the pseudo is
6762 made; leave new_spill_reg_store alone. */
6765 && SET_SRC (set) == rl->reg_rtx
6766 && SET_DEST (set) == rld[s].reg_rtx)
6768 /* Usually the next instruction will be the
6769 secondary reload insn; if we can confirm
6770 that it is, setting new_spill_reg_store to
6771 that insn will allow an extra optimization. */
6772 rtx s_reg = rld[s].reg_rtx;
6773 rtx next = NEXT_INSN (p);
6774 rld[s].out = rl->out;
6775 rld[s].out_reg = rl->out_reg;
6776 set = single_set (next);
6777 if (set && SET_SRC (set) == s_reg
6778 && ! new_spill_reg_store[REGNO (s_reg)])
6780 SET_HARD_REG_BIT (reg_is_output_reload,
6782 new_spill_reg_store[REGNO (s_reg)] = next;
6786 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6791 if (rl->when_needed == RELOAD_OTHER)
6793 emit_insns (other_output_reload_insns[rl->opnum]);
6794 other_output_reload_insns[rl->opnum] = get_insns ();
6797 output_reload_insns[rl->opnum] = get_insns ();
6799 if (flag_non_call_exceptions)
6800 copy_eh_notes (insn, get_insns ());
6805 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6806 and has the number J. */
6808 do_input_reload (chain, rl, j)
6809 struct insn_chain *chain;
6813 int expect_occurrences = 1;
6814 rtx insn = chain->insn;
6815 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6816 ? rl->in_reg : rl->in);
6819 /* AUTO_INC reloads need to be handled even if inherited. We got an
6820 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6821 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6822 && ! rtx_equal_p (rl->reg_rtx, old)
6823 && rl->reg_rtx != 0)
6824 emit_input_reload_insns (chain, rld + j, old, j);
6826 /* When inheriting a wider reload, we have a MEM in rl->in,
6827 e.g. inheriting a SImode output reload for
6828 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6829 if (optimize && reload_inherited[j] && rl->in
6830 && GET_CODE (rl->in) == MEM
6831 && GET_CODE (rl->in_reg) == MEM
6832 && reload_spill_index[j] >= 0
6833 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6836 = count_occurrences (PATTERN (insn), rl->in, 0) == 1 ? 0 : -1;
6837 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6840 /* If we are reloading a register that was recently stored in with an
6841 output-reload, see if we can prove there was
6842 actually no need to store the old value in it. */
6845 && (reload_inherited[j] || reload_override_in[j])
6847 && GET_CODE (rl->reg_rtx) == REG
6848 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6850 /* There doesn't seem to be any reason to restrict this to pseudos
6851 and doing so loses in the case where we are copying from a
6852 register of the wrong class. */
6853 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6854 >= FIRST_PSEUDO_REGISTER)
6856 /* The insn might have already some references to stackslots
6857 replaced by MEMs, while reload_out_reg still names the
6859 && (dead_or_set_p (insn,
6860 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6861 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6863 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6866 /* Do output reloading for reload RL, which is for the insn described by
6867 CHAIN and has the number J.
6868 ??? At some point we need to support handling output reloads of
6869 JUMP_INSNs or insns that set cc0. */
6871 do_output_reload (chain, rl, j)
6872 struct insn_chain *chain;
6877 rtx insn = chain->insn;
6878 /* If this is an output reload that stores something that is
6879 not loaded in this same reload, see if we can eliminate a previous
6881 rtx pseudo = rl->out_reg;
6884 && GET_CODE (pseudo) == REG
6885 && ! rtx_equal_p (rl->in_reg, pseudo)
6886 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6887 && reg_last_reload_reg[REGNO (pseudo)])
6889 int pseudo_no = REGNO (pseudo);
6890 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6892 /* We don't need to test full validity of last_regno for
6893 inherit here; we only want to know if the store actually
6894 matches the pseudo. */
6895 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6896 && reg_reloaded_contents[last_regno] == pseudo_no
6897 && spill_reg_store[last_regno]
6898 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6899 delete_output_reload (insn, j, last_regno);
6904 || rl->reg_rtx == old
6905 || rl->reg_rtx == 0)
6908 /* An output operand that dies right away does need a reload,
6909 but need not be copied from it. Show the new location in the
6911 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6912 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6914 XEXP (note, 0) = rl->reg_rtx;
6917 /* Likewise for a SUBREG of an operand that dies. */
6918 else if (GET_CODE (old) == SUBREG
6919 && GET_CODE (SUBREG_REG (old)) == REG
6920 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6923 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6927 else if (GET_CODE (old) == SCRATCH)
6928 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6929 but we don't want to make an output reload. */
6932 /* If is a JUMP_INSN, we can't support output reloads yet. */
6933 if (GET_CODE (insn) == JUMP_INSN)
6936 emit_output_reload_insns (chain, rld + j, j);
6939 /* Output insns to reload values in and out of the chosen reload regs. */
6942 emit_reload_insns (chain)
6943 struct insn_chain *chain;
6945 rtx insn = chain->insn;
6949 CLEAR_HARD_REG_SET (reg_reloaded_died);
6951 for (j = 0; j < reload_n_operands; j++)
6952 input_reload_insns[j] = input_address_reload_insns[j]
6953 = inpaddr_address_reload_insns[j]
6954 = output_reload_insns[j] = output_address_reload_insns[j]
6955 = outaddr_address_reload_insns[j]
6956 = other_output_reload_insns[j] = 0;
6957 other_input_address_reload_insns = 0;
6958 other_input_reload_insns = 0;
6959 operand_reload_insns = 0;
6960 other_operand_reload_insns = 0;
6962 /* Dump reloads into the dump file. */
6965 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6966 debug_reload_to_stream (rtl_dump_file);
6969 /* Now output the instructions to copy the data into and out of the
6970 reload registers. Do these in the order that the reloads were reported,
6971 since reloads of base and index registers precede reloads of operands
6972 and the operands may need the base and index registers reloaded. */
6974 for (j = 0; j < n_reloads; j++)
6977 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6978 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6980 do_input_reload (chain, rld + j, j);
6981 do_output_reload (chain, rld + j, j);
6984 /* Now write all the insns we made for reloads in the order expected by
6985 the allocation functions. Prior to the insn being reloaded, we write
6986 the following reloads:
6988 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6990 RELOAD_OTHER reloads.
6992 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6993 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6994 RELOAD_FOR_INPUT reload for the operand.
6996 RELOAD_FOR_OPADDR_ADDRS reloads.
6998 RELOAD_FOR_OPERAND_ADDRESS reloads.
7000 After the insn being reloaded, we write the following:
7002 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7003 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7004 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7005 reloads for the operand. The RELOAD_OTHER output reloads are
7006 output in descending order by reload number. */
7008 emit_insns_before (other_input_address_reload_insns, insn);
7009 emit_insns_before (other_input_reload_insns, insn);
7011 for (j = 0; j < reload_n_operands; j++)
7013 emit_insns_before (inpaddr_address_reload_insns[j], insn);
7014 emit_insns_before (input_address_reload_insns[j], insn);
7015 emit_insns_before (input_reload_insns[j], insn);
7018 emit_insns_before (other_operand_reload_insns, insn);
7019 emit_insns_before (operand_reload_insns, insn);
7021 for (j = 0; j < reload_n_operands; j++)
7023 rtx x = emit_insns_after (outaddr_address_reload_insns[j], insn);
7024 x = emit_insns_after (output_address_reload_insns[j], x);
7025 x = emit_insns_after (output_reload_insns[j], x);
7026 emit_insns_after (other_output_reload_insns[j], x);
7029 /* For all the spill regs newly reloaded in this instruction,
7030 record what they were reloaded from, so subsequent instructions
7031 can inherit the reloads.
7033 Update spill_reg_store for the reloads of this insn.
7034 Copy the elements that were updated in the loop above. */
7036 for (j = 0; j < n_reloads; j++)
7038 int r = reload_order[j];
7039 int i = reload_spill_index[r];
7041 /* If this is a non-inherited input reload from a pseudo, we must
7042 clear any memory of a previous store to the same pseudo. Only do
7043 something if there will not be an output reload for the pseudo
7045 if (rld[r].in_reg != 0
7046 && ! (reload_inherited[r] || reload_override_in[r]))
7048 rtx reg = rld[r].in_reg;
7050 if (GET_CODE (reg) == SUBREG)
7051 reg = SUBREG_REG (reg);
7053 if (GET_CODE (reg) == REG
7054 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7055 && ! reg_has_output_reload[REGNO (reg)])
7057 int nregno = REGNO (reg);
7059 if (reg_last_reload_reg[nregno])
7061 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7063 if (reg_reloaded_contents[last_regno] == nregno)
7064 spill_reg_store[last_regno] = 0;
7069 /* I is nonneg if this reload used a register.
7070 If rld[r].reg_rtx is 0, this is an optional reload
7071 that we opted to ignore. */
7073 if (i >= 0 && rld[r].reg_rtx != 0)
7075 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
7077 int part_reaches_end = 0;
7078 int all_reaches_end = 1;
7080 /* For a multi register reload, we need to check if all or part
7081 of the value lives to the end. */
7082 for (k = 0; k < nr; k++)
7084 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7085 rld[r].when_needed))
7086 part_reaches_end = 1;
7088 all_reaches_end = 0;
7091 /* Ignore reloads that don't reach the end of the insn in
7093 if (all_reaches_end)
7095 /* First, clear out memory of what used to be in this spill reg.
7096 If consecutive registers are used, clear them all. */
7098 for (k = 0; k < nr; k++)
7099 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7101 /* Maybe the spill reg contains a copy of reload_out. */
7103 && (GET_CODE (rld[r].out) == REG
7107 || GET_CODE (rld[r].out_reg) == REG))
7109 rtx out = (GET_CODE (rld[r].out) == REG
7113 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7114 int nregno = REGNO (out);
7115 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7116 : HARD_REGNO_NREGS (nregno,
7117 GET_MODE (rld[r].reg_rtx)));
7119 spill_reg_store[i] = new_spill_reg_store[i];
7120 spill_reg_stored_to[i] = out;
7121 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7123 /* If NREGNO is a hard register, it may occupy more than
7124 one register. If it does, say what is in the
7125 rest of the registers assuming that both registers
7126 agree on how many words the object takes. If not,
7127 invalidate the subsequent registers. */
7129 if (nregno < FIRST_PSEUDO_REGISTER)
7130 for (k = 1; k < nnr; k++)
7131 reg_last_reload_reg[nregno + k]
7133 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7134 REGNO (rld[r].reg_rtx) + k)
7137 /* Now do the inverse operation. */
7138 for (k = 0; k < nr; k++)
7140 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7141 reg_reloaded_contents[i + k]
7142 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7145 reg_reloaded_insn[i + k] = insn;
7146 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7150 /* Maybe the spill reg contains a copy of reload_in. Only do
7151 something if there will not be an output reload for
7152 the register being reloaded. */
7153 else if (rld[r].out_reg == 0
7155 && ((GET_CODE (rld[r].in) == REG
7156 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7157 && ! reg_has_output_reload[REGNO (rld[r].in)])
7158 || (GET_CODE (rld[r].in_reg) == REG
7159 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7160 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7165 if (GET_CODE (rld[r].in) == REG
7166 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7167 nregno = REGNO (rld[r].in);
7168 else if (GET_CODE (rld[r].in_reg) == REG)
7169 nregno = REGNO (rld[r].in_reg);
7171 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7173 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7174 : HARD_REGNO_NREGS (nregno,
7175 GET_MODE (rld[r].reg_rtx)));
7177 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7179 if (nregno < FIRST_PSEUDO_REGISTER)
7180 for (k = 1; k < nnr; k++)
7181 reg_last_reload_reg[nregno + k]
7183 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7184 REGNO (rld[r].reg_rtx) + k)
7187 /* Unless we inherited this reload, show we haven't
7188 recently done a store.
7189 Previous stores of inherited auto_inc expressions
7190 also have to be discarded. */
7191 if (! reload_inherited[r]
7192 || (rld[r].out && ! rld[r].out_reg))
7193 spill_reg_store[i] = 0;
7195 for (k = 0; k < nr; k++)
7197 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7198 reg_reloaded_contents[i + k]
7199 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7202 reg_reloaded_insn[i + k] = insn;
7203 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7208 /* However, if part of the reload reaches the end, then we must
7209 invalidate the old info for the part that survives to the end. */
7210 else if (part_reaches_end)
7212 for (k = 0; k < nr; k++)
7213 if (reload_reg_reaches_end_p (i + k,
7215 rld[r].when_needed))
7216 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7220 /* The following if-statement was #if 0'd in 1.34 (or before...).
7221 It's reenabled in 1.35 because supposedly nothing else
7222 deals with this problem. */
7224 /* If a register gets output-reloaded from a non-spill register,
7225 that invalidates any previous reloaded copy of it.
7226 But forget_old_reloads_1 won't get to see it, because
7227 it thinks only about the original insn. So invalidate it here. */
7228 if (i < 0 && rld[r].out != 0
7229 && (GET_CODE (rld[r].out) == REG
7230 || (GET_CODE (rld[r].out) == MEM
7231 && GET_CODE (rld[r].out_reg) == REG)))
7233 rtx out = (GET_CODE (rld[r].out) == REG
7234 ? rld[r].out : rld[r].out_reg);
7235 int nregno = REGNO (out);
7236 if (nregno >= FIRST_PSEUDO_REGISTER)
7238 rtx src_reg, store_insn = NULL_RTX;
7240 reg_last_reload_reg[nregno] = 0;
7242 /* If we can find a hard register that is stored, record
7243 the storing insn so that we may delete this insn with
7244 delete_output_reload. */
7245 src_reg = rld[r].reg_rtx;
7247 /* If this is an optional reload, try to find the source reg
7248 from an input reload. */
7251 rtx set = single_set (insn);
7252 if (set && SET_DEST (set) == rld[r].out)
7256 src_reg = SET_SRC (set);
7258 for (k = 0; k < n_reloads; k++)
7260 if (rld[k].in == src_reg)
7262 src_reg = rld[k].reg_rtx;
7269 store_insn = new_spill_reg_store[REGNO (src_reg)];
7270 if (src_reg && GET_CODE (src_reg) == REG
7271 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7273 int src_regno = REGNO (src_reg);
7274 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7275 /* The place where to find a death note varies with
7276 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7277 necessarily checked exactly in the code that moves
7278 notes, so just check both locations. */
7279 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7280 if (! note && store_insn)
7281 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7284 spill_reg_store[src_regno + nr] = store_insn;
7285 spill_reg_stored_to[src_regno + nr] = out;
7286 reg_reloaded_contents[src_regno + nr] = nregno;
7287 reg_reloaded_insn[src_regno + nr] = store_insn;
7288 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7289 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7290 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7292 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7294 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7296 reg_last_reload_reg[nregno] = src_reg;
7301 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7303 while (num_regs-- > 0)
7304 reg_last_reload_reg[nregno + num_regs] = 0;
7308 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7311 /* Emit code to perform a reload from IN (which may be a reload register) to
7312 OUT (which may also be a reload register). IN or OUT is from operand
7313 OPNUM with reload type TYPE.
7315 Returns first insn emitted. */
7318 gen_reload (out, in, opnum, type)
7322 enum reload_type type;
7324 rtx last = get_last_insn ();
7327 /* If IN is a paradoxical SUBREG, remove it and try to put the
7328 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7329 if (GET_CODE (in) == SUBREG
7330 && (GET_MODE_SIZE (GET_MODE (in))
7331 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7332 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7333 in = SUBREG_REG (in), out = tem;
7334 else if (GET_CODE (out) == SUBREG
7335 && (GET_MODE_SIZE (GET_MODE (out))
7336 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7337 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7338 out = SUBREG_REG (out), in = tem;
7340 /* How to do this reload can get quite tricky. Normally, we are being
7341 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7342 register that didn't get a hard register. In that case we can just
7343 call emit_move_insn.
7345 We can also be asked to reload a PLUS that adds a register or a MEM to
7346 another register, constant or MEM. This can occur during frame pointer
7347 elimination and while reloading addresses. This case is handled by
7348 trying to emit a single insn to perform the add. If it is not valid,
7349 we use a two insn sequence.
7351 Finally, we could be called to handle an 'o' constraint by putting
7352 an address into a register. In that case, we first try to do this
7353 with a named pattern of "reload_load_address". If no such pattern
7354 exists, we just emit a SET insn and hope for the best (it will normally
7355 be valid on machines that use 'o').
7357 This entire process is made complex because reload will never
7358 process the insns we generate here and so we must ensure that
7359 they will fit their constraints and also by the fact that parts of
7360 IN might be being reloaded separately and replaced with spill registers.
7361 Because of this, we are, in some sense, just guessing the right approach
7362 here. The one listed above seems to work.
7364 ??? At some point, this whole thing needs to be rethought. */
7366 if (GET_CODE (in) == PLUS
7367 && (GET_CODE (XEXP (in, 0)) == REG
7368 || GET_CODE (XEXP (in, 0)) == SUBREG
7369 || GET_CODE (XEXP (in, 0)) == MEM)
7370 && (GET_CODE (XEXP (in, 1)) == REG
7371 || GET_CODE (XEXP (in, 1)) == SUBREG
7372 || CONSTANT_P (XEXP (in, 1))
7373 || GET_CODE (XEXP (in, 1)) == MEM))
7375 /* We need to compute the sum of a register or a MEM and another
7376 register, constant, or MEM, and put it into the reload
7377 register. The best possible way of doing this is if the machine
7378 has a three-operand ADD insn that accepts the required operands.
7380 The simplest approach is to try to generate such an insn and see if it
7381 is recognized and matches its constraints. If so, it can be used.
7383 It might be better not to actually emit the insn unless it is valid,
7384 but we need to pass the insn as an operand to `recog' and
7385 `extract_insn' and it is simpler to emit and then delete the insn if
7386 not valid than to dummy things up. */
7388 rtx op0, op1, tem, insn;
7391 op0 = find_replacement (&XEXP (in, 0));
7392 op1 = find_replacement (&XEXP (in, 1));
7394 /* Since constraint checking is strict, commutativity won't be
7395 checked, so we need to do that here to avoid spurious failure
7396 if the add instruction is two-address and the second operand
7397 of the add is the same as the reload reg, which is frequently
7398 the case. If the insn would be A = B + A, rearrange it so
7399 it will be A = A + B as constrain_operands expects. */
7401 if (GET_CODE (XEXP (in, 1)) == REG
7402 && REGNO (out) == REGNO (XEXP (in, 1)))
7403 tem = op0, op0 = op1, op1 = tem;
7405 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7406 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7408 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7409 code = recog_memoized (insn);
7413 extract_insn (insn);
7414 /* We want constrain operands to treat this insn strictly in
7415 its validity determination, i.e., the way it would after reload
7417 if (constrain_operands (1))
7421 delete_insns_since (last);
7423 /* If that failed, we must use a conservative two-insn sequence.
7425 Use a move to copy one operand into the reload register. Prefer
7426 to reload a constant, MEM or pseudo since the move patterns can
7427 handle an arbitrary operand. If OP1 is not a constant, MEM or
7428 pseudo and OP1 is not a valid operand for an add instruction, then
7431 After reloading one of the operands into the reload register, add
7432 the reload register to the output register.
7434 If there is another way to do this for a specific machine, a
7435 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7438 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7440 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7441 || (GET_CODE (op1) == REG
7442 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7443 || (code != CODE_FOR_nothing
7444 && ! ((*insn_data[code].operand[2].predicate)
7445 (op1, insn_data[code].operand[2].mode))))
7446 tem = op0, op0 = op1, op1 = tem;
7448 gen_reload (out, op0, opnum, type);
7450 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7451 This fixes a problem on the 32K where the stack pointer cannot
7452 be used as an operand of an add insn. */
7454 if (rtx_equal_p (op0, op1))
7457 insn = emit_insn (gen_add2_insn (out, op1));
7459 /* If that failed, copy the address register to the reload register.
7460 Then add the constant to the reload register. */
7462 code = recog_memoized (insn);
7466 extract_insn (insn);
7467 /* We want constrain operands to treat this insn strictly in
7468 its validity determination, i.e., the way it would after reload
7470 if (constrain_operands (1))
7472 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7474 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7479 delete_insns_since (last);
7481 gen_reload (out, op1, opnum, type);
7482 insn = emit_insn (gen_add2_insn (out, op0));
7483 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7486 #ifdef SECONDARY_MEMORY_NEEDED
7487 /* If we need a memory location to do the move, do it that way. */
7488 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7489 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7490 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7491 REGNO_REG_CLASS (REGNO (out)),
7494 /* Get the memory to use and rewrite both registers to its mode. */
7495 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7497 if (GET_MODE (loc) != GET_MODE (out))
7498 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7500 if (GET_MODE (loc) != GET_MODE (in))
7501 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7503 gen_reload (loc, in, opnum, type);
7504 gen_reload (out, loc, opnum, type);
7508 /* If IN is a simple operand, use gen_move_insn. */
7509 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7510 emit_insn (gen_move_insn (out, in));
7512 #ifdef HAVE_reload_load_address
7513 else if (HAVE_reload_load_address)
7514 emit_insn (gen_reload_load_address (out, in));
7517 /* Otherwise, just write (set OUT IN) and hope for the best. */
7519 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7521 /* Return the first insn emitted.
7522 We can not just return get_last_insn, because there may have
7523 been multiple instructions emitted. Also note that gen_move_insn may
7524 emit more than one insn itself, so we can not assume that there is one
7525 insn emitted per emit_insn_before call. */
7527 return last ? NEXT_INSN (last) : get_insns ();
7530 /* Delete a previously made output-reload
7531 whose result we now believe is not needed.
7532 First we double-check.
7534 INSN is the insn now being processed.
7535 LAST_RELOAD_REG is the hard register number for which we want to delete
7536 the last output reload.
7537 J is the reload-number that originally used REG. The caller has made
7538 certain that reload J doesn't use REG any longer for input. */
7541 delete_output_reload (insn, j, last_reload_reg)
7544 int last_reload_reg;
7546 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7547 rtx reg = spill_reg_stored_to[last_reload_reg];
7550 int n_inherited = 0;
7554 /* Get the raw pseudo-register referred to. */
7556 while (GET_CODE (reg) == SUBREG)
7557 reg = SUBREG_REG (reg);
7558 substed = reg_equiv_memory_loc[REGNO (reg)];
7560 /* This is unsafe if the operand occurs more often in the current
7561 insn than it is inherited. */
7562 for (k = n_reloads - 1; k >= 0; k--)
7564 rtx reg2 = rld[k].in;
7567 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7568 reg2 = rld[k].in_reg;
7570 if (rld[k].out && ! rld[k].out_reg)
7571 reg2 = XEXP (rld[k].in_reg, 0);
7573 while (GET_CODE (reg2) == SUBREG)
7574 reg2 = SUBREG_REG (reg2);
7575 if (rtx_equal_p (reg2, reg))
7577 if (reload_inherited[k] || reload_override_in[k] || k == j)
7580 reg2 = rld[k].out_reg;
7583 while (GET_CODE (reg2) == SUBREG)
7584 reg2 = XEXP (reg2, 0);
7585 if (rtx_equal_p (reg2, reg))
7592 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7594 n_occurrences += count_occurrences (PATTERN (insn),
7595 eliminate_regs (substed, 0,
7597 if (n_occurrences > n_inherited)
7600 /* If the pseudo-reg we are reloading is no longer referenced
7601 anywhere between the store into it and here,
7602 and no jumps or labels intervene, then the value can get
7603 here through the reload reg alone.
7604 Otherwise, give up--return. */
7605 for (i1 = NEXT_INSN (output_reload_insn);
7606 i1 != insn; i1 = NEXT_INSN (i1))
7608 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7610 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7611 && reg_mentioned_p (reg, PATTERN (i1)))
7613 /* If this is USE in front of INSN, we only have to check that
7614 there are no more references than accounted for by inheritance. */
7615 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7617 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7618 i1 = NEXT_INSN (i1);
7620 if (n_occurrences <= n_inherited && i1 == insn)
7626 /* The caller has already checked that REG dies or is set in INSN.
7627 It has also checked that we are optimizing, and thus some inaccurancies
7628 in the debugging information are acceptable.
7629 So we could just delete output_reload_insn.
7630 But in some cases we can improve the debugging information without
7631 sacrificing optimization - maybe even improving the code:
7632 See if the pseudo reg has been completely replaced
7633 with reload regs. If so, delete the store insn
7634 and forget we had a stack slot for the pseudo. */
7635 if (rld[j].out != rld[j].in
7636 && REG_N_DEATHS (REGNO (reg)) == 1
7637 && REG_N_SETS (REGNO (reg)) == 1
7638 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7639 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7643 /* We know that it was used only between here
7644 and the beginning of the current basic block.
7645 (We also know that the last use before INSN was
7646 the output reload we are thinking of deleting, but never mind that.)
7647 Search that range; see if any ref remains. */
7648 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7650 rtx set = single_set (i2);
7652 /* Uses which just store in the pseudo don't count,
7653 since if they are the only uses, they are dead. */
7654 if (set != 0 && SET_DEST (set) == reg)
7656 if (GET_CODE (i2) == CODE_LABEL
7657 || GET_CODE (i2) == JUMP_INSN)
7659 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7660 && reg_mentioned_p (reg, PATTERN (i2)))
7662 /* Some other ref remains; just delete the output reload we
7664 delete_address_reloads (output_reload_insn, insn);
7665 delete_insn (output_reload_insn);
7670 /* Delete the now-dead stores into this pseudo. */
7671 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7673 rtx set = single_set (i2);
7675 if (set != 0 && SET_DEST (set) == reg)
7677 delete_address_reloads (i2, insn);
7678 /* This might be a basic block head,
7679 thus don't use delete_insn. */
7682 if (GET_CODE (i2) == CODE_LABEL
7683 || GET_CODE (i2) == JUMP_INSN)
7687 /* For the debugging info,
7688 say the pseudo lives in this reload reg. */
7689 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7690 alter_reg (REGNO (reg), -1);
7692 delete_address_reloads (output_reload_insn, insn);
7693 delete_insn (output_reload_insn);
7697 /* We are going to delete DEAD_INSN. Recursively delete loads of
7698 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7699 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7701 delete_address_reloads (dead_insn, current_insn)
7702 rtx dead_insn, current_insn;
7704 rtx set = single_set (dead_insn);
7705 rtx set2, dst, prev, next;
7708 rtx dst = SET_DEST (set);
7709 if (GET_CODE (dst) == MEM)
7710 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7712 /* If we deleted the store from a reloaded post_{in,de}c expression,
7713 we can delete the matching adds. */
7714 prev = PREV_INSN (dead_insn);
7715 next = NEXT_INSN (dead_insn);
7716 if (! prev || ! next)
7718 set = single_set (next);
7719 set2 = single_set (prev);
7721 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7722 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7723 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7725 dst = SET_DEST (set);
7726 if (! rtx_equal_p (dst, SET_DEST (set2))
7727 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7728 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7729 || (INTVAL (XEXP (SET_SRC (set), 1))
7730 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7732 delete_related_insns (prev);
7733 delete_related_insns (next);
7736 /* Subfunction of delete_address_reloads: process registers found in X. */
7738 delete_address_reloads_1 (dead_insn, x, current_insn)
7739 rtx dead_insn, x, current_insn;
7741 rtx prev, set, dst, i2;
7743 enum rtx_code code = GET_CODE (x);
7747 const char *fmt = GET_RTX_FORMAT (code);
7748 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7751 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7752 else if (fmt[i] == 'E')
7754 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7755 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7762 if (spill_reg_order[REGNO (x)] < 0)
7765 /* Scan backwards for the insn that sets x. This might be a way back due
7767 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7769 code = GET_CODE (prev);
7770 if (code == CODE_LABEL || code == JUMP_INSN)
7772 if (GET_RTX_CLASS (code) != 'i')
7774 if (reg_set_p (x, PATTERN (prev)))
7776 if (reg_referenced_p (x, PATTERN (prev)))
7779 if (! prev || INSN_UID (prev) < reload_first_uid)
7781 /* Check that PREV only sets the reload register. */
7782 set = single_set (prev);
7785 dst = SET_DEST (set);
7786 if (GET_CODE (dst) != REG
7787 || ! rtx_equal_p (dst, x))
7789 if (! reg_set_p (dst, PATTERN (dead_insn)))
7791 /* Check if DST was used in a later insn -
7792 it might have been inherited. */
7793 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7795 if (GET_CODE (i2) == CODE_LABEL)
7799 if (reg_referenced_p (dst, PATTERN (i2)))
7801 /* If there is a reference to the register in the current insn,
7802 it might be loaded in a non-inherited reload. If no other
7803 reload uses it, that means the register is set before
7805 if (i2 == current_insn)
7807 for (j = n_reloads - 1; j >= 0; j--)
7808 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7809 || reload_override_in[j] == dst)
7811 for (j = n_reloads - 1; j >= 0; j--)
7812 if (rld[j].in && rld[j].reg_rtx == dst)
7819 if (GET_CODE (i2) == JUMP_INSN)
7821 /* If DST is still live at CURRENT_INSN, check if it is used for
7822 any reload. Note that even if CURRENT_INSN sets DST, we still
7823 have to check the reloads. */
7824 if (i2 == current_insn)
7826 for (j = n_reloads - 1; j >= 0; j--)
7827 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7828 || reload_override_in[j] == dst)
7830 /* ??? We can't finish the loop here, because dst might be
7831 allocated to a pseudo in this block if no reload in this
7832 block needs any of the clsses containing DST - see
7833 spill_hard_reg. There is no easy way to tell this, so we
7834 have to scan till the end of the basic block. */
7836 if (reg_set_p (dst, PATTERN (i2)))
7840 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7841 reg_reloaded_contents[REGNO (dst)] = -1;
7845 /* Output reload-insns to reload VALUE into RELOADREG.
7846 VALUE is an autoincrement or autodecrement RTX whose operand
7847 is a register or memory location;
7848 so reloading involves incrementing that location.
7849 IN is either identical to VALUE, or some cheaper place to reload from.
7851 INC_AMOUNT is the number to increment or decrement by (always positive).
7852 This cannot be deduced from VALUE.
7854 Return the instruction that stores into RELOADREG. */
7857 inc_for_reload (reloadreg, in, value, inc_amount)
7862 /* REG or MEM to be copied and incremented. */
7863 rtx incloc = XEXP (value, 0);
7864 /* Nonzero if increment after copying. */
7865 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7871 rtx real_in = in == value ? XEXP (in, 0) : in;
7873 /* No hard register is equivalent to this register after
7874 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7875 we could inc/dec that register as well (maybe even using it for
7876 the source), but I'm not sure it's worth worrying about. */
7877 if (GET_CODE (incloc) == REG)
7878 reg_last_reload_reg[REGNO (incloc)] = 0;
7880 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7881 inc_amount = -inc_amount;
7883 inc = GEN_INT (inc_amount);
7885 /* If this is post-increment, first copy the location to the reload reg. */
7886 if (post && real_in != reloadreg)
7887 emit_insn (gen_move_insn (reloadreg, real_in));
7891 /* See if we can directly increment INCLOC. Use a method similar to
7892 that in gen_reload. */
7894 last = get_last_insn ();
7895 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7896 gen_rtx_PLUS (GET_MODE (incloc),
7899 code = recog_memoized (add_insn);
7902 extract_insn (add_insn);
7903 if (constrain_operands (1))
7905 /* If this is a pre-increment and we have incremented the value
7906 where it lives, copy the incremented value to RELOADREG to
7907 be used as an address. */
7910 emit_insn (gen_move_insn (reloadreg, incloc));
7915 delete_insns_since (last);
7918 /* If couldn't do the increment directly, must increment in RELOADREG.
7919 The way we do this depends on whether this is pre- or post-increment.
7920 For pre-increment, copy INCLOC to the reload register, increment it
7921 there, then save back. */
7925 if (in != reloadreg)
7926 emit_insn (gen_move_insn (reloadreg, real_in));
7927 emit_insn (gen_add2_insn (reloadreg, inc));
7928 store = emit_insn (gen_move_insn (incloc, reloadreg));
7933 Because this might be a jump insn or a compare, and because RELOADREG
7934 may not be available after the insn in an input reload, we must do
7935 the incrementation before the insn being reloaded for.
7937 We have already copied IN to RELOADREG. Increment the copy in
7938 RELOADREG, save that back, then decrement RELOADREG so it has
7939 the original value. */
7941 emit_insn (gen_add2_insn (reloadreg, inc));
7942 store = emit_insn (gen_move_insn (incloc, reloadreg));
7943 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7949 /* Return 1 if we are certain that the constraint-string STRING allows
7950 the hard register REG. Return 0 if we can't be sure of this. */
7953 constraint_accepts_reg_p (string, reg)
7958 int regno = true_regnum (reg);
7961 /* Initialize for first alternative. */
7963 /* Check that each alternative contains `g' or `r'. */
7965 switch (c = *string++)
7968 /* If an alternative lacks `g' or `r', we lose. */
7971 /* If an alternative lacks `g' or `r', we lose. */
7974 /* Initialize for next alternative. */
7979 /* Any general reg wins for this alternative. */
7980 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7984 /* Any reg in specified class wins for this alternative. */
7986 enum reg_class class = REG_CLASS_FROM_LETTER (c);
7988 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
7994 /* INSN is a no-op; delete it.
7995 If this sets the return value of the function, we must keep a USE around,
7996 in case this is in a different basic block than the final USE. Otherwise,
7997 we could loose important register lifeness information on
7998 SMALL_REGISTER_CLASSES machines, where return registers might be used as
7999 spills: subsequent passes assume that spill registers are dead at the end
8001 VALUE must be the return value in such a case, NULL otherwise. */
8003 reload_cse_delete_noop_set (insn, value)
8008 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
8009 INSN_CODE (insn) = -1;
8010 REG_NOTES (insn) = NULL_RTX;
8016 /* See whether a single set SET is a noop. */
8018 reload_cse_noop_set_p (set)
8021 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
8024 /* Try to simplify INSN. */
8026 reload_cse_simplify (insn)
8029 rtx body = PATTERN (insn);
8031 if (GET_CODE (body) == SET)
8035 /* Simplify even if we may think it is a no-op.
8036 We may think a memory load of a value smaller than WORD_SIZE
8037 is redundant because we haven't taken into account possible
8038 implicit extension. reload_cse_simplify_set() will bring
8039 this out, so it's safer to simplify before we delete. */
8040 count += reload_cse_simplify_set (body, insn);
8042 if (!count && reload_cse_noop_set_p (body))
8044 rtx value = SET_DEST (body);
8045 if (! REG_FUNCTION_VALUE_P (SET_DEST (body)))
8047 reload_cse_delete_noop_set (insn, value);
8052 apply_change_group ();
8054 reload_cse_simplify_operands (insn);
8056 else if (GET_CODE (body) == PARALLEL)
8060 rtx value = NULL_RTX;
8062 /* If every action in a PARALLEL is a noop, we can delete
8063 the entire PARALLEL. */
8064 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8066 rtx part = XVECEXP (body, 0, i);
8067 if (GET_CODE (part) == SET)
8069 if (! reload_cse_noop_set_p (part))
8071 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
8075 value = SET_DEST (part);
8078 else if (GET_CODE (part) != CLOBBER)
8084 reload_cse_delete_noop_set (insn, value);
8085 /* We're done with this insn. */
8089 /* It's not a no-op, but we can try to simplify it. */
8090 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8091 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8092 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8095 apply_change_group ();
8097 reload_cse_simplify_operands (insn);
8101 /* Do a very simple CSE pass over the hard registers.
8103 This function detects no-op moves where we happened to assign two
8104 different pseudo-registers to the same hard register, and then
8105 copied one to the other. Reload will generate a useless
8106 instruction copying a register to itself.
8108 This function also detects cases where we load a value from memory
8109 into two different registers, and (if memory is more expensive than
8110 registers) changes it to simply copy the first register into the
8113 Another optimization is performed that scans the operands of each
8114 instruction to see whether the value is already available in a
8115 hard register. It then replaces the operand with the hard register
8116 if possible, much like an optional reload would. */
8119 reload_cse_regs_1 (first)
8125 init_alias_analysis ();
8127 for (insn = first; insn; insn = NEXT_INSN (insn))
8130 reload_cse_simplify (insn);
8132 cselib_process_insn (insn);
8136 end_alias_analysis ();
8140 /* Call cse / combine like post-reload optimization phases.
8141 FIRST is the first instruction. */
8143 reload_cse_regs (first)
8146 reload_cse_regs_1 (first);
8148 reload_cse_move2add (first);
8149 if (flag_expensive_optimizations)
8150 reload_cse_regs_1 (first);
8153 /* Try to simplify a single SET instruction. SET is the set pattern.
8154 INSN is the instruction it came from.
8155 This function only handles one case: if we set a register to a value
8156 which is not a register, we try to find that value in some other register
8157 and change the set into a register copy. */
8160 reload_cse_simplify_set (set, insn)
8167 enum reg_class dclass;
8170 struct elt_loc_list *l;
8171 #ifdef LOAD_EXTEND_OP
8172 enum rtx_code extend_op = NIL;
8175 dreg = true_regnum (SET_DEST (set));
8179 src = SET_SRC (set);
8180 if (side_effects_p (src) || true_regnum (src) >= 0)
8183 dclass = REGNO_REG_CLASS (dreg);
8185 #ifdef LOAD_EXTEND_OP
8186 /* When replacing a memory with a register, we need to honor assumptions
8187 that combine made wrt the contents of sign bits. We'll do this by
8188 generating an extend instruction instead of a reg->reg copy. Thus
8189 the destination must be a register that we can widen. */
8190 if (GET_CODE (src) == MEM
8191 && GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD
8192 && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != NIL
8193 && GET_CODE (SET_DEST (set)) != REG)
8197 /* If memory loads are cheaper than register copies, don't change them. */
8198 if (GET_CODE (src) == MEM)
8199 old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
8200 else if (CONSTANT_P (src))
8201 old_cost = rtx_cost (src, SET);
8202 else if (GET_CODE (src) == REG)
8203 old_cost = REGISTER_MOVE_COST (GET_MODE (src),
8204 REGNO_REG_CLASS (REGNO (src)), dclass);
8207 old_cost = rtx_cost (src, SET);
8209 val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0);
8212 for (l = val->locs; l; l = l->next)
8214 rtx this_rtx = l->loc;
8217 if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0))
8219 #ifdef LOAD_EXTEND_OP
8220 if (extend_op != NIL)
8222 HOST_WIDE_INT this_val;
8224 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
8225 constants, such as SYMBOL_REF, cannot be extended. */
8226 if (GET_CODE (this_rtx) != CONST_INT)
8229 this_val = INTVAL (this_rtx);
8233 this_val &= GET_MODE_MASK (GET_MODE (src));
8236 /* ??? In theory we're already extended. */
8237 if (this_val == trunc_int_for_mode (this_val, GET_MODE (src)))
8242 this_rtx = GEN_INT (this_val);
8245 this_cost = rtx_cost (this_rtx, SET);
8247 else if (GET_CODE (this_rtx) == REG)
8249 #ifdef LOAD_EXTEND_OP
8250 if (extend_op != NIL)
8252 this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx);
8253 this_cost = rtx_cost (this_rtx, SET);
8257 this_cost = REGISTER_MOVE_COST (GET_MODE (this_rtx),
8258 REGNO_REG_CLASS (REGNO (this_rtx)),
8264 /* If equal costs, prefer registers over anything else. That
8265 tends to lead to smaller instructions on some machines. */
8266 if (this_cost < old_cost
8267 || (this_cost == old_cost
8268 && GET_CODE (this_rtx) == REG
8269 && GET_CODE (SET_SRC (set)) != REG))
8271 #ifdef LOAD_EXTEND_OP
8272 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD
8273 && extend_op != NIL)
8275 rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set)));
8276 ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set));
8277 validate_change (insn, &SET_DEST (set), wide_dest, 1);
8281 validate_change (insn, &SET_SRC (set), copy_rtx (this_rtx), 1);
8282 old_cost = this_cost, did_change = 1;
8289 /* Try to replace operands in INSN with equivalent values that are already
8290 in registers. This can be viewed as optional reloading.
8292 For each non-register operand in the insn, see if any hard regs are
8293 known to be equivalent to that operand. Record the alternatives which
8294 can accept these hard registers. Among all alternatives, select the
8295 ones which are better or equal to the one currently matching, where
8296 "better" is in terms of '?' and '!' constraints. Among the remaining
8297 alternatives, select the one which replaces most operands with
8301 reload_cse_simplify_operands (insn)
8306 /* For each operand, all registers that are equivalent to it. */
8307 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
8309 const char *constraints[MAX_RECOG_OPERANDS];
8311 /* Vector recording how bad an alternative is. */
8312 int *alternative_reject;
8313 /* Vector recording how many registers can be introduced by choosing
8314 this alternative. */
8315 int *alternative_nregs;
8316 /* Array of vectors recording, for each operand and each alternative,
8317 which hard register to substitute, or -1 if the operand should be
8319 int *op_alt_regno[MAX_RECOG_OPERANDS];
8320 /* Array of alternatives, sorted in order of decreasing desirability. */
8321 int *alternative_order;
8322 rtx reg = gen_rtx_REG (VOIDmode, -1);
8324 extract_insn (insn);
8326 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8329 /* Figure out which alternative currently matches. */
8330 if (! constrain_operands (1))
8331 fatal_insn_not_found (insn);
8333 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8334 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8335 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8336 memset ((char *)alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
8337 memset ((char *)alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
8339 /* For each operand, find out which regs are equivalent. */
8340 for (i = 0; i < recog_data.n_operands; i++)
8343 struct elt_loc_list *l;
8345 CLEAR_HARD_REG_SET (equiv_regs[i]);
8347 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8348 right, so avoid the problem here. Likewise if we have a constant
8349 and the insn pattern doesn't tell us the mode we need. */
8350 if (GET_CODE (recog_data.operand[i]) == CODE_LABEL
8351 || (CONSTANT_P (recog_data.operand[i])
8352 && recog_data.operand_mode[i] == VOIDmode))
8355 v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0);
8359 for (l = v->locs; l; l = l->next)
8360 if (GET_CODE (l->loc) == REG)
8361 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
8364 for (i = 0; i < recog_data.n_operands; i++)
8366 enum machine_mode mode;
8370 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8371 for (j = 0; j < recog_data.n_alternatives; j++)
8372 op_alt_regno[i][j] = -1;
8374 p = constraints[i] = recog_data.constraints[i];
8375 mode = recog_data.operand_mode[i];
8377 /* Add the reject values for each alternative given by the constraints
8378 for this operand. */
8386 alternative_reject[j] += 3;
8388 alternative_reject[j] += 300;
8391 /* We won't change operands which are already registers. We
8392 also don't want to modify output operands. */
8393 regno = true_regnum (recog_data.operand[i]);
8395 || constraints[i][0] == '='
8396 || constraints[i][0] == '+')
8399 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8401 int class = (int) NO_REGS;
8403 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
8406 REGNO (reg) = regno;
8407 PUT_MODE (reg, mode);
8409 /* We found a register equal to this operand. Now look for all
8410 alternatives that can accept this register and have not been
8411 assigned a register they can use yet. */
8420 case '=': case '+': case '?':
8421 case '#': case '&': case '!':
8423 case '0': case '1': case '2': case '3': case '4':
8424 case '5': case '6': case '7': case '8': case '9':
8425 case 'm': case '<': case '>': case 'V': case 'o':
8426 case 'E': case 'F': case 'G': case 'H':
8427 case 's': case 'i': case 'n':
8428 case 'I': case 'J': case 'K': case 'L':
8429 case 'M': case 'N': case 'O': case 'P':
8431 /* These don't say anything we care about. */
8435 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8440 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
8443 case ',': case '\0':
8444 /* See if REGNO fits this alternative, and set it up as the
8445 replacement register if we don't have one for this
8446 alternative yet and the operand being replaced is not
8447 a cheap CONST_INT. */
8448 if (op_alt_regno[i][j] == -1
8449 && reg_fits_class_p (reg, class, 0, mode)
8450 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8451 || (rtx_cost (recog_data.operand[i], SET)
8452 > rtx_cost (reg, SET))))
8454 alternative_nregs[j]++;
8455 op_alt_regno[i][j] = regno;
8467 /* Record all alternatives which are better or equal to the currently
8468 matching one in the alternative_order array. */
8469 for (i = j = 0; i < recog_data.n_alternatives; i++)
8470 if (alternative_reject[i] <= alternative_reject[which_alternative])
8471 alternative_order[j++] = i;
8472 recog_data.n_alternatives = j;
8474 /* Sort it. Given a small number of alternatives, a dumb algorithm
8475 won't hurt too much. */
8476 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8479 int best_reject = alternative_reject[alternative_order[i]];
8480 int best_nregs = alternative_nregs[alternative_order[i]];
8483 for (j = i + 1; j < recog_data.n_alternatives; j++)
8485 int this_reject = alternative_reject[alternative_order[j]];
8486 int this_nregs = alternative_nregs[alternative_order[j]];
8488 if (this_reject < best_reject
8489 || (this_reject == best_reject && this_nregs < best_nregs))
8492 best_reject = this_reject;
8493 best_nregs = this_nregs;
8497 tmp = alternative_order[best];
8498 alternative_order[best] = alternative_order[i];
8499 alternative_order[i] = tmp;
8502 /* Substitute the operands as determined by op_alt_regno for the best
8504 j = alternative_order[0];
8506 for (i = 0; i < recog_data.n_operands; i++)
8508 enum machine_mode mode = recog_data.operand_mode[i];
8509 if (op_alt_regno[i][j] == -1)
8512 validate_change (insn, recog_data.operand_loc[i],
8513 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8516 for (i = recog_data.n_dups - 1; i >= 0; i--)
8518 int op = recog_data.dup_num[i];
8519 enum machine_mode mode = recog_data.operand_mode[op];
8521 if (op_alt_regno[op][j] == -1)
8524 validate_change (insn, recog_data.dup_loc[i],
8525 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8528 return apply_change_group ();
8531 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8533 This code might also be useful when reload gave up on reg+reg addresssing
8534 because of clashes between the return register and INDEX_REG_CLASS. */
8536 /* The maximum number of uses of a register we can keep track of to
8537 replace them with reg+reg addressing. */
8538 #define RELOAD_COMBINE_MAX_USES 6
8540 /* INSN is the insn where a register has ben used, and USEP points to the
8541 location of the register within the rtl. */
8542 struct reg_use { rtx insn, *usep; };
8544 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8545 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8546 indicates where it becomes live again.
8547 Otherwise, USE_INDEX is the index of the last encountered use of the
8548 register (which is first among these we have seen since we scan backwards),
8549 OFFSET contains the constant offset that is added to the register in
8550 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8551 last, of these uses.
8552 STORE_RUID is always meaningful if we only want to use a value in a
8553 register in a different place: it denotes the next insn in the insn
8554 stream (i.e. the last ecountered) that sets or clobbers the register. */
8557 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8562 } reg_state[FIRST_PSEUDO_REGISTER];
8564 /* Reverse linear uid. This is increased in reload_combine while scanning
8565 the instructions from last to first. It is used to set last_label_ruid
8566 and the store_ruid / use_ruid fields in reg_state. */
8567 static int reload_combine_ruid;
8569 #define LABEL_LIVE(LABEL) \
8570 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8576 int first_index_reg = -1;
8577 int last_index_reg = 0;
8580 int last_label_ruid;
8581 int min_labelno, n_labels;
8582 HARD_REG_SET ever_live_at_start, *label_live;
8584 /* If reg+reg can be used in offsetable memory addresses, the main chunk of
8585 reload has already used it where appropriate, so there is no use in
8586 trying to generate it now. */
8587 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8590 /* To avoid wasting too much time later searching for an index register,
8591 determine the minimum and maximum index register numbers. */
8592 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8593 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
8595 if (first_index_reg == -1)
8596 first_index_reg = r;
8601 /* If no index register is available, we can quit now. */
8602 if (first_index_reg == -1)
8605 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8606 information is a bit fuzzy immediately after reload, but it's
8607 still good enough to determine which registers are live at a jump
8609 min_labelno = get_first_label_num ();
8610 n_labels = max_label_num () - min_labelno;
8611 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8612 CLEAR_HARD_REG_SET (ever_live_at_start);
8614 for (i = n_basic_blocks - 1; i >= 0; i--)
8616 insn = BLOCK_HEAD (i);
8617 if (GET_CODE (insn) == CODE_LABEL)
8621 REG_SET_TO_HARD_REG_SET (live,
8622 BASIC_BLOCK (i)->global_live_at_start);
8623 compute_use_by_pseudos (&live,
8624 BASIC_BLOCK (i)->global_live_at_start);
8625 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8626 IOR_HARD_REG_SET (ever_live_at_start, live);
8630 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8631 last_label_ruid = reload_combine_ruid = 0;
8632 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8634 reg_state[r].store_ruid = reload_combine_ruid;
8636 reg_state[r].use_index = -1;
8638 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8641 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8645 /* We cannot do our optimization across labels. Invalidating all the use
8646 information we have would be costly, so we just note where the label
8647 is and then later disable any optimization that would cross it. */
8648 if (GET_CODE (insn) == CODE_LABEL)
8649 last_label_ruid = reload_combine_ruid;
8650 else if (GET_CODE (insn) == BARRIER)
8651 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8652 if (! fixed_regs[r])
8653 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8655 if (! INSN_P (insn))
8658 reload_combine_ruid++;
8660 /* Look for (set (REGX) (CONST_INT))
8661 (set (REGX) (PLUS (REGX) (REGY)))
8663 ... (MEM (REGX)) ...
8665 (set (REGZ) (CONST_INT))
8667 ... (MEM (PLUS (REGZ) (REGY)))... .
8669 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8670 and that we know all uses of REGX before it dies. */
8671 set = single_set (insn);
8673 && GET_CODE (SET_DEST (set)) == REG
8674 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
8675 GET_MODE (SET_DEST (set)))
8677 && GET_CODE (SET_SRC (set)) == PLUS
8678 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
8679 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
8680 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
8682 rtx reg = SET_DEST (set);
8683 rtx plus = SET_SRC (set);
8684 rtx base = XEXP (plus, 1);
8685 rtx prev = prev_nonnote_insn (insn);
8686 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
8687 unsigned int regno = REGNO (reg);
8688 rtx const_reg = NULL_RTX;
8689 rtx reg_sum = NULL_RTX;
8691 /* Now, we need an index register.
8692 We'll set index_reg to this index register, const_reg to the
8693 register that is to be loaded with the constant
8694 (denoted as REGZ in the substitution illustration above),
8695 and reg_sum to the register-register that we want to use to
8696 substitute uses of REG (typically in MEMs) with.
8697 First check REG and BASE for being index registers;
8698 we can use them even if they are not dead. */
8699 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
8700 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8708 /* Otherwise, look for a free index register. Since we have
8709 checked above that neiter REG nor BASE are index registers,
8710 if we find anything at all, it will be different from these
8712 for (i = first_index_reg; i <= last_index_reg; i++)
8714 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8716 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
8717 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
8718 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
8720 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
8722 const_reg = index_reg;
8723 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
8729 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8730 (REGY), i.e. BASE, is not clobbered before the last use we'll
8733 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
8734 && rtx_equal_p (SET_DEST (prev_set), reg)
8735 && reg_state[regno].use_index >= 0
8736 && (reg_state[REGNO (base)].store_ruid
8737 <= reg_state[regno].use_ruid)
8742 /* Change destination register and, if necessary, the
8743 constant value in PREV, the constant loading instruction. */
8744 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
8745 if (reg_state[regno].offset != const0_rtx)
8746 validate_change (prev,
8747 &SET_SRC (prev_set),
8748 GEN_INT (INTVAL (SET_SRC (prev_set))
8749 + INTVAL (reg_state[regno].offset)),
8752 /* Now for every use of REG that we have recorded, replace REG
8754 for (i = reg_state[regno].use_index;
8755 i < RELOAD_COMBINE_MAX_USES; i++)
8756 validate_change (reg_state[regno].reg_use[i].insn,
8757 reg_state[regno].reg_use[i].usep,
8760 if (apply_change_group ())
8764 /* Delete the reg-reg addition. */
8767 if (reg_state[regno].offset != const0_rtx)
8768 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8770 for (np = ®_NOTES (prev); *np;)
8772 if (REG_NOTE_KIND (*np) == REG_EQUAL
8773 || REG_NOTE_KIND (*np) == REG_EQUIV)
8774 *np = XEXP (*np, 1);
8776 np = &XEXP (*np, 1);
8779 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8780 reg_state[REGNO (const_reg)].store_ruid
8781 = reload_combine_ruid;
8787 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
8789 if (GET_CODE (insn) == CALL_INSN)
8793 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8794 if (call_used_regs[r])
8796 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8797 reg_state[r].store_ruid = reload_combine_ruid;
8800 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
8801 link = XEXP (link, 1))
8803 rtx usage_rtx = XEXP (XEXP (link, 0), 0);
8804 if (GET_CODE (usage_rtx) == REG)
8807 unsigned int start_reg = REGNO (usage_rtx);
8808 unsigned int num_regs =
8809 HARD_REGNO_NREGS (start_reg, GET_MODE (usage_rtx));
8810 unsigned int end_reg = start_reg + num_regs - 1;
8811 for (i = start_reg; i <= end_reg; i++)
8812 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
8814 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8815 reg_state[i].store_ruid = reload_combine_ruid;
8818 reg_state[i].use_index = -1;
8823 else if (GET_CODE (insn) == JUMP_INSN
8824 && GET_CODE (PATTERN (insn)) != RETURN)
8826 /* Non-spill registers might be used at the call destination in
8827 some unknown fashion, so we have to mark the unknown use. */
8830 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
8831 && JUMP_LABEL (insn))
8832 live = &LABEL_LIVE (JUMP_LABEL (insn));
8834 live = &ever_live_at_start;
8836 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8837 if (TEST_HARD_REG_BIT (*live, i))
8838 reg_state[i].use_index = -1;
8841 reload_combine_note_use (&PATTERN (insn), insn);
8842 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8844 if (REG_NOTE_KIND (note) == REG_INC
8845 && GET_CODE (XEXP (note, 0)) == REG)
8847 int regno = REGNO (XEXP (note, 0));
8849 reg_state[regno].store_ruid = reload_combine_ruid;
8850 reg_state[regno].use_index = -1;
8858 /* Check if DST is a register or a subreg of a register; if it is,
8859 update reg_state[regno].store_ruid and reg_state[regno].use_index
8860 accordingly. Called via note_stores from reload_combine. */
8863 reload_combine_note_store (dst, set, data)
8865 void *data ATTRIBUTE_UNUSED;
8869 enum machine_mode mode = GET_MODE (dst);
8871 if (GET_CODE (dst) == SUBREG)
8873 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
8874 GET_MODE (SUBREG_REG (dst)),
8877 dst = SUBREG_REG (dst);
8879 if (GET_CODE (dst) != REG)
8881 regno += REGNO (dst);
8883 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8884 careful with registers / register parts that are not full words.
8886 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8887 if (GET_CODE (set) != SET
8888 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
8889 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
8890 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
8892 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8894 reg_state[i].use_index = -1;
8895 reg_state[i].store_ruid = reload_combine_ruid;
8900 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8902 reg_state[i].store_ruid = reload_combine_ruid;
8903 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8908 /* XP points to a piece of rtl that has to be checked for any uses of
8910 *XP is the pattern of INSN, or a part of it.
8911 Called from reload_combine, and recursively by itself. */
8913 reload_combine_note_use (xp, insn)
8917 enum rtx_code code = x->code;
8920 rtx offset = const0_rtx; /* For the REG case below. */
8925 if (GET_CODE (SET_DEST (x)) == REG)
8927 reload_combine_note_use (&SET_SRC (x), insn);
8933 /* If this is the USE of a return value, we can't change it. */
8934 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
8936 /* Mark the return register as used in an unknown fashion. */
8937 rtx reg = XEXP (x, 0);
8938 int regno = REGNO (reg);
8939 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
8941 while (--nregs >= 0)
8942 reg_state[regno + nregs].use_index = -1;
8948 if (GET_CODE (SET_DEST (x)) == REG)
8950 /* No spurious CLOBBERs of pseudo registers may remain. */
8951 if (REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER)
8958 /* We are interested in (plus (reg) (const_int)) . */
8959 if (GET_CODE (XEXP (x, 0)) != REG
8960 || GET_CODE (XEXP (x, 1)) != CONST_INT)
8962 offset = XEXP (x, 1);
8967 int regno = REGNO (x);
8971 /* No spurious USEs of pseudo registers may remain. */
8972 if (regno >= FIRST_PSEUDO_REGISTER)
8975 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x));
8977 /* We can't substitute into multi-hard-reg uses. */
8980 while (--nregs >= 0)
8981 reg_state[regno + nregs].use_index = -1;
8985 /* If this register is already used in some unknown fashion, we
8987 If we decrement the index from zero to -1, we can't store more
8988 uses, so this register becomes used in an unknown fashion. */
8989 use_index = --reg_state[regno].use_index;
8993 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
8995 /* We have found another use for a register that is already
8996 used later. Check if the offsets match; if not, mark the
8997 register as used in an unknown fashion. */
8998 if (! rtx_equal_p (offset, reg_state[regno].offset))
9000 reg_state[regno].use_index = -1;
9006 /* This is the first use of this register we have seen since we
9007 marked it as dead. */
9008 reg_state[regno].offset = offset;
9009 reg_state[regno].use_ruid = reload_combine_ruid;
9011 reg_state[regno].reg_use[use_index].insn = insn;
9012 reg_state[regno].reg_use[use_index].usep = xp;
9020 /* Recursively process the components of X. */
9021 fmt = GET_RTX_FORMAT (code);
9022 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9025 reload_combine_note_use (&XEXP (x, i), insn);
9026 else if (fmt[i] == 'E')
9028 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9029 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9034 /* See if we can reduce the cost of a constant by replacing a move
9035 with an add. We track situations in which a register is set to a
9036 constant or to a register plus a constant. */
9037 /* We cannot do our optimization across labels. Invalidating all the
9038 information about register contents we have would be costly, so we
9039 use move2add_last_label_luid to note where the label is and then
9040 later disable any optimization that would cross it.
9041 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9042 reg_set_luid[n] is greater than last_label_luid[n] . */
9043 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9045 /* If reg_base_reg[n] is negative, register n has been set to
9046 reg_offset[n] in mode reg_mode[n] .
9047 If reg_base_reg[n] is non-negative, register n has been set to the
9048 sum of reg_offset[n] and the value of register reg_base_reg[n]
9049 before reg_set_luid[n], calculated in mode reg_mode[n] . */
9050 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
9051 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9052 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9054 /* move2add_luid is linearily increased while scanning the instructions
9055 from first to last. It is used to set reg_set_luid in
9056 reload_cse_move2add and move2add_note_store. */
9057 static int move2add_luid;
9059 /* move2add_last_label_luid is set whenever a label is found. Labels
9060 invalidate all previously collected reg_offset data. */
9061 static int move2add_last_label_luid;
9063 /* Generate a CONST_INT and force it in the range of MODE. */
9065 static HOST_WIDE_INT
9066 sext_for_mode (mode, value)
9067 enum machine_mode mode;
9068 HOST_WIDE_INT value;
9070 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
9071 int width = GET_MODE_BITSIZE (mode);
9073 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
9075 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
9076 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
9077 cval |= (HOST_WIDE_INT) -1 << width;
9082 /* ??? We don't know how zero / sign extension is handled, hence we
9083 can't go from a narrower to a wider mode. */
9084 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
9085 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
9086 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
9087 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \
9088 GET_MODE_BITSIZE (INMODE))))
9091 reload_cse_move2add (first)
9097 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9098 reg_set_luid[i] = 0;
9100 move2add_last_label_luid = 0;
9102 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
9106 if (GET_CODE (insn) == CODE_LABEL)
9108 move2add_last_label_luid = move2add_luid;
9109 /* We're going to increment move2add_luid twice after a
9110 label, so that we can use move2add_last_label_luid + 1 as
9111 the luid for constants. */
9115 if (! INSN_P (insn))
9117 pat = PATTERN (insn);
9118 /* For simplicity, we only perform this optimization on
9119 straightforward SETs. */
9120 if (GET_CODE (pat) == SET
9121 && GET_CODE (SET_DEST (pat)) == REG)
9123 rtx reg = SET_DEST (pat);
9124 int regno = REGNO (reg);
9125 rtx src = SET_SRC (pat);
9127 /* Check if we have valid information on the contents of this
9128 register in the mode of REG. */
9129 if (reg_set_luid[regno] > move2add_last_label_luid
9130 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno]))
9132 /* Try to transform (set (REGX) (CONST_INT A))
9134 (set (REGX) (CONST_INT B))
9136 (set (REGX) (CONST_INT A))
9138 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9140 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
9143 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9145 - reg_offset[regno]));
9146 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9147 use (set (reg) (reg)) instead.
9148 We don't delete this insn, nor do we convert it into a
9149 note, to avoid losing register notes or the return
9150 value flag. jump2 already knowns how to get rid of
9152 if (new_src == const0_rtx)
9153 success = validate_change (insn, &SET_SRC (pat), reg, 0);
9154 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
9155 && have_add2_insn (reg, new_src))
9156 success = validate_change (insn, &PATTERN (insn),
9157 gen_add2_insn (reg, new_src), 0);
9158 reg_set_luid[regno] = move2add_luid;
9159 reg_mode[regno] = GET_MODE (reg);
9160 reg_offset[regno] = INTVAL (src);
9164 /* Try to transform (set (REGX) (REGY))
9165 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9168 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9171 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9173 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9174 else if (GET_CODE (src) == REG
9175 && reg_set_luid[regno] == reg_set_luid[REGNO (src)]
9176 && reg_base_reg[regno] == reg_base_reg[REGNO (src)]
9177 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg),
9178 reg_mode[REGNO (src)]))
9180 rtx next = next_nonnote_insn (insn);
9183 set = single_set (next);
9185 && SET_DEST (set) == reg
9186 && GET_CODE (SET_SRC (set)) == PLUS
9187 && XEXP (SET_SRC (set), 0) == reg
9188 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9190 rtx src3 = XEXP (SET_SRC (set), 1);
9191 HOST_WIDE_INT added_offset = INTVAL (src3);
9192 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)];
9193 HOST_WIDE_INT regno_offset = reg_offset[regno];
9194 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9200 if (new_src == const0_rtx)
9201 /* See above why we create (set (reg) (reg)) here. */
9203 = validate_change (next, &SET_SRC (set), reg, 0);
9204 else if ((rtx_cost (new_src, PLUS)
9205 < COSTS_N_INSNS (1) + rtx_cost (src3, SET))
9206 && have_add2_insn (reg, new_src))
9208 = validate_change (next, &PATTERN (next),
9209 gen_add2_insn (reg, new_src), 0);
9213 reg_mode[regno] = GET_MODE (reg);
9214 reg_offset[regno] = sext_for_mode (GET_MODE (reg),
9223 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9225 if (REG_NOTE_KIND (note) == REG_INC
9226 && GET_CODE (XEXP (note, 0)) == REG)
9228 /* Reset the information about this register. */
9229 int regno = REGNO (XEXP (note, 0));
9230 if (regno < FIRST_PSEUDO_REGISTER)
9231 reg_set_luid[regno] = 0;
9234 note_stores (PATTERN (insn), move2add_note_store, NULL);
9235 /* If this is a CALL_INSN, all call used registers are stored with
9237 if (GET_CODE (insn) == CALL_INSN)
9239 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9241 if (call_used_regs[i])
9242 /* Reset the information about this register. */
9243 reg_set_luid[i] = 0;
9249 /* SET is a SET or CLOBBER that sets DST.
9250 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9251 Called from reload_cse_move2add via note_stores. */
9254 move2add_note_store (dst, set, data)
9256 void *data ATTRIBUTE_UNUSED;
9258 unsigned int regno = 0;
9260 enum machine_mode mode = GET_MODE (dst);
9262 if (GET_CODE (dst) == SUBREG)
9264 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
9265 GET_MODE (SUBREG_REG (dst)),
9268 dst = SUBREG_REG (dst);
9271 /* Some targets do argument pushes without adding REG_INC notes. */
9273 if (GET_CODE (dst) == MEM)
9275 dst = XEXP (dst, 0);
9276 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC
9277 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC)
9278 reg_set_luid[REGNO (XEXP (dst, 0))] = 0;
9281 if (GET_CODE (dst) != REG)
9284 regno += REGNO (dst);
9286 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9287 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9288 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9289 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9291 rtx src = SET_SRC (set);
9293 HOST_WIDE_INT offset;
9295 /* This may be different from mode, if SET_DEST (set) is a
9297 enum machine_mode dst_mode = GET_MODE (dst);
9299 switch (GET_CODE (src))
9302 if (GET_CODE (XEXP (src, 0)) == REG)
9304 base_reg = XEXP (src, 0);
9306 if (GET_CODE (XEXP (src, 1)) == CONST_INT)
9307 offset = INTVAL (XEXP (src, 1));
9308 else if (GET_CODE (XEXP (src, 1)) == REG
9309 && (reg_set_luid[REGNO (XEXP (src, 1))]
9310 > move2add_last_label_luid)
9311 && (MODES_OK_FOR_MOVE2ADD
9312 (dst_mode, reg_mode[REGNO (XEXP (src, 1))])))
9314 if (reg_base_reg[REGNO (XEXP (src, 1))] < 0)
9315 offset = reg_offset[REGNO (XEXP (src, 1))];
9316 /* Maybe the first register is known to be a
9318 else if (reg_set_luid[REGNO (base_reg)]
9319 > move2add_last_label_luid
9320 && (MODES_OK_FOR_MOVE2ADD
9321 (dst_mode, reg_mode[REGNO (XEXP (src, 1))]))
9322 && reg_base_reg[REGNO (base_reg)] < 0)
9324 offset = reg_offset[REGNO (base_reg)];
9325 base_reg = XEXP (src, 1);
9344 /* Start tracking the register as a constant. */
9345 reg_base_reg[regno] = -1;
9346 reg_offset[regno] = INTVAL (SET_SRC (set));
9347 /* We assign the same luid to all registers set to constants. */
9348 reg_set_luid[regno] = move2add_last_label_luid + 1;
9349 reg_mode[regno] = mode;
9354 /* Invalidate the contents of the register. */
9355 reg_set_luid[regno] = 0;
9359 base_regno = REGNO (base_reg);
9360 /* If information about the base register is not valid, set it
9361 up as a new base register, pretending its value is known
9362 starting from the current insn. */
9363 if (reg_set_luid[base_regno] <= move2add_last_label_luid)
9365 reg_base_reg[base_regno] = base_regno;
9366 reg_offset[base_regno] = 0;
9367 reg_set_luid[base_regno] = move2add_luid;
9368 reg_mode[base_regno] = mode;
9370 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode,
9371 reg_mode[base_regno]))
9374 reg_mode[regno] = mode;
9376 /* Copy base information from our base register. */
9377 reg_set_luid[regno] = reg_set_luid[base_regno];
9378 reg_base_reg[regno] = reg_base_reg[base_regno];
9380 /* Compute the sum of the offsets or constants. */
9381 reg_offset[regno] = sext_for_mode (dst_mode,
9383 + reg_offset[base_regno]);
9387 unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode);
9389 for (i = regno; i < endregno; i++)
9390 /* Reset the information about this register. */
9391 reg_set_luid[i] = 0;
9397 add_auto_inc_notes (insn, x)
9401 enum rtx_code code = GET_CODE (x);
9405 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9408 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9412 /* Scan all the operand sub-expressions. */
9413 fmt = GET_RTX_FORMAT (code);
9414 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9417 add_auto_inc_notes (insn, XEXP (x, i));
9418 else if (fmt[i] == 'E')
9419 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9420 add_auto_inc_notes (insn, XVECEXP (x, i, j));
9425 /* Copy EH notes from an insn to its reloads. */
9427 copy_eh_notes (insn, x)
9431 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
9434 for (; x != 0; x = NEXT_INSN (x))
9436 if (may_trap_p (PATTERN (x)))
9438 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
9444 /* This is used by reload pass, that does emit some instructions after
9445 abnormal calls moving basic block end, but in fact it wants to emit
9446 them on the edge. Looks for abnormal call edges, find backward the
9447 proper call and fix the damage.
9449 Similar handle instructions throwing exceptions internally. */
9451 fixup_abnormal_edges ()
9454 bool inserted = false;
9456 for (i = 0; i < n_basic_blocks; i++)
9458 basic_block bb = BASIC_BLOCK (i);
9461 /* Look for cases we are interested in - an calls or instructions causing
9463 for (e = bb->succ; e; e = e->succ_next)
9465 if (e->flags & EDGE_ABNORMAL_CALL)
9467 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
9468 == (EDGE_ABNORMAL | EDGE_EH))
9471 if (e && GET_CODE (bb->end) != CALL_INSN && !can_throw_internal (bb->end))
9473 rtx insn = bb->end, stop = NEXT_INSN (bb->end);
9475 for (e = bb->succ; e; e = e->succ_next)
9476 if (e->flags & EDGE_FALLTHRU)
9478 /* Get past the new insns generated. Allow notes, as the insns may
9479 be already deleted. */
9480 while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE)
9481 && !can_throw_internal (insn)
9482 && insn != bb->head)
9483 insn = PREV_INSN (insn);
9484 if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn))
9488 insn = NEXT_INSN (insn);
9489 while (insn && insn != stop)
9491 next = NEXT_INSN (insn);
9494 insert_insn_on_edge (PATTERN (insn), e);
9502 commit_edge_insertions ();
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