1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "rtl-error.h"
32 #include "insn-config.h"
38 #include "addresses.h"
39 #include "basic-block.h"
50 /* This file contains the reload pass of the compiler, which is
51 run after register allocation has been done. It checks that
52 each insn is valid (operands required to be in registers really
53 are in registers of the proper class) and fixes up invalid ones
54 by copying values temporarily into registers for the insns
57 The results of register allocation are described by the vector
58 reg_renumber; the insns still contain pseudo regs, but reg_renumber
59 can be used to find which hard reg, if any, a pseudo reg is in.
61 The technique we always use is to free up a few hard regs that are
62 called ``reload regs'', and for each place where a pseudo reg
63 must be in a hard reg, copy it temporarily into one of the reload regs.
65 Reload regs are allocated locally for every instruction that needs
66 reloads. When there are pseudos which are allocated to a register that
67 has been chosen as a reload reg, such pseudos must be ``spilled''.
68 This means that they go to other hard regs, or to stack slots if no other
69 available hard regs can be found. Spilling can invalidate more
70 insns, requiring additional need for reloads, so we must keep checking
71 until the process stabilizes.
73 For machines with different classes of registers, we must keep track
74 of the register class needed for each reload, and make sure that
75 we allocate enough reload registers of each class.
77 The file reload.c contains the code that checks one insn for
78 validity and reports the reloads that it needs. This file
79 is in charge of scanning the entire rtl code, accumulating the
80 reload needs, spilling, assigning reload registers to use for
81 fixing up each insn, and generating the new insns to copy values
82 into the reload registers. */
84 /* During reload_as_needed, element N contains a REG rtx for the hard reg
85 into which reg N has been reloaded (perhaps for a previous insn). */
86 static rtx *reg_last_reload_reg;
88 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
89 for an output reload that stores into reg N. */
90 static regset_head reg_has_output_reload;
92 /* Indicates which hard regs are reload-registers for an output reload
93 in the current insn. */
94 static HARD_REG_SET reg_is_output_reload;
96 /* Element N is the constant value to which pseudo reg N is equivalent,
97 or zero if pseudo reg N is not equivalent to a constant.
98 find_reloads looks at this in order to replace pseudo reg N
99 with the constant it stands for. */
100 rtx *reg_equiv_constant;
102 /* Element N is an invariant value to which pseudo reg N is equivalent.
103 eliminate_regs_in_insn uses this to replace pseudos in particular
105 rtx *reg_equiv_invariant;
107 /* Element N is a memory location to which pseudo reg N is equivalent,
108 prior to any register elimination (such as frame pointer to stack
109 pointer). Depending on whether or not it is a valid address, this value
110 is transferred to either reg_equiv_address or reg_equiv_mem. */
111 rtx *reg_equiv_memory_loc;
113 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
114 collector can keep track of what is inside. */
115 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
117 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
118 This is used when the address is not valid as a memory address
119 (because its displacement is too big for the machine.) */
120 rtx *reg_equiv_address;
122 /* Element N is the memory slot to which pseudo reg N is equivalent,
123 or zero if pseudo reg N is not equivalent to a memory slot. */
126 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
127 alternate representations of the location of pseudo reg N. */
128 rtx *reg_equiv_alt_mem_list;
130 /* Widest width in which each pseudo reg is referred to (via subreg). */
131 static unsigned int *reg_max_ref_width;
133 /* Element N is the list of insns that initialized reg N from its equivalent
134 constant or memory slot. */
136 int reg_equiv_init_size;
138 /* Vector to remember old contents of reg_renumber before spilling. */
139 static short *reg_old_renumber;
141 /* During reload_as_needed, element N contains the last pseudo regno reloaded
142 into hard register N. If that pseudo reg occupied more than one register,
143 reg_reloaded_contents points to that pseudo for each spill register in
144 use; all of these must remain set for an inheritance to occur. */
145 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
147 /* During reload_as_needed, element N contains the insn for which
148 hard register N was last used. Its contents are significant only
149 when reg_reloaded_valid is set for this register. */
150 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
152 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
153 static HARD_REG_SET reg_reloaded_valid;
154 /* Indicate if the register was dead at the end of the reload.
155 This is only valid if reg_reloaded_contents is set and valid. */
156 static HARD_REG_SET reg_reloaded_dead;
158 /* Indicate whether the register's current value is one that is not
159 safe to retain across a call, even for registers that are normally
160 call-saved. This is only meaningful for members of reg_reloaded_valid. */
161 static HARD_REG_SET reg_reloaded_call_part_clobbered;
163 /* Number of spill-regs so far; number of valid elements of spill_regs. */
166 /* In parallel with spill_regs, contains REG rtx's for those regs.
167 Holds the last rtx used for any given reg, or 0 if it has never
168 been used for spilling yet. This rtx is reused, provided it has
170 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
172 /* In parallel with spill_regs, contains nonzero for a spill reg
173 that was stored after the last time it was used.
174 The precise value is the insn generated to do the store. */
175 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
177 /* This is the register that was stored with spill_reg_store. This is a
178 copy of reload_out / reload_out_reg when the value was stored; if
179 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
180 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
182 /* This table is the inverse mapping of spill_regs:
183 indexed by hard reg number,
184 it contains the position of that reg in spill_regs,
185 or -1 for something that is not in spill_regs.
187 ?!? This is no longer accurate. */
188 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
190 /* This reg set indicates registers that can't be used as spill registers for
191 the currently processed insn. These are the hard registers which are live
192 during the insn, but not allocated to pseudos, as well as fixed
194 static HARD_REG_SET bad_spill_regs;
196 /* These are the hard registers that can't be used as spill register for any
197 insn. This includes registers used for user variables and registers that
198 we can't eliminate. A register that appears in this set also can't be used
199 to retry register allocation. */
200 static HARD_REG_SET bad_spill_regs_global;
202 /* Describes order of use of registers for reloading
203 of spilled pseudo-registers. `n_spills' is the number of
204 elements that are actually valid; new ones are added at the end.
206 Both spill_regs and spill_reg_order are used on two occasions:
207 once during find_reload_regs, where they keep track of the spill registers
208 for a single insn, but also during reload_as_needed where they show all
209 the registers ever used by reload. For the latter case, the information
210 is calculated during finish_spills. */
211 static short spill_regs[FIRST_PSEUDO_REGISTER];
213 /* This vector of reg sets indicates, for each pseudo, which hard registers
214 may not be used for retrying global allocation because the register was
215 formerly spilled from one of them. If we allowed reallocating a pseudo to
216 a register that it was already allocated to, reload might not
218 static HARD_REG_SET *pseudo_previous_regs;
220 /* This vector of reg sets indicates, for each pseudo, which hard
221 registers may not be used for retrying global allocation because they
222 are used as spill registers during one of the insns in which the
224 static HARD_REG_SET *pseudo_forbidden_regs;
226 /* All hard regs that have been used as spill registers for any insn are
227 marked in this set. */
228 static HARD_REG_SET used_spill_regs;
230 /* Index of last register assigned as a spill register. We allocate in
231 a round-robin fashion. */
232 static int last_spill_reg;
234 /* Nonzero if indirect addressing is supported on the machine; this means
235 that spilling (REG n) does not require reloading it into a register in
236 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
237 value indicates the level of indirect addressing supported, e.g., two
238 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
240 static char spill_indirect_levels;
242 /* Nonzero if indirect addressing is supported when the innermost MEM is
243 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
244 which these are valid is the same as spill_indirect_levels, above. */
245 char indirect_symref_ok;
247 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
248 char double_reg_address_ok;
250 /* Record the stack slot for each spilled hard register. */
251 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
253 /* Width allocated so far for that stack slot. */
254 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
256 /* Record which pseudos needed to be spilled. */
257 static regset_head spilled_pseudos;
259 /* Record which pseudos changed their allocation in finish_spills. */
260 static regset_head changed_allocation_pseudos;
262 /* Used for communication between order_regs_for_reload and count_pseudo.
263 Used to avoid counting one pseudo twice. */
264 static regset_head pseudos_counted;
266 /* First uid used by insns created by reload in this function.
267 Used in find_equiv_reg. */
268 int reload_first_uid;
270 /* Flag set by local-alloc or global-alloc if anything is live in
271 a call-clobbered reg across calls. */
272 int caller_save_needed;
274 /* Set to 1 while reload_as_needed is operating.
275 Required by some machines to handle any generated moves differently. */
276 int reload_in_progress = 0;
278 /* These arrays record the insn_code of insns that may be needed to
279 perform input and output reloads of special objects. They provide a
280 place to pass a scratch register. */
281 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
282 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
284 /* This obstack is used for allocation of rtl during register elimination.
285 The allocated storage can be freed once find_reloads has processed the
287 static struct obstack reload_obstack;
289 /* Points to the beginning of the reload_obstack. All insn_chain structures
290 are allocated first. */
291 static char *reload_startobj;
293 /* The point after all insn_chain structures. Used to quickly deallocate
294 memory allocated in copy_reloads during calculate_needs_all_insns. */
295 static char *reload_firstobj;
297 /* This points before all local rtl generated by register elimination.
298 Used to quickly free all memory after processing one insn. */
299 static char *reload_insn_firstobj;
301 /* List of insn_chain instructions, one for every insn that reload needs to
303 struct insn_chain *reload_insn_chain;
305 /* List of all insns needing reloads. */
306 static struct insn_chain *insns_need_reload;
308 /* This structure is used to record information about register eliminations.
309 Each array entry describes one possible way of eliminating a register
310 in favor of another. If there is more than one way of eliminating a
311 particular register, the most preferred should be specified first. */
315 int from; /* Register number to be eliminated. */
316 int to; /* Register number used as replacement. */
317 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
318 int can_eliminate; /* Nonzero if this elimination can be done. */
319 int can_eliminate_previous; /* Value returned by TARGET_CAN_ELIMINATE
320 target hook in previous scan over insns
322 HOST_WIDE_INT offset; /* Current offset between the two regs. */
323 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
324 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
325 rtx from_rtx; /* REG rtx for the register to be eliminated.
326 We cannot simply compare the number since
327 we might then spuriously replace a hard
328 register corresponding to a pseudo
329 assigned to the reg to be eliminated. */
330 rtx to_rtx; /* REG rtx for the replacement. */
333 static struct elim_table *reg_eliminate = 0;
335 /* This is an intermediate structure to initialize the table. It has
336 exactly the members provided by ELIMINABLE_REGS. */
337 static const struct elim_table_1
341 } reg_eliminate_1[] =
343 /* If a set of eliminable registers was specified, define the table from it.
344 Otherwise, default to the normal case of the frame pointer being
345 replaced by the stack pointer. */
347 #ifdef ELIMINABLE_REGS
350 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
353 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
355 /* Record the number of pending eliminations that have an offset not equal
356 to their initial offset. If nonzero, we use a new copy of each
357 replacement result in any insns encountered. */
358 int num_not_at_initial_offset;
360 /* Count the number of registers that we may be able to eliminate. */
361 static int num_eliminable;
362 /* And the number of registers that are equivalent to a constant that
363 can be eliminated to frame_pointer / arg_pointer + constant. */
364 static int num_eliminable_invariants;
366 /* For each label, we record the offset of each elimination. If we reach
367 a label by more than one path and an offset differs, we cannot do the
368 elimination. This information is indexed by the difference of the
369 number of the label and the first label number. We can't offset the
370 pointer itself as this can cause problems on machines with segmented
371 memory. The first table is an array of flags that records whether we
372 have yet encountered a label and the second table is an array of arrays,
373 one entry in the latter array for each elimination. */
375 static int first_label_num;
376 static char *offsets_known_at;
377 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
379 /* Stack of addresses where an rtx has been changed. We can undo the
380 changes by popping items off the stack and restoring the original
381 value at each location.
383 We use this simplistic undo capability rather than copy_rtx as copy_rtx
384 will not make a deep copy of a normally sharable rtx, such as
385 (const (plus (symbol_ref) (const_int))). If such an expression appears
386 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
387 rtx expression would be changed. See PR 42431. */
391 DEF_VEC_ALLOC_P(rtx_p,heap);
392 static VEC(rtx_p,heap) *substitute_stack;
394 /* Number of labels in the current function. */
396 static int num_labels;
398 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
399 static void maybe_fix_stack_asms (void);
400 static void copy_reloads (struct insn_chain *);
401 static void calculate_needs_all_insns (int);
402 static int find_reg (struct insn_chain *, int);
403 static void find_reload_regs (struct insn_chain *);
404 static void select_reload_regs (void);
405 static void delete_caller_save_insns (void);
407 static void spill_failure (rtx, enum reg_class);
408 static void count_spilled_pseudo (int, int, int);
409 static void delete_dead_insn (rtx);
410 static void alter_reg (int, int, bool);
411 static void set_label_offsets (rtx, rtx, int);
412 static void check_eliminable_occurrences (rtx);
413 static void elimination_effects (rtx, enum machine_mode);
414 static rtx eliminate_regs_1 (rtx, enum machine_mode, rtx, bool, bool);
415 static int eliminate_regs_in_insn (rtx, int);
416 static void update_eliminable_offsets (void);
417 static void mark_not_eliminable (rtx, const_rtx, void *);
418 static void set_initial_elim_offsets (void);
419 static bool verify_initial_elim_offsets (void);
420 static void set_initial_label_offsets (void);
421 static void set_offsets_for_label (rtx);
422 static void init_eliminable_invariants (rtx, bool);
423 static void init_elim_table (void);
424 static void free_reg_equiv (void);
425 static void update_eliminables (HARD_REG_SET *);
426 static void elimination_costs_in_insn (rtx);
427 static void spill_hard_reg (unsigned int, int);
428 static int finish_spills (int);
429 static void scan_paradoxical_subregs (rtx);
430 static void count_pseudo (int);
431 static void order_regs_for_reload (struct insn_chain *);
432 static void reload_as_needed (int);
433 static void forget_old_reloads_1 (rtx, const_rtx, void *);
434 static void forget_marked_reloads (regset);
435 static int reload_reg_class_lower (const void *, const void *);
436 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
438 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
440 static int reload_reg_free_p (unsigned int, int, enum reload_type);
441 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
443 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
445 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
446 static int allocate_reload_reg (struct insn_chain *, int, int);
447 static int conflicts_with_override (rtx);
448 static void failed_reload (rtx, int);
449 static int set_reload_reg (int, int);
450 static void choose_reload_regs_init (struct insn_chain *, rtx *);
451 static void choose_reload_regs (struct insn_chain *);
452 static void merge_assigned_reloads (rtx);
453 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
455 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
457 static void do_input_reload (struct insn_chain *, struct reload *, int);
458 static void do_output_reload (struct insn_chain *, struct reload *, int);
459 static void emit_reload_insns (struct insn_chain *);
460 static void delete_output_reload (rtx, int, int, rtx);
461 static void delete_address_reloads (rtx, rtx);
462 static void delete_address_reloads_1 (rtx, rtx, rtx);
463 static rtx inc_for_reload (rtx, rtx, rtx, int);
465 static void add_auto_inc_notes (rtx, rtx);
467 static void substitute (rtx *, const_rtx, rtx);
468 static bool gen_reload_chain_without_interm_reg_p (int, int);
469 static int reloads_conflict (int, int);
470 static rtx gen_reload (rtx, rtx, int, enum reload_type);
471 static rtx emit_insn_if_valid_for_reload (rtx);
473 /* Initialize the reload pass. This is called at the beginning of compilation
474 and may be called again if the target is reinitialized. */
481 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
482 Set spill_indirect_levels to the number of levels such addressing is
483 permitted, zero if it is not permitted at all. */
486 = gen_rtx_MEM (Pmode,
489 LAST_VIRTUAL_REGISTER + 1),
491 spill_indirect_levels = 0;
493 while (memory_address_p (QImode, tem))
495 spill_indirect_levels++;
496 tem = gen_rtx_MEM (Pmode, tem);
499 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
501 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
502 indirect_symref_ok = memory_address_p (QImode, tem);
504 /* See if reg+reg is a valid (and offsettable) address. */
506 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
508 tem = gen_rtx_PLUS (Pmode,
509 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
510 gen_rtx_REG (Pmode, i));
512 /* This way, we make sure that reg+reg is an offsettable address. */
513 tem = plus_constant (tem, 4);
515 if (memory_address_p (QImode, tem))
517 double_reg_address_ok = 1;
522 /* Initialize obstack for our rtl allocation. */
523 gcc_obstack_init (&reload_obstack);
524 reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
526 INIT_REG_SET (&spilled_pseudos);
527 INIT_REG_SET (&changed_allocation_pseudos);
528 INIT_REG_SET (&pseudos_counted);
531 /* List of insn chains that are currently unused. */
532 static struct insn_chain *unused_insn_chains = 0;
534 /* Allocate an empty insn_chain structure. */
536 new_insn_chain (void)
538 struct insn_chain *c;
540 if (unused_insn_chains == 0)
542 c = XOBNEW (&reload_obstack, struct insn_chain);
543 INIT_REG_SET (&c->live_throughout);
544 INIT_REG_SET (&c->dead_or_set);
548 c = unused_insn_chains;
549 unused_insn_chains = c->next;
551 c->is_caller_save_insn = 0;
552 c->need_operand_change = 0;
558 /* Small utility function to set all regs in hard reg set TO which are
559 allocated to pseudos in regset FROM. */
562 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
565 reg_set_iterator rsi;
567 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
569 int r = reg_renumber[regno];
573 /* reload_combine uses the information from DF_LIVE_IN,
574 which might still contain registers that have not
575 actually been allocated since they have an
577 gcc_assert (ira_conflicts_p || reload_completed);
580 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
584 /* Replace all pseudos found in LOC with their corresponding
588 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
601 unsigned int regno = REGNO (x);
603 if (regno < FIRST_PSEUDO_REGISTER)
606 x = eliminate_regs (x, mem_mode, usage);
610 replace_pseudos_in (loc, mem_mode, usage);
614 if (reg_equiv_constant[regno])
615 *loc = reg_equiv_constant[regno];
616 else if (reg_equiv_mem[regno])
617 *loc = reg_equiv_mem[regno];
618 else if (reg_equiv_address[regno])
619 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
622 gcc_assert (!REG_P (regno_reg_rtx[regno])
623 || REGNO (regno_reg_rtx[regno]) != regno);
624 *loc = regno_reg_rtx[regno];
629 else if (code == MEM)
631 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
635 /* Process each of our operands recursively. */
636 fmt = GET_RTX_FORMAT (code);
637 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
639 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
640 else if (*fmt == 'E')
641 for (j = 0; j < XVECLEN (x, i); j++)
642 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
645 /* Determine if the current function has an exception receiver block
646 that reaches the exit block via non-exceptional edges */
649 has_nonexceptional_receiver (void)
653 basic_block *tos, *worklist, bb;
655 /* If we're not optimizing, then just err on the safe side. */
659 /* First determine which blocks can reach exit via normal paths. */
660 tos = worklist = XNEWVEC (basic_block, n_basic_blocks + 1);
663 bb->flags &= ~BB_REACHABLE;
665 /* Place the exit block on our worklist. */
666 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
667 *tos++ = EXIT_BLOCK_PTR;
669 /* Iterate: find everything reachable from what we've already seen. */
670 while (tos != worklist)
674 FOR_EACH_EDGE (e, ei, bb->preds)
675 if (!(e->flags & EDGE_ABNORMAL))
677 basic_block src = e->src;
679 if (!(src->flags & BB_REACHABLE))
681 src->flags |= BB_REACHABLE;
688 /* Now see if there's a reachable block with an exceptional incoming
691 if (bb->flags & BB_REACHABLE)
692 FOR_EACH_EDGE (e, ei, bb->preds)
693 if (e->flags & EDGE_ABNORMAL)
696 /* No exceptional block reached exit unexceptionally. */
701 /* Global variables used by reload and its subroutines. */
703 /* The current basic block while in calculate_elim_costs_all_insns. */
704 static basic_block elim_bb;
706 /* Set during calculate_needs if an insn needs register elimination. */
707 static int something_needs_elimination;
708 /* Set during calculate_needs if an insn needs an operand changed. */
709 static int something_needs_operands_changed;
710 /* Set by alter_regs if we spilled a register to the stack. */
711 static bool something_was_spilled;
713 /* Nonzero means we couldn't get enough spill regs. */
716 /* Temporary array of pseudo-register number. */
717 static int *temp_pseudo_reg_arr;
719 /* Main entry point for the reload pass.
721 FIRST is the first insn of the function being compiled.
723 GLOBAL nonzero means we were called from global_alloc
724 and should attempt to reallocate any pseudoregs that we
725 displace from hard regs we will use for reloads.
726 If GLOBAL is zero, we do not have enough information to do that,
727 so any pseudo reg that is spilled must go to the stack.
729 Return value is nonzero if reload failed
730 and we must not do any more for this function. */
733 reload (rtx first, int global)
737 struct elim_table *ep;
740 /* Make sure even insns with volatile mem refs are recognizable. */
745 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
747 /* Make sure that the last insn in the chain
748 is not something that needs reloading. */
749 emit_note (NOTE_INSN_DELETED);
751 /* Enable find_equiv_reg to distinguish insns made by reload. */
752 reload_first_uid = get_max_uid ();
754 #ifdef SECONDARY_MEMORY_NEEDED
755 /* Initialize the secondary memory table. */
756 clear_secondary_mem ();
759 /* We don't have a stack slot for any spill reg yet. */
760 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
761 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
763 /* Initialize the save area information for caller-save, in case some
767 /* Compute which hard registers are now in use
768 as homes for pseudo registers.
769 This is done here rather than (eg) in global_alloc
770 because this point is reached even if not optimizing. */
771 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
774 /* A function that has a nonlocal label that can reach the exit
775 block via non-exceptional paths must save all call-saved
777 if (cfun->has_nonlocal_label
778 && has_nonexceptional_receiver ())
779 crtl->saves_all_registers = 1;
781 if (crtl->saves_all_registers)
782 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
783 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
784 df_set_regs_ever_live (i, true);
786 reg_old_renumber = XCNEWVEC (short, max_regno);
787 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
788 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
789 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
791 CLEAR_HARD_REG_SET (bad_spill_regs_global);
793 init_eliminable_invariants (first, true);
796 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
797 stack slots to the pseudos that lack hard regs or equivalents.
798 Do not touch virtual registers. */
800 temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
801 for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
802 temp_pseudo_reg_arr[n++] = i;
805 /* Ask IRA to order pseudo-registers for better stack slot
807 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width);
809 for (i = 0; i < n; i++)
810 alter_reg (temp_pseudo_reg_arr[i], -1, false);
812 /* If we have some registers we think can be eliminated, scan all insns to
813 see if there is an insn that sets one of these registers to something
814 other than itself plus a constant. If so, the register cannot be
815 eliminated. Doing this scan here eliminates an extra pass through the
816 main reload loop in the most common case where register elimination
818 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
820 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
822 maybe_fix_stack_asms ();
824 insns_need_reload = 0;
825 something_needs_elimination = 0;
827 /* Initialize to -1, which means take the first spill register. */
830 /* Spill any hard regs that we know we can't eliminate. */
831 CLEAR_HARD_REG_SET (used_spill_regs);
832 /* There can be multiple ways to eliminate a register;
833 they should be listed adjacently.
834 Elimination for any register fails only if all possible ways fail. */
835 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
838 int can_eliminate = 0;
841 can_eliminate |= ep->can_eliminate;
844 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
846 spill_hard_reg (from, 1);
849 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
850 if (frame_pointer_needed)
851 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
853 finish_spills (global);
855 /* From now on, we may need to generate moves differently. We may also
856 allow modifications of insns which cause them to not be recognized.
857 Any such modifications will be cleaned up during reload itself. */
858 reload_in_progress = 1;
860 /* This loop scans the entire function each go-round
861 and repeats until one repetition spills no additional hard regs. */
864 int something_changed;
866 HOST_WIDE_INT starting_frame_size;
868 starting_frame_size = get_frame_size ();
869 something_was_spilled = false;
871 set_initial_elim_offsets ();
872 set_initial_label_offsets ();
874 /* For each pseudo register that has an equivalent location defined,
875 try to eliminate any eliminable registers (such as the frame pointer)
876 assuming initial offsets for the replacement register, which
879 If the resulting location is directly addressable, substitute
880 the MEM we just got directly for the old REG.
882 If it is not addressable but is a constant or the sum of a hard reg
883 and constant, it is probably not addressable because the constant is
884 out of range, in that case record the address; we will generate
885 hairy code to compute the address in a register each time it is
886 needed. Similarly if it is a hard register, but one that is not
887 valid as an address register.
889 If the location is not addressable, but does not have one of the
890 above forms, assign a stack slot. We have to do this to avoid the
891 potential of producing lots of reloads if, e.g., a location involves
892 a pseudo that didn't get a hard register and has an equivalent memory
893 location that also involves a pseudo that didn't get a hard register.
895 Perhaps at some point we will improve reload_when_needed handling
896 so this problem goes away. But that's very hairy. */
898 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
899 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
901 rtx x = eliminate_regs (reg_equiv_memory_loc[i], VOIDmode,
904 if (strict_memory_address_addr_space_p
905 (GET_MODE (regno_reg_rtx[i]), XEXP (x, 0),
907 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
908 else if (CONSTANT_P (XEXP (x, 0))
909 || (REG_P (XEXP (x, 0))
910 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
911 || (GET_CODE (XEXP (x, 0)) == PLUS
912 && REG_P (XEXP (XEXP (x, 0), 0))
913 && (REGNO (XEXP (XEXP (x, 0), 0))
914 < FIRST_PSEUDO_REGISTER)
915 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
916 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
919 /* Make a new stack slot. Then indicate that something
920 changed so we go back and recompute offsets for
921 eliminable registers because the allocation of memory
922 below might change some offset. reg_equiv_{mem,address}
923 will be set up for this pseudo on the next pass around
925 reg_equiv_memory_loc[i] = 0;
926 reg_equiv_init[i] = 0;
927 alter_reg (i, -1, true);
931 if (caller_save_needed)
934 /* If we allocated another stack slot, redo elimination bookkeeping. */
935 if (something_was_spilled || starting_frame_size != get_frame_size ())
937 if (starting_frame_size && crtl->stack_alignment_needed)
939 /* If we have a stack frame, we must align it now. The
940 stack size may be a part of the offset computation for
941 register elimination. So if this changes the stack size,
942 then repeat the elimination bookkeeping. We don't
943 realign when there is no stack, as that will cause a
944 stack frame when none is needed should
945 STARTING_FRAME_OFFSET not be already aligned to
947 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
948 if (starting_frame_size != get_frame_size ())
952 if (caller_save_needed)
954 save_call_clobbered_regs ();
955 /* That might have allocated new insn_chain structures. */
956 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
959 calculate_needs_all_insns (global);
961 if (! ira_conflicts_p)
962 /* Don't do it for IRA. We need this info because we don't
963 change live_throughout and dead_or_set for chains when IRA
965 CLEAR_REG_SET (&spilled_pseudos);
969 something_changed = 0;
971 /* If we allocated any new memory locations, make another pass
972 since it might have changed elimination offsets. */
973 if (something_was_spilled || starting_frame_size != get_frame_size ())
974 something_changed = 1;
976 /* Even if the frame size remained the same, we might still have
977 changed elimination offsets, e.g. if find_reloads called
978 force_const_mem requiring the back end to allocate a constant
979 pool base register that needs to be saved on the stack. */
980 else if (!verify_initial_elim_offsets ())
981 something_changed = 1;
984 HARD_REG_SET to_spill;
985 CLEAR_HARD_REG_SET (to_spill);
986 update_eliminables (&to_spill);
987 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
989 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
990 if (TEST_HARD_REG_BIT (to_spill, i))
992 spill_hard_reg (i, 1);
995 /* Regardless of the state of spills, if we previously had
996 a register that we thought we could eliminate, but now can
997 not eliminate, we must run another pass.
999 Consider pseudos which have an entry in reg_equiv_* which
1000 reference an eliminable register. We must make another pass
1001 to update reg_equiv_* so that we do not substitute in the
1002 old value from when we thought the elimination could be
1004 something_changed = 1;
1008 select_reload_regs ();
1012 if (insns_need_reload != 0 || did_spill)
1013 something_changed |= finish_spills (global);
1015 if (! something_changed)
1018 if (caller_save_needed)
1019 delete_caller_save_insns ();
1021 obstack_free (&reload_obstack, reload_firstobj);
1024 /* If global-alloc was run, notify it of any register eliminations we have
1027 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1028 if (ep->can_eliminate)
1029 mark_elimination (ep->from, ep->to);
1031 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1032 If that insn didn't set the register (i.e., it copied the register to
1033 memory), just delete that insn instead of the equivalencing insn plus
1034 anything now dead. If we call delete_dead_insn on that insn, we may
1035 delete the insn that actually sets the register if the register dies
1036 there and that is incorrect. */
1038 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1040 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1043 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1045 rtx equiv_insn = XEXP (list, 0);
1047 /* If we already deleted the insn or if it may trap, we can't
1048 delete it. The latter case shouldn't happen, but can
1049 if an insn has a variable address, gets a REG_EH_REGION
1050 note added to it, and then gets converted into a load
1051 from a constant address. */
1052 if (NOTE_P (equiv_insn)
1053 || can_throw_internal (equiv_insn))
1055 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1056 delete_dead_insn (equiv_insn);
1058 SET_INSN_DELETED (equiv_insn);
1063 /* Use the reload registers where necessary
1064 by generating move instructions to move the must-be-register
1065 values into or out of the reload registers. */
1067 if (insns_need_reload != 0 || something_needs_elimination
1068 || something_needs_operands_changed)
1070 HOST_WIDE_INT old_frame_size = get_frame_size ();
1072 reload_as_needed (global);
1074 gcc_assert (old_frame_size == get_frame_size ());
1076 gcc_assert (verify_initial_elim_offsets ());
1079 /* If we were able to eliminate the frame pointer, show that it is no
1080 longer live at the start of any basic block. If it ls live by
1081 virtue of being in a pseudo, that pseudo will be marked live
1082 and hence the frame pointer will be known to be live via that
1085 if (! frame_pointer_needed)
1087 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1089 /* Come here (with failure set nonzero) if we can't get enough spill
1093 CLEAR_REG_SET (&changed_allocation_pseudos);
1094 CLEAR_REG_SET (&spilled_pseudos);
1095 reload_in_progress = 0;
1097 /* Now eliminate all pseudo regs by modifying them into
1098 their equivalent memory references.
1099 The REG-rtx's for the pseudos are modified in place,
1100 so all insns that used to refer to them now refer to memory.
1102 For a reg that has a reg_equiv_address, all those insns
1103 were changed by reloading so that no insns refer to it any longer;
1104 but the DECL_RTL of a variable decl may refer to it,
1105 and if so this causes the debugging info to mention the variable. */
1107 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1111 if (reg_equiv_mem[i])
1112 addr = XEXP (reg_equiv_mem[i], 0);
1114 if (reg_equiv_address[i])
1115 addr = reg_equiv_address[i];
1119 if (reg_renumber[i] < 0)
1121 rtx reg = regno_reg_rtx[i];
1123 REG_USERVAR_P (reg) = 0;
1124 PUT_CODE (reg, MEM);
1125 XEXP (reg, 0) = addr;
1126 if (reg_equiv_memory_loc[i])
1127 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1130 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1131 MEM_ATTRS (reg) = 0;
1133 MEM_NOTRAP_P (reg) = 1;
1135 else if (reg_equiv_mem[i])
1136 XEXP (reg_equiv_mem[i], 0) = addr;
1139 /* We don't want complex addressing modes in debug insns
1140 if simpler ones will do, so delegitimize equivalences
1142 if (MAY_HAVE_DEBUG_INSNS && reg_renumber[i] < 0)
1144 rtx reg = regno_reg_rtx[i];
1148 if (reg_equiv_constant[i])
1149 equiv = reg_equiv_constant[i];
1150 else if (reg_equiv_invariant[i])
1151 equiv = reg_equiv_invariant[i];
1152 else if (reg && MEM_P (reg))
1153 equiv = targetm.delegitimize_address (reg);
1154 else if (reg && REG_P (reg) && (int)REGNO (reg) != i)
1160 for (use = DF_REG_USE_CHAIN (i); use; use = next)
1162 insn = DF_REF_INSN (use);
1164 /* Make sure the next ref is for a different instruction,
1165 so that we're not affected by the rescan. */
1166 next = DF_REF_NEXT_REG (use);
1167 while (next && DF_REF_INSN (next) == insn)
1168 next = DF_REF_NEXT_REG (next);
1170 if (DEBUG_INSN_P (insn))
1174 INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
1175 df_insn_rescan_debug_internal (insn);
1178 INSN_VAR_LOCATION_LOC (insn)
1179 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn),
1186 /* We must set reload_completed now since the cleanup_subreg_operands call
1187 below will re-recognize each insn and reload may have generated insns
1188 which are only valid during and after reload. */
1189 reload_completed = 1;
1191 /* Make a pass over all the insns and delete all USEs which we inserted
1192 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1193 notes. Delete all CLOBBER insns, except those that refer to the return
1194 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1195 from misarranging variable-array code, and simplify (subreg (reg))
1196 operands. Strip and regenerate REG_INC notes that may have been moved
1199 for (insn = first; insn; insn = NEXT_INSN (insn))
1205 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1206 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1208 if ((GET_CODE (PATTERN (insn)) == USE
1209 /* We mark with QImode USEs introduced by reload itself. */
1210 && (GET_MODE (insn) == QImode
1211 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1212 || (GET_CODE (PATTERN (insn)) == CLOBBER
1213 && (!MEM_P (XEXP (PATTERN (insn), 0))
1214 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1215 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1216 && XEXP (XEXP (PATTERN (insn), 0), 0)
1217 != stack_pointer_rtx))
1218 && (!REG_P (XEXP (PATTERN (insn), 0))
1219 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1225 /* Some CLOBBERs may survive until here and still reference unassigned
1226 pseudos with const equivalent, which may in turn cause ICE in later
1227 passes if the reference remains in place. */
1228 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1229 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1230 VOIDmode, PATTERN (insn));
1232 /* Discard obvious no-ops, even without -O. This optimization
1233 is fast and doesn't interfere with debugging. */
1234 if (NONJUMP_INSN_P (insn)
1235 && GET_CODE (PATTERN (insn)) == SET
1236 && REG_P (SET_SRC (PATTERN (insn)))
1237 && REG_P (SET_DEST (PATTERN (insn)))
1238 && (REGNO (SET_SRC (PATTERN (insn)))
1239 == REGNO (SET_DEST (PATTERN (insn)))))
1245 pnote = ®_NOTES (insn);
1248 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1249 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1250 || REG_NOTE_KIND (*pnote) == REG_INC)
1251 *pnote = XEXP (*pnote, 1);
1253 pnote = &XEXP (*pnote, 1);
1257 add_auto_inc_notes (insn, PATTERN (insn));
1260 /* Simplify (subreg (reg)) if it appears as an operand. */
1261 cleanup_subreg_operands (insn);
1263 /* Clean up invalid ASMs so that they don't confuse later passes.
1265 if (asm_noperands (PATTERN (insn)) >= 0)
1267 extract_insn (insn);
1268 if (!constrain_operands (1))
1270 error_for_asm (insn,
1271 "%<asm%> operand has impossible constraints");
1278 /* If we are doing generic stack checking, give a warning if this
1279 function's frame size is larger than we expect. */
1280 if (flag_stack_check == GENERIC_STACK_CHECK)
1282 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1283 static int verbose_warned = 0;
1285 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1286 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1287 size += UNITS_PER_WORD;
1289 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1291 warning (0, "frame size too large for reliable stack checking");
1292 if (! verbose_warned)
1294 warning (0, "try reducing the number of local variables");
1300 free (temp_pseudo_reg_arr);
1302 /* Indicate that we no longer have known memory locations or constants. */
1305 free (reg_max_ref_width);
1306 free (reg_old_renumber);
1307 free (pseudo_previous_regs);
1308 free (pseudo_forbidden_regs);
1310 CLEAR_HARD_REG_SET (used_spill_regs);
1311 for (i = 0; i < n_spills; i++)
1312 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1314 /* Free all the insn_chain structures at once. */
1315 obstack_free (&reload_obstack, reload_startobj);
1316 unused_insn_chains = 0;
1317 fixup_abnormal_edges ();
1319 /* Replacing pseudos with their memory equivalents might have
1320 created shared rtx. Subsequent passes would get confused
1321 by this, so unshare everything here. */
1322 unshare_all_rtl_again (first);
1324 #ifdef STACK_BOUNDARY
1325 /* init_emit has set the alignment of the hard frame pointer
1326 to STACK_BOUNDARY. It is very likely no longer valid if
1327 the hard frame pointer was used for register allocation. */
1328 if (!frame_pointer_needed)
1329 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1332 VEC_free (rtx_p, heap, substitute_stack);
1337 /* Yet another special case. Unfortunately, reg-stack forces people to
1338 write incorrect clobbers in asm statements. These clobbers must not
1339 cause the register to appear in bad_spill_regs, otherwise we'll call
1340 fatal_insn later. We clear the corresponding regnos in the live
1341 register sets to avoid this.
1342 The whole thing is rather sick, I'm afraid. */
1345 maybe_fix_stack_asms (void)
1348 const char *constraints[MAX_RECOG_OPERANDS];
1349 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1350 struct insn_chain *chain;
1352 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1355 HARD_REG_SET clobbered, allowed;
1358 if (! INSN_P (chain->insn)
1359 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1361 pat = PATTERN (chain->insn);
1362 if (GET_CODE (pat) != PARALLEL)
1365 CLEAR_HARD_REG_SET (clobbered);
1366 CLEAR_HARD_REG_SET (allowed);
1368 /* First, make a mask of all stack regs that are clobbered. */
1369 for (i = 0; i < XVECLEN (pat, 0); i++)
1371 rtx t = XVECEXP (pat, 0, i);
1372 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1373 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1376 /* Get the operand values and constraints out of the insn. */
1377 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1378 constraints, operand_mode, NULL);
1380 /* For every operand, see what registers are allowed. */
1381 for (i = 0; i < noperands; i++)
1383 const char *p = constraints[i];
1384 /* For every alternative, we compute the class of registers allowed
1385 for reloading in CLS, and merge its contents into the reg set
1387 int cls = (int) NO_REGS;
1393 if (c == '\0' || c == ',' || c == '#')
1395 /* End of one alternative - mark the regs in the current
1396 class, and reset the class. */
1397 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1403 } while (c != '\0' && c != ',');
1411 case '=': case '+': case '*': case '%': case '?': case '!':
1412 case '0': case '1': case '2': case '3': case '4': case '<':
1413 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1414 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1415 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1416 case TARGET_MEM_CONSTRAINT:
1420 cls = (int) reg_class_subunion[cls]
1421 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1426 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1430 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1431 cls = (int) reg_class_subunion[cls]
1432 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1434 cls = (int) reg_class_subunion[cls]
1435 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1437 p += CONSTRAINT_LEN (c, p);
1440 /* Those of the registers which are clobbered, but allowed by the
1441 constraints, must be usable as reload registers. So clear them
1442 out of the life information. */
1443 AND_HARD_REG_SET (allowed, clobbered);
1444 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1445 if (TEST_HARD_REG_BIT (allowed, i))
1447 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1448 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1455 /* Copy the global variables n_reloads and rld into the corresponding elts
1458 copy_reloads (struct insn_chain *chain)
1460 chain->n_reloads = n_reloads;
1461 chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1462 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1463 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1466 /* Walk the chain of insns, and determine for each whether it needs reloads
1467 and/or eliminations. Build the corresponding insns_need_reload list, and
1468 set something_needs_elimination as appropriate. */
1470 calculate_needs_all_insns (int global)
1472 struct insn_chain **pprev_reload = &insns_need_reload;
1473 struct insn_chain *chain, *next = 0;
1475 something_needs_elimination = 0;
1477 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1478 for (chain = reload_insn_chain; chain != 0; chain = next)
1480 rtx insn = chain->insn;
1484 /* Clear out the shortcuts. */
1485 chain->n_reloads = 0;
1486 chain->need_elim = 0;
1487 chain->need_reload = 0;
1488 chain->need_operand_change = 0;
1490 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1491 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1492 what effects this has on the known offsets at labels. */
1494 if (LABEL_P (insn) || JUMP_P (insn)
1495 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1496 set_label_offsets (insn, insn, 0);
1500 rtx old_body = PATTERN (insn);
1501 int old_code = INSN_CODE (insn);
1502 rtx old_notes = REG_NOTES (insn);
1503 int did_elimination = 0;
1504 int operands_changed = 0;
1505 rtx set = single_set (insn);
1507 /* Skip insns that only set an equivalence. */
1508 if (set && REG_P (SET_DEST (set))
1509 && reg_renumber[REGNO (SET_DEST (set))] < 0
1510 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1511 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1512 && reg_equiv_init[REGNO (SET_DEST (set))])
1515 /* If needed, eliminate any eliminable registers. */
1516 if (num_eliminable || num_eliminable_invariants)
1517 did_elimination = eliminate_regs_in_insn (insn, 0);
1519 /* Analyze the instruction. */
1520 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1521 global, spill_reg_order);
1523 /* If a no-op set needs more than one reload, this is likely
1524 to be something that needs input address reloads. We
1525 can't get rid of this cleanly later, and it is of no use
1526 anyway, so discard it now.
1527 We only do this when expensive_optimizations is enabled,
1528 since this complements reload inheritance / output
1529 reload deletion, and it can make debugging harder. */
1530 if (flag_expensive_optimizations && n_reloads > 1)
1532 rtx set = single_set (insn);
1535 ((SET_SRC (set) == SET_DEST (set)
1536 && REG_P (SET_SRC (set))
1537 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1538 || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1539 && reg_renumber[REGNO (SET_SRC (set))] < 0
1540 && reg_renumber[REGNO (SET_DEST (set))] < 0
1541 && reg_equiv_memory_loc[REGNO (SET_SRC (set))] != NULL
1542 && reg_equiv_memory_loc[REGNO (SET_DEST (set))] != NULL
1543 && rtx_equal_p (reg_equiv_memory_loc
1544 [REGNO (SET_SRC (set))],
1545 reg_equiv_memory_loc
1546 [REGNO (SET_DEST (set))]))))
1548 if (ira_conflicts_p)
1549 /* Inform IRA about the insn deletion. */
1550 ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1551 REGNO (SET_SRC (set)));
1553 /* Delete it from the reload chain. */
1555 chain->prev->next = next;
1557 reload_insn_chain = next;
1559 next->prev = chain->prev;
1560 chain->next = unused_insn_chains;
1561 unused_insn_chains = chain;
1566 update_eliminable_offsets ();
1568 /* Remember for later shortcuts which insns had any reloads or
1569 register eliminations. */
1570 chain->need_elim = did_elimination;
1571 chain->need_reload = n_reloads > 0;
1572 chain->need_operand_change = operands_changed;
1574 /* Discard any register replacements done. */
1575 if (did_elimination)
1577 obstack_free (&reload_obstack, reload_insn_firstobj);
1578 PATTERN (insn) = old_body;
1579 INSN_CODE (insn) = old_code;
1580 REG_NOTES (insn) = old_notes;
1581 something_needs_elimination = 1;
1584 something_needs_operands_changed |= operands_changed;
1588 copy_reloads (chain);
1589 *pprev_reload = chain;
1590 pprev_reload = &chain->next_need_reload;
1597 /* This function is called from the register allocator to set up estimates
1598 for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1599 an invariant. The structure is similar to calculate_needs_all_insns. */
1602 calculate_elim_costs_all_insns (void)
1604 int *reg_equiv_init_cost;
1608 reg_equiv_init_cost = XCNEWVEC (int, max_regno);
1610 init_eliminable_invariants (get_insns (), false);
1612 set_initial_elim_offsets ();
1613 set_initial_label_offsets ();
1620 FOR_BB_INSNS (bb, insn)
1622 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1623 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1624 what effects this has on the known offsets at labels. */
1626 if (LABEL_P (insn) || JUMP_P (insn)
1627 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1628 set_label_offsets (insn, insn, 0);
1632 rtx set = single_set (insn);
1634 /* Skip insns that only set an equivalence. */
1635 if (set && REG_P (SET_DEST (set))
1636 && reg_renumber[REGNO (SET_DEST (set))] < 0
1637 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1638 || (reg_equiv_invariant[REGNO (SET_DEST (set))])))
1640 unsigned regno = REGNO (SET_DEST (set));
1641 rtx init = reg_equiv_init[regno];
1644 rtx t = eliminate_regs_1 (SET_SRC (set), VOIDmode, insn,
1646 int cost = rtx_cost (t, SET,
1647 optimize_bb_for_speed_p (bb));
1648 int freq = REG_FREQ_FROM_BB (bb);
1650 reg_equiv_init_cost[regno] = cost * freq;
1654 /* If needed, eliminate any eliminable registers. */
1655 if (num_eliminable || num_eliminable_invariants)
1656 elimination_costs_in_insn (insn);
1659 update_eliminable_offsets ();
1663 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1665 if (reg_equiv_invariant[i])
1667 if (reg_equiv_init[i])
1669 int cost = reg_equiv_init_cost[i];
1672 "Reg %d has equivalence, initial gains %d\n", i, cost);
1674 ira_adjust_equiv_reg_cost (i, cost);
1680 "Reg %d had equivalence, but can't be eliminated\n",
1682 ira_adjust_equiv_reg_cost (i, 0);
1688 free (reg_equiv_init_cost);
1691 /* Comparison function for qsort to decide which of two reloads
1692 should be handled first. *P1 and *P2 are the reload numbers. */
1695 reload_reg_class_lower (const void *r1p, const void *r2p)
1697 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1700 /* Consider required reloads before optional ones. */
1701 t = rld[r1].optional - rld[r2].optional;
1705 /* Count all solitary classes before non-solitary ones. */
1706 t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1707 - (reg_class_size[(int) rld[r1].rclass] == 1));
1711 /* Aside from solitaires, consider all multi-reg groups first. */
1712 t = rld[r2].nregs - rld[r1].nregs;
1716 /* Consider reloads in order of increasing reg-class number. */
1717 t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1721 /* If reloads are equally urgent, sort by reload number,
1722 so that the results of qsort leave nothing to chance. */
1726 /* The cost of spilling each hard reg. */
1727 static int spill_cost[FIRST_PSEUDO_REGISTER];
1729 /* When spilling multiple hard registers, we use SPILL_COST for the first
1730 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1731 only the first hard reg for a multi-reg pseudo. */
1732 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1734 /* Map of hard regno to pseudo regno currently occupying the hard
1736 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1738 /* Update the spill cost arrays, considering that pseudo REG is live. */
1741 count_pseudo (int reg)
1743 int freq = REG_FREQ (reg);
1744 int r = reg_renumber[reg];
1747 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1748 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1749 /* Ignore spilled pseudo-registers which can be here only if IRA
1751 || (ira_conflicts_p && r < 0))
1754 SET_REGNO_REG_SET (&pseudos_counted, reg);
1756 gcc_assert (r >= 0);
1758 spill_add_cost[r] += freq;
1759 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1762 hard_regno_to_pseudo_regno[r + nregs] = reg;
1763 spill_cost[r + nregs] += freq;
1767 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1768 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1771 order_regs_for_reload (struct insn_chain *chain)
1774 HARD_REG_SET used_by_pseudos;
1775 HARD_REG_SET used_by_pseudos2;
1776 reg_set_iterator rsi;
1778 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1780 memset (spill_cost, 0, sizeof spill_cost);
1781 memset (spill_add_cost, 0, sizeof spill_add_cost);
1782 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1783 hard_regno_to_pseudo_regno[i] = -1;
1785 /* Count number of uses of each hard reg by pseudo regs allocated to it
1786 and then order them by decreasing use. First exclude hard registers
1787 that are live in or across this insn. */
1789 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1790 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1791 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1792 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1794 /* Now find out which pseudos are allocated to it, and update
1796 CLEAR_REG_SET (&pseudos_counted);
1798 EXECUTE_IF_SET_IN_REG_SET
1799 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1803 EXECUTE_IF_SET_IN_REG_SET
1804 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1808 CLEAR_REG_SET (&pseudos_counted);
1811 /* Vector of reload-numbers showing the order in which the reloads should
1813 static short reload_order[MAX_RELOADS];
1815 /* This is used to keep track of the spill regs used in one insn. */
1816 static HARD_REG_SET used_spill_regs_local;
1818 /* We decided to spill hard register SPILLED, which has a size of
1819 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1820 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1821 update SPILL_COST/SPILL_ADD_COST. */
1824 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1826 int freq = REG_FREQ (reg);
1827 int r = reg_renumber[reg];
1828 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1830 /* Ignore spilled pseudo-registers which can be here only if IRA is
1832 if ((ira_conflicts_p && r < 0)
1833 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1834 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1837 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1839 spill_add_cost[r] -= freq;
1842 hard_regno_to_pseudo_regno[r + nregs] = -1;
1843 spill_cost[r + nregs] -= freq;
1847 /* Find reload register to use for reload number ORDER. */
1850 find_reg (struct insn_chain *chain, int order)
1852 int rnum = reload_order[order];
1853 struct reload *rl = rld + rnum;
1854 int best_cost = INT_MAX;
1856 unsigned int i, j, n;
1858 HARD_REG_SET not_usable;
1859 HARD_REG_SET used_by_other_reload;
1860 reg_set_iterator rsi;
1861 static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1862 static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1864 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1865 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1866 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
1868 CLEAR_HARD_REG_SET (used_by_other_reload);
1869 for (k = 0; k < order; k++)
1871 int other = reload_order[k];
1873 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1874 for (j = 0; j < rld[other].nregs; j++)
1875 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1878 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1880 #ifdef REG_ALLOC_ORDER
1881 unsigned int regno = reg_alloc_order[i];
1883 unsigned int regno = i;
1886 if (! TEST_HARD_REG_BIT (not_usable, regno)
1887 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1888 && HARD_REGNO_MODE_OK (regno, rl->mode))
1890 int this_cost = spill_cost[regno];
1892 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1894 for (j = 1; j < this_nregs; j++)
1896 this_cost += spill_add_cost[regno + j];
1897 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1898 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1904 if (ira_conflicts_p)
1906 /* Ask IRA to find a better pseudo-register for
1908 for (n = j = 0; j < this_nregs; j++)
1910 int r = hard_regno_to_pseudo_regno[regno + j];
1914 if (n == 0 || regno_pseudo_regs[n - 1] != r)
1915 regno_pseudo_regs[n++] = r;
1917 regno_pseudo_regs[n++] = -1;
1919 || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1920 best_regno_pseudo_regs,
1927 best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1928 if (regno_pseudo_regs[j] < 0)
1935 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1937 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1939 if (this_cost < best_cost
1940 /* Among registers with equal cost, prefer caller-saved ones, or
1941 use REG_ALLOC_ORDER if it is defined. */
1942 || (this_cost == best_cost
1943 #ifdef REG_ALLOC_ORDER
1944 && (inv_reg_alloc_order[regno]
1945 < inv_reg_alloc_order[best_reg])
1947 && call_used_regs[regno]
1948 && ! call_used_regs[best_reg]
1953 best_cost = this_cost;
1961 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1963 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1964 rl->regno = best_reg;
1966 EXECUTE_IF_SET_IN_REG_SET
1967 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1969 count_spilled_pseudo (best_reg, rl->nregs, j);
1972 EXECUTE_IF_SET_IN_REG_SET
1973 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1975 count_spilled_pseudo (best_reg, rl->nregs, j);
1978 for (i = 0; i < rl->nregs; i++)
1980 gcc_assert (spill_cost[best_reg + i] == 0);
1981 gcc_assert (spill_add_cost[best_reg + i] == 0);
1982 gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
1983 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1988 /* Find more reload regs to satisfy the remaining need of an insn, which
1990 Do it by ascending class number, since otherwise a reg
1991 might be spilled for a big class and might fail to count
1992 for a smaller class even though it belongs to that class. */
1995 find_reload_regs (struct insn_chain *chain)
1999 /* In order to be certain of getting the registers we need,
2000 we must sort the reloads into order of increasing register class.
2001 Then our grabbing of reload registers will parallel the process
2002 that provided the reload registers. */
2003 for (i = 0; i < chain->n_reloads; i++)
2005 /* Show whether this reload already has a hard reg. */
2006 if (chain->rld[i].reg_rtx)
2008 int regno = REGNO (chain->rld[i].reg_rtx);
2009 chain->rld[i].regno = regno;
2011 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
2014 chain->rld[i].regno = -1;
2015 reload_order[i] = i;
2018 n_reloads = chain->n_reloads;
2019 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
2021 CLEAR_HARD_REG_SET (used_spill_regs_local);
2024 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
2026 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
2028 /* Compute the order of preference for hard registers to spill. */
2030 order_regs_for_reload (chain);
2032 for (i = 0; i < n_reloads; i++)
2034 int r = reload_order[i];
2036 /* Ignore reloads that got marked inoperative. */
2037 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
2038 && ! rld[r].optional
2039 && rld[r].regno == -1)
2040 if (! find_reg (chain, i))
2043 fprintf (dump_file, "reload failure for reload %d\n", r);
2044 spill_failure (chain->insn, rld[r].rclass);
2050 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
2051 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
2053 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2057 select_reload_regs (void)
2059 struct insn_chain *chain;
2061 /* Try to satisfy the needs for each insn. */
2062 for (chain = insns_need_reload; chain != 0;
2063 chain = chain->next_need_reload)
2064 find_reload_regs (chain);
2067 /* Delete all insns that were inserted by emit_caller_save_insns during
2070 delete_caller_save_insns (void)
2072 struct insn_chain *c = reload_insn_chain;
2076 while (c != 0 && c->is_caller_save_insn)
2078 struct insn_chain *next = c->next;
2081 if (c == reload_insn_chain)
2082 reload_insn_chain = next;
2086 next->prev = c->prev;
2088 c->prev->next = next;
2089 c->next = unused_insn_chains;
2090 unused_insn_chains = c;
2098 /* Handle the failure to find a register to spill.
2099 INSN should be one of the insns which needed this particular spill reg. */
2102 spill_failure (rtx insn, enum reg_class rclass)
2104 if (asm_noperands (PATTERN (insn)) >= 0)
2105 error_for_asm (insn, "can't find a register in class %qs while "
2106 "reloading %<asm%>",
2107 reg_class_names[rclass]);
2110 error ("unable to find a register to spill in class %qs",
2111 reg_class_names[rclass]);
2115 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2116 debug_reload_to_stream (dump_file);
2118 fatal_insn ("this is the insn:", insn);
2122 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2123 data that is dead in INSN. */
2126 delete_dead_insn (rtx insn)
2128 rtx prev = prev_real_insn (insn);
2131 /* If the previous insn sets a register that dies in our insn, delete it
2133 if (prev && GET_CODE (PATTERN (prev)) == SET
2134 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2135 && reg_mentioned_p (prev_dest, PATTERN (insn))
2136 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2137 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2138 delete_dead_insn (prev);
2140 SET_INSN_DELETED (insn);
2143 /* Modify the home of pseudo-reg I.
2144 The new home is present in reg_renumber[I].
2146 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2147 or it may be -1, meaning there is none or it is not relevant.
2148 This is used so that all pseudos spilled from a given hard reg
2149 can share one stack slot. */
2152 alter_reg (int i, int from_reg, bool dont_share_p)
2154 /* When outputting an inline function, this can happen
2155 for a reg that isn't actually used. */
2156 if (regno_reg_rtx[i] == 0)
2159 /* If the reg got changed to a MEM at rtl-generation time,
2161 if (!REG_P (regno_reg_rtx[i]))
2164 /* Modify the reg-rtx to contain the new hard reg
2165 number or else to contain its pseudo reg number. */
2166 SET_REGNO (regno_reg_rtx[i],
2167 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2169 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2170 allocate a stack slot for it. */
2172 if (reg_renumber[i] < 0
2173 && REG_N_REFS (i) > 0
2174 && reg_equiv_constant[i] == 0
2175 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
2176 && reg_equiv_memory_loc[i] == 0)
2179 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2180 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2181 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2182 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2183 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2186 something_was_spilled = true;
2188 if (ira_conflicts_p)
2190 /* Mark the spill for IRA. */
2191 SET_REGNO_REG_SET (&spilled_pseudos, i);
2193 x = ira_reuse_stack_slot (i, inherent_size, total_size);
2199 /* Each pseudo reg has an inherent size which comes from its own mode,
2200 and a total size which provides room for paradoxical subregs
2201 which refer to the pseudo reg in wider modes.
2203 We can use a slot already allocated if it provides both
2204 enough inherent space and enough total space.
2205 Otherwise, we allocate a new slot, making sure that it has no less
2206 inherent space, and no less total space, then the previous slot. */
2207 else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
2211 /* No known place to spill from => no slot to reuse. */
2212 x = assign_stack_local (mode, total_size,
2213 min_align > inherent_align
2214 || total_size > inherent_size ? -1 : 0);
2218 /* Cancel the big-endian correction done in assign_stack_local.
2219 Get the address of the beginning of the slot. This is so we
2220 can do a big-endian correction unconditionally below. */
2221 if (BYTES_BIG_ENDIAN)
2223 adjust = inherent_size - total_size;
2226 = adjust_address_nv (x, mode_for_size (total_size
2232 if (! dont_share_p && ira_conflicts_p)
2233 /* Inform IRA about allocation a new stack slot. */
2234 ira_mark_new_stack_slot (stack_slot, i, total_size);
2237 /* Reuse a stack slot if possible. */
2238 else if (spill_stack_slot[from_reg] != 0
2239 && spill_stack_slot_width[from_reg] >= total_size
2240 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2242 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2243 x = spill_stack_slot[from_reg];
2245 /* Allocate a bigger slot. */
2248 /* Compute maximum size needed, both for inherent size
2249 and for total size. */
2252 if (spill_stack_slot[from_reg])
2254 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2256 mode = GET_MODE (spill_stack_slot[from_reg]);
2257 if (spill_stack_slot_width[from_reg] > total_size)
2258 total_size = spill_stack_slot_width[from_reg];
2259 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2260 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2263 /* Make a slot with that size. */
2264 x = assign_stack_local (mode, total_size,
2265 min_align > inherent_align
2266 || total_size > inherent_size ? -1 : 0);
2269 /* Cancel the big-endian correction done in assign_stack_local.
2270 Get the address of the beginning of the slot. This is so we
2271 can do a big-endian correction unconditionally below. */
2272 if (BYTES_BIG_ENDIAN)
2274 adjust = GET_MODE_SIZE (mode) - total_size;
2277 = adjust_address_nv (x, mode_for_size (total_size
2283 spill_stack_slot[from_reg] = stack_slot;
2284 spill_stack_slot_width[from_reg] = total_size;
2287 /* On a big endian machine, the "address" of the slot
2288 is the address of the low part that fits its inherent mode. */
2289 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2290 adjust += (total_size - inherent_size);
2292 /* If we have any adjustment to make, or if the stack slot is the
2293 wrong mode, make a new stack slot. */
2294 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2296 /* Set all of the memory attributes as appropriate for a spill. */
2297 set_mem_attrs_for_spill (x);
2299 /* Save the stack slot for later. */
2300 reg_equiv_memory_loc[i] = x;
2304 /* Mark the slots in regs_ever_live for the hard regs used by
2305 pseudo-reg number REGNO, accessed in MODE. */
2308 mark_home_live_1 (int regno, enum machine_mode mode)
2312 i = reg_renumber[regno];
2315 lim = end_hard_regno (mode, i);
2317 df_set_regs_ever_live(i++, true);
2320 /* Mark the slots in regs_ever_live for the hard regs
2321 used by pseudo-reg number REGNO. */
2324 mark_home_live (int regno)
2326 if (reg_renumber[regno] >= 0)
2327 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2330 /* This function handles the tracking of elimination offsets around branches.
2332 X is a piece of RTL being scanned.
2334 INSN is the insn that it came from, if any.
2336 INITIAL_P is nonzero if we are to set the offset to be the initial
2337 offset and zero if we are setting the offset of the label to be the
2341 set_label_offsets (rtx x, rtx insn, int initial_p)
2343 enum rtx_code code = GET_CODE (x);
2346 struct elim_table *p;
2351 if (LABEL_REF_NONLOCAL_P (x))
2356 /* ... fall through ... */
2359 /* If we know nothing about this label, set the desired offsets. Note
2360 that this sets the offset at a label to be the offset before a label
2361 if we don't know anything about the label. This is not correct for
2362 the label after a BARRIER, but is the best guess we can make. If
2363 we guessed wrong, we will suppress an elimination that might have
2364 been possible had we been able to guess correctly. */
2366 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2368 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2369 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2370 = (initial_p ? reg_eliminate[i].initial_offset
2371 : reg_eliminate[i].offset);
2372 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2375 /* Otherwise, if this is the definition of a label and it is
2376 preceded by a BARRIER, set our offsets to the known offset of
2380 && (tem = prev_nonnote_insn (insn)) != 0
2382 set_offsets_for_label (insn);
2384 /* If neither of the above cases is true, compare each offset
2385 with those previously recorded and suppress any eliminations
2386 where the offsets disagree. */
2388 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2389 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2390 != (initial_p ? reg_eliminate[i].initial_offset
2391 : reg_eliminate[i].offset))
2392 reg_eliminate[i].can_eliminate = 0;
2397 set_label_offsets (PATTERN (insn), insn, initial_p);
2399 /* ... fall through ... */
2403 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2404 to indirectly and hence must have all eliminations at their
2406 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2407 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2408 set_label_offsets (XEXP (tem, 0), insn, 1);
2414 /* Each of the labels in the parallel or address vector must be
2415 at their initial offsets. We want the first field for PARALLEL
2416 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2418 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2419 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2424 /* We only care about setting PC. If the source is not RETURN,
2425 IF_THEN_ELSE, or a label, disable any eliminations not at
2426 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2427 isn't one of those possibilities. For branches to a label,
2428 call ourselves recursively.
2430 Note that this can disable elimination unnecessarily when we have
2431 a non-local goto since it will look like a non-constant jump to
2432 someplace in the current function. This isn't a significant
2433 problem since such jumps will normally be when all elimination
2434 pairs are back to their initial offsets. */
2436 if (SET_DEST (x) != pc_rtx)
2439 switch (GET_CODE (SET_SRC (x)))
2446 set_label_offsets (SET_SRC (x), insn, initial_p);
2450 tem = XEXP (SET_SRC (x), 1);
2451 if (GET_CODE (tem) == LABEL_REF)
2452 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2453 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2456 tem = XEXP (SET_SRC (x), 2);
2457 if (GET_CODE (tem) == LABEL_REF)
2458 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2459 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2467 /* If we reach here, all eliminations must be at their initial
2468 offset because we are doing a jump to a variable address. */
2469 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2470 if (p->offset != p->initial_offset)
2471 p->can_eliminate = 0;
2479 /* Called through for_each_rtx, this function examines every reg that occurs
2480 in PX and adjusts the costs for its elimination which are gathered by IRA.
2481 DATA is the insn in which PX occurs. We do not recurse into MEM
2485 note_reg_elim_costly (rtx *px, void *data)
2487 rtx insn = (rtx)data;
2494 && REGNO (x) >= FIRST_PSEUDO_REGISTER
2495 && reg_equiv_init[REGNO (x)]
2496 && reg_equiv_invariant[REGNO (x)])
2498 rtx t = reg_equiv_invariant[REGNO (x)];
2499 rtx new_rtx = eliminate_regs_1 (t, Pmode, insn, true, true);
2500 int cost = rtx_cost (new_rtx, SET, optimize_bb_for_speed_p (elim_bb));
2501 int freq = REG_FREQ_FROM_BB (elim_bb);
2504 ira_adjust_equiv_reg_cost (REGNO (x), -cost * freq);
2509 /* Scan X and replace any eliminable registers (such as fp) with a
2510 replacement (such as sp), plus an offset.
2512 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2513 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2514 MEM, we are allowed to replace a sum of a register and the constant zero
2515 with the register, which we cannot do outside a MEM. In addition, we need
2516 to record the fact that a register is referenced outside a MEM.
2518 If INSN is an insn, it is the insn containing X. If we replace a REG
2519 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2520 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2521 the REG is being modified.
2523 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2524 That's used when we eliminate in expressions stored in notes.
2525 This means, do not set ref_outside_mem even if the reference
2528 If FOR_COSTS is true, we are being called before reload in order to
2529 estimate the costs of keeping registers with an equivalence unallocated.
2531 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2532 replacements done assuming all offsets are at their initial values. If
2533 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2534 encounter, return the actual location so that find_reloads will do
2535 the proper thing. */
2538 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2539 bool may_use_invariant, bool for_costs)
2541 enum rtx_code code = GET_CODE (x);
2542 struct elim_table *ep;
2549 if (! current_function_decl)
2572 /* First handle the case where we encounter a bare register that
2573 is eliminable. Replace it with a PLUS. */
2574 if (regno < FIRST_PSEUDO_REGISTER)
2576 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2578 if (ep->from_rtx == x && ep->can_eliminate)
2579 return plus_constant (ep->to_rtx, ep->previous_offset);
2582 else if (reg_renumber && reg_renumber[regno] < 0
2583 && reg_equiv_invariant && reg_equiv_invariant[regno])
2585 if (may_use_invariant || (insn && DEBUG_INSN_P (insn)))
2586 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2587 mem_mode, insn, true, for_costs);
2588 /* There exists at least one use of REGNO that cannot be
2589 eliminated. Prevent the defining insn from being deleted. */
2590 reg_equiv_init[regno] = NULL_RTX;
2592 alter_reg (regno, -1, true);
2596 /* You might think handling MINUS in a manner similar to PLUS is a
2597 good idea. It is not. It has been tried multiple times and every
2598 time the change has had to have been reverted.
2600 Other parts of reload know a PLUS is special (gen_reload for example)
2601 and require special code to handle code a reloaded PLUS operand.
2603 Also consider backends where the flags register is clobbered by a
2604 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2605 lea instruction comes to mind). If we try to reload a MINUS, we
2606 may kill the flags register that was holding a useful value.
2608 So, please before trying to handle MINUS, consider reload as a
2609 whole instead of this little section as well as the backend issues. */
2611 /* If this is the sum of an eliminable register and a constant, rework
2613 if (REG_P (XEXP (x, 0))
2614 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2615 && CONSTANT_P (XEXP (x, 1)))
2617 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2619 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2621 /* The only time we want to replace a PLUS with a REG (this
2622 occurs when the constant operand of the PLUS is the negative
2623 of the offset) is when we are inside a MEM. We won't want
2624 to do so at other times because that would change the
2625 structure of the insn in a way that reload can't handle.
2626 We special-case the commonest situation in
2627 eliminate_regs_in_insn, so just replace a PLUS with a
2628 PLUS here, unless inside a MEM. */
2629 if (mem_mode != 0 && CONST_INT_P (XEXP (x, 1))
2630 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2633 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2634 plus_constant (XEXP (x, 1),
2635 ep->previous_offset));
2638 /* If the register is not eliminable, we are done since the other
2639 operand is a constant. */
2643 /* If this is part of an address, we want to bring any constant to the
2644 outermost PLUS. We will do this by doing register replacement in
2645 our operands and seeing if a constant shows up in one of them.
2647 Note that there is no risk of modifying the structure of the insn,
2648 since we only get called for its operands, thus we are either
2649 modifying the address inside a MEM, or something like an address
2650 operand of a load-address insn. */
2653 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2655 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2658 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2660 /* If one side is a PLUS and the other side is a pseudo that
2661 didn't get a hard register but has a reg_equiv_constant,
2662 we must replace the constant here since it may no longer
2663 be in the position of any operand. */
2664 if (GET_CODE (new0) == PLUS && REG_P (new1)
2665 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2666 && reg_renumber[REGNO (new1)] < 0
2667 && reg_equiv_constant != 0
2668 && reg_equiv_constant[REGNO (new1)] != 0)
2669 new1 = reg_equiv_constant[REGNO (new1)];
2670 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2671 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2672 && reg_renumber[REGNO (new0)] < 0
2673 && reg_equiv_constant[REGNO (new0)] != 0)
2674 new0 = reg_equiv_constant[REGNO (new0)];
2676 new_rtx = form_sum (GET_MODE (x), new0, new1);
2678 /* As above, if we are not inside a MEM we do not want to
2679 turn a PLUS into something else. We might try to do so here
2680 for an addition of 0 if we aren't optimizing. */
2681 if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2682 return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2690 /* If this is the product of an eliminable register and a
2691 constant, apply the distribute law and move the constant out
2692 so that we have (plus (mult ..) ..). This is needed in order
2693 to keep load-address insns valid. This case is pathological.
2694 We ignore the possibility of overflow here. */
2695 if (REG_P (XEXP (x, 0))
2696 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2697 && CONST_INT_P (XEXP (x, 1)))
2698 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2700 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2703 /* Refs inside notes or in DEBUG_INSNs don't count for
2705 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2706 || GET_CODE (insn) == INSN_LIST
2707 || DEBUG_INSN_P (insn))))
2708 ep->ref_outside_mem = 1;
2711 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2712 ep->previous_offset * INTVAL (XEXP (x, 1)));
2715 /* ... fall through ... */
2719 /* See comments before PLUS about handling MINUS. */
2721 case DIV: case UDIV:
2722 case MOD: case UMOD:
2723 case AND: case IOR: case XOR:
2724 case ROTATERT: case ROTATE:
2725 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2727 case GE: case GT: case GEU: case GTU:
2728 case LE: case LT: case LEU: case LTU:
2730 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2732 rtx new1 = XEXP (x, 1)
2733 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false,
2736 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2737 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2742 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2745 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2747 if (new_rtx != XEXP (x, 0))
2749 /* If this is a REG_DEAD note, it is not valid anymore.
2750 Using the eliminated version could result in creating a
2751 REG_DEAD note for the stack or frame pointer. */
2752 if (REG_NOTE_KIND (x) == REG_DEAD)
2754 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2758 x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2762 /* ... fall through ... */
2765 /* Now do eliminations in the rest of the chain. If this was
2766 an EXPR_LIST, this might result in allocating more memory than is
2767 strictly needed, but it simplifies the code. */
2770 new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2772 if (new_rtx != XEXP (x, 1))
2774 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2782 /* We do not support elimination of a register that is modified.
2783 elimination_effects has already make sure that this does not
2789 /* We do not support elimination of a register that is modified.
2790 elimination_effects has already make sure that this does not
2791 happen. The only remaining case we need to consider here is
2792 that the increment value may be an eliminable register. */
2793 if (GET_CODE (XEXP (x, 1)) == PLUS
2794 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2796 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2797 insn, true, for_costs);
2799 if (new_rtx != XEXP (XEXP (x, 1), 1))
2800 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2801 gen_rtx_PLUS (GET_MODE (x),
2802 XEXP (x, 0), new_rtx));
2806 case STRICT_LOW_PART:
2808 case SIGN_EXTEND: case ZERO_EXTEND:
2809 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2810 case FLOAT: case FIX:
2811 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2820 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2822 if (new_rtx != XEXP (x, 0))
2823 return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2827 /* Similar to above processing, but preserve SUBREG_BYTE.
2828 Convert (subreg (mem)) to (mem) if not paradoxical.
2829 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2830 pseudo didn't get a hard reg, we must replace this with the
2831 eliminated version of the memory location because push_reload
2832 may do the replacement in certain circumstances. */
2833 if (REG_P (SUBREG_REG (x))
2834 && (GET_MODE_SIZE (GET_MODE (x))
2835 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2836 && reg_equiv_memory_loc != 0
2837 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2839 new_rtx = SUBREG_REG (x);
2842 new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false,
2845 if (new_rtx != SUBREG_REG (x))
2847 int x_size = GET_MODE_SIZE (GET_MODE (x));
2848 int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2851 && ((x_size < new_size
2852 #ifdef WORD_REGISTER_OPERATIONS
2853 /* On these machines, combine can create rtl of the form
2854 (set (subreg:m1 (reg:m2 R) 0) ...)
2855 where m1 < m2, and expects something interesting to
2856 happen to the entire word. Moreover, it will use the
2857 (reg:m2 R) later, expecting all bits to be preserved.
2858 So if the number of words is the same, preserve the
2859 subreg so that push_reload can see it. */
2860 && ! ((x_size - 1) / UNITS_PER_WORD
2861 == (new_size -1 ) / UNITS_PER_WORD)
2864 || x_size == new_size)
2866 return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2868 return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2874 /* Our only special processing is to pass the mode of the MEM to our
2875 recursive call and copy the flags. While we are here, handle this
2876 case more efficiently. */
2878 new_rtx = eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), insn, true,
2881 && memory_address_p (GET_MODE (x), XEXP (x, 0))
2882 && !memory_address_p (GET_MODE (x), new_rtx))
2883 for_each_rtx (&XEXP (x, 0), note_reg_elim_costly, insn);
2885 return replace_equiv_address_nv (x, new_rtx);
2888 /* Handle insn_list USE that a call to a pure function may generate. */
2889 new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false,
2891 if (new_rtx != XEXP (x, 0))
2892 return gen_rtx_USE (GET_MODE (x), new_rtx);
2896 gcc_assert (insn && DEBUG_INSN_P (insn));
2907 /* Process each of our operands recursively. If any have changed, make a
2909 fmt = GET_RTX_FORMAT (code);
2910 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2914 new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false,
2916 if (new_rtx != XEXP (x, i) && ! copied)
2918 x = shallow_copy_rtx (x);
2921 XEXP (x, i) = new_rtx;
2923 else if (*fmt == 'E')
2926 for (j = 0; j < XVECLEN (x, i); j++)
2928 new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false,
2930 if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2932 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2936 x = shallow_copy_rtx (x);
2939 XVEC (x, i) = new_v;
2942 XVECEXP (x, i, j) = new_rtx;
2951 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2953 return eliminate_regs_1 (x, mem_mode, insn, false, false);
2956 /* Scan rtx X for modifications of elimination target registers. Update
2957 the table of eliminables to reflect the changed state. MEM_MODE is
2958 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2961 elimination_effects (rtx x, enum machine_mode mem_mode)
2963 enum rtx_code code = GET_CODE (x);
2964 struct elim_table *ep;
2989 /* First handle the case where we encounter a bare register that
2990 is eliminable. Replace it with a PLUS. */
2991 if (regno < FIRST_PSEUDO_REGISTER)
2993 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2995 if (ep->from_rtx == x && ep->can_eliminate)
2998 ep->ref_outside_mem = 1;
3003 else if (reg_renumber[regno] < 0 && reg_equiv_constant
3004 && reg_equiv_constant[regno]
3005 && ! function_invariant_p (reg_equiv_constant[regno]))
3006 elimination_effects (reg_equiv_constant[regno], mem_mode);
3015 /* If we modify the source of an elimination rule, disable it. */
3016 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3017 if (ep->from_rtx == XEXP (x, 0))
3018 ep->can_eliminate = 0;
3020 /* If we modify the target of an elimination rule by adding a constant,
3021 update its offset. If we modify the target in any other way, we'll
3022 have to disable the rule as well. */
3023 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3024 if (ep->to_rtx == XEXP (x, 0))
3026 int size = GET_MODE_SIZE (mem_mode);
3028 /* If more bytes than MEM_MODE are pushed, account for them. */
3029 #ifdef PUSH_ROUNDING
3030 if (ep->to_rtx == stack_pointer_rtx)
3031 size = PUSH_ROUNDING (size);
3033 if (code == PRE_DEC || code == POST_DEC)
3035 else if (code == PRE_INC || code == POST_INC)
3037 else if (code == PRE_MODIFY || code == POST_MODIFY)
3039 if (GET_CODE (XEXP (x, 1)) == PLUS
3040 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
3041 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
3042 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
3044 ep->can_eliminate = 0;
3048 /* These two aren't unary operators. */
3049 if (code == POST_MODIFY || code == PRE_MODIFY)
3052 /* Fall through to generic unary operation case. */
3053 case STRICT_LOW_PART:
3055 case SIGN_EXTEND: case ZERO_EXTEND:
3056 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3057 case FLOAT: case FIX:
3058 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3067 elimination_effects (XEXP (x, 0), mem_mode);
3071 if (REG_P (SUBREG_REG (x))
3072 && (GET_MODE_SIZE (GET_MODE (x))
3073 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3074 && reg_equiv_memory_loc != 0
3075 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
3078 elimination_effects (SUBREG_REG (x), mem_mode);
3082 /* If using a register that is the source of an eliminate we still
3083 think can be performed, note it cannot be performed since we don't
3084 know how this register is used. */
3085 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3086 if (ep->from_rtx == XEXP (x, 0))
3087 ep->can_eliminate = 0;
3089 elimination_effects (XEXP (x, 0), mem_mode);
3093 /* If clobbering a register that is the replacement register for an
3094 elimination we still think can be performed, note that it cannot
3095 be performed. Otherwise, we need not be concerned about it. */
3096 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3097 if (ep->to_rtx == XEXP (x, 0))
3098 ep->can_eliminate = 0;
3100 elimination_effects (XEXP (x, 0), mem_mode);
3104 /* Check for setting a register that we know about. */
3105 if (REG_P (SET_DEST (x)))
3107 /* See if this is setting the replacement register for an
3110 If DEST is the hard frame pointer, we do nothing because we
3111 assume that all assignments to the frame pointer are for
3112 non-local gotos and are being done at a time when they are valid
3113 and do not disturb anything else. Some machines want to
3114 eliminate a fake argument pointer (or even a fake frame pointer)
3115 with either the real frame or the stack pointer. Assignments to
3116 the hard frame pointer must not prevent this elimination. */
3118 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3120 if (ep->to_rtx == SET_DEST (x)
3121 && SET_DEST (x) != hard_frame_pointer_rtx)
3123 /* If it is being incremented, adjust the offset. Otherwise,
3124 this elimination can't be done. */
3125 rtx src = SET_SRC (x);
3127 if (GET_CODE (src) == PLUS
3128 && XEXP (src, 0) == SET_DEST (x)
3129 && CONST_INT_P (XEXP (src, 1)))
3130 ep->offset -= INTVAL (XEXP (src, 1));
3132 ep->can_eliminate = 0;
3136 elimination_effects (SET_DEST (x), VOIDmode);
3137 elimination_effects (SET_SRC (x), VOIDmode);
3141 /* Our only special processing is to pass the mode of the MEM to our
3143 elimination_effects (XEXP (x, 0), GET_MODE (x));
3150 fmt = GET_RTX_FORMAT (code);
3151 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3154 elimination_effects (XEXP (x, i), mem_mode);
3155 else if (*fmt == 'E')
3156 for (j = 0; j < XVECLEN (x, i); j++)
3157 elimination_effects (XVECEXP (x, i, j), mem_mode);
3161 /* Descend through rtx X and verify that no references to eliminable registers
3162 remain. If any do remain, mark the involved register as not
3166 check_eliminable_occurrences (rtx x)
3175 code = GET_CODE (x);
3177 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3179 struct elim_table *ep;
3181 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3182 if (ep->from_rtx == x)
3183 ep->can_eliminate = 0;
3187 fmt = GET_RTX_FORMAT (code);
3188 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3191 check_eliminable_occurrences (XEXP (x, i));
3192 else if (*fmt == 'E')
3195 for (j = 0; j < XVECLEN (x, i); j++)
3196 check_eliminable_occurrences (XVECEXP (x, i, j));
3201 /* Scan INSN and eliminate all eliminable registers in it.
3203 If REPLACE is nonzero, do the replacement destructively. Also
3204 delete the insn as dead it if it is setting an eliminable register.
3206 If REPLACE is zero, do all our allocations in reload_obstack.
3208 If no eliminations were done and this insn doesn't require any elimination
3209 processing (these are not identical conditions: it might be updating sp,
3210 but not referencing fp; this needs to be seen during reload_as_needed so
3211 that the offset between fp and sp can be taken into consideration), zero
3212 is returned. Otherwise, 1 is returned. */
3215 eliminate_regs_in_insn (rtx insn, int replace)
3217 int icode = recog_memoized (insn);
3218 rtx old_body = PATTERN (insn);
3219 int insn_is_asm = asm_noperands (old_body) >= 0;
3220 rtx old_set = single_set (insn);
3224 rtx substed_operand[MAX_RECOG_OPERANDS];
3225 rtx orig_operand[MAX_RECOG_OPERANDS];
3226 struct elim_table *ep;
3227 rtx plus_src, plus_cst_src;
3229 if (! insn_is_asm && icode < 0)
3231 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3232 || GET_CODE (PATTERN (insn)) == CLOBBER
3233 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3234 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3235 || GET_CODE (PATTERN (insn)) == ASM_INPUT
3236 || DEBUG_INSN_P (insn));
3237 if (DEBUG_INSN_P (insn))
3238 INSN_VAR_LOCATION_LOC (insn)
3239 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn), VOIDmode, insn);
3243 if (old_set != 0 && REG_P (SET_DEST (old_set))
3244 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3246 /* Check for setting an eliminable register. */
3247 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3248 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3250 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3251 /* If this is setting the frame pointer register to the
3252 hardware frame pointer register and this is an elimination
3253 that will be done (tested above), this insn is really
3254 adjusting the frame pointer downward to compensate for
3255 the adjustment done before a nonlocal goto. */
3256 if (ep->from == FRAME_POINTER_REGNUM
3257 && ep->to == HARD_FRAME_POINTER_REGNUM)
3259 rtx base = SET_SRC (old_set);
3260 rtx base_insn = insn;
3261 HOST_WIDE_INT offset = 0;
3263 while (base != ep->to_rtx)
3265 rtx prev_insn, prev_set;
3267 if (GET_CODE (base) == PLUS
3268 && CONST_INT_P (XEXP (base, 1)))
3270 offset += INTVAL (XEXP (base, 1));
3271 base = XEXP (base, 0);
3273 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3274 && (prev_set = single_set (prev_insn)) != 0
3275 && rtx_equal_p (SET_DEST (prev_set), base))
3277 base = SET_SRC (prev_set);
3278 base_insn = prev_insn;
3284 if (base == ep->to_rtx)
3287 = plus_constant (ep->to_rtx, offset - ep->offset);
3289 new_body = old_body;
3292 new_body = copy_insn (old_body);
3293 if (REG_NOTES (insn))
3294 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3296 PATTERN (insn) = new_body;
3297 old_set = single_set (insn);
3299 /* First see if this insn remains valid when we
3300 make the change. If not, keep the INSN_CODE
3301 the same and let reload fit it up. */
3302 validate_change (insn, &SET_SRC (old_set), src, 1);
3303 validate_change (insn, &SET_DEST (old_set),
3305 if (! apply_change_group ())
3307 SET_SRC (old_set) = src;
3308 SET_DEST (old_set) = ep->to_rtx;
3317 /* In this case this insn isn't serving a useful purpose. We
3318 will delete it in reload_as_needed once we know that this
3319 elimination is, in fact, being done.
3321 If REPLACE isn't set, we can't delete this insn, but needn't
3322 process it since it won't be used unless something changes. */
3325 delete_dead_insn (insn);
3333 /* We allow one special case which happens to work on all machines we
3334 currently support: a single set with the source or a REG_EQUAL
3335 note being a PLUS of an eliminable register and a constant. */
3336 plus_src = plus_cst_src = 0;
3337 if (old_set && REG_P (SET_DEST (old_set)))
3339 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3340 plus_src = SET_SRC (old_set);
3341 /* First see if the source is of the form (plus (...) CST). */
3343 && CONST_INT_P (XEXP (plus_src, 1)))
3344 plus_cst_src = plus_src;
3345 else if (REG_P (SET_SRC (old_set))
3348 /* Otherwise, see if we have a REG_EQUAL note of the form
3349 (plus (...) CST). */
3351 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3353 if ((REG_NOTE_KIND (links) == REG_EQUAL
3354 || REG_NOTE_KIND (links) == REG_EQUIV)
3355 && GET_CODE (XEXP (links, 0)) == PLUS
3356 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3358 plus_cst_src = XEXP (links, 0);
3364 /* Check that the first operand of the PLUS is a hard reg or
3365 the lowpart subreg of one. */
3368 rtx reg = XEXP (plus_cst_src, 0);
3369 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3370 reg = SUBREG_REG (reg);
3372 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3378 rtx reg = XEXP (plus_cst_src, 0);
3379 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3381 if (GET_CODE (reg) == SUBREG)
3382 reg = SUBREG_REG (reg);
3384 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3385 if (ep->from_rtx == reg && ep->can_eliminate)
3387 rtx to_rtx = ep->to_rtx;
3388 offset += ep->offset;
3389 offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
3391 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3392 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3394 /* If we have a nonzero offset, and the source is already
3395 a simple REG, the following transformation would
3396 increase the cost of the insn by replacing a simple REG
3397 with (plus (reg sp) CST). So try only when we already
3398 had a PLUS before. */
3399 if (offset == 0 || plus_src)
3401 rtx new_src = plus_constant (to_rtx, offset);
3403 new_body = old_body;
3406 new_body = copy_insn (old_body);
3407 if (REG_NOTES (insn))
3408 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3410 PATTERN (insn) = new_body;
3411 old_set = single_set (insn);
3413 /* First see if this insn remains valid when we make the
3414 change. If not, try to replace the whole pattern with
3415 a simple set (this may help if the original insn was a
3416 PARALLEL that was only recognized as single_set due to
3417 REG_UNUSED notes). If this isn't valid either, keep
3418 the INSN_CODE the same and let reload fix it up. */
3419 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3421 rtx new_pat = gen_rtx_SET (VOIDmode,
3422 SET_DEST (old_set), new_src);
3424 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3425 SET_SRC (old_set) = new_src;
3432 /* This can't have an effect on elimination offsets, so skip right
3438 /* Determine the effects of this insn on elimination offsets. */
3439 elimination_effects (old_body, VOIDmode);
3441 /* Eliminate all eliminable registers occurring in operands that
3442 can be handled by reload. */
3443 extract_insn (insn);
3444 for (i = 0; i < recog_data.n_operands; i++)
3446 orig_operand[i] = recog_data.operand[i];
3447 substed_operand[i] = recog_data.operand[i];
3449 /* For an asm statement, every operand is eliminable. */
3450 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3452 bool is_set_src, in_plus;
3454 /* Check for setting a register that we know about. */
3455 if (recog_data.operand_type[i] != OP_IN
3456 && REG_P (orig_operand[i]))
3458 /* If we are assigning to a register that can be eliminated, it
3459 must be as part of a PARALLEL, since the code above handles
3460 single SETs. We must indicate that we can no longer
3461 eliminate this reg. */
3462 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3464 if (ep->from_rtx == orig_operand[i])
3465 ep->can_eliminate = 0;
3468 /* Companion to the above plus substitution, we can allow
3469 invariants as the source of a plain move. */
3472 && recog_data.operand_loc[i] == &SET_SRC (old_set))
3476 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3477 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3481 = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3482 replace ? insn : NULL_RTX,
3483 is_set_src || in_plus, false);
3484 if (substed_operand[i] != orig_operand[i])
3486 /* Terminate the search in check_eliminable_occurrences at
3488 *recog_data.operand_loc[i] = 0;
3490 /* If an output operand changed from a REG to a MEM and INSN is an
3491 insn, write a CLOBBER insn. */
3492 if (recog_data.operand_type[i] != OP_IN
3493 && REG_P (orig_operand[i])
3494 && MEM_P (substed_operand[i])
3496 emit_insn_after (gen_clobber (orig_operand[i]), insn);
3500 for (i = 0; i < recog_data.n_dups; i++)
3501 *recog_data.dup_loc[i]
3502 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3504 /* If any eliminable remain, they aren't eliminable anymore. */
3505 check_eliminable_occurrences (old_body);
3507 /* Substitute the operands; the new values are in the substed_operand
3509 for (i = 0; i < recog_data.n_operands; i++)
3510 *recog_data.operand_loc[i] = substed_operand[i];
3511 for (i = 0; i < recog_data.n_dups; i++)
3512 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3514 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3515 re-recognize the insn. We do this in case we had a simple addition
3516 but now can do this as a load-address. This saves an insn in this
3518 If re-recognition fails, the old insn code number will still be used,
3519 and some register operands may have changed into PLUS expressions.
3520 These will be handled by find_reloads by loading them into a register
3525 /* If we aren't replacing things permanently and we changed something,
3526 make another copy to ensure that all the RTL is new. Otherwise
3527 things can go wrong if find_reload swaps commutative operands
3528 and one is inside RTL that has been copied while the other is not. */
3529 new_body = old_body;
3532 new_body = copy_insn (old_body);
3533 if (REG_NOTES (insn))
3534 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3536 PATTERN (insn) = new_body;
3538 /* If we had a move insn but now we don't, rerecognize it. This will
3539 cause spurious re-recognition if the old move had a PARALLEL since
3540 the new one still will, but we can't call single_set without
3541 having put NEW_BODY into the insn and the re-recognition won't
3542 hurt in this rare case. */
3543 /* ??? Why this huge if statement - why don't we just rerecognize the
3547 && ((REG_P (SET_SRC (old_set))
3548 && (GET_CODE (new_body) != SET
3549 || !REG_P (SET_SRC (new_body))))
3550 /* If this was a load from or store to memory, compare
3551 the MEM in recog_data.operand to the one in the insn.
3552 If they are not equal, then rerecognize the insn. */
3554 && ((MEM_P (SET_SRC (old_set))
3555 && SET_SRC (old_set) != recog_data.operand[1])
3556 || (MEM_P (SET_DEST (old_set))
3557 && SET_DEST (old_set) != recog_data.operand[0])))
3558 /* If this was an add insn before, rerecognize. */
3559 || GET_CODE (SET_SRC (old_set)) == PLUS))
3561 int new_icode = recog (PATTERN (insn), insn, 0);
3563 INSN_CODE (insn) = new_icode;
3567 /* Restore the old body. If there were any changes to it, we made a copy
3568 of it while the changes were still in place, so we'll correctly return
3569 a modified insn below. */
3572 /* Restore the old body. */
3573 for (i = 0; i < recog_data.n_operands; i++)
3574 /* Restoring a top-level match_parallel would clobber the new_body
3575 we installed in the insn. */
3576 if (recog_data.operand_loc[i] != &PATTERN (insn))
3577 *recog_data.operand_loc[i] = orig_operand[i];
3578 for (i = 0; i < recog_data.n_dups; i++)
3579 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3582 /* Update all elimination pairs to reflect the status after the current
3583 insn. The changes we make were determined by the earlier call to
3584 elimination_effects.
3586 We also detect cases where register elimination cannot be done,
3587 namely, if a register would be both changed and referenced outside a MEM
3588 in the resulting insn since such an insn is often undefined and, even if
3589 not, we cannot know what meaning will be given to it. Note that it is
3590 valid to have a register used in an address in an insn that changes it
3591 (presumably with a pre- or post-increment or decrement).
3593 If anything changes, return nonzero. */
3595 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3597 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3598 ep->can_eliminate = 0;
3600 ep->ref_outside_mem = 0;
3602 if (ep->previous_offset != ep->offset)
3607 /* If we changed something, perform elimination in REG_NOTES. This is
3608 needed even when REPLACE is zero because a REG_DEAD note might refer
3609 to a register that we eliminate and could cause a different number
3610 of spill registers to be needed in the final reload pass than in
3612 if (val && REG_NOTES (insn) != 0)
3614 = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true,
3620 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3621 register allocator. INSN is the instruction we need to examine, we perform
3622 eliminations in its operands and record cases where eliminating a reg with
3623 an invariant equivalence would add extra cost. */
3626 elimination_costs_in_insn (rtx insn)
3628 int icode = recog_memoized (insn);
3629 rtx old_body = PATTERN (insn);
3630 int insn_is_asm = asm_noperands (old_body) >= 0;
3631 rtx old_set = single_set (insn);
3633 rtx orig_operand[MAX_RECOG_OPERANDS];
3634 rtx orig_dup[MAX_RECOG_OPERANDS];
3635 struct elim_table *ep;
3636 rtx plus_src, plus_cst_src;
3639 if (! insn_is_asm && icode < 0)
3641 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3642 || GET_CODE (PATTERN (insn)) == CLOBBER
3643 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3644 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3645 || GET_CODE (PATTERN (insn)) == ASM_INPUT
3646 || DEBUG_INSN_P (insn));
3650 if (old_set != 0 && REG_P (SET_DEST (old_set))
3651 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3653 /* Check for setting an eliminable register. */
3654 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3655 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3659 /* We allow one special case which happens to work on all machines we
3660 currently support: a single set with the source or a REG_EQUAL
3661 note being a PLUS of an eliminable register and a constant. */
3662 plus_src = plus_cst_src = 0;
3664 if (old_set && REG_P (SET_DEST (old_set)))
3667 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3668 plus_src = SET_SRC (old_set);
3669 /* First see if the source is of the form (plus (...) CST). */
3671 && CONST_INT_P (XEXP (plus_src, 1)))
3672 plus_cst_src = plus_src;
3673 else if (REG_P (SET_SRC (old_set))
3676 /* Otherwise, see if we have a REG_EQUAL note of the form
3677 (plus (...) CST). */
3679 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3681 if ((REG_NOTE_KIND (links) == REG_EQUAL
3682 || REG_NOTE_KIND (links) == REG_EQUIV)
3683 && GET_CODE (XEXP (links, 0)) == PLUS
3684 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3686 plus_cst_src = XEXP (links, 0);
3693 /* Determine the effects of this insn on elimination offsets. */
3694 elimination_effects (old_body, VOIDmode);
3696 /* Eliminate all eliminable registers occurring in operands that
3697 can be handled by reload. */
3698 extract_insn (insn);
3699 for (i = 0; i < recog_data.n_dups; i++)
3700 orig_dup[i] = *recog_data.dup_loc[i];
3702 for (i = 0; i < recog_data.n_operands; i++)
3704 orig_operand[i] = recog_data.operand[i];
3706 /* For an asm statement, every operand is eliminable. */
3707 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3709 bool is_set_src, in_plus;
3711 /* Check for setting a register that we know about. */
3712 if (recog_data.operand_type[i] != OP_IN
3713 && REG_P (orig_operand[i]))
3715 /* If we are assigning to a register that can be eliminated, it
3716 must be as part of a PARALLEL, since the code above handles
3717 single SETs. We must indicate that we can no longer
3718 eliminate this reg. */
3719 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3721 if (ep->from_rtx == orig_operand[i])
3722 ep->can_eliminate = 0;
3725 /* Companion to the above plus substitution, we can allow
3726 invariants as the source of a plain move. */
3728 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3730 if (is_set_src && !sets_reg_p)
3731 note_reg_elim_costly (&SET_SRC (old_set), insn);
3733 if (plus_src && sets_reg_p
3734 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3735 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3738 eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3740 is_set_src || in_plus, true);
3741 /* Terminate the search in check_eliminable_occurrences at
3743 *recog_data.operand_loc[i] = 0;
3747 for (i = 0; i < recog_data.n_dups; i++)
3748 *recog_data.dup_loc[i]
3749 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3751 /* If any eliminable remain, they aren't eliminable anymore. */
3752 check_eliminable_occurrences (old_body);
3754 /* Restore the old body. */
3755 for (i = 0; i < recog_data.n_operands; i++)
3756 *recog_data.operand_loc[i] = orig_operand[i];
3757 for (i = 0; i < recog_data.n_dups; i++)
3758 *recog_data.dup_loc[i] = orig_dup[i];
3760 /* Update all elimination pairs to reflect the status after the current
3761 insn. The changes we make were determined by the earlier call to
3762 elimination_effects. */
3764 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3766 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3767 ep->can_eliminate = 0;
3769 ep->ref_outside_mem = 0;
3775 /* Loop through all elimination pairs.
3776 Recalculate the number not at initial offset.
3778 Compute the maximum offset (minimum offset if the stack does not
3779 grow downward) for each elimination pair. */
3782 update_eliminable_offsets (void)
3784 struct elim_table *ep;
3786 num_not_at_initial_offset = 0;
3787 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3789 ep->previous_offset = ep->offset;
3790 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3791 num_not_at_initial_offset++;
3795 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3796 replacement we currently believe is valid, mark it as not eliminable if X
3797 modifies DEST in any way other than by adding a constant integer to it.
3799 If DEST is the frame pointer, we do nothing because we assume that
3800 all assignments to the hard frame pointer are nonlocal gotos and are being
3801 done at a time when they are valid and do not disturb anything else.
3802 Some machines want to eliminate a fake argument pointer with either the
3803 frame or stack pointer. Assignments to the hard frame pointer must not
3804 prevent this elimination.
3806 Called via note_stores from reload before starting its passes to scan
3807 the insns of the function. */
3810 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3814 /* A SUBREG of a hard register here is just changing its mode. We should
3815 not see a SUBREG of an eliminable hard register, but check just in
3817 if (GET_CODE (dest) == SUBREG)
3818 dest = SUBREG_REG (dest);
3820 if (dest == hard_frame_pointer_rtx)
3823 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3824 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3825 && (GET_CODE (x) != SET
3826 || GET_CODE (SET_SRC (x)) != PLUS
3827 || XEXP (SET_SRC (x), 0) != dest
3828 || !CONST_INT_P (XEXP (SET_SRC (x), 1))))
3830 reg_eliminate[i].can_eliminate_previous
3831 = reg_eliminate[i].can_eliminate = 0;
3836 /* Verify that the initial elimination offsets did not change since the
3837 last call to set_initial_elim_offsets. This is used to catch cases
3838 where something illegal happened during reload_as_needed that could
3839 cause incorrect code to be generated if we did not check for it. */
3842 verify_initial_elim_offsets (void)
3846 if (!num_eliminable)
3849 #ifdef ELIMINABLE_REGS
3851 struct elim_table *ep;
3853 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3855 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3856 if (t != ep->initial_offset)
3861 INITIAL_FRAME_POINTER_OFFSET (t);
3862 if (t != reg_eliminate[0].initial_offset)
3869 /* Reset all offsets on eliminable registers to their initial values. */
3872 set_initial_elim_offsets (void)
3874 struct elim_table *ep = reg_eliminate;
3876 #ifdef ELIMINABLE_REGS
3877 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3879 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3880 ep->previous_offset = ep->offset = ep->initial_offset;
3883 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3884 ep->previous_offset = ep->offset = ep->initial_offset;
3887 num_not_at_initial_offset = 0;
3890 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3893 set_initial_eh_label_offset (rtx label)
3895 set_label_offsets (label, NULL_RTX, 1);
3898 /* Initialize the known label offsets.
3899 Set a known offset for each forced label to be at the initial offset
3900 of each elimination. We do this because we assume that all
3901 computed jumps occur from a location where each elimination is
3902 at its initial offset.
3903 For all other labels, show that we don't know the offsets. */
3906 set_initial_label_offsets (void)
3909 memset (offsets_known_at, 0, num_labels);
3911 for (x = forced_labels; x; x = XEXP (x, 1))
3913 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3915 for_each_eh_label (set_initial_eh_label_offset);
3918 /* Set all elimination offsets to the known values for the code label given
3922 set_offsets_for_label (rtx insn)
3925 int label_nr = CODE_LABEL_NUMBER (insn);
3926 struct elim_table *ep;
3928 num_not_at_initial_offset = 0;
3929 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3931 ep->offset = ep->previous_offset
3932 = offsets_at[label_nr - first_label_num][i];
3933 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3934 num_not_at_initial_offset++;
3938 /* See if anything that happened changes which eliminations are valid.
3939 For example, on the SPARC, whether or not the frame pointer can
3940 be eliminated can depend on what registers have been used. We need
3941 not check some conditions again (such as flag_omit_frame_pointer)
3942 since they can't have changed. */
3945 update_eliminables (HARD_REG_SET *pset)
3947 int previous_frame_pointer_needed = frame_pointer_needed;
3948 struct elim_table *ep;
3950 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3951 if ((ep->from == HARD_FRAME_POINTER_REGNUM
3952 && targetm.frame_pointer_required ())
3953 #ifdef ELIMINABLE_REGS
3954 || ! targetm.can_eliminate (ep->from, ep->to)
3957 ep->can_eliminate = 0;
3959 /* Look for the case where we have discovered that we can't replace
3960 register A with register B and that means that we will now be
3961 trying to replace register A with register C. This means we can
3962 no longer replace register C with register B and we need to disable
3963 such an elimination, if it exists. This occurs often with A == ap,
3964 B == sp, and C == fp. */
3966 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3968 struct elim_table *op;
3971 if (! ep->can_eliminate && ep->can_eliminate_previous)
3973 /* Find the current elimination for ep->from, if there is a
3975 for (op = reg_eliminate;
3976 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3977 if (op->from == ep->from && op->can_eliminate)
3983 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3985 for (op = reg_eliminate;
3986 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3987 if (op->from == new_to && op->to == ep->to)
3988 op->can_eliminate = 0;
3992 /* See if any registers that we thought we could eliminate the previous
3993 time are no longer eliminable. If so, something has changed and we
3994 must spill the register. Also, recompute the number of eliminable
3995 registers and see if the frame pointer is needed; it is if there is
3996 no elimination of the frame pointer that we can perform. */
3998 frame_pointer_needed = 1;
3999 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4001 if (ep->can_eliminate
4002 && ep->from == FRAME_POINTER_REGNUM
4003 && ep->to != HARD_FRAME_POINTER_REGNUM
4004 && (! SUPPORTS_STACK_ALIGNMENT
4005 || ! crtl->stack_realign_needed))
4006 frame_pointer_needed = 0;
4008 if (! ep->can_eliminate && ep->can_eliminate_previous)
4010 ep->can_eliminate_previous = 0;
4011 SET_HARD_REG_BIT (*pset, ep->from);
4016 /* If we didn't need a frame pointer last time, but we do now, spill
4017 the hard frame pointer. */
4018 if (frame_pointer_needed && ! previous_frame_pointer_needed)
4019 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
4022 /* Return true if X is used as the target register of an elimination. */
4025 elimination_target_reg_p (rtx x)
4027 struct elim_table *ep;
4029 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4030 if (ep->to_rtx == x && ep->can_eliminate)
4036 /* Initialize the table of registers to eliminate.
4037 Pre-condition: global flag frame_pointer_needed has been set before
4038 calling this function. */
4041 init_elim_table (void)
4043 struct elim_table *ep;
4044 #ifdef ELIMINABLE_REGS
4045 const struct elim_table_1 *ep1;
4049 reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
4053 #ifdef ELIMINABLE_REGS
4054 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
4055 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
4057 ep->from = ep1->from;
4059 ep->can_eliminate = ep->can_eliminate_previous
4060 = (targetm.can_eliminate (ep->from, ep->to)
4061 && ! (ep->to == STACK_POINTER_REGNUM
4062 && frame_pointer_needed
4063 && (! SUPPORTS_STACK_ALIGNMENT
4064 || ! stack_realign_fp)));
4067 reg_eliminate[0].from = reg_eliminate_1[0].from;
4068 reg_eliminate[0].to = reg_eliminate_1[0].to;
4069 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
4070 = ! frame_pointer_needed;
4073 /* Count the number of eliminable registers and build the FROM and TO
4074 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
4075 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
4076 We depend on this. */
4077 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4079 num_eliminable += ep->can_eliminate;
4080 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
4081 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
4085 /* Find all the pseudo registers that didn't get hard regs
4086 but do have known equivalent constants or memory slots.
4087 These include parameters (known equivalent to parameter slots)
4088 and cse'd or loop-moved constant memory addresses.
4090 Record constant equivalents in reg_equiv_constant
4091 so they will be substituted by find_reloads.
4092 Record memory equivalents in reg_mem_equiv so they can
4093 be substituted eventually by altering the REG-rtx's. */
4096 init_eliminable_invariants (rtx first, bool do_subregs)
4101 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
4102 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
4103 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
4104 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
4105 reg_equiv_address = XCNEWVEC (rtx, max_regno);
4107 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
4109 reg_max_ref_width = NULL;
4111 num_eliminable_invariants = 0;
4113 first_label_num = get_first_label_num ();
4114 num_labels = max_label_num () - first_label_num;
4116 /* Allocate the tables used to store offset information at labels. */
4117 offsets_known_at = XNEWVEC (char, num_labels);
4118 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
4120 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4121 to. If DO_SUBREGS is true, also find all paradoxical subregs and
4122 find largest such for each pseudo. FIRST is the head of the insn
4125 for (insn = first; insn; insn = NEXT_INSN (insn))
4127 rtx set = single_set (insn);
4129 /* We may introduce USEs that we want to remove at the end, so
4130 we'll mark them with QImode. Make sure there are no
4131 previously-marked insns left by say regmove. */
4132 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
4133 && GET_MODE (insn) != VOIDmode)
4134 PUT_MODE (insn, VOIDmode);
4136 if (do_subregs && NONDEBUG_INSN_P (insn))
4137 scan_paradoxical_subregs (PATTERN (insn));
4139 if (set != 0 && REG_P (SET_DEST (set)))
4141 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
4147 i = REGNO (SET_DEST (set));
4150 if (i <= LAST_VIRTUAL_REGISTER)
4153 /* If flag_pic and we have constant, verify it's legitimate. */
4155 || !flag_pic || LEGITIMATE_PIC_OPERAND_P (x))
4157 /* It can happen that a REG_EQUIV note contains a MEM
4158 that is not a legitimate memory operand. As later
4159 stages of reload assume that all addresses found
4160 in the reg_equiv_* arrays were originally legitimate,
4161 we ignore such REG_EQUIV notes. */
4162 if (memory_operand (x, VOIDmode))
4164 /* Always unshare the equivalence, so we can
4165 substitute into this insn without touching the
4167 reg_equiv_memory_loc[i] = copy_rtx (x);
4169 else if (function_invariant_p (x))
4171 if (GET_CODE (x) == PLUS)
4173 /* This is PLUS of frame pointer and a constant,
4174 and might be shared. Unshare it. */
4175 reg_equiv_invariant[i] = copy_rtx (x);
4176 num_eliminable_invariants++;
4178 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4180 reg_equiv_invariant[i] = x;
4181 num_eliminable_invariants++;
4183 else if (LEGITIMATE_CONSTANT_P (x))
4184 reg_equiv_constant[i] = x;
4187 reg_equiv_memory_loc[i]
4188 = force_const_mem (GET_MODE (SET_DEST (set)), x);
4189 if (! reg_equiv_memory_loc[i])
4190 reg_equiv_init[i] = NULL_RTX;
4195 reg_equiv_init[i] = NULL_RTX;
4200 reg_equiv_init[i] = NULL_RTX;
4205 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4206 if (reg_equiv_init[i])
4208 fprintf (dump_file, "init_insns for %u: ", i);
4209 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
4210 fprintf (dump_file, "\n");
4214 /* Indicate that we no longer have known memory locations or constants.
4215 Free all data involved in tracking these. */
4218 free_reg_equiv (void)
4222 if (reg_equiv_constant)
4223 free (reg_equiv_constant);
4224 if (reg_equiv_invariant)
4225 free (reg_equiv_invariant);
4226 reg_equiv_constant = 0;
4227 reg_equiv_invariant = 0;
4228 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
4229 reg_equiv_memory_loc = 0;
4231 if (offsets_known_at)
4232 free (offsets_known_at);
4236 offsets_known_at = 0;
4238 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4239 if (reg_equiv_alt_mem_list[i])
4240 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
4241 free (reg_equiv_alt_mem_list);
4243 free (reg_equiv_mem);
4244 free (reg_equiv_address);
4247 /* Kick all pseudos out of hard register REGNO.
4249 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4250 because we found we can't eliminate some register. In the case, no pseudos
4251 are allowed to be in the register, even if they are only in a block that
4252 doesn't require spill registers, unlike the case when we are spilling this
4253 hard reg to produce another spill register.
4255 Return nonzero if any pseudos needed to be kicked out. */
4258 spill_hard_reg (unsigned int regno, int cant_eliminate)
4264 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
4265 df_set_regs_ever_live (regno, true);
4268 /* Spill every pseudo reg that was allocated to this reg
4269 or to something that overlaps this reg. */
4271 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4272 if (reg_renumber[i] >= 0
4273 && (unsigned int) reg_renumber[i] <= regno
4274 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
4275 SET_REGNO_REG_SET (&spilled_pseudos, i);
4278 /* After find_reload_regs has been run for all insn that need reloads,
4279 and/or spill_hard_regs was called, this function is used to actually
4280 spill pseudo registers and try to reallocate them. It also sets up the
4281 spill_regs array for use by choose_reload_regs. */
4284 finish_spills (int global)
4286 struct insn_chain *chain;
4287 int something_changed = 0;
4289 reg_set_iterator rsi;
4291 /* Build the spill_regs array for the function. */
4292 /* If there are some registers still to eliminate and one of the spill regs
4293 wasn't ever used before, additional stack space may have to be
4294 allocated to store this register. Thus, we may have changed the offset
4295 between the stack and frame pointers, so mark that something has changed.
4297 One might think that we need only set VAL to 1 if this is a call-used
4298 register. However, the set of registers that must be saved by the
4299 prologue is not identical to the call-used set. For example, the
4300 register used by the call insn for the return PC is a call-used register,
4301 but must be saved by the prologue. */
4304 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4305 if (TEST_HARD_REG_BIT (used_spill_regs, i))
4307 spill_reg_order[i] = n_spills;
4308 spill_regs[n_spills++] = i;
4309 if (num_eliminable && ! df_regs_ever_live_p (i))
4310 something_changed = 1;
4311 df_set_regs_ever_live (i, true);
4314 spill_reg_order[i] = -1;
4316 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
4317 if (! ira_conflicts_p || reg_renumber[i] >= 0)
4319 /* Record the current hard register the pseudo is allocated to
4320 in pseudo_previous_regs so we avoid reallocating it to the
4321 same hard reg in a later pass. */
4322 gcc_assert (reg_renumber[i] >= 0);
4324 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
4325 /* Mark it as no longer having a hard register home. */
4326 reg_renumber[i] = -1;
4327 if (ira_conflicts_p)
4328 /* Inform IRA about the change. */
4329 ira_mark_allocation_change (i);
4330 /* We will need to scan everything again. */
4331 something_changed = 1;
4334 /* Retry global register allocation if possible. */
4335 if (global && ira_conflicts_p)
4339 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
4340 /* For every insn that needs reloads, set the registers used as spill
4341 regs in pseudo_forbidden_regs for every pseudo live across the
4343 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
4345 EXECUTE_IF_SET_IN_REG_SET
4346 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
4348 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4349 chain->used_spill_regs);
4351 EXECUTE_IF_SET_IN_REG_SET
4352 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
4354 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4355 chain->used_spill_regs);
4359 /* Retry allocating the pseudos spilled in IRA and the
4360 reload. For each reg, merge the various reg sets that
4361 indicate which hard regs can't be used, and call
4362 ira_reassign_pseudos. */
4363 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
4364 if (reg_old_renumber[i] != reg_renumber[i])
4366 if (reg_renumber[i] < 0)
4367 temp_pseudo_reg_arr[n++] = i;
4369 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4371 if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
4372 bad_spill_regs_global,
4373 pseudo_forbidden_regs, pseudo_previous_regs,
4375 something_changed = 1;
4377 /* Fix up the register information in the insn chain.
4378 This involves deleting those of the spilled pseudos which did not get
4379 a new hard register home from the live_{before,after} sets. */
4380 for (chain = reload_insn_chain; chain; chain = chain->next)
4382 HARD_REG_SET used_by_pseudos;
4383 HARD_REG_SET used_by_pseudos2;
4385 if (! ira_conflicts_p)
4387 /* Don't do it for IRA because IRA and the reload still can
4388 assign hard registers to the spilled pseudos on next
4389 reload iterations. */
4390 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
4391 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
4393 /* Mark any unallocated hard regs as available for spills. That
4394 makes inheritance work somewhat better. */
4395 if (chain->need_reload)
4397 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
4398 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
4399 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
4401 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
4402 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
4403 /* Value of chain->used_spill_regs from previous iteration
4404 may be not included in the value calculated here because
4405 of possible removing caller-saves insns (see function
4406 delete_caller_save_insns. */
4407 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
4408 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4412 CLEAR_REG_SET (&changed_allocation_pseudos);
4413 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4414 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4416 int regno = reg_renumber[i];
4417 if (reg_old_renumber[i] == regno)
4420 SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4422 alter_reg (i, reg_old_renumber[i], false);
4423 reg_old_renumber[i] = regno;
4427 fprintf (dump_file, " Register %d now on stack.\n\n", i);
4429 fprintf (dump_file, " Register %d now in %d.\n\n",
4430 i, reg_renumber[i]);
4434 return something_changed;
4437 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4440 scan_paradoxical_subregs (rtx x)
4444 enum rtx_code code = GET_CODE (x);
4455 case CONST_VECTOR: /* shouldn't happen, but just in case. */
4463 if (REG_P (SUBREG_REG (x))
4464 && (GET_MODE_SIZE (GET_MODE (x))
4465 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
4467 reg_max_ref_width[REGNO (SUBREG_REG (x))]
4468 = GET_MODE_SIZE (GET_MODE (x));
4469 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
4477 fmt = GET_RTX_FORMAT (code);
4478 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4481 scan_paradoxical_subregs (XEXP (x, i));
4482 else if (fmt[i] == 'E')
4485 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4486 scan_paradoxical_subregs (XVECEXP (x, i, j));
4491 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4492 examine all of the reload insns between PREV and NEXT exclusive, and
4493 annotate all that may trap. */
4496 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
4498 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4501 if (!insn_could_throw_p (insn))
4502 remove_note (insn, note);
4503 copy_reg_eh_region_note_forward (note, NEXT_INSN (prev), next);
4506 /* Reload pseudo-registers into hard regs around each insn as needed.
4507 Additional register load insns are output before the insn that needs it
4508 and perhaps store insns after insns that modify the reloaded pseudo reg.
4510 reg_last_reload_reg and reg_reloaded_contents keep track of
4511 which registers are already available in reload registers.
4512 We update these for the reloads that we perform,
4513 as the insns are scanned. */
4516 reload_as_needed (int live_known)
4518 struct insn_chain *chain;
4519 #if defined (AUTO_INC_DEC)
4524 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4525 memset (spill_reg_store, 0, sizeof spill_reg_store);
4526 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4527 INIT_REG_SET (®_has_output_reload);
4528 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4529 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4531 set_initial_elim_offsets ();
4533 for (chain = reload_insn_chain; chain; chain = chain->next)
4536 rtx insn = chain->insn;
4537 rtx old_next = NEXT_INSN (insn);
4539 rtx old_prev = PREV_INSN (insn);
4542 /* If we pass a label, copy the offsets from the label information
4543 into the current offsets of each elimination. */
4545 set_offsets_for_label (insn);
4547 else if (INSN_P (insn))
4549 regset_head regs_to_forget;
4550 INIT_REG_SET (®s_to_forget);
4551 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4553 /* If this is a USE and CLOBBER of a MEM, ensure that any
4554 references to eliminable registers have been removed. */
4556 if ((GET_CODE (PATTERN (insn)) == USE
4557 || GET_CODE (PATTERN (insn)) == CLOBBER)
4558 && MEM_P (XEXP (PATTERN (insn), 0)))
4559 XEXP (XEXP (PATTERN (insn), 0), 0)
4560 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4561 GET_MODE (XEXP (PATTERN (insn), 0)),
4564 /* If we need to do register elimination processing, do so.
4565 This might delete the insn, in which case we are done. */
4566 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4568 eliminate_regs_in_insn (insn, 1);
4571 update_eliminable_offsets ();
4572 CLEAR_REG_SET (®s_to_forget);
4577 /* If need_elim is nonzero but need_reload is zero, one might think
4578 that we could simply set n_reloads to 0. However, find_reloads
4579 could have done some manipulation of the insn (such as swapping
4580 commutative operands), and these manipulations are lost during
4581 the first pass for every insn that needs register elimination.
4582 So the actions of find_reloads must be redone here. */
4584 if (! chain->need_elim && ! chain->need_reload
4585 && ! chain->need_operand_change)
4587 /* First find the pseudo regs that must be reloaded for this insn.
4588 This info is returned in the tables reload_... (see reload.h).
4589 Also modify the body of INSN by substituting RELOAD
4590 rtx's for those pseudo regs. */
4593 CLEAR_REG_SET (®_has_output_reload);
4594 CLEAR_HARD_REG_SET (reg_is_output_reload);
4596 find_reloads (insn, 1, spill_indirect_levels, live_known,
4602 rtx next = NEXT_INSN (insn);
4605 prev = PREV_INSN (insn);
4607 /* Now compute which reload regs to reload them into. Perhaps
4608 reusing reload regs from previous insns, or else output
4609 load insns to reload them. Maybe output store insns too.
4610 Record the choices of reload reg in reload_reg_rtx. */
4611 choose_reload_regs (chain);
4613 /* Merge any reloads that we didn't combine for fear of
4614 increasing the number of spill registers needed but now
4615 discover can be safely merged. */
4616 if (targetm.small_register_classes_for_mode_p (VOIDmode))
4617 merge_assigned_reloads (insn);
4619 /* Generate the insns to reload operands into or out of
4620 their reload regs. */
4621 emit_reload_insns (chain);
4623 /* Substitute the chosen reload regs from reload_reg_rtx
4624 into the insn's body (or perhaps into the bodies of other
4625 load and store insn that we just made for reloading
4626 and that we moved the structure into). */
4627 subst_reloads (insn);
4629 /* Adjust the exception region notes for loads and stores. */
4630 if (cfun->can_throw_non_call_exceptions && !CALL_P (insn))
4631 fixup_eh_region_note (insn, prev, next);
4633 /* If this was an ASM, make sure that all the reload insns
4634 we have generated are valid. If not, give an error
4636 if (asm_noperands (PATTERN (insn)) >= 0)
4637 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4638 if (p != insn && INSN_P (p)
4639 && GET_CODE (PATTERN (p)) != USE
4640 && (recog_memoized (p) < 0
4641 || (extract_insn (p), ! constrain_operands (1))))
4643 error_for_asm (insn,
4644 "%<asm%> operand requires "
4645 "impossible reload");
4650 if (num_eliminable && chain->need_elim)
4651 update_eliminable_offsets ();
4653 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4654 is no longer validly lying around to save a future reload.
4655 Note that this does not detect pseudos that were reloaded
4656 for this insn in order to be stored in
4657 (obeying register constraints). That is correct; such reload
4658 registers ARE still valid. */
4659 forget_marked_reloads (®s_to_forget);
4660 CLEAR_REG_SET (®s_to_forget);
4662 /* There may have been CLOBBER insns placed after INSN. So scan
4663 between INSN and NEXT and use them to forget old reloads. */
4664 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4665 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4666 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4669 /* Likewise for regs altered by auto-increment in this insn.
4670 REG_INC notes have been changed by reloading:
4671 find_reloads_address_1 records substitutions for them,
4672 which have been performed by subst_reloads above. */
4673 for (i = n_reloads - 1; i >= 0; i--)
4675 rtx in_reg = rld[i].in_reg;
4678 enum rtx_code code = GET_CODE (in_reg);
4679 /* PRE_INC / PRE_DEC will have the reload register ending up
4680 with the same value as the stack slot, but that doesn't
4681 hold true for POST_INC / POST_DEC. Either we have to
4682 convert the memory access to a true POST_INC / POST_DEC,
4683 or we can't use the reload register for inheritance. */
4684 if ((code == POST_INC || code == POST_DEC)
4685 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4686 REGNO (rld[i].reg_rtx))
4687 /* Make sure it is the inc/dec pseudo, and not
4688 some other (e.g. output operand) pseudo. */
4689 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4690 == REGNO (XEXP (in_reg, 0))))
4693 rtx reload_reg = rld[i].reg_rtx;
4694 enum machine_mode mode = GET_MODE (reload_reg);
4698 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4700 /* We really want to ignore REG_INC notes here, so
4701 use PATTERN (p) as argument to reg_set_p . */
4702 if (reg_set_p (reload_reg, PATTERN (p)))
4704 n = count_occurrences (PATTERN (p), reload_reg, 0);
4710 = gen_rtx_fmt_e (code, mode, reload_reg);
4712 validate_replace_rtx_group (reload_reg,
4714 n = verify_changes (0);
4716 /* We must also verify that the constraints
4717 are met after the replacement. Make sure
4718 extract_insn is only called for an insn
4719 where the replacements were found to be
4724 n = constrain_operands (1);
4727 /* If the constraints were not met, then
4728 undo the replacement, else confirm it. */
4732 confirm_change_group ();
4738 add_reg_note (p, REG_INC, reload_reg);
4739 /* Mark this as having an output reload so that the
4740 REG_INC processing code below won't invalidate
4741 the reload for inheritance. */
4742 SET_HARD_REG_BIT (reg_is_output_reload,
4743 REGNO (reload_reg));
4744 SET_REGNO_REG_SET (®_has_output_reload,
4745 REGNO (XEXP (in_reg, 0)));
4748 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4751 else if ((code == PRE_INC || code == PRE_DEC)
4752 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4753 REGNO (rld[i].reg_rtx))
4754 /* Make sure it is the inc/dec pseudo, and not
4755 some other (e.g. output operand) pseudo. */
4756 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4757 == REGNO (XEXP (in_reg, 0))))
4759 SET_HARD_REG_BIT (reg_is_output_reload,
4760 REGNO (rld[i].reg_rtx));
4761 SET_REGNO_REG_SET (®_has_output_reload,
4762 REGNO (XEXP (in_reg, 0)));
4764 else if (code == PRE_INC || code == PRE_DEC
4765 || code == POST_INC || code == POST_DEC)
4767 int in_regno = REGNO (XEXP (in_reg, 0));
4769 if (reg_last_reload_reg[in_regno] != NULL_RTX)
4772 bool forget_p = true;
4774 in_hard_regno = REGNO (reg_last_reload_reg[in_regno]);
4775 if (TEST_HARD_REG_BIT (reg_reloaded_valid,
4778 for (x = old_prev ? NEXT_INSN (old_prev) : insn;
4781 if (x == reg_reloaded_insn[in_hard_regno])
4787 /* If for some reasons, we didn't set up
4788 reg_last_reload_reg in this insn,
4789 invalidate inheritance from previous
4790 insns for the incremented/decremented
4791 register. Such registers will be not in
4792 reg_has_output_reload. Invalidate it
4793 also if the corresponding element in
4794 reg_reloaded_insn is also
4797 forget_old_reloads_1 (XEXP (in_reg, 0),
4803 /* If a pseudo that got a hard register is auto-incremented,
4804 we must purge records of copying it into pseudos without
4806 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4807 if (REG_NOTE_KIND (x) == REG_INC)
4809 /* See if this pseudo reg was reloaded in this insn.
4810 If so, its last-reload info is still valid
4811 because it is based on this insn's reload. */
4812 for (i = 0; i < n_reloads; i++)
4813 if (rld[i].out == XEXP (x, 0))
4817 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4821 /* A reload reg's contents are unknown after a label. */
4823 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4825 /* Don't assume a reload reg is still good after a call insn
4826 if it is a call-used reg, or if it contains a value that will
4827 be partially clobbered by the call. */
4828 else if (CALL_P (insn))
4830 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4831 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4836 free (reg_last_reload_reg);
4837 CLEAR_REG_SET (®_has_output_reload);
4840 /* Discard all record of any value reloaded from X,
4841 or reloaded in X from someplace else;
4842 unless X is an output reload reg of the current insn.
4844 X may be a hard reg (the reload reg)
4845 or it may be a pseudo reg that was reloaded from.
4847 When DATA is non-NULL just mark the registers in regset
4848 to be forgotten later. */
4851 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4856 regset regs = (regset) data;
4858 /* note_stores does give us subregs of hard regs,
4859 subreg_regno_offset requires a hard reg. */
4860 while (GET_CODE (x) == SUBREG)
4862 /* We ignore the subreg offset when calculating the regno,
4863 because we are using the entire underlying hard register
4873 if (regno >= FIRST_PSEUDO_REGISTER)
4879 nr = hard_regno_nregs[regno][GET_MODE (x)];
4880 /* Storing into a spilled-reg invalidates its contents.
4881 This can happen if a block-local pseudo is allocated to that reg
4882 and it wasn't spilled because this block's total need is 0.
4883 Then some insn might have an optional reload and use this reg. */
4885 for (i = 0; i < nr; i++)
4886 /* But don't do this if the reg actually serves as an output
4887 reload reg in the current instruction. */
4889 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4891 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4892 spill_reg_store[regno + i] = 0;
4898 SET_REGNO_REG_SET (regs, regno + nr);
4901 /* Since value of X has changed,
4902 forget any value previously copied from it. */
4905 /* But don't forget a copy if this is the output reload
4906 that establishes the copy's validity. */
4908 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4909 reg_last_reload_reg[regno + nr] = 0;
4913 /* Forget the reloads marked in regset by previous function. */
4915 forget_marked_reloads (regset regs)
4918 reg_set_iterator rsi;
4919 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4921 if (reg < FIRST_PSEUDO_REGISTER
4922 /* But don't do this if the reg actually serves as an output
4923 reload reg in the current instruction. */
4925 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4927 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4928 spill_reg_store[reg] = 0;
4931 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4932 reg_last_reload_reg[reg] = 0;
4936 /* The following HARD_REG_SETs indicate when each hard register is
4937 used for a reload of various parts of the current insn. */
4939 /* If reg is unavailable for all reloads. */
4940 static HARD_REG_SET reload_reg_unavailable;
4941 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4942 static HARD_REG_SET reload_reg_used;
4943 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4944 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4945 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4946 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4947 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4948 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4949 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4950 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4951 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4952 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4953 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4954 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4955 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4956 static HARD_REG_SET reload_reg_used_in_op_addr;
4957 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4958 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4959 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4960 static HARD_REG_SET reload_reg_used_in_insn;
4961 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4962 static HARD_REG_SET reload_reg_used_in_other_addr;
4964 /* If reg is in use as a reload reg for any sort of reload. */
4965 static HARD_REG_SET reload_reg_used_at_all;
4967 /* If reg is use as an inherited reload. We just mark the first register
4969 static HARD_REG_SET reload_reg_used_for_inherit;
4971 /* Records which hard regs are used in any way, either as explicit use or
4972 by being allocated to a pseudo during any point of the current insn. */
4973 static HARD_REG_SET reg_used_in_insn;
4975 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4976 TYPE. MODE is used to indicate how many consecutive regs are
4980 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4981 enum machine_mode mode)
4983 unsigned int nregs = hard_regno_nregs[regno][mode];
4986 for (i = regno; i < nregs + regno; i++)
4991 SET_HARD_REG_BIT (reload_reg_used, i);
4994 case RELOAD_FOR_INPUT_ADDRESS:
4995 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4998 case RELOAD_FOR_INPADDR_ADDRESS:
4999 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
5002 case RELOAD_FOR_OUTPUT_ADDRESS:
5003 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
5006 case RELOAD_FOR_OUTADDR_ADDRESS:
5007 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
5010 case RELOAD_FOR_OPERAND_ADDRESS:
5011 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
5014 case RELOAD_FOR_OPADDR_ADDR:
5015 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
5018 case RELOAD_FOR_OTHER_ADDRESS:
5019 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
5022 case RELOAD_FOR_INPUT:
5023 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
5026 case RELOAD_FOR_OUTPUT:
5027 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
5030 case RELOAD_FOR_INSN:
5031 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
5035 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
5039 /* Similarly, but show REGNO is no longer in use for a reload. */
5042 clear_reload_reg_in_use (unsigned int regno, int opnum,
5043 enum reload_type type, enum machine_mode mode)
5045 unsigned int nregs = hard_regno_nregs[regno][mode];
5046 unsigned int start_regno, end_regno, r;
5048 /* A complication is that for some reload types, inheritance might
5049 allow multiple reloads of the same types to share a reload register.
5050 We set check_opnum if we have to check only reloads with the same
5051 operand number, and check_any if we have to check all reloads. */
5052 int check_opnum = 0;
5054 HARD_REG_SET *used_in_set;
5059 used_in_set = &reload_reg_used;
5062 case RELOAD_FOR_INPUT_ADDRESS:
5063 used_in_set = &reload_reg_used_in_input_addr[opnum];
5066 case RELOAD_FOR_INPADDR_ADDRESS:
5068 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
5071 case RELOAD_FOR_OUTPUT_ADDRESS:
5072 used_in_set = &reload_reg_used_in_output_addr[opnum];
5075 case RELOAD_FOR_OUTADDR_ADDRESS:
5077 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
5080 case RELOAD_FOR_OPERAND_ADDRESS:
5081 used_in_set = &reload_reg_used_in_op_addr;
5084 case RELOAD_FOR_OPADDR_ADDR:
5086 used_in_set = &reload_reg_used_in_op_addr_reload;
5089 case RELOAD_FOR_OTHER_ADDRESS:
5090 used_in_set = &reload_reg_used_in_other_addr;
5094 case RELOAD_FOR_INPUT:
5095 used_in_set = &reload_reg_used_in_input[opnum];
5098 case RELOAD_FOR_OUTPUT:
5099 used_in_set = &reload_reg_used_in_output[opnum];
5102 case RELOAD_FOR_INSN:
5103 used_in_set = &reload_reg_used_in_insn;
5108 /* We resolve conflicts with remaining reloads of the same type by
5109 excluding the intervals of reload registers by them from the
5110 interval of freed reload registers. Since we only keep track of
5111 one set of interval bounds, we might have to exclude somewhat
5112 more than what would be necessary if we used a HARD_REG_SET here.
5113 But this should only happen very infrequently, so there should
5114 be no reason to worry about it. */
5116 start_regno = regno;
5117 end_regno = regno + nregs;
5118 if (check_opnum || check_any)
5120 for (i = n_reloads - 1; i >= 0; i--)
5122 if (rld[i].when_needed == type
5123 && (check_any || rld[i].opnum == opnum)
5126 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
5127 unsigned int conflict_end
5128 = end_hard_regno (rld[i].mode, conflict_start);
5130 /* If there is an overlap with the first to-be-freed register,
5131 adjust the interval start. */
5132 if (conflict_start <= start_regno && conflict_end > start_regno)
5133 start_regno = conflict_end;
5134 /* Otherwise, if there is a conflict with one of the other
5135 to-be-freed registers, adjust the interval end. */
5136 if (conflict_start > start_regno && conflict_start < end_regno)
5137 end_regno = conflict_start;
5142 for (r = start_regno; r < end_regno; r++)
5143 CLEAR_HARD_REG_BIT (*used_in_set, r);
5146 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5147 specified by OPNUM and TYPE. */
5150 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
5154 /* In use for a RELOAD_OTHER means it's not available for anything. */
5155 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
5156 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5162 /* In use for anything means we can't use it for RELOAD_OTHER. */
5163 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
5164 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5165 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5166 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5169 for (i = 0; i < reload_n_operands; i++)
5170 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5171 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5172 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5173 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5174 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5175 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5180 case RELOAD_FOR_INPUT:
5181 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5182 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
5185 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5188 /* If it is used for some other input, can't use it. */
5189 for (i = 0; i < reload_n_operands; i++)
5190 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5193 /* If it is used in a later operand's address, can't use it. */
5194 for (i = opnum + 1; i < reload_n_operands; i++)
5195 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5196 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5201 case RELOAD_FOR_INPUT_ADDRESS:
5202 /* Can't use a register if it is used for an input address for this
5203 operand or used as an input in an earlier one. */
5204 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
5205 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5208 for (i = 0; i < opnum; i++)
5209 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5214 case RELOAD_FOR_INPADDR_ADDRESS:
5215 /* Can't use a register if it is used for an input address
5216 for this operand or used as an input in an earlier
5218 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5221 for (i = 0; i < opnum; i++)
5222 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5227 case RELOAD_FOR_OUTPUT_ADDRESS:
5228 /* Can't use a register if it is used for an output address for this
5229 operand or used as an output in this or a later operand. Note
5230 that multiple output operands are emitted in reverse order, so
5231 the conflicting ones are those with lower indices. */
5232 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
5235 for (i = 0; i <= opnum; i++)
5236 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5241 case RELOAD_FOR_OUTADDR_ADDRESS:
5242 /* Can't use a register if it is used for an output address
5243 for this operand or used as an output in this or a
5244 later operand. Note that multiple output operands are
5245 emitted in reverse order, so the conflicting ones are
5246 those with lower indices. */
5247 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5250 for (i = 0; i <= opnum; i++)
5251 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5256 case RELOAD_FOR_OPERAND_ADDRESS:
5257 for (i = 0; i < reload_n_operands; i++)
5258 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5261 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5262 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5264 case RELOAD_FOR_OPADDR_ADDR:
5265 for (i = 0; i < reload_n_operands; i++)
5266 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5269 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
5271 case RELOAD_FOR_OUTPUT:
5272 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5273 outputs, or an operand address for this or an earlier output.
5274 Note that multiple output operands are emitted in reverse order,
5275 so the conflicting ones are those with higher indices. */
5276 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5279 for (i = 0; i < reload_n_operands; i++)
5280 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5283 for (i = opnum; i < reload_n_operands; i++)
5284 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5285 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5290 case RELOAD_FOR_INSN:
5291 for (i = 0; i < reload_n_operands; i++)
5292 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5293 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5296 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5297 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5299 case RELOAD_FOR_OTHER_ADDRESS:
5300 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
5307 /* Return 1 if the value in reload reg REGNO, as used by a reload
5308 needed for the part of the insn specified by OPNUM and TYPE,
5309 is still available in REGNO at the end of the insn.
5311 We can assume that the reload reg was already tested for availability
5312 at the time it is needed, and we should not check this again,
5313 in case the reg has already been marked in use. */
5316 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
5323 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5324 its value must reach the end. */
5327 /* If this use is for part of the insn,
5328 its value reaches if no subsequent part uses the same register.
5329 Just like the above function, don't try to do this with lots
5332 case RELOAD_FOR_OTHER_ADDRESS:
5333 /* Here we check for everything else, since these don't conflict
5334 with anything else and everything comes later. */
5336 for (i = 0; i < reload_n_operands; i++)
5337 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5338 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5339 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
5340 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5341 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5342 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5345 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5346 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5347 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5348 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
5350 case RELOAD_FOR_INPUT_ADDRESS:
5351 case RELOAD_FOR_INPADDR_ADDRESS:
5352 /* Similar, except that we check only for this and subsequent inputs
5353 and the address of only subsequent inputs and we do not need
5354 to check for RELOAD_OTHER objects since they are known not to
5357 for (i = opnum; i < reload_n_operands; i++)
5358 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5361 for (i = opnum + 1; i < reload_n_operands; i++)
5362 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5363 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5366 for (i = 0; i < reload_n_operands; i++)
5367 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5368 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5369 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5372 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5375 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5376 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5377 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5379 case RELOAD_FOR_INPUT:
5380 /* Similar to input address, except we start at the next operand for
5381 both input and input address and we do not check for
5382 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5385 for (i = opnum + 1; i < reload_n_operands; i++)
5386 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5387 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5388 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5391 /* ... fall through ... */
5393 case RELOAD_FOR_OPERAND_ADDRESS:
5394 /* Check outputs and their addresses. */
5396 for (i = 0; i < reload_n_operands; i++)
5397 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5398 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5399 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5402 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5404 case RELOAD_FOR_OPADDR_ADDR:
5405 for (i = 0; i < reload_n_operands; i++)
5406 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5407 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5408 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5411 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5412 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5413 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5415 case RELOAD_FOR_INSN:
5416 /* These conflict with other outputs with RELOAD_OTHER. So
5417 we need only check for output addresses. */
5419 opnum = reload_n_operands;
5421 /* ... fall through ... */
5423 case RELOAD_FOR_OUTPUT:
5424 case RELOAD_FOR_OUTPUT_ADDRESS:
5425 case RELOAD_FOR_OUTADDR_ADDRESS:
5426 /* We already know these can't conflict with a later output. So the
5427 only thing to check are later output addresses.
5428 Note that multiple output operands are emitted in reverse order,
5429 so the conflicting ones are those with lower indices. */
5430 for (i = 0; i < opnum; i++)
5431 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5432 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5442 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5443 every register in the range [REGNO, REGNO + NREGS). */
5446 reload_regs_reach_end_p (unsigned int regno, int nregs,
5447 int opnum, enum reload_type type)
5451 for (i = 0; i < nregs; i++)
5452 if (!reload_reg_reaches_end_p (regno + i, opnum, type))
5458 /* Returns whether R1 and R2 are uniquely chained: the value of one
5459 is used by the other, and that value is not used by any other
5460 reload for this insn. This is used to partially undo the decision
5461 made in find_reloads when in the case of multiple
5462 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5463 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5464 reloads. This code tries to avoid the conflict created by that
5465 change. It might be cleaner to explicitly keep track of which
5466 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5467 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5468 this after the fact. */
5470 reloads_unique_chain_p (int r1, int r2)
5474 /* We only check input reloads. */
5475 if (! rld[r1].in || ! rld[r2].in)
5478 /* Avoid anything with output reloads. */
5479 if (rld[r1].out || rld[r2].out)
5482 /* "chained" means one reload is a component of the other reload,
5483 not the same as the other reload. */
5484 if (rld[r1].opnum != rld[r2].opnum
5485 || rtx_equal_p (rld[r1].in, rld[r2].in)
5486 || rld[r1].optional || rld[r2].optional
5487 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5488 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5491 for (i = 0; i < n_reloads; i ++)
5492 /* Look for input reloads that aren't our two */
5493 if (i != r1 && i != r2 && rld[i].in)
5495 /* If our reload is mentioned at all, it isn't a simple chain. */
5496 if (reg_mentioned_p (rld[r1].in, rld[i].in))
5502 /* The recursive function change all occurrences of WHAT in *WHERE
5505 substitute (rtx *where, const_rtx what, rtx repl)
5514 if (*where == what || rtx_equal_p (*where, what))
5516 /* Record the location of the changed rtx. */
5517 VEC_safe_push (rtx_p, heap, substitute_stack, where);
5522 code = GET_CODE (*where);
5523 fmt = GET_RTX_FORMAT (code);
5524 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5530 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5531 substitute (&XVECEXP (*where, i, j), what, repl);
5533 else if (fmt[i] == 'e')
5534 substitute (&XEXP (*where, i), what, repl);
5538 /* The function returns TRUE if chain of reload R1 and R2 (in any
5539 order) can be evaluated without usage of intermediate register for
5540 the reload containing another reload. It is important to see
5541 gen_reload to understand what the function is trying to do. As an
5542 example, let us have reload chain
5545 r1: <something> + const
5547 and reload R2 got reload reg HR. The function returns true if
5548 there is a correct insn HR = HR + <something>. Otherwise,
5549 gen_reload will use intermediate register (and this is the reload
5550 reg for R1) to reload <something>.
5552 We need this function to find a conflict for chain reloads. In our
5553 example, if HR = HR + <something> is incorrect insn, then we cannot
5554 use HR as a reload register for R2. If we do use it then we get a
5563 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5565 /* Assume other cases in gen_reload are not possible for
5566 chain reloads or do need an intermediate hard registers. */
5569 rtx out, in, tem, insn;
5570 rtx last = get_last_insn ();
5572 /* Make r2 a component of r1. */
5573 if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5579 gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5580 regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5581 gcc_assert (regno >= 0);
5582 out = gen_rtx_REG (rld[r1].mode, regno);
5584 substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5586 /* If IN is a paradoxical SUBREG, remove it and try to put the
5587 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5588 if (GET_CODE (in) == SUBREG
5589 && (GET_MODE_SIZE (GET_MODE (in))
5590 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
5591 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
5592 in = SUBREG_REG (in), out = tem;
5594 if (GET_CODE (in) == PLUS
5595 && (REG_P (XEXP (in, 0))
5596 || GET_CODE (XEXP (in, 0)) == SUBREG
5597 || MEM_P (XEXP (in, 0)))
5598 && (REG_P (XEXP (in, 1))
5599 || GET_CODE (XEXP (in, 1)) == SUBREG
5600 || CONSTANT_P (XEXP (in, 1))
5601 || MEM_P (XEXP (in, 1))))
5603 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
5604 code = recog_memoized (insn);
5609 extract_insn (insn);
5610 /* We want constrain operands to treat this insn strictly in
5611 its validity determination, i.e., the way it would after
5612 reload has completed. */
5613 result = constrain_operands (1);
5616 delete_insns_since (last);
5619 /* Restore the original value at each changed address within R1. */
5620 while (!VEC_empty (rtx_p, substitute_stack))
5622 rtx *where = VEC_pop (rtx_p, substitute_stack);
5623 *where = rld[r2].in;
5629 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5632 This function uses the same algorithm as reload_reg_free_p above. */
5635 reloads_conflict (int r1, int r2)
5637 enum reload_type r1_type = rld[r1].when_needed;
5638 enum reload_type r2_type = rld[r2].when_needed;
5639 int r1_opnum = rld[r1].opnum;
5640 int r2_opnum = rld[r2].opnum;
5642 /* RELOAD_OTHER conflicts with everything. */
5643 if (r2_type == RELOAD_OTHER)
5646 /* Otherwise, check conflicts differently for each type. */
5650 case RELOAD_FOR_INPUT:
5651 return (r2_type == RELOAD_FOR_INSN
5652 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5653 || r2_type == RELOAD_FOR_OPADDR_ADDR
5654 || r2_type == RELOAD_FOR_INPUT
5655 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5656 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5657 && r2_opnum > r1_opnum));
5659 case RELOAD_FOR_INPUT_ADDRESS:
5660 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5661 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5663 case RELOAD_FOR_INPADDR_ADDRESS:
5664 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5665 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5667 case RELOAD_FOR_OUTPUT_ADDRESS:
5668 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5669 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5671 case RELOAD_FOR_OUTADDR_ADDRESS:
5672 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5673 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5675 case RELOAD_FOR_OPERAND_ADDRESS:
5676 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5677 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5678 && (!reloads_unique_chain_p (r1, r2)
5679 || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5681 case RELOAD_FOR_OPADDR_ADDR:
5682 return (r2_type == RELOAD_FOR_INPUT
5683 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5685 case RELOAD_FOR_OUTPUT:
5686 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5687 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5688 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5689 && r2_opnum >= r1_opnum));
5691 case RELOAD_FOR_INSN:
5692 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5693 || r2_type == RELOAD_FOR_INSN
5694 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5696 case RELOAD_FOR_OTHER_ADDRESS:
5697 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5707 /* Indexed by reload number, 1 if incoming value
5708 inherited from previous insns. */
5709 static char reload_inherited[MAX_RELOADS];
5711 /* For an inherited reload, this is the insn the reload was inherited from,
5712 if we know it. Otherwise, this is 0. */
5713 static rtx reload_inheritance_insn[MAX_RELOADS];
5715 /* If nonzero, this is a place to get the value of the reload,
5716 rather than using reload_in. */
5717 static rtx reload_override_in[MAX_RELOADS];
5719 /* For each reload, the hard register number of the register used,
5720 or -1 if we did not need a register for this reload. */
5721 static int reload_spill_index[MAX_RELOADS];
5723 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5724 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5726 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5727 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5729 /* Subroutine of free_for_value_p, used to check a single register.
5730 START_REGNO is the starting regno of the full reload register
5731 (possibly comprising multiple hard registers) that we are considering. */
5734 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5735 enum reload_type type, rtx value, rtx out,
5736 int reloadnum, int ignore_address_reloads)
5739 /* Set if we see an input reload that must not share its reload register
5740 with any new earlyclobber, but might otherwise share the reload
5741 register with an output or input-output reload. */
5742 int check_earlyclobber = 0;
5746 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5749 if (out == const0_rtx)
5755 /* We use some pseudo 'time' value to check if the lifetimes of the
5756 new register use would overlap with the one of a previous reload
5757 that is not read-only or uses a different value.
5758 The 'time' used doesn't have to be linear in any shape or form, just
5760 Some reload types use different 'buckets' for each operand.
5761 So there are MAX_RECOG_OPERANDS different time values for each
5763 We compute TIME1 as the time when the register for the prospective
5764 new reload ceases to be live, and TIME2 for each existing
5765 reload as the time when that the reload register of that reload
5767 Where there is little to be gained by exact lifetime calculations,
5768 we just make conservative assumptions, i.e. a longer lifetime;
5769 this is done in the 'default:' cases. */
5772 case RELOAD_FOR_OTHER_ADDRESS:
5773 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5774 time1 = copy ? 0 : 1;
5777 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5779 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5780 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5781 respectively, to the time values for these, we get distinct time
5782 values. To get distinct time values for each operand, we have to
5783 multiply opnum by at least three. We round that up to four because
5784 multiply by four is often cheaper. */
5785 case RELOAD_FOR_INPADDR_ADDRESS:
5786 time1 = opnum * 4 + 2;
5788 case RELOAD_FOR_INPUT_ADDRESS:
5789 time1 = opnum * 4 + 3;
5791 case RELOAD_FOR_INPUT:
5792 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5793 executes (inclusive). */
5794 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5796 case RELOAD_FOR_OPADDR_ADDR:
5798 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5799 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5801 case RELOAD_FOR_OPERAND_ADDRESS:
5802 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5804 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5806 case RELOAD_FOR_OUTADDR_ADDRESS:
5807 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5809 case RELOAD_FOR_OUTPUT_ADDRESS:
5810 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5813 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5816 for (i = 0; i < n_reloads; i++)
5818 rtx reg = rld[i].reg_rtx;
5819 if (reg && REG_P (reg)
5820 && ((unsigned) regno - true_regnum (reg)
5821 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5824 rtx other_input = rld[i].in;
5826 /* If the other reload loads the same input value, that
5827 will not cause a conflict only if it's loading it into
5828 the same register. */
5829 if (true_regnum (reg) != start_regno)
5830 other_input = NULL_RTX;
5831 if (! other_input || ! rtx_equal_p (other_input, value)
5832 || rld[i].out || out)
5835 switch (rld[i].when_needed)
5837 case RELOAD_FOR_OTHER_ADDRESS:
5840 case RELOAD_FOR_INPADDR_ADDRESS:
5841 /* find_reloads makes sure that a
5842 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5843 by at most one - the first -
5844 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5845 address reload is inherited, the address address reload
5846 goes away, so we can ignore this conflict. */
5847 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5848 && ignore_address_reloads
5849 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5850 Then the address address is still needed to store
5851 back the new address. */
5852 && ! rld[reloadnum].out)
5854 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5855 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5857 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5858 && ignore_address_reloads
5859 /* Unless we are reloading an auto_inc expression. */
5860 && ! rld[reloadnum].out)
5862 time2 = rld[i].opnum * 4 + 2;
5864 case RELOAD_FOR_INPUT_ADDRESS:
5865 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5866 && ignore_address_reloads
5867 && ! rld[reloadnum].out)
5869 time2 = rld[i].opnum * 4 + 3;
5871 case RELOAD_FOR_INPUT:
5872 time2 = rld[i].opnum * 4 + 4;
5873 check_earlyclobber = 1;
5875 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5876 == MAX_RECOG_OPERAND * 4 */
5877 case RELOAD_FOR_OPADDR_ADDR:
5878 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5879 && ignore_address_reloads
5880 && ! rld[reloadnum].out)
5882 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5884 case RELOAD_FOR_OPERAND_ADDRESS:
5885 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5886 check_earlyclobber = 1;
5888 case RELOAD_FOR_INSN:
5889 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5891 case RELOAD_FOR_OUTPUT:
5892 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5893 instruction is executed. */
5894 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5896 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5897 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5899 case RELOAD_FOR_OUTADDR_ADDRESS:
5900 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5901 && ignore_address_reloads
5902 && ! rld[reloadnum].out)
5904 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5906 case RELOAD_FOR_OUTPUT_ADDRESS:
5907 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5910 /* If there is no conflict in the input part, handle this
5911 like an output reload. */
5912 if (! rld[i].in || rtx_equal_p (other_input, value))
5914 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5915 /* Earlyclobbered outputs must conflict with inputs. */
5916 if (earlyclobber_operand_p (rld[i].out))
5917 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5922 /* RELOAD_OTHER might be live beyond instruction execution,
5923 but this is not obvious when we set time2 = 1. So check
5924 here if there might be a problem with the new reload
5925 clobbering the register used by the RELOAD_OTHER. */
5933 && (! rld[i].in || rld[i].out
5934 || ! rtx_equal_p (other_input, value)))
5935 || (out && rld[reloadnum].out_reg
5936 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5942 /* Earlyclobbered outputs must conflict with inputs. */
5943 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5949 /* Return 1 if the value in reload reg REGNO, as used by a reload
5950 needed for the part of the insn specified by OPNUM and TYPE,
5951 may be used to load VALUE into it.
5953 MODE is the mode in which the register is used, this is needed to
5954 determine how many hard regs to test.
5956 Other read-only reloads with the same value do not conflict
5957 unless OUT is nonzero and these other reloads have to live while
5958 output reloads live.
5959 If OUT is CONST0_RTX, this is a special case: it means that the
5960 test should not be for using register REGNO as reload register, but
5961 for copying from register REGNO into the reload register.
5963 RELOADNUM is the number of the reload we want to load this value for;
5964 a reload does not conflict with itself.
5966 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5967 reloads that load an address for the very reload we are considering.
5969 The caller has to make sure that there is no conflict with the return
5973 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5974 enum reload_type type, rtx value, rtx out, int reloadnum,
5975 int ignore_address_reloads)
5977 int nregs = hard_regno_nregs[regno][mode];
5979 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5980 value, out, reloadnum,
5981 ignore_address_reloads))
5986 /* Return nonzero if the rtx X is invariant over the current function. */
5987 /* ??? Actually, the places where we use this expect exactly what is
5988 tested here, and not everything that is function invariant. In
5989 particular, the frame pointer and arg pointer are special cased;
5990 pic_offset_table_rtx is not, and we must not spill these things to
5994 function_invariant_p (const_rtx x)
5998 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
6000 if (GET_CODE (x) == PLUS
6001 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
6002 && GET_CODE (XEXP (x, 1)) == CONST_INT)
6007 /* Determine whether the reload reg X overlaps any rtx'es used for
6008 overriding inheritance. Return nonzero if so. */
6011 conflicts_with_override (rtx x)
6014 for (i = 0; i < n_reloads; i++)
6015 if (reload_override_in[i]
6016 && reg_overlap_mentioned_p (x, reload_override_in[i]))
6021 /* Give an error message saying we failed to find a reload for INSN,
6022 and clear out reload R. */
6024 failed_reload (rtx insn, int r)
6026 if (asm_noperands (PATTERN (insn)) < 0)
6027 /* It's the compiler's fault. */
6028 fatal_insn ("could not find a spill register", insn);
6030 /* It's the user's fault; the operand's mode and constraint
6031 don't match. Disable this reload so we don't crash in final. */
6032 error_for_asm (insn,
6033 "%<asm%> operand constraint incompatible with operand size");
6037 rld[r].optional = 1;
6038 rld[r].secondary_p = 1;
6041 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6042 for reload R. If it's valid, get an rtx for it. Return nonzero if
6045 set_reload_reg (int i, int r)
6048 rtx reg = spill_reg_rtx[i];
6050 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
6051 spill_reg_rtx[i] = reg
6052 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
6054 regno = true_regnum (reg);
6056 /* Detect when the reload reg can't hold the reload mode.
6057 This used to be one `if', but Sequent compiler can't handle that. */
6058 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
6060 enum machine_mode test_mode = VOIDmode;
6062 test_mode = GET_MODE (rld[r].in);
6063 /* If rld[r].in has VOIDmode, it means we will load it
6064 in whatever mode the reload reg has: to wit, rld[r].mode.
6065 We have already tested that for validity. */
6066 /* Aside from that, we need to test that the expressions
6067 to reload from or into have modes which are valid for this
6068 reload register. Otherwise the reload insns would be invalid. */
6069 if (! (rld[r].in != 0 && test_mode != VOIDmode
6070 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
6071 if (! (rld[r].out != 0
6072 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
6074 /* The reg is OK. */
6077 /* Mark as in use for this insn the reload regs we use
6079 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
6080 rld[r].when_needed, rld[r].mode);
6082 rld[r].reg_rtx = reg;
6083 reload_spill_index[r] = spill_regs[i];
6090 /* Find a spill register to use as a reload register for reload R.
6091 LAST_RELOAD is nonzero if this is the last reload for the insn being
6094 Set rld[R].reg_rtx to the register allocated.
6096 We return 1 if successful, or 0 if we couldn't find a spill reg and
6097 we didn't change anything. */
6100 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
6105 /* If we put this reload ahead, thinking it is a group,
6106 then insist on finding a group. Otherwise we can grab a
6107 reg that some other reload needs.
6108 (That can happen when we have a 68000 DATA_OR_FP_REG
6109 which is a group of data regs or one fp reg.)
6110 We need not be so restrictive if there are no more reloads
6113 ??? Really it would be nicer to have smarter handling
6114 for that kind of reg class, where a problem like this is normal.
6115 Perhaps those classes should be avoided for reloading
6116 by use of more alternatives. */
6118 int force_group = rld[r].nregs > 1 && ! last_reload;
6120 /* If we want a single register and haven't yet found one,
6121 take any reg in the right class and not in use.
6122 If we want a consecutive group, here is where we look for it.
6124 We use three passes so we can first look for reload regs to
6125 reuse, which are already in use for other reloads in this insn,
6126 and only then use additional registers which are not "bad", then
6127 finally any register.
6129 I think that maximizing reuse is needed to make sure we don't
6130 run out of reload regs. Suppose we have three reloads, and
6131 reloads A and B can share regs. These need two regs.
6132 Suppose A and B are given different regs.
6133 That leaves none for C. */
6134 for (pass = 0; pass < 3; pass++)
6136 /* I is the index in spill_regs.
6137 We advance it round-robin between insns to use all spill regs
6138 equally, so that inherited reloads have a chance
6139 of leapfrogging each other. */
6143 for (count = 0; count < n_spills; count++)
6145 int rclass = (int) rld[r].rclass;
6151 regnum = spill_regs[i];
6153 if ((reload_reg_free_p (regnum, rld[r].opnum,
6156 /* We check reload_reg_used to make sure we
6157 don't clobber the return register. */
6158 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
6159 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
6160 rld[r].when_needed, rld[r].in,
6162 && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
6163 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
6164 /* Look first for regs to share, then for unshared. But
6165 don't share regs used for inherited reloads; they are
6166 the ones we want to preserve. */
6168 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
6170 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
6173 int nr = hard_regno_nregs[regnum][rld[r].mode];
6175 /* During the second pass we want to avoid reload registers
6176 which are "bad" for this reload. */
6178 && ira_bad_reload_regno (regnum, rld[r].in, rld[r].out))
6181 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6182 (on 68000) got us two FP regs. If NR is 1,
6183 we would reject both of them. */
6186 /* If we need only one reg, we have already won. */
6189 /* But reject a single reg if we demand a group. */
6194 /* Otherwise check that as many consecutive regs as we need
6195 are available here. */
6198 int regno = regnum + nr - 1;
6199 if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
6200 && spill_reg_order[regno] >= 0
6201 && reload_reg_free_p (regno, rld[r].opnum,
6202 rld[r].when_needed)))
6211 /* If we found something on the current pass, omit later passes. */
6212 if (count < n_spills)
6216 /* We should have found a spill register by now. */
6217 if (count >= n_spills)
6220 /* I is the index in SPILL_REG_RTX of the reload register we are to
6221 allocate. Get an rtx for it and find its register number. */
6223 return set_reload_reg (i, r);
6226 /* Initialize all the tables needed to allocate reload registers.
6227 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6228 is the array we use to restore the reg_rtx field for every reload. */
6231 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
6235 for (i = 0; i < n_reloads; i++)
6236 rld[i].reg_rtx = save_reload_reg_rtx[i];
6238 memset (reload_inherited, 0, MAX_RELOADS);
6239 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
6240 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
6242 CLEAR_HARD_REG_SET (reload_reg_used);
6243 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
6244 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
6245 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
6246 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
6247 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
6249 CLEAR_HARD_REG_SET (reg_used_in_insn);
6252 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
6253 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6254 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
6255 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6256 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
6257 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
6260 for (i = 0; i < reload_n_operands; i++)
6262 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
6263 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
6264 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
6265 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
6266 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
6267 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
6270 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
6272 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
6274 for (i = 0; i < n_reloads; i++)
6275 /* If we have already decided to use a certain register,
6276 don't use it in another way. */
6278 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
6279 rld[i].when_needed, rld[i].mode);
6282 /* Assign hard reg targets for the pseudo-registers we must reload
6283 into hard regs for this insn.
6284 Also output the instructions to copy them in and out of the hard regs.
6286 For machines with register classes, we are responsible for
6287 finding a reload reg in the proper class. */
6290 choose_reload_regs (struct insn_chain *chain)
6292 rtx insn = chain->insn;
6294 unsigned int max_group_size = 1;
6295 enum reg_class group_class = NO_REGS;
6296 int pass, win, inheritance;
6298 rtx save_reload_reg_rtx[MAX_RELOADS];
6300 /* In order to be certain of getting the registers we need,
6301 we must sort the reloads into order of increasing register class.
6302 Then our grabbing of reload registers will parallel the process
6303 that provided the reload registers.
6305 Also note whether any of the reloads wants a consecutive group of regs.
6306 If so, record the maximum size of the group desired and what
6307 register class contains all the groups needed by this insn. */
6309 for (j = 0; j < n_reloads; j++)
6311 reload_order[j] = j;
6312 if (rld[j].reg_rtx != NULL_RTX)
6314 gcc_assert (REG_P (rld[j].reg_rtx)
6315 && HARD_REGISTER_P (rld[j].reg_rtx));
6316 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
6319 reload_spill_index[j] = -1;
6321 if (rld[j].nregs > 1)
6323 max_group_size = MAX (rld[j].nregs, max_group_size);
6325 = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
6328 save_reload_reg_rtx[j] = rld[j].reg_rtx;
6332 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
6334 /* If -O, try first with inheritance, then turning it off.
6335 If not -O, don't do inheritance.
6336 Using inheritance when not optimizing leads to paradoxes
6337 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6338 because one side of the comparison might be inherited. */
6340 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
6342 choose_reload_regs_init (chain, save_reload_reg_rtx);
6344 /* Process the reloads in order of preference just found.
6345 Beyond this point, subregs can be found in reload_reg_rtx.
6347 This used to look for an existing reloaded home for all of the
6348 reloads, and only then perform any new reloads. But that could lose
6349 if the reloads were done out of reg-class order because a later
6350 reload with a looser constraint might have an old home in a register
6351 needed by an earlier reload with a tighter constraint.
6353 To solve this, we make two passes over the reloads, in the order
6354 described above. In the first pass we try to inherit a reload
6355 from a previous insn. If there is a later reload that needs a
6356 class that is a proper subset of the class being processed, we must
6357 also allocate a spill register during the first pass.
6359 Then make a second pass over the reloads to allocate any reloads
6360 that haven't been given registers yet. */
6362 for (j = 0; j < n_reloads; j++)
6364 int r = reload_order[j];
6365 rtx search_equiv = NULL_RTX;
6367 /* Ignore reloads that got marked inoperative. */
6368 if (rld[r].out == 0 && rld[r].in == 0
6369 && ! rld[r].secondary_p)
6372 /* If find_reloads chose to use reload_in or reload_out as a reload
6373 register, we don't need to chose one. Otherwise, try even if it
6374 found one since we might save an insn if we find the value lying
6376 Try also when reload_in is a pseudo without a hard reg. */
6377 if (rld[r].in != 0 && rld[r].reg_rtx != 0
6378 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
6379 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
6380 && !MEM_P (rld[r].in)
6381 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
6384 #if 0 /* No longer needed for correct operation.
6385 It might give better code, or might not; worth an experiment? */
6386 /* If this is an optional reload, we can't inherit from earlier insns
6387 until we are sure that any non-optional reloads have been allocated.
6388 The following code takes advantage of the fact that optional reloads
6389 are at the end of reload_order. */
6390 if (rld[r].optional != 0)
6391 for (i = 0; i < j; i++)
6392 if ((rld[reload_order[i]].out != 0
6393 || rld[reload_order[i]].in != 0
6394 || rld[reload_order[i]].secondary_p)
6395 && ! rld[reload_order[i]].optional
6396 && rld[reload_order[i]].reg_rtx == 0)
6397 allocate_reload_reg (chain, reload_order[i], 0);
6400 /* First see if this pseudo is already available as reloaded
6401 for a previous insn. We cannot try to inherit for reloads
6402 that are smaller than the maximum number of registers needed
6403 for groups unless the register we would allocate cannot be used
6406 We could check here to see if this is a secondary reload for
6407 an object that is already in a register of the desired class.
6408 This would avoid the need for the secondary reload register.
6409 But this is complex because we can't easily determine what
6410 objects might want to be loaded via this reload. So let a
6411 register be allocated here. In `emit_reload_insns' we suppress
6412 one of the loads in the case described above. */
6418 enum machine_mode mode = VOIDmode;
6422 else if (REG_P (rld[r].in))
6424 regno = REGNO (rld[r].in);
6425 mode = GET_MODE (rld[r].in);
6427 else if (REG_P (rld[r].in_reg))
6429 regno = REGNO (rld[r].in_reg);
6430 mode = GET_MODE (rld[r].in_reg);
6432 else if (GET_CODE (rld[r].in_reg) == SUBREG
6433 && REG_P (SUBREG_REG (rld[r].in_reg)))
6435 regno = REGNO (SUBREG_REG (rld[r].in_reg));
6436 if (regno < FIRST_PSEUDO_REGISTER)
6437 regno = subreg_regno (rld[r].in_reg);
6439 byte = SUBREG_BYTE (rld[r].in_reg);
6440 mode = GET_MODE (rld[r].in_reg);
6443 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6444 && REG_P (XEXP (rld[r].in_reg, 0)))
6446 regno = REGNO (XEXP (rld[r].in_reg, 0));
6447 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6448 rld[r].out = rld[r].in;
6452 /* This won't work, since REGNO can be a pseudo reg number.
6453 Also, it takes much more hair to keep track of all the things
6454 that can invalidate an inherited reload of part of a pseudoreg. */
6455 else if (GET_CODE (rld[r].in) == SUBREG
6456 && REG_P (SUBREG_REG (rld[r].in)))
6457 regno = subreg_regno (rld[r].in);
6461 && reg_last_reload_reg[regno] != 0
6462 #ifdef CANNOT_CHANGE_MODE_CLASS
6463 /* Verify that the register it's in can be used in
6465 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
6466 GET_MODE (reg_last_reload_reg[regno]),
6471 enum reg_class rclass = rld[r].rclass, last_class;
6472 rtx last_reg = reg_last_reload_reg[regno];
6473 enum machine_mode need_mode;
6475 i = REGNO (last_reg);
6476 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6477 last_class = REGNO_REG_CLASS (i);
6483 = smallest_mode_for_size
6484 (GET_MODE_BITSIZE (mode) + byte * BITS_PER_UNIT,
6485 GET_MODE_CLASS (mode) == MODE_PARTIAL_INT
6486 ? MODE_INT : GET_MODE_CLASS (mode));
6488 if ((GET_MODE_SIZE (GET_MODE (last_reg))
6489 >= GET_MODE_SIZE (need_mode))
6490 && reg_reloaded_contents[i] == regno
6491 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6492 && HARD_REGNO_MODE_OK (i, rld[r].mode)
6493 && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6494 /* Even if we can't use this register as a reload
6495 register, we might use it for reload_override_in,
6496 if copying it to the desired class is cheap
6498 || ((register_move_cost (mode, last_class, rclass)
6499 < memory_move_cost (mode, rclass, true))
6500 && (secondary_reload_class (1, rclass, mode,
6503 #ifdef SECONDARY_MEMORY_NEEDED
6504 && ! SECONDARY_MEMORY_NEEDED (last_class, rclass,
6509 && (rld[r].nregs == max_group_size
6510 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6512 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6513 rld[r].when_needed, rld[r].in,
6516 /* If a group is needed, verify that all the subsequent
6517 registers still have their values intact. */
6518 int nr = hard_regno_nregs[i][rld[r].mode];
6521 for (k = 1; k < nr; k++)
6522 if (reg_reloaded_contents[i + k] != regno
6523 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6531 last_reg = (GET_MODE (last_reg) == mode
6532 ? last_reg : gen_rtx_REG (mode, i));
6535 for (k = 0; k < nr; k++)
6536 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6539 /* We found a register that contains the
6540 value we need. If this register is the
6541 same as an `earlyclobber' operand of the
6542 current insn, just mark it as a place to
6543 reload from since we can't use it as the
6544 reload register itself. */
6546 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6547 if (reg_overlap_mentioned_for_reload_p
6548 (reg_last_reload_reg[regno],
6549 reload_earlyclobbers[i1]))
6552 if (i1 != n_earlyclobbers
6553 || ! (free_for_value_p (i, rld[r].mode,
6555 rld[r].when_needed, rld[r].in,
6557 /* Don't use it if we'd clobber a pseudo reg. */
6558 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6560 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6561 /* Don't clobber the frame pointer. */
6562 || (i == HARD_FRAME_POINTER_REGNUM
6563 && frame_pointer_needed
6565 /* Don't really use the inherited spill reg
6566 if we need it wider than we've got it. */
6567 || (GET_MODE_SIZE (rld[r].mode)
6568 > GET_MODE_SIZE (mode))
6571 /* If find_reloads chose reload_out as reload
6572 register, stay with it - that leaves the
6573 inherited register for subsequent reloads. */
6574 || (rld[r].out && rld[r].reg_rtx
6575 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6577 if (! rld[r].optional)
6579 reload_override_in[r] = last_reg;
6580 reload_inheritance_insn[r]
6581 = reg_reloaded_insn[i];
6587 /* We can use this as a reload reg. */
6588 /* Mark the register as in use for this part of
6590 mark_reload_reg_in_use (i,
6594 rld[r].reg_rtx = last_reg;
6595 reload_inherited[r] = 1;
6596 reload_inheritance_insn[r]
6597 = reg_reloaded_insn[i];
6598 reload_spill_index[r] = i;
6599 for (k = 0; k < nr; k++)
6600 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6608 /* Here's another way to see if the value is already lying around. */
6611 && ! reload_inherited[r]
6613 && (CONSTANT_P (rld[r].in)
6614 || GET_CODE (rld[r].in) == PLUS
6615 || REG_P (rld[r].in)
6616 || MEM_P (rld[r].in))
6617 && (rld[r].nregs == max_group_size
6618 || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6619 search_equiv = rld[r].in;
6620 /* If this is an output reload from a simple move insn, look
6621 if an equivalence for the input is available. */
6622 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
6624 rtx set = single_set (insn);
6627 && rtx_equal_p (rld[r].out, SET_DEST (set))
6628 && CONSTANT_P (SET_SRC (set)))
6629 search_equiv = SET_SRC (set);
6635 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6636 -1, NULL, 0, rld[r].mode);
6642 regno = REGNO (equiv);
6645 /* This must be a SUBREG of a hard register.
6646 Make a new REG since this might be used in an
6647 address and not all machines support SUBREGs
6649 gcc_assert (GET_CODE (equiv) == SUBREG);
6650 regno = subreg_regno (equiv);
6651 equiv = gen_rtx_REG (rld[r].mode, regno);
6652 /* If we choose EQUIV as the reload register, but the
6653 loop below decides to cancel the inheritance, we'll
6654 end up reloading EQUIV in rld[r].mode, not the mode
6655 it had originally. That isn't safe when EQUIV isn't
6656 available as a spill register since its value might
6657 still be live at this point. */
6658 for (i = regno; i < regno + (int) rld[r].nregs; i++)
6659 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6664 /* If we found a spill reg, reject it unless it is free
6665 and of the desired class. */
6669 int bad_for_class = 0;
6670 int max_regno = regno + rld[r].nregs;
6672 for (i = regno; i < max_regno; i++)
6674 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6676 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6681 && ! free_for_value_p (regno, rld[r].mode,
6682 rld[r].opnum, rld[r].when_needed,
6683 rld[r].in, rld[r].out, r, 1))
6688 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6691 /* We found a register that contains the value we need.
6692 If this register is the same as an `earlyclobber' operand
6693 of the current insn, just mark it as a place to reload from
6694 since we can't use it as the reload register itself. */
6697 for (i = 0; i < n_earlyclobbers; i++)
6698 if (reg_overlap_mentioned_for_reload_p (equiv,
6699 reload_earlyclobbers[i]))
6701 if (! rld[r].optional)
6702 reload_override_in[r] = equiv;
6707 /* If the equiv register we have found is explicitly clobbered
6708 in the current insn, it depends on the reload type if we
6709 can use it, use it for reload_override_in, or not at all.
6710 In particular, we then can't use EQUIV for a
6711 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6715 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6716 switch (rld[r].when_needed)
6718 case RELOAD_FOR_OTHER_ADDRESS:
6719 case RELOAD_FOR_INPADDR_ADDRESS:
6720 case RELOAD_FOR_INPUT_ADDRESS:
6721 case RELOAD_FOR_OPADDR_ADDR:
6724 case RELOAD_FOR_INPUT:
6725 case RELOAD_FOR_OPERAND_ADDRESS:
6726 if (! rld[r].optional)
6727 reload_override_in[r] = equiv;
6733 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6734 switch (rld[r].when_needed)
6736 case RELOAD_FOR_OTHER_ADDRESS:
6737 case RELOAD_FOR_INPADDR_ADDRESS:
6738 case RELOAD_FOR_INPUT_ADDRESS:
6739 case RELOAD_FOR_OPADDR_ADDR:
6740 case RELOAD_FOR_OPERAND_ADDRESS:
6741 case RELOAD_FOR_INPUT:
6744 if (! rld[r].optional)
6745 reload_override_in[r] = equiv;
6753 /* If we found an equivalent reg, say no code need be generated
6754 to load it, and use it as our reload reg. */
6756 && (regno != HARD_FRAME_POINTER_REGNUM
6757 || !frame_pointer_needed))
6759 int nr = hard_regno_nregs[regno][rld[r].mode];
6761 rld[r].reg_rtx = equiv;
6762 reload_spill_index[r] = regno;
6763 reload_inherited[r] = 1;
6765 /* If reg_reloaded_valid is not set for this register,
6766 there might be a stale spill_reg_store lying around.
6767 We must clear it, since otherwise emit_reload_insns
6768 might delete the store. */
6769 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6770 spill_reg_store[regno] = NULL_RTX;
6771 /* If any of the hard registers in EQUIV are spill
6772 registers, mark them as in use for this insn. */
6773 for (k = 0; k < nr; k++)
6775 i = spill_reg_order[regno + k];
6778 mark_reload_reg_in_use (regno, rld[r].opnum,
6781 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6788 /* If we found a register to use already, or if this is an optional
6789 reload, we are done. */
6790 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6794 /* No longer needed for correct operation. Might or might
6795 not give better code on the average. Want to experiment? */
6797 /* See if there is a later reload that has a class different from our
6798 class that intersects our class or that requires less register
6799 than our reload. If so, we must allocate a register to this
6800 reload now, since that reload might inherit a previous reload
6801 and take the only available register in our class. Don't do this
6802 for optional reloads since they will force all previous reloads
6803 to be allocated. Also don't do this for reloads that have been
6806 for (i = j + 1; i < n_reloads; i++)
6808 int s = reload_order[i];
6810 if ((rld[s].in == 0 && rld[s].out == 0
6811 && ! rld[s].secondary_p)
6815 if ((rld[s].rclass != rld[r].rclass
6816 && reg_classes_intersect_p (rld[r].rclass,
6818 || rld[s].nregs < rld[r].nregs)
6825 allocate_reload_reg (chain, r, j == n_reloads - 1);
6829 /* Now allocate reload registers for anything non-optional that
6830 didn't get one yet. */
6831 for (j = 0; j < n_reloads; j++)
6833 int r = reload_order[j];
6835 /* Ignore reloads that got marked inoperative. */
6836 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6839 /* Skip reloads that already have a register allocated or are
6841 if (rld[r].reg_rtx != 0 || rld[r].optional)
6844 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6848 /* If that loop got all the way, we have won. */
6855 /* Loop around and try without any inheritance. */
6860 /* First undo everything done by the failed attempt
6861 to allocate with inheritance. */
6862 choose_reload_regs_init (chain, save_reload_reg_rtx);
6864 /* Some sanity tests to verify that the reloads found in the first
6865 pass are identical to the ones we have now. */
6866 gcc_assert (chain->n_reloads == n_reloads);
6868 for (i = 0; i < n_reloads; i++)
6870 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6872 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6873 for (j = 0; j < n_spills; j++)
6874 if (spill_regs[j] == chain->rld[i].regno)
6875 if (! set_reload_reg (j, i))
6876 failed_reload (chain->insn, i);
6880 /* If we thought we could inherit a reload, because it seemed that
6881 nothing else wanted the same reload register earlier in the insn,
6882 verify that assumption, now that all reloads have been assigned.
6883 Likewise for reloads where reload_override_in has been set. */
6885 /* If doing expensive optimizations, do one preliminary pass that doesn't
6886 cancel any inheritance, but removes reloads that have been needed only
6887 for reloads that we know can be inherited. */
6888 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6890 for (j = 0; j < n_reloads; j++)
6892 int r = reload_order[j];
6894 if (reload_inherited[r] && rld[r].reg_rtx)
6895 check_reg = rld[r].reg_rtx;
6896 else if (reload_override_in[r]
6897 && (REG_P (reload_override_in[r])
6898 || GET_CODE (reload_override_in[r]) == SUBREG))
6899 check_reg = reload_override_in[r];
6902 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6903 rld[r].opnum, rld[r].when_needed, rld[r].in,
6904 (reload_inherited[r]
6905 ? rld[r].out : const0_rtx),
6910 reload_inherited[r] = 0;
6911 reload_override_in[r] = 0;
6913 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6914 reload_override_in, then we do not need its related
6915 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6916 likewise for other reload types.
6917 We handle this by removing a reload when its only replacement
6918 is mentioned in reload_in of the reload we are going to inherit.
6919 A special case are auto_inc expressions; even if the input is
6920 inherited, we still need the address for the output. We can
6921 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6922 If we succeeded removing some reload and we are doing a preliminary
6923 pass just to remove such reloads, make another pass, since the
6924 removal of one reload might allow us to inherit another one. */
6926 && rld[r].out != rld[r].in
6927 && remove_address_replacements (rld[r].in) && pass)
6932 /* Now that reload_override_in is known valid,
6933 actually override reload_in. */
6934 for (j = 0; j < n_reloads; j++)
6935 if (reload_override_in[j])
6936 rld[j].in = reload_override_in[j];
6938 /* If this reload won't be done because it has been canceled or is
6939 optional and not inherited, clear reload_reg_rtx so other
6940 routines (such as subst_reloads) don't get confused. */
6941 for (j = 0; j < n_reloads; j++)
6942 if (rld[j].reg_rtx != 0
6943 && ((rld[j].optional && ! reload_inherited[j])
6944 || (rld[j].in == 0 && rld[j].out == 0
6945 && ! rld[j].secondary_p)))
6947 int regno = true_regnum (rld[j].reg_rtx);
6949 if (spill_reg_order[regno] >= 0)
6950 clear_reload_reg_in_use (regno, rld[j].opnum,
6951 rld[j].when_needed, rld[j].mode);
6953 reload_spill_index[j] = -1;
6956 /* Record which pseudos and which spill regs have output reloads. */
6957 for (j = 0; j < n_reloads; j++)
6959 int r = reload_order[j];
6961 i = reload_spill_index[r];
6963 /* I is nonneg if this reload uses a register.
6964 If rld[r].reg_rtx is 0, this is an optional reload
6965 that we opted to ignore. */
6966 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6967 && rld[r].reg_rtx != 0)
6969 int nregno = REGNO (rld[r].out_reg);
6972 if (nregno < FIRST_PSEUDO_REGISTER)
6973 nr = hard_regno_nregs[nregno][rld[r].mode];
6976 SET_REGNO_REG_SET (®_has_output_reload,
6981 nr = hard_regno_nregs[i][rld[r].mode];
6983 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6986 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6987 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6988 || rld[r].when_needed == RELOAD_FOR_INSN);
6993 /* Deallocate the reload register for reload R. This is called from
6994 remove_address_replacements. */
6997 deallocate_reload_reg (int r)
7001 if (! rld[r].reg_rtx)
7003 regno = true_regnum (rld[r].reg_rtx);
7005 if (spill_reg_order[regno] >= 0)
7006 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
7008 reload_spill_index[r] = -1;
7011 /* If the small_register_classes_for_mode_p target hook returns true for
7012 some machine modes, we may not have merged two reloads of the same item
7013 for fear that we might not have enough reload registers. However,
7014 normally they will get the same reload register and hence actually need
7015 not be loaded twice.
7017 Here we check for the most common case of this phenomenon: when we have
7018 a number of reloads for the same object, each of which were allocated
7019 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
7020 reload, and is not modified in the insn itself. If we find such,
7021 merge all the reloads and set the resulting reload to RELOAD_OTHER.
7022 This will not increase the number of spill registers needed and will
7023 prevent redundant code. */
7026 merge_assigned_reloads (rtx insn)
7030 /* Scan all the reloads looking for ones that only load values and
7031 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
7032 assigned and not modified by INSN. */
7034 for (i = 0; i < n_reloads; i++)
7036 int conflicting_input = 0;
7037 int max_input_address_opnum = -1;
7038 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
7040 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
7041 || rld[i].out != 0 || rld[i].reg_rtx == 0
7042 || reg_set_p (rld[i].reg_rtx, insn))
7045 /* Look at all other reloads. Ensure that the only use of this
7046 reload_reg_rtx is in a reload that just loads the same value
7047 as we do. Note that any secondary reloads must be of the identical
7048 class since the values, modes, and result registers are the
7049 same, so we need not do anything with any secondary reloads. */
7051 for (j = 0; j < n_reloads; j++)
7053 if (i == j || rld[j].reg_rtx == 0
7054 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
7058 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
7059 && rld[j].opnum > max_input_address_opnum)
7060 max_input_address_opnum = rld[j].opnum;
7062 /* If the reload regs aren't exactly the same (e.g, different modes)
7063 or if the values are different, we can't merge this reload.
7064 But if it is an input reload, we might still merge
7065 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
7067 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
7068 || rld[j].out != 0 || rld[j].in == 0
7069 || ! rtx_equal_p (rld[i].in, rld[j].in))
7071 if (rld[j].when_needed != RELOAD_FOR_INPUT
7072 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
7073 || rld[i].opnum > rld[j].opnum)
7074 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
7076 conflicting_input = 1;
7077 if (min_conflicting_input_opnum > rld[j].opnum)
7078 min_conflicting_input_opnum = rld[j].opnum;
7082 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
7083 we, in fact, found any matching reloads. */
7086 && max_input_address_opnum <= min_conflicting_input_opnum)
7088 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
7090 for (j = 0; j < n_reloads; j++)
7091 if (i != j && rld[j].reg_rtx != 0
7092 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
7093 && (! conflicting_input
7094 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
7095 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
7097 rld[i].when_needed = RELOAD_OTHER;
7099 reload_spill_index[j] = -1;
7100 transfer_replacements (i, j);
7103 /* If this is now RELOAD_OTHER, look for any reloads that
7104 load parts of this operand and set them to
7105 RELOAD_FOR_OTHER_ADDRESS if they were for inputs,
7106 RELOAD_OTHER for outputs. Note that this test is
7107 equivalent to looking for reloads for this operand
7110 We must take special care with RELOAD_FOR_OUTPUT_ADDRESS;
7111 it may share registers with a RELOAD_FOR_INPUT, so we can
7112 not change it to RELOAD_FOR_OTHER_ADDRESS. We should
7113 never need to, since we do not modify RELOAD_FOR_OUTPUT.
7115 It is possible that the RELOAD_FOR_OPERAND_ADDRESS
7116 instruction is assigned the same register as the earlier
7117 RELOAD_FOR_OTHER_ADDRESS instruction. Merging these two
7118 instructions will cause the RELOAD_FOR_OTHER_ADDRESS
7119 instruction to be deleted later on. */
7121 if (rld[i].when_needed == RELOAD_OTHER)
7122 for (j = 0; j < n_reloads; j++)
7124 && rld[j].when_needed != RELOAD_OTHER
7125 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
7126 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
7127 && rld[j].when_needed != RELOAD_FOR_OPERAND_ADDRESS
7128 && (! conflicting_input
7129 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
7130 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
7131 && reg_overlap_mentioned_for_reload_p (rld[j].in,
7137 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
7138 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
7139 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
7141 /* Check to see if we accidentally converted two
7142 reloads that use the same reload register with
7143 different inputs to the same type. If so, the
7144 resulting code won't work. */
7146 for (k = 0; k < j; k++)
7147 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
7148 || rld[k].when_needed != rld[j].when_needed
7149 || !rtx_equal_p (rld[k].reg_rtx,
7151 || rtx_equal_p (rld[k].in,
7158 /* These arrays are filled by emit_reload_insns and its subroutines. */
7159 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
7160 static rtx other_input_address_reload_insns = 0;
7161 static rtx other_input_reload_insns = 0;
7162 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
7163 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7164 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
7165 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
7166 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7167 static rtx operand_reload_insns = 0;
7168 static rtx other_operand_reload_insns = 0;
7169 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
7171 /* Values to be put in spill_reg_store are put here first. */
7172 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
7173 static HARD_REG_SET reg_reloaded_died;
7175 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7176 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
7177 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
7178 adjusted register, and return true. Otherwise, return false. */
7180 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
7181 enum reg_class new_class,
7182 enum machine_mode new_mode)
7187 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
7189 unsigned regno = REGNO (reg);
7191 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
7193 if (GET_MODE (reg) != new_mode)
7195 if (!HARD_REGNO_MODE_OK (regno, new_mode))
7197 if (hard_regno_nregs[regno][new_mode]
7198 > hard_regno_nregs[regno][GET_MODE (reg)])
7200 reg = reload_adjust_reg_for_mode (reg, new_mode);
7208 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7209 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7210 nonzero, if that is suitable. On success, change *RELOAD_REG to the
7211 adjusted register, and return true. Otherwise, return false. */
7213 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
7214 enum insn_code icode)
7217 enum reg_class new_class = scratch_reload_class (icode);
7218 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
7220 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
7221 new_class, new_mode);
7224 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7225 has the number J. OLD contains the value to be used as input. */
7228 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
7231 rtx insn = chain->insn;
7233 rtx oldequiv_reg = 0;
7236 enum machine_mode mode;
7239 /* delete_output_reload is only invoked properly if old contains
7240 the original pseudo register. Since this is replaced with a
7241 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7242 find the pseudo in RELOAD_IN_REG. */
7243 if (reload_override_in[j]
7244 && REG_P (rl->in_reg))
7251 else if (REG_P (oldequiv))
7252 oldequiv_reg = oldequiv;
7253 else if (GET_CODE (oldequiv) == SUBREG)
7254 oldequiv_reg = SUBREG_REG (oldequiv);
7256 reloadreg = reload_reg_rtx_for_input[j];
7257 mode = GET_MODE (reloadreg);
7259 /* If we are reloading from a register that was recently stored in
7260 with an output-reload, see if we can prove there was
7261 actually no need to store the old value in it. */
7263 if (optimize && REG_P (oldequiv)
7264 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
7265 && spill_reg_store[REGNO (oldequiv)]
7267 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
7268 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
7270 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
7272 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7275 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
7276 oldequiv = SUBREG_REG (oldequiv);
7277 if (GET_MODE (oldequiv) != VOIDmode
7278 && mode != GET_MODE (oldequiv))
7279 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
7281 /* Switch to the right place to emit the reload insns. */
7282 switch (rl->when_needed)
7285 where = &other_input_reload_insns;
7287 case RELOAD_FOR_INPUT:
7288 where = &input_reload_insns[rl->opnum];
7290 case RELOAD_FOR_INPUT_ADDRESS:
7291 where = &input_address_reload_insns[rl->opnum];
7293 case RELOAD_FOR_INPADDR_ADDRESS:
7294 where = &inpaddr_address_reload_insns[rl->opnum];
7296 case RELOAD_FOR_OUTPUT_ADDRESS:
7297 where = &output_address_reload_insns[rl->opnum];
7299 case RELOAD_FOR_OUTADDR_ADDRESS:
7300 where = &outaddr_address_reload_insns[rl->opnum];
7302 case RELOAD_FOR_OPERAND_ADDRESS:
7303 where = &operand_reload_insns;
7305 case RELOAD_FOR_OPADDR_ADDR:
7306 where = &other_operand_reload_insns;
7308 case RELOAD_FOR_OTHER_ADDRESS:
7309 where = &other_input_address_reload_insns;
7315 push_to_sequence (*where);
7317 /* Auto-increment addresses must be reloaded in a special way. */
7318 if (rl->out && ! rl->out_reg)
7320 /* We are not going to bother supporting the case where a
7321 incremented register can't be copied directly from
7322 OLDEQUIV since this seems highly unlikely. */
7323 gcc_assert (rl->secondary_in_reload < 0);
7325 if (reload_inherited[j])
7326 oldequiv = reloadreg;
7328 old = XEXP (rl->in_reg, 0);
7330 if (optimize && REG_P (oldequiv)
7331 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
7332 && spill_reg_store[REGNO (oldequiv)]
7334 && (dead_or_set_p (insn,
7335 spill_reg_stored_to[REGNO (oldequiv)])
7336 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
7338 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
7340 /* Prevent normal processing of this reload. */
7342 /* Output a special code sequence for this case. */
7343 new_spill_reg_store[REGNO (reloadreg)]
7344 = inc_for_reload (reloadreg, oldequiv, rl->out,
7348 /* If we are reloading a pseudo-register that was set by the previous
7349 insn, see if we can get rid of that pseudo-register entirely
7350 by redirecting the previous insn into our reload register. */
7352 else if (optimize && REG_P (old)
7353 && REGNO (old) >= FIRST_PSEUDO_REGISTER
7354 && dead_or_set_p (insn, old)
7355 /* This is unsafe if some other reload
7356 uses the same reg first. */
7357 && ! conflicts_with_override (reloadreg)
7358 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
7359 rl->when_needed, old, rl->out, j, 0))
7361 rtx temp = PREV_INSN (insn);
7362 while (temp && (NOTE_P (temp) || DEBUG_INSN_P (temp)))
7363 temp = PREV_INSN (temp);
7365 && NONJUMP_INSN_P (temp)
7366 && GET_CODE (PATTERN (temp)) == SET
7367 && SET_DEST (PATTERN (temp)) == old
7368 /* Make sure we can access insn_operand_constraint. */
7369 && asm_noperands (PATTERN (temp)) < 0
7370 /* This is unsafe if operand occurs more than once in current
7371 insn. Perhaps some occurrences aren't reloaded. */
7372 && count_occurrences (PATTERN (insn), old, 0) == 1)
7374 rtx old = SET_DEST (PATTERN (temp));
7375 /* Store into the reload register instead of the pseudo. */
7376 SET_DEST (PATTERN (temp)) = reloadreg;
7378 /* Verify that resulting insn is valid. */
7379 extract_insn (temp);
7380 if (constrain_operands (1))
7382 /* If the previous insn is an output reload, the source is
7383 a reload register, and its spill_reg_store entry will
7384 contain the previous destination. This is now
7386 if (REG_P (SET_SRC (PATTERN (temp)))
7387 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
7389 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7390 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7393 /* If these are the only uses of the pseudo reg,
7394 pretend for GDB it lives in the reload reg we used. */
7395 if (REG_N_DEATHS (REGNO (old)) == 1
7396 && REG_N_SETS (REGNO (old)) == 1)
7398 reg_renumber[REGNO (old)] = REGNO (reloadreg);
7399 if (ira_conflicts_p)
7400 /* Inform IRA about the change. */
7401 ira_mark_allocation_change (REGNO (old));
7402 alter_reg (REGNO (old), -1, false);
7406 /* Adjust any debug insns between temp and insn. */
7407 while ((temp = NEXT_INSN (temp)) != insn)
7408 if (DEBUG_INSN_P (temp))
7409 replace_rtx (PATTERN (temp), old, reloadreg);
7411 gcc_assert (NOTE_P (temp));
7415 SET_DEST (PATTERN (temp)) = old;
7420 /* We can't do that, so output an insn to load RELOADREG. */
7422 /* If we have a secondary reload, pick up the secondary register
7423 and icode, if any. If OLDEQUIV and OLD are different or
7424 if this is an in-out reload, recompute whether or not we
7425 still need a secondary register and what the icode should
7426 be. If we still need a secondary register and the class or
7427 icode is different, go back to reloading from OLD if using
7428 OLDEQUIV means that we got the wrong type of register. We
7429 cannot have different class or icode due to an in-out reload
7430 because we don't make such reloads when both the input and
7431 output need secondary reload registers. */
7433 if (! special && rl->secondary_in_reload >= 0)
7435 rtx second_reload_reg = 0;
7436 rtx third_reload_reg = 0;
7437 int secondary_reload = rl->secondary_in_reload;
7438 rtx real_oldequiv = oldequiv;
7441 enum insn_code icode;
7442 enum insn_code tertiary_icode = CODE_FOR_nothing;
7444 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7445 and similarly for OLD.
7446 See comments in get_secondary_reload in reload.c. */
7447 /* If it is a pseudo that cannot be replaced with its
7448 equivalent MEM, we must fall back to reload_in, which
7449 will have all the necessary substitutions registered.
7450 Likewise for a pseudo that can't be replaced with its
7451 equivalent constant.
7453 Take extra care for subregs of such pseudos. Note that
7454 we cannot use reg_equiv_mem in this case because it is
7455 not in the right mode. */
7458 if (GET_CODE (tmp) == SUBREG)
7459 tmp = SUBREG_REG (tmp);
7461 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7462 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
7463 || reg_equiv_constant[REGNO (tmp)] != 0))
7465 if (! reg_equiv_mem[REGNO (tmp)]
7466 || num_not_at_initial_offset
7467 || GET_CODE (oldequiv) == SUBREG)
7468 real_oldequiv = rl->in;
7470 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
7474 if (GET_CODE (tmp) == SUBREG)
7475 tmp = SUBREG_REG (tmp);
7477 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7478 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
7479 || reg_equiv_constant[REGNO (tmp)] != 0))
7481 if (! reg_equiv_mem[REGNO (tmp)]
7482 || num_not_at_initial_offset
7483 || GET_CODE (old) == SUBREG)
7486 real_old = reg_equiv_mem[REGNO (tmp)];
7489 second_reload_reg = rld[secondary_reload].reg_rtx;
7490 if (rld[secondary_reload].secondary_in_reload >= 0)
7492 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7494 third_reload_reg = rld[tertiary_reload].reg_rtx;
7495 tertiary_icode = rld[secondary_reload].secondary_in_icode;
7496 /* We'd have to add more code for quartary reloads. */
7497 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7499 icode = rl->secondary_in_icode;
7501 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7502 || (rl->in != 0 && rl->out != 0))
7504 secondary_reload_info sri, sri2;
7505 enum reg_class new_class, new_t_class;
7507 sri.icode = CODE_FOR_nothing;
7508 sri.prev_sri = NULL;
7509 new_class = targetm.secondary_reload (1, real_oldequiv, rl->rclass,
7512 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7513 second_reload_reg = 0;
7514 else if (new_class == NO_REGS)
7516 if (reload_adjust_reg_for_icode (&second_reload_reg,
7518 (enum insn_code) sri.icode))
7520 icode = (enum insn_code) sri.icode;
7521 third_reload_reg = 0;
7526 real_oldequiv = real_old;
7529 else if (sri.icode != CODE_FOR_nothing)
7530 /* We currently lack a way to express this in reloads. */
7534 sri2.icode = CODE_FOR_nothing;
7535 sri2.prev_sri = &sri;
7536 new_t_class = targetm.secondary_reload (1, real_oldequiv,
7537 new_class, mode, &sri);
7538 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7540 if (reload_adjust_reg_for_temp (&second_reload_reg,
7544 third_reload_reg = 0;
7545 tertiary_icode = (enum insn_code) sri2.icode;
7550 real_oldequiv = real_old;
7553 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7555 rtx intermediate = second_reload_reg;
7557 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7559 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7563 second_reload_reg = intermediate;
7564 tertiary_icode = (enum insn_code) sri2.icode;
7569 real_oldequiv = real_old;
7572 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7574 rtx intermediate = second_reload_reg;
7576 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7578 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7581 second_reload_reg = intermediate;
7582 tertiary_icode = (enum insn_code) sri2.icode;
7587 real_oldequiv = real_old;
7592 /* This could be handled more intelligently too. */
7594 real_oldequiv = real_old;
7599 /* If we still need a secondary reload register, check
7600 to see if it is being used as a scratch or intermediate
7601 register and generate code appropriately. If we need
7602 a scratch register, use REAL_OLDEQUIV since the form of
7603 the insn may depend on the actual address if it is
7606 if (second_reload_reg)
7608 if (icode != CODE_FOR_nothing)
7610 /* We'd have to add extra code to handle this case. */
7611 gcc_assert (!third_reload_reg);
7613 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7614 second_reload_reg));
7619 /* See if we need a scratch register to load the
7620 intermediate register (a tertiary reload). */
7621 if (tertiary_icode != CODE_FOR_nothing)
7623 emit_insn ((GEN_FCN (tertiary_icode)
7624 (second_reload_reg, real_oldequiv,
7625 third_reload_reg)));
7627 else if (third_reload_reg)
7629 gen_reload (third_reload_reg, real_oldequiv,
7632 gen_reload (second_reload_reg, third_reload_reg,
7637 gen_reload (second_reload_reg, real_oldequiv,
7641 oldequiv = second_reload_reg;
7646 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7648 rtx real_oldequiv = oldequiv;
7650 if ((REG_P (oldequiv)
7651 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7652 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
7653 || reg_equiv_constant[REGNO (oldequiv)] != 0))
7654 || (GET_CODE (oldequiv) == SUBREG
7655 && REG_P (SUBREG_REG (oldequiv))
7656 && (REGNO (SUBREG_REG (oldequiv))
7657 >= FIRST_PSEUDO_REGISTER)
7658 && ((reg_equiv_memory_loc
7659 [REGNO (SUBREG_REG (oldequiv))] != 0)
7660 || (reg_equiv_constant
7661 [REGNO (SUBREG_REG (oldequiv))] != 0)))
7662 || (CONSTANT_P (oldequiv)
7663 && (PREFERRED_RELOAD_CLASS (oldequiv,
7664 REGNO_REG_CLASS (REGNO (reloadreg)))
7666 real_oldequiv = rl->in;
7667 gen_reload (reloadreg, real_oldequiv, rl->opnum,
7671 if (cfun->can_throw_non_call_exceptions)
7672 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7674 /* End this sequence. */
7675 *where = get_insns ();
7678 /* Update reload_override_in so that delete_address_reloads_1
7679 can see the actual register usage. */
7681 reload_override_in[j] = oldequiv;
7684 /* Generate insns to for the output reload RL, which is for the insn described
7685 by CHAIN and has the number J. */
7687 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7691 rtx insn = chain->insn;
7694 enum machine_mode mode;
7698 if (rl->when_needed == RELOAD_OTHER)
7701 push_to_sequence (output_reload_insns[rl->opnum]);
7703 rl_reg_rtx = reload_reg_rtx_for_output[j];
7704 mode = GET_MODE (rl_reg_rtx);
7706 reloadreg = rl_reg_rtx;
7708 /* If we need two reload regs, set RELOADREG to the intermediate
7709 one, since it will be stored into OLD. We might need a secondary
7710 register only for an input reload, so check again here. */
7712 if (rl->secondary_out_reload >= 0)
7715 int secondary_reload = rl->secondary_out_reload;
7716 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7718 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7719 && reg_equiv_mem[REGNO (old)] != 0)
7720 real_old = reg_equiv_mem[REGNO (old)];
7722 if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7724 rtx second_reloadreg = reloadreg;
7725 reloadreg = rld[secondary_reload].reg_rtx;
7727 /* See if RELOADREG is to be used as a scratch register
7728 or as an intermediate register. */
7729 if (rl->secondary_out_icode != CODE_FOR_nothing)
7731 /* We'd have to add extra code to handle this case. */
7732 gcc_assert (tertiary_reload < 0);
7734 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7735 (real_old, second_reloadreg, reloadreg)));
7740 /* See if we need both a scratch and intermediate reload
7743 enum insn_code tertiary_icode
7744 = rld[secondary_reload].secondary_out_icode;
7746 /* We'd have to add more code for quartary reloads. */
7747 gcc_assert (tertiary_reload < 0
7748 || rld[tertiary_reload].secondary_out_reload < 0);
7750 if (GET_MODE (reloadreg) != mode)
7751 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7753 if (tertiary_icode != CODE_FOR_nothing)
7755 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7758 /* Copy primary reload reg to secondary reload reg.
7759 (Note that these have been swapped above, then
7760 secondary reload reg to OLD using our insn.) */
7762 /* If REAL_OLD is a paradoxical SUBREG, remove it
7763 and try to put the opposite SUBREG on
7765 if (GET_CODE (real_old) == SUBREG
7766 && (GET_MODE_SIZE (GET_MODE (real_old))
7767 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7768 && 0 != (tem = gen_lowpart_common
7769 (GET_MODE (SUBREG_REG (real_old)),
7771 real_old = SUBREG_REG (real_old), reloadreg = tem;
7773 gen_reload (reloadreg, second_reloadreg,
7774 rl->opnum, rl->when_needed);
7775 emit_insn ((GEN_FCN (tertiary_icode)
7776 (real_old, reloadreg, third_reloadreg)));
7782 /* Copy between the reload regs here and then to
7785 gen_reload (reloadreg, second_reloadreg,
7786 rl->opnum, rl->when_needed);
7787 if (tertiary_reload >= 0)
7789 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7791 gen_reload (third_reloadreg, reloadreg,
7792 rl->opnum, rl->when_needed);
7793 reloadreg = third_reloadreg;
7800 /* Output the last reload insn. */
7805 /* Don't output the last reload if OLD is not the dest of
7806 INSN and is in the src and is clobbered by INSN. */
7807 if (! flag_expensive_optimizations
7809 || !(set = single_set (insn))
7810 || rtx_equal_p (old, SET_DEST (set))
7811 || !reg_mentioned_p (old, SET_SRC (set))
7812 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7813 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7814 gen_reload (old, reloadreg, rl->opnum,
7818 /* Look at all insns we emitted, just to be safe. */
7819 for (p = get_insns (); p; p = NEXT_INSN (p))
7822 rtx pat = PATTERN (p);
7824 /* If this output reload doesn't come from a spill reg,
7825 clear any memory of reloaded copies of the pseudo reg.
7826 If this output reload comes from a spill reg,
7827 reg_has_output_reload will make this do nothing. */
7828 note_stores (pat, forget_old_reloads_1, NULL);
7830 if (reg_mentioned_p (rl_reg_rtx, pat))
7832 rtx set = single_set (insn);
7833 if (reload_spill_index[j] < 0
7835 && SET_SRC (set) == rl_reg_rtx)
7837 int src = REGNO (SET_SRC (set));
7839 reload_spill_index[j] = src;
7840 SET_HARD_REG_BIT (reg_is_output_reload, src);
7841 if (find_regno_note (insn, REG_DEAD, src))
7842 SET_HARD_REG_BIT (reg_reloaded_died, src);
7844 if (HARD_REGISTER_P (rl_reg_rtx))
7846 int s = rl->secondary_out_reload;
7847 set = single_set (p);
7848 /* If this reload copies only to the secondary reload
7849 register, the secondary reload does the actual
7851 if (s >= 0 && set == NULL_RTX)
7852 /* We can't tell what function the secondary reload
7853 has and where the actual store to the pseudo is
7854 made; leave new_spill_reg_store alone. */
7857 && SET_SRC (set) == rl_reg_rtx
7858 && SET_DEST (set) == rld[s].reg_rtx)
7860 /* Usually the next instruction will be the
7861 secondary reload insn; if we can confirm
7862 that it is, setting new_spill_reg_store to
7863 that insn will allow an extra optimization. */
7864 rtx s_reg = rld[s].reg_rtx;
7865 rtx next = NEXT_INSN (p);
7866 rld[s].out = rl->out;
7867 rld[s].out_reg = rl->out_reg;
7868 set = single_set (next);
7869 if (set && SET_SRC (set) == s_reg
7870 && ! new_spill_reg_store[REGNO (s_reg)])
7872 SET_HARD_REG_BIT (reg_is_output_reload,
7874 new_spill_reg_store[REGNO (s_reg)] = next;
7878 new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7883 if (rl->when_needed == RELOAD_OTHER)
7885 emit_insn (other_output_reload_insns[rl->opnum]);
7886 other_output_reload_insns[rl->opnum] = get_insns ();
7889 output_reload_insns[rl->opnum] = get_insns ();
7891 if (cfun->can_throw_non_call_exceptions)
7892 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7897 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7898 and has the number J. */
7900 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7902 rtx insn = chain->insn;
7903 rtx old = (rl->in && MEM_P (rl->in)
7904 ? rl->in_reg : rl->in);
7905 rtx reg_rtx = rl->reg_rtx;
7909 enum machine_mode mode;
7911 /* Determine the mode to reload in.
7912 This is very tricky because we have three to choose from.
7913 There is the mode the insn operand wants (rl->inmode).
7914 There is the mode of the reload register RELOADREG.
7915 There is the intrinsic mode of the operand, which we could find
7916 by stripping some SUBREGs.
7917 It turns out that RELOADREG's mode is irrelevant:
7918 we can change that arbitrarily.
7920 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7921 then the reload reg may not support QImode moves, so use SImode.
7922 If foo is in memory due to spilling a pseudo reg, this is safe,
7923 because the QImode value is in the least significant part of a
7924 slot big enough for a SImode. If foo is some other sort of
7925 memory reference, then it is impossible to reload this case,
7926 so previous passes had better make sure this never happens.
7928 Then consider a one-word union which has SImode and one of its
7929 members is a float, being fetched as (SUBREG:SF union:SI).
7930 We must fetch that as SFmode because we could be loading into
7931 a float-only register. In this case OLD's mode is correct.
7933 Consider an immediate integer: it has VOIDmode. Here we need
7934 to get a mode from something else.
7936 In some cases, there is a fourth mode, the operand's
7937 containing mode. If the insn specifies a containing mode for
7938 this operand, it overrides all others.
7940 I am not sure whether the algorithm here is always right,
7941 but it does the right things in those cases. */
7943 mode = GET_MODE (old);
7944 if (mode == VOIDmode)
7947 /* We cannot use gen_lowpart_common since it can do the wrong thing
7948 when REG_RTX has a multi-word mode. Note that REG_RTX must
7949 always be a REG here. */
7950 if (GET_MODE (reg_rtx) != mode)
7951 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7953 reload_reg_rtx_for_input[j] = reg_rtx;
7956 /* AUTO_INC reloads need to be handled even if inherited. We got an
7957 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7958 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7959 && ! rtx_equal_p (reg_rtx, old)
7961 emit_input_reload_insns (chain, rld + j, old, j);
7963 /* When inheriting a wider reload, we have a MEM in rl->in,
7964 e.g. inheriting a SImode output reload for
7965 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7966 if (optimize && reload_inherited[j] && rl->in
7968 && MEM_P (rl->in_reg)
7969 && reload_spill_index[j] >= 0
7970 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7971 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7973 /* If we are reloading a register that was recently stored in with an
7974 output-reload, see if we can prove there was
7975 actually no need to store the old value in it. */
7978 && (reload_inherited[j] || reload_override_in[j])
7981 && spill_reg_store[REGNO (reg_rtx)] != 0
7983 /* There doesn't seem to be any reason to restrict this to pseudos
7984 and doing so loses in the case where we are copying from a
7985 register of the wrong class. */
7986 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7988 /* The insn might have already some references to stackslots
7989 replaced by MEMs, while reload_out_reg still names the
7991 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7992 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7993 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7996 /* Do output reloading for reload RL, which is for the insn described by
7997 CHAIN and has the number J.
7998 ??? At some point we need to support handling output reloads of
7999 JUMP_INSNs or insns that set cc0. */
8001 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
8004 rtx insn = chain->insn;
8005 /* If this is an output reload that stores something that is
8006 not loaded in this same reload, see if we can eliminate a previous
8008 rtx pseudo = rl->out_reg;
8009 rtx reg_rtx = rl->reg_rtx;
8011 if (rl->out && reg_rtx)
8013 enum machine_mode mode;
8015 /* Determine the mode to reload in.
8016 See comments above (for input reloading). */
8017 mode = GET_MODE (rl->out);
8018 if (mode == VOIDmode)
8020 /* VOIDmode should never happen for an output. */
8021 if (asm_noperands (PATTERN (insn)) < 0)
8022 /* It's the compiler's fault. */
8023 fatal_insn ("VOIDmode on an output", insn);
8024 error_for_asm (insn, "output operand is constant in %<asm%>");
8025 /* Prevent crash--use something we know is valid. */
8027 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
8029 if (GET_MODE (reg_rtx) != mode)
8030 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
8032 reload_reg_rtx_for_output[j] = reg_rtx;
8037 && ! rtx_equal_p (rl->in_reg, pseudo)
8038 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
8039 && reg_last_reload_reg[REGNO (pseudo)])
8041 int pseudo_no = REGNO (pseudo);
8042 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
8044 /* We don't need to test full validity of last_regno for
8045 inherit here; we only want to know if the store actually
8046 matches the pseudo. */
8047 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
8048 && reg_reloaded_contents[last_regno] == pseudo_no
8049 && spill_reg_store[last_regno]
8050 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
8051 delete_output_reload (insn, j, last_regno, reg_rtx);
8057 || rtx_equal_p (old, reg_rtx))
8060 /* An output operand that dies right away does need a reload,
8061 but need not be copied from it. Show the new location in the
8063 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
8064 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
8066 XEXP (note, 0) = reg_rtx;
8069 /* Likewise for a SUBREG of an operand that dies. */
8070 else if (GET_CODE (old) == SUBREG
8071 && REG_P (SUBREG_REG (old))
8072 && 0 != (note = find_reg_note (insn, REG_UNUSED,
8075 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
8078 else if (GET_CODE (old) == SCRATCH)
8079 /* If we aren't optimizing, there won't be a REG_UNUSED note,
8080 but we don't want to make an output reload. */
8083 /* If is a JUMP_INSN, we can't support output reloads yet. */
8084 gcc_assert (NONJUMP_INSN_P (insn));
8086 emit_output_reload_insns (chain, rld + j, j);
8089 /* A reload copies values of MODE from register SRC to register DEST.
8090 Return true if it can be treated for inheritance purposes like a
8091 group of reloads, each one reloading a single hard register. The
8092 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
8093 occupy the same number of hard registers. */
8096 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
8097 int src ATTRIBUTE_UNUSED,
8098 enum machine_mode mode ATTRIBUTE_UNUSED)
8100 #ifdef CANNOT_CHANGE_MODE_CLASS
8101 return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
8102 && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
8108 /* Output insns to reload values in and out of the chosen reload regs. */
8111 emit_reload_insns (struct insn_chain *chain)
8113 rtx insn = chain->insn;
8117 CLEAR_HARD_REG_SET (reg_reloaded_died);
8119 for (j = 0; j < reload_n_operands; j++)
8120 input_reload_insns[j] = input_address_reload_insns[j]
8121 = inpaddr_address_reload_insns[j]
8122 = output_reload_insns[j] = output_address_reload_insns[j]
8123 = outaddr_address_reload_insns[j]
8124 = other_output_reload_insns[j] = 0;
8125 other_input_address_reload_insns = 0;
8126 other_input_reload_insns = 0;
8127 operand_reload_insns = 0;
8128 other_operand_reload_insns = 0;
8130 /* Dump reloads into the dump file. */
8133 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
8134 debug_reload_to_stream (dump_file);
8137 /* Now output the instructions to copy the data into and out of the
8138 reload registers. Do these in the order that the reloads were reported,
8139 since reloads of base and index registers precede reloads of operands
8140 and the operands may need the base and index registers reloaded. */
8142 for (j = 0; j < n_reloads; j++)
8144 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
8148 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
8149 new_spill_reg_store[i] = 0;
8152 do_input_reload (chain, rld + j, j);
8153 do_output_reload (chain, rld + j, j);
8156 /* Now write all the insns we made for reloads in the order expected by
8157 the allocation functions. Prior to the insn being reloaded, we write
8158 the following reloads:
8160 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8162 RELOAD_OTHER reloads.
8164 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8165 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8166 RELOAD_FOR_INPUT reload for the operand.
8168 RELOAD_FOR_OPADDR_ADDRS reloads.
8170 RELOAD_FOR_OPERAND_ADDRESS reloads.
8172 After the insn being reloaded, we write the following:
8174 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8175 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8176 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8177 reloads for the operand. The RELOAD_OTHER output reloads are
8178 output in descending order by reload number. */
8180 emit_insn_before (other_input_address_reload_insns, insn);
8181 emit_insn_before (other_input_reload_insns, insn);
8183 for (j = 0; j < reload_n_operands; j++)
8185 emit_insn_before (inpaddr_address_reload_insns[j], insn);
8186 emit_insn_before (input_address_reload_insns[j], insn);
8187 emit_insn_before (input_reload_insns[j], insn);
8190 emit_insn_before (other_operand_reload_insns, insn);
8191 emit_insn_before (operand_reload_insns, insn);
8193 for (j = 0; j < reload_n_operands; j++)
8195 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
8196 x = emit_insn_after (output_address_reload_insns[j], x);
8197 x = emit_insn_after (output_reload_insns[j], x);
8198 emit_insn_after (other_output_reload_insns[j], x);
8201 /* For all the spill regs newly reloaded in this instruction,
8202 record what they were reloaded from, so subsequent instructions
8203 can inherit the reloads.
8205 Update spill_reg_store for the reloads of this insn.
8206 Copy the elements that were updated in the loop above. */
8208 for (j = 0; j < n_reloads; j++)
8210 int r = reload_order[j];
8211 int i = reload_spill_index[r];
8213 /* If this is a non-inherited input reload from a pseudo, we must
8214 clear any memory of a previous store to the same pseudo. Only do
8215 something if there will not be an output reload for the pseudo
8217 if (rld[r].in_reg != 0
8218 && ! (reload_inherited[r] || reload_override_in[r]))
8220 rtx reg = rld[r].in_reg;
8222 if (GET_CODE (reg) == SUBREG)
8223 reg = SUBREG_REG (reg);
8226 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
8227 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
8229 int nregno = REGNO (reg);
8231 if (reg_last_reload_reg[nregno])
8233 int last_regno = REGNO (reg_last_reload_reg[nregno]);
8235 if (reg_reloaded_contents[last_regno] == nregno)
8236 spill_reg_store[last_regno] = 0;
8241 /* I is nonneg if this reload used a register.
8242 If rld[r].reg_rtx is 0, this is an optional reload
8243 that we opted to ignore. */
8245 if (i >= 0 && rld[r].reg_rtx != 0)
8247 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
8250 /* For a multi register reload, we need to check if all or part
8251 of the value lives to the end. */
8252 for (k = 0; k < nr; k++)
8253 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
8254 rld[r].when_needed))
8255 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
8257 /* Maybe the spill reg contains a copy of reload_out. */
8259 && (REG_P (rld[r].out)
8263 || REG_P (rld[r].out_reg)))
8266 enum machine_mode mode;
8269 reg = reload_reg_rtx_for_output[r];
8270 mode = GET_MODE (reg);
8271 regno = REGNO (reg);
8272 nregs = hard_regno_nregs[regno][mode];
8273 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
8274 rld[r].when_needed))
8276 rtx out = (REG_P (rld[r].out)
8280 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
8281 int out_regno = REGNO (out);
8282 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
8283 : hard_regno_nregs[out_regno][mode]);
8286 spill_reg_store[regno] = new_spill_reg_store[regno];
8287 spill_reg_stored_to[regno] = out;
8288 reg_last_reload_reg[out_regno] = reg;
8290 piecemeal = (HARD_REGISTER_NUM_P (out_regno)
8291 && nregs == out_nregs
8292 && inherit_piecemeal_p (out_regno, regno, mode));
8294 /* If OUT_REGNO is a hard register, it may occupy more than
8295 one register. If it does, say what is in the
8296 rest of the registers assuming that both registers
8297 agree on how many words the object takes. If not,
8298 invalidate the subsequent registers. */
8300 if (HARD_REGISTER_NUM_P (out_regno))
8301 for (k = 1; k < out_nregs; k++)
8302 reg_last_reload_reg[out_regno + k]
8303 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8305 /* Now do the inverse operation. */
8306 for (k = 0; k < nregs; k++)
8308 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8309 reg_reloaded_contents[regno + k]
8310 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
8313 reg_reloaded_insn[regno + k] = insn;
8314 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8315 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8316 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8319 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8324 /* Maybe the spill reg contains a copy of reload_in. Only do
8325 something if there will not be an output reload for
8326 the register being reloaded. */
8327 else if (rld[r].out_reg == 0
8329 && ((REG_P (rld[r].in)
8330 && !HARD_REGISTER_P (rld[r].in)
8331 && !REGNO_REG_SET_P (®_has_output_reload,
8333 || (REG_P (rld[r].in_reg)
8334 && !REGNO_REG_SET_P (®_has_output_reload,
8335 REGNO (rld[r].in_reg))))
8336 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
8339 enum machine_mode mode;
8342 reg = reload_reg_rtx_for_input[r];
8343 mode = GET_MODE (reg);
8344 regno = REGNO (reg);
8345 nregs = hard_regno_nregs[regno][mode];
8346 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
8347 rld[r].when_needed))
8354 if (REG_P (rld[r].in)
8355 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
8357 else if (REG_P (rld[r].in_reg))
8360 in = XEXP (rld[r].in_reg, 0);
8361 in_regno = REGNO (in);
8363 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
8364 : hard_regno_nregs[in_regno][mode]);
8366 reg_last_reload_reg[in_regno] = reg;
8368 piecemeal = (HARD_REGISTER_NUM_P (in_regno)
8369 && nregs == in_nregs
8370 && inherit_piecemeal_p (regno, in_regno, mode));
8372 if (HARD_REGISTER_NUM_P (in_regno))
8373 for (k = 1; k < in_nregs; k++)
8374 reg_last_reload_reg[in_regno + k]
8375 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8377 /* Unless we inherited this reload, show we haven't
8378 recently done a store.
8379 Previous stores of inherited auto_inc expressions
8380 also have to be discarded. */
8381 if (! reload_inherited[r]
8382 || (rld[r].out && ! rld[r].out_reg))
8383 spill_reg_store[regno] = 0;
8385 for (k = 0; k < nregs; k++)
8387 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8388 reg_reloaded_contents[regno + k]
8389 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
8392 reg_reloaded_insn[regno + k] = insn;
8393 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8394 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8395 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8398 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8405 /* The following if-statement was #if 0'd in 1.34 (or before...).
8406 It's reenabled in 1.35 because supposedly nothing else
8407 deals with this problem. */
8409 /* If a register gets output-reloaded from a non-spill register,
8410 that invalidates any previous reloaded copy of it.
8411 But forget_old_reloads_1 won't get to see it, because
8412 it thinks only about the original insn. So invalidate it here.
8413 Also do the same thing for RELOAD_OTHER constraints where the
8414 output is discarded. */
8416 && ((rld[r].out != 0
8417 && (REG_P (rld[r].out)
8418 || (MEM_P (rld[r].out)
8419 && REG_P (rld[r].out_reg))))
8420 || (rld[r].out == 0 && rld[r].out_reg
8421 && REG_P (rld[r].out_reg))))
8423 rtx out = ((rld[r].out && REG_P (rld[r].out))
8424 ? rld[r].out : rld[r].out_reg);
8425 int out_regno = REGNO (out);
8426 enum machine_mode mode = GET_MODE (out);
8428 /* REG_RTX is now set or clobbered by the main instruction.
8429 As the comment above explains, forget_old_reloads_1 only
8430 sees the original instruction, and there is no guarantee
8431 that the original instruction also clobbered REG_RTX.
8432 For example, if find_reloads sees that the input side of
8433 a matched operand pair dies in this instruction, it may
8434 use the input register as the reload register.
8436 Calling forget_old_reloads_1 is a waste of effort if
8437 REG_RTX is also the output register.
8439 If we know that REG_RTX holds the value of a pseudo
8440 register, the code after the call will record that fact. */
8441 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8442 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8444 if (!HARD_REGISTER_NUM_P (out_regno))
8446 rtx src_reg, store_insn = NULL_RTX;
8448 reg_last_reload_reg[out_regno] = 0;
8450 /* If we can find a hard register that is stored, record
8451 the storing insn so that we may delete this insn with
8452 delete_output_reload. */
8453 src_reg = reload_reg_rtx_for_output[r];
8455 /* If this is an optional reload, try to find the source reg
8456 from an input reload. */
8459 rtx set = single_set (insn);
8460 if (set && SET_DEST (set) == rld[r].out)
8464 src_reg = SET_SRC (set);
8466 for (k = 0; k < n_reloads; k++)
8468 if (rld[k].in == src_reg)
8470 src_reg = reload_reg_rtx_for_input[k];
8477 store_insn = new_spill_reg_store[REGNO (src_reg)];
8478 if (src_reg && REG_P (src_reg)
8479 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8481 int src_regno, src_nregs, k;
8484 gcc_assert (GET_MODE (src_reg) == mode);
8485 src_regno = REGNO (src_reg);
8486 src_nregs = hard_regno_nregs[src_regno][mode];
8487 /* The place where to find a death note varies with
8488 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8489 necessarily checked exactly in the code that moves
8490 notes, so just check both locations. */
8491 note = find_regno_note (insn, REG_DEAD, src_regno);
8492 if (! note && store_insn)
8493 note = find_regno_note (store_insn, REG_DEAD, src_regno);
8494 for (k = 0; k < src_nregs; k++)
8496 spill_reg_store[src_regno + k] = store_insn;
8497 spill_reg_stored_to[src_regno + k] = out;
8498 reg_reloaded_contents[src_regno + k] = out_regno;
8499 reg_reloaded_insn[src_regno + k] = store_insn;
8500 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8501 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8502 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
8504 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8507 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8509 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8511 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8513 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8515 reg_last_reload_reg[out_regno] = src_reg;
8516 /* We have to set reg_has_output_reload here, or else
8517 forget_old_reloads_1 will clear reg_last_reload_reg
8519 SET_REGNO_REG_SET (®_has_output_reload,
8525 int k, out_nregs = hard_regno_nregs[out_regno][mode];
8527 for (k = 0; k < out_nregs; k++)
8528 reg_last_reload_reg[out_regno + k] = 0;
8532 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
8535 /* Go through the motions to emit INSN and test if it is strictly valid.
8536 Return the emitted insn if valid, else return NULL. */
8539 emit_insn_if_valid_for_reload (rtx insn)
8541 rtx last = get_last_insn ();
8544 insn = emit_insn (insn);
8545 code = recog_memoized (insn);
8549 extract_insn (insn);
8550 /* We want constrain operands to treat this insn strictly in its
8551 validity determination, i.e., the way it would after reload has
8553 if (constrain_operands (1))
8557 delete_insns_since (last);
8561 /* Emit code to perform a reload from IN (which may be a reload register) to
8562 OUT (which may also be a reload register). IN or OUT is from operand
8563 OPNUM with reload type TYPE.
8565 Returns first insn emitted. */
8568 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8570 rtx last = get_last_insn ();
8573 /* If IN is a paradoxical SUBREG, remove it and try to put the
8574 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8575 if (GET_CODE (in) == SUBREG
8576 && (GET_MODE_SIZE (GET_MODE (in))
8577 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
8578 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
8579 in = SUBREG_REG (in), out = tem;
8580 else if (GET_CODE (out) == SUBREG
8581 && (GET_MODE_SIZE (GET_MODE (out))
8582 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
8583 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
8584 out = SUBREG_REG (out), in = tem;
8586 /* How to do this reload can get quite tricky. Normally, we are being
8587 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8588 register that didn't get a hard register. In that case we can just
8589 call emit_move_insn.
8591 We can also be asked to reload a PLUS that adds a register or a MEM to
8592 another register, constant or MEM. This can occur during frame pointer
8593 elimination and while reloading addresses. This case is handled by
8594 trying to emit a single insn to perform the add. If it is not valid,
8595 we use a two insn sequence.
8597 Or we can be asked to reload an unary operand that was a fragment of
8598 an addressing mode, into a register. If it isn't recognized as-is,
8599 we try making the unop operand and the reload-register the same:
8600 (set reg:X (unop:X expr:Y))
8601 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8603 Finally, we could be called to handle an 'o' constraint by putting
8604 an address into a register. In that case, we first try to do this
8605 with a named pattern of "reload_load_address". If no such pattern
8606 exists, we just emit a SET insn and hope for the best (it will normally
8607 be valid on machines that use 'o').
8609 This entire process is made complex because reload will never
8610 process the insns we generate here and so we must ensure that
8611 they will fit their constraints and also by the fact that parts of
8612 IN might be being reloaded separately and replaced with spill registers.
8613 Because of this, we are, in some sense, just guessing the right approach
8614 here. The one listed above seems to work.
8616 ??? At some point, this whole thing needs to be rethought. */
8618 if (GET_CODE (in) == PLUS
8619 && (REG_P (XEXP (in, 0))
8620 || GET_CODE (XEXP (in, 0)) == SUBREG
8621 || MEM_P (XEXP (in, 0)))
8622 && (REG_P (XEXP (in, 1))
8623 || GET_CODE (XEXP (in, 1)) == SUBREG
8624 || CONSTANT_P (XEXP (in, 1))
8625 || MEM_P (XEXP (in, 1))))
8627 /* We need to compute the sum of a register or a MEM and another
8628 register, constant, or MEM, and put it into the reload
8629 register. The best possible way of doing this is if the machine
8630 has a three-operand ADD insn that accepts the required operands.
8632 The simplest approach is to try to generate such an insn and see if it
8633 is recognized and matches its constraints. If so, it can be used.
8635 It might be better not to actually emit the insn unless it is valid,
8636 but we need to pass the insn as an operand to `recog' and
8637 `extract_insn' and it is simpler to emit and then delete the insn if
8638 not valid than to dummy things up. */
8640 rtx op0, op1, tem, insn;
8643 op0 = find_replacement (&XEXP (in, 0));
8644 op1 = find_replacement (&XEXP (in, 1));
8646 /* Since constraint checking is strict, commutativity won't be
8647 checked, so we need to do that here to avoid spurious failure
8648 if the add instruction is two-address and the second operand
8649 of the add is the same as the reload reg, which is frequently
8650 the case. If the insn would be A = B + A, rearrange it so
8651 it will be A = A + B as constrain_operands expects. */
8653 if (REG_P (XEXP (in, 1))
8654 && REGNO (out) == REGNO (XEXP (in, 1)))
8655 tem = op0, op0 = op1, op1 = tem;
8657 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8658 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8660 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8664 /* If that failed, we must use a conservative two-insn sequence.
8666 Use a move to copy one operand into the reload register. Prefer
8667 to reload a constant, MEM or pseudo since the move patterns can
8668 handle an arbitrary operand. If OP1 is not a constant, MEM or
8669 pseudo and OP1 is not a valid operand for an add instruction, then
8672 After reloading one of the operands into the reload register, add
8673 the reload register to the output register.
8675 If there is another way to do this for a specific machine, a
8676 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8679 code = (int) optab_handler (add_optab, GET_MODE (out))->insn_code;
8681 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8683 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8684 || (code != CODE_FOR_nothing
8685 && ! ((*insn_data[code].operand[2].predicate)
8686 (op1, insn_data[code].operand[2].mode))))
8687 tem = op0, op0 = op1, op1 = tem;
8689 gen_reload (out, op0, opnum, type);
8691 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8692 This fixes a problem on the 32K where the stack pointer cannot
8693 be used as an operand of an add insn. */
8695 if (rtx_equal_p (op0, op1))
8698 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8701 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8702 set_unique_reg_note (insn, REG_EQUIV, in);
8706 /* If that failed, copy the address register to the reload register.
8707 Then add the constant to the reload register. */
8709 gcc_assert (!reg_overlap_mentioned_p (out, op0));
8710 gen_reload (out, op1, opnum, type);
8711 insn = emit_insn (gen_add2_insn (out, op0));
8712 set_unique_reg_note (insn, REG_EQUIV, in);
8715 #ifdef SECONDARY_MEMORY_NEEDED
8716 /* If we need a memory location to do the move, do it that way. */
8717 else if ((REG_P (in)
8718 || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))))
8719 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
8721 || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out))))
8722 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
8723 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
8724 REGNO_REG_CLASS (reg_or_subregno (out)),
8727 /* Get the memory to use and rewrite both registers to its mode. */
8728 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8730 if (GET_MODE (loc) != GET_MODE (out))
8731 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
8733 if (GET_MODE (loc) != GET_MODE (in))
8734 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
8736 gen_reload (loc, in, opnum, type);
8737 gen_reload (out, loc, opnum, type);
8740 else if (REG_P (out) && UNARY_P (in))
8747 op1 = find_replacement (&XEXP (in, 0));
8748 if (op1 != XEXP (in, 0))
8749 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8751 /* First, try a plain SET. */
8752 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8756 /* If that failed, move the inner operand to the reload
8757 register, and try the same unop with the inner expression
8758 replaced with the reload register. */
8760 if (GET_MODE (op1) != GET_MODE (out))
8761 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8765 gen_reload (out_moded, op1, opnum, type);
8768 = gen_rtx_SET (VOIDmode, out,
8769 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8771 insn = emit_insn_if_valid_for_reload (insn);
8774 set_unique_reg_note (insn, REG_EQUIV, in);
8778 fatal_insn ("Failure trying to reload:", set);
8780 /* If IN is a simple operand, use gen_move_insn. */
8781 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8783 tem = emit_insn (gen_move_insn (out, in));
8784 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8785 mark_jump_label (in, tem, 0);
8788 #ifdef HAVE_reload_load_address
8789 else if (HAVE_reload_load_address)
8790 emit_insn (gen_reload_load_address (out, in));
8793 /* Otherwise, just write (set OUT IN) and hope for the best. */
8795 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8797 /* Return the first insn emitted.
8798 We can not just return get_last_insn, because there may have
8799 been multiple instructions emitted. Also note that gen_move_insn may
8800 emit more than one insn itself, so we can not assume that there is one
8801 insn emitted per emit_insn_before call. */
8803 return last ? NEXT_INSN (last) : get_insns ();
8806 /* Delete a previously made output-reload whose result we now believe
8807 is not needed. First we double-check.
8809 INSN is the insn now being processed.
8810 LAST_RELOAD_REG is the hard register number for which we want to delete
8811 the last output reload.
8812 J is the reload-number that originally used REG. The caller has made
8813 certain that reload J doesn't use REG any longer for input.
8814 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8817 delete_output_reload (rtx insn, int j, int last_reload_reg, rtx new_reload_reg)
8819 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8820 rtx reg = spill_reg_stored_to[last_reload_reg];
8823 int n_inherited = 0;
8827 /* It is possible that this reload has been only used to set another reload
8828 we eliminated earlier and thus deleted this instruction too. */
8829 if (INSN_DELETED_P (output_reload_insn))
8832 /* Get the raw pseudo-register referred to. */
8834 while (GET_CODE (reg) == SUBREG)
8835 reg = SUBREG_REG (reg);
8836 substed = reg_equiv_memory_loc[REGNO (reg)];
8838 /* This is unsafe if the operand occurs more often in the current
8839 insn than it is inherited. */
8840 for (k = n_reloads - 1; k >= 0; k--)
8842 rtx reg2 = rld[k].in;
8845 if (MEM_P (reg2) || reload_override_in[k])
8846 reg2 = rld[k].in_reg;
8848 if (rld[k].out && ! rld[k].out_reg)
8849 reg2 = XEXP (rld[k].in_reg, 0);
8851 while (GET_CODE (reg2) == SUBREG)
8852 reg2 = SUBREG_REG (reg2);
8853 if (rtx_equal_p (reg2, reg))
8855 if (reload_inherited[k] || reload_override_in[k] || k == j)
8861 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8862 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8863 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8866 n_occurrences += count_occurrences (PATTERN (insn),
8867 eliminate_regs (substed, VOIDmode,
8869 for (i1 = reg_equiv_alt_mem_list[REGNO (reg)]; i1; i1 = XEXP (i1, 1))
8871 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8872 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8874 if (n_occurrences > n_inherited)
8877 /* If the pseudo-reg we are reloading is no longer referenced
8878 anywhere between the store into it and here,
8879 and we're within the same basic block, then the value can only
8880 pass through the reload reg and end up here.
8881 Otherwise, give up--return. */
8882 for (i1 = NEXT_INSN (output_reload_insn);
8883 i1 != insn; i1 = NEXT_INSN (i1))
8885 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8887 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8888 && reg_mentioned_p (reg, PATTERN (i1)))
8890 /* If this is USE in front of INSN, we only have to check that
8891 there are no more references than accounted for by inheritance. */
8892 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8894 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8895 i1 = NEXT_INSN (i1);
8897 if (n_occurrences <= n_inherited && i1 == insn)
8903 /* We will be deleting the insn. Remove the spill reg information. */
8904 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8906 spill_reg_store[last_reload_reg + k] = 0;
8907 spill_reg_stored_to[last_reload_reg + k] = 0;
8910 /* The caller has already checked that REG dies or is set in INSN.
8911 It has also checked that we are optimizing, and thus some
8912 inaccuracies in the debugging information are acceptable.
8913 So we could just delete output_reload_insn. But in some cases
8914 we can improve the debugging information without sacrificing
8915 optimization - maybe even improving the code: See if the pseudo
8916 reg has been completely replaced with reload regs. If so, delete
8917 the store insn and forget we had a stack slot for the pseudo. */
8918 if (rld[j].out != rld[j].in
8919 && REG_N_DEATHS (REGNO (reg)) == 1
8920 && REG_N_SETS (REGNO (reg)) == 1
8921 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8922 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8926 /* We know that it was used only between here and the beginning of
8927 the current basic block. (We also know that the last use before
8928 INSN was the output reload we are thinking of deleting, but never
8929 mind that.) Search that range; see if any ref remains. */
8930 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8932 rtx set = single_set (i2);
8934 /* Uses which just store in the pseudo don't count,
8935 since if they are the only uses, they are dead. */
8936 if (set != 0 && SET_DEST (set) == reg)
8941 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8942 && reg_mentioned_p (reg, PATTERN (i2)))
8944 /* Some other ref remains; just delete the output reload we
8946 delete_address_reloads (output_reload_insn, insn);
8947 delete_insn (output_reload_insn);
8952 /* Delete the now-dead stores into this pseudo. Note that this
8953 loop also takes care of deleting output_reload_insn. */
8954 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8956 rtx set = single_set (i2);
8958 if (set != 0 && SET_DEST (set) == reg)
8960 delete_address_reloads (i2, insn);
8968 /* For the debugging info, say the pseudo lives in this reload reg. */
8969 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8970 if (ira_conflicts_p)
8971 /* Inform IRA about the change. */
8972 ira_mark_allocation_change (REGNO (reg));
8973 alter_reg (REGNO (reg), -1, false);
8977 delete_address_reloads (output_reload_insn, insn);
8978 delete_insn (output_reload_insn);
8982 /* We are going to delete DEAD_INSN. Recursively delete loads of
8983 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8984 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8986 delete_address_reloads (rtx dead_insn, rtx current_insn)
8988 rtx set = single_set (dead_insn);
8989 rtx set2, dst, prev, next;
8992 rtx dst = SET_DEST (set);
8994 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8996 /* If we deleted the store from a reloaded post_{in,de}c expression,
8997 we can delete the matching adds. */
8998 prev = PREV_INSN (dead_insn);
8999 next = NEXT_INSN (dead_insn);
9000 if (! prev || ! next)
9002 set = single_set (next);
9003 set2 = single_set (prev);
9005 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
9006 || !CONST_INT_P (XEXP (SET_SRC (set), 1))
9007 || !CONST_INT_P (XEXP (SET_SRC (set2), 1)))
9009 dst = SET_DEST (set);
9010 if (! rtx_equal_p (dst, SET_DEST (set2))
9011 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
9012 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
9013 || (INTVAL (XEXP (SET_SRC (set), 1))
9014 != -INTVAL (XEXP (SET_SRC (set2), 1))))
9016 delete_related_insns (prev);
9017 delete_related_insns (next);
9020 /* Subfunction of delete_address_reloads: process registers found in X. */
9022 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
9024 rtx prev, set, dst, i2;
9026 enum rtx_code code = GET_CODE (x);
9030 const char *fmt = GET_RTX_FORMAT (code);
9031 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9034 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
9035 else if (fmt[i] == 'E')
9037 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9038 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
9045 if (spill_reg_order[REGNO (x)] < 0)
9048 /* Scan backwards for the insn that sets x. This might be a way back due
9050 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
9052 code = GET_CODE (prev);
9053 if (code == CODE_LABEL || code == JUMP_INSN)
9057 if (reg_set_p (x, PATTERN (prev)))
9059 if (reg_referenced_p (x, PATTERN (prev)))
9062 if (! prev || INSN_UID (prev) < reload_first_uid)
9064 /* Check that PREV only sets the reload register. */
9065 set = single_set (prev);
9068 dst = SET_DEST (set);
9070 || ! rtx_equal_p (dst, x))
9072 if (! reg_set_p (dst, PATTERN (dead_insn)))
9074 /* Check if DST was used in a later insn -
9075 it might have been inherited. */
9076 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
9082 if (reg_referenced_p (dst, PATTERN (i2)))
9084 /* If there is a reference to the register in the current insn,
9085 it might be loaded in a non-inherited reload. If no other
9086 reload uses it, that means the register is set before
9088 if (i2 == current_insn)
9090 for (j = n_reloads - 1; j >= 0; j--)
9091 if ((rld[j].reg_rtx == dst && reload_inherited[j])
9092 || reload_override_in[j] == dst)
9094 for (j = n_reloads - 1; j >= 0; j--)
9095 if (rld[j].in && rld[j].reg_rtx == dst)
9104 /* If DST is still live at CURRENT_INSN, check if it is used for
9105 any reload. Note that even if CURRENT_INSN sets DST, we still
9106 have to check the reloads. */
9107 if (i2 == current_insn)
9109 for (j = n_reloads - 1; j >= 0; j--)
9110 if ((rld[j].reg_rtx == dst && reload_inherited[j])
9111 || reload_override_in[j] == dst)
9113 /* ??? We can't finish the loop here, because dst might be
9114 allocated to a pseudo in this block if no reload in this
9115 block needs any of the classes containing DST - see
9116 spill_hard_reg. There is no easy way to tell this, so we
9117 have to scan till the end of the basic block. */
9119 if (reg_set_p (dst, PATTERN (i2)))
9123 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
9124 reg_reloaded_contents[REGNO (dst)] = -1;
9128 /* Output reload-insns to reload VALUE into RELOADREG.
9129 VALUE is an autoincrement or autodecrement RTX whose operand
9130 is a register or memory location;
9131 so reloading involves incrementing that location.
9132 IN is either identical to VALUE, or some cheaper place to reload from.
9134 INC_AMOUNT is the number to increment or decrement by (always positive).
9135 This cannot be deduced from VALUE.
9137 Return the instruction that stores into RELOADREG. */
9140 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
9142 /* REG or MEM to be copied and incremented. */
9143 rtx incloc = find_replacement (&XEXP (value, 0));
9144 /* Nonzero if increment after copying. */
9145 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
9146 || GET_CODE (value) == POST_MODIFY);
9152 rtx real_in = in == value ? incloc : in;
9154 /* No hard register is equivalent to this register after
9155 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
9156 we could inc/dec that register as well (maybe even using it for
9157 the source), but I'm not sure it's worth worrying about. */
9159 reg_last_reload_reg[REGNO (incloc)] = 0;
9161 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
9163 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
9164 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
9168 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
9169 inc_amount = -inc_amount;
9171 inc = GEN_INT (inc_amount);
9174 /* If this is post-increment, first copy the location to the reload reg. */
9175 if (post && real_in != reloadreg)
9176 emit_insn (gen_move_insn (reloadreg, real_in));
9180 /* See if we can directly increment INCLOC. Use a method similar to
9181 that in gen_reload. */
9183 last = get_last_insn ();
9184 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
9185 gen_rtx_PLUS (GET_MODE (incloc),
9188 code = recog_memoized (add_insn);
9191 extract_insn (add_insn);
9192 if (constrain_operands (1))
9194 /* If this is a pre-increment and we have incremented the value
9195 where it lives, copy the incremented value to RELOADREG to
9196 be used as an address. */
9199 emit_insn (gen_move_insn (reloadreg, incloc));
9204 delete_insns_since (last);
9207 /* If couldn't do the increment directly, must increment in RELOADREG.
9208 The way we do this depends on whether this is pre- or post-increment.
9209 For pre-increment, copy INCLOC to the reload register, increment it
9210 there, then save back. */
9214 if (in != reloadreg)
9215 emit_insn (gen_move_insn (reloadreg, real_in));
9216 emit_insn (gen_add2_insn (reloadreg, inc));
9217 store = emit_insn (gen_move_insn (incloc, reloadreg));
9222 Because this might be a jump insn or a compare, and because RELOADREG
9223 may not be available after the insn in an input reload, we must do
9224 the incrementation before the insn being reloaded for.
9226 We have already copied IN to RELOADREG. Increment the copy in
9227 RELOADREG, save that back, then decrement RELOADREG so it has
9228 the original value. */
9230 emit_insn (gen_add2_insn (reloadreg, inc));
9231 store = emit_insn (gen_move_insn (incloc, reloadreg));
9232 if (CONST_INT_P (inc))
9233 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
9235 emit_insn (gen_sub2_insn (reloadreg, inc));
9243 add_auto_inc_notes (rtx insn, rtx x)
9245 enum rtx_code code = GET_CODE (x);
9249 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9251 add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
9255 /* Scan all the operand sub-expressions. */
9256 fmt = GET_RTX_FORMAT (code);
9257 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9260 add_auto_inc_notes (insn, XEXP (x, i));
9261 else if (fmt[i] == 'E')
9262 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9263 add_auto_inc_notes (insn, XVECEXP (x, i, j));
9268 /* This is used by reload pass, that does emit some instructions after
9269 abnormal calls moving basic block end, but in fact it wants to emit
9270 them on the edge. Looks for abnormal call edges, find backward the
9271 proper call and fix the damage.
9273 Similar handle instructions throwing exceptions internally. */
9275 fixup_abnormal_edges (void)
9277 bool inserted = false;
9285 /* Look for cases we are interested in - calls or instructions causing
9287 FOR_EACH_EDGE (e, ei, bb->succs)
9289 if (e->flags & EDGE_ABNORMAL_CALL)
9291 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
9292 == (EDGE_ABNORMAL | EDGE_EH))
9295 if (e && !CALL_P (BB_END (bb))
9296 && !can_throw_internal (BB_END (bb)))
9300 /* Get past the new insns generated. Allow notes, as the insns
9301 may be already deleted. */
9303 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
9304 && !can_throw_internal (insn)
9305 && insn != BB_HEAD (bb))
9306 insn = PREV_INSN (insn);
9308 if (CALL_P (insn) || can_throw_internal (insn))
9312 stop = NEXT_INSN (BB_END (bb));
9314 insn = NEXT_INSN (insn);
9316 FOR_EACH_EDGE (e, ei, bb->succs)
9317 if (e->flags & EDGE_FALLTHRU)
9320 while (insn && insn != stop)
9322 next = NEXT_INSN (insn);
9327 /* Sometimes there's still the return value USE.
9328 If it's placed after a trapping call (i.e. that
9329 call is the last insn anyway), we have no fallthru
9330 edge. Simply delete this use and don't try to insert
9331 on the non-existent edge. */
9332 if (GET_CODE (PATTERN (insn)) != USE)
9334 /* We're not deleting it, we're moving it. */
9335 INSN_DELETED_P (insn) = 0;
9336 PREV_INSN (insn) = NULL_RTX;
9337 NEXT_INSN (insn) = NULL_RTX;
9339 insert_insn_on_edge (insn, e);
9343 else if (!BARRIER_P (insn))
9344 set_block_for_insn (insn, NULL);
9349 /* It may be that we don't find any such trapping insn. In this
9350 case we discovered quite late that the insn that had been
9351 marked as can_throw_internal in fact couldn't trap at all.
9352 So we should in fact delete the EH edges out of the block. */
9354 purge_dead_edges (bb);
9358 /* We've possibly turned single trapping insn into multiple ones. */
9359 if (cfun->can_throw_non_call_exceptions)
9362 blocks = sbitmap_alloc (last_basic_block);
9363 sbitmap_ones (blocks);
9364 find_many_sub_basic_blocks (blocks);
9365 sbitmap_free (blocks);
9369 commit_edge_insertions ();
9371 #ifdef ENABLE_CHECKING
9372 /* Verify that we didn't turn one trapping insn into many, and that
9373 we found and corrected all of the problems wrt fixups on the
9375 verify_flow_info ();
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