1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx *reg_equiv_memory_loc;
105 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
106 collector can keep track of what is inside. */
107 varray_type reg_equiv_memory_loc_varray;
109 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
110 This is used when the address is not valid as a memory address
111 (because its displacement is too big for the machine.) */
112 rtx *reg_equiv_address;
114 /* Element N is the memory slot to which pseudo reg N is equivalent,
115 or zero if pseudo reg N is not equivalent to a memory slot. */
118 /* Widest width in which each pseudo reg is referred to (via subreg). */
119 static unsigned int *reg_max_ref_width;
121 /* Element N is the list of insns that initialized reg N from its equivalent
122 constant or memory slot. */
123 static rtx *reg_equiv_init;
125 /* Vector to remember old contents of reg_renumber before spilling. */
126 static short *reg_old_renumber;
128 /* During reload_as_needed, element N contains the last pseudo regno reloaded
129 into hard register N. If that pseudo reg occupied more than one register,
130 reg_reloaded_contents points to that pseudo for each spill register in
131 use; all of these must remain set for an inheritance to occur. */
132 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
134 /* During reload_as_needed, element N contains the insn for which
135 hard register N was last used. Its contents are significant only
136 when reg_reloaded_valid is set for this register. */
137 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
139 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
140 static HARD_REG_SET reg_reloaded_valid;
141 /* Indicate if the register was dead at the end of the reload.
142 This is only valid if reg_reloaded_contents is set and valid. */
143 static HARD_REG_SET reg_reloaded_dead;
145 /* Indicate whether the register's current value is one that is not
146 safe to retain across a call, even for registers that are normally
148 static HARD_REG_SET reg_reloaded_call_part_clobbered;
150 /* Number of spill-regs so far; number of valid elements of spill_regs. */
153 /* In parallel with spill_regs, contains REG rtx's for those regs.
154 Holds the last rtx used for any given reg, or 0 if it has never
155 been used for spilling yet. This rtx is reused, provided it has
157 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
159 /* In parallel with spill_regs, contains nonzero for a spill reg
160 that was stored after the last time it was used.
161 The precise value is the insn generated to do the store. */
162 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
164 /* This is the register that was stored with spill_reg_store. This is a
165 copy of reload_out / reload_out_reg when the value was stored; if
166 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
167 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
169 /* This table is the inverse mapping of spill_regs:
170 indexed by hard reg number,
171 it contains the position of that reg in spill_regs,
172 or -1 for something that is not in spill_regs.
174 ?!? This is no longer accurate. */
175 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
177 /* This reg set indicates registers that can't be used as spill registers for
178 the currently processed insn. These are the hard registers which are live
179 during the insn, but not allocated to pseudos, as well as fixed
181 static HARD_REG_SET bad_spill_regs;
183 /* These are the hard registers that can't be used as spill register for any
184 insn. This includes registers used for user variables and registers that
185 we can't eliminate. A register that appears in this set also can't be used
186 to retry register allocation. */
187 static HARD_REG_SET bad_spill_regs_global;
189 /* Describes order of use of registers for reloading
190 of spilled pseudo-registers. `n_spills' is the number of
191 elements that are actually valid; new ones are added at the end.
193 Both spill_regs and spill_reg_order are used on two occasions:
194 once during find_reload_regs, where they keep track of the spill registers
195 for a single insn, but also during reload_as_needed where they show all
196 the registers ever used by reload. For the latter case, the information
197 is calculated during finish_spills. */
198 static short spill_regs[FIRST_PSEUDO_REGISTER];
200 /* This vector of reg sets indicates, for each pseudo, which hard registers
201 may not be used for retrying global allocation because the register was
202 formerly spilled from one of them. If we allowed reallocating a pseudo to
203 a register that it was already allocated to, reload might not
205 static HARD_REG_SET *pseudo_previous_regs;
207 /* This vector of reg sets indicates, for each pseudo, which hard
208 registers may not be used for retrying global allocation because they
209 are used as spill registers during one of the insns in which the
211 static HARD_REG_SET *pseudo_forbidden_regs;
213 /* All hard regs that have been used as spill registers for any insn are
214 marked in this set. */
215 static HARD_REG_SET used_spill_regs;
217 /* Index of last register assigned as a spill register. We allocate in
218 a round-robin fashion. */
219 static int last_spill_reg;
221 /* Nonzero if indirect addressing is supported on the machine; this means
222 that spilling (REG n) does not require reloading it into a register in
223 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
224 value indicates the level of indirect addressing supported, e.g., two
225 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
227 static char spill_indirect_levels;
229 /* Nonzero if indirect addressing is supported when the innermost MEM is
230 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
231 which these are valid is the same as spill_indirect_levels, above. */
232 char indirect_symref_ok;
234 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
235 char double_reg_address_ok;
237 /* Record the stack slot for each spilled hard register. */
238 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
240 /* Width allocated so far for that stack slot. */
241 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
243 /* Record which pseudos needed to be spilled. */
244 static regset_head spilled_pseudos;
246 /* Used for communication between order_regs_for_reload and count_pseudo.
247 Used to avoid counting one pseudo twice. */
248 static regset_head pseudos_counted;
250 /* First uid used by insns created by reload in this function.
251 Used in find_equiv_reg. */
252 int reload_first_uid;
254 /* Flag set by local-alloc or global-alloc if anything is live in
255 a call-clobbered reg across calls. */
256 int caller_save_needed;
258 /* Set to 1 while reload_as_needed is operating.
259 Required by some machines to handle any generated moves differently. */
260 int reload_in_progress = 0;
262 /* These arrays record the insn_code of insns that may be needed to
263 perform input and output reloads of special objects. They provide a
264 place to pass a scratch register. */
265 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
266 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
268 /* This obstack is used for allocation of rtl during register elimination.
269 The allocated storage can be freed once find_reloads has processed the
271 struct obstack reload_obstack;
273 /* Points to the beginning of the reload_obstack. All insn_chain structures
274 are allocated first. */
275 char *reload_startobj;
277 /* The point after all insn_chain structures. Used to quickly deallocate
278 memory allocated in copy_reloads during calculate_needs_all_insns. */
279 char *reload_firstobj;
281 /* This points before all local rtl generated by register elimination.
282 Used to quickly free all memory after processing one insn. */
283 static char *reload_insn_firstobj;
285 /* List of insn_chain instructions, one for every insn that reload needs to
287 struct insn_chain *reload_insn_chain;
289 /* List of all insns needing reloads. */
290 static struct insn_chain *insns_need_reload;
292 /* This structure is used to record information about register eliminations.
293 Each array entry describes one possible way of eliminating a register
294 in favor of another. If there is more than one way of eliminating a
295 particular register, the most preferred should be specified first. */
299 int from; /* Register number to be eliminated. */
300 int to; /* Register number used as replacement. */
301 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
302 int can_eliminate; /* Nonzero if this elimination can be done. */
303 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
304 insns made by reload. */
305 HOST_WIDE_INT offset; /* Current offset between the two regs. */
306 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
307 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
308 rtx from_rtx; /* REG rtx for the register to be eliminated.
309 We cannot simply compare the number since
310 we might then spuriously replace a hard
311 register corresponding to a pseudo
312 assigned to the reg to be eliminated. */
313 rtx to_rtx; /* REG rtx for the replacement. */
316 static struct elim_table *reg_eliminate = 0;
318 /* This is an intermediate structure to initialize the table. It has
319 exactly the members provided by ELIMINABLE_REGS. */
320 static const struct elim_table_1
324 } reg_eliminate_1[] =
326 /* If a set of eliminable registers was specified, define the table from it.
327 Otherwise, default to the normal case of the frame pointer being
328 replaced by the stack pointer. */
330 #ifdef ELIMINABLE_REGS
333 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
336 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
338 /* Record the number of pending eliminations that have an offset not equal
339 to their initial offset. If nonzero, we use a new copy of each
340 replacement result in any insns encountered. */
341 int num_not_at_initial_offset;
343 /* Count the number of registers that we may be able to eliminate. */
344 static int num_eliminable;
345 /* And the number of registers that are equivalent to a constant that
346 can be eliminated to frame_pointer / arg_pointer + constant. */
347 static int num_eliminable_invariants;
349 /* For each label, we record the offset of each elimination. If we reach
350 a label by more than one path and an offset differs, we cannot do the
351 elimination. This information is indexed by the difference of the
352 number of the label and the first label number. We can't offset the
353 pointer itself as this can cause problems on machines with segmented
354 memory. The first table is an array of flags that records whether we
355 have yet encountered a label and the second table is an array of arrays,
356 one entry in the latter array for each elimination. */
358 static int first_label_num;
359 static char *offsets_known_at;
360 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
362 /* Number of labels in the current function. */
364 static int num_labels;
366 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
367 static void maybe_fix_stack_asms (void);
368 static void copy_reloads (struct insn_chain *);
369 static void calculate_needs_all_insns (int);
370 static int find_reg (struct insn_chain *, int);
371 static void find_reload_regs (struct insn_chain *);
372 static void select_reload_regs (void);
373 static void delete_caller_save_insns (void);
375 static void spill_failure (rtx, enum reg_class);
376 static void count_spilled_pseudo (int, int, int);
377 static void delete_dead_insn (rtx);
378 static void alter_reg (int, int);
379 static void set_label_offsets (rtx, rtx, int);
380 static void check_eliminable_occurrences (rtx);
381 static void elimination_effects (rtx, enum machine_mode);
382 static int eliminate_regs_in_insn (rtx, int);
383 static void update_eliminable_offsets (void);
384 static void mark_not_eliminable (rtx, rtx, void *);
385 static void set_initial_elim_offsets (void);
386 static void verify_initial_elim_offsets (void);
387 static void set_initial_label_offsets (void);
388 static void set_offsets_for_label (rtx);
389 static void init_elim_table (void);
390 static void update_eliminables (HARD_REG_SET *);
391 static void spill_hard_reg (unsigned int, int);
392 static int finish_spills (int);
393 static void ior_hard_reg_set (HARD_REG_SET *, HARD_REG_SET *);
394 static void scan_paradoxical_subregs (rtx);
395 static void count_pseudo (int);
396 static void order_regs_for_reload (struct insn_chain *);
397 static void reload_as_needed (int);
398 static void forget_old_reloads_1 (rtx, rtx, void *);
399 static int reload_reg_class_lower (const void *, const void *);
400 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
402 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
404 static int reload_reg_free_p (unsigned int, int, enum reload_type);
405 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
407 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
409 static int function_invariant_p (rtx);
410 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
411 static int allocate_reload_reg (struct insn_chain *, int, int);
412 static int conflicts_with_override (rtx);
413 static void failed_reload (rtx, int);
414 static int set_reload_reg (int, int);
415 static void choose_reload_regs_init (struct insn_chain *, rtx *);
416 static void choose_reload_regs (struct insn_chain *);
417 static void merge_assigned_reloads (rtx);
418 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
420 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
422 static void do_input_reload (struct insn_chain *, struct reload *, int);
423 static void do_output_reload (struct insn_chain *, struct reload *, int);
424 static bool inherit_piecemeal_p (int, int);
425 static void emit_reload_insns (struct insn_chain *);
426 static void delete_output_reload (rtx, int, int);
427 static void delete_address_reloads (rtx, rtx);
428 static void delete_address_reloads_1 (rtx, rtx, rtx);
429 static rtx inc_for_reload (rtx, rtx, rtx, int);
431 static void add_auto_inc_notes (rtx, rtx);
433 static void copy_eh_notes (rtx, rtx);
435 /* Initialize the reload pass once per compilation. */
442 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
443 Set spill_indirect_levels to the number of levels such addressing is
444 permitted, zero if it is not permitted at all. */
447 = gen_rtx_MEM (Pmode,
450 LAST_VIRTUAL_REGISTER + 1),
452 spill_indirect_levels = 0;
454 while (memory_address_p (QImode, tem))
456 spill_indirect_levels++;
457 tem = gen_rtx_MEM (Pmode, tem);
460 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
462 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
463 indirect_symref_ok = memory_address_p (QImode, tem);
465 /* See if reg+reg is a valid (and offsettable) address. */
467 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
469 tem = gen_rtx_PLUS (Pmode,
470 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
471 gen_rtx_REG (Pmode, i));
473 /* This way, we make sure that reg+reg is an offsettable address. */
474 tem = plus_constant (tem, 4);
476 if (memory_address_p (QImode, tem))
478 double_reg_address_ok = 1;
483 /* Initialize obstack for our rtl allocation. */
484 gcc_obstack_init (&reload_obstack);
485 reload_startobj = obstack_alloc (&reload_obstack, 0);
487 INIT_REG_SET (&spilled_pseudos);
488 INIT_REG_SET (&pseudos_counted);
489 VARRAY_RTX_INIT (reg_equiv_memory_loc_varray, 0, "reg_equiv_memory_loc");
492 /* List of insn chains that are currently unused. */
493 static struct insn_chain *unused_insn_chains = 0;
495 /* Allocate an empty insn_chain structure. */
497 new_insn_chain (void)
499 struct insn_chain *c;
501 if (unused_insn_chains == 0)
503 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
504 INIT_REG_SET (&c->live_throughout);
505 INIT_REG_SET (&c->dead_or_set);
509 c = unused_insn_chains;
510 unused_insn_chains = c->next;
512 c->is_caller_save_insn = 0;
513 c->need_operand_change = 0;
519 /* Small utility function to set all regs in hard reg set TO which are
520 allocated to pseudos in regset FROM. */
523 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
527 EXECUTE_IF_SET_IN_REG_SET
528 (from, FIRST_PSEUDO_REGISTER, regno,
530 int r = reg_renumber[regno];
535 /* reload_combine uses the information from
536 BASIC_BLOCK->global_live_at_start, which might still
537 contain registers that have not actually been allocated
538 since they have an equivalence. */
539 gcc_assert (reload_completed);
543 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)];
545 SET_HARD_REG_BIT (*to, r + nregs);
550 /* Replace all pseudos found in LOC with their corresponding
554 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
567 unsigned int regno = REGNO (x);
569 if (regno < FIRST_PSEUDO_REGISTER)
572 x = eliminate_regs (x, mem_mode, usage);
576 replace_pseudos_in (loc, mem_mode, usage);
580 if (reg_equiv_constant[regno])
581 *loc = reg_equiv_constant[regno];
582 else if (reg_equiv_mem[regno])
583 *loc = reg_equiv_mem[regno];
584 else if (reg_equiv_address[regno])
585 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
588 gcc_assert (!REG_P (regno_reg_rtx[regno])
589 || REGNO (regno_reg_rtx[regno]) != regno);
590 *loc = regno_reg_rtx[regno];
595 else if (code == MEM)
597 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
601 /* Process each of our operands recursively. */
602 fmt = GET_RTX_FORMAT (code);
603 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
605 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
606 else if (*fmt == 'E')
607 for (j = 0; j < XVECLEN (x, i); j++)
608 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
612 /* Global variables used by reload and its subroutines. */
614 /* Set during calculate_needs if an insn needs register elimination. */
615 static int something_needs_elimination;
616 /* Set during calculate_needs if an insn needs an operand changed. */
617 int something_needs_operands_changed;
619 /* Nonzero means we couldn't get enough spill regs. */
622 /* Main entry point for the reload pass.
624 FIRST is the first insn of the function being compiled.
626 GLOBAL nonzero means we were called from global_alloc
627 and should attempt to reallocate any pseudoregs that we
628 displace from hard regs we will use for reloads.
629 If GLOBAL is zero, we do not have enough information to do that,
630 so any pseudo reg that is spilled must go to the stack.
632 Return value is nonzero if reload failed
633 and we must not do any more for this function. */
636 reload (rtx first, int global)
640 struct elim_table *ep;
643 /* Make sure even insns with volatile mem refs are recognizable. */
648 reload_firstobj = obstack_alloc (&reload_obstack, 0);
650 /* Make sure that the last insn in the chain
651 is not something that needs reloading. */
652 emit_note (NOTE_INSN_DELETED);
654 /* Enable find_equiv_reg to distinguish insns made by reload. */
655 reload_first_uid = get_max_uid ();
657 #ifdef SECONDARY_MEMORY_NEEDED
658 /* Initialize the secondary memory table. */
659 clear_secondary_mem ();
662 /* We don't have a stack slot for any spill reg yet. */
663 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
664 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
666 /* Initialize the save area information for caller-save, in case some
670 /* Compute which hard registers are now in use
671 as homes for pseudo registers.
672 This is done here rather than (eg) in global_alloc
673 because this point is reached even if not optimizing. */
674 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
677 /* A function that receives a nonlocal goto must save all call-saved
679 if (current_function_has_nonlocal_label)
680 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
681 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
682 regs_ever_live[i] = 1;
684 #ifdef NON_SAVING_SETJMP
685 /* A function that calls setjmp should save and restore all the
686 call-saved registers on a system where longjmp clobbers them. */
687 if (NON_SAVING_SETJMP && current_function_calls_setjmp)
689 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
690 if (! call_used_regs[i])
691 regs_ever_live[i] = 1;
695 /* Find all the pseudo registers that didn't get hard regs
696 but do have known equivalent constants or memory slots.
697 These include parameters (known equivalent to parameter slots)
698 and cse'd or loop-moved constant memory addresses.
700 Record constant equivalents in reg_equiv_constant
701 so they will be substituted by find_reloads.
702 Record memory equivalents in reg_mem_equiv so they can
703 be substituted eventually by altering the REG-rtx's. */
705 reg_equiv_constant = xcalloc (max_regno, sizeof (rtx));
706 reg_equiv_mem = xcalloc (max_regno, sizeof (rtx));
707 reg_equiv_init = xcalloc (max_regno, sizeof (rtx));
708 reg_equiv_address = xcalloc (max_regno, sizeof (rtx));
709 reg_max_ref_width = xcalloc (max_regno, sizeof (int));
710 reg_old_renumber = xcalloc (max_regno, sizeof (short));
711 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
712 pseudo_forbidden_regs = xmalloc (max_regno * sizeof (HARD_REG_SET));
713 pseudo_previous_regs = xcalloc (max_regno, sizeof (HARD_REG_SET));
715 CLEAR_HARD_REG_SET (bad_spill_regs_global);
717 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
718 to. Also find all paradoxical subregs and find largest such for
721 num_eliminable_invariants = 0;
722 for (insn = first; insn; insn = NEXT_INSN (insn))
724 rtx set = single_set (insn);
726 /* We may introduce USEs that we want to remove at the end, so
727 we'll mark them with QImode. Make sure there are no
728 previously-marked insns left by say regmove. */
729 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
730 && GET_MODE (insn) != VOIDmode)
731 PUT_MODE (insn, VOIDmode);
733 if (set != 0 && REG_P (SET_DEST (set)))
735 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
737 && (! function_invariant_p (XEXP (note, 0))
739 /* A function invariant is often CONSTANT_P but may
740 include a register. We promise to only pass
741 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
742 || (CONSTANT_P (XEXP (note, 0))
743 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))))
745 rtx x = XEXP (note, 0);
746 i = REGNO (SET_DEST (set));
747 if (i > LAST_VIRTUAL_REGISTER)
749 /* It can happen that a REG_EQUIV note contains a MEM
750 that is not a legitimate memory operand. As later
751 stages of reload assume that all addresses found
752 in the reg_equiv_* arrays were originally legitimate,
753 we ignore such REG_EQUIV notes. */
754 if (memory_operand (x, VOIDmode))
756 /* Always unshare the equivalence, so we can
757 substitute into this insn without touching the
759 reg_equiv_memory_loc[i] = copy_rtx (x);
761 else if (function_invariant_p (x))
763 if (GET_CODE (x) == PLUS)
765 /* This is PLUS of frame pointer and a constant,
766 and might be shared. Unshare it. */
767 reg_equiv_constant[i] = copy_rtx (x);
768 num_eliminable_invariants++;
770 else if (x == frame_pointer_rtx
771 || x == arg_pointer_rtx)
773 reg_equiv_constant[i] = x;
774 num_eliminable_invariants++;
776 else if (LEGITIMATE_CONSTANT_P (x))
777 reg_equiv_constant[i] = x;
780 reg_equiv_memory_loc[i]
781 = force_const_mem (GET_MODE (SET_DEST (set)), x);
782 if (!reg_equiv_memory_loc[i])
789 /* If this register is being made equivalent to a MEM
790 and the MEM is not SET_SRC, the equivalencing insn
791 is one with the MEM as a SET_DEST and it occurs later.
792 So don't mark this insn now. */
794 || rtx_equal_p (SET_SRC (set), x))
796 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
801 /* If this insn is setting a MEM from a register equivalent to it,
802 this is the equivalencing insn. */
803 else if (set && MEM_P (SET_DEST (set))
804 && REG_P (SET_SRC (set))
805 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
806 && rtx_equal_p (SET_DEST (set),
807 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
808 reg_equiv_init[REGNO (SET_SRC (set))]
809 = gen_rtx_INSN_LIST (VOIDmode, insn,
810 reg_equiv_init[REGNO (SET_SRC (set))]);
813 scan_paradoxical_subregs (PATTERN (insn));
818 first_label_num = get_first_label_num ();
819 num_labels = max_label_num () - first_label_num;
821 /* Allocate the tables used to store offset information at labels. */
822 /* We used to use alloca here, but the size of what it would try to
823 allocate would occasionally cause it to exceed the stack limit and
824 cause a core dump. */
825 offsets_known_at = xmalloc (num_labels);
826 offsets_at = xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
828 /* Alter each pseudo-reg rtx to contain its hard reg number.
829 Assign stack slots to the pseudos that lack hard regs or equivalents.
830 Do not touch virtual registers. */
832 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
835 /* If we have some registers we think can be eliminated, scan all insns to
836 see if there is an insn that sets one of these registers to something
837 other than itself plus a constant. If so, the register cannot be
838 eliminated. Doing this scan here eliminates an extra pass through the
839 main reload loop in the most common case where register elimination
841 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
843 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
845 maybe_fix_stack_asms ();
847 insns_need_reload = 0;
848 something_needs_elimination = 0;
850 /* Initialize to -1, which means take the first spill register. */
853 /* Spill any hard regs that we know we can't eliminate. */
854 CLEAR_HARD_REG_SET (used_spill_regs);
855 /* There can be multiple ways to eliminate a register;
856 they should be listed adjacently.
857 Elimination for any register fails only if all possible ways fail. */
858 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
861 int can_eliminate = 0;
864 can_eliminate |= ep->can_eliminate;
867 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
869 spill_hard_reg (from, 1);
872 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
873 if (frame_pointer_needed)
874 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
876 finish_spills (global);
878 /* From now on, we may need to generate moves differently. We may also
879 allow modifications of insns which cause them to not be recognized.
880 Any such modifications will be cleaned up during reload itself. */
881 reload_in_progress = 1;
883 /* This loop scans the entire function each go-round
884 and repeats until one repetition spills no additional hard regs. */
887 int something_changed;
890 HOST_WIDE_INT starting_frame_size;
892 /* Round size of stack frame to stack_alignment_needed. This must be done
893 here because the stack size may be a part of the offset computation
894 for register elimination, and there might have been new stack slots
895 created in the last iteration of this loop. */
896 if (cfun->stack_alignment_needed)
897 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
899 starting_frame_size = get_frame_size ();
901 set_initial_elim_offsets ();
902 set_initial_label_offsets ();
904 /* For each pseudo register that has an equivalent location defined,
905 try to eliminate any eliminable registers (such as the frame pointer)
906 assuming initial offsets for the replacement register, which
909 If the resulting location is directly addressable, substitute
910 the MEM we just got directly for the old REG.
912 If it is not addressable but is a constant or the sum of a hard reg
913 and constant, it is probably not addressable because the constant is
914 out of range, in that case record the address; we will generate
915 hairy code to compute the address in a register each time it is
916 needed. Similarly if it is a hard register, but one that is not
917 valid as an address register.
919 If the location is not addressable, but does not have one of the
920 above forms, assign a stack slot. We have to do this to avoid the
921 potential of producing lots of reloads if, e.g., a location involves
922 a pseudo that didn't get a hard register and has an equivalent memory
923 location that also involves a pseudo that didn't get a hard register.
925 Perhaps at some point we will improve reload_when_needed handling
926 so this problem goes away. But that's very hairy. */
928 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
929 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
931 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
933 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
935 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
936 else if (CONSTANT_P (XEXP (x, 0))
937 || (REG_P (XEXP (x, 0))
938 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
939 || (GET_CODE (XEXP (x, 0)) == PLUS
940 && REG_P (XEXP (XEXP (x, 0), 0))
941 && (REGNO (XEXP (XEXP (x, 0), 0))
942 < FIRST_PSEUDO_REGISTER)
943 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
944 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
947 /* Make a new stack slot. Then indicate that something
948 changed so we go back and recompute offsets for
949 eliminable registers because the allocation of memory
950 below might change some offset. reg_equiv_{mem,address}
951 will be set up for this pseudo on the next pass around
953 reg_equiv_memory_loc[i] = 0;
954 reg_equiv_init[i] = 0;
959 if (caller_save_needed)
962 /* If we allocated another stack slot, redo elimination bookkeeping. */
963 if (starting_frame_size != get_frame_size ())
966 if (caller_save_needed)
968 save_call_clobbered_regs ();
969 /* That might have allocated new insn_chain structures. */
970 reload_firstobj = obstack_alloc (&reload_obstack, 0);
973 calculate_needs_all_insns (global);
975 CLEAR_REG_SET (&spilled_pseudos);
978 something_changed = 0;
980 /* If we allocated any new memory locations, make another pass
981 since it might have changed elimination offsets. */
982 if (starting_frame_size != get_frame_size ())
983 something_changed = 1;
986 HARD_REG_SET to_spill;
987 CLEAR_HARD_REG_SET (to_spill);
988 update_eliminables (&to_spill);
989 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
990 if (TEST_HARD_REG_BIT (to_spill, i))
992 spill_hard_reg (i, 1);
995 /* Regardless of the state of spills, if we previously had
996 a register that we thought we could eliminate, but now can
997 not eliminate, we must run another pass.
999 Consider pseudos which have an entry in reg_equiv_* which
1000 reference an eliminable register. We must make another pass
1001 to update reg_equiv_* so that we do not substitute in the
1002 old value from when we thought the elimination could be
1004 something_changed = 1;
1008 select_reload_regs ();
1012 if (insns_need_reload != 0 || did_spill)
1013 something_changed |= finish_spills (global);
1015 if (! something_changed)
1018 if (caller_save_needed)
1019 delete_caller_save_insns ();
1021 obstack_free (&reload_obstack, reload_firstobj);
1024 /* If global-alloc was run, notify it of any register eliminations we have
1027 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1028 if (ep->can_eliminate)
1029 mark_elimination (ep->from, ep->to);
1031 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1032 If that insn didn't set the register (i.e., it copied the register to
1033 memory), just delete that insn instead of the equivalencing insn plus
1034 anything now dead. If we call delete_dead_insn on that insn, we may
1035 delete the insn that actually sets the register if the register dies
1036 there and that is incorrect. */
1038 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1040 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1043 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1045 rtx equiv_insn = XEXP (list, 0);
1047 /* If we already deleted the insn or if it may trap, we can't
1048 delete it. The latter case shouldn't happen, but can
1049 if an insn has a variable address, gets a REG_EH_REGION
1050 note added to it, and then gets converted into an load
1051 from a constant address. */
1052 if (NOTE_P (equiv_insn)
1053 || can_throw_internal (equiv_insn))
1055 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1056 delete_dead_insn (equiv_insn);
1058 SET_INSN_DELETED (equiv_insn);
1063 /* Use the reload registers where necessary
1064 by generating move instructions to move the must-be-register
1065 values into or out of the reload registers. */
1067 if (insns_need_reload != 0 || something_needs_elimination
1068 || something_needs_operands_changed)
1070 HOST_WIDE_INT old_frame_size = get_frame_size ();
1072 reload_as_needed (global);
1074 gcc_assert (old_frame_size == get_frame_size ());
1077 verify_initial_elim_offsets ();
1080 /* If we were able to eliminate the frame pointer, show that it is no
1081 longer live at the start of any basic block. If it ls live by
1082 virtue of being in a pseudo, that pseudo will be marked live
1083 and hence the frame pointer will be known to be live via that
1086 if (! frame_pointer_needed)
1088 CLEAR_REGNO_REG_SET (bb->global_live_at_start,
1089 HARD_FRAME_POINTER_REGNUM);
1091 /* Come here (with failure set nonzero) if we can't get enough spill regs
1092 and we decide not to abort about it. */
1095 CLEAR_REG_SET (&spilled_pseudos);
1096 reload_in_progress = 0;
1098 /* Now eliminate all pseudo regs by modifying them into
1099 their equivalent memory references.
1100 The REG-rtx's for the pseudos are modified in place,
1101 so all insns that used to refer to them now refer to memory.
1103 For a reg that has a reg_equiv_address, all those insns
1104 were changed by reloading so that no insns refer to it any longer;
1105 but the DECL_RTL of a variable decl may refer to it,
1106 and if so this causes the debugging info to mention the variable. */
1108 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1112 if (reg_equiv_mem[i])
1113 addr = XEXP (reg_equiv_mem[i], 0);
1115 if (reg_equiv_address[i])
1116 addr = reg_equiv_address[i];
1120 if (reg_renumber[i] < 0)
1122 rtx reg = regno_reg_rtx[i];
1124 REG_USERVAR_P (reg) = 0;
1125 PUT_CODE (reg, MEM);
1126 XEXP (reg, 0) = addr;
1127 if (reg_equiv_memory_loc[i])
1128 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1131 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1132 MEM_ATTRS (reg) = 0;
1135 else if (reg_equiv_mem[i])
1136 XEXP (reg_equiv_mem[i], 0) = addr;
1140 /* We must set reload_completed now since the cleanup_subreg_operands call
1141 below will re-recognize each insn and reload may have generated insns
1142 which are only valid during and after reload. */
1143 reload_completed = 1;
1145 /* Make a pass over all the insns and delete all USEs which we inserted
1146 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1147 notes. Delete all CLOBBER insns, except those that refer to the return
1148 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1149 from misarranging variable-array code, and simplify (subreg (reg))
1150 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1151 are no longer useful or accurate. Strip and regenerate REG_INC notes
1152 that may have been moved around. */
1154 for (insn = first; insn; insn = NEXT_INSN (insn))
1160 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1161 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1163 if ((GET_CODE (PATTERN (insn)) == USE
1164 /* We mark with QImode USEs introduced by reload itself. */
1165 && (GET_MODE (insn) == QImode
1166 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1167 || (GET_CODE (PATTERN (insn)) == CLOBBER
1168 && (!MEM_P (XEXP (PATTERN (insn), 0))
1169 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1170 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1171 && XEXP (XEXP (PATTERN (insn), 0), 0)
1172 != stack_pointer_rtx))
1173 && (!REG_P (XEXP (PATTERN (insn), 0))
1174 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1180 /* Some CLOBBERs may survive until here and still reference unassigned
1181 pseudos with const equivalent, which may in turn cause ICE in later
1182 passes if the reference remains in place. */
1183 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1184 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1185 VOIDmode, PATTERN (insn));
1187 pnote = ®_NOTES (insn);
1190 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1191 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1192 || REG_NOTE_KIND (*pnote) == REG_INC
1193 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1194 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1195 *pnote = XEXP (*pnote, 1);
1197 pnote = &XEXP (*pnote, 1);
1201 add_auto_inc_notes (insn, PATTERN (insn));
1204 /* And simplify (subreg (reg)) if it appears as an operand. */
1205 cleanup_subreg_operands (insn);
1208 /* If we are doing stack checking, give a warning if this function's
1209 frame size is larger than we expect. */
1210 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1212 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1213 static int verbose_warned = 0;
1215 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1216 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1217 size += UNITS_PER_WORD;
1219 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1221 warning ("frame size too large for reliable stack checking");
1222 if (! verbose_warned)
1224 warning ("try reducing the number of local variables");
1230 /* Indicate that we no longer have known memory locations or constants. */
1231 if (reg_equiv_constant)
1232 free (reg_equiv_constant);
1233 reg_equiv_constant = 0;
1234 VARRAY_GROW (reg_equiv_memory_loc_varray, 0);
1235 reg_equiv_memory_loc = 0;
1237 if (offsets_known_at)
1238 free (offsets_known_at);
1242 free (reg_equiv_mem);
1243 free (reg_equiv_init);
1244 free (reg_equiv_address);
1245 free (reg_max_ref_width);
1246 free (reg_old_renumber);
1247 free (pseudo_previous_regs);
1248 free (pseudo_forbidden_regs);
1250 CLEAR_HARD_REG_SET (used_spill_regs);
1251 for (i = 0; i < n_spills; i++)
1252 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1254 /* Free all the insn_chain structures at once. */
1255 obstack_free (&reload_obstack, reload_startobj);
1256 unused_insn_chains = 0;
1257 fixup_abnormal_edges ();
1259 /* Replacing pseudos with their memory equivalents might have
1260 created shared rtx. Subsequent passes would get confused
1261 by this, so unshare everything here. */
1262 unshare_all_rtl_again (first);
1264 #ifdef STACK_BOUNDARY
1265 /* init_emit has set the alignment of the hard frame pointer
1266 to STACK_BOUNDARY. It is very likely no longer valid if
1267 the hard frame pointer was used for register allocation. */
1268 if (!frame_pointer_needed)
1269 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1275 /* Yet another special case. Unfortunately, reg-stack forces people to
1276 write incorrect clobbers in asm statements. These clobbers must not
1277 cause the register to appear in bad_spill_regs, otherwise we'll call
1278 fatal_insn later. We clear the corresponding regnos in the live
1279 register sets to avoid this.
1280 The whole thing is rather sick, I'm afraid. */
1283 maybe_fix_stack_asms (void)
1286 const char *constraints[MAX_RECOG_OPERANDS];
1287 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1288 struct insn_chain *chain;
1290 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1293 HARD_REG_SET clobbered, allowed;
1296 if (! INSN_P (chain->insn)
1297 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1299 pat = PATTERN (chain->insn);
1300 if (GET_CODE (pat) != PARALLEL)
1303 CLEAR_HARD_REG_SET (clobbered);
1304 CLEAR_HARD_REG_SET (allowed);
1306 /* First, make a mask of all stack regs that are clobbered. */
1307 for (i = 0; i < XVECLEN (pat, 0); i++)
1309 rtx t = XVECEXP (pat, 0, i);
1310 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1311 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1314 /* Get the operand values and constraints out of the insn. */
1315 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1316 constraints, operand_mode);
1318 /* For every operand, see what registers are allowed. */
1319 for (i = 0; i < noperands; i++)
1321 const char *p = constraints[i];
1322 /* For every alternative, we compute the class of registers allowed
1323 for reloading in CLS, and merge its contents into the reg set
1325 int cls = (int) NO_REGS;
1331 if (c == '\0' || c == ',' || c == '#')
1333 /* End of one alternative - mark the regs in the current
1334 class, and reset the class. */
1335 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1341 } while (c != '\0' && c != ',');
1349 case '=': case '+': case '*': case '%': case '?': case '!':
1350 case '0': case '1': case '2': case '3': case '4': case 'm':
1351 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1352 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1353 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1358 cls = (int) reg_class_subunion[cls]
1359 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1364 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1368 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1369 cls = (int) reg_class_subunion[cls]
1370 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1372 cls = (int) reg_class_subunion[cls]
1373 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1375 p += CONSTRAINT_LEN (c, p);
1378 /* Those of the registers which are clobbered, but allowed by the
1379 constraints, must be usable as reload registers. So clear them
1380 out of the life information. */
1381 AND_HARD_REG_SET (allowed, clobbered);
1382 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1383 if (TEST_HARD_REG_BIT (allowed, i))
1385 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1386 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1393 /* Copy the global variables n_reloads and rld into the corresponding elts
1396 copy_reloads (struct insn_chain *chain)
1398 chain->n_reloads = n_reloads;
1399 chain->rld = obstack_alloc (&reload_obstack,
1400 n_reloads * sizeof (struct reload));
1401 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1402 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1405 /* Walk the chain of insns, and determine for each whether it needs reloads
1406 and/or eliminations. Build the corresponding insns_need_reload list, and
1407 set something_needs_elimination as appropriate. */
1409 calculate_needs_all_insns (int global)
1411 struct insn_chain **pprev_reload = &insns_need_reload;
1412 struct insn_chain *chain, *next = 0;
1414 something_needs_elimination = 0;
1416 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1417 for (chain = reload_insn_chain; chain != 0; chain = next)
1419 rtx insn = chain->insn;
1423 /* Clear out the shortcuts. */
1424 chain->n_reloads = 0;
1425 chain->need_elim = 0;
1426 chain->need_reload = 0;
1427 chain->need_operand_change = 0;
1429 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1430 include REG_LABEL), we need to see what effects this has on the
1431 known offsets at labels. */
1433 if (LABEL_P (insn) || JUMP_P (insn)
1434 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1435 set_label_offsets (insn, insn, 0);
1439 rtx old_body = PATTERN (insn);
1440 int old_code = INSN_CODE (insn);
1441 rtx old_notes = REG_NOTES (insn);
1442 int did_elimination = 0;
1443 int operands_changed = 0;
1444 rtx set = single_set (insn);
1446 /* Skip insns that only set an equivalence. */
1447 if (set && REG_P (SET_DEST (set))
1448 && reg_renumber[REGNO (SET_DEST (set))] < 0
1449 && reg_equiv_constant[REGNO (SET_DEST (set))])
1452 /* If needed, eliminate any eliminable registers. */
1453 if (num_eliminable || num_eliminable_invariants)
1454 did_elimination = eliminate_regs_in_insn (insn, 0);
1456 /* Analyze the instruction. */
1457 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1458 global, spill_reg_order);
1460 /* If a no-op set needs more than one reload, this is likely
1461 to be something that needs input address reloads. We
1462 can't get rid of this cleanly later, and it is of no use
1463 anyway, so discard it now.
1464 We only do this when expensive_optimizations is enabled,
1465 since this complements reload inheritance / output
1466 reload deletion, and it can make debugging harder. */
1467 if (flag_expensive_optimizations && n_reloads > 1)
1469 rtx set = single_set (insn);
1471 && SET_SRC (set) == SET_DEST (set)
1472 && REG_P (SET_SRC (set))
1473 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1476 /* Delete it from the reload chain. */
1478 chain->prev->next = next;
1480 reload_insn_chain = next;
1482 next->prev = chain->prev;
1483 chain->next = unused_insn_chains;
1484 unused_insn_chains = chain;
1489 update_eliminable_offsets ();
1491 /* Remember for later shortcuts which insns had any reloads or
1492 register eliminations. */
1493 chain->need_elim = did_elimination;
1494 chain->need_reload = n_reloads > 0;
1495 chain->need_operand_change = operands_changed;
1497 /* Discard any register replacements done. */
1498 if (did_elimination)
1500 obstack_free (&reload_obstack, reload_insn_firstobj);
1501 PATTERN (insn) = old_body;
1502 INSN_CODE (insn) = old_code;
1503 REG_NOTES (insn) = old_notes;
1504 something_needs_elimination = 1;
1507 something_needs_operands_changed |= operands_changed;
1511 copy_reloads (chain);
1512 *pprev_reload = chain;
1513 pprev_reload = &chain->next_need_reload;
1520 /* Comparison function for qsort to decide which of two reloads
1521 should be handled first. *P1 and *P2 are the reload numbers. */
1524 reload_reg_class_lower (const void *r1p, const void *r2p)
1526 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1529 /* Consider required reloads before optional ones. */
1530 t = rld[r1].optional - rld[r2].optional;
1534 /* Count all solitary classes before non-solitary ones. */
1535 t = ((reg_class_size[(int) rld[r2].class] == 1)
1536 - (reg_class_size[(int) rld[r1].class] == 1));
1540 /* Aside from solitaires, consider all multi-reg groups first. */
1541 t = rld[r2].nregs - rld[r1].nregs;
1545 /* Consider reloads in order of increasing reg-class number. */
1546 t = (int) rld[r1].class - (int) rld[r2].class;
1550 /* If reloads are equally urgent, sort by reload number,
1551 so that the results of qsort leave nothing to chance. */
1555 /* The cost of spilling each hard reg. */
1556 static int spill_cost[FIRST_PSEUDO_REGISTER];
1558 /* When spilling multiple hard registers, we use SPILL_COST for the first
1559 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1560 only the first hard reg for a multi-reg pseudo. */
1561 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1563 /* Update the spill cost arrays, considering that pseudo REG is live. */
1566 count_pseudo (int reg)
1568 int freq = REG_FREQ (reg);
1569 int r = reg_renumber[reg];
1572 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1573 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1576 SET_REGNO_REG_SET (&pseudos_counted, reg);
1578 gcc_assert (r >= 0);
1580 spill_add_cost[r] += freq;
1582 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1584 spill_cost[r + nregs] += freq;
1587 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1588 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1591 order_regs_for_reload (struct insn_chain *chain)
1594 HARD_REG_SET used_by_pseudos;
1595 HARD_REG_SET used_by_pseudos2;
1597 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1599 memset (spill_cost, 0, sizeof spill_cost);
1600 memset (spill_add_cost, 0, sizeof spill_add_cost);
1602 /* Count number of uses of each hard reg by pseudo regs allocated to it
1603 and then order them by decreasing use. First exclude hard registers
1604 that are live in or across this insn. */
1606 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1607 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1608 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1609 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1611 /* Now find out which pseudos are allocated to it, and update
1613 CLEAR_REG_SET (&pseudos_counted);
1615 EXECUTE_IF_SET_IN_REG_SET
1616 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1620 EXECUTE_IF_SET_IN_REG_SET
1621 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1625 CLEAR_REG_SET (&pseudos_counted);
1628 /* Vector of reload-numbers showing the order in which the reloads should
1630 static short reload_order[MAX_RELOADS];
1632 /* This is used to keep track of the spill regs used in one insn. */
1633 static HARD_REG_SET used_spill_regs_local;
1635 /* We decided to spill hard register SPILLED, which has a size of
1636 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1637 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1638 update SPILL_COST/SPILL_ADD_COST. */
1641 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1643 int r = reg_renumber[reg];
1644 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1646 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1647 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1650 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1652 spill_add_cost[r] -= REG_FREQ (reg);
1654 spill_cost[r + nregs] -= REG_FREQ (reg);
1657 /* Find reload register to use for reload number ORDER. */
1660 find_reg (struct insn_chain *chain, int order)
1662 int rnum = reload_order[order];
1663 struct reload *rl = rld + rnum;
1664 int best_cost = INT_MAX;
1668 HARD_REG_SET not_usable;
1669 HARD_REG_SET used_by_other_reload;
1671 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1672 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1673 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1675 CLEAR_HARD_REG_SET (used_by_other_reload);
1676 for (k = 0; k < order; k++)
1678 int other = reload_order[k];
1680 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1681 for (j = 0; j < rld[other].nregs; j++)
1682 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1685 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1687 unsigned int regno = i;
1689 if (! TEST_HARD_REG_BIT (not_usable, regno)
1690 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1691 && HARD_REGNO_MODE_OK (regno, rl->mode))
1693 int this_cost = spill_cost[regno];
1695 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1697 for (j = 1; j < this_nregs; j++)
1699 this_cost += spill_add_cost[regno + j];
1700 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1701 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1706 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1708 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1710 if (this_cost < best_cost
1711 /* Among registers with equal cost, prefer caller-saved ones, or
1712 use REG_ALLOC_ORDER if it is defined. */
1713 || (this_cost == best_cost
1714 #ifdef REG_ALLOC_ORDER
1715 && (inv_reg_alloc_order[regno]
1716 < inv_reg_alloc_order[best_reg])
1718 && call_used_regs[regno]
1719 && ! call_used_regs[best_reg]
1724 best_cost = this_cost;
1732 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1734 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1735 rl->regno = best_reg;
1737 EXECUTE_IF_SET_IN_REG_SET
1738 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1740 count_spilled_pseudo (best_reg, rl->nregs, j);
1743 EXECUTE_IF_SET_IN_REG_SET
1744 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1746 count_spilled_pseudo (best_reg, rl->nregs, j);
1749 for (i = 0; i < rl->nregs; i++)
1751 gcc_assert (spill_cost[best_reg + i] == 0);
1752 gcc_assert (spill_add_cost[best_reg + i] == 0);
1753 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1758 /* Find more reload regs to satisfy the remaining need of an insn, which
1760 Do it by ascending class number, since otherwise a reg
1761 might be spilled for a big class and might fail to count
1762 for a smaller class even though it belongs to that class. */
1765 find_reload_regs (struct insn_chain *chain)
1769 /* In order to be certain of getting the registers we need,
1770 we must sort the reloads into order of increasing register class.
1771 Then our grabbing of reload registers will parallel the process
1772 that provided the reload registers. */
1773 for (i = 0; i < chain->n_reloads; i++)
1775 /* Show whether this reload already has a hard reg. */
1776 if (chain->rld[i].reg_rtx)
1778 int regno = REGNO (chain->rld[i].reg_rtx);
1779 chain->rld[i].regno = regno;
1781 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1784 chain->rld[i].regno = -1;
1785 reload_order[i] = i;
1788 n_reloads = chain->n_reloads;
1789 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1791 CLEAR_HARD_REG_SET (used_spill_regs_local);
1794 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1796 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1798 /* Compute the order of preference for hard registers to spill. */
1800 order_regs_for_reload (chain);
1802 for (i = 0; i < n_reloads; i++)
1804 int r = reload_order[i];
1806 /* Ignore reloads that got marked inoperative. */
1807 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1808 && ! rld[r].optional
1809 && rld[r].regno == -1)
1810 if (! find_reg (chain, i))
1812 spill_failure (chain->insn, rld[r].class);
1818 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1819 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1821 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1825 select_reload_regs (void)
1827 struct insn_chain *chain;
1829 /* Try to satisfy the needs for each insn. */
1830 for (chain = insns_need_reload; chain != 0;
1831 chain = chain->next_need_reload)
1832 find_reload_regs (chain);
1835 /* Delete all insns that were inserted by emit_caller_save_insns during
1838 delete_caller_save_insns (void)
1840 struct insn_chain *c = reload_insn_chain;
1844 while (c != 0 && c->is_caller_save_insn)
1846 struct insn_chain *next = c->next;
1849 if (c == reload_insn_chain)
1850 reload_insn_chain = next;
1854 next->prev = c->prev;
1856 c->prev->next = next;
1857 c->next = unused_insn_chains;
1858 unused_insn_chains = c;
1866 /* Handle the failure to find a register to spill.
1867 INSN should be one of the insns which needed this particular spill reg. */
1870 spill_failure (rtx insn, enum reg_class class)
1872 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1873 if (asm_noperands (PATTERN (insn)) >= 0)
1874 error_for_asm (insn, "can't find a register in class %qs while "
1875 "reloading %<asm%>",
1876 reg_class_names[class]);
1879 error ("unable to find a register to spill in class %qs",
1880 reg_class_names[class]);
1881 fatal_insn ("this is the insn:", insn);
1885 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1886 data that is dead in INSN. */
1889 delete_dead_insn (rtx insn)
1891 rtx prev = prev_real_insn (insn);
1894 /* If the previous insn sets a register that dies in our insn, delete it
1896 if (prev && GET_CODE (PATTERN (prev)) == SET
1897 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
1898 && reg_mentioned_p (prev_dest, PATTERN (insn))
1899 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1900 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1901 delete_dead_insn (prev);
1903 SET_INSN_DELETED (insn);
1906 /* Modify the home of pseudo-reg I.
1907 The new home is present in reg_renumber[I].
1909 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1910 or it may be -1, meaning there is none or it is not relevant.
1911 This is used so that all pseudos spilled from a given hard reg
1912 can share one stack slot. */
1915 alter_reg (int i, int from_reg)
1917 /* When outputting an inline function, this can happen
1918 for a reg that isn't actually used. */
1919 if (regno_reg_rtx[i] == 0)
1922 /* If the reg got changed to a MEM at rtl-generation time,
1924 if (!REG_P (regno_reg_rtx[i]))
1927 /* Modify the reg-rtx to contain the new hard reg
1928 number or else to contain its pseudo reg number. */
1929 REGNO (regno_reg_rtx[i])
1930 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1932 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1933 allocate a stack slot for it. */
1935 if (reg_renumber[i] < 0
1936 && REG_N_REFS (i) > 0
1937 && reg_equiv_constant[i] == 0
1938 && reg_equiv_memory_loc[i] == 0)
1941 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1942 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1945 /* Each pseudo reg has an inherent size which comes from its own mode,
1946 and a total size which provides room for paradoxical subregs
1947 which refer to the pseudo reg in wider modes.
1949 We can use a slot already allocated if it provides both
1950 enough inherent space and enough total space.
1951 Otherwise, we allocate a new slot, making sure that it has no less
1952 inherent space, and no less total space, then the previous slot. */
1955 /* No known place to spill from => no slot to reuse. */
1956 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1957 inherent_size == total_size ? 0 : -1);
1958 if (BYTES_BIG_ENDIAN)
1959 /* Cancel the big-endian correction done in assign_stack_local.
1960 Get the address of the beginning of the slot.
1961 This is so we can do a big-endian correction unconditionally
1963 adjust = inherent_size - total_size;
1965 /* Nothing can alias this slot except this pseudo. */
1966 set_mem_alias_set (x, new_alias_set ());
1969 /* Reuse a stack slot if possible. */
1970 else if (spill_stack_slot[from_reg] != 0
1971 && spill_stack_slot_width[from_reg] >= total_size
1972 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1974 x = spill_stack_slot[from_reg];
1976 /* Allocate a bigger slot. */
1979 /* Compute maximum size needed, both for inherent size
1980 and for total size. */
1981 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1984 if (spill_stack_slot[from_reg])
1986 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1988 mode = GET_MODE (spill_stack_slot[from_reg]);
1989 if (spill_stack_slot_width[from_reg] > total_size)
1990 total_size = spill_stack_slot_width[from_reg];
1993 /* Make a slot with that size. */
1994 x = assign_stack_local (mode, total_size,
1995 inherent_size == total_size ? 0 : -1);
1998 /* All pseudos mapped to this slot can alias each other. */
1999 if (spill_stack_slot[from_reg])
2000 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2002 set_mem_alias_set (x, new_alias_set ());
2004 if (BYTES_BIG_ENDIAN)
2006 /* Cancel the big-endian correction done in assign_stack_local.
2007 Get the address of the beginning of the slot.
2008 This is so we can do a big-endian correction unconditionally
2010 adjust = GET_MODE_SIZE (mode) - total_size;
2013 = adjust_address_nv (x, mode_for_size (total_size
2019 spill_stack_slot[from_reg] = stack_slot;
2020 spill_stack_slot_width[from_reg] = total_size;
2023 /* On a big endian machine, the "address" of the slot
2024 is the address of the low part that fits its inherent mode. */
2025 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2026 adjust += (total_size - inherent_size);
2028 /* If we have any adjustment to make, or if the stack slot is the
2029 wrong mode, make a new stack slot. */
2030 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2032 /* If we have a decl for the original register, set it for the
2033 memory. If this is a shared MEM, make a copy. */
2034 if (REG_EXPR (regno_reg_rtx[i])
2035 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2037 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2039 /* We can do this only for the DECLs home pseudo, not for
2040 any copies of it, since otherwise when the stack slot
2041 is reused, nonoverlapping_memrefs_p might think they
2043 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2045 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2048 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2052 /* Save the stack slot for later. */
2053 reg_equiv_memory_loc[i] = x;
2057 /* Mark the slots in regs_ever_live for the hard regs
2058 used by pseudo-reg number REGNO. */
2061 mark_home_live (int regno)
2065 i = reg_renumber[regno];
2068 lim = i + hard_regno_nregs[i][PSEUDO_REGNO_MODE (regno)];
2070 regs_ever_live[i++] = 1;
2073 /* This function handles the tracking of elimination offsets around branches.
2075 X is a piece of RTL being scanned.
2077 INSN is the insn that it came from, if any.
2079 INITIAL_P is nonzero if we are to set the offset to be the initial
2080 offset and zero if we are setting the offset of the label to be the
2084 set_label_offsets (rtx x, rtx insn, int initial_p)
2086 enum rtx_code code = GET_CODE (x);
2089 struct elim_table *p;
2094 if (LABEL_REF_NONLOCAL_P (x))
2099 /* ... fall through ... */
2102 /* If we know nothing about this label, set the desired offsets. Note
2103 that this sets the offset at a label to be the offset before a label
2104 if we don't know anything about the label. This is not correct for
2105 the label after a BARRIER, but is the best guess we can make. If
2106 we guessed wrong, we will suppress an elimination that might have
2107 been possible had we been able to guess correctly. */
2109 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2111 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2112 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2113 = (initial_p ? reg_eliminate[i].initial_offset
2114 : reg_eliminate[i].offset);
2115 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2118 /* Otherwise, if this is the definition of a label and it is
2119 preceded by a BARRIER, set our offsets to the known offset of
2123 && (tem = prev_nonnote_insn (insn)) != 0
2125 set_offsets_for_label (insn);
2127 /* If neither of the above cases is true, compare each offset
2128 with those previously recorded and suppress any eliminations
2129 where the offsets disagree. */
2131 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2132 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2133 != (initial_p ? reg_eliminate[i].initial_offset
2134 : reg_eliminate[i].offset))
2135 reg_eliminate[i].can_eliminate = 0;
2140 set_label_offsets (PATTERN (insn), insn, initial_p);
2142 /* ... fall through ... */
2146 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2147 and hence must have all eliminations at their initial offsets. */
2148 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2149 if (REG_NOTE_KIND (tem) == REG_LABEL)
2150 set_label_offsets (XEXP (tem, 0), insn, 1);
2156 /* Each of the labels in the parallel or address vector must be
2157 at their initial offsets. We want the first field for PARALLEL
2158 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2160 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2161 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2166 /* We only care about setting PC. If the source is not RETURN,
2167 IF_THEN_ELSE, or a label, disable any eliminations not at
2168 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2169 isn't one of those possibilities. For branches to a label,
2170 call ourselves recursively.
2172 Note that this can disable elimination unnecessarily when we have
2173 a non-local goto since it will look like a non-constant jump to
2174 someplace in the current function. This isn't a significant
2175 problem since such jumps will normally be when all elimination
2176 pairs are back to their initial offsets. */
2178 if (SET_DEST (x) != pc_rtx)
2181 switch (GET_CODE (SET_SRC (x)))
2188 set_label_offsets (SET_SRC (x), insn, initial_p);
2192 tem = XEXP (SET_SRC (x), 1);
2193 if (GET_CODE (tem) == LABEL_REF)
2194 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2195 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2198 tem = XEXP (SET_SRC (x), 2);
2199 if (GET_CODE (tem) == LABEL_REF)
2200 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2201 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2209 /* If we reach here, all eliminations must be at their initial
2210 offset because we are doing a jump to a variable address. */
2211 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2212 if (p->offset != p->initial_offset)
2213 p->can_eliminate = 0;
2221 /* Scan X and replace any eliminable registers (such as fp) with a
2222 replacement (such as sp), plus an offset.
2224 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2225 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2226 MEM, we are allowed to replace a sum of a register and the constant zero
2227 with the register, which we cannot do outside a MEM. In addition, we need
2228 to record the fact that a register is referenced outside a MEM.
2230 If INSN is an insn, it is the insn containing X. If we replace a REG
2231 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2232 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2233 the REG is being modified.
2235 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2236 That's used when we eliminate in expressions stored in notes.
2237 This means, do not set ref_outside_mem even if the reference
2240 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2241 replacements done assuming all offsets are at their initial values. If
2242 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2243 encounter, return the actual location so that find_reloads will do
2244 the proper thing. */
2247 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2249 enum rtx_code code = GET_CODE (x);
2250 struct elim_table *ep;
2257 if (! current_function_decl)
2279 /* First handle the case where we encounter a bare register that
2280 is eliminable. Replace it with a PLUS. */
2281 if (regno < FIRST_PSEUDO_REGISTER)
2283 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2285 if (ep->from_rtx == x && ep->can_eliminate)
2286 return plus_constant (ep->to_rtx, ep->previous_offset);
2289 else if (reg_renumber && reg_renumber[regno] < 0
2290 && reg_equiv_constant && reg_equiv_constant[regno]
2291 && ! CONSTANT_P (reg_equiv_constant[regno]))
2292 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2296 /* You might think handling MINUS in a manner similar to PLUS is a
2297 good idea. It is not. It has been tried multiple times and every
2298 time the change has had to have been reverted.
2300 Other parts of reload know a PLUS is special (gen_reload for example)
2301 and require special code to handle code a reloaded PLUS operand.
2303 Also consider backends where the flags register is clobbered by a
2304 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2305 lea instruction comes to mind). If we try to reload a MINUS, we
2306 may kill the flags register that was holding a useful value.
2308 So, please before trying to handle MINUS, consider reload as a
2309 whole instead of this little section as well as the backend issues. */
2311 /* If this is the sum of an eliminable register and a constant, rework
2313 if (REG_P (XEXP (x, 0))
2314 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2315 && CONSTANT_P (XEXP (x, 1)))
2317 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2319 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2321 /* The only time we want to replace a PLUS with a REG (this
2322 occurs when the constant operand of the PLUS is the negative
2323 of the offset) is when we are inside a MEM. We won't want
2324 to do so at other times because that would change the
2325 structure of the insn in a way that reload can't handle.
2326 We special-case the commonest situation in
2327 eliminate_regs_in_insn, so just replace a PLUS with a
2328 PLUS here, unless inside a MEM. */
2329 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2330 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2333 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2334 plus_constant (XEXP (x, 1),
2335 ep->previous_offset));
2338 /* If the register is not eliminable, we are done since the other
2339 operand is a constant. */
2343 /* If this is part of an address, we want to bring any constant to the
2344 outermost PLUS. We will do this by doing register replacement in
2345 our operands and seeing if a constant shows up in one of them.
2347 Note that there is no risk of modifying the structure of the insn,
2348 since we only get called for its operands, thus we are either
2349 modifying the address inside a MEM, or something like an address
2350 operand of a load-address insn. */
2353 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2354 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2356 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2358 /* If one side is a PLUS and the other side is a pseudo that
2359 didn't get a hard register but has a reg_equiv_constant,
2360 we must replace the constant here since it may no longer
2361 be in the position of any operand. */
2362 if (GET_CODE (new0) == PLUS && REG_P (new1)
2363 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2364 && reg_renumber[REGNO (new1)] < 0
2365 && reg_equiv_constant != 0
2366 && reg_equiv_constant[REGNO (new1)] != 0)
2367 new1 = reg_equiv_constant[REGNO (new1)];
2368 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2369 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2370 && reg_renumber[REGNO (new0)] < 0
2371 && reg_equiv_constant[REGNO (new0)] != 0)
2372 new0 = reg_equiv_constant[REGNO (new0)];
2374 new = form_sum (new0, new1);
2376 /* As above, if we are not inside a MEM we do not want to
2377 turn a PLUS into something else. We might try to do so here
2378 for an addition of 0 if we aren't optimizing. */
2379 if (! mem_mode && GET_CODE (new) != PLUS)
2380 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2388 /* If this is the product of an eliminable register and a
2389 constant, apply the distribute law and move the constant out
2390 so that we have (plus (mult ..) ..). This is needed in order
2391 to keep load-address insns valid. This case is pathological.
2392 We ignore the possibility of overflow here. */
2393 if (REG_P (XEXP (x, 0))
2394 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2395 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2396 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2398 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2401 /* Refs inside notes don't count for this purpose. */
2402 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2403 || GET_CODE (insn) == INSN_LIST)))
2404 ep->ref_outside_mem = 1;
2407 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2408 ep->previous_offset * INTVAL (XEXP (x, 1)));
2411 /* ... fall through ... */
2415 /* See comments before PLUS about handling MINUS. */
2417 case DIV: case UDIV:
2418 case MOD: case UMOD:
2419 case AND: case IOR: case XOR:
2420 case ROTATERT: case ROTATE:
2421 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2423 case GE: case GT: case GEU: case GTU:
2424 case LE: case LT: case LEU: case LTU:
2426 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2428 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2430 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2431 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2436 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2439 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2440 if (new != XEXP (x, 0))
2442 /* If this is a REG_DEAD note, it is not valid anymore.
2443 Using the eliminated version could result in creating a
2444 REG_DEAD note for the stack or frame pointer. */
2445 if (GET_MODE (x) == REG_DEAD)
2447 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2450 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2454 /* ... fall through ... */
2457 /* Now do eliminations in the rest of the chain. If this was
2458 an EXPR_LIST, this might result in allocating more memory than is
2459 strictly needed, but it simplifies the code. */
2462 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2463 if (new != XEXP (x, 1))
2465 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2473 case STRICT_LOW_PART:
2475 case SIGN_EXTEND: case ZERO_EXTEND:
2476 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2477 case FLOAT: case FIX:
2478 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2486 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2487 if (new != XEXP (x, 0))
2488 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2492 /* Similar to above processing, but preserve SUBREG_BYTE.
2493 Convert (subreg (mem)) to (mem) if not paradoxical.
2494 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2495 pseudo didn't get a hard reg, we must replace this with the
2496 eliminated version of the memory location because push_reload
2497 may do the replacement in certain circumstances. */
2498 if (REG_P (SUBREG_REG (x))
2499 && (GET_MODE_SIZE (GET_MODE (x))
2500 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2501 && reg_equiv_memory_loc != 0
2502 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2504 new = SUBREG_REG (x);
2507 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2509 if (new != SUBREG_REG (x))
2511 int x_size = GET_MODE_SIZE (GET_MODE (x));
2512 int new_size = GET_MODE_SIZE (GET_MODE (new));
2515 && ((x_size < new_size
2516 #ifdef WORD_REGISTER_OPERATIONS
2517 /* On these machines, combine can create rtl of the form
2518 (set (subreg:m1 (reg:m2 R) 0) ...)
2519 where m1 < m2, and expects something interesting to
2520 happen to the entire word. Moreover, it will use the
2521 (reg:m2 R) later, expecting all bits to be preserved.
2522 So if the number of words is the same, preserve the
2523 subreg so that push_reload can see it. */
2524 && ! ((x_size - 1) / UNITS_PER_WORD
2525 == (new_size -1 ) / UNITS_PER_WORD)
2528 || x_size == new_size)
2530 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2532 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2538 /* Our only special processing is to pass the mode of the MEM to our
2539 recursive call and copy the flags. While we are here, handle this
2540 case more efficiently. */
2542 replace_equiv_address_nv (x,
2543 eliminate_regs (XEXP (x, 0),
2544 GET_MODE (x), insn));
2547 /* Handle insn_list USE that a call to a pure function may generate. */
2548 new = eliminate_regs (XEXP (x, 0), 0, insn);
2549 if (new != XEXP (x, 0))
2550 return gen_rtx_USE (GET_MODE (x), new);
2562 /* Process each of our operands recursively. If any have changed, make a
2564 fmt = GET_RTX_FORMAT (code);
2565 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2569 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2570 if (new != XEXP (x, i) && ! copied)
2572 rtx new_x = rtx_alloc (code);
2573 memcpy (new_x, x, RTX_SIZE (code));
2579 else if (*fmt == 'E')
2582 for (j = 0; j < XVECLEN (x, i); j++)
2584 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2585 if (new != XVECEXP (x, i, j) && ! copied_vec)
2587 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2591 rtx new_x = rtx_alloc (code);
2592 memcpy (new_x, x, RTX_SIZE (code));
2596 XVEC (x, i) = new_v;
2599 XVECEXP (x, i, j) = new;
2607 /* Scan rtx X for modifications of elimination target registers. Update
2608 the table of eliminables to reflect the changed state. MEM_MODE is
2609 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2612 elimination_effects (rtx x, enum machine_mode mem_mode)
2614 enum rtx_code code = GET_CODE (x);
2615 struct elim_table *ep;
2639 /* First handle the case where we encounter a bare register that
2640 is eliminable. Replace it with a PLUS. */
2641 if (regno < FIRST_PSEUDO_REGISTER)
2643 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2645 if (ep->from_rtx == x && ep->can_eliminate)
2648 ep->ref_outside_mem = 1;
2653 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2654 && reg_equiv_constant[regno]
2655 && ! function_invariant_p (reg_equiv_constant[regno]))
2656 elimination_effects (reg_equiv_constant[regno], mem_mode);
2665 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2666 if (ep->to_rtx == XEXP (x, 0))
2668 int size = GET_MODE_SIZE (mem_mode);
2670 /* If more bytes than MEM_MODE are pushed, account for them. */
2671 #ifdef PUSH_ROUNDING
2672 if (ep->to_rtx == stack_pointer_rtx)
2673 size = PUSH_ROUNDING (size);
2675 if (code == PRE_DEC || code == POST_DEC)
2677 else if (code == PRE_INC || code == POST_INC)
2679 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2680 && GET_CODE (XEXP (x, 1)) == PLUS
2681 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2682 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2683 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2686 /* These two aren't unary operators. */
2687 if (code == POST_MODIFY || code == PRE_MODIFY)
2690 /* Fall through to generic unary operation case. */
2691 case STRICT_LOW_PART:
2693 case SIGN_EXTEND: case ZERO_EXTEND:
2694 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2695 case FLOAT: case FIX:
2696 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2704 elimination_effects (XEXP (x, 0), mem_mode);
2708 if (REG_P (SUBREG_REG (x))
2709 && (GET_MODE_SIZE (GET_MODE (x))
2710 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2711 && reg_equiv_memory_loc != 0
2712 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2715 elimination_effects (SUBREG_REG (x), mem_mode);
2719 /* If using a register that is the source of an eliminate we still
2720 think can be performed, note it cannot be performed since we don't
2721 know how this register is used. */
2722 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2723 if (ep->from_rtx == XEXP (x, 0))
2724 ep->can_eliminate = 0;
2726 elimination_effects (XEXP (x, 0), mem_mode);
2730 /* If clobbering a register that is the replacement register for an
2731 elimination we still think can be performed, note that it cannot
2732 be performed. Otherwise, we need not be concerned about it. */
2733 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2734 if (ep->to_rtx == XEXP (x, 0))
2735 ep->can_eliminate = 0;
2737 elimination_effects (XEXP (x, 0), mem_mode);
2741 /* Check for setting a register that we know about. */
2742 if (REG_P (SET_DEST (x)))
2744 /* See if this is setting the replacement register for an
2747 If DEST is the hard frame pointer, we do nothing because we
2748 assume that all assignments to the frame pointer are for
2749 non-local gotos and are being done at a time when they are valid
2750 and do not disturb anything else. Some machines want to
2751 eliminate a fake argument pointer (or even a fake frame pointer)
2752 with either the real frame or the stack pointer. Assignments to
2753 the hard frame pointer must not prevent this elimination. */
2755 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2757 if (ep->to_rtx == SET_DEST (x)
2758 && SET_DEST (x) != hard_frame_pointer_rtx)
2760 /* If it is being incremented, adjust the offset. Otherwise,
2761 this elimination can't be done. */
2762 rtx src = SET_SRC (x);
2764 if (GET_CODE (src) == PLUS
2765 && XEXP (src, 0) == SET_DEST (x)
2766 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2767 ep->offset -= INTVAL (XEXP (src, 1));
2769 ep->can_eliminate = 0;
2773 elimination_effects (SET_DEST (x), 0);
2774 elimination_effects (SET_SRC (x), 0);
2778 /* Our only special processing is to pass the mode of the MEM to our
2780 elimination_effects (XEXP (x, 0), GET_MODE (x));
2787 fmt = GET_RTX_FORMAT (code);
2788 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2791 elimination_effects (XEXP (x, i), mem_mode);
2792 else if (*fmt == 'E')
2793 for (j = 0; j < XVECLEN (x, i); j++)
2794 elimination_effects (XVECEXP (x, i, j), mem_mode);
2798 /* Descend through rtx X and verify that no references to eliminable registers
2799 remain. If any do remain, mark the involved register as not
2803 check_eliminable_occurrences (rtx x)
2812 code = GET_CODE (x);
2814 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2816 struct elim_table *ep;
2818 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2819 if (ep->from_rtx == x)
2820 ep->can_eliminate = 0;
2824 fmt = GET_RTX_FORMAT (code);
2825 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2828 check_eliminable_occurrences (XEXP (x, i));
2829 else if (*fmt == 'E')
2832 for (j = 0; j < XVECLEN (x, i); j++)
2833 check_eliminable_occurrences (XVECEXP (x, i, j));
2838 /* Scan INSN and eliminate all eliminable registers in it.
2840 If REPLACE is nonzero, do the replacement destructively. Also
2841 delete the insn as dead it if it is setting an eliminable register.
2843 If REPLACE is zero, do all our allocations in reload_obstack.
2845 If no eliminations were done and this insn doesn't require any elimination
2846 processing (these are not identical conditions: it might be updating sp,
2847 but not referencing fp; this needs to be seen during reload_as_needed so
2848 that the offset between fp and sp can be taken into consideration), zero
2849 is returned. Otherwise, 1 is returned. */
2852 eliminate_regs_in_insn (rtx insn, int replace)
2854 int icode = recog_memoized (insn);
2855 rtx old_body = PATTERN (insn);
2856 int insn_is_asm = asm_noperands (old_body) >= 0;
2857 rtx old_set = single_set (insn);
2861 rtx substed_operand[MAX_RECOG_OPERANDS];
2862 rtx orig_operand[MAX_RECOG_OPERANDS];
2863 struct elim_table *ep;
2866 if (! insn_is_asm && icode < 0)
2868 gcc_assert (GET_CODE (PATTERN (insn)) == USE
2869 || GET_CODE (PATTERN (insn)) == CLOBBER
2870 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2871 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2872 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
2876 if (old_set != 0 && REG_P (SET_DEST (old_set))
2877 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2879 /* Check for setting an eliminable register. */
2880 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2881 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2883 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2884 /* If this is setting the frame pointer register to the
2885 hardware frame pointer register and this is an elimination
2886 that will be done (tested above), this insn is really
2887 adjusting the frame pointer downward to compensate for
2888 the adjustment done before a nonlocal goto. */
2889 if (ep->from == FRAME_POINTER_REGNUM
2890 && ep->to == HARD_FRAME_POINTER_REGNUM)
2892 rtx base = SET_SRC (old_set);
2893 rtx base_insn = insn;
2894 HOST_WIDE_INT offset = 0;
2896 while (base != ep->to_rtx)
2898 rtx prev_insn, prev_set;
2900 if (GET_CODE (base) == PLUS
2901 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2903 offset += INTVAL (XEXP (base, 1));
2904 base = XEXP (base, 0);
2906 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2907 && (prev_set = single_set (prev_insn)) != 0
2908 && rtx_equal_p (SET_DEST (prev_set), base))
2910 base = SET_SRC (prev_set);
2911 base_insn = prev_insn;
2917 if (base == ep->to_rtx)
2920 = plus_constant (ep->to_rtx, offset - ep->offset);
2922 new_body = old_body;
2925 new_body = copy_insn (old_body);
2926 if (REG_NOTES (insn))
2927 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2929 PATTERN (insn) = new_body;
2930 old_set = single_set (insn);
2932 /* First see if this insn remains valid when we
2933 make the change. If not, keep the INSN_CODE
2934 the same and let reload fit it up. */
2935 validate_change (insn, &SET_SRC (old_set), src, 1);
2936 validate_change (insn, &SET_DEST (old_set),
2938 if (! apply_change_group ())
2940 SET_SRC (old_set) = src;
2941 SET_DEST (old_set) = ep->to_rtx;
2950 /* In this case this insn isn't serving a useful purpose. We
2951 will delete it in reload_as_needed once we know that this
2952 elimination is, in fact, being done.
2954 If REPLACE isn't set, we can't delete this insn, but needn't
2955 process it since it won't be used unless something changes. */
2958 delete_dead_insn (insn);
2966 /* We allow one special case which happens to work on all machines we
2967 currently support: a single set with the source or a REG_EQUAL
2968 note being a PLUS of an eliminable register and a constant. */
2970 if (old_set && REG_P (SET_DEST (old_set)))
2972 /* First see if the source is of the form (plus (reg) CST). */
2973 if (GET_CODE (SET_SRC (old_set)) == PLUS
2974 && REG_P (XEXP (SET_SRC (old_set), 0))
2975 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
2976 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
2977 plus_src = SET_SRC (old_set);
2978 else if (REG_P (SET_SRC (old_set)))
2980 /* Otherwise, see if we have a REG_EQUAL note of the form
2981 (plus (reg) CST). */
2983 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
2985 if (REG_NOTE_KIND (links) == REG_EQUAL
2986 && GET_CODE (XEXP (links, 0)) == PLUS
2987 && REG_P (XEXP (XEXP (links, 0), 0))
2988 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT
2989 && REGNO (XEXP (XEXP (links, 0), 0)) < FIRST_PSEUDO_REGISTER)
2991 plus_src = XEXP (links, 0);
2999 rtx reg = XEXP (plus_src, 0);
3000 HOST_WIDE_INT offset = INTVAL (XEXP (plus_src, 1));
3002 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3003 if (ep->from_rtx == reg && ep->can_eliminate)
3005 offset += ep->offset;
3010 /* We assume here that if we need a PARALLEL with
3011 CLOBBERs for this assignment, we can do with the
3012 MATCH_SCRATCHes that add_clobbers allocates.
3013 There's not much we can do if that doesn't work. */
3014 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3018 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3021 rtvec vec = rtvec_alloc (num_clobbers + 1);
3023 vec->elem[0] = PATTERN (insn);
3024 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3025 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3027 gcc_assert (INSN_CODE (insn) >= 0);
3029 /* If we have a nonzero offset, and the source is already
3030 a simple REG, the following transformation would
3031 increase the cost of the insn by replacing a simple REG
3032 with (plus (reg sp) CST). So try only when plus_src
3033 comes from old_set proper, not REG_NOTES. */
3034 else if (SET_SRC (old_set) == plus_src)
3036 new_body = old_body;
3039 new_body = copy_insn (old_body);
3040 if (REG_NOTES (insn))
3041 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3043 PATTERN (insn) = new_body;
3044 old_set = single_set (insn);
3046 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3047 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3053 /* This can't have an effect on elimination offsets, so skip right
3059 /* Determine the effects of this insn on elimination offsets. */
3060 elimination_effects (old_body, 0);
3062 /* Eliminate all eliminable registers occurring in operands that
3063 can be handled by reload. */
3064 extract_insn (insn);
3065 for (i = 0; i < recog_data.n_operands; i++)
3067 orig_operand[i] = recog_data.operand[i];
3068 substed_operand[i] = recog_data.operand[i];
3070 /* For an asm statement, every operand is eliminable. */
3071 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3073 /* Check for setting a register that we know about. */
3074 if (recog_data.operand_type[i] != OP_IN
3075 && REG_P (orig_operand[i]))
3077 /* If we are assigning to a register that can be eliminated, it
3078 must be as part of a PARALLEL, since the code above handles
3079 single SETs. We must indicate that we can no longer
3080 eliminate this reg. */
3081 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3083 if (ep->from_rtx == orig_operand[i])
3084 ep->can_eliminate = 0;
3087 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3088 replace ? insn : NULL_RTX);
3089 if (substed_operand[i] != orig_operand[i])
3091 /* Terminate the search in check_eliminable_occurrences at
3093 *recog_data.operand_loc[i] = 0;
3095 /* If an output operand changed from a REG to a MEM and INSN is an
3096 insn, write a CLOBBER insn. */
3097 if (recog_data.operand_type[i] != OP_IN
3098 && REG_P (orig_operand[i])
3099 && MEM_P (substed_operand[i])
3101 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3106 for (i = 0; i < recog_data.n_dups; i++)
3107 *recog_data.dup_loc[i]
3108 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3110 /* If any eliminable remain, they aren't eliminable anymore. */
3111 check_eliminable_occurrences (old_body);
3113 /* Substitute the operands; the new values are in the substed_operand
3115 for (i = 0; i < recog_data.n_operands; i++)
3116 *recog_data.operand_loc[i] = substed_operand[i];
3117 for (i = 0; i < recog_data.n_dups; i++)
3118 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3120 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3121 re-recognize the insn. We do this in case we had a simple addition
3122 but now can do this as a load-address. This saves an insn in this
3124 If re-recognition fails, the old insn code number will still be used,
3125 and some register operands may have changed into PLUS expressions.
3126 These will be handled by find_reloads by loading them into a register
3131 /* If we aren't replacing things permanently and we changed something,
3132 make another copy to ensure that all the RTL is new. Otherwise
3133 things can go wrong if find_reload swaps commutative operands
3134 and one is inside RTL that has been copied while the other is not. */
3135 new_body = old_body;
3138 new_body = copy_insn (old_body);
3139 if (REG_NOTES (insn))
3140 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3142 PATTERN (insn) = new_body;
3144 /* If we had a move insn but now we don't, rerecognize it. This will
3145 cause spurious re-recognition if the old move had a PARALLEL since
3146 the new one still will, but we can't call single_set without
3147 having put NEW_BODY into the insn and the re-recognition won't
3148 hurt in this rare case. */
3149 /* ??? Why this huge if statement - why don't we just rerecognize the
3153 && ((REG_P (SET_SRC (old_set))
3154 && (GET_CODE (new_body) != SET
3155 || !REG_P (SET_SRC (new_body))))
3156 /* If this was a load from or store to memory, compare
3157 the MEM in recog_data.operand to the one in the insn.
3158 If they are not equal, then rerecognize the insn. */
3160 && ((MEM_P (SET_SRC (old_set))
3161 && SET_SRC (old_set) != recog_data.operand[1])
3162 || (MEM_P (SET_DEST (old_set))
3163 && SET_DEST (old_set) != recog_data.operand[0])))
3164 /* If this was an add insn before, rerecognize. */
3165 || GET_CODE (SET_SRC (old_set)) == PLUS))
3167 int new_icode = recog (PATTERN (insn), insn, 0);
3169 INSN_CODE (insn) = icode;
3173 /* Restore the old body. If there were any changes to it, we made a copy
3174 of it while the changes were still in place, so we'll correctly return
3175 a modified insn below. */
3178 /* Restore the old body. */
3179 for (i = 0; i < recog_data.n_operands; i++)
3180 *recog_data.operand_loc[i] = orig_operand[i];
3181 for (i = 0; i < recog_data.n_dups; i++)
3182 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3185 /* Update all elimination pairs to reflect the status after the current
3186 insn. The changes we make were determined by the earlier call to
3187 elimination_effects.
3189 We also detect cases where register elimination cannot be done,
3190 namely, if a register would be both changed and referenced outside a MEM
3191 in the resulting insn since such an insn is often undefined and, even if
3192 not, we cannot know what meaning will be given to it. Note that it is
3193 valid to have a register used in an address in an insn that changes it
3194 (presumably with a pre- or post-increment or decrement).
3196 If anything changes, return nonzero. */
3198 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3200 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3201 ep->can_eliminate = 0;
3203 ep->ref_outside_mem = 0;
3205 if (ep->previous_offset != ep->offset)
3210 /* If we changed something, perform elimination in REG_NOTES. This is
3211 needed even when REPLACE is zero because a REG_DEAD note might refer
3212 to a register that we eliminate and could cause a different number
3213 of spill registers to be needed in the final reload pass than in
3215 if (val && REG_NOTES (insn) != 0)
3216 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3221 /* Loop through all elimination pairs.
3222 Recalculate the number not at initial offset.
3224 Compute the maximum offset (minimum offset if the stack does not
3225 grow downward) for each elimination pair. */
3228 update_eliminable_offsets (void)
3230 struct elim_table *ep;
3232 num_not_at_initial_offset = 0;
3233 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3235 ep->previous_offset = ep->offset;
3236 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3237 num_not_at_initial_offset++;
3241 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3242 replacement we currently believe is valid, mark it as not eliminable if X
3243 modifies DEST in any way other than by adding a constant integer to it.
3245 If DEST is the frame pointer, we do nothing because we assume that
3246 all assignments to the hard frame pointer are nonlocal gotos and are being
3247 done at a time when they are valid and do not disturb anything else.
3248 Some machines want to eliminate a fake argument pointer with either the
3249 frame or stack pointer. Assignments to the hard frame pointer must not
3250 prevent this elimination.
3252 Called via note_stores from reload before starting its passes to scan
3253 the insns of the function. */
3256 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3260 /* A SUBREG of a hard register here is just changing its mode. We should
3261 not see a SUBREG of an eliminable hard register, but check just in
3263 if (GET_CODE (dest) == SUBREG)
3264 dest = SUBREG_REG (dest);
3266 if (dest == hard_frame_pointer_rtx)
3269 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3270 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3271 && (GET_CODE (x) != SET
3272 || GET_CODE (SET_SRC (x)) != PLUS
3273 || XEXP (SET_SRC (x), 0) != dest
3274 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3276 reg_eliminate[i].can_eliminate_previous
3277 = reg_eliminate[i].can_eliminate = 0;
3282 /* Verify that the initial elimination offsets did not change since the
3283 last call to set_initial_elim_offsets. This is used to catch cases
3284 where something illegal happened during reload_as_needed that could
3285 cause incorrect code to be generated if we did not check for it. */
3288 verify_initial_elim_offsets (void)
3292 #ifdef ELIMINABLE_REGS
3293 struct elim_table *ep;
3295 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3297 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3298 gcc_assert (t == ep->initial_offset);
3301 INITIAL_FRAME_POINTER_OFFSET (t);
3302 gcc_assert (t == reg_eliminate[0].initial_offset);
3306 /* Reset all offsets on eliminable registers to their initial values. */
3309 set_initial_elim_offsets (void)
3311 struct elim_table *ep = reg_eliminate;
3313 #ifdef ELIMINABLE_REGS
3314 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3316 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3317 ep->previous_offset = ep->offset = ep->initial_offset;
3320 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3321 ep->previous_offset = ep->offset = ep->initial_offset;
3324 num_not_at_initial_offset = 0;
3327 /* Initialize the known label offsets.
3328 Set a known offset for each forced label to be at the initial offset
3329 of each elimination. We do this because we assume that all
3330 computed jumps occur from a location where each elimination is
3331 at its initial offset.
3332 For all other labels, show that we don't know the offsets. */
3335 set_initial_label_offsets (void)
3338 memset (offsets_known_at, 0, num_labels);
3340 for (x = forced_labels; x; x = XEXP (x, 1))
3342 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3345 /* Set all elimination offsets to the known values for the code label given
3349 set_offsets_for_label (rtx insn)
3352 int label_nr = CODE_LABEL_NUMBER (insn);
3353 struct elim_table *ep;
3355 num_not_at_initial_offset = 0;
3356 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3358 ep->offset = ep->previous_offset
3359 = offsets_at[label_nr - first_label_num][i];
3360 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3361 num_not_at_initial_offset++;
3365 /* See if anything that happened changes which eliminations are valid.
3366 For example, on the SPARC, whether or not the frame pointer can
3367 be eliminated can depend on what registers have been used. We need
3368 not check some conditions again (such as flag_omit_frame_pointer)
3369 since they can't have changed. */
3372 update_eliminables (HARD_REG_SET *pset)
3374 int previous_frame_pointer_needed = frame_pointer_needed;
3375 struct elim_table *ep;
3377 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3378 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3379 #ifdef ELIMINABLE_REGS
3380 || ! CAN_ELIMINATE (ep->from, ep->to)
3383 ep->can_eliminate = 0;
3385 /* Look for the case where we have discovered that we can't replace
3386 register A with register B and that means that we will now be
3387 trying to replace register A with register C. This means we can
3388 no longer replace register C with register B and we need to disable
3389 such an elimination, if it exists. This occurs often with A == ap,
3390 B == sp, and C == fp. */
3392 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3394 struct elim_table *op;
3397 if (! ep->can_eliminate && ep->can_eliminate_previous)
3399 /* Find the current elimination for ep->from, if there is a
3401 for (op = reg_eliminate;
3402 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3403 if (op->from == ep->from && op->can_eliminate)
3409 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3411 for (op = reg_eliminate;
3412 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3413 if (op->from == new_to && op->to == ep->to)
3414 op->can_eliminate = 0;
3418 /* See if any registers that we thought we could eliminate the previous
3419 time are no longer eliminable. If so, something has changed and we
3420 must spill the register. Also, recompute the number of eliminable
3421 registers and see if the frame pointer is needed; it is if there is
3422 no elimination of the frame pointer that we can perform. */
3424 frame_pointer_needed = 1;
3425 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3427 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3428 && ep->to != HARD_FRAME_POINTER_REGNUM)
3429 frame_pointer_needed = 0;
3431 if (! ep->can_eliminate && ep->can_eliminate_previous)
3433 ep->can_eliminate_previous = 0;
3434 SET_HARD_REG_BIT (*pset, ep->from);
3439 /* If we didn't need a frame pointer last time, but we do now, spill
3440 the hard frame pointer. */
3441 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3442 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3445 /* Initialize the table of registers to eliminate. */
3448 init_elim_table (void)
3450 struct elim_table *ep;
3451 #ifdef ELIMINABLE_REGS
3452 const struct elim_table_1 *ep1;
3456 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3458 /* Does this function require a frame pointer? */
3460 frame_pointer_needed = (! flag_omit_frame_pointer
3461 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3462 and restore sp for alloca. So we can't eliminate
3463 the frame pointer in that case. At some point,
3464 we should improve this by emitting the
3465 sp-adjusting insns for this case. */
3466 || (current_function_calls_alloca
3467 && EXIT_IGNORE_STACK)
3468 || FRAME_POINTER_REQUIRED);
3472 #ifdef ELIMINABLE_REGS
3473 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3474 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3476 ep->from = ep1->from;
3478 ep->can_eliminate = ep->can_eliminate_previous
3479 = (CAN_ELIMINATE (ep->from, ep->to)
3480 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3483 reg_eliminate[0].from = reg_eliminate_1[0].from;
3484 reg_eliminate[0].to = reg_eliminate_1[0].to;
3485 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3486 = ! frame_pointer_needed;
3489 /* Count the number of eliminable registers and build the FROM and TO
3490 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3491 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3492 We depend on this. */
3493 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3495 num_eliminable += ep->can_eliminate;
3496 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3497 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3501 /* Kick all pseudos out of hard register REGNO.
3503 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3504 because we found we can't eliminate some register. In the case, no pseudos
3505 are allowed to be in the register, even if they are only in a block that
3506 doesn't require spill registers, unlike the case when we are spilling this
3507 hard reg to produce another spill register.
3509 Return nonzero if any pseudos needed to be kicked out. */
3512 spill_hard_reg (unsigned int regno, int cant_eliminate)
3518 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3519 regs_ever_live[regno] = 1;
3522 /* Spill every pseudo reg that was allocated to this reg
3523 or to something that overlaps this reg. */
3525 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3526 if (reg_renumber[i] >= 0
3527 && (unsigned int) reg_renumber[i] <= regno
3528 && ((unsigned int) reg_renumber[i]
3529 + hard_regno_nregs[(unsigned int) reg_renumber[i]]
3530 [PSEUDO_REGNO_MODE (i)]
3532 SET_REGNO_REG_SET (&spilled_pseudos, i);
3535 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3536 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3539 ior_hard_reg_set (HARD_REG_SET *set1, HARD_REG_SET *set2)
3541 IOR_HARD_REG_SET (*set1, *set2);
3544 /* After find_reload_regs has been run for all insn that need reloads,
3545 and/or spill_hard_regs was called, this function is used to actually
3546 spill pseudo registers and try to reallocate them. It also sets up the
3547 spill_regs array for use by choose_reload_regs. */
3550 finish_spills (int global)
3552 struct insn_chain *chain;
3553 int something_changed = 0;
3556 /* Build the spill_regs array for the function. */
3557 /* If there are some registers still to eliminate and one of the spill regs
3558 wasn't ever used before, additional stack space may have to be
3559 allocated to store this register. Thus, we may have changed the offset
3560 between the stack and frame pointers, so mark that something has changed.
3562 One might think that we need only set VAL to 1 if this is a call-used
3563 register. However, the set of registers that must be saved by the
3564 prologue is not identical to the call-used set. For example, the
3565 register used by the call insn for the return PC is a call-used register,
3566 but must be saved by the prologue. */
3569 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3570 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3572 spill_reg_order[i] = n_spills;
3573 spill_regs[n_spills++] = i;
3574 if (num_eliminable && ! regs_ever_live[i])
3575 something_changed = 1;
3576 regs_ever_live[i] = 1;
3579 spill_reg_order[i] = -1;
3581 EXECUTE_IF_SET_IN_REG_SET
3582 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3584 /* Record the current hard register the pseudo is allocated to in
3585 pseudo_previous_regs so we avoid reallocating it to the same
3586 hard reg in a later pass. */
3587 gcc_assert (reg_renumber[i] >= 0);
3589 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3590 /* Mark it as no longer having a hard register home. */
3591 reg_renumber[i] = -1;
3592 /* We will need to scan everything again. */
3593 something_changed = 1;
3596 /* Retry global register allocation if possible. */
3599 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3600 /* For every insn that needs reloads, set the registers used as spill
3601 regs in pseudo_forbidden_regs for every pseudo live across the
3603 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3605 EXECUTE_IF_SET_IN_REG_SET
3606 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3608 ior_hard_reg_set (pseudo_forbidden_regs + i,
3609 &chain->used_spill_regs);
3611 EXECUTE_IF_SET_IN_REG_SET
3612 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3614 ior_hard_reg_set (pseudo_forbidden_regs + i,
3615 &chain->used_spill_regs);
3619 /* Retry allocating the spilled pseudos. For each reg, merge the
3620 various reg sets that indicate which hard regs can't be used,
3621 and call retry_global_alloc.
3622 We change spill_pseudos here to only contain pseudos that did not
3623 get a new hard register. */
3624 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3625 if (reg_old_renumber[i] != reg_renumber[i])
3627 HARD_REG_SET forbidden;
3628 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3629 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3630 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3631 retry_global_alloc (i, forbidden);
3632 if (reg_renumber[i] >= 0)
3633 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3637 /* Fix up the register information in the insn chain.
3638 This involves deleting those of the spilled pseudos which did not get
3639 a new hard register home from the live_{before,after} sets. */
3640 for (chain = reload_insn_chain; chain; chain = chain->next)
3642 HARD_REG_SET used_by_pseudos;
3643 HARD_REG_SET used_by_pseudos2;
3645 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3646 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3648 /* Mark any unallocated hard regs as available for spills. That
3649 makes inheritance work somewhat better. */
3650 if (chain->need_reload)
3652 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3653 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3654 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3656 /* Save the old value for the sanity test below. */
3657 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3659 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3660 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3661 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3662 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3664 /* Make sure we only enlarge the set. */
3665 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3671 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3672 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3674 int regno = reg_renumber[i];
3675 if (reg_old_renumber[i] == regno)
3678 alter_reg (i, reg_old_renumber[i]);
3679 reg_old_renumber[i] = regno;
3683 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3685 fprintf (dump_file, " Register %d now in %d.\n\n",
3686 i, reg_renumber[i]);
3690 return something_changed;
3693 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3696 scan_paradoxical_subregs (rtx x)
3700 enum rtx_code code = GET_CODE (x);
3710 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3718 if (REG_P (SUBREG_REG (x))
3719 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3720 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3721 = GET_MODE_SIZE (GET_MODE (x));
3728 fmt = GET_RTX_FORMAT (code);
3729 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3732 scan_paradoxical_subregs (XEXP (x, i));
3733 else if (fmt[i] == 'E')
3736 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3737 scan_paradoxical_subregs (XVECEXP (x, i, j));
3742 /* Reload pseudo-registers into hard regs around each insn as needed.
3743 Additional register load insns are output before the insn that needs it
3744 and perhaps store insns after insns that modify the reloaded pseudo reg.
3746 reg_last_reload_reg and reg_reloaded_contents keep track of
3747 which registers are already available in reload registers.
3748 We update these for the reloads that we perform,
3749 as the insns are scanned. */
3752 reload_as_needed (int live_known)
3754 struct insn_chain *chain;
3755 #if defined (AUTO_INC_DEC)
3760 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3761 memset (spill_reg_store, 0, sizeof spill_reg_store);
3762 reg_last_reload_reg = xcalloc (max_regno, sizeof (rtx));
3763 reg_has_output_reload = xmalloc (max_regno);
3764 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3765 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
3767 set_initial_elim_offsets ();
3769 for (chain = reload_insn_chain; chain; chain = chain->next)
3772 rtx insn = chain->insn;
3773 rtx old_next = NEXT_INSN (insn);
3775 /* If we pass a label, copy the offsets from the label information
3776 into the current offsets of each elimination. */
3778 set_offsets_for_label (insn);
3780 else if (INSN_P (insn))
3782 rtx oldpat = copy_rtx (PATTERN (insn));
3784 /* If this is a USE and CLOBBER of a MEM, ensure that any
3785 references to eliminable registers have been removed. */
3787 if ((GET_CODE (PATTERN (insn)) == USE
3788 || GET_CODE (PATTERN (insn)) == CLOBBER)
3789 && MEM_P (XEXP (PATTERN (insn), 0)))
3790 XEXP (XEXP (PATTERN (insn), 0), 0)
3791 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3792 GET_MODE (XEXP (PATTERN (insn), 0)),
3795 /* If we need to do register elimination processing, do so.
3796 This might delete the insn, in which case we are done. */
3797 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3799 eliminate_regs_in_insn (insn, 1);
3802 update_eliminable_offsets ();
3807 /* If need_elim is nonzero but need_reload is zero, one might think
3808 that we could simply set n_reloads to 0. However, find_reloads
3809 could have done some manipulation of the insn (such as swapping
3810 commutative operands), and these manipulations are lost during
3811 the first pass for every insn that needs register elimination.
3812 So the actions of find_reloads must be redone here. */
3814 if (! chain->need_elim && ! chain->need_reload
3815 && ! chain->need_operand_change)
3817 /* First find the pseudo regs that must be reloaded for this insn.
3818 This info is returned in the tables reload_... (see reload.h).
3819 Also modify the body of INSN by substituting RELOAD
3820 rtx's for those pseudo regs. */
3823 memset (reg_has_output_reload, 0, max_regno);
3824 CLEAR_HARD_REG_SET (reg_is_output_reload);
3826 find_reloads (insn, 1, spill_indirect_levels, live_known,
3832 rtx next = NEXT_INSN (insn);
3835 prev = PREV_INSN (insn);
3837 /* Now compute which reload regs to reload them into. Perhaps
3838 reusing reload regs from previous insns, or else output
3839 load insns to reload them. Maybe output store insns too.
3840 Record the choices of reload reg in reload_reg_rtx. */
3841 choose_reload_regs (chain);
3843 /* Merge any reloads that we didn't combine for fear of
3844 increasing the number of spill registers needed but now
3845 discover can be safely merged. */
3846 if (SMALL_REGISTER_CLASSES)
3847 merge_assigned_reloads (insn);
3849 /* Generate the insns to reload operands into or out of
3850 their reload regs. */
3851 emit_reload_insns (chain);
3853 /* Substitute the chosen reload regs from reload_reg_rtx
3854 into the insn's body (or perhaps into the bodies of other
3855 load and store insn that we just made for reloading
3856 and that we moved the structure into). */
3857 subst_reloads (insn);
3859 /* If this was an ASM, make sure that all the reload insns
3860 we have generated are valid. If not, give an error
3863 if (asm_noperands (PATTERN (insn)) >= 0)
3864 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3865 if (p != insn && INSN_P (p)
3866 && GET_CODE (PATTERN (p)) != USE
3867 && (recog_memoized (p) < 0
3868 || (extract_insn (p), ! constrain_operands (1))))
3870 error_for_asm (insn,
3871 "%<asm%> operand requires "
3872 "impossible reload");
3877 if (num_eliminable && chain->need_elim)
3878 update_eliminable_offsets ();
3880 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3881 is no longer validly lying around to save a future reload.
3882 Note that this does not detect pseudos that were reloaded
3883 for this insn in order to be stored in
3884 (obeying register constraints). That is correct; such reload
3885 registers ARE still valid. */
3886 note_stores (oldpat, forget_old_reloads_1, NULL);
3888 /* There may have been CLOBBER insns placed after INSN. So scan
3889 between INSN and NEXT and use them to forget old reloads. */
3890 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3891 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
3892 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3895 /* Likewise for regs altered by auto-increment in this insn.
3896 REG_INC notes have been changed by reloading:
3897 find_reloads_address_1 records substitutions for them,
3898 which have been performed by subst_reloads above. */
3899 for (i = n_reloads - 1; i >= 0; i--)
3901 rtx in_reg = rld[i].in_reg;
3904 enum rtx_code code = GET_CODE (in_reg);
3905 /* PRE_INC / PRE_DEC will have the reload register ending up
3906 with the same value as the stack slot, but that doesn't
3907 hold true for POST_INC / POST_DEC. Either we have to
3908 convert the memory access to a true POST_INC / POST_DEC,
3909 or we can't use the reload register for inheritance. */
3910 if ((code == POST_INC || code == POST_DEC)
3911 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3912 REGNO (rld[i].reg_rtx))
3913 /* Make sure it is the inc/dec pseudo, and not
3914 some other (e.g. output operand) pseudo. */
3915 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3916 == REGNO (XEXP (in_reg, 0))))
3919 rtx reload_reg = rld[i].reg_rtx;
3920 enum machine_mode mode = GET_MODE (reload_reg);
3924 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3926 /* We really want to ignore REG_INC notes here, so
3927 use PATTERN (p) as argument to reg_set_p . */
3928 if (reg_set_p (reload_reg, PATTERN (p)))
3930 n = count_occurrences (PATTERN (p), reload_reg, 0);
3935 n = validate_replace_rtx (reload_reg,
3936 gen_rtx_fmt_e (code,
3941 /* We must also verify that the constraints
3942 are met after the replacement. */
3945 n = constrain_operands (1);
3949 /* If the constraints were not met, then
3950 undo the replacement. */
3953 validate_replace_rtx (gen_rtx_fmt_e (code,
3966 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3968 /* Mark this as having an output reload so that the
3969 REG_INC processing code below won't invalidate
3970 the reload for inheritance. */
3971 SET_HARD_REG_BIT (reg_is_output_reload,
3972 REGNO (reload_reg));
3973 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3976 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
3979 else if ((code == PRE_INC || code == PRE_DEC)
3980 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3981 REGNO (rld[i].reg_rtx))
3982 /* Make sure it is the inc/dec pseudo, and not
3983 some other (e.g. output operand) pseudo. */
3984 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3985 == REGNO (XEXP (in_reg, 0))))
3987 SET_HARD_REG_BIT (reg_is_output_reload,
3988 REGNO (rld[i].reg_rtx));
3989 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3993 /* If a pseudo that got a hard register is auto-incremented,
3994 we must purge records of copying it into pseudos without
3996 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3997 if (REG_NOTE_KIND (x) == REG_INC)
3999 /* See if this pseudo reg was reloaded in this insn.
4000 If so, its last-reload info is still valid
4001 because it is based on this insn's reload. */
4002 for (i = 0; i < n_reloads; i++)
4003 if (rld[i].out == XEXP (x, 0))
4007 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4011 /* A reload reg's contents are unknown after a label. */
4013 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4015 /* Don't assume a reload reg is still good after a call insn
4016 if it is a call-used reg, or if it contains a value that will
4017 be partially clobbered by the call. */
4018 else if (CALL_P (insn))
4020 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4021 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4026 free (reg_last_reload_reg);
4027 free (reg_has_output_reload);
4030 /* Discard all record of any value reloaded from X,
4031 or reloaded in X from someplace else;
4032 unless X is an output reload reg of the current insn.
4034 X may be a hard reg (the reload reg)
4035 or it may be a pseudo reg that was reloaded from. */
4038 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4039 void *data ATTRIBUTE_UNUSED)
4044 /* note_stores does give us subregs of hard regs,
4045 subreg_regno_offset will abort if it is not a hard reg. */
4046 while (GET_CODE (x) == SUBREG)
4048 /* We ignore the subreg offset when calculating the regno,
4049 because we are using the entire underlying hard register
4059 if (regno >= FIRST_PSEUDO_REGISTER)
4065 nr = hard_regno_nregs[regno][GET_MODE (x)];
4066 /* Storing into a spilled-reg invalidates its contents.
4067 This can happen if a block-local pseudo is allocated to that reg
4068 and it wasn't spilled because this block's total need is 0.
4069 Then some insn might have an optional reload and use this reg. */
4070 for (i = 0; i < nr; i++)
4071 /* But don't do this if the reg actually serves as an output
4072 reload reg in the current instruction. */
4074 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4076 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4077 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4078 spill_reg_store[regno + i] = 0;
4082 /* Since value of X has changed,
4083 forget any value previously copied from it. */
4086 /* But don't forget a copy if this is the output reload
4087 that establishes the copy's validity. */
4088 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4089 reg_last_reload_reg[regno + nr] = 0;
4092 /* The following HARD_REG_SETs indicate when each hard register is
4093 used for a reload of various parts of the current insn. */
4095 /* If reg is unavailable for all reloads. */
4096 static HARD_REG_SET reload_reg_unavailable;
4097 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4098 static HARD_REG_SET reload_reg_used;
4099 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4100 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4101 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4102 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4103 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4104 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4105 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4106 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4107 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4108 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4109 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4110 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4111 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4112 static HARD_REG_SET reload_reg_used_in_op_addr;
4113 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4114 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4115 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4116 static HARD_REG_SET reload_reg_used_in_insn;
4117 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4118 static HARD_REG_SET reload_reg_used_in_other_addr;
4120 /* If reg is in use as a reload reg for any sort of reload. */
4121 static HARD_REG_SET reload_reg_used_at_all;
4123 /* If reg is use as an inherited reload. We just mark the first register
4125 static HARD_REG_SET reload_reg_used_for_inherit;
4127 /* Records which hard regs are used in any way, either as explicit use or
4128 by being allocated to a pseudo during any point of the current insn. */
4129 static HARD_REG_SET reg_used_in_insn;
4131 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4132 TYPE. MODE is used to indicate how many consecutive regs are
4136 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4137 enum machine_mode mode)
4139 unsigned int nregs = hard_regno_nregs[regno][mode];
4142 for (i = regno; i < nregs + regno; i++)
4147 SET_HARD_REG_BIT (reload_reg_used, i);
4150 case RELOAD_FOR_INPUT_ADDRESS:
4151 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4154 case RELOAD_FOR_INPADDR_ADDRESS:
4155 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4158 case RELOAD_FOR_OUTPUT_ADDRESS:
4159 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4162 case RELOAD_FOR_OUTADDR_ADDRESS:
4163 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4166 case RELOAD_FOR_OPERAND_ADDRESS:
4167 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4170 case RELOAD_FOR_OPADDR_ADDR:
4171 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4174 case RELOAD_FOR_OTHER_ADDRESS:
4175 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4178 case RELOAD_FOR_INPUT:
4179 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4182 case RELOAD_FOR_OUTPUT:
4183 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4186 case RELOAD_FOR_INSN:
4187 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4191 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4195 /* Similarly, but show REGNO is no longer in use for a reload. */
4198 clear_reload_reg_in_use (unsigned int regno, int opnum,
4199 enum reload_type type, enum machine_mode mode)
4201 unsigned int nregs = hard_regno_nregs[regno][mode];
4202 unsigned int start_regno, end_regno, r;
4204 /* A complication is that for some reload types, inheritance might
4205 allow multiple reloads of the same types to share a reload register.
4206 We set check_opnum if we have to check only reloads with the same
4207 operand number, and check_any if we have to check all reloads. */
4208 int check_opnum = 0;
4210 HARD_REG_SET *used_in_set;
4215 used_in_set = &reload_reg_used;
4218 case RELOAD_FOR_INPUT_ADDRESS:
4219 used_in_set = &reload_reg_used_in_input_addr[opnum];
4222 case RELOAD_FOR_INPADDR_ADDRESS:
4224 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4227 case RELOAD_FOR_OUTPUT_ADDRESS:
4228 used_in_set = &reload_reg_used_in_output_addr[opnum];
4231 case RELOAD_FOR_OUTADDR_ADDRESS:
4233 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4236 case RELOAD_FOR_OPERAND_ADDRESS:
4237 used_in_set = &reload_reg_used_in_op_addr;
4240 case RELOAD_FOR_OPADDR_ADDR:
4242 used_in_set = &reload_reg_used_in_op_addr_reload;
4245 case RELOAD_FOR_OTHER_ADDRESS:
4246 used_in_set = &reload_reg_used_in_other_addr;
4250 case RELOAD_FOR_INPUT:
4251 used_in_set = &reload_reg_used_in_input[opnum];
4254 case RELOAD_FOR_OUTPUT:
4255 used_in_set = &reload_reg_used_in_output[opnum];
4258 case RELOAD_FOR_INSN:
4259 used_in_set = &reload_reg_used_in_insn;
4264 /* We resolve conflicts with remaining reloads of the same type by
4265 excluding the intervals of reload registers by them from the
4266 interval of freed reload registers. Since we only keep track of
4267 one set of interval bounds, we might have to exclude somewhat
4268 more than what would be necessary if we used a HARD_REG_SET here.
4269 But this should only happen very infrequently, so there should
4270 be no reason to worry about it. */
4272 start_regno = regno;
4273 end_regno = regno + nregs;
4274 if (check_opnum || check_any)
4276 for (i = n_reloads - 1; i >= 0; i--)
4278 if (rld[i].when_needed == type
4279 && (check_any || rld[i].opnum == opnum)
4282 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4283 unsigned int conflict_end
4285 + hard_regno_nregs[conflict_start][rld[i].mode]);
4287 /* If there is an overlap with the first to-be-freed register,
4288 adjust the interval start. */
4289 if (conflict_start <= start_regno && conflict_end > start_regno)
4290 start_regno = conflict_end;
4291 /* Otherwise, if there is a conflict with one of the other
4292 to-be-freed registers, adjust the interval end. */
4293 if (conflict_start > start_regno && conflict_start < end_regno)
4294 end_regno = conflict_start;
4299 for (r = start_regno; r < end_regno; r++)
4300 CLEAR_HARD_REG_BIT (*used_in_set, r);
4303 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4304 specified by OPNUM and TYPE. */
4307 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4311 /* In use for a RELOAD_OTHER means it's not available for anything. */
4312 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4313 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4319 /* In use for anything means we can't use it for RELOAD_OTHER. */
4320 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4321 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4322 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4323 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4326 for (i = 0; i < reload_n_operands; i++)
4327 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4328 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4329 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4330 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4331 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4332 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4337 case RELOAD_FOR_INPUT:
4338 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4339 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4342 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4345 /* If it is used for some other input, can't use it. */
4346 for (i = 0; i < reload_n_operands; i++)
4347 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4350 /* If it is used in a later operand's address, can't use it. */
4351 for (i = opnum + 1; i < reload_n_operands; i++)
4352 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4353 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4358 case RELOAD_FOR_INPUT_ADDRESS:
4359 /* Can't use a register if it is used for an input address for this
4360 operand or used as an input in an earlier one. */
4361 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4362 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4365 for (i = 0; i < opnum; i++)
4366 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4371 case RELOAD_FOR_INPADDR_ADDRESS:
4372 /* Can't use a register if it is used for an input address
4373 for this operand or used as an input in an earlier
4375 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4378 for (i = 0; i < opnum; i++)
4379 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4384 case RELOAD_FOR_OUTPUT_ADDRESS:
4385 /* Can't use a register if it is used for an output address for this
4386 operand or used as an output in this or a later operand. Note
4387 that multiple output operands are emitted in reverse order, so
4388 the conflicting ones are those with lower indices. */
4389 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4392 for (i = 0; i <= opnum; i++)
4393 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4398 case RELOAD_FOR_OUTADDR_ADDRESS:
4399 /* Can't use a register if it is used for an output address
4400 for this operand or used as an output in this or a
4401 later operand. Note that multiple output operands are
4402 emitted in reverse order, so the conflicting ones are
4403 those with lower indices. */
4404 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4407 for (i = 0; i <= opnum; i++)
4408 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4413 case RELOAD_FOR_OPERAND_ADDRESS:
4414 for (i = 0; i < reload_n_operands; i++)
4415 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4418 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4419 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4421 case RELOAD_FOR_OPADDR_ADDR:
4422 for (i = 0; i < reload_n_operands; i++)
4423 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4426 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4428 case RELOAD_FOR_OUTPUT:
4429 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4430 outputs, or an operand address for this or an earlier output.
4431 Note that multiple output operands are emitted in reverse order,
4432 so the conflicting ones are those with higher indices. */
4433 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4436 for (i = 0; i < reload_n_operands; i++)
4437 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4440 for (i = opnum; i < reload_n_operands; i++)
4441 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4442 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4447 case RELOAD_FOR_INSN:
4448 for (i = 0; i < reload_n_operands; i++)
4449 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4450 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4453 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4454 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4456 case RELOAD_FOR_OTHER_ADDRESS:
4457 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4464 /* Return 1 if the value in reload reg REGNO, as used by a reload
4465 needed for the part of the insn specified by OPNUM and TYPE,
4466 is still available in REGNO at the end of the insn.
4468 We can assume that the reload reg was already tested for availability
4469 at the time it is needed, and we should not check this again,
4470 in case the reg has already been marked in use. */
4473 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4480 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4481 its value must reach the end. */
4484 /* If this use is for part of the insn,
4485 its value reaches if no subsequent part uses the same register.
4486 Just like the above function, don't try to do this with lots
4489 case RELOAD_FOR_OTHER_ADDRESS:
4490 /* Here we check for everything else, since these don't conflict
4491 with anything else and everything comes later. */
4493 for (i = 0; i < reload_n_operands; i++)
4494 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4495 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4496 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4497 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4498 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4499 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4502 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4503 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4504 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4505 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4507 case RELOAD_FOR_INPUT_ADDRESS:
4508 case RELOAD_FOR_INPADDR_ADDRESS:
4509 /* Similar, except that we check only for this and subsequent inputs
4510 and the address of only subsequent inputs and we do not need
4511 to check for RELOAD_OTHER objects since they are known not to
4514 for (i = opnum; i < reload_n_operands; i++)
4515 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4518 for (i = opnum + 1; i < reload_n_operands; i++)
4519 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4520 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4523 for (i = 0; i < reload_n_operands; i++)
4524 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4525 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4526 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4529 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4532 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4533 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4534 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4536 case RELOAD_FOR_INPUT:
4537 /* Similar to input address, except we start at the next operand for
4538 both input and input address and we do not check for
4539 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4542 for (i = opnum + 1; i < reload_n_operands; i++)
4543 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4544 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4545 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4548 /* ... fall through ... */
4550 case RELOAD_FOR_OPERAND_ADDRESS:
4551 /* Check outputs and their addresses. */
4553 for (i = 0; i < reload_n_operands; i++)
4554 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4555 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4556 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4559 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4561 case RELOAD_FOR_OPADDR_ADDR:
4562 for (i = 0; i < reload_n_operands; i++)
4563 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4564 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4565 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4568 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4569 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4570 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4572 case RELOAD_FOR_INSN:
4573 /* These conflict with other outputs with RELOAD_OTHER. So
4574 we need only check for output addresses. */
4576 opnum = reload_n_operands;
4578 /* ... fall through ... */
4580 case RELOAD_FOR_OUTPUT:
4581 case RELOAD_FOR_OUTPUT_ADDRESS:
4582 case RELOAD_FOR_OUTADDR_ADDRESS:
4583 /* We already know these can't conflict with a later output. So the
4584 only thing to check are later output addresses.
4585 Note that multiple output operands are emitted in reverse order,
4586 so the conflicting ones are those with lower indices. */
4587 for (i = 0; i < opnum; i++)
4588 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4589 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4599 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4602 This function uses the same algorithm as reload_reg_free_p above. */
4605 reloads_conflict (int r1, int r2)
4607 enum reload_type r1_type = rld[r1].when_needed;
4608 enum reload_type r2_type = rld[r2].when_needed;
4609 int r1_opnum = rld[r1].opnum;
4610 int r2_opnum = rld[r2].opnum;
4612 /* RELOAD_OTHER conflicts with everything. */
4613 if (r2_type == RELOAD_OTHER)
4616 /* Otherwise, check conflicts differently for each type. */
4620 case RELOAD_FOR_INPUT:
4621 return (r2_type == RELOAD_FOR_INSN
4622 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4623 || r2_type == RELOAD_FOR_OPADDR_ADDR
4624 || r2_type == RELOAD_FOR_INPUT
4625 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4626 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4627 && r2_opnum > r1_opnum));
4629 case RELOAD_FOR_INPUT_ADDRESS:
4630 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4631 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4633 case RELOAD_FOR_INPADDR_ADDRESS:
4634 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4635 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4637 case RELOAD_FOR_OUTPUT_ADDRESS:
4638 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4639 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4641 case RELOAD_FOR_OUTADDR_ADDRESS:
4642 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4643 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4645 case RELOAD_FOR_OPERAND_ADDRESS:
4646 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4647 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4649 case RELOAD_FOR_OPADDR_ADDR:
4650 return (r2_type == RELOAD_FOR_INPUT
4651 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4653 case RELOAD_FOR_OUTPUT:
4654 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4655 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4656 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4657 && r2_opnum >= r1_opnum));
4659 case RELOAD_FOR_INSN:
4660 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4661 || r2_type == RELOAD_FOR_INSN
4662 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4664 case RELOAD_FOR_OTHER_ADDRESS:
4665 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4675 /* Indexed by reload number, 1 if incoming value
4676 inherited from previous insns. */
4677 char reload_inherited[MAX_RELOADS];
4679 /* For an inherited reload, this is the insn the reload was inherited from,
4680 if we know it. Otherwise, this is 0. */
4681 rtx reload_inheritance_insn[MAX_RELOADS];
4683 /* If nonzero, this is a place to get the value of the reload,
4684 rather than using reload_in. */
4685 rtx reload_override_in[MAX_RELOADS];
4687 /* For each reload, the hard register number of the register used,
4688 or -1 if we did not need a register for this reload. */
4689 int reload_spill_index[MAX_RELOADS];
4691 /* Subroutine of free_for_value_p, used to check a single register.
4692 START_REGNO is the starting regno of the full reload register
4693 (possibly comprising multiple hard registers) that we are considering. */
4696 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4697 enum reload_type type, rtx value, rtx out,
4698 int reloadnum, int ignore_address_reloads)
4701 /* Set if we see an input reload that must not share its reload register
4702 with any new earlyclobber, but might otherwise share the reload
4703 register with an output or input-output reload. */
4704 int check_earlyclobber = 0;
4708 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4711 if (out == const0_rtx)
4717 /* We use some pseudo 'time' value to check if the lifetimes of the
4718 new register use would overlap with the one of a previous reload
4719 that is not read-only or uses a different value.
4720 The 'time' used doesn't have to be linear in any shape or form, just
4722 Some reload types use different 'buckets' for each operand.
4723 So there are MAX_RECOG_OPERANDS different time values for each
4725 We compute TIME1 as the time when the register for the prospective
4726 new reload ceases to be live, and TIME2 for each existing
4727 reload as the time when that the reload register of that reload
4729 Where there is little to be gained by exact lifetime calculations,
4730 we just make conservative assumptions, i.e. a longer lifetime;
4731 this is done in the 'default:' cases. */
4734 case RELOAD_FOR_OTHER_ADDRESS:
4735 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4736 time1 = copy ? 0 : 1;
4739 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4741 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4742 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4743 respectively, to the time values for these, we get distinct time
4744 values. To get distinct time values for each operand, we have to
4745 multiply opnum by at least three. We round that up to four because
4746 multiply by four is often cheaper. */
4747 case RELOAD_FOR_INPADDR_ADDRESS:
4748 time1 = opnum * 4 + 2;
4750 case RELOAD_FOR_INPUT_ADDRESS:
4751 time1 = opnum * 4 + 3;
4753 case RELOAD_FOR_INPUT:
4754 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4755 executes (inclusive). */
4756 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4758 case RELOAD_FOR_OPADDR_ADDR:
4760 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4761 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4763 case RELOAD_FOR_OPERAND_ADDRESS:
4764 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4766 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4768 case RELOAD_FOR_OUTADDR_ADDRESS:
4769 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4771 case RELOAD_FOR_OUTPUT_ADDRESS:
4772 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4775 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4778 for (i = 0; i < n_reloads; i++)
4780 rtx reg = rld[i].reg_rtx;
4781 if (reg && REG_P (reg)
4782 && ((unsigned) regno - true_regnum (reg)
4783 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
4786 rtx other_input = rld[i].in;
4788 /* If the other reload loads the same input value, that
4789 will not cause a conflict only if it's loading it into
4790 the same register. */
4791 if (true_regnum (reg) != start_regno)
4792 other_input = NULL_RTX;
4793 if (! other_input || ! rtx_equal_p (other_input, value)
4794 || rld[i].out || out)
4797 switch (rld[i].when_needed)
4799 case RELOAD_FOR_OTHER_ADDRESS:
4802 case RELOAD_FOR_INPADDR_ADDRESS:
4803 /* find_reloads makes sure that a
4804 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4805 by at most one - the first -
4806 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4807 address reload is inherited, the address address reload
4808 goes away, so we can ignore this conflict. */
4809 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4810 && ignore_address_reloads
4811 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4812 Then the address address is still needed to store
4813 back the new address. */
4814 && ! rld[reloadnum].out)
4816 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4817 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4819 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4820 && ignore_address_reloads
4821 /* Unless we are reloading an auto_inc expression. */
4822 && ! rld[reloadnum].out)
4824 time2 = rld[i].opnum * 4 + 2;
4826 case RELOAD_FOR_INPUT_ADDRESS:
4827 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4828 && ignore_address_reloads
4829 && ! rld[reloadnum].out)
4831 time2 = rld[i].opnum * 4 + 3;
4833 case RELOAD_FOR_INPUT:
4834 time2 = rld[i].opnum * 4 + 4;
4835 check_earlyclobber = 1;
4837 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4838 == MAX_RECOG_OPERAND * 4 */
4839 case RELOAD_FOR_OPADDR_ADDR:
4840 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4841 && ignore_address_reloads
4842 && ! rld[reloadnum].out)
4844 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4846 case RELOAD_FOR_OPERAND_ADDRESS:
4847 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4848 check_earlyclobber = 1;
4850 case RELOAD_FOR_INSN:
4851 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4853 case RELOAD_FOR_OUTPUT:
4854 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4855 instruction is executed. */
4856 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4858 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4859 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4861 case RELOAD_FOR_OUTADDR_ADDRESS:
4862 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4863 && ignore_address_reloads
4864 && ! rld[reloadnum].out)
4866 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4868 case RELOAD_FOR_OUTPUT_ADDRESS:
4869 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4872 /* If there is no conflict in the input part, handle this
4873 like an output reload. */
4874 if (! rld[i].in || rtx_equal_p (other_input, value))
4876 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4877 /* Earlyclobbered outputs must conflict with inputs. */
4878 if (earlyclobber_operand_p (rld[i].out))
4879 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4884 /* RELOAD_OTHER might be live beyond instruction execution,
4885 but this is not obvious when we set time2 = 1. So check
4886 here if there might be a problem with the new reload
4887 clobbering the register used by the RELOAD_OTHER. */
4895 && (! rld[i].in || rld[i].out
4896 || ! rtx_equal_p (other_input, value)))
4897 || (out && rld[reloadnum].out_reg
4898 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4904 /* Earlyclobbered outputs must conflict with inputs. */
4905 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4911 /* Return 1 if the value in reload reg REGNO, as used by a reload
4912 needed for the part of the insn specified by OPNUM and TYPE,
4913 may be used to load VALUE into it.
4915 MODE is the mode in which the register is used, this is needed to
4916 determine how many hard regs to test.
4918 Other read-only reloads with the same value do not conflict
4919 unless OUT is nonzero and these other reloads have to live while
4920 output reloads live.
4921 If OUT is CONST0_RTX, this is a special case: it means that the
4922 test should not be for using register REGNO as reload register, but
4923 for copying from register REGNO into the reload register.
4925 RELOADNUM is the number of the reload we want to load this value for;
4926 a reload does not conflict with itself.
4928 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4929 reloads that load an address for the very reload we are considering.
4931 The caller has to make sure that there is no conflict with the return
4935 free_for_value_p (int regno, enum machine_mode mode, int opnum,
4936 enum reload_type type, rtx value, rtx out, int reloadnum,
4937 int ignore_address_reloads)
4939 int nregs = hard_regno_nregs[regno][mode];
4941 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
4942 value, out, reloadnum,
4943 ignore_address_reloads))
4948 /* Return nonzero if the rtx X is invariant over the current function. */
4949 /* ??? Actually, the places where we use this expect exactly what
4950 * is tested here, and not everything that is function invariant. In
4951 * particular, the frame pointer and arg pointer are special cased;
4952 * pic_offset_table_rtx is not, and this will cause aborts when we
4953 * go to spill these things to memory. */
4956 function_invariant_p (rtx x)
4960 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4962 if (GET_CODE (x) == PLUS
4963 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
4964 && CONSTANT_P (XEXP (x, 1)))
4969 /* Determine whether the reload reg X overlaps any rtx'es used for
4970 overriding inheritance. Return nonzero if so. */
4973 conflicts_with_override (rtx x)
4976 for (i = 0; i < n_reloads; i++)
4977 if (reload_override_in[i]
4978 && reg_overlap_mentioned_p (x, reload_override_in[i]))
4983 /* Give an error message saying we failed to find a reload for INSN,
4984 and clear out reload R. */
4986 failed_reload (rtx insn, int r)
4988 if (asm_noperands (PATTERN (insn)) < 0)
4989 /* It's the compiler's fault. */
4990 fatal_insn ("could not find a spill register", insn);
4992 /* It's the user's fault; the operand's mode and constraint
4993 don't match. Disable this reload so we don't crash in final. */
4994 error_for_asm (insn,
4995 "%<asm%> operand constraint incompatible with operand size");
4999 rld[r].optional = 1;
5000 rld[r].secondary_p = 1;
5003 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5004 for reload R. If it's valid, get an rtx for it. Return nonzero if
5007 set_reload_reg (int i, int r)
5010 rtx reg = spill_reg_rtx[i];
5012 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5013 spill_reg_rtx[i] = reg
5014 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5016 regno = true_regnum (reg);
5018 /* Detect when the reload reg can't hold the reload mode.
5019 This used to be one `if', but Sequent compiler can't handle that. */
5020 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5022 enum machine_mode test_mode = VOIDmode;
5024 test_mode = GET_MODE (rld[r].in);
5025 /* If rld[r].in has VOIDmode, it means we will load it
5026 in whatever mode the reload reg has: to wit, rld[r].mode.
5027 We have already tested that for validity. */
5028 /* Aside from that, we need to test that the expressions
5029 to reload from or into have modes which are valid for this
5030 reload register. Otherwise the reload insns would be invalid. */
5031 if (! (rld[r].in != 0 && test_mode != VOIDmode
5032 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5033 if (! (rld[r].out != 0
5034 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5036 /* The reg is OK. */
5039 /* Mark as in use for this insn the reload regs we use
5041 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5042 rld[r].when_needed, rld[r].mode);
5044 rld[r].reg_rtx = reg;
5045 reload_spill_index[r] = spill_regs[i];
5052 /* Find a spill register to use as a reload register for reload R.
5053 LAST_RELOAD is nonzero if this is the last reload for the insn being
5056 Set rld[R].reg_rtx to the register allocated.
5058 We return 1 if successful, or 0 if we couldn't find a spill reg and
5059 we didn't change anything. */
5062 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5067 /* If we put this reload ahead, thinking it is a group,
5068 then insist on finding a group. Otherwise we can grab a
5069 reg that some other reload needs.
5070 (That can happen when we have a 68000 DATA_OR_FP_REG
5071 which is a group of data regs or one fp reg.)
5072 We need not be so restrictive if there are no more reloads
5075 ??? Really it would be nicer to have smarter handling
5076 for that kind of reg class, where a problem like this is normal.
5077 Perhaps those classes should be avoided for reloading
5078 by use of more alternatives. */
5080 int force_group = rld[r].nregs > 1 && ! last_reload;
5082 /* If we want a single register and haven't yet found one,
5083 take any reg in the right class and not in use.
5084 If we want a consecutive group, here is where we look for it.
5086 We use two passes so we can first look for reload regs to
5087 reuse, which are already in use for other reloads in this insn,
5088 and only then use additional registers.
5089 I think that maximizing reuse is needed to make sure we don't
5090 run out of reload regs. Suppose we have three reloads, and
5091 reloads A and B can share regs. These need two regs.
5092 Suppose A and B are given different regs.
5093 That leaves none for C. */
5094 for (pass = 0; pass < 2; pass++)
5096 /* I is the index in spill_regs.
5097 We advance it round-robin between insns to use all spill regs
5098 equally, so that inherited reloads have a chance
5099 of leapfrogging each other. */
5103 for (count = 0; count < n_spills; count++)
5105 int class = (int) rld[r].class;
5111 regnum = spill_regs[i];
5113 if ((reload_reg_free_p (regnum, rld[r].opnum,
5116 /* We check reload_reg_used to make sure we
5117 don't clobber the return register. */
5118 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5119 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5120 rld[r].when_needed, rld[r].in,
5122 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5123 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5124 /* Look first for regs to share, then for unshared. But
5125 don't share regs used for inherited reloads; they are
5126 the ones we want to preserve. */
5128 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5130 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5133 int nr = hard_regno_nregs[regnum][rld[r].mode];
5134 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5135 (on 68000) got us two FP regs. If NR is 1,
5136 we would reject both of them. */
5139 /* If we need only one reg, we have already won. */
5142 /* But reject a single reg if we demand a group. */
5147 /* Otherwise check that as many consecutive regs as we need
5148 are available here. */
5151 int regno = regnum + nr - 1;
5152 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5153 && spill_reg_order[regno] >= 0
5154 && reload_reg_free_p (regno, rld[r].opnum,
5155 rld[r].when_needed)))
5164 /* If we found something on pass 1, omit pass 2. */
5165 if (count < n_spills)
5169 /* We should have found a spill register by now. */
5170 if (count >= n_spills)
5173 /* I is the index in SPILL_REG_RTX of the reload register we are to
5174 allocate. Get an rtx for it and find its register number. */
5176 return set_reload_reg (i, r);
5179 /* Initialize all the tables needed to allocate reload registers.
5180 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5181 is the array we use to restore the reg_rtx field for every reload. */
5184 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5188 for (i = 0; i < n_reloads; i++)
5189 rld[i].reg_rtx = save_reload_reg_rtx[i];
5191 memset (reload_inherited, 0, MAX_RELOADS);
5192 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5193 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5195 CLEAR_HARD_REG_SET (reload_reg_used);
5196 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5197 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5198 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5199 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5200 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5202 CLEAR_HARD_REG_SET (reg_used_in_insn);
5205 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5206 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5207 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5208 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5209 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5210 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5213 for (i = 0; i < reload_n_operands; i++)
5215 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5216 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5217 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5218 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5219 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5220 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5223 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5225 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5227 for (i = 0; i < n_reloads; i++)
5228 /* If we have already decided to use a certain register,
5229 don't use it in another way. */
5231 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5232 rld[i].when_needed, rld[i].mode);
5235 /* Assign hard reg targets for the pseudo-registers we must reload
5236 into hard regs for this insn.
5237 Also output the instructions to copy them in and out of the hard regs.
5239 For machines with register classes, we are responsible for
5240 finding a reload reg in the proper class. */
5243 choose_reload_regs (struct insn_chain *chain)
5245 rtx insn = chain->insn;
5247 unsigned int max_group_size = 1;
5248 enum reg_class group_class = NO_REGS;
5249 int pass, win, inheritance;
5251 rtx save_reload_reg_rtx[MAX_RELOADS];
5253 /* In order to be certain of getting the registers we need,
5254 we must sort the reloads into order of increasing register class.
5255 Then our grabbing of reload registers will parallel the process
5256 that provided the reload registers.
5258 Also note whether any of the reloads wants a consecutive group of regs.
5259 If so, record the maximum size of the group desired and what
5260 register class contains all the groups needed by this insn. */
5262 for (j = 0; j < n_reloads; j++)
5264 reload_order[j] = j;
5265 reload_spill_index[j] = -1;
5267 if (rld[j].nregs > 1)
5269 max_group_size = MAX (rld[j].nregs, max_group_size);
5271 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5274 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5278 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5280 /* If -O, try first with inheritance, then turning it off.
5281 If not -O, don't do inheritance.
5282 Using inheritance when not optimizing leads to paradoxes
5283 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5284 because one side of the comparison might be inherited. */
5286 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5288 choose_reload_regs_init (chain, save_reload_reg_rtx);
5290 /* Process the reloads in order of preference just found.
5291 Beyond this point, subregs can be found in reload_reg_rtx.
5293 This used to look for an existing reloaded home for all of the
5294 reloads, and only then perform any new reloads. But that could lose
5295 if the reloads were done out of reg-class order because a later
5296 reload with a looser constraint might have an old home in a register
5297 needed by an earlier reload with a tighter constraint.
5299 To solve this, we make two passes over the reloads, in the order
5300 described above. In the first pass we try to inherit a reload
5301 from a previous insn. If there is a later reload that needs a
5302 class that is a proper subset of the class being processed, we must
5303 also allocate a spill register during the first pass.
5305 Then make a second pass over the reloads to allocate any reloads
5306 that haven't been given registers yet. */
5308 for (j = 0; j < n_reloads; j++)
5310 int r = reload_order[j];
5311 rtx search_equiv = NULL_RTX;
5313 /* Ignore reloads that got marked inoperative. */
5314 if (rld[r].out == 0 && rld[r].in == 0
5315 && ! rld[r].secondary_p)
5318 /* If find_reloads chose to use reload_in or reload_out as a reload
5319 register, we don't need to chose one. Otherwise, try even if it
5320 found one since we might save an insn if we find the value lying
5322 Try also when reload_in is a pseudo without a hard reg. */
5323 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5324 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5325 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5326 && !MEM_P (rld[r].in)
5327 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5330 #if 0 /* No longer needed for correct operation.
5331 It might give better code, or might not; worth an experiment? */
5332 /* If this is an optional reload, we can't inherit from earlier insns
5333 until we are sure that any non-optional reloads have been allocated.
5334 The following code takes advantage of the fact that optional reloads
5335 are at the end of reload_order. */
5336 if (rld[r].optional != 0)
5337 for (i = 0; i < j; i++)
5338 if ((rld[reload_order[i]].out != 0
5339 || rld[reload_order[i]].in != 0
5340 || rld[reload_order[i]].secondary_p)
5341 && ! rld[reload_order[i]].optional
5342 && rld[reload_order[i]].reg_rtx == 0)
5343 allocate_reload_reg (chain, reload_order[i], 0);
5346 /* First see if this pseudo is already available as reloaded
5347 for a previous insn. We cannot try to inherit for reloads
5348 that are smaller than the maximum number of registers needed
5349 for groups unless the register we would allocate cannot be used
5352 We could check here to see if this is a secondary reload for
5353 an object that is already in a register of the desired class.
5354 This would avoid the need for the secondary reload register.
5355 But this is complex because we can't easily determine what
5356 objects might want to be loaded via this reload. So let a
5357 register be allocated here. In `emit_reload_insns' we suppress
5358 one of the loads in the case described above. */
5364 enum machine_mode mode = VOIDmode;
5368 else if (REG_P (rld[r].in))
5370 regno = REGNO (rld[r].in);
5371 mode = GET_MODE (rld[r].in);
5373 else if (REG_P (rld[r].in_reg))
5375 regno = REGNO (rld[r].in_reg);
5376 mode = GET_MODE (rld[r].in_reg);
5378 else if (GET_CODE (rld[r].in_reg) == SUBREG
5379 && REG_P (SUBREG_REG (rld[r].in_reg)))
5381 byte = SUBREG_BYTE (rld[r].in_reg);
5382 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5383 if (regno < FIRST_PSEUDO_REGISTER)
5384 regno = subreg_regno (rld[r].in_reg);
5385 mode = GET_MODE (rld[r].in_reg);
5388 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5389 || GET_CODE (rld[r].in_reg) == PRE_DEC
5390 || GET_CODE (rld[r].in_reg) == POST_INC
5391 || GET_CODE (rld[r].in_reg) == POST_DEC)
5392 && REG_P (XEXP (rld[r].in_reg, 0)))
5394 regno = REGNO (XEXP (rld[r].in_reg, 0));
5395 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5396 rld[r].out = rld[r].in;
5400 /* This won't work, since REGNO can be a pseudo reg number.
5401 Also, it takes much more hair to keep track of all the things
5402 that can invalidate an inherited reload of part of a pseudoreg. */
5403 else if (GET_CODE (rld[r].in) == SUBREG
5404 && REG_P (SUBREG_REG (rld[r].in)))
5405 regno = subreg_regno (rld[r].in);
5408 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5410 enum reg_class class = rld[r].class, last_class;
5411 rtx last_reg = reg_last_reload_reg[regno];
5412 enum machine_mode need_mode;
5414 i = REGNO (last_reg);
5415 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5416 last_class = REGNO_REG_CLASS (i);
5422 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5423 GET_MODE_CLASS (mode));
5426 #ifdef CANNOT_CHANGE_MODE_CLASS
5427 (!REG_CANNOT_CHANGE_MODE_P (i, GET_MODE (last_reg),
5431 (GET_MODE_SIZE (GET_MODE (last_reg))
5432 >= GET_MODE_SIZE (need_mode))
5433 #ifdef CANNOT_CHANGE_MODE_CLASS
5436 && reg_reloaded_contents[i] == regno
5437 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5438 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5439 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5440 /* Even if we can't use this register as a reload
5441 register, we might use it for reload_override_in,
5442 if copying it to the desired class is cheap
5444 || ((REGISTER_MOVE_COST (mode, last_class, class)
5445 < MEMORY_MOVE_COST (mode, class, 1))
5446 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5447 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5451 #ifdef SECONDARY_MEMORY_NEEDED
5452 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5457 && (rld[r].nregs == max_group_size
5458 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5460 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5461 rld[r].when_needed, rld[r].in,
5464 /* If a group is needed, verify that all the subsequent
5465 registers still have their values intact. */
5466 int nr = hard_regno_nregs[i][rld[r].mode];
5469 for (k = 1; k < nr; k++)
5470 if (reg_reloaded_contents[i + k] != regno
5471 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5479 last_reg = (GET_MODE (last_reg) == mode
5480 ? last_reg : gen_rtx_REG (mode, i));
5483 for (k = 0; k < nr; k++)
5484 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5487 /* We found a register that contains the
5488 value we need. If this register is the
5489 same as an `earlyclobber' operand of the
5490 current insn, just mark it as a place to
5491 reload from since we can't use it as the
5492 reload register itself. */
5494 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5495 if (reg_overlap_mentioned_for_reload_p
5496 (reg_last_reload_reg[regno],
5497 reload_earlyclobbers[i1]))
5500 if (i1 != n_earlyclobbers
5501 || ! (free_for_value_p (i, rld[r].mode,
5503 rld[r].when_needed, rld[r].in,
5505 /* Don't use it if we'd clobber a pseudo reg. */
5506 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5508 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5509 /* Don't clobber the frame pointer. */
5510 || (i == HARD_FRAME_POINTER_REGNUM
5511 && frame_pointer_needed
5513 /* Don't really use the inherited spill reg
5514 if we need it wider than we've got it. */
5515 || (GET_MODE_SIZE (rld[r].mode)
5516 > GET_MODE_SIZE (mode))
5519 /* If find_reloads chose reload_out as reload
5520 register, stay with it - that leaves the
5521 inherited register for subsequent reloads. */
5522 || (rld[r].out && rld[r].reg_rtx
5523 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5525 if (! rld[r].optional)
5527 reload_override_in[r] = last_reg;
5528 reload_inheritance_insn[r]
5529 = reg_reloaded_insn[i];
5535 /* We can use this as a reload reg. */
5536 /* Mark the register as in use for this part of
5538 mark_reload_reg_in_use (i,
5542 rld[r].reg_rtx = last_reg;
5543 reload_inherited[r] = 1;
5544 reload_inheritance_insn[r]
5545 = reg_reloaded_insn[i];
5546 reload_spill_index[r] = i;
5547 for (k = 0; k < nr; k++)
5548 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5556 /* Here's another way to see if the value is already lying around. */
5559 && ! reload_inherited[r]
5561 && (CONSTANT_P (rld[r].in)
5562 || GET_CODE (rld[r].in) == PLUS
5563 || REG_P (rld[r].in)
5564 || MEM_P (rld[r].in))
5565 && (rld[r].nregs == max_group_size
5566 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5567 search_equiv = rld[r].in;
5568 /* If this is an output reload from a simple move insn, look
5569 if an equivalence for the input is available. */
5570 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5572 rtx set = single_set (insn);
5575 && rtx_equal_p (rld[r].out, SET_DEST (set))
5576 && CONSTANT_P (SET_SRC (set)))
5577 search_equiv = SET_SRC (set);
5583 = find_equiv_reg (search_equiv, insn, rld[r].class,
5584 -1, NULL, 0, rld[r].mode);
5590 regno = REGNO (equiv);
5593 /* This must be a SUBREG of a hard register.
5594 Make a new REG since this might be used in an
5595 address and not all machines support SUBREGs
5597 gcc_assert (GET_CODE (equiv) == SUBREG);
5598 regno = subreg_regno (equiv);
5599 equiv = gen_rtx_REG (rld[r].mode, regno);
5603 /* If we found a spill reg, reject it unless it is free
5604 and of the desired class. */
5608 int bad_for_class = 0;
5609 int max_regno = regno + rld[r].nregs;
5611 for (i = regno; i < max_regno; i++)
5613 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5615 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5620 && ! free_for_value_p (regno, rld[r].mode,
5621 rld[r].opnum, rld[r].when_needed,
5622 rld[r].in, rld[r].out, r, 1))
5627 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5630 /* We found a register that contains the value we need.
5631 If this register is the same as an `earlyclobber' operand
5632 of the current insn, just mark it as a place to reload from
5633 since we can't use it as the reload register itself. */
5636 for (i = 0; i < n_earlyclobbers; i++)
5637 if (reg_overlap_mentioned_for_reload_p (equiv,
5638 reload_earlyclobbers[i]))
5640 if (! rld[r].optional)
5641 reload_override_in[r] = equiv;
5646 /* If the equiv register we have found is explicitly clobbered
5647 in the current insn, it depends on the reload type if we
5648 can use it, use it for reload_override_in, or not at all.
5649 In particular, we then can't use EQUIV for a
5650 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5654 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5655 switch (rld[r].when_needed)
5657 case RELOAD_FOR_OTHER_ADDRESS:
5658 case RELOAD_FOR_INPADDR_ADDRESS:
5659 case RELOAD_FOR_INPUT_ADDRESS:
5660 case RELOAD_FOR_OPADDR_ADDR:
5663 case RELOAD_FOR_INPUT:
5664 case RELOAD_FOR_OPERAND_ADDRESS:
5665 if (! rld[r].optional)
5666 reload_override_in[r] = equiv;
5672 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5673 switch (rld[r].when_needed)
5675 case RELOAD_FOR_OTHER_ADDRESS:
5676 case RELOAD_FOR_INPADDR_ADDRESS:
5677 case RELOAD_FOR_INPUT_ADDRESS:
5678 case RELOAD_FOR_OPADDR_ADDR:
5679 case RELOAD_FOR_OPERAND_ADDRESS:
5680 case RELOAD_FOR_INPUT:
5683 if (! rld[r].optional)
5684 reload_override_in[r] = equiv;
5692 /* If we found an equivalent reg, say no code need be generated
5693 to load it, and use it as our reload reg. */
5695 && (regno != HARD_FRAME_POINTER_REGNUM
5696 || !frame_pointer_needed))
5698 int nr = hard_regno_nregs[regno][rld[r].mode];
5700 rld[r].reg_rtx = equiv;
5701 reload_inherited[r] = 1;
5703 /* If reg_reloaded_valid is not set for this register,
5704 there might be a stale spill_reg_store lying around.
5705 We must clear it, since otherwise emit_reload_insns
5706 might delete the store. */
5707 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5708 spill_reg_store[regno] = NULL_RTX;
5709 /* If any of the hard registers in EQUIV are spill
5710 registers, mark them as in use for this insn. */
5711 for (k = 0; k < nr; k++)
5713 i = spill_reg_order[regno + k];
5716 mark_reload_reg_in_use (regno, rld[r].opnum,
5719 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5726 /* If we found a register to use already, or if this is an optional
5727 reload, we are done. */
5728 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5732 /* No longer needed for correct operation. Might or might
5733 not give better code on the average. Want to experiment? */
5735 /* See if there is a later reload that has a class different from our
5736 class that intersects our class or that requires less register
5737 than our reload. If so, we must allocate a register to this
5738 reload now, since that reload might inherit a previous reload
5739 and take the only available register in our class. Don't do this
5740 for optional reloads since they will force all previous reloads
5741 to be allocated. Also don't do this for reloads that have been
5744 for (i = j + 1; i < n_reloads; i++)
5746 int s = reload_order[i];
5748 if ((rld[s].in == 0 && rld[s].out == 0
5749 && ! rld[s].secondary_p)
5753 if ((rld[s].class != rld[r].class
5754 && reg_classes_intersect_p (rld[r].class,
5756 || rld[s].nregs < rld[r].nregs)
5763 allocate_reload_reg (chain, r, j == n_reloads - 1);
5767 /* Now allocate reload registers for anything non-optional that
5768 didn't get one yet. */
5769 for (j = 0; j < n_reloads; j++)
5771 int r = reload_order[j];
5773 /* Ignore reloads that got marked inoperative. */
5774 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5777 /* Skip reloads that already have a register allocated or are
5779 if (rld[r].reg_rtx != 0 || rld[r].optional)
5782 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5786 /* If that loop got all the way, we have won. */
5793 /* Loop around and try without any inheritance. */
5798 /* First undo everything done by the failed attempt
5799 to allocate with inheritance. */
5800 choose_reload_regs_init (chain, save_reload_reg_rtx);
5802 /* Some sanity tests to verify that the reloads found in the first
5803 pass are identical to the ones we have now. */
5804 gcc_assert (chain->n_reloads == n_reloads);
5806 for (i = 0; i < n_reloads; i++)
5808 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5810 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
5811 for (j = 0; j < n_spills; j++)
5812 if (spill_regs[j] == chain->rld[i].regno)
5813 if (! set_reload_reg (j, i))
5814 failed_reload (chain->insn, i);
5818 /* If we thought we could inherit a reload, because it seemed that
5819 nothing else wanted the same reload register earlier in the insn,
5820 verify that assumption, now that all reloads have been assigned.
5821 Likewise for reloads where reload_override_in has been set. */
5823 /* If doing expensive optimizations, do one preliminary pass that doesn't
5824 cancel any inheritance, but removes reloads that have been needed only
5825 for reloads that we know can be inherited. */
5826 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5828 for (j = 0; j < n_reloads; j++)
5830 int r = reload_order[j];
5832 if (reload_inherited[r] && rld[r].reg_rtx)
5833 check_reg = rld[r].reg_rtx;
5834 else if (reload_override_in[r]
5835 && (REG_P (reload_override_in[r])
5836 || GET_CODE (reload_override_in[r]) == SUBREG))
5837 check_reg = reload_override_in[r];
5840 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5841 rld[r].opnum, rld[r].when_needed, rld[r].in,
5842 (reload_inherited[r]
5843 ? rld[r].out : const0_rtx),
5848 reload_inherited[r] = 0;
5849 reload_override_in[r] = 0;
5851 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5852 reload_override_in, then we do not need its related
5853 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5854 likewise for other reload types.
5855 We handle this by removing a reload when its only replacement
5856 is mentioned in reload_in of the reload we are going to inherit.
5857 A special case are auto_inc expressions; even if the input is
5858 inherited, we still need the address for the output. We can
5859 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5860 If we succeeded removing some reload and we are doing a preliminary
5861 pass just to remove such reloads, make another pass, since the
5862 removal of one reload might allow us to inherit another one. */
5864 && rld[r].out != rld[r].in
5865 && remove_address_replacements (rld[r].in) && pass)
5870 /* Now that reload_override_in is known valid,
5871 actually override reload_in. */
5872 for (j = 0; j < n_reloads; j++)
5873 if (reload_override_in[j])
5874 rld[j].in = reload_override_in[j];
5876 /* If this reload won't be done because it has been canceled or is
5877 optional and not inherited, clear reload_reg_rtx so other
5878 routines (such as subst_reloads) don't get confused. */
5879 for (j = 0; j < n_reloads; j++)
5880 if (rld[j].reg_rtx != 0
5881 && ((rld[j].optional && ! reload_inherited[j])
5882 || (rld[j].in == 0 && rld[j].out == 0
5883 && ! rld[j].secondary_p)))
5885 int regno = true_regnum (rld[j].reg_rtx);
5887 if (spill_reg_order[regno] >= 0)
5888 clear_reload_reg_in_use (regno, rld[j].opnum,
5889 rld[j].when_needed, rld[j].mode);
5891 reload_spill_index[j] = -1;
5894 /* Record which pseudos and which spill regs have output reloads. */
5895 for (j = 0; j < n_reloads; j++)
5897 int r = reload_order[j];
5899 i = reload_spill_index[r];
5901 /* I is nonneg if this reload uses a register.
5902 If rld[r].reg_rtx is 0, this is an optional reload
5903 that we opted to ignore. */
5904 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
5905 && rld[r].reg_rtx != 0)
5907 int nregno = REGNO (rld[r].out_reg);
5910 if (nregno < FIRST_PSEUDO_REGISTER)
5911 nr = hard_regno_nregs[nregno][rld[r].mode];
5914 reg_has_output_reload[nregno + nr] = 1;
5918 nr = hard_regno_nregs[i][rld[r].mode];
5920 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5923 gcc_assert (rld[r].when_needed == RELOAD_OTHER
5924 || rld[r].when_needed == RELOAD_FOR_OUTPUT
5925 || rld[r].when_needed == RELOAD_FOR_INSN);
5930 /* Deallocate the reload register for reload R. This is called from
5931 remove_address_replacements. */
5934 deallocate_reload_reg (int r)
5938 if (! rld[r].reg_rtx)
5940 regno = true_regnum (rld[r].reg_rtx);
5942 if (spill_reg_order[regno] >= 0)
5943 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5945 reload_spill_index[r] = -1;
5948 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
5949 reloads of the same item for fear that we might not have enough reload
5950 registers. However, normally they will get the same reload register
5951 and hence actually need not be loaded twice.
5953 Here we check for the most common case of this phenomenon: when we have
5954 a number of reloads for the same object, each of which were allocated
5955 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5956 reload, and is not modified in the insn itself. If we find such,
5957 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5958 This will not increase the number of spill registers needed and will
5959 prevent redundant code. */
5962 merge_assigned_reloads (rtx insn)
5966 /* Scan all the reloads looking for ones that only load values and
5967 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5968 assigned and not modified by INSN. */
5970 for (i = 0; i < n_reloads; i++)
5972 int conflicting_input = 0;
5973 int max_input_address_opnum = -1;
5974 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
5976 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
5977 || rld[i].out != 0 || rld[i].reg_rtx == 0
5978 || reg_set_p (rld[i].reg_rtx, insn))
5981 /* Look at all other reloads. Ensure that the only use of this
5982 reload_reg_rtx is in a reload that just loads the same value
5983 as we do. Note that any secondary reloads must be of the identical
5984 class since the values, modes, and result registers are the
5985 same, so we need not do anything with any secondary reloads. */
5987 for (j = 0; j < n_reloads; j++)
5989 if (i == j || rld[j].reg_rtx == 0
5990 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
5994 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5995 && rld[j].opnum > max_input_address_opnum)
5996 max_input_address_opnum = rld[j].opnum;
5998 /* If the reload regs aren't exactly the same (e.g, different modes)
5999 or if the values are different, we can't merge this reload.
6000 But if it is an input reload, we might still merge
6001 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6003 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6004 || rld[j].out != 0 || rld[j].in == 0
6005 || ! rtx_equal_p (rld[i].in, rld[j].in))
6007 if (rld[j].when_needed != RELOAD_FOR_INPUT
6008 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6009 || rld[i].opnum > rld[j].opnum)
6010 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6012 conflicting_input = 1;
6013 if (min_conflicting_input_opnum > rld[j].opnum)
6014 min_conflicting_input_opnum = rld[j].opnum;
6018 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6019 we, in fact, found any matching reloads. */
6022 && max_input_address_opnum <= min_conflicting_input_opnum)
6024 for (j = 0; j < n_reloads; j++)
6025 if (i != j && rld[j].reg_rtx != 0
6026 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6027 && (! conflicting_input
6028 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6029 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6031 rld[i].when_needed = RELOAD_OTHER;
6033 reload_spill_index[j] = -1;
6034 transfer_replacements (i, j);
6037 /* If this is now RELOAD_OTHER, look for any reloads that load
6038 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6039 if they were for inputs, RELOAD_OTHER for outputs. Note that
6040 this test is equivalent to looking for reloads for this operand
6042 /* We must take special care when there are two or more reloads to
6043 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6044 same value or a part of it; we must not change its type if there
6045 is a conflicting input. */
6047 if (rld[i].when_needed == RELOAD_OTHER)
6048 for (j = 0; j < n_reloads; j++)
6050 && rld[j].when_needed != RELOAD_OTHER
6051 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6052 && (! conflicting_input
6053 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6054 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6055 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6061 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6062 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6063 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6065 /* Check to see if we accidentally converted two reloads
6066 that use the same reload register with different inputs
6067 to the same type. If so, the resulting code won't work,
6070 for (k = 0; k < j; k++)
6071 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6072 || rld[k].when_needed != rld[j].when_needed
6073 || !rtx_equal_p (rld[k].reg_rtx,
6075 || rtx_equal_p (rld[k].in,
6082 /* These arrays are filled by emit_reload_insns and its subroutines. */
6083 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6084 static rtx other_input_address_reload_insns = 0;
6085 static rtx other_input_reload_insns = 0;
6086 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6087 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6088 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6089 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6090 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6091 static rtx operand_reload_insns = 0;
6092 static rtx other_operand_reload_insns = 0;
6093 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6095 /* Values to be put in spill_reg_store are put here first. */
6096 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6097 static HARD_REG_SET reg_reloaded_died;
6099 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6100 has the number J. OLD contains the value to be used as input. */
6103 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6106 rtx insn = chain->insn;
6107 rtx reloadreg = rl->reg_rtx;
6108 rtx oldequiv_reg = 0;
6111 enum machine_mode mode;
6114 /* Determine the mode to reload in.
6115 This is very tricky because we have three to choose from.
6116 There is the mode the insn operand wants (rl->inmode).
6117 There is the mode of the reload register RELOADREG.
6118 There is the intrinsic mode of the operand, which we could find
6119 by stripping some SUBREGs.
6120 It turns out that RELOADREG's mode is irrelevant:
6121 we can change that arbitrarily.
6123 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6124 then the reload reg may not support QImode moves, so use SImode.
6125 If foo is in memory due to spilling a pseudo reg, this is safe,
6126 because the QImode value is in the least significant part of a
6127 slot big enough for a SImode. If foo is some other sort of
6128 memory reference, then it is impossible to reload this case,
6129 so previous passes had better make sure this never happens.
6131 Then consider a one-word union which has SImode and one of its
6132 members is a float, being fetched as (SUBREG:SF union:SI).
6133 We must fetch that as SFmode because we could be loading into
6134 a float-only register. In this case OLD's mode is correct.
6136 Consider an immediate integer: it has VOIDmode. Here we need
6137 to get a mode from something else.
6139 In some cases, there is a fourth mode, the operand's
6140 containing mode. If the insn specifies a containing mode for
6141 this operand, it overrides all others.
6143 I am not sure whether the algorithm here is always right,
6144 but it does the right things in those cases. */
6146 mode = GET_MODE (old);
6147 if (mode == VOIDmode)
6150 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6151 /* If we need a secondary register for this operation, see if
6152 the value is already in a register in that class. Don't
6153 do this if the secondary register will be used as a scratch
6156 if (rl->secondary_in_reload >= 0
6157 && rl->secondary_in_icode == CODE_FOR_nothing
6160 = find_equiv_reg (old, insn,
6161 rld[rl->secondary_in_reload].class,
6165 /* If reloading from memory, see if there is a register
6166 that already holds the same value. If so, reload from there.
6167 We can pass 0 as the reload_reg_p argument because
6168 any other reload has either already been emitted,
6169 in which case find_equiv_reg will see the reload-insn,
6170 or has yet to be emitted, in which case it doesn't matter
6171 because we will use this equiv reg right away. */
6173 if (oldequiv == 0 && optimize
6176 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6177 && reg_renumber[REGNO (old)] < 0)))
6178 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6182 unsigned int regno = true_regnum (oldequiv);
6184 /* Don't use OLDEQUIV if any other reload changes it at an
6185 earlier stage of this insn or at this stage. */
6186 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6187 rl->in, const0_rtx, j, 0))
6190 /* If it is no cheaper to copy from OLDEQUIV into the
6191 reload register than it would be to move from memory,
6192 don't use it. Likewise, if we need a secondary register
6196 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6197 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6199 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6200 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6201 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6205 #ifdef SECONDARY_MEMORY_NEEDED
6206 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6214 /* delete_output_reload is only invoked properly if old contains
6215 the original pseudo register. Since this is replaced with a
6216 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6217 find the pseudo in RELOAD_IN_REG. */
6219 && reload_override_in[j]
6220 && REG_P (rl->in_reg))
6227 else if (REG_P (oldequiv))
6228 oldequiv_reg = oldequiv;
6229 else if (GET_CODE (oldequiv) == SUBREG)
6230 oldequiv_reg = SUBREG_REG (oldequiv);
6232 /* If we are reloading from a register that was recently stored in
6233 with an output-reload, see if we can prove there was
6234 actually no need to store the old value in it. */
6236 if (optimize && REG_P (oldequiv)
6237 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6238 && spill_reg_store[REGNO (oldequiv)]
6240 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6241 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6243 delete_output_reload (insn, j, REGNO (oldequiv));
6245 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6246 then load RELOADREG from OLDEQUIV. Note that we cannot use
6247 gen_lowpart_common since it can do the wrong thing when
6248 RELOADREG has a multi-word mode. Note that RELOADREG
6249 must always be a REG here. */
6251 if (GET_MODE (reloadreg) != mode)
6252 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6253 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6254 oldequiv = SUBREG_REG (oldequiv);
6255 if (GET_MODE (oldequiv) != VOIDmode
6256 && mode != GET_MODE (oldequiv))
6257 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6259 /* Switch to the right place to emit the reload insns. */
6260 switch (rl->when_needed)
6263 where = &other_input_reload_insns;
6265 case RELOAD_FOR_INPUT:
6266 where = &input_reload_insns[rl->opnum];
6268 case RELOAD_FOR_INPUT_ADDRESS:
6269 where = &input_address_reload_insns[rl->opnum];
6271 case RELOAD_FOR_INPADDR_ADDRESS:
6272 where = &inpaddr_address_reload_insns[rl->opnum];
6274 case RELOAD_FOR_OUTPUT_ADDRESS:
6275 where = &output_address_reload_insns[rl->opnum];
6277 case RELOAD_FOR_OUTADDR_ADDRESS:
6278 where = &outaddr_address_reload_insns[rl->opnum];
6280 case RELOAD_FOR_OPERAND_ADDRESS:
6281 where = &operand_reload_insns;
6283 case RELOAD_FOR_OPADDR_ADDR:
6284 where = &other_operand_reload_insns;
6286 case RELOAD_FOR_OTHER_ADDRESS:
6287 where = &other_input_address_reload_insns;
6293 push_to_sequence (*where);
6295 /* Auto-increment addresses must be reloaded in a special way. */
6296 if (rl->out && ! rl->out_reg)
6298 /* We are not going to bother supporting the case where a
6299 incremented register can't be copied directly from
6300 OLDEQUIV since this seems highly unlikely. */
6301 gcc_assert (rl->secondary_in_reload < 0);
6303 if (reload_inherited[j])
6304 oldequiv = reloadreg;
6306 old = XEXP (rl->in_reg, 0);
6308 if (optimize && REG_P (oldequiv)
6309 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6310 && spill_reg_store[REGNO (oldequiv)]
6312 && (dead_or_set_p (insn,
6313 spill_reg_stored_to[REGNO (oldequiv)])
6314 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6316 delete_output_reload (insn, j, REGNO (oldequiv));
6318 /* Prevent normal processing of this reload. */
6320 /* Output a special code sequence for this case. */
6321 new_spill_reg_store[REGNO (reloadreg)]
6322 = inc_for_reload (reloadreg, oldequiv, rl->out,
6326 /* If we are reloading a pseudo-register that was set by the previous
6327 insn, see if we can get rid of that pseudo-register entirely
6328 by redirecting the previous insn into our reload register. */
6330 else if (optimize && REG_P (old)
6331 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6332 && dead_or_set_p (insn, old)
6333 /* This is unsafe if some other reload
6334 uses the same reg first. */
6335 && ! conflicts_with_override (reloadreg)
6336 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6337 rl->when_needed, old, rl->out, j, 0))
6339 rtx temp = PREV_INSN (insn);
6340 while (temp && NOTE_P (temp))
6341 temp = PREV_INSN (temp);
6343 && NONJUMP_INSN_P (temp)
6344 && GET_CODE (PATTERN (temp)) == SET
6345 && SET_DEST (PATTERN (temp)) == old
6346 /* Make sure we can access insn_operand_constraint. */
6347 && asm_noperands (PATTERN (temp)) < 0
6348 /* This is unsafe if operand occurs more than once in current
6349 insn. Perhaps some occurrences aren't reloaded. */
6350 && count_occurrences (PATTERN (insn), old, 0) == 1)
6352 rtx old = SET_DEST (PATTERN (temp));
6353 /* Store into the reload register instead of the pseudo. */
6354 SET_DEST (PATTERN (temp)) = reloadreg;
6356 /* Verify that resulting insn is valid. */
6357 extract_insn (temp);
6358 if (constrain_operands (1))
6360 /* If the previous insn is an output reload, the source is
6361 a reload register, and its spill_reg_store entry will
6362 contain the previous destination. This is now
6364 if (REG_P (SET_SRC (PATTERN (temp)))
6365 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6367 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6368 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6371 /* If these are the only uses of the pseudo reg,
6372 pretend for GDB it lives in the reload reg we used. */
6373 if (REG_N_DEATHS (REGNO (old)) == 1
6374 && REG_N_SETS (REGNO (old)) == 1)
6376 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6377 alter_reg (REGNO (old), -1);
6383 SET_DEST (PATTERN (temp)) = old;
6388 /* We can't do that, so output an insn to load RELOADREG. */
6390 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6391 /* If we have a secondary reload, pick up the secondary register
6392 and icode, if any. If OLDEQUIV and OLD are different or
6393 if this is an in-out reload, recompute whether or not we
6394 still need a secondary register and what the icode should
6395 be. If we still need a secondary register and the class or
6396 icode is different, go back to reloading from OLD if using
6397 OLDEQUIV means that we got the wrong type of register. We
6398 cannot have different class or icode due to an in-out reload
6399 because we don't make such reloads when both the input and
6400 output need secondary reload registers. */
6402 if (! special && rl->secondary_in_reload >= 0)
6404 rtx second_reload_reg = 0;
6405 int secondary_reload = rl->secondary_in_reload;
6406 rtx real_oldequiv = oldequiv;
6409 enum insn_code icode;
6411 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6412 and similarly for OLD.
6413 See comments in get_secondary_reload in reload.c. */
6414 /* If it is a pseudo that cannot be replaced with its
6415 equivalent MEM, we must fall back to reload_in, which
6416 will have all the necessary substitutions registered.
6417 Likewise for a pseudo that can't be replaced with its
6418 equivalent constant.
6420 Take extra care for subregs of such pseudos. Note that
6421 we cannot use reg_equiv_mem in this case because it is
6422 not in the right mode. */
6425 if (GET_CODE (tmp) == SUBREG)
6426 tmp = SUBREG_REG (tmp);
6428 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6429 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6430 || reg_equiv_constant[REGNO (tmp)] != 0))
6432 if (! reg_equiv_mem[REGNO (tmp)]
6433 || num_not_at_initial_offset
6434 || GET_CODE (oldequiv) == SUBREG)
6435 real_oldequiv = rl->in;
6437 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6441 if (GET_CODE (tmp) == SUBREG)
6442 tmp = SUBREG_REG (tmp);
6444 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6445 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6446 || reg_equiv_constant[REGNO (tmp)] != 0))
6448 if (! reg_equiv_mem[REGNO (tmp)]
6449 || num_not_at_initial_offset
6450 || GET_CODE (old) == SUBREG)
6453 real_old = reg_equiv_mem[REGNO (tmp)];
6456 second_reload_reg = rld[secondary_reload].reg_rtx;
6457 icode = rl->secondary_in_icode;
6459 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6460 || (rl->in != 0 && rl->out != 0))
6462 enum reg_class new_class
6463 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6464 mode, real_oldequiv);
6466 if (new_class == NO_REGS)
6467 second_reload_reg = 0;
6470 enum insn_code new_icode;
6471 enum machine_mode new_mode;
6473 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6474 REGNO (second_reload_reg)))
6475 oldequiv = old, real_oldequiv = real_old;
6478 new_icode = reload_in_optab[(int) mode];
6479 if (new_icode != CODE_FOR_nothing
6480 && ((insn_data[(int) new_icode].operand[0].predicate
6481 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6483 || (insn_data[(int) new_icode].operand[1].predicate
6484 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6485 (real_oldequiv, mode)))))
6486 new_icode = CODE_FOR_nothing;
6488 if (new_icode == CODE_FOR_nothing)
6491 new_mode = insn_data[(int) new_icode].operand[2].mode;
6493 if (GET_MODE (second_reload_reg) != new_mode)
6495 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6497 oldequiv = old, real_oldequiv = real_old;
6500 = reload_adjust_reg_for_mode (second_reload_reg,
6507 /* If we still need a secondary reload register, check
6508 to see if it is being used as a scratch or intermediate
6509 register and generate code appropriately. If we need
6510 a scratch register, use REAL_OLDEQUIV since the form of
6511 the insn may depend on the actual address if it is
6514 if (second_reload_reg)
6516 if (icode != CODE_FOR_nothing)
6518 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6519 second_reload_reg));
6524 /* See if we need a scratch register to load the
6525 intermediate register (a tertiary reload). */
6526 enum insn_code tertiary_icode
6527 = rld[secondary_reload].secondary_in_icode;
6529 if (tertiary_icode != CODE_FOR_nothing)
6531 rtx third_reload_reg
6532 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6534 emit_insn ((GEN_FCN (tertiary_icode)
6535 (second_reload_reg, real_oldequiv,
6536 third_reload_reg)));
6539 gen_reload (second_reload_reg, real_oldequiv,
6543 oldequiv = second_reload_reg;
6549 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6551 rtx real_oldequiv = oldequiv;
6553 if ((REG_P (oldequiv)
6554 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6555 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6556 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6557 || (GET_CODE (oldequiv) == SUBREG
6558 && REG_P (SUBREG_REG (oldequiv))
6559 && (REGNO (SUBREG_REG (oldequiv))
6560 >= FIRST_PSEUDO_REGISTER)
6561 && ((reg_equiv_memory_loc
6562 [REGNO (SUBREG_REG (oldequiv))] != 0)
6563 || (reg_equiv_constant
6564 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6565 || (CONSTANT_P (oldequiv)
6566 && (PREFERRED_RELOAD_CLASS (oldequiv,
6567 REGNO_REG_CLASS (REGNO (reloadreg)))
6569 real_oldequiv = rl->in;
6570 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6574 if (flag_non_call_exceptions)
6575 copy_eh_notes (insn, get_insns ());
6577 /* End this sequence. */
6578 *where = get_insns ();
6581 /* Update reload_override_in so that delete_address_reloads_1
6582 can see the actual register usage. */
6584 reload_override_in[j] = oldequiv;
6587 /* Generate insns to for the output reload RL, which is for the insn described
6588 by CHAIN and has the number J. */
6590 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6593 rtx reloadreg = rl->reg_rtx;
6594 rtx insn = chain->insn;
6597 enum machine_mode mode = GET_MODE (old);
6600 if (rl->when_needed == RELOAD_OTHER)
6603 push_to_sequence (output_reload_insns[rl->opnum]);
6605 /* Determine the mode to reload in.
6606 See comments above (for input reloading). */
6608 if (mode == VOIDmode)
6610 /* VOIDmode should never happen for an output. */
6611 if (asm_noperands (PATTERN (insn)) < 0)
6612 /* It's the compiler's fault. */
6613 fatal_insn ("VOIDmode on an output", insn);
6614 error_for_asm (insn, "output operand is constant in %<asm%>");
6615 /* Prevent crash--use something we know is valid. */
6617 old = gen_rtx_REG (mode, REGNO (reloadreg));
6620 if (GET_MODE (reloadreg) != mode)
6621 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6623 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6625 /* If we need two reload regs, set RELOADREG to the intermediate
6626 one, since it will be stored into OLD. We might need a secondary
6627 register only for an input reload, so check again here. */
6629 if (rl->secondary_out_reload >= 0)
6633 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
6634 && reg_equiv_mem[REGNO (old)] != 0)
6635 real_old = reg_equiv_mem[REGNO (old)];
6637 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6641 rtx second_reloadreg = reloadreg;
6642 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6644 /* See if RELOADREG is to be used as a scratch register
6645 or as an intermediate register. */
6646 if (rl->secondary_out_icode != CODE_FOR_nothing)
6648 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6649 (real_old, second_reloadreg, reloadreg)));
6654 /* See if we need both a scratch and intermediate reload
6657 int secondary_reload = rl->secondary_out_reload;
6658 enum insn_code tertiary_icode
6659 = rld[secondary_reload].secondary_out_icode;
6661 if (GET_MODE (reloadreg) != mode)
6662 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6664 if (tertiary_icode != CODE_FOR_nothing)
6667 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6670 /* Copy primary reload reg to secondary reload reg.
6671 (Note that these have been swapped above, then
6672 secondary reload reg to OLD using our insn.) */
6674 /* If REAL_OLD is a paradoxical SUBREG, remove it
6675 and try to put the opposite SUBREG on
6677 if (GET_CODE (real_old) == SUBREG
6678 && (GET_MODE_SIZE (GET_MODE (real_old))
6679 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6680 && 0 != (tem = gen_lowpart_common
6681 (GET_MODE (SUBREG_REG (real_old)),
6683 real_old = SUBREG_REG (real_old), reloadreg = tem;
6685 gen_reload (reloadreg, second_reloadreg,
6686 rl->opnum, rl->when_needed);
6687 emit_insn ((GEN_FCN (tertiary_icode)
6688 (real_old, reloadreg, third_reloadreg)));
6693 /* Copy between the reload regs here and then to
6696 gen_reload (reloadreg, second_reloadreg,
6697 rl->opnum, rl->when_needed);
6703 /* Output the last reload insn. */
6708 /* Don't output the last reload if OLD is not the dest of
6709 INSN and is in the src and is clobbered by INSN. */
6710 if (! flag_expensive_optimizations
6712 || !(set = single_set (insn))
6713 || rtx_equal_p (old, SET_DEST (set))
6714 || !reg_mentioned_p (old, SET_SRC (set))
6715 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6716 gen_reload (old, reloadreg, rl->opnum,
6720 /* Look at all insns we emitted, just to be safe. */
6721 for (p = get_insns (); p; p = NEXT_INSN (p))
6724 rtx pat = PATTERN (p);
6726 /* If this output reload doesn't come from a spill reg,
6727 clear any memory of reloaded copies of the pseudo reg.
6728 If this output reload comes from a spill reg,
6729 reg_has_output_reload will make this do nothing. */
6730 note_stores (pat, forget_old_reloads_1, NULL);
6732 if (reg_mentioned_p (rl->reg_rtx, pat))
6734 rtx set = single_set (insn);
6735 if (reload_spill_index[j] < 0
6737 && SET_SRC (set) == rl->reg_rtx)
6739 int src = REGNO (SET_SRC (set));
6741 reload_spill_index[j] = src;
6742 SET_HARD_REG_BIT (reg_is_output_reload, src);
6743 if (find_regno_note (insn, REG_DEAD, src))
6744 SET_HARD_REG_BIT (reg_reloaded_died, src);
6746 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6748 int s = rl->secondary_out_reload;
6749 set = single_set (p);
6750 /* If this reload copies only to the secondary reload
6751 register, the secondary reload does the actual
6753 if (s >= 0 && set == NULL_RTX)
6754 /* We can't tell what function the secondary reload
6755 has and where the actual store to the pseudo is
6756 made; leave new_spill_reg_store alone. */
6759 && SET_SRC (set) == rl->reg_rtx
6760 && SET_DEST (set) == rld[s].reg_rtx)
6762 /* Usually the next instruction will be the
6763 secondary reload insn; if we can confirm
6764 that it is, setting new_spill_reg_store to
6765 that insn will allow an extra optimization. */
6766 rtx s_reg = rld[s].reg_rtx;
6767 rtx next = NEXT_INSN (p);
6768 rld[s].out = rl->out;
6769 rld[s].out_reg = rl->out_reg;
6770 set = single_set (next);
6771 if (set && SET_SRC (set) == s_reg
6772 && ! new_spill_reg_store[REGNO (s_reg)])
6774 SET_HARD_REG_BIT (reg_is_output_reload,
6776 new_spill_reg_store[REGNO (s_reg)] = next;
6780 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6785 if (rl->when_needed == RELOAD_OTHER)
6787 emit_insn (other_output_reload_insns[rl->opnum]);
6788 other_output_reload_insns[rl->opnum] = get_insns ();
6791 output_reload_insns[rl->opnum] = get_insns ();
6793 if (flag_non_call_exceptions)
6794 copy_eh_notes (insn, get_insns ());
6799 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6800 and has the number J. */
6802 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
6804 rtx insn = chain->insn;
6805 rtx old = (rl->in && MEM_P (rl->in)
6806 ? rl->in_reg : rl->in);
6809 /* AUTO_INC reloads need to be handled even if inherited. We got an
6810 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6811 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6812 && ! rtx_equal_p (rl->reg_rtx, old)
6813 && rl->reg_rtx != 0)
6814 emit_input_reload_insns (chain, rld + j, old, j);
6816 /* When inheriting a wider reload, we have a MEM in rl->in,
6817 e.g. inheriting a SImode output reload for
6818 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6819 if (optimize && reload_inherited[j] && rl->in
6821 && MEM_P (rl->in_reg)
6822 && reload_spill_index[j] >= 0
6823 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6824 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6826 /* If we are reloading a register that was recently stored in with an
6827 output-reload, see if we can prove there was
6828 actually no need to store the old value in it. */
6831 && (reload_inherited[j] || reload_override_in[j])
6833 && REG_P (rl->reg_rtx)
6834 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6836 /* There doesn't seem to be any reason to restrict this to pseudos
6837 and doing so loses in the case where we are copying from a
6838 register of the wrong class. */
6839 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6840 >= FIRST_PSEUDO_REGISTER)
6842 /* The insn might have already some references to stackslots
6843 replaced by MEMs, while reload_out_reg still names the
6845 && (dead_or_set_p (insn,
6846 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6847 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6849 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6852 /* Do output reloading for reload RL, which is for the insn described by
6853 CHAIN and has the number J.
6854 ??? At some point we need to support handling output reloads of
6855 JUMP_INSNs or insns that set cc0. */
6857 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
6860 rtx insn = chain->insn;
6861 /* If this is an output reload that stores something that is
6862 not loaded in this same reload, see if we can eliminate a previous
6864 rtx pseudo = rl->out_reg;
6869 && ! rtx_equal_p (rl->in_reg, pseudo)
6870 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6871 && reg_last_reload_reg[REGNO (pseudo)])
6873 int pseudo_no = REGNO (pseudo);
6874 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6876 /* We don't need to test full validity of last_regno for
6877 inherit here; we only want to know if the store actually
6878 matches the pseudo. */
6879 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6880 && reg_reloaded_contents[last_regno] == pseudo_no
6881 && spill_reg_store[last_regno]
6882 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6883 delete_output_reload (insn, j, last_regno);
6888 || rl->reg_rtx == old
6889 || rl->reg_rtx == 0)
6892 /* An output operand that dies right away does need a reload,
6893 but need not be copied from it. Show the new location in the
6895 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
6896 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6898 XEXP (note, 0) = rl->reg_rtx;
6901 /* Likewise for a SUBREG of an operand that dies. */
6902 else if (GET_CODE (old) == SUBREG
6903 && REG_P (SUBREG_REG (old))
6904 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6907 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6911 else if (GET_CODE (old) == SCRATCH)
6912 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6913 but we don't want to make an output reload. */
6916 /* If is a JUMP_INSN, we can't support output reloads yet. */
6917 gcc_assert (!JUMP_P (insn));
6919 emit_output_reload_insns (chain, rld + j, j);
6922 /* Reload number R reloads from or to a group of hard registers starting at
6923 register REGNO. Return true if it can be treated for inheritance purposes
6924 like a group of reloads, each one reloading a single hard register.
6925 The caller has already checked that the spill register and REGNO use
6926 the same number of registers to store the reload value. */
6929 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
6931 #ifdef CANNOT_CHANGE_MODE_CLASS
6932 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
6933 GET_MODE (rld[r].reg_rtx),
6934 reg_raw_mode[reload_spill_index[r]])
6935 && !REG_CANNOT_CHANGE_MODE_P (regno,
6936 GET_MODE (rld[r].reg_rtx),
6937 reg_raw_mode[regno]));
6943 /* Output insns to reload values in and out of the chosen reload regs. */
6946 emit_reload_insns (struct insn_chain *chain)
6948 rtx insn = chain->insn;
6952 CLEAR_HARD_REG_SET (reg_reloaded_died);
6954 for (j = 0; j < reload_n_operands; j++)
6955 input_reload_insns[j] = input_address_reload_insns[j]
6956 = inpaddr_address_reload_insns[j]
6957 = output_reload_insns[j] = output_address_reload_insns[j]
6958 = outaddr_address_reload_insns[j]
6959 = other_output_reload_insns[j] = 0;
6960 other_input_address_reload_insns = 0;
6961 other_input_reload_insns = 0;
6962 operand_reload_insns = 0;
6963 other_operand_reload_insns = 0;
6965 /* Dump reloads into the dump file. */
6968 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6969 debug_reload_to_stream (dump_file);
6972 /* Now output the instructions to copy the data into and out of the
6973 reload registers. Do these in the order that the reloads were reported,
6974 since reloads of base and index registers precede reloads of operands
6975 and the operands may need the base and index registers reloaded. */
6977 for (j = 0; j < n_reloads; j++)
6980 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6981 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6983 do_input_reload (chain, rld + j, j);
6984 do_output_reload (chain, rld + j, j);
6987 /* Now write all the insns we made for reloads in the order expected by
6988 the allocation functions. Prior to the insn being reloaded, we write
6989 the following reloads:
6991 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6993 RELOAD_OTHER reloads.
6995 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6996 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6997 RELOAD_FOR_INPUT reload for the operand.
6999 RELOAD_FOR_OPADDR_ADDRS reloads.
7001 RELOAD_FOR_OPERAND_ADDRESS reloads.
7003 After the insn being reloaded, we write the following:
7005 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7006 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7007 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7008 reloads for the operand. The RELOAD_OTHER output reloads are
7009 output in descending order by reload number. */
7011 emit_insn_before_sameloc (other_input_address_reload_insns, insn);
7012 emit_insn_before_sameloc (other_input_reload_insns, insn);
7014 for (j = 0; j < reload_n_operands; j++)
7016 emit_insn_before_sameloc (inpaddr_address_reload_insns[j], insn);
7017 emit_insn_before_sameloc (input_address_reload_insns[j], insn);
7018 emit_insn_before_sameloc (input_reload_insns[j], insn);
7021 emit_insn_before_sameloc (other_operand_reload_insns, insn);
7022 emit_insn_before_sameloc (operand_reload_insns, insn);
7024 for (j = 0; j < reload_n_operands; j++)
7026 rtx x = emit_insn_after_sameloc (outaddr_address_reload_insns[j], insn);
7027 x = emit_insn_after_sameloc (output_address_reload_insns[j], x);
7028 x = emit_insn_after_sameloc (output_reload_insns[j], x);
7029 emit_insn_after_sameloc (other_output_reload_insns[j], x);
7032 /* For all the spill regs newly reloaded in this instruction,
7033 record what they were reloaded from, so subsequent instructions
7034 can inherit the reloads.
7036 Update spill_reg_store for the reloads of this insn.
7037 Copy the elements that were updated in the loop above. */
7039 for (j = 0; j < n_reloads; j++)
7041 int r = reload_order[j];
7042 int i = reload_spill_index[r];
7044 /* If this is a non-inherited input reload from a pseudo, we must
7045 clear any memory of a previous store to the same pseudo. Only do
7046 something if there will not be an output reload for the pseudo
7048 if (rld[r].in_reg != 0
7049 && ! (reload_inherited[r] || reload_override_in[r]))
7051 rtx reg = rld[r].in_reg;
7053 if (GET_CODE (reg) == SUBREG)
7054 reg = SUBREG_REG (reg);
7057 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7058 && ! reg_has_output_reload[REGNO (reg)])
7060 int nregno = REGNO (reg);
7062 if (reg_last_reload_reg[nregno])
7064 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7066 if (reg_reloaded_contents[last_regno] == nregno)
7067 spill_reg_store[last_regno] = 0;
7072 /* I is nonneg if this reload used a register.
7073 If rld[r].reg_rtx is 0, this is an optional reload
7074 that we opted to ignore. */
7076 if (i >= 0 && rld[r].reg_rtx != 0)
7078 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7080 int part_reaches_end = 0;
7081 int all_reaches_end = 1;
7083 /* For a multi register reload, we need to check if all or part
7084 of the value lives to the end. */
7085 for (k = 0; k < nr; k++)
7087 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7088 rld[r].when_needed))
7089 part_reaches_end = 1;
7091 all_reaches_end = 0;
7094 /* Ignore reloads that don't reach the end of the insn in
7096 if (all_reaches_end)
7098 /* First, clear out memory of what used to be in this spill reg.
7099 If consecutive registers are used, clear them all. */
7101 for (k = 0; k < nr; k++)
7103 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7104 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7107 /* Maybe the spill reg contains a copy of reload_out. */
7109 && (REG_P (rld[r].out)
7113 || REG_P (rld[r].out_reg)))
7115 rtx out = (REG_P (rld[r].out)
7119 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7120 int nregno = REGNO (out);
7121 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7122 : hard_regno_nregs[nregno]
7123 [GET_MODE (rld[r].reg_rtx)]);
7126 spill_reg_store[i] = new_spill_reg_store[i];
7127 spill_reg_stored_to[i] = out;
7128 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7130 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7132 && inherit_piecemeal_p (r, nregno));
7134 /* If NREGNO is a hard register, it may occupy more than
7135 one register. If it does, say what is in the
7136 rest of the registers assuming that both registers
7137 agree on how many words the object takes. If not,
7138 invalidate the subsequent registers. */
7140 if (nregno < FIRST_PSEUDO_REGISTER)
7141 for (k = 1; k < nnr; k++)
7142 reg_last_reload_reg[nregno + k]
7144 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7147 /* Now do the inverse operation. */
7148 for (k = 0; k < nr; k++)
7150 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7151 reg_reloaded_contents[i + k]
7152 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7155 reg_reloaded_insn[i + k] = insn;
7156 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7157 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7158 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7162 /* Maybe the spill reg contains a copy of reload_in. Only do
7163 something if there will not be an output reload for
7164 the register being reloaded. */
7165 else if (rld[r].out_reg == 0
7167 && ((REG_P (rld[r].in)
7168 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7169 && ! reg_has_output_reload[REGNO (rld[r].in)])
7170 || (REG_P (rld[r].in_reg)
7171 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7172 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7179 if (REG_P (rld[r].in)
7180 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7182 else if (REG_P (rld[r].in_reg))
7185 in = XEXP (rld[r].in_reg, 0);
7186 nregno = REGNO (in);
7188 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7189 : hard_regno_nregs[nregno]
7190 [GET_MODE (rld[r].reg_rtx)]);
7192 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7194 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7196 && inherit_piecemeal_p (r, nregno));
7198 if (nregno < FIRST_PSEUDO_REGISTER)
7199 for (k = 1; k < nnr; k++)
7200 reg_last_reload_reg[nregno + k]
7202 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7205 /* Unless we inherited this reload, show we haven't
7206 recently done a store.
7207 Previous stores of inherited auto_inc expressions
7208 also have to be discarded. */
7209 if (! reload_inherited[r]
7210 || (rld[r].out && ! rld[r].out_reg))
7211 spill_reg_store[i] = 0;
7213 for (k = 0; k < nr; k++)
7215 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7216 reg_reloaded_contents[i + k]
7217 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7220 reg_reloaded_insn[i + k] = insn;
7221 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7222 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7223 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7228 /* However, if part of the reload reaches the end, then we must
7229 invalidate the old info for the part that survives to the end. */
7230 else if (part_reaches_end)
7232 for (k = 0; k < nr; k++)
7233 if (reload_reg_reaches_end_p (i + k,
7235 rld[r].when_needed))
7236 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7240 /* The following if-statement was #if 0'd in 1.34 (or before...).
7241 It's reenabled in 1.35 because supposedly nothing else
7242 deals with this problem. */
7244 /* If a register gets output-reloaded from a non-spill register,
7245 that invalidates any previous reloaded copy of it.
7246 But forget_old_reloads_1 won't get to see it, because
7247 it thinks only about the original insn. So invalidate it here. */
7248 if (i < 0 && rld[r].out != 0
7249 && (REG_P (rld[r].out)
7250 || (MEM_P (rld[r].out)
7251 && REG_P (rld[r].out_reg))))
7253 rtx out = (REG_P (rld[r].out)
7254 ? rld[r].out : rld[r].out_reg);
7255 int nregno = REGNO (out);
7256 if (nregno >= FIRST_PSEUDO_REGISTER)
7258 rtx src_reg, store_insn = NULL_RTX;
7260 reg_last_reload_reg[nregno] = 0;
7262 /* If we can find a hard register that is stored, record
7263 the storing insn so that we may delete this insn with
7264 delete_output_reload. */
7265 src_reg = rld[r].reg_rtx;
7267 /* If this is an optional reload, try to find the source reg
7268 from an input reload. */
7271 rtx set = single_set (insn);
7272 if (set && SET_DEST (set) == rld[r].out)
7276 src_reg = SET_SRC (set);
7278 for (k = 0; k < n_reloads; k++)
7280 if (rld[k].in == src_reg)
7282 src_reg = rld[k].reg_rtx;
7289 store_insn = new_spill_reg_store[REGNO (src_reg)];
7290 if (src_reg && REG_P (src_reg)
7291 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7293 int src_regno = REGNO (src_reg);
7294 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7295 /* The place where to find a death note varies with
7296 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7297 necessarily checked exactly in the code that moves
7298 notes, so just check both locations. */
7299 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7300 if (! note && store_insn)
7301 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7304 spill_reg_store[src_regno + nr] = store_insn;
7305 spill_reg_stored_to[src_regno + nr] = out;
7306 reg_reloaded_contents[src_regno + nr] = nregno;
7307 reg_reloaded_insn[src_regno + nr] = store_insn;
7308 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7309 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7310 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7311 GET_MODE (src_reg)))
7312 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7314 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7316 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7318 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7320 reg_last_reload_reg[nregno] = src_reg;
7321 /* We have to set reg_has_output_reload here, or else
7322 forget_old_reloads_1 will clear reg_last_reload_reg
7324 reg_has_output_reload[nregno] = 1;
7329 int num_regs = hard_regno_nregs[nregno][GET_MODE (rld[r].out)];
7331 while (num_regs-- > 0)
7332 reg_last_reload_reg[nregno + num_regs] = 0;
7336 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7339 /* Emit code to perform a reload from IN (which may be a reload register) to
7340 OUT (which may also be a reload register). IN or OUT is from operand
7341 OPNUM with reload type TYPE.
7343 Returns first insn emitted. */
7346 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7348 rtx last = get_last_insn ();
7351 /* If IN is a paradoxical SUBREG, remove it and try to put the
7352 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7353 if (GET_CODE (in) == SUBREG
7354 && (GET_MODE_SIZE (GET_MODE (in))
7355 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7356 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7357 in = SUBREG_REG (in), out = tem;
7358 else if (GET_CODE (out) == SUBREG
7359 && (GET_MODE_SIZE (GET_MODE (out))
7360 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7361 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7362 out = SUBREG_REG (out), in = tem;
7364 /* How to do this reload can get quite tricky. Normally, we are being
7365 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7366 register that didn't get a hard register. In that case we can just
7367 call emit_move_insn.
7369 We can also be asked to reload a PLUS that adds a register or a MEM to
7370 another register, constant or MEM. This can occur during frame pointer
7371 elimination and while reloading addresses. This case is handled by
7372 trying to emit a single insn to perform the add. If it is not valid,
7373 we use a two insn sequence.
7375 Finally, we could be called to handle an 'o' constraint by putting
7376 an address into a register. In that case, we first try to do this
7377 with a named pattern of "reload_load_address". If no such pattern
7378 exists, we just emit a SET insn and hope for the best (it will normally
7379 be valid on machines that use 'o').
7381 This entire process is made complex because reload will never
7382 process the insns we generate here and so we must ensure that
7383 they will fit their constraints and also by the fact that parts of
7384 IN might be being reloaded separately and replaced with spill registers.
7385 Because of this, we are, in some sense, just guessing the right approach
7386 here. The one listed above seems to work.
7388 ??? At some point, this whole thing needs to be rethought. */
7390 if (GET_CODE (in) == PLUS
7391 && (REG_P (XEXP (in, 0))
7392 || GET_CODE (XEXP (in, 0)) == SUBREG
7393 || MEM_P (XEXP (in, 0)))
7394 && (REG_P (XEXP (in, 1))
7395 || GET_CODE (XEXP (in, 1)) == SUBREG
7396 || CONSTANT_P (XEXP (in, 1))
7397 || MEM_P (XEXP (in, 1))))
7399 /* We need to compute the sum of a register or a MEM and another
7400 register, constant, or MEM, and put it into the reload
7401 register. The best possible way of doing this is if the machine
7402 has a three-operand ADD insn that accepts the required operands.
7404 The simplest approach is to try to generate such an insn and see if it
7405 is recognized and matches its constraints. If so, it can be used.
7407 It might be better not to actually emit the insn unless it is valid,
7408 but we need to pass the insn as an operand to `recog' and
7409 `extract_insn' and it is simpler to emit and then delete the insn if
7410 not valid than to dummy things up. */
7412 rtx op0, op1, tem, insn;
7415 op0 = find_replacement (&XEXP (in, 0));
7416 op1 = find_replacement (&XEXP (in, 1));
7418 /* Since constraint checking is strict, commutativity won't be
7419 checked, so we need to do that here to avoid spurious failure
7420 if the add instruction is two-address and the second operand
7421 of the add is the same as the reload reg, which is frequently
7422 the case. If the insn would be A = B + A, rearrange it so
7423 it will be A = A + B as constrain_operands expects. */
7425 if (REG_P (XEXP (in, 1))
7426 && REGNO (out) == REGNO (XEXP (in, 1)))
7427 tem = op0, op0 = op1, op1 = tem;
7429 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7430 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7432 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7433 code = recog_memoized (insn);
7437 extract_insn (insn);
7438 /* We want constrain operands to treat this insn strictly in
7439 its validity determination, i.e., the way it would after reload
7441 if (constrain_operands (1))
7445 delete_insns_since (last);
7447 /* If that failed, we must use a conservative two-insn sequence.
7449 Use a move to copy one operand into the reload register. Prefer
7450 to reload a constant, MEM or pseudo since the move patterns can
7451 handle an arbitrary operand. If OP1 is not a constant, MEM or
7452 pseudo and OP1 is not a valid operand for an add instruction, then
7455 After reloading one of the operands into the reload register, add
7456 the reload register to the output register.
7458 If there is another way to do this for a specific machine, a
7459 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7462 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7464 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7466 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7467 || (code != CODE_FOR_nothing
7468 && ! ((*insn_data[code].operand[2].predicate)
7469 (op1, insn_data[code].operand[2].mode))))
7470 tem = op0, op0 = op1, op1 = tem;
7472 gen_reload (out, op0, opnum, type);
7474 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7475 This fixes a problem on the 32K where the stack pointer cannot
7476 be used as an operand of an add insn. */
7478 if (rtx_equal_p (op0, op1))
7481 insn = emit_insn (gen_add2_insn (out, op1));
7483 /* If that failed, copy the address register to the reload register.
7484 Then add the constant to the reload register. */
7486 code = recog_memoized (insn);
7490 extract_insn (insn);
7491 /* We want constrain operands to treat this insn strictly in
7492 its validity determination, i.e., the way it would after reload
7494 if (constrain_operands (1))
7496 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7498 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7503 delete_insns_since (last);
7505 gen_reload (out, op1, opnum, type);
7506 insn = emit_insn (gen_add2_insn (out, op0));
7507 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7510 #ifdef SECONDARY_MEMORY_NEEDED
7511 /* If we need a memory location to do the move, do it that way. */
7512 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7513 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7514 && (REG_P (out) || GET_CODE (out) == SUBREG)
7515 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7516 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7517 REGNO_REG_CLASS (reg_or_subregno (out)),
7520 /* Get the memory to use and rewrite both registers to its mode. */
7521 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7523 if (GET_MODE (loc) != GET_MODE (out))
7524 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7526 if (GET_MODE (loc) != GET_MODE (in))
7527 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7529 gen_reload (loc, in, opnum, type);
7530 gen_reload (out, loc, opnum, type);
7534 /* If IN is a simple operand, use gen_move_insn. */
7535 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
7536 emit_insn (gen_move_insn (out, in));
7538 #ifdef HAVE_reload_load_address
7539 else if (HAVE_reload_load_address)
7540 emit_insn (gen_reload_load_address (out, in));
7543 /* Otherwise, just write (set OUT IN) and hope for the best. */
7545 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7547 /* Return the first insn emitted.
7548 We can not just return get_last_insn, because there may have
7549 been multiple instructions emitted. Also note that gen_move_insn may
7550 emit more than one insn itself, so we can not assume that there is one
7551 insn emitted per emit_insn_before call. */
7553 return last ? NEXT_INSN (last) : get_insns ();
7556 /* Delete a previously made output-reload whose result we now believe
7557 is not needed. First we double-check.
7559 INSN is the insn now being processed.
7560 LAST_RELOAD_REG is the hard register number for which we want to delete
7561 the last output reload.
7562 J is the reload-number that originally used REG. The caller has made
7563 certain that reload J doesn't use REG any longer for input. */
7566 delete_output_reload (rtx insn, int j, int last_reload_reg)
7568 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7569 rtx reg = spill_reg_stored_to[last_reload_reg];
7572 int n_inherited = 0;
7576 /* It is possible that this reload has been only used to set another reload
7577 we eliminated earlier and thus deleted this instruction too. */
7578 if (INSN_DELETED_P (output_reload_insn))
7581 /* Get the raw pseudo-register referred to. */
7583 while (GET_CODE (reg) == SUBREG)
7584 reg = SUBREG_REG (reg);
7585 substed = reg_equiv_memory_loc[REGNO (reg)];
7587 /* This is unsafe if the operand occurs more often in the current
7588 insn than it is inherited. */
7589 for (k = n_reloads - 1; k >= 0; k--)
7591 rtx reg2 = rld[k].in;
7594 if (MEM_P (reg2) || reload_override_in[k])
7595 reg2 = rld[k].in_reg;
7597 if (rld[k].out && ! rld[k].out_reg)
7598 reg2 = XEXP (rld[k].in_reg, 0);
7600 while (GET_CODE (reg2) == SUBREG)
7601 reg2 = SUBREG_REG (reg2);
7602 if (rtx_equal_p (reg2, reg))
7604 if (reload_inherited[k] || reload_override_in[k] || k == j)
7607 reg2 = rld[k].out_reg;
7610 while (GET_CODE (reg2) == SUBREG)
7611 reg2 = XEXP (reg2, 0);
7612 if (rtx_equal_p (reg2, reg))
7619 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7621 n_occurrences += count_occurrences (PATTERN (insn),
7622 eliminate_regs (substed, 0,
7624 if (n_occurrences > n_inherited)
7627 /* If the pseudo-reg we are reloading is no longer referenced
7628 anywhere between the store into it and here,
7629 and no jumps or labels intervene, then the value can get
7630 here through the reload reg alone.
7631 Otherwise, give up--return. */
7632 for (i1 = NEXT_INSN (output_reload_insn);
7633 i1 != insn; i1 = NEXT_INSN (i1))
7635 if (LABEL_P (i1) || JUMP_P (i1))
7637 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
7638 && reg_mentioned_p (reg, PATTERN (i1)))
7640 /* If this is USE in front of INSN, we only have to check that
7641 there are no more references than accounted for by inheritance. */
7642 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
7644 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7645 i1 = NEXT_INSN (i1);
7647 if (n_occurrences <= n_inherited && i1 == insn)
7653 /* We will be deleting the insn. Remove the spill reg information. */
7654 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
7656 spill_reg_store[last_reload_reg + k] = 0;
7657 spill_reg_stored_to[last_reload_reg + k] = 0;
7660 /* The caller has already checked that REG dies or is set in INSN.
7661 It has also checked that we are optimizing, and thus some
7662 inaccuracies in the debugging information are acceptable.
7663 So we could just delete output_reload_insn. But in some cases
7664 we can improve the debugging information without sacrificing
7665 optimization - maybe even improving the code: See if the pseudo
7666 reg has been completely replaced with reload regs. If so, delete
7667 the store insn and forget we had a stack slot for the pseudo. */
7668 if (rld[j].out != rld[j].in
7669 && REG_N_DEATHS (REGNO (reg)) == 1
7670 && REG_N_SETS (REGNO (reg)) == 1
7671 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7672 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7676 /* We know that it was used only between here and the beginning of
7677 the current basic block. (We also know that the last use before
7678 INSN was the output reload we are thinking of deleting, but never
7679 mind that.) Search that range; see if any ref remains. */
7680 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7682 rtx set = single_set (i2);
7684 /* Uses which just store in the pseudo don't count,
7685 since if they are the only uses, they are dead. */
7686 if (set != 0 && SET_DEST (set) == reg)
7691 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
7692 && reg_mentioned_p (reg, PATTERN (i2)))
7694 /* Some other ref remains; just delete the output reload we
7696 delete_address_reloads (output_reload_insn, insn);
7697 delete_insn (output_reload_insn);
7702 /* Delete the now-dead stores into this pseudo. Note that this
7703 loop also takes care of deleting output_reload_insn. */
7704 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7706 rtx set = single_set (i2);
7708 if (set != 0 && SET_DEST (set) == reg)
7710 delete_address_reloads (i2, insn);
7718 /* For the debugging info, say the pseudo lives in this reload reg. */
7719 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7720 alter_reg (REGNO (reg), -1);
7724 delete_address_reloads (output_reload_insn, insn);
7725 delete_insn (output_reload_insn);
7729 /* We are going to delete DEAD_INSN. Recursively delete loads of
7730 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7731 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7733 delete_address_reloads (rtx dead_insn, rtx current_insn)
7735 rtx set = single_set (dead_insn);
7736 rtx set2, dst, prev, next;
7739 rtx dst = SET_DEST (set);
7741 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7743 /* If we deleted the store from a reloaded post_{in,de}c expression,
7744 we can delete the matching adds. */
7745 prev = PREV_INSN (dead_insn);
7746 next = NEXT_INSN (dead_insn);
7747 if (! prev || ! next)
7749 set = single_set (next);
7750 set2 = single_set (prev);
7752 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7753 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7754 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7756 dst = SET_DEST (set);
7757 if (! rtx_equal_p (dst, SET_DEST (set2))
7758 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7759 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7760 || (INTVAL (XEXP (SET_SRC (set), 1))
7761 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7763 delete_related_insns (prev);
7764 delete_related_insns (next);
7767 /* Subfunction of delete_address_reloads: process registers found in X. */
7769 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
7771 rtx prev, set, dst, i2;
7773 enum rtx_code code = GET_CODE (x);
7777 const char *fmt = GET_RTX_FORMAT (code);
7778 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7781 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7782 else if (fmt[i] == 'E')
7784 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7785 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7792 if (spill_reg_order[REGNO (x)] < 0)
7795 /* Scan backwards for the insn that sets x. This might be a way back due
7797 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7799 code = GET_CODE (prev);
7800 if (code == CODE_LABEL || code == JUMP_INSN)
7804 if (reg_set_p (x, PATTERN (prev)))
7806 if (reg_referenced_p (x, PATTERN (prev)))
7809 if (! prev || INSN_UID (prev) < reload_first_uid)
7811 /* Check that PREV only sets the reload register. */
7812 set = single_set (prev);
7815 dst = SET_DEST (set);
7817 || ! rtx_equal_p (dst, x))
7819 if (! reg_set_p (dst, PATTERN (dead_insn)))
7821 /* Check if DST was used in a later insn -
7822 it might have been inherited. */
7823 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7829 if (reg_referenced_p (dst, PATTERN (i2)))
7831 /* If there is a reference to the register in the current insn,
7832 it might be loaded in a non-inherited reload. If no other
7833 reload uses it, that means the register is set before
7835 if (i2 == current_insn)
7837 for (j = n_reloads - 1; j >= 0; j--)
7838 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7839 || reload_override_in[j] == dst)
7841 for (j = n_reloads - 1; j >= 0; j--)
7842 if (rld[j].in && rld[j].reg_rtx == dst)
7851 /* If DST is still live at CURRENT_INSN, check if it is used for
7852 any reload. Note that even if CURRENT_INSN sets DST, we still
7853 have to check the reloads. */
7854 if (i2 == current_insn)
7856 for (j = n_reloads - 1; j >= 0; j--)
7857 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7858 || reload_override_in[j] == dst)
7860 /* ??? We can't finish the loop here, because dst might be
7861 allocated to a pseudo in this block if no reload in this
7862 block needs any of the classes containing DST - see
7863 spill_hard_reg. There is no easy way to tell this, so we
7864 have to scan till the end of the basic block. */
7866 if (reg_set_p (dst, PATTERN (i2)))
7870 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7871 reg_reloaded_contents[REGNO (dst)] = -1;
7875 /* Output reload-insns to reload VALUE into RELOADREG.
7876 VALUE is an autoincrement or autodecrement RTX whose operand
7877 is a register or memory location;
7878 so reloading involves incrementing that location.
7879 IN is either identical to VALUE, or some cheaper place to reload from.
7881 INC_AMOUNT is the number to increment or decrement by (always positive).
7882 This cannot be deduced from VALUE.
7884 Return the instruction that stores into RELOADREG. */
7887 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
7889 /* REG or MEM to be copied and incremented. */
7890 rtx incloc = XEXP (value, 0);
7891 /* Nonzero if increment after copying. */
7892 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7898 rtx real_in = in == value ? XEXP (in, 0) : in;
7900 /* No hard register is equivalent to this register after
7901 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7902 we could inc/dec that register as well (maybe even using it for
7903 the source), but I'm not sure it's worth worrying about. */
7905 reg_last_reload_reg[REGNO (incloc)] = 0;
7907 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7908 inc_amount = -inc_amount;
7910 inc = GEN_INT (inc_amount);
7912 /* If this is post-increment, first copy the location to the reload reg. */
7913 if (post && real_in != reloadreg)
7914 emit_insn (gen_move_insn (reloadreg, real_in));
7918 /* See if we can directly increment INCLOC. Use a method similar to
7919 that in gen_reload. */
7921 last = get_last_insn ();
7922 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7923 gen_rtx_PLUS (GET_MODE (incloc),
7926 code = recog_memoized (add_insn);
7929 extract_insn (add_insn);
7930 if (constrain_operands (1))
7932 /* If this is a pre-increment and we have incremented the value
7933 where it lives, copy the incremented value to RELOADREG to
7934 be used as an address. */
7937 emit_insn (gen_move_insn (reloadreg, incloc));
7942 delete_insns_since (last);
7945 /* If couldn't do the increment directly, must increment in RELOADREG.
7946 The way we do this depends on whether this is pre- or post-increment.
7947 For pre-increment, copy INCLOC to the reload register, increment it
7948 there, then save back. */
7952 if (in != reloadreg)
7953 emit_insn (gen_move_insn (reloadreg, real_in));
7954 emit_insn (gen_add2_insn (reloadreg, inc));
7955 store = emit_insn (gen_move_insn (incloc, reloadreg));
7960 Because this might be a jump insn or a compare, and because RELOADREG
7961 may not be available after the insn in an input reload, we must do
7962 the incrementation before the insn being reloaded for.
7964 We have already copied IN to RELOADREG. Increment the copy in
7965 RELOADREG, save that back, then decrement RELOADREG so it has
7966 the original value. */
7968 emit_insn (gen_add2_insn (reloadreg, inc));
7969 store = emit_insn (gen_move_insn (incloc, reloadreg));
7970 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7978 add_auto_inc_notes (rtx insn, rtx x)
7980 enum rtx_code code = GET_CODE (x);
7984 if (code == MEM && auto_inc_p (XEXP (x, 0)))
7987 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
7991 /* Scan all the operand sub-expressions. */
7992 fmt = GET_RTX_FORMAT (code);
7993 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7996 add_auto_inc_notes (insn, XEXP (x, i));
7997 else if (fmt[i] == 'E')
7998 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7999 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8004 /* Copy EH notes from an insn to its reloads. */
8006 copy_eh_notes (rtx insn, rtx x)
8008 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8011 for (; x != 0; x = NEXT_INSN (x))
8013 if (may_trap_p (PATTERN (x)))
8015 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8021 /* This is used by reload pass, that does emit some instructions after
8022 abnormal calls moving basic block end, but in fact it wants to emit
8023 them on the edge. Looks for abnormal call edges, find backward the
8024 proper call and fix the damage.
8026 Similar handle instructions throwing exceptions internally. */
8028 fixup_abnormal_edges (void)
8030 bool inserted = false;
8038 /* Look for cases we are interested in - calls or instructions causing
8040 FOR_EACH_EDGE (e, ei, bb->succs)
8042 if (e->flags & EDGE_ABNORMAL_CALL)
8044 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8045 == (EDGE_ABNORMAL | EDGE_EH))
8048 if (e && !CALL_P (BB_END (bb))
8049 && !can_throw_internal (BB_END (bb)))
8051 rtx insn = BB_END (bb), stop = NEXT_INSN (BB_END (bb));
8053 FOR_EACH_EDGE (e, ei, bb->succs)
8054 if (e->flags & EDGE_FALLTHRU)
8056 /* Get past the new insns generated. Allow notes, as the insns may
8057 be already deleted. */
8058 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8059 && !can_throw_internal (insn)
8060 && insn != BB_HEAD (bb))
8061 insn = PREV_INSN (insn);
8062 gcc_assert (CALL_P (insn) || can_throw_internal (insn));
8065 insn = NEXT_INSN (insn);
8066 while (insn && insn != stop)
8068 next = NEXT_INSN (insn);
8073 /* Sometimes there's still the return value USE.
8074 If it's placed after a trapping call (i.e. that
8075 call is the last insn anyway), we have no fallthru
8076 edge. Simply delete this use and don't try to insert
8077 on the non-existent edge. */
8078 if (GET_CODE (PATTERN (insn)) != USE)
8080 /* We're not deleting it, we're moving it. */
8081 INSN_DELETED_P (insn) = 0;
8082 PREV_INSN (insn) = NULL_RTX;
8083 NEXT_INSN (insn) = NULL_RTX;
8085 insert_insn_on_edge (insn, e);
8092 /* We've possibly turned single trapping insn into multiple ones. */
8093 if (flag_non_call_exceptions)
8096 blocks = sbitmap_alloc (last_basic_block);
8097 sbitmap_ones (blocks);
8098 find_many_sub_basic_blocks (blocks);
8101 commit_edge_insertions ();
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