1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
48 /* This file contains the reload pass of the compiler, which is
49 run after register allocation has been done. It checks that
50 each insn is valid (operands required to be in registers really
51 are in registers of the proper class) and fixes up invalid ones
52 by copying values temporarily into registers for the insns
55 The results of register allocation are described by the vector
56 reg_renumber; the insns still contain pseudo regs, but reg_renumber
57 can be used to find which hard reg, if any, a pseudo reg is in.
59 The technique we always use is to free up a few hard regs that are
60 called ``reload regs'', and for each place where a pseudo reg
61 must be in a hard reg, copy it temporarily into one of the reload regs.
63 Reload regs are allocated locally for every instruction that needs
64 reloads. When there are pseudos which are allocated to a register that
65 has been chosen as a reload reg, such pseudos must be ``spilled''.
66 This means that they go to other hard regs, or to stack slots if no other
67 available hard regs can be found. Spilling can invalidate more
68 insns, requiring additional need for reloads, so we must keep checking
69 until the process stabilizes.
71 For machines with different classes of registers, we must keep track
72 of the register class needed for each reload, and make sure that
73 we allocate enough reload registers of each class.
75 The file reload.c contains the code that checks one insn for
76 validity and reports the reloads that it needs. This file
77 is in charge of scanning the entire rtl code, accumulating the
78 reload needs, spilling, assigning reload registers to use for
79 fixing up each insn, and generating the new insns to copy values
80 into the reload registers. */
82 #ifndef REGISTER_MOVE_COST
83 #define REGISTER_MOVE_COST(m, x, y) 2
87 #define LOCAL_REGNO(REGNO) 0
90 /* During reload_as_needed, element N contains a REG rtx for the hard reg
91 into which reg N has been reloaded (perhaps for a previous insn). */
92 static rtx *reg_last_reload_reg;
94 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
95 for an output reload that stores into reg N. */
96 static char *reg_has_output_reload;
98 /* Indicates which hard regs are reload-registers for an output reload
99 in the current insn. */
100 static HARD_REG_SET reg_is_output_reload;
102 /* Element N is the constant value to which pseudo reg N is equivalent,
103 or zero if pseudo reg N is not equivalent to a constant.
104 find_reloads looks at this in order to replace pseudo reg N
105 with the constant it stands for. */
106 rtx *reg_equiv_constant;
108 /* Element N is a memory location to which pseudo reg N is equivalent,
109 prior to any register elimination (such as frame pointer to stack
110 pointer). Depending on whether or not it is a valid address, this value
111 is transferred to either reg_equiv_address or reg_equiv_mem. */
112 rtx *reg_equiv_memory_loc;
114 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
115 This is used when the address is not valid as a memory address
116 (because its displacement is too big for the machine.) */
117 rtx *reg_equiv_address;
119 /* Element N is the memory slot to which pseudo reg N is equivalent,
120 or zero if pseudo reg N is not equivalent to a memory slot. */
123 /* Widest width in which each pseudo reg is referred to (via subreg). */
124 static unsigned int *reg_max_ref_width;
126 /* Element N is the list of insns that initialized reg N from its equivalent
127 constant or memory slot. */
128 static rtx *reg_equiv_init;
130 /* Vector to remember old contents of reg_renumber before spilling. */
131 static short *reg_old_renumber;
133 /* During reload_as_needed, element N contains the last pseudo regno reloaded
134 into hard register N. If that pseudo reg occupied more than one register,
135 reg_reloaded_contents points to that pseudo for each spill register in
136 use; all of these must remain set for an inheritance to occur. */
137 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
139 /* During reload_as_needed, element N contains the insn for which
140 hard register N was last used. Its contents are significant only
141 when reg_reloaded_valid is set for this register. */
142 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
144 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
145 static HARD_REG_SET reg_reloaded_valid;
146 /* Indicate if the register was dead at the end of the reload.
147 This is only valid if reg_reloaded_contents is set and valid. */
148 static HARD_REG_SET reg_reloaded_dead;
150 /* Number of spill-regs so far; number of valid elements of spill_regs. */
153 /* In parallel with spill_regs, contains REG rtx's for those regs.
154 Holds the last rtx used for any given reg, or 0 if it has never
155 been used for spilling yet. This rtx is reused, provided it has
157 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
159 /* In parallel with spill_regs, contains nonzero for a spill reg
160 that was stored after the last time it was used.
161 The precise value is the insn generated to do the store. */
162 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
164 /* This is the register that was stored with spill_reg_store. This is a
165 copy of reload_out / reload_out_reg when the value was stored; if
166 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
167 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
169 /* This table is the inverse mapping of spill_regs:
170 indexed by hard reg number,
171 it contains the position of that reg in spill_regs,
172 or -1 for something that is not in spill_regs.
174 ?!? This is no longer accurate. */
175 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
177 /* This reg set indicates registers that can't be used as spill registers for
178 the currently processed insn. These are the hard registers which are live
179 during the insn, but not allocated to pseudos, as well as fixed
181 static HARD_REG_SET bad_spill_regs;
183 /* These are the hard registers that can't be used as spill register for any
184 insn. This includes registers used for user variables and registers that
185 we can't eliminate. A register that appears in this set also can't be used
186 to retry register allocation. */
187 static HARD_REG_SET bad_spill_regs_global;
189 /* Describes order of use of registers for reloading
190 of spilled pseudo-registers. `n_spills' is the number of
191 elements that are actually valid; new ones are added at the end.
193 Both spill_regs and spill_reg_order are used on two occasions:
194 once during find_reload_regs, where they keep track of the spill registers
195 for a single insn, but also during reload_as_needed where they show all
196 the registers ever used by reload. For the latter case, the information
197 is calculated during finish_spills. */
198 static short spill_regs[FIRST_PSEUDO_REGISTER];
200 /* This vector of reg sets indicates, for each pseudo, which hard registers
201 may not be used for retrying global allocation because the register was
202 formerly spilled from one of them. If we allowed reallocating a pseudo to
203 a register that it was already allocated to, reload might not
205 static HARD_REG_SET *pseudo_previous_regs;
207 /* This vector of reg sets indicates, for each pseudo, which hard
208 registers may not be used for retrying global allocation because they
209 are used as spill registers during one of the insns in which the
211 static HARD_REG_SET *pseudo_forbidden_regs;
213 /* All hard regs that have been used as spill registers for any insn are
214 marked in this set. */
215 static HARD_REG_SET used_spill_regs;
217 /* Index of last register assigned as a spill register. We allocate in
218 a round-robin fashion. */
219 static int last_spill_reg;
221 /* Nonzero if indirect addressing is supported on the machine; this means
222 that spilling (REG n) does not require reloading it into a register in
223 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
224 value indicates the level of indirect addressing supported, e.g., two
225 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
227 static char spill_indirect_levels;
229 /* Nonzero if indirect addressing is supported when the innermost MEM is
230 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
231 which these are valid is the same as spill_indirect_levels, above. */
232 char indirect_symref_ok;
234 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
235 char double_reg_address_ok;
237 /* Record the stack slot for each spilled hard register. */
238 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
240 /* Width allocated so far for that stack slot. */
241 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
243 /* Record which pseudos needed to be spilled. */
244 static regset_head spilled_pseudos;
246 /* Used for communication between order_regs_for_reload and count_pseudo.
247 Used to avoid counting one pseudo twice. */
248 static regset_head pseudos_counted;
250 /* First uid used by insns created by reload in this function.
251 Used in find_equiv_reg. */
252 int reload_first_uid;
254 /* Flag set by local-alloc or global-alloc if anything is live in
255 a call-clobbered reg across calls. */
256 int caller_save_needed;
258 /* Set to 1 while reload_as_needed is operating.
259 Required by some machines to handle any generated moves differently. */
260 int reload_in_progress = 0;
262 /* These arrays record the insn_code of insns that may be needed to
263 perform input and output reloads of special objects. They provide a
264 place to pass a scratch register. */
265 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
266 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
268 /* This obstack is used for allocation of rtl during register elimination.
269 The allocated storage can be freed once find_reloads has processed the
271 struct obstack reload_obstack;
273 /* Points to the beginning of the reload_obstack. All insn_chain structures
274 are allocated first. */
275 char *reload_startobj;
277 /* The point after all insn_chain structures. Used to quickly deallocate
278 memory allocated in copy_reloads during calculate_needs_all_insns. */
279 char *reload_firstobj;
281 /* This points before all local rtl generated by register elimination.
282 Used to quickly free all memory after processing one insn. */
283 static char *reload_insn_firstobj;
285 /* List of insn_chain instructions, one for every insn that reload needs to
287 struct insn_chain *reload_insn_chain;
290 extern tree current_function_decl;
292 extern union tree_node *current_function_decl;
295 /* List of all insns needing reloads. */
296 static struct insn_chain *insns_need_reload;
298 /* This structure is used to record information about register eliminations.
299 Each array entry describes one possible way of eliminating a register
300 in favor of another. If there is more than one way of eliminating a
301 particular register, the most preferred should be specified first. */
305 int from; /* Register number to be eliminated. */
306 int to; /* Register number used as replacement. */
307 int initial_offset; /* Initial difference between values. */
308 int can_eliminate; /* Nonzero if this elimination can be done. */
309 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
310 insns made by reload. */
311 int offset; /* Current offset between the two regs. */
312 int previous_offset; /* Offset at end of previous insn. */
313 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
314 rtx from_rtx; /* REG rtx for the register to be eliminated.
315 We cannot simply compare the number since
316 we might then spuriously replace a hard
317 register corresponding to a pseudo
318 assigned to the reg to be eliminated. */
319 rtx to_rtx; /* REG rtx for the replacement. */
322 static struct elim_table *reg_eliminate = 0;
324 /* This is an intermediate structure to initialize the table. It has
325 exactly the members provided by ELIMINABLE_REGS. */
326 static const struct elim_table_1
330 } reg_eliminate_1[] =
332 /* If a set of eliminable registers was specified, define the table from it.
333 Otherwise, default to the normal case of the frame pointer being
334 replaced by the stack pointer. */
336 #ifdef ELIMINABLE_REGS
339 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
342 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
344 /* Record the number of pending eliminations that have an offset not equal
345 to their initial offset. If nonzero, we use a new copy of each
346 replacement result in any insns encountered. */
347 int num_not_at_initial_offset;
349 /* Count the number of registers that we may be able to eliminate. */
350 static int num_eliminable;
351 /* And the number of registers that are equivalent to a constant that
352 can be eliminated to frame_pointer / arg_pointer + constant. */
353 static int num_eliminable_invariants;
355 /* For each label, we record the offset of each elimination. If we reach
356 a label by more than one path and an offset differs, we cannot do the
357 elimination. This information is indexed by the number of the label.
358 The first table is an array of flags that records whether we have yet
359 encountered a label and the second table is an array of arrays, one
360 entry in the latter array for each elimination. */
362 static char *offsets_known_at;
363 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
365 /* Number of labels in the current function. */
367 static int num_labels;
369 static void replace_pseudos_in_call_usage PARAMS ((rtx *,
372 static void maybe_fix_stack_asms PARAMS ((void));
373 static void copy_reloads PARAMS ((struct insn_chain *));
374 static void calculate_needs_all_insns PARAMS ((int));
375 static int find_reg PARAMS ((struct insn_chain *, int));
376 static void find_reload_regs PARAMS ((struct insn_chain *));
377 static void select_reload_regs PARAMS ((void));
378 static void delete_caller_save_insns PARAMS ((void));
380 static void spill_failure PARAMS ((rtx, enum reg_class));
381 static void count_spilled_pseudo PARAMS ((int, int, int));
382 static void delete_dead_insn PARAMS ((rtx));
383 static void alter_reg PARAMS ((int, int));
384 static void set_label_offsets PARAMS ((rtx, rtx, int));
385 static void check_eliminable_occurrences PARAMS ((rtx));
386 static void elimination_effects PARAMS ((rtx, enum machine_mode));
387 static int eliminate_regs_in_insn PARAMS ((rtx, int));
388 static void update_eliminable_offsets PARAMS ((void));
389 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
390 static void set_initial_elim_offsets PARAMS ((void));
391 static void verify_initial_elim_offsets PARAMS ((void));
392 static void set_initial_label_offsets PARAMS ((void));
393 static void set_offsets_for_label PARAMS ((rtx));
394 static void init_elim_table PARAMS ((void));
395 static void update_eliminables PARAMS ((HARD_REG_SET *));
396 static void spill_hard_reg PARAMS ((unsigned int, int));
397 static int finish_spills PARAMS ((int));
398 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
399 static void scan_paradoxical_subregs PARAMS ((rtx));
400 static void count_pseudo PARAMS ((int));
401 static void order_regs_for_reload PARAMS ((struct insn_chain *));
402 static void reload_as_needed PARAMS ((int));
403 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
404 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
405 static void mark_reload_reg_in_use PARAMS ((unsigned int, int,
408 static void clear_reload_reg_in_use PARAMS ((unsigned int, int,
411 static int reload_reg_free_p PARAMS ((unsigned int, int,
413 static int reload_reg_free_for_value_p PARAMS ((int, int, int,
415 rtx, rtx, int, int));
416 static int free_for_value_p PARAMS ((int, enum machine_mode, int,
417 enum reload_type, rtx, rtx,
419 static int reload_reg_reaches_end_p PARAMS ((unsigned int, int,
421 static int allocate_reload_reg PARAMS ((struct insn_chain *, int,
423 static int conflicts_with_override PARAMS ((rtx));
424 static void failed_reload PARAMS ((rtx, int));
425 static int set_reload_reg PARAMS ((int, int));
426 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
427 static void choose_reload_regs PARAMS ((struct insn_chain *));
428 static void merge_assigned_reloads PARAMS ((rtx));
429 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
430 struct reload *, rtx, int));
431 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
432 struct reload *, int));
433 static void do_input_reload PARAMS ((struct insn_chain *,
434 struct reload *, int));
435 static void do_output_reload PARAMS ((struct insn_chain *,
436 struct reload *, int));
437 static void emit_reload_insns PARAMS ((struct insn_chain *));
438 static void delete_output_reload PARAMS ((rtx, int, int));
439 static void delete_address_reloads PARAMS ((rtx, rtx));
440 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
441 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
442 static void reload_cse_regs_1 PARAMS ((rtx));
443 static int reload_cse_noop_set_p PARAMS ((rtx));
444 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
445 static int reload_cse_simplify_operands PARAMS ((rtx, rtx));
446 static void reload_combine PARAMS ((void));
447 static void reload_combine_note_use PARAMS ((rtx *, rtx));
448 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
449 static void reload_cse_move2add PARAMS ((rtx));
450 static void move2add_note_store PARAMS ((rtx, rtx, void *));
452 static void add_auto_inc_notes PARAMS ((rtx, rtx));
454 static void copy_eh_notes PARAMS ((rtx, rtx));
455 static HOST_WIDE_INT sext_for_mode PARAMS ((enum machine_mode,
457 static void failed_reload PARAMS ((rtx, int));
458 static int set_reload_reg PARAMS ((int, int));
459 static void reload_cse_simplify PARAMS ((rtx, rtx));
460 void fixup_abnormal_edges PARAMS ((void));
461 extern void dump_needs PARAMS ((struct insn_chain *));
463 /* Initialize the reload pass once per compilation. */
470 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
471 Set spill_indirect_levels to the number of levels such addressing is
472 permitted, zero if it is not permitted at all. */
475 = gen_rtx_MEM (Pmode,
478 LAST_VIRTUAL_REGISTER + 1),
480 spill_indirect_levels = 0;
482 while (memory_address_p (QImode, tem))
484 spill_indirect_levels++;
485 tem = gen_rtx_MEM (Pmode, tem);
488 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
490 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
491 indirect_symref_ok = memory_address_p (QImode, tem);
493 /* See if reg+reg is a valid (and offsettable) address. */
495 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
497 tem = gen_rtx_PLUS (Pmode,
498 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
499 gen_rtx_REG (Pmode, i));
501 /* This way, we make sure that reg+reg is an offsettable address. */
502 tem = plus_constant (tem, 4);
504 if (memory_address_p (QImode, tem))
506 double_reg_address_ok = 1;
511 /* Initialize obstack for our rtl allocation. */
512 gcc_obstack_init (&reload_obstack);
513 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
515 INIT_REG_SET (&spilled_pseudos);
516 INIT_REG_SET (&pseudos_counted);
519 /* List of insn chains that are currently unused. */
520 static struct insn_chain *unused_insn_chains = 0;
522 /* Allocate an empty insn_chain structure. */
526 struct insn_chain *c;
528 if (unused_insn_chains == 0)
530 c = (struct insn_chain *)
531 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
532 INIT_REG_SET (&c->live_throughout);
533 INIT_REG_SET (&c->dead_or_set);
537 c = unused_insn_chains;
538 unused_insn_chains = c->next;
540 c->is_caller_save_insn = 0;
541 c->need_operand_change = 0;
547 /* Small utility function to set all regs in hard reg set TO which are
548 allocated to pseudos in regset FROM. */
551 compute_use_by_pseudos (to, from)
557 EXECUTE_IF_SET_IN_REG_SET
558 (from, FIRST_PSEUDO_REGISTER, regno,
560 int r = reg_renumber[regno];
565 /* reload_combine uses the information from
566 BASIC_BLOCK->global_live_at_start, which might still
567 contain registers that have not actually been allocated
568 since they have an equivalence. */
569 if (! reload_completed)
574 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
576 SET_HARD_REG_BIT (*to, r + nregs);
581 /* Replace all pseudos found in LOC with their corresponding
585 replace_pseudos_in_call_usage (loc, mem_mode, usage)
587 enum machine_mode mem_mode;
601 unsigned int regno = REGNO (x);
603 if (regno < FIRST_PSEUDO_REGISTER)
606 x = eliminate_regs (x, mem_mode, usage);
610 replace_pseudos_in_call_usage (loc, mem_mode, usage);
614 if (reg_equiv_constant[regno])
615 *loc = reg_equiv_constant[regno];
616 else if (reg_equiv_mem[regno])
617 *loc = reg_equiv_mem[regno];
618 else if (reg_equiv_address[regno])
619 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
620 else if (GET_CODE (regno_reg_rtx[regno]) != REG
621 || REGNO (regno_reg_rtx[regno]) != regno)
622 *loc = regno_reg_rtx[regno];
628 else if (code == MEM)
630 replace_pseudos_in_call_usage (& XEXP (x, 0), GET_MODE (x), usage);
634 /* Process each of our operands recursively. */
635 fmt = GET_RTX_FORMAT (code);
636 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
638 replace_pseudos_in_call_usage (&XEXP (x, i), mem_mode, usage);
639 else if (*fmt == 'E')
640 for (j = 0; j < XVECLEN (x, i); j++)
641 replace_pseudos_in_call_usage (& XVECEXP (x, i, j), mem_mode, usage);
645 /* Global variables used by reload and its subroutines. */
647 /* Set during calculate_needs if an insn needs register elimination. */
648 static int something_needs_elimination;
649 /* Set during calculate_needs if an insn needs an operand changed. */
650 int something_needs_operands_changed;
652 /* Nonzero means we couldn't get enough spill regs. */
655 /* Main entry point for the reload pass.
657 FIRST is the first insn of the function being compiled.
659 GLOBAL nonzero means we were called from global_alloc
660 and should attempt to reallocate any pseudoregs that we
661 displace from hard regs we will use for reloads.
662 If GLOBAL is zero, we do not have enough information to do that,
663 so any pseudo reg that is spilled must go to the stack.
665 Return value is nonzero if reload failed
666 and we must not do any more for this function. */
669 reload (first, global)
675 struct elim_table *ep;
678 /* The two pointers used to track the true location of the memory used
679 for label offsets. */
680 char *real_known_ptr = NULL;
681 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
683 /* Make sure even insns with volatile mem refs are recognizable. */
688 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
690 /* Make sure that the last insn in the chain
691 is not something that needs reloading. */
692 emit_note (NULL, NOTE_INSN_DELETED);
694 /* Enable find_equiv_reg to distinguish insns made by reload. */
695 reload_first_uid = get_max_uid ();
697 #ifdef SECONDARY_MEMORY_NEEDED
698 /* Initialize the secondary memory table. */
699 clear_secondary_mem ();
702 /* We don't have a stack slot for any spill reg yet. */
703 memset ((char *) spill_stack_slot, 0, sizeof spill_stack_slot);
704 memset ((char *) spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
706 /* Initialize the save area information for caller-save, in case some
710 /* Compute which hard registers are now in use
711 as homes for pseudo registers.
712 This is done here rather than (eg) in global_alloc
713 because this point is reached even if not optimizing. */
714 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
717 /* A function that receives a nonlocal goto must save all call-saved
719 if (current_function_has_nonlocal_label)
720 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
721 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
722 regs_ever_live[i] = 1;
724 /* Find all the pseudo registers that didn't get hard regs
725 but do have known equivalent constants or memory slots.
726 These include parameters (known equivalent to parameter slots)
727 and cse'd or loop-moved constant memory addresses.
729 Record constant equivalents in reg_equiv_constant
730 so they will be substituted by find_reloads.
731 Record memory equivalents in reg_mem_equiv so they can
732 be substituted eventually by altering the REG-rtx's. */
734 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
735 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
736 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
737 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
738 reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int));
739 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
740 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
741 pseudo_forbidden_regs
742 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
744 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
746 CLEAR_HARD_REG_SET (bad_spill_regs_global);
748 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
749 Also find all paradoxical subregs and find largest such for each pseudo.
750 On machines with small register classes, record hard registers that
751 are used for user variables. These can never be used for spills.
752 Also look for a "constant" REG_SETJMP. This means that all
753 caller-saved registers must be marked live. */
755 num_eliminable_invariants = 0;
756 for (insn = first; insn; insn = NEXT_INSN (insn))
758 rtx set = single_set (insn);
760 /* We may introduce USEs that we want to remove at the end, so
761 we'll mark them with QImode. Make sure there are no
762 previously-marked insns left by say regmove. */
763 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
764 && GET_MODE (insn) != VOIDmode)
765 PUT_MODE (insn, VOIDmode);
767 if (GET_CODE (insn) == CALL_INSN
768 && find_reg_note (insn, REG_SETJMP, NULL))
769 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
770 if (! call_used_regs[i])
771 regs_ever_live[i] = 1;
773 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
775 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
777 #ifdef LEGITIMATE_PIC_OPERAND_P
778 && (! function_invariant_p (XEXP (note, 0))
780 /* A function invariant is often CONSTANT_P but may
781 include a register. We promise to only pass
782 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
783 || (CONSTANT_P (XEXP (note, 0))
784 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))))
788 rtx x = XEXP (note, 0);
789 i = REGNO (SET_DEST (set));
790 if (i > LAST_VIRTUAL_REGISTER)
792 /* It can happen that a REG_EQUIV note contains a MEM
793 that is not a legitimate memory operand. As later
794 stages of reload assume that all addresses found
795 in the reg_equiv_* arrays were originally legitimate,
796 we ignore such REG_EQUIV notes. */
797 if (memory_operand (x, VOIDmode))
799 /* Always unshare the equivalence, so we can
800 substitute into this insn without touching the
802 reg_equiv_memory_loc[i] = copy_rtx (x);
804 else if (function_invariant_p (x))
806 if (GET_CODE (x) == PLUS)
808 /* This is PLUS of frame pointer and a constant,
809 and might be shared. Unshare it. */
810 reg_equiv_constant[i] = copy_rtx (x);
811 num_eliminable_invariants++;
813 else if (x == frame_pointer_rtx
814 || x == arg_pointer_rtx)
816 reg_equiv_constant[i] = x;
817 num_eliminable_invariants++;
819 else if (LEGITIMATE_CONSTANT_P (x))
820 reg_equiv_constant[i] = x;
823 reg_equiv_memory_loc[i]
824 = force_const_mem (GET_MODE (SET_DEST (set)), x);
825 if (!reg_equiv_memory_loc[i])
832 /* If this register is being made equivalent to a MEM
833 and the MEM is not SET_SRC, the equivalencing insn
834 is one with the MEM as a SET_DEST and it occurs later.
835 So don't mark this insn now. */
836 if (GET_CODE (x) != MEM
837 || rtx_equal_p (SET_SRC (set), x))
839 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
844 /* If this insn is setting a MEM from a register equivalent to it,
845 this is the equivalencing insn. */
846 else if (set && GET_CODE (SET_DEST (set)) == MEM
847 && GET_CODE (SET_SRC (set)) == REG
848 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
849 && rtx_equal_p (SET_DEST (set),
850 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
851 reg_equiv_init[REGNO (SET_SRC (set))]
852 = gen_rtx_INSN_LIST (VOIDmode, insn,
853 reg_equiv_init[REGNO (SET_SRC (set))]);
856 scan_paradoxical_subregs (PATTERN (insn));
861 num_labels = max_label_num () - get_first_label_num ();
863 /* Allocate the tables used to store offset information at labels. */
864 /* We used to use alloca here, but the size of what it would try to
865 allocate would occasionally cause it to exceed the stack limit and
866 cause a core dump. */
867 real_known_ptr = xmalloc (num_labels);
869 = (int (*)[NUM_ELIMINABLE_REGS])
870 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
872 offsets_known_at = real_known_ptr - get_first_label_num ();
874 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
876 /* Alter each pseudo-reg rtx to contain its hard reg number.
877 Assign stack slots to the pseudos that lack hard regs or equivalents.
878 Do not touch virtual registers. */
880 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
883 /* If we have some registers we think can be eliminated, scan all insns to
884 see if there is an insn that sets one of these registers to something
885 other than itself plus a constant. If so, the register cannot be
886 eliminated. Doing this scan here eliminates an extra pass through the
887 main reload loop in the most common case where register elimination
889 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
890 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
891 || GET_CODE (insn) == CALL_INSN)
892 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
894 maybe_fix_stack_asms ();
896 insns_need_reload = 0;
897 something_needs_elimination = 0;
899 /* Initialize to -1, which means take the first spill register. */
902 /* Spill any hard regs that we know we can't eliminate. */
903 CLEAR_HARD_REG_SET (used_spill_regs);
904 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
905 if (! ep->can_eliminate)
906 spill_hard_reg (ep->from, 1);
908 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
909 if (frame_pointer_needed)
910 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
912 finish_spills (global);
914 /* From now on, we may need to generate moves differently. We may also
915 allow modifications of insns which cause them to not be recognized.
916 Any such modifications will be cleaned up during reload itself. */
917 reload_in_progress = 1;
919 /* This loop scans the entire function each go-round
920 and repeats until one repetition spills no additional hard regs. */
923 int something_changed;
926 HOST_WIDE_INT starting_frame_size;
928 /* Round size of stack frame to stack_alignment_needed. This must be done
929 here because the stack size may be a part of the offset computation
930 for register elimination, and there might have been new stack slots
931 created in the last iteration of this loop. */
932 if (cfun->stack_alignment_needed)
933 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
935 starting_frame_size = get_frame_size ();
937 set_initial_elim_offsets ();
938 set_initial_label_offsets ();
940 /* For each pseudo register that has an equivalent location defined,
941 try to eliminate any eliminable registers (such as the frame pointer)
942 assuming initial offsets for the replacement register, which
945 If the resulting location is directly addressable, substitute
946 the MEM we just got directly for the old REG.
948 If it is not addressable but is a constant or the sum of a hard reg
949 and constant, it is probably not addressable because the constant is
950 out of range, in that case record the address; we will generate
951 hairy code to compute the address in a register each time it is
952 needed. Similarly if it is a hard register, but one that is not
953 valid as an address register.
955 If the location is not addressable, but does not have one of the
956 above forms, assign a stack slot. We have to do this to avoid the
957 potential of producing lots of reloads if, e.g., a location involves
958 a pseudo that didn't get a hard register and has an equivalent memory
959 location that also involves a pseudo that didn't get a hard register.
961 Perhaps at some point we will improve reload_when_needed handling
962 so this problem goes away. But that's very hairy. */
964 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
965 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
967 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
969 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
971 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
972 else if (CONSTANT_P (XEXP (x, 0))
973 || (GET_CODE (XEXP (x, 0)) == REG
974 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
975 || (GET_CODE (XEXP (x, 0)) == PLUS
976 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
977 && (REGNO (XEXP (XEXP (x, 0), 0))
978 < FIRST_PSEUDO_REGISTER)
979 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
980 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
983 /* Make a new stack slot. Then indicate that something
984 changed so we go back and recompute offsets for
985 eliminable registers because the allocation of memory
986 below might change some offset. reg_equiv_{mem,address}
987 will be set up for this pseudo on the next pass around
989 reg_equiv_memory_loc[i] = 0;
990 reg_equiv_init[i] = 0;
995 if (caller_save_needed)
998 /* If we allocated another stack slot, redo elimination bookkeeping. */
999 if (starting_frame_size != get_frame_size ())
1002 if (caller_save_needed)
1004 save_call_clobbered_regs ();
1005 /* That might have allocated new insn_chain structures. */
1006 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1009 calculate_needs_all_insns (global);
1011 CLEAR_REG_SET (&spilled_pseudos);
1014 something_changed = 0;
1016 /* If we allocated any new memory locations, make another pass
1017 since it might have changed elimination offsets. */
1018 if (starting_frame_size != get_frame_size ())
1019 something_changed = 1;
1022 HARD_REG_SET to_spill;
1023 CLEAR_HARD_REG_SET (to_spill);
1024 update_eliminables (&to_spill);
1025 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1026 if (TEST_HARD_REG_BIT (to_spill, i))
1028 spill_hard_reg (i, 1);
1031 /* Regardless of the state of spills, if we previously had
1032 a register that we thought we could eliminate, but now can
1033 not eliminate, we must run another pass.
1035 Consider pseudos which have an entry in reg_equiv_* which
1036 reference an eliminable register. We must make another pass
1037 to update reg_equiv_* so that we do not substitute in the
1038 old value from when we thought the elimination could be
1040 something_changed = 1;
1044 select_reload_regs ();
1048 if (insns_need_reload != 0 || did_spill)
1049 something_changed |= finish_spills (global);
1051 if (! something_changed)
1054 if (caller_save_needed)
1055 delete_caller_save_insns ();
1057 obstack_free (&reload_obstack, reload_firstobj);
1060 /* If global-alloc was run, notify it of any register eliminations we have
1063 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1064 if (ep->can_eliminate)
1065 mark_elimination (ep->from, ep->to);
1067 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1068 If that insn didn't set the register (i.e., it copied the register to
1069 memory), just delete that insn instead of the equivalencing insn plus
1070 anything now dead. If we call delete_dead_insn on that insn, we may
1071 delete the insn that actually sets the register if the register dies
1072 there and that is incorrect. */
1074 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1076 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1079 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1081 rtx equiv_insn = XEXP (list, 0);
1083 /* If we already deleted the insn or if it may trap, we can't
1084 delete it. The latter case shouldn't happen, but can
1085 if an insn has a variable address, gets a REG_EH_REGION
1086 note added to it, and then gets converted into an load
1087 from a constant address. */
1088 if (GET_CODE (equiv_insn) == NOTE
1089 || can_throw_internal (equiv_insn))
1091 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1092 delete_dead_insn (equiv_insn);
1095 PUT_CODE (equiv_insn, NOTE);
1096 NOTE_SOURCE_FILE (equiv_insn) = 0;
1097 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1103 /* Use the reload registers where necessary
1104 by generating move instructions to move the must-be-register
1105 values into or out of the reload registers. */
1107 if (insns_need_reload != 0 || something_needs_elimination
1108 || something_needs_operands_changed)
1110 HOST_WIDE_INT old_frame_size = get_frame_size ();
1112 reload_as_needed (global);
1114 if (old_frame_size != get_frame_size ())
1118 verify_initial_elim_offsets ();
1121 /* If we were able to eliminate the frame pointer, show that it is no
1122 longer live at the start of any basic block. If it ls live by
1123 virtue of being in a pseudo, that pseudo will be marked live
1124 and hence the frame pointer will be known to be live via that
1127 if (! frame_pointer_needed)
1129 CLEAR_REGNO_REG_SET (bb->global_live_at_start,
1130 HARD_FRAME_POINTER_REGNUM);
1132 /* Come here (with failure set nonzero) if we can't get enough spill regs
1133 and we decide not to abort about it. */
1136 CLEAR_REG_SET (&spilled_pseudos);
1137 reload_in_progress = 0;
1139 /* Now eliminate all pseudo regs by modifying them into
1140 their equivalent memory references.
1141 The REG-rtx's for the pseudos are modified in place,
1142 so all insns that used to refer to them now refer to memory.
1144 For a reg that has a reg_equiv_address, all those insns
1145 were changed by reloading so that no insns refer to it any longer;
1146 but the DECL_RTL of a variable decl may refer to it,
1147 and if so this causes the debugging info to mention the variable. */
1149 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1153 if (reg_equiv_mem[i])
1154 addr = XEXP (reg_equiv_mem[i], 0);
1156 if (reg_equiv_address[i])
1157 addr = reg_equiv_address[i];
1161 if (reg_renumber[i] < 0)
1163 rtx reg = regno_reg_rtx[i];
1165 REG_USERVAR_P (reg) = 0;
1166 PUT_CODE (reg, MEM);
1167 XEXP (reg, 0) = addr;
1168 if (reg_equiv_memory_loc[i])
1169 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1172 RTX_UNCHANGING_P (reg) = MEM_IN_STRUCT_P (reg)
1173 = MEM_SCALAR_P (reg) = 0;
1174 MEM_ATTRS (reg) = 0;
1177 else if (reg_equiv_mem[i])
1178 XEXP (reg_equiv_mem[i], 0) = addr;
1182 /* We must set reload_completed now since the cleanup_subreg_operands call
1183 below will re-recognize each insn and reload may have generated insns
1184 which are only valid during and after reload. */
1185 reload_completed = 1;
1187 /* Make a pass over all the insns and delete all USEs which we inserted
1188 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1189 notes. Delete all CLOBBER insns, except those that refer to the return
1190 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1191 from misarranging variable-array code, and simplify (subreg (reg))
1192 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1193 are no longer useful or accurate. Strip and regenerate REG_INC notes
1194 that may have been moved around. */
1196 for (insn = first; insn; insn = NEXT_INSN (insn))
1201 if (GET_CODE (insn) == CALL_INSN)
1202 replace_pseudos_in_call_usage (& CALL_INSN_FUNCTION_USAGE (insn),
1204 CALL_INSN_FUNCTION_USAGE (insn));
1206 if ((GET_CODE (PATTERN (insn)) == USE
1207 /* We mark with QImode USEs introduced by reload itself. */
1208 && (GET_MODE (insn) == QImode
1209 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1210 || (GET_CODE (PATTERN (insn)) == CLOBBER
1211 && (GET_CODE (XEXP (PATTERN (insn), 0)) != MEM
1212 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1213 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1214 && XEXP (XEXP (PATTERN (insn), 0), 0)
1215 != stack_pointer_rtx))
1216 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1217 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1223 pnote = ®_NOTES (insn);
1226 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1227 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1228 || REG_NOTE_KIND (*pnote) == REG_INC
1229 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1230 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1231 *pnote = XEXP (*pnote, 1);
1233 pnote = &XEXP (*pnote, 1);
1237 add_auto_inc_notes (insn, PATTERN (insn));
1240 /* And simplify (subreg (reg)) if it appears as an operand. */
1241 cleanup_subreg_operands (insn);
1244 /* If we are doing stack checking, give a warning if this function's
1245 frame size is larger than we expect. */
1246 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1248 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1249 static int verbose_warned = 0;
1251 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1252 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1253 size += UNITS_PER_WORD;
1255 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1257 warning ("frame size too large for reliable stack checking");
1258 if (! verbose_warned)
1260 warning ("try reducing the number of local variables");
1266 /* Indicate that we no longer have known memory locations or constants. */
1267 if (reg_equiv_constant)
1268 free (reg_equiv_constant);
1269 reg_equiv_constant = 0;
1270 if (reg_equiv_memory_loc)
1271 free (reg_equiv_memory_loc);
1272 reg_equiv_memory_loc = 0;
1275 free (real_known_ptr);
1279 free (reg_equiv_mem);
1280 free (reg_equiv_init);
1281 free (reg_equiv_address);
1282 free (reg_max_ref_width);
1283 free (reg_old_renumber);
1284 free (pseudo_previous_regs);
1285 free (pseudo_forbidden_regs);
1287 CLEAR_HARD_REG_SET (used_spill_regs);
1288 for (i = 0; i < n_spills; i++)
1289 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1291 /* Free all the insn_chain structures at once. */
1292 obstack_free (&reload_obstack, reload_startobj);
1293 unused_insn_chains = 0;
1294 fixup_abnormal_edges ();
1296 /* Replacing pseudos with their memory equivalents might have
1297 created shared rtx. Subsequent passes would get confused
1298 by this, so unshare everything here. */
1299 unshare_all_rtl_again (first);
1304 /* Yet another special case. Unfortunately, reg-stack forces people to
1305 write incorrect clobbers in asm statements. These clobbers must not
1306 cause the register to appear in bad_spill_regs, otherwise we'll call
1307 fatal_insn later. We clear the corresponding regnos in the live
1308 register sets to avoid this.
1309 The whole thing is rather sick, I'm afraid. */
1312 maybe_fix_stack_asms ()
1315 const char *constraints[MAX_RECOG_OPERANDS];
1316 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1317 struct insn_chain *chain;
1319 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1322 HARD_REG_SET clobbered, allowed;
1325 if (! INSN_P (chain->insn)
1326 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1328 pat = PATTERN (chain->insn);
1329 if (GET_CODE (pat) != PARALLEL)
1332 CLEAR_HARD_REG_SET (clobbered);
1333 CLEAR_HARD_REG_SET (allowed);
1335 /* First, make a mask of all stack regs that are clobbered. */
1336 for (i = 0; i < XVECLEN (pat, 0); i++)
1338 rtx t = XVECEXP (pat, 0, i);
1339 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1340 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1343 /* Get the operand values and constraints out of the insn. */
1344 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1345 constraints, operand_mode);
1347 /* For every operand, see what registers are allowed. */
1348 for (i = 0; i < noperands; i++)
1350 const char *p = constraints[i];
1351 /* For every alternative, we compute the class of registers allowed
1352 for reloading in CLS, and merge its contents into the reg set
1354 int cls = (int) NO_REGS;
1360 if (c == '\0' || c == ',' || c == '#')
1362 /* End of one alternative - mark the regs in the current
1363 class, and reset the class. */
1364 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1370 } while (c != '\0' && c != ',');
1378 case '=': case '+': case '*': case '%': case '?': case '!':
1379 case '0': case '1': case '2': case '3': case '4': case 'm':
1380 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1381 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1382 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1387 cls = (int) reg_class_subunion[cls]
1388 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1393 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1397 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1398 cls = (int) reg_class_subunion[cls]
1399 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1401 cls = (int) reg_class_subunion[cls]
1402 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1404 p += CONSTRAINT_LEN (c, p);
1407 /* Those of the registers which are clobbered, but allowed by the
1408 constraints, must be usable as reload registers. So clear them
1409 out of the life information. */
1410 AND_HARD_REG_SET (allowed, clobbered);
1411 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1412 if (TEST_HARD_REG_BIT (allowed, i))
1414 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1415 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1422 /* Copy the global variables n_reloads and rld into the corresponding elts
1425 copy_reloads (chain)
1426 struct insn_chain *chain;
1428 chain->n_reloads = n_reloads;
1430 = (struct reload *) obstack_alloc (&reload_obstack,
1431 n_reloads * sizeof (struct reload));
1432 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1433 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1436 /* Walk the chain of insns, and determine for each whether it needs reloads
1437 and/or eliminations. Build the corresponding insns_need_reload list, and
1438 set something_needs_elimination as appropriate. */
1440 calculate_needs_all_insns (global)
1443 struct insn_chain **pprev_reload = &insns_need_reload;
1444 struct insn_chain *chain, *next = 0;
1446 something_needs_elimination = 0;
1448 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1449 for (chain = reload_insn_chain; chain != 0; chain = next)
1451 rtx insn = chain->insn;
1455 /* Clear out the shortcuts. */
1456 chain->n_reloads = 0;
1457 chain->need_elim = 0;
1458 chain->need_reload = 0;
1459 chain->need_operand_change = 0;
1461 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1462 include REG_LABEL), we need to see what effects this has on the
1463 known offsets at labels. */
1465 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1466 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1467 set_label_offsets (insn, insn, 0);
1471 rtx old_body = PATTERN (insn);
1472 int old_code = INSN_CODE (insn);
1473 rtx old_notes = REG_NOTES (insn);
1474 int did_elimination = 0;
1475 int operands_changed = 0;
1476 rtx set = single_set (insn);
1478 /* Skip insns that only set an equivalence. */
1479 if (set && GET_CODE (SET_DEST (set)) == REG
1480 && reg_renumber[REGNO (SET_DEST (set))] < 0
1481 && reg_equiv_constant[REGNO (SET_DEST (set))])
1484 /* If needed, eliminate any eliminable registers. */
1485 if (num_eliminable || num_eliminable_invariants)
1486 did_elimination = eliminate_regs_in_insn (insn, 0);
1488 /* Analyze the instruction. */
1489 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1490 global, spill_reg_order);
1492 /* If a no-op set needs more than one reload, this is likely
1493 to be something that needs input address reloads. We
1494 can't get rid of this cleanly later, and it is of no use
1495 anyway, so discard it now.
1496 We only do this when expensive_optimizations is enabled,
1497 since this complements reload inheritance / output
1498 reload deletion, and it can make debugging harder. */
1499 if (flag_expensive_optimizations && n_reloads > 1)
1501 rtx set = single_set (insn);
1503 && SET_SRC (set) == SET_DEST (set)
1504 && GET_CODE (SET_SRC (set)) == REG
1505 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1508 /* Delete it from the reload chain. */
1510 chain->prev->next = next;
1512 reload_insn_chain = next;
1514 next->prev = chain->prev;
1515 chain->next = unused_insn_chains;
1516 unused_insn_chains = chain;
1521 update_eliminable_offsets ();
1523 /* Remember for later shortcuts which insns had any reloads or
1524 register eliminations. */
1525 chain->need_elim = did_elimination;
1526 chain->need_reload = n_reloads > 0;
1527 chain->need_operand_change = operands_changed;
1529 /* Discard any register replacements done. */
1530 if (did_elimination)
1532 obstack_free (&reload_obstack, reload_insn_firstobj);
1533 PATTERN (insn) = old_body;
1534 INSN_CODE (insn) = old_code;
1535 REG_NOTES (insn) = old_notes;
1536 something_needs_elimination = 1;
1539 something_needs_operands_changed |= operands_changed;
1543 copy_reloads (chain);
1544 *pprev_reload = chain;
1545 pprev_reload = &chain->next_need_reload;
1552 /* Comparison function for qsort to decide which of two reloads
1553 should be handled first. *P1 and *P2 are the reload numbers. */
1556 reload_reg_class_lower (r1p, r2p)
1560 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1563 /* Consider required reloads before optional ones. */
1564 t = rld[r1].optional - rld[r2].optional;
1568 /* Count all solitary classes before non-solitary ones. */
1569 t = ((reg_class_size[(int) rld[r2].class] == 1)
1570 - (reg_class_size[(int) rld[r1].class] == 1));
1574 /* Aside from solitaires, consider all multi-reg groups first. */
1575 t = rld[r2].nregs - rld[r1].nregs;
1579 /* Consider reloads in order of increasing reg-class number. */
1580 t = (int) rld[r1].class - (int) rld[r2].class;
1584 /* If reloads are equally urgent, sort by reload number,
1585 so that the results of qsort leave nothing to chance. */
1589 /* The cost of spilling each hard reg. */
1590 static int spill_cost[FIRST_PSEUDO_REGISTER];
1592 /* When spilling multiple hard registers, we use SPILL_COST for the first
1593 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1594 only the first hard reg for a multi-reg pseudo. */
1595 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1597 /* Update the spill cost arrays, considering that pseudo REG is live. */
1603 int freq = REG_FREQ (reg);
1604 int r = reg_renumber[reg];
1607 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1608 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1611 SET_REGNO_REG_SET (&pseudos_counted, reg);
1616 spill_add_cost[r] += freq;
1618 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1620 spill_cost[r + nregs] += freq;
1623 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1624 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1627 order_regs_for_reload (chain)
1628 struct insn_chain *chain;
1631 HARD_REG_SET used_by_pseudos;
1632 HARD_REG_SET used_by_pseudos2;
1634 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1636 memset (spill_cost, 0, sizeof spill_cost);
1637 memset (spill_add_cost, 0, sizeof spill_add_cost);
1639 /* Count number of uses of each hard reg by pseudo regs allocated to it
1640 and then order them by decreasing use. First exclude hard registers
1641 that are live in or across this insn. */
1643 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1644 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1645 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1646 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1648 /* Now find out which pseudos are allocated to it, and update
1650 CLEAR_REG_SET (&pseudos_counted);
1652 EXECUTE_IF_SET_IN_REG_SET
1653 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1657 EXECUTE_IF_SET_IN_REG_SET
1658 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1662 CLEAR_REG_SET (&pseudos_counted);
1665 /* Vector of reload-numbers showing the order in which the reloads should
1667 static short reload_order[MAX_RELOADS];
1669 /* This is used to keep track of the spill regs used in one insn. */
1670 static HARD_REG_SET used_spill_regs_local;
1672 /* We decided to spill hard register SPILLED, which has a size of
1673 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1674 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1675 update SPILL_COST/SPILL_ADD_COST. */
1678 count_spilled_pseudo (spilled, spilled_nregs, reg)
1679 int spilled, spilled_nregs, reg;
1681 int r = reg_renumber[reg];
1682 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1684 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1685 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1688 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1690 spill_add_cost[r] -= REG_FREQ (reg);
1692 spill_cost[r + nregs] -= REG_FREQ (reg);
1695 /* Find reload register to use for reload number ORDER. */
1698 find_reg (chain, order)
1699 struct insn_chain *chain;
1702 int rnum = reload_order[order];
1703 struct reload *rl = rld + rnum;
1704 int best_cost = INT_MAX;
1708 HARD_REG_SET not_usable;
1709 HARD_REG_SET used_by_other_reload;
1711 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1712 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1713 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1715 CLEAR_HARD_REG_SET (used_by_other_reload);
1716 for (k = 0; k < order; k++)
1718 int other = reload_order[k];
1720 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1721 for (j = 0; j < rld[other].nregs; j++)
1722 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1725 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1727 unsigned int regno = i;
1729 if (! TEST_HARD_REG_BIT (not_usable, regno)
1730 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1731 && HARD_REGNO_MODE_OK (regno, rl->mode))
1733 int this_cost = spill_cost[regno];
1735 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1737 for (j = 1; j < this_nregs; j++)
1739 this_cost += spill_add_cost[regno + j];
1740 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1741 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1746 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1748 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1750 if (this_cost < best_cost
1751 /* Among registers with equal cost, prefer caller-saved ones, or
1752 use REG_ALLOC_ORDER if it is defined. */
1753 || (this_cost == best_cost
1754 #ifdef REG_ALLOC_ORDER
1755 && (inv_reg_alloc_order[regno]
1756 < inv_reg_alloc_order[best_reg])
1758 && call_used_regs[regno]
1759 && ! call_used_regs[best_reg]
1764 best_cost = this_cost;
1772 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1774 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1775 rl->regno = best_reg;
1777 EXECUTE_IF_SET_IN_REG_SET
1778 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1780 count_spilled_pseudo (best_reg, rl->nregs, j);
1783 EXECUTE_IF_SET_IN_REG_SET
1784 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1786 count_spilled_pseudo (best_reg, rl->nregs, j);
1789 for (i = 0; i < rl->nregs; i++)
1791 if (spill_cost[best_reg + i] != 0
1792 || spill_add_cost[best_reg + i] != 0)
1794 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1799 /* Find more reload regs to satisfy the remaining need of an insn, which
1801 Do it by ascending class number, since otherwise a reg
1802 might be spilled for a big class and might fail to count
1803 for a smaller class even though it belongs to that class. */
1806 find_reload_regs (chain)
1807 struct insn_chain *chain;
1811 /* In order to be certain of getting the registers we need,
1812 we must sort the reloads into order of increasing register class.
1813 Then our grabbing of reload registers will parallel the process
1814 that provided the reload registers. */
1815 for (i = 0; i < chain->n_reloads; i++)
1817 /* Show whether this reload already has a hard reg. */
1818 if (chain->rld[i].reg_rtx)
1820 int regno = REGNO (chain->rld[i].reg_rtx);
1821 chain->rld[i].regno = regno;
1823 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1826 chain->rld[i].regno = -1;
1827 reload_order[i] = i;
1830 n_reloads = chain->n_reloads;
1831 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1833 CLEAR_HARD_REG_SET (used_spill_regs_local);
1836 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1838 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1840 /* Compute the order of preference for hard registers to spill. */
1842 order_regs_for_reload (chain);
1844 for (i = 0; i < n_reloads; i++)
1846 int r = reload_order[i];
1848 /* Ignore reloads that got marked inoperative. */
1849 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1850 && ! rld[r].optional
1851 && rld[r].regno == -1)
1852 if (! find_reg (chain, i))
1854 spill_failure (chain->insn, rld[r].class);
1860 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1861 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1863 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1867 select_reload_regs ()
1869 struct insn_chain *chain;
1871 /* Try to satisfy the needs for each insn. */
1872 for (chain = insns_need_reload; chain != 0;
1873 chain = chain->next_need_reload)
1874 find_reload_regs (chain);
1877 /* Delete all insns that were inserted by emit_caller_save_insns during
1880 delete_caller_save_insns ()
1882 struct insn_chain *c = reload_insn_chain;
1886 while (c != 0 && c->is_caller_save_insn)
1888 struct insn_chain *next = c->next;
1891 if (c == reload_insn_chain)
1892 reload_insn_chain = next;
1896 next->prev = c->prev;
1898 c->prev->next = next;
1899 c->next = unused_insn_chains;
1900 unused_insn_chains = c;
1908 /* Handle the failure to find a register to spill.
1909 INSN should be one of the insns which needed this particular spill reg. */
1912 spill_failure (insn, class)
1914 enum reg_class class;
1916 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1917 if (asm_noperands (PATTERN (insn)) >= 0)
1918 error_for_asm (insn, "can't find a register in class `%s' while reloading `asm'",
1919 reg_class_names[class]);
1922 error ("unable to find a register to spill in class `%s'",
1923 reg_class_names[class]);
1924 fatal_insn ("this is the insn:", insn);
1928 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1929 data that is dead in INSN. */
1932 delete_dead_insn (insn)
1935 rtx prev = prev_real_insn (insn);
1938 /* If the previous insn sets a register that dies in our insn, delete it
1940 if (prev && GET_CODE (PATTERN (prev)) == SET
1941 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1942 && reg_mentioned_p (prev_dest, PATTERN (insn))
1943 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1944 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1945 delete_dead_insn (prev);
1947 PUT_CODE (insn, NOTE);
1948 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1949 NOTE_SOURCE_FILE (insn) = 0;
1952 /* Modify the home of pseudo-reg I.
1953 The new home is present in reg_renumber[I].
1955 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1956 or it may be -1, meaning there is none or it is not relevant.
1957 This is used so that all pseudos spilled from a given hard reg
1958 can share one stack slot. */
1961 alter_reg (i, from_reg)
1965 /* When outputting an inline function, this can happen
1966 for a reg that isn't actually used. */
1967 if (regno_reg_rtx[i] == 0)
1970 /* If the reg got changed to a MEM at rtl-generation time,
1972 if (GET_CODE (regno_reg_rtx[i]) != REG)
1975 /* Modify the reg-rtx to contain the new hard reg
1976 number or else to contain its pseudo reg number. */
1977 REGNO (regno_reg_rtx[i])
1978 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1980 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1981 allocate a stack slot for it. */
1983 if (reg_renumber[i] < 0
1984 && REG_N_REFS (i) > 0
1985 && reg_equiv_constant[i] == 0
1986 && reg_equiv_memory_loc[i] == 0)
1989 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1990 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1993 /* Each pseudo reg has an inherent size which comes from its own mode,
1994 and a total size which provides room for paradoxical subregs
1995 which refer to the pseudo reg in wider modes.
1997 We can use a slot already allocated if it provides both
1998 enough inherent space and enough total space.
1999 Otherwise, we allocate a new slot, making sure that it has no less
2000 inherent space, and no less total space, then the previous slot. */
2003 /* No known place to spill from => no slot to reuse. */
2004 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
2005 inherent_size == total_size ? 0 : -1);
2006 if (BYTES_BIG_ENDIAN)
2007 /* Cancel the big-endian correction done in assign_stack_local.
2008 Get the address of the beginning of the slot.
2009 This is so we can do a big-endian correction unconditionally
2011 adjust = inherent_size - total_size;
2013 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2015 /* Nothing can alias this slot except this pseudo. */
2016 set_mem_alias_set (x, new_alias_set ());
2019 /* Reuse a stack slot if possible. */
2020 else if (spill_stack_slot[from_reg] != 0
2021 && spill_stack_slot_width[from_reg] >= total_size
2022 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2024 x = spill_stack_slot[from_reg];
2026 /* Allocate a bigger slot. */
2029 /* Compute maximum size needed, both for inherent size
2030 and for total size. */
2031 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2034 if (spill_stack_slot[from_reg])
2036 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2038 mode = GET_MODE (spill_stack_slot[from_reg]);
2039 if (spill_stack_slot_width[from_reg] > total_size)
2040 total_size = spill_stack_slot_width[from_reg];
2043 /* Make a slot with that size. */
2044 x = assign_stack_local (mode, total_size,
2045 inherent_size == total_size ? 0 : -1);
2048 /* All pseudos mapped to this slot can alias each other. */
2049 if (spill_stack_slot[from_reg])
2050 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2052 set_mem_alias_set (x, new_alias_set ());
2054 if (BYTES_BIG_ENDIAN)
2056 /* Cancel the big-endian correction done in assign_stack_local.
2057 Get the address of the beginning of the slot.
2058 This is so we can do a big-endian correction unconditionally
2060 adjust = GET_MODE_SIZE (mode) - total_size;
2063 = adjust_address_nv (x, mode_for_size (total_size
2069 spill_stack_slot[from_reg] = stack_slot;
2070 spill_stack_slot_width[from_reg] = total_size;
2073 /* On a big endian machine, the "address" of the slot
2074 is the address of the low part that fits its inherent mode. */
2075 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2076 adjust += (total_size - inherent_size);
2078 /* If we have any adjustment to make, or if the stack slot is the
2079 wrong mode, make a new stack slot. */
2080 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2082 /* If we have a decl for the original register, set it for the
2083 memory. If this is a shared MEM, make a copy. */
2086 rtx decl = DECL_RTL_IF_SET (REGNO_DECL (i));
2088 /* We can do this only for the DECLs home pseudo, not for
2089 any copies of it, since otherwise when the stack slot
2090 is reused, nonoverlapping_memrefs_p might think they
2092 if (decl && GET_CODE (decl) == REG && REGNO (decl) == (unsigned) i)
2094 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2097 set_mem_expr (x, REGNO_DECL (i));
2101 /* Save the stack slot for later. */
2102 reg_equiv_memory_loc[i] = x;
2106 /* Mark the slots in regs_ever_live for the hard regs
2107 used by pseudo-reg number REGNO. */
2110 mark_home_live (regno)
2115 i = reg_renumber[regno];
2118 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2120 regs_ever_live[i++] = 1;
2123 /* This function handles the tracking of elimination offsets around branches.
2125 X is a piece of RTL being scanned.
2127 INSN is the insn that it came from, if any.
2129 INITIAL_P is nonzero if we are to set the offset to be the initial
2130 offset and zero if we are setting the offset of the label to be the
2134 set_label_offsets (x, insn, initial_p)
2139 enum rtx_code code = GET_CODE (x);
2142 struct elim_table *p;
2147 if (LABEL_REF_NONLOCAL_P (x))
2152 /* ... fall through ... */
2155 /* If we know nothing about this label, set the desired offsets. Note
2156 that this sets the offset at a label to be the offset before a label
2157 if we don't know anything about the label. This is not correct for
2158 the label after a BARRIER, but is the best guess we can make. If
2159 we guessed wrong, we will suppress an elimination that might have
2160 been possible had we been able to guess correctly. */
2162 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2164 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2165 offsets_at[CODE_LABEL_NUMBER (x)][i]
2166 = (initial_p ? reg_eliminate[i].initial_offset
2167 : reg_eliminate[i].offset);
2168 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2171 /* Otherwise, if this is the definition of a label and it is
2172 preceded by a BARRIER, set our offsets to the known offset of
2176 && (tem = prev_nonnote_insn (insn)) != 0
2177 && GET_CODE (tem) == BARRIER)
2178 set_offsets_for_label (insn);
2180 /* If neither of the above cases is true, compare each offset
2181 with those previously recorded and suppress any eliminations
2182 where the offsets disagree. */
2184 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2185 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2186 != (initial_p ? reg_eliminate[i].initial_offset
2187 : reg_eliminate[i].offset))
2188 reg_eliminate[i].can_eliminate = 0;
2193 set_label_offsets (PATTERN (insn), insn, initial_p);
2195 /* ... fall through ... */
2199 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2200 and hence must have all eliminations at their initial offsets. */
2201 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2202 if (REG_NOTE_KIND (tem) == REG_LABEL)
2203 set_label_offsets (XEXP (tem, 0), insn, 1);
2209 /* Each of the labels in the parallel or address vector must be
2210 at their initial offsets. We want the first field for PARALLEL
2211 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2213 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2214 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2219 /* We only care about setting PC. If the source is not RETURN,
2220 IF_THEN_ELSE, or a label, disable any eliminations not at
2221 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2222 isn't one of those possibilities. For branches to a label,
2223 call ourselves recursively.
2225 Note that this can disable elimination unnecessarily when we have
2226 a non-local goto since it will look like a non-constant jump to
2227 someplace in the current function. This isn't a significant
2228 problem since such jumps will normally be when all elimination
2229 pairs are back to their initial offsets. */
2231 if (SET_DEST (x) != pc_rtx)
2234 switch (GET_CODE (SET_SRC (x)))
2241 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2245 tem = XEXP (SET_SRC (x), 1);
2246 if (GET_CODE (tem) == LABEL_REF)
2247 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2248 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2251 tem = XEXP (SET_SRC (x), 2);
2252 if (GET_CODE (tem) == LABEL_REF)
2253 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2254 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2262 /* If we reach here, all eliminations must be at their initial
2263 offset because we are doing a jump to a variable address. */
2264 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2265 if (p->offset != p->initial_offset)
2266 p->can_eliminate = 0;
2274 /* Scan X and replace any eliminable registers (such as fp) with a
2275 replacement (such as sp), plus an offset.
2277 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2278 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2279 MEM, we are allowed to replace a sum of a register and the constant zero
2280 with the register, which we cannot do outside a MEM. In addition, we need
2281 to record the fact that a register is referenced outside a MEM.
2283 If INSN is an insn, it is the insn containing X. If we replace a REG
2284 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2285 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2286 the REG is being modified.
2288 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2289 That's used when we eliminate in expressions stored in notes.
2290 This means, do not set ref_outside_mem even if the reference
2293 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2294 replacements done assuming all offsets are at their initial values. If
2295 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2296 encounter, return the actual location so that find_reloads will do
2297 the proper thing. */
2300 eliminate_regs (x, mem_mode, insn)
2302 enum machine_mode mem_mode;
2305 enum rtx_code code = GET_CODE (x);
2306 struct elim_table *ep;
2313 if (! current_function_decl)
2333 /* This is only for the benefit of the debugging backends, which call
2334 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2335 removed after CSE. */
2336 new = eliminate_regs (XEXP (x, 0), 0, insn);
2337 if (GET_CODE (new) == MEM)
2338 return XEXP (new, 0);
2344 /* First handle the case where we encounter a bare register that
2345 is eliminable. Replace it with a PLUS. */
2346 if (regno < FIRST_PSEUDO_REGISTER)
2348 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2350 if (ep->from_rtx == x && ep->can_eliminate)
2351 return plus_constant (ep->to_rtx, ep->previous_offset);
2354 else if (reg_renumber && reg_renumber[regno] < 0
2355 && reg_equiv_constant && reg_equiv_constant[regno]
2356 && ! CONSTANT_P (reg_equiv_constant[regno]))
2357 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2361 /* You might think handling MINUS in a manner similar to PLUS is a
2362 good idea. It is not. It has been tried multiple times and every
2363 time the change has had to have been reverted.
2365 Other parts of reload know a PLUS is special (gen_reload for example)
2366 and require special code to handle code a reloaded PLUS operand.
2368 Also consider backends where the flags register is clobbered by a
2369 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2370 lea instruction comes to mind). If we try to reload a MINUS, we
2371 may kill the flags register that was holding a useful value.
2373 So, please before trying to handle MINUS, consider reload as a
2374 whole instead of this little section as well as the backend issues. */
2376 /* If this is the sum of an eliminable register and a constant, rework
2378 if (GET_CODE (XEXP (x, 0)) == REG
2379 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2380 && CONSTANT_P (XEXP (x, 1)))
2382 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2384 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2386 /* The only time we want to replace a PLUS with a REG (this
2387 occurs when the constant operand of the PLUS is the negative
2388 of the offset) is when we are inside a MEM. We won't want
2389 to do so at other times because that would change the
2390 structure of the insn in a way that reload can't handle.
2391 We special-case the commonest situation in
2392 eliminate_regs_in_insn, so just replace a PLUS with a
2393 PLUS here, unless inside a MEM. */
2394 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2395 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2398 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2399 plus_constant (XEXP (x, 1),
2400 ep->previous_offset));
2403 /* If the register is not eliminable, we are done since the other
2404 operand is a constant. */
2408 /* If this is part of an address, we want to bring any constant to the
2409 outermost PLUS. We will do this by doing register replacement in
2410 our operands and seeing if a constant shows up in one of them.
2412 Note that there is no risk of modifying the structure of the insn,
2413 since we only get called for its operands, thus we are either
2414 modifying the address inside a MEM, or something like an address
2415 operand of a load-address insn. */
2418 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2419 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2421 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2423 /* If one side is a PLUS and the other side is a pseudo that
2424 didn't get a hard register but has a reg_equiv_constant,
2425 we must replace the constant here since it may no longer
2426 be in the position of any operand. */
2427 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2428 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2429 && reg_renumber[REGNO (new1)] < 0
2430 && reg_equiv_constant != 0
2431 && reg_equiv_constant[REGNO (new1)] != 0)
2432 new1 = reg_equiv_constant[REGNO (new1)];
2433 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2434 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2435 && reg_renumber[REGNO (new0)] < 0
2436 && reg_equiv_constant[REGNO (new0)] != 0)
2437 new0 = reg_equiv_constant[REGNO (new0)];
2439 new = form_sum (new0, new1);
2441 /* As above, if we are not inside a MEM we do not want to
2442 turn a PLUS into something else. We might try to do so here
2443 for an addition of 0 if we aren't optimizing. */
2444 if (! mem_mode && GET_CODE (new) != PLUS)
2445 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2453 /* If this is the product of an eliminable register and a
2454 constant, apply the distribute law and move the constant out
2455 so that we have (plus (mult ..) ..). This is needed in order
2456 to keep load-address insns valid. This case is pathological.
2457 We ignore the possibility of overflow here. */
2458 if (GET_CODE (XEXP (x, 0)) == REG
2459 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2460 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2461 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2463 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2466 /* Refs inside notes don't count for this purpose. */
2467 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2468 || GET_CODE (insn) == INSN_LIST)))
2469 ep->ref_outside_mem = 1;
2472 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2473 ep->previous_offset * INTVAL (XEXP (x, 1)));
2476 /* ... fall through ... */
2480 /* See comments before PLUS about handling MINUS. */
2482 case DIV: case UDIV:
2483 case MOD: case UMOD:
2484 case AND: case IOR: case XOR:
2485 case ROTATERT: case ROTATE:
2486 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2488 case GE: case GT: case GEU: case GTU:
2489 case LE: case LT: case LEU: case LTU:
2491 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2493 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2495 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2496 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2501 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2504 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2505 if (new != XEXP (x, 0))
2507 /* If this is a REG_DEAD note, it is not valid anymore.
2508 Using the eliminated version could result in creating a
2509 REG_DEAD note for the stack or frame pointer. */
2510 if (GET_MODE (x) == REG_DEAD)
2512 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2515 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2519 /* ... fall through ... */
2522 /* Now do eliminations in the rest of the chain. If this was
2523 an EXPR_LIST, this might result in allocating more memory than is
2524 strictly needed, but it simplifies the code. */
2527 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2528 if (new != XEXP (x, 1))
2530 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2538 case STRICT_LOW_PART:
2540 case SIGN_EXTEND: case ZERO_EXTEND:
2541 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2542 case FLOAT: case FIX:
2543 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2547 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2548 if (new != XEXP (x, 0))
2549 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2553 /* Similar to above processing, but preserve SUBREG_BYTE.
2554 Convert (subreg (mem)) to (mem) if not paradoxical.
2555 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2556 pseudo didn't get a hard reg, we must replace this with the
2557 eliminated version of the memory location because push_reloads
2558 may do the replacement in certain circumstances. */
2559 if (GET_CODE (SUBREG_REG (x)) == REG
2560 && (GET_MODE_SIZE (GET_MODE (x))
2561 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2562 && reg_equiv_memory_loc != 0
2563 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2565 new = SUBREG_REG (x);
2568 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2570 if (new != SUBREG_REG (x))
2572 int x_size = GET_MODE_SIZE (GET_MODE (x));
2573 int new_size = GET_MODE_SIZE (GET_MODE (new));
2575 if (GET_CODE (new) == MEM
2576 && ((x_size < new_size
2577 #ifdef WORD_REGISTER_OPERATIONS
2578 /* On these machines, combine can create rtl of the form
2579 (set (subreg:m1 (reg:m2 R) 0) ...)
2580 where m1 < m2, and expects something interesting to
2581 happen to the entire word. Moreover, it will use the
2582 (reg:m2 R) later, expecting all bits to be preserved.
2583 So if the number of words is the same, preserve the
2584 subreg so that push_reloads can see it. */
2585 && ! ((x_size - 1) / UNITS_PER_WORD
2586 == (new_size -1 ) / UNITS_PER_WORD)
2589 || x_size == new_size)
2591 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2593 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2599 /* This is only for the benefit of the debugging backends, which call
2600 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2601 removed after CSE. */
2602 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2603 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2605 /* Our only special processing is to pass the mode of the MEM to our
2606 recursive call and copy the flags. While we are here, handle this
2607 case more efficiently. */
2609 replace_equiv_address_nv (x,
2610 eliminate_regs (XEXP (x, 0),
2611 GET_MODE (x), insn));
2614 /* Handle insn_list USE that a call to a pure function may generate. */
2615 new = eliminate_regs (XEXP (x, 0), 0, insn);
2616 if (new != XEXP (x, 0))
2617 return gen_rtx_USE (GET_MODE (x), new);
2629 /* Process each of our operands recursively. If any have changed, make a
2631 fmt = GET_RTX_FORMAT (code);
2632 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2636 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2637 if (new != XEXP (x, i) && ! copied)
2639 rtx new_x = rtx_alloc (code);
2641 (sizeof (*new_x) - sizeof (new_x->fld)
2642 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2648 else if (*fmt == 'E')
2651 for (j = 0; j < XVECLEN (x, i); j++)
2653 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2654 if (new != XVECEXP (x, i, j) && ! copied_vec)
2656 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2660 rtx new_x = rtx_alloc (code);
2662 (sizeof (*new_x) - sizeof (new_x->fld)
2663 + (sizeof (new_x->fld[0])
2664 * GET_RTX_LENGTH (code))));
2668 XVEC (x, i) = new_v;
2671 XVECEXP (x, i, j) = new;
2679 /* Scan rtx X for modifications of elimination target registers. Update
2680 the table of eliminables to reflect the changed state. MEM_MODE is
2681 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2684 elimination_effects (x, mem_mode)
2686 enum machine_mode mem_mode;
2689 enum rtx_code code = GET_CODE (x);
2690 struct elim_table *ep;
2717 /* First handle the case where we encounter a bare register that
2718 is eliminable. Replace it with a PLUS. */
2719 if (regno < FIRST_PSEUDO_REGISTER)
2721 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2723 if (ep->from_rtx == x && ep->can_eliminate)
2726 ep->ref_outside_mem = 1;
2731 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2732 && reg_equiv_constant[regno]
2733 && ! function_invariant_p (reg_equiv_constant[regno]))
2734 elimination_effects (reg_equiv_constant[regno], mem_mode);
2743 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2744 if (ep->to_rtx == XEXP (x, 0))
2746 int size = GET_MODE_SIZE (mem_mode);
2748 /* If more bytes than MEM_MODE are pushed, account for them. */
2749 #ifdef PUSH_ROUNDING
2750 if (ep->to_rtx == stack_pointer_rtx)
2751 size = PUSH_ROUNDING (size);
2753 if (code == PRE_DEC || code == POST_DEC)
2755 else if (code == PRE_INC || code == POST_INC)
2757 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2758 && GET_CODE (XEXP (x, 1)) == PLUS
2759 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2760 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2761 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2764 /* These two aren't unary operators. */
2765 if (code == POST_MODIFY || code == PRE_MODIFY)
2768 /* Fall through to generic unary operation case. */
2769 case STRICT_LOW_PART:
2771 case SIGN_EXTEND: case ZERO_EXTEND:
2772 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2773 case FLOAT: case FIX:
2774 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2778 elimination_effects (XEXP (x, 0), mem_mode);
2782 if (GET_CODE (SUBREG_REG (x)) == REG
2783 && (GET_MODE_SIZE (GET_MODE (x))
2784 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2785 && reg_equiv_memory_loc != 0
2786 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2789 elimination_effects (SUBREG_REG (x), mem_mode);
2793 /* If using a register that is the source of an eliminate we still
2794 think can be performed, note it cannot be performed since we don't
2795 know how this register is used. */
2796 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2797 if (ep->from_rtx == XEXP (x, 0))
2798 ep->can_eliminate = 0;
2800 elimination_effects (XEXP (x, 0), mem_mode);
2804 /* If clobbering a register that is the replacement register for an
2805 elimination we still think can be performed, note that it cannot
2806 be performed. Otherwise, we need not be concerned about it. */
2807 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2808 if (ep->to_rtx == XEXP (x, 0))
2809 ep->can_eliminate = 0;
2811 elimination_effects (XEXP (x, 0), mem_mode);
2815 /* Check for setting a register that we know about. */
2816 if (GET_CODE (SET_DEST (x)) == REG)
2818 /* See if this is setting the replacement register for an
2821 If DEST is the hard frame pointer, we do nothing because we
2822 assume that all assignments to the frame pointer are for
2823 non-local gotos and are being done at a time when they are valid
2824 and do not disturb anything else. Some machines want to
2825 eliminate a fake argument pointer (or even a fake frame pointer)
2826 with either the real frame or the stack pointer. Assignments to
2827 the hard frame pointer must not prevent this elimination. */
2829 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2831 if (ep->to_rtx == SET_DEST (x)
2832 && SET_DEST (x) != hard_frame_pointer_rtx)
2834 /* If it is being incremented, adjust the offset. Otherwise,
2835 this elimination can't be done. */
2836 rtx src = SET_SRC (x);
2838 if (GET_CODE (src) == PLUS
2839 && XEXP (src, 0) == SET_DEST (x)
2840 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2841 ep->offset -= INTVAL (XEXP (src, 1));
2843 ep->can_eliminate = 0;
2847 elimination_effects (SET_DEST (x), 0);
2848 elimination_effects (SET_SRC (x), 0);
2852 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2855 /* Our only special processing is to pass the mode of the MEM to our
2857 elimination_effects (XEXP (x, 0), GET_MODE (x));
2864 fmt = GET_RTX_FORMAT (code);
2865 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2868 elimination_effects (XEXP (x, i), mem_mode);
2869 else if (*fmt == 'E')
2870 for (j = 0; j < XVECLEN (x, i); j++)
2871 elimination_effects (XVECEXP (x, i, j), mem_mode);
2875 /* Descend through rtx X and verify that no references to eliminable registers
2876 remain. If any do remain, mark the involved register as not
2880 check_eliminable_occurrences (x)
2890 code = GET_CODE (x);
2892 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2894 struct elim_table *ep;
2896 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2897 if (ep->from_rtx == x && ep->can_eliminate)
2898 ep->can_eliminate = 0;
2902 fmt = GET_RTX_FORMAT (code);
2903 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2906 check_eliminable_occurrences (XEXP (x, i));
2907 else if (*fmt == 'E')
2910 for (j = 0; j < XVECLEN (x, i); j++)
2911 check_eliminable_occurrences (XVECEXP (x, i, j));
2916 /* Scan INSN and eliminate all eliminable registers in it.
2918 If REPLACE is nonzero, do the replacement destructively. Also
2919 delete the insn as dead it if it is setting an eliminable register.
2921 If REPLACE is zero, do all our allocations in reload_obstack.
2923 If no eliminations were done and this insn doesn't require any elimination
2924 processing (these are not identical conditions: it might be updating sp,
2925 but not referencing fp; this needs to be seen during reload_as_needed so
2926 that the offset between fp and sp can be taken into consideration), zero
2927 is returned. Otherwise, 1 is returned. */
2930 eliminate_regs_in_insn (insn, replace)
2934 int icode = recog_memoized (insn);
2935 rtx old_body = PATTERN (insn);
2936 int insn_is_asm = asm_noperands (old_body) >= 0;
2937 rtx old_set = single_set (insn);
2941 rtx substed_operand[MAX_RECOG_OPERANDS];
2942 rtx orig_operand[MAX_RECOG_OPERANDS];
2943 struct elim_table *ep;
2945 if (! insn_is_asm && icode < 0)
2947 if (GET_CODE (PATTERN (insn)) == USE
2948 || GET_CODE (PATTERN (insn)) == CLOBBER
2949 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2950 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2951 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2956 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2957 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2959 /* Check for setting an eliminable register. */
2960 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2961 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2963 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2964 /* If this is setting the frame pointer register to the
2965 hardware frame pointer register and this is an elimination
2966 that will be done (tested above), this insn is really
2967 adjusting the frame pointer downward to compensate for
2968 the adjustment done before a nonlocal goto. */
2969 if (ep->from == FRAME_POINTER_REGNUM
2970 && ep->to == HARD_FRAME_POINTER_REGNUM)
2972 rtx base = SET_SRC (old_set);
2973 rtx base_insn = insn;
2976 while (base != ep->to_rtx)
2978 rtx prev_insn, prev_set;
2980 if (GET_CODE (base) == PLUS
2981 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2983 offset += INTVAL (XEXP (base, 1));
2984 base = XEXP (base, 0);
2986 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2987 && (prev_set = single_set (prev_insn)) != 0
2988 && rtx_equal_p (SET_DEST (prev_set), base))
2990 base = SET_SRC (prev_set);
2991 base_insn = prev_insn;
2997 if (base == ep->to_rtx)
3000 = plus_constant (ep->to_rtx, offset - ep->offset);
3002 new_body = old_body;
3005 new_body = copy_insn (old_body);
3006 if (REG_NOTES (insn))
3007 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3009 PATTERN (insn) = new_body;
3010 old_set = single_set (insn);
3012 /* First see if this insn remains valid when we
3013 make the change. If not, keep the INSN_CODE
3014 the same and let reload fit it up. */
3015 validate_change (insn, &SET_SRC (old_set), src, 1);
3016 validate_change (insn, &SET_DEST (old_set),
3018 if (! apply_change_group ())
3020 SET_SRC (old_set) = src;
3021 SET_DEST (old_set) = ep->to_rtx;
3030 /* In this case this insn isn't serving a useful purpose. We
3031 will delete it in reload_as_needed once we know that this
3032 elimination is, in fact, being done.
3034 If REPLACE isn't set, we can't delete this insn, but needn't
3035 process it since it won't be used unless something changes. */
3038 delete_dead_insn (insn);
3046 /* We allow one special case which happens to work on all machines we
3047 currently support: a single set with the source being a PLUS of an
3048 eliminable register and a constant. */
3050 && GET_CODE (SET_DEST (old_set)) == REG
3051 && GET_CODE (SET_SRC (old_set)) == PLUS
3052 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3053 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
3054 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
3056 rtx reg = XEXP (SET_SRC (old_set), 0);
3057 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
3059 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3060 if (ep->from_rtx == reg && ep->can_eliminate)
3062 offset += ep->offset;
3067 /* We assume here that if we need a PARALLEL with
3068 CLOBBERs for this assignment, we can do with the
3069 MATCH_SCRATCHes that add_clobbers allocates.
3070 There's not much we can do if that doesn't work. */
3071 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3075 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3078 rtvec vec = rtvec_alloc (num_clobbers + 1);
3080 vec->elem[0] = PATTERN (insn);
3081 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3082 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3084 if (INSN_CODE (insn) < 0)
3089 new_body = old_body;
3092 new_body = copy_insn (old_body);
3093 if (REG_NOTES (insn))
3094 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3096 PATTERN (insn) = new_body;
3097 old_set = single_set (insn);
3099 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3100 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3103 /* This can't have an effect on elimination offsets, so skip right
3109 /* Determine the effects of this insn on elimination offsets. */
3110 elimination_effects (old_body, 0);
3112 /* Eliminate all eliminable registers occurring in operands that
3113 can be handled by reload. */
3114 extract_insn (insn);
3115 for (i = 0; i < recog_data.n_operands; i++)
3117 orig_operand[i] = recog_data.operand[i];
3118 substed_operand[i] = recog_data.operand[i];
3120 /* For an asm statement, every operand is eliminable. */
3121 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3123 /* Check for setting a register that we know about. */
3124 if (recog_data.operand_type[i] != OP_IN
3125 && GET_CODE (orig_operand[i]) == REG)
3127 /* If we are assigning to a register that can be eliminated, it
3128 must be as part of a PARALLEL, since the code above handles
3129 single SETs. We must indicate that we can no longer
3130 eliminate this reg. */
3131 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3133 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3134 ep->can_eliminate = 0;
3137 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3138 replace ? insn : NULL_RTX);
3139 if (substed_operand[i] != orig_operand[i])
3141 /* Terminate the search in check_eliminable_occurrences at
3143 *recog_data.operand_loc[i] = 0;
3145 /* If an output operand changed from a REG to a MEM and INSN is an
3146 insn, write a CLOBBER insn. */
3147 if (recog_data.operand_type[i] != OP_IN
3148 && GET_CODE (orig_operand[i]) == REG
3149 && GET_CODE (substed_operand[i]) == MEM
3151 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3156 for (i = 0; i < recog_data.n_dups; i++)
3157 *recog_data.dup_loc[i]
3158 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3160 /* If any eliminable remain, they aren't eliminable anymore. */
3161 check_eliminable_occurrences (old_body);
3163 /* Substitute the operands; the new values are in the substed_operand
3165 for (i = 0; i < recog_data.n_operands; i++)
3166 *recog_data.operand_loc[i] = substed_operand[i];
3167 for (i = 0; i < recog_data.n_dups; i++)
3168 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3170 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3171 re-recognize the insn. We do this in case we had a simple addition
3172 but now can do this as a load-address. This saves an insn in this
3174 If re-recognition fails, the old insn code number will still be used,
3175 and some register operands may have changed into PLUS expressions.
3176 These will be handled by find_reloads by loading them into a register
3181 /* If we aren't replacing things permanently and we changed something,
3182 make another copy to ensure that all the RTL is new. Otherwise
3183 things can go wrong if find_reload swaps commutative operands
3184 and one is inside RTL that has been copied while the other is not. */
3185 new_body = old_body;
3188 new_body = copy_insn (old_body);
3189 if (REG_NOTES (insn))
3190 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3192 PATTERN (insn) = new_body;
3194 /* If we had a move insn but now we don't, rerecognize it. This will
3195 cause spurious re-recognition if the old move had a PARALLEL since
3196 the new one still will, but we can't call single_set without
3197 having put NEW_BODY into the insn and the re-recognition won't
3198 hurt in this rare case. */
3199 /* ??? Why this huge if statement - why don't we just rerecognize the
3203 && ((GET_CODE (SET_SRC (old_set)) == REG
3204 && (GET_CODE (new_body) != SET
3205 || GET_CODE (SET_SRC (new_body)) != REG))
3206 /* If this was a load from or store to memory, compare
3207 the MEM in recog_data.operand to the one in the insn.
3208 If they are not equal, then rerecognize the insn. */
3210 && ((GET_CODE (SET_SRC (old_set)) == MEM
3211 && SET_SRC (old_set) != recog_data.operand[1])
3212 || (GET_CODE (SET_DEST (old_set)) == MEM
3213 && SET_DEST (old_set) != recog_data.operand[0])))
3214 /* If this was an add insn before, rerecognize. */
3215 || GET_CODE (SET_SRC (old_set)) == PLUS))
3217 int new_icode = recog (PATTERN (insn), insn, 0);
3219 INSN_CODE (insn) = icode;
3223 /* Restore the old body. If there were any changes to it, we made a copy
3224 of it while the changes were still in place, so we'll correctly return
3225 a modified insn below. */
3228 /* Restore the old body. */
3229 for (i = 0; i < recog_data.n_operands; i++)
3230 *recog_data.operand_loc[i] = orig_operand[i];
3231 for (i = 0; i < recog_data.n_dups; i++)
3232 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3235 /* Update all elimination pairs to reflect the status after the current
3236 insn. The changes we make were determined by the earlier call to
3237 elimination_effects.
3239 We also detect cases where register elimination cannot be done,
3240 namely, if a register would be both changed and referenced outside a MEM
3241 in the resulting insn since such an insn is often undefined and, even if
3242 not, we cannot know what meaning will be given to it. Note that it is
3243 valid to have a register used in an address in an insn that changes it
3244 (presumably with a pre- or post-increment or decrement).
3246 If anything changes, return nonzero. */
3248 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3250 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3251 ep->can_eliminate = 0;
3253 ep->ref_outside_mem = 0;
3255 if (ep->previous_offset != ep->offset)
3260 /* If we changed something, perform elimination in REG_NOTES. This is
3261 needed even when REPLACE is zero because a REG_DEAD note might refer
3262 to a register that we eliminate and could cause a different number
3263 of spill registers to be needed in the final reload pass than in
3265 if (val && REG_NOTES (insn) != 0)
3266 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3271 /* Loop through all elimination pairs.
3272 Recalculate the number not at initial offset.
3274 Compute the maximum offset (minimum offset if the stack does not
3275 grow downward) for each elimination pair. */
3278 update_eliminable_offsets ()
3280 struct elim_table *ep;
3282 num_not_at_initial_offset = 0;
3283 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3285 ep->previous_offset = ep->offset;
3286 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3287 num_not_at_initial_offset++;
3291 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3292 replacement we currently believe is valid, mark it as not eliminable if X
3293 modifies DEST in any way other than by adding a constant integer to it.
3295 If DEST is the frame pointer, we do nothing because we assume that
3296 all assignments to the hard frame pointer are nonlocal gotos and are being
3297 done at a time when they are valid and do not disturb anything else.
3298 Some machines want to eliminate a fake argument pointer with either the
3299 frame or stack pointer. Assignments to the hard frame pointer must not
3300 prevent this elimination.
3302 Called via note_stores from reload before starting its passes to scan
3303 the insns of the function. */
3306 mark_not_eliminable (dest, x, data)
3309 void *data ATTRIBUTE_UNUSED;
3313 /* A SUBREG of a hard register here is just changing its mode. We should
3314 not see a SUBREG of an eliminable hard register, but check just in
3316 if (GET_CODE (dest) == SUBREG)
3317 dest = SUBREG_REG (dest);
3319 if (dest == hard_frame_pointer_rtx)
3322 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3323 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3324 && (GET_CODE (x) != SET
3325 || GET_CODE (SET_SRC (x)) != PLUS
3326 || XEXP (SET_SRC (x), 0) != dest
3327 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3329 reg_eliminate[i].can_eliminate_previous
3330 = reg_eliminate[i].can_eliminate = 0;
3335 /* Verify that the initial elimination offsets did not change since the
3336 last call to set_initial_elim_offsets. This is used to catch cases
3337 where something illegal happened during reload_as_needed that could
3338 cause incorrect code to be generated if we did not check for it. */
3341 verify_initial_elim_offsets ()
3345 #ifdef ELIMINABLE_REGS
3346 struct elim_table *ep;
3348 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3350 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3351 if (t != ep->initial_offset)
3355 INITIAL_FRAME_POINTER_OFFSET (t);
3356 if (t != reg_eliminate[0].initial_offset)
3361 /* Reset all offsets on eliminable registers to their initial values. */
3364 set_initial_elim_offsets ()
3366 struct elim_table *ep = reg_eliminate;
3368 #ifdef ELIMINABLE_REGS
3369 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3371 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3372 ep->previous_offset = ep->offset = ep->initial_offset;
3375 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3376 ep->previous_offset = ep->offset = ep->initial_offset;
3379 num_not_at_initial_offset = 0;
3382 /* Initialize the known label offsets.
3383 Set a known offset for each forced label to be at the initial offset
3384 of each elimination. We do this because we assume that all
3385 computed jumps occur from a location where each elimination is
3386 at its initial offset.
3387 For all other labels, show that we don't know the offsets. */
3390 set_initial_label_offsets ()
3393 memset ((char *) &offsets_known_at[get_first_label_num ()], 0, num_labels);
3395 for (x = forced_labels; x; x = XEXP (x, 1))
3397 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3400 /* Set all elimination offsets to the known values for the code label given
3404 set_offsets_for_label (insn)
3408 int label_nr = CODE_LABEL_NUMBER (insn);
3409 struct elim_table *ep;
3411 num_not_at_initial_offset = 0;
3412 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3414 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3415 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3416 num_not_at_initial_offset++;
3420 /* See if anything that happened changes which eliminations are valid.
3421 For example, on the SPARC, whether or not the frame pointer can
3422 be eliminated can depend on what registers have been used. We need
3423 not check some conditions again (such as flag_omit_frame_pointer)
3424 since they can't have changed. */
3427 update_eliminables (pset)
3430 int previous_frame_pointer_needed = frame_pointer_needed;
3431 struct elim_table *ep;
3433 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3434 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3435 #ifdef ELIMINABLE_REGS
3436 || ! CAN_ELIMINATE (ep->from, ep->to)
3439 ep->can_eliminate = 0;
3441 /* Look for the case where we have discovered that we can't replace
3442 register A with register B and that means that we will now be
3443 trying to replace register A with register C. This means we can
3444 no longer replace register C with register B and we need to disable
3445 such an elimination, if it exists. This occurs often with A == ap,
3446 B == sp, and C == fp. */
3448 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3450 struct elim_table *op;
3453 if (! ep->can_eliminate && ep->can_eliminate_previous)
3455 /* Find the current elimination for ep->from, if there is a
3457 for (op = reg_eliminate;
3458 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3459 if (op->from == ep->from && op->can_eliminate)
3465 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3467 for (op = reg_eliminate;
3468 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3469 if (op->from == new_to && op->to == ep->to)
3470 op->can_eliminate = 0;
3474 /* See if any registers that we thought we could eliminate the previous
3475 time are no longer eliminable. If so, something has changed and we
3476 must spill the register. Also, recompute the number of eliminable
3477 registers and see if the frame pointer is needed; it is if there is
3478 no elimination of the frame pointer that we can perform. */
3480 frame_pointer_needed = 1;
3481 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3483 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3484 && ep->to != HARD_FRAME_POINTER_REGNUM)
3485 frame_pointer_needed = 0;
3487 if (! ep->can_eliminate && ep->can_eliminate_previous)
3489 ep->can_eliminate_previous = 0;
3490 SET_HARD_REG_BIT (*pset, ep->from);
3495 /* If we didn't need a frame pointer last time, but we do now, spill
3496 the hard frame pointer. */
3497 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3498 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3501 /* Initialize the table of registers to eliminate. */
3506 struct elim_table *ep;
3507 #ifdef ELIMINABLE_REGS
3508 const struct elim_table_1 *ep1;
3512 reg_eliminate = (struct elim_table *)
3513 xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3515 /* Does this function require a frame pointer? */
3517 frame_pointer_needed = (! flag_omit_frame_pointer
3518 #ifdef EXIT_IGNORE_STACK
3519 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3520 and restore sp for alloca. So we can't eliminate
3521 the frame pointer in that case. At some point,
3522 we should improve this by emitting the
3523 sp-adjusting insns for this case. */
3524 || (current_function_calls_alloca
3525 && EXIT_IGNORE_STACK)
3527 || FRAME_POINTER_REQUIRED);
3531 #ifdef ELIMINABLE_REGS
3532 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3533 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3535 ep->from = ep1->from;
3537 ep->can_eliminate = ep->can_eliminate_previous
3538 = (CAN_ELIMINATE (ep->from, ep->to)
3539 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3542 reg_eliminate[0].from = reg_eliminate_1[0].from;
3543 reg_eliminate[0].to = reg_eliminate_1[0].to;
3544 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3545 = ! frame_pointer_needed;
3548 /* Count the number of eliminable registers and build the FROM and TO
3549 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3550 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3551 We depend on this. */
3552 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3554 num_eliminable += ep->can_eliminate;
3555 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3556 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3560 /* Kick all pseudos out of hard register REGNO.
3562 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3563 because we found we can't eliminate some register. In the case, no pseudos
3564 are allowed to be in the register, even if they are only in a block that
3565 doesn't require spill registers, unlike the case when we are spilling this
3566 hard reg to produce another spill register.
3568 Return nonzero if any pseudos needed to be kicked out. */
3571 spill_hard_reg (regno, cant_eliminate)
3579 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3580 regs_ever_live[regno] = 1;
3583 /* Spill every pseudo reg that was allocated to this reg
3584 or to something that overlaps this reg. */
3586 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3587 if (reg_renumber[i] >= 0
3588 && (unsigned int) reg_renumber[i] <= regno
3589 && ((unsigned int) reg_renumber[i]
3590 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3591 PSEUDO_REGNO_MODE (i))
3593 SET_REGNO_REG_SET (&spilled_pseudos, i);
3596 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3597 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3600 ior_hard_reg_set (set1, set2)
3601 HARD_REG_SET *set1, *set2;
3603 IOR_HARD_REG_SET (*set1, *set2);
3606 /* After find_reload_regs has been run for all insn that need reloads,
3607 and/or spill_hard_regs was called, this function is used to actually
3608 spill pseudo registers and try to reallocate them. It also sets up the
3609 spill_regs array for use by choose_reload_regs. */
3612 finish_spills (global)
3615 struct insn_chain *chain;
3616 int something_changed = 0;
3619 /* Build the spill_regs array for the function. */
3620 /* If there are some registers still to eliminate and one of the spill regs
3621 wasn't ever used before, additional stack space may have to be
3622 allocated to store this register. Thus, we may have changed the offset
3623 between the stack and frame pointers, so mark that something has changed.
3625 One might think that we need only set VAL to 1 if this is a call-used
3626 register. However, the set of registers that must be saved by the
3627 prologue is not identical to the call-used set. For example, the
3628 register used by the call insn for the return PC is a call-used register,
3629 but must be saved by the prologue. */
3632 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3633 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3635 spill_reg_order[i] = n_spills;
3636 spill_regs[n_spills++] = i;
3637 if (num_eliminable && ! regs_ever_live[i])
3638 something_changed = 1;
3639 regs_ever_live[i] = 1;
3642 spill_reg_order[i] = -1;
3644 EXECUTE_IF_SET_IN_REG_SET
3645 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3647 /* Record the current hard register the pseudo is allocated to in
3648 pseudo_previous_regs so we avoid reallocating it to the same
3649 hard reg in a later pass. */
3650 if (reg_renumber[i] < 0)
3653 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3654 /* Mark it as no longer having a hard register home. */
3655 reg_renumber[i] = -1;
3656 /* We will need to scan everything again. */
3657 something_changed = 1;
3660 /* Retry global register allocation if possible. */
3663 memset ((char *) pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3664 /* For every insn that needs reloads, set the registers used as spill
3665 regs in pseudo_forbidden_regs for every pseudo live across the
3667 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3669 EXECUTE_IF_SET_IN_REG_SET
3670 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3672 ior_hard_reg_set (pseudo_forbidden_regs + i,
3673 &chain->used_spill_regs);
3675 EXECUTE_IF_SET_IN_REG_SET
3676 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3678 ior_hard_reg_set (pseudo_forbidden_regs + i,
3679 &chain->used_spill_regs);
3683 /* Retry allocating the spilled pseudos. For each reg, merge the
3684 various reg sets that indicate which hard regs can't be used,
3685 and call retry_global_alloc.
3686 We change spill_pseudos here to only contain pseudos that did not
3687 get a new hard register. */
3688 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3689 if (reg_old_renumber[i] != reg_renumber[i])
3691 HARD_REG_SET forbidden;
3692 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3693 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3694 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3695 retry_global_alloc (i, forbidden);
3696 if (reg_renumber[i] >= 0)
3697 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3701 /* Fix up the register information in the insn chain.
3702 This involves deleting those of the spilled pseudos which did not get
3703 a new hard register home from the live_{before,after} sets. */
3704 for (chain = reload_insn_chain; chain; chain = chain->next)
3706 HARD_REG_SET used_by_pseudos;
3707 HARD_REG_SET used_by_pseudos2;
3709 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3710 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3712 /* Mark any unallocated hard regs as available for spills. That
3713 makes inheritance work somewhat better. */
3714 if (chain->need_reload)
3716 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3717 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3718 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3720 /* Save the old value for the sanity test below. */
3721 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3723 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3724 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3725 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3726 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3728 /* Make sure we only enlarge the set. */
3729 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3735 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3736 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3738 int regno = reg_renumber[i];
3739 if (reg_old_renumber[i] == regno)
3742 alter_reg (i, reg_old_renumber[i]);
3743 reg_old_renumber[i] = regno;
3747 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3749 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3750 i, reg_renumber[i]);
3754 return something_changed;
3757 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3758 Also mark any hard registers used to store user variables as
3759 forbidden from being used for spill registers. */
3762 scan_paradoxical_subregs (x)
3767 enum rtx_code code = GET_CODE (x);
3773 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3774 && REG_USERVAR_P (x))
3775 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3784 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3792 if (GET_CODE (SUBREG_REG (x)) == REG
3793 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3794 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3795 = GET_MODE_SIZE (GET_MODE (x));
3802 fmt = GET_RTX_FORMAT (code);
3803 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3806 scan_paradoxical_subregs (XEXP (x, i));
3807 else if (fmt[i] == 'E')
3810 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3811 scan_paradoxical_subregs (XVECEXP (x, i, j));
3816 /* Reload pseudo-registers into hard regs around each insn as needed.
3817 Additional register load insns are output before the insn that needs it
3818 and perhaps store insns after insns that modify the reloaded pseudo reg.
3820 reg_last_reload_reg and reg_reloaded_contents keep track of
3821 which registers are already available in reload registers.
3822 We update these for the reloads that we perform,
3823 as the insns are scanned. */
3826 reload_as_needed (live_known)
3829 struct insn_chain *chain;
3830 #if defined (AUTO_INC_DEC)
3835 memset ((char *) spill_reg_rtx, 0, sizeof spill_reg_rtx);
3836 memset ((char *) spill_reg_store, 0, sizeof spill_reg_store);
3837 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3838 reg_has_output_reload = (char *) xmalloc (max_regno);
3839 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3841 set_initial_elim_offsets ();
3843 for (chain = reload_insn_chain; chain; chain = chain->next)
3846 rtx insn = chain->insn;
3847 rtx old_next = NEXT_INSN (insn);
3849 /* If we pass a label, copy the offsets from the label information
3850 into the current offsets of each elimination. */
3851 if (GET_CODE (insn) == CODE_LABEL)
3852 set_offsets_for_label (insn);
3854 else if (INSN_P (insn))
3856 rtx oldpat = copy_rtx (PATTERN (insn));
3858 /* If this is a USE and CLOBBER of a MEM, ensure that any
3859 references to eliminable registers have been removed. */
3861 if ((GET_CODE (PATTERN (insn)) == USE
3862 || GET_CODE (PATTERN (insn)) == CLOBBER)
3863 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3864 XEXP (XEXP (PATTERN (insn), 0), 0)
3865 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3866 GET_MODE (XEXP (PATTERN (insn), 0)),
3869 /* If we need to do register elimination processing, do so.
3870 This might delete the insn, in which case we are done. */
3871 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3873 eliminate_regs_in_insn (insn, 1);
3874 if (GET_CODE (insn) == NOTE)
3876 update_eliminable_offsets ();
3881 /* If need_elim is nonzero but need_reload is zero, one might think
3882 that we could simply set n_reloads to 0. However, find_reloads
3883 could have done some manipulation of the insn (such as swapping
3884 commutative operands), and these manipulations are lost during
3885 the first pass for every insn that needs register elimination.
3886 So the actions of find_reloads must be redone here. */
3888 if (! chain->need_elim && ! chain->need_reload
3889 && ! chain->need_operand_change)
3891 /* First find the pseudo regs that must be reloaded for this insn.
3892 This info is returned in the tables reload_... (see reload.h).
3893 Also modify the body of INSN by substituting RELOAD
3894 rtx's for those pseudo regs. */
3897 memset (reg_has_output_reload, 0, max_regno);
3898 CLEAR_HARD_REG_SET (reg_is_output_reload);
3900 find_reloads (insn, 1, spill_indirect_levels, live_known,
3906 rtx next = NEXT_INSN (insn);
3909 prev = PREV_INSN (insn);
3911 /* Now compute which reload regs to reload them into. Perhaps
3912 reusing reload regs from previous insns, or else output
3913 load insns to reload them. Maybe output store insns too.
3914 Record the choices of reload reg in reload_reg_rtx. */
3915 choose_reload_regs (chain);
3917 /* Merge any reloads that we didn't combine for fear of
3918 increasing the number of spill registers needed but now
3919 discover can be safely merged. */
3920 if (SMALL_REGISTER_CLASSES)
3921 merge_assigned_reloads (insn);
3923 /* Generate the insns to reload operands into or out of
3924 their reload regs. */
3925 emit_reload_insns (chain);
3927 /* Substitute the chosen reload regs from reload_reg_rtx
3928 into the insn's body (or perhaps into the bodies of other
3929 load and store insn that we just made for reloading
3930 and that we moved the structure into). */
3931 subst_reloads (insn);
3933 /* If this was an ASM, make sure that all the reload insns
3934 we have generated are valid. If not, give an error
3937 if (asm_noperands (PATTERN (insn)) >= 0)
3938 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3939 if (p != insn && INSN_P (p)
3940 && (recog_memoized (p) < 0
3941 || (extract_insn (p), ! constrain_operands (1))))
3943 error_for_asm (insn,
3944 "`asm' operand requires impossible reload");
3949 if (num_eliminable && chain->need_elim)
3950 update_eliminable_offsets ();
3952 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3953 is no longer validly lying around to save a future reload.
3954 Note that this does not detect pseudos that were reloaded
3955 for this insn in order to be stored in
3956 (obeying register constraints). That is correct; such reload
3957 registers ARE still valid. */
3958 note_stores (oldpat, forget_old_reloads_1, NULL);
3960 /* There may have been CLOBBER insns placed after INSN. So scan
3961 between INSN and NEXT and use them to forget old reloads. */
3962 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3963 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3964 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3967 /* Likewise for regs altered by auto-increment in this insn.
3968 REG_INC notes have been changed by reloading:
3969 find_reloads_address_1 records substitutions for them,
3970 which have been performed by subst_reloads above. */
3971 for (i = n_reloads - 1; i >= 0; i--)
3973 rtx in_reg = rld[i].in_reg;
3976 enum rtx_code code = GET_CODE (in_reg);
3977 /* PRE_INC / PRE_DEC will have the reload register ending up
3978 with the same value as the stack slot, but that doesn't
3979 hold true for POST_INC / POST_DEC. Either we have to
3980 convert the memory access to a true POST_INC / POST_DEC,
3981 or we can't use the reload register for inheritance. */
3982 if ((code == POST_INC || code == POST_DEC)
3983 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3984 REGNO (rld[i].reg_rtx))
3985 /* Make sure it is the inc/dec pseudo, and not
3986 some other (e.g. output operand) pseudo. */
3987 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3988 == REGNO (XEXP (in_reg, 0))))
3991 rtx reload_reg = rld[i].reg_rtx;
3992 enum machine_mode mode = GET_MODE (reload_reg);
3996 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3998 /* We really want to ignore REG_INC notes here, so
3999 use PATTERN (p) as argument to reg_set_p . */
4000 if (reg_set_p (reload_reg, PATTERN (p)))
4002 n = count_occurrences (PATTERN (p), reload_reg, 0);
4007 n = validate_replace_rtx (reload_reg,
4008 gen_rtx (code, mode,
4012 /* We must also verify that the constraints
4013 are met after the replacement. */
4016 n = constrain_operands (1);
4020 /* If the constraints were not met, then
4021 undo the replacement. */
4024 validate_replace_rtx (gen_rtx (code, mode,
4036 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4038 /* Mark this as having an output reload so that the
4039 REG_INC processing code below won't invalidate
4040 the reload for inheritance. */
4041 SET_HARD_REG_BIT (reg_is_output_reload,
4042 REGNO (reload_reg));
4043 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4046 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4049 else if ((code == PRE_INC || code == PRE_DEC)
4050 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4051 REGNO (rld[i].reg_rtx))
4052 /* Make sure it is the inc/dec pseudo, and not
4053 some other (e.g. output operand) pseudo. */
4054 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4055 == REGNO (XEXP (in_reg, 0))))
4057 SET_HARD_REG_BIT (reg_is_output_reload,
4058 REGNO (rld[i].reg_rtx));
4059 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4063 /* If a pseudo that got a hard register is auto-incremented,
4064 we must purge records of copying it into pseudos without
4066 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4067 if (REG_NOTE_KIND (x) == REG_INC)
4069 /* See if this pseudo reg was reloaded in this insn.
4070 If so, its last-reload info is still valid
4071 because it is based on this insn's reload. */
4072 for (i = 0; i < n_reloads; i++)
4073 if (rld[i].out == XEXP (x, 0))
4077 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4081 /* A reload reg's contents are unknown after a label. */
4082 if (GET_CODE (insn) == CODE_LABEL)
4083 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4085 /* Don't assume a reload reg is still good after a call insn
4086 if it is a call-used reg. */
4087 else if (GET_CODE (insn) == CALL_INSN)
4088 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4092 free (reg_last_reload_reg);
4093 free (reg_has_output_reload);
4096 /* Discard all record of any value reloaded from X,
4097 or reloaded in X from someplace else;
4098 unless X is an output reload reg of the current insn.
4100 X may be a hard reg (the reload reg)
4101 or it may be a pseudo reg that was reloaded from. */
4104 forget_old_reloads_1 (x, ignored, data)
4106 rtx ignored ATTRIBUTE_UNUSED;
4107 void *data ATTRIBUTE_UNUSED;
4112 /* note_stores does give us subregs of hard regs,
4113 subreg_regno_offset will abort if it is not a hard reg. */
4114 while (GET_CODE (x) == SUBREG)
4116 /* We ignore the subreg offset when calculating the regno,
4117 because we are using the entire underlying hard register
4122 if (GET_CODE (x) != REG)
4127 if (regno >= FIRST_PSEUDO_REGISTER)
4133 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4134 /* Storing into a spilled-reg invalidates its contents.
4135 This can happen if a block-local pseudo is allocated to that reg
4136 and it wasn't spilled because this block's total need is 0.
4137 Then some insn might have an optional reload and use this reg. */
4138 for (i = 0; i < nr; i++)
4139 /* But don't do this if the reg actually serves as an output
4140 reload reg in the current instruction. */
4142 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4144 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4145 spill_reg_store[regno + i] = 0;
4149 /* Since value of X has changed,
4150 forget any value previously copied from it. */
4153 /* But don't forget a copy if this is the output reload
4154 that establishes the copy's validity. */
4155 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4156 reg_last_reload_reg[regno + nr] = 0;
4159 /* The following HARD_REG_SETs indicate when each hard register is
4160 used for a reload of various parts of the current insn. */
4162 /* If reg is unavailable for all reloads. */
4163 static HARD_REG_SET reload_reg_unavailable;
4164 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4165 static HARD_REG_SET reload_reg_used;
4166 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4167 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4168 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4169 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4170 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4171 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4172 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4173 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4174 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4175 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4176 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4177 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4178 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4179 static HARD_REG_SET reload_reg_used_in_op_addr;
4180 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4181 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4182 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4183 static HARD_REG_SET reload_reg_used_in_insn;
4184 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4185 static HARD_REG_SET reload_reg_used_in_other_addr;
4187 /* If reg is in use as a reload reg for any sort of reload. */
4188 static HARD_REG_SET reload_reg_used_at_all;
4190 /* If reg is use as an inherited reload. We just mark the first register
4192 static HARD_REG_SET reload_reg_used_for_inherit;
4194 /* Records which hard regs are used in any way, either as explicit use or
4195 by being allocated to a pseudo during any point of the current insn. */
4196 static HARD_REG_SET reg_used_in_insn;
4198 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4199 TYPE. MODE is used to indicate how many consecutive regs are
4203 mark_reload_reg_in_use (regno, opnum, type, mode)
4206 enum reload_type type;
4207 enum machine_mode mode;
4209 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4212 for (i = regno; i < nregs + regno; i++)
4217 SET_HARD_REG_BIT (reload_reg_used, i);
4220 case RELOAD_FOR_INPUT_ADDRESS:
4221 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4224 case RELOAD_FOR_INPADDR_ADDRESS:
4225 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4228 case RELOAD_FOR_OUTPUT_ADDRESS:
4229 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4232 case RELOAD_FOR_OUTADDR_ADDRESS:
4233 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4236 case RELOAD_FOR_OPERAND_ADDRESS:
4237 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4240 case RELOAD_FOR_OPADDR_ADDR:
4241 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4244 case RELOAD_FOR_OTHER_ADDRESS:
4245 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4248 case RELOAD_FOR_INPUT:
4249 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4252 case RELOAD_FOR_OUTPUT:
4253 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4256 case RELOAD_FOR_INSN:
4257 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4261 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4265 /* Similarly, but show REGNO is no longer in use for a reload. */
4268 clear_reload_reg_in_use (regno, opnum, type, mode)
4271 enum reload_type type;
4272 enum machine_mode mode;
4274 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4275 unsigned int start_regno, end_regno, r;
4277 /* A complication is that for some reload types, inheritance might
4278 allow multiple reloads of the same types to share a reload register.
4279 We set check_opnum if we have to check only reloads with the same
4280 operand number, and check_any if we have to check all reloads. */
4281 int check_opnum = 0;
4283 HARD_REG_SET *used_in_set;
4288 used_in_set = &reload_reg_used;
4291 case RELOAD_FOR_INPUT_ADDRESS:
4292 used_in_set = &reload_reg_used_in_input_addr[opnum];
4295 case RELOAD_FOR_INPADDR_ADDRESS:
4297 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4300 case RELOAD_FOR_OUTPUT_ADDRESS:
4301 used_in_set = &reload_reg_used_in_output_addr[opnum];
4304 case RELOAD_FOR_OUTADDR_ADDRESS:
4306 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4309 case RELOAD_FOR_OPERAND_ADDRESS:
4310 used_in_set = &reload_reg_used_in_op_addr;
4313 case RELOAD_FOR_OPADDR_ADDR:
4315 used_in_set = &reload_reg_used_in_op_addr_reload;
4318 case RELOAD_FOR_OTHER_ADDRESS:
4319 used_in_set = &reload_reg_used_in_other_addr;
4323 case RELOAD_FOR_INPUT:
4324 used_in_set = &reload_reg_used_in_input[opnum];
4327 case RELOAD_FOR_OUTPUT:
4328 used_in_set = &reload_reg_used_in_output[opnum];
4331 case RELOAD_FOR_INSN:
4332 used_in_set = &reload_reg_used_in_insn;
4337 /* We resolve conflicts with remaining reloads of the same type by
4338 excluding the intervals of reload registers by them from the
4339 interval of freed reload registers. Since we only keep track of
4340 one set of interval bounds, we might have to exclude somewhat
4341 more than what would be necessary if we used a HARD_REG_SET here.
4342 But this should only happen very infrequently, so there should
4343 be no reason to worry about it. */
4345 start_regno = regno;
4346 end_regno = regno + nregs;
4347 if (check_opnum || check_any)
4349 for (i = n_reloads - 1; i >= 0; i--)
4351 if (rld[i].when_needed == type
4352 && (check_any || rld[i].opnum == opnum)
4355 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4356 unsigned int conflict_end
4358 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4360 /* If there is an overlap with the first to-be-freed register,
4361 adjust the interval start. */
4362 if (conflict_start <= start_regno && conflict_end > start_regno)
4363 start_regno = conflict_end;
4364 /* Otherwise, if there is a conflict with one of the other
4365 to-be-freed registers, adjust the interval end. */
4366 if (conflict_start > start_regno && conflict_start < end_regno)
4367 end_regno = conflict_start;
4372 for (r = start_regno; r < end_regno; r++)
4373 CLEAR_HARD_REG_BIT (*used_in_set, r);
4376 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4377 specified by OPNUM and TYPE. */
4380 reload_reg_free_p (regno, opnum, type)
4383 enum reload_type type;
4387 /* In use for a RELOAD_OTHER means it's not available for anything. */
4388 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4389 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4395 /* In use for anything means we can't use it for RELOAD_OTHER. */
4396 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4397 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4398 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4401 for (i = 0; i < reload_n_operands; i++)
4402 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4403 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4404 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4405 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4406 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4407 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4412 case RELOAD_FOR_INPUT:
4413 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4414 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4417 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4420 /* If it is used for some other input, can't use it. */
4421 for (i = 0; i < reload_n_operands; i++)
4422 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4425 /* If it is used in a later operand's address, can't use it. */
4426 for (i = opnum + 1; i < reload_n_operands; i++)
4427 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4428 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4433 case RELOAD_FOR_INPUT_ADDRESS:
4434 /* Can't use a register if it is used for an input address for this
4435 operand or used as an input in an earlier one. */
4436 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4437 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4440 for (i = 0; i < opnum; i++)
4441 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4446 case RELOAD_FOR_INPADDR_ADDRESS:
4447 /* Can't use a register if it is used for an input address
4448 for this operand or used as an input in an earlier
4450 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4453 for (i = 0; i < opnum; i++)
4454 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4459 case RELOAD_FOR_OUTPUT_ADDRESS:
4460 /* Can't use a register if it is used for an output address for this
4461 operand or used as an output in this or a later operand. Note
4462 that multiple output operands are emitted in reverse order, so
4463 the conflicting ones are those with lower indices. */
4464 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4467 for (i = 0; i <= opnum; i++)
4468 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4473 case RELOAD_FOR_OUTADDR_ADDRESS:
4474 /* Can't use a register if it is used for an output address
4475 for this operand or used as an output in this or a
4476 later operand. Note that multiple output operands are
4477 emitted in reverse order, so the conflicting ones are
4478 those with lower indices. */
4479 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4482 for (i = 0; i <= opnum; i++)
4483 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4488 case RELOAD_FOR_OPERAND_ADDRESS:
4489 for (i = 0; i < reload_n_operands; i++)
4490 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4493 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4494 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4496 case RELOAD_FOR_OPADDR_ADDR:
4497 for (i = 0; i < reload_n_operands; i++)
4498 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4501 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4503 case RELOAD_FOR_OUTPUT:
4504 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4505 outputs, or an operand address for this or an earlier output.
4506 Note that multiple output operands are emitted in reverse order,
4507 so the conflicting ones are those with higher indices. */
4508 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4511 for (i = 0; i < reload_n_operands; i++)
4512 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4515 for (i = opnum; i < reload_n_operands; i++)
4516 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4517 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4522 case RELOAD_FOR_INSN:
4523 for (i = 0; i < reload_n_operands; i++)
4524 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4525 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4528 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4529 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4531 case RELOAD_FOR_OTHER_ADDRESS:
4532 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4537 /* Return 1 if the value in reload reg REGNO, as used by a reload
4538 needed for the part of the insn specified by OPNUM and TYPE,
4539 is still available in REGNO at the end of the insn.
4541 We can assume that the reload reg was already tested for availability
4542 at the time it is needed, and we should not check this again,
4543 in case the reg has already been marked in use. */
4546 reload_reg_reaches_end_p (regno, opnum, type)
4549 enum reload_type type;
4556 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4557 its value must reach the end. */
4560 /* If this use is for part of the insn,
4561 its value reaches if no subsequent part uses the same register.
4562 Just like the above function, don't try to do this with lots
4565 case RELOAD_FOR_OTHER_ADDRESS:
4566 /* Here we check for everything else, since these don't conflict
4567 with anything else and everything comes later. */
4569 for (i = 0; i < reload_n_operands; i++)
4570 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4571 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4572 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4573 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4574 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4575 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4578 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4579 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4580 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4582 case RELOAD_FOR_INPUT_ADDRESS:
4583 case RELOAD_FOR_INPADDR_ADDRESS:
4584 /* Similar, except that we check only for this and subsequent inputs
4585 and the address of only subsequent inputs and we do not need
4586 to check for RELOAD_OTHER objects since they are known not to
4589 for (i = opnum; i < reload_n_operands; i++)
4590 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4593 for (i = opnum + 1; i < reload_n_operands; i++)
4594 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4595 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4598 for (i = 0; i < reload_n_operands; i++)
4599 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4600 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4601 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4604 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4607 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4608 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4609 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4611 case RELOAD_FOR_INPUT:
4612 /* Similar to input address, except we start at the next operand for
4613 both input and input address and we do not check for
4614 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4617 for (i = opnum + 1; i < reload_n_operands; i++)
4618 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4619 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4620 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4623 /* ... fall through ... */
4625 case RELOAD_FOR_OPERAND_ADDRESS:
4626 /* Check outputs and their addresses. */
4628 for (i = 0; i < reload_n_operands; i++)
4629 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4630 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4631 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4634 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4636 case RELOAD_FOR_OPADDR_ADDR:
4637 for (i = 0; i < reload_n_operands; i++)
4638 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4639 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4640 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4643 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4644 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4645 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4647 case RELOAD_FOR_INSN:
4648 /* These conflict with other outputs with RELOAD_OTHER. So
4649 we need only check for output addresses. */
4651 opnum = reload_n_operands;
4653 /* ... fall through ... */
4655 case RELOAD_FOR_OUTPUT:
4656 case RELOAD_FOR_OUTPUT_ADDRESS:
4657 case RELOAD_FOR_OUTADDR_ADDRESS:
4658 /* We already know these can't conflict with a later output. So the
4659 only thing to check are later output addresses.
4660 Note that multiple output operands are emitted in reverse order,
4661 so the conflicting ones are those with lower indices. */
4662 for (i = 0; i < opnum; i++)
4663 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4664 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4673 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4676 This function uses the same algorithm as reload_reg_free_p above. */
4679 reloads_conflict (r1, r2)
4682 enum reload_type r1_type = rld[r1].when_needed;
4683 enum reload_type r2_type = rld[r2].when_needed;
4684 int r1_opnum = rld[r1].opnum;
4685 int r2_opnum = rld[r2].opnum;
4687 /* RELOAD_OTHER conflicts with everything. */
4688 if (r2_type == RELOAD_OTHER)
4691 /* Otherwise, check conflicts differently for each type. */
4695 case RELOAD_FOR_INPUT:
4696 return (r2_type == RELOAD_FOR_INSN
4697 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4698 || r2_type == RELOAD_FOR_OPADDR_ADDR
4699 || r2_type == RELOAD_FOR_INPUT
4700 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4701 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4702 && r2_opnum > r1_opnum));
4704 case RELOAD_FOR_INPUT_ADDRESS:
4705 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4706 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4708 case RELOAD_FOR_INPADDR_ADDRESS:
4709 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4710 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4712 case RELOAD_FOR_OUTPUT_ADDRESS:
4713 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4714 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4716 case RELOAD_FOR_OUTADDR_ADDRESS:
4717 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4718 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4720 case RELOAD_FOR_OPERAND_ADDRESS:
4721 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4722 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4724 case RELOAD_FOR_OPADDR_ADDR:
4725 return (r2_type == RELOAD_FOR_INPUT
4726 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4728 case RELOAD_FOR_OUTPUT:
4729 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4730 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4731 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4732 && r2_opnum >= r1_opnum));
4734 case RELOAD_FOR_INSN:
4735 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4736 || r2_type == RELOAD_FOR_INSN
4737 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4739 case RELOAD_FOR_OTHER_ADDRESS:
4740 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4750 /* Indexed by reload number, 1 if incoming value
4751 inherited from previous insns. */
4752 char reload_inherited[MAX_RELOADS];
4754 /* For an inherited reload, this is the insn the reload was inherited from,
4755 if we know it. Otherwise, this is 0. */
4756 rtx reload_inheritance_insn[MAX_RELOADS];
4758 /* If nonzero, this is a place to get the value of the reload,
4759 rather than using reload_in. */
4760 rtx reload_override_in[MAX_RELOADS];
4762 /* For each reload, the hard register number of the register used,
4763 or -1 if we did not need a register for this reload. */
4764 int reload_spill_index[MAX_RELOADS];
4766 /* Subroutine of free_for_value_p, used to check a single register.
4767 START_REGNO is the starting regno of the full reload register
4768 (possibly comprising multiple hard registers) that we are considering. */
4771 reload_reg_free_for_value_p (start_regno, regno, opnum, type, value, out,
4772 reloadnum, ignore_address_reloads)
4773 int start_regno, regno;
4775 enum reload_type type;
4778 int ignore_address_reloads;
4781 /* Set if we see an input reload that must not share its reload register
4782 with any new earlyclobber, but might otherwise share the reload
4783 register with an output or input-output reload. */
4784 int check_earlyclobber = 0;
4788 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4791 if (out == const0_rtx)
4797 /* We use some pseudo 'time' value to check if the lifetimes of the
4798 new register use would overlap with the one of a previous reload
4799 that is not read-only or uses a different value.
4800 The 'time' used doesn't have to be linear in any shape or form, just
4802 Some reload types use different 'buckets' for each operand.
4803 So there are MAX_RECOG_OPERANDS different time values for each
4805 We compute TIME1 as the time when the register for the prospective
4806 new reload ceases to be live, and TIME2 for each existing
4807 reload as the time when that the reload register of that reload
4809 Where there is little to be gained by exact lifetime calculations,
4810 we just make conservative assumptions, i.e. a longer lifetime;
4811 this is done in the 'default:' cases. */
4814 case RELOAD_FOR_OTHER_ADDRESS:
4815 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4816 time1 = copy ? 0 : 1;
4819 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4821 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4822 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4823 respectively, to the time values for these, we get distinct time
4824 values. To get distinct time values for each operand, we have to
4825 multiply opnum by at least three. We round that up to four because
4826 multiply by four is often cheaper. */
4827 case RELOAD_FOR_INPADDR_ADDRESS:
4828 time1 = opnum * 4 + 2;
4830 case RELOAD_FOR_INPUT_ADDRESS:
4831 time1 = opnum * 4 + 3;
4833 case RELOAD_FOR_INPUT:
4834 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4835 executes (inclusive). */
4836 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4838 case RELOAD_FOR_OPADDR_ADDR:
4840 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4841 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4843 case RELOAD_FOR_OPERAND_ADDRESS:
4844 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4846 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4848 case RELOAD_FOR_OUTADDR_ADDRESS:
4849 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4851 case RELOAD_FOR_OUTPUT_ADDRESS:
4852 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4855 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4858 for (i = 0; i < n_reloads; i++)
4860 rtx reg = rld[i].reg_rtx;
4861 if (reg && GET_CODE (reg) == REG
4862 && ((unsigned) regno - true_regnum (reg)
4863 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned) 1)
4866 rtx other_input = rld[i].in;
4868 /* If the other reload loads the same input value, that
4869 will not cause a conflict only if it's loading it into
4870 the same register. */
4871 if (true_regnum (reg) != start_regno)
4872 other_input = NULL_RTX;
4873 if (! other_input || ! rtx_equal_p (other_input, value)
4874 || rld[i].out || out)
4877 switch (rld[i].when_needed)
4879 case RELOAD_FOR_OTHER_ADDRESS:
4882 case RELOAD_FOR_INPADDR_ADDRESS:
4883 /* find_reloads makes sure that a
4884 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4885 by at most one - the first -
4886 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4887 address reload is inherited, the address address reload
4888 goes away, so we can ignore this conflict. */
4889 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4890 && ignore_address_reloads
4891 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4892 Then the address address is still needed to store
4893 back the new address. */
4894 && ! rld[reloadnum].out)
4896 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4897 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4899 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4900 && ignore_address_reloads
4901 /* Unless we are reloading an auto_inc expression. */
4902 && ! rld[reloadnum].out)
4904 time2 = rld[i].opnum * 4 + 2;
4906 case RELOAD_FOR_INPUT_ADDRESS:
4907 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4908 && ignore_address_reloads
4909 && ! rld[reloadnum].out)
4911 time2 = rld[i].opnum * 4 + 3;
4913 case RELOAD_FOR_INPUT:
4914 time2 = rld[i].opnum * 4 + 4;
4915 check_earlyclobber = 1;
4917 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4918 == MAX_RECOG_OPERAND * 4 */
4919 case RELOAD_FOR_OPADDR_ADDR:
4920 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4921 && ignore_address_reloads
4922 && ! rld[reloadnum].out)
4924 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4926 case RELOAD_FOR_OPERAND_ADDRESS:
4927 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4928 check_earlyclobber = 1;
4930 case RELOAD_FOR_INSN:
4931 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4933 case RELOAD_FOR_OUTPUT:
4934 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4935 instruction is executed. */
4936 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4938 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4939 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4941 case RELOAD_FOR_OUTADDR_ADDRESS:
4942 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4943 && ignore_address_reloads
4944 && ! rld[reloadnum].out)
4946 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4948 case RELOAD_FOR_OUTPUT_ADDRESS:
4949 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4952 /* If there is no conflict in the input part, handle this
4953 like an output reload. */
4954 if (! rld[i].in || rtx_equal_p (other_input, value))
4956 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4957 /* Earlyclobbered outputs must conflict with inputs. */
4958 if (earlyclobber_operand_p (rld[i].out))
4959 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4964 /* RELOAD_OTHER might be live beyond instruction execution,
4965 but this is not obvious when we set time2 = 1. So check
4966 here if there might be a problem with the new reload
4967 clobbering the register used by the RELOAD_OTHER. */
4975 && (! rld[i].in || rld[i].out
4976 || ! rtx_equal_p (other_input, value)))
4977 || (out && rld[reloadnum].out_reg
4978 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4984 /* Earlyclobbered outputs must conflict with inputs. */
4985 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4991 /* Return 1 if the value in reload reg REGNO, as used by a reload
4992 needed for the part of the insn specified by OPNUM and TYPE,
4993 may be used to load VALUE into it.
4995 MODE is the mode in which the register is used, this is needed to
4996 determine how many hard regs to test.
4998 Other read-only reloads with the same value do not conflict
4999 unless OUT is nonzero and these other reloads have to live while
5000 output reloads live.
5001 If OUT is CONST0_RTX, this is a special case: it means that the
5002 test should not be for using register REGNO as reload register, but
5003 for copying from register REGNO into the reload register.
5005 RELOADNUM is the number of the reload we want to load this value for;
5006 a reload does not conflict with itself.
5008 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5009 reloads that load an address for the very reload we are considering.
5011 The caller has to make sure that there is no conflict with the return
5015 free_for_value_p (regno, mode, opnum, type, value, out, reloadnum,
5016 ignore_address_reloads)
5018 enum machine_mode mode;
5020 enum reload_type type;
5023 int ignore_address_reloads;
5025 int nregs = HARD_REGNO_NREGS (regno, mode);
5027 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5028 value, out, reloadnum,
5029 ignore_address_reloads))
5034 /* Determine whether the reload reg X overlaps any rtx'es used for
5035 overriding inheritance. Return nonzero if so. */
5038 conflicts_with_override (x)
5042 for (i = 0; i < n_reloads; i++)
5043 if (reload_override_in[i]
5044 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5049 /* Give an error message saying we failed to find a reload for INSN,
5050 and clear out reload R. */
5052 failed_reload (insn, r)
5056 if (asm_noperands (PATTERN (insn)) < 0)
5057 /* It's the compiler's fault. */
5058 fatal_insn ("could not find a spill register", insn);
5060 /* It's the user's fault; the operand's mode and constraint
5061 don't match. Disable this reload so we don't crash in final. */
5062 error_for_asm (insn,
5063 "`asm' operand constraint incompatible with operand size");
5067 rld[r].optional = 1;
5068 rld[r].secondary_p = 1;
5071 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5072 for reload R. If it's valid, get an rtx for it. Return nonzero if
5075 set_reload_reg (i, r)
5079 rtx reg = spill_reg_rtx[i];
5081 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5082 spill_reg_rtx[i] = reg
5083 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5085 regno = true_regnum (reg);
5087 /* Detect when the reload reg can't hold the reload mode.
5088 This used to be one `if', but Sequent compiler can't handle that. */
5089 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5091 enum machine_mode test_mode = VOIDmode;
5093 test_mode = GET_MODE (rld[r].in);
5094 /* If rld[r].in has VOIDmode, it means we will load it
5095 in whatever mode the reload reg has: to wit, rld[r].mode.
5096 We have already tested that for validity. */
5097 /* Aside from that, we need to test that the expressions
5098 to reload from or into have modes which are valid for this
5099 reload register. Otherwise the reload insns would be invalid. */
5100 if (! (rld[r].in != 0 && test_mode != VOIDmode
5101 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5102 if (! (rld[r].out != 0
5103 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5105 /* The reg is OK. */
5108 /* Mark as in use for this insn the reload regs we use
5110 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5111 rld[r].when_needed, rld[r].mode);
5113 rld[r].reg_rtx = reg;
5114 reload_spill_index[r] = spill_regs[i];
5121 /* Find a spill register to use as a reload register for reload R.
5122 LAST_RELOAD is nonzero if this is the last reload for the insn being
5125 Set rld[R].reg_rtx to the register allocated.
5127 We return 1 if successful, or 0 if we couldn't find a spill reg and
5128 we didn't change anything. */
5131 allocate_reload_reg (chain, r, last_reload)
5132 struct insn_chain *chain ATTRIBUTE_UNUSED;
5138 /* If we put this reload ahead, thinking it is a group,
5139 then insist on finding a group. Otherwise we can grab a
5140 reg that some other reload needs.
5141 (That can happen when we have a 68000 DATA_OR_FP_REG
5142 which is a group of data regs or one fp reg.)
5143 We need not be so restrictive if there are no more reloads
5146 ??? Really it would be nicer to have smarter handling
5147 for that kind of reg class, where a problem like this is normal.
5148 Perhaps those classes should be avoided for reloading
5149 by use of more alternatives. */
5151 int force_group = rld[r].nregs > 1 && ! last_reload;
5153 /* If we want a single register and haven't yet found one,
5154 take any reg in the right class and not in use.
5155 If we want a consecutive group, here is where we look for it.
5157 We use two passes so we can first look for reload regs to
5158 reuse, which are already in use for other reloads in this insn,
5159 and only then use additional registers.
5160 I think that maximizing reuse is needed to make sure we don't
5161 run out of reload regs. Suppose we have three reloads, and
5162 reloads A and B can share regs. These need two regs.
5163 Suppose A and B are given different regs.
5164 That leaves none for C. */
5165 for (pass = 0; pass < 2; pass++)
5167 /* I is the index in spill_regs.
5168 We advance it round-robin between insns to use all spill regs
5169 equally, so that inherited reloads have a chance
5170 of leapfrogging each other. */
5174 for (count = 0; count < n_spills; count++)
5176 int class = (int) rld[r].class;
5182 regnum = spill_regs[i];
5184 if ((reload_reg_free_p (regnum, rld[r].opnum,
5187 /* We check reload_reg_used to make sure we
5188 don't clobber the return register. */
5189 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5190 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5191 rld[r].when_needed, rld[r].in,
5193 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5194 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5195 /* Look first for regs to share, then for unshared. But
5196 don't share regs used for inherited reloads; they are
5197 the ones we want to preserve. */
5199 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5201 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5204 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5205 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5206 (on 68000) got us two FP regs. If NR is 1,
5207 we would reject both of them. */
5210 /* If we need only one reg, we have already won. */
5213 /* But reject a single reg if we demand a group. */
5218 /* Otherwise check that as many consecutive regs as we need
5219 are available here. */
5222 int regno = regnum + nr - 1;
5223 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5224 && spill_reg_order[regno] >= 0
5225 && reload_reg_free_p (regno, rld[r].opnum,
5226 rld[r].when_needed)))
5235 /* If we found something on pass 1, omit pass 2. */
5236 if (count < n_spills)
5240 /* We should have found a spill register by now. */
5241 if (count >= n_spills)
5244 /* I is the index in SPILL_REG_RTX of the reload register we are to
5245 allocate. Get an rtx for it and find its register number. */
5247 return set_reload_reg (i, r);
5250 /* Initialize all the tables needed to allocate reload registers.
5251 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5252 is the array we use to restore the reg_rtx field for every reload. */
5255 choose_reload_regs_init (chain, save_reload_reg_rtx)
5256 struct insn_chain *chain;
5257 rtx *save_reload_reg_rtx;
5261 for (i = 0; i < n_reloads; i++)
5262 rld[i].reg_rtx = save_reload_reg_rtx[i];
5264 memset (reload_inherited, 0, MAX_RELOADS);
5265 memset ((char *) reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5266 memset ((char *) reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5268 CLEAR_HARD_REG_SET (reload_reg_used);
5269 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5270 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5271 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5272 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5273 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5275 CLEAR_HARD_REG_SET (reg_used_in_insn);
5278 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5279 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5280 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5281 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5282 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5283 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5286 for (i = 0; i < reload_n_operands; i++)
5288 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5289 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5290 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5291 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5292 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5293 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5296 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5298 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5300 for (i = 0; i < n_reloads; i++)
5301 /* If we have already decided to use a certain register,
5302 don't use it in another way. */
5304 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5305 rld[i].when_needed, rld[i].mode);
5308 /* Assign hard reg targets for the pseudo-registers we must reload
5309 into hard regs for this insn.
5310 Also output the instructions to copy them in and out of the hard regs.
5312 For machines with register classes, we are responsible for
5313 finding a reload reg in the proper class. */
5316 choose_reload_regs (chain)
5317 struct insn_chain *chain;
5319 rtx insn = chain->insn;
5321 unsigned int max_group_size = 1;
5322 enum reg_class group_class = NO_REGS;
5323 int pass, win, inheritance;
5325 rtx save_reload_reg_rtx[MAX_RELOADS];
5327 /* In order to be certain of getting the registers we need,
5328 we must sort the reloads into order of increasing register class.
5329 Then our grabbing of reload registers will parallel the process
5330 that provided the reload registers.
5332 Also note whether any of the reloads wants a consecutive group of regs.
5333 If so, record the maximum size of the group desired and what
5334 register class contains all the groups needed by this insn. */
5336 for (j = 0; j < n_reloads; j++)
5338 reload_order[j] = j;
5339 reload_spill_index[j] = -1;
5341 if (rld[j].nregs > 1)
5343 max_group_size = MAX (rld[j].nregs, max_group_size);
5345 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5348 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5352 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5354 /* If -O, try first with inheritance, then turning it off.
5355 If not -O, don't do inheritance.
5356 Using inheritance when not optimizing leads to paradoxes
5357 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5358 because one side of the comparison might be inherited. */
5360 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5362 choose_reload_regs_init (chain, save_reload_reg_rtx);
5364 /* Process the reloads in order of preference just found.
5365 Beyond this point, subregs can be found in reload_reg_rtx.
5367 This used to look for an existing reloaded home for all of the
5368 reloads, and only then perform any new reloads. But that could lose
5369 if the reloads were done out of reg-class order because a later
5370 reload with a looser constraint might have an old home in a register
5371 needed by an earlier reload with a tighter constraint.
5373 To solve this, we make two passes over the reloads, in the order
5374 described above. In the first pass we try to inherit a reload
5375 from a previous insn. If there is a later reload that needs a
5376 class that is a proper subset of the class being processed, we must
5377 also allocate a spill register during the first pass.
5379 Then make a second pass over the reloads to allocate any reloads
5380 that haven't been given registers yet. */
5382 for (j = 0; j < n_reloads; j++)
5384 int r = reload_order[j];
5385 rtx search_equiv = NULL_RTX;
5387 /* Ignore reloads that got marked inoperative. */
5388 if (rld[r].out == 0 && rld[r].in == 0
5389 && ! rld[r].secondary_p)
5392 /* If find_reloads chose to use reload_in or reload_out as a reload
5393 register, we don't need to chose one. Otherwise, try even if it
5394 found one since we might save an insn if we find the value lying
5396 Try also when reload_in is a pseudo without a hard reg. */
5397 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5398 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5399 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5400 && GET_CODE (rld[r].in) != MEM
5401 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5404 #if 0 /* No longer needed for correct operation.
5405 It might give better code, or might not; worth an experiment? */
5406 /* If this is an optional reload, we can't inherit from earlier insns
5407 until we are sure that any non-optional reloads have been allocated.
5408 The following code takes advantage of the fact that optional reloads
5409 are at the end of reload_order. */
5410 if (rld[r].optional != 0)
5411 for (i = 0; i < j; i++)
5412 if ((rld[reload_order[i]].out != 0
5413 || rld[reload_order[i]].in != 0
5414 || rld[reload_order[i]].secondary_p)
5415 && ! rld[reload_order[i]].optional
5416 && rld[reload_order[i]].reg_rtx == 0)
5417 allocate_reload_reg (chain, reload_order[i], 0);
5420 /* First see if this pseudo is already available as reloaded
5421 for a previous insn. We cannot try to inherit for reloads
5422 that are smaller than the maximum number of registers needed
5423 for groups unless the register we would allocate cannot be used
5426 We could check here to see if this is a secondary reload for
5427 an object that is already in a register of the desired class.
5428 This would avoid the need for the secondary reload register.
5429 But this is complex because we can't easily determine what
5430 objects might want to be loaded via this reload. So let a
5431 register be allocated here. In `emit_reload_insns' we suppress
5432 one of the loads in the case described above. */
5438 enum machine_mode mode = VOIDmode;
5442 else if (GET_CODE (rld[r].in) == REG)
5444 regno = REGNO (rld[r].in);
5445 mode = GET_MODE (rld[r].in);
5447 else if (GET_CODE (rld[r].in_reg) == REG)
5449 regno = REGNO (rld[r].in_reg);
5450 mode = GET_MODE (rld[r].in_reg);
5452 else if (GET_CODE (rld[r].in_reg) == SUBREG
5453 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5455 byte = SUBREG_BYTE (rld[r].in_reg);
5456 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5457 if (regno < FIRST_PSEUDO_REGISTER)
5458 regno = subreg_regno (rld[r].in_reg);
5459 mode = GET_MODE (rld[r].in_reg);
5462 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5463 || GET_CODE (rld[r].in_reg) == PRE_DEC
5464 || GET_CODE (rld[r].in_reg) == POST_INC
5465 || GET_CODE (rld[r].in_reg) == POST_DEC)
5466 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5468 regno = REGNO (XEXP (rld[r].in_reg, 0));
5469 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5470 rld[r].out = rld[r].in;
5474 /* This won't work, since REGNO can be a pseudo reg number.
5475 Also, it takes much more hair to keep track of all the things
5476 that can invalidate an inherited reload of part of a pseudoreg. */
5477 else if (GET_CODE (rld[r].in) == SUBREG
5478 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5479 regno = subreg_regno (rld[r].in);
5482 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5484 enum reg_class class = rld[r].class, last_class;
5485 rtx last_reg = reg_last_reload_reg[regno];
5486 enum machine_mode need_mode;
5488 i = REGNO (last_reg);
5489 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5490 last_class = REGNO_REG_CLASS (i);
5496 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5497 GET_MODE_CLASS (mode));
5500 #ifdef CANNOT_CHANGE_MODE_CLASS
5501 (!REG_CANNOT_CHANGE_MODE_P (i, GET_MODE (last_reg),
5505 (GET_MODE_SIZE (GET_MODE (last_reg))
5506 >= GET_MODE_SIZE (need_mode))
5507 #ifdef CANNOT_CHANGE_MODE_CLASS
5510 && reg_reloaded_contents[i] == regno
5511 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5512 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5513 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5514 /* Even if we can't use this register as a reload
5515 register, we might use it for reload_override_in,
5516 if copying it to the desired class is cheap
5518 || ((REGISTER_MOVE_COST (mode, last_class, class)
5519 < MEMORY_MOVE_COST (mode, class, 1))
5520 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5521 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5525 #ifdef SECONDARY_MEMORY_NEEDED
5526 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5531 && (rld[r].nregs == max_group_size
5532 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5534 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5535 rld[r].when_needed, rld[r].in,
5538 /* If a group is needed, verify that all the subsequent
5539 registers still have their values intact. */
5540 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5543 for (k = 1; k < nr; k++)
5544 if (reg_reloaded_contents[i + k] != regno
5545 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5553 last_reg = (GET_MODE (last_reg) == mode
5554 ? last_reg : gen_rtx_REG (mode, i));
5557 for (k = 0; k < nr; k++)
5558 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5561 /* We found a register that contains the
5562 value we need. If this register is the
5563 same as an `earlyclobber' operand of the
5564 current insn, just mark it as a place to
5565 reload from since we can't use it as the
5566 reload register itself. */
5568 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5569 if (reg_overlap_mentioned_for_reload_p
5570 (reg_last_reload_reg[regno],
5571 reload_earlyclobbers[i1]))
5574 if (i1 != n_earlyclobbers
5575 || ! (free_for_value_p (i, rld[r].mode,
5577 rld[r].when_needed, rld[r].in,
5579 /* Don't use it if we'd clobber a pseudo reg. */
5580 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5582 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5583 /* Don't clobber the frame pointer. */
5584 || (i == HARD_FRAME_POINTER_REGNUM
5585 && frame_pointer_needed
5587 /* Don't really use the inherited spill reg
5588 if we need it wider than we've got it. */
5589 || (GET_MODE_SIZE (rld[r].mode)
5590 > GET_MODE_SIZE (mode))
5593 /* If find_reloads chose reload_out as reload
5594 register, stay with it - that leaves the
5595 inherited register for subsequent reloads. */
5596 || (rld[r].out && rld[r].reg_rtx
5597 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5599 if (! rld[r].optional)
5601 reload_override_in[r] = last_reg;
5602 reload_inheritance_insn[r]
5603 = reg_reloaded_insn[i];
5609 /* We can use this as a reload reg. */
5610 /* Mark the register as in use for this part of
5612 mark_reload_reg_in_use (i,
5616 rld[r].reg_rtx = last_reg;
5617 reload_inherited[r] = 1;
5618 reload_inheritance_insn[r]
5619 = reg_reloaded_insn[i];
5620 reload_spill_index[r] = i;
5621 for (k = 0; k < nr; k++)
5622 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5630 /* Here's another way to see if the value is already lying around. */
5633 && ! reload_inherited[r]
5635 && (CONSTANT_P (rld[r].in)
5636 || GET_CODE (rld[r].in) == PLUS
5637 || GET_CODE (rld[r].in) == REG
5638 || GET_CODE (rld[r].in) == MEM)
5639 && (rld[r].nregs == max_group_size
5640 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5641 search_equiv = rld[r].in;
5642 /* If this is an output reload from a simple move insn, look
5643 if an equivalence for the input is available. */
5644 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5646 rtx set = single_set (insn);
5649 && rtx_equal_p (rld[r].out, SET_DEST (set))
5650 && CONSTANT_P (SET_SRC (set)))
5651 search_equiv = SET_SRC (set);
5657 = find_equiv_reg (search_equiv, insn, rld[r].class,
5658 -1, NULL, 0, rld[r].mode);
5663 if (GET_CODE (equiv) == REG)
5664 regno = REGNO (equiv);
5665 else if (GET_CODE (equiv) == SUBREG)
5667 /* This must be a SUBREG of a hard register.
5668 Make a new REG since this might be used in an
5669 address and not all machines support SUBREGs
5671 regno = subreg_regno (equiv);
5672 equiv = gen_rtx_REG (rld[r].mode, regno);
5678 /* If we found a spill reg, reject it unless it is free
5679 and of the desired class. */
5681 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5682 && ! free_for_value_p (regno, rld[r].mode,
5683 rld[r].opnum, rld[r].when_needed,
5684 rld[r].in, rld[r].out, r, 1))
5685 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5689 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5692 /* We found a register that contains the value we need.
5693 If this register is the same as an `earlyclobber' operand
5694 of the current insn, just mark it as a place to reload from
5695 since we can't use it as the reload register itself. */
5698 for (i = 0; i < n_earlyclobbers; i++)
5699 if (reg_overlap_mentioned_for_reload_p (equiv,
5700 reload_earlyclobbers[i]))
5702 if (! rld[r].optional)
5703 reload_override_in[r] = equiv;
5708 /* If the equiv register we have found is explicitly clobbered
5709 in the current insn, it depends on the reload type if we
5710 can use it, use it for reload_override_in, or not at all.
5711 In particular, we then can't use EQUIV for a
5712 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5716 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5717 switch (rld[r].when_needed)
5719 case RELOAD_FOR_OTHER_ADDRESS:
5720 case RELOAD_FOR_INPADDR_ADDRESS:
5721 case RELOAD_FOR_INPUT_ADDRESS:
5722 case RELOAD_FOR_OPADDR_ADDR:
5725 case RELOAD_FOR_INPUT:
5726 case RELOAD_FOR_OPERAND_ADDRESS:
5727 if (! rld[r].optional)
5728 reload_override_in[r] = equiv;
5734 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5735 switch (rld[r].when_needed)
5737 case RELOAD_FOR_OTHER_ADDRESS:
5738 case RELOAD_FOR_INPADDR_ADDRESS:
5739 case RELOAD_FOR_INPUT_ADDRESS:
5740 case RELOAD_FOR_OPADDR_ADDR:
5741 case RELOAD_FOR_OPERAND_ADDRESS:
5742 case RELOAD_FOR_INPUT:
5745 if (! rld[r].optional)
5746 reload_override_in[r] = equiv;
5754 /* If we found an equivalent reg, say no code need be generated
5755 to load it, and use it as our reload reg. */
5757 && (regno != HARD_FRAME_POINTER_REGNUM
5758 || !frame_pointer_needed))
5760 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5762 rld[r].reg_rtx = equiv;
5763 reload_inherited[r] = 1;
5765 /* If reg_reloaded_valid is not set for this register,
5766 there might be a stale spill_reg_store lying around.
5767 We must clear it, since otherwise emit_reload_insns
5768 might delete the store. */
5769 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5770 spill_reg_store[regno] = NULL_RTX;
5771 /* If any of the hard registers in EQUIV are spill
5772 registers, mark them as in use for this insn. */
5773 for (k = 0; k < nr; k++)
5775 i = spill_reg_order[regno + k];
5778 mark_reload_reg_in_use (regno, rld[r].opnum,
5781 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5788 /* If we found a register to use already, or if this is an optional
5789 reload, we are done. */
5790 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5794 /* No longer needed for correct operation. Might or might
5795 not give better code on the average. Want to experiment? */
5797 /* See if there is a later reload that has a class different from our
5798 class that intersects our class or that requires less register
5799 than our reload. If so, we must allocate a register to this
5800 reload now, since that reload might inherit a previous reload
5801 and take the only available register in our class. Don't do this
5802 for optional reloads since they will force all previous reloads
5803 to be allocated. Also don't do this for reloads that have been
5806 for (i = j + 1; i < n_reloads; i++)
5808 int s = reload_order[i];
5810 if ((rld[s].in == 0 && rld[s].out == 0
5811 && ! rld[s].secondary_p)
5815 if ((rld[s].class != rld[r].class
5816 && reg_classes_intersect_p (rld[r].class,
5818 || rld[s].nregs < rld[r].nregs)
5825 allocate_reload_reg (chain, r, j == n_reloads - 1);
5829 /* Now allocate reload registers for anything non-optional that
5830 didn't get one yet. */
5831 for (j = 0; j < n_reloads; j++)
5833 int r = reload_order[j];
5835 /* Ignore reloads that got marked inoperative. */
5836 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5839 /* Skip reloads that already have a register allocated or are
5841 if (rld[r].reg_rtx != 0 || rld[r].optional)
5844 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5848 /* If that loop got all the way, we have won. */
5855 /* Loop around and try without any inheritance. */
5860 /* First undo everything done by the failed attempt
5861 to allocate with inheritance. */
5862 choose_reload_regs_init (chain, save_reload_reg_rtx);
5864 /* Some sanity tests to verify that the reloads found in the first
5865 pass are identical to the ones we have now. */
5866 if (chain->n_reloads != n_reloads)
5869 for (i = 0; i < n_reloads; i++)
5871 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5873 if (chain->rld[i].when_needed != rld[i].when_needed)
5875 for (j = 0; j < n_spills; j++)
5876 if (spill_regs[j] == chain->rld[i].regno)
5877 if (! set_reload_reg (j, i))
5878 failed_reload (chain->insn, i);
5882 /* If we thought we could inherit a reload, because it seemed that
5883 nothing else wanted the same reload register earlier in the insn,
5884 verify that assumption, now that all reloads have been assigned.
5885 Likewise for reloads where reload_override_in has been set. */
5887 /* If doing expensive optimizations, do one preliminary pass that doesn't
5888 cancel any inheritance, but removes reloads that have been needed only
5889 for reloads that we know can be inherited. */
5890 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5892 for (j = 0; j < n_reloads; j++)
5894 int r = reload_order[j];
5896 if (reload_inherited[r] && rld[r].reg_rtx)
5897 check_reg = rld[r].reg_rtx;
5898 else if (reload_override_in[r]
5899 && (GET_CODE (reload_override_in[r]) == REG
5900 || GET_CODE (reload_override_in[r]) == SUBREG))
5901 check_reg = reload_override_in[r];
5904 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5905 rld[r].opnum, rld[r].when_needed, rld[r].in,
5906 (reload_inherited[r]
5907 ? rld[r].out : const0_rtx),
5912 reload_inherited[r] = 0;
5913 reload_override_in[r] = 0;
5915 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5916 reload_override_in, then we do not need its related
5917 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5918 likewise for other reload types.
5919 We handle this by removing a reload when its only replacement
5920 is mentioned in reload_in of the reload we are going to inherit.
5921 A special case are auto_inc expressions; even if the input is
5922 inherited, we still need the address for the output. We can
5923 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5924 If we succeeded removing some reload and we are doing a preliminary
5925 pass just to remove such reloads, make another pass, since the
5926 removal of one reload might allow us to inherit another one. */
5928 && rld[r].out != rld[r].in
5929 && remove_address_replacements (rld[r].in) && pass)
5934 /* Now that reload_override_in is known valid,
5935 actually override reload_in. */
5936 for (j = 0; j < n_reloads; j++)
5937 if (reload_override_in[j])
5938 rld[j].in = reload_override_in[j];
5940 /* If this reload won't be done because it has been canceled or is
5941 optional and not inherited, clear reload_reg_rtx so other
5942 routines (such as subst_reloads) don't get confused. */
5943 for (j = 0; j < n_reloads; j++)
5944 if (rld[j].reg_rtx != 0
5945 && ((rld[j].optional && ! reload_inherited[j])
5946 || (rld[j].in == 0 && rld[j].out == 0
5947 && ! rld[j].secondary_p)))
5949 int regno = true_regnum (rld[j].reg_rtx);
5951 if (spill_reg_order[regno] >= 0)
5952 clear_reload_reg_in_use (regno, rld[j].opnum,
5953 rld[j].when_needed, rld[j].mode);
5955 reload_spill_index[j] = -1;
5958 /* Record which pseudos and which spill regs have output reloads. */
5959 for (j = 0; j < n_reloads; j++)
5961 int r = reload_order[j];
5963 i = reload_spill_index[r];
5965 /* I is nonneg if this reload uses a register.
5966 If rld[r].reg_rtx is 0, this is an optional reload
5967 that we opted to ignore. */
5968 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5969 && rld[r].reg_rtx != 0)
5971 int nregno = REGNO (rld[r].out_reg);
5974 if (nregno < FIRST_PSEUDO_REGISTER)
5975 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5978 reg_has_output_reload[nregno + nr] = 1;
5982 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5984 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5987 if (rld[r].when_needed != RELOAD_OTHER
5988 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5989 && rld[r].when_needed != RELOAD_FOR_INSN)
5995 /* Deallocate the reload register for reload R. This is called from
5996 remove_address_replacements. */
5999 deallocate_reload_reg (r)
6004 if (! rld[r].reg_rtx)
6006 regno = true_regnum (rld[r].reg_rtx);
6008 if (spill_reg_order[regno] >= 0)
6009 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6011 reload_spill_index[r] = -1;
6014 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6015 reloads of the same item for fear that we might not have enough reload
6016 registers. However, normally they will get the same reload register
6017 and hence actually need not be loaded twice.
6019 Here we check for the most common case of this phenomenon: when we have
6020 a number of reloads for the same object, each of which were allocated
6021 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6022 reload, and is not modified in the insn itself. If we find such,
6023 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6024 This will not increase the number of spill registers needed and will
6025 prevent redundant code. */
6028 merge_assigned_reloads (insn)
6033 /* Scan all the reloads looking for ones that only load values and
6034 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6035 assigned and not modified by INSN. */
6037 for (i = 0; i < n_reloads; i++)
6039 int conflicting_input = 0;
6040 int max_input_address_opnum = -1;
6041 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6043 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6044 || rld[i].out != 0 || rld[i].reg_rtx == 0
6045 || reg_set_p (rld[i].reg_rtx, insn))
6048 /* Look at all other reloads. Ensure that the only use of this
6049 reload_reg_rtx is in a reload that just loads the same value
6050 as we do. Note that any secondary reloads must be of the identical
6051 class since the values, modes, and result registers are the
6052 same, so we need not do anything with any secondary reloads. */
6054 for (j = 0; j < n_reloads; j++)
6056 if (i == j || rld[j].reg_rtx == 0
6057 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6061 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6062 && rld[j].opnum > max_input_address_opnum)
6063 max_input_address_opnum = rld[j].opnum;
6065 /* If the reload regs aren't exactly the same (e.g, different modes)
6066 or if the values are different, we can't merge this reload.
6067 But if it is an input reload, we might still merge
6068 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6070 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6071 || rld[j].out != 0 || rld[j].in == 0
6072 || ! rtx_equal_p (rld[i].in, rld[j].in))
6074 if (rld[j].when_needed != RELOAD_FOR_INPUT
6075 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6076 || rld[i].opnum > rld[j].opnum)
6077 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6079 conflicting_input = 1;
6080 if (min_conflicting_input_opnum > rld[j].opnum)
6081 min_conflicting_input_opnum = rld[j].opnum;
6085 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6086 we, in fact, found any matching reloads. */
6089 && max_input_address_opnum <= min_conflicting_input_opnum)
6091 for (j = 0; j < n_reloads; j++)
6092 if (i != j && rld[j].reg_rtx != 0
6093 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6094 && (! conflicting_input
6095 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6096 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6098 rld[i].when_needed = RELOAD_OTHER;
6100 reload_spill_index[j] = -1;
6101 transfer_replacements (i, j);
6104 /* If this is now RELOAD_OTHER, look for any reloads that load
6105 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6106 if they were for inputs, RELOAD_OTHER for outputs. Note that
6107 this test is equivalent to looking for reloads for this operand
6109 /* We must take special care when there are two or more reloads to
6110 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6111 same value or a part of it; we must not change its type if there
6112 is a conflicting input. */
6114 if (rld[i].when_needed == RELOAD_OTHER)
6115 for (j = 0; j < n_reloads; j++)
6117 && rld[j].when_needed != RELOAD_OTHER
6118 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6119 && (! conflicting_input
6120 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6121 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6122 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6128 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6129 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6130 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6132 /* Check to see if we accidentally converted two reloads
6133 that use the same reload register to the same type.
6134 If so, the resulting code won't work, so abort. */
6136 for (k = 0; k < j; k++)
6137 if (rld[k].in != 0 && rld[k].reg_rtx != 0
6138 && rld[k].when_needed == rld[j].when_needed
6139 && rtx_equal_p (rld[k].reg_rtx, rld[j].reg_rtx))
6146 /* These arrays are filled by emit_reload_insns and its subroutines. */
6147 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6148 static rtx other_input_address_reload_insns = 0;
6149 static rtx other_input_reload_insns = 0;
6150 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6151 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6152 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6153 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6154 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6155 static rtx operand_reload_insns = 0;
6156 static rtx other_operand_reload_insns = 0;
6157 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6159 /* Values to be put in spill_reg_store are put here first. */
6160 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6161 static HARD_REG_SET reg_reloaded_died;
6163 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6164 has the number J. OLD contains the value to be used as input. */
6167 emit_input_reload_insns (chain, rl, old, j)
6168 struct insn_chain *chain;
6173 rtx insn = chain->insn;
6174 rtx reloadreg = rl->reg_rtx;
6175 rtx oldequiv_reg = 0;
6178 enum machine_mode mode;
6181 /* Determine the mode to reload in.
6182 This is very tricky because we have three to choose from.
6183 There is the mode the insn operand wants (rl->inmode).
6184 There is the mode of the reload register RELOADREG.
6185 There is the intrinsic mode of the operand, which we could find
6186 by stripping some SUBREGs.
6187 It turns out that RELOADREG's mode is irrelevant:
6188 we can change that arbitrarily.
6190 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6191 then the reload reg may not support QImode moves, so use SImode.
6192 If foo is in memory due to spilling a pseudo reg, this is safe,
6193 because the QImode value is in the least significant part of a
6194 slot big enough for a SImode. If foo is some other sort of
6195 memory reference, then it is impossible to reload this case,
6196 so previous passes had better make sure this never happens.
6198 Then consider a one-word union which has SImode and one of its
6199 members is a float, being fetched as (SUBREG:SF union:SI).
6200 We must fetch that as SFmode because we could be loading into
6201 a float-only register. In this case OLD's mode is correct.
6203 Consider an immediate integer: it has VOIDmode. Here we need
6204 to get a mode from something else.
6206 In some cases, there is a fourth mode, the operand's
6207 containing mode. If the insn specifies a containing mode for
6208 this operand, it overrides all others.
6210 I am not sure whether the algorithm here is always right,
6211 but it does the right things in those cases. */
6213 mode = GET_MODE (old);
6214 if (mode == VOIDmode)
6217 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6218 /* If we need a secondary register for this operation, see if
6219 the value is already in a register in that class. Don't
6220 do this if the secondary register will be used as a scratch
6223 if (rl->secondary_in_reload >= 0
6224 && rl->secondary_in_icode == CODE_FOR_nothing
6227 = find_equiv_reg (old, insn,
6228 rld[rl->secondary_in_reload].class,
6232 /* If reloading from memory, see if there is a register
6233 that already holds the same value. If so, reload from there.
6234 We can pass 0 as the reload_reg_p argument because
6235 any other reload has either already been emitted,
6236 in which case find_equiv_reg will see the reload-insn,
6237 or has yet to be emitted, in which case it doesn't matter
6238 because we will use this equiv reg right away. */
6240 if (oldequiv == 0 && optimize
6241 && (GET_CODE (old) == MEM
6242 || (GET_CODE (old) == REG
6243 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6244 && reg_renumber[REGNO (old)] < 0)))
6245 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6249 unsigned int regno = true_regnum (oldequiv);
6251 /* Don't use OLDEQUIV if any other reload changes it at an
6252 earlier stage of this insn or at this stage. */
6253 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6254 rl->in, const0_rtx, j, 0))
6257 /* If it is no cheaper to copy from OLDEQUIV into the
6258 reload register than it would be to move from memory,
6259 don't use it. Likewise, if we need a secondary register
6263 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6264 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6266 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6267 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6268 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6272 #ifdef SECONDARY_MEMORY_NEEDED
6273 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6281 /* delete_output_reload is only invoked properly if old contains
6282 the original pseudo register. Since this is replaced with a
6283 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6284 find the pseudo in RELOAD_IN_REG. */
6286 && reload_override_in[j]
6287 && GET_CODE (rl->in_reg) == REG)
6294 else if (GET_CODE (oldequiv) == REG)
6295 oldequiv_reg = oldequiv;
6296 else if (GET_CODE (oldequiv) == SUBREG)
6297 oldequiv_reg = SUBREG_REG (oldequiv);
6299 /* If we are reloading from a register that was recently stored in
6300 with an output-reload, see if we can prove there was
6301 actually no need to store the old value in it. */
6303 if (optimize && GET_CODE (oldequiv) == REG
6304 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6305 && spill_reg_store[REGNO (oldequiv)]
6306 && GET_CODE (old) == REG
6307 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6308 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6310 delete_output_reload (insn, j, REGNO (oldequiv));
6312 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6313 then load RELOADREG from OLDEQUIV. Note that we cannot use
6314 gen_lowpart_common since it can do the wrong thing when
6315 RELOADREG has a multi-word mode. Note that RELOADREG
6316 must always be a REG here. */
6318 if (GET_MODE (reloadreg) != mode)
6319 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6320 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6321 oldequiv = SUBREG_REG (oldequiv);
6322 if (GET_MODE (oldequiv) != VOIDmode
6323 && mode != GET_MODE (oldequiv))
6324 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6326 /* Switch to the right place to emit the reload insns. */
6327 switch (rl->when_needed)
6330 where = &other_input_reload_insns;
6332 case RELOAD_FOR_INPUT:
6333 where = &input_reload_insns[rl->opnum];
6335 case RELOAD_FOR_INPUT_ADDRESS:
6336 where = &input_address_reload_insns[rl->opnum];
6338 case RELOAD_FOR_INPADDR_ADDRESS:
6339 where = &inpaddr_address_reload_insns[rl->opnum];
6341 case RELOAD_FOR_OUTPUT_ADDRESS:
6342 where = &output_address_reload_insns[rl->opnum];
6344 case RELOAD_FOR_OUTADDR_ADDRESS:
6345 where = &outaddr_address_reload_insns[rl->opnum];
6347 case RELOAD_FOR_OPERAND_ADDRESS:
6348 where = &operand_reload_insns;
6350 case RELOAD_FOR_OPADDR_ADDR:
6351 where = &other_operand_reload_insns;
6353 case RELOAD_FOR_OTHER_ADDRESS:
6354 where = &other_input_address_reload_insns;
6360 push_to_sequence (*where);
6362 /* Auto-increment addresses must be reloaded in a special way. */
6363 if (rl->out && ! rl->out_reg)
6365 /* We are not going to bother supporting the case where a
6366 incremented register can't be copied directly from
6367 OLDEQUIV since this seems highly unlikely. */
6368 if (rl->secondary_in_reload >= 0)
6371 if (reload_inherited[j])
6372 oldequiv = reloadreg;
6374 old = XEXP (rl->in_reg, 0);
6376 if (optimize && GET_CODE (oldequiv) == REG
6377 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6378 && spill_reg_store[REGNO (oldequiv)]
6379 && GET_CODE (old) == REG
6380 && (dead_or_set_p (insn,
6381 spill_reg_stored_to[REGNO (oldequiv)])
6382 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6384 delete_output_reload (insn, j, REGNO (oldequiv));
6386 /* Prevent normal processing of this reload. */
6388 /* Output a special code sequence for this case. */
6389 new_spill_reg_store[REGNO (reloadreg)]
6390 = inc_for_reload (reloadreg, oldequiv, rl->out,
6394 /* If we are reloading a pseudo-register that was set by the previous
6395 insn, see if we can get rid of that pseudo-register entirely
6396 by redirecting the previous insn into our reload register. */
6398 else if (optimize && GET_CODE (old) == REG
6399 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6400 && dead_or_set_p (insn, old)
6401 /* This is unsafe if some other reload
6402 uses the same reg first. */
6403 && ! conflicts_with_override (reloadreg)
6404 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6405 rl->when_needed, old, rl->out, j, 0))
6407 rtx temp = PREV_INSN (insn);
6408 while (temp && GET_CODE (temp) == NOTE)
6409 temp = PREV_INSN (temp);
6411 && GET_CODE (temp) == INSN
6412 && GET_CODE (PATTERN (temp)) == SET
6413 && SET_DEST (PATTERN (temp)) == old
6414 /* Make sure we can access insn_operand_constraint. */
6415 && asm_noperands (PATTERN (temp)) < 0
6416 /* This is unsafe if operand occurs more than once in current
6417 insn. Perhaps some occurrences aren't reloaded. */
6418 && count_occurrences (PATTERN (insn), old, 0) == 1)
6420 rtx old = SET_DEST (PATTERN (temp));
6421 /* Store into the reload register instead of the pseudo. */
6422 SET_DEST (PATTERN (temp)) = reloadreg;
6424 /* Verify that resulting insn is valid. */
6425 extract_insn (temp);
6426 if (constrain_operands (1))
6428 /* If the previous insn is an output reload, the source is
6429 a reload register, and its spill_reg_store entry will
6430 contain the previous destination. This is now
6432 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6433 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6435 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6436 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6439 /* If these are the only uses of the pseudo reg,
6440 pretend for GDB it lives in the reload reg we used. */
6441 if (REG_N_DEATHS (REGNO (old)) == 1
6442 && REG_N_SETS (REGNO (old)) == 1)
6444 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6445 alter_reg (REGNO (old), -1);
6451 SET_DEST (PATTERN (temp)) = old;
6456 /* We can't do that, so output an insn to load RELOADREG. */
6458 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6459 /* If we have a secondary reload, pick up the secondary register
6460 and icode, if any. If OLDEQUIV and OLD are different or
6461 if this is an in-out reload, recompute whether or not we
6462 still need a secondary register and what the icode should
6463 be. If we still need a secondary register and the class or
6464 icode is different, go back to reloading from OLD if using
6465 OLDEQUIV means that we got the wrong type of register. We
6466 cannot have different class or icode due to an in-out reload
6467 because we don't make such reloads when both the input and
6468 output need secondary reload registers. */
6470 if (! special && rl->secondary_in_reload >= 0)
6472 rtx second_reload_reg = 0;
6473 int secondary_reload = rl->secondary_in_reload;
6474 rtx real_oldequiv = oldequiv;
6477 enum insn_code icode;
6479 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6480 and similarly for OLD.
6481 See comments in get_secondary_reload in reload.c. */
6482 /* If it is a pseudo that cannot be replaced with its
6483 equivalent MEM, we must fall back to reload_in, which
6484 will have all the necessary substitutions registered.
6485 Likewise for a pseudo that can't be replaced with its
6486 equivalent constant.
6488 Take extra care for subregs of such pseudos. Note that
6489 we cannot use reg_equiv_mem in this case because it is
6490 not in the right mode. */
6493 if (GET_CODE (tmp) == SUBREG)
6494 tmp = SUBREG_REG (tmp);
6495 if (GET_CODE (tmp) == REG
6496 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6497 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6498 || reg_equiv_constant[REGNO (tmp)] != 0))
6500 if (! reg_equiv_mem[REGNO (tmp)]
6501 || num_not_at_initial_offset
6502 || GET_CODE (oldequiv) == SUBREG)
6503 real_oldequiv = rl->in;
6505 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6509 if (GET_CODE (tmp) == SUBREG)
6510 tmp = SUBREG_REG (tmp);
6511 if (GET_CODE (tmp) == REG
6512 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6513 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6514 || reg_equiv_constant[REGNO (tmp)] != 0))
6516 if (! reg_equiv_mem[REGNO (tmp)]
6517 || num_not_at_initial_offset
6518 || GET_CODE (old) == SUBREG)
6521 real_old = reg_equiv_mem[REGNO (tmp)];
6524 second_reload_reg = rld[secondary_reload].reg_rtx;
6525 icode = rl->secondary_in_icode;
6527 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6528 || (rl->in != 0 && rl->out != 0))
6530 enum reg_class new_class
6531 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6532 mode, real_oldequiv);
6534 if (new_class == NO_REGS)
6535 second_reload_reg = 0;
6538 enum insn_code new_icode;
6539 enum machine_mode new_mode;
6541 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6542 REGNO (second_reload_reg)))
6543 oldequiv = old, real_oldequiv = real_old;
6546 new_icode = reload_in_optab[(int) mode];
6547 if (new_icode != CODE_FOR_nothing
6548 && ((insn_data[(int) new_icode].operand[0].predicate
6549 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6551 || (insn_data[(int) new_icode].operand[1].predicate
6552 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6553 (real_oldequiv, mode)))))
6554 new_icode = CODE_FOR_nothing;
6556 if (new_icode == CODE_FOR_nothing)
6559 new_mode = insn_data[(int) new_icode].operand[2].mode;
6561 if (GET_MODE (second_reload_reg) != new_mode)
6563 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6565 oldequiv = old, real_oldequiv = real_old;
6568 = gen_rtx_REG (new_mode,
6569 REGNO (second_reload_reg));
6575 /* If we still need a secondary reload register, check
6576 to see if it is being used as a scratch or intermediate
6577 register and generate code appropriately. If we need
6578 a scratch register, use REAL_OLDEQUIV since the form of
6579 the insn may depend on the actual address if it is
6582 if (second_reload_reg)
6584 if (icode != CODE_FOR_nothing)
6586 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6587 second_reload_reg));
6592 /* See if we need a scratch register to load the
6593 intermediate register (a tertiary reload). */
6594 enum insn_code tertiary_icode
6595 = rld[secondary_reload].secondary_in_icode;
6597 if (tertiary_icode != CODE_FOR_nothing)
6599 rtx third_reload_reg
6600 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6602 emit_insn ((GEN_FCN (tertiary_icode)
6603 (second_reload_reg, real_oldequiv,
6604 third_reload_reg)));
6607 gen_reload (second_reload_reg, real_oldequiv,
6611 oldequiv = second_reload_reg;
6617 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6619 rtx real_oldequiv = oldequiv;
6621 if ((GET_CODE (oldequiv) == REG
6622 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6623 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6624 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6625 || (GET_CODE (oldequiv) == SUBREG
6626 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6627 && (REGNO (SUBREG_REG (oldequiv))
6628 >= FIRST_PSEUDO_REGISTER)
6629 && ((reg_equiv_memory_loc
6630 [REGNO (SUBREG_REG (oldequiv))] != 0)
6631 || (reg_equiv_constant
6632 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6633 || (CONSTANT_P (oldequiv)
6634 && (PREFERRED_RELOAD_CLASS (oldequiv,
6635 REGNO_REG_CLASS (REGNO (reloadreg)))
6637 real_oldequiv = rl->in;
6638 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6642 if (flag_non_call_exceptions)
6643 copy_eh_notes (insn, get_insns ());
6645 /* End this sequence. */
6646 *where = get_insns ();
6649 /* Update reload_override_in so that delete_address_reloads_1
6650 can see the actual register usage. */
6652 reload_override_in[j] = oldequiv;
6655 /* Generate insns to for the output reload RL, which is for the insn described
6656 by CHAIN and has the number J. */
6658 emit_output_reload_insns (chain, rl, j)
6659 struct insn_chain *chain;
6663 rtx reloadreg = rl->reg_rtx;
6664 rtx insn = chain->insn;
6667 enum machine_mode mode = GET_MODE (old);
6670 if (rl->when_needed == RELOAD_OTHER)
6673 push_to_sequence (output_reload_insns[rl->opnum]);
6675 /* Determine the mode to reload in.
6676 See comments above (for input reloading). */
6678 if (mode == VOIDmode)
6680 /* VOIDmode should never happen for an output. */
6681 if (asm_noperands (PATTERN (insn)) < 0)
6682 /* It's the compiler's fault. */
6683 fatal_insn ("VOIDmode on an output", insn);
6684 error_for_asm (insn, "output operand is constant in `asm'");
6685 /* Prevent crash--use something we know is valid. */
6687 old = gen_rtx_REG (mode, REGNO (reloadreg));
6690 if (GET_MODE (reloadreg) != mode)
6691 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6693 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6695 /* If we need two reload regs, set RELOADREG to the intermediate
6696 one, since it will be stored into OLD. We might need a secondary
6697 register only for an input reload, so check again here. */
6699 if (rl->secondary_out_reload >= 0)
6703 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6704 && reg_equiv_mem[REGNO (old)] != 0)
6705 real_old = reg_equiv_mem[REGNO (old)];
6707 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6711 rtx second_reloadreg = reloadreg;
6712 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6714 /* See if RELOADREG is to be used as a scratch register
6715 or as an intermediate register. */
6716 if (rl->secondary_out_icode != CODE_FOR_nothing)
6718 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6719 (real_old, second_reloadreg, reloadreg)));
6724 /* See if we need both a scratch and intermediate reload
6727 int secondary_reload = rl->secondary_out_reload;
6728 enum insn_code tertiary_icode
6729 = rld[secondary_reload].secondary_out_icode;
6731 if (GET_MODE (reloadreg) != mode)
6732 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6734 if (tertiary_icode != CODE_FOR_nothing)
6737 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6740 /* Copy primary reload reg to secondary reload reg.
6741 (Note that these have been swapped above, then
6742 secondary reload reg to OLD using our insn.) */
6744 /* If REAL_OLD is a paradoxical SUBREG, remove it
6745 and try to put the opposite SUBREG on
6747 if (GET_CODE (real_old) == SUBREG
6748 && (GET_MODE_SIZE (GET_MODE (real_old))
6749 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6750 && 0 != (tem = gen_lowpart_common
6751 (GET_MODE (SUBREG_REG (real_old)),
6753 real_old = SUBREG_REG (real_old), reloadreg = tem;
6755 gen_reload (reloadreg, second_reloadreg,
6756 rl->opnum, rl->when_needed);
6757 emit_insn ((GEN_FCN (tertiary_icode)
6758 (real_old, reloadreg, third_reloadreg)));
6763 /* Copy between the reload regs here and then to
6766 gen_reload (reloadreg, second_reloadreg,
6767 rl->opnum, rl->when_needed);
6773 /* Output the last reload insn. */
6778 /* Don't output the last reload if OLD is not the dest of
6779 INSN and is in the src and is clobbered by INSN. */
6780 if (! flag_expensive_optimizations
6781 || GET_CODE (old) != REG
6782 || !(set = single_set (insn))
6783 || rtx_equal_p (old, SET_DEST (set))
6784 || !reg_mentioned_p (old, SET_SRC (set))
6785 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6786 gen_reload (old, reloadreg, rl->opnum,
6790 /* Look at all insns we emitted, just to be safe. */
6791 for (p = get_insns (); p; p = NEXT_INSN (p))
6794 rtx pat = PATTERN (p);
6796 /* If this output reload doesn't come from a spill reg,
6797 clear any memory of reloaded copies of the pseudo reg.
6798 If this output reload comes from a spill reg,
6799 reg_has_output_reload will make this do nothing. */
6800 note_stores (pat, forget_old_reloads_1, NULL);
6802 if (reg_mentioned_p (rl->reg_rtx, pat))
6804 rtx set = single_set (insn);
6805 if (reload_spill_index[j] < 0
6807 && SET_SRC (set) == rl->reg_rtx)
6809 int src = REGNO (SET_SRC (set));
6811 reload_spill_index[j] = src;
6812 SET_HARD_REG_BIT (reg_is_output_reload, src);
6813 if (find_regno_note (insn, REG_DEAD, src))
6814 SET_HARD_REG_BIT (reg_reloaded_died, src);
6816 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6818 int s = rl->secondary_out_reload;
6819 set = single_set (p);
6820 /* If this reload copies only to the secondary reload
6821 register, the secondary reload does the actual
6823 if (s >= 0 && set == NULL_RTX)
6824 /* We can't tell what function the secondary reload
6825 has and where the actual store to the pseudo is
6826 made; leave new_spill_reg_store alone. */
6829 && SET_SRC (set) == rl->reg_rtx
6830 && SET_DEST (set) == rld[s].reg_rtx)
6832 /* Usually the next instruction will be the
6833 secondary reload insn; if we can confirm
6834 that it is, setting new_spill_reg_store to
6835 that insn will allow an extra optimization. */
6836 rtx s_reg = rld[s].reg_rtx;
6837 rtx next = NEXT_INSN (p);
6838 rld[s].out = rl->out;
6839 rld[s].out_reg = rl->out_reg;
6840 set = single_set (next);
6841 if (set && SET_SRC (set) == s_reg
6842 && ! new_spill_reg_store[REGNO (s_reg)])
6844 SET_HARD_REG_BIT (reg_is_output_reload,
6846 new_spill_reg_store[REGNO (s_reg)] = next;
6850 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6855 if (rl->when_needed == RELOAD_OTHER)
6857 emit_insn (other_output_reload_insns[rl->opnum]);
6858 other_output_reload_insns[rl->opnum] = get_insns ();
6861 output_reload_insns[rl->opnum] = get_insns ();
6863 if (flag_non_call_exceptions)
6864 copy_eh_notes (insn, get_insns ());
6869 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6870 and has the number J. */
6872 do_input_reload (chain, rl, j)
6873 struct insn_chain *chain;
6877 rtx insn = chain->insn;
6878 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6879 ? rl->in_reg : rl->in);
6882 /* AUTO_INC reloads need to be handled even if inherited. We got an
6883 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6884 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6885 && ! rtx_equal_p (rl->reg_rtx, old)
6886 && rl->reg_rtx != 0)
6887 emit_input_reload_insns (chain, rld + j, old, j);
6889 /* When inheriting a wider reload, we have a MEM in rl->in,
6890 e.g. inheriting a SImode output reload for
6891 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6892 if (optimize && reload_inherited[j] && rl->in
6893 && GET_CODE (rl->in) == MEM
6894 && GET_CODE (rl->in_reg) == MEM
6895 && reload_spill_index[j] >= 0
6896 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6897 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6899 /* If we are reloading a register that was recently stored in with an
6900 output-reload, see if we can prove there was
6901 actually no need to store the old value in it. */
6904 && (reload_inherited[j] || reload_override_in[j])
6906 && GET_CODE (rl->reg_rtx) == REG
6907 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6909 /* There doesn't seem to be any reason to restrict this to pseudos
6910 and doing so loses in the case where we are copying from a
6911 register of the wrong class. */
6912 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6913 >= FIRST_PSEUDO_REGISTER)
6915 /* The insn might have already some references to stackslots
6916 replaced by MEMs, while reload_out_reg still names the
6918 && (dead_or_set_p (insn,
6919 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6920 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6922 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6925 /* Do output reloading for reload RL, which is for the insn described by
6926 CHAIN and has the number J.
6927 ??? At some point we need to support handling output reloads of
6928 JUMP_INSNs or insns that set cc0. */
6930 do_output_reload (chain, rl, j)
6931 struct insn_chain *chain;
6936 rtx insn = chain->insn;
6937 /* If this is an output reload that stores something that is
6938 not loaded in this same reload, see if we can eliminate a previous
6940 rtx pseudo = rl->out_reg;
6944 && GET_CODE (pseudo) == REG
6945 && ! rtx_equal_p (rl->in_reg, pseudo)
6946 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6947 && reg_last_reload_reg[REGNO (pseudo)])
6949 int pseudo_no = REGNO (pseudo);
6950 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6952 /* We don't need to test full validity of last_regno for
6953 inherit here; we only want to know if the store actually
6954 matches the pseudo. */
6955 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6956 && reg_reloaded_contents[last_regno] == pseudo_no
6957 && spill_reg_store[last_regno]
6958 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6959 delete_output_reload (insn, j, last_regno);
6964 || rl->reg_rtx == old
6965 || rl->reg_rtx == 0)
6968 /* An output operand that dies right away does need a reload,
6969 but need not be copied from it. Show the new location in the
6971 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6972 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6974 XEXP (note, 0) = rl->reg_rtx;
6977 /* Likewise for a SUBREG of an operand that dies. */
6978 else if (GET_CODE (old) == SUBREG
6979 && GET_CODE (SUBREG_REG (old)) == REG
6980 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6983 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6987 else if (GET_CODE (old) == SCRATCH)
6988 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6989 but we don't want to make an output reload. */
6992 /* If is a JUMP_INSN, we can't support output reloads yet. */
6993 if (GET_CODE (insn) == JUMP_INSN)
6996 emit_output_reload_insns (chain, rld + j, j);
6999 /* Output insns to reload values in and out of the chosen reload regs. */
7002 emit_reload_insns (chain)
7003 struct insn_chain *chain;
7005 rtx insn = chain->insn;
7009 CLEAR_HARD_REG_SET (reg_reloaded_died);
7011 for (j = 0; j < reload_n_operands; j++)
7012 input_reload_insns[j] = input_address_reload_insns[j]
7013 = inpaddr_address_reload_insns[j]
7014 = output_reload_insns[j] = output_address_reload_insns[j]
7015 = outaddr_address_reload_insns[j]
7016 = other_output_reload_insns[j] = 0;
7017 other_input_address_reload_insns = 0;
7018 other_input_reload_insns = 0;
7019 operand_reload_insns = 0;
7020 other_operand_reload_insns = 0;
7022 /* Dump reloads into the dump file. */
7025 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7026 debug_reload_to_stream (rtl_dump_file);
7029 /* Now output the instructions to copy the data into and out of the
7030 reload registers. Do these in the order that the reloads were reported,
7031 since reloads of base and index registers precede reloads of operands
7032 and the operands may need the base and index registers reloaded. */
7034 for (j = 0; j < n_reloads; j++)
7037 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7038 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7040 do_input_reload (chain, rld + j, j);
7041 do_output_reload (chain, rld + j, j);
7044 /* Now write all the insns we made for reloads in the order expected by
7045 the allocation functions. Prior to the insn being reloaded, we write
7046 the following reloads:
7048 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7050 RELOAD_OTHER reloads.
7052 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7053 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7054 RELOAD_FOR_INPUT reload for the operand.
7056 RELOAD_FOR_OPADDR_ADDRS reloads.
7058 RELOAD_FOR_OPERAND_ADDRESS reloads.
7060 After the insn being reloaded, we write the following:
7062 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7063 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7064 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7065 reloads for the operand. The RELOAD_OTHER output reloads are
7066 output in descending order by reload number. */
7068 emit_insn_before (other_input_address_reload_insns, insn);
7069 emit_insn_before (other_input_reload_insns, insn);
7071 for (j = 0; j < reload_n_operands; j++)
7073 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7074 emit_insn_before (input_address_reload_insns[j], insn);
7075 emit_insn_before (input_reload_insns[j], insn);
7078 emit_insn_before (other_operand_reload_insns, insn);
7079 emit_insn_before (operand_reload_insns, insn);
7081 for (j = 0; j < reload_n_operands; j++)
7083 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7084 x = emit_insn_after (output_address_reload_insns[j], x);
7085 x = emit_insn_after (output_reload_insns[j], x);
7086 emit_insn_after (other_output_reload_insns[j], x);
7089 /* For all the spill regs newly reloaded in this instruction,
7090 record what they were reloaded from, so subsequent instructions
7091 can inherit the reloads.
7093 Update spill_reg_store for the reloads of this insn.
7094 Copy the elements that were updated in the loop above. */
7096 for (j = 0; j < n_reloads; j++)
7098 int r = reload_order[j];
7099 int i = reload_spill_index[r];
7101 /* If this is a non-inherited input reload from a pseudo, we must
7102 clear any memory of a previous store to the same pseudo. Only do
7103 something if there will not be an output reload for the pseudo
7105 if (rld[r].in_reg != 0
7106 && ! (reload_inherited[r] || reload_override_in[r]))
7108 rtx reg = rld[r].in_reg;
7110 if (GET_CODE (reg) == SUBREG)
7111 reg = SUBREG_REG (reg);
7113 if (GET_CODE (reg) == REG
7114 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7115 && ! reg_has_output_reload[REGNO (reg)])
7117 int nregno = REGNO (reg);
7119 if (reg_last_reload_reg[nregno])
7121 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7123 if (reg_reloaded_contents[last_regno] == nregno)
7124 spill_reg_store[last_regno] = 0;
7129 /* I is nonneg if this reload used a register.
7130 If rld[r].reg_rtx is 0, this is an optional reload
7131 that we opted to ignore. */
7133 if (i >= 0 && rld[r].reg_rtx != 0)
7135 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
7137 int part_reaches_end = 0;
7138 int all_reaches_end = 1;
7140 /* For a multi register reload, we need to check if all or part
7141 of the value lives to the end. */
7142 for (k = 0; k < nr; k++)
7144 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7145 rld[r].when_needed))
7146 part_reaches_end = 1;
7148 all_reaches_end = 0;
7151 /* Ignore reloads that don't reach the end of the insn in
7153 if (all_reaches_end)
7155 /* First, clear out memory of what used to be in this spill reg.
7156 If consecutive registers are used, clear them all. */
7158 for (k = 0; k < nr; k++)
7159 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7161 /* Maybe the spill reg contains a copy of reload_out. */
7163 && (GET_CODE (rld[r].out) == REG
7167 || GET_CODE (rld[r].out_reg) == REG))
7169 rtx out = (GET_CODE (rld[r].out) == REG
7173 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7174 int nregno = REGNO (out);
7175 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7176 : HARD_REGNO_NREGS (nregno,
7177 GET_MODE (rld[r].reg_rtx)));
7179 spill_reg_store[i] = new_spill_reg_store[i];
7180 spill_reg_stored_to[i] = out;
7181 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7183 /* If NREGNO is a hard register, it may occupy more than
7184 one register. If it does, say what is in the
7185 rest of the registers assuming that both registers
7186 agree on how many words the object takes. If not,
7187 invalidate the subsequent registers. */
7189 if (nregno < FIRST_PSEUDO_REGISTER)
7190 for (k = 1; k < nnr; k++)
7191 reg_last_reload_reg[nregno + k]
7193 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7196 /* Now do the inverse operation. */
7197 for (k = 0; k < nr; k++)
7199 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7200 reg_reloaded_contents[i + k]
7201 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7204 reg_reloaded_insn[i + k] = insn;
7205 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7209 /* Maybe the spill reg contains a copy of reload_in. Only do
7210 something if there will not be an output reload for
7211 the register being reloaded. */
7212 else if (rld[r].out_reg == 0
7214 && ((GET_CODE (rld[r].in) == REG
7215 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7216 && ! reg_has_output_reload[REGNO (rld[r].in)])
7217 || (GET_CODE (rld[r].in_reg) == REG
7218 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7219 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7224 if (GET_CODE (rld[r].in) == REG
7225 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7226 nregno = REGNO (rld[r].in);
7227 else if (GET_CODE (rld[r].in_reg) == REG)
7228 nregno = REGNO (rld[r].in_reg);
7230 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7232 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7233 : HARD_REGNO_NREGS (nregno,
7234 GET_MODE (rld[r].reg_rtx)));
7236 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7238 if (nregno < FIRST_PSEUDO_REGISTER)
7239 for (k = 1; k < nnr; k++)
7240 reg_last_reload_reg[nregno + k]
7242 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7245 /* Unless we inherited this reload, show we haven't
7246 recently done a store.
7247 Previous stores of inherited auto_inc expressions
7248 also have to be discarded. */
7249 if (! reload_inherited[r]
7250 || (rld[r].out && ! rld[r].out_reg))
7251 spill_reg_store[i] = 0;
7253 for (k = 0; k < nr; k++)
7255 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7256 reg_reloaded_contents[i + k]
7257 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7260 reg_reloaded_insn[i + k] = insn;
7261 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7266 /* However, if part of the reload reaches the end, then we must
7267 invalidate the old info for the part that survives to the end. */
7268 else if (part_reaches_end)
7270 for (k = 0; k < nr; k++)
7271 if (reload_reg_reaches_end_p (i + k,
7273 rld[r].when_needed))
7274 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7278 /* The following if-statement was #if 0'd in 1.34 (or before...).
7279 It's reenabled in 1.35 because supposedly nothing else
7280 deals with this problem. */
7282 /* If a register gets output-reloaded from a non-spill register,
7283 that invalidates any previous reloaded copy of it.
7284 But forget_old_reloads_1 won't get to see it, because
7285 it thinks only about the original insn. So invalidate it here. */
7286 if (i < 0 && rld[r].out != 0
7287 && (GET_CODE (rld[r].out) == REG
7288 || (GET_CODE (rld[r].out) == MEM
7289 && GET_CODE (rld[r].out_reg) == REG)))
7291 rtx out = (GET_CODE (rld[r].out) == REG
7292 ? rld[r].out : rld[r].out_reg);
7293 int nregno = REGNO (out);
7294 if (nregno >= FIRST_PSEUDO_REGISTER)
7296 rtx src_reg, store_insn = NULL_RTX;
7298 reg_last_reload_reg[nregno] = 0;
7300 /* If we can find a hard register that is stored, record
7301 the storing insn so that we may delete this insn with
7302 delete_output_reload. */
7303 src_reg = rld[r].reg_rtx;
7305 /* If this is an optional reload, try to find the source reg
7306 from an input reload. */
7309 rtx set = single_set (insn);
7310 if (set && SET_DEST (set) == rld[r].out)
7314 src_reg = SET_SRC (set);
7316 for (k = 0; k < n_reloads; k++)
7318 if (rld[k].in == src_reg)
7320 src_reg = rld[k].reg_rtx;
7327 store_insn = new_spill_reg_store[REGNO (src_reg)];
7328 if (src_reg && GET_CODE (src_reg) == REG
7329 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7331 int src_regno = REGNO (src_reg);
7332 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7333 /* The place where to find a death note varies with
7334 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7335 necessarily checked exactly in the code that moves
7336 notes, so just check both locations. */
7337 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7338 if (! note && store_insn)
7339 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7342 spill_reg_store[src_regno + nr] = store_insn;
7343 spill_reg_stored_to[src_regno + nr] = out;
7344 reg_reloaded_contents[src_regno + nr] = nregno;
7345 reg_reloaded_insn[src_regno + nr] = store_insn;
7346 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7347 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7348 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7350 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7352 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7354 reg_last_reload_reg[nregno] = src_reg;
7359 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7361 while (num_regs-- > 0)
7362 reg_last_reload_reg[nregno + num_regs] = 0;
7366 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7369 /* Emit code to perform a reload from IN (which may be a reload register) to
7370 OUT (which may also be a reload register). IN or OUT is from operand
7371 OPNUM with reload type TYPE.
7373 Returns first insn emitted. */
7376 gen_reload (out, in, opnum, type)
7380 enum reload_type type;
7382 rtx last = get_last_insn ();
7385 /* If IN is a paradoxical SUBREG, remove it and try to put the
7386 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7387 if (GET_CODE (in) == SUBREG
7388 && (GET_MODE_SIZE (GET_MODE (in))
7389 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7390 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7391 in = SUBREG_REG (in), out = tem;
7392 else if (GET_CODE (out) == SUBREG
7393 && (GET_MODE_SIZE (GET_MODE (out))
7394 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7395 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7396 out = SUBREG_REG (out), in = tem;
7398 /* How to do this reload can get quite tricky. Normally, we are being
7399 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7400 register that didn't get a hard register. In that case we can just
7401 call emit_move_insn.
7403 We can also be asked to reload a PLUS that adds a register or a MEM to
7404 another register, constant or MEM. This can occur during frame pointer
7405 elimination and while reloading addresses. This case is handled by
7406 trying to emit a single insn to perform the add. If it is not valid,
7407 we use a two insn sequence.
7409 Finally, we could be called to handle an 'o' constraint by putting
7410 an address into a register. In that case, we first try to do this
7411 with a named pattern of "reload_load_address". If no such pattern
7412 exists, we just emit a SET insn and hope for the best (it will normally
7413 be valid on machines that use 'o').
7415 This entire process is made complex because reload will never
7416 process the insns we generate here and so we must ensure that
7417 they will fit their constraints and also by the fact that parts of
7418 IN might be being reloaded separately and replaced with spill registers.
7419 Because of this, we are, in some sense, just guessing the right approach
7420 here. The one listed above seems to work.
7422 ??? At some point, this whole thing needs to be rethought. */
7424 if (GET_CODE (in) == PLUS
7425 && (GET_CODE (XEXP (in, 0)) == REG
7426 || GET_CODE (XEXP (in, 0)) == SUBREG
7427 || GET_CODE (XEXP (in, 0)) == MEM)
7428 && (GET_CODE (XEXP (in, 1)) == REG
7429 || GET_CODE (XEXP (in, 1)) == SUBREG
7430 || CONSTANT_P (XEXP (in, 1))
7431 || GET_CODE (XEXP (in, 1)) == MEM))
7433 /* We need to compute the sum of a register or a MEM and another
7434 register, constant, or MEM, and put it into the reload
7435 register. The best possible way of doing this is if the machine
7436 has a three-operand ADD insn that accepts the required operands.
7438 The simplest approach is to try to generate such an insn and see if it
7439 is recognized and matches its constraints. If so, it can be used.
7441 It might be better not to actually emit the insn unless it is valid,
7442 but we need to pass the insn as an operand to `recog' and
7443 `extract_insn' and it is simpler to emit and then delete the insn if
7444 not valid than to dummy things up. */
7446 rtx op0, op1, tem, insn;
7449 op0 = find_replacement (&XEXP (in, 0));
7450 op1 = find_replacement (&XEXP (in, 1));
7452 /* Since constraint checking is strict, commutativity won't be
7453 checked, so we need to do that here to avoid spurious failure
7454 if the add instruction is two-address and the second operand
7455 of the add is the same as the reload reg, which is frequently
7456 the case. If the insn would be A = B + A, rearrange it so
7457 it will be A = A + B as constrain_operands expects. */
7459 if (GET_CODE (XEXP (in, 1)) == REG
7460 && REGNO (out) == REGNO (XEXP (in, 1)))
7461 tem = op0, op0 = op1, op1 = tem;
7463 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7464 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7466 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7467 code = recog_memoized (insn);
7471 extract_insn (insn);
7472 /* We want constrain operands to treat this insn strictly in
7473 its validity determination, i.e., the way it would after reload
7475 if (constrain_operands (1))
7479 delete_insns_since (last);
7481 /* If that failed, we must use a conservative two-insn sequence.
7483 Use a move to copy one operand into the reload register. Prefer
7484 to reload a constant, MEM or pseudo since the move patterns can
7485 handle an arbitrary operand. If OP1 is not a constant, MEM or
7486 pseudo and OP1 is not a valid operand for an add instruction, then
7489 After reloading one of the operands into the reload register, add
7490 the reload register to the output register.
7492 If there is another way to do this for a specific machine, a
7493 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7496 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7498 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7499 || (GET_CODE (op1) == REG
7500 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7501 || (code != CODE_FOR_nothing
7502 && ! ((*insn_data[code].operand[2].predicate)
7503 (op1, insn_data[code].operand[2].mode))))
7504 tem = op0, op0 = op1, op1 = tem;
7506 gen_reload (out, op0, opnum, type);
7508 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7509 This fixes a problem on the 32K where the stack pointer cannot
7510 be used as an operand of an add insn. */
7512 if (rtx_equal_p (op0, op1))
7515 insn = emit_insn (gen_add2_insn (out, op1));
7517 /* If that failed, copy the address register to the reload register.
7518 Then add the constant to the reload register. */
7520 code = recog_memoized (insn);
7524 extract_insn (insn);
7525 /* We want constrain operands to treat this insn strictly in
7526 its validity determination, i.e., the way it would after reload
7528 if (constrain_operands (1))
7530 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7532 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7537 delete_insns_since (last);
7539 gen_reload (out, op1, opnum, type);
7540 insn = emit_insn (gen_add2_insn (out, op0));
7541 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7544 #ifdef SECONDARY_MEMORY_NEEDED
7545 /* If we need a memory location to do the move, do it that way. */
7546 else if ((GET_CODE (in) == REG || GET_CODE (in) == SUBREG)
7547 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7548 && (GET_CODE (out) == REG || GET_CODE (out) == SUBREG)
7549 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7550 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7551 REGNO_REG_CLASS (reg_or_subregno (out)),
7554 /* Get the memory to use and rewrite both registers to its mode. */
7555 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7557 if (GET_MODE (loc) != GET_MODE (out))
7558 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7560 if (GET_MODE (loc) != GET_MODE (in))
7561 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7563 gen_reload (loc, in, opnum, type);
7564 gen_reload (out, loc, opnum, type);
7568 /* If IN is a simple operand, use gen_move_insn. */
7569 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7570 emit_insn (gen_move_insn (out, in));
7572 #ifdef HAVE_reload_load_address
7573 else if (HAVE_reload_load_address)
7574 emit_insn (gen_reload_load_address (out, in));
7577 /* Otherwise, just write (set OUT IN) and hope for the best. */
7579 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7581 /* Return the first insn emitted.
7582 We can not just return get_last_insn, because there may have
7583 been multiple instructions emitted. Also note that gen_move_insn may
7584 emit more than one insn itself, so we can not assume that there is one
7585 insn emitted per emit_insn_before call. */
7587 return last ? NEXT_INSN (last) : get_insns ();
7590 /* Delete a previously made output-reload whose result we now believe
7591 is not needed. First we double-check.
7593 INSN is the insn now being processed.
7594 LAST_RELOAD_REG is the hard register number for which we want to delete
7595 the last output reload.
7596 J is the reload-number that originally used REG. The caller has made
7597 certain that reload J doesn't use REG any longer for input. */
7600 delete_output_reload (insn, j, last_reload_reg)
7603 int last_reload_reg;
7605 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7606 rtx reg = spill_reg_stored_to[last_reload_reg];
7609 int n_inherited = 0;
7613 /* It is possible that this reload has been only used to set another reload
7614 we eliminated earlier and thus deleted this instruction too. */
7615 if (INSN_DELETED_P (output_reload_insn))
7618 /* Get the raw pseudo-register referred to. */
7620 while (GET_CODE (reg) == SUBREG)
7621 reg = SUBREG_REG (reg);
7622 substed = reg_equiv_memory_loc[REGNO (reg)];
7624 /* This is unsafe if the operand occurs more often in the current
7625 insn than it is inherited. */
7626 for (k = n_reloads - 1; k >= 0; k--)
7628 rtx reg2 = rld[k].in;
7631 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7632 reg2 = rld[k].in_reg;
7634 if (rld[k].out && ! rld[k].out_reg)
7635 reg2 = XEXP (rld[k].in_reg, 0);
7637 while (GET_CODE (reg2) == SUBREG)
7638 reg2 = SUBREG_REG (reg2);
7639 if (rtx_equal_p (reg2, reg))
7641 if (reload_inherited[k] || reload_override_in[k] || k == j)
7644 reg2 = rld[k].out_reg;
7647 while (GET_CODE (reg2) == SUBREG)
7648 reg2 = XEXP (reg2, 0);
7649 if (rtx_equal_p (reg2, reg))
7656 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7658 n_occurrences += count_occurrences (PATTERN (insn),
7659 eliminate_regs (substed, 0,
7661 if (n_occurrences > n_inherited)
7664 /* If the pseudo-reg we are reloading is no longer referenced
7665 anywhere between the store into it and here,
7666 and no jumps or labels intervene, then the value can get
7667 here through the reload reg alone.
7668 Otherwise, give up--return. */
7669 for (i1 = NEXT_INSN (output_reload_insn);
7670 i1 != insn; i1 = NEXT_INSN (i1))
7672 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7674 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7675 && reg_mentioned_p (reg, PATTERN (i1)))
7677 /* If this is USE in front of INSN, we only have to check that
7678 there are no more references than accounted for by inheritance. */
7679 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7681 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7682 i1 = NEXT_INSN (i1);
7684 if (n_occurrences <= n_inherited && i1 == insn)
7690 /* We will be deleting the insn. Remove the spill reg information. */
7691 for (k = HARD_REGNO_NREGS (last_reload_reg, GET_MODE (reg)); k-- > 0; )
7693 spill_reg_store[last_reload_reg + k] = 0;
7694 spill_reg_stored_to[last_reload_reg + k] = 0;
7697 /* The caller has already checked that REG dies or is set in INSN.
7698 It has also checked that we are optimizing, and thus some
7699 inaccuracies in the debugging information are acceptable.
7700 So we could just delete output_reload_insn. But in some cases
7701 we can improve the debugging information without sacrificing
7702 optimization - maybe even improving the code: See if the pseudo
7703 reg has been completely replaced with reload regs. If so, delete
7704 the store insn and forget we had a stack slot for the pseudo. */
7705 if (rld[j].out != rld[j].in
7706 && REG_N_DEATHS (REGNO (reg)) == 1
7707 && REG_N_SETS (REGNO (reg)) == 1
7708 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7709 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7713 /* We know that it was used only between here and the beginning of
7714 the current basic block. (We also know that the last use before
7715 INSN was the output reload we are thinking of deleting, but never
7716 mind that.) Search that range; see if any ref remains. */
7717 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7719 rtx set = single_set (i2);
7721 /* Uses which just store in the pseudo don't count,
7722 since if they are the only uses, they are dead. */
7723 if (set != 0 && SET_DEST (set) == reg)
7725 if (GET_CODE (i2) == CODE_LABEL
7726 || GET_CODE (i2) == JUMP_INSN)
7728 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7729 && reg_mentioned_p (reg, PATTERN (i2)))
7731 /* Some other ref remains; just delete the output reload we
7733 delete_address_reloads (output_reload_insn, insn);
7734 delete_insn (output_reload_insn);
7739 /* Delete the now-dead stores into this pseudo. Note that this
7740 loop also takes care of deleting output_reload_insn. */
7741 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7743 rtx set = single_set (i2);
7745 if (set != 0 && SET_DEST (set) == reg)
7747 delete_address_reloads (i2, insn);
7750 if (GET_CODE (i2) == CODE_LABEL
7751 || GET_CODE (i2) == JUMP_INSN)
7755 /* For the debugging info, say the pseudo lives in this reload reg. */
7756 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7757 alter_reg (REGNO (reg), -1);
7761 delete_address_reloads (output_reload_insn, insn);
7762 delete_insn (output_reload_insn);
7766 /* We are going to delete DEAD_INSN. Recursively delete loads of
7767 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7768 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7770 delete_address_reloads (dead_insn, current_insn)
7771 rtx dead_insn, current_insn;
7773 rtx set = single_set (dead_insn);
7774 rtx set2, dst, prev, next;
7777 rtx dst = SET_DEST (set);
7778 if (GET_CODE (dst) == MEM)
7779 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7781 /* If we deleted the store from a reloaded post_{in,de}c expression,
7782 we can delete the matching adds. */
7783 prev = PREV_INSN (dead_insn);
7784 next = NEXT_INSN (dead_insn);
7785 if (! prev || ! next)
7787 set = single_set (next);
7788 set2 = single_set (prev);
7790 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7791 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7792 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7794 dst = SET_DEST (set);
7795 if (! rtx_equal_p (dst, SET_DEST (set2))
7796 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7797 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7798 || (INTVAL (XEXP (SET_SRC (set), 1))
7799 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7801 delete_related_insns (prev);
7802 delete_related_insns (next);
7805 /* Subfunction of delete_address_reloads: process registers found in X. */
7807 delete_address_reloads_1 (dead_insn, x, current_insn)
7808 rtx dead_insn, x, current_insn;
7810 rtx prev, set, dst, i2;
7812 enum rtx_code code = GET_CODE (x);
7816 const char *fmt = GET_RTX_FORMAT (code);
7817 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7820 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7821 else if (fmt[i] == 'E')
7823 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7824 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7831 if (spill_reg_order[REGNO (x)] < 0)
7834 /* Scan backwards for the insn that sets x. This might be a way back due
7836 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7838 code = GET_CODE (prev);
7839 if (code == CODE_LABEL || code == JUMP_INSN)
7841 if (GET_RTX_CLASS (code) != 'i')
7843 if (reg_set_p (x, PATTERN (prev)))
7845 if (reg_referenced_p (x, PATTERN (prev)))
7848 if (! prev || INSN_UID (prev) < reload_first_uid)
7850 /* Check that PREV only sets the reload register. */
7851 set = single_set (prev);
7854 dst = SET_DEST (set);
7855 if (GET_CODE (dst) != REG
7856 || ! rtx_equal_p (dst, x))
7858 if (! reg_set_p (dst, PATTERN (dead_insn)))
7860 /* Check if DST was used in a later insn -
7861 it might have been inherited. */
7862 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7864 if (GET_CODE (i2) == CODE_LABEL)
7868 if (reg_referenced_p (dst, PATTERN (i2)))
7870 /* If there is a reference to the register in the current insn,
7871 it might be loaded in a non-inherited reload. If no other
7872 reload uses it, that means the register is set before
7874 if (i2 == current_insn)
7876 for (j = n_reloads - 1; j >= 0; j--)
7877 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7878 || reload_override_in[j] == dst)
7880 for (j = n_reloads - 1; j >= 0; j--)
7881 if (rld[j].in && rld[j].reg_rtx == dst)
7888 if (GET_CODE (i2) == JUMP_INSN)
7890 /* If DST is still live at CURRENT_INSN, check if it is used for
7891 any reload. Note that even if CURRENT_INSN sets DST, we still
7892 have to check the reloads. */
7893 if (i2 == current_insn)
7895 for (j = n_reloads - 1; j >= 0; j--)
7896 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7897 || reload_override_in[j] == dst)
7899 /* ??? We can't finish the loop here, because dst might be
7900 allocated to a pseudo in this block if no reload in this
7901 block needs any of the classes containing DST - see
7902 spill_hard_reg. There is no easy way to tell this, so we
7903 have to scan till the end of the basic block. */
7905 if (reg_set_p (dst, PATTERN (i2)))
7909 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7910 reg_reloaded_contents[REGNO (dst)] = -1;
7914 /* Output reload-insns to reload VALUE into RELOADREG.
7915 VALUE is an autoincrement or autodecrement RTX whose operand
7916 is a register or memory location;
7917 so reloading involves incrementing that location.
7918 IN is either identical to VALUE, or some cheaper place to reload from.
7920 INC_AMOUNT is the number to increment or decrement by (always positive).
7921 This cannot be deduced from VALUE.
7923 Return the instruction that stores into RELOADREG. */
7926 inc_for_reload (reloadreg, in, value, inc_amount)
7931 /* REG or MEM to be copied and incremented. */
7932 rtx incloc = XEXP (value, 0);
7933 /* Nonzero if increment after copying. */
7934 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7940 rtx real_in = in == value ? XEXP (in, 0) : in;
7942 /* No hard register is equivalent to this register after
7943 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7944 we could inc/dec that register as well (maybe even using it for
7945 the source), but I'm not sure it's worth worrying about. */
7946 if (GET_CODE (incloc) == REG)
7947 reg_last_reload_reg[REGNO (incloc)] = 0;
7949 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7950 inc_amount = -inc_amount;
7952 inc = GEN_INT (inc_amount);
7954 /* If this is post-increment, first copy the location to the reload reg. */
7955 if (post && real_in != reloadreg)
7956 emit_insn (gen_move_insn (reloadreg, real_in));
7960 /* See if we can directly increment INCLOC. Use a method similar to
7961 that in gen_reload. */
7963 last = get_last_insn ();
7964 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7965 gen_rtx_PLUS (GET_MODE (incloc),
7968 code = recog_memoized (add_insn);
7971 extract_insn (add_insn);
7972 if (constrain_operands (1))
7974 /* If this is a pre-increment and we have incremented the value
7975 where it lives, copy the incremented value to RELOADREG to
7976 be used as an address. */
7979 emit_insn (gen_move_insn (reloadreg, incloc));
7984 delete_insns_since (last);
7987 /* If couldn't do the increment directly, must increment in RELOADREG.
7988 The way we do this depends on whether this is pre- or post-increment.
7989 For pre-increment, copy INCLOC to the reload register, increment it
7990 there, then save back. */
7994 if (in != reloadreg)
7995 emit_insn (gen_move_insn (reloadreg, real_in));
7996 emit_insn (gen_add2_insn (reloadreg, inc));
7997 store = emit_insn (gen_move_insn (incloc, reloadreg));
8002 Because this might be a jump insn or a compare, and because RELOADREG
8003 may not be available after the insn in an input reload, we must do
8004 the incrementation before the insn being reloaded for.
8006 We have already copied IN to RELOADREG. Increment the copy in
8007 RELOADREG, save that back, then decrement RELOADREG so it has
8008 the original value. */
8010 emit_insn (gen_add2_insn (reloadreg, inc));
8011 store = emit_insn (gen_move_insn (incloc, reloadreg));
8012 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8019 /* See whether a single set SET is a noop. */
8021 reload_cse_noop_set_p (set)
8024 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
8027 /* Try to simplify INSN. */
8029 reload_cse_simplify (insn, testreg)
8033 rtx body = PATTERN (insn);
8035 if (GET_CODE (body) == SET)
8039 /* Simplify even if we may think it is a no-op.
8040 We may think a memory load of a value smaller than WORD_SIZE
8041 is redundant because we haven't taken into account possible
8042 implicit extension. reload_cse_simplify_set() will bring
8043 this out, so it's safer to simplify before we delete. */
8044 count += reload_cse_simplify_set (body, insn);
8046 if (!count && reload_cse_noop_set_p (body))
8048 rtx value = SET_DEST (body);
8050 && ! REG_FUNCTION_VALUE_P (value))
8052 delete_insn_and_edges (insn);
8057 apply_change_group ();
8059 reload_cse_simplify_operands (insn, testreg);
8061 else if (GET_CODE (body) == PARALLEL)
8065 rtx value = NULL_RTX;
8067 /* If every action in a PARALLEL is a noop, we can delete
8068 the entire PARALLEL. */
8069 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8071 rtx part = XVECEXP (body, 0, i);
8072 if (GET_CODE (part) == SET)
8074 if (! reload_cse_noop_set_p (part))
8076 if (REG_P (SET_DEST (part))
8077 && REG_FUNCTION_VALUE_P (SET_DEST (part)))
8081 value = SET_DEST (part);
8084 else if (GET_CODE (part) != CLOBBER)
8090 delete_insn_and_edges (insn);
8091 /* We're done with this insn. */
8095 /* It's not a no-op, but we can try to simplify it. */
8096 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8097 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8098 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8101 apply_change_group ();
8103 reload_cse_simplify_operands (insn, testreg);
8107 /* Do a very simple CSE pass over the hard registers.
8109 This function detects no-op moves where we happened to assign two
8110 different pseudo-registers to the same hard register, and then
8111 copied one to the other. Reload will generate a useless
8112 instruction copying a register to itself.
8114 This function also detects cases where we load a value from memory
8115 into two different registers, and (if memory is more expensive than
8116 registers) changes it to simply copy the first register into the
8119 Another optimization is performed that scans the operands of each
8120 instruction to see whether the value is already available in a
8121 hard register. It then replaces the operand with the hard register
8122 if possible, much like an optional reload would. */
8125 reload_cse_regs_1 (first)
8129 rtx testreg = gen_rtx_REG (VOIDmode, -1);
8132 init_alias_analysis ();
8134 for (insn = first; insn; insn = NEXT_INSN (insn))
8137 reload_cse_simplify (insn, testreg);
8139 cselib_process_insn (insn);
8143 end_alias_analysis ();
8147 /* Call cse / combine like post-reload optimization phases.
8148 FIRST is the first instruction. */
8150 reload_cse_regs (first)
8153 reload_cse_regs_1 (first);
8155 reload_cse_move2add (first);
8156 if (flag_expensive_optimizations)
8157 reload_cse_regs_1 (first);
8160 /* Try to simplify a single SET instruction. SET is the set pattern.
8161 INSN is the instruction it came from.
8162 This function only handles one case: if we set a register to a value
8163 which is not a register, we try to find that value in some other register
8164 and change the set into a register copy. */
8167 reload_cse_simplify_set (set, insn)
8174 enum reg_class dclass;
8177 struct elt_loc_list *l;
8178 #ifdef LOAD_EXTEND_OP
8179 enum rtx_code extend_op = NIL;
8182 dreg = true_regnum (SET_DEST (set));
8186 src = SET_SRC (set);
8187 if (side_effects_p (src) || true_regnum (src) >= 0)
8190 dclass = REGNO_REG_CLASS (dreg);
8192 #ifdef LOAD_EXTEND_OP
8193 /* When replacing a memory with a register, we need to honor assumptions
8194 that combine made wrt the contents of sign bits. We'll do this by
8195 generating an extend instruction instead of a reg->reg copy. Thus
8196 the destination must be a register that we can widen. */
8197 if (GET_CODE (src) == MEM
8198 && GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD
8199 && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != NIL
8200 && GET_CODE (SET_DEST (set)) != REG)
8204 /* If memory loads are cheaper than register copies, don't change them. */
8205 if (GET_CODE (src) == MEM)
8206 old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
8207 else if (CONSTANT_P (src))
8208 old_cost = rtx_cost (src, SET);
8209 else if (GET_CODE (src) == REG)
8210 old_cost = REGISTER_MOVE_COST (GET_MODE (src),
8211 REGNO_REG_CLASS (REGNO (src)), dclass);
8214 old_cost = rtx_cost (src, SET);
8216 val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0);
8219 for (l = val->locs; l; l = l->next)
8221 rtx this_rtx = l->loc;
8224 if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0))
8226 #ifdef LOAD_EXTEND_OP
8227 if (extend_op != NIL)
8229 HOST_WIDE_INT this_val;
8231 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
8232 constants, such as SYMBOL_REF, cannot be extended. */
8233 if (GET_CODE (this_rtx) != CONST_INT)
8236 this_val = INTVAL (this_rtx);
8240 this_val &= GET_MODE_MASK (GET_MODE (src));
8243 /* ??? In theory we're already extended. */
8244 if (this_val == trunc_int_for_mode (this_val, GET_MODE (src)))
8249 this_rtx = GEN_INT (this_val);
8252 this_cost = rtx_cost (this_rtx, SET);
8254 else if (GET_CODE (this_rtx) == REG)
8256 #ifdef LOAD_EXTEND_OP
8257 if (extend_op != NIL)
8259 this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx);
8260 this_cost = rtx_cost (this_rtx, SET);
8264 this_cost = REGISTER_MOVE_COST (GET_MODE (this_rtx),
8265 REGNO_REG_CLASS (REGNO (this_rtx)),
8271 /* If equal costs, prefer registers over anything else. That
8272 tends to lead to smaller instructions on some machines. */
8273 if (this_cost < old_cost
8274 || (this_cost == old_cost
8275 && GET_CODE (this_rtx) == REG
8276 && GET_CODE (SET_SRC (set)) != REG))
8278 #ifdef LOAD_EXTEND_OP
8279 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD
8280 && extend_op != NIL)
8282 rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set)));
8283 ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set));
8284 validate_change (insn, &SET_DEST (set), wide_dest, 1);
8288 validate_change (insn, &SET_SRC (set), copy_rtx (this_rtx), 1);
8289 old_cost = this_cost, did_change = 1;
8296 /* Try to replace operands in INSN with equivalent values that are already
8297 in registers. This can be viewed as optional reloading.
8299 For each non-register operand in the insn, see if any hard regs are
8300 known to be equivalent to that operand. Record the alternatives which
8301 can accept these hard registers. Among all alternatives, select the
8302 ones which are better or equal to the one currently matching, where
8303 "better" is in terms of '?' and '!' constraints. Among the remaining
8304 alternatives, select the one which replaces most operands with
8308 reload_cse_simplify_operands (insn, testreg)
8314 /* For each operand, all registers that are equivalent to it. */
8315 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
8317 const char *constraints[MAX_RECOG_OPERANDS];
8319 /* Vector recording how bad an alternative is. */
8320 int *alternative_reject;
8321 /* Vector recording how many registers can be introduced by choosing
8322 this alternative. */
8323 int *alternative_nregs;
8324 /* Array of vectors recording, for each operand and each alternative,
8325 which hard register to substitute, or -1 if the operand should be
8327 int *op_alt_regno[MAX_RECOG_OPERANDS];
8328 /* Array of alternatives, sorted in order of decreasing desirability. */
8329 int *alternative_order;
8331 extract_insn (insn);
8333 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8336 /* Figure out which alternative currently matches. */
8337 if (! constrain_operands (1))
8338 fatal_insn_not_found (insn);
8340 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8341 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8342 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8343 memset ((char *) alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
8344 memset ((char *) alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
8346 /* For each operand, find out which regs are equivalent. */
8347 for (i = 0; i < recog_data.n_operands; i++)
8350 struct elt_loc_list *l;
8352 CLEAR_HARD_REG_SET (equiv_regs[i]);
8354 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8355 right, so avoid the problem here. Likewise if we have a constant
8356 and the insn pattern doesn't tell us the mode we need. */
8357 if (GET_CODE (recog_data.operand[i]) == CODE_LABEL
8358 || (CONSTANT_P (recog_data.operand[i])
8359 && recog_data.operand_mode[i] == VOIDmode))
8362 v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0);
8366 for (l = v->locs; l; l = l->next)
8367 if (GET_CODE (l->loc) == REG)
8368 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
8371 for (i = 0; i < recog_data.n_operands; i++)
8373 enum machine_mode mode;
8377 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8378 for (j = 0; j < recog_data.n_alternatives; j++)
8379 op_alt_regno[i][j] = -1;
8381 p = constraints[i] = recog_data.constraints[i];
8382 mode = recog_data.operand_mode[i];
8384 /* Add the reject values for each alternative given by the constraints
8385 for this operand. */
8393 alternative_reject[j] += 3;
8395 alternative_reject[j] += 300;
8398 /* We won't change operands which are already registers. We
8399 also don't want to modify output operands. */
8400 regno = true_regnum (recog_data.operand[i]);
8402 || constraints[i][0] == '='
8403 || constraints[i][0] == '+')
8406 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8408 int class = (int) NO_REGS;
8410 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
8413 REGNO (testreg) = regno;
8414 PUT_MODE (testreg, mode);
8416 /* We found a register equal to this operand. Now look for all
8417 alternatives that can accept this register and have not been
8418 assigned a register they can use yet. */
8427 case '=': case '+': case '?':
8428 case '#': case '&': case '!':
8430 case '0': case '1': case '2': case '3': case '4':
8431 case '5': case '6': case '7': case '8': case '9':
8432 case 'm': case '<': case '>': case 'V': case 'o':
8433 case 'E': case 'F': case 'G': case 'H':
8434 case 's': case 'i': case 'n':
8435 case 'I': case 'J': case 'K': case 'L':
8436 case 'M': case 'N': case 'O': case 'P':
8438 /* These don't say anything we care about. */
8442 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8447 = (reg_class_subunion
8449 [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c, p)]);
8452 case ',': case '\0':
8453 /* See if REGNO fits this alternative, and set it up as the
8454 replacement register if we don't have one for this
8455 alternative yet and the operand being replaced is not
8456 a cheap CONST_INT. */
8457 if (op_alt_regno[i][j] == -1
8458 && reg_fits_class_p (testreg, class, 0, mode)
8459 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8460 || (rtx_cost (recog_data.operand[i], SET)
8461 > rtx_cost (testreg, SET))))
8463 alternative_nregs[j]++;
8464 op_alt_regno[i][j] = regno;
8469 p += CONSTRAINT_LEN (c, p);
8477 /* Record all alternatives which are better or equal to the currently
8478 matching one in the alternative_order array. */
8479 for (i = j = 0; i < recog_data.n_alternatives; i++)
8480 if (alternative_reject[i] <= alternative_reject[which_alternative])
8481 alternative_order[j++] = i;
8482 recog_data.n_alternatives = j;
8484 /* Sort it. Given a small number of alternatives, a dumb algorithm
8485 won't hurt too much. */
8486 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8489 int best_reject = alternative_reject[alternative_order[i]];
8490 int best_nregs = alternative_nregs[alternative_order[i]];
8493 for (j = i + 1; j < recog_data.n_alternatives; j++)
8495 int this_reject = alternative_reject[alternative_order[j]];
8496 int this_nregs = alternative_nregs[alternative_order[j]];
8498 if (this_reject < best_reject
8499 || (this_reject == best_reject && this_nregs < best_nregs))
8502 best_reject = this_reject;
8503 best_nregs = this_nregs;
8507 tmp = alternative_order[best];
8508 alternative_order[best] = alternative_order[i];
8509 alternative_order[i] = tmp;
8512 /* Substitute the operands as determined by op_alt_regno for the best
8514 j = alternative_order[0];
8516 for (i = 0; i < recog_data.n_operands; i++)
8518 enum machine_mode mode = recog_data.operand_mode[i];
8519 if (op_alt_regno[i][j] == -1)
8522 validate_change (insn, recog_data.operand_loc[i],
8523 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8526 for (i = recog_data.n_dups - 1; i >= 0; i--)
8528 int op = recog_data.dup_num[i];
8529 enum machine_mode mode = recog_data.operand_mode[op];
8531 if (op_alt_regno[op][j] == -1)
8534 validate_change (insn, recog_data.dup_loc[i],
8535 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8538 return apply_change_group ();
8541 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8543 This code might also be useful when reload gave up on reg+reg addressing
8544 because of clashes between the return register and INDEX_REG_CLASS. */
8546 /* The maximum number of uses of a register we can keep track of to
8547 replace them with reg+reg addressing. */
8548 #define RELOAD_COMBINE_MAX_USES 6
8550 /* INSN is the insn where a register has ben used, and USEP points to the
8551 location of the register within the rtl. */
8552 struct reg_use { rtx insn, *usep; };
8554 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8555 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8556 indicates where it becomes live again.
8557 Otherwise, USE_INDEX is the index of the last encountered use of the
8558 register (which is first among these we have seen since we scan backwards),
8559 OFFSET contains the constant offset that is added to the register in
8560 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8561 last, of these uses.
8562 STORE_RUID is always meaningful if we only want to use a value in a
8563 register in a different place: it denotes the next insn in the insn
8564 stream (i.e. the last encountered) that sets or clobbers the register. */
8567 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8572 } reg_state[FIRST_PSEUDO_REGISTER];
8574 /* Reverse linear uid. This is increased in reload_combine while scanning
8575 the instructions from last to first. It is used to set last_label_ruid
8576 and the store_ruid / use_ruid fields in reg_state. */
8577 static int reload_combine_ruid;
8579 #define LABEL_LIVE(LABEL) \
8580 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8586 int first_index_reg = -1;
8587 int last_index_reg = 0;
8591 int last_label_ruid;
8592 int min_labelno, n_labels;
8593 HARD_REG_SET ever_live_at_start, *label_live;
8595 /* If reg+reg can be used in offsetable memory addresses, the main chunk of
8596 reload has already used it where appropriate, so there is no use in
8597 trying to generate it now. */
8598 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8601 /* To avoid wasting too much time later searching for an index register,
8602 determine the minimum and maximum index register numbers. */
8603 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8604 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
8606 if (first_index_reg == -1)
8607 first_index_reg = r;
8612 /* If no index register is available, we can quit now. */
8613 if (first_index_reg == -1)
8616 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8617 information is a bit fuzzy immediately after reload, but it's
8618 still good enough to determine which registers are live at a jump
8620 min_labelno = get_first_label_num ();
8621 n_labels = max_label_num () - min_labelno;
8622 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8623 CLEAR_HARD_REG_SET (ever_live_at_start);
8625 FOR_EACH_BB_REVERSE (bb)
8628 if (GET_CODE (insn) == CODE_LABEL)
8632 REG_SET_TO_HARD_REG_SET (live,
8633 bb->global_live_at_start);
8634 compute_use_by_pseudos (&live,
8635 bb->global_live_at_start);
8636 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8637 IOR_HARD_REG_SET (ever_live_at_start, live);
8641 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8642 last_label_ruid = reload_combine_ruid = 0;
8643 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8645 reg_state[r].store_ruid = reload_combine_ruid;
8647 reg_state[r].use_index = -1;
8649 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8652 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8656 /* We cannot do our optimization across labels. Invalidating all the use
8657 information we have would be costly, so we just note where the label
8658 is and then later disable any optimization that would cross it. */
8659 if (GET_CODE (insn) == CODE_LABEL)
8660 last_label_ruid = reload_combine_ruid;
8661 else if (GET_CODE (insn) == BARRIER)
8662 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8663 if (! fixed_regs[r])
8664 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8666 if (! INSN_P (insn))
8669 reload_combine_ruid++;
8671 /* Look for (set (REGX) (CONST_INT))
8672 (set (REGX) (PLUS (REGX) (REGY)))
8674 ... (MEM (REGX)) ...
8676 (set (REGZ) (CONST_INT))
8678 ... (MEM (PLUS (REGZ) (REGY)))... .
8680 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8681 and that we know all uses of REGX before it dies. */
8682 set = single_set (insn);
8684 && GET_CODE (SET_DEST (set)) == REG
8685 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
8686 GET_MODE (SET_DEST (set)))
8688 && GET_CODE (SET_SRC (set)) == PLUS
8689 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
8690 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
8691 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
8693 rtx reg = SET_DEST (set);
8694 rtx plus = SET_SRC (set);
8695 rtx base = XEXP (plus, 1);
8696 rtx prev = prev_nonnote_insn (insn);
8697 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
8698 unsigned int regno = REGNO (reg);
8699 rtx const_reg = NULL_RTX;
8700 rtx reg_sum = NULL_RTX;
8702 /* Now, we need an index register.
8703 We'll set index_reg to this index register, const_reg to the
8704 register that is to be loaded with the constant
8705 (denoted as REGZ in the substitution illustration above),
8706 and reg_sum to the register-register that we want to use to
8707 substitute uses of REG (typically in MEMs) with.
8708 First check REG and BASE for being index registers;
8709 we can use them even if they are not dead. */
8710 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
8711 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8719 /* Otherwise, look for a free index register. Since we have
8720 checked above that neiter REG nor BASE are index registers,
8721 if we find anything at all, it will be different from these
8723 for (i = first_index_reg; i <= last_index_reg; i++)
8725 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8727 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
8728 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
8729 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
8731 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
8733 const_reg = index_reg;
8734 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
8740 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8741 (REGY), i.e. BASE, is not clobbered before the last use we'll
8744 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
8745 && rtx_equal_p (SET_DEST (prev_set), reg)
8746 && reg_state[regno].use_index >= 0
8747 && (reg_state[REGNO (base)].store_ruid
8748 <= reg_state[regno].use_ruid)
8753 /* Change destination register and, if necessary, the
8754 constant value in PREV, the constant loading instruction. */
8755 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
8756 if (reg_state[regno].offset != const0_rtx)
8757 validate_change (prev,
8758 &SET_SRC (prev_set),
8759 GEN_INT (INTVAL (SET_SRC (prev_set))
8760 + INTVAL (reg_state[regno].offset)),
8763 /* Now for every use of REG that we have recorded, replace REG
8765 for (i = reg_state[regno].use_index;
8766 i < RELOAD_COMBINE_MAX_USES; i++)
8767 validate_change (reg_state[regno].reg_use[i].insn,
8768 reg_state[regno].reg_use[i].usep,
8769 /* Each change must have its own
8771 copy_rtx (reg_sum), 1);
8773 if (apply_change_group ())
8777 /* Delete the reg-reg addition. */
8780 if (reg_state[regno].offset != const0_rtx)
8781 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8783 for (np = ®_NOTES (prev); *np;)
8785 if (REG_NOTE_KIND (*np) == REG_EQUAL
8786 || REG_NOTE_KIND (*np) == REG_EQUIV)
8787 *np = XEXP (*np, 1);
8789 np = &XEXP (*np, 1);
8792 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8793 reg_state[REGNO (const_reg)].store_ruid
8794 = reload_combine_ruid;
8800 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
8802 if (GET_CODE (insn) == CALL_INSN)
8806 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8807 if (call_used_regs[r])
8809 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8810 reg_state[r].store_ruid = reload_combine_ruid;
8813 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
8814 link = XEXP (link, 1))
8816 rtx usage_rtx = XEXP (XEXP (link, 0), 0);
8817 if (GET_CODE (usage_rtx) == REG)
8820 unsigned int start_reg = REGNO (usage_rtx);
8821 unsigned int num_regs =
8822 HARD_REGNO_NREGS (start_reg, GET_MODE (usage_rtx));
8823 unsigned int end_reg = start_reg + num_regs - 1;
8824 for (i = start_reg; i <= end_reg; i++)
8825 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
8827 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8828 reg_state[i].store_ruid = reload_combine_ruid;
8831 reg_state[i].use_index = -1;
8836 else if (GET_CODE (insn) == JUMP_INSN
8837 && GET_CODE (PATTERN (insn)) != RETURN)
8839 /* Non-spill registers might be used at the call destination in
8840 some unknown fashion, so we have to mark the unknown use. */
8843 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
8844 && JUMP_LABEL (insn))
8845 live = &LABEL_LIVE (JUMP_LABEL (insn));
8847 live = &ever_live_at_start;
8849 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8850 if (TEST_HARD_REG_BIT (*live, i))
8851 reg_state[i].use_index = -1;
8854 reload_combine_note_use (&PATTERN (insn), insn);
8855 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8857 if (REG_NOTE_KIND (note) == REG_INC
8858 && GET_CODE (XEXP (note, 0)) == REG)
8860 int regno = REGNO (XEXP (note, 0));
8862 reg_state[regno].store_ruid = reload_combine_ruid;
8863 reg_state[regno].use_index = -1;
8871 /* Check if DST is a register or a subreg of a register; if it is,
8872 update reg_state[regno].store_ruid and reg_state[regno].use_index
8873 accordingly. Called via note_stores from reload_combine. */
8876 reload_combine_note_store (dst, set, data)
8878 void *data ATTRIBUTE_UNUSED;
8882 enum machine_mode mode = GET_MODE (dst);
8884 if (GET_CODE (dst) == SUBREG)
8886 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
8887 GET_MODE (SUBREG_REG (dst)),
8890 dst = SUBREG_REG (dst);
8892 if (GET_CODE (dst) != REG)
8894 regno += REGNO (dst);
8896 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8897 careful with registers / register parts that are not full words.
8899 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8900 if (GET_CODE (set) != SET
8901 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
8902 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
8903 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
8905 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8907 reg_state[i].use_index = -1;
8908 reg_state[i].store_ruid = reload_combine_ruid;
8913 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8915 reg_state[i].store_ruid = reload_combine_ruid;
8916 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8921 /* XP points to a piece of rtl that has to be checked for any uses of
8923 *XP is the pattern of INSN, or a part of it.
8924 Called from reload_combine, and recursively by itself. */
8926 reload_combine_note_use (xp, insn)
8930 enum rtx_code code = x->code;
8933 rtx offset = const0_rtx; /* For the REG case below. */
8938 if (GET_CODE (SET_DEST (x)) == REG)
8940 reload_combine_note_use (&SET_SRC (x), insn);
8946 /* If this is the USE of a return value, we can't change it. */
8947 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
8949 /* Mark the return register as used in an unknown fashion. */
8950 rtx reg = XEXP (x, 0);
8951 int regno = REGNO (reg);
8952 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
8954 while (--nregs >= 0)
8955 reg_state[regno + nregs].use_index = -1;
8961 if (GET_CODE (SET_DEST (x)) == REG)
8963 /* No spurious CLOBBERs of pseudo registers may remain. */
8964 if (REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER)
8971 /* We are interested in (plus (reg) (const_int)) . */
8972 if (GET_CODE (XEXP (x, 0)) != REG
8973 || GET_CODE (XEXP (x, 1)) != CONST_INT)
8975 offset = XEXP (x, 1);
8980 int regno = REGNO (x);
8984 /* No spurious USEs of pseudo registers may remain. */
8985 if (regno >= FIRST_PSEUDO_REGISTER)
8988 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x));
8990 /* We can't substitute into multi-hard-reg uses. */
8993 while (--nregs >= 0)
8994 reg_state[regno + nregs].use_index = -1;
8998 /* If this register is already used in some unknown fashion, we
9000 If we decrement the index from zero to -1, we can't store more
9001 uses, so this register becomes used in an unknown fashion. */
9002 use_index = --reg_state[regno].use_index;
9006 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
9008 /* We have found another use for a register that is already
9009 used later. Check if the offsets match; if not, mark the
9010 register as used in an unknown fashion. */
9011 if (! rtx_equal_p (offset, reg_state[regno].offset))
9013 reg_state[regno].use_index = -1;
9019 /* This is the first use of this register we have seen since we
9020 marked it as dead. */
9021 reg_state[regno].offset = offset;
9022 reg_state[regno].use_ruid = reload_combine_ruid;
9024 reg_state[regno].reg_use[use_index].insn = insn;
9025 reg_state[regno].reg_use[use_index].usep = xp;
9033 /* Recursively process the components of X. */
9034 fmt = GET_RTX_FORMAT (code);
9035 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9038 reload_combine_note_use (&XEXP (x, i), insn);
9039 else if (fmt[i] == 'E')
9041 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9042 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9047 /* See if we can reduce the cost of a constant by replacing a move
9048 with an add. We track situations in which a register is set to a
9049 constant or to a register plus a constant. */
9050 /* We cannot do our optimization across labels. Invalidating all the
9051 information about register contents we have would be costly, so we
9052 use move2add_last_label_luid to note where the label is and then
9053 later disable any optimization that would cross it.
9054 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9055 reg_set_luid[n] is greater than last_label_luid[n] . */
9056 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9058 /* If reg_base_reg[n] is negative, register n has been set to
9059 reg_offset[n] in mode reg_mode[n] .
9060 If reg_base_reg[n] is non-negative, register n has been set to the
9061 sum of reg_offset[n] and the value of register reg_base_reg[n]
9062 before reg_set_luid[n], calculated in mode reg_mode[n] . */
9063 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
9064 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9065 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9067 /* move2add_luid is linearly increased while scanning the instructions
9068 from first to last. It is used to set reg_set_luid in
9069 reload_cse_move2add and move2add_note_store. */
9070 static int move2add_luid;
9072 /* move2add_last_label_luid is set whenever a label is found. Labels
9073 invalidate all previously collected reg_offset data. */
9074 static int move2add_last_label_luid;
9076 /* Generate a CONST_INT and force it in the range of MODE. */
9078 static HOST_WIDE_INT
9079 sext_for_mode (mode, value)
9080 enum machine_mode mode;
9081 HOST_WIDE_INT value;
9083 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
9084 int width = GET_MODE_BITSIZE (mode);
9086 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
9088 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
9089 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
9090 cval |= (HOST_WIDE_INT) -1 << width;
9095 /* ??? We don't know how zero / sign extension is handled, hence we
9096 can't go from a narrower to a wider mode. */
9097 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
9098 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
9099 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
9100 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \
9101 GET_MODE_BITSIZE (INMODE))))
9104 reload_cse_move2add (first)
9110 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9111 reg_set_luid[i] = 0;
9113 move2add_last_label_luid = 0;
9115 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
9119 if (GET_CODE (insn) == CODE_LABEL)
9121 move2add_last_label_luid = move2add_luid;
9122 /* We're going to increment move2add_luid twice after a
9123 label, so that we can use move2add_last_label_luid + 1 as
9124 the luid for constants. */
9128 if (! INSN_P (insn))
9130 pat = PATTERN (insn);
9131 /* For simplicity, we only perform this optimization on
9132 straightforward SETs. */
9133 if (GET_CODE (pat) == SET
9134 && GET_CODE (SET_DEST (pat)) == REG)
9136 rtx reg = SET_DEST (pat);
9137 int regno = REGNO (reg);
9138 rtx src = SET_SRC (pat);
9140 /* Check if we have valid information on the contents of this
9141 register in the mode of REG. */
9142 if (reg_set_luid[regno] > move2add_last_label_luid
9143 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno]))
9145 /* Try to transform (set (REGX) (CONST_INT A))
9147 (set (REGX) (CONST_INT B))
9149 (set (REGX) (CONST_INT A))
9151 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9153 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
9156 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9158 - reg_offset[regno]));
9159 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9160 use (set (reg) (reg)) instead.
9161 We don't delete this insn, nor do we convert it into a
9162 note, to avoid losing register notes or the return
9163 value flag. jump2 already knows how to get rid of
9165 if (new_src == const0_rtx)
9166 success = validate_change (insn, &SET_SRC (pat), reg, 0);
9167 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
9168 && have_add2_insn (reg, new_src))
9169 success = validate_change (insn, &PATTERN (insn),
9170 gen_add2_insn (reg, new_src), 0);
9171 reg_set_luid[regno] = move2add_luid;
9172 reg_mode[regno] = GET_MODE (reg);
9173 reg_offset[regno] = INTVAL (src);
9177 /* Try to transform (set (REGX) (REGY))
9178 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9181 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9184 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9186 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9187 else if (GET_CODE (src) == REG
9188 && reg_set_luid[regno] == reg_set_luid[REGNO (src)]
9189 && reg_base_reg[regno] == reg_base_reg[REGNO (src)]
9190 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg),
9191 reg_mode[REGNO (src)]))
9193 rtx next = next_nonnote_insn (insn);
9196 set = single_set (next);
9198 && SET_DEST (set) == reg
9199 && GET_CODE (SET_SRC (set)) == PLUS
9200 && XEXP (SET_SRC (set), 0) == reg
9201 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9203 rtx src3 = XEXP (SET_SRC (set), 1);
9204 HOST_WIDE_INT added_offset = INTVAL (src3);
9205 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)];
9206 HOST_WIDE_INT regno_offset = reg_offset[regno];
9207 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9213 if (new_src == const0_rtx)
9214 /* See above why we create (set (reg) (reg)) here. */
9216 = validate_change (next, &SET_SRC (set), reg, 0);
9217 else if ((rtx_cost (new_src, PLUS)
9218 < COSTS_N_INSNS (1) + rtx_cost (src3, SET))
9219 && have_add2_insn (reg, new_src))
9221 = validate_change (next, &PATTERN (next),
9222 gen_add2_insn (reg, new_src), 0);
9226 reg_mode[regno] = GET_MODE (reg);
9227 reg_offset[regno] = sext_for_mode (GET_MODE (reg),
9236 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9238 if (REG_NOTE_KIND (note) == REG_INC
9239 && GET_CODE (XEXP (note, 0)) == REG)
9241 /* Reset the information about this register. */
9242 int regno = REGNO (XEXP (note, 0));
9243 if (regno < FIRST_PSEUDO_REGISTER)
9244 reg_set_luid[regno] = 0;
9247 note_stores (PATTERN (insn), move2add_note_store, NULL);
9248 /* If this is a CALL_INSN, all call used registers are stored with
9250 if (GET_CODE (insn) == CALL_INSN)
9252 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9254 if (call_used_regs[i])
9255 /* Reset the information about this register. */
9256 reg_set_luid[i] = 0;
9262 /* SET is a SET or CLOBBER that sets DST.
9263 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9264 Called from reload_cse_move2add via note_stores. */
9267 move2add_note_store (dst, set, data)
9269 void *data ATTRIBUTE_UNUSED;
9271 unsigned int regno = 0;
9273 enum machine_mode mode = GET_MODE (dst);
9275 if (GET_CODE (dst) == SUBREG)
9277 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
9278 GET_MODE (SUBREG_REG (dst)),
9281 dst = SUBREG_REG (dst);
9284 /* Some targets do argument pushes without adding REG_INC notes. */
9286 if (GET_CODE (dst) == MEM)
9288 dst = XEXP (dst, 0);
9289 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC
9290 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC)
9291 reg_set_luid[REGNO (XEXP (dst, 0))] = 0;
9294 if (GET_CODE (dst) != REG)
9297 regno += REGNO (dst);
9299 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9300 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9301 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9302 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9304 rtx src = SET_SRC (set);
9306 HOST_WIDE_INT offset;
9308 /* This may be different from mode, if SET_DEST (set) is a
9310 enum machine_mode dst_mode = GET_MODE (dst);
9312 switch (GET_CODE (src))
9315 if (GET_CODE (XEXP (src, 0)) == REG)
9317 base_reg = XEXP (src, 0);
9319 if (GET_CODE (XEXP (src, 1)) == CONST_INT)
9320 offset = INTVAL (XEXP (src, 1));
9321 else if (GET_CODE (XEXP (src, 1)) == REG
9322 && (reg_set_luid[REGNO (XEXP (src, 1))]
9323 > move2add_last_label_luid)
9324 && (MODES_OK_FOR_MOVE2ADD
9325 (dst_mode, reg_mode[REGNO (XEXP (src, 1))])))
9327 if (reg_base_reg[REGNO (XEXP (src, 1))] < 0)
9328 offset = reg_offset[REGNO (XEXP (src, 1))];
9329 /* Maybe the first register is known to be a
9331 else if (reg_set_luid[REGNO (base_reg)]
9332 > move2add_last_label_luid
9333 && (MODES_OK_FOR_MOVE2ADD
9334 (dst_mode, reg_mode[REGNO (XEXP (src, 1))]))
9335 && reg_base_reg[REGNO (base_reg)] < 0)
9337 offset = reg_offset[REGNO (base_reg)];
9338 base_reg = XEXP (src, 1);
9357 /* Start tracking the register as a constant. */
9358 reg_base_reg[regno] = -1;
9359 reg_offset[regno] = INTVAL (SET_SRC (set));
9360 /* We assign the same luid to all registers set to constants. */
9361 reg_set_luid[regno] = move2add_last_label_luid + 1;
9362 reg_mode[regno] = mode;
9367 /* Invalidate the contents of the register. */
9368 reg_set_luid[regno] = 0;
9372 base_regno = REGNO (base_reg);
9373 /* If information about the base register is not valid, set it
9374 up as a new base register, pretending its value is known
9375 starting from the current insn. */
9376 if (reg_set_luid[base_regno] <= move2add_last_label_luid)
9378 reg_base_reg[base_regno] = base_regno;
9379 reg_offset[base_regno] = 0;
9380 reg_set_luid[base_regno] = move2add_luid;
9381 reg_mode[base_regno] = mode;
9383 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode,
9384 reg_mode[base_regno]))
9387 reg_mode[regno] = mode;
9389 /* Copy base information from our base register. */
9390 reg_set_luid[regno] = reg_set_luid[base_regno];
9391 reg_base_reg[regno] = reg_base_reg[base_regno];
9393 /* Compute the sum of the offsets or constants. */
9394 reg_offset[regno] = sext_for_mode (dst_mode,
9396 + reg_offset[base_regno]);
9400 unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode);
9402 for (i = regno; i < endregno; i++)
9403 /* Reset the information about this register. */
9404 reg_set_luid[i] = 0;
9410 add_auto_inc_notes (insn, x)
9414 enum rtx_code code = GET_CODE (x);
9418 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9421 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9425 /* Scan all the operand sub-expressions. */
9426 fmt = GET_RTX_FORMAT (code);
9427 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9430 add_auto_inc_notes (insn, XEXP (x, i));
9431 else if (fmt[i] == 'E')
9432 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9433 add_auto_inc_notes (insn, XVECEXP (x, i, j));
9438 /* Copy EH notes from an insn to its reloads. */
9440 copy_eh_notes (insn, x)
9444 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
9447 for (; x != 0; x = NEXT_INSN (x))
9449 if (may_trap_p (PATTERN (x)))
9451 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
9457 /* This is used by reload pass, that does emit some instructions after
9458 abnormal calls moving basic block end, but in fact it wants to emit
9459 them on the edge. Looks for abnormal call edges, find backward the
9460 proper call and fix the damage.
9462 Similar handle instructions throwing exceptions internally. */
9464 fixup_abnormal_edges ()
9466 bool inserted = false;
9473 /* Look for cases we are interested in - calls or instructions causing
9475 for (e = bb->succ; e; e = e->succ_next)
9477 if (e->flags & EDGE_ABNORMAL_CALL)
9479 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
9480 == (EDGE_ABNORMAL | EDGE_EH))
9483 if (e && GET_CODE (bb->end) != CALL_INSN && !can_throw_internal (bb->end))
9485 rtx insn = bb->end, stop = NEXT_INSN (bb->end);
9487 for (e = bb->succ; e; e = e->succ_next)
9488 if (e->flags & EDGE_FALLTHRU)
9490 /* Get past the new insns generated. Allow notes, as the insns may
9491 be already deleted. */
9492 while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE)
9493 && !can_throw_internal (insn)
9494 && insn != bb->head)
9495 insn = PREV_INSN (insn);
9496 if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn))
9500 insn = NEXT_INSN (insn);
9501 while (insn && insn != stop)
9503 next = NEXT_INSN (insn);
9508 /* Sometimes there's still the return value USE.
9509 If it's placed after a trapping call (i.e. that
9510 call is the last insn anyway), we have no fallthru
9511 edge. Simply delete this use and don't try to insert
9512 on the non-existent edge. */
9513 if (GET_CODE (PATTERN (insn)) != USE)
9515 /* We're not deleting it, we're moving it. */
9516 INSN_DELETED_P (insn) = 0;
9517 PREV_INSN (insn) = NULL_RTX;
9518 NEXT_INSN (insn) = NULL_RTX;
9520 insert_insn_on_edge (insn, e);
9528 commit_edge_insertions ();
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