1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx *reg_equiv_memory_loc;
105 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
106 collector can keep track of what is inside. */
107 varray_type reg_equiv_memory_loc_varray;
109 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
110 This is used when the address is not valid as a memory address
111 (because its displacement is too big for the machine.) */
112 rtx *reg_equiv_address;
114 /* Element N is the memory slot to which pseudo reg N is equivalent,
115 or zero if pseudo reg N is not equivalent to a memory slot. */
118 /* Widest width in which each pseudo reg is referred to (via subreg). */
119 static unsigned int *reg_max_ref_width;
121 /* Element N is the list of insns that initialized reg N from its equivalent
122 constant or memory slot. */
123 static rtx *reg_equiv_init;
125 /* Vector to remember old contents of reg_renumber before spilling. */
126 static short *reg_old_renumber;
128 /* During reload_as_needed, element N contains the last pseudo regno reloaded
129 into hard register N. If that pseudo reg occupied more than one register,
130 reg_reloaded_contents points to that pseudo for each spill register in
131 use; all of these must remain set for an inheritance to occur. */
132 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
134 /* During reload_as_needed, element N contains the insn for which
135 hard register N was last used. Its contents are significant only
136 when reg_reloaded_valid is set for this register. */
137 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
139 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
140 static HARD_REG_SET reg_reloaded_valid;
141 /* Indicate if the register was dead at the end of the reload.
142 This is only valid if reg_reloaded_contents is set and valid. */
143 static HARD_REG_SET reg_reloaded_dead;
145 /* Indicate whether the register's current value is one that is not
146 safe to retain across a call, even for registers that are normally
148 static HARD_REG_SET reg_reloaded_call_part_clobbered;
150 /* Number of spill-regs so far; number of valid elements of spill_regs. */
153 /* In parallel with spill_regs, contains REG rtx's for those regs.
154 Holds the last rtx used for any given reg, or 0 if it has never
155 been used for spilling yet. This rtx is reused, provided it has
157 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
159 /* In parallel with spill_regs, contains nonzero for a spill reg
160 that was stored after the last time it was used.
161 The precise value is the insn generated to do the store. */
162 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
164 /* This is the register that was stored with spill_reg_store. This is a
165 copy of reload_out / reload_out_reg when the value was stored; if
166 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
167 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
169 /* This table is the inverse mapping of spill_regs:
170 indexed by hard reg number,
171 it contains the position of that reg in spill_regs,
172 or -1 for something that is not in spill_regs.
174 ?!? This is no longer accurate. */
175 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
177 /* This reg set indicates registers that can't be used as spill registers for
178 the currently processed insn. These are the hard registers which are live
179 during the insn, but not allocated to pseudos, as well as fixed
181 static HARD_REG_SET bad_spill_regs;
183 /* These are the hard registers that can't be used as spill register for any
184 insn. This includes registers used for user variables and registers that
185 we can't eliminate. A register that appears in this set also can't be used
186 to retry register allocation. */
187 static HARD_REG_SET bad_spill_regs_global;
189 /* Describes order of use of registers for reloading
190 of spilled pseudo-registers. `n_spills' is the number of
191 elements that are actually valid; new ones are added at the end.
193 Both spill_regs and spill_reg_order are used on two occasions:
194 once during find_reload_regs, where they keep track of the spill registers
195 for a single insn, but also during reload_as_needed where they show all
196 the registers ever used by reload. For the latter case, the information
197 is calculated during finish_spills. */
198 static short spill_regs[FIRST_PSEUDO_REGISTER];
200 /* This vector of reg sets indicates, for each pseudo, which hard registers
201 may not be used for retrying global allocation because the register was
202 formerly spilled from one of them. If we allowed reallocating a pseudo to
203 a register that it was already allocated to, reload might not
205 static HARD_REG_SET *pseudo_previous_regs;
207 /* This vector of reg sets indicates, for each pseudo, which hard
208 registers may not be used for retrying global allocation because they
209 are used as spill registers during one of the insns in which the
211 static HARD_REG_SET *pseudo_forbidden_regs;
213 /* All hard regs that have been used as spill registers for any insn are
214 marked in this set. */
215 static HARD_REG_SET used_spill_regs;
217 /* Index of last register assigned as a spill register. We allocate in
218 a round-robin fashion. */
219 static int last_spill_reg;
221 /* Nonzero if indirect addressing is supported on the machine; this means
222 that spilling (REG n) does not require reloading it into a register in
223 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
224 value indicates the level of indirect addressing supported, e.g., two
225 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
227 static char spill_indirect_levels;
229 /* Nonzero if indirect addressing is supported when the innermost MEM is
230 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
231 which these are valid is the same as spill_indirect_levels, above. */
232 char indirect_symref_ok;
234 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
235 char double_reg_address_ok;
237 /* Record the stack slot for each spilled hard register. */
238 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
240 /* Width allocated so far for that stack slot. */
241 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
243 /* Record which pseudos needed to be spilled. */
244 static regset_head spilled_pseudos;
246 /* Used for communication between order_regs_for_reload and count_pseudo.
247 Used to avoid counting one pseudo twice. */
248 static regset_head pseudos_counted;
250 /* First uid used by insns created by reload in this function.
251 Used in find_equiv_reg. */
252 int reload_first_uid;
254 /* Flag set by local-alloc or global-alloc if anything is live in
255 a call-clobbered reg across calls. */
256 int caller_save_needed;
258 /* Set to 1 while reload_as_needed is operating.
259 Required by some machines to handle any generated moves differently. */
260 int reload_in_progress = 0;
262 /* These arrays record the insn_code of insns that may be needed to
263 perform input and output reloads of special objects. They provide a
264 place to pass a scratch register. */
265 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
266 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
268 /* This obstack is used for allocation of rtl during register elimination.
269 The allocated storage can be freed once find_reloads has processed the
271 struct obstack reload_obstack;
273 /* Points to the beginning of the reload_obstack. All insn_chain structures
274 are allocated first. */
275 static char *reload_startobj;
277 /* The point after all insn_chain structures. Used to quickly deallocate
278 memory allocated in copy_reloads during calculate_needs_all_insns. */
279 static char *reload_firstobj;
281 /* This points before all local rtl generated by register elimination.
282 Used to quickly free all memory after processing one insn. */
283 static char *reload_insn_firstobj;
285 /* List of insn_chain instructions, one for every insn that reload needs to
287 struct insn_chain *reload_insn_chain;
289 /* List of all insns needing reloads. */
290 static struct insn_chain *insns_need_reload;
292 /* This structure is used to record information about register eliminations.
293 Each array entry describes one possible way of eliminating a register
294 in favor of another. If there is more than one way of eliminating a
295 particular register, the most preferred should be specified first. */
299 int from; /* Register number to be eliminated. */
300 int to; /* Register number used as replacement. */
301 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
302 int can_eliminate; /* Nonzero if this elimination can be done. */
303 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
304 insns made by reload. */
305 HOST_WIDE_INT offset; /* Current offset between the two regs. */
306 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
307 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
308 rtx from_rtx; /* REG rtx for the register to be eliminated.
309 We cannot simply compare the number since
310 we might then spuriously replace a hard
311 register corresponding to a pseudo
312 assigned to the reg to be eliminated. */
313 rtx to_rtx; /* REG rtx for the replacement. */
316 static struct elim_table *reg_eliminate = 0;
318 /* This is an intermediate structure to initialize the table. It has
319 exactly the members provided by ELIMINABLE_REGS. */
320 static const struct elim_table_1
324 } reg_eliminate_1[] =
326 /* If a set of eliminable registers was specified, define the table from it.
327 Otherwise, default to the normal case of the frame pointer being
328 replaced by the stack pointer. */
330 #ifdef ELIMINABLE_REGS
333 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
336 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
338 /* Record the number of pending eliminations that have an offset not equal
339 to their initial offset. If nonzero, we use a new copy of each
340 replacement result in any insns encountered. */
341 int num_not_at_initial_offset;
343 /* Count the number of registers that we may be able to eliminate. */
344 static int num_eliminable;
345 /* And the number of registers that are equivalent to a constant that
346 can be eliminated to frame_pointer / arg_pointer + constant. */
347 static int num_eliminable_invariants;
349 /* For each label, we record the offset of each elimination. If we reach
350 a label by more than one path and an offset differs, we cannot do the
351 elimination. This information is indexed by the difference of the
352 number of the label and the first label number. We can't offset the
353 pointer itself as this can cause problems on machines with segmented
354 memory. The first table is an array of flags that records whether we
355 have yet encountered a label and the second table is an array of arrays,
356 one entry in the latter array for each elimination. */
358 static int first_label_num;
359 static char *offsets_known_at;
360 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
362 /* Number of labels in the current function. */
364 static int num_labels;
366 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
367 static void maybe_fix_stack_asms (void);
368 static void copy_reloads (struct insn_chain *);
369 static void calculate_needs_all_insns (int);
370 static int find_reg (struct insn_chain *, int);
371 static void find_reload_regs (struct insn_chain *);
372 static void select_reload_regs (void);
373 static void delete_caller_save_insns (void);
375 static void spill_failure (rtx, enum reg_class);
376 static void count_spilled_pseudo (int, int, int);
377 static void delete_dead_insn (rtx);
378 static void alter_reg (int, int);
379 static void set_label_offsets (rtx, rtx, int);
380 static void check_eliminable_occurrences (rtx);
381 static void elimination_effects (rtx, enum machine_mode);
382 static int eliminate_regs_in_insn (rtx, int);
383 static void update_eliminable_offsets (void);
384 static void mark_not_eliminable (rtx, rtx, void *);
385 static void set_initial_elim_offsets (void);
386 static void verify_initial_elim_offsets (void);
387 static void set_initial_label_offsets (void);
388 static void set_offsets_for_label (rtx);
389 static void init_elim_table (void);
390 static void update_eliminables (HARD_REG_SET *);
391 static void spill_hard_reg (unsigned int, int);
392 static int finish_spills (int);
393 static void scan_paradoxical_subregs (rtx);
394 static void count_pseudo (int);
395 static void order_regs_for_reload (struct insn_chain *);
396 static void reload_as_needed (int);
397 static void forget_old_reloads_1 (rtx, rtx, void *);
398 static int reload_reg_class_lower (const void *, const void *);
399 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
401 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
403 static int reload_reg_free_p (unsigned int, int, enum reload_type);
404 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
406 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
408 static int function_invariant_p (rtx);
409 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
410 static int allocate_reload_reg (struct insn_chain *, int, int);
411 static int conflicts_with_override (rtx);
412 static void failed_reload (rtx, int);
413 static int set_reload_reg (int, int);
414 static void choose_reload_regs_init (struct insn_chain *, rtx *);
415 static void choose_reload_regs (struct insn_chain *);
416 static void merge_assigned_reloads (rtx);
417 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
419 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
421 static void do_input_reload (struct insn_chain *, struct reload *, int);
422 static void do_output_reload (struct insn_chain *, struct reload *, int);
423 static bool inherit_piecemeal_p (int, int);
424 static void emit_reload_insns (struct insn_chain *);
425 static void delete_output_reload (rtx, int, int);
426 static void delete_address_reloads (rtx, rtx);
427 static void delete_address_reloads_1 (rtx, rtx, rtx);
428 static rtx inc_for_reload (rtx, rtx, rtx, int);
430 static void add_auto_inc_notes (rtx, rtx);
432 static void copy_eh_notes (rtx, rtx);
433 static int reloads_conflict (int, int);
434 static rtx gen_reload (rtx, rtx, int, enum reload_type);
436 /* Initialize the reload pass once per compilation. */
443 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
444 Set spill_indirect_levels to the number of levels such addressing is
445 permitted, zero if it is not permitted at all. */
448 = gen_rtx_MEM (Pmode,
451 LAST_VIRTUAL_REGISTER + 1),
453 spill_indirect_levels = 0;
455 while (memory_address_p (QImode, tem))
457 spill_indirect_levels++;
458 tem = gen_rtx_MEM (Pmode, tem);
461 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
463 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
464 indirect_symref_ok = memory_address_p (QImode, tem);
466 /* See if reg+reg is a valid (and offsettable) address. */
468 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
470 tem = gen_rtx_PLUS (Pmode,
471 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
472 gen_rtx_REG (Pmode, i));
474 /* This way, we make sure that reg+reg is an offsettable address. */
475 tem = plus_constant (tem, 4);
477 if (memory_address_p (QImode, tem))
479 double_reg_address_ok = 1;
484 /* Initialize obstack for our rtl allocation. */
485 gcc_obstack_init (&reload_obstack);
486 reload_startobj = obstack_alloc (&reload_obstack, 0);
488 INIT_REG_SET (&spilled_pseudos);
489 INIT_REG_SET (&pseudos_counted);
490 VARRAY_RTX_INIT (reg_equiv_memory_loc_varray, 0, "reg_equiv_memory_loc");
493 /* List of insn chains that are currently unused. */
494 static struct insn_chain *unused_insn_chains = 0;
496 /* Allocate an empty insn_chain structure. */
498 new_insn_chain (void)
500 struct insn_chain *c;
502 if (unused_insn_chains == 0)
504 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
505 INIT_REG_SET (&c->live_throughout);
506 INIT_REG_SET (&c->dead_or_set);
510 c = unused_insn_chains;
511 unused_insn_chains = c->next;
513 c->is_caller_save_insn = 0;
514 c->need_operand_change = 0;
520 /* Small utility function to set all regs in hard reg set TO which are
521 allocated to pseudos in regset FROM. */
524 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
527 reg_set_iterator rsi;
529 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
531 int r = reg_renumber[regno];
536 /* reload_combine uses the information from
537 BASIC_BLOCK->global_live_at_start, which might still
538 contain registers that have not actually been allocated
539 since they have an equivalence. */
540 gcc_assert (reload_completed);
544 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)];
546 SET_HARD_REG_BIT (*to, r + nregs);
551 /* Replace all pseudos found in LOC with their corresponding
555 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
568 unsigned int regno = REGNO (x);
570 if (regno < FIRST_PSEUDO_REGISTER)
573 x = eliminate_regs (x, mem_mode, usage);
577 replace_pseudos_in (loc, mem_mode, usage);
581 if (reg_equiv_constant[regno])
582 *loc = reg_equiv_constant[regno];
583 else if (reg_equiv_mem[regno])
584 *loc = reg_equiv_mem[regno];
585 else if (reg_equiv_address[regno])
586 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
589 gcc_assert (!REG_P (regno_reg_rtx[regno])
590 || REGNO (regno_reg_rtx[regno]) != regno);
591 *loc = regno_reg_rtx[regno];
596 else if (code == MEM)
598 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
602 /* Process each of our operands recursively. */
603 fmt = GET_RTX_FORMAT (code);
604 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
606 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
607 else if (*fmt == 'E')
608 for (j = 0; j < XVECLEN (x, i); j++)
609 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
613 /* Global variables used by reload and its subroutines. */
615 /* Set during calculate_needs if an insn needs register elimination. */
616 static int something_needs_elimination;
617 /* Set during calculate_needs if an insn needs an operand changed. */
618 static int something_needs_operands_changed;
620 /* Nonzero means we couldn't get enough spill regs. */
623 /* Main entry point for the reload pass.
625 FIRST is the first insn of the function being compiled.
627 GLOBAL nonzero means we were called from global_alloc
628 and should attempt to reallocate any pseudoregs that we
629 displace from hard regs we will use for reloads.
630 If GLOBAL is zero, we do not have enough information to do that,
631 so any pseudo reg that is spilled must go to the stack.
633 Return value is nonzero if reload failed
634 and we must not do any more for this function. */
637 reload (rtx first, int global)
641 struct elim_table *ep;
644 /* Make sure even insns with volatile mem refs are recognizable. */
649 reload_firstobj = obstack_alloc (&reload_obstack, 0);
651 /* Make sure that the last insn in the chain
652 is not something that needs reloading. */
653 emit_note (NOTE_INSN_DELETED);
655 /* Enable find_equiv_reg to distinguish insns made by reload. */
656 reload_first_uid = get_max_uid ();
658 #ifdef SECONDARY_MEMORY_NEEDED
659 /* Initialize the secondary memory table. */
660 clear_secondary_mem ();
663 /* We don't have a stack slot for any spill reg yet. */
664 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
665 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
667 /* Initialize the save area information for caller-save, in case some
671 /* Compute which hard registers are now in use
672 as homes for pseudo registers.
673 This is done here rather than (eg) in global_alloc
674 because this point is reached even if not optimizing. */
675 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
678 /* A function that receives a nonlocal goto must save all call-saved
680 if (current_function_has_nonlocal_label)
681 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
682 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
683 regs_ever_live[i] = 1;
685 /* Find all the pseudo registers that didn't get hard regs
686 but do have known equivalent constants or memory slots.
687 These include parameters (known equivalent to parameter slots)
688 and cse'd or loop-moved constant memory addresses.
690 Record constant equivalents in reg_equiv_constant
691 so they will be substituted by find_reloads.
692 Record memory equivalents in reg_mem_equiv so they can
693 be substituted eventually by altering the REG-rtx's. */
695 reg_equiv_constant = xcalloc (max_regno, sizeof (rtx));
696 reg_equiv_mem = xcalloc (max_regno, sizeof (rtx));
697 reg_equiv_init = xcalloc (max_regno, sizeof (rtx));
698 reg_equiv_address = xcalloc (max_regno, sizeof (rtx));
699 reg_max_ref_width = xcalloc (max_regno, sizeof (int));
700 reg_old_renumber = xcalloc (max_regno, sizeof (short));
701 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
702 pseudo_forbidden_regs = xmalloc (max_regno * sizeof (HARD_REG_SET));
703 pseudo_previous_regs = xcalloc (max_regno, sizeof (HARD_REG_SET));
705 CLEAR_HARD_REG_SET (bad_spill_regs_global);
707 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
708 to. Also find all paradoxical subregs and find largest such for
711 num_eliminable_invariants = 0;
712 for (insn = first; insn; insn = NEXT_INSN (insn))
714 rtx set = single_set (insn);
716 /* We may introduce USEs that we want to remove at the end, so
717 we'll mark them with QImode. Make sure there are no
718 previously-marked insns left by say regmove. */
719 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
720 && GET_MODE (insn) != VOIDmode)
721 PUT_MODE (insn, VOIDmode);
723 if (set != 0 && REG_P (SET_DEST (set)))
725 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
727 && (! function_invariant_p (XEXP (note, 0))
729 /* A function invariant is often CONSTANT_P but may
730 include a register. We promise to only pass
731 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
732 || (CONSTANT_P (XEXP (note, 0))
733 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))))
735 rtx x = XEXP (note, 0);
736 i = REGNO (SET_DEST (set));
737 if (i > LAST_VIRTUAL_REGISTER)
739 /* It can happen that a REG_EQUIV note contains a MEM
740 that is not a legitimate memory operand. As later
741 stages of reload assume that all addresses found
742 in the reg_equiv_* arrays were originally legitimate,
743 we ignore such REG_EQUIV notes. */
744 if (memory_operand (x, VOIDmode))
746 /* Always unshare the equivalence, so we can
747 substitute into this insn without touching the
749 reg_equiv_memory_loc[i] = copy_rtx (x);
751 else if (function_invariant_p (x))
753 if (GET_CODE (x) == PLUS)
755 /* This is PLUS of frame pointer and a constant,
756 and might be shared. Unshare it. */
757 reg_equiv_constant[i] = copy_rtx (x);
758 num_eliminable_invariants++;
760 else if (x == frame_pointer_rtx
761 || x == arg_pointer_rtx)
763 reg_equiv_constant[i] = x;
764 num_eliminable_invariants++;
766 else if (LEGITIMATE_CONSTANT_P (x))
767 reg_equiv_constant[i] = x;
770 reg_equiv_memory_loc[i]
771 = force_const_mem (GET_MODE (SET_DEST (set)), x);
772 if (!reg_equiv_memory_loc[i])
779 /* If this register is being made equivalent to a MEM
780 and the MEM is not SET_SRC, the equivalencing insn
781 is one with the MEM as a SET_DEST and it occurs later.
782 So don't mark this insn now. */
784 || rtx_equal_p (SET_SRC (set), x))
786 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
791 /* If this insn is setting a MEM from a register equivalent to it,
792 this is the equivalencing insn. */
793 else if (set && MEM_P (SET_DEST (set))
794 && REG_P (SET_SRC (set))
795 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
796 && rtx_equal_p (SET_DEST (set),
797 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
798 reg_equiv_init[REGNO (SET_SRC (set))]
799 = gen_rtx_INSN_LIST (VOIDmode, insn,
800 reg_equiv_init[REGNO (SET_SRC (set))]);
803 scan_paradoxical_subregs (PATTERN (insn));
808 first_label_num = get_first_label_num ();
809 num_labels = max_label_num () - first_label_num;
811 /* Allocate the tables used to store offset information at labels. */
812 /* We used to use alloca here, but the size of what it would try to
813 allocate would occasionally cause it to exceed the stack limit and
814 cause a core dump. */
815 offsets_known_at = xmalloc (num_labels);
816 offsets_at = xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
818 /* Alter each pseudo-reg rtx to contain its hard reg number.
819 Assign stack slots to the pseudos that lack hard regs or equivalents.
820 Do not touch virtual registers. */
822 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
825 /* If we have some registers we think can be eliminated, scan all insns to
826 see if there is an insn that sets one of these registers to something
827 other than itself plus a constant. If so, the register cannot be
828 eliminated. Doing this scan here eliminates an extra pass through the
829 main reload loop in the most common case where register elimination
831 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
833 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
835 maybe_fix_stack_asms ();
837 insns_need_reload = 0;
838 something_needs_elimination = 0;
840 /* Initialize to -1, which means take the first spill register. */
843 /* Spill any hard regs that we know we can't eliminate. */
844 CLEAR_HARD_REG_SET (used_spill_regs);
845 /* There can be multiple ways to eliminate a register;
846 they should be listed adjacently.
847 Elimination for any register fails only if all possible ways fail. */
848 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
851 int can_eliminate = 0;
854 can_eliminate |= ep->can_eliminate;
857 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
859 spill_hard_reg (from, 1);
862 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
863 if (frame_pointer_needed)
864 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
866 finish_spills (global);
868 /* From now on, we may need to generate moves differently. We may also
869 allow modifications of insns which cause them to not be recognized.
870 Any such modifications will be cleaned up during reload itself. */
871 reload_in_progress = 1;
873 /* This loop scans the entire function each go-round
874 and repeats until one repetition spills no additional hard regs. */
877 int something_changed;
880 HOST_WIDE_INT starting_frame_size;
882 /* Round size of stack frame to stack_alignment_needed. This must be done
883 here because the stack size may be a part of the offset computation
884 for register elimination, and there might have been new stack slots
885 created in the last iteration of this loop. */
886 if (cfun->stack_alignment_needed)
887 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
889 starting_frame_size = get_frame_size ();
891 set_initial_elim_offsets ();
892 set_initial_label_offsets ();
894 /* For each pseudo register that has an equivalent location defined,
895 try to eliminate any eliminable registers (such as the frame pointer)
896 assuming initial offsets for the replacement register, which
899 If the resulting location is directly addressable, substitute
900 the MEM we just got directly for the old REG.
902 If it is not addressable but is a constant or the sum of a hard reg
903 and constant, it is probably not addressable because the constant is
904 out of range, in that case record the address; we will generate
905 hairy code to compute the address in a register each time it is
906 needed. Similarly if it is a hard register, but one that is not
907 valid as an address register.
909 If the location is not addressable, but does not have one of the
910 above forms, assign a stack slot. We have to do this to avoid the
911 potential of producing lots of reloads if, e.g., a location involves
912 a pseudo that didn't get a hard register and has an equivalent memory
913 location that also involves a pseudo that didn't get a hard register.
915 Perhaps at some point we will improve reload_when_needed handling
916 so this problem goes away. But that's very hairy. */
918 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
919 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
921 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
923 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
925 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
926 else if (CONSTANT_P (XEXP (x, 0))
927 || (REG_P (XEXP (x, 0))
928 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
929 || (GET_CODE (XEXP (x, 0)) == PLUS
930 && REG_P (XEXP (XEXP (x, 0), 0))
931 && (REGNO (XEXP (XEXP (x, 0), 0))
932 < FIRST_PSEUDO_REGISTER)
933 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
934 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
937 /* Make a new stack slot. Then indicate that something
938 changed so we go back and recompute offsets for
939 eliminable registers because the allocation of memory
940 below might change some offset. reg_equiv_{mem,address}
941 will be set up for this pseudo on the next pass around
943 reg_equiv_memory_loc[i] = 0;
944 reg_equiv_init[i] = 0;
949 if (caller_save_needed)
952 /* If we allocated another stack slot, redo elimination bookkeeping. */
953 if (starting_frame_size != get_frame_size ())
956 if (caller_save_needed)
958 save_call_clobbered_regs ();
959 /* That might have allocated new insn_chain structures. */
960 reload_firstobj = obstack_alloc (&reload_obstack, 0);
963 calculate_needs_all_insns (global);
965 CLEAR_REG_SET (&spilled_pseudos);
968 something_changed = 0;
970 /* If we allocated any new memory locations, make another pass
971 since it might have changed elimination offsets. */
972 if (starting_frame_size != get_frame_size ())
973 something_changed = 1;
976 HARD_REG_SET to_spill;
977 CLEAR_HARD_REG_SET (to_spill);
978 update_eliminables (&to_spill);
979 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
980 if (TEST_HARD_REG_BIT (to_spill, i))
982 spill_hard_reg (i, 1);
985 /* Regardless of the state of spills, if we previously had
986 a register that we thought we could eliminate, but now can
987 not eliminate, we must run another pass.
989 Consider pseudos which have an entry in reg_equiv_* which
990 reference an eliminable register. We must make another pass
991 to update reg_equiv_* so that we do not substitute in the
992 old value from when we thought the elimination could be
994 something_changed = 1;
998 select_reload_regs ();
1002 if (insns_need_reload != 0 || did_spill)
1003 something_changed |= finish_spills (global);
1005 if (! something_changed)
1008 if (caller_save_needed)
1009 delete_caller_save_insns ();
1011 obstack_free (&reload_obstack, reload_firstobj);
1014 /* If global-alloc was run, notify it of any register eliminations we have
1017 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1018 if (ep->can_eliminate)
1019 mark_elimination (ep->from, ep->to);
1021 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1022 If that insn didn't set the register (i.e., it copied the register to
1023 memory), just delete that insn instead of the equivalencing insn plus
1024 anything now dead. If we call delete_dead_insn on that insn, we may
1025 delete the insn that actually sets the register if the register dies
1026 there and that is incorrect. */
1028 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1030 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1033 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1035 rtx equiv_insn = XEXP (list, 0);
1037 /* If we already deleted the insn or if it may trap, we can't
1038 delete it. The latter case shouldn't happen, but can
1039 if an insn has a variable address, gets a REG_EH_REGION
1040 note added to it, and then gets converted into an load
1041 from a constant address. */
1042 if (NOTE_P (equiv_insn)
1043 || can_throw_internal (equiv_insn))
1045 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1046 delete_dead_insn (equiv_insn);
1048 SET_INSN_DELETED (equiv_insn);
1053 /* Use the reload registers where necessary
1054 by generating move instructions to move the must-be-register
1055 values into or out of the reload registers. */
1057 if (insns_need_reload != 0 || something_needs_elimination
1058 || something_needs_operands_changed)
1060 HOST_WIDE_INT old_frame_size = get_frame_size ();
1062 reload_as_needed (global);
1064 gcc_assert (old_frame_size == get_frame_size ());
1067 verify_initial_elim_offsets ();
1070 /* If we were able to eliminate the frame pointer, show that it is no
1071 longer live at the start of any basic block. If it ls live by
1072 virtue of being in a pseudo, that pseudo will be marked live
1073 and hence the frame pointer will be known to be live via that
1076 if (! frame_pointer_needed)
1078 CLEAR_REGNO_REG_SET (bb->global_live_at_start,
1079 HARD_FRAME_POINTER_REGNUM);
1081 /* Come here (with failure set nonzero) if we can't get enough spill regs
1082 and we decide not to abort about it. */
1085 CLEAR_REG_SET (&spilled_pseudos);
1086 reload_in_progress = 0;
1088 /* Now eliminate all pseudo regs by modifying them into
1089 their equivalent memory references.
1090 The REG-rtx's for the pseudos are modified in place,
1091 so all insns that used to refer to them now refer to memory.
1093 For a reg that has a reg_equiv_address, all those insns
1094 were changed by reloading so that no insns refer to it any longer;
1095 but the DECL_RTL of a variable decl may refer to it,
1096 and if so this causes the debugging info to mention the variable. */
1098 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1102 if (reg_equiv_mem[i])
1103 addr = XEXP (reg_equiv_mem[i], 0);
1105 if (reg_equiv_address[i])
1106 addr = reg_equiv_address[i];
1110 if (reg_renumber[i] < 0)
1112 rtx reg = regno_reg_rtx[i];
1114 REG_USERVAR_P (reg) = 0;
1115 PUT_CODE (reg, MEM);
1116 XEXP (reg, 0) = addr;
1117 if (reg_equiv_memory_loc[i])
1118 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1121 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1122 MEM_ATTRS (reg) = 0;
1125 else if (reg_equiv_mem[i])
1126 XEXP (reg_equiv_mem[i], 0) = addr;
1130 /* We must set reload_completed now since the cleanup_subreg_operands call
1131 below will re-recognize each insn and reload may have generated insns
1132 which are only valid during and after reload. */
1133 reload_completed = 1;
1135 /* Make a pass over all the insns and delete all USEs which we inserted
1136 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1137 notes. Delete all CLOBBER insns, except those that refer to the return
1138 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1139 from misarranging variable-array code, and simplify (subreg (reg))
1140 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1141 are no longer useful or accurate. Strip and regenerate REG_INC notes
1142 that may have been moved around. */
1144 for (insn = first; insn; insn = NEXT_INSN (insn))
1150 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1151 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1153 if ((GET_CODE (PATTERN (insn)) == USE
1154 /* We mark with QImode USEs introduced by reload itself. */
1155 && (GET_MODE (insn) == QImode
1156 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1157 || (GET_CODE (PATTERN (insn)) == CLOBBER
1158 && (!MEM_P (XEXP (PATTERN (insn), 0))
1159 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1160 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1161 && XEXP (XEXP (PATTERN (insn), 0), 0)
1162 != stack_pointer_rtx))
1163 && (!REG_P (XEXP (PATTERN (insn), 0))
1164 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1170 /* Some CLOBBERs may survive until here and still reference unassigned
1171 pseudos with const equivalent, which may in turn cause ICE in later
1172 passes if the reference remains in place. */
1173 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1174 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1175 VOIDmode, PATTERN (insn));
1177 pnote = ®_NOTES (insn);
1180 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1181 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1182 || REG_NOTE_KIND (*pnote) == REG_INC
1183 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1184 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1185 *pnote = XEXP (*pnote, 1);
1187 pnote = &XEXP (*pnote, 1);
1191 add_auto_inc_notes (insn, PATTERN (insn));
1194 /* And simplify (subreg (reg)) if it appears as an operand. */
1195 cleanup_subreg_operands (insn);
1198 /* If we are doing stack checking, give a warning if this function's
1199 frame size is larger than we expect. */
1200 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1202 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1203 static int verbose_warned = 0;
1205 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1206 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1207 size += UNITS_PER_WORD;
1209 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1211 warning ("frame size too large for reliable stack checking");
1212 if (! verbose_warned)
1214 warning ("try reducing the number of local variables");
1220 /* Indicate that we no longer have known memory locations or constants. */
1221 if (reg_equiv_constant)
1222 free (reg_equiv_constant);
1223 reg_equiv_constant = 0;
1224 VARRAY_GROW (reg_equiv_memory_loc_varray, 0);
1225 reg_equiv_memory_loc = 0;
1227 if (offsets_known_at)
1228 free (offsets_known_at);
1232 free (reg_equiv_mem);
1233 free (reg_equiv_init);
1234 free (reg_equiv_address);
1235 free (reg_max_ref_width);
1236 free (reg_old_renumber);
1237 free (pseudo_previous_regs);
1238 free (pseudo_forbidden_regs);
1240 CLEAR_HARD_REG_SET (used_spill_regs);
1241 for (i = 0; i < n_spills; i++)
1242 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1244 /* Free all the insn_chain structures at once. */
1245 obstack_free (&reload_obstack, reload_startobj);
1246 unused_insn_chains = 0;
1247 fixup_abnormal_edges ();
1249 /* Replacing pseudos with their memory equivalents might have
1250 created shared rtx. Subsequent passes would get confused
1251 by this, so unshare everything here. */
1252 unshare_all_rtl_again (first);
1254 #ifdef STACK_BOUNDARY
1255 /* init_emit has set the alignment of the hard frame pointer
1256 to STACK_BOUNDARY. It is very likely no longer valid if
1257 the hard frame pointer was used for register allocation. */
1258 if (!frame_pointer_needed)
1259 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1265 /* Yet another special case. Unfortunately, reg-stack forces people to
1266 write incorrect clobbers in asm statements. These clobbers must not
1267 cause the register to appear in bad_spill_regs, otherwise we'll call
1268 fatal_insn later. We clear the corresponding regnos in the live
1269 register sets to avoid this.
1270 The whole thing is rather sick, I'm afraid. */
1273 maybe_fix_stack_asms (void)
1276 const char *constraints[MAX_RECOG_OPERANDS];
1277 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1278 struct insn_chain *chain;
1280 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1283 HARD_REG_SET clobbered, allowed;
1286 if (! INSN_P (chain->insn)
1287 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1289 pat = PATTERN (chain->insn);
1290 if (GET_CODE (pat) != PARALLEL)
1293 CLEAR_HARD_REG_SET (clobbered);
1294 CLEAR_HARD_REG_SET (allowed);
1296 /* First, make a mask of all stack regs that are clobbered. */
1297 for (i = 0; i < XVECLEN (pat, 0); i++)
1299 rtx t = XVECEXP (pat, 0, i);
1300 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1301 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1304 /* Get the operand values and constraints out of the insn. */
1305 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1306 constraints, operand_mode);
1308 /* For every operand, see what registers are allowed. */
1309 for (i = 0; i < noperands; i++)
1311 const char *p = constraints[i];
1312 /* For every alternative, we compute the class of registers allowed
1313 for reloading in CLS, and merge its contents into the reg set
1315 int cls = (int) NO_REGS;
1321 if (c == '\0' || c == ',' || c == '#')
1323 /* End of one alternative - mark the regs in the current
1324 class, and reset the class. */
1325 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1331 } while (c != '\0' && c != ',');
1339 case '=': case '+': case '*': case '%': case '?': case '!':
1340 case '0': case '1': case '2': case '3': case '4': case 'm':
1341 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1342 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1343 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1348 cls = (int) reg_class_subunion[cls]
1349 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1354 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1358 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1359 cls = (int) reg_class_subunion[cls]
1360 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1362 cls = (int) reg_class_subunion[cls]
1363 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1365 p += CONSTRAINT_LEN (c, p);
1368 /* Those of the registers which are clobbered, but allowed by the
1369 constraints, must be usable as reload registers. So clear them
1370 out of the life information. */
1371 AND_HARD_REG_SET (allowed, clobbered);
1372 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1373 if (TEST_HARD_REG_BIT (allowed, i))
1375 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1376 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1383 /* Copy the global variables n_reloads and rld into the corresponding elts
1386 copy_reloads (struct insn_chain *chain)
1388 chain->n_reloads = n_reloads;
1389 chain->rld = obstack_alloc (&reload_obstack,
1390 n_reloads * sizeof (struct reload));
1391 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1392 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1395 /* Walk the chain of insns, and determine for each whether it needs reloads
1396 and/or eliminations. Build the corresponding insns_need_reload list, and
1397 set something_needs_elimination as appropriate. */
1399 calculate_needs_all_insns (int global)
1401 struct insn_chain **pprev_reload = &insns_need_reload;
1402 struct insn_chain *chain, *next = 0;
1404 something_needs_elimination = 0;
1406 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1407 for (chain = reload_insn_chain; chain != 0; chain = next)
1409 rtx insn = chain->insn;
1413 /* Clear out the shortcuts. */
1414 chain->n_reloads = 0;
1415 chain->need_elim = 0;
1416 chain->need_reload = 0;
1417 chain->need_operand_change = 0;
1419 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1420 include REG_LABEL), we need to see what effects this has on the
1421 known offsets at labels. */
1423 if (LABEL_P (insn) || JUMP_P (insn)
1424 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1425 set_label_offsets (insn, insn, 0);
1429 rtx old_body = PATTERN (insn);
1430 int old_code = INSN_CODE (insn);
1431 rtx old_notes = REG_NOTES (insn);
1432 int did_elimination = 0;
1433 int operands_changed = 0;
1434 rtx set = single_set (insn);
1436 /* Skip insns that only set an equivalence. */
1437 if (set && REG_P (SET_DEST (set))
1438 && reg_renumber[REGNO (SET_DEST (set))] < 0
1439 && reg_equiv_constant[REGNO (SET_DEST (set))])
1442 /* If needed, eliminate any eliminable registers. */
1443 if (num_eliminable || num_eliminable_invariants)
1444 did_elimination = eliminate_regs_in_insn (insn, 0);
1446 /* Analyze the instruction. */
1447 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1448 global, spill_reg_order);
1450 /* If a no-op set needs more than one reload, this is likely
1451 to be something that needs input address reloads. We
1452 can't get rid of this cleanly later, and it is of no use
1453 anyway, so discard it now.
1454 We only do this when expensive_optimizations is enabled,
1455 since this complements reload inheritance / output
1456 reload deletion, and it can make debugging harder. */
1457 if (flag_expensive_optimizations && n_reloads > 1)
1459 rtx set = single_set (insn);
1461 && SET_SRC (set) == SET_DEST (set)
1462 && REG_P (SET_SRC (set))
1463 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1466 /* Delete it from the reload chain. */
1468 chain->prev->next = next;
1470 reload_insn_chain = next;
1472 next->prev = chain->prev;
1473 chain->next = unused_insn_chains;
1474 unused_insn_chains = chain;
1479 update_eliminable_offsets ();
1481 /* Remember for later shortcuts which insns had any reloads or
1482 register eliminations. */
1483 chain->need_elim = did_elimination;
1484 chain->need_reload = n_reloads > 0;
1485 chain->need_operand_change = operands_changed;
1487 /* Discard any register replacements done. */
1488 if (did_elimination)
1490 obstack_free (&reload_obstack, reload_insn_firstobj);
1491 PATTERN (insn) = old_body;
1492 INSN_CODE (insn) = old_code;
1493 REG_NOTES (insn) = old_notes;
1494 something_needs_elimination = 1;
1497 something_needs_operands_changed |= operands_changed;
1501 copy_reloads (chain);
1502 *pprev_reload = chain;
1503 pprev_reload = &chain->next_need_reload;
1510 /* Comparison function for qsort to decide which of two reloads
1511 should be handled first. *P1 and *P2 are the reload numbers. */
1514 reload_reg_class_lower (const void *r1p, const void *r2p)
1516 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1519 /* Consider required reloads before optional ones. */
1520 t = rld[r1].optional - rld[r2].optional;
1524 /* Count all solitary classes before non-solitary ones. */
1525 t = ((reg_class_size[(int) rld[r2].class] == 1)
1526 - (reg_class_size[(int) rld[r1].class] == 1));
1530 /* Aside from solitaires, consider all multi-reg groups first. */
1531 t = rld[r2].nregs - rld[r1].nregs;
1535 /* Consider reloads in order of increasing reg-class number. */
1536 t = (int) rld[r1].class - (int) rld[r2].class;
1540 /* If reloads are equally urgent, sort by reload number,
1541 so that the results of qsort leave nothing to chance. */
1545 /* The cost of spilling each hard reg. */
1546 static int spill_cost[FIRST_PSEUDO_REGISTER];
1548 /* When spilling multiple hard registers, we use SPILL_COST for the first
1549 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1550 only the first hard reg for a multi-reg pseudo. */
1551 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1553 /* Update the spill cost arrays, considering that pseudo REG is live. */
1556 count_pseudo (int reg)
1558 int freq = REG_FREQ (reg);
1559 int r = reg_renumber[reg];
1562 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1563 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1566 SET_REGNO_REG_SET (&pseudos_counted, reg);
1568 gcc_assert (r >= 0);
1570 spill_add_cost[r] += freq;
1572 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1574 spill_cost[r + nregs] += freq;
1577 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1578 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1581 order_regs_for_reload (struct insn_chain *chain)
1584 HARD_REG_SET used_by_pseudos;
1585 HARD_REG_SET used_by_pseudos2;
1586 reg_set_iterator rsi;
1588 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1590 memset (spill_cost, 0, sizeof spill_cost);
1591 memset (spill_add_cost, 0, sizeof spill_add_cost);
1593 /* Count number of uses of each hard reg by pseudo regs allocated to it
1594 and then order them by decreasing use. First exclude hard registers
1595 that are live in or across this insn. */
1597 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1598 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1599 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1600 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1602 /* Now find out which pseudos are allocated to it, and update
1604 CLEAR_REG_SET (&pseudos_counted);
1606 EXECUTE_IF_SET_IN_REG_SET
1607 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1611 EXECUTE_IF_SET_IN_REG_SET
1612 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1616 CLEAR_REG_SET (&pseudos_counted);
1619 /* Vector of reload-numbers showing the order in which the reloads should
1621 static short reload_order[MAX_RELOADS];
1623 /* This is used to keep track of the spill regs used in one insn. */
1624 static HARD_REG_SET used_spill_regs_local;
1626 /* We decided to spill hard register SPILLED, which has a size of
1627 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1628 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1629 update SPILL_COST/SPILL_ADD_COST. */
1632 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1634 int r = reg_renumber[reg];
1635 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1637 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1638 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1641 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1643 spill_add_cost[r] -= REG_FREQ (reg);
1645 spill_cost[r + nregs] -= REG_FREQ (reg);
1648 /* Find reload register to use for reload number ORDER. */
1651 find_reg (struct insn_chain *chain, int order)
1653 int rnum = reload_order[order];
1654 struct reload *rl = rld + rnum;
1655 int best_cost = INT_MAX;
1659 HARD_REG_SET not_usable;
1660 HARD_REG_SET used_by_other_reload;
1661 reg_set_iterator rsi;
1663 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1664 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1665 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1667 CLEAR_HARD_REG_SET (used_by_other_reload);
1668 for (k = 0; k < order; k++)
1670 int other = reload_order[k];
1672 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1673 for (j = 0; j < rld[other].nregs; j++)
1674 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1677 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1679 unsigned int regno = i;
1681 if (! TEST_HARD_REG_BIT (not_usable, regno)
1682 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1683 && HARD_REGNO_MODE_OK (regno, rl->mode))
1685 int this_cost = spill_cost[regno];
1687 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1689 for (j = 1; j < this_nregs; j++)
1691 this_cost += spill_add_cost[regno + j];
1692 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1693 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1698 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1700 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1702 if (this_cost < best_cost
1703 /* Among registers with equal cost, prefer caller-saved ones, or
1704 use REG_ALLOC_ORDER if it is defined. */
1705 || (this_cost == best_cost
1706 #ifdef REG_ALLOC_ORDER
1707 && (inv_reg_alloc_order[regno]
1708 < inv_reg_alloc_order[best_reg])
1710 && call_used_regs[regno]
1711 && ! call_used_regs[best_reg]
1716 best_cost = this_cost;
1724 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1726 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1727 rl->regno = best_reg;
1729 EXECUTE_IF_SET_IN_REG_SET
1730 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1732 count_spilled_pseudo (best_reg, rl->nregs, j);
1735 EXECUTE_IF_SET_IN_REG_SET
1736 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1738 count_spilled_pseudo (best_reg, rl->nregs, j);
1741 for (i = 0; i < rl->nregs; i++)
1743 gcc_assert (spill_cost[best_reg + i] == 0);
1744 gcc_assert (spill_add_cost[best_reg + i] == 0);
1745 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1750 /* Find more reload regs to satisfy the remaining need of an insn, which
1752 Do it by ascending class number, since otherwise a reg
1753 might be spilled for a big class and might fail to count
1754 for a smaller class even though it belongs to that class. */
1757 find_reload_regs (struct insn_chain *chain)
1761 /* In order to be certain of getting the registers we need,
1762 we must sort the reloads into order of increasing register class.
1763 Then our grabbing of reload registers will parallel the process
1764 that provided the reload registers. */
1765 for (i = 0; i < chain->n_reloads; i++)
1767 /* Show whether this reload already has a hard reg. */
1768 if (chain->rld[i].reg_rtx)
1770 int regno = REGNO (chain->rld[i].reg_rtx);
1771 chain->rld[i].regno = regno;
1773 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1776 chain->rld[i].regno = -1;
1777 reload_order[i] = i;
1780 n_reloads = chain->n_reloads;
1781 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1783 CLEAR_HARD_REG_SET (used_spill_regs_local);
1786 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1788 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1790 /* Compute the order of preference for hard registers to spill. */
1792 order_regs_for_reload (chain);
1794 for (i = 0; i < n_reloads; i++)
1796 int r = reload_order[i];
1798 /* Ignore reloads that got marked inoperative. */
1799 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1800 && ! rld[r].optional
1801 && rld[r].regno == -1)
1802 if (! find_reg (chain, i))
1804 spill_failure (chain->insn, rld[r].class);
1810 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1811 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1813 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1817 select_reload_regs (void)
1819 struct insn_chain *chain;
1821 /* Try to satisfy the needs for each insn. */
1822 for (chain = insns_need_reload; chain != 0;
1823 chain = chain->next_need_reload)
1824 find_reload_regs (chain);
1827 /* Delete all insns that were inserted by emit_caller_save_insns during
1830 delete_caller_save_insns (void)
1832 struct insn_chain *c = reload_insn_chain;
1836 while (c != 0 && c->is_caller_save_insn)
1838 struct insn_chain *next = c->next;
1841 if (c == reload_insn_chain)
1842 reload_insn_chain = next;
1846 next->prev = c->prev;
1848 c->prev->next = next;
1849 c->next = unused_insn_chains;
1850 unused_insn_chains = c;
1858 /* Handle the failure to find a register to spill.
1859 INSN should be one of the insns which needed this particular spill reg. */
1862 spill_failure (rtx insn, enum reg_class class)
1864 if (asm_noperands (PATTERN (insn)) >= 0)
1865 error_for_asm (insn, "can't find a register in class %qs while "
1866 "reloading %<asm%>",
1867 reg_class_names[class]);
1870 error ("unable to find a register to spill in class %qs",
1871 reg_class_names[class]);
1872 fatal_insn ("this is the insn:", insn);
1876 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1877 data that is dead in INSN. */
1880 delete_dead_insn (rtx insn)
1882 rtx prev = prev_real_insn (insn);
1885 /* If the previous insn sets a register that dies in our insn, delete it
1887 if (prev && GET_CODE (PATTERN (prev)) == SET
1888 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
1889 && reg_mentioned_p (prev_dest, PATTERN (insn))
1890 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1891 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1892 delete_dead_insn (prev);
1894 SET_INSN_DELETED (insn);
1897 /* Modify the home of pseudo-reg I.
1898 The new home is present in reg_renumber[I].
1900 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1901 or it may be -1, meaning there is none or it is not relevant.
1902 This is used so that all pseudos spilled from a given hard reg
1903 can share one stack slot. */
1906 alter_reg (int i, int from_reg)
1908 /* When outputting an inline function, this can happen
1909 for a reg that isn't actually used. */
1910 if (regno_reg_rtx[i] == 0)
1913 /* If the reg got changed to a MEM at rtl-generation time,
1915 if (!REG_P (regno_reg_rtx[i]))
1918 /* Modify the reg-rtx to contain the new hard reg
1919 number or else to contain its pseudo reg number. */
1920 REGNO (regno_reg_rtx[i])
1921 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1923 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1924 allocate a stack slot for it. */
1926 if (reg_renumber[i] < 0
1927 && REG_N_REFS (i) > 0
1928 && reg_equiv_constant[i] == 0
1929 && reg_equiv_memory_loc[i] == 0)
1932 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1933 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1936 /* Each pseudo reg has an inherent size which comes from its own mode,
1937 and a total size which provides room for paradoxical subregs
1938 which refer to the pseudo reg in wider modes.
1940 We can use a slot already allocated if it provides both
1941 enough inherent space and enough total space.
1942 Otherwise, we allocate a new slot, making sure that it has no less
1943 inherent space, and no less total space, then the previous slot. */
1946 /* No known place to spill from => no slot to reuse. */
1947 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1948 inherent_size == total_size ? 0 : -1);
1949 if (BYTES_BIG_ENDIAN)
1950 /* Cancel the big-endian correction done in assign_stack_local.
1951 Get the address of the beginning of the slot.
1952 This is so we can do a big-endian correction unconditionally
1954 adjust = inherent_size - total_size;
1956 /* Nothing can alias this slot except this pseudo. */
1957 set_mem_alias_set (x, new_alias_set ());
1960 /* Reuse a stack slot if possible. */
1961 else if (spill_stack_slot[from_reg] != 0
1962 && spill_stack_slot_width[from_reg] >= total_size
1963 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1965 x = spill_stack_slot[from_reg];
1967 /* Allocate a bigger slot. */
1970 /* Compute maximum size needed, both for inherent size
1971 and for total size. */
1972 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1975 if (spill_stack_slot[from_reg])
1977 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1979 mode = GET_MODE (spill_stack_slot[from_reg]);
1980 if (spill_stack_slot_width[from_reg] > total_size)
1981 total_size = spill_stack_slot_width[from_reg];
1984 /* Make a slot with that size. */
1985 x = assign_stack_local (mode, total_size,
1986 inherent_size == total_size ? 0 : -1);
1989 /* All pseudos mapped to this slot can alias each other. */
1990 if (spill_stack_slot[from_reg])
1991 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
1993 set_mem_alias_set (x, new_alias_set ());
1995 if (BYTES_BIG_ENDIAN)
1997 /* Cancel the big-endian correction done in assign_stack_local.
1998 Get the address of the beginning of the slot.
1999 This is so we can do a big-endian correction unconditionally
2001 adjust = GET_MODE_SIZE (mode) - total_size;
2004 = adjust_address_nv (x, mode_for_size (total_size
2010 spill_stack_slot[from_reg] = stack_slot;
2011 spill_stack_slot_width[from_reg] = total_size;
2014 /* On a big endian machine, the "address" of the slot
2015 is the address of the low part that fits its inherent mode. */
2016 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2017 adjust += (total_size - inherent_size);
2019 /* If we have any adjustment to make, or if the stack slot is the
2020 wrong mode, make a new stack slot. */
2021 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2023 /* If we have a decl for the original register, set it for the
2024 memory. If this is a shared MEM, make a copy. */
2025 if (REG_EXPR (regno_reg_rtx[i])
2026 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2028 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2030 /* We can do this only for the DECLs home pseudo, not for
2031 any copies of it, since otherwise when the stack slot
2032 is reused, nonoverlapping_memrefs_p might think they
2034 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2036 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2039 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2043 /* Save the stack slot for later. */
2044 reg_equiv_memory_loc[i] = x;
2048 /* Mark the slots in regs_ever_live for the hard regs
2049 used by pseudo-reg number REGNO. */
2052 mark_home_live (int regno)
2056 i = reg_renumber[regno];
2059 lim = i + hard_regno_nregs[i][PSEUDO_REGNO_MODE (regno)];
2061 regs_ever_live[i++] = 1;
2064 /* This function handles the tracking of elimination offsets around branches.
2066 X is a piece of RTL being scanned.
2068 INSN is the insn that it came from, if any.
2070 INITIAL_P is nonzero if we are to set the offset to be the initial
2071 offset and zero if we are setting the offset of the label to be the
2075 set_label_offsets (rtx x, rtx insn, int initial_p)
2077 enum rtx_code code = GET_CODE (x);
2080 struct elim_table *p;
2085 if (LABEL_REF_NONLOCAL_P (x))
2090 /* ... fall through ... */
2093 /* If we know nothing about this label, set the desired offsets. Note
2094 that this sets the offset at a label to be the offset before a label
2095 if we don't know anything about the label. This is not correct for
2096 the label after a BARRIER, but is the best guess we can make. If
2097 we guessed wrong, we will suppress an elimination that might have
2098 been possible had we been able to guess correctly. */
2100 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2102 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2103 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2104 = (initial_p ? reg_eliminate[i].initial_offset
2105 : reg_eliminate[i].offset);
2106 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2109 /* Otherwise, if this is the definition of a label and it is
2110 preceded by a BARRIER, set our offsets to the known offset of
2114 && (tem = prev_nonnote_insn (insn)) != 0
2116 set_offsets_for_label (insn);
2118 /* If neither of the above cases is true, compare each offset
2119 with those previously recorded and suppress any eliminations
2120 where the offsets disagree. */
2122 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2123 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2124 != (initial_p ? reg_eliminate[i].initial_offset
2125 : reg_eliminate[i].offset))
2126 reg_eliminate[i].can_eliminate = 0;
2131 set_label_offsets (PATTERN (insn), insn, initial_p);
2133 /* ... fall through ... */
2137 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2138 and hence must have all eliminations at their initial offsets. */
2139 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2140 if (REG_NOTE_KIND (tem) == REG_LABEL)
2141 set_label_offsets (XEXP (tem, 0), insn, 1);
2147 /* Each of the labels in the parallel or address vector must be
2148 at their initial offsets. We want the first field for PARALLEL
2149 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2151 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2152 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2157 /* We only care about setting PC. If the source is not RETURN,
2158 IF_THEN_ELSE, or a label, disable any eliminations not at
2159 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2160 isn't one of those possibilities. For branches to a label,
2161 call ourselves recursively.
2163 Note that this can disable elimination unnecessarily when we have
2164 a non-local goto since it will look like a non-constant jump to
2165 someplace in the current function. This isn't a significant
2166 problem since such jumps will normally be when all elimination
2167 pairs are back to their initial offsets. */
2169 if (SET_DEST (x) != pc_rtx)
2172 switch (GET_CODE (SET_SRC (x)))
2179 set_label_offsets (SET_SRC (x), insn, initial_p);
2183 tem = XEXP (SET_SRC (x), 1);
2184 if (GET_CODE (tem) == LABEL_REF)
2185 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2186 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2189 tem = XEXP (SET_SRC (x), 2);
2190 if (GET_CODE (tem) == LABEL_REF)
2191 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2192 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2200 /* If we reach here, all eliminations must be at their initial
2201 offset because we are doing a jump to a variable address. */
2202 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2203 if (p->offset != p->initial_offset)
2204 p->can_eliminate = 0;
2212 /* Scan X and replace any eliminable registers (such as fp) with a
2213 replacement (such as sp), plus an offset.
2215 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2216 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2217 MEM, we are allowed to replace a sum of a register and the constant zero
2218 with the register, which we cannot do outside a MEM. In addition, we need
2219 to record the fact that a register is referenced outside a MEM.
2221 If INSN is an insn, it is the insn containing X. If we replace a REG
2222 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2223 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2224 the REG is being modified.
2226 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2227 That's used when we eliminate in expressions stored in notes.
2228 This means, do not set ref_outside_mem even if the reference
2231 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2232 replacements done assuming all offsets are at their initial values. If
2233 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2234 encounter, return the actual location so that find_reloads will do
2235 the proper thing. */
2238 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2240 enum rtx_code code = GET_CODE (x);
2241 struct elim_table *ep;
2248 if (! current_function_decl)
2270 /* First handle the case where we encounter a bare register that
2271 is eliminable. Replace it with a PLUS. */
2272 if (regno < FIRST_PSEUDO_REGISTER)
2274 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2276 if (ep->from_rtx == x && ep->can_eliminate)
2277 return plus_constant (ep->to_rtx, ep->previous_offset);
2280 else if (reg_renumber && reg_renumber[regno] < 0
2281 && reg_equiv_constant && reg_equiv_constant[regno]
2282 && ! CONSTANT_P (reg_equiv_constant[regno]))
2283 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2287 /* You might think handling MINUS in a manner similar to PLUS is a
2288 good idea. It is not. It has been tried multiple times and every
2289 time the change has had to have been reverted.
2291 Other parts of reload know a PLUS is special (gen_reload for example)
2292 and require special code to handle code a reloaded PLUS operand.
2294 Also consider backends where the flags register is clobbered by a
2295 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2296 lea instruction comes to mind). If we try to reload a MINUS, we
2297 may kill the flags register that was holding a useful value.
2299 So, please before trying to handle MINUS, consider reload as a
2300 whole instead of this little section as well as the backend issues. */
2302 /* If this is the sum of an eliminable register and a constant, rework
2304 if (REG_P (XEXP (x, 0))
2305 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2306 && CONSTANT_P (XEXP (x, 1)))
2308 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2310 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2312 /* The only time we want to replace a PLUS with a REG (this
2313 occurs when the constant operand of the PLUS is the negative
2314 of the offset) is when we are inside a MEM. We won't want
2315 to do so at other times because that would change the
2316 structure of the insn in a way that reload can't handle.
2317 We special-case the commonest situation in
2318 eliminate_regs_in_insn, so just replace a PLUS with a
2319 PLUS here, unless inside a MEM. */
2320 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2321 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2324 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2325 plus_constant (XEXP (x, 1),
2326 ep->previous_offset));
2329 /* If the register is not eliminable, we are done since the other
2330 operand is a constant. */
2334 /* If this is part of an address, we want to bring any constant to the
2335 outermost PLUS. We will do this by doing register replacement in
2336 our operands and seeing if a constant shows up in one of them.
2338 Note that there is no risk of modifying the structure of the insn,
2339 since we only get called for its operands, thus we are either
2340 modifying the address inside a MEM, or something like an address
2341 operand of a load-address insn. */
2344 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2345 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2347 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2349 /* If one side is a PLUS and the other side is a pseudo that
2350 didn't get a hard register but has a reg_equiv_constant,
2351 we must replace the constant here since it may no longer
2352 be in the position of any operand. */
2353 if (GET_CODE (new0) == PLUS && REG_P (new1)
2354 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2355 && reg_renumber[REGNO (new1)] < 0
2356 && reg_equiv_constant != 0
2357 && reg_equiv_constant[REGNO (new1)] != 0)
2358 new1 = reg_equiv_constant[REGNO (new1)];
2359 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2360 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2361 && reg_renumber[REGNO (new0)] < 0
2362 && reg_equiv_constant[REGNO (new0)] != 0)
2363 new0 = reg_equiv_constant[REGNO (new0)];
2365 new = form_sum (new0, new1);
2367 /* As above, if we are not inside a MEM we do not want to
2368 turn a PLUS into something else. We might try to do so here
2369 for an addition of 0 if we aren't optimizing. */
2370 if (! mem_mode && GET_CODE (new) != PLUS)
2371 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2379 /* If this is the product of an eliminable register and a
2380 constant, apply the distribute law and move the constant out
2381 so that we have (plus (mult ..) ..). This is needed in order
2382 to keep load-address insns valid. This case is pathological.
2383 We ignore the possibility of overflow here. */
2384 if (REG_P (XEXP (x, 0))
2385 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2386 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2387 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2389 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2392 /* Refs inside notes don't count for this purpose. */
2393 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2394 || GET_CODE (insn) == INSN_LIST)))
2395 ep->ref_outside_mem = 1;
2398 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2399 ep->previous_offset * INTVAL (XEXP (x, 1)));
2402 /* ... fall through ... */
2406 /* See comments before PLUS about handling MINUS. */
2408 case DIV: case UDIV:
2409 case MOD: case UMOD:
2410 case AND: case IOR: case XOR:
2411 case ROTATERT: case ROTATE:
2412 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2414 case GE: case GT: case GEU: case GTU:
2415 case LE: case LT: case LEU: case LTU:
2417 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2419 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2421 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2422 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2427 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2430 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2431 if (new != XEXP (x, 0))
2433 /* If this is a REG_DEAD note, it is not valid anymore.
2434 Using the eliminated version could result in creating a
2435 REG_DEAD note for the stack or frame pointer. */
2436 if (GET_MODE (x) == REG_DEAD)
2438 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2441 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2445 /* ... fall through ... */
2448 /* Now do eliminations in the rest of the chain. If this was
2449 an EXPR_LIST, this might result in allocating more memory than is
2450 strictly needed, but it simplifies the code. */
2453 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2454 if (new != XEXP (x, 1))
2456 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2464 case STRICT_LOW_PART:
2466 case SIGN_EXTEND: case ZERO_EXTEND:
2467 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2468 case FLOAT: case FIX:
2469 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2477 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2478 if (new != XEXP (x, 0))
2479 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2483 /* Similar to above processing, but preserve SUBREG_BYTE.
2484 Convert (subreg (mem)) to (mem) if not paradoxical.
2485 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2486 pseudo didn't get a hard reg, we must replace this with the
2487 eliminated version of the memory location because push_reload
2488 may do the replacement in certain circumstances. */
2489 if (REG_P (SUBREG_REG (x))
2490 && (GET_MODE_SIZE (GET_MODE (x))
2491 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2492 && reg_equiv_memory_loc != 0
2493 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2495 new = SUBREG_REG (x);
2498 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2500 if (new != SUBREG_REG (x))
2502 int x_size = GET_MODE_SIZE (GET_MODE (x));
2503 int new_size = GET_MODE_SIZE (GET_MODE (new));
2506 && ((x_size < new_size
2507 #ifdef WORD_REGISTER_OPERATIONS
2508 /* On these machines, combine can create rtl of the form
2509 (set (subreg:m1 (reg:m2 R) 0) ...)
2510 where m1 < m2, and expects something interesting to
2511 happen to the entire word. Moreover, it will use the
2512 (reg:m2 R) later, expecting all bits to be preserved.
2513 So if the number of words is the same, preserve the
2514 subreg so that push_reload can see it. */
2515 && ! ((x_size - 1) / UNITS_PER_WORD
2516 == (new_size -1 ) / UNITS_PER_WORD)
2519 || x_size == new_size)
2521 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2523 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2529 /* Our only special processing is to pass the mode of the MEM to our
2530 recursive call and copy the flags. While we are here, handle this
2531 case more efficiently. */
2533 replace_equiv_address_nv (x,
2534 eliminate_regs (XEXP (x, 0),
2535 GET_MODE (x), insn));
2538 /* Handle insn_list USE that a call to a pure function may generate. */
2539 new = eliminate_regs (XEXP (x, 0), 0, insn);
2540 if (new != XEXP (x, 0))
2541 return gen_rtx_USE (GET_MODE (x), new);
2553 /* Process each of our operands recursively. If any have changed, make a
2555 fmt = GET_RTX_FORMAT (code);
2556 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2560 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2561 if (new != XEXP (x, i) && ! copied)
2563 rtx new_x = rtx_alloc (code);
2564 memcpy (new_x, x, RTX_SIZE (code));
2570 else if (*fmt == 'E')
2573 for (j = 0; j < XVECLEN (x, i); j++)
2575 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2576 if (new != XVECEXP (x, i, j) && ! copied_vec)
2578 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2582 rtx new_x = rtx_alloc (code);
2583 memcpy (new_x, x, RTX_SIZE (code));
2587 XVEC (x, i) = new_v;
2590 XVECEXP (x, i, j) = new;
2598 /* Scan rtx X for modifications of elimination target registers. Update
2599 the table of eliminables to reflect the changed state. MEM_MODE is
2600 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2603 elimination_effects (rtx x, enum machine_mode mem_mode)
2605 enum rtx_code code = GET_CODE (x);
2606 struct elim_table *ep;
2630 /* First handle the case where we encounter a bare register that
2631 is eliminable. Replace it with a PLUS. */
2632 if (regno < FIRST_PSEUDO_REGISTER)
2634 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2636 if (ep->from_rtx == x && ep->can_eliminate)
2639 ep->ref_outside_mem = 1;
2644 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2645 && reg_equiv_constant[regno]
2646 && ! function_invariant_p (reg_equiv_constant[regno]))
2647 elimination_effects (reg_equiv_constant[regno], mem_mode);
2656 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2657 if (ep->to_rtx == XEXP (x, 0))
2659 int size = GET_MODE_SIZE (mem_mode);
2661 /* If more bytes than MEM_MODE are pushed, account for them. */
2662 #ifdef PUSH_ROUNDING
2663 if (ep->to_rtx == stack_pointer_rtx)
2664 size = PUSH_ROUNDING (size);
2666 if (code == PRE_DEC || code == POST_DEC)
2668 else if (code == PRE_INC || code == POST_INC)
2670 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2671 && GET_CODE (XEXP (x, 1)) == PLUS
2672 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2673 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2674 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2677 /* These two aren't unary operators. */
2678 if (code == POST_MODIFY || code == PRE_MODIFY)
2681 /* Fall through to generic unary operation case. */
2682 case STRICT_LOW_PART:
2684 case SIGN_EXTEND: case ZERO_EXTEND:
2685 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2686 case FLOAT: case FIX:
2687 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2695 elimination_effects (XEXP (x, 0), mem_mode);
2699 if (REG_P (SUBREG_REG (x))
2700 && (GET_MODE_SIZE (GET_MODE (x))
2701 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2702 && reg_equiv_memory_loc != 0
2703 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2706 elimination_effects (SUBREG_REG (x), mem_mode);
2710 /* If using a register that is the source of an eliminate we still
2711 think can be performed, note it cannot be performed since we don't
2712 know how this register is used. */
2713 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2714 if (ep->from_rtx == XEXP (x, 0))
2715 ep->can_eliminate = 0;
2717 elimination_effects (XEXP (x, 0), mem_mode);
2721 /* If clobbering a register that is the replacement register for an
2722 elimination we still think can be performed, note that it cannot
2723 be performed. Otherwise, we need not be concerned about it. */
2724 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2725 if (ep->to_rtx == XEXP (x, 0))
2726 ep->can_eliminate = 0;
2728 elimination_effects (XEXP (x, 0), mem_mode);
2732 /* Check for setting a register that we know about. */
2733 if (REG_P (SET_DEST (x)))
2735 /* See if this is setting the replacement register for an
2738 If DEST is the hard frame pointer, we do nothing because we
2739 assume that all assignments to the frame pointer are for
2740 non-local gotos and are being done at a time when they are valid
2741 and do not disturb anything else. Some machines want to
2742 eliminate a fake argument pointer (or even a fake frame pointer)
2743 with either the real frame or the stack pointer. Assignments to
2744 the hard frame pointer must not prevent this elimination. */
2746 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2748 if (ep->to_rtx == SET_DEST (x)
2749 && SET_DEST (x) != hard_frame_pointer_rtx)
2751 /* If it is being incremented, adjust the offset. Otherwise,
2752 this elimination can't be done. */
2753 rtx src = SET_SRC (x);
2755 if (GET_CODE (src) == PLUS
2756 && XEXP (src, 0) == SET_DEST (x)
2757 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2758 ep->offset -= INTVAL (XEXP (src, 1));
2760 ep->can_eliminate = 0;
2764 elimination_effects (SET_DEST (x), 0);
2765 elimination_effects (SET_SRC (x), 0);
2769 /* Our only special processing is to pass the mode of the MEM to our
2771 elimination_effects (XEXP (x, 0), GET_MODE (x));
2778 fmt = GET_RTX_FORMAT (code);
2779 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2782 elimination_effects (XEXP (x, i), mem_mode);
2783 else if (*fmt == 'E')
2784 for (j = 0; j < XVECLEN (x, i); j++)
2785 elimination_effects (XVECEXP (x, i, j), mem_mode);
2789 /* Descend through rtx X and verify that no references to eliminable registers
2790 remain. If any do remain, mark the involved register as not
2794 check_eliminable_occurrences (rtx x)
2803 code = GET_CODE (x);
2805 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2807 struct elim_table *ep;
2809 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2810 if (ep->from_rtx == x)
2811 ep->can_eliminate = 0;
2815 fmt = GET_RTX_FORMAT (code);
2816 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2819 check_eliminable_occurrences (XEXP (x, i));
2820 else if (*fmt == 'E')
2823 for (j = 0; j < XVECLEN (x, i); j++)
2824 check_eliminable_occurrences (XVECEXP (x, i, j));
2829 /* Scan INSN and eliminate all eliminable registers in it.
2831 If REPLACE is nonzero, do the replacement destructively. Also
2832 delete the insn as dead it if it is setting an eliminable register.
2834 If REPLACE is zero, do all our allocations in reload_obstack.
2836 If no eliminations were done and this insn doesn't require any elimination
2837 processing (these are not identical conditions: it might be updating sp,
2838 but not referencing fp; this needs to be seen during reload_as_needed so
2839 that the offset between fp and sp can be taken into consideration), zero
2840 is returned. Otherwise, 1 is returned. */
2843 eliminate_regs_in_insn (rtx insn, int replace)
2845 int icode = recog_memoized (insn);
2846 rtx old_body = PATTERN (insn);
2847 int insn_is_asm = asm_noperands (old_body) >= 0;
2848 rtx old_set = single_set (insn);
2852 rtx substed_operand[MAX_RECOG_OPERANDS];
2853 rtx orig_operand[MAX_RECOG_OPERANDS];
2854 struct elim_table *ep;
2857 if (! insn_is_asm && icode < 0)
2859 gcc_assert (GET_CODE (PATTERN (insn)) == USE
2860 || GET_CODE (PATTERN (insn)) == CLOBBER
2861 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2862 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2863 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
2867 if (old_set != 0 && REG_P (SET_DEST (old_set))
2868 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2870 /* Check for setting an eliminable register. */
2871 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2872 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2874 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2875 /* If this is setting the frame pointer register to the
2876 hardware frame pointer register and this is an elimination
2877 that will be done (tested above), this insn is really
2878 adjusting the frame pointer downward to compensate for
2879 the adjustment done before a nonlocal goto. */
2880 if (ep->from == FRAME_POINTER_REGNUM
2881 && ep->to == HARD_FRAME_POINTER_REGNUM)
2883 rtx base = SET_SRC (old_set);
2884 rtx base_insn = insn;
2885 HOST_WIDE_INT offset = 0;
2887 while (base != ep->to_rtx)
2889 rtx prev_insn, prev_set;
2891 if (GET_CODE (base) == PLUS
2892 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2894 offset += INTVAL (XEXP (base, 1));
2895 base = XEXP (base, 0);
2897 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2898 && (prev_set = single_set (prev_insn)) != 0
2899 && rtx_equal_p (SET_DEST (prev_set), base))
2901 base = SET_SRC (prev_set);
2902 base_insn = prev_insn;
2908 if (base == ep->to_rtx)
2911 = plus_constant (ep->to_rtx, offset - ep->offset);
2913 new_body = old_body;
2916 new_body = copy_insn (old_body);
2917 if (REG_NOTES (insn))
2918 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2920 PATTERN (insn) = new_body;
2921 old_set = single_set (insn);
2923 /* First see if this insn remains valid when we
2924 make the change. If not, keep the INSN_CODE
2925 the same and let reload fit it up. */
2926 validate_change (insn, &SET_SRC (old_set), src, 1);
2927 validate_change (insn, &SET_DEST (old_set),
2929 if (! apply_change_group ())
2931 SET_SRC (old_set) = src;
2932 SET_DEST (old_set) = ep->to_rtx;
2941 /* In this case this insn isn't serving a useful purpose. We
2942 will delete it in reload_as_needed once we know that this
2943 elimination is, in fact, being done.
2945 If REPLACE isn't set, we can't delete this insn, but needn't
2946 process it since it won't be used unless something changes. */
2949 delete_dead_insn (insn);
2957 /* We allow one special case which happens to work on all machines we
2958 currently support: a single set with the source or a REG_EQUAL
2959 note being a PLUS of an eliminable register and a constant. */
2961 if (old_set && REG_P (SET_DEST (old_set)))
2963 /* First see if the source is of the form (plus (reg) CST). */
2964 if (GET_CODE (SET_SRC (old_set)) == PLUS
2965 && REG_P (XEXP (SET_SRC (old_set), 0))
2966 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
2967 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
2968 plus_src = SET_SRC (old_set);
2969 else if (REG_P (SET_SRC (old_set)))
2971 /* Otherwise, see if we have a REG_EQUAL note of the form
2972 (plus (reg) CST). */
2974 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
2976 if (REG_NOTE_KIND (links) == REG_EQUAL
2977 && GET_CODE (XEXP (links, 0)) == PLUS
2978 && REG_P (XEXP (XEXP (links, 0), 0))
2979 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT
2980 && REGNO (XEXP (XEXP (links, 0), 0)) < FIRST_PSEUDO_REGISTER)
2982 plus_src = XEXP (links, 0);
2990 rtx reg = XEXP (plus_src, 0);
2991 HOST_WIDE_INT offset = INTVAL (XEXP (plus_src, 1));
2993 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2994 if (ep->from_rtx == reg && ep->can_eliminate)
2996 offset += ep->offset;
3001 /* We assume here that if we need a PARALLEL with
3002 CLOBBERs for this assignment, we can do with the
3003 MATCH_SCRATCHes that add_clobbers allocates.
3004 There's not much we can do if that doesn't work. */
3005 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3009 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3012 rtvec vec = rtvec_alloc (num_clobbers + 1);
3014 vec->elem[0] = PATTERN (insn);
3015 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3016 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3018 gcc_assert (INSN_CODE (insn) >= 0);
3020 /* If we have a nonzero offset, and the source is already
3021 a simple REG, the following transformation would
3022 increase the cost of the insn by replacing a simple REG
3023 with (plus (reg sp) CST). So try only when plus_src
3024 comes from old_set proper, not REG_NOTES. */
3025 else if (SET_SRC (old_set) == plus_src)
3027 new_body = old_body;
3030 new_body = copy_insn (old_body);
3031 if (REG_NOTES (insn))
3032 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3034 PATTERN (insn) = new_body;
3035 old_set = single_set (insn);
3037 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3038 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3044 /* This can't have an effect on elimination offsets, so skip right
3050 /* Determine the effects of this insn on elimination offsets. */
3051 elimination_effects (old_body, 0);
3053 /* Eliminate all eliminable registers occurring in operands that
3054 can be handled by reload. */
3055 extract_insn (insn);
3056 for (i = 0; i < recog_data.n_operands; i++)
3058 orig_operand[i] = recog_data.operand[i];
3059 substed_operand[i] = recog_data.operand[i];
3061 /* For an asm statement, every operand is eliminable. */
3062 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3064 /* Check for setting a register that we know about. */
3065 if (recog_data.operand_type[i] != OP_IN
3066 && REG_P (orig_operand[i]))
3068 /* If we are assigning to a register that can be eliminated, it
3069 must be as part of a PARALLEL, since the code above handles
3070 single SETs. We must indicate that we can no longer
3071 eliminate this reg. */
3072 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3074 if (ep->from_rtx == orig_operand[i])
3075 ep->can_eliminate = 0;
3078 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3079 replace ? insn : NULL_RTX);
3080 if (substed_operand[i] != orig_operand[i])
3082 /* Terminate the search in check_eliminable_occurrences at
3084 *recog_data.operand_loc[i] = 0;
3086 /* If an output operand changed from a REG to a MEM and INSN is an
3087 insn, write a CLOBBER insn. */
3088 if (recog_data.operand_type[i] != OP_IN
3089 && REG_P (orig_operand[i])
3090 && MEM_P (substed_operand[i])
3092 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3097 for (i = 0; i < recog_data.n_dups; i++)
3098 *recog_data.dup_loc[i]
3099 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3101 /* If any eliminable remain, they aren't eliminable anymore. */
3102 check_eliminable_occurrences (old_body);
3104 /* Substitute the operands; the new values are in the substed_operand
3106 for (i = 0; i < recog_data.n_operands; i++)
3107 *recog_data.operand_loc[i] = substed_operand[i];
3108 for (i = 0; i < recog_data.n_dups; i++)
3109 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3111 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3112 re-recognize the insn. We do this in case we had a simple addition
3113 but now can do this as a load-address. This saves an insn in this
3115 If re-recognition fails, the old insn code number will still be used,
3116 and some register operands may have changed into PLUS expressions.
3117 These will be handled by find_reloads by loading them into a register
3122 /* If we aren't replacing things permanently and we changed something,
3123 make another copy to ensure that all the RTL is new. Otherwise
3124 things can go wrong if find_reload swaps commutative operands
3125 and one is inside RTL that has been copied while the other is not. */
3126 new_body = old_body;
3129 new_body = copy_insn (old_body);
3130 if (REG_NOTES (insn))
3131 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3133 PATTERN (insn) = new_body;
3135 /* If we had a move insn but now we don't, rerecognize it. This will
3136 cause spurious re-recognition if the old move had a PARALLEL since
3137 the new one still will, but we can't call single_set without
3138 having put NEW_BODY into the insn and the re-recognition won't
3139 hurt in this rare case. */
3140 /* ??? Why this huge if statement - why don't we just rerecognize the
3144 && ((REG_P (SET_SRC (old_set))
3145 && (GET_CODE (new_body) != SET
3146 || !REG_P (SET_SRC (new_body))))
3147 /* If this was a load from or store to memory, compare
3148 the MEM in recog_data.operand to the one in the insn.
3149 If they are not equal, then rerecognize the insn. */
3151 && ((MEM_P (SET_SRC (old_set))
3152 && SET_SRC (old_set) != recog_data.operand[1])
3153 || (MEM_P (SET_DEST (old_set))
3154 && SET_DEST (old_set) != recog_data.operand[0])))
3155 /* If this was an add insn before, rerecognize. */
3156 || GET_CODE (SET_SRC (old_set)) == PLUS))
3158 int new_icode = recog (PATTERN (insn), insn, 0);
3160 INSN_CODE (insn) = icode;
3164 /* Restore the old body. If there were any changes to it, we made a copy
3165 of it while the changes were still in place, so we'll correctly return
3166 a modified insn below. */
3169 /* Restore the old body. */
3170 for (i = 0; i < recog_data.n_operands; i++)
3171 *recog_data.operand_loc[i] = orig_operand[i];
3172 for (i = 0; i < recog_data.n_dups; i++)
3173 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3176 /* Update all elimination pairs to reflect the status after the current
3177 insn. The changes we make were determined by the earlier call to
3178 elimination_effects.
3180 We also detect cases where register elimination cannot be done,
3181 namely, if a register would be both changed and referenced outside a MEM
3182 in the resulting insn since such an insn is often undefined and, even if
3183 not, we cannot know what meaning will be given to it. Note that it is
3184 valid to have a register used in an address in an insn that changes it
3185 (presumably with a pre- or post-increment or decrement).
3187 If anything changes, return nonzero. */
3189 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3191 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3192 ep->can_eliminate = 0;
3194 ep->ref_outside_mem = 0;
3196 if (ep->previous_offset != ep->offset)
3201 /* If we changed something, perform elimination in REG_NOTES. This is
3202 needed even when REPLACE is zero because a REG_DEAD note might refer
3203 to a register that we eliminate and could cause a different number
3204 of spill registers to be needed in the final reload pass than in
3206 if (val && REG_NOTES (insn) != 0)
3207 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3212 /* Loop through all elimination pairs.
3213 Recalculate the number not at initial offset.
3215 Compute the maximum offset (minimum offset if the stack does not
3216 grow downward) for each elimination pair. */
3219 update_eliminable_offsets (void)
3221 struct elim_table *ep;
3223 num_not_at_initial_offset = 0;
3224 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3226 ep->previous_offset = ep->offset;
3227 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3228 num_not_at_initial_offset++;
3232 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3233 replacement we currently believe is valid, mark it as not eliminable if X
3234 modifies DEST in any way other than by adding a constant integer to it.
3236 If DEST is the frame pointer, we do nothing because we assume that
3237 all assignments to the hard frame pointer are nonlocal gotos and are being
3238 done at a time when they are valid and do not disturb anything else.
3239 Some machines want to eliminate a fake argument pointer with either the
3240 frame or stack pointer. Assignments to the hard frame pointer must not
3241 prevent this elimination.
3243 Called via note_stores from reload before starting its passes to scan
3244 the insns of the function. */
3247 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3251 /* A SUBREG of a hard register here is just changing its mode. We should
3252 not see a SUBREG of an eliminable hard register, but check just in
3254 if (GET_CODE (dest) == SUBREG)
3255 dest = SUBREG_REG (dest);
3257 if (dest == hard_frame_pointer_rtx)
3260 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3261 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3262 && (GET_CODE (x) != SET
3263 || GET_CODE (SET_SRC (x)) != PLUS
3264 || XEXP (SET_SRC (x), 0) != dest
3265 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3267 reg_eliminate[i].can_eliminate_previous
3268 = reg_eliminate[i].can_eliminate = 0;
3273 /* Verify that the initial elimination offsets did not change since the
3274 last call to set_initial_elim_offsets. This is used to catch cases
3275 where something illegal happened during reload_as_needed that could
3276 cause incorrect code to be generated if we did not check for it. */
3279 verify_initial_elim_offsets (void)
3283 #ifdef ELIMINABLE_REGS
3284 struct elim_table *ep;
3286 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3288 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3289 gcc_assert (t == ep->initial_offset);
3292 INITIAL_FRAME_POINTER_OFFSET (t);
3293 gcc_assert (t == reg_eliminate[0].initial_offset);
3297 /* Reset all offsets on eliminable registers to their initial values. */
3300 set_initial_elim_offsets (void)
3302 struct elim_table *ep = reg_eliminate;
3304 #ifdef ELIMINABLE_REGS
3305 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3307 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3308 ep->previous_offset = ep->offset = ep->initial_offset;
3311 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3312 ep->previous_offset = ep->offset = ep->initial_offset;
3315 num_not_at_initial_offset = 0;
3318 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3321 set_initial_eh_label_offset (rtx label)
3323 set_label_offsets (label, NULL_RTX, 1);
3326 /* Initialize the known label offsets.
3327 Set a known offset for each forced label to be at the initial offset
3328 of each elimination. We do this because we assume that all
3329 computed jumps occur from a location where each elimination is
3330 at its initial offset.
3331 For all other labels, show that we don't know the offsets. */
3334 set_initial_label_offsets (void)
3337 memset (offsets_known_at, 0, num_labels);
3339 for (x = forced_labels; x; x = XEXP (x, 1))
3341 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3343 for_each_eh_label (set_initial_eh_label_offset);
3346 /* Set all elimination offsets to the known values for the code label given
3350 set_offsets_for_label (rtx insn)
3353 int label_nr = CODE_LABEL_NUMBER (insn);
3354 struct elim_table *ep;
3356 num_not_at_initial_offset = 0;
3357 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3359 ep->offset = ep->previous_offset
3360 = offsets_at[label_nr - first_label_num][i];
3361 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3362 num_not_at_initial_offset++;
3366 /* See if anything that happened changes which eliminations are valid.
3367 For example, on the SPARC, whether or not the frame pointer can
3368 be eliminated can depend on what registers have been used. We need
3369 not check some conditions again (such as flag_omit_frame_pointer)
3370 since they can't have changed. */
3373 update_eliminables (HARD_REG_SET *pset)
3375 int previous_frame_pointer_needed = frame_pointer_needed;
3376 struct elim_table *ep;
3378 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3379 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3380 #ifdef ELIMINABLE_REGS
3381 || ! CAN_ELIMINATE (ep->from, ep->to)
3384 ep->can_eliminate = 0;
3386 /* Look for the case where we have discovered that we can't replace
3387 register A with register B and that means that we will now be
3388 trying to replace register A with register C. This means we can
3389 no longer replace register C with register B and we need to disable
3390 such an elimination, if it exists. This occurs often with A == ap,
3391 B == sp, and C == fp. */
3393 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3395 struct elim_table *op;
3398 if (! ep->can_eliminate && ep->can_eliminate_previous)
3400 /* Find the current elimination for ep->from, if there is a
3402 for (op = reg_eliminate;
3403 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3404 if (op->from == ep->from && op->can_eliminate)
3410 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3412 for (op = reg_eliminate;
3413 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3414 if (op->from == new_to && op->to == ep->to)
3415 op->can_eliminate = 0;
3419 /* See if any registers that we thought we could eliminate the previous
3420 time are no longer eliminable. If so, something has changed and we
3421 must spill the register. Also, recompute the number of eliminable
3422 registers and see if the frame pointer is needed; it is if there is
3423 no elimination of the frame pointer that we can perform. */
3425 frame_pointer_needed = 1;
3426 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3428 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3429 && ep->to != HARD_FRAME_POINTER_REGNUM)
3430 frame_pointer_needed = 0;
3432 if (! ep->can_eliminate && ep->can_eliminate_previous)
3434 ep->can_eliminate_previous = 0;
3435 SET_HARD_REG_BIT (*pset, ep->from);
3440 /* If we didn't need a frame pointer last time, but we do now, spill
3441 the hard frame pointer. */
3442 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3443 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3446 /* Initialize the table of registers to eliminate. */
3449 init_elim_table (void)
3451 struct elim_table *ep;
3452 #ifdef ELIMINABLE_REGS
3453 const struct elim_table_1 *ep1;
3457 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3459 /* Does this function require a frame pointer? */
3461 frame_pointer_needed = (! flag_omit_frame_pointer
3462 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3463 and restore sp for alloca. So we can't eliminate
3464 the frame pointer in that case. At some point,
3465 we should improve this by emitting the
3466 sp-adjusting insns for this case. */
3467 || (current_function_calls_alloca
3468 && EXIT_IGNORE_STACK)
3469 || FRAME_POINTER_REQUIRED);
3473 #ifdef ELIMINABLE_REGS
3474 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3475 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3477 ep->from = ep1->from;
3479 ep->can_eliminate = ep->can_eliminate_previous
3480 = (CAN_ELIMINATE (ep->from, ep->to)
3481 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3484 reg_eliminate[0].from = reg_eliminate_1[0].from;
3485 reg_eliminate[0].to = reg_eliminate_1[0].to;
3486 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3487 = ! frame_pointer_needed;
3490 /* Count the number of eliminable registers and build the FROM and TO
3491 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3492 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3493 We depend on this. */
3494 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3496 num_eliminable += ep->can_eliminate;
3497 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3498 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3502 /* Kick all pseudos out of hard register REGNO.
3504 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3505 because we found we can't eliminate some register. In the case, no pseudos
3506 are allowed to be in the register, even if they are only in a block that
3507 doesn't require spill registers, unlike the case when we are spilling this
3508 hard reg to produce another spill register.
3510 Return nonzero if any pseudos needed to be kicked out. */
3513 spill_hard_reg (unsigned int regno, int cant_eliminate)
3519 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3520 regs_ever_live[regno] = 1;
3523 /* Spill every pseudo reg that was allocated to this reg
3524 or to something that overlaps this reg. */
3526 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3527 if (reg_renumber[i] >= 0
3528 && (unsigned int) reg_renumber[i] <= regno
3529 && ((unsigned int) reg_renumber[i]
3530 + hard_regno_nregs[(unsigned int) reg_renumber[i]]
3531 [PSEUDO_REGNO_MODE (i)]
3533 SET_REGNO_REG_SET (&spilled_pseudos, i);
3536 /* After find_reload_regs has been run for all insn that need reloads,
3537 and/or spill_hard_regs was called, this function is used to actually
3538 spill pseudo registers and try to reallocate them. It also sets up the
3539 spill_regs array for use by choose_reload_regs. */
3542 finish_spills (int global)
3544 struct insn_chain *chain;
3545 int something_changed = 0;
3547 reg_set_iterator rsi;
3549 /* Build the spill_regs array for the function. */
3550 /* If there are some registers still to eliminate and one of the spill regs
3551 wasn't ever used before, additional stack space may have to be
3552 allocated to store this register. Thus, we may have changed the offset
3553 between the stack and frame pointers, so mark that something has changed.
3555 One might think that we need only set VAL to 1 if this is a call-used
3556 register. However, the set of registers that must be saved by the
3557 prologue is not identical to the call-used set. For example, the
3558 register used by the call insn for the return PC is a call-used register,
3559 but must be saved by the prologue. */
3562 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3563 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3565 spill_reg_order[i] = n_spills;
3566 spill_regs[n_spills++] = i;
3567 if (num_eliminable && ! regs_ever_live[i])
3568 something_changed = 1;
3569 regs_ever_live[i] = 1;
3572 spill_reg_order[i] = -1;
3574 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3576 /* Record the current hard register the pseudo is allocated to in
3577 pseudo_previous_regs so we avoid reallocating it to the same
3578 hard reg in a later pass. */
3579 gcc_assert (reg_renumber[i] >= 0);
3581 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3582 /* Mark it as no longer having a hard register home. */
3583 reg_renumber[i] = -1;
3584 /* We will need to scan everything again. */
3585 something_changed = 1;
3588 /* Retry global register allocation if possible. */
3591 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3592 /* For every insn that needs reloads, set the registers used as spill
3593 regs in pseudo_forbidden_regs for every pseudo live across the
3595 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3597 EXECUTE_IF_SET_IN_REG_SET
3598 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3600 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3601 chain->used_spill_regs);
3603 EXECUTE_IF_SET_IN_REG_SET
3604 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3606 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3607 chain->used_spill_regs);
3611 /* Retry allocating the spilled pseudos. For each reg, merge the
3612 various reg sets that indicate which hard regs can't be used,
3613 and call retry_global_alloc.
3614 We change spill_pseudos here to only contain pseudos that did not
3615 get a new hard register. */
3616 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3617 if (reg_old_renumber[i] != reg_renumber[i])
3619 HARD_REG_SET forbidden;
3620 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3621 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3622 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3623 retry_global_alloc (i, forbidden);
3624 if (reg_renumber[i] >= 0)
3625 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3629 /* Fix up the register information in the insn chain.
3630 This involves deleting those of the spilled pseudos which did not get
3631 a new hard register home from the live_{before,after} sets. */
3632 for (chain = reload_insn_chain; chain; chain = chain->next)
3634 HARD_REG_SET used_by_pseudos;
3635 HARD_REG_SET used_by_pseudos2;
3637 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3638 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3640 /* Mark any unallocated hard regs as available for spills. That
3641 makes inheritance work somewhat better. */
3642 if (chain->need_reload)
3644 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3645 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3646 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3648 /* Save the old value for the sanity test below. */
3649 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3651 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3652 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3653 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3654 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3656 /* Make sure we only enlarge the set. */
3657 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3663 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3664 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3666 int regno = reg_renumber[i];
3667 if (reg_old_renumber[i] == regno)
3670 alter_reg (i, reg_old_renumber[i]);
3671 reg_old_renumber[i] = regno;
3675 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3677 fprintf (dump_file, " Register %d now in %d.\n\n",
3678 i, reg_renumber[i]);
3682 return something_changed;
3685 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3688 scan_paradoxical_subregs (rtx x)
3692 enum rtx_code code = GET_CODE (x);
3702 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3710 if (REG_P (SUBREG_REG (x))
3711 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3712 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3713 = GET_MODE_SIZE (GET_MODE (x));
3720 fmt = GET_RTX_FORMAT (code);
3721 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3724 scan_paradoxical_subregs (XEXP (x, i));
3725 else if (fmt[i] == 'E')
3728 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3729 scan_paradoxical_subregs (XVECEXP (x, i, j));
3734 /* Reload pseudo-registers into hard regs around each insn as needed.
3735 Additional register load insns are output before the insn that needs it
3736 and perhaps store insns after insns that modify the reloaded pseudo reg.
3738 reg_last_reload_reg and reg_reloaded_contents keep track of
3739 which registers are already available in reload registers.
3740 We update these for the reloads that we perform,
3741 as the insns are scanned. */
3744 reload_as_needed (int live_known)
3746 struct insn_chain *chain;
3747 #if defined (AUTO_INC_DEC)
3752 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3753 memset (spill_reg_store, 0, sizeof spill_reg_store);
3754 reg_last_reload_reg = xcalloc (max_regno, sizeof (rtx));
3755 reg_has_output_reload = xmalloc (max_regno);
3756 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3757 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
3759 set_initial_elim_offsets ();
3761 for (chain = reload_insn_chain; chain; chain = chain->next)
3764 rtx insn = chain->insn;
3765 rtx old_next = NEXT_INSN (insn);
3767 /* If we pass a label, copy the offsets from the label information
3768 into the current offsets of each elimination. */
3770 set_offsets_for_label (insn);
3772 else if (INSN_P (insn))
3774 rtx oldpat = copy_rtx (PATTERN (insn));
3776 /* If this is a USE and CLOBBER of a MEM, ensure that any
3777 references to eliminable registers have been removed. */
3779 if ((GET_CODE (PATTERN (insn)) == USE
3780 || GET_CODE (PATTERN (insn)) == CLOBBER)
3781 && MEM_P (XEXP (PATTERN (insn), 0)))
3782 XEXP (XEXP (PATTERN (insn), 0), 0)
3783 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3784 GET_MODE (XEXP (PATTERN (insn), 0)),
3787 /* If we need to do register elimination processing, do so.
3788 This might delete the insn, in which case we are done. */
3789 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3791 eliminate_regs_in_insn (insn, 1);
3794 update_eliminable_offsets ();
3799 /* If need_elim is nonzero but need_reload is zero, one might think
3800 that we could simply set n_reloads to 0. However, find_reloads
3801 could have done some manipulation of the insn (such as swapping
3802 commutative operands), and these manipulations are lost during
3803 the first pass for every insn that needs register elimination.
3804 So the actions of find_reloads must be redone here. */
3806 if (! chain->need_elim && ! chain->need_reload
3807 && ! chain->need_operand_change)
3809 /* First find the pseudo regs that must be reloaded for this insn.
3810 This info is returned in the tables reload_... (see reload.h).
3811 Also modify the body of INSN by substituting RELOAD
3812 rtx's for those pseudo regs. */
3815 memset (reg_has_output_reload, 0, max_regno);
3816 CLEAR_HARD_REG_SET (reg_is_output_reload);
3818 find_reloads (insn, 1, spill_indirect_levels, live_known,
3824 rtx next = NEXT_INSN (insn);
3827 prev = PREV_INSN (insn);
3829 /* Now compute which reload regs to reload them into. Perhaps
3830 reusing reload regs from previous insns, or else output
3831 load insns to reload them. Maybe output store insns too.
3832 Record the choices of reload reg in reload_reg_rtx. */
3833 choose_reload_regs (chain);
3835 /* Merge any reloads that we didn't combine for fear of
3836 increasing the number of spill registers needed but now
3837 discover can be safely merged. */
3838 if (SMALL_REGISTER_CLASSES)
3839 merge_assigned_reloads (insn);
3841 /* Generate the insns to reload operands into or out of
3842 their reload regs. */
3843 emit_reload_insns (chain);
3845 /* Substitute the chosen reload regs from reload_reg_rtx
3846 into the insn's body (or perhaps into the bodies of other
3847 load and store insn that we just made for reloading
3848 and that we moved the structure into). */
3849 subst_reloads (insn);
3851 /* If this was an ASM, make sure that all the reload insns
3852 we have generated are valid. If not, give an error
3855 if (asm_noperands (PATTERN (insn)) >= 0)
3856 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3857 if (p != insn && INSN_P (p)
3858 && GET_CODE (PATTERN (p)) != USE
3859 && (recog_memoized (p) < 0
3860 || (extract_insn (p), ! constrain_operands (1))))
3862 error_for_asm (insn,
3863 "%<asm%> operand requires "
3864 "impossible reload");
3869 if (num_eliminable && chain->need_elim)
3870 update_eliminable_offsets ();
3872 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3873 is no longer validly lying around to save a future reload.
3874 Note that this does not detect pseudos that were reloaded
3875 for this insn in order to be stored in
3876 (obeying register constraints). That is correct; such reload
3877 registers ARE still valid. */
3878 note_stores (oldpat, forget_old_reloads_1, NULL);
3880 /* There may have been CLOBBER insns placed after INSN. So scan
3881 between INSN and NEXT and use them to forget old reloads. */
3882 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3883 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
3884 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3887 /* Likewise for regs altered by auto-increment in this insn.
3888 REG_INC notes have been changed by reloading:
3889 find_reloads_address_1 records substitutions for them,
3890 which have been performed by subst_reloads above. */
3891 for (i = n_reloads - 1; i >= 0; i--)
3893 rtx in_reg = rld[i].in_reg;
3896 enum rtx_code code = GET_CODE (in_reg);
3897 /* PRE_INC / PRE_DEC will have the reload register ending up
3898 with the same value as the stack slot, but that doesn't
3899 hold true for POST_INC / POST_DEC. Either we have to
3900 convert the memory access to a true POST_INC / POST_DEC,
3901 or we can't use the reload register for inheritance. */
3902 if ((code == POST_INC || code == POST_DEC)
3903 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3904 REGNO (rld[i].reg_rtx))
3905 /* Make sure it is the inc/dec pseudo, and not
3906 some other (e.g. output operand) pseudo. */
3907 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3908 == REGNO (XEXP (in_reg, 0))))
3911 rtx reload_reg = rld[i].reg_rtx;
3912 enum machine_mode mode = GET_MODE (reload_reg);
3916 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3918 /* We really want to ignore REG_INC notes here, so
3919 use PATTERN (p) as argument to reg_set_p . */
3920 if (reg_set_p (reload_reg, PATTERN (p)))
3922 n = count_occurrences (PATTERN (p), reload_reg, 0);
3927 n = validate_replace_rtx (reload_reg,
3928 gen_rtx_fmt_e (code,
3933 /* We must also verify that the constraints
3934 are met after the replacement. */
3937 n = constrain_operands (1);
3941 /* If the constraints were not met, then
3942 undo the replacement. */
3945 validate_replace_rtx (gen_rtx_fmt_e (code,
3958 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3960 /* Mark this as having an output reload so that the
3961 REG_INC processing code below won't invalidate
3962 the reload for inheritance. */
3963 SET_HARD_REG_BIT (reg_is_output_reload,
3964 REGNO (reload_reg));
3965 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3968 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
3971 else if ((code == PRE_INC || code == PRE_DEC)
3972 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3973 REGNO (rld[i].reg_rtx))
3974 /* Make sure it is the inc/dec pseudo, and not
3975 some other (e.g. output operand) pseudo. */
3976 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3977 == REGNO (XEXP (in_reg, 0))))
3979 SET_HARD_REG_BIT (reg_is_output_reload,
3980 REGNO (rld[i].reg_rtx));
3981 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3985 /* If a pseudo that got a hard register is auto-incremented,
3986 we must purge records of copying it into pseudos without
3988 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3989 if (REG_NOTE_KIND (x) == REG_INC)
3991 /* See if this pseudo reg was reloaded in this insn.
3992 If so, its last-reload info is still valid
3993 because it is based on this insn's reload. */
3994 for (i = 0; i < n_reloads; i++)
3995 if (rld[i].out == XEXP (x, 0))
3999 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4003 /* A reload reg's contents are unknown after a label. */
4005 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4007 /* Don't assume a reload reg is still good after a call insn
4008 if it is a call-used reg, or if it contains a value that will
4009 be partially clobbered by the call. */
4010 else if (CALL_P (insn))
4012 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4013 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4018 free (reg_last_reload_reg);
4019 free (reg_has_output_reload);
4022 /* Discard all record of any value reloaded from X,
4023 or reloaded in X from someplace else;
4024 unless X is an output reload reg of the current insn.
4026 X may be a hard reg (the reload reg)
4027 or it may be a pseudo reg that was reloaded from. */
4030 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4031 void *data ATTRIBUTE_UNUSED)
4036 /* note_stores does give us subregs of hard regs,
4037 subreg_regno_offset will abort if it is not a hard reg. */
4038 while (GET_CODE (x) == SUBREG)
4040 /* We ignore the subreg offset when calculating the regno,
4041 because we are using the entire underlying hard register
4051 if (regno >= FIRST_PSEUDO_REGISTER)
4057 nr = hard_regno_nregs[regno][GET_MODE (x)];
4058 /* Storing into a spilled-reg invalidates its contents.
4059 This can happen if a block-local pseudo is allocated to that reg
4060 and it wasn't spilled because this block's total need is 0.
4061 Then some insn might have an optional reload and use this reg. */
4062 for (i = 0; i < nr; i++)
4063 /* But don't do this if the reg actually serves as an output
4064 reload reg in the current instruction. */
4066 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4068 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4069 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4070 spill_reg_store[regno + i] = 0;
4074 /* Since value of X has changed,
4075 forget any value previously copied from it. */
4078 /* But don't forget a copy if this is the output reload
4079 that establishes the copy's validity. */
4080 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4081 reg_last_reload_reg[regno + nr] = 0;
4084 /* The following HARD_REG_SETs indicate when each hard register is
4085 used for a reload of various parts of the current insn. */
4087 /* If reg is unavailable for all reloads. */
4088 static HARD_REG_SET reload_reg_unavailable;
4089 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4090 static HARD_REG_SET reload_reg_used;
4091 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4092 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4093 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4094 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4095 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4096 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4097 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4098 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4099 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4100 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4101 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4102 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4103 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4104 static HARD_REG_SET reload_reg_used_in_op_addr;
4105 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4106 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4107 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4108 static HARD_REG_SET reload_reg_used_in_insn;
4109 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4110 static HARD_REG_SET reload_reg_used_in_other_addr;
4112 /* If reg is in use as a reload reg for any sort of reload. */
4113 static HARD_REG_SET reload_reg_used_at_all;
4115 /* If reg is use as an inherited reload. We just mark the first register
4117 static HARD_REG_SET reload_reg_used_for_inherit;
4119 /* Records which hard regs are used in any way, either as explicit use or
4120 by being allocated to a pseudo during any point of the current insn. */
4121 static HARD_REG_SET reg_used_in_insn;
4123 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4124 TYPE. MODE is used to indicate how many consecutive regs are
4128 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4129 enum machine_mode mode)
4131 unsigned int nregs = hard_regno_nregs[regno][mode];
4134 for (i = regno; i < nregs + regno; i++)
4139 SET_HARD_REG_BIT (reload_reg_used, i);
4142 case RELOAD_FOR_INPUT_ADDRESS:
4143 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4146 case RELOAD_FOR_INPADDR_ADDRESS:
4147 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4150 case RELOAD_FOR_OUTPUT_ADDRESS:
4151 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4154 case RELOAD_FOR_OUTADDR_ADDRESS:
4155 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4158 case RELOAD_FOR_OPERAND_ADDRESS:
4159 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4162 case RELOAD_FOR_OPADDR_ADDR:
4163 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4166 case RELOAD_FOR_OTHER_ADDRESS:
4167 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4170 case RELOAD_FOR_INPUT:
4171 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4174 case RELOAD_FOR_OUTPUT:
4175 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4178 case RELOAD_FOR_INSN:
4179 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4183 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4187 /* Similarly, but show REGNO is no longer in use for a reload. */
4190 clear_reload_reg_in_use (unsigned int regno, int opnum,
4191 enum reload_type type, enum machine_mode mode)
4193 unsigned int nregs = hard_regno_nregs[regno][mode];
4194 unsigned int start_regno, end_regno, r;
4196 /* A complication is that for some reload types, inheritance might
4197 allow multiple reloads of the same types to share a reload register.
4198 We set check_opnum if we have to check only reloads with the same
4199 operand number, and check_any if we have to check all reloads. */
4200 int check_opnum = 0;
4202 HARD_REG_SET *used_in_set;
4207 used_in_set = &reload_reg_used;
4210 case RELOAD_FOR_INPUT_ADDRESS:
4211 used_in_set = &reload_reg_used_in_input_addr[opnum];
4214 case RELOAD_FOR_INPADDR_ADDRESS:
4216 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4219 case RELOAD_FOR_OUTPUT_ADDRESS:
4220 used_in_set = &reload_reg_used_in_output_addr[opnum];
4223 case RELOAD_FOR_OUTADDR_ADDRESS:
4225 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4228 case RELOAD_FOR_OPERAND_ADDRESS:
4229 used_in_set = &reload_reg_used_in_op_addr;
4232 case RELOAD_FOR_OPADDR_ADDR:
4234 used_in_set = &reload_reg_used_in_op_addr_reload;
4237 case RELOAD_FOR_OTHER_ADDRESS:
4238 used_in_set = &reload_reg_used_in_other_addr;
4242 case RELOAD_FOR_INPUT:
4243 used_in_set = &reload_reg_used_in_input[opnum];
4246 case RELOAD_FOR_OUTPUT:
4247 used_in_set = &reload_reg_used_in_output[opnum];
4250 case RELOAD_FOR_INSN:
4251 used_in_set = &reload_reg_used_in_insn;
4256 /* We resolve conflicts with remaining reloads of the same type by
4257 excluding the intervals of reload registers by them from the
4258 interval of freed reload registers. Since we only keep track of
4259 one set of interval bounds, we might have to exclude somewhat
4260 more than what would be necessary if we used a HARD_REG_SET here.
4261 But this should only happen very infrequently, so there should
4262 be no reason to worry about it. */
4264 start_regno = regno;
4265 end_regno = regno + nregs;
4266 if (check_opnum || check_any)
4268 for (i = n_reloads - 1; i >= 0; i--)
4270 if (rld[i].when_needed == type
4271 && (check_any || rld[i].opnum == opnum)
4274 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4275 unsigned int conflict_end
4277 + hard_regno_nregs[conflict_start][rld[i].mode]);
4279 /* If there is an overlap with the first to-be-freed register,
4280 adjust the interval start. */
4281 if (conflict_start <= start_regno && conflict_end > start_regno)
4282 start_regno = conflict_end;
4283 /* Otherwise, if there is a conflict with one of the other
4284 to-be-freed registers, adjust the interval end. */
4285 if (conflict_start > start_regno && conflict_start < end_regno)
4286 end_regno = conflict_start;
4291 for (r = start_regno; r < end_regno; r++)
4292 CLEAR_HARD_REG_BIT (*used_in_set, r);
4295 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4296 specified by OPNUM and TYPE. */
4299 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4303 /* In use for a RELOAD_OTHER means it's not available for anything. */
4304 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4305 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4311 /* In use for anything means we can't use it for RELOAD_OTHER. */
4312 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4313 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4314 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4315 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4318 for (i = 0; i < reload_n_operands; i++)
4319 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4320 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4321 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4322 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4323 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4324 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4329 case RELOAD_FOR_INPUT:
4330 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4331 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4334 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4337 /* If it is used for some other input, can't use it. */
4338 for (i = 0; i < reload_n_operands; i++)
4339 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4342 /* If it is used in a later operand's address, can't use it. */
4343 for (i = opnum + 1; i < reload_n_operands; i++)
4344 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4345 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4350 case RELOAD_FOR_INPUT_ADDRESS:
4351 /* Can't use a register if it is used for an input address for this
4352 operand or used as an input in an earlier one. */
4353 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4354 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4357 for (i = 0; i < opnum; i++)
4358 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4363 case RELOAD_FOR_INPADDR_ADDRESS:
4364 /* Can't use a register if it is used for an input address
4365 for this operand or used as an input in an earlier
4367 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4370 for (i = 0; i < opnum; i++)
4371 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4376 case RELOAD_FOR_OUTPUT_ADDRESS:
4377 /* Can't use a register if it is used for an output address for this
4378 operand or used as an output in this or a later operand. Note
4379 that multiple output operands are emitted in reverse order, so
4380 the conflicting ones are those with lower indices. */
4381 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4384 for (i = 0; i <= opnum; i++)
4385 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4390 case RELOAD_FOR_OUTADDR_ADDRESS:
4391 /* Can't use a register if it is used for an output address
4392 for this operand or used as an output in this or a
4393 later operand. Note that multiple output operands are
4394 emitted in reverse order, so the conflicting ones are
4395 those with lower indices. */
4396 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4399 for (i = 0; i <= opnum; i++)
4400 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4405 case RELOAD_FOR_OPERAND_ADDRESS:
4406 for (i = 0; i < reload_n_operands; i++)
4407 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4410 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4411 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4413 case RELOAD_FOR_OPADDR_ADDR:
4414 for (i = 0; i < reload_n_operands; i++)
4415 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4418 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4420 case RELOAD_FOR_OUTPUT:
4421 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4422 outputs, or an operand address for this or an earlier output.
4423 Note that multiple output operands are emitted in reverse order,
4424 so the conflicting ones are those with higher indices. */
4425 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4428 for (i = 0; i < reload_n_operands; i++)
4429 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4432 for (i = opnum; i < reload_n_operands; i++)
4433 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4434 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4439 case RELOAD_FOR_INSN:
4440 for (i = 0; i < reload_n_operands; i++)
4441 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4442 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4445 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4446 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4448 case RELOAD_FOR_OTHER_ADDRESS:
4449 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4456 /* Return 1 if the value in reload reg REGNO, as used by a reload
4457 needed for the part of the insn specified by OPNUM and TYPE,
4458 is still available in REGNO at the end of the insn.
4460 We can assume that the reload reg was already tested for availability
4461 at the time it is needed, and we should not check this again,
4462 in case the reg has already been marked in use. */
4465 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4472 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4473 its value must reach the end. */
4476 /* If this use is for part of the insn,
4477 its value reaches if no subsequent part uses the same register.
4478 Just like the above function, don't try to do this with lots
4481 case RELOAD_FOR_OTHER_ADDRESS:
4482 /* Here we check for everything else, since these don't conflict
4483 with anything else and everything comes later. */
4485 for (i = 0; i < reload_n_operands; i++)
4486 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4487 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4488 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4489 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4490 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4491 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4494 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4495 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4496 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4497 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4499 case RELOAD_FOR_INPUT_ADDRESS:
4500 case RELOAD_FOR_INPADDR_ADDRESS:
4501 /* Similar, except that we check only for this and subsequent inputs
4502 and the address of only subsequent inputs and we do not need
4503 to check for RELOAD_OTHER objects since they are known not to
4506 for (i = opnum; i < reload_n_operands; i++)
4507 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4510 for (i = opnum + 1; i < reload_n_operands; i++)
4511 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4512 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4515 for (i = 0; i < reload_n_operands; i++)
4516 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4517 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4518 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4521 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4524 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4525 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4526 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4528 case RELOAD_FOR_INPUT:
4529 /* Similar to input address, except we start at the next operand for
4530 both input and input address and we do not check for
4531 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4534 for (i = opnum + 1; i < reload_n_operands; i++)
4535 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4536 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4537 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4540 /* ... fall through ... */
4542 case RELOAD_FOR_OPERAND_ADDRESS:
4543 /* Check outputs and their addresses. */
4545 for (i = 0; i < reload_n_operands; i++)
4546 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4547 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4548 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4551 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4553 case RELOAD_FOR_OPADDR_ADDR:
4554 for (i = 0; i < reload_n_operands; i++)
4555 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4556 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4557 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4560 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4561 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4562 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4564 case RELOAD_FOR_INSN:
4565 /* These conflict with other outputs with RELOAD_OTHER. So
4566 we need only check for output addresses. */
4568 opnum = reload_n_operands;
4570 /* ... fall through ... */
4572 case RELOAD_FOR_OUTPUT:
4573 case RELOAD_FOR_OUTPUT_ADDRESS:
4574 case RELOAD_FOR_OUTADDR_ADDRESS:
4575 /* We already know these can't conflict with a later output. So the
4576 only thing to check are later output addresses.
4577 Note that multiple output operands are emitted in reverse order,
4578 so the conflicting ones are those with lower indices. */
4579 for (i = 0; i < opnum; i++)
4580 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4581 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4591 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4594 This function uses the same algorithm as reload_reg_free_p above. */
4597 reloads_conflict (int r1, int r2)
4599 enum reload_type r1_type = rld[r1].when_needed;
4600 enum reload_type r2_type = rld[r2].when_needed;
4601 int r1_opnum = rld[r1].opnum;
4602 int r2_opnum = rld[r2].opnum;
4604 /* RELOAD_OTHER conflicts with everything. */
4605 if (r2_type == RELOAD_OTHER)
4608 /* Otherwise, check conflicts differently for each type. */
4612 case RELOAD_FOR_INPUT:
4613 return (r2_type == RELOAD_FOR_INSN
4614 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4615 || r2_type == RELOAD_FOR_OPADDR_ADDR
4616 || r2_type == RELOAD_FOR_INPUT
4617 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4618 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4619 && r2_opnum > r1_opnum));
4621 case RELOAD_FOR_INPUT_ADDRESS:
4622 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4623 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4625 case RELOAD_FOR_INPADDR_ADDRESS:
4626 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4627 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4629 case RELOAD_FOR_OUTPUT_ADDRESS:
4630 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4631 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4633 case RELOAD_FOR_OUTADDR_ADDRESS:
4634 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4635 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4637 case RELOAD_FOR_OPERAND_ADDRESS:
4638 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4639 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4641 case RELOAD_FOR_OPADDR_ADDR:
4642 return (r2_type == RELOAD_FOR_INPUT
4643 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4645 case RELOAD_FOR_OUTPUT:
4646 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4647 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4648 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4649 && r2_opnum >= r1_opnum));
4651 case RELOAD_FOR_INSN:
4652 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4653 || r2_type == RELOAD_FOR_INSN
4654 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4656 case RELOAD_FOR_OTHER_ADDRESS:
4657 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4667 /* Indexed by reload number, 1 if incoming value
4668 inherited from previous insns. */
4669 static char reload_inherited[MAX_RELOADS];
4671 /* For an inherited reload, this is the insn the reload was inherited from,
4672 if we know it. Otherwise, this is 0. */
4673 static rtx reload_inheritance_insn[MAX_RELOADS];
4675 /* If nonzero, this is a place to get the value of the reload,
4676 rather than using reload_in. */
4677 static rtx reload_override_in[MAX_RELOADS];
4679 /* For each reload, the hard register number of the register used,
4680 or -1 if we did not need a register for this reload. */
4681 static int reload_spill_index[MAX_RELOADS];
4683 /* Subroutine of free_for_value_p, used to check a single register.
4684 START_REGNO is the starting regno of the full reload register
4685 (possibly comprising multiple hard registers) that we are considering. */
4688 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4689 enum reload_type type, rtx value, rtx out,
4690 int reloadnum, int ignore_address_reloads)
4693 /* Set if we see an input reload that must not share its reload register
4694 with any new earlyclobber, but might otherwise share the reload
4695 register with an output or input-output reload. */
4696 int check_earlyclobber = 0;
4700 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4703 if (out == const0_rtx)
4709 /* We use some pseudo 'time' value to check if the lifetimes of the
4710 new register use would overlap with the one of a previous reload
4711 that is not read-only or uses a different value.
4712 The 'time' used doesn't have to be linear in any shape or form, just
4714 Some reload types use different 'buckets' for each operand.
4715 So there are MAX_RECOG_OPERANDS different time values for each
4717 We compute TIME1 as the time when the register for the prospective
4718 new reload ceases to be live, and TIME2 for each existing
4719 reload as the time when that the reload register of that reload
4721 Where there is little to be gained by exact lifetime calculations,
4722 we just make conservative assumptions, i.e. a longer lifetime;
4723 this is done in the 'default:' cases. */
4726 case RELOAD_FOR_OTHER_ADDRESS:
4727 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4728 time1 = copy ? 0 : 1;
4731 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4733 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4734 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4735 respectively, to the time values for these, we get distinct time
4736 values. To get distinct time values for each operand, we have to
4737 multiply opnum by at least three. We round that up to four because
4738 multiply by four is often cheaper. */
4739 case RELOAD_FOR_INPADDR_ADDRESS:
4740 time1 = opnum * 4 + 2;
4742 case RELOAD_FOR_INPUT_ADDRESS:
4743 time1 = opnum * 4 + 3;
4745 case RELOAD_FOR_INPUT:
4746 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4747 executes (inclusive). */
4748 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4750 case RELOAD_FOR_OPADDR_ADDR:
4752 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4753 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4755 case RELOAD_FOR_OPERAND_ADDRESS:
4756 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4758 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4760 case RELOAD_FOR_OUTADDR_ADDRESS:
4761 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4763 case RELOAD_FOR_OUTPUT_ADDRESS:
4764 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4767 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4770 for (i = 0; i < n_reloads; i++)
4772 rtx reg = rld[i].reg_rtx;
4773 if (reg && REG_P (reg)
4774 && ((unsigned) regno - true_regnum (reg)
4775 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
4778 rtx other_input = rld[i].in;
4780 /* If the other reload loads the same input value, that
4781 will not cause a conflict only if it's loading it into
4782 the same register. */
4783 if (true_regnum (reg) != start_regno)
4784 other_input = NULL_RTX;
4785 if (! other_input || ! rtx_equal_p (other_input, value)
4786 || rld[i].out || out)
4789 switch (rld[i].when_needed)
4791 case RELOAD_FOR_OTHER_ADDRESS:
4794 case RELOAD_FOR_INPADDR_ADDRESS:
4795 /* find_reloads makes sure that a
4796 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4797 by at most one - the first -
4798 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4799 address reload is inherited, the address address reload
4800 goes away, so we can ignore this conflict. */
4801 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4802 && ignore_address_reloads
4803 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4804 Then the address address is still needed to store
4805 back the new address. */
4806 && ! rld[reloadnum].out)
4808 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4809 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4811 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4812 && ignore_address_reloads
4813 /* Unless we are reloading an auto_inc expression. */
4814 && ! rld[reloadnum].out)
4816 time2 = rld[i].opnum * 4 + 2;
4818 case RELOAD_FOR_INPUT_ADDRESS:
4819 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4820 && ignore_address_reloads
4821 && ! rld[reloadnum].out)
4823 time2 = rld[i].opnum * 4 + 3;
4825 case RELOAD_FOR_INPUT:
4826 time2 = rld[i].opnum * 4 + 4;
4827 check_earlyclobber = 1;
4829 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4830 == MAX_RECOG_OPERAND * 4 */
4831 case RELOAD_FOR_OPADDR_ADDR:
4832 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4833 && ignore_address_reloads
4834 && ! rld[reloadnum].out)
4836 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4838 case RELOAD_FOR_OPERAND_ADDRESS:
4839 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4840 check_earlyclobber = 1;
4842 case RELOAD_FOR_INSN:
4843 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4845 case RELOAD_FOR_OUTPUT:
4846 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4847 instruction is executed. */
4848 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4850 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4851 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4853 case RELOAD_FOR_OUTADDR_ADDRESS:
4854 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4855 && ignore_address_reloads
4856 && ! rld[reloadnum].out)
4858 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4860 case RELOAD_FOR_OUTPUT_ADDRESS:
4861 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4864 /* If there is no conflict in the input part, handle this
4865 like an output reload. */
4866 if (! rld[i].in || rtx_equal_p (other_input, value))
4868 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4869 /* Earlyclobbered outputs must conflict with inputs. */
4870 if (earlyclobber_operand_p (rld[i].out))
4871 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4876 /* RELOAD_OTHER might be live beyond instruction execution,
4877 but this is not obvious when we set time2 = 1. So check
4878 here if there might be a problem with the new reload
4879 clobbering the register used by the RELOAD_OTHER. */
4887 && (! rld[i].in || rld[i].out
4888 || ! rtx_equal_p (other_input, value)))
4889 || (out && rld[reloadnum].out_reg
4890 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4896 /* Earlyclobbered outputs must conflict with inputs. */
4897 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4903 /* Return 1 if the value in reload reg REGNO, as used by a reload
4904 needed for the part of the insn specified by OPNUM and TYPE,
4905 may be used to load VALUE into it.
4907 MODE is the mode in which the register is used, this is needed to
4908 determine how many hard regs to test.
4910 Other read-only reloads with the same value do not conflict
4911 unless OUT is nonzero and these other reloads have to live while
4912 output reloads live.
4913 If OUT is CONST0_RTX, this is a special case: it means that the
4914 test should not be for using register REGNO as reload register, but
4915 for copying from register REGNO into the reload register.
4917 RELOADNUM is the number of the reload we want to load this value for;
4918 a reload does not conflict with itself.
4920 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4921 reloads that load an address for the very reload we are considering.
4923 The caller has to make sure that there is no conflict with the return
4927 free_for_value_p (int regno, enum machine_mode mode, int opnum,
4928 enum reload_type type, rtx value, rtx out, int reloadnum,
4929 int ignore_address_reloads)
4931 int nregs = hard_regno_nregs[regno][mode];
4933 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
4934 value, out, reloadnum,
4935 ignore_address_reloads))
4940 /* Return nonzero if the rtx X is invariant over the current function. */
4941 /* ??? Actually, the places where we use this expect exactly what
4942 * is tested here, and not everything that is function invariant. In
4943 * particular, the frame pointer and arg pointer are special cased;
4944 * pic_offset_table_rtx is not, and this will cause aborts when we
4945 * go to spill these things to memory. */
4948 function_invariant_p (rtx x)
4952 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4954 if (GET_CODE (x) == PLUS
4955 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
4956 && CONSTANT_P (XEXP (x, 1)))
4961 /* Determine whether the reload reg X overlaps any rtx'es used for
4962 overriding inheritance. Return nonzero if so. */
4965 conflicts_with_override (rtx x)
4968 for (i = 0; i < n_reloads; i++)
4969 if (reload_override_in[i]
4970 && reg_overlap_mentioned_p (x, reload_override_in[i]))
4975 /* Give an error message saying we failed to find a reload for INSN,
4976 and clear out reload R. */
4978 failed_reload (rtx insn, int r)
4980 if (asm_noperands (PATTERN (insn)) < 0)
4981 /* It's the compiler's fault. */
4982 fatal_insn ("could not find a spill register", insn);
4984 /* It's the user's fault; the operand's mode and constraint
4985 don't match. Disable this reload so we don't crash in final. */
4986 error_for_asm (insn,
4987 "%<asm%> operand constraint incompatible with operand size");
4991 rld[r].optional = 1;
4992 rld[r].secondary_p = 1;
4995 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
4996 for reload R. If it's valid, get an rtx for it. Return nonzero if
4999 set_reload_reg (int i, int r)
5002 rtx reg = spill_reg_rtx[i];
5004 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5005 spill_reg_rtx[i] = reg
5006 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5008 regno = true_regnum (reg);
5010 /* Detect when the reload reg can't hold the reload mode.
5011 This used to be one `if', but Sequent compiler can't handle that. */
5012 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5014 enum machine_mode test_mode = VOIDmode;
5016 test_mode = GET_MODE (rld[r].in);
5017 /* If rld[r].in has VOIDmode, it means we will load it
5018 in whatever mode the reload reg has: to wit, rld[r].mode.
5019 We have already tested that for validity. */
5020 /* Aside from that, we need to test that the expressions
5021 to reload from or into have modes which are valid for this
5022 reload register. Otherwise the reload insns would be invalid. */
5023 if (! (rld[r].in != 0 && test_mode != VOIDmode
5024 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5025 if (! (rld[r].out != 0
5026 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5028 /* The reg is OK. */
5031 /* Mark as in use for this insn the reload regs we use
5033 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5034 rld[r].when_needed, rld[r].mode);
5036 rld[r].reg_rtx = reg;
5037 reload_spill_index[r] = spill_regs[i];
5044 /* Find a spill register to use as a reload register for reload R.
5045 LAST_RELOAD is nonzero if this is the last reload for the insn being
5048 Set rld[R].reg_rtx to the register allocated.
5050 We return 1 if successful, or 0 if we couldn't find a spill reg and
5051 we didn't change anything. */
5054 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5059 /* If we put this reload ahead, thinking it is a group,
5060 then insist on finding a group. Otherwise we can grab a
5061 reg that some other reload needs.
5062 (That can happen when we have a 68000 DATA_OR_FP_REG
5063 which is a group of data regs or one fp reg.)
5064 We need not be so restrictive if there are no more reloads
5067 ??? Really it would be nicer to have smarter handling
5068 for that kind of reg class, where a problem like this is normal.
5069 Perhaps those classes should be avoided for reloading
5070 by use of more alternatives. */
5072 int force_group = rld[r].nregs > 1 && ! last_reload;
5074 /* If we want a single register and haven't yet found one,
5075 take any reg in the right class and not in use.
5076 If we want a consecutive group, here is where we look for it.
5078 We use two passes so we can first look for reload regs to
5079 reuse, which are already in use for other reloads in this insn,
5080 and only then use additional registers.
5081 I think that maximizing reuse is needed to make sure we don't
5082 run out of reload regs. Suppose we have three reloads, and
5083 reloads A and B can share regs. These need two regs.
5084 Suppose A and B are given different regs.
5085 That leaves none for C. */
5086 for (pass = 0; pass < 2; pass++)
5088 /* I is the index in spill_regs.
5089 We advance it round-robin between insns to use all spill regs
5090 equally, so that inherited reloads have a chance
5091 of leapfrogging each other. */
5095 for (count = 0; count < n_spills; count++)
5097 int class = (int) rld[r].class;
5103 regnum = spill_regs[i];
5105 if ((reload_reg_free_p (regnum, rld[r].opnum,
5108 /* We check reload_reg_used to make sure we
5109 don't clobber the return register. */
5110 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5111 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5112 rld[r].when_needed, rld[r].in,
5114 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5115 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5116 /* Look first for regs to share, then for unshared. But
5117 don't share regs used for inherited reloads; they are
5118 the ones we want to preserve. */
5120 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5122 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5125 int nr = hard_regno_nregs[regnum][rld[r].mode];
5126 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5127 (on 68000) got us two FP regs. If NR is 1,
5128 we would reject both of them. */
5131 /* If we need only one reg, we have already won. */
5134 /* But reject a single reg if we demand a group. */
5139 /* Otherwise check that as many consecutive regs as we need
5140 are available here. */
5143 int regno = regnum + nr - 1;
5144 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5145 && spill_reg_order[regno] >= 0
5146 && reload_reg_free_p (regno, rld[r].opnum,
5147 rld[r].when_needed)))
5156 /* If we found something on pass 1, omit pass 2. */
5157 if (count < n_spills)
5161 /* We should have found a spill register by now. */
5162 if (count >= n_spills)
5165 /* I is the index in SPILL_REG_RTX of the reload register we are to
5166 allocate. Get an rtx for it and find its register number. */
5168 return set_reload_reg (i, r);
5171 /* Initialize all the tables needed to allocate reload registers.
5172 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5173 is the array we use to restore the reg_rtx field for every reload. */
5176 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5180 for (i = 0; i < n_reloads; i++)
5181 rld[i].reg_rtx = save_reload_reg_rtx[i];
5183 memset (reload_inherited, 0, MAX_RELOADS);
5184 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5185 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5187 CLEAR_HARD_REG_SET (reload_reg_used);
5188 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5189 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5190 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5191 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5192 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5194 CLEAR_HARD_REG_SET (reg_used_in_insn);
5197 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5198 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5199 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5200 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5201 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5202 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5205 for (i = 0; i < reload_n_operands; i++)
5207 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5208 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5209 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5210 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5211 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5212 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5215 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5217 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5219 for (i = 0; i < n_reloads; i++)
5220 /* If we have already decided to use a certain register,
5221 don't use it in another way. */
5223 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5224 rld[i].when_needed, rld[i].mode);
5227 /* Assign hard reg targets for the pseudo-registers we must reload
5228 into hard regs for this insn.
5229 Also output the instructions to copy them in and out of the hard regs.
5231 For machines with register classes, we are responsible for
5232 finding a reload reg in the proper class. */
5235 choose_reload_regs (struct insn_chain *chain)
5237 rtx insn = chain->insn;
5239 unsigned int max_group_size = 1;
5240 enum reg_class group_class = NO_REGS;
5241 int pass, win, inheritance;
5243 rtx save_reload_reg_rtx[MAX_RELOADS];
5245 /* In order to be certain of getting the registers we need,
5246 we must sort the reloads into order of increasing register class.
5247 Then our grabbing of reload registers will parallel the process
5248 that provided the reload registers.
5250 Also note whether any of the reloads wants a consecutive group of regs.
5251 If so, record the maximum size of the group desired and what
5252 register class contains all the groups needed by this insn. */
5254 for (j = 0; j < n_reloads; j++)
5256 reload_order[j] = j;
5257 reload_spill_index[j] = -1;
5259 if (rld[j].nregs > 1)
5261 max_group_size = MAX (rld[j].nregs, max_group_size);
5263 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5266 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5270 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5272 /* If -O, try first with inheritance, then turning it off.
5273 If not -O, don't do inheritance.
5274 Using inheritance when not optimizing leads to paradoxes
5275 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5276 because one side of the comparison might be inherited. */
5278 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5280 choose_reload_regs_init (chain, save_reload_reg_rtx);
5282 /* Process the reloads in order of preference just found.
5283 Beyond this point, subregs can be found in reload_reg_rtx.
5285 This used to look for an existing reloaded home for all of the
5286 reloads, and only then perform any new reloads. But that could lose
5287 if the reloads were done out of reg-class order because a later
5288 reload with a looser constraint might have an old home in a register
5289 needed by an earlier reload with a tighter constraint.
5291 To solve this, we make two passes over the reloads, in the order
5292 described above. In the first pass we try to inherit a reload
5293 from a previous insn. If there is a later reload that needs a
5294 class that is a proper subset of the class being processed, we must
5295 also allocate a spill register during the first pass.
5297 Then make a second pass over the reloads to allocate any reloads
5298 that haven't been given registers yet. */
5300 for (j = 0; j < n_reloads; j++)
5302 int r = reload_order[j];
5303 rtx search_equiv = NULL_RTX;
5305 /* Ignore reloads that got marked inoperative. */
5306 if (rld[r].out == 0 && rld[r].in == 0
5307 && ! rld[r].secondary_p)
5310 /* If find_reloads chose to use reload_in or reload_out as a reload
5311 register, we don't need to chose one. Otherwise, try even if it
5312 found one since we might save an insn if we find the value lying
5314 Try also when reload_in is a pseudo without a hard reg. */
5315 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5316 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5317 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5318 && !MEM_P (rld[r].in)
5319 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5322 #if 0 /* No longer needed for correct operation.
5323 It might give better code, or might not; worth an experiment? */
5324 /* If this is an optional reload, we can't inherit from earlier insns
5325 until we are sure that any non-optional reloads have been allocated.
5326 The following code takes advantage of the fact that optional reloads
5327 are at the end of reload_order. */
5328 if (rld[r].optional != 0)
5329 for (i = 0; i < j; i++)
5330 if ((rld[reload_order[i]].out != 0
5331 || rld[reload_order[i]].in != 0
5332 || rld[reload_order[i]].secondary_p)
5333 && ! rld[reload_order[i]].optional
5334 && rld[reload_order[i]].reg_rtx == 0)
5335 allocate_reload_reg (chain, reload_order[i], 0);
5338 /* First see if this pseudo is already available as reloaded
5339 for a previous insn. We cannot try to inherit for reloads
5340 that are smaller than the maximum number of registers needed
5341 for groups unless the register we would allocate cannot be used
5344 We could check here to see if this is a secondary reload for
5345 an object that is already in a register of the desired class.
5346 This would avoid the need for the secondary reload register.
5347 But this is complex because we can't easily determine what
5348 objects might want to be loaded via this reload. So let a
5349 register be allocated here. In `emit_reload_insns' we suppress
5350 one of the loads in the case described above. */
5356 enum machine_mode mode = VOIDmode;
5360 else if (REG_P (rld[r].in))
5362 regno = REGNO (rld[r].in);
5363 mode = GET_MODE (rld[r].in);
5365 else if (REG_P (rld[r].in_reg))
5367 regno = REGNO (rld[r].in_reg);
5368 mode = GET_MODE (rld[r].in_reg);
5370 else if (GET_CODE (rld[r].in_reg) == SUBREG
5371 && REG_P (SUBREG_REG (rld[r].in_reg)))
5373 byte = SUBREG_BYTE (rld[r].in_reg);
5374 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5375 if (regno < FIRST_PSEUDO_REGISTER)
5376 regno = subreg_regno (rld[r].in_reg);
5377 mode = GET_MODE (rld[r].in_reg);
5380 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5381 || GET_CODE (rld[r].in_reg) == PRE_DEC
5382 || GET_CODE (rld[r].in_reg) == POST_INC
5383 || GET_CODE (rld[r].in_reg) == POST_DEC)
5384 && REG_P (XEXP (rld[r].in_reg, 0)))
5386 regno = REGNO (XEXP (rld[r].in_reg, 0));
5387 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5388 rld[r].out = rld[r].in;
5392 /* This won't work, since REGNO can be a pseudo reg number.
5393 Also, it takes much more hair to keep track of all the things
5394 that can invalidate an inherited reload of part of a pseudoreg. */
5395 else if (GET_CODE (rld[r].in) == SUBREG
5396 && REG_P (SUBREG_REG (rld[r].in)))
5397 regno = subreg_regno (rld[r].in);
5400 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5402 enum reg_class class = rld[r].class, last_class;
5403 rtx last_reg = reg_last_reload_reg[regno];
5404 enum machine_mode need_mode;
5406 i = REGNO (last_reg);
5407 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5408 last_class = REGNO_REG_CLASS (i);
5414 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
5415 + byte * BITS_PER_UNIT,
5416 GET_MODE_CLASS (mode));
5418 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5419 >= GET_MODE_SIZE (need_mode))
5420 #ifdef CANNOT_CHANGE_MODE_CLASS
5421 /* Verify that the register in "i" can be obtained
5423 && !REG_CANNOT_CHANGE_MODE_P (REGNO (last_reg),
5424 GET_MODE (last_reg),
5427 && reg_reloaded_contents[i] == regno
5428 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5429 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5430 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5431 /* Even if we can't use this register as a reload
5432 register, we might use it for reload_override_in,
5433 if copying it to the desired class is cheap
5435 || ((REGISTER_MOVE_COST (mode, last_class, class)
5436 < MEMORY_MOVE_COST (mode, class, 1))
5437 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5438 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5442 #ifdef SECONDARY_MEMORY_NEEDED
5443 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5448 && (rld[r].nregs == max_group_size
5449 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5451 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5452 rld[r].when_needed, rld[r].in,
5455 /* If a group is needed, verify that all the subsequent
5456 registers still have their values intact. */
5457 int nr = hard_regno_nregs[i][rld[r].mode];
5460 for (k = 1; k < nr; k++)
5461 if (reg_reloaded_contents[i + k] != regno
5462 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5470 last_reg = (GET_MODE (last_reg) == mode
5471 ? last_reg : gen_rtx_REG (mode, i));
5474 for (k = 0; k < nr; k++)
5475 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5478 /* We found a register that contains the
5479 value we need. If this register is the
5480 same as an `earlyclobber' operand of the
5481 current insn, just mark it as a place to
5482 reload from since we can't use it as the
5483 reload register itself. */
5485 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5486 if (reg_overlap_mentioned_for_reload_p
5487 (reg_last_reload_reg[regno],
5488 reload_earlyclobbers[i1]))
5491 if (i1 != n_earlyclobbers
5492 || ! (free_for_value_p (i, rld[r].mode,
5494 rld[r].when_needed, rld[r].in,
5496 /* Don't use it if we'd clobber a pseudo reg. */
5497 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5499 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5500 /* Don't clobber the frame pointer. */
5501 || (i == HARD_FRAME_POINTER_REGNUM
5502 && frame_pointer_needed
5504 /* Don't really use the inherited spill reg
5505 if we need it wider than we've got it. */
5506 || (GET_MODE_SIZE (rld[r].mode)
5507 > GET_MODE_SIZE (mode))
5510 /* If find_reloads chose reload_out as reload
5511 register, stay with it - that leaves the
5512 inherited register for subsequent reloads. */
5513 || (rld[r].out && rld[r].reg_rtx
5514 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5516 if (! rld[r].optional)
5518 reload_override_in[r] = last_reg;
5519 reload_inheritance_insn[r]
5520 = reg_reloaded_insn[i];
5526 /* We can use this as a reload reg. */
5527 /* Mark the register as in use for this part of
5529 mark_reload_reg_in_use (i,
5533 rld[r].reg_rtx = last_reg;
5534 reload_inherited[r] = 1;
5535 reload_inheritance_insn[r]
5536 = reg_reloaded_insn[i];
5537 reload_spill_index[r] = i;
5538 for (k = 0; k < nr; k++)
5539 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5547 /* Here's another way to see if the value is already lying around. */
5550 && ! reload_inherited[r]
5552 && (CONSTANT_P (rld[r].in)
5553 || GET_CODE (rld[r].in) == PLUS
5554 || REG_P (rld[r].in)
5555 || MEM_P (rld[r].in))
5556 && (rld[r].nregs == max_group_size
5557 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5558 search_equiv = rld[r].in;
5559 /* If this is an output reload from a simple move insn, look
5560 if an equivalence for the input is available. */
5561 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5563 rtx set = single_set (insn);
5566 && rtx_equal_p (rld[r].out, SET_DEST (set))
5567 && CONSTANT_P (SET_SRC (set)))
5568 search_equiv = SET_SRC (set);
5574 = find_equiv_reg (search_equiv, insn, rld[r].class,
5575 -1, NULL, 0, rld[r].mode);
5581 regno = REGNO (equiv);
5584 /* This must be a SUBREG of a hard register.
5585 Make a new REG since this might be used in an
5586 address and not all machines support SUBREGs
5588 gcc_assert (GET_CODE (equiv) == SUBREG);
5589 regno = subreg_regno (equiv);
5590 equiv = gen_rtx_REG (rld[r].mode, regno);
5591 /* If we choose EQUIV as the reload register, but the
5592 loop below decides to cancel the inheritance, we'll
5593 end up reloading EQUIV in rld[r].mode, not the mode
5594 it had originally. That isn't safe when EQUIV isn't
5595 available as a spill register since its value might
5596 still be live at this point. */
5597 for (i = regno; i < regno + (int) rld[r].nregs; i++)
5598 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
5603 /* If we found a spill reg, reject it unless it is free
5604 and of the desired class. */
5608 int bad_for_class = 0;
5609 int max_regno = regno + rld[r].nregs;
5611 for (i = regno; i < max_regno; i++)
5613 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5615 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5620 && ! free_for_value_p (regno, rld[r].mode,
5621 rld[r].opnum, rld[r].when_needed,
5622 rld[r].in, rld[r].out, r, 1))
5627 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5630 /* We found a register that contains the value we need.
5631 If this register is the same as an `earlyclobber' operand
5632 of the current insn, just mark it as a place to reload from
5633 since we can't use it as the reload register itself. */
5636 for (i = 0; i < n_earlyclobbers; i++)
5637 if (reg_overlap_mentioned_for_reload_p (equiv,
5638 reload_earlyclobbers[i]))
5640 if (! rld[r].optional)
5641 reload_override_in[r] = equiv;
5646 /* If the equiv register we have found is explicitly clobbered
5647 in the current insn, it depends on the reload type if we
5648 can use it, use it for reload_override_in, or not at all.
5649 In particular, we then can't use EQUIV for a
5650 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5654 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5655 switch (rld[r].when_needed)
5657 case RELOAD_FOR_OTHER_ADDRESS:
5658 case RELOAD_FOR_INPADDR_ADDRESS:
5659 case RELOAD_FOR_INPUT_ADDRESS:
5660 case RELOAD_FOR_OPADDR_ADDR:
5663 case RELOAD_FOR_INPUT:
5664 case RELOAD_FOR_OPERAND_ADDRESS:
5665 if (! rld[r].optional)
5666 reload_override_in[r] = equiv;
5672 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5673 switch (rld[r].when_needed)
5675 case RELOAD_FOR_OTHER_ADDRESS:
5676 case RELOAD_FOR_INPADDR_ADDRESS:
5677 case RELOAD_FOR_INPUT_ADDRESS:
5678 case RELOAD_FOR_OPADDR_ADDR:
5679 case RELOAD_FOR_OPERAND_ADDRESS:
5680 case RELOAD_FOR_INPUT:
5683 if (! rld[r].optional)
5684 reload_override_in[r] = equiv;
5692 /* If we found an equivalent reg, say no code need be generated
5693 to load it, and use it as our reload reg. */
5695 && (regno != HARD_FRAME_POINTER_REGNUM
5696 || !frame_pointer_needed))
5698 int nr = hard_regno_nregs[regno][rld[r].mode];
5700 rld[r].reg_rtx = equiv;
5701 reload_inherited[r] = 1;
5703 /* If reg_reloaded_valid is not set for this register,
5704 there might be a stale spill_reg_store lying around.
5705 We must clear it, since otherwise emit_reload_insns
5706 might delete the store. */
5707 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5708 spill_reg_store[regno] = NULL_RTX;
5709 /* If any of the hard registers in EQUIV are spill
5710 registers, mark them as in use for this insn. */
5711 for (k = 0; k < nr; k++)
5713 i = spill_reg_order[regno + k];
5716 mark_reload_reg_in_use (regno, rld[r].opnum,
5719 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5726 /* If we found a register to use already, or if this is an optional
5727 reload, we are done. */
5728 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5732 /* No longer needed for correct operation. Might or might
5733 not give better code on the average. Want to experiment? */
5735 /* See if there is a later reload that has a class different from our
5736 class that intersects our class or that requires less register
5737 than our reload. If so, we must allocate a register to this
5738 reload now, since that reload might inherit a previous reload
5739 and take the only available register in our class. Don't do this
5740 for optional reloads since they will force all previous reloads
5741 to be allocated. Also don't do this for reloads that have been
5744 for (i = j + 1; i < n_reloads; i++)
5746 int s = reload_order[i];
5748 if ((rld[s].in == 0 && rld[s].out == 0
5749 && ! rld[s].secondary_p)
5753 if ((rld[s].class != rld[r].class
5754 && reg_classes_intersect_p (rld[r].class,
5756 || rld[s].nregs < rld[r].nregs)
5763 allocate_reload_reg (chain, r, j == n_reloads - 1);
5767 /* Now allocate reload registers for anything non-optional that
5768 didn't get one yet. */
5769 for (j = 0; j < n_reloads; j++)
5771 int r = reload_order[j];
5773 /* Ignore reloads that got marked inoperative. */
5774 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5777 /* Skip reloads that already have a register allocated or are
5779 if (rld[r].reg_rtx != 0 || rld[r].optional)
5782 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5786 /* If that loop got all the way, we have won. */
5793 /* Loop around and try without any inheritance. */
5798 /* First undo everything done by the failed attempt
5799 to allocate with inheritance. */
5800 choose_reload_regs_init (chain, save_reload_reg_rtx);
5802 /* Some sanity tests to verify that the reloads found in the first
5803 pass are identical to the ones we have now. */
5804 gcc_assert (chain->n_reloads == n_reloads);
5806 for (i = 0; i < n_reloads; i++)
5808 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5810 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
5811 for (j = 0; j < n_spills; j++)
5812 if (spill_regs[j] == chain->rld[i].regno)
5813 if (! set_reload_reg (j, i))
5814 failed_reload (chain->insn, i);
5818 /* If we thought we could inherit a reload, because it seemed that
5819 nothing else wanted the same reload register earlier in the insn,
5820 verify that assumption, now that all reloads have been assigned.
5821 Likewise for reloads where reload_override_in has been set. */
5823 /* If doing expensive optimizations, do one preliminary pass that doesn't
5824 cancel any inheritance, but removes reloads that have been needed only
5825 for reloads that we know can be inherited. */
5826 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5828 for (j = 0; j < n_reloads; j++)
5830 int r = reload_order[j];
5832 if (reload_inherited[r] && rld[r].reg_rtx)
5833 check_reg = rld[r].reg_rtx;
5834 else if (reload_override_in[r]
5835 && (REG_P (reload_override_in[r])
5836 || GET_CODE (reload_override_in[r]) == SUBREG))
5837 check_reg = reload_override_in[r];
5840 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5841 rld[r].opnum, rld[r].when_needed, rld[r].in,
5842 (reload_inherited[r]
5843 ? rld[r].out : const0_rtx),
5848 reload_inherited[r] = 0;
5849 reload_override_in[r] = 0;
5851 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5852 reload_override_in, then we do not need its related
5853 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5854 likewise for other reload types.
5855 We handle this by removing a reload when its only replacement
5856 is mentioned in reload_in of the reload we are going to inherit.
5857 A special case are auto_inc expressions; even if the input is
5858 inherited, we still need the address for the output. We can
5859 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5860 If we succeeded removing some reload and we are doing a preliminary
5861 pass just to remove such reloads, make another pass, since the
5862 removal of one reload might allow us to inherit another one. */
5864 && rld[r].out != rld[r].in
5865 && remove_address_replacements (rld[r].in) && pass)
5870 /* Now that reload_override_in is known valid,
5871 actually override reload_in. */
5872 for (j = 0; j < n_reloads; j++)
5873 if (reload_override_in[j])
5874 rld[j].in = reload_override_in[j];
5876 /* If this reload won't be done because it has been canceled or is
5877 optional and not inherited, clear reload_reg_rtx so other
5878 routines (such as subst_reloads) don't get confused. */
5879 for (j = 0; j < n_reloads; j++)
5880 if (rld[j].reg_rtx != 0
5881 && ((rld[j].optional && ! reload_inherited[j])
5882 || (rld[j].in == 0 && rld[j].out == 0
5883 && ! rld[j].secondary_p)))
5885 int regno = true_regnum (rld[j].reg_rtx);
5887 if (spill_reg_order[regno] >= 0)
5888 clear_reload_reg_in_use (regno, rld[j].opnum,
5889 rld[j].when_needed, rld[j].mode);
5891 reload_spill_index[j] = -1;
5894 /* Record which pseudos and which spill regs have output reloads. */
5895 for (j = 0; j < n_reloads; j++)
5897 int r = reload_order[j];
5899 i = reload_spill_index[r];
5901 /* I is nonneg if this reload uses a register.
5902 If rld[r].reg_rtx is 0, this is an optional reload
5903 that we opted to ignore. */
5904 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
5905 && rld[r].reg_rtx != 0)
5907 int nregno = REGNO (rld[r].out_reg);
5910 if (nregno < FIRST_PSEUDO_REGISTER)
5911 nr = hard_regno_nregs[nregno][rld[r].mode];
5914 reg_has_output_reload[nregno + nr] = 1;
5918 nr = hard_regno_nregs[i][rld[r].mode];
5920 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5923 gcc_assert (rld[r].when_needed == RELOAD_OTHER
5924 || rld[r].when_needed == RELOAD_FOR_OUTPUT
5925 || rld[r].when_needed == RELOAD_FOR_INSN);
5930 /* Deallocate the reload register for reload R. This is called from
5931 remove_address_replacements. */
5934 deallocate_reload_reg (int r)
5938 if (! rld[r].reg_rtx)
5940 regno = true_regnum (rld[r].reg_rtx);
5942 if (spill_reg_order[regno] >= 0)
5943 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5945 reload_spill_index[r] = -1;
5948 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
5949 reloads of the same item for fear that we might not have enough reload
5950 registers. However, normally they will get the same reload register
5951 and hence actually need not be loaded twice.
5953 Here we check for the most common case of this phenomenon: when we have
5954 a number of reloads for the same object, each of which were allocated
5955 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5956 reload, and is not modified in the insn itself. If we find such,
5957 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5958 This will not increase the number of spill registers needed and will
5959 prevent redundant code. */
5962 merge_assigned_reloads (rtx insn)
5966 /* Scan all the reloads looking for ones that only load values and
5967 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5968 assigned and not modified by INSN. */
5970 for (i = 0; i < n_reloads; i++)
5972 int conflicting_input = 0;
5973 int max_input_address_opnum = -1;
5974 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
5976 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
5977 || rld[i].out != 0 || rld[i].reg_rtx == 0
5978 || reg_set_p (rld[i].reg_rtx, insn))
5981 /* Look at all other reloads. Ensure that the only use of this
5982 reload_reg_rtx is in a reload that just loads the same value
5983 as we do. Note that any secondary reloads must be of the identical
5984 class since the values, modes, and result registers are the
5985 same, so we need not do anything with any secondary reloads. */
5987 for (j = 0; j < n_reloads; j++)
5989 if (i == j || rld[j].reg_rtx == 0
5990 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
5994 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5995 && rld[j].opnum > max_input_address_opnum)
5996 max_input_address_opnum = rld[j].opnum;
5998 /* If the reload regs aren't exactly the same (e.g, different modes)
5999 or if the values are different, we can't merge this reload.
6000 But if it is an input reload, we might still merge
6001 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6003 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6004 || rld[j].out != 0 || rld[j].in == 0
6005 || ! rtx_equal_p (rld[i].in, rld[j].in))
6007 if (rld[j].when_needed != RELOAD_FOR_INPUT
6008 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6009 || rld[i].opnum > rld[j].opnum)
6010 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6012 conflicting_input = 1;
6013 if (min_conflicting_input_opnum > rld[j].opnum)
6014 min_conflicting_input_opnum = rld[j].opnum;
6018 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6019 we, in fact, found any matching reloads. */
6022 && max_input_address_opnum <= min_conflicting_input_opnum)
6024 for (j = 0; j < n_reloads; j++)
6025 if (i != j && rld[j].reg_rtx != 0
6026 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6027 && (! conflicting_input
6028 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6029 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6031 rld[i].when_needed = RELOAD_OTHER;
6033 reload_spill_index[j] = -1;
6034 transfer_replacements (i, j);
6037 /* If this is now RELOAD_OTHER, look for any reloads that load
6038 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6039 if they were for inputs, RELOAD_OTHER for outputs. Note that
6040 this test is equivalent to looking for reloads for this operand
6042 /* We must take special care when there are two or more reloads to
6043 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6044 same value or a part of it; we must not change its type if there
6045 is a conflicting input. */
6047 if (rld[i].when_needed == RELOAD_OTHER)
6048 for (j = 0; j < n_reloads; j++)
6050 && rld[j].when_needed != RELOAD_OTHER
6051 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6052 && (! conflicting_input
6053 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6054 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6055 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6061 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6062 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6063 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6065 /* Check to see if we accidentally converted two reloads
6066 that use the same reload register with different inputs
6067 to the same type. If so, the resulting code won't work,
6070 for (k = 0; k < j; k++)
6071 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6072 || rld[k].when_needed != rld[j].when_needed
6073 || !rtx_equal_p (rld[k].reg_rtx,
6075 || rtx_equal_p (rld[k].in,
6082 /* These arrays are filled by emit_reload_insns and its subroutines. */
6083 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6084 static rtx other_input_address_reload_insns = 0;
6085 static rtx other_input_reload_insns = 0;
6086 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6087 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6088 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6089 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6090 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6091 static rtx operand_reload_insns = 0;
6092 static rtx other_operand_reload_insns = 0;
6093 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6095 /* Values to be put in spill_reg_store are put here first. */
6096 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6097 static HARD_REG_SET reg_reloaded_died;
6099 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6100 has the number J. OLD contains the value to be used as input. */
6103 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6106 rtx insn = chain->insn;
6107 rtx reloadreg = rl->reg_rtx;
6108 rtx oldequiv_reg = 0;
6111 enum machine_mode mode;
6114 /* Determine the mode to reload in.
6115 This is very tricky because we have three to choose from.
6116 There is the mode the insn operand wants (rl->inmode).
6117 There is the mode of the reload register RELOADREG.
6118 There is the intrinsic mode of the operand, which we could find
6119 by stripping some SUBREGs.
6120 It turns out that RELOADREG's mode is irrelevant:
6121 we can change that arbitrarily.
6123 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6124 then the reload reg may not support QImode moves, so use SImode.
6125 If foo is in memory due to spilling a pseudo reg, this is safe,
6126 because the QImode value is in the least significant part of a
6127 slot big enough for a SImode. If foo is some other sort of
6128 memory reference, then it is impossible to reload this case,
6129 so previous passes had better make sure this never happens.
6131 Then consider a one-word union which has SImode and one of its
6132 members is a float, being fetched as (SUBREG:SF union:SI).
6133 We must fetch that as SFmode because we could be loading into
6134 a float-only register. In this case OLD's mode is correct.
6136 Consider an immediate integer: it has VOIDmode. Here we need
6137 to get a mode from something else.
6139 In some cases, there is a fourth mode, the operand's
6140 containing mode. If the insn specifies a containing mode for
6141 this operand, it overrides all others.
6143 I am not sure whether the algorithm here is always right,
6144 but it does the right things in those cases. */
6146 mode = GET_MODE (old);
6147 if (mode == VOIDmode)
6150 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6151 /* If we need a secondary register for this operation, see if
6152 the value is already in a register in that class. Don't
6153 do this if the secondary register will be used as a scratch
6156 if (rl->secondary_in_reload >= 0
6157 && rl->secondary_in_icode == CODE_FOR_nothing
6160 = find_equiv_reg (old, insn,
6161 rld[rl->secondary_in_reload].class,
6165 /* If reloading from memory, see if there is a register
6166 that already holds the same value. If so, reload from there.
6167 We can pass 0 as the reload_reg_p argument because
6168 any other reload has either already been emitted,
6169 in which case find_equiv_reg will see the reload-insn,
6170 or has yet to be emitted, in which case it doesn't matter
6171 because we will use this equiv reg right away. */
6173 if (oldequiv == 0 && optimize
6176 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6177 && reg_renumber[REGNO (old)] < 0)))
6178 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6182 unsigned int regno = true_regnum (oldequiv);
6184 /* Don't use OLDEQUIV if any other reload changes it at an
6185 earlier stage of this insn or at this stage. */
6186 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6187 rl->in, const0_rtx, j, 0))
6190 /* If it is no cheaper to copy from OLDEQUIV into the
6191 reload register than it would be to move from memory,
6192 don't use it. Likewise, if we need a secondary register
6196 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6197 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6199 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6200 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6201 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6205 #ifdef SECONDARY_MEMORY_NEEDED
6206 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6214 /* delete_output_reload is only invoked properly if old contains
6215 the original pseudo register. Since this is replaced with a
6216 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6217 find the pseudo in RELOAD_IN_REG. */
6219 && reload_override_in[j]
6220 && REG_P (rl->in_reg))
6227 else if (REG_P (oldequiv))
6228 oldequiv_reg = oldequiv;
6229 else if (GET_CODE (oldequiv) == SUBREG)
6230 oldequiv_reg = SUBREG_REG (oldequiv);
6232 /* If we are reloading from a register that was recently stored in
6233 with an output-reload, see if we can prove there was
6234 actually no need to store the old value in it. */
6236 if (optimize && REG_P (oldequiv)
6237 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6238 && spill_reg_store[REGNO (oldequiv)]
6240 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6241 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6243 delete_output_reload (insn, j, REGNO (oldequiv));
6245 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6246 then load RELOADREG from OLDEQUIV. Note that we cannot use
6247 gen_lowpart_common since it can do the wrong thing when
6248 RELOADREG has a multi-word mode. Note that RELOADREG
6249 must always be a REG here. */
6251 if (GET_MODE (reloadreg) != mode)
6252 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6253 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6254 oldequiv = SUBREG_REG (oldequiv);
6255 if (GET_MODE (oldequiv) != VOIDmode
6256 && mode != GET_MODE (oldequiv))
6257 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6259 /* Switch to the right place to emit the reload insns. */
6260 switch (rl->when_needed)
6263 where = &other_input_reload_insns;
6265 case RELOAD_FOR_INPUT:
6266 where = &input_reload_insns[rl->opnum];
6268 case RELOAD_FOR_INPUT_ADDRESS:
6269 where = &input_address_reload_insns[rl->opnum];
6271 case RELOAD_FOR_INPADDR_ADDRESS:
6272 where = &inpaddr_address_reload_insns[rl->opnum];
6274 case RELOAD_FOR_OUTPUT_ADDRESS:
6275 where = &output_address_reload_insns[rl->opnum];
6277 case RELOAD_FOR_OUTADDR_ADDRESS:
6278 where = &outaddr_address_reload_insns[rl->opnum];
6280 case RELOAD_FOR_OPERAND_ADDRESS:
6281 where = &operand_reload_insns;
6283 case RELOAD_FOR_OPADDR_ADDR:
6284 where = &other_operand_reload_insns;
6286 case RELOAD_FOR_OTHER_ADDRESS:
6287 where = &other_input_address_reload_insns;
6293 push_to_sequence (*where);
6295 /* Auto-increment addresses must be reloaded in a special way. */
6296 if (rl->out && ! rl->out_reg)
6298 /* We are not going to bother supporting the case where a
6299 incremented register can't be copied directly from
6300 OLDEQUIV since this seems highly unlikely. */
6301 gcc_assert (rl->secondary_in_reload < 0);
6303 if (reload_inherited[j])
6304 oldequiv = reloadreg;
6306 old = XEXP (rl->in_reg, 0);
6308 if (optimize && REG_P (oldequiv)
6309 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6310 && spill_reg_store[REGNO (oldequiv)]
6312 && (dead_or_set_p (insn,
6313 spill_reg_stored_to[REGNO (oldequiv)])
6314 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6316 delete_output_reload (insn, j, REGNO (oldequiv));
6318 /* Prevent normal processing of this reload. */
6320 /* Output a special code sequence for this case. */
6321 new_spill_reg_store[REGNO (reloadreg)]
6322 = inc_for_reload (reloadreg, oldequiv, rl->out,
6326 /* If we are reloading a pseudo-register that was set by the previous
6327 insn, see if we can get rid of that pseudo-register entirely
6328 by redirecting the previous insn into our reload register. */
6330 else if (optimize && REG_P (old)
6331 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6332 && dead_or_set_p (insn, old)
6333 /* This is unsafe if some other reload
6334 uses the same reg first. */
6335 && ! conflicts_with_override (reloadreg)
6336 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6337 rl->when_needed, old, rl->out, j, 0))
6339 rtx temp = PREV_INSN (insn);
6340 while (temp && NOTE_P (temp))
6341 temp = PREV_INSN (temp);
6343 && NONJUMP_INSN_P (temp)
6344 && GET_CODE (PATTERN (temp)) == SET
6345 && SET_DEST (PATTERN (temp)) == old
6346 /* Make sure we can access insn_operand_constraint. */
6347 && asm_noperands (PATTERN (temp)) < 0
6348 /* This is unsafe if operand occurs more than once in current
6349 insn. Perhaps some occurrences aren't reloaded. */
6350 && count_occurrences (PATTERN (insn), old, 0) == 1)
6352 rtx old = SET_DEST (PATTERN (temp));
6353 /* Store into the reload register instead of the pseudo. */
6354 SET_DEST (PATTERN (temp)) = reloadreg;
6356 /* Verify that resulting insn is valid. */
6357 extract_insn (temp);
6358 if (constrain_operands (1))
6360 /* If the previous insn is an output reload, the source is
6361 a reload register, and its spill_reg_store entry will
6362 contain the previous destination. This is now
6364 if (REG_P (SET_SRC (PATTERN (temp)))
6365 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6367 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6368 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6371 /* If these are the only uses of the pseudo reg,
6372 pretend for GDB it lives in the reload reg we used. */
6373 if (REG_N_DEATHS (REGNO (old)) == 1
6374 && REG_N_SETS (REGNO (old)) == 1)
6376 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6377 alter_reg (REGNO (old), -1);
6383 SET_DEST (PATTERN (temp)) = old;
6388 /* We can't do that, so output an insn to load RELOADREG. */
6390 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6391 /* If we have a secondary reload, pick up the secondary register
6392 and icode, if any. If OLDEQUIV and OLD are different or
6393 if this is an in-out reload, recompute whether or not we
6394 still need a secondary register and what the icode should
6395 be. If we still need a secondary register and the class or
6396 icode is different, go back to reloading from OLD if using
6397 OLDEQUIV means that we got the wrong type of register. We
6398 cannot have different class or icode due to an in-out reload
6399 because we don't make such reloads when both the input and
6400 output need secondary reload registers. */
6402 if (! special && rl->secondary_in_reload >= 0)
6404 rtx second_reload_reg = 0;
6405 int secondary_reload = rl->secondary_in_reload;
6406 rtx real_oldequiv = oldequiv;
6409 enum insn_code icode;
6411 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6412 and similarly for OLD.
6413 See comments in get_secondary_reload in reload.c. */
6414 /* If it is a pseudo that cannot be replaced with its
6415 equivalent MEM, we must fall back to reload_in, which
6416 will have all the necessary substitutions registered.
6417 Likewise for a pseudo that can't be replaced with its
6418 equivalent constant.
6420 Take extra care for subregs of such pseudos. Note that
6421 we cannot use reg_equiv_mem in this case because it is
6422 not in the right mode. */
6425 if (GET_CODE (tmp) == SUBREG)
6426 tmp = SUBREG_REG (tmp);
6428 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6429 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6430 || reg_equiv_constant[REGNO (tmp)] != 0))
6432 if (! reg_equiv_mem[REGNO (tmp)]
6433 || num_not_at_initial_offset
6434 || GET_CODE (oldequiv) == SUBREG)
6435 real_oldequiv = rl->in;
6437 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6441 if (GET_CODE (tmp) == SUBREG)
6442 tmp = SUBREG_REG (tmp);
6444 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6445 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6446 || reg_equiv_constant[REGNO (tmp)] != 0))
6448 if (! reg_equiv_mem[REGNO (tmp)]
6449 || num_not_at_initial_offset
6450 || GET_CODE (old) == SUBREG)
6453 real_old = reg_equiv_mem[REGNO (tmp)];
6456 second_reload_reg = rld[secondary_reload].reg_rtx;
6457 icode = rl->secondary_in_icode;
6459 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6460 || (rl->in != 0 && rl->out != 0))
6462 enum reg_class new_class
6463 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6464 mode, real_oldequiv);
6466 if (new_class == NO_REGS)
6467 second_reload_reg = 0;
6470 enum insn_code new_icode;
6471 enum machine_mode new_mode;
6473 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6474 REGNO (second_reload_reg)))
6475 oldequiv = old, real_oldequiv = real_old;
6478 new_icode = reload_in_optab[(int) mode];
6479 if (new_icode != CODE_FOR_nothing
6480 && ((insn_data[(int) new_icode].operand[0].predicate
6481 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6483 || (insn_data[(int) new_icode].operand[1].predicate
6484 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6485 (real_oldequiv, mode)))))
6486 new_icode = CODE_FOR_nothing;
6488 if (new_icode == CODE_FOR_nothing)
6491 new_mode = insn_data[(int) new_icode].operand[2].mode;
6493 if (GET_MODE (second_reload_reg) != new_mode)
6495 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6497 oldequiv = old, real_oldequiv = real_old;
6500 = reload_adjust_reg_for_mode (second_reload_reg,
6507 /* If we still need a secondary reload register, check
6508 to see if it is being used as a scratch or intermediate
6509 register and generate code appropriately. If we need
6510 a scratch register, use REAL_OLDEQUIV since the form of
6511 the insn may depend on the actual address if it is
6514 if (second_reload_reg)
6516 if (icode != CODE_FOR_nothing)
6518 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6519 second_reload_reg));
6524 /* See if we need a scratch register to load the
6525 intermediate register (a tertiary reload). */
6526 enum insn_code tertiary_icode
6527 = rld[secondary_reload].secondary_in_icode;
6529 if (tertiary_icode != CODE_FOR_nothing)
6531 rtx third_reload_reg
6532 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6534 emit_insn ((GEN_FCN (tertiary_icode)
6535 (second_reload_reg, real_oldequiv,
6536 third_reload_reg)));
6539 gen_reload (second_reload_reg, real_oldequiv,
6543 oldequiv = second_reload_reg;
6549 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6551 rtx real_oldequiv = oldequiv;
6553 if ((REG_P (oldequiv)
6554 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6555 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6556 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6557 || (GET_CODE (oldequiv) == SUBREG
6558 && REG_P (SUBREG_REG (oldequiv))
6559 && (REGNO (SUBREG_REG (oldequiv))
6560 >= FIRST_PSEUDO_REGISTER)
6561 && ((reg_equiv_memory_loc
6562 [REGNO (SUBREG_REG (oldequiv))] != 0)
6563 || (reg_equiv_constant
6564 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6565 || (CONSTANT_P (oldequiv)
6566 && (PREFERRED_RELOAD_CLASS (oldequiv,
6567 REGNO_REG_CLASS (REGNO (reloadreg)))
6569 real_oldequiv = rl->in;
6570 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6574 if (flag_non_call_exceptions)
6575 copy_eh_notes (insn, get_insns ());
6577 /* End this sequence. */
6578 *where = get_insns ();
6581 /* Update reload_override_in so that delete_address_reloads_1
6582 can see the actual register usage. */
6584 reload_override_in[j] = oldequiv;
6587 /* Generate insns to for the output reload RL, which is for the insn described
6588 by CHAIN and has the number J. */
6590 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6593 rtx reloadreg = rl->reg_rtx;
6594 rtx insn = chain->insn;
6597 enum machine_mode mode = GET_MODE (old);
6600 if (rl->when_needed == RELOAD_OTHER)
6603 push_to_sequence (output_reload_insns[rl->opnum]);
6605 /* Determine the mode to reload in.
6606 See comments above (for input reloading). */
6608 if (mode == VOIDmode)
6610 /* VOIDmode should never happen for an output. */
6611 if (asm_noperands (PATTERN (insn)) < 0)
6612 /* It's the compiler's fault. */
6613 fatal_insn ("VOIDmode on an output", insn);
6614 error_for_asm (insn, "output operand is constant in %<asm%>");
6615 /* Prevent crash--use something we know is valid. */
6617 old = gen_rtx_REG (mode, REGNO (reloadreg));
6620 if (GET_MODE (reloadreg) != mode)
6621 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6623 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6625 /* If we need two reload regs, set RELOADREG to the intermediate
6626 one, since it will be stored into OLD. We might need a secondary
6627 register only for an input reload, so check again here. */
6629 if (rl->secondary_out_reload >= 0)
6633 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
6634 && reg_equiv_mem[REGNO (old)] != 0)
6635 real_old = reg_equiv_mem[REGNO (old)];
6637 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6641 rtx second_reloadreg = reloadreg;
6642 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6644 /* See if RELOADREG is to be used as a scratch register
6645 or as an intermediate register. */
6646 if (rl->secondary_out_icode != CODE_FOR_nothing)
6648 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6649 (real_old, second_reloadreg, reloadreg)));
6654 /* See if we need both a scratch and intermediate reload
6657 int secondary_reload = rl->secondary_out_reload;
6658 enum insn_code tertiary_icode
6659 = rld[secondary_reload].secondary_out_icode;
6661 if (GET_MODE (reloadreg) != mode)
6662 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6664 if (tertiary_icode != CODE_FOR_nothing)
6667 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6670 /* Copy primary reload reg to secondary reload reg.
6671 (Note that these have been swapped above, then
6672 secondary reload reg to OLD using our insn.) */
6674 /* If REAL_OLD is a paradoxical SUBREG, remove it
6675 and try to put the opposite SUBREG on
6677 if (GET_CODE (real_old) == SUBREG
6678 && (GET_MODE_SIZE (GET_MODE (real_old))
6679 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6680 && 0 != (tem = gen_lowpart_common
6681 (GET_MODE (SUBREG_REG (real_old)),
6683 real_old = SUBREG_REG (real_old), reloadreg = tem;
6685 gen_reload (reloadreg, second_reloadreg,
6686 rl->opnum, rl->when_needed);
6687 emit_insn ((GEN_FCN (tertiary_icode)
6688 (real_old, reloadreg, third_reloadreg)));
6693 /* Copy between the reload regs here and then to
6696 gen_reload (reloadreg, second_reloadreg,
6697 rl->opnum, rl->when_needed);
6703 /* Output the last reload insn. */
6708 /* Don't output the last reload if OLD is not the dest of
6709 INSN and is in the src and is clobbered by INSN. */
6710 if (! flag_expensive_optimizations
6712 || !(set = single_set (insn))
6713 || rtx_equal_p (old, SET_DEST (set))
6714 || !reg_mentioned_p (old, SET_SRC (set))
6715 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
6716 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
6717 gen_reload (old, reloadreg, rl->opnum,
6721 /* Look at all insns we emitted, just to be safe. */
6722 for (p = get_insns (); p; p = NEXT_INSN (p))
6725 rtx pat = PATTERN (p);
6727 /* If this output reload doesn't come from a spill reg,
6728 clear any memory of reloaded copies of the pseudo reg.
6729 If this output reload comes from a spill reg,
6730 reg_has_output_reload will make this do nothing. */
6731 note_stores (pat, forget_old_reloads_1, NULL);
6733 if (reg_mentioned_p (rl->reg_rtx, pat))
6735 rtx set = single_set (insn);
6736 if (reload_spill_index[j] < 0
6738 && SET_SRC (set) == rl->reg_rtx)
6740 int src = REGNO (SET_SRC (set));
6742 reload_spill_index[j] = src;
6743 SET_HARD_REG_BIT (reg_is_output_reload, src);
6744 if (find_regno_note (insn, REG_DEAD, src))
6745 SET_HARD_REG_BIT (reg_reloaded_died, src);
6747 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6749 int s = rl->secondary_out_reload;
6750 set = single_set (p);
6751 /* If this reload copies only to the secondary reload
6752 register, the secondary reload does the actual
6754 if (s >= 0 && set == NULL_RTX)
6755 /* We can't tell what function the secondary reload
6756 has and where the actual store to the pseudo is
6757 made; leave new_spill_reg_store alone. */
6760 && SET_SRC (set) == rl->reg_rtx
6761 && SET_DEST (set) == rld[s].reg_rtx)
6763 /* Usually the next instruction will be the
6764 secondary reload insn; if we can confirm
6765 that it is, setting new_spill_reg_store to
6766 that insn will allow an extra optimization. */
6767 rtx s_reg = rld[s].reg_rtx;
6768 rtx next = NEXT_INSN (p);
6769 rld[s].out = rl->out;
6770 rld[s].out_reg = rl->out_reg;
6771 set = single_set (next);
6772 if (set && SET_SRC (set) == s_reg
6773 && ! new_spill_reg_store[REGNO (s_reg)])
6775 SET_HARD_REG_BIT (reg_is_output_reload,
6777 new_spill_reg_store[REGNO (s_reg)] = next;
6781 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6786 if (rl->when_needed == RELOAD_OTHER)
6788 emit_insn (other_output_reload_insns[rl->opnum]);
6789 other_output_reload_insns[rl->opnum] = get_insns ();
6792 output_reload_insns[rl->opnum] = get_insns ();
6794 if (flag_non_call_exceptions)
6795 copy_eh_notes (insn, get_insns ());
6800 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6801 and has the number J. */
6803 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
6805 rtx insn = chain->insn;
6806 rtx old = (rl->in && MEM_P (rl->in)
6807 ? rl->in_reg : rl->in);
6810 /* AUTO_INC reloads need to be handled even if inherited. We got an
6811 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6812 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6813 && ! rtx_equal_p (rl->reg_rtx, old)
6814 && rl->reg_rtx != 0)
6815 emit_input_reload_insns (chain, rld + j, old, j);
6817 /* When inheriting a wider reload, we have a MEM in rl->in,
6818 e.g. inheriting a SImode output reload for
6819 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6820 if (optimize && reload_inherited[j] && rl->in
6822 && MEM_P (rl->in_reg)
6823 && reload_spill_index[j] >= 0
6824 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6825 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6827 /* If we are reloading a register that was recently stored in with an
6828 output-reload, see if we can prove there was
6829 actually no need to store the old value in it. */
6832 /* Only attempt this for input reloads; for RELOAD_OTHER we miss
6833 that there may be multiple uses of the previous output reload.
6834 Restricting to RELOAD_FOR_INPUT is mostly paranoia. */
6835 && rl->when_needed == RELOAD_FOR_INPUT
6836 && (reload_inherited[j] || reload_override_in[j])
6838 && REG_P (rl->reg_rtx)
6839 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6841 /* There doesn't seem to be any reason to restrict this to pseudos
6842 and doing so loses in the case where we are copying from a
6843 register of the wrong class. */
6844 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6845 >= FIRST_PSEUDO_REGISTER)
6847 /* The insn might have already some references to stackslots
6848 replaced by MEMs, while reload_out_reg still names the
6850 && (dead_or_set_p (insn,
6851 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6852 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6854 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6857 /* Do output reloading for reload RL, which is for the insn described by
6858 CHAIN and has the number J.
6859 ??? At some point we need to support handling output reloads of
6860 JUMP_INSNs or insns that set cc0. */
6862 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
6865 rtx insn = chain->insn;
6866 /* If this is an output reload that stores something that is
6867 not loaded in this same reload, see if we can eliminate a previous
6869 rtx pseudo = rl->out_reg;
6874 && ! rtx_equal_p (rl->in_reg, pseudo)
6875 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6876 && reg_last_reload_reg[REGNO (pseudo)])
6878 int pseudo_no = REGNO (pseudo);
6879 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6881 /* We don't need to test full validity of last_regno for
6882 inherit here; we only want to know if the store actually
6883 matches the pseudo. */
6884 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6885 && reg_reloaded_contents[last_regno] == pseudo_no
6886 && spill_reg_store[last_regno]
6887 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6888 delete_output_reload (insn, j, last_regno);
6893 || rl->reg_rtx == old
6894 || rl->reg_rtx == 0)
6897 /* An output operand that dies right away does need a reload,
6898 but need not be copied from it. Show the new location in the
6900 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
6901 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6903 XEXP (note, 0) = rl->reg_rtx;
6906 /* Likewise for a SUBREG of an operand that dies. */
6907 else if (GET_CODE (old) == SUBREG
6908 && REG_P (SUBREG_REG (old))
6909 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6912 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6916 else if (GET_CODE (old) == SCRATCH)
6917 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6918 but we don't want to make an output reload. */
6921 /* If is a JUMP_INSN, we can't support output reloads yet. */
6922 gcc_assert (!JUMP_P (insn));
6924 emit_output_reload_insns (chain, rld + j, j);
6927 /* Reload number R reloads from or to a group of hard registers starting at
6928 register REGNO. Return true if it can be treated for inheritance purposes
6929 like a group of reloads, each one reloading a single hard register.
6930 The caller has already checked that the spill register and REGNO use
6931 the same number of registers to store the reload value. */
6934 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
6936 #ifdef CANNOT_CHANGE_MODE_CLASS
6937 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
6938 GET_MODE (rld[r].reg_rtx),
6939 reg_raw_mode[reload_spill_index[r]])
6940 && !REG_CANNOT_CHANGE_MODE_P (regno,
6941 GET_MODE (rld[r].reg_rtx),
6942 reg_raw_mode[regno]));
6948 /* Output insns to reload values in and out of the chosen reload regs. */
6951 emit_reload_insns (struct insn_chain *chain)
6953 rtx insn = chain->insn;
6957 CLEAR_HARD_REG_SET (reg_reloaded_died);
6959 for (j = 0; j < reload_n_operands; j++)
6960 input_reload_insns[j] = input_address_reload_insns[j]
6961 = inpaddr_address_reload_insns[j]
6962 = output_reload_insns[j] = output_address_reload_insns[j]
6963 = outaddr_address_reload_insns[j]
6964 = other_output_reload_insns[j] = 0;
6965 other_input_address_reload_insns = 0;
6966 other_input_reload_insns = 0;
6967 operand_reload_insns = 0;
6968 other_operand_reload_insns = 0;
6970 /* Dump reloads into the dump file. */
6973 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6974 debug_reload_to_stream (dump_file);
6977 /* Now output the instructions to copy the data into and out of the
6978 reload registers. Do these in the order that the reloads were reported,
6979 since reloads of base and index registers precede reloads of operands
6980 and the operands may need the base and index registers reloaded. */
6982 for (j = 0; j < n_reloads; j++)
6985 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6986 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6988 do_input_reload (chain, rld + j, j);
6989 do_output_reload (chain, rld + j, j);
6992 /* Now write all the insns we made for reloads in the order expected by
6993 the allocation functions. Prior to the insn being reloaded, we write
6994 the following reloads:
6996 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6998 RELOAD_OTHER reloads.
7000 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7001 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7002 RELOAD_FOR_INPUT reload for the operand.
7004 RELOAD_FOR_OPADDR_ADDRS reloads.
7006 RELOAD_FOR_OPERAND_ADDRESS reloads.
7008 After the insn being reloaded, we write the following:
7010 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7011 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7012 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7013 reloads for the operand. The RELOAD_OTHER output reloads are
7014 output in descending order by reload number. */
7016 emit_insn_before (other_input_address_reload_insns, insn);
7017 emit_insn_before (other_input_reload_insns, insn);
7019 for (j = 0; j < reload_n_operands; j++)
7021 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7022 emit_insn_before (input_address_reload_insns[j], insn);
7023 emit_insn_before (input_reload_insns[j], insn);
7026 emit_insn_before (other_operand_reload_insns, insn);
7027 emit_insn_before (operand_reload_insns, insn);
7029 for (j = 0; j < reload_n_operands; j++)
7031 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7032 x = emit_insn_after (output_address_reload_insns[j], x);
7033 x = emit_insn_after (output_reload_insns[j], x);
7034 emit_insn_after (other_output_reload_insns[j], x);
7037 /* For all the spill regs newly reloaded in this instruction,
7038 record what they were reloaded from, so subsequent instructions
7039 can inherit the reloads.
7041 Update spill_reg_store for the reloads of this insn.
7042 Copy the elements that were updated in the loop above. */
7044 for (j = 0; j < n_reloads; j++)
7046 int r = reload_order[j];
7047 int i = reload_spill_index[r];
7049 /* If this is a non-inherited input reload from a pseudo, we must
7050 clear any memory of a previous store to the same pseudo. Only do
7051 something if there will not be an output reload for the pseudo
7053 if (rld[r].in_reg != 0
7054 && ! (reload_inherited[r] || reload_override_in[r]))
7056 rtx reg = rld[r].in_reg;
7058 if (GET_CODE (reg) == SUBREG)
7059 reg = SUBREG_REG (reg);
7062 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7063 && ! reg_has_output_reload[REGNO (reg)])
7065 int nregno = REGNO (reg);
7067 if (reg_last_reload_reg[nregno])
7069 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7071 if (reg_reloaded_contents[last_regno] == nregno)
7072 spill_reg_store[last_regno] = 0;
7077 /* I is nonneg if this reload used a register.
7078 If rld[r].reg_rtx is 0, this is an optional reload
7079 that we opted to ignore. */
7081 if (i >= 0 && rld[r].reg_rtx != 0)
7083 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7085 int part_reaches_end = 0;
7086 int all_reaches_end = 1;
7088 /* For a multi register reload, we need to check if all or part
7089 of the value lives to the end. */
7090 for (k = 0; k < nr; k++)
7092 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7093 rld[r].when_needed))
7094 part_reaches_end = 1;
7096 all_reaches_end = 0;
7099 /* Ignore reloads that don't reach the end of the insn in
7101 if (all_reaches_end)
7103 /* First, clear out memory of what used to be in this spill reg.
7104 If consecutive registers are used, clear them all. */
7106 for (k = 0; k < nr; k++)
7108 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7109 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7112 /* Maybe the spill reg contains a copy of reload_out. */
7114 && (REG_P (rld[r].out)
7118 || REG_P (rld[r].out_reg)))
7120 rtx out = (REG_P (rld[r].out)
7124 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7125 int nregno = REGNO (out);
7126 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7127 : hard_regno_nregs[nregno]
7128 [GET_MODE (rld[r].reg_rtx)]);
7131 spill_reg_store[i] = new_spill_reg_store[i];
7132 spill_reg_stored_to[i] = out;
7133 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7135 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7137 && inherit_piecemeal_p (r, nregno));
7139 /* If NREGNO is a hard register, it may occupy more than
7140 one register. If it does, say what is in the
7141 rest of the registers assuming that both registers
7142 agree on how many words the object takes. If not,
7143 invalidate the subsequent registers. */
7145 if (nregno < FIRST_PSEUDO_REGISTER)
7146 for (k = 1; k < nnr; k++)
7147 reg_last_reload_reg[nregno + k]
7149 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7152 /* Now do the inverse operation. */
7153 for (k = 0; k < nr; k++)
7155 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7156 reg_reloaded_contents[i + k]
7157 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7160 reg_reloaded_insn[i + k] = insn;
7161 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7162 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7163 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7167 /* Maybe the spill reg contains a copy of reload_in. Only do
7168 something if there will not be an output reload for
7169 the register being reloaded. */
7170 else if (rld[r].out_reg == 0
7172 && ((REG_P (rld[r].in)
7173 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7174 && ! reg_has_output_reload[REGNO (rld[r].in)])
7175 || (REG_P (rld[r].in_reg)
7176 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7177 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7184 if (REG_P (rld[r].in)
7185 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7187 else if (REG_P (rld[r].in_reg))
7190 in = XEXP (rld[r].in_reg, 0);
7191 nregno = REGNO (in);
7193 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7194 : hard_regno_nregs[nregno]
7195 [GET_MODE (rld[r].reg_rtx)]);
7197 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7199 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7201 && inherit_piecemeal_p (r, nregno));
7203 if (nregno < FIRST_PSEUDO_REGISTER)
7204 for (k = 1; k < nnr; k++)
7205 reg_last_reload_reg[nregno + k]
7207 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7210 /* Unless we inherited this reload, show we haven't
7211 recently done a store.
7212 Previous stores of inherited auto_inc expressions
7213 also have to be discarded. */
7214 if (! reload_inherited[r]
7215 || (rld[r].out && ! rld[r].out_reg))
7216 spill_reg_store[i] = 0;
7218 for (k = 0; k < nr; k++)
7220 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7221 reg_reloaded_contents[i + k]
7222 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7225 reg_reloaded_insn[i + k] = insn;
7226 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7227 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7228 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7233 /* However, if part of the reload reaches the end, then we must
7234 invalidate the old info for the part that survives to the end. */
7235 else if (part_reaches_end)
7237 for (k = 0; k < nr; k++)
7238 if (reload_reg_reaches_end_p (i + k,
7240 rld[r].when_needed))
7241 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7245 /* The following if-statement was #if 0'd in 1.34 (or before...).
7246 It's reenabled in 1.35 because supposedly nothing else
7247 deals with this problem. */
7249 /* If a register gets output-reloaded from a non-spill register,
7250 that invalidates any previous reloaded copy of it.
7251 But forget_old_reloads_1 won't get to see it, because
7252 it thinks only about the original insn. So invalidate it here. */
7253 if (i < 0 && rld[r].out != 0
7254 && (REG_P (rld[r].out)
7255 || (MEM_P (rld[r].out)
7256 && REG_P (rld[r].out_reg))))
7258 rtx out = (REG_P (rld[r].out)
7259 ? rld[r].out : rld[r].out_reg);
7260 int nregno = REGNO (out);
7261 if (nregno >= FIRST_PSEUDO_REGISTER)
7263 rtx src_reg, store_insn = NULL_RTX;
7265 reg_last_reload_reg[nregno] = 0;
7267 /* If we can find a hard register that is stored, record
7268 the storing insn so that we may delete this insn with
7269 delete_output_reload. */
7270 src_reg = rld[r].reg_rtx;
7272 /* If this is an optional reload, try to find the source reg
7273 from an input reload. */
7276 rtx set = single_set (insn);
7277 if (set && SET_DEST (set) == rld[r].out)
7281 src_reg = SET_SRC (set);
7283 for (k = 0; k < n_reloads; k++)
7285 if (rld[k].in == src_reg)
7287 src_reg = rld[k].reg_rtx;
7294 store_insn = new_spill_reg_store[REGNO (src_reg)];
7295 if (src_reg && REG_P (src_reg)
7296 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7298 int src_regno = REGNO (src_reg);
7299 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7300 /* The place where to find a death note varies with
7301 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7302 necessarily checked exactly in the code that moves
7303 notes, so just check both locations. */
7304 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7305 if (! note && store_insn)
7306 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7309 spill_reg_store[src_regno + nr] = store_insn;
7310 spill_reg_stored_to[src_regno + nr] = out;
7311 reg_reloaded_contents[src_regno + nr] = nregno;
7312 reg_reloaded_insn[src_regno + nr] = store_insn;
7313 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7314 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7315 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7316 GET_MODE (src_reg)))
7317 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7319 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7321 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7323 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7325 reg_last_reload_reg[nregno] = src_reg;
7326 /* We have to set reg_has_output_reload here, or else
7327 forget_old_reloads_1 will clear reg_last_reload_reg
7329 reg_has_output_reload[nregno] = 1;
7334 int num_regs = hard_regno_nregs[nregno][GET_MODE (rld[r].out)];
7336 while (num_regs-- > 0)
7337 reg_last_reload_reg[nregno + num_regs] = 0;
7341 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7344 /* Emit code to perform a reload from IN (which may be a reload register) to
7345 OUT (which may also be a reload register). IN or OUT is from operand
7346 OPNUM with reload type TYPE.
7348 Returns first insn emitted. */
7351 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7353 rtx last = get_last_insn ();
7356 /* If IN is a paradoxical SUBREG, remove it and try to put the
7357 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7358 if (GET_CODE (in) == SUBREG
7359 && (GET_MODE_SIZE (GET_MODE (in))
7360 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7361 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7362 in = SUBREG_REG (in), out = tem;
7363 else if (GET_CODE (out) == SUBREG
7364 && (GET_MODE_SIZE (GET_MODE (out))
7365 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7366 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7367 out = SUBREG_REG (out), in = tem;
7369 /* How to do this reload can get quite tricky. Normally, we are being
7370 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7371 register that didn't get a hard register. In that case we can just
7372 call emit_move_insn.
7374 We can also be asked to reload a PLUS that adds a register or a MEM to
7375 another register, constant or MEM. This can occur during frame pointer
7376 elimination and while reloading addresses. This case is handled by
7377 trying to emit a single insn to perform the add. If it is not valid,
7378 we use a two insn sequence.
7380 Finally, we could be called to handle an 'o' constraint by putting
7381 an address into a register. In that case, we first try to do this
7382 with a named pattern of "reload_load_address". If no such pattern
7383 exists, we just emit a SET insn and hope for the best (it will normally
7384 be valid on machines that use 'o').
7386 This entire process is made complex because reload will never
7387 process the insns we generate here and so we must ensure that
7388 they will fit their constraints and also by the fact that parts of
7389 IN might be being reloaded separately and replaced with spill registers.
7390 Because of this, we are, in some sense, just guessing the right approach
7391 here. The one listed above seems to work.
7393 ??? At some point, this whole thing needs to be rethought. */
7395 if (GET_CODE (in) == PLUS
7396 && (REG_P (XEXP (in, 0))
7397 || GET_CODE (XEXP (in, 0)) == SUBREG
7398 || MEM_P (XEXP (in, 0)))
7399 && (REG_P (XEXP (in, 1))
7400 || GET_CODE (XEXP (in, 1)) == SUBREG
7401 || CONSTANT_P (XEXP (in, 1))
7402 || MEM_P (XEXP (in, 1))))
7404 /* We need to compute the sum of a register or a MEM and another
7405 register, constant, or MEM, and put it into the reload
7406 register. The best possible way of doing this is if the machine
7407 has a three-operand ADD insn that accepts the required operands.
7409 The simplest approach is to try to generate such an insn and see if it
7410 is recognized and matches its constraints. If so, it can be used.
7412 It might be better not to actually emit the insn unless it is valid,
7413 but we need to pass the insn as an operand to `recog' and
7414 `extract_insn' and it is simpler to emit and then delete the insn if
7415 not valid than to dummy things up. */
7417 rtx op0, op1, tem, insn;
7420 op0 = find_replacement (&XEXP (in, 0));
7421 op1 = find_replacement (&XEXP (in, 1));
7423 /* Since constraint checking is strict, commutativity won't be
7424 checked, so we need to do that here to avoid spurious failure
7425 if the add instruction is two-address and the second operand
7426 of the add is the same as the reload reg, which is frequently
7427 the case. If the insn would be A = B + A, rearrange it so
7428 it will be A = A + B as constrain_operands expects. */
7430 if (REG_P (XEXP (in, 1))
7431 && REGNO (out) == REGNO (XEXP (in, 1)))
7432 tem = op0, op0 = op1, op1 = tem;
7434 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7435 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7437 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7438 code = recog_memoized (insn);
7442 extract_insn (insn);
7443 /* We want constrain operands to treat this insn strictly in
7444 its validity determination, i.e., the way it would after reload
7446 if (constrain_operands (1))
7450 delete_insns_since (last);
7452 /* If that failed, we must use a conservative two-insn sequence.
7454 Use a move to copy one operand into the reload register. Prefer
7455 to reload a constant, MEM or pseudo since the move patterns can
7456 handle an arbitrary operand. If OP1 is not a constant, MEM or
7457 pseudo and OP1 is not a valid operand for an add instruction, then
7460 After reloading one of the operands into the reload register, add
7461 the reload register to the output register.
7463 If there is another way to do this for a specific machine, a
7464 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7467 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7469 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7471 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7472 || (code != CODE_FOR_nothing
7473 && ! ((*insn_data[code].operand[2].predicate)
7474 (op1, insn_data[code].operand[2].mode))))
7475 tem = op0, op0 = op1, op1 = tem;
7477 gen_reload (out, op0, opnum, type);
7479 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7480 This fixes a problem on the 32K where the stack pointer cannot
7481 be used as an operand of an add insn. */
7483 if (rtx_equal_p (op0, op1))
7486 insn = emit_insn (gen_add2_insn (out, op1));
7488 /* If that failed, copy the address register to the reload register.
7489 Then add the constant to the reload register. */
7491 code = recog_memoized (insn);
7495 extract_insn (insn);
7496 /* We want constrain operands to treat this insn strictly in
7497 its validity determination, i.e., the way it would after reload
7499 if (constrain_operands (1))
7501 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7503 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7508 delete_insns_since (last);
7510 gen_reload (out, op1, opnum, type);
7511 insn = emit_insn (gen_add2_insn (out, op0));
7512 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7515 #ifdef SECONDARY_MEMORY_NEEDED
7516 /* If we need a memory location to do the move, do it that way. */
7517 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7518 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7519 && (REG_P (out) || GET_CODE (out) == SUBREG)
7520 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7521 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7522 REGNO_REG_CLASS (reg_or_subregno (out)),
7525 /* Get the memory to use and rewrite both registers to its mode. */
7526 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7528 if (GET_MODE (loc) != GET_MODE (out))
7529 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7531 if (GET_MODE (loc) != GET_MODE (in))
7532 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7534 gen_reload (loc, in, opnum, type);
7535 gen_reload (out, loc, opnum, type);
7539 /* If IN is a simple operand, use gen_move_insn. */
7540 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
7541 emit_insn (gen_move_insn (out, in));
7543 #ifdef HAVE_reload_load_address
7544 else if (HAVE_reload_load_address)
7545 emit_insn (gen_reload_load_address (out, in));
7548 /* Otherwise, just write (set OUT IN) and hope for the best. */
7550 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7552 /* Return the first insn emitted.
7553 We can not just return get_last_insn, because there may have
7554 been multiple instructions emitted. Also note that gen_move_insn may
7555 emit more than one insn itself, so we can not assume that there is one
7556 insn emitted per emit_insn_before call. */
7558 return last ? NEXT_INSN (last) : get_insns ();
7561 /* Delete a previously made output-reload whose result we now believe
7562 is not needed. First we double-check.
7564 INSN is the insn now being processed.
7565 LAST_RELOAD_REG is the hard register number for which we want to delete
7566 the last output reload.
7567 J is the reload-number that originally used REG. The caller has made
7568 certain that reload J doesn't use REG any longer for input. */
7571 delete_output_reload (rtx insn, int j, int last_reload_reg)
7573 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7574 rtx reg = spill_reg_stored_to[last_reload_reg];
7577 int n_inherited = 0;
7581 /* It is possible that this reload has been only used to set another reload
7582 we eliminated earlier and thus deleted this instruction too. */
7583 if (INSN_DELETED_P (output_reload_insn))
7586 /* Get the raw pseudo-register referred to. */
7588 while (GET_CODE (reg) == SUBREG)
7589 reg = SUBREG_REG (reg);
7590 substed = reg_equiv_memory_loc[REGNO (reg)];
7592 /* This is unsafe if the operand occurs more often in the current
7593 insn than it is inherited. */
7594 for (k = n_reloads - 1; k >= 0; k--)
7596 rtx reg2 = rld[k].in;
7599 if (MEM_P (reg2) || reload_override_in[k])
7600 reg2 = rld[k].in_reg;
7602 if (rld[k].out && ! rld[k].out_reg)
7603 reg2 = XEXP (rld[k].in_reg, 0);
7605 while (GET_CODE (reg2) == SUBREG)
7606 reg2 = SUBREG_REG (reg2);
7607 if (rtx_equal_p (reg2, reg))
7609 if (reload_inherited[k] || reload_override_in[k] || k == j)
7612 reg2 = rld[k].out_reg;
7615 while (GET_CODE (reg2) == SUBREG)
7616 reg2 = XEXP (reg2, 0);
7617 if (rtx_equal_p (reg2, reg))
7624 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7626 n_occurrences += count_occurrences (PATTERN (insn),
7627 eliminate_regs (substed, 0,
7629 if (n_occurrences > n_inherited)
7632 /* If the pseudo-reg we are reloading is no longer referenced
7633 anywhere between the store into it and here,
7634 and we're within the same basic block, then the value can only
7635 pass through the reload reg and end up here.
7636 Otherwise, give up--return. */
7637 for (i1 = NEXT_INSN (output_reload_insn);
7638 i1 != insn; i1 = NEXT_INSN (i1))
7640 if (NOTE_INSN_BASIC_BLOCK_P (i1))
7642 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
7643 && reg_mentioned_p (reg, PATTERN (i1)))
7645 /* If this is USE in front of INSN, we only have to check that
7646 there are no more references than accounted for by inheritance. */
7647 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
7649 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7650 i1 = NEXT_INSN (i1);
7652 if (n_occurrences <= n_inherited && i1 == insn)
7658 /* We will be deleting the insn. Remove the spill reg information. */
7659 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
7661 spill_reg_store[last_reload_reg + k] = 0;
7662 spill_reg_stored_to[last_reload_reg + k] = 0;
7665 /* The caller has already checked that REG dies or is set in INSN.
7666 It has also checked that we are optimizing, and thus some
7667 inaccuracies in the debugging information are acceptable.
7668 So we could just delete output_reload_insn. But in some cases
7669 we can improve the debugging information without sacrificing
7670 optimization - maybe even improving the code: See if the pseudo
7671 reg has been completely replaced with reload regs. If so, delete
7672 the store insn and forget we had a stack slot for the pseudo. */
7673 if (rld[j].out != rld[j].in
7674 && REG_N_DEATHS (REGNO (reg)) == 1
7675 && REG_N_SETS (REGNO (reg)) == 1
7676 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7677 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7681 /* We know that it was used only between here and the beginning of
7682 the current basic block. (We also know that the last use before
7683 INSN was the output reload we are thinking of deleting, but never
7684 mind that.) Search that range; see if any ref remains. */
7685 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7687 rtx set = single_set (i2);
7689 /* Uses which just store in the pseudo don't count,
7690 since if they are the only uses, they are dead. */
7691 if (set != 0 && SET_DEST (set) == reg)
7696 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
7697 && reg_mentioned_p (reg, PATTERN (i2)))
7699 /* Some other ref remains; just delete the output reload we
7701 delete_address_reloads (output_reload_insn, insn);
7702 delete_insn (output_reload_insn);
7707 /* Delete the now-dead stores into this pseudo. Note that this
7708 loop also takes care of deleting output_reload_insn. */
7709 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7711 rtx set = single_set (i2);
7713 if (set != 0 && SET_DEST (set) == reg)
7715 delete_address_reloads (i2, insn);
7723 /* For the debugging info, say the pseudo lives in this reload reg. */
7724 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7725 alter_reg (REGNO (reg), -1);
7729 delete_address_reloads (output_reload_insn, insn);
7730 delete_insn (output_reload_insn);
7734 /* We are going to delete DEAD_INSN. Recursively delete loads of
7735 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7736 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7738 delete_address_reloads (rtx dead_insn, rtx current_insn)
7740 rtx set = single_set (dead_insn);
7741 rtx set2, dst, prev, next;
7744 rtx dst = SET_DEST (set);
7746 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7748 /* If we deleted the store from a reloaded post_{in,de}c expression,
7749 we can delete the matching adds. */
7750 prev = PREV_INSN (dead_insn);
7751 next = NEXT_INSN (dead_insn);
7752 if (! prev || ! next)
7754 set = single_set (next);
7755 set2 = single_set (prev);
7757 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7758 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7759 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7761 dst = SET_DEST (set);
7762 if (! rtx_equal_p (dst, SET_DEST (set2))
7763 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7764 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7765 || (INTVAL (XEXP (SET_SRC (set), 1))
7766 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7768 delete_related_insns (prev);
7769 delete_related_insns (next);
7772 /* Subfunction of delete_address_reloads: process registers found in X. */
7774 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
7776 rtx prev, set, dst, i2;
7778 enum rtx_code code = GET_CODE (x);
7782 const char *fmt = GET_RTX_FORMAT (code);
7783 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7786 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7787 else if (fmt[i] == 'E')
7789 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7790 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7797 if (spill_reg_order[REGNO (x)] < 0)
7800 /* Scan backwards for the insn that sets x. This might be a way back due
7802 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7804 code = GET_CODE (prev);
7805 if (code == CODE_LABEL || code == JUMP_INSN)
7809 if (reg_set_p (x, PATTERN (prev)))
7811 if (reg_referenced_p (x, PATTERN (prev)))
7814 if (! prev || INSN_UID (prev) < reload_first_uid)
7816 /* Check that PREV only sets the reload register. */
7817 set = single_set (prev);
7820 dst = SET_DEST (set);
7822 || ! rtx_equal_p (dst, x))
7824 if (! reg_set_p (dst, PATTERN (dead_insn)))
7826 /* Check if DST was used in a later insn -
7827 it might have been inherited. */
7828 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7834 if (reg_referenced_p (dst, PATTERN (i2)))
7836 /* If there is a reference to the register in the current insn,
7837 it might be loaded in a non-inherited reload. If no other
7838 reload uses it, that means the register is set before
7840 if (i2 == current_insn)
7842 for (j = n_reloads - 1; j >= 0; j--)
7843 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7844 || reload_override_in[j] == dst)
7846 for (j = n_reloads - 1; j >= 0; j--)
7847 if (rld[j].in && rld[j].reg_rtx == dst)
7856 /* If DST is still live at CURRENT_INSN, check if it is used for
7857 any reload. Note that even if CURRENT_INSN sets DST, we still
7858 have to check the reloads. */
7859 if (i2 == current_insn)
7861 for (j = n_reloads - 1; j >= 0; j--)
7862 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7863 || reload_override_in[j] == dst)
7865 /* ??? We can't finish the loop here, because dst might be
7866 allocated to a pseudo in this block if no reload in this
7867 block needs any of the classes containing DST - see
7868 spill_hard_reg. There is no easy way to tell this, so we
7869 have to scan till the end of the basic block. */
7871 if (reg_set_p (dst, PATTERN (i2)))
7875 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7876 reg_reloaded_contents[REGNO (dst)] = -1;
7880 /* Output reload-insns to reload VALUE into RELOADREG.
7881 VALUE is an autoincrement or autodecrement RTX whose operand
7882 is a register or memory location;
7883 so reloading involves incrementing that location.
7884 IN is either identical to VALUE, or some cheaper place to reload from.
7886 INC_AMOUNT is the number to increment or decrement by (always positive).
7887 This cannot be deduced from VALUE.
7889 Return the instruction that stores into RELOADREG. */
7892 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
7894 /* REG or MEM to be copied and incremented. */
7895 rtx incloc = XEXP (value, 0);
7896 /* Nonzero if increment after copying. */
7897 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7903 rtx real_in = in == value ? XEXP (in, 0) : in;
7905 /* No hard register is equivalent to this register after
7906 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7907 we could inc/dec that register as well (maybe even using it for
7908 the source), but I'm not sure it's worth worrying about. */
7910 reg_last_reload_reg[REGNO (incloc)] = 0;
7912 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7913 inc_amount = -inc_amount;
7915 inc = GEN_INT (inc_amount);
7917 /* If this is post-increment, first copy the location to the reload reg. */
7918 if (post && real_in != reloadreg)
7919 emit_insn (gen_move_insn (reloadreg, real_in));
7923 /* See if we can directly increment INCLOC. Use a method similar to
7924 that in gen_reload. */
7926 last = get_last_insn ();
7927 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7928 gen_rtx_PLUS (GET_MODE (incloc),
7931 code = recog_memoized (add_insn);
7934 extract_insn (add_insn);
7935 if (constrain_operands (1))
7937 /* If this is a pre-increment and we have incremented the value
7938 where it lives, copy the incremented value to RELOADREG to
7939 be used as an address. */
7942 emit_insn (gen_move_insn (reloadreg, incloc));
7947 delete_insns_since (last);
7950 /* If couldn't do the increment directly, must increment in RELOADREG.
7951 The way we do this depends on whether this is pre- or post-increment.
7952 For pre-increment, copy INCLOC to the reload register, increment it
7953 there, then save back. */
7957 if (in != reloadreg)
7958 emit_insn (gen_move_insn (reloadreg, real_in));
7959 emit_insn (gen_add2_insn (reloadreg, inc));
7960 store = emit_insn (gen_move_insn (incloc, reloadreg));
7965 Because this might be a jump insn or a compare, and because RELOADREG
7966 may not be available after the insn in an input reload, we must do
7967 the incrementation before the insn being reloaded for.
7969 We have already copied IN to RELOADREG. Increment the copy in
7970 RELOADREG, save that back, then decrement RELOADREG so it has
7971 the original value. */
7973 emit_insn (gen_add2_insn (reloadreg, inc));
7974 store = emit_insn (gen_move_insn (incloc, reloadreg));
7975 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7983 add_auto_inc_notes (rtx insn, rtx x)
7985 enum rtx_code code = GET_CODE (x);
7989 if (code == MEM && auto_inc_p (XEXP (x, 0)))
7992 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
7996 /* Scan all the operand sub-expressions. */
7997 fmt = GET_RTX_FORMAT (code);
7998 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8001 add_auto_inc_notes (insn, XEXP (x, i));
8002 else if (fmt[i] == 'E')
8003 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8004 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8009 /* Copy EH notes from an insn to its reloads. */
8011 copy_eh_notes (rtx insn, rtx x)
8013 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8016 for (; x != 0; x = NEXT_INSN (x))
8018 if (may_trap_p (PATTERN (x)))
8020 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8026 /* This is used by reload pass, that does emit some instructions after
8027 abnormal calls moving basic block end, but in fact it wants to emit
8028 them on the edge. Looks for abnormal call edges, find backward the
8029 proper call and fix the damage.
8031 Similar handle instructions throwing exceptions internally. */
8033 fixup_abnormal_edges (void)
8035 bool inserted = false;
8043 /* Look for cases we are interested in - calls or instructions causing
8045 FOR_EACH_EDGE (e, ei, bb->succs)
8047 if (e->flags & EDGE_ABNORMAL_CALL)
8049 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8050 == (EDGE_ABNORMAL | EDGE_EH))
8053 if (e && !CALL_P (BB_END (bb))
8054 && !can_throw_internal (BB_END (bb)))
8056 rtx insn = BB_END (bb), stop = NEXT_INSN (BB_END (bb));
8058 FOR_EACH_EDGE (e, ei, bb->succs)
8059 if (e->flags & EDGE_FALLTHRU)
8061 /* Get past the new insns generated. Allow notes, as the insns may
8062 be already deleted. */
8063 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8064 && !can_throw_internal (insn)
8065 && insn != BB_HEAD (bb))
8066 insn = PREV_INSN (insn);
8067 gcc_assert (CALL_P (insn) || can_throw_internal (insn));
8070 insn = NEXT_INSN (insn);
8071 while (insn && insn != stop)
8073 next = NEXT_INSN (insn);
8078 /* Sometimes there's still the return value USE.
8079 If it's placed after a trapping call (i.e. that
8080 call is the last insn anyway), we have no fallthru
8081 edge. Simply delete this use and don't try to insert
8082 on the non-existent edge. */
8083 if (GET_CODE (PATTERN (insn)) != USE)
8085 /* We're not deleting it, we're moving it. */
8086 INSN_DELETED_P (insn) = 0;
8087 PREV_INSN (insn) = NULL_RTX;
8088 NEXT_INSN (insn) = NULL_RTX;
8090 insert_insn_on_edge (insn, e);
8097 /* We've possibly turned single trapping insn into multiple ones. */
8098 if (flag_non_call_exceptions)
8101 blocks = sbitmap_alloc (last_basic_block);
8102 sbitmap_ones (blocks);
8103 find_many_sub_basic_blocks (blocks);
8106 commit_edge_insertions ();
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