1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 88, 89, 92, 93, 94, 1995 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "insn-config.h"
27 #include "insn-flags.h"
28 #include "insn-codes.h"
32 #include "hard-reg-set.h"
35 #include "basic-block.h"
39 /* This file contains the reload pass of the compiler, which is
40 run after register allocation has been done. It checks that
41 each insn is valid (operands required to be in registers really
42 are in registers of the proper class) and fixes up invalid ones
43 by copying values temporarily into registers for the insns
46 The results of register allocation are described by the vector
47 reg_renumber; the insns still contain pseudo regs, but reg_renumber
48 can be used to find which hard reg, if any, a pseudo reg is in.
50 The technique we always use is to free up a few hard regs that are
51 called ``reload regs'', and for each place where a pseudo reg
52 must be in a hard reg, copy it temporarily into one of the reload regs.
54 All the pseudos that were formerly allocated to the hard regs that
55 are now in use as reload regs must be ``spilled''. This means
56 that they go to other hard regs, or to stack slots if no other
57 available hard regs can be found. Spilling can invalidate more
58 insns, requiring additional need for reloads, so we must keep checking
59 until the process stabilizes.
61 For machines with different classes of registers, we must keep track
62 of the register class needed for each reload, and make sure that
63 we allocate enough reload registers of each class.
65 The file reload.c contains the code that checks one insn for
66 validity and reports the reloads that it needs. This file
67 is in charge of scanning the entire rtl code, accumulating the
68 reload needs, spilling, assigning reload registers to use for
69 fixing up each insn, and generating the new insns to copy values
70 into the reload registers. */
73 #ifndef REGISTER_MOVE_COST
74 #define REGISTER_MOVE_COST(x, y) 2
77 #ifndef MEMORY_MOVE_COST
78 #define MEMORY_MOVE_COST(x) 4
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx *reg_equiv_memory_loc;
105 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
106 This is used when the address is not valid as a memory address
107 (because its displacement is too big for the machine.) */
108 rtx *reg_equiv_address;
110 /* Element N is the memory slot to which pseudo reg N is equivalent,
111 or zero if pseudo reg N is not equivalent to a memory slot. */
114 /* Widest width in which each pseudo reg is referred to (via subreg). */
115 static int *reg_max_ref_width;
117 /* Element N is the insn that initialized reg N from its equivalent
118 constant or memory slot. */
119 static rtx *reg_equiv_init;
121 /* During reload_as_needed, element N contains the last pseudo regno
122 reloaded into the Nth reload register. This vector is in parallel
123 with spill_regs. If that pseudo reg occupied more than one register,
124 reg_reloaded_contents points to that pseudo for each spill register in
125 use; all of these must remain set for an inheritance to occur. */
126 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
128 /* During reload_as_needed, element N contains the insn for which
129 the Nth reload register was last used. This vector is in parallel
130 with spill_regs, and its contents are significant only when
131 reg_reloaded_contents is significant. */
132 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
134 /* Number of spill-regs so far; number of valid elements of spill_regs. */
137 /* In parallel with spill_regs, contains REG rtx's for those regs.
138 Holds the last rtx used for any given reg, or 0 if it has never
139 been used for spilling yet. This rtx is reused, provided it has
141 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
143 /* In parallel with spill_regs, contains nonzero for a spill reg
144 that was stored after the last time it was used.
145 The precise value is the insn generated to do the store. */
146 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
148 /* This table is the inverse mapping of spill_regs:
149 indexed by hard reg number,
150 it contains the position of that reg in spill_regs,
151 or -1 for something that is not in spill_regs. */
152 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
154 /* This reg set indicates registers that may not be used for retrying global
155 allocation. The registers that may not be used include all spill registers
156 and the frame pointer (if we are using one). */
157 HARD_REG_SET forbidden_regs;
159 /* This reg set indicates registers that are not good for spill registers.
160 They will not be used to complete groups of spill registers. This includes
161 all fixed registers, registers that may be eliminated, and, if
162 SMALL_REGISTER_CLASSES is not defined, registers explicitly used in the rtl.
164 (spill_reg_order prevents these registers from being used to start a
166 static HARD_REG_SET bad_spill_regs;
168 /* Describes order of use of registers for reloading
169 of spilled pseudo-registers. `spills' is the number of
170 elements that are actually valid; new ones are added at the end. */
171 static short spill_regs[FIRST_PSEUDO_REGISTER];
173 /* Index of last register assigned as a spill register. We allocate in
174 a round-robin fashion. */
176 static int last_spill_reg;
178 /* Describes order of preference for putting regs into spill_regs.
179 Contains the numbers of all the hard regs, in order most preferred first.
180 This order is different for each function.
181 It is set up by order_regs_for_reload.
182 Empty elements at the end contain -1. */
183 static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
185 /* 1 for a hard register that appears explicitly in the rtl
186 (for example, function value registers, special registers
187 used by insns, structure value pointer registers). */
188 static char regs_explicitly_used[FIRST_PSEUDO_REGISTER];
190 /* Indicates if a register was counted against the need for
191 groups. 0 means it can count against max_nongroup instead. */
192 static HARD_REG_SET counted_for_groups;
194 /* Indicates if a register was counted against the need for
195 non-groups. 0 means it can become part of a new group.
196 During choose_reload_regs, 1 here means don't use this reg
197 as part of a group, even if it seems to be otherwise ok. */
198 static HARD_REG_SET counted_for_nongroups;
200 /* Indexed by pseudo reg number N,
201 says may not delete stores into the real (memory) home of pseudo N.
202 This is set if we already substituted a memory equivalent in some uses,
203 which happens when we have to eliminate the fp from it. */
204 static char *cannot_omit_stores;
206 /* Nonzero if indirect addressing is supported on the machine; this means
207 that spilling (REG n) does not require reloading it into a register in
208 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
209 value indicates the level of indirect addressing supported, e.g., two
210 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
213 static char spill_indirect_levels;
215 /* Nonzero if indirect addressing is supported when the innermost MEM is
216 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
217 which these are valid is the same as spill_indirect_levels, above. */
219 char indirect_symref_ok;
221 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
223 char double_reg_address_ok;
225 /* Record the stack slot for each spilled hard register. */
227 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
229 /* Width allocated so far for that stack slot. */
231 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
233 /* Indexed by register class and basic block number, nonzero if there is
234 any need for a spill register of that class in that basic block.
235 The pointer is 0 if we did stupid allocation and don't know
236 the structure of basic blocks. */
238 char *basic_block_needs[N_REG_CLASSES];
240 /* First uid used by insns created by reload in this function.
241 Used in find_equiv_reg. */
242 int reload_first_uid;
244 /* Flag set by local-alloc or global-alloc if anything is live in
245 a call-clobbered reg across calls. */
247 int caller_save_needed;
249 /* Set to 1 while reload_as_needed is operating.
250 Required by some machines to handle any generated moves differently. */
252 int reload_in_progress = 0;
254 /* These arrays record the insn_code of insns that may be needed to
255 perform input and output reloads of special objects. They provide a
256 place to pass a scratch register. */
258 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
259 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
261 /* This obstack is used for allocation of rtl during register elimination.
262 The allocated storage can be freed once find_reloads has processed the
265 struct obstack reload_obstack;
266 char *reload_firstobj;
268 #define obstack_chunk_alloc xmalloc
269 #define obstack_chunk_free free
271 /* List of labels that must never be deleted. */
272 extern rtx forced_labels;
274 /* This structure is used to record information about register eliminations.
275 Each array entry describes one possible way of eliminating a register
276 in favor of another. If there is more than one way of eliminating a
277 particular register, the most preferred should be specified first. */
279 static struct elim_table
281 int from; /* Register number to be eliminated. */
282 int to; /* Register number used as replacement. */
283 int initial_offset; /* Initial difference between values. */
284 int can_eliminate; /* Non-zero if this elimination can be done. */
285 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
286 insns made by reload. */
287 int offset; /* Current offset between the two regs. */
288 int max_offset; /* Maximum offset between the two regs. */
289 int previous_offset; /* Offset at end of previous insn. */
290 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
291 rtx from_rtx; /* REG rtx for the register to be eliminated.
292 We cannot simply compare the number since
293 we might then spuriously replace a hard
294 register corresponding to a pseudo
295 assigned to the reg to be eliminated. */
296 rtx to_rtx; /* REG rtx for the replacement. */
299 /* If a set of eliminable registers was specified, define the table from it.
300 Otherwise, default to the normal case of the frame pointer being
301 replaced by the stack pointer. */
303 #ifdef ELIMINABLE_REGS
306 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
309 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate / sizeof reg_eliminate[0])
311 /* Record the number of pending eliminations that have an offset not equal
312 to their initial offset. If non-zero, we use a new copy of each
313 replacement result in any insns encountered. */
314 static int num_not_at_initial_offset;
316 /* Count the number of registers that we may be able to eliminate. */
317 static int num_eliminable;
319 /* For each label, we record the offset of each elimination. If we reach
320 a label by more than one path and an offset differs, we cannot do the
321 elimination. This information is indexed by the number of the label.
322 The first table is an array of flags that records whether we have yet
323 encountered a label and the second table is an array of arrays, one
324 entry in the latter array for each elimination. */
326 static char *offsets_known_at;
327 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
329 /* Number of labels in the current function. */
331 static int num_labels;
333 struct hard_reg_n_uses { int regno; int uses; };
335 static int possible_group_p PROTO((int, int *));
336 static void count_possible_groups PROTO((int *, enum machine_mode *,
338 static int modes_equiv_for_class_p PROTO((enum machine_mode,
341 static void spill_failure PROTO((rtx));
342 static int new_spill_reg PROTO((int, int, int *, int *, int,
344 static void delete_dead_insn PROTO((rtx));
345 static void alter_reg PROTO((int, int));
346 static void mark_scratch_live PROTO((rtx));
347 static void set_label_offsets PROTO((rtx, rtx, int));
348 static int eliminate_regs_in_insn PROTO((rtx, int));
349 static void mark_not_eliminable PROTO((rtx, rtx));
350 static int spill_hard_reg PROTO((int, int, FILE *, int));
351 static void scan_paradoxical_subregs PROTO((rtx));
352 static int hard_reg_use_compare PROTO((struct hard_reg_n_uses *,
353 struct hard_reg_n_uses *));
354 static void order_regs_for_reload PROTO((void));
355 static int compare_spill_regs PROTO((short *, short *));
356 static void reload_as_needed PROTO((rtx, int));
357 static void forget_old_reloads_1 PROTO((rtx, rtx));
358 static int reload_reg_class_lower PROTO((short *, short *));
359 static void mark_reload_reg_in_use PROTO((int, int, enum reload_type,
361 static void clear_reload_reg_in_use PROTO((int, int, enum reload_type,
363 static int reload_reg_free_p PROTO((int, int, enum reload_type));
364 static int reload_reg_free_before_p PROTO((int, int, enum reload_type));
365 static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type));
366 static int reloads_conflict PROTO((int, int));
367 static int allocate_reload_reg PROTO((int, rtx, int, int));
368 static void choose_reload_regs PROTO((rtx, rtx));
369 static void merge_assigned_reloads PROTO((rtx));
370 static void emit_reload_insns PROTO((rtx));
371 static void delete_output_reload PROTO((rtx, int, rtx));
372 static void inc_for_reload PROTO((rtx, rtx, int));
373 static int constraint_accepts_reg_p PROTO((char *, rtx));
374 static int count_occurrences PROTO((rtx, rtx));
376 /* Initialize the reload pass once per compilation. */
383 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
384 Set spill_indirect_levels to the number of levels such addressing is
385 permitted, zero if it is not permitted at all. */
388 = gen_rtx (MEM, Pmode,
389 gen_rtx (PLUS, Pmode,
390 gen_rtx (REG, Pmode, LAST_VIRTUAL_REGISTER + 1),
392 spill_indirect_levels = 0;
394 while (memory_address_p (QImode, tem))
396 spill_indirect_levels++;
397 tem = gen_rtx (MEM, Pmode, tem);
400 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
402 tem = gen_rtx (MEM, Pmode, gen_rtx (SYMBOL_REF, Pmode, "foo"));
403 indirect_symref_ok = memory_address_p (QImode, tem);
405 /* See if reg+reg is a valid (and offsettable) address. */
407 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
409 tem = gen_rtx (PLUS, Pmode,
410 gen_rtx (REG, Pmode, HARD_FRAME_POINTER_REGNUM),
411 gen_rtx (REG, Pmode, i));
412 /* This way, we make sure that reg+reg is an offsettable address. */
413 tem = plus_constant (tem, 4);
415 if (memory_address_p (QImode, tem))
417 double_reg_address_ok = 1;
422 /* Initialize obstack for our rtl allocation. */
423 gcc_obstack_init (&reload_obstack);
424 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
427 /* Main entry point for the reload pass.
429 FIRST is the first insn of the function being compiled.
431 GLOBAL nonzero means we were called from global_alloc
432 and should attempt to reallocate any pseudoregs that we
433 displace from hard regs we will use for reloads.
434 If GLOBAL is zero, we do not have enough information to do that,
435 so any pseudo reg that is spilled must go to the stack.
437 DUMPFILE is the global-reg debugging dump file stream, or 0.
438 If it is nonzero, messages are written to it to describe
439 which registers are seized as reload regs, which pseudo regs
440 are spilled from them, and where the pseudo regs are reallocated to.
442 Return value is nonzero if reload failed
443 and we must not do any more for this function. */
446 reload (first, global, dumpfile)
452 register int i, j, k;
454 register struct elim_table *ep;
456 int something_changed;
457 int something_needs_reloads;
458 int something_needs_elimination;
459 int new_basic_block_needs;
460 enum reg_class caller_save_spill_class = NO_REGS;
461 int caller_save_group_size = 1;
463 /* Nonzero means we couldn't get enough spill regs. */
466 /* The basic block number currently being processed for INSN. */
469 /* Make sure even insns with volatile mem refs are recognizable. */
472 /* Enable find_equiv_reg to distinguish insns made by reload. */
473 reload_first_uid = get_max_uid ();
475 for (i = 0; i < N_REG_CLASSES; i++)
476 basic_block_needs[i] = 0;
478 #ifdef SECONDARY_MEMORY_NEEDED
479 /* Initialize the secondary memory table. */
480 clear_secondary_mem ();
483 /* Remember which hard regs appear explicitly
484 before we merge into `regs_ever_live' the ones in which
485 pseudo regs have been allocated. */
486 bcopy (regs_ever_live, regs_explicitly_used, sizeof regs_ever_live);
488 /* We don't have a stack slot for any spill reg yet. */
489 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
490 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
492 /* Initialize the save area information for caller-save, in case some
496 /* Compute which hard registers are now in use
497 as homes for pseudo registers.
498 This is done here rather than (eg) in global_alloc
499 because this point is reached even if not optimizing. */
501 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
504 for (i = 0; i < scratch_list_length; i++)
506 mark_scratch_live (scratch_list[i]);
508 /* Make sure that the last insn in the chain
509 is not something that needs reloading. */
510 emit_note (NULL_PTR, NOTE_INSN_DELETED);
512 /* Find all the pseudo registers that didn't get hard regs
513 but do have known equivalent constants or memory slots.
514 These include parameters (known equivalent to parameter slots)
515 and cse'd or loop-moved constant memory addresses.
517 Record constant equivalents in reg_equiv_constant
518 so they will be substituted by find_reloads.
519 Record memory equivalents in reg_mem_equiv so they can
520 be substituted eventually by altering the REG-rtx's. */
522 reg_equiv_constant = (rtx *) alloca (max_regno * sizeof (rtx));
523 bzero ((char *) reg_equiv_constant, max_regno * sizeof (rtx));
524 reg_equiv_memory_loc = (rtx *) alloca (max_regno * sizeof (rtx));
525 bzero ((char *) reg_equiv_memory_loc, max_regno * sizeof (rtx));
526 reg_equiv_mem = (rtx *) alloca (max_regno * sizeof (rtx));
527 bzero ((char *) reg_equiv_mem, max_regno * sizeof (rtx));
528 reg_equiv_init = (rtx *) alloca (max_regno * sizeof (rtx));
529 bzero ((char *) reg_equiv_init, max_regno * sizeof (rtx));
530 reg_equiv_address = (rtx *) alloca (max_regno * sizeof (rtx));
531 bzero ((char *) reg_equiv_address, max_regno * sizeof (rtx));
532 reg_max_ref_width = (int *) alloca (max_regno * sizeof (int));
533 bzero ((char *) reg_max_ref_width, max_regno * sizeof (int));
534 cannot_omit_stores = (char *) alloca (max_regno);
535 bzero (cannot_omit_stores, max_regno);
537 #ifdef SMALL_REGISTER_CLASSES
538 CLEAR_HARD_REG_SET (forbidden_regs);
541 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
542 Also find all paradoxical subregs and find largest such for each pseudo.
543 On machines with small register classes, record hard registers that
544 are used for user variables. These can never be used for spills. */
546 for (insn = first; insn; insn = NEXT_INSN (insn))
548 rtx set = single_set (insn);
550 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
552 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
554 #ifdef LEGITIMATE_PIC_OPERAND_P
555 && (! CONSTANT_P (XEXP (note, 0)) || ! flag_pic
556 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
560 rtx x = XEXP (note, 0);
561 i = REGNO (SET_DEST (set));
562 if (i > LAST_VIRTUAL_REGISTER)
564 if (GET_CODE (x) == MEM)
565 reg_equiv_memory_loc[i] = x;
566 else if (CONSTANT_P (x))
568 if (LEGITIMATE_CONSTANT_P (x))
569 reg_equiv_constant[i] = x;
571 reg_equiv_memory_loc[i]
572 = force_const_mem (GET_MODE (SET_DEST (set)), x);
577 /* If this register is being made equivalent to a MEM
578 and the MEM is not SET_SRC, the equivalencing insn
579 is one with the MEM as a SET_DEST and it occurs later.
580 So don't mark this insn now. */
581 if (GET_CODE (x) != MEM
582 || rtx_equal_p (SET_SRC (set), x))
583 reg_equiv_init[i] = insn;
588 /* If this insn is setting a MEM from a register equivalent to it,
589 this is the equivalencing insn. */
590 else if (set && GET_CODE (SET_DEST (set)) == MEM
591 && GET_CODE (SET_SRC (set)) == REG
592 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
593 && rtx_equal_p (SET_DEST (set),
594 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
595 reg_equiv_init[REGNO (SET_SRC (set))] = insn;
597 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
598 scan_paradoxical_subregs (PATTERN (insn));
601 /* Does this function require a frame pointer? */
603 frame_pointer_needed = (! flag_omit_frame_pointer
604 #ifdef EXIT_IGNORE_STACK
605 /* ?? If EXIT_IGNORE_STACK is set, we will not save
606 and restore sp for alloca. So we can't eliminate
607 the frame pointer in that case. At some point,
608 we should improve this by emitting the
609 sp-adjusting insns for this case. */
610 || (current_function_calls_alloca
611 && EXIT_IGNORE_STACK)
613 || FRAME_POINTER_REQUIRED);
617 /* Initialize the table of registers to eliminate. The way we do this
618 depends on how the eliminable registers were defined. */
619 #ifdef ELIMINABLE_REGS
620 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
622 ep->can_eliminate = ep->can_eliminate_previous
623 = (CAN_ELIMINATE (ep->from, ep->to)
624 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
627 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
628 = ! frame_pointer_needed;
631 /* Count the number of eliminable registers and build the FROM and TO
632 REG rtx's. Note that code in gen_rtx will cause, e.g.,
633 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
634 We depend on this. */
635 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
637 num_eliminable += ep->can_eliminate;
638 ep->from_rtx = gen_rtx (REG, Pmode, ep->from);
639 ep->to_rtx = gen_rtx (REG, Pmode, ep->to);
642 num_labels = max_label_num () - get_first_label_num ();
644 /* Allocate the tables used to store offset information at labels. */
645 offsets_known_at = (char *) alloca (num_labels);
647 = (int (*)[NUM_ELIMINABLE_REGS])
648 alloca (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
650 offsets_known_at -= get_first_label_num ();
651 offsets_at -= get_first_label_num ();
653 /* Alter each pseudo-reg rtx to contain its hard reg number.
654 Assign stack slots to the pseudos that lack hard regs or equivalents.
655 Do not touch virtual registers. */
657 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
660 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done here
661 because the stack size may be a part of the offset computation for
662 register elimination. */
663 assign_stack_local (BLKmode, 0, 0);
665 /* If we have some registers we think can be eliminated, scan all insns to
666 see if there is an insn that sets one of these registers to something
667 other than itself plus a constant. If so, the register cannot be
668 eliminated. Doing this scan here eliminates an extra pass through the
669 main reload loop in the most common case where register elimination
671 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
672 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
673 || GET_CODE (insn) == CALL_INSN)
674 note_stores (PATTERN (insn), mark_not_eliminable);
676 #ifndef REGISTER_CONSTRAINTS
677 /* If all the pseudo regs have hard regs,
678 except for those that are never referenced,
679 we know that no reloads are needed. */
680 /* But that is not true if there are register constraints, since
681 in that case some pseudos might be in the wrong kind of hard reg. */
683 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
684 if (reg_renumber[i] == -1 && reg_n_refs[i] != 0)
687 if (i == max_regno && num_eliminable == 0 && ! caller_save_needed)
691 /* Compute the order of preference for hard registers to spill.
692 Store them by decreasing preference in potential_reload_regs. */
694 order_regs_for_reload ();
696 /* So far, no hard regs have been spilled. */
698 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
699 spill_reg_order[i] = -1;
701 /* Initialize to -1, which means take the first spill register. */
704 /* On most machines, we can't use any register explicitly used in the
705 rtl as a spill register. But on some, we have to. Those will have
706 taken care to keep the life of hard regs as short as possible. */
708 #ifndef SMALL_REGISTER_CLASSES
709 COPY_HARD_REG_SET (forbidden_regs, bad_spill_regs);
712 /* Spill any hard regs that we know we can't eliminate. */
713 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
714 if (! ep->can_eliminate)
715 spill_hard_reg (ep->from, global, dumpfile, 1);
717 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
718 if (frame_pointer_needed)
719 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, global, dumpfile, 1);
723 for (i = 0; i < N_REG_CLASSES; i++)
725 basic_block_needs[i] = (char *) alloca (n_basic_blocks);
726 bzero (basic_block_needs[i], n_basic_blocks);
729 /* From now on, we need to emit any moves without making new pseudos. */
730 reload_in_progress = 1;
732 /* This loop scans the entire function each go-round
733 and repeats until one repetition spills no additional hard regs. */
735 /* This flag is set when a pseudo reg is spilled,
736 to require another pass. Note that getting an additional reload
737 reg does not necessarily imply any pseudo reg was spilled;
738 sometimes we find a reload reg that no pseudo reg was allocated in. */
739 something_changed = 1;
740 /* This flag is set if there are any insns that require reloading. */
741 something_needs_reloads = 0;
742 /* This flag is set if there are any insns that require register
744 something_needs_elimination = 0;
745 while (something_changed)
749 /* For each class, number of reload regs needed in that class.
750 This is the maximum over all insns of the needs in that class
751 of the individual insn. */
752 int max_needs[N_REG_CLASSES];
753 /* For each class, size of group of consecutive regs
754 that is needed for the reloads of this class. */
755 int group_size[N_REG_CLASSES];
756 /* For each class, max number of consecutive groups needed.
757 (Each group contains group_size[CLASS] consecutive registers.) */
758 int max_groups[N_REG_CLASSES];
759 /* For each class, max number needed of regs that don't belong
760 to any of the groups. */
761 int max_nongroups[N_REG_CLASSES];
762 /* For each class, the machine mode which requires consecutive
763 groups of regs of that class.
764 If two different modes ever require groups of one class,
765 they must be the same size and equally restrictive for that class,
766 otherwise we can't handle the complexity. */
767 enum machine_mode group_mode[N_REG_CLASSES];
768 /* Record the insn where each maximum need is first found. */
769 rtx max_needs_insn[N_REG_CLASSES];
770 rtx max_groups_insn[N_REG_CLASSES];
771 rtx max_nongroups_insn[N_REG_CLASSES];
773 int starting_frame_size = get_frame_size ();
774 int previous_frame_pointer_needed = frame_pointer_needed;
775 static char *reg_class_names[] = REG_CLASS_NAMES;
777 something_changed = 0;
778 bzero ((char *) max_needs, sizeof max_needs);
779 bzero ((char *) max_groups, sizeof max_groups);
780 bzero ((char *) max_nongroups, sizeof max_nongroups);
781 bzero ((char *) max_needs_insn, sizeof max_needs_insn);
782 bzero ((char *) max_groups_insn, sizeof max_groups_insn);
783 bzero ((char *) max_nongroups_insn, sizeof max_nongroups_insn);
784 bzero ((char *) group_size, sizeof group_size);
785 for (i = 0; i < N_REG_CLASSES; i++)
786 group_mode[i] = VOIDmode;
788 /* Keep track of which basic blocks are needing the reloads. */
791 /* Remember whether any element of basic_block_needs
792 changes from 0 to 1 in this pass. */
793 new_basic_block_needs = 0;
795 /* Reset all offsets on eliminable registers to their initial values. */
796 #ifdef ELIMINABLE_REGS
797 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
799 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
800 ep->previous_offset = ep->offset
801 = ep->max_offset = ep->initial_offset;
804 #ifdef INITIAL_FRAME_POINTER_OFFSET
805 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
807 if (!FRAME_POINTER_REQUIRED)
809 reg_eliminate[0].initial_offset = 0;
811 reg_eliminate[0].previous_offset = reg_eliminate[0].max_offset
812 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
815 num_not_at_initial_offset = 0;
817 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
819 /* Set a known offset for each forced label to be at the initial offset
820 of each elimination. We do this because we assume that all
821 computed jumps occur from a location where each elimination is
822 at its initial offset. */
824 for (x = forced_labels; x; x = XEXP (x, 1))
826 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
828 /* For each pseudo register that has an equivalent location defined,
829 try to eliminate any eliminable registers (such as the frame pointer)
830 assuming initial offsets for the replacement register, which
833 If the resulting location is directly addressable, substitute
834 the MEM we just got directly for the old REG.
836 If it is not addressable but is a constant or the sum of a hard reg
837 and constant, it is probably not addressable because the constant is
838 out of range, in that case record the address; we will generate
839 hairy code to compute the address in a register each time it is
840 needed. Similarly if it is a hard register, but one that is not
841 valid as an address register.
843 If the location is not addressable, but does not have one of the
844 above forms, assign a stack slot. We have to do this to avoid the
845 potential of producing lots of reloads if, e.g., a location involves
846 a pseudo that didn't get a hard register and has an equivalent memory
847 location that also involves a pseudo that didn't get a hard register.
849 Perhaps at some point we will improve reload_when_needed handling
850 so this problem goes away. But that's very hairy. */
852 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
853 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
855 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
857 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
859 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
860 else if (CONSTANT_P (XEXP (x, 0))
861 || (GET_CODE (XEXP (x, 0)) == REG
862 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
863 || (GET_CODE (XEXP (x, 0)) == PLUS
864 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
865 && (REGNO (XEXP (XEXP (x, 0), 0))
866 < FIRST_PSEUDO_REGISTER)
867 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
868 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
871 /* Make a new stack slot. Then indicate that something
872 changed so we go back and recompute offsets for
873 eliminable registers because the allocation of memory
874 below might change some offset. reg_equiv_{mem,address}
875 will be set up for this pseudo on the next pass around
877 reg_equiv_memory_loc[i] = 0;
878 reg_equiv_init[i] = 0;
880 something_changed = 1;
884 /* If we allocated another pseudo to the stack, redo elimination
886 if (something_changed)
889 /* If caller-saves needs a group, initialize the group to include
890 the size and mode required for caller-saves. */
892 if (caller_save_group_size > 1)
894 group_mode[(int) caller_save_spill_class] = Pmode;
895 group_size[(int) caller_save_spill_class] = caller_save_group_size;
898 /* Compute the most additional registers needed by any instruction.
899 Collect information separately for each class of regs. */
901 for (insn = first; insn; insn = NEXT_INSN (insn))
903 if (global && this_block + 1 < n_basic_blocks
904 && insn == basic_block_head[this_block+1])
907 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which
908 might include REG_LABEL), we need to see what effects this
909 has on the known offsets at labels. */
911 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
912 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
913 && REG_NOTES (insn) != 0))
914 set_label_offsets (insn, insn, 0);
916 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
918 /* Nonzero means don't use a reload reg that overlaps
919 the place where a function value can be returned. */
920 rtx avoid_return_reg = 0;
922 rtx old_body = PATTERN (insn);
923 int old_code = INSN_CODE (insn);
924 rtx old_notes = REG_NOTES (insn);
925 int did_elimination = 0;
927 /* To compute the number of reload registers of each class
928 needed for an insn, we must simulate what choose_reload_regs
929 can do. We do this by splitting an insn into an "input" and
930 an "output" part. RELOAD_OTHER reloads are used in both.
931 The input part uses those reloads, RELOAD_FOR_INPUT reloads,
932 which must be live over the entire input section of reloads,
933 and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
934 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the
937 The registers needed for output are RELOAD_OTHER and
938 RELOAD_FOR_OUTPUT, which are live for the entire output
939 portion, and the maximum of all the RELOAD_FOR_OUTPUT_ADDRESS
940 reloads for each operand.
942 The total number of registers needed is the maximum of the
943 inputs and outputs. */
947 /* [0] is normal, [1] is nongroup. */
948 int regs[2][N_REG_CLASSES];
949 int groups[N_REG_CLASSES];
952 /* Each `struct needs' corresponds to one RELOAD_... type. */
958 struct needs other_addr;
959 struct needs op_addr;
960 struct needs op_addr_reload;
961 struct needs in_addr[MAX_RECOG_OPERANDS];
962 struct needs out_addr[MAX_RECOG_OPERANDS];
965 /* If needed, eliminate any eliminable registers. */
967 did_elimination = eliminate_regs_in_insn (insn, 0);
969 #ifdef SMALL_REGISTER_CLASSES
970 /* Set avoid_return_reg if this is an insn
971 that might use the value of a function call. */
972 if (GET_CODE (insn) == CALL_INSN)
974 if (GET_CODE (PATTERN (insn)) == SET)
975 after_call = SET_DEST (PATTERN (insn));
976 else if (GET_CODE (PATTERN (insn)) == PARALLEL
977 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
978 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
982 else if (after_call != 0
983 && !(GET_CODE (PATTERN (insn)) == SET
984 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
986 if (reg_referenced_p (after_call, PATTERN (insn)))
987 avoid_return_reg = after_call;
990 #endif /* SMALL_REGISTER_CLASSES */
992 /* Analyze the instruction. */
993 find_reloads (insn, 0, spill_indirect_levels, global,
996 /* Remember for later shortcuts which insns had any reloads or
997 register eliminations.
999 One might think that it would be worthwhile to mark insns
1000 that need register replacements but not reloads, but this is
1001 not safe because find_reloads may do some manipulation of
1002 the insn (such as swapping commutative operands), which would
1003 be lost when we restore the old pattern after register
1004 replacement. So the actions of find_reloads must be redone in
1005 subsequent passes or in reload_as_needed.
1007 However, it is safe to mark insns that need reloads
1008 but not register replacement. */
1010 PUT_MODE (insn, (did_elimination ? QImode
1011 : n_reloads ? HImode
1012 : GET_MODE (insn) == DImode ? DImode
1015 /* Discard any register replacements done. */
1016 if (did_elimination)
1018 obstack_free (&reload_obstack, reload_firstobj);
1019 PATTERN (insn) = old_body;
1020 INSN_CODE (insn) = old_code;
1021 REG_NOTES (insn) = old_notes;
1022 something_needs_elimination = 1;
1025 /* If this insn has no reloads, we need not do anything except
1026 in the case of a CALL_INSN when we have caller-saves and
1027 caller-save needs reloads. */
1030 && ! (GET_CODE (insn) == CALL_INSN
1031 && caller_save_spill_class != NO_REGS))
1034 something_needs_reloads = 1;
1035 bzero ((char *) &insn_needs, sizeof insn_needs);
1037 /* Count each reload once in every class
1038 containing the reload's own class. */
1040 for (i = 0; i < n_reloads; i++)
1042 register enum reg_class *p;
1043 enum reg_class class = reload_reg_class[i];
1045 enum machine_mode mode;
1047 struct needs *this_needs;
1049 /* Don't count the dummy reloads, for which one of the
1050 regs mentioned in the insn can be used for reloading.
1051 Don't count optional reloads.
1052 Don't count reloads that got combined with others. */
1053 if (reload_reg_rtx[i] != 0
1054 || reload_optional[i] != 0
1055 || (reload_out[i] == 0 && reload_in[i] == 0
1056 && ! reload_secondary_p[i]))
1059 /* Show that a reload register of this class is needed
1060 in this basic block. We do not use insn_needs and
1061 insn_groups because they are overly conservative for
1063 if (global && ! basic_block_needs[(int) class][this_block])
1065 basic_block_needs[(int) class][this_block] = 1;
1066 new_basic_block_needs = 1;
1070 mode = reload_inmode[i];
1071 if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode))
1072 mode = reload_outmode[i];
1073 size = CLASS_MAX_NREGS (class, mode);
1075 /* If this class doesn't want a group, determine if we have
1076 a nongroup need or a regular need. We have a nongroup
1077 need if this reload conflicts with a group reload whose
1078 class intersects with this reload's class. */
1082 for (j = 0; j < n_reloads; j++)
1083 if ((CLASS_MAX_NREGS (reload_reg_class[j],
1084 (GET_MODE_SIZE (reload_outmode[j])
1085 > GET_MODE_SIZE (reload_inmode[j]))
1089 && (!reload_optional[j])
1090 && (reload_in[j] != 0 || reload_out[j] != 0
1091 || reload_secondary_p[j])
1092 && reloads_conflict (i, j)
1093 && reg_classes_intersect_p (class,
1094 reload_reg_class[j]))
1100 /* Decide which time-of-use to count this reload for. */
1101 switch (reload_when_needed[i])
1104 this_needs = &insn_needs.other;
1106 case RELOAD_FOR_INPUT:
1107 this_needs = &insn_needs.input;
1109 case RELOAD_FOR_OUTPUT:
1110 this_needs = &insn_needs.output;
1112 case RELOAD_FOR_INSN:
1113 this_needs = &insn_needs.insn;
1115 case RELOAD_FOR_OTHER_ADDRESS:
1116 this_needs = &insn_needs.other_addr;
1118 case RELOAD_FOR_INPUT_ADDRESS:
1119 this_needs = &insn_needs.in_addr[reload_opnum[i]];
1121 case RELOAD_FOR_OUTPUT_ADDRESS:
1122 this_needs = &insn_needs.out_addr[reload_opnum[i]];
1124 case RELOAD_FOR_OPERAND_ADDRESS:
1125 this_needs = &insn_needs.op_addr;
1127 case RELOAD_FOR_OPADDR_ADDR:
1128 this_needs = &insn_needs.op_addr_reload;
1134 enum machine_mode other_mode, allocate_mode;
1136 /* Count number of groups needed separately from
1137 number of individual regs needed. */
1138 this_needs->groups[(int) class]++;
1139 p = reg_class_superclasses[(int) class];
1140 while (*p != LIM_REG_CLASSES)
1141 this_needs->groups[(int) *p++]++;
1143 /* Record size and mode of a group of this class. */
1144 /* If more than one size group is needed,
1145 make all groups the largest needed size. */
1146 if (group_size[(int) class] < size)
1148 other_mode = group_mode[(int) class];
1149 allocate_mode = mode;
1151 group_size[(int) class] = size;
1152 group_mode[(int) class] = mode;
1157 allocate_mode = group_mode[(int) class];
1160 /* Crash if two dissimilar machine modes both need
1161 groups of consecutive regs of the same class. */
1163 if (other_mode != VOIDmode && other_mode != allocate_mode
1164 && ! modes_equiv_for_class_p (allocate_mode,
1166 fatal_insn ("Two dissimilar machine modes both need groups of consecutive regs of the same class",
1171 this_needs->regs[nongroup_need][(int) class] += 1;
1172 p = reg_class_superclasses[(int) class];
1173 while (*p != LIM_REG_CLASSES)
1174 this_needs->regs[nongroup_need][(int) *p++] += 1;
1180 /* All reloads have been counted for this insn;
1181 now merge the various times of use.
1182 This sets insn_needs, etc., to the maximum total number
1183 of registers needed at any point in this insn. */
1185 for (i = 0; i < N_REG_CLASSES; i++)
1187 int in_max, out_max;
1189 /* Compute normal and nongroup needs. */
1190 for (j = 0; j <= 1; j++)
1192 for (in_max = 0, out_max = 0, k = 0;
1193 k < reload_n_operands; k++)
1196 = MAX (in_max, insn_needs.in_addr[k].regs[j][i]);
1198 = MAX (out_max, insn_needs.out_addr[k].regs[j][i]);
1201 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1202 and operand addresses but not things used to reload
1203 them. Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads
1204 don't conflict with things needed to reload inputs or
1207 in_max = MAX (MAX (insn_needs.op_addr.regs[j][i],
1208 insn_needs.op_addr_reload.regs[j][i]),
1211 out_max = MAX (out_max, insn_needs.insn.regs[j][i]);
1213 insn_needs.input.regs[j][i]
1214 = MAX (insn_needs.input.regs[j][i]
1215 + insn_needs.op_addr.regs[j][i]
1216 + insn_needs.insn.regs[j][i],
1217 in_max + insn_needs.input.regs[j][i]);
1219 insn_needs.output.regs[j][i] += out_max;
1220 insn_needs.other.regs[j][i]
1221 += MAX (MAX (insn_needs.input.regs[j][i],
1222 insn_needs.output.regs[j][i]),
1223 insn_needs.other_addr.regs[j][i]);
1227 /* Now compute group needs. */
1228 for (in_max = 0, out_max = 0, j = 0;
1229 j < reload_n_operands; j++)
1231 in_max = MAX (in_max, insn_needs.in_addr[j].groups[i]);
1233 = MAX (out_max, insn_needs.out_addr[j].groups[i]);
1236 in_max = MAX (MAX (insn_needs.op_addr.groups[i],
1237 insn_needs.op_addr_reload.groups[i]),
1239 out_max = MAX (out_max, insn_needs.insn.groups[i]);
1241 insn_needs.input.groups[i]
1242 = MAX (insn_needs.input.groups[i]
1243 + insn_needs.op_addr.groups[i]
1244 + insn_needs.insn.groups[i],
1245 in_max + insn_needs.input.groups[i]);
1247 insn_needs.output.groups[i] += out_max;
1248 insn_needs.other.groups[i]
1249 += MAX (MAX (insn_needs.input.groups[i],
1250 insn_needs.output.groups[i]),
1251 insn_needs.other_addr.groups[i]);
1254 /* If this is a CALL_INSN and caller-saves will need
1255 a spill register, act as if the spill register is
1256 needed for this insn. However, the spill register
1257 can be used by any reload of this insn, so we only
1258 need do something if no need for that class has
1261 The assumption that every CALL_INSN will trigger a
1262 caller-save is highly conservative, however, the number
1263 of cases where caller-saves will need a spill register but
1264 a block containing a CALL_INSN won't need a spill register
1265 of that class should be quite rare.
1267 If a group is needed, the size and mode of the group will
1268 have been set up at the beginning of this loop. */
1270 if (GET_CODE (insn) == CALL_INSN
1271 && caller_save_spill_class != NO_REGS)
1273 /* See if this register would conflict with any reload
1274 that needs a group. */
1275 int nongroup_need = 0;
1276 int *caller_save_needs;
1278 for (j = 0; j < n_reloads; j++)
1279 if ((CLASS_MAX_NREGS (reload_reg_class[j],
1280 (GET_MODE_SIZE (reload_outmode[j])
1281 > GET_MODE_SIZE (reload_inmode[j]))
1285 && reg_classes_intersect_p (caller_save_spill_class,
1286 reload_reg_class[j]))
1293 = (caller_save_group_size > 1
1294 ? insn_needs.other.groups
1295 : insn_needs.other.regs[nongroup_need]);
1297 if (caller_save_needs[(int) caller_save_spill_class] == 0)
1299 register enum reg_class *p
1300 = reg_class_superclasses[(int) caller_save_spill_class];
1302 caller_save_needs[(int) caller_save_spill_class]++;
1304 while (*p != LIM_REG_CLASSES)
1305 caller_save_needs[(int) *p++] += 1;
1308 /* Show that this basic block will need a register of
1312 && ! (basic_block_needs[(int) caller_save_spill_class]
1315 basic_block_needs[(int) caller_save_spill_class]
1317 new_basic_block_needs = 1;
1321 #ifdef SMALL_REGISTER_CLASSES
1322 /* If this insn stores the value of a function call,
1323 and that value is in a register that has been spilled,
1324 and if the insn needs a reload in a class
1325 that might use that register as the reload register,
1326 then add add an extra need in that class.
1327 This makes sure we have a register available that does
1328 not overlap the return value. */
1330 if (avoid_return_reg)
1332 int regno = REGNO (avoid_return_reg);
1334 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
1336 int basic_needs[N_REG_CLASSES], basic_groups[N_REG_CLASSES];
1338 /* First compute the "basic needs", which counts a
1339 need only in the smallest class in which it
1342 bcopy ((char *) insn_needs.other.regs[0],
1343 (char *) basic_needs, sizeof basic_needs);
1344 bcopy ((char *) insn_needs.other.groups,
1345 (char *) basic_groups, sizeof basic_groups);
1347 for (i = 0; i < N_REG_CLASSES; i++)
1351 if (basic_needs[i] >= 0)
1352 for (p = reg_class_superclasses[i];
1353 *p != LIM_REG_CLASSES; p++)
1354 basic_needs[(int) *p] -= basic_needs[i];
1356 if (basic_groups[i] >= 0)
1357 for (p = reg_class_superclasses[i];
1358 *p != LIM_REG_CLASSES; p++)
1359 basic_groups[(int) *p] -= basic_groups[i];
1362 /* Now count extra regs if there might be a conflict with
1363 the return value register. */
1365 for (r = regno; r < regno + nregs; r++)
1366 if (spill_reg_order[r] >= 0)
1367 for (i = 0; i < N_REG_CLASSES; i++)
1368 if (TEST_HARD_REG_BIT (reg_class_contents[i], r))
1370 if (basic_needs[i] > 0)
1374 insn_needs.other.regs[0][i]++;
1375 p = reg_class_superclasses[i];
1376 while (*p != LIM_REG_CLASSES)
1377 insn_needs.other.regs[0][(int) *p++]++;
1379 if (basic_groups[i] > 0)
1383 insn_needs.other.groups[i]++;
1384 p = reg_class_superclasses[i];
1385 while (*p != LIM_REG_CLASSES)
1386 insn_needs.other.groups[(int) *p++]++;
1390 #endif /* SMALL_REGISTER_CLASSES */
1392 /* For each class, collect maximum need of any insn. */
1394 for (i = 0; i < N_REG_CLASSES; i++)
1396 if (max_needs[i] < insn_needs.other.regs[0][i])
1398 max_needs[i] = insn_needs.other.regs[0][i];
1399 max_needs_insn[i] = insn;
1401 if (max_groups[i] < insn_needs.other.groups[i])
1403 max_groups[i] = insn_needs.other.groups[i];
1404 max_groups_insn[i] = insn;
1406 if (max_nongroups[i] < insn_needs.other.regs[1][i])
1408 max_nongroups[i] = insn_needs.other.regs[1][i];
1409 max_nongroups_insn[i] = insn;
1413 /* Note that there is a continue statement above. */
1416 /* If we allocated any new memory locations, make another pass
1417 since it might have changed elimination offsets. */
1418 if (starting_frame_size != get_frame_size ())
1419 something_changed = 1;
1422 for (i = 0; i < N_REG_CLASSES; i++)
1424 if (max_needs[i] > 0)
1426 ";; Need %d reg%s of class %s (for insn %d).\n",
1427 max_needs[i], max_needs[i] == 1 ? "" : "s",
1428 reg_class_names[i], INSN_UID (max_needs_insn[i]));
1429 if (max_nongroups[i] > 0)
1431 ";; Need %d nongroup reg%s of class %s (for insn %d).\n",
1432 max_nongroups[i], max_nongroups[i] == 1 ? "" : "s",
1433 reg_class_names[i], INSN_UID (max_nongroups_insn[i]));
1434 if (max_groups[i] > 0)
1436 ";; Need %d group%s (%smode) of class %s (for insn %d).\n",
1437 max_groups[i], max_groups[i] == 1 ? "" : "s",
1438 mode_name[(int) group_mode[i]],
1439 reg_class_names[i], INSN_UID (max_groups_insn[i]));
1442 /* If we have caller-saves, set up the save areas and see if caller-save
1443 will need a spill register. */
1445 if (caller_save_needed
1446 && ! setup_save_areas (&something_changed)
1447 && caller_save_spill_class == NO_REGS)
1449 /* The class we will need depends on whether the machine
1450 supports the sum of two registers for an address; see
1451 find_address_reloads for details. */
1453 caller_save_spill_class
1454 = double_reg_address_ok ? INDEX_REG_CLASS : BASE_REG_CLASS;
1455 caller_save_group_size
1456 = CLASS_MAX_NREGS (caller_save_spill_class, Pmode);
1457 something_changed = 1;
1460 /* See if anything that happened changes which eliminations are valid.
1461 For example, on the Sparc, whether or not the frame pointer can
1462 be eliminated can depend on what registers have been used. We need
1463 not check some conditions again (such as flag_omit_frame_pointer)
1464 since they can't have changed. */
1466 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1467 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
1468 #ifdef ELIMINABLE_REGS
1469 || ! CAN_ELIMINATE (ep->from, ep->to)
1472 ep->can_eliminate = 0;
1474 /* Look for the case where we have discovered that we can't replace
1475 register A with register B and that means that we will now be
1476 trying to replace register A with register C. This means we can
1477 no longer replace register C with register B and we need to disable
1478 such an elimination, if it exists. This occurs often with A == ap,
1479 B == sp, and C == fp. */
1481 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1483 struct elim_table *op;
1484 register int new_to = -1;
1486 if (! ep->can_eliminate && ep->can_eliminate_previous)
1488 /* Find the current elimination for ep->from, if there is a
1490 for (op = reg_eliminate;
1491 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1492 if (op->from == ep->from && op->can_eliminate)
1498 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
1500 for (op = reg_eliminate;
1501 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1502 if (op->from == new_to && op->to == ep->to)
1503 op->can_eliminate = 0;
1507 /* See if any registers that we thought we could eliminate the previous
1508 time are no longer eliminable. If so, something has changed and we
1509 must spill the register. Also, recompute the number of eliminable
1510 registers and see if the frame pointer is needed; it is if there is
1511 no elimination of the frame pointer that we can perform. */
1513 frame_pointer_needed = 1;
1514 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1516 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
1517 && ep->to != HARD_FRAME_POINTER_REGNUM)
1518 frame_pointer_needed = 0;
1520 if (! ep->can_eliminate && ep->can_eliminate_previous)
1522 ep->can_eliminate_previous = 0;
1523 spill_hard_reg (ep->from, global, dumpfile, 1);
1524 something_changed = 1;
1529 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1530 /* If we didn't need a frame pointer last time, but we do now, spill
1531 the hard frame pointer. */
1532 if (frame_pointer_needed && ! previous_frame_pointer_needed)
1534 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, global, dumpfile, 1);
1535 something_changed = 1;
1539 /* If all needs are met, we win. */
1541 for (i = 0; i < N_REG_CLASSES; i++)
1542 if (max_needs[i] > 0 || max_groups[i] > 0 || max_nongroups[i] > 0)
1544 if (i == N_REG_CLASSES && !new_basic_block_needs && ! something_changed)
1547 /* Not all needs are met; must spill some hard regs. */
1549 /* Put all registers spilled so far back in potential_reload_regs, but
1550 put them at the front, since we've already spilled most of the
1551 pseudos in them (we might have left some pseudos unspilled if they
1552 were in a block that didn't need any spill registers of a conflicting
1553 class. We used to try to mark off the need for those registers,
1554 but doing so properly is very complex and reallocating them is the
1555 simpler approach. First, "pack" potential_reload_regs by pushing
1556 any nonnegative entries towards the end. That will leave room
1557 for the registers we already spilled.
1559 Also, undo the marking of the spill registers from the last time
1560 around in FORBIDDEN_REGS since we will be probably be allocating
1563 ??? It is theoretically possible that we might end up not using one
1564 of our previously-spilled registers in this allocation, even though
1565 they are at the head of the list. It's not clear what to do about
1566 this, but it was no better before, when we marked off the needs met
1567 by the previously-spilled registers. With the current code, globals
1568 can be allocated into these registers, but locals cannot. */
1572 for (i = j = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
1573 if (potential_reload_regs[i] != -1)
1574 potential_reload_regs[j--] = potential_reload_regs[i];
1576 for (i = 0; i < n_spills; i++)
1578 potential_reload_regs[i] = spill_regs[i];
1579 spill_reg_order[spill_regs[i]] = -1;
1580 CLEAR_HARD_REG_BIT (forbidden_regs, spill_regs[i]);
1586 /* Now find more reload regs to satisfy the remaining need
1587 Do it by ascending class number, since otherwise a reg
1588 might be spilled for a big class and might fail to count
1589 for a smaller class even though it belongs to that class.
1591 Count spilled regs in `spills', and add entries to
1592 `spill_regs' and `spill_reg_order'.
1594 ??? Note there is a problem here.
1595 When there is a need for a group in a high-numbered class,
1596 and also need for non-group regs that come from a lower class,
1597 the non-group regs are chosen first. If there aren't many regs,
1598 they might leave no room for a group.
1600 This was happening on the 386. To fix it, we added the code
1601 that calls possible_group_p, so that the lower class won't
1602 break up the last possible group.
1604 Really fixing the problem would require changes above
1605 in counting the regs already spilled, and in choose_reload_regs.
1606 It might be hard to avoid introducing bugs there. */
1608 CLEAR_HARD_REG_SET (counted_for_groups);
1609 CLEAR_HARD_REG_SET (counted_for_nongroups);
1611 for (class = 0; class < N_REG_CLASSES; class++)
1613 /* First get the groups of registers.
1614 If we got single registers first, we might fragment
1616 while (max_groups[class] > 0)
1618 /* If any single spilled regs happen to form groups,
1619 count them now. Maybe we don't really need
1620 to spill another group. */
1621 count_possible_groups (group_size, group_mode, max_groups,
1624 if (max_groups[class] <= 0)
1627 /* Groups of size 2 (the only groups used on most machines)
1628 are treated specially. */
1629 if (group_size[class] == 2)
1631 /* First, look for a register that will complete a group. */
1632 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1636 j = potential_reload_regs[i];
1637 if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1639 ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1640 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1641 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1642 && HARD_REGNO_MODE_OK (other, group_mode[class])
1643 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1645 /* We don't want one part of another group.
1646 We could get "two groups" that overlap! */
1647 && ! TEST_HARD_REG_BIT (counted_for_groups, other))
1649 (j < FIRST_PSEUDO_REGISTER - 1
1650 && (other = j + 1, spill_reg_order[other] >= 0)
1651 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1652 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1653 && HARD_REGNO_MODE_OK (j, group_mode[class])
1654 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1656 && ! TEST_HARD_REG_BIT (counted_for_groups,
1659 register enum reg_class *p;
1661 /* We have found one that will complete a group,
1662 so count off one group as provided. */
1663 max_groups[class]--;
1664 p = reg_class_superclasses[class];
1665 while (*p != LIM_REG_CLASSES)
1667 if (group_size [(int) *p] <= group_size [class])
1668 max_groups[(int) *p]--;
1672 /* Indicate both these regs are part of a group. */
1673 SET_HARD_REG_BIT (counted_for_groups, j);
1674 SET_HARD_REG_BIT (counted_for_groups, other);
1678 /* We can't complete a group, so start one. */
1679 #ifdef SMALL_REGISTER_CLASSES
1680 /* Look for a pair neither of which is explicitly used. */
1681 if (i == FIRST_PSEUDO_REGISTER)
1682 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1685 j = potential_reload_regs[i];
1686 /* Verify that J+1 is a potential reload reg. */
1687 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1688 if (potential_reload_regs[k] == j + 1)
1690 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1691 && k < FIRST_PSEUDO_REGISTER
1692 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1693 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1694 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1695 && HARD_REGNO_MODE_OK (j, group_mode[class])
1696 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1698 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1)
1699 /* Reject J at this stage
1700 if J+1 was explicitly used. */
1701 && ! regs_explicitly_used[j + 1])
1705 /* Now try any group at all
1706 whose registers are not in bad_spill_regs. */
1707 if (i == FIRST_PSEUDO_REGISTER)
1708 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1711 j = potential_reload_regs[i];
1712 /* Verify that J+1 is a potential reload reg. */
1713 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1714 if (potential_reload_regs[k] == j + 1)
1716 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1717 && k < FIRST_PSEUDO_REGISTER
1718 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1719 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1720 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1721 && HARD_REGNO_MODE_OK (j, group_mode[class])
1722 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1724 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1))
1728 /* I should be the index in potential_reload_regs
1729 of the new reload reg we have found. */
1731 if (i >= FIRST_PSEUDO_REGISTER)
1733 /* There are no groups left to spill. */
1734 spill_failure (max_groups_insn[class]);
1740 |= new_spill_reg (i, class, max_needs, NULL_PTR,
1745 /* For groups of more than 2 registers,
1746 look for a sufficient sequence of unspilled registers,
1747 and spill them all at once. */
1748 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1752 j = potential_reload_regs[i];
1754 && j + group_size[class] <= FIRST_PSEUDO_REGISTER
1755 && HARD_REGNO_MODE_OK (j, group_mode[class]))
1757 /* Check each reg in the sequence. */
1758 for (k = 0; k < group_size[class]; k++)
1759 if (! (spill_reg_order[j + k] < 0
1760 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1761 && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1763 /* We got a full sequence, so spill them all. */
1764 if (k == group_size[class])
1766 register enum reg_class *p;
1767 for (k = 0; k < group_size[class]; k++)
1770 SET_HARD_REG_BIT (counted_for_groups, j + k);
1771 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1772 if (potential_reload_regs[idx] == j + k)
1775 |= new_spill_reg (idx, class,
1776 max_needs, NULL_PTR,
1780 /* We have found one that will complete a group,
1781 so count off one group as provided. */
1782 max_groups[class]--;
1783 p = reg_class_superclasses[class];
1784 while (*p != LIM_REG_CLASSES)
1786 if (group_size [(int) *p]
1787 <= group_size [class])
1788 max_groups[(int) *p]--;
1795 /* We couldn't find any registers for this reload.
1796 Avoid going into an infinite loop. */
1797 if (i >= FIRST_PSEUDO_REGISTER)
1799 /* There are no groups left. */
1800 spill_failure (max_groups_insn[class]);
1807 /* Now similarly satisfy all need for single registers. */
1809 while (max_needs[class] > 0 || max_nongroups[class] > 0)
1811 #ifdef SMALL_REGISTER_CLASSES
1812 /* This should be right for all machines, but only the 386
1813 is known to need it, so this conditional plays safe.
1814 ??? For 2.5, try making this unconditional. */
1815 /* If we spilled enough regs, but they weren't counted
1816 against the non-group need, see if we can count them now.
1817 If so, we can avoid some actual spilling. */
1818 if (max_needs[class] <= 0 && max_nongroups[class] > 0)
1819 for (i = 0; i < n_spills; i++)
1820 if (TEST_HARD_REG_BIT (reg_class_contents[class],
1822 && !TEST_HARD_REG_BIT (counted_for_groups,
1824 && !TEST_HARD_REG_BIT (counted_for_nongroups,
1826 && max_nongroups[class] > 0)
1828 register enum reg_class *p;
1830 SET_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]);
1831 max_nongroups[class]--;
1832 p = reg_class_superclasses[class];
1833 while (*p != LIM_REG_CLASSES)
1834 max_nongroups[(int) *p++]--;
1836 if (max_needs[class] <= 0 && max_nongroups[class] <= 0)
1840 /* Consider the potential reload regs that aren't
1841 yet in use as reload regs, in order of preference.
1842 Find the most preferred one that's in this class. */
1844 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1845 if (potential_reload_regs[i] >= 0
1846 && TEST_HARD_REG_BIT (reg_class_contents[class],
1847 potential_reload_regs[i])
1848 /* If this reg will not be available for groups,
1849 pick one that does not foreclose possible groups.
1850 This is a kludge, and not very general,
1851 but it should be sufficient to make the 386 work,
1852 and the problem should not occur on machines with
1854 && (max_nongroups[class] == 0
1855 || possible_group_p (potential_reload_regs[i], max_groups)))
1858 /* If we couldn't get a register, try to get one even if we
1859 might foreclose possible groups. This may cause problems
1860 later, but that's better than aborting now, since it is
1861 possible that we will, in fact, be able to form the needed
1862 group even with this allocation. */
1864 if (i >= FIRST_PSEUDO_REGISTER
1865 && (asm_noperands (max_needs[class] > 0
1866 ? max_needs_insn[class]
1867 : max_nongroups_insn[class])
1869 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1870 if (potential_reload_regs[i] >= 0
1871 && TEST_HARD_REG_BIT (reg_class_contents[class],
1872 potential_reload_regs[i]))
1875 /* I should be the index in potential_reload_regs
1876 of the new reload reg we have found. */
1878 if (i >= FIRST_PSEUDO_REGISTER)
1880 /* There are no possible registers left to spill. */
1881 spill_failure (max_needs[class] > 0 ? max_needs_insn[class]
1882 : max_nongroups_insn[class]);
1888 |= new_spill_reg (i, class, max_needs, max_nongroups,
1894 /* If global-alloc was run, notify it of any register eliminations we have
1897 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1898 if (ep->can_eliminate)
1899 mark_elimination (ep->from, ep->to);
1901 /* Insert code to save and restore call-clobbered hard regs
1902 around calls. Tell if what mode to use so that we will process
1903 those insns in reload_as_needed if we have to. */
1905 if (caller_save_needed)
1906 save_call_clobbered_regs (num_eliminable ? QImode
1907 : caller_save_spill_class != NO_REGS ? HImode
1910 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1911 If that insn didn't set the register (i.e., it copied the register to
1912 memory), just delete that insn instead of the equivalencing insn plus
1913 anything now dead. If we call delete_dead_insn on that insn, we may
1914 delete the insn that actually sets the register if the register die
1915 there and that is incorrect. */
1917 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1918 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0
1919 && GET_CODE (reg_equiv_init[i]) != NOTE)
1921 if (reg_set_p (regno_reg_rtx[i], PATTERN (reg_equiv_init[i])))
1922 delete_dead_insn (reg_equiv_init[i]);
1925 PUT_CODE (reg_equiv_init[i], NOTE);
1926 NOTE_SOURCE_FILE (reg_equiv_init[i]) = 0;
1927 NOTE_LINE_NUMBER (reg_equiv_init[i]) = NOTE_INSN_DELETED;
1931 /* Use the reload registers where necessary
1932 by generating move instructions to move the must-be-register
1933 values into or out of the reload registers. */
1935 if (something_needs_reloads || something_needs_elimination
1936 || (caller_save_needed && num_eliminable)
1937 || caller_save_spill_class != NO_REGS)
1938 reload_as_needed (first, global);
1940 /* If we were able to eliminate the frame pointer, show that it is no
1941 longer live at the start of any basic block. If it ls live by
1942 virtue of being in a pseudo, that pseudo will be marked live
1943 and hence the frame pointer will be known to be live via that
1946 if (! frame_pointer_needed)
1947 for (i = 0; i < n_basic_blocks; i++)
1948 basic_block_live_at_start[i][HARD_FRAME_POINTER_REGNUM / REGSET_ELT_BITS]
1949 &= ~ ((REGSET_ELT_TYPE) 1 << (HARD_FRAME_POINTER_REGNUM
1950 % REGSET_ELT_BITS));
1952 /* Come here (with failure set nonzero) if we can't get enough spill regs
1953 and we decide not to abort about it. */
1956 reload_in_progress = 0;
1958 /* Now eliminate all pseudo regs by modifying them into
1959 their equivalent memory references.
1960 The REG-rtx's for the pseudos are modified in place,
1961 so all insns that used to refer to them now refer to memory.
1963 For a reg that has a reg_equiv_address, all those insns
1964 were changed by reloading so that no insns refer to it any longer;
1965 but the DECL_RTL of a variable decl may refer to it,
1966 and if so this causes the debugging info to mention the variable. */
1968 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1972 if (reg_equiv_mem[i])
1974 addr = XEXP (reg_equiv_mem[i], 0);
1975 in_struct = MEM_IN_STRUCT_P (reg_equiv_mem[i]);
1977 if (reg_equiv_address[i])
1978 addr = reg_equiv_address[i];
1981 if (reg_renumber[i] < 0)
1983 rtx reg = regno_reg_rtx[i];
1984 XEXP (reg, 0) = addr;
1985 REG_USERVAR_P (reg) = 0;
1986 MEM_IN_STRUCT_P (reg) = in_struct;
1987 PUT_CODE (reg, MEM);
1989 else if (reg_equiv_mem[i])
1990 XEXP (reg_equiv_mem[i], 0) = addr;
1994 #ifdef PRESERVE_DEATH_INFO_REGNO_P
1995 /* Make a pass over all the insns and remove death notes for things that
1996 are no longer registers or no longer die in the insn (e.g., an input
1997 and output pseudo being tied). */
1999 for (insn = first; insn; insn = NEXT_INSN (insn))
2000 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
2004 for (note = REG_NOTES (insn); note; note = next)
2006 next = XEXP (note, 1);
2007 if (REG_NOTE_KIND (note) == REG_DEAD
2008 && (GET_CODE (XEXP (note, 0)) != REG
2009 || reg_set_p (XEXP (note, 0), PATTERN (insn))))
2010 remove_note (insn, note);
2015 /* Indicate that we no longer have known memory locations or constants. */
2016 reg_equiv_constant = 0;
2017 reg_equiv_memory_loc = 0;
2020 free (scratch_list);
2023 free (scratch_block);
2029 /* Nonzero if, after spilling reg REGNO for non-groups,
2030 it will still be possible to find a group if we still need one. */
2033 possible_group_p (regno, max_groups)
2038 int class = (int) NO_REGS;
2040 for (i = 0; i < (int) N_REG_CLASSES; i++)
2041 if (max_groups[i] > 0)
2047 if (class == (int) NO_REGS)
2050 /* Consider each pair of consecutive registers. */
2051 for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
2053 /* Ignore pairs that include reg REGNO. */
2054 if (i == regno || i + 1 == regno)
2057 /* Ignore pairs that are outside the class that needs the group.
2058 ??? Here we fail to handle the case where two different classes
2059 independently need groups. But this never happens with our
2060 current machine descriptions. */
2061 if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
2062 && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
2065 /* A pair of consecutive regs we can still spill does the trick. */
2066 if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
2067 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2068 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
2071 /* A pair of one already spilled and one we can spill does it
2072 provided the one already spilled is not otherwise reserved. */
2073 if (spill_reg_order[i] < 0
2074 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2075 && spill_reg_order[i + 1] >= 0
2076 && ! TEST_HARD_REG_BIT (counted_for_groups, i + 1)
2077 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i + 1))
2079 if (spill_reg_order[i + 1] < 0
2080 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
2081 && spill_reg_order[i] >= 0
2082 && ! TEST_HARD_REG_BIT (counted_for_groups, i)
2083 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i))
2090 /* Count any groups of CLASS that can be formed from the registers recently
2094 count_possible_groups (group_size, group_mode, max_groups, class)
2096 enum machine_mode *group_mode;
2103 /* Now find all consecutive groups of spilled registers
2104 and mark each group off against the need for such groups.
2105 But don't count them against ordinary need, yet. */
2107 if (group_size[class] == 0)
2110 CLEAR_HARD_REG_SET (new);
2112 /* Make a mask of all the regs that are spill regs in class I. */
2113 for (i = 0; i < n_spills; i++)
2114 if (TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i])
2115 && ! TEST_HARD_REG_BIT (counted_for_groups, spill_regs[i])
2116 && ! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
2117 SET_HARD_REG_BIT (new, spill_regs[i]);
2119 /* Find each consecutive group of them. */
2120 for (i = 0; i < FIRST_PSEUDO_REGISTER && max_groups[class] > 0; i++)
2121 if (TEST_HARD_REG_BIT (new, i)
2122 && i + group_size[class] <= FIRST_PSEUDO_REGISTER
2123 && HARD_REGNO_MODE_OK (i, group_mode[class]))
2125 for (j = 1; j < group_size[class]; j++)
2126 if (! TEST_HARD_REG_BIT (new, i + j))
2129 if (j == group_size[class])
2131 /* We found a group. Mark it off against this class's need for
2132 groups, and against each superclass too. */
2133 register enum reg_class *p;
2135 max_groups[class]--;
2136 p = reg_class_superclasses[class];
2137 while (*p != LIM_REG_CLASSES)
2139 if (group_size [(int) *p] <= group_size [class])
2140 max_groups[(int) *p]--;
2144 /* Don't count these registers again. */
2145 for (j = 0; j < group_size[class]; j++)
2146 SET_HARD_REG_BIT (counted_for_groups, i + j);
2149 /* Skip to the last reg in this group. When i is incremented above,
2150 it will then point to the first reg of the next possible group. */
2155 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2156 another mode that needs to be reloaded for the same register class CLASS.
2157 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2158 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2160 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2161 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2162 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2163 causes unnecessary failures on machines requiring alignment of register
2164 groups when the two modes are different sizes, because the larger mode has
2165 more strict alignment rules than the smaller mode. */
2168 modes_equiv_for_class_p (allocate_mode, other_mode, class)
2169 enum machine_mode allocate_mode, other_mode;
2170 enum reg_class class;
2173 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2175 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
2176 && HARD_REGNO_MODE_OK (regno, allocate_mode)
2177 && ! HARD_REGNO_MODE_OK (regno, other_mode))
2183 /* Handle the failure to find a register to spill.
2184 INSN should be one of the insns which needed this particular spill reg. */
2187 spill_failure (insn)
2190 if (asm_noperands (PATTERN (insn)) >= 0)
2191 error_for_asm (insn, "`asm' needs too many reloads");
2193 fatal_insn ("Unable to find a register to spill.", insn);
2196 /* Add a new register to the tables of available spill-registers
2197 (as well as spilling all pseudos allocated to the register).
2198 I is the index of this register in potential_reload_regs.
2199 CLASS is the regclass whose need is being satisfied.
2200 MAX_NEEDS and MAX_NONGROUPS are the vectors of needs,
2201 so that this register can count off against them.
2202 MAX_NONGROUPS is 0 if this register is part of a group.
2203 GLOBAL and DUMPFILE are the same as the args that `reload' got. */
2206 new_spill_reg (i, class, max_needs, max_nongroups, global, dumpfile)
2214 register enum reg_class *p;
2216 int regno = potential_reload_regs[i];
2218 if (i >= FIRST_PSEUDO_REGISTER)
2219 abort (); /* Caller failed to find any register. */
2221 if (fixed_regs[regno] || TEST_HARD_REG_BIT (forbidden_regs, regno))
2222 fatal ("fixed or forbidden register was spilled.\n\
2223 This may be due to a compiler bug or to impossible asm\n\
2224 statements or clauses.");
2226 /* Make reg REGNO an additional reload reg. */
2228 potential_reload_regs[i] = -1;
2229 spill_regs[n_spills] = regno;
2230 spill_reg_order[regno] = n_spills;
2232 fprintf (dumpfile, "Spilling reg %d.\n", spill_regs[n_spills]);
2234 /* Clear off the needs we just satisfied. */
2237 p = reg_class_superclasses[class];
2238 while (*p != LIM_REG_CLASSES)
2239 max_needs[(int) *p++]--;
2241 if (max_nongroups && max_nongroups[class] > 0)
2243 SET_HARD_REG_BIT (counted_for_nongroups, regno);
2244 max_nongroups[class]--;
2245 p = reg_class_superclasses[class];
2246 while (*p != LIM_REG_CLASSES)
2247 max_nongroups[(int) *p++]--;
2250 /* Spill every pseudo reg that was allocated to this reg
2251 or to something that overlaps this reg. */
2253 val = spill_hard_reg (spill_regs[n_spills], global, dumpfile, 0);
2255 /* If there are some registers still to eliminate and this register
2256 wasn't ever used before, additional stack space may have to be
2257 allocated to store this register. Thus, we may have changed the offset
2258 between the stack and frame pointers, so mark that something has changed.
2259 (If new pseudos were spilled, thus requiring more space, VAL would have
2260 been set non-zero by the call to spill_hard_reg above since additional
2261 reloads may be needed in that case.
2263 One might think that we need only set VAL to 1 if this is a call-used
2264 register. However, the set of registers that must be saved by the
2265 prologue is not identical to the call-used set. For example, the
2266 register used by the call insn for the return PC is a call-used register,
2267 but must be saved by the prologue. */
2268 if (num_eliminable && ! regs_ever_live[spill_regs[n_spills]])
2271 regs_ever_live[spill_regs[n_spills]] = 1;
2277 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2278 data that is dead in INSN. */
2281 delete_dead_insn (insn)
2284 rtx prev = prev_real_insn (insn);
2287 /* If the previous insn sets a register that dies in our insn, delete it
2289 if (prev && GET_CODE (PATTERN (prev)) == SET
2290 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
2291 && reg_mentioned_p (prev_dest, PATTERN (insn))
2292 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)))
2293 delete_dead_insn (prev);
2295 PUT_CODE (insn, NOTE);
2296 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2297 NOTE_SOURCE_FILE (insn) = 0;
2300 /* Modify the home of pseudo-reg I.
2301 The new home is present in reg_renumber[I].
2303 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2304 or it may be -1, meaning there is none or it is not relevant.
2305 This is used so that all pseudos spilled from a given hard reg
2306 can share one stack slot. */
2309 alter_reg (i, from_reg)
2313 /* When outputting an inline function, this can happen
2314 for a reg that isn't actually used. */
2315 if (regno_reg_rtx[i] == 0)
2318 /* If the reg got changed to a MEM at rtl-generation time,
2320 if (GET_CODE (regno_reg_rtx[i]) != REG)
2323 /* Modify the reg-rtx to contain the new hard reg
2324 number or else to contain its pseudo reg number. */
2325 REGNO (regno_reg_rtx[i])
2326 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2328 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2329 allocate a stack slot for it. */
2331 if (reg_renumber[i] < 0
2332 && reg_n_refs[i] > 0
2333 && reg_equiv_constant[i] == 0
2334 && reg_equiv_memory_loc[i] == 0)
2337 int inherent_size = PSEUDO_REGNO_BYTES (i);
2338 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2341 /* Each pseudo reg has an inherent size which comes from its own mode,
2342 and a total size which provides room for paradoxical subregs
2343 which refer to the pseudo reg in wider modes.
2345 We can use a slot already allocated if it provides both
2346 enough inherent space and enough total space.
2347 Otherwise, we allocate a new slot, making sure that it has no less
2348 inherent space, and no less total space, then the previous slot. */
2351 /* No known place to spill from => no slot to reuse. */
2352 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size, -1);
2353 if (BYTES_BIG_ENDIAN)
2354 /* Cancel the big-endian correction done in assign_stack_local.
2355 Get the address of the beginning of the slot.
2356 This is so we can do a big-endian correction unconditionally
2358 adjust = inherent_size - total_size;
2360 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2362 /* Reuse a stack slot if possible. */
2363 else if (spill_stack_slot[from_reg] != 0
2364 && spill_stack_slot_width[from_reg] >= total_size
2365 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2367 x = spill_stack_slot[from_reg];
2368 /* Allocate a bigger slot. */
2371 /* Compute maximum size needed, both for inherent size
2372 and for total size. */
2373 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2375 if (spill_stack_slot[from_reg])
2377 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2379 mode = GET_MODE (spill_stack_slot[from_reg]);
2380 if (spill_stack_slot_width[from_reg] > total_size)
2381 total_size = spill_stack_slot_width[from_reg];
2383 /* Make a slot with that size. */
2384 x = assign_stack_local (mode, total_size, -1);
2386 if (BYTES_BIG_ENDIAN)
2388 /* Cancel the big-endian correction done in assign_stack_local.
2389 Get the address of the beginning of the slot.
2390 This is so we can do a big-endian correction unconditionally
2392 adjust = GET_MODE_SIZE (mode) - total_size;
2394 stack_slot = gen_rtx (MEM, mode_for_size (total_size
2397 plus_constant (XEXP (x, 0), adjust));
2399 spill_stack_slot[from_reg] = stack_slot;
2400 spill_stack_slot_width[from_reg] = total_size;
2403 /* On a big endian machine, the "address" of the slot
2404 is the address of the low part that fits its inherent mode. */
2405 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2406 adjust += (total_size - inherent_size);
2408 /* If we have any adjustment to make, or if the stack slot is the
2409 wrong mode, make a new stack slot. */
2410 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2412 x = gen_rtx (MEM, GET_MODE (regno_reg_rtx[i]),
2413 plus_constant (XEXP (x, 0), adjust));
2414 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2417 /* Save the stack slot for later. */
2418 reg_equiv_memory_loc[i] = x;
2422 /* Mark the slots in regs_ever_live for the hard regs
2423 used by pseudo-reg number REGNO. */
2426 mark_home_live (regno)
2429 register int i, lim;
2430 i = reg_renumber[regno];
2433 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2435 regs_ever_live[i++] = 1;
2438 /* Mark the registers used in SCRATCH as being live. */
2441 mark_scratch_live (scratch)
2445 int regno = REGNO (scratch);
2446 int lim = regno + HARD_REGNO_NREGS (regno, GET_MODE (scratch));
2448 for (i = regno; i < lim; i++)
2449 regs_ever_live[i] = 1;
2452 /* This function handles the tracking of elimination offsets around branches.
2454 X is a piece of RTL being scanned.
2456 INSN is the insn that it came from, if any.
2458 INITIAL_P is non-zero if we are to set the offset to be the initial
2459 offset and zero if we are setting the offset of the label to be the
2463 set_label_offsets (x, insn, initial_p)
2468 enum rtx_code code = GET_CODE (x);
2471 struct elim_table *p;
2476 if (LABEL_REF_NONLOCAL_P (x))
2481 /* ... fall through ... */
2484 /* If we know nothing about this label, set the desired offsets. Note
2485 that this sets the offset at a label to be the offset before a label
2486 if we don't know anything about the label. This is not correct for
2487 the label after a BARRIER, but is the best guess we can make. If
2488 we guessed wrong, we will suppress an elimination that might have
2489 been possible had we been able to guess correctly. */
2491 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2493 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2494 offsets_at[CODE_LABEL_NUMBER (x)][i]
2495 = (initial_p ? reg_eliminate[i].initial_offset
2496 : reg_eliminate[i].offset);
2497 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2500 /* Otherwise, if this is the definition of a label and it is
2501 preceded by a BARRIER, set our offsets to the known offset of
2505 && (tem = prev_nonnote_insn (insn)) != 0
2506 && GET_CODE (tem) == BARRIER)
2508 num_not_at_initial_offset = 0;
2509 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2511 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
2512 = offsets_at[CODE_LABEL_NUMBER (x)][i];
2513 if (reg_eliminate[i].can_eliminate
2514 && (reg_eliminate[i].offset
2515 != reg_eliminate[i].initial_offset))
2516 num_not_at_initial_offset++;
2521 /* If neither of the above cases is true, compare each offset
2522 with those previously recorded and suppress any eliminations
2523 where the offsets disagree. */
2525 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2526 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2527 != (initial_p ? reg_eliminate[i].initial_offset
2528 : reg_eliminate[i].offset))
2529 reg_eliminate[i].can_eliminate = 0;
2534 set_label_offsets (PATTERN (insn), insn, initial_p);
2536 /* ... fall through ... */
2540 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2541 and hence must have all eliminations at their initial offsets. */
2542 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2543 if (REG_NOTE_KIND (tem) == REG_LABEL)
2544 set_label_offsets (XEXP (tem, 0), insn, 1);
2549 /* Each of the labels in the address vector must be at their initial
2550 offsets. We want the first first for ADDR_VEC and the second
2551 field for ADDR_DIFF_VEC. */
2553 for (i = 0; i < XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2554 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2559 /* We only care about setting PC. If the source is not RETURN,
2560 IF_THEN_ELSE, or a label, disable any eliminations not at
2561 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2562 isn't one of those possibilities. For branches to a label,
2563 call ourselves recursively.
2565 Note that this can disable elimination unnecessarily when we have
2566 a non-local goto since it will look like a non-constant jump to
2567 someplace in the current function. This isn't a significant
2568 problem since such jumps will normally be when all elimination
2569 pairs are back to their initial offsets. */
2571 if (SET_DEST (x) != pc_rtx)
2574 switch (GET_CODE (SET_SRC (x)))
2581 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2585 tem = XEXP (SET_SRC (x), 1);
2586 if (GET_CODE (tem) == LABEL_REF)
2587 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2588 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2591 tem = XEXP (SET_SRC (x), 2);
2592 if (GET_CODE (tem) == LABEL_REF)
2593 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2594 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2599 /* If we reach here, all eliminations must be at their initial
2600 offset because we are doing a jump to a variable address. */
2601 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2602 if (p->offset != p->initial_offset)
2603 p->can_eliminate = 0;
2607 /* Used for communication between the next two function to properly share
2608 the vector for an ASM_OPERANDS. */
2610 static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec;
2612 /* Scan X and replace any eliminable registers (such as fp) with a
2613 replacement (such as sp), plus an offset.
2615 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2616 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2617 MEM, we are allowed to replace a sum of a register and the constant zero
2618 with the register, which we cannot do outside a MEM. In addition, we need
2619 to record the fact that a register is referenced outside a MEM.
2621 If INSN is an insn, it is the insn containing X. If we replace a REG
2622 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2623 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2624 that the REG is being modified.
2626 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2627 That's used when we eliminate in expressions stored in notes.
2628 This means, do not set ref_outside_mem even if the reference
2631 If we see a modification to a register we know about, take the
2632 appropriate action (see case SET, below).
2634 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2635 replacements done assuming all offsets are at their initial values. If
2636 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2637 encounter, return the actual location so that find_reloads will do
2638 the proper thing. */
2641 eliminate_regs (x, mem_mode, insn)
2643 enum machine_mode mem_mode;
2646 enum rtx_code code = GET_CODE (x);
2647 struct elim_table *ep;
2672 /* First handle the case where we encounter a bare register that
2673 is eliminable. Replace it with a PLUS. */
2674 if (regno < FIRST_PSEUDO_REGISTER)
2676 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2678 if (ep->from_rtx == x && ep->can_eliminate)
2681 /* Refs inside notes don't count for this purpose. */
2682 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2683 || GET_CODE (insn) == INSN_LIST)))
2684 ep->ref_outside_mem = 1;
2685 return plus_constant (ep->to_rtx, ep->previous_offset);
2689 else if (reg_equiv_memory_loc && reg_equiv_memory_loc[regno]
2690 && (reg_equiv_address[regno] || num_not_at_initial_offset))
2692 /* In this case, find_reloads would attempt to either use an
2693 incorrect address (if something is not at its initial offset)
2694 or substitute an replaced address into an insn (which loses
2695 if the offset is changed by some later action). So we simply
2696 return the replaced stack slot (assuming it is changed by
2697 elimination) and ignore the fact that this is actually a
2698 reference to the pseudo. Ensure we make a copy of the
2699 address in case it is shared. */
2700 new = eliminate_regs (reg_equiv_memory_loc[regno],
2702 if (new != reg_equiv_memory_loc[regno])
2704 cannot_omit_stores[regno] = 1;
2705 return copy_rtx (new);
2711 /* If this is the sum of an eliminable register and a constant, rework
2713 if (GET_CODE (XEXP (x, 0)) == REG
2714 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2715 && CONSTANT_P (XEXP (x, 1)))
2717 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2719 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2722 /* Refs inside notes don't count for this purpose. */
2723 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2724 || GET_CODE (insn) == INSN_LIST)))
2725 ep->ref_outside_mem = 1;
2727 /* The only time we want to replace a PLUS with a REG (this
2728 occurs when the constant operand of the PLUS is the negative
2729 of the offset) is when we are inside a MEM. We won't want
2730 to do so at other times because that would change the
2731 structure of the insn in a way that reload can't handle.
2732 We special-case the commonest situation in
2733 eliminate_regs_in_insn, so just replace a PLUS with a
2734 PLUS here, unless inside a MEM. */
2735 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2736 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2739 return gen_rtx (PLUS, Pmode, ep->to_rtx,
2740 plus_constant (XEXP (x, 1),
2741 ep->previous_offset));
2744 /* If the register is not eliminable, we are done since the other
2745 operand is a constant. */
2749 /* If this is part of an address, we want to bring any constant to the
2750 outermost PLUS. We will do this by doing register replacement in
2751 our operands and seeing if a constant shows up in one of them.
2753 We assume here this is part of an address (or a "load address" insn)
2754 since an eliminable register is not likely to appear in any other
2757 If we have (plus (eliminable) (reg)), we want to produce
2758 (plus (plus (replacement) (reg) (const))). If this was part of a
2759 normal add insn, (plus (replacement) (reg)) will be pushed as a
2760 reload. This is the desired action. */
2763 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2764 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2766 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2768 /* If one side is a PLUS and the other side is a pseudo that
2769 didn't get a hard register but has a reg_equiv_constant,
2770 we must replace the constant here since it may no longer
2771 be in the position of any operand. */
2772 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2773 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2774 && reg_renumber[REGNO (new1)] < 0
2775 && reg_equiv_constant != 0
2776 && reg_equiv_constant[REGNO (new1)] != 0)
2777 new1 = reg_equiv_constant[REGNO (new1)];
2778 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2779 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2780 && reg_renumber[REGNO (new0)] < 0
2781 && reg_equiv_constant[REGNO (new0)] != 0)
2782 new0 = reg_equiv_constant[REGNO (new0)];
2784 new = form_sum (new0, new1);
2786 /* As above, if we are not inside a MEM we do not want to
2787 turn a PLUS into something else. We might try to do so here
2788 for an addition of 0 if we aren't optimizing. */
2789 if (! mem_mode && GET_CODE (new) != PLUS)
2790 return gen_rtx (PLUS, GET_MODE (x), new, const0_rtx);
2798 /* If this is the product of an eliminable register and a
2799 constant, apply the distribute law and move the constant out
2800 so that we have (plus (mult ..) ..). This is needed in order
2801 to keep load-address insns valid. This case is pathological.
2802 We ignore the possibility of overflow here. */
2803 if (GET_CODE (XEXP (x, 0)) == REG
2804 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2805 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2806 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2808 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2811 /* Refs inside notes don't count for this purpose. */
2812 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2813 || GET_CODE (insn) == INSN_LIST)))
2814 ep->ref_outside_mem = 1;
2817 plus_constant (gen_rtx (MULT, Pmode, ep->to_rtx, XEXP (x, 1)),
2818 ep->previous_offset * INTVAL (XEXP (x, 1)));
2821 /* ... fall through ... */
2826 case DIV: case UDIV:
2827 case MOD: case UMOD:
2828 case AND: case IOR: case XOR:
2829 case ROTATERT: case ROTATE:
2830 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2832 case GE: case GT: case GEU: case GTU:
2833 case LE: case LT: case LEU: case LTU:
2835 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2837 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2839 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2840 return gen_rtx (code, GET_MODE (x), new0, new1);
2845 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2848 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2849 if (new != XEXP (x, 0))
2850 x = gen_rtx (EXPR_LIST, REG_NOTE_KIND (x), new, XEXP (x, 1));
2853 /* ... fall through ... */
2856 /* Now do eliminations in the rest of the chain. If this was
2857 an EXPR_LIST, this might result in allocating more memory than is
2858 strictly needed, but it simplifies the code. */
2861 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2862 if (new != XEXP (x, 1))
2863 return gen_rtx (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2871 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2872 if (ep->to_rtx == XEXP (x, 0))
2874 int size = GET_MODE_SIZE (mem_mode);
2876 /* If more bytes than MEM_MODE are pushed, account for them. */
2877 #ifdef PUSH_ROUNDING
2878 if (ep->to_rtx == stack_pointer_rtx)
2879 size = PUSH_ROUNDING (size);
2881 if (code == PRE_DEC || code == POST_DEC)
2887 /* Fall through to generic unary operation case. */
2889 case STRICT_LOW_PART:
2891 case SIGN_EXTEND: case ZERO_EXTEND:
2892 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2893 case FLOAT: case FIX:
2894 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2898 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2899 if (new != XEXP (x, 0))
2900 return gen_rtx (code, GET_MODE (x), new);
2904 /* Similar to above processing, but preserve SUBREG_WORD.
2905 Convert (subreg (mem)) to (mem) if not paradoxical.
2906 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2907 pseudo didn't get a hard reg, we must replace this with the
2908 eliminated version of the memory location because push_reloads
2909 may do the replacement in certain circumstances. */
2910 if (GET_CODE (SUBREG_REG (x)) == REG
2911 && (GET_MODE_SIZE (GET_MODE (x))
2912 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2913 && reg_equiv_memory_loc != 0
2914 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2916 new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))],
2919 /* If we didn't change anything, we must retain the pseudo. */
2920 if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))])
2921 new = SUBREG_REG (x);
2924 /* Otherwise, ensure NEW isn't shared in case we have to reload
2926 new = copy_rtx (new);
2928 /* In this case, we must show that the pseudo is used in this
2929 insn so that delete_output_reload will do the right thing. */
2930 if (insn != 0 && GET_CODE (insn) != EXPR_LIST
2931 && GET_CODE (insn) != INSN_LIST)
2932 emit_insn_before (gen_rtx (USE, VOIDmode, SUBREG_REG (x)),
2937 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2939 if (new != XEXP (x, 0))
2941 if (GET_CODE (new) == MEM
2942 && (GET_MODE_SIZE (GET_MODE (x))
2943 <= GET_MODE_SIZE (GET_MODE (new)))
2944 #ifdef LOAD_EXTEND_OP
2945 /* On these machines we will be reloading what is
2946 inside the SUBREG if it originally was a pseudo and
2947 the inner and outer modes are both a word or
2948 smaller. So leave the SUBREG then. */
2949 && ! (GET_CODE (SUBREG_REG (x)) == REG
2950 && GET_MODE_SIZE (GET_MODE (x)) <= UNITS_PER_WORD
2951 && GET_MODE_SIZE (GET_MODE (new)) <= UNITS_PER_WORD
2952 && (GET_MODE_SIZE (GET_MODE (x))
2953 > GET_MODE_SIZE (GET_MODE (new)))
2954 && INTEGRAL_MODE_P (GET_MODE (new))
2955 && LOAD_EXTEND_OP (GET_MODE (new)) != NIL)
2959 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2960 enum machine_mode mode = GET_MODE (x);
2962 if (BYTES_BIG_ENDIAN)
2963 offset += (MIN (UNITS_PER_WORD,
2964 GET_MODE_SIZE (GET_MODE (new)))
2965 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2967 PUT_MODE (new, mode);
2968 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2972 return gen_rtx (SUBREG, GET_MODE (x), new, SUBREG_WORD (x));
2978 /* If clobbering a register that is the replacement register for an
2979 elimination we still think can be performed, note that it cannot
2980 be performed. Otherwise, we need not be concerned about it. */
2981 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2982 if (ep->to_rtx == XEXP (x, 0))
2983 ep->can_eliminate = 0;
2985 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2986 if (new != XEXP (x, 0))
2987 return gen_rtx (code, GET_MODE (x), new);
2993 /* Properly handle sharing input and constraint vectors. */
2994 if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec)
2996 /* When we come to a new vector not seen before,
2997 scan all its elements; keep the old vector if none
2998 of them changes; otherwise, make a copy. */
2999 old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x);
3000 temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx));
3001 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3002 temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i),
3005 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3006 if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i))
3009 if (i == ASM_OPERANDS_INPUT_LENGTH (x))
3010 new_asm_operands_vec = old_asm_operands_vec;
3012 new_asm_operands_vec
3013 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec);
3016 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
3017 if (new_asm_operands_vec == old_asm_operands_vec)
3020 new = gen_rtx (ASM_OPERANDS, VOIDmode, ASM_OPERANDS_TEMPLATE (x),
3021 ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
3022 ASM_OPERANDS_OUTPUT_IDX (x), new_asm_operands_vec,
3023 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x),
3024 ASM_OPERANDS_SOURCE_FILE (x),
3025 ASM_OPERANDS_SOURCE_LINE (x));
3026 new->volatil = x->volatil;
3031 /* Check for setting a register that we know about. */
3032 if (GET_CODE (SET_DEST (x)) == REG)
3034 /* See if this is setting the replacement register for an
3037 If DEST is the hard frame pointer, we do nothing because we
3038 assume that all assignments to the frame pointer are for
3039 non-local gotos and are being done at a time when they are valid
3040 and do not disturb anything else. Some machines want to
3041 eliminate a fake argument pointer (or even a fake frame pointer)
3042 with either the real frame or the stack pointer. Assignments to
3043 the hard frame pointer must not prevent this elimination. */
3045 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3047 if (ep->to_rtx == SET_DEST (x)
3048 && SET_DEST (x) != hard_frame_pointer_rtx)
3050 /* If it is being incremented, adjust the offset. Otherwise,
3051 this elimination can't be done. */
3052 rtx src = SET_SRC (x);
3054 if (GET_CODE (src) == PLUS
3055 && XEXP (src, 0) == SET_DEST (x)
3056 && GET_CODE (XEXP (src, 1)) == CONST_INT)
3057 ep->offset -= INTVAL (XEXP (src, 1));
3059 ep->can_eliminate = 0;
3062 /* Now check to see we are assigning to a register that can be
3063 eliminated. If so, it must be as part of a PARALLEL, since we
3064 will not have been called if this is a single SET. So indicate
3065 that we can no longer eliminate this reg. */
3066 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3068 if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate)
3069 ep->can_eliminate = 0;
3072 /* Now avoid the loop below in this common case. */
3074 rtx new0 = eliminate_regs (SET_DEST (x), 0, insn);
3075 rtx new1 = eliminate_regs (SET_SRC (x), 0, insn);
3077 /* If SET_DEST changed from a REG to a MEM and INSN is an insn,
3078 write a CLOBBER insn. */
3079 if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM
3080 && insn != 0 && GET_CODE (insn) != EXPR_LIST
3081 && GET_CODE (insn) != INSN_LIST)
3082 emit_insn_after (gen_rtx (CLOBBER, VOIDmode, SET_DEST (x)), insn);
3084 if (new0 != SET_DEST (x) || new1 != SET_SRC (x))
3085 return gen_rtx (SET, VOIDmode, new0, new1);
3091 /* Our only special processing is to pass the mode of the MEM to our
3092 recursive call and copy the flags. While we are here, handle this
3093 case more efficiently. */
3094 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
3095 if (new != XEXP (x, 0))
3097 new = gen_rtx (MEM, GET_MODE (x), new);
3098 new->volatil = x->volatil;
3099 new->unchanging = x->unchanging;
3100 new->in_struct = x->in_struct;
3107 /* Process each of our operands recursively. If any have changed, make a
3109 fmt = GET_RTX_FORMAT (code);
3110 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3114 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
3115 if (new != XEXP (x, i) && ! copied)
3117 rtx new_x = rtx_alloc (code);
3118 bcopy ((char *) x, (char *) new_x,
3119 (sizeof (*new_x) - sizeof (new_x->fld)
3120 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
3126 else if (*fmt == 'E')
3129 for (j = 0; j < XVECLEN (x, i); j++)
3131 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
3132 if (new != XVECEXP (x, i, j) && ! copied_vec)
3134 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
3135 &XVECEXP (x, i, 0));
3138 rtx new_x = rtx_alloc (code);
3139 bcopy ((char *) x, (char *) new_x,
3140 (sizeof (*new_x) - sizeof (new_x->fld)
3141 + (sizeof (new_x->fld[0])
3142 * GET_RTX_LENGTH (code))));
3146 XVEC (x, i) = new_v;
3149 XVECEXP (x, i, j) = new;
3157 /* Scan INSN and eliminate all eliminable registers in it.
3159 If REPLACE is nonzero, do the replacement destructively. Also
3160 delete the insn as dead it if it is setting an eliminable register.
3162 If REPLACE is zero, do all our allocations in reload_obstack.
3164 If no eliminations were done and this insn doesn't require any elimination
3165 processing (these are not identical conditions: it might be updating sp,
3166 but not referencing fp; this needs to be seen during reload_as_needed so
3167 that the offset between fp and sp can be taken into consideration), zero
3168 is returned. Otherwise, 1 is returned. */
3171 eliminate_regs_in_insn (insn, replace)
3175 rtx old_body = PATTERN (insn);
3176 rtx old_set = single_set (insn);
3179 struct elim_table *ep;
3182 push_obstacks (&reload_obstack, &reload_obstack);
3184 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
3185 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3187 /* Check for setting an eliminable register. */
3188 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3189 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3191 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3192 /* If this is setting the frame pointer register to the
3193 hardware frame pointer register and this is an elimination
3194 that will be done (tested above), this insn is really
3195 adjusting the frame pointer downward to compensate for
3196 the adjustment done before a nonlocal goto. */
3197 if (ep->from == FRAME_POINTER_REGNUM
3198 && ep->to == HARD_FRAME_POINTER_REGNUM)
3200 rtx src = SET_SRC (old_set);
3203 if (src == ep->to_rtx)
3205 else if (GET_CODE (src) == PLUS
3206 && GET_CODE (XEXP (src, 0)) == CONST_INT)
3207 offset = INTVAL (XEXP (src, 0)), ok = 1;
3214 = plus_constant (ep->to_rtx, offset - ep->offset);
3216 /* First see if this insn remains valid when we
3217 make the change. If not, keep the INSN_CODE
3218 the same and let reload fit it up. */
3219 validate_change (insn, &SET_SRC (old_set), src, 1);
3220 validate_change (insn, &SET_DEST (old_set),
3222 if (! apply_change_group ())
3224 SET_SRC (old_set) = src;
3225 SET_DEST (old_set) = ep->to_rtx;
3235 /* In this case this insn isn't serving a useful purpose. We
3236 will delete it in reload_as_needed once we know that this
3237 elimination is, in fact, being done.
3239 If REPLACE isn't set, we can't delete this insn, but needn't
3240 process it since it won't be used unless something changes. */
3242 delete_dead_insn (insn);
3247 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3248 in the insn is the negative of the offset in FROM. Substitute
3249 (set (reg) (reg to)) for the insn and change its code.
3251 We have to do this here, rather than in eliminate_regs, do that we can
3252 change the insn code. */
3254 if (GET_CODE (SET_SRC (old_set)) == PLUS
3255 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3256 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT)
3257 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3259 if (ep->from_rtx == XEXP (SET_SRC (old_set), 0)
3260 && ep->can_eliminate)
3262 /* We must stop at the first elimination that will be used.
3263 If this one would replace the PLUS with a REG, do it
3264 now. Otherwise, quit the loop and let eliminate_regs
3265 do its normal replacement. */
3266 if (ep->offset == - INTVAL (XEXP (SET_SRC (old_set), 1)))
3268 /* We assume here that we don't need a PARALLEL of
3269 any CLOBBERs for this assignment. There's not
3270 much we can do if we do need it. */
3271 PATTERN (insn) = gen_rtx (SET, VOIDmode,
3272 SET_DEST (old_set), ep->to_rtx);
3273 INSN_CODE (insn) = -1;
3282 old_asm_operands_vec = 0;
3284 /* Replace the body of this insn with a substituted form. If we changed
3285 something, return non-zero.
3287 If we are replacing a body that was a (set X (plus Y Z)), try to
3288 re-recognize the insn. We do this in case we had a simple addition
3289 but now can do this as a load-address. This saves an insn in this
3292 new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX);
3293 if (new_body != old_body)
3295 /* If we aren't replacing things permanently and we changed something,
3296 make another copy to ensure that all the RTL is new. Otherwise
3297 things can go wrong if find_reload swaps commutative operands
3298 and one is inside RTL that has been copied while the other is not. */
3300 /* Don't copy an asm_operands because (1) there's no need and (2)
3301 copy_rtx can't do it properly when there are multiple outputs. */
3302 if (! replace && asm_noperands (old_body) < 0)
3303 new_body = copy_rtx (new_body);
3305 /* If we had a move insn but now we don't, rerecognize it. This will
3306 cause spurious re-recognition if the old move had a PARALLEL since
3307 the new one still will, but we can't call single_set without
3308 having put NEW_BODY into the insn and the re-recognition won't
3309 hurt in this rare case. */
3311 && ((GET_CODE (SET_SRC (old_set)) == REG
3312 && (GET_CODE (new_body) != SET
3313 || GET_CODE (SET_SRC (new_body)) != REG))
3314 /* If this was a load from or store to memory, compare
3315 the MEM in recog_operand to the one in the insn. If they
3316 are not equal, then rerecognize the insn. */
3318 && ((GET_CODE (SET_SRC (old_set)) == MEM
3319 && SET_SRC (old_set) != recog_operand[1])
3320 || (GET_CODE (SET_DEST (old_set)) == MEM
3321 && SET_DEST (old_set) != recog_operand[0])))
3322 /* If this was an add insn before, rerecognize. */
3323 || GET_CODE (SET_SRC (old_set)) == PLUS))
3325 if (! validate_change (insn, &PATTERN (insn), new_body, 0))
3326 /* If recognition fails, store the new body anyway.
3327 It's normal to have recognition failures here
3328 due to bizarre memory addresses; reloading will fix them. */
3329 PATTERN (insn) = new_body;
3332 PATTERN (insn) = new_body;
3337 /* Loop through all elimination pairs. See if any have changed and
3338 recalculate the number not at initial offset.
3340 Compute the maximum offset (minimum offset if the stack does not
3341 grow downward) for each elimination pair.
3343 We also detect a cases where register elimination cannot be done,
3344 namely, if a register would be both changed and referenced outside a MEM
3345 in the resulting insn since such an insn is often undefined and, even if
3346 not, we cannot know what meaning will be given to it. Note that it is
3347 valid to have a register used in an address in an insn that changes it
3348 (presumably with a pre- or post-increment or decrement).
3350 If anything changes, return nonzero. */
3352 num_not_at_initial_offset = 0;
3353 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3355 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3356 ep->can_eliminate = 0;
3358 ep->ref_outside_mem = 0;
3360 if (ep->previous_offset != ep->offset)
3363 ep->previous_offset = ep->offset;
3364 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3365 num_not_at_initial_offset++;
3367 #ifdef STACK_GROWS_DOWNWARD
3368 ep->max_offset = MAX (ep->max_offset, ep->offset);
3370 ep->max_offset = MIN (ep->max_offset, ep->offset);
3375 /* If we changed something, perform elimination in REG_NOTES. This is
3376 needed even when REPLACE is zero because a REG_DEAD note might refer
3377 to a register that we eliminate and could cause a different number
3378 of spill registers to be needed in the final reload pass than in
3380 if (val && REG_NOTES (insn) != 0)
3381 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3389 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3390 replacement we currently believe is valid, mark it as not eliminable if X
3391 modifies DEST in any way other than by adding a constant integer to it.
3393 If DEST is the frame pointer, we do nothing because we assume that
3394 all assignments to the hard frame pointer are nonlocal gotos and are being
3395 done at a time when they are valid and do not disturb anything else.
3396 Some machines want to eliminate a fake argument pointer with either the
3397 frame or stack pointer. Assignments to the hard frame pointer must not
3398 prevent this elimination.
3400 Called via note_stores from reload before starting its passes to scan
3401 the insns of the function. */
3404 mark_not_eliminable (dest, x)
3410 /* A SUBREG of a hard register here is just changing its mode. We should
3411 not see a SUBREG of an eliminable hard register, but check just in
3413 if (GET_CODE (dest) == SUBREG)
3414 dest = SUBREG_REG (dest);
3416 if (dest == hard_frame_pointer_rtx)
3419 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3420 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3421 && (GET_CODE (x) != SET
3422 || GET_CODE (SET_SRC (x)) != PLUS
3423 || XEXP (SET_SRC (x), 0) != dest
3424 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3426 reg_eliminate[i].can_eliminate_previous
3427 = reg_eliminate[i].can_eliminate = 0;
3432 /* Kick all pseudos out of hard register REGNO.
3433 If GLOBAL is nonzero, try to find someplace else to put them.
3434 If DUMPFILE is nonzero, log actions taken on that file.
3436 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3437 because we found we can't eliminate some register. In the case, no pseudos
3438 are allowed to be in the register, even if they are only in a block that
3439 doesn't require spill registers, unlike the case when we are spilling this
3440 hard reg to produce another spill register.
3442 Return nonzero if any pseudos needed to be kicked out. */
3445 spill_hard_reg (regno, global, dumpfile, cant_eliminate)
3451 enum reg_class class = REGNO_REG_CLASS (regno);
3452 int something_changed = 0;
3455 SET_HARD_REG_BIT (forbidden_regs, regno);
3458 regs_ever_live[regno] = 1;
3460 /* Spill every pseudo reg that was allocated to this reg
3461 or to something that overlaps this reg. */
3463 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3464 if (reg_renumber[i] >= 0
3465 && reg_renumber[i] <= regno
3467 + HARD_REGNO_NREGS (reg_renumber[i],
3468 PSEUDO_REGNO_MODE (i))
3471 /* If this register belongs solely to a basic block which needed no
3472 spilling of any class that this register is contained in,
3473 leave it be, unless we are spilling this register because
3474 it was a hard register that can't be eliminated. */
3476 if (! cant_eliminate
3477 && basic_block_needs[0]
3478 && reg_basic_block[i] >= 0
3479 && basic_block_needs[(int) class][reg_basic_block[i]] == 0)
3483 for (p = reg_class_superclasses[(int) class];
3484 *p != LIM_REG_CLASSES; p++)
3485 if (basic_block_needs[(int) *p][reg_basic_block[i]] > 0)
3488 if (*p == LIM_REG_CLASSES)
3492 /* Mark it as no longer having a hard register home. */
3493 reg_renumber[i] = -1;
3494 /* We will need to scan everything again. */
3495 something_changed = 1;
3497 retry_global_alloc (i, forbidden_regs);
3499 alter_reg (i, regno);
3502 if (reg_renumber[i] == -1)
3503 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3505 fprintf (dumpfile, " Register %d now in %d.\n\n",
3506 i, reg_renumber[i]);
3509 for (i = 0; i < scratch_list_length; i++)
3511 if (scratch_list[i] && REGNO (scratch_list[i]) == regno)
3513 if (! cant_eliminate && basic_block_needs[0]
3514 && ! basic_block_needs[(int) class][scratch_block[i]])
3518 for (p = reg_class_superclasses[(int) class];
3519 *p != LIM_REG_CLASSES; p++)
3520 if (basic_block_needs[(int) *p][scratch_block[i]] > 0)
3523 if (*p == LIM_REG_CLASSES)
3526 PUT_CODE (scratch_list[i], SCRATCH);
3527 scratch_list[i] = 0;
3528 something_changed = 1;
3533 return something_changed;
3536 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3537 Also mark any hard registers used to store user variables as
3538 forbidden from being used for spill registers. */
3541 scan_paradoxical_subregs (x)
3546 register enum rtx_code code = GET_CODE (x);
3551 #ifdef SMALL_REGISTER_CLASSES
3552 if (REGNO (x) < FIRST_PSEUDO_REGISTER && REG_USERVAR_P (x))
3553 SET_HARD_REG_BIT (forbidden_regs, REGNO (x));
3569 if (GET_CODE (SUBREG_REG (x)) == REG
3570 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3571 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3572 = GET_MODE_SIZE (GET_MODE (x));
3576 fmt = GET_RTX_FORMAT (code);
3577 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3580 scan_paradoxical_subregs (XEXP (x, i));
3581 else if (fmt[i] == 'E')
3584 for (j = XVECLEN (x, i) - 1; j >=0; j--)
3585 scan_paradoxical_subregs (XVECEXP (x, i, j));
3591 hard_reg_use_compare (p1, p2)
3592 struct hard_reg_n_uses *p1, *p2;
3594 int tem = p1->uses - p2->uses;
3595 if (tem != 0) return tem;
3596 /* If regs are equally good, sort by regno,
3597 so that the results of qsort leave nothing to chance. */
3598 return p1->regno - p2->regno;
3601 /* Choose the order to consider regs for use as reload registers
3602 based on how much trouble would be caused by spilling one.
3603 Store them in order of decreasing preference in potential_reload_regs. */
3606 order_regs_for_reload ()
3612 struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
3614 CLEAR_HARD_REG_SET (bad_spill_regs);
3616 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3617 potential_reload_regs[i] = -1;
3619 /* Count number of uses of each hard reg by pseudo regs allocated to it
3620 and then order them by decreasing use. */
3622 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3624 hard_reg_n_uses[i].uses = 0;
3625 hard_reg_n_uses[i].regno = i;
3628 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3630 int regno = reg_renumber[i];
3633 int lim = regno + HARD_REGNO_NREGS (regno, PSEUDO_REGNO_MODE (i));
3635 hard_reg_n_uses[regno++].uses += reg_n_refs[i];
3637 large += reg_n_refs[i];
3640 /* Now fixed registers (which cannot safely be used for reloading)
3641 get a very high use count so they will be considered least desirable.
3642 Registers used explicitly in the rtl code are almost as bad. */
3644 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3648 hard_reg_n_uses[i].uses += 2 * large + 2;
3649 SET_HARD_REG_BIT (bad_spill_regs, i);
3651 else if (regs_explicitly_used[i])
3653 hard_reg_n_uses[i].uses += large + 1;
3654 #ifndef SMALL_REGISTER_CLASSES
3655 /* ??? We are doing this here because of the potential that
3656 bad code may be generated if a register explicitly used in
3657 an insn was used as a spill register for that insn. But
3658 not using these are spill registers may lose on some machine.
3659 We'll have to see how this works out. */
3660 SET_HARD_REG_BIT (bad_spill_regs, i);
3664 hard_reg_n_uses[HARD_FRAME_POINTER_REGNUM].uses += 2 * large + 2;
3665 SET_HARD_REG_BIT (bad_spill_regs, HARD_FRAME_POINTER_REGNUM);
3667 #ifdef ELIMINABLE_REGS
3668 /* If registers other than the frame pointer are eliminable, mark them as
3670 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3672 hard_reg_n_uses[reg_eliminate[i].from].uses += 2 * large + 2;
3673 SET_HARD_REG_BIT (bad_spill_regs, reg_eliminate[i].from);
3677 /* Prefer registers not so far used, for use in temporary loading.
3678 Among them, if REG_ALLOC_ORDER is defined, use that order.
3679 Otherwise, prefer registers not preserved by calls. */
3681 #ifdef REG_ALLOC_ORDER
3682 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3684 int regno = reg_alloc_order[i];
3686 if (hard_reg_n_uses[regno].uses == 0)
3687 potential_reload_regs[o++] = regno;
3690 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3692 if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i])
3693 potential_reload_regs[o++] = i;
3695 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3697 if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i])
3698 potential_reload_regs[o++] = i;
3702 qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
3703 sizeof hard_reg_n_uses[0], hard_reg_use_compare);
3705 /* Now add the regs that are already used,
3706 preferring those used less often. The fixed and otherwise forbidden
3707 registers will be at the end of this list. */
3709 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3710 if (hard_reg_n_uses[i].uses != 0)
3711 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
3714 /* Used in reload_as_needed to sort the spilled regs. */
3717 compare_spill_regs (r1, r2)
3723 /* Reload pseudo-registers into hard regs around each insn as needed.
3724 Additional register load insns are output before the insn that needs it
3725 and perhaps store insns after insns that modify the reloaded pseudo reg.
3727 reg_last_reload_reg and reg_reloaded_contents keep track of
3728 which registers are already available in reload registers.
3729 We update these for the reloads that we perform,
3730 as the insns are scanned. */
3733 reload_as_needed (first, live_known)
3743 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
3744 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
3745 reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
3746 bzero ((char *) reg_last_reload_reg, max_regno * sizeof (rtx));
3747 reg_has_output_reload = (char *) alloca (max_regno);
3748 for (i = 0; i < n_spills; i++)
3750 reg_reloaded_contents[i] = -1;
3751 reg_reloaded_insn[i] = 0;
3754 /* Reset all offsets on eliminable registers to their initial values. */
3755 #ifdef ELIMINABLE_REGS
3756 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3758 INITIAL_ELIMINATION_OFFSET (reg_eliminate[i].from, reg_eliminate[i].to,
3759 reg_eliminate[i].initial_offset);
3760 reg_eliminate[i].previous_offset
3761 = reg_eliminate[i].offset = reg_eliminate[i].initial_offset;
3764 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
3765 reg_eliminate[0].previous_offset
3766 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
3769 num_not_at_initial_offset = 0;
3771 /* Order the spilled regs, so that allocate_reload_regs can guarantee to
3772 pack registers with group needs. */
3775 qsort (spill_regs, n_spills, sizeof (short), compare_spill_regs);
3776 for (i = 0; i < n_spills; i++)
3777 spill_reg_order[spill_regs[i]] = i;
3780 for (insn = first; insn;)
3782 register rtx next = NEXT_INSN (insn);
3784 /* Notice when we move to a new basic block. */
3785 if (live_known && this_block + 1 < n_basic_blocks
3786 && insn == basic_block_head[this_block+1])
3789 /* If we pass a label, copy the offsets from the label information
3790 into the current offsets of each elimination. */
3791 if (GET_CODE (insn) == CODE_LABEL)
3793 num_not_at_initial_offset = 0;
3794 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3796 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
3797 = offsets_at[CODE_LABEL_NUMBER (insn)][i];
3798 if (reg_eliminate[i].can_eliminate
3799 && (reg_eliminate[i].offset
3800 != reg_eliminate[i].initial_offset))
3801 num_not_at_initial_offset++;
3805 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
3807 rtx avoid_return_reg = 0;
3808 rtx oldpat = PATTERN (insn);
3810 #ifdef SMALL_REGISTER_CLASSES
3811 /* Set avoid_return_reg if this is an insn
3812 that might use the value of a function call. */
3813 if (GET_CODE (insn) == CALL_INSN)
3815 if (GET_CODE (PATTERN (insn)) == SET)
3816 after_call = SET_DEST (PATTERN (insn));
3817 else if (GET_CODE (PATTERN (insn)) == PARALLEL
3818 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
3819 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
3823 else if (after_call != 0
3824 && !(GET_CODE (PATTERN (insn)) == SET
3825 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
3827 if (reg_referenced_p (after_call, PATTERN (insn)))
3828 avoid_return_reg = after_call;
3831 #endif /* SMALL_REGISTER_CLASSES */
3833 /* If this is a USE and CLOBBER of a MEM, ensure that any
3834 references to eliminable registers have been removed. */
3836 if ((GET_CODE (PATTERN (insn)) == USE
3837 || GET_CODE (PATTERN (insn)) == CLOBBER)
3838 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3839 XEXP (XEXP (PATTERN (insn), 0), 0)
3840 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3841 GET_MODE (XEXP (PATTERN (insn), 0)), NULL_RTX);
3843 /* If we need to do register elimination processing, do so.
3844 This might delete the insn, in which case we are done. */
3845 if (num_eliminable && GET_MODE (insn) == QImode)
3847 eliminate_regs_in_insn (insn, 1);
3848 if (GET_CODE (insn) == NOTE)
3855 if (GET_MODE (insn) == VOIDmode)
3857 /* First find the pseudo regs that must be reloaded for this insn.
3858 This info is returned in the tables reload_... (see reload.h).
3859 Also modify the body of INSN by substituting RELOAD
3860 rtx's for those pseudo regs. */
3863 bzero (reg_has_output_reload, max_regno);
3864 CLEAR_HARD_REG_SET (reg_is_output_reload);
3866 find_reloads (insn, 1, spill_indirect_levels, live_known,
3872 rtx prev = PREV_INSN (insn), next = NEXT_INSN (insn);
3876 /* If this block has not had spilling done for a
3877 particular clas and we have any non-optionals that need a
3878 spill reg in that class, abort. */
3880 for (class = 0; class < N_REG_CLASSES; class++)
3881 if (basic_block_needs[class] != 0
3882 && basic_block_needs[class][this_block] == 0)
3883 for (i = 0; i < n_reloads; i++)
3884 if (class == (int) reload_reg_class[i]
3885 && reload_reg_rtx[i] == 0
3886 && ! reload_optional[i]
3887 && (reload_in[i] != 0 || reload_out[i] != 0
3888 || reload_secondary_p[i] != 0))
3889 fatal_insn ("Non-optional registers need a spill register", insn);
3891 /* Now compute which reload regs to reload them into. Perhaps
3892 reusing reload regs from previous insns, or else output
3893 load insns to reload them. Maybe output store insns too.
3894 Record the choices of reload reg in reload_reg_rtx. */
3895 choose_reload_regs (insn, avoid_return_reg);
3897 #ifdef SMALL_REGISTER_CLASSES
3898 /* Merge any reloads that we didn't combine for fear of
3899 increasing the number of spill registers needed but now
3900 discover can be safely merged. */
3901 merge_assigned_reloads (insn);
3904 /* Generate the insns to reload operands into or out of
3905 their reload regs. */
3906 emit_reload_insns (insn);
3908 /* Substitute the chosen reload regs from reload_reg_rtx
3909 into the insn's body (or perhaps into the bodies of other
3910 load and store insn that we just made for reloading
3911 and that we moved the structure into). */
3914 /* If this was an ASM, make sure that all the reload insns
3915 we have generated are valid. If not, give an error
3918 if (asm_noperands (PATTERN (insn)) >= 0)
3919 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3920 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
3921 && (recog_memoized (p) < 0
3922 || (insn_extract (p),
3923 ! constrain_operands (INSN_CODE (p), 1))))
3925 error_for_asm (insn,
3926 "`asm' operand requires impossible reload");
3928 NOTE_SOURCE_FILE (p) = 0;
3929 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
3932 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3933 is no longer validly lying around to save a future reload.
3934 Note that this does not detect pseudos that were reloaded
3935 for this insn in order to be stored in
3936 (obeying register constraints). That is correct; such reload
3937 registers ARE still valid. */
3938 note_stores (oldpat, forget_old_reloads_1);
3940 /* There may have been CLOBBER insns placed after INSN. So scan
3941 between INSN and NEXT and use them to forget old reloads. */
3942 for (x = NEXT_INSN (insn); x != next; x = NEXT_INSN (x))
3943 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3944 note_stores (PATTERN (x), forget_old_reloads_1);
3947 /* Likewise for regs altered by auto-increment in this insn.
3948 But note that the reg-notes are not changed by reloading:
3949 they still contain the pseudo-regs, not the spill regs. */
3950 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3951 if (REG_NOTE_KIND (x) == REG_INC)
3953 /* See if this pseudo reg was reloaded in this insn.
3954 If so, its last-reload info is still valid
3955 because it is based on this insn's reload. */
3956 for (i = 0; i < n_reloads; i++)
3957 if (reload_out[i] == XEXP (x, 0))
3961 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX);
3965 /* A reload reg's contents are unknown after a label. */
3966 if (GET_CODE (insn) == CODE_LABEL)
3967 for (i = 0; i < n_spills; i++)
3969 reg_reloaded_contents[i] = -1;
3970 reg_reloaded_insn[i] = 0;
3973 /* Don't assume a reload reg is still good after a call insn
3974 if it is a call-used reg. */
3975 else if (GET_CODE (insn) == CALL_INSN)
3976 for (i = 0; i < n_spills; i++)
3977 if (call_used_regs[spill_regs[i]])
3979 reg_reloaded_contents[i] = -1;
3980 reg_reloaded_insn[i] = 0;
3983 /* In case registers overlap, allow certain insns to invalidate
3984 particular hard registers. */
3986 #ifdef INSN_CLOBBERS_REGNO_P
3987 for (i = 0 ; i < n_spills ; i++)
3988 if (INSN_CLOBBERS_REGNO_P (insn, spill_regs[i]))
3990 reg_reloaded_contents[i] = -1;
3991 reg_reloaded_insn[i] = 0;
4003 /* Discard all record of any value reloaded from X,
4004 or reloaded in X from someplace else;
4005 unless X is an output reload reg of the current insn.
4007 X may be a hard reg (the reload reg)
4008 or it may be a pseudo reg that was reloaded from. */
4011 forget_old_reloads_1 (x, ignored)
4019 /* note_stores does give us subregs of hard regs. */
4020 while (GET_CODE (x) == SUBREG)
4022 offset += SUBREG_WORD (x);
4026 if (GET_CODE (x) != REG)
4029 regno = REGNO (x) + offset;
4031 if (regno >= FIRST_PSEUDO_REGISTER)
4036 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4037 /* Storing into a spilled-reg invalidates its contents.
4038 This can happen if a block-local pseudo is allocated to that reg
4039 and it wasn't spilled because this block's total need is 0.
4040 Then some insn might have an optional reload and use this reg. */
4041 for (i = 0; i < nr; i++)
4042 if (spill_reg_order[regno + i] >= 0
4043 /* But don't do this if the reg actually serves as an output
4044 reload reg in the current instruction. */
4046 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i)))
4048 reg_reloaded_contents[spill_reg_order[regno + i]] = -1;
4049 reg_reloaded_insn[spill_reg_order[regno + i]] = 0;
4053 /* Since value of X has changed,
4054 forget any value previously copied from it. */
4057 /* But don't forget a copy if this is the output reload
4058 that establishes the copy's validity. */
4059 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4060 reg_last_reload_reg[regno + nr] = 0;
4063 /* For each reload, the mode of the reload register. */
4064 static enum machine_mode reload_mode[MAX_RELOADS];
4066 /* For each reload, the largest number of registers it will require. */
4067 static int reload_nregs[MAX_RELOADS];
4069 /* Comparison function for qsort to decide which of two reloads
4070 should be handled first. *P1 and *P2 are the reload numbers. */
4073 reload_reg_class_lower (p1, p2)
4076 register int r1 = *p1, r2 = *p2;
4079 /* Consider required reloads before optional ones. */
4080 t = reload_optional[r1] - reload_optional[r2];
4084 /* Count all solitary classes before non-solitary ones. */
4085 t = ((reg_class_size[(int) reload_reg_class[r2]] == 1)
4086 - (reg_class_size[(int) reload_reg_class[r1]] == 1));
4090 /* Aside from solitaires, consider all multi-reg groups first. */
4091 t = reload_nregs[r2] - reload_nregs[r1];
4095 /* Consider reloads in order of increasing reg-class number. */
4096 t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2];
4100 /* If reloads are equally urgent, sort by reload number,
4101 so that the results of qsort leave nothing to chance. */
4105 /* The following HARD_REG_SETs indicate when each hard register is
4106 used for a reload of various parts of the current insn. */
4108 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4109 static HARD_REG_SET reload_reg_used;
4110 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4111 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4112 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4113 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4114 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4115 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4116 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4117 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4118 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4119 static HARD_REG_SET reload_reg_used_in_op_addr;
4120 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4121 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4122 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4123 static HARD_REG_SET reload_reg_used_in_insn;
4124 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4125 static HARD_REG_SET reload_reg_used_in_other_addr;
4127 /* If reg is in use as a reload reg for any sort of reload. */
4128 static HARD_REG_SET reload_reg_used_at_all;
4130 /* If reg is use as an inherited reload. We just mark the first register
4132 static HARD_REG_SET reload_reg_used_for_inherit;
4134 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4135 TYPE. MODE is used to indicate how many consecutive regs are
4139 mark_reload_reg_in_use (regno, opnum, type, mode)
4142 enum reload_type type;
4143 enum machine_mode mode;
4145 int nregs = HARD_REGNO_NREGS (regno, mode);
4148 for (i = regno; i < nregs + regno; i++)
4153 SET_HARD_REG_BIT (reload_reg_used, i);
4156 case RELOAD_FOR_INPUT_ADDRESS:
4157 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4160 case RELOAD_FOR_OUTPUT_ADDRESS:
4161 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4164 case RELOAD_FOR_OPERAND_ADDRESS:
4165 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4168 case RELOAD_FOR_OPADDR_ADDR:
4169 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4172 case RELOAD_FOR_OTHER_ADDRESS:
4173 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4176 case RELOAD_FOR_INPUT:
4177 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4180 case RELOAD_FOR_OUTPUT:
4181 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4184 case RELOAD_FOR_INSN:
4185 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4189 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4193 /* Similarly, but show REGNO is no longer in use for a reload. */
4196 clear_reload_reg_in_use (regno, opnum, type, mode)
4199 enum reload_type type;
4200 enum machine_mode mode;
4202 int nregs = HARD_REGNO_NREGS (regno, mode);
4205 for (i = regno; i < nregs + regno; i++)
4210 CLEAR_HARD_REG_BIT (reload_reg_used, i);
4213 case RELOAD_FOR_INPUT_ADDRESS:
4214 CLEAR_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4217 case RELOAD_FOR_OUTPUT_ADDRESS:
4218 CLEAR_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4221 case RELOAD_FOR_OPERAND_ADDRESS:
4222 CLEAR_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4225 case RELOAD_FOR_OPADDR_ADDR:
4226 CLEAR_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4229 case RELOAD_FOR_OTHER_ADDRESS:
4230 CLEAR_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4233 case RELOAD_FOR_INPUT:
4234 CLEAR_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4237 case RELOAD_FOR_OUTPUT:
4238 CLEAR_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4241 case RELOAD_FOR_INSN:
4242 CLEAR_HARD_REG_BIT (reload_reg_used_in_insn, i);
4248 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4249 specified by OPNUM and TYPE. */
4252 reload_reg_free_p (regno, opnum, type)
4255 enum reload_type type;
4259 /* In use for a RELOAD_OTHER means it's not available for anything except
4260 RELOAD_FOR_OTHER_ADDRESS. Recall that RELOAD_FOR_OTHER_ADDRESS is known
4261 to be used only for inputs. */
4263 if (type != RELOAD_FOR_OTHER_ADDRESS
4264 && TEST_HARD_REG_BIT (reload_reg_used, regno))
4270 /* In use for anything except RELOAD_FOR_OTHER_ADDRESS means
4271 we can't use it for RELOAD_OTHER. */
4272 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4273 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4274 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4277 for (i = 0; i < reload_n_operands; i++)
4278 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4279 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4280 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4281 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4286 case RELOAD_FOR_INPUT:
4287 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4288 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4291 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4294 /* If it is used for some other input, can't use it. */
4295 for (i = 0; i < reload_n_operands; i++)
4296 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4299 /* If it is used in a later operand's address, can't use it. */
4300 for (i = opnum + 1; i < reload_n_operands; i++)
4301 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4306 case RELOAD_FOR_INPUT_ADDRESS:
4307 /* Can't use a register if it is used for an input address for this
4308 operand or used as an input in an earlier one. */
4309 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno))
4312 for (i = 0; i < opnum; i++)
4313 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4318 case RELOAD_FOR_OUTPUT_ADDRESS:
4319 /* Can't use a register if it is used for an output address for this
4320 operand or used as an output in this or a later operand. */
4321 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4324 for (i = opnum; i < reload_n_operands; i++)
4325 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4330 case RELOAD_FOR_OPERAND_ADDRESS:
4331 for (i = 0; i < reload_n_operands; i++)
4332 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4335 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4336 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4338 case RELOAD_FOR_OPADDR_ADDR:
4339 for (i = 0; i < reload_n_operands; i++)
4340 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4343 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4345 case RELOAD_FOR_OUTPUT:
4346 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4347 outputs, or an operand address for this or an earlier output. */
4348 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4351 for (i = 0; i < reload_n_operands; i++)
4352 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4355 for (i = 0; i <= opnum; i++)
4356 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno))
4361 case RELOAD_FOR_INSN:
4362 for (i = 0; i < reload_n_operands; i++)
4363 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4364 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4367 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4368 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4370 case RELOAD_FOR_OTHER_ADDRESS:
4371 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4376 /* Return 1 if the value in reload reg REGNO, as used by a reload
4377 needed for the part of the insn specified by OPNUM and TYPE,
4378 is not in use for a reload in any prior part of the insn.
4380 We can assume that the reload reg was already tested for availability
4381 at the time it is needed, and we should not check this again,
4382 in case the reg has already been marked in use. */
4385 reload_reg_free_before_p (regno, opnum, type)
4388 enum reload_type type;
4394 case RELOAD_FOR_OTHER_ADDRESS:
4395 /* These always come first. */
4399 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4401 /* If this use is for part of the insn,
4402 check the reg is not in use for any prior part. It is tempting
4403 to try to do this by falling through from objecs that occur
4404 later in the insn to ones that occur earlier, but that will not
4405 correctly take into account the fact that here we MUST ignore
4406 things that would prevent the register from being allocated in
4407 the first place, since we know that it was allocated. */
4409 case RELOAD_FOR_OUTPUT_ADDRESS:
4410 /* Earlier reloads are for earlier outputs or their addresses,
4411 any RELOAD_FOR_INSN reloads, any inputs or their addresses, or any
4412 RELOAD_FOR_OTHER_ADDRESS reloads (we know it can't conflict with
4414 for (i = 0; i < opnum; i++)
4415 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4416 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4419 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4422 for (i = 0; i < reload_n_operands; i++)
4423 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4424 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4427 return (! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4428 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4429 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4431 case RELOAD_FOR_OUTPUT:
4432 /* This can't be used in the output address for this operand and
4433 anything that can't be used for it, except that we've already
4434 tested for RELOAD_FOR_INSN objects. */
4436 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4439 for (i = 0; i < opnum; i++)
4440 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4441 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4444 for (i = 0; i < reload_n_operands; i++)
4445 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4446 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4447 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4450 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4452 case RELOAD_FOR_OPERAND_ADDRESS:
4453 case RELOAD_FOR_OPADDR_ADDR:
4454 case RELOAD_FOR_INSN:
4455 /* These can't conflict with inputs, or each other, so all we have to
4456 test is input addresses and the addresses of OTHER items. */
4458 for (i = 0; i < reload_n_operands; i++)
4459 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4462 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4464 case RELOAD_FOR_INPUT:
4465 /* The only things earlier are the address for this and
4466 earlier inputs, other inputs (which we know we don't conflict
4467 with), and addresses of RELOAD_OTHER objects. */
4469 for (i = 0; i <= opnum; i++)
4470 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4473 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4475 case RELOAD_FOR_INPUT_ADDRESS:
4476 /* Similarly, all we have to check is for use in earlier inputs'
4478 for (i = 0; i < opnum; i++)
4479 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4482 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4487 /* Return 1 if the value in reload reg REGNO, as used by a reload
4488 needed for the part of the insn specified by OPNUM and TYPE,
4489 is still available in REGNO at the end of the insn.
4491 We can assume that the reload reg was already tested for availability
4492 at the time it is needed, and we should not check this again,
4493 in case the reg has already been marked in use. */
4496 reload_reg_reaches_end_p (regno, opnum, type)
4499 enum reload_type type;
4506 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4507 its value must reach the end. */
4510 /* If this use is for part of the insn,
4511 its value reaches if no subsequent part uses the same register.
4512 Just like the above function, don't try to do this with lots
4515 case RELOAD_FOR_OTHER_ADDRESS:
4516 /* Here we check for everything else, since these don't conflict
4517 with anything else and everything comes later. */
4519 for (i = 0; i < reload_n_operands; i++)
4520 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4521 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4522 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4523 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4526 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4527 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4528 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4530 case RELOAD_FOR_INPUT_ADDRESS:
4531 /* Similar, except that we check only for this and subsequent inputs
4532 and the address of only subsequent inputs and we do not need
4533 to check for RELOAD_OTHER objects since they are known not to
4536 for (i = opnum; i < reload_n_operands; i++)
4537 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4540 for (i = opnum + 1; i < reload_n_operands; i++)
4541 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4544 for (i = 0; i < reload_n_operands; i++)
4545 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4546 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4549 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4552 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4553 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4555 case RELOAD_FOR_INPUT:
4556 /* Similar to input address, except we start at the next operand for
4557 both input and input address and we do not check for
4558 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4561 for (i = opnum + 1; i < reload_n_operands; i++)
4562 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4563 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4566 /* ... fall through ... */
4568 case RELOAD_FOR_OPERAND_ADDRESS:
4569 /* Check outputs and their addresses. */
4571 for (i = 0; i < reload_n_operands; i++)
4572 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4573 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4578 case RELOAD_FOR_OPADDR_ADDR:
4579 for (i = 0; i < reload_n_operands; i++)
4580 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4581 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4584 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4585 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4587 case RELOAD_FOR_INSN:
4588 /* These conflict with other outputs with RELOAD_OTHER. So
4589 we need only check for output addresses. */
4593 /* ... fall through ... */
4595 case RELOAD_FOR_OUTPUT:
4596 case RELOAD_FOR_OUTPUT_ADDRESS:
4597 /* We already know these can't conflict with a later output. So the
4598 only thing to check are later output addresses. */
4599 for (i = opnum + 1; i < reload_n_operands; i++)
4600 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno))
4609 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4612 This function uses the same algorithm as reload_reg_free_p above. */
4615 reloads_conflict (r1, r2)
4618 enum reload_type r1_type = reload_when_needed[r1];
4619 enum reload_type r2_type = reload_when_needed[r2];
4620 int r1_opnum = reload_opnum[r1];
4621 int r2_opnum = reload_opnum[r2];
4623 /* RELOAD_OTHER conflicts with everything except RELOAD_FOR_OTHER_ADDRESS. */
4625 if (r2_type == RELOAD_OTHER && r1_type != RELOAD_FOR_OTHER_ADDRESS)
4628 /* Otherwise, check conflicts differently for each type. */
4632 case RELOAD_FOR_INPUT:
4633 return (r2_type == RELOAD_FOR_INSN
4634 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4635 || r2_type == RELOAD_FOR_OPADDR_ADDR
4636 || r2_type == RELOAD_FOR_INPUT
4637 || (r2_type == RELOAD_FOR_INPUT_ADDRESS && r2_opnum > r1_opnum));
4639 case RELOAD_FOR_INPUT_ADDRESS:
4640 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4641 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4643 case RELOAD_FOR_OUTPUT_ADDRESS:
4644 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4645 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4647 case RELOAD_FOR_OPERAND_ADDRESS:
4648 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4649 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4651 case RELOAD_FOR_OPADDR_ADDR:
4652 return (r2_type == RELOAD_FOR_INPUT
4653 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4655 case RELOAD_FOR_OUTPUT:
4656 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4657 || (r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4658 && r2_opnum >= r1_opnum));
4660 case RELOAD_FOR_INSN:
4661 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4662 || r2_type == RELOAD_FOR_INSN
4663 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4665 case RELOAD_FOR_OTHER_ADDRESS:
4666 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4669 return r2_type != RELOAD_FOR_OTHER_ADDRESS;
4676 /* Vector of reload-numbers showing the order in which the reloads should
4678 short reload_order[MAX_RELOADS];
4680 /* Indexed by reload number, 1 if incoming value
4681 inherited from previous insns. */
4682 char reload_inherited[MAX_RELOADS];
4684 /* For an inherited reload, this is the insn the reload was inherited from,
4685 if we know it. Otherwise, this is 0. */
4686 rtx reload_inheritance_insn[MAX_RELOADS];
4688 /* If non-zero, this is a place to get the value of the reload,
4689 rather than using reload_in. */
4690 rtx reload_override_in[MAX_RELOADS];
4692 /* For each reload, the index in spill_regs of the spill register used,
4693 or -1 if we did not need one of the spill registers for this reload. */
4694 int reload_spill_index[MAX_RELOADS];
4696 /* Find a spill register to use as a reload register for reload R.
4697 LAST_RELOAD is non-zero if this is the last reload for the insn being
4700 Set reload_reg_rtx[R] to the register allocated.
4702 If NOERROR is nonzero, we return 1 if successful,
4703 or 0 if we couldn't find a spill reg and we didn't change anything. */
4706 allocate_reload_reg (r, insn, last_reload, noerror)
4718 /* If we put this reload ahead, thinking it is a group,
4719 then insist on finding a group. Otherwise we can grab a
4720 reg that some other reload needs.
4721 (That can happen when we have a 68000 DATA_OR_FP_REG
4722 which is a group of data regs or one fp reg.)
4723 We need not be so restrictive if there are no more reloads
4726 ??? Really it would be nicer to have smarter handling
4727 for that kind of reg class, where a problem like this is normal.
4728 Perhaps those classes should be avoided for reloading
4729 by use of more alternatives. */
4731 int force_group = reload_nregs[r] > 1 && ! last_reload;
4733 /* If we want a single register and haven't yet found one,
4734 take any reg in the right class and not in use.
4735 If we want a consecutive group, here is where we look for it.
4737 We use two passes so we can first look for reload regs to
4738 reuse, which are already in use for other reloads in this insn,
4739 and only then use additional registers.
4740 I think that maximizing reuse is needed to make sure we don't
4741 run out of reload regs. Suppose we have three reloads, and
4742 reloads A and B can share regs. These need two regs.
4743 Suppose A and B are given different regs.
4744 That leaves none for C. */
4745 for (pass = 0; pass < 2; pass++)
4747 /* I is the index in spill_regs.
4748 We advance it round-robin between insns to use all spill regs
4749 equally, so that inherited reloads have a chance
4750 of leapfrogging each other. Don't do this, however, when we have
4751 group needs and failure would be fatal; if we only have a relatively
4752 small number of spill registers, and more than one of them has
4753 group needs, then by starting in the middle, we may end up
4754 allocating the first one in such a way that we are not left with
4755 sufficient groups to handle the rest. */
4757 if (noerror || ! force_group)
4762 for (count = 0; count < n_spills; count++)
4764 int class = (int) reload_reg_class[r];
4766 i = (i + 1) % n_spills;
4768 if (reload_reg_free_p (spill_regs[i], reload_opnum[r],
4769 reload_when_needed[r])
4770 && TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i])
4771 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
4772 /* Look first for regs to share, then for unshared. But
4773 don't share regs used for inherited reloads; they are
4774 the ones we want to preserve. */
4776 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
4778 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
4781 int nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
4782 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
4783 (on 68000) got us two FP regs. If NR is 1,
4784 we would reject both of them. */
4786 nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]);
4787 /* If we need only one reg, we have already won. */
4790 /* But reject a single reg if we demand a group. */
4795 /* Otherwise check that as many consecutive regs as we need
4797 Also, don't use for a group registers that are
4798 needed for nongroups. */
4799 if (! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
4802 regno = spill_regs[i] + nr - 1;
4803 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
4804 && spill_reg_order[regno] >= 0
4805 && reload_reg_free_p (regno, reload_opnum[r],
4806 reload_when_needed[r])
4807 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
4817 /* If we found something on pass 1, omit pass 2. */
4818 if (count < n_spills)
4822 /* We should have found a spill register by now. */
4823 if (count == n_spills)
4830 /* I is the index in SPILL_REG_RTX of the reload register we are to
4831 allocate. Get an rtx for it and find its register number. */
4833 new = spill_reg_rtx[i];
4835 if (new == 0 || GET_MODE (new) != reload_mode[r])
4836 spill_reg_rtx[i] = new
4837 = gen_rtx (REG, reload_mode[r], spill_regs[i]);
4839 regno = true_regnum (new);
4841 /* Detect when the reload reg can't hold the reload mode.
4842 This used to be one `if', but Sequent compiler can't handle that. */
4843 if (HARD_REGNO_MODE_OK (regno, reload_mode[r]))
4845 enum machine_mode test_mode = VOIDmode;
4847 test_mode = GET_MODE (reload_in[r]);
4848 /* If reload_in[r] has VOIDmode, it means we will load it
4849 in whatever mode the reload reg has: to wit, reload_mode[r].
4850 We have already tested that for validity. */
4851 /* Aside from that, we need to test that the expressions
4852 to reload from or into have modes which are valid for this
4853 reload register. Otherwise the reload insns would be invalid. */
4854 if (! (reload_in[r] != 0 && test_mode != VOIDmode
4855 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
4856 if (! (reload_out[r] != 0
4857 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r]))))
4859 /* The reg is OK. */
4862 /* Mark as in use for this insn the reload regs we use
4864 mark_reload_reg_in_use (spill_regs[i], reload_opnum[r],
4865 reload_when_needed[r], reload_mode[r]);
4867 reload_reg_rtx[r] = new;
4868 reload_spill_index[r] = i;
4873 /* The reg is not OK. */
4878 if (asm_noperands (PATTERN (insn)) < 0)
4879 /* It's the compiler's fault. */
4880 fatal_insn ("Could not find a spill register", insn);
4882 /* It's the user's fault; the operand's mode and constraint
4883 don't match. Disable this reload so we don't crash in final. */
4884 error_for_asm (insn,
4885 "`asm' operand constraint incompatible with operand size");
4888 reload_reg_rtx[r] = 0;
4889 reload_optional[r] = 1;
4890 reload_secondary_p[r] = 1;
4895 /* Assign hard reg targets for the pseudo-registers we must reload
4896 into hard regs for this insn.
4897 Also output the instructions to copy them in and out of the hard regs.
4899 For machines with register classes, we are responsible for
4900 finding a reload reg in the proper class. */
4903 choose_reload_regs (insn, avoid_return_reg)
4905 rtx avoid_return_reg;
4908 int max_group_size = 1;
4909 enum reg_class group_class = NO_REGS;
4912 rtx save_reload_reg_rtx[MAX_RELOADS];
4913 char save_reload_inherited[MAX_RELOADS];
4914 rtx save_reload_inheritance_insn[MAX_RELOADS];
4915 rtx save_reload_override_in[MAX_RELOADS];
4916 int save_reload_spill_index[MAX_RELOADS];
4917 HARD_REG_SET save_reload_reg_used;
4918 HARD_REG_SET save_reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4919 HARD_REG_SET save_reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4920 HARD_REG_SET save_reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4921 HARD_REG_SET save_reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4922 HARD_REG_SET save_reload_reg_used_in_op_addr;
4923 HARD_REG_SET save_reload_reg_used_in_op_addr_reload;
4924 HARD_REG_SET save_reload_reg_used_in_insn;
4925 HARD_REG_SET save_reload_reg_used_in_other_addr;
4926 HARD_REG_SET save_reload_reg_used_at_all;
4928 bzero (reload_inherited, MAX_RELOADS);
4929 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
4930 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
4932 CLEAR_HARD_REG_SET (reload_reg_used);
4933 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
4934 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
4935 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
4936 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
4937 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
4939 for (i = 0; i < reload_n_operands; i++)
4941 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
4942 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
4943 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
4944 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
4947 #ifdef SMALL_REGISTER_CLASSES
4948 /* Don't bother with avoiding the return reg
4949 if we have no mandatory reload that could use it. */
4950 if (avoid_return_reg)
4953 int regno = REGNO (avoid_return_reg);
4955 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
4958 for (r = regno; r < regno + nregs; r++)
4959 if (spill_reg_order[r] >= 0)
4960 for (j = 0; j < n_reloads; j++)
4961 if (!reload_optional[j] && reload_reg_rtx[j] == 0
4962 && (reload_in[j] != 0 || reload_out[j] != 0
4963 || reload_secondary_p[j])
4965 TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[j]], r))
4968 avoid_return_reg = 0;
4970 #endif /* SMALL_REGISTER_CLASSES */
4972 #if 0 /* Not needed, now that we can always retry without inheritance. */
4973 /* See if we have more mandatory reloads than spill regs.
4974 If so, then we cannot risk optimizations that could prevent
4975 reloads from sharing one spill register.
4977 Since we will try finding a better register than reload_reg_rtx
4978 unless it is equal to reload_in or reload_out, count such reloads. */
4982 #ifdef SMALL_REGISTER_CLASSES
4983 int tem = (avoid_return_reg != 0);
4985 for (j = 0; j < n_reloads; j++)
4986 if (! reload_optional[j]
4987 && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j])
4988 && (reload_reg_rtx[j] == 0
4989 || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j])
4990 && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j]))))
4997 #ifdef SMALL_REGISTER_CLASSES
4998 /* Don't use the subroutine call return reg for a reload
4999 if we are supposed to avoid it. */
5000 if (avoid_return_reg)
5002 int regno = REGNO (avoid_return_reg);
5004 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
5007 for (r = regno; r < regno + nregs; r++)
5008 if (spill_reg_order[r] >= 0)
5009 SET_HARD_REG_BIT (reload_reg_used, r);
5011 #endif /* SMALL_REGISTER_CLASSES */
5013 /* In order to be certain of getting the registers we need,
5014 we must sort the reloads into order of increasing register class.
5015 Then our grabbing of reload registers will parallel the process
5016 that provided the reload registers.
5018 Also note whether any of the reloads wants a consecutive group of regs.
5019 If so, record the maximum size of the group desired and what
5020 register class contains all the groups needed by this insn. */
5022 for (j = 0; j < n_reloads; j++)
5024 reload_order[j] = j;
5025 reload_spill_index[j] = -1;
5028 = (reload_inmode[j] == VOIDmode
5029 || (GET_MODE_SIZE (reload_outmode[j])
5030 > GET_MODE_SIZE (reload_inmode[j])))
5031 ? reload_outmode[j] : reload_inmode[j];
5033 reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]);
5035 if (reload_nregs[j] > 1)
5037 max_group_size = MAX (reload_nregs[j], max_group_size);
5038 group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class];
5041 /* If we have already decided to use a certain register,
5042 don't use it in another way. */
5043 if (reload_reg_rtx[j])
5044 mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]), reload_opnum[j],
5045 reload_when_needed[j], reload_mode[j]);
5049 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5051 bcopy ((char *) reload_reg_rtx, (char *) save_reload_reg_rtx,
5052 sizeof reload_reg_rtx);
5053 bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited);
5054 bcopy ((char *) reload_inheritance_insn,
5055 (char *) save_reload_inheritance_insn,
5056 sizeof reload_inheritance_insn);
5057 bcopy ((char *) reload_override_in, (char *) save_reload_override_in,
5058 sizeof reload_override_in);
5059 bcopy ((char *) reload_spill_index, (char *) save_reload_spill_index,
5060 sizeof reload_spill_index);
5061 COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used);
5062 COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all);
5063 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr,
5064 reload_reg_used_in_op_addr);
5066 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr_reload,
5067 reload_reg_used_in_op_addr_reload);
5069 COPY_HARD_REG_SET (save_reload_reg_used_in_insn,
5070 reload_reg_used_in_insn);
5071 COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr,
5072 reload_reg_used_in_other_addr);
5074 for (i = 0; i < reload_n_operands; i++)
5076 COPY_HARD_REG_SET (save_reload_reg_used_in_output[i],
5077 reload_reg_used_in_output[i]);
5078 COPY_HARD_REG_SET (save_reload_reg_used_in_input[i],
5079 reload_reg_used_in_input[i]);
5080 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr[i],
5081 reload_reg_used_in_input_addr[i]);
5082 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr[i],
5083 reload_reg_used_in_output_addr[i]);
5086 /* If -O, try first with inheritance, then turning it off.
5087 If not -O, don't do inheritance.
5088 Using inheritance when not optimizing leads to paradoxes
5089 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5090 because one side of the comparison might be inherited. */
5092 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5094 /* Process the reloads in order of preference just found.
5095 Beyond this point, subregs can be found in reload_reg_rtx.
5097 This used to look for an existing reloaded home for all
5098 of the reloads, and only then perform any new reloads.
5099 But that could lose if the reloads were done out of reg-class order
5100 because a later reload with a looser constraint might have an old
5101 home in a register needed by an earlier reload with a tighter constraint.
5103 To solve this, we make two passes over the reloads, in the order
5104 described above. In the first pass we try to inherit a reload
5105 from a previous insn. If there is a later reload that needs a
5106 class that is a proper subset of the class being processed, we must
5107 also allocate a spill register during the first pass.
5109 Then make a second pass over the reloads to allocate any reloads
5110 that haven't been given registers yet. */
5112 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5114 for (j = 0; j < n_reloads; j++)
5116 register int r = reload_order[j];
5118 /* Ignore reloads that got marked inoperative. */
5119 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
5122 /* If find_reloads chose a to use reload_in or reload_out as a reload
5123 register, we don't need to chose one. Otherwise, try even if it found
5124 one since we might save an insn if we find the value lying around. */
5125 if (reload_in[r] != 0 && reload_reg_rtx[r] != 0
5126 && (rtx_equal_p (reload_in[r], reload_reg_rtx[r])
5127 || rtx_equal_p (reload_out[r], reload_reg_rtx[r])))
5130 #if 0 /* No longer needed for correct operation.
5131 It might give better code, or might not; worth an experiment? */
5132 /* If this is an optional reload, we can't inherit from earlier insns
5133 until we are sure that any non-optional reloads have been allocated.
5134 The following code takes advantage of the fact that optional reloads
5135 are at the end of reload_order. */
5136 if (reload_optional[r] != 0)
5137 for (i = 0; i < j; i++)
5138 if ((reload_out[reload_order[i]] != 0
5139 || reload_in[reload_order[i]] != 0
5140 || reload_secondary_p[reload_order[i]])
5141 && ! reload_optional[reload_order[i]]
5142 && reload_reg_rtx[reload_order[i]] == 0)
5143 allocate_reload_reg (reload_order[i], insn, 0, inheritance);
5146 /* First see if this pseudo is already available as reloaded
5147 for a previous insn. We cannot try to inherit for reloads
5148 that are smaller than the maximum number of registers needed
5149 for groups unless the register we would allocate cannot be used
5152 We could check here to see if this is a secondary reload for
5153 an object that is already in a register of the desired class.
5154 This would avoid the need for the secondary reload register.
5155 But this is complex because we can't easily determine what
5156 objects might want to be loaded via this reload. So let a register
5157 be allocated here. In `emit_reload_insns' we suppress one of the
5158 loads in the case described above. */
5162 register int regno = -1;
5163 enum machine_mode mode;
5165 if (reload_in[r] == 0)
5167 else if (GET_CODE (reload_in[r]) == REG)
5169 regno = REGNO (reload_in[r]);
5170 mode = GET_MODE (reload_in[r]);
5172 else if (GET_CODE (reload_in_reg[r]) == REG)
5174 regno = REGNO (reload_in_reg[r]);
5175 mode = GET_MODE (reload_in_reg[r]);
5178 /* This won't work, since REGNO can be a pseudo reg number.
5179 Also, it takes much more hair to keep track of all the things
5180 that can invalidate an inherited reload of part of a pseudoreg. */
5181 else if (GET_CODE (reload_in[r]) == SUBREG
5182 && GET_CODE (SUBREG_REG (reload_in[r])) == REG)
5183 regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]);
5186 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5188 i = spill_reg_order[REGNO (reg_last_reload_reg[regno])];
5190 if (reg_reloaded_contents[i] == regno
5191 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno]))
5192 >= GET_MODE_SIZE (mode))
5193 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
5194 && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5196 && (reload_nregs[r] == max_group_size
5197 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5199 && reload_reg_free_p (spill_regs[i], reload_opnum[r],
5200 reload_when_needed[r])
5201 && reload_reg_free_before_p (spill_regs[i],
5203 reload_when_needed[r]))
5205 /* If a group is needed, verify that all the subsequent
5206 registers still have their values intact. */
5208 = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
5211 for (k = 1; k < nr; k++)
5212 if (reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
5220 /* We found a register that contains the
5221 value we need. If this register is the
5222 same as an `earlyclobber' operand of the
5223 current insn, just mark it as a place to
5224 reload from since we can't use it as the
5225 reload register itself. */
5227 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5228 if (reg_overlap_mentioned_for_reload_p
5229 (reg_last_reload_reg[regno],
5230 reload_earlyclobbers[i1]))
5233 if (i1 != n_earlyclobbers
5234 /* Don't really use the inherited spill reg
5235 if we need it wider than we've got it. */
5236 || (GET_MODE_SIZE (reload_mode[r])
5237 > GET_MODE_SIZE (mode)))
5238 reload_override_in[r] = reg_last_reload_reg[regno];
5242 /* We can use this as a reload reg. */
5243 /* Mark the register as in use for this part of
5245 mark_reload_reg_in_use (spill_regs[i],
5247 reload_when_needed[r],
5249 reload_reg_rtx[r] = reg_last_reload_reg[regno];
5250 reload_inherited[r] = 1;
5251 reload_inheritance_insn[r]
5252 = reg_reloaded_insn[i];
5253 reload_spill_index[r] = i;
5254 for (k = 0; k < nr; k++)
5255 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5263 /* Here's another way to see if the value is already lying around. */
5265 && reload_in[r] != 0
5266 && ! reload_inherited[r]
5267 && reload_out[r] == 0
5268 && (CONSTANT_P (reload_in[r])
5269 || GET_CODE (reload_in[r]) == PLUS
5270 || GET_CODE (reload_in[r]) == REG
5271 || GET_CODE (reload_in[r]) == MEM)
5272 && (reload_nregs[r] == max_group_size
5273 || ! reg_classes_intersect_p (reload_reg_class[r], group_class)))
5276 = find_equiv_reg (reload_in[r], insn, reload_reg_class[r],
5277 -1, NULL_PTR, 0, reload_mode[r]);
5282 if (GET_CODE (equiv) == REG)
5283 regno = REGNO (equiv);
5284 else if (GET_CODE (equiv) == SUBREG)
5286 /* This must be a SUBREG of a hard register.
5287 Make a new REG since this might be used in an
5288 address and not all machines support SUBREGs
5290 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
5291 equiv = gen_rtx (REG, reload_mode[r], regno);
5297 /* If we found a spill reg, reject it unless it is free
5298 and of the desired class. */
5300 && ((spill_reg_order[regno] >= 0
5301 && ! reload_reg_free_before_p (regno, reload_opnum[r],
5302 reload_when_needed[r]))
5303 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5307 if (equiv != 0 && TEST_HARD_REG_BIT (reload_reg_used_at_all, regno))
5310 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5313 /* We found a register that contains the value we need.
5314 If this register is the same as an `earlyclobber' operand
5315 of the current insn, just mark it as a place to reload from
5316 since we can't use it as the reload register itself. */
5319 for (i = 0; i < n_earlyclobbers; i++)
5320 if (reg_overlap_mentioned_for_reload_p (equiv,
5321 reload_earlyclobbers[i]))
5323 reload_override_in[r] = equiv;
5328 /* JRV: If the equiv register we have found is explicitly
5329 clobbered in the current insn, mark but don't use, as above. */
5331 if (equiv != 0 && regno_clobbered_p (regno, insn))
5333 reload_override_in[r] = equiv;
5337 /* If we found an equivalent reg, say no code need be generated
5338 to load it, and use it as our reload reg. */
5339 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5341 reload_reg_rtx[r] = equiv;
5342 reload_inherited[r] = 1;
5343 /* If it is a spill reg,
5344 mark the spill reg as in use for this insn. */
5345 i = spill_reg_order[regno];
5348 int nr = HARD_REGNO_NREGS (regno, reload_mode[r]);
5350 mark_reload_reg_in_use (regno, reload_opnum[r],
5351 reload_when_needed[r],
5353 for (k = 0; k < nr; k++)
5354 SET_HARD_REG_BIT (reload_reg_used_for_inherit, regno + k);
5359 /* If we found a register to use already, or if this is an optional
5360 reload, we are done. */
5361 if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0)
5364 #if 0 /* No longer needed for correct operation. Might or might not
5365 give better code on the average. Want to experiment? */
5367 /* See if there is a later reload that has a class different from our
5368 class that intersects our class or that requires less register
5369 than our reload. If so, we must allocate a register to this
5370 reload now, since that reload might inherit a previous reload
5371 and take the only available register in our class. Don't do this
5372 for optional reloads since they will force all previous reloads
5373 to be allocated. Also don't do this for reloads that have been
5376 for (i = j + 1; i < n_reloads; i++)
5378 int s = reload_order[i];
5380 if ((reload_in[s] == 0 && reload_out[s] == 0
5381 && ! reload_secondary_p[s])
5382 || reload_optional[s])
5385 if ((reload_reg_class[s] != reload_reg_class[r]
5386 && reg_classes_intersect_p (reload_reg_class[r],
5387 reload_reg_class[s]))
5388 || reload_nregs[s] < reload_nregs[r])
5395 allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance);
5399 /* Now allocate reload registers for anything non-optional that
5400 didn't get one yet. */
5401 for (j = 0; j < n_reloads; j++)
5403 register int r = reload_order[j];
5405 /* Ignore reloads that got marked inoperative. */
5406 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
5409 /* Skip reloads that already have a register allocated or are
5411 if (reload_reg_rtx[r] != 0 || reload_optional[r])
5414 if (! allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance))
5418 /* If that loop got all the way, we have won. */
5423 /* Loop around and try without any inheritance. */
5424 /* First undo everything done by the failed attempt
5425 to allocate with inheritance. */
5426 bcopy ((char *) save_reload_reg_rtx, (char *) reload_reg_rtx,
5427 sizeof reload_reg_rtx);
5428 bcopy ((char *) save_reload_inherited, (char *) reload_inherited,
5429 sizeof reload_inherited);
5430 bcopy ((char *) save_reload_inheritance_insn,
5431 (char *) reload_inheritance_insn,
5432 sizeof reload_inheritance_insn);
5433 bcopy ((char *) save_reload_override_in, (char *) reload_override_in,
5434 sizeof reload_override_in);
5435 bcopy ((char *) save_reload_spill_index, (char *) reload_spill_index,
5436 sizeof reload_spill_index);
5437 COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used);
5438 COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all);
5439 COPY_HARD_REG_SET (reload_reg_used_in_op_addr,
5440 save_reload_reg_used_in_op_addr);
5441 COPY_HARD_REG_SET (reload_reg_used_in_op_addr_reload,
5442 save_reload_reg_used_in_op_addr_reload);
5443 COPY_HARD_REG_SET (reload_reg_used_in_insn,
5444 save_reload_reg_used_in_insn);
5445 COPY_HARD_REG_SET (reload_reg_used_in_other_addr,
5446 save_reload_reg_used_in_other_addr);
5448 for (i = 0; i < reload_n_operands; i++)
5450 COPY_HARD_REG_SET (reload_reg_used_in_input[i],
5451 save_reload_reg_used_in_input[i]);
5452 COPY_HARD_REG_SET (reload_reg_used_in_output[i],
5453 save_reload_reg_used_in_output[i]);
5454 COPY_HARD_REG_SET (reload_reg_used_in_input_addr[i],
5455 save_reload_reg_used_in_input_addr[i]);
5456 COPY_HARD_REG_SET (reload_reg_used_in_output_addr[i],
5457 save_reload_reg_used_in_output_addr[i]);
5461 /* If we thought we could inherit a reload, because it seemed that
5462 nothing else wanted the same reload register earlier in the insn,
5463 verify that assumption, now that all reloads have been assigned. */
5465 for (j = 0; j < n_reloads; j++)
5467 register int r = reload_order[j];
5469 if (reload_inherited[r] && reload_reg_rtx[r] != 0
5470 && ! reload_reg_free_before_p (true_regnum (reload_reg_rtx[r]),
5472 reload_when_needed[r]))
5473 reload_inherited[r] = 0;
5475 /* If we found a better place to reload from,
5476 validate it in the same fashion, if it is a reload reg. */
5477 if (reload_override_in[r]
5478 && (GET_CODE (reload_override_in[r]) == REG
5479 || GET_CODE (reload_override_in[r]) == SUBREG))
5481 int regno = true_regnum (reload_override_in[r]);
5482 if (spill_reg_order[regno] >= 0
5483 && ! reload_reg_free_before_p (regno, reload_opnum[r],
5484 reload_when_needed[r]))
5485 reload_override_in[r] = 0;
5489 /* Now that reload_override_in is known valid,
5490 actually override reload_in. */
5491 for (j = 0; j < n_reloads; j++)
5492 if (reload_override_in[j])
5493 reload_in[j] = reload_override_in[j];
5495 /* If this reload won't be done because it has been cancelled or is
5496 optional and not inherited, clear reload_reg_rtx so other
5497 routines (such as subst_reloads) don't get confused. */
5498 for (j = 0; j < n_reloads; j++)
5499 if (reload_reg_rtx[j] != 0
5500 && ((reload_optional[j] && ! reload_inherited[j])
5501 || (reload_in[j] == 0 && reload_out[j] == 0
5502 && ! reload_secondary_p[j])))
5504 int regno = true_regnum (reload_reg_rtx[j]);
5506 if (spill_reg_order[regno] >= 0)
5507 clear_reload_reg_in_use (regno, reload_opnum[j],
5508 reload_when_needed[j], reload_mode[j]);
5509 reload_reg_rtx[j] = 0;
5512 /* Record which pseudos and which spill regs have output reloads. */
5513 for (j = 0; j < n_reloads; j++)
5515 register int r = reload_order[j];
5517 i = reload_spill_index[r];
5519 /* I is nonneg if this reload used one of the spill regs.
5520 If reload_reg_rtx[r] is 0, this is an optional reload
5521 that we opted to ignore. */
5522 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG
5523 && reload_reg_rtx[r] != 0)
5525 register int nregno = REGNO (reload_out[r]);
5528 if (nregno < FIRST_PSEUDO_REGISTER)
5529 nr = HARD_REGNO_NREGS (nregno, reload_mode[r]);
5532 reg_has_output_reload[nregno + nr] = 1;
5536 nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
5538 SET_HARD_REG_BIT (reg_is_output_reload, spill_regs[i] + nr);
5541 if (reload_when_needed[r] != RELOAD_OTHER
5542 && reload_when_needed[r] != RELOAD_FOR_OUTPUT
5543 && reload_when_needed[r] != RELOAD_FOR_INSN)
5549 /* If SMALL_REGISTER_CLASSES are defined, we may not have merged two
5550 reloads of the same item for fear that we might not have enough reload
5551 registers. However, normally they will get the same reload register
5552 and hence actually need not be loaded twice.
5554 Here we check for the most common case of this phenomenon: when we have
5555 a number of reloads for the same object, each of which were allocated
5556 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5557 reload, and is not modified in the insn itself. If we find such,
5558 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5559 This will not increase the number of spill registers needed and will
5560 prevent redundant code. */
5562 #ifdef SMALL_REGISTER_CLASSES
5565 merge_assigned_reloads (insn)
5570 /* Scan all the reloads looking for ones that only load values and
5571 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5572 assigned and not modified by INSN. */
5574 for (i = 0; i < n_reloads; i++)
5576 if (reload_in[i] == 0 || reload_when_needed[i] == RELOAD_OTHER
5577 || reload_out[i] != 0 || reload_reg_rtx[i] == 0
5578 || reg_set_p (reload_reg_rtx[i], insn))
5581 /* Look at all other reloads. Ensure that the only use of this
5582 reload_reg_rtx is in a reload that just loads the same value
5583 as we do. Note that any secondary reloads must be of the identical
5584 class since the values, modes, and result registers are the
5585 same, so we need not do anything with any secondary reloads. */
5587 for (j = 0; j < n_reloads; j++)
5589 if (i == j || reload_reg_rtx[j] == 0
5590 || ! reg_overlap_mentioned_p (reload_reg_rtx[j],
5594 /* If the reload regs aren't exactly the same (e.g, different modes)
5595 or if the values are different, we can't merge anything with this
5598 if (! rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
5599 || reload_out[j] != 0 || reload_in[j] == 0
5600 || ! rtx_equal_p (reload_in[i], reload_in[j]))
5604 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5605 we, in fact, found any matching reloads. */
5609 for (j = 0; j < n_reloads; j++)
5610 if (i != j && reload_reg_rtx[j] != 0
5611 && rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j]))
5613 reload_when_needed[i] = RELOAD_OTHER;
5615 transfer_replacements (i, j);
5618 /* If this is now RELOAD_OTHER, look for any reloads that load
5619 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
5620 if they were for inputs, RELOAD_OTHER for outputs. Note that
5621 this test is equivalent to looking for reloads for this operand
5624 if (reload_when_needed[i] == RELOAD_OTHER)
5625 for (j = 0; j < n_reloads; j++)
5626 if (reload_in[j] != 0
5627 && reload_when_needed[i] != RELOAD_OTHER
5628 && reg_overlap_mentioned_for_reload_p (reload_in[j],
5630 reload_when_needed[j]
5631 = reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS
5632 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER;
5636 #endif /* SMALL_RELOAD_CLASSES */
5638 /* Output insns to reload values in and out of the chosen reload regs. */
5641 emit_reload_insns (insn)
5645 rtx input_reload_insns[MAX_RECOG_OPERANDS];
5646 rtx other_input_address_reload_insns = 0;
5647 rtx other_input_reload_insns = 0;
5648 rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
5649 rtx output_reload_insns[MAX_RECOG_OPERANDS];
5650 rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
5651 rtx operand_reload_insns = 0;
5652 rtx other_operand_reload_insns = 0;
5653 rtx other_output_reload_insns = 0;
5654 rtx following_insn = NEXT_INSN (insn);
5655 rtx before_insn = insn;
5657 /* Values to be put in spill_reg_store are put here first. */
5658 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
5660 for (j = 0; j < reload_n_operands; j++)
5661 input_reload_insns[j] = input_address_reload_insns[j]
5662 = output_reload_insns[j] = output_address_reload_insns[j] = 0;
5664 /* Now output the instructions to copy the data into and out of the
5665 reload registers. Do these in the order that the reloads were reported,
5666 since reloads of base and index registers precede reloads of operands
5667 and the operands may need the base and index registers reloaded. */
5669 for (j = 0; j < n_reloads; j++)
5672 rtx oldequiv_reg = 0;
5674 if (reload_spill_index[j] >= 0)
5675 new_spill_reg_store[reload_spill_index[j]] = 0;
5678 if (old != 0 && ! reload_inherited[j]
5679 && ! rtx_equal_p (reload_reg_rtx[j], old)
5680 && reload_reg_rtx[j] != 0)
5682 register rtx reloadreg = reload_reg_rtx[j];
5684 enum machine_mode mode;
5687 /* Determine the mode to reload in.
5688 This is very tricky because we have three to choose from.
5689 There is the mode the insn operand wants (reload_inmode[J]).
5690 There is the mode of the reload register RELOADREG.
5691 There is the intrinsic mode of the operand, which we could find
5692 by stripping some SUBREGs.
5693 It turns out that RELOADREG's mode is irrelevant:
5694 we can change that arbitrarily.
5696 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
5697 then the reload reg may not support QImode moves, so use SImode.
5698 If foo is in memory due to spilling a pseudo reg, this is safe,
5699 because the QImode value is in the least significant part of a
5700 slot big enough for a SImode. If foo is some other sort of
5701 memory reference, then it is impossible to reload this case,
5702 so previous passes had better make sure this never happens.
5704 Then consider a one-word union which has SImode and one of its
5705 members is a float, being fetched as (SUBREG:SF union:SI).
5706 We must fetch that as SFmode because we could be loading into
5707 a float-only register. In this case OLD's mode is correct.
5709 Consider an immediate integer: it has VOIDmode. Here we need
5710 to get a mode from something else.
5712 In some cases, there is a fourth mode, the operand's
5713 containing mode. If the insn specifies a containing mode for
5714 this operand, it overrides all others.
5716 I am not sure whether the algorithm here is always right,
5717 but it does the right things in those cases. */
5719 mode = GET_MODE (old);
5720 if (mode == VOIDmode)
5721 mode = reload_inmode[j];
5723 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5724 /* If we need a secondary register for this operation, see if
5725 the value is already in a register in that class. Don't
5726 do this if the secondary register will be used as a scratch
5729 if (reload_secondary_in_reload[j] >= 0
5730 && reload_secondary_in_icode[j] == CODE_FOR_nothing
5733 = find_equiv_reg (old, insn,
5734 reload_reg_class[reload_secondary_in_reload[j]],
5735 -1, NULL_PTR, 0, mode);
5738 /* If reloading from memory, see if there is a register
5739 that already holds the same value. If so, reload from there.
5740 We can pass 0 as the reload_reg_p argument because
5741 any other reload has either already been emitted,
5742 in which case find_equiv_reg will see the reload-insn,
5743 or has yet to be emitted, in which case it doesn't matter
5744 because we will use this equiv reg right away. */
5746 if (oldequiv == 0 && optimize
5747 && (GET_CODE (old) == MEM
5748 || (GET_CODE (old) == REG
5749 && REGNO (old) >= FIRST_PSEUDO_REGISTER
5750 && reg_renumber[REGNO (old)] < 0)))
5751 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
5752 -1, NULL_PTR, 0, mode);
5756 int regno = true_regnum (oldequiv);
5758 /* If OLDEQUIV is a spill register, don't use it for this
5759 if any other reload needs it at an earlier stage of this insn
5760 or at this stage. */
5761 if (spill_reg_order[regno] >= 0
5762 && (! reload_reg_free_p (regno, reload_opnum[j],
5763 reload_when_needed[j])
5764 || ! reload_reg_free_before_p (regno, reload_opnum[j],
5765 reload_when_needed[j])))
5768 /* If OLDEQUIV is not a spill register,
5769 don't use it if any other reload wants it. */
5770 if (spill_reg_order[regno] < 0)
5773 for (k = 0; k < n_reloads; k++)
5774 if (reload_reg_rtx[k] != 0 && k != j
5775 && reg_overlap_mentioned_for_reload_p (reload_reg_rtx[k],
5783 /* If it is no cheaper to copy from OLDEQUIV into the
5784 reload register than it would be to move from memory,
5785 don't use it. Likewise, if we need a secondary register
5789 && ((REGNO_REG_CLASS (regno) != reload_reg_class[j]
5790 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
5791 reload_reg_class[j])
5792 >= MEMORY_MOVE_COST (mode)))
5793 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5794 || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
5798 #ifdef SECONDARY_MEMORY_NEEDED
5799 || SECONDARY_MEMORY_NEEDED (reload_reg_class[j],
5800 REGNO_REG_CLASS (regno),
5809 else if (GET_CODE (oldequiv) == REG)
5810 oldequiv_reg = oldequiv;
5811 else if (GET_CODE (oldequiv) == SUBREG)
5812 oldequiv_reg = SUBREG_REG (oldequiv);
5814 /* If we are reloading from a register that was recently stored in
5815 with an output-reload, see if we can prove there was
5816 actually no need to store the old value in it. */
5818 if (optimize && GET_CODE (oldequiv) == REG
5819 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
5820 && spill_reg_order[REGNO (oldequiv)] >= 0
5821 && spill_reg_store[spill_reg_order[REGNO (oldequiv)]] != 0
5822 && find_reg_note (insn, REG_DEAD, reload_in[j])
5823 /* This is unsafe if operand occurs more than once in current
5824 insn. Perhaps some occurrences weren't reloaded. */
5825 && count_occurrences (PATTERN (insn), reload_in[j]) == 1)
5826 delete_output_reload
5827 (insn, j, spill_reg_store[spill_reg_order[REGNO (oldequiv)]]);
5829 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
5830 then load RELOADREG from OLDEQUIV. Note that we cannot use
5831 gen_lowpart_common since it can do the wrong thing when
5832 RELOADREG has a multi-word mode. Note that RELOADREG
5833 must always be a REG here. */
5835 if (GET_MODE (reloadreg) != mode)
5836 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
5837 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
5838 oldequiv = SUBREG_REG (oldequiv);
5839 if (GET_MODE (oldequiv) != VOIDmode
5840 && mode != GET_MODE (oldequiv))
5841 oldequiv = gen_rtx (SUBREG, mode, oldequiv, 0);
5843 /* Switch to the right place to emit the reload insns. */
5844 switch (reload_when_needed[j])
5847 where = &other_input_reload_insns;
5849 case RELOAD_FOR_INPUT:
5850 where = &input_reload_insns[reload_opnum[j]];
5852 case RELOAD_FOR_INPUT_ADDRESS:
5853 where = &input_address_reload_insns[reload_opnum[j]];
5855 case RELOAD_FOR_OUTPUT_ADDRESS:
5856 where = &output_address_reload_insns[reload_opnum[j]];
5858 case RELOAD_FOR_OPERAND_ADDRESS:
5859 where = &operand_reload_insns;
5861 case RELOAD_FOR_OPADDR_ADDR:
5862 where = &other_operand_reload_insns;
5864 case RELOAD_FOR_OTHER_ADDRESS:
5865 where = &other_input_address_reload_insns;
5871 push_to_sequence (*where);
5874 /* Auto-increment addresses must be reloaded in a special way. */
5875 if (GET_CODE (oldequiv) == POST_INC
5876 || GET_CODE (oldequiv) == POST_DEC
5877 || GET_CODE (oldequiv) == PRE_INC
5878 || GET_CODE (oldequiv) == PRE_DEC)
5880 /* We are not going to bother supporting the case where a
5881 incremented register can't be copied directly from
5882 OLDEQUIV since this seems highly unlikely. */
5883 if (reload_secondary_in_reload[j] >= 0)
5885 /* Prevent normal processing of this reload. */
5887 /* Output a special code sequence for this case. */
5888 inc_for_reload (reloadreg, oldequiv, reload_inc[j]);
5891 /* If we are reloading a pseudo-register that was set by the previous
5892 insn, see if we can get rid of that pseudo-register entirely
5893 by redirecting the previous insn into our reload register. */
5895 else if (optimize && GET_CODE (old) == REG
5896 && REGNO (old) >= FIRST_PSEUDO_REGISTER
5897 && dead_or_set_p (insn, old)
5898 /* This is unsafe if some other reload
5899 uses the same reg first. */
5900 && reload_reg_free_before_p (REGNO (reloadreg),
5902 reload_when_needed[j]))
5904 rtx temp = PREV_INSN (insn);
5905 while (temp && GET_CODE (temp) == NOTE)
5906 temp = PREV_INSN (temp);
5908 && GET_CODE (temp) == INSN
5909 && GET_CODE (PATTERN (temp)) == SET
5910 && SET_DEST (PATTERN (temp)) == old
5911 /* Make sure we can access insn_operand_constraint. */
5912 && asm_noperands (PATTERN (temp)) < 0
5913 /* This is unsafe if prev insn rejects our reload reg. */
5914 && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0],
5916 /* This is unsafe if operand occurs more than once in current
5917 insn. Perhaps some occurrences aren't reloaded. */
5918 && count_occurrences (PATTERN (insn), old) == 1
5919 /* Don't risk splitting a matching pair of operands. */
5920 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
5922 /* Store into the reload register instead of the pseudo. */
5923 SET_DEST (PATTERN (temp)) = reloadreg;
5924 /* If these are the only uses of the pseudo reg,
5925 pretend for GDB it lives in the reload reg we used. */
5926 if (reg_n_deaths[REGNO (old)] == 1
5927 && reg_n_sets[REGNO (old)] == 1)
5929 reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]);
5930 alter_reg (REGNO (old), -1);
5936 /* We can't do that, so output an insn to load RELOADREG. */
5940 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5941 rtx second_reload_reg = 0;
5942 enum insn_code icode;
5944 /* If we have a secondary reload, pick up the secondary register
5945 and icode, if any. If OLDEQUIV and OLD are different or
5946 if this is an in-out reload, recompute whether or not we
5947 still need a secondary register and what the icode should
5948 be. If we still need a secondary register and the class or
5949 icode is different, go back to reloading from OLD if using
5950 OLDEQUIV means that we got the wrong type of register. We
5951 cannot have different class or icode due to an in-out reload
5952 because we don't make such reloads when both the input and
5953 output need secondary reload registers. */
5955 if (reload_secondary_in_reload[j] >= 0)
5957 int secondary_reload = reload_secondary_in_reload[j];
5958 rtx real_oldequiv = oldequiv;
5961 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
5962 and similarly for OLD.
5963 See comments in get_secondary_reload in reload.c. */
5964 if (GET_CODE (oldequiv) == REG
5965 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
5966 && reg_equiv_mem[REGNO (oldequiv)] != 0)
5967 real_oldequiv = reg_equiv_mem[REGNO (oldequiv)];
5969 if (GET_CODE (old) == REG
5970 && REGNO (old) >= FIRST_PSEUDO_REGISTER
5971 && reg_equiv_mem[REGNO (old)] != 0)
5972 real_old = reg_equiv_mem[REGNO (old)];
5974 second_reload_reg = reload_reg_rtx[secondary_reload];
5975 icode = reload_secondary_in_icode[j];
5977 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
5978 || (reload_in[j] != 0 && reload_out[j] != 0))
5980 enum reg_class new_class
5981 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
5982 mode, real_oldequiv);
5984 if (new_class == NO_REGS)
5985 second_reload_reg = 0;
5988 enum insn_code new_icode;
5989 enum machine_mode new_mode;
5991 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
5992 REGNO (second_reload_reg)))
5993 oldequiv = old, real_oldequiv = real_old;
5996 new_icode = reload_in_optab[(int) mode];
5997 if (new_icode != CODE_FOR_nothing
5998 && ((insn_operand_predicate[(int) new_icode][0]
5999 && ! ((*insn_operand_predicate[(int) new_icode][0])
6001 || (insn_operand_predicate[(int) new_icode][1]
6002 && ! ((*insn_operand_predicate[(int) new_icode][1])
6003 (real_oldequiv, mode)))))
6004 new_icode = CODE_FOR_nothing;
6006 if (new_icode == CODE_FOR_nothing)
6009 new_mode = insn_operand_mode[(int) new_icode][2];
6011 if (GET_MODE (second_reload_reg) != new_mode)
6013 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6015 oldequiv = old, real_oldequiv = real_old;
6018 = gen_rtx (REG, new_mode,
6019 REGNO (second_reload_reg));
6025 /* If we still need a secondary reload register, check
6026 to see if it is being used as a scratch or intermediate
6027 register and generate code appropriately. If we need
6028 a scratch register, use REAL_OLDEQUIV since the form of
6029 the insn may depend on the actual address if it is
6032 if (second_reload_reg)
6034 if (icode != CODE_FOR_nothing)
6036 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6037 second_reload_reg));
6042 /* See if we need a scratch register to load the
6043 intermediate register (a tertiary reload). */
6044 enum insn_code tertiary_icode
6045 = reload_secondary_in_icode[secondary_reload];
6047 if (tertiary_icode != CODE_FOR_nothing)
6049 rtx third_reload_reg
6050 = reload_reg_rtx[reload_secondary_in_reload[secondary_reload]];
6052 emit_insn ((GEN_FCN (tertiary_icode)
6053 (second_reload_reg, real_oldequiv,
6054 third_reload_reg)));
6057 gen_reload (second_reload_reg, oldequiv,
6059 reload_when_needed[j]);
6061 oldequiv = second_reload_reg;
6067 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6068 gen_reload (reloadreg, oldequiv, reload_opnum[j],
6069 reload_when_needed[j]);
6071 #if defined(SECONDARY_INPUT_RELOAD_CLASS) && defined(PRESERVE_DEATH_INFO_REGNO_P)
6072 /* We may have to make a REG_DEAD note for the secondary reload
6073 register in the insns we just made. Find the last insn that
6074 mentioned the register. */
6075 if (! special && second_reload_reg
6076 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reload_reg)))
6080 for (prev = get_last_insn (); prev;
6081 prev = PREV_INSN (prev))
6082 if (GET_RTX_CLASS (GET_CODE (prev) == 'i')
6083 && reg_overlap_mentioned_for_reload_p (second_reload_reg,
6086 REG_NOTES (prev) = gen_rtx (EXPR_LIST, REG_DEAD,
6095 /* End this sequence. */
6096 *where = get_insns ();
6100 /* Add a note saying the input reload reg
6101 dies in this insn, if anyone cares. */
6102 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6104 && reload_reg_rtx[j] != old
6105 && reload_reg_rtx[j] != 0
6106 && reload_out[j] == 0
6107 && ! reload_inherited[j]
6108 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j])))
6110 register rtx reloadreg = reload_reg_rtx[j];
6113 /* We can't abort here because we need to support this for sched.c.
6114 It's not terrible to miss a REG_DEAD note, but we should try
6115 to figure out how to do this correctly. */
6116 /* The code below is incorrect for address-only reloads. */
6117 if (reload_when_needed[j] != RELOAD_OTHER
6118 && reload_when_needed[j] != RELOAD_FOR_INPUT)
6122 /* Add a death note to this insn, for an input reload. */
6124 if ((reload_when_needed[j] == RELOAD_OTHER
6125 || reload_when_needed[j] == RELOAD_FOR_INPUT)
6126 && ! dead_or_set_p (insn, reloadreg))
6128 = gen_rtx (EXPR_LIST, REG_DEAD,
6129 reloadreg, REG_NOTES (insn));
6132 /* When we inherit a reload, the last marked death of the reload reg
6133 may no longer really be a death. */
6134 if (reload_reg_rtx[j] != 0
6135 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j]))
6136 && reload_inherited[j])
6138 /* Handle inheriting an output reload.
6139 Remove the death note from the output reload insn. */
6140 if (reload_spill_index[j] >= 0
6141 && GET_CODE (reload_in[j]) == REG
6142 && spill_reg_store[reload_spill_index[j]] != 0
6143 && find_regno_note (spill_reg_store[reload_spill_index[j]],
6144 REG_DEAD, REGNO (reload_reg_rtx[j])))
6145 remove_death (REGNO (reload_reg_rtx[j]),
6146 spill_reg_store[reload_spill_index[j]]);
6147 /* Likewise for input reloads that were inherited. */
6148 else if (reload_spill_index[j] >= 0
6149 && GET_CODE (reload_in[j]) == REG
6150 && spill_reg_store[reload_spill_index[j]] == 0
6151 && reload_inheritance_insn[j] != 0
6152 && find_regno_note (reload_inheritance_insn[j], REG_DEAD,
6153 REGNO (reload_reg_rtx[j])))
6154 remove_death (REGNO (reload_reg_rtx[j]),
6155 reload_inheritance_insn[j]);
6160 /* We got this register from find_equiv_reg.
6161 Search back for its last death note and get rid of it.
6162 But don't search back too far.
6163 Don't go past a place where this reg is set,
6164 since a death note before that remains valid. */
6165 for (prev = PREV_INSN (insn);
6166 prev && GET_CODE (prev) != CODE_LABEL;
6167 prev = PREV_INSN (prev))
6168 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
6169 && dead_or_set_p (prev, reload_reg_rtx[j]))
6171 if (find_regno_note (prev, REG_DEAD,
6172 REGNO (reload_reg_rtx[j])))
6173 remove_death (REGNO (reload_reg_rtx[j]), prev);
6179 /* We might have used find_equiv_reg above to choose an alternate
6180 place from which to reload. If so, and it died, we need to remove
6181 that death and move it to one of the insns we just made. */
6183 if (oldequiv_reg != 0
6184 && PRESERVE_DEATH_INFO_REGNO_P (true_regnum (oldequiv_reg)))
6188 for (prev = PREV_INSN (insn); prev && GET_CODE (prev) != CODE_LABEL;
6189 prev = PREV_INSN (prev))
6190 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
6191 && dead_or_set_p (prev, oldequiv_reg))
6193 if (find_regno_note (prev, REG_DEAD, REGNO (oldequiv_reg)))
6195 for (prev1 = this_reload_insn;
6196 prev1; prev1 = PREV_INSN (prev1))
6197 if (GET_RTX_CLASS (GET_CODE (prev1) == 'i')
6198 && reg_overlap_mentioned_for_reload_p (oldequiv_reg,
6201 REG_NOTES (prev1) = gen_rtx (EXPR_LIST, REG_DEAD,
6206 remove_death (REGNO (oldequiv_reg), prev);
6213 /* If we are reloading a register that was recently stored in with an
6214 output-reload, see if we can prove there was
6215 actually no need to store the old value in it. */
6217 if (optimize && reload_inherited[j] && reload_spill_index[j] >= 0
6218 && reload_in[j] != 0
6219 && GET_CODE (reload_in[j]) == REG
6221 /* There doesn't seem to be any reason to restrict this to pseudos
6222 and doing so loses in the case where we are copying from a
6223 register of the wrong class. */
6224 && REGNO (reload_in[j]) >= FIRST_PSEUDO_REGISTER
6226 && spill_reg_store[reload_spill_index[j]] != 0
6227 /* This is unsafe if some other reload uses the same reg first. */
6228 && reload_reg_free_before_p (spill_regs[reload_spill_index[j]],
6229 reload_opnum[j], reload_when_needed[j])
6230 && dead_or_set_p (insn, reload_in[j])
6231 /* This is unsafe if operand occurs more than once in current
6232 insn. Perhaps some occurrences weren't reloaded. */
6233 && count_occurrences (PATTERN (insn), reload_in[j]) == 1)
6234 delete_output_reload (insn, j,
6235 spill_reg_store[reload_spill_index[j]]);
6237 /* Input-reloading is done. Now do output-reloading,
6238 storing the value from the reload-register after the main insn
6239 if reload_out[j] is nonzero.
6241 ??? At some point we need to support handling output reloads of
6242 JUMP_INSNs or insns that set cc0. */
6243 old = reload_out[j];
6245 && reload_reg_rtx[j] != old
6246 && reload_reg_rtx[j] != 0)
6248 register rtx reloadreg = reload_reg_rtx[j];
6249 register rtx second_reloadreg = 0;
6251 enum machine_mode mode;
6254 /* An output operand that dies right away does need a reload,
6255 but need not be copied from it. Show the new location in the
6257 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6258 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6260 XEXP (note, 0) = reload_reg_rtx[j];
6263 /* Likewise for a SUBREG of an operand that dies. */
6264 else if (GET_CODE (old) == SUBREG
6265 && GET_CODE (SUBREG_REG (old)) == REG
6266 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6269 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6273 else if (GET_CODE (old) == SCRATCH)
6274 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6275 but we don't want to make an output reload. */
6279 /* Strip off of OLD any size-increasing SUBREGs such as
6280 (SUBREG:SI foo:QI 0). */
6282 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
6283 && (GET_MODE_SIZE (GET_MODE (old))
6284 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
6285 old = SUBREG_REG (old);
6288 /* If is a JUMP_INSN, we can't support output reloads yet. */
6289 if (GET_CODE (insn) == JUMP_INSN)
6292 if (reload_when_needed[j] == RELOAD_OTHER)
6295 push_to_sequence (output_reload_insns[reload_opnum[j]]);
6297 /* Determine the mode to reload in.
6298 See comments above (for input reloading). */
6300 mode = GET_MODE (old);
6301 if (mode == VOIDmode)
6303 /* VOIDmode should never happen for an output. */
6304 if (asm_noperands (PATTERN (insn)) < 0)
6305 /* It's the compiler's fault. */
6306 fatal_insn ("VOIDmode on an output", insn);
6307 error_for_asm (insn, "output operand is constant in `asm'");
6308 /* Prevent crash--use something we know is valid. */
6310 old = gen_rtx (REG, mode, REGNO (reloadreg));
6313 if (GET_MODE (reloadreg) != mode)
6314 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
6316 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6318 /* If we need two reload regs, set RELOADREG to the intermediate
6319 one, since it will be stored into OLD. We might need a secondary
6320 register only for an input reload, so check again here. */
6322 if (reload_secondary_out_reload[j] >= 0)
6326 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6327 && reg_equiv_mem[REGNO (old)] != 0)
6328 real_old = reg_equiv_mem[REGNO (old)];
6330 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j],
6334 second_reloadreg = reloadreg;
6335 reloadreg = reload_reg_rtx[reload_secondary_out_reload[j]];
6337 /* See if RELOADREG is to be used as a scratch register
6338 or as an intermediate register. */
6339 if (reload_secondary_out_icode[j] != CODE_FOR_nothing)
6341 emit_insn ((GEN_FCN (reload_secondary_out_icode[j])
6342 (real_old, second_reloadreg, reloadreg)));
6347 /* See if we need both a scratch and intermediate reload
6350 int secondary_reload = reload_secondary_out_reload[j];
6351 enum insn_code tertiary_icode
6352 = reload_secondary_out_icode[secondary_reload];
6354 if (GET_MODE (reloadreg) != mode)
6355 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
6357 if (tertiary_icode != CODE_FOR_nothing)
6360 = reload_reg_rtx[reload_secondary_out_reload[secondary_reload]];
6363 /* Copy primary reload reg to secondary reload reg.
6364 (Note that these have been swapped above, then
6365 secondary reload reg to OLD using our insn. */
6367 /* If REAL_OLD is a paradoxical SUBREG, remove it
6368 and try to put the opposite SUBREG on
6370 if (GET_CODE (real_old) == SUBREG
6371 && (GET_MODE_SIZE (GET_MODE (real_old))
6372 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6373 && 0 != (tem = gen_lowpart_common
6374 (GET_MODE (SUBREG_REG (real_old)),
6376 real_old = SUBREG_REG (real_old), reloadreg = tem;
6378 gen_reload (reloadreg, second_reloadreg,
6379 reload_opnum[j], reload_when_needed[j]);
6380 emit_insn ((GEN_FCN (tertiary_icode)
6381 (real_old, reloadreg, third_reloadreg)));
6386 /* Copy between the reload regs here and then to
6389 gen_reload (reloadreg, second_reloadreg,
6390 reload_opnum[j], reload_when_needed[j]);
6396 /* Output the last reload insn. */
6398 gen_reload (old, reloadreg, reload_opnum[j],
6399 reload_when_needed[j]);
6401 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6402 /* If final will look at death notes for this reg,
6403 put one on the last output-reload insn to use it. Similarly
6404 for any secondary register. */
6405 if (PRESERVE_DEATH_INFO_REGNO_P (REGNO (reloadreg)))
6406 for (p = get_last_insn (); p; p = PREV_INSN (p))
6407 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
6408 && reg_overlap_mentioned_for_reload_p (reloadreg,
6410 REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
6411 reloadreg, REG_NOTES (p));
6413 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6415 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reloadreg)))
6416 for (p = get_last_insn (); p; p = PREV_INSN (p))
6417 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
6418 && reg_overlap_mentioned_for_reload_p (second_reloadreg,
6420 REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
6421 second_reloadreg, REG_NOTES (p));
6424 /* Look at all insns we emitted, just to be safe. */
6425 for (p = get_insns (); p; p = NEXT_INSN (p))
6426 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
6428 /* If this output reload doesn't come from a spill reg,
6429 clear any memory of reloaded copies of the pseudo reg.
6430 If this output reload comes from a spill reg,
6431 reg_has_output_reload will make this do nothing. */
6432 note_stores (PATTERN (p), forget_old_reloads_1);
6434 if (reg_mentioned_p (reload_reg_rtx[j], PATTERN (p))
6435 && reload_spill_index[j] >= 0)
6436 new_spill_reg_store[reload_spill_index[j]] = p;
6439 if (reload_when_needed[j] == RELOAD_OTHER)
6441 if (other_output_reload_insns)
6442 emit_insns (other_output_reload_insns);
6443 other_output_reload_insns = get_insns ();
6446 output_reload_insns[reload_opnum[j]] = get_insns ();
6452 /* Now write all the insns we made for reloads in the order expected by
6453 the allocation functions. Prior to the insn being reloaded, we write
6454 the following reloads:
6456 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6458 RELOAD_OTHER reloads, output in ascending order by reload number.
6460 For each operand, any RELOAD_FOR_INPUT_ADDRESS reloads followed by
6461 the RELOAD_FOR_INPUT reload for the operand.
6463 RELOAD_FOR_OPADDR_ADDRS reloads.
6465 RELOAD_FOR_OPERAND_ADDRESS reloads.
6467 After the insn being reloaded, we write the following:
6469 For each operand, any RELOAD_FOR_OUTPUT_ADDRESS reload followed by
6470 the RELOAD_FOR_OUTPUT reload for that operand.
6472 Any RELOAD_OTHER output reloads, output in descending order by
6475 emit_insns_before (other_input_address_reload_insns, before_insn);
6476 emit_insns_before (other_input_reload_insns, before_insn);
6478 for (j = 0; j < reload_n_operands; j++)
6480 emit_insns_before (input_address_reload_insns[j], before_insn);
6481 emit_insns_before (input_reload_insns[j], before_insn);
6484 emit_insns_before (other_operand_reload_insns, before_insn);
6485 emit_insns_before (operand_reload_insns, before_insn);
6487 for (j = 0; j < reload_n_operands; j++)
6489 emit_insns_before (output_address_reload_insns[j], following_insn);
6490 emit_insns_before (output_reload_insns[j], following_insn);
6493 emit_insns_before (other_output_reload_insns, following_insn);
6495 /* Move death notes from INSN
6496 to output-operand-address and output reload insns. */
6497 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6500 /* Loop over those insns, last ones first. */
6501 for (insn1 = PREV_INSN (following_insn); insn1 != insn;
6502 insn1 = PREV_INSN (insn1))
6503 if (GET_CODE (insn1) == INSN && GET_CODE (PATTERN (insn1)) == SET)
6505 rtx source = SET_SRC (PATTERN (insn1));
6506 rtx dest = SET_DEST (PATTERN (insn1));
6508 /* The note we will examine next. */
6509 rtx reg_notes = REG_NOTES (insn);
6510 /* The place that pointed to this note. */
6511 rtx *prev_reg_note = ®_NOTES (insn);
6513 /* If the note is for something used in the source of this
6514 reload insn, or in the output address, move the note. */
6517 rtx next_reg_notes = XEXP (reg_notes, 1);
6518 if (REG_NOTE_KIND (reg_notes) == REG_DEAD
6519 && GET_CODE (XEXP (reg_notes, 0)) == REG
6520 && ((GET_CODE (dest) != REG
6521 && reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
6523 || reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
6526 *prev_reg_note = next_reg_notes;
6527 XEXP (reg_notes, 1) = REG_NOTES (insn1);
6528 REG_NOTES (insn1) = reg_notes;
6531 prev_reg_note = &XEXP (reg_notes, 1);
6533 reg_notes = next_reg_notes;
6539 /* For all the spill regs newly reloaded in this instruction,
6540 record what they were reloaded from, so subsequent instructions
6541 can inherit the reloads.
6543 Update spill_reg_store for the reloads of this insn.
6544 Copy the elements that were updated in the loop above. */
6546 for (j = 0; j < n_reloads; j++)
6548 register int r = reload_order[j];
6549 register int i = reload_spill_index[r];
6551 /* I is nonneg if this reload used one of the spill regs.
6552 If reload_reg_rtx[r] is 0, this is an optional reload
6553 that we opted to ignore.
6555 Also ignore reloads that don't reach the end of the insn,
6556 since we will eventually see the one that does. */
6558 if (i >= 0 && reload_reg_rtx[r] != 0
6559 && reload_reg_reaches_end_p (spill_regs[i], reload_opnum[r],
6560 reload_when_needed[r]))
6562 /* First, clear out memory of what used to be in this spill reg.
6563 If consecutive registers are used, clear them all. */
6565 = HARD_REGNO_NREGS (spill_regs[i], GET_MODE (reload_reg_rtx[r]));
6568 for (k = 0; k < nr; k++)
6570 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] = -1;
6571 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = 0;
6574 /* Maybe the spill reg contains a copy of reload_out. */
6575 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
6577 register int nregno = REGNO (reload_out[r]);
6578 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6579 : HARD_REGNO_NREGS (nregno,
6580 GET_MODE (reload_reg_rtx[r])));
6582 spill_reg_store[i] = new_spill_reg_store[i];
6583 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
6585 /* If NREGNO is a hard register, it may occupy more than
6586 one register. If it does, say what is in the
6587 rest of the registers assuming that both registers
6588 agree on how many words the object takes. If not,
6589 invalidate the subsequent registers. */
6591 if (nregno < FIRST_PSEUDO_REGISTER)
6592 for (k = 1; k < nnr; k++)
6593 reg_last_reload_reg[nregno + k]
6594 = (nr == nnr ? gen_rtx (REG,
6595 reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
6596 REGNO (reload_reg_rtx[r]) + k)
6599 /* Now do the inverse operation. */
6600 for (k = 0; k < nr; k++)
6602 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
6603 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr ? nregno
6605 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = insn;
6609 /* Maybe the spill reg contains a copy of reload_in. Only do
6610 something if there will not be an output reload for
6611 the register being reloaded. */
6612 else if (reload_out[r] == 0
6613 && reload_in[r] != 0
6614 && ((GET_CODE (reload_in[r]) == REG
6615 && ! reg_has_output_reload[REGNO (reload_in[r])]
6616 || (GET_CODE (reload_in_reg[r]) == REG
6617 && ! reg_has_output_reload[REGNO (reload_in_reg[r])]))))
6619 register int nregno;
6622 if (GET_CODE (reload_in[r]) == REG)
6623 nregno = REGNO (reload_in[r]);
6625 nregno = REGNO (reload_in_reg[r]);
6627 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6628 : HARD_REGNO_NREGS (nregno,
6629 GET_MODE (reload_reg_rtx[r])));
6631 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
6633 if (nregno < FIRST_PSEUDO_REGISTER)
6634 for (k = 1; k < nnr; k++)
6635 reg_last_reload_reg[nregno + k]
6636 = (nr == nnr ? gen_rtx (REG,
6637 reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
6638 REGNO (reload_reg_rtx[r]) + k)
6641 /* Unless we inherited this reload, show we haven't
6642 recently done a store. */
6643 if (! reload_inherited[r])
6644 spill_reg_store[i] = 0;
6646 for (k = 0; k < nr; k++)
6648 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
6649 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr ? nregno
6651 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]]
6657 /* The following if-statement was #if 0'd in 1.34 (or before...).
6658 It's reenabled in 1.35 because supposedly nothing else
6659 deals with this problem. */
6661 /* If a register gets output-reloaded from a non-spill register,
6662 that invalidates any previous reloaded copy of it.
6663 But forget_old_reloads_1 won't get to see it, because
6664 it thinks only about the original insn. So invalidate it here. */
6665 if (i < 0 && reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
6667 register int nregno = REGNO (reload_out[r]);
6668 if (nregno >= FIRST_PSEUDO_REGISTER)
6669 reg_last_reload_reg[nregno] = 0;
6672 int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (reload_out[r]));
6674 while (num_regs-- > 0)
6675 reg_last_reload_reg[nregno + num_regs] = 0;
6681 /* Emit code to perform a reload from IN (which may be a reload register) to
6682 OUT (which may also be a reload register). IN or OUT is from operand
6683 OPNUM with reload type TYPE.
6685 Returns first insn emitted. */
6688 gen_reload (out, in, opnum, type)
6692 enum reload_type type;
6694 rtx last = get_last_insn ();
6697 /* If IN is a paradoxical SUBREG, remove it and try to put the
6698 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
6699 if (GET_CODE (in) == SUBREG
6700 && (GET_MODE_SIZE (GET_MODE (in))
6701 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
6702 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
6703 in = SUBREG_REG (in), out = tem;
6704 else if (GET_CODE (out) == SUBREG
6705 && (GET_MODE_SIZE (GET_MODE (out))
6706 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
6707 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
6708 out = SUBREG_REG (out), in = tem;
6710 /* How to do this reload can get quite tricky. Normally, we are being
6711 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
6712 register that didn't get a hard register. In that case we can just
6713 call emit_move_insn.
6715 We can also be asked to reload a PLUS that adds a register or a MEM to
6716 another register, constant or MEM. This can occur during frame pointer
6717 elimination and while reloading addresses. This case is handled by
6718 trying to emit a single insn to perform the add. If it is not valid,
6719 we use a two insn sequence.
6721 Finally, we could be called to handle an 'o' constraint by putting
6722 an address into a register. In that case, we first try to do this
6723 with a named pattern of "reload_load_address". If no such pattern
6724 exists, we just emit a SET insn and hope for the best (it will normally
6725 be valid on machines that use 'o').
6727 This entire process is made complex because reload will never
6728 process the insns we generate here and so we must ensure that
6729 they will fit their constraints and also by the fact that parts of
6730 IN might be being reloaded separately and replaced with spill registers.
6731 Because of this, we are, in some sense, just guessing the right approach
6732 here. The one listed above seems to work.
6734 ??? At some point, this whole thing needs to be rethought. */
6736 if (GET_CODE (in) == PLUS
6737 && (GET_CODE (XEXP (in, 0)) == REG
6738 || GET_CODE (XEXP (in, 0)) == MEM)
6739 && (GET_CODE (XEXP (in, 1)) == REG
6740 || CONSTANT_P (XEXP (in, 1))
6741 || GET_CODE (XEXP (in, 1)) == MEM))
6743 /* We need to compute the sum of a register or a MEM and another
6744 register, constant, or MEM, and put it into the reload
6745 register. The best possible way of doing this is if the machine
6746 has a three-operand ADD insn that accepts the required operands.
6748 The simplest approach is to try to generate such an insn and see if it
6749 is recognized and matches its constraints. If so, it can be used.
6751 It might be better not to actually emit the insn unless it is valid,
6752 but we need to pass the insn as an operand to `recog' and
6753 `insn_extract' and it is simpler to emit and then delete the insn if
6754 not valid than to dummy things up. */
6756 rtx op0, op1, tem, insn;
6759 op0 = find_replacement (&XEXP (in, 0));
6760 op1 = find_replacement (&XEXP (in, 1));
6762 /* Since constraint checking is strict, commutativity won't be
6763 checked, so we need to do that here to avoid spurious failure
6764 if the add instruction is two-address and the second operand
6765 of the add is the same as the reload reg, which is frequently
6766 the case. If the insn would be A = B + A, rearrange it so
6767 it will be A = A + B as constrain_operands expects. */
6769 if (GET_CODE (XEXP (in, 1)) == REG
6770 && REGNO (out) == REGNO (XEXP (in, 1)))
6771 tem = op0, op0 = op1, op1 = tem;
6773 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
6774 in = gen_rtx (PLUS, GET_MODE (in), op0, op1);
6776 insn = emit_insn (gen_rtx (SET, VOIDmode, out, in));
6777 code = recog_memoized (insn);
6781 insn_extract (insn);
6782 /* We want constrain operands to treat this insn strictly in
6783 its validity determination, i.e., the way it would after reload
6785 if (constrain_operands (code, 1))
6789 delete_insns_since (last);
6791 /* If that failed, we must use a conservative two-insn sequence.
6792 use move to copy constant, MEM, or pseudo register to the reload
6793 register since "move" will be able to handle an arbitrary operand,
6794 unlike add which can't, in general. Then add the registers.
6796 If there is another way to do this for a specific machine, a
6797 DEFINE_PEEPHOLE should be specified that recognizes the sequence
6800 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM
6801 || (GET_CODE (op1) == REG
6802 && REGNO (op1) >= FIRST_PSEUDO_REGISTER))
6803 tem = op0, op0 = op1, op1 = tem;
6805 emit_insn (gen_move_insn (out, op0));
6807 /* If OP0 and OP1 are the same, we can use OUT for OP1.
6808 This fixes a problem on the 32K where the stack pointer cannot
6809 be used as an operand of an add insn. */
6811 if (rtx_equal_p (op0, op1))
6814 insn = emit_insn (gen_add2_insn (out, op1));
6816 /* If that failed, copy the address register to the reload register.
6817 Then add the constant to the reload register. */
6819 code = recog_memoized (insn);
6823 insn_extract (insn);
6824 /* We want constrain operands to treat this insn strictly in
6825 its validity determination, i.e., the way it would after reload
6827 if (constrain_operands (code, 1))
6831 delete_insns_since (last);
6833 emit_insn (gen_move_insn (out, op1));
6834 emit_insn (gen_add2_insn (out, op0));
6837 #ifdef SECONDARY_MEMORY_NEEDED
6838 /* If we need a memory location to do the move, do it that way. */
6839 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
6840 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
6841 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
6842 REGNO_REG_CLASS (REGNO (out)),
6845 /* Get the memory to use and rewrite both registers to its mode. */
6846 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
6848 if (GET_MODE (loc) != GET_MODE (out))
6849 out = gen_rtx (REG, GET_MODE (loc), REGNO (out));
6851 if (GET_MODE (loc) != GET_MODE (in))
6852 in = gen_rtx (REG, GET_MODE (loc), REGNO (in));
6854 emit_insn (gen_move_insn (loc, in));
6855 emit_insn (gen_move_insn (out, loc));
6859 /* If IN is a simple operand, use gen_move_insn. */
6860 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
6861 emit_insn (gen_move_insn (out, in));
6863 #ifdef HAVE_reload_load_address
6864 else if (HAVE_reload_load_address)
6865 emit_insn (gen_reload_load_address (out, in));
6868 /* Otherwise, just write (set OUT IN) and hope for the best. */
6870 emit_insn (gen_rtx (SET, VOIDmode, out, in));
6872 /* Return the first insn emitted.
6873 We can not just return get_last_insn, because there may have
6874 been multiple instructions emitted. Also note that gen_move_insn may
6875 emit more than one insn itself, so we can not assume that there is one
6876 insn emitted per emit_insn_before call. */
6878 return last ? NEXT_INSN (last) : get_insns ();
6881 /* Delete a previously made output-reload
6882 whose result we now believe is not needed.
6883 First we double-check.
6885 INSN is the insn now being processed.
6886 OUTPUT_RELOAD_INSN is the insn of the output reload.
6887 J is the reload-number for this insn. */
6890 delete_output_reload (insn, j, output_reload_insn)
6893 rtx output_reload_insn;
6897 /* Get the raw pseudo-register referred to. */
6899 rtx reg = reload_in[j];
6900 while (GET_CODE (reg) == SUBREG)
6901 reg = SUBREG_REG (reg);
6903 /* If the pseudo-reg we are reloading is no longer referenced
6904 anywhere between the store into it and here,
6905 and no jumps or labels intervene, then the value can get
6906 here through the reload reg alone.
6907 Otherwise, give up--return. */
6908 for (i1 = NEXT_INSN (output_reload_insn);
6909 i1 != insn; i1 = NEXT_INSN (i1))
6911 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
6913 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
6914 && reg_mentioned_p (reg, PATTERN (i1)))
6918 if (cannot_omit_stores[REGNO (reg)])
6921 /* If this insn will store in the pseudo again,
6922 the previous store can be removed. */
6923 if (reload_out[j] == reload_in[j])
6924 delete_insn (output_reload_insn);
6926 /* See if the pseudo reg has been completely replaced
6927 with reload regs. If so, delete the store insn
6928 and forget we had a stack slot for the pseudo. */
6929 else if (reg_n_deaths[REGNO (reg)] == 1
6930 && reg_basic_block[REGNO (reg)] >= 0
6931 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
6935 /* We know that it was used only between here
6936 and the beginning of the current basic block.
6937 (We also know that the last use before INSN was
6938 the output reload we are thinking of deleting, but never mind that.)
6939 Search that range; see if any ref remains. */
6940 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
6942 rtx set = single_set (i2);
6944 /* Uses which just store in the pseudo don't count,
6945 since if they are the only uses, they are dead. */
6946 if (set != 0 && SET_DEST (set) == reg)
6948 if (GET_CODE (i2) == CODE_LABEL
6949 || GET_CODE (i2) == JUMP_INSN)
6951 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
6952 && reg_mentioned_p (reg, PATTERN (i2)))
6953 /* Some other ref remains;
6954 we can't do anything. */
6958 /* Delete the now-dead stores into this pseudo. */
6959 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
6961 rtx set = single_set (i2);
6963 if (set != 0 && SET_DEST (set) == reg)
6965 if (GET_CODE (i2) == CODE_LABEL
6966 || GET_CODE (i2) == JUMP_INSN)
6970 /* For the debugging info,
6971 say the pseudo lives in this reload reg. */
6972 reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]);
6973 alter_reg (REGNO (reg), -1);
6977 /* Output reload-insns to reload VALUE into RELOADREG.
6978 VALUE is an autoincrement or autodecrement RTX whose operand
6979 is a register or memory location;
6980 so reloading involves incrementing that location.
6982 INC_AMOUNT is the number to increment or decrement by (always positive).
6983 This cannot be deduced from VALUE. */
6986 inc_for_reload (reloadreg, value, inc_amount)
6991 /* REG or MEM to be copied and incremented. */
6992 rtx incloc = XEXP (value, 0);
6993 /* Nonzero if increment after copying. */
6994 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7000 /* No hard register is equivalent to this register after
7001 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7002 we could inc/dec that register as well (maybe even using it for
7003 the source), but I'm not sure it's worth worrying about. */
7004 if (GET_CODE (incloc) == REG)
7005 reg_last_reload_reg[REGNO (incloc)] = 0;
7007 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7008 inc_amount = - inc_amount;
7010 inc = GEN_INT (inc_amount);
7012 /* If this is post-increment, first copy the location to the reload reg. */
7014 emit_insn (gen_move_insn (reloadreg, incloc));
7016 /* See if we can directly increment INCLOC. Use a method similar to that
7019 last = get_last_insn ();
7020 add_insn = emit_insn (gen_rtx (SET, VOIDmode, incloc,
7021 gen_rtx (PLUS, GET_MODE (incloc),
7024 code = recog_memoized (add_insn);
7027 insn_extract (add_insn);
7028 if (constrain_operands (code, 1))
7030 /* If this is a pre-increment and we have incremented the value
7031 where it lives, copy the incremented value to RELOADREG to
7032 be used as an address. */
7035 emit_insn (gen_move_insn (reloadreg, incloc));
7041 delete_insns_since (last);
7043 /* If couldn't do the increment directly, must increment in RELOADREG.
7044 The way we do this depends on whether this is pre- or post-increment.
7045 For pre-increment, copy INCLOC to the reload register, increment it
7046 there, then save back. */
7050 emit_insn (gen_move_insn (reloadreg, incloc));
7051 emit_insn (gen_add2_insn (reloadreg, inc));
7052 emit_insn (gen_move_insn (incloc, reloadreg));
7057 Because this might be a jump insn or a compare, and because RELOADREG
7058 may not be available after the insn in an input reload, we must do
7059 the incrementation before the insn being reloaded for.
7061 We have already copied INCLOC to RELOADREG. Increment the copy in
7062 RELOADREG, save that back, then decrement RELOADREG so it has
7063 the original value. */
7065 emit_insn (gen_add2_insn (reloadreg, inc));
7066 emit_insn (gen_move_insn (incloc, reloadreg));
7067 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7073 /* Return 1 if we are certain that the constraint-string STRING allows
7074 the hard register REG. Return 0 if we can't be sure of this. */
7077 constraint_accepts_reg_p (string, reg)
7082 int regno = true_regnum (reg);
7085 /* Initialize for first alternative. */
7087 /* Check that each alternative contains `g' or `r'. */
7089 switch (c = *string++)
7092 /* If an alternative lacks `g' or `r', we lose. */
7095 /* If an alternative lacks `g' or `r', we lose. */
7098 /* Initialize for next alternative. */
7103 /* Any general reg wins for this alternative. */
7104 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7108 /* Any reg in specified class wins for this alternative. */
7110 enum reg_class class = REG_CLASS_FROM_LETTER (c);
7112 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
7118 /* Return the number of places FIND appears within X, but don't count
7119 an occurrence if some SET_DEST is FIND. */
7122 count_occurrences (x, find)
7123 register rtx x, find;
7126 register enum rtx_code code;
7127 register char *format_ptr;
7135 code = GET_CODE (x);
7150 if (SET_DEST (x) == find)
7151 return count_occurrences (SET_SRC (x), find);
7155 format_ptr = GET_RTX_FORMAT (code);
7158 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7160 switch (*format_ptr++)
7163 count += count_occurrences (XEXP (x, i), find);
7167 if (XVEC (x, i) != NULL)
7169 for (j = 0; j < XVECLEN (x, i); j++)
7170 count += count_occurrences (XVECEXP (x, i, j), find);
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