1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
33 #include "insn-config.h"
39 #include "addresses.h"
40 #include "basic-block.h"
50 /* This file contains the reload pass of the compiler, which is
51 run after register allocation has been done. It checks that
52 each insn is valid (operands required to be in registers really
53 are in registers of the proper class) and fixes up invalid ones
54 by copying values temporarily into registers for the insns
57 The results of register allocation are described by the vector
58 reg_renumber; the insns still contain pseudo regs, but reg_renumber
59 can be used to find which hard reg, if any, a pseudo reg is in.
61 The technique we always use is to free up a few hard regs that are
62 called ``reload regs'', and for each place where a pseudo reg
63 must be in a hard reg, copy it temporarily into one of the reload regs.
65 Reload regs are allocated locally for every instruction that needs
66 reloads. When there are pseudos which are allocated to a register that
67 has been chosen as a reload reg, such pseudos must be ``spilled''.
68 This means that they go to other hard regs, or to stack slots if no other
69 available hard regs can be found. Spilling can invalidate more
70 insns, requiring additional need for reloads, so we must keep checking
71 until the process stabilizes.
73 For machines with different classes of registers, we must keep track
74 of the register class needed for each reload, and make sure that
75 we allocate enough reload registers of each class.
77 The file reload.c contains the code that checks one insn for
78 validity and reports the reloads that it needs. This file
79 is in charge of scanning the entire rtl code, accumulating the
80 reload needs, spilling, assigning reload registers to use for
81 fixing up each insn, and generating the new insns to copy values
82 into the reload registers. */
84 /* During reload_as_needed, element N contains a REG rtx for the hard reg
85 into which reg N has been reloaded (perhaps for a previous insn). */
86 static rtx *reg_last_reload_reg;
88 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
89 for an output reload that stores into reg N. */
90 static regset_head reg_has_output_reload;
92 /* Indicates which hard regs are reload-registers for an output reload
93 in the current insn. */
94 static HARD_REG_SET reg_is_output_reload;
96 /* Element N is the constant value to which pseudo reg N is equivalent,
97 or zero if pseudo reg N is not equivalent to a constant.
98 find_reloads looks at this in order to replace pseudo reg N
99 with the constant it stands for. */
100 rtx *reg_equiv_constant;
102 /* Element N is an invariant value to which pseudo reg N is equivalent.
103 eliminate_regs_in_insn uses this to replace pseudos in particular
105 rtx *reg_equiv_invariant;
107 /* Element N is a memory location to which pseudo reg N is equivalent,
108 prior to any register elimination (such as frame pointer to stack
109 pointer). Depending on whether or not it is a valid address, this value
110 is transferred to either reg_equiv_address or reg_equiv_mem. */
111 rtx *reg_equiv_memory_loc;
113 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
114 collector can keep track of what is inside. */
115 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
117 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
118 This is used when the address is not valid as a memory address
119 (because its displacement is too big for the machine.) */
120 rtx *reg_equiv_address;
122 /* Element N is the memory slot to which pseudo reg N is equivalent,
123 or zero if pseudo reg N is not equivalent to a memory slot. */
126 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
127 alternate representations of the location of pseudo reg N. */
128 rtx *reg_equiv_alt_mem_list;
130 /* Widest width in which each pseudo reg is referred to (via subreg). */
131 static unsigned int *reg_max_ref_width;
133 /* Element N is the list of insns that initialized reg N from its equivalent
134 constant or memory slot. */
136 int reg_equiv_init_size;
138 /* Vector to remember old contents of reg_renumber before spilling. */
139 static short *reg_old_renumber;
141 /* During reload_as_needed, element N contains the last pseudo regno reloaded
142 into hard register N. If that pseudo reg occupied more than one register,
143 reg_reloaded_contents points to that pseudo for each spill register in
144 use; all of these must remain set for an inheritance to occur. */
145 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
147 /* During reload_as_needed, element N contains the insn for which
148 hard register N was last used. Its contents are significant only
149 when reg_reloaded_valid is set for this register. */
150 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
152 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
153 static HARD_REG_SET reg_reloaded_valid;
154 /* Indicate if the register was dead at the end of the reload.
155 This is only valid if reg_reloaded_contents is set and valid. */
156 static HARD_REG_SET reg_reloaded_dead;
158 /* Indicate whether the register's current value is one that is not
159 safe to retain across a call, even for registers that are normally
161 static HARD_REG_SET reg_reloaded_call_part_clobbered;
163 /* Number of spill-regs so far; number of valid elements of spill_regs. */
166 /* In parallel with spill_regs, contains REG rtx's for those regs.
167 Holds the last rtx used for any given reg, or 0 if it has never
168 been used for spilling yet. This rtx is reused, provided it has
170 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
172 /* In parallel with spill_regs, contains nonzero for a spill reg
173 that was stored after the last time it was used.
174 The precise value is the insn generated to do the store. */
175 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
177 /* This is the register that was stored with spill_reg_store. This is a
178 copy of reload_out / reload_out_reg when the value was stored; if
179 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
180 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
182 /* This table is the inverse mapping of spill_regs:
183 indexed by hard reg number,
184 it contains the position of that reg in spill_regs,
185 or -1 for something that is not in spill_regs.
187 ?!? This is no longer accurate. */
188 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
190 /* This reg set indicates registers that can't be used as spill registers for
191 the currently processed insn. These are the hard registers which are live
192 during the insn, but not allocated to pseudos, as well as fixed
194 static HARD_REG_SET bad_spill_regs;
196 /* These are the hard registers that can't be used as spill register for any
197 insn. This includes registers used for user variables and registers that
198 we can't eliminate. A register that appears in this set also can't be used
199 to retry register allocation. */
200 static HARD_REG_SET bad_spill_regs_global;
202 /* Describes order of use of registers for reloading
203 of spilled pseudo-registers. `n_spills' is the number of
204 elements that are actually valid; new ones are added at the end.
206 Both spill_regs and spill_reg_order are used on two occasions:
207 once during find_reload_regs, where they keep track of the spill registers
208 for a single insn, but also during reload_as_needed where they show all
209 the registers ever used by reload. For the latter case, the information
210 is calculated during finish_spills. */
211 static short spill_regs[FIRST_PSEUDO_REGISTER];
213 /* This vector of reg sets indicates, for each pseudo, which hard registers
214 may not be used for retrying global allocation because the register was
215 formerly spilled from one of them. If we allowed reallocating a pseudo to
216 a register that it was already allocated to, reload might not
218 static HARD_REG_SET *pseudo_previous_regs;
220 /* This vector of reg sets indicates, for each pseudo, which hard
221 registers may not be used for retrying global allocation because they
222 are used as spill registers during one of the insns in which the
224 static HARD_REG_SET *pseudo_forbidden_regs;
226 /* All hard regs that have been used as spill registers for any insn are
227 marked in this set. */
228 static HARD_REG_SET used_spill_regs;
230 /* Index of last register assigned as a spill register. We allocate in
231 a round-robin fashion. */
232 static int last_spill_reg;
234 /* Nonzero if indirect addressing is supported on the machine; this means
235 that spilling (REG n) does not require reloading it into a register in
236 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
237 value indicates the level of indirect addressing supported, e.g., two
238 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
240 static char spill_indirect_levels;
242 /* Nonzero if indirect addressing is supported when the innermost MEM is
243 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
244 which these are valid is the same as spill_indirect_levels, above. */
245 char indirect_symref_ok;
247 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
248 char double_reg_address_ok;
250 /* Record the stack slot for each spilled hard register. */
251 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
253 /* Width allocated so far for that stack slot. */
254 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
256 /* Record which pseudos needed to be spilled. */
257 static regset_head spilled_pseudos;
259 /* Used for communication between order_regs_for_reload and count_pseudo.
260 Used to avoid counting one pseudo twice. */
261 static regset_head pseudos_counted;
263 /* First uid used by insns created by reload in this function.
264 Used in find_equiv_reg. */
265 int reload_first_uid;
267 /* Flag set by local-alloc or global-alloc if anything is live in
268 a call-clobbered reg across calls. */
269 int caller_save_needed;
271 /* Set to 1 while reload_as_needed is operating.
272 Required by some machines to handle any generated moves differently. */
273 int reload_in_progress = 0;
275 /* These arrays record the insn_code of insns that may be needed to
276 perform input and output reloads of special objects. They provide a
277 place to pass a scratch register. */
278 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
279 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
281 /* This obstack is used for allocation of rtl during register elimination.
282 The allocated storage can be freed once find_reloads has processed the
284 static struct obstack reload_obstack;
286 /* Points to the beginning of the reload_obstack. All insn_chain structures
287 are allocated first. */
288 static char *reload_startobj;
290 /* The point after all insn_chain structures. Used to quickly deallocate
291 memory allocated in copy_reloads during calculate_needs_all_insns. */
292 static char *reload_firstobj;
294 /* This points before all local rtl generated by register elimination.
295 Used to quickly free all memory after processing one insn. */
296 static char *reload_insn_firstobj;
298 /* List of insn_chain instructions, one for every insn that reload needs to
300 struct insn_chain *reload_insn_chain;
302 /* List of all insns needing reloads. */
303 static struct insn_chain *insns_need_reload;
305 /* This structure is used to record information about register eliminations.
306 Each array entry describes one possible way of eliminating a register
307 in favor of another. If there is more than one way of eliminating a
308 particular register, the most preferred should be specified first. */
312 int from; /* Register number to be eliminated. */
313 int to; /* Register number used as replacement. */
314 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
315 int can_eliminate; /* Nonzero if this elimination can be done. */
316 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
317 insns made by reload. */
318 HOST_WIDE_INT offset; /* Current offset between the two regs. */
319 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
320 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
321 rtx from_rtx; /* REG rtx for the register to be eliminated.
322 We cannot simply compare the number since
323 we might then spuriously replace a hard
324 register corresponding to a pseudo
325 assigned to the reg to be eliminated. */
326 rtx to_rtx; /* REG rtx for the replacement. */
329 static struct elim_table *reg_eliminate = 0;
331 /* This is an intermediate structure to initialize the table. It has
332 exactly the members provided by ELIMINABLE_REGS. */
333 static const struct elim_table_1
337 } reg_eliminate_1[] =
339 /* If a set of eliminable registers was specified, define the table from it.
340 Otherwise, default to the normal case of the frame pointer being
341 replaced by the stack pointer. */
343 #ifdef ELIMINABLE_REGS
346 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
349 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
351 /* Record the number of pending eliminations that have an offset not equal
352 to their initial offset. If nonzero, we use a new copy of each
353 replacement result in any insns encountered. */
354 int num_not_at_initial_offset;
356 /* Count the number of registers that we may be able to eliminate. */
357 static int num_eliminable;
358 /* And the number of registers that are equivalent to a constant that
359 can be eliminated to frame_pointer / arg_pointer + constant. */
360 static int num_eliminable_invariants;
362 /* For each label, we record the offset of each elimination. If we reach
363 a label by more than one path and an offset differs, we cannot do the
364 elimination. This information is indexed by the difference of the
365 number of the label and the first label number. We can't offset the
366 pointer itself as this can cause problems on machines with segmented
367 memory. The first table is an array of flags that records whether we
368 have yet encountered a label and the second table is an array of arrays,
369 one entry in the latter array for each elimination. */
371 static int first_label_num;
372 static char *offsets_known_at;
373 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
375 /* Number of labels in the current function. */
377 static int num_labels;
379 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
380 static void maybe_fix_stack_asms (void);
381 static void copy_reloads (struct insn_chain *);
382 static void calculate_needs_all_insns (int);
383 static int find_reg (struct insn_chain *, int);
384 static void find_reload_regs (struct insn_chain *);
385 static void select_reload_regs (void);
386 static void delete_caller_save_insns (void);
388 static void spill_failure (rtx, enum reg_class);
389 static void count_spilled_pseudo (int, int, int);
390 static void delete_dead_insn (rtx);
391 static void alter_reg (int, int);
392 static void set_label_offsets (rtx, rtx, int);
393 static void check_eliminable_occurrences (rtx);
394 static void elimination_effects (rtx, enum machine_mode);
395 static int eliminate_regs_in_insn (rtx, int);
396 static void update_eliminable_offsets (void);
397 static void mark_not_eliminable (rtx, rtx, void *);
398 static void set_initial_elim_offsets (void);
399 static bool verify_initial_elim_offsets (void);
400 static void set_initial_label_offsets (void);
401 static void set_offsets_for_label (rtx);
402 static void init_elim_table (void);
403 static void update_eliminables (HARD_REG_SET *);
404 static void spill_hard_reg (unsigned int, int);
405 static int finish_spills (int);
406 static void scan_paradoxical_subregs (rtx);
407 static void count_pseudo (int);
408 static void order_regs_for_reload (struct insn_chain *);
409 static void reload_as_needed (int);
410 static void forget_old_reloads_1 (rtx, rtx, void *);
411 static void forget_marked_reloads (regset);
412 static int reload_reg_class_lower (const void *, const void *);
413 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
415 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
417 static int reload_reg_free_p (unsigned int, int, enum reload_type);
418 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
420 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
422 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
423 static int allocate_reload_reg (struct insn_chain *, int, int);
424 static int conflicts_with_override (rtx);
425 static void failed_reload (rtx, int);
426 static int set_reload_reg (int, int);
427 static void choose_reload_regs_init (struct insn_chain *, rtx *);
428 static void choose_reload_regs (struct insn_chain *);
429 static void merge_assigned_reloads (rtx);
430 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
432 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
434 static void do_input_reload (struct insn_chain *, struct reload *, int);
435 static void do_output_reload (struct insn_chain *, struct reload *, int);
436 static bool inherit_piecemeal_p (int, int);
437 static void emit_reload_insns (struct insn_chain *);
438 static void delete_output_reload (rtx, int, int);
439 static void delete_address_reloads (rtx, rtx);
440 static void delete_address_reloads_1 (rtx, rtx, rtx);
441 static rtx inc_for_reload (rtx, rtx, rtx, int);
443 static void add_auto_inc_notes (rtx, rtx);
445 static void copy_eh_notes (rtx, rtx);
446 static int reloads_conflict (int, int);
447 static rtx gen_reload (rtx, rtx, int, enum reload_type);
448 static rtx emit_insn_if_valid_for_reload (rtx);
450 /* Initialize the reload pass once per compilation. */
457 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
458 Set spill_indirect_levels to the number of levels such addressing is
459 permitted, zero if it is not permitted at all. */
462 = gen_rtx_MEM (Pmode,
465 LAST_VIRTUAL_REGISTER + 1),
467 spill_indirect_levels = 0;
469 while (memory_address_p (QImode, tem))
471 spill_indirect_levels++;
472 tem = gen_rtx_MEM (Pmode, tem);
475 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
477 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
478 indirect_symref_ok = memory_address_p (QImode, tem);
480 /* See if reg+reg is a valid (and offsettable) address. */
482 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
484 tem = gen_rtx_PLUS (Pmode,
485 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
486 gen_rtx_REG (Pmode, i));
488 /* This way, we make sure that reg+reg is an offsettable address. */
489 tem = plus_constant (tem, 4);
491 if (memory_address_p (QImode, tem))
493 double_reg_address_ok = 1;
498 /* Initialize obstack for our rtl allocation. */
499 gcc_obstack_init (&reload_obstack);
500 reload_startobj = obstack_alloc (&reload_obstack, 0);
502 INIT_REG_SET (&spilled_pseudos);
503 INIT_REG_SET (&pseudos_counted);
506 /* List of insn chains that are currently unused. */
507 static struct insn_chain *unused_insn_chains = 0;
509 /* Allocate an empty insn_chain structure. */
511 new_insn_chain (void)
513 struct insn_chain *c;
515 if (unused_insn_chains == 0)
517 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
518 INIT_REG_SET (&c->live_throughout);
519 INIT_REG_SET (&c->dead_or_set);
523 c = unused_insn_chains;
524 unused_insn_chains = c->next;
526 c->is_caller_save_insn = 0;
527 c->need_operand_change = 0;
533 /* Small utility function to set all regs in hard reg set TO which are
534 allocated to pseudos in regset FROM. */
537 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
540 reg_set_iterator rsi;
542 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
544 int r = reg_renumber[regno];
549 /* reload_combine uses the information from
550 BASIC_BLOCK->global_live_at_start, which might still
551 contain registers that have not actually been allocated
552 since they have an equivalence. */
553 gcc_assert (reload_completed);
557 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)];
559 SET_HARD_REG_BIT (*to, r + nregs);
564 /* Replace all pseudos found in LOC with their corresponding
568 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
581 unsigned int regno = REGNO (x);
583 if (regno < FIRST_PSEUDO_REGISTER)
586 x = eliminate_regs (x, mem_mode, usage);
590 replace_pseudos_in (loc, mem_mode, usage);
594 if (reg_equiv_constant[regno])
595 *loc = reg_equiv_constant[regno];
596 else if (reg_equiv_mem[regno])
597 *loc = reg_equiv_mem[regno];
598 else if (reg_equiv_address[regno])
599 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
602 gcc_assert (!REG_P (regno_reg_rtx[regno])
603 || REGNO (regno_reg_rtx[regno]) != regno);
604 *loc = regno_reg_rtx[regno];
609 else if (code == MEM)
611 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
615 /* Process each of our operands recursively. */
616 fmt = GET_RTX_FORMAT (code);
617 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
619 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
620 else if (*fmt == 'E')
621 for (j = 0; j < XVECLEN (x, i); j++)
622 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
626 /* Global variables used by reload and its subroutines. */
628 /* Set during calculate_needs if an insn needs register elimination. */
629 static int something_needs_elimination;
630 /* Set during calculate_needs if an insn needs an operand changed. */
631 static int something_needs_operands_changed;
633 /* Nonzero means we couldn't get enough spill regs. */
636 /* Main entry point for the reload pass.
638 FIRST is the first insn of the function being compiled.
640 GLOBAL nonzero means we were called from global_alloc
641 and should attempt to reallocate any pseudoregs that we
642 displace from hard regs we will use for reloads.
643 If GLOBAL is zero, we do not have enough information to do that,
644 so any pseudo reg that is spilled must go to the stack.
646 Return value is nonzero if reload failed
647 and we must not do any more for this function. */
650 reload (rtx first, int global)
654 struct elim_table *ep;
657 /* Make sure even insns with volatile mem refs are recognizable. */
662 reload_firstobj = obstack_alloc (&reload_obstack, 0);
664 /* Make sure that the last insn in the chain
665 is not something that needs reloading. */
666 emit_note (NOTE_INSN_DELETED);
668 /* Enable find_equiv_reg to distinguish insns made by reload. */
669 reload_first_uid = get_max_uid ();
671 #ifdef SECONDARY_MEMORY_NEEDED
672 /* Initialize the secondary memory table. */
673 clear_secondary_mem ();
676 /* We don't have a stack slot for any spill reg yet. */
677 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
678 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
680 /* Initialize the save area information for caller-save, in case some
684 /* Compute which hard registers are now in use
685 as homes for pseudo registers.
686 This is done here rather than (eg) in global_alloc
687 because this point is reached even if not optimizing. */
688 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
691 /* A function that receives a nonlocal goto must save all call-saved
693 if (current_function_has_nonlocal_label)
694 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
695 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
696 regs_ever_live[i] = 1;
698 /* Find all the pseudo registers that didn't get hard regs
699 but do have known equivalent constants or memory slots.
700 These include parameters (known equivalent to parameter slots)
701 and cse'd or loop-moved constant memory addresses.
703 Record constant equivalents in reg_equiv_constant
704 so they will be substituted by find_reloads.
705 Record memory equivalents in reg_mem_equiv so they can
706 be substituted eventually by altering the REG-rtx's. */
708 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
709 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
710 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
711 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
712 reg_equiv_address = XCNEWVEC (rtx, max_regno);
713 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
714 reg_old_renumber = XCNEWVEC (short, max_regno);
715 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
716 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
717 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
719 CLEAR_HARD_REG_SET (bad_spill_regs_global);
721 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
722 to. Also find all paradoxical subregs and find largest such for
725 num_eliminable_invariants = 0;
726 for (insn = first; insn; insn = NEXT_INSN (insn))
728 rtx set = single_set (insn);
730 /* We may introduce USEs that we want to remove at the end, so
731 we'll mark them with QImode. Make sure there are no
732 previously-marked insns left by say regmove. */
733 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
734 && GET_MODE (insn) != VOIDmode)
735 PUT_MODE (insn, VOIDmode);
738 scan_paradoxical_subregs (PATTERN (insn));
740 if (set != 0 && REG_P (SET_DEST (set)))
742 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
748 i = REGNO (SET_DEST (set));
751 if (i <= LAST_VIRTUAL_REGISTER)
754 if (! function_invariant_p (x)
756 /* A function invariant is often CONSTANT_P but may
757 include a register. We promise to only pass
758 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
760 && LEGITIMATE_PIC_OPERAND_P (x)))
762 /* It can happen that a REG_EQUIV note contains a MEM
763 that is not a legitimate memory operand. As later
764 stages of reload assume that all addresses found
765 in the reg_equiv_* arrays were originally legitimate,
766 we ignore such REG_EQUIV notes. */
767 if (memory_operand (x, VOIDmode))
769 /* Always unshare the equivalence, so we can
770 substitute into this insn without touching the
772 reg_equiv_memory_loc[i] = copy_rtx (x);
774 else if (function_invariant_p (x))
776 if (GET_CODE (x) == PLUS)
778 /* This is PLUS of frame pointer and a constant,
779 and might be shared. Unshare it. */
780 reg_equiv_invariant[i] = copy_rtx (x);
781 num_eliminable_invariants++;
783 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
785 reg_equiv_invariant[i] = x;
786 num_eliminable_invariants++;
788 else if (LEGITIMATE_CONSTANT_P (x))
789 reg_equiv_constant[i] = x;
792 reg_equiv_memory_loc[i]
793 = force_const_mem (GET_MODE (SET_DEST (set)), x);
794 if (! reg_equiv_memory_loc[i])
795 reg_equiv_init[i] = NULL_RTX;
800 reg_equiv_init[i] = NULL_RTX;
805 reg_equiv_init[i] = NULL_RTX;
810 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
811 if (reg_equiv_init[i])
813 fprintf (dump_file, "init_insns for %u: ", i);
814 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
815 fprintf (dump_file, "\n");
820 first_label_num = get_first_label_num ();
821 num_labels = max_label_num () - first_label_num;
823 /* Allocate the tables used to store offset information at labels. */
824 /* We used to use alloca here, but the size of what it would try to
825 allocate would occasionally cause it to exceed the stack limit and
826 cause a core dump. */
827 offsets_known_at = XNEWVEC (char, num_labels);
828 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
830 /* Alter each pseudo-reg rtx to contain its hard reg number.
831 Assign stack slots to the pseudos that lack hard regs or equivalents.
832 Do not touch virtual registers. */
834 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
837 /* If we have some registers we think can be eliminated, scan all insns to
838 see if there is an insn that sets one of these registers to something
839 other than itself plus a constant. If so, the register cannot be
840 eliminated. Doing this scan here eliminates an extra pass through the
841 main reload loop in the most common case where register elimination
843 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
845 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
847 maybe_fix_stack_asms ();
849 insns_need_reload = 0;
850 something_needs_elimination = 0;
852 /* Initialize to -1, which means take the first spill register. */
855 /* Spill any hard regs that we know we can't eliminate. */
856 CLEAR_HARD_REG_SET (used_spill_regs);
857 /* There can be multiple ways to eliminate a register;
858 they should be listed adjacently.
859 Elimination for any register fails only if all possible ways fail. */
860 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
863 int can_eliminate = 0;
866 can_eliminate |= ep->can_eliminate;
869 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
871 spill_hard_reg (from, 1);
874 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
875 if (frame_pointer_needed)
876 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
878 finish_spills (global);
880 /* From now on, we may need to generate moves differently. We may also
881 allow modifications of insns which cause them to not be recognized.
882 Any such modifications will be cleaned up during reload itself. */
883 reload_in_progress = 1;
885 /* This loop scans the entire function each go-round
886 and repeats until one repetition spills no additional hard regs. */
889 int something_changed;
891 HOST_WIDE_INT starting_frame_size;
893 starting_frame_size = get_frame_size ();
895 set_initial_elim_offsets ();
896 set_initial_label_offsets ();
898 /* For each pseudo register that has an equivalent location defined,
899 try to eliminate any eliminable registers (such as the frame pointer)
900 assuming initial offsets for the replacement register, which
903 If the resulting location is directly addressable, substitute
904 the MEM we just got directly for the old REG.
906 If it is not addressable but is a constant or the sum of a hard reg
907 and constant, it is probably not addressable because the constant is
908 out of range, in that case record the address; we will generate
909 hairy code to compute the address in a register each time it is
910 needed. Similarly if it is a hard register, but one that is not
911 valid as an address register.
913 If the location is not addressable, but does not have one of the
914 above forms, assign a stack slot. We have to do this to avoid the
915 potential of producing lots of reloads if, e.g., a location involves
916 a pseudo that didn't get a hard register and has an equivalent memory
917 location that also involves a pseudo that didn't get a hard register.
919 Perhaps at some point we will improve reload_when_needed handling
920 so this problem goes away. But that's very hairy. */
922 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
923 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
925 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
927 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
929 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
930 else if (CONSTANT_P (XEXP (x, 0))
931 || (REG_P (XEXP (x, 0))
932 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
933 || (GET_CODE (XEXP (x, 0)) == PLUS
934 && REG_P (XEXP (XEXP (x, 0), 0))
935 && (REGNO (XEXP (XEXP (x, 0), 0))
936 < FIRST_PSEUDO_REGISTER)
937 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
938 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
941 /* Make a new stack slot. Then indicate that something
942 changed so we go back and recompute offsets for
943 eliminable registers because the allocation of memory
944 below might change some offset. reg_equiv_{mem,address}
945 will be set up for this pseudo on the next pass around
947 reg_equiv_memory_loc[i] = 0;
948 reg_equiv_init[i] = 0;
953 if (caller_save_needed)
956 /* If we allocated another stack slot, redo elimination bookkeeping. */
957 if (starting_frame_size != get_frame_size ())
959 if (starting_frame_size && cfun->stack_alignment_needed)
961 /* If we have a stack frame, we must align it now. The
962 stack size may be a part of the offset computation for
963 register elimination. So if this changes the stack size,
964 then repeat the elimination bookkeeping. We don't
965 realign when there is no stack, as that will cause a
966 stack frame when none is needed should
967 STARTING_FRAME_OFFSET not be already aligned to
969 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
970 if (starting_frame_size != get_frame_size ())
974 if (caller_save_needed)
976 save_call_clobbered_regs ();
977 /* That might have allocated new insn_chain structures. */
978 reload_firstobj = obstack_alloc (&reload_obstack, 0);
981 calculate_needs_all_insns (global);
983 CLEAR_REG_SET (&spilled_pseudos);
986 something_changed = 0;
988 /* If we allocated any new memory locations, make another pass
989 since it might have changed elimination offsets. */
990 if (starting_frame_size != get_frame_size ())
991 something_changed = 1;
993 /* Even if the frame size remained the same, we might still have
994 changed elimination offsets, e.g. if find_reloads called
995 force_const_mem requiring the back end to allocate a constant
996 pool base register that needs to be saved on the stack. */
997 else if (!verify_initial_elim_offsets ())
998 something_changed = 1;
1001 HARD_REG_SET to_spill;
1002 CLEAR_HARD_REG_SET (to_spill);
1003 update_eliminables (&to_spill);
1004 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
1006 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1007 if (TEST_HARD_REG_BIT (to_spill, i))
1009 spill_hard_reg (i, 1);
1012 /* Regardless of the state of spills, if we previously had
1013 a register that we thought we could eliminate, but now can
1014 not eliminate, we must run another pass.
1016 Consider pseudos which have an entry in reg_equiv_* which
1017 reference an eliminable register. We must make another pass
1018 to update reg_equiv_* so that we do not substitute in the
1019 old value from when we thought the elimination could be
1021 something_changed = 1;
1025 select_reload_regs ();
1029 if (insns_need_reload != 0 || did_spill)
1030 something_changed |= finish_spills (global);
1032 if (! something_changed)
1035 if (caller_save_needed)
1036 delete_caller_save_insns ();
1038 obstack_free (&reload_obstack, reload_firstobj);
1041 /* If global-alloc was run, notify it of any register eliminations we have
1044 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1045 if (ep->can_eliminate)
1046 mark_elimination (ep->from, ep->to);
1048 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1049 If that insn didn't set the register (i.e., it copied the register to
1050 memory), just delete that insn instead of the equivalencing insn plus
1051 anything now dead. If we call delete_dead_insn on that insn, we may
1052 delete the insn that actually sets the register if the register dies
1053 there and that is incorrect. */
1055 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1057 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1060 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1062 rtx equiv_insn = XEXP (list, 0);
1064 /* If we already deleted the insn or if it may trap, we can't
1065 delete it. The latter case shouldn't happen, but can
1066 if an insn has a variable address, gets a REG_EH_REGION
1067 note added to it, and then gets converted into a load
1068 from a constant address. */
1069 if (NOTE_P (equiv_insn)
1070 || can_throw_internal (equiv_insn))
1072 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1073 delete_dead_insn (equiv_insn);
1075 SET_INSN_DELETED (equiv_insn);
1080 /* Use the reload registers where necessary
1081 by generating move instructions to move the must-be-register
1082 values into or out of the reload registers. */
1084 if (insns_need_reload != 0 || something_needs_elimination
1085 || something_needs_operands_changed)
1087 HOST_WIDE_INT old_frame_size = get_frame_size ();
1089 reload_as_needed (global);
1091 gcc_assert (old_frame_size == get_frame_size ());
1093 gcc_assert (verify_initial_elim_offsets ());
1096 /* If we were able to eliminate the frame pointer, show that it is no
1097 longer live at the start of any basic block. If it ls live by
1098 virtue of being in a pseudo, that pseudo will be marked live
1099 and hence the frame pointer will be known to be live via that
1102 if (! frame_pointer_needed)
1104 CLEAR_REGNO_REG_SET (bb->il.rtl->global_live_at_start,
1105 HARD_FRAME_POINTER_REGNUM);
1107 /* Come here (with failure set nonzero) if we can't get enough spill
1111 CLEAR_REG_SET (&spilled_pseudos);
1112 reload_in_progress = 0;
1114 /* Now eliminate all pseudo regs by modifying them into
1115 their equivalent memory references.
1116 The REG-rtx's for the pseudos are modified in place,
1117 so all insns that used to refer to them now refer to memory.
1119 For a reg that has a reg_equiv_address, all those insns
1120 were changed by reloading so that no insns refer to it any longer;
1121 but the DECL_RTL of a variable decl may refer to it,
1122 and if so this causes the debugging info to mention the variable. */
1124 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1128 if (reg_equiv_mem[i])
1129 addr = XEXP (reg_equiv_mem[i], 0);
1131 if (reg_equiv_address[i])
1132 addr = reg_equiv_address[i];
1136 if (reg_renumber[i] < 0)
1138 rtx reg = regno_reg_rtx[i];
1140 REG_USERVAR_P (reg) = 0;
1141 PUT_CODE (reg, MEM);
1142 XEXP (reg, 0) = addr;
1143 if (reg_equiv_memory_loc[i])
1144 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1147 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1148 MEM_ATTRS (reg) = 0;
1150 MEM_NOTRAP_P (reg) = 1;
1152 else if (reg_equiv_mem[i])
1153 XEXP (reg_equiv_mem[i], 0) = addr;
1157 /* We must set reload_completed now since the cleanup_subreg_operands call
1158 below will re-recognize each insn and reload may have generated insns
1159 which are only valid during and after reload. */
1160 reload_completed = 1;
1162 /* Make a pass over all the insns and delete all USEs which we inserted
1163 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1164 notes. Delete all CLOBBER insns, except those that refer to the return
1165 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1166 from misarranging variable-array code, and simplify (subreg (reg))
1167 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1168 are no longer useful or accurate. Strip and regenerate REG_INC notes
1169 that may have been moved around. */
1171 for (insn = first; insn; insn = NEXT_INSN (insn))
1176 /* Clean up invalid ASMs so that they don't confuse later passes.
1178 if (asm_noperands (PATTERN (insn)) >= 0)
1180 extract_insn (insn);
1181 if (!constrain_operands (1))
1183 error_for_asm (insn,
1184 "%<asm%> operand has impossible constraints");
1191 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1192 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1194 if ((GET_CODE (PATTERN (insn)) == USE
1195 /* We mark with QImode USEs introduced by reload itself. */
1196 && (GET_MODE (insn) == QImode
1197 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1198 || (GET_CODE (PATTERN (insn)) == CLOBBER
1199 && (!MEM_P (XEXP (PATTERN (insn), 0))
1200 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1201 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1202 && XEXP (XEXP (PATTERN (insn), 0), 0)
1203 != stack_pointer_rtx))
1204 && (!REG_P (XEXP (PATTERN (insn), 0))
1205 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1211 /* Some CLOBBERs may survive until here and still reference unassigned
1212 pseudos with const equivalent, which may in turn cause ICE in later
1213 passes if the reference remains in place. */
1214 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1215 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1216 VOIDmode, PATTERN (insn));
1218 /* Discard obvious no-ops, even without -O. This optimization
1219 is fast and doesn't interfere with debugging. */
1220 if (NONJUMP_INSN_P (insn)
1221 && GET_CODE (PATTERN (insn)) == SET
1222 && REG_P (SET_SRC (PATTERN (insn)))
1223 && REG_P (SET_DEST (PATTERN (insn)))
1224 && (REGNO (SET_SRC (PATTERN (insn)))
1225 == REGNO (SET_DEST (PATTERN (insn)))))
1231 pnote = ®_NOTES (insn);
1234 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1235 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1236 || REG_NOTE_KIND (*pnote) == REG_INC
1237 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1238 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1239 *pnote = XEXP (*pnote, 1);
1241 pnote = &XEXP (*pnote, 1);
1245 add_auto_inc_notes (insn, PATTERN (insn));
1248 /* And simplify (subreg (reg)) if it appears as an operand. */
1249 cleanup_subreg_operands (insn);
1252 /* If we are doing stack checking, give a warning if this function's
1253 frame size is larger than we expect. */
1254 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1256 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1257 static int verbose_warned = 0;
1259 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1260 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1261 size += UNITS_PER_WORD;
1263 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1265 warning (0, "frame size too large for reliable stack checking");
1266 if (! verbose_warned)
1268 warning (0, "try reducing the number of local variables");
1274 /* Indicate that we no longer have known memory locations or constants. */
1275 if (reg_equiv_constant)
1276 free (reg_equiv_constant);
1277 if (reg_equiv_invariant)
1278 free (reg_equiv_invariant);
1279 reg_equiv_constant = 0;
1280 reg_equiv_invariant = 0;
1281 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
1282 reg_equiv_memory_loc = 0;
1284 if (offsets_known_at)
1285 free (offsets_known_at);
1289 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1290 if (reg_equiv_alt_mem_list[i])
1291 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
1292 free (reg_equiv_alt_mem_list);
1294 free (reg_equiv_mem);
1296 free (reg_equiv_address);
1297 free (reg_max_ref_width);
1298 free (reg_old_renumber);
1299 free (pseudo_previous_regs);
1300 free (pseudo_forbidden_regs);
1302 CLEAR_HARD_REG_SET (used_spill_regs);
1303 for (i = 0; i < n_spills; i++)
1304 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1306 /* Free all the insn_chain structures at once. */
1307 obstack_free (&reload_obstack, reload_startobj);
1308 unused_insn_chains = 0;
1309 fixup_abnormal_edges ();
1311 /* Replacing pseudos with their memory equivalents might have
1312 created shared rtx. Subsequent passes would get confused
1313 by this, so unshare everything here. */
1314 unshare_all_rtl_again (first);
1316 #ifdef STACK_BOUNDARY
1317 /* init_emit has set the alignment of the hard frame pointer
1318 to STACK_BOUNDARY. It is very likely no longer valid if
1319 the hard frame pointer was used for register allocation. */
1320 if (!frame_pointer_needed)
1321 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1327 /* Yet another special case. Unfortunately, reg-stack forces people to
1328 write incorrect clobbers in asm statements. These clobbers must not
1329 cause the register to appear in bad_spill_regs, otherwise we'll call
1330 fatal_insn later. We clear the corresponding regnos in the live
1331 register sets to avoid this.
1332 The whole thing is rather sick, I'm afraid. */
1335 maybe_fix_stack_asms (void)
1338 const char *constraints[MAX_RECOG_OPERANDS];
1339 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1340 struct insn_chain *chain;
1342 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1345 HARD_REG_SET clobbered, allowed;
1348 if (! INSN_P (chain->insn)
1349 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1351 pat = PATTERN (chain->insn);
1352 if (GET_CODE (pat) != PARALLEL)
1355 CLEAR_HARD_REG_SET (clobbered);
1356 CLEAR_HARD_REG_SET (allowed);
1358 /* First, make a mask of all stack regs that are clobbered. */
1359 for (i = 0; i < XVECLEN (pat, 0); i++)
1361 rtx t = XVECEXP (pat, 0, i);
1362 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1363 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1366 /* Get the operand values and constraints out of the insn. */
1367 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1368 constraints, operand_mode);
1370 /* For every operand, see what registers are allowed. */
1371 for (i = 0; i < noperands; i++)
1373 const char *p = constraints[i];
1374 /* For every alternative, we compute the class of registers allowed
1375 for reloading in CLS, and merge its contents into the reg set
1377 int cls = (int) NO_REGS;
1383 if (c == '\0' || c == ',' || c == '#')
1385 /* End of one alternative - mark the regs in the current
1386 class, and reset the class. */
1387 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1393 } while (c != '\0' && c != ',');
1401 case '=': case '+': case '*': case '%': case '?': case '!':
1402 case '0': case '1': case '2': case '3': case '4': case 'm':
1403 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1404 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1405 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1410 cls = (int) reg_class_subunion[cls]
1411 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1416 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1420 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1421 cls = (int) reg_class_subunion[cls]
1422 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1424 cls = (int) reg_class_subunion[cls]
1425 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1427 p += CONSTRAINT_LEN (c, p);
1430 /* Those of the registers which are clobbered, but allowed by the
1431 constraints, must be usable as reload registers. So clear them
1432 out of the life information. */
1433 AND_HARD_REG_SET (allowed, clobbered);
1434 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1435 if (TEST_HARD_REG_BIT (allowed, i))
1437 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1438 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1445 /* Copy the global variables n_reloads and rld into the corresponding elts
1448 copy_reloads (struct insn_chain *chain)
1450 chain->n_reloads = n_reloads;
1451 chain->rld = obstack_alloc (&reload_obstack,
1452 n_reloads * sizeof (struct reload));
1453 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1454 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1457 /* Walk the chain of insns, and determine for each whether it needs reloads
1458 and/or eliminations. Build the corresponding insns_need_reload list, and
1459 set something_needs_elimination as appropriate. */
1461 calculate_needs_all_insns (int global)
1463 struct insn_chain **pprev_reload = &insns_need_reload;
1464 struct insn_chain *chain, *next = 0;
1466 something_needs_elimination = 0;
1468 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1469 for (chain = reload_insn_chain; chain != 0; chain = next)
1471 rtx insn = chain->insn;
1475 /* Clear out the shortcuts. */
1476 chain->n_reloads = 0;
1477 chain->need_elim = 0;
1478 chain->need_reload = 0;
1479 chain->need_operand_change = 0;
1481 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1482 include REG_LABEL), we need to see what effects this has on the
1483 known offsets at labels. */
1485 if (LABEL_P (insn) || JUMP_P (insn)
1486 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1487 set_label_offsets (insn, insn, 0);
1491 rtx old_body = PATTERN (insn);
1492 int old_code = INSN_CODE (insn);
1493 rtx old_notes = REG_NOTES (insn);
1494 int did_elimination = 0;
1495 int operands_changed = 0;
1496 rtx set = single_set (insn);
1498 /* Skip insns that only set an equivalence. */
1499 if (set && REG_P (SET_DEST (set))
1500 && reg_renumber[REGNO (SET_DEST (set))] < 0
1501 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1502 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1503 && reg_equiv_init[REGNO (SET_DEST (set))])
1506 /* If needed, eliminate any eliminable registers. */
1507 if (num_eliminable || num_eliminable_invariants)
1508 did_elimination = eliminate_regs_in_insn (insn, 0);
1510 /* Analyze the instruction. */
1511 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1512 global, spill_reg_order);
1514 /* If a no-op set needs more than one reload, this is likely
1515 to be something that needs input address reloads. We
1516 can't get rid of this cleanly later, and it is of no use
1517 anyway, so discard it now.
1518 We only do this when expensive_optimizations is enabled,
1519 since this complements reload inheritance / output
1520 reload deletion, and it can make debugging harder. */
1521 if (flag_expensive_optimizations && n_reloads > 1)
1523 rtx set = single_set (insn);
1525 && SET_SRC (set) == SET_DEST (set)
1526 && REG_P (SET_SRC (set))
1527 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1530 /* Delete it from the reload chain. */
1532 chain->prev->next = next;
1534 reload_insn_chain = next;
1536 next->prev = chain->prev;
1537 chain->next = unused_insn_chains;
1538 unused_insn_chains = chain;
1543 update_eliminable_offsets ();
1545 /* Remember for later shortcuts which insns had any reloads or
1546 register eliminations. */
1547 chain->need_elim = did_elimination;
1548 chain->need_reload = n_reloads > 0;
1549 chain->need_operand_change = operands_changed;
1551 /* Discard any register replacements done. */
1552 if (did_elimination)
1554 obstack_free (&reload_obstack, reload_insn_firstobj);
1555 PATTERN (insn) = old_body;
1556 INSN_CODE (insn) = old_code;
1557 REG_NOTES (insn) = old_notes;
1558 something_needs_elimination = 1;
1561 something_needs_operands_changed |= operands_changed;
1565 copy_reloads (chain);
1566 *pprev_reload = chain;
1567 pprev_reload = &chain->next_need_reload;
1574 /* Comparison function for qsort to decide which of two reloads
1575 should be handled first. *P1 and *P2 are the reload numbers. */
1578 reload_reg_class_lower (const void *r1p, const void *r2p)
1580 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1583 /* Consider required reloads before optional ones. */
1584 t = rld[r1].optional - rld[r2].optional;
1588 /* Count all solitary classes before non-solitary ones. */
1589 t = ((reg_class_size[(int) rld[r2].class] == 1)
1590 - (reg_class_size[(int) rld[r1].class] == 1));
1594 /* Aside from solitaires, consider all multi-reg groups first. */
1595 t = rld[r2].nregs - rld[r1].nregs;
1599 /* Consider reloads in order of increasing reg-class number. */
1600 t = (int) rld[r1].class - (int) rld[r2].class;
1604 /* If reloads are equally urgent, sort by reload number,
1605 so that the results of qsort leave nothing to chance. */
1609 /* The cost of spilling each hard reg. */
1610 static int spill_cost[FIRST_PSEUDO_REGISTER];
1612 /* When spilling multiple hard registers, we use SPILL_COST for the first
1613 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1614 only the first hard reg for a multi-reg pseudo. */
1615 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1617 /* Update the spill cost arrays, considering that pseudo REG is live. */
1620 count_pseudo (int reg)
1622 int freq = REG_FREQ (reg);
1623 int r = reg_renumber[reg];
1626 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1627 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1630 SET_REGNO_REG_SET (&pseudos_counted, reg);
1632 gcc_assert (r >= 0);
1634 spill_add_cost[r] += freq;
1636 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1638 spill_cost[r + nregs] += freq;
1641 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1642 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1645 order_regs_for_reload (struct insn_chain *chain)
1648 HARD_REG_SET used_by_pseudos;
1649 HARD_REG_SET used_by_pseudos2;
1650 reg_set_iterator rsi;
1652 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1654 memset (spill_cost, 0, sizeof spill_cost);
1655 memset (spill_add_cost, 0, sizeof spill_add_cost);
1657 /* Count number of uses of each hard reg by pseudo regs allocated to it
1658 and then order them by decreasing use. First exclude hard registers
1659 that are live in or across this insn. */
1661 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1662 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1663 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1664 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1666 /* Now find out which pseudos are allocated to it, and update
1668 CLEAR_REG_SET (&pseudos_counted);
1670 EXECUTE_IF_SET_IN_REG_SET
1671 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1675 EXECUTE_IF_SET_IN_REG_SET
1676 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1680 CLEAR_REG_SET (&pseudos_counted);
1683 /* Vector of reload-numbers showing the order in which the reloads should
1685 static short reload_order[MAX_RELOADS];
1687 /* This is used to keep track of the spill regs used in one insn. */
1688 static HARD_REG_SET used_spill_regs_local;
1690 /* We decided to spill hard register SPILLED, which has a size of
1691 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1692 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1693 update SPILL_COST/SPILL_ADD_COST. */
1696 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1698 int r = reg_renumber[reg];
1699 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1701 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1702 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1705 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1707 spill_add_cost[r] -= REG_FREQ (reg);
1709 spill_cost[r + nregs] -= REG_FREQ (reg);
1712 /* Find reload register to use for reload number ORDER. */
1715 find_reg (struct insn_chain *chain, int order)
1717 int rnum = reload_order[order];
1718 struct reload *rl = rld + rnum;
1719 int best_cost = INT_MAX;
1723 HARD_REG_SET not_usable;
1724 HARD_REG_SET used_by_other_reload;
1725 reg_set_iterator rsi;
1727 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1728 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1729 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1731 CLEAR_HARD_REG_SET (used_by_other_reload);
1732 for (k = 0; k < order; k++)
1734 int other = reload_order[k];
1736 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1737 for (j = 0; j < rld[other].nregs; j++)
1738 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1741 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1743 unsigned int regno = i;
1745 if (! TEST_HARD_REG_BIT (not_usable, regno)
1746 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1747 && HARD_REGNO_MODE_OK (regno, rl->mode))
1749 int this_cost = spill_cost[regno];
1751 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1753 for (j = 1; j < this_nregs; j++)
1755 this_cost += spill_add_cost[regno + j];
1756 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1757 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1762 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1764 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1766 if (this_cost < best_cost
1767 /* Among registers with equal cost, prefer caller-saved ones, or
1768 use REG_ALLOC_ORDER if it is defined. */
1769 || (this_cost == best_cost
1770 #ifdef REG_ALLOC_ORDER
1771 && (inv_reg_alloc_order[regno]
1772 < inv_reg_alloc_order[best_reg])
1774 && call_used_regs[regno]
1775 && ! call_used_regs[best_reg]
1780 best_cost = this_cost;
1788 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1790 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1791 rl->regno = best_reg;
1793 EXECUTE_IF_SET_IN_REG_SET
1794 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1796 count_spilled_pseudo (best_reg, rl->nregs, j);
1799 EXECUTE_IF_SET_IN_REG_SET
1800 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1802 count_spilled_pseudo (best_reg, rl->nregs, j);
1805 for (i = 0; i < rl->nregs; i++)
1807 gcc_assert (spill_cost[best_reg + i] == 0);
1808 gcc_assert (spill_add_cost[best_reg + i] == 0);
1809 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1814 /* Find more reload regs to satisfy the remaining need of an insn, which
1816 Do it by ascending class number, since otherwise a reg
1817 might be spilled for a big class and might fail to count
1818 for a smaller class even though it belongs to that class. */
1821 find_reload_regs (struct insn_chain *chain)
1825 /* In order to be certain of getting the registers we need,
1826 we must sort the reloads into order of increasing register class.
1827 Then our grabbing of reload registers will parallel the process
1828 that provided the reload registers. */
1829 for (i = 0; i < chain->n_reloads; i++)
1831 /* Show whether this reload already has a hard reg. */
1832 if (chain->rld[i].reg_rtx)
1834 int regno = REGNO (chain->rld[i].reg_rtx);
1835 chain->rld[i].regno = regno;
1837 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1840 chain->rld[i].regno = -1;
1841 reload_order[i] = i;
1844 n_reloads = chain->n_reloads;
1845 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1847 CLEAR_HARD_REG_SET (used_spill_regs_local);
1850 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1852 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1854 /* Compute the order of preference for hard registers to spill. */
1856 order_regs_for_reload (chain);
1858 for (i = 0; i < n_reloads; i++)
1860 int r = reload_order[i];
1862 /* Ignore reloads that got marked inoperative. */
1863 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1864 && ! rld[r].optional
1865 && rld[r].regno == -1)
1866 if (! find_reg (chain, i))
1869 fprintf (dump_file, "reload failure for reload %d\n", r);
1870 spill_failure (chain->insn, rld[r].class);
1876 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1877 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1879 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1883 select_reload_regs (void)
1885 struct insn_chain *chain;
1887 /* Try to satisfy the needs for each insn. */
1888 for (chain = insns_need_reload; chain != 0;
1889 chain = chain->next_need_reload)
1890 find_reload_regs (chain);
1893 /* Delete all insns that were inserted by emit_caller_save_insns during
1896 delete_caller_save_insns (void)
1898 struct insn_chain *c = reload_insn_chain;
1902 while (c != 0 && c->is_caller_save_insn)
1904 struct insn_chain *next = c->next;
1907 if (c == reload_insn_chain)
1908 reload_insn_chain = next;
1912 next->prev = c->prev;
1914 c->prev->next = next;
1915 c->next = unused_insn_chains;
1916 unused_insn_chains = c;
1924 /* Handle the failure to find a register to spill.
1925 INSN should be one of the insns which needed this particular spill reg. */
1928 spill_failure (rtx insn, enum reg_class class)
1930 if (asm_noperands (PATTERN (insn)) >= 0)
1931 error_for_asm (insn, "can't find a register in class %qs while "
1932 "reloading %<asm%>",
1933 reg_class_names[class]);
1936 error ("unable to find a register to spill in class %qs",
1937 reg_class_names[class]);
1941 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
1942 debug_reload_to_stream (dump_file);
1944 fatal_insn ("this is the insn:", insn);
1948 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1949 data that is dead in INSN. */
1952 delete_dead_insn (rtx insn)
1954 rtx prev = prev_real_insn (insn);
1957 /* If the previous insn sets a register that dies in our insn, delete it
1959 if (prev && GET_CODE (PATTERN (prev)) == SET
1960 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
1961 && reg_mentioned_p (prev_dest, PATTERN (insn))
1962 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1963 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1964 delete_dead_insn (prev);
1966 SET_INSN_DELETED (insn);
1969 /* Modify the home of pseudo-reg I.
1970 The new home is present in reg_renumber[I].
1972 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1973 or it may be -1, meaning there is none or it is not relevant.
1974 This is used so that all pseudos spilled from a given hard reg
1975 can share one stack slot. */
1978 alter_reg (int i, int from_reg)
1980 /* When outputting an inline function, this can happen
1981 for a reg that isn't actually used. */
1982 if (regno_reg_rtx[i] == 0)
1985 /* If the reg got changed to a MEM at rtl-generation time,
1987 if (!REG_P (regno_reg_rtx[i]))
1990 /* Modify the reg-rtx to contain the new hard reg
1991 number or else to contain its pseudo reg number. */
1992 REGNO (regno_reg_rtx[i])
1993 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1995 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1996 allocate a stack slot for it. */
1998 if (reg_renumber[i] < 0
1999 && REG_N_REFS (i) > 0
2000 && reg_equiv_constant[i] == 0
2001 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
2002 && reg_equiv_memory_loc[i] == 0)
2005 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2006 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2007 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2008 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2009 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2012 /* Each pseudo reg has an inherent size which comes from its own mode,
2013 and a total size which provides room for paradoxical subregs
2014 which refer to the pseudo reg in wider modes.
2016 We can use a slot already allocated if it provides both
2017 enough inherent space and enough total space.
2018 Otherwise, we allocate a new slot, making sure that it has no less
2019 inherent space, and no less total space, then the previous slot. */
2022 /* No known place to spill from => no slot to reuse. */
2023 x = assign_stack_local (mode, total_size,
2024 min_align > inherent_align
2025 || total_size > inherent_size ? -1 : 0);
2026 if (BYTES_BIG_ENDIAN)
2027 /* Cancel the big-endian correction done in assign_stack_local.
2028 Get the address of the beginning of the slot.
2029 This is so we can do a big-endian correction unconditionally
2031 adjust = inherent_size - total_size;
2033 /* Nothing can alias this slot except this pseudo. */
2034 set_mem_alias_set (x, new_alias_set ());
2037 /* Reuse a stack slot if possible. */
2038 else if (spill_stack_slot[from_reg] != 0
2039 && spill_stack_slot_width[from_reg] >= total_size
2040 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2042 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2043 x = spill_stack_slot[from_reg];
2045 /* Allocate a bigger slot. */
2048 /* Compute maximum size needed, both for inherent size
2049 and for total size. */
2052 if (spill_stack_slot[from_reg])
2054 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2056 mode = GET_MODE (spill_stack_slot[from_reg]);
2057 if (spill_stack_slot_width[from_reg] > total_size)
2058 total_size = spill_stack_slot_width[from_reg];
2059 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2060 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2063 /* Make a slot with that size. */
2064 x = assign_stack_local (mode, total_size,
2065 min_align > inherent_align
2066 || total_size > inherent_size ? -1 : 0);
2069 /* All pseudos mapped to this slot can alias each other. */
2070 if (spill_stack_slot[from_reg])
2071 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2073 set_mem_alias_set (x, new_alias_set ());
2075 if (BYTES_BIG_ENDIAN)
2077 /* Cancel the big-endian correction done in assign_stack_local.
2078 Get the address of the beginning of the slot.
2079 This is so we can do a big-endian correction unconditionally
2081 adjust = GET_MODE_SIZE (mode) - total_size;
2084 = adjust_address_nv (x, mode_for_size (total_size
2090 spill_stack_slot[from_reg] = stack_slot;
2091 spill_stack_slot_width[from_reg] = total_size;
2094 /* On a big endian machine, the "address" of the slot
2095 is the address of the low part that fits its inherent mode. */
2096 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2097 adjust += (total_size - inherent_size);
2099 /* If we have any adjustment to make, or if the stack slot is the
2100 wrong mode, make a new stack slot. */
2101 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2103 /* If we have a decl for the original register, set it for the
2104 memory. If this is a shared MEM, make a copy. */
2105 if (REG_EXPR (regno_reg_rtx[i])
2106 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2108 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2110 /* We can do this only for the DECLs home pseudo, not for
2111 any copies of it, since otherwise when the stack slot
2112 is reused, nonoverlapping_memrefs_p might think they
2114 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2116 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2119 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2123 /* Save the stack slot for later. */
2124 reg_equiv_memory_loc[i] = x;
2128 /* Mark the slots in regs_ever_live for the hard regs
2129 used by pseudo-reg number REGNO. */
2132 mark_home_live (int regno)
2136 i = reg_renumber[regno];
2139 lim = i + hard_regno_nregs[i][PSEUDO_REGNO_MODE (regno)];
2141 regs_ever_live[i++] = 1;
2144 /* This function handles the tracking of elimination offsets around branches.
2146 X is a piece of RTL being scanned.
2148 INSN is the insn that it came from, if any.
2150 INITIAL_P is nonzero if we are to set the offset to be the initial
2151 offset and zero if we are setting the offset of the label to be the
2155 set_label_offsets (rtx x, rtx insn, int initial_p)
2157 enum rtx_code code = GET_CODE (x);
2160 struct elim_table *p;
2165 if (LABEL_REF_NONLOCAL_P (x))
2170 /* ... fall through ... */
2173 /* If we know nothing about this label, set the desired offsets. Note
2174 that this sets the offset at a label to be the offset before a label
2175 if we don't know anything about the label. This is not correct for
2176 the label after a BARRIER, but is the best guess we can make. If
2177 we guessed wrong, we will suppress an elimination that might have
2178 been possible had we been able to guess correctly. */
2180 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2182 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2183 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2184 = (initial_p ? reg_eliminate[i].initial_offset
2185 : reg_eliminate[i].offset);
2186 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2189 /* Otherwise, if this is the definition of a label and it is
2190 preceded by a BARRIER, set our offsets to the known offset of
2194 && (tem = prev_nonnote_insn (insn)) != 0
2196 set_offsets_for_label (insn);
2198 /* If neither of the above cases is true, compare each offset
2199 with those previously recorded and suppress any eliminations
2200 where the offsets disagree. */
2202 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2203 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2204 != (initial_p ? reg_eliminate[i].initial_offset
2205 : reg_eliminate[i].offset))
2206 reg_eliminate[i].can_eliminate = 0;
2211 set_label_offsets (PATTERN (insn), insn, initial_p);
2213 /* ... fall through ... */
2217 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2218 and hence must have all eliminations at their initial offsets. */
2219 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2220 if (REG_NOTE_KIND (tem) == REG_LABEL)
2221 set_label_offsets (XEXP (tem, 0), insn, 1);
2227 /* Each of the labels in the parallel or address vector must be
2228 at their initial offsets. We want the first field for PARALLEL
2229 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2231 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2232 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2237 /* We only care about setting PC. If the source is not RETURN,
2238 IF_THEN_ELSE, or a label, disable any eliminations not at
2239 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2240 isn't one of those possibilities. For branches to a label,
2241 call ourselves recursively.
2243 Note that this can disable elimination unnecessarily when we have
2244 a non-local goto since it will look like a non-constant jump to
2245 someplace in the current function. This isn't a significant
2246 problem since such jumps will normally be when all elimination
2247 pairs are back to their initial offsets. */
2249 if (SET_DEST (x) != pc_rtx)
2252 switch (GET_CODE (SET_SRC (x)))
2259 set_label_offsets (SET_SRC (x), insn, initial_p);
2263 tem = XEXP (SET_SRC (x), 1);
2264 if (GET_CODE (tem) == LABEL_REF)
2265 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2266 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2269 tem = XEXP (SET_SRC (x), 2);
2270 if (GET_CODE (tem) == LABEL_REF)
2271 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2272 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2280 /* If we reach here, all eliminations must be at their initial
2281 offset because we are doing a jump to a variable address. */
2282 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2283 if (p->offset != p->initial_offset)
2284 p->can_eliminate = 0;
2292 /* Scan X and replace any eliminable registers (such as fp) with a
2293 replacement (such as sp), plus an offset.
2295 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2296 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2297 MEM, we are allowed to replace a sum of a register and the constant zero
2298 with the register, which we cannot do outside a MEM. In addition, we need
2299 to record the fact that a register is referenced outside a MEM.
2301 If INSN is an insn, it is the insn containing X. If we replace a REG
2302 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2303 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2304 the REG is being modified.
2306 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2307 That's used when we eliminate in expressions stored in notes.
2308 This means, do not set ref_outside_mem even if the reference
2311 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2312 replacements done assuming all offsets are at their initial values. If
2313 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2314 encounter, return the actual location so that find_reloads will do
2315 the proper thing. */
2318 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2319 bool may_use_invariant)
2321 enum rtx_code code = GET_CODE (x);
2322 struct elim_table *ep;
2329 if (! current_function_decl)
2351 /* First handle the case where we encounter a bare register that
2352 is eliminable. Replace it with a PLUS. */
2353 if (regno < FIRST_PSEUDO_REGISTER)
2355 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2357 if (ep->from_rtx == x && ep->can_eliminate)
2358 return plus_constant (ep->to_rtx, ep->previous_offset);
2361 else if (reg_renumber && reg_renumber[regno] < 0
2362 && reg_equiv_invariant && reg_equiv_invariant[regno])
2364 if (may_use_invariant)
2365 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2366 mem_mode, insn, true);
2367 /* There exists at least one use of REGNO that cannot be
2368 eliminated. Prevent the defining insn from being deleted. */
2369 reg_equiv_init[regno] = NULL_RTX;
2370 alter_reg (regno, -1);
2374 /* You might think handling MINUS in a manner similar to PLUS is a
2375 good idea. It is not. It has been tried multiple times and every
2376 time the change has had to have been reverted.
2378 Other parts of reload know a PLUS is special (gen_reload for example)
2379 and require special code to handle code a reloaded PLUS operand.
2381 Also consider backends where the flags register is clobbered by a
2382 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2383 lea instruction comes to mind). If we try to reload a MINUS, we
2384 may kill the flags register that was holding a useful value.
2386 So, please before trying to handle MINUS, consider reload as a
2387 whole instead of this little section as well as the backend issues. */
2389 /* If this is the sum of an eliminable register and a constant, rework
2391 if (REG_P (XEXP (x, 0))
2392 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2393 && CONSTANT_P (XEXP (x, 1)))
2395 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2397 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2399 /* The only time we want to replace a PLUS with a REG (this
2400 occurs when the constant operand of the PLUS is the negative
2401 of the offset) is when we are inside a MEM. We won't want
2402 to do so at other times because that would change the
2403 structure of the insn in a way that reload can't handle.
2404 We special-case the commonest situation in
2405 eliminate_regs_in_insn, so just replace a PLUS with a
2406 PLUS here, unless inside a MEM. */
2407 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2408 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2411 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2412 plus_constant (XEXP (x, 1),
2413 ep->previous_offset));
2416 /* If the register is not eliminable, we are done since the other
2417 operand is a constant. */
2421 /* If this is part of an address, we want to bring any constant to the
2422 outermost PLUS. We will do this by doing register replacement in
2423 our operands and seeing if a constant shows up in one of them.
2425 Note that there is no risk of modifying the structure of the insn,
2426 since we only get called for its operands, thus we are either
2427 modifying the address inside a MEM, or something like an address
2428 operand of a load-address insn. */
2431 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2432 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2434 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2436 /* If one side is a PLUS and the other side is a pseudo that
2437 didn't get a hard register but has a reg_equiv_constant,
2438 we must replace the constant here since it may no longer
2439 be in the position of any operand. */
2440 if (GET_CODE (new0) == PLUS && REG_P (new1)
2441 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2442 && reg_renumber[REGNO (new1)] < 0
2443 && reg_equiv_constant != 0
2444 && reg_equiv_constant[REGNO (new1)] != 0)
2445 new1 = reg_equiv_constant[REGNO (new1)];
2446 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2447 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2448 && reg_renumber[REGNO (new0)] < 0
2449 && reg_equiv_constant[REGNO (new0)] != 0)
2450 new0 = reg_equiv_constant[REGNO (new0)];
2452 new = form_sum (new0, new1);
2454 /* As above, if we are not inside a MEM we do not want to
2455 turn a PLUS into something else. We might try to do so here
2456 for an addition of 0 if we aren't optimizing. */
2457 if (! mem_mode && GET_CODE (new) != PLUS)
2458 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2466 /* If this is the product of an eliminable register and a
2467 constant, apply the distribute law and move the constant out
2468 so that we have (plus (mult ..) ..). This is needed in order
2469 to keep load-address insns valid. This case is pathological.
2470 We ignore the possibility of overflow here. */
2471 if (REG_P (XEXP (x, 0))
2472 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2473 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2474 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2476 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2479 /* Refs inside notes don't count for this purpose. */
2480 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2481 || GET_CODE (insn) == INSN_LIST)))
2482 ep->ref_outside_mem = 1;
2485 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2486 ep->previous_offset * INTVAL (XEXP (x, 1)));
2489 /* ... fall through ... */
2493 /* See comments before PLUS about handling MINUS. */
2495 case DIV: case UDIV:
2496 case MOD: case UMOD:
2497 case AND: case IOR: case XOR:
2498 case ROTATERT: case ROTATE:
2499 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2501 case GE: case GT: case GEU: case GTU:
2502 case LE: case LT: case LEU: case LTU:
2504 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2505 rtx new1 = XEXP (x, 1)
2506 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2508 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2509 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2514 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2517 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2518 if (new != XEXP (x, 0))
2520 /* If this is a REG_DEAD note, it is not valid anymore.
2521 Using the eliminated version could result in creating a
2522 REG_DEAD note for the stack or frame pointer. */
2523 if (GET_MODE (x) == REG_DEAD)
2525 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2528 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2532 /* ... fall through ... */
2535 /* Now do eliminations in the rest of the chain. If this was
2536 an EXPR_LIST, this might result in allocating more memory than is
2537 strictly needed, but it simplifies the code. */
2540 new = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2541 if (new != XEXP (x, 1))
2543 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2551 case STRICT_LOW_PART:
2553 case SIGN_EXTEND: case ZERO_EXTEND:
2554 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2555 case FLOAT: case FIX:
2556 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2565 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2566 if (new != XEXP (x, 0))
2567 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2571 /* Similar to above processing, but preserve SUBREG_BYTE.
2572 Convert (subreg (mem)) to (mem) if not paradoxical.
2573 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2574 pseudo didn't get a hard reg, we must replace this with the
2575 eliminated version of the memory location because push_reload
2576 may do the replacement in certain circumstances. */
2577 if (REG_P (SUBREG_REG (x))
2578 && (GET_MODE_SIZE (GET_MODE (x))
2579 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2580 && reg_equiv_memory_loc != 0
2581 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2583 new = SUBREG_REG (x);
2586 new = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2588 if (new != SUBREG_REG (x))
2590 int x_size = GET_MODE_SIZE (GET_MODE (x));
2591 int new_size = GET_MODE_SIZE (GET_MODE (new));
2594 && ((x_size < new_size
2595 #ifdef WORD_REGISTER_OPERATIONS
2596 /* On these machines, combine can create rtl of the form
2597 (set (subreg:m1 (reg:m2 R) 0) ...)
2598 where m1 < m2, and expects something interesting to
2599 happen to the entire word. Moreover, it will use the
2600 (reg:m2 R) later, expecting all bits to be preserved.
2601 So if the number of words is the same, preserve the
2602 subreg so that push_reload can see it. */
2603 && ! ((x_size - 1) / UNITS_PER_WORD
2604 == (new_size -1 ) / UNITS_PER_WORD)
2607 || x_size == new_size)
2609 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2611 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2617 /* Our only special processing is to pass the mode of the MEM to our
2618 recursive call and copy the flags. While we are here, handle this
2619 case more efficiently. */
2621 replace_equiv_address_nv (x,
2622 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2626 /* Handle insn_list USE that a call to a pure function may generate. */
2627 new = eliminate_regs_1 (XEXP (x, 0), 0, insn, false);
2628 if (new != XEXP (x, 0))
2629 return gen_rtx_USE (GET_MODE (x), new);
2641 /* Process each of our operands recursively. If any have changed, make a
2643 fmt = GET_RTX_FORMAT (code);
2644 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2648 new = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2649 if (new != XEXP (x, i) && ! copied)
2651 x = shallow_copy_rtx (x);
2656 else if (*fmt == 'E')
2659 for (j = 0; j < XVECLEN (x, i); j++)
2661 new = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2662 if (new != XVECEXP (x, i, j) && ! copied_vec)
2664 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2668 x = shallow_copy_rtx (x);
2671 XVEC (x, i) = new_v;
2674 XVECEXP (x, i, j) = new;
2683 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2685 return eliminate_regs_1 (x, mem_mode, insn, false);
2688 /* Scan rtx X for modifications of elimination target registers. Update
2689 the table of eliminables to reflect the changed state. MEM_MODE is
2690 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2693 elimination_effects (rtx x, enum machine_mode mem_mode)
2695 enum rtx_code code = GET_CODE (x);
2696 struct elim_table *ep;
2720 /* First handle the case where we encounter a bare register that
2721 is eliminable. Replace it with a PLUS. */
2722 if (regno < FIRST_PSEUDO_REGISTER)
2724 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2726 if (ep->from_rtx == x && ep->can_eliminate)
2729 ep->ref_outside_mem = 1;
2734 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2735 && reg_equiv_constant[regno]
2736 && ! function_invariant_p (reg_equiv_constant[regno]))
2737 elimination_effects (reg_equiv_constant[regno], mem_mode);
2746 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2747 if (ep->to_rtx == XEXP (x, 0))
2749 int size = GET_MODE_SIZE (mem_mode);
2751 /* If more bytes than MEM_MODE are pushed, account for them. */
2752 #ifdef PUSH_ROUNDING
2753 if (ep->to_rtx == stack_pointer_rtx)
2754 size = PUSH_ROUNDING (size);
2756 if (code == PRE_DEC || code == POST_DEC)
2758 else if (code == PRE_INC || code == POST_INC)
2760 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2761 && GET_CODE (XEXP (x, 1)) == PLUS
2762 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2763 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2764 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2767 /* These two aren't unary operators. */
2768 if (code == POST_MODIFY || code == PRE_MODIFY)
2771 /* Fall through to generic unary operation case. */
2772 case STRICT_LOW_PART:
2774 case SIGN_EXTEND: case ZERO_EXTEND:
2775 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2776 case FLOAT: case FIX:
2777 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2786 elimination_effects (XEXP (x, 0), mem_mode);
2790 if (REG_P (SUBREG_REG (x))
2791 && (GET_MODE_SIZE (GET_MODE (x))
2792 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2793 && reg_equiv_memory_loc != 0
2794 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2797 elimination_effects (SUBREG_REG (x), mem_mode);
2801 /* If using a register that is the source of an eliminate we still
2802 think can be performed, note it cannot be performed since we don't
2803 know how this register is used. */
2804 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2805 if (ep->from_rtx == XEXP (x, 0))
2806 ep->can_eliminate = 0;
2808 elimination_effects (XEXP (x, 0), mem_mode);
2812 /* If clobbering a register that is the replacement register for an
2813 elimination we still think can be performed, note that it cannot
2814 be performed. Otherwise, we need not be concerned about it. */
2815 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2816 if (ep->to_rtx == XEXP (x, 0))
2817 ep->can_eliminate = 0;
2819 elimination_effects (XEXP (x, 0), mem_mode);
2823 /* Check for setting a register that we know about. */
2824 if (REG_P (SET_DEST (x)))
2826 /* See if this is setting the replacement register for an
2829 If DEST is the hard frame pointer, we do nothing because we
2830 assume that all assignments to the frame pointer are for
2831 non-local gotos and are being done at a time when they are valid
2832 and do not disturb anything else. Some machines want to
2833 eliminate a fake argument pointer (or even a fake frame pointer)
2834 with either the real frame or the stack pointer. Assignments to
2835 the hard frame pointer must not prevent this elimination. */
2837 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2839 if (ep->to_rtx == SET_DEST (x)
2840 && SET_DEST (x) != hard_frame_pointer_rtx)
2842 /* If it is being incremented, adjust the offset. Otherwise,
2843 this elimination can't be done. */
2844 rtx src = SET_SRC (x);
2846 if (GET_CODE (src) == PLUS
2847 && XEXP (src, 0) == SET_DEST (x)
2848 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2849 ep->offset -= INTVAL (XEXP (src, 1));
2851 ep->can_eliminate = 0;
2855 elimination_effects (SET_DEST (x), 0);
2856 elimination_effects (SET_SRC (x), 0);
2860 /* Our only special processing is to pass the mode of the MEM to our
2862 elimination_effects (XEXP (x, 0), GET_MODE (x));
2869 fmt = GET_RTX_FORMAT (code);
2870 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2873 elimination_effects (XEXP (x, i), mem_mode);
2874 else if (*fmt == 'E')
2875 for (j = 0; j < XVECLEN (x, i); j++)
2876 elimination_effects (XVECEXP (x, i, j), mem_mode);
2880 /* Descend through rtx X and verify that no references to eliminable registers
2881 remain. If any do remain, mark the involved register as not
2885 check_eliminable_occurrences (rtx x)
2894 code = GET_CODE (x);
2896 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2898 struct elim_table *ep;
2900 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2901 if (ep->from_rtx == x)
2902 ep->can_eliminate = 0;
2906 fmt = GET_RTX_FORMAT (code);
2907 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2910 check_eliminable_occurrences (XEXP (x, i));
2911 else if (*fmt == 'E')
2914 for (j = 0; j < XVECLEN (x, i); j++)
2915 check_eliminable_occurrences (XVECEXP (x, i, j));
2920 /* Scan INSN and eliminate all eliminable registers in it.
2922 If REPLACE is nonzero, do the replacement destructively. Also
2923 delete the insn as dead it if it is setting an eliminable register.
2925 If REPLACE is zero, do all our allocations in reload_obstack.
2927 If no eliminations were done and this insn doesn't require any elimination
2928 processing (these are not identical conditions: it might be updating sp,
2929 but not referencing fp; this needs to be seen during reload_as_needed so
2930 that the offset between fp and sp can be taken into consideration), zero
2931 is returned. Otherwise, 1 is returned. */
2934 eliminate_regs_in_insn (rtx insn, int replace)
2936 int icode = recog_memoized (insn);
2937 rtx old_body = PATTERN (insn);
2938 int insn_is_asm = asm_noperands (old_body) >= 0;
2939 rtx old_set = single_set (insn);
2943 rtx substed_operand[MAX_RECOG_OPERANDS];
2944 rtx orig_operand[MAX_RECOG_OPERANDS];
2945 struct elim_table *ep;
2946 rtx plus_src, plus_cst_src;
2948 if (! insn_is_asm && icode < 0)
2950 gcc_assert (GET_CODE (PATTERN (insn)) == USE
2951 || GET_CODE (PATTERN (insn)) == CLOBBER
2952 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2953 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2954 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
2958 if (old_set != 0 && REG_P (SET_DEST (old_set))
2959 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2961 /* Check for setting an eliminable register. */
2962 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2963 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2965 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2966 /* If this is setting the frame pointer register to the
2967 hardware frame pointer register and this is an elimination
2968 that will be done (tested above), this insn is really
2969 adjusting the frame pointer downward to compensate for
2970 the adjustment done before a nonlocal goto. */
2971 if (ep->from == FRAME_POINTER_REGNUM
2972 && ep->to == HARD_FRAME_POINTER_REGNUM)
2974 rtx base = SET_SRC (old_set);
2975 rtx base_insn = insn;
2976 HOST_WIDE_INT offset = 0;
2978 while (base != ep->to_rtx)
2980 rtx prev_insn, prev_set;
2982 if (GET_CODE (base) == PLUS
2983 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2985 offset += INTVAL (XEXP (base, 1));
2986 base = XEXP (base, 0);
2988 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2989 && (prev_set = single_set (prev_insn)) != 0
2990 && rtx_equal_p (SET_DEST (prev_set), base))
2992 base = SET_SRC (prev_set);
2993 base_insn = prev_insn;
2999 if (base == ep->to_rtx)
3002 = plus_constant (ep->to_rtx, offset - ep->offset);
3004 new_body = old_body;
3007 new_body = copy_insn (old_body);
3008 if (REG_NOTES (insn))
3009 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3011 PATTERN (insn) = new_body;
3012 old_set = single_set (insn);
3014 /* First see if this insn remains valid when we
3015 make the change. If not, keep the INSN_CODE
3016 the same and let reload fit it up. */
3017 validate_change (insn, &SET_SRC (old_set), src, 1);
3018 validate_change (insn, &SET_DEST (old_set),
3020 if (! apply_change_group ())
3022 SET_SRC (old_set) = src;
3023 SET_DEST (old_set) = ep->to_rtx;
3032 /* In this case this insn isn't serving a useful purpose. We
3033 will delete it in reload_as_needed once we know that this
3034 elimination is, in fact, being done.
3036 If REPLACE isn't set, we can't delete this insn, but needn't
3037 process it since it won't be used unless something changes. */
3040 delete_dead_insn (insn);
3048 /* We allow one special case which happens to work on all machines we
3049 currently support: a single set with the source or a REG_EQUAL
3050 note being a PLUS of an eliminable register and a constant. */
3051 plus_src = plus_cst_src = 0;
3052 if (old_set && REG_P (SET_DEST (old_set)))
3054 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3055 plus_src = SET_SRC (old_set);
3056 /* First see if the source is of the form (plus (...) CST). */
3058 && GET_CODE (XEXP (plus_src, 1)) == CONST_INT)
3059 plus_cst_src = plus_src;
3060 else if (REG_P (SET_SRC (old_set))
3063 /* Otherwise, see if we have a REG_EQUAL note of the form
3064 (plus (...) CST). */
3066 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3068 if (REG_NOTE_KIND (links) == REG_EQUAL
3069 && GET_CODE (XEXP (links, 0)) == PLUS
3070 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT)
3072 plus_cst_src = XEXP (links, 0);
3078 /* Check that the first operand of the PLUS is a hard reg or
3079 the lowpart subreg of one. */
3082 rtx reg = XEXP (plus_cst_src, 0);
3083 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3084 reg = SUBREG_REG (reg);
3086 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3092 rtx reg = XEXP (plus_cst_src, 0);
3093 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3095 if (GET_CODE (reg) == SUBREG)
3096 reg = SUBREG_REG (reg);
3098 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3099 if (ep->from_rtx == reg && ep->can_eliminate)
3101 rtx to_rtx = ep->to_rtx;
3102 offset += ep->offset;
3103 offset = trunc_int_for_mode (offset, GET_MODE (reg));
3105 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3106 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3111 /* We assume here that if we need a PARALLEL with
3112 CLOBBERs for this assignment, we can do with the
3113 MATCH_SCRATCHes that add_clobbers allocates.
3114 There's not much we can do if that doesn't work. */
3115 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3119 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3122 rtvec vec = rtvec_alloc (num_clobbers + 1);
3124 vec->elem[0] = PATTERN (insn);
3125 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3126 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3128 gcc_assert (INSN_CODE (insn) >= 0);
3130 /* If we have a nonzero offset, and the source is already
3131 a simple REG, the following transformation would
3132 increase the cost of the insn by replacing a simple REG
3133 with (plus (reg sp) CST). So try only when we already
3134 had a PLUS before. */
3137 new_body = old_body;
3140 new_body = copy_insn (old_body);
3141 if (REG_NOTES (insn))
3142 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3144 PATTERN (insn) = new_body;
3145 old_set = single_set (insn);
3147 XEXP (SET_SRC (old_set), 0) = to_rtx;
3148 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3154 /* This can't have an effect on elimination offsets, so skip right
3160 /* Determine the effects of this insn on elimination offsets. */
3161 elimination_effects (old_body, 0);
3163 /* Eliminate all eliminable registers occurring in operands that
3164 can be handled by reload. */
3165 extract_insn (insn);
3166 for (i = 0; i < recog_data.n_operands; i++)
3168 orig_operand[i] = recog_data.operand[i];
3169 substed_operand[i] = recog_data.operand[i];
3171 /* For an asm statement, every operand is eliminable. */
3172 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3174 bool is_set_src, in_plus;
3176 /* Check for setting a register that we know about. */
3177 if (recog_data.operand_type[i] != OP_IN
3178 && REG_P (orig_operand[i]))
3180 /* If we are assigning to a register that can be eliminated, it
3181 must be as part of a PARALLEL, since the code above handles
3182 single SETs. We must indicate that we can no longer
3183 eliminate this reg. */
3184 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3186 if (ep->from_rtx == orig_operand[i])
3187 ep->can_eliminate = 0;
3190 /* Companion to the above plus substitution, we can allow
3191 invariants as the source of a plain move. */
3193 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3197 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3198 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3202 = eliminate_regs_1 (recog_data.operand[i], 0,
3203 replace ? insn : NULL_RTX,
3204 is_set_src || in_plus);
3205 if (substed_operand[i] != orig_operand[i])
3207 /* Terminate the search in check_eliminable_occurrences at
3209 *recog_data.operand_loc[i] = 0;
3211 /* If an output operand changed from a REG to a MEM and INSN is an
3212 insn, write a CLOBBER insn. */
3213 if (recog_data.operand_type[i] != OP_IN
3214 && REG_P (orig_operand[i])
3215 && MEM_P (substed_operand[i])
3217 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3222 for (i = 0; i < recog_data.n_dups; i++)
3223 *recog_data.dup_loc[i]
3224 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3226 /* If any eliminable remain, they aren't eliminable anymore. */
3227 check_eliminable_occurrences (old_body);
3229 /* Substitute the operands; the new values are in the substed_operand
3231 for (i = 0; i < recog_data.n_operands; i++)
3232 *recog_data.operand_loc[i] = substed_operand[i];
3233 for (i = 0; i < recog_data.n_dups; i++)
3234 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3236 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3237 re-recognize the insn. We do this in case we had a simple addition
3238 but now can do this as a load-address. This saves an insn in this
3240 If re-recognition fails, the old insn code number will still be used,
3241 and some register operands may have changed into PLUS expressions.
3242 These will be handled by find_reloads by loading them into a register
3247 /* If we aren't replacing things permanently and we changed something,
3248 make another copy to ensure that all the RTL is new. Otherwise
3249 things can go wrong if find_reload swaps commutative operands
3250 and one is inside RTL that has been copied while the other is not. */
3251 new_body = old_body;
3254 new_body = copy_insn (old_body);
3255 if (REG_NOTES (insn))
3256 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3258 PATTERN (insn) = new_body;
3260 /* If we had a move insn but now we don't, rerecognize it. This will
3261 cause spurious re-recognition if the old move had a PARALLEL since
3262 the new one still will, but we can't call single_set without
3263 having put NEW_BODY into the insn and the re-recognition won't
3264 hurt in this rare case. */
3265 /* ??? Why this huge if statement - why don't we just rerecognize the
3269 && ((REG_P (SET_SRC (old_set))
3270 && (GET_CODE (new_body) != SET
3271 || !REG_P (SET_SRC (new_body))))
3272 /* If this was a load from or store to memory, compare
3273 the MEM in recog_data.operand to the one in the insn.
3274 If they are not equal, then rerecognize the insn. */
3276 && ((MEM_P (SET_SRC (old_set))
3277 && SET_SRC (old_set) != recog_data.operand[1])
3278 || (MEM_P (SET_DEST (old_set))
3279 && SET_DEST (old_set) != recog_data.operand[0])))
3280 /* If this was an add insn before, rerecognize. */
3281 || GET_CODE (SET_SRC (old_set)) == PLUS))
3283 int new_icode = recog (PATTERN (insn), insn, 0);
3285 INSN_CODE (insn) = new_icode;
3289 /* Restore the old body. If there were any changes to it, we made a copy
3290 of it while the changes were still in place, so we'll correctly return
3291 a modified insn below. */
3294 /* Restore the old body. */
3295 for (i = 0; i < recog_data.n_operands; i++)
3296 *recog_data.operand_loc[i] = orig_operand[i];
3297 for (i = 0; i < recog_data.n_dups; i++)
3298 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3301 /* Update all elimination pairs to reflect the status after the current
3302 insn. The changes we make were determined by the earlier call to
3303 elimination_effects.
3305 We also detect cases where register elimination cannot be done,
3306 namely, if a register would be both changed and referenced outside a MEM
3307 in the resulting insn since such an insn is often undefined and, even if
3308 not, we cannot know what meaning will be given to it. Note that it is
3309 valid to have a register used in an address in an insn that changes it
3310 (presumably with a pre- or post-increment or decrement).
3312 If anything changes, return nonzero. */
3314 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3316 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3317 ep->can_eliminate = 0;
3319 ep->ref_outside_mem = 0;
3321 if (ep->previous_offset != ep->offset)
3326 /* If we changed something, perform elimination in REG_NOTES. This is
3327 needed even when REPLACE is zero because a REG_DEAD note might refer
3328 to a register that we eliminate and could cause a different number
3329 of spill registers to be needed in the final reload pass than in
3331 if (val && REG_NOTES (insn) != 0)
3333 = eliminate_regs_1 (REG_NOTES (insn), 0, REG_NOTES (insn), true);
3338 /* Loop through all elimination pairs.
3339 Recalculate the number not at initial offset.
3341 Compute the maximum offset (minimum offset if the stack does not
3342 grow downward) for each elimination pair. */
3345 update_eliminable_offsets (void)
3347 struct elim_table *ep;
3349 num_not_at_initial_offset = 0;
3350 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3352 ep->previous_offset = ep->offset;
3353 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3354 num_not_at_initial_offset++;
3358 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3359 replacement we currently believe is valid, mark it as not eliminable if X
3360 modifies DEST in any way other than by adding a constant integer to it.
3362 If DEST is the frame pointer, we do nothing because we assume that
3363 all assignments to the hard frame pointer are nonlocal gotos and are being
3364 done at a time when they are valid and do not disturb anything else.
3365 Some machines want to eliminate a fake argument pointer with either the
3366 frame or stack pointer. Assignments to the hard frame pointer must not
3367 prevent this elimination.
3369 Called via note_stores from reload before starting its passes to scan
3370 the insns of the function. */
3373 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3377 /* A SUBREG of a hard register here is just changing its mode. We should
3378 not see a SUBREG of an eliminable hard register, but check just in
3380 if (GET_CODE (dest) == SUBREG)
3381 dest = SUBREG_REG (dest);
3383 if (dest == hard_frame_pointer_rtx)
3386 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3387 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3388 && (GET_CODE (x) != SET
3389 || GET_CODE (SET_SRC (x)) != PLUS
3390 || XEXP (SET_SRC (x), 0) != dest
3391 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3393 reg_eliminate[i].can_eliminate_previous
3394 = reg_eliminate[i].can_eliminate = 0;
3399 /* Verify that the initial elimination offsets did not change since the
3400 last call to set_initial_elim_offsets. This is used to catch cases
3401 where something illegal happened during reload_as_needed that could
3402 cause incorrect code to be generated if we did not check for it. */
3405 verify_initial_elim_offsets (void)
3409 if (!num_eliminable)
3412 #ifdef ELIMINABLE_REGS
3414 struct elim_table *ep;
3416 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3418 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3419 if (t != ep->initial_offset)
3424 INITIAL_FRAME_POINTER_OFFSET (t);
3425 if (t != reg_eliminate[0].initial_offset)
3432 /* Reset all offsets on eliminable registers to their initial values. */
3435 set_initial_elim_offsets (void)
3437 struct elim_table *ep = reg_eliminate;
3439 #ifdef ELIMINABLE_REGS
3440 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3442 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3443 ep->previous_offset = ep->offset = ep->initial_offset;
3446 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3447 ep->previous_offset = ep->offset = ep->initial_offset;
3450 num_not_at_initial_offset = 0;
3453 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3456 set_initial_eh_label_offset (rtx label)
3458 set_label_offsets (label, NULL_RTX, 1);
3461 /* Initialize the known label offsets.
3462 Set a known offset for each forced label to be at the initial offset
3463 of each elimination. We do this because we assume that all
3464 computed jumps occur from a location where each elimination is
3465 at its initial offset.
3466 For all other labels, show that we don't know the offsets. */
3469 set_initial_label_offsets (void)
3472 memset (offsets_known_at, 0, num_labels);
3474 for (x = forced_labels; x; x = XEXP (x, 1))
3476 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3478 for_each_eh_label (set_initial_eh_label_offset);
3481 /* Set all elimination offsets to the known values for the code label given
3485 set_offsets_for_label (rtx insn)
3488 int label_nr = CODE_LABEL_NUMBER (insn);
3489 struct elim_table *ep;
3491 num_not_at_initial_offset = 0;
3492 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3494 ep->offset = ep->previous_offset
3495 = offsets_at[label_nr - first_label_num][i];
3496 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3497 num_not_at_initial_offset++;
3501 /* See if anything that happened changes which eliminations are valid.
3502 For example, on the SPARC, whether or not the frame pointer can
3503 be eliminated can depend on what registers have been used. We need
3504 not check some conditions again (such as flag_omit_frame_pointer)
3505 since they can't have changed. */
3508 update_eliminables (HARD_REG_SET *pset)
3510 int previous_frame_pointer_needed = frame_pointer_needed;
3511 struct elim_table *ep;
3513 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3514 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3515 #ifdef ELIMINABLE_REGS
3516 || ! CAN_ELIMINATE (ep->from, ep->to)
3519 ep->can_eliminate = 0;
3521 /* Look for the case where we have discovered that we can't replace
3522 register A with register B and that means that we will now be
3523 trying to replace register A with register C. This means we can
3524 no longer replace register C with register B and we need to disable
3525 such an elimination, if it exists. This occurs often with A == ap,
3526 B == sp, and C == fp. */
3528 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3530 struct elim_table *op;
3533 if (! ep->can_eliminate && ep->can_eliminate_previous)
3535 /* Find the current elimination for ep->from, if there is a
3537 for (op = reg_eliminate;
3538 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3539 if (op->from == ep->from && op->can_eliminate)
3545 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3547 for (op = reg_eliminate;
3548 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3549 if (op->from == new_to && op->to == ep->to)
3550 op->can_eliminate = 0;
3554 /* See if any registers that we thought we could eliminate the previous
3555 time are no longer eliminable. If so, something has changed and we
3556 must spill the register. Also, recompute the number of eliminable
3557 registers and see if the frame pointer is needed; it is if there is
3558 no elimination of the frame pointer that we can perform. */
3560 frame_pointer_needed = 1;
3561 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3563 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3564 && ep->to != HARD_FRAME_POINTER_REGNUM)
3565 frame_pointer_needed = 0;
3567 if (! ep->can_eliminate && ep->can_eliminate_previous)
3569 ep->can_eliminate_previous = 0;
3570 SET_HARD_REG_BIT (*pset, ep->from);
3575 /* If we didn't need a frame pointer last time, but we do now, spill
3576 the hard frame pointer. */
3577 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3578 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3581 /* Initialize the table of registers to eliminate. */
3584 init_elim_table (void)
3586 struct elim_table *ep;
3587 #ifdef ELIMINABLE_REGS
3588 const struct elim_table_1 *ep1;
3592 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3594 /* Does this function require a frame pointer? */
3596 frame_pointer_needed = (! flag_omit_frame_pointer
3597 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3598 and restore sp for alloca. So we can't eliminate
3599 the frame pointer in that case. At some point,
3600 we should improve this by emitting the
3601 sp-adjusting insns for this case. */
3602 || (current_function_calls_alloca
3603 && EXIT_IGNORE_STACK)
3604 || current_function_accesses_prior_frames
3605 || FRAME_POINTER_REQUIRED);
3609 #ifdef ELIMINABLE_REGS
3610 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3611 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3613 ep->from = ep1->from;
3615 ep->can_eliminate = ep->can_eliminate_previous
3616 = (CAN_ELIMINATE (ep->from, ep->to)
3617 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3620 reg_eliminate[0].from = reg_eliminate_1[0].from;
3621 reg_eliminate[0].to = reg_eliminate_1[0].to;
3622 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3623 = ! frame_pointer_needed;
3626 /* Count the number of eliminable registers and build the FROM and TO
3627 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3628 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3629 We depend on this. */
3630 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3632 num_eliminable += ep->can_eliminate;
3633 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3634 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3638 /* Kick all pseudos out of hard register REGNO.
3640 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3641 because we found we can't eliminate some register. In the case, no pseudos
3642 are allowed to be in the register, even if they are only in a block that
3643 doesn't require spill registers, unlike the case when we are spilling this
3644 hard reg to produce another spill register.
3646 Return nonzero if any pseudos needed to be kicked out. */
3649 spill_hard_reg (unsigned int regno, int cant_eliminate)
3655 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3656 regs_ever_live[regno] = 1;
3659 /* Spill every pseudo reg that was allocated to this reg
3660 or to something that overlaps this reg. */
3662 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3663 if (reg_renumber[i] >= 0
3664 && (unsigned int) reg_renumber[i] <= regno
3665 && ((unsigned int) reg_renumber[i]
3666 + hard_regno_nregs[(unsigned int) reg_renumber[i]]
3667 [PSEUDO_REGNO_MODE (i)]
3669 SET_REGNO_REG_SET (&spilled_pseudos, i);
3672 /* After find_reload_regs has been run for all insn that need reloads,
3673 and/or spill_hard_regs was called, this function is used to actually
3674 spill pseudo registers and try to reallocate them. It also sets up the
3675 spill_regs array for use by choose_reload_regs. */
3678 finish_spills (int global)
3680 struct insn_chain *chain;
3681 int something_changed = 0;
3683 reg_set_iterator rsi;
3685 /* Build the spill_regs array for the function. */
3686 /* If there are some registers still to eliminate and one of the spill regs
3687 wasn't ever used before, additional stack space may have to be
3688 allocated to store this register. Thus, we may have changed the offset
3689 between the stack and frame pointers, so mark that something has changed.
3691 One might think that we need only set VAL to 1 if this is a call-used
3692 register. However, the set of registers that must be saved by the
3693 prologue is not identical to the call-used set. For example, the
3694 register used by the call insn for the return PC is a call-used register,
3695 but must be saved by the prologue. */
3698 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3699 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3701 spill_reg_order[i] = n_spills;
3702 spill_regs[n_spills++] = i;
3703 if (num_eliminable && ! regs_ever_live[i])
3704 something_changed = 1;
3705 regs_ever_live[i] = 1;
3708 spill_reg_order[i] = -1;
3710 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3712 /* Record the current hard register the pseudo is allocated to in
3713 pseudo_previous_regs so we avoid reallocating it to the same
3714 hard reg in a later pass. */
3715 gcc_assert (reg_renumber[i] >= 0);
3717 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3718 /* Mark it as no longer having a hard register home. */
3719 reg_renumber[i] = -1;
3720 /* We will need to scan everything again. */
3721 something_changed = 1;
3724 /* Retry global register allocation if possible. */
3727 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3728 /* For every insn that needs reloads, set the registers used as spill
3729 regs in pseudo_forbidden_regs for every pseudo live across the
3731 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3733 EXECUTE_IF_SET_IN_REG_SET
3734 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3736 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3737 chain->used_spill_regs);
3739 EXECUTE_IF_SET_IN_REG_SET
3740 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3742 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3743 chain->used_spill_regs);
3747 /* Retry allocating the spilled pseudos. For each reg, merge the
3748 various reg sets that indicate which hard regs can't be used,
3749 and call retry_global_alloc.
3750 We change spill_pseudos here to only contain pseudos that did not
3751 get a new hard register. */
3752 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3753 if (reg_old_renumber[i] != reg_renumber[i])
3755 HARD_REG_SET forbidden;
3756 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3757 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3758 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3759 retry_global_alloc (i, forbidden);
3760 if (reg_renumber[i] >= 0)
3761 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3765 /* Fix up the register information in the insn chain.
3766 This involves deleting those of the spilled pseudos which did not get
3767 a new hard register home from the live_{before,after} sets. */
3768 for (chain = reload_insn_chain; chain; chain = chain->next)
3770 HARD_REG_SET used_by_pseudos;
3771 HARD_REG_SET used_by_pseudos2;
3773 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3774 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3776 /* Mark any unallocated hard regs as available for spills. That
3777 makes inheritance work somewhat better. */
3778 if (chain->need_reload)
3780 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3781 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3782 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3784 /* Save the old value for the sanity test below. */
3785 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3787 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3788 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3789 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3790 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3792 /* Make sure we only enlarge the set. */
3793 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3799 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3800 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3802 int regno = reg_renumber[i];
3803 if (reg_old_renumber[i] == regno)
3806 alter_reg (i, reg_old_renumber[i]);
3807 reg_old_renumber[i] = regno;
3811 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3813 fprintf (dump_file, " Register %d now in %d.\n\n",
3814 i, reg_renumber[i]);
3818 return something_changed;
3821 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3824 scan_paradoxical_subregs (rtx x)
3828 enum rtx_code code = GET_CODE (x);
3838 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3846 if (REG_P (SUBREG_REG (x))
3847 && (GET_MODE_SIZE (GET_MODE (x))
3848 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
3849 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3850 = GET_MODE_SIZE (GET_MODE (x));
3857 fmt = GET_RTX_FORMAT (code);
3858 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3861 scan_paradoxical_subregs (XEXP (x, i));
3862 else if (fmt[i] == 'E')
3865 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3866 scan_paradoxical_subregs (XVECEXP (x, i, j));
3871 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
3872 examine all of the reload insns between PREV and NEXT exclusive, and
3873 annotate all that may trap. */
3876 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
3878 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
3879 unsigned int trap_count;
3885 if (may_trap_p (PATTERN (insn)))
3889 remove_note (insn, note);
3893 for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i))
3894 if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i)))
3898 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (note, 0), REG_NOTES (i));
3902 /* Reload pseudo-registers into hard regs around each insn as needed.
3903 Additional register load insns are output before the insn that needs it
3904 and perhaps store insns after insns that modify the reloaded pseudo reg.
3906 reg_last_reload_reg and reg_reloaded_contents keep track of
3907 which registers are already available in reload registers.
3908 We update these for the reloads that we perform,
3909 as the insns are scanned. */
3912 reload_as_needed (int live_known)
3914 struct insn_chain *chain;
3915 #if defined (AUTO_INC_DEC)
3920 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3921 memset (spill_reg_store, 0, sizeof spill_reg_store);
3922 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
3923 INIT_REG_SET (®_has_output_reload);
3924 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3925 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
3927 set_initial_elim_offsets ();
3929 for (chain = reload_insn_chain; chain; chain = chain->next)
3932 rtx insn = chain->insn;
3933 rtx old_next = NEXT_INSN (insn);
3935 /* If we pass a label, copy the offsets from the label information
3936 into the current offsets of each elimination. */
3938 set_offsets_for_label (insn);
3940 else if (INSN_P (insn))
3942 regset_head regs_to_forget;
3943 INIT_REG_SET (®s_to_forget);
3944 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
3946 /* If this is a USE and CLOBBER of a MEM, ensure that any
3947 references to eliminable registers have been removed. */
3949 if ((GET_CODE (PATTERN (insn)) == USE
3950 || GET_CODE (PATTERN (insn)) == CLOBBER)
3951 && MEM_P (XEXP (PATTERN (insn), 0)))
3952 XEXP (XEXP (PATTERN (insn), 0), 0)
3953 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3954 GET_MODE (XEXP (PATTERN (insn), 0)),
3957 /* If we need to do register elimination processing, do so.
3958 This might delete the insn, in which case we are done. */
3959 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3961 eliminate_regs_in_insn (insn, 1);
3964 update_eliminable_offsets ();
3965 CLEAR_REG_SET (®s_to_forget);
3970 /* If need_elim is nonzero but need_reload is zero, one might think
3971 that we could simply set n_reloads to 0. However, find_reloads
3972 could have done some manipulation of the insn (such as swapping
3973 commutative operands), and these manipulations are lost during
3974 the first pass for every insn that needs register elimination.
3975 So the actions of find_reloads must be redone here. */
3977 if (! chain->need_elim && ! chain->need_reload
3978 && ! chain->need_operand_change)
3980 /* First find the pseudo regs that must be reloaded for this insn.
3981 This info is returned in the tables reload_... (see reload.h).
3982 Also modify the body of INSN by substituting RELOAD
3983 rtx's for those pseudo regs. */
3986 CLEAR_REG_SET (®_has_output_reload);
3987 CLEAR_HARD_REG_SET (reg_is_output_reload);
3989 find_reloads (insn, 1, spill_indirect_levels, live_known,
3995 rtx next = NEXT_INSN (insn);
3998 prev = PREV_INSN (insn);
4000 /* Now compute which reload regs to reload them into. Perhaps
4001 reusing reload regs from previous insns, or else output
4002 load insns to reload them. Maybe output store insns too.
4003 Record the choices of reload reg in reload_reg_rtx. */
4004 choose_reload_regs (chain);
4006 /* Merge any reloads that we didn't combine for fear of
4007 increasing the number of spill registers needed but now
4008 discover can be safely merged. */
4009 if (SMALL_REGISTER_CLASSES)
4010 merge_assigned_reloads (insn);
4012 /* Generate the insns to reload operands into or out of
4013 their reload regs. */
4014 emit_reload_insns (chain);
4016 /* Substitute the chosen reload regs from reload_reg_rtx
4017 into the insn's body (or perhaps into the bodies of other
4018 load and store insn that we just made for reloading
4019 and that we moved the structure into). */
4020 subst_reloads (insn);
4022 /* Adjust the exception region notes for loads and stores. */
4023 if (flag_non_call_exceptions && !CALL_P (insn))
4024 fixup_eh_region_note (insn, prev, next);
4026 /* If this was an ASM, make sure that all the reload insns
4027 we have generated are valid. If not, give an error
4029 if (asm_noperands (PATTERN (insn)) >= 0)
4030 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4031 if (p != insn && INSN_P (p)
4032 && GET_CODE (PATTERN (p)) != USE
4033 && (recog_memoized (p) < 0
4034 || (extract_insn (p), ! constrain_operands (1))))
4036 error_for_asm (insn,
4037 "%<asm%> operand requires "
4038 "impossible reload");
4043 if (num_eliminable && chain->need_elim)
4044 update_eliminable_offsets ();
4046 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4047 is no longer validly lying around to save a future reload.
4048 Note that this does not detect pseudos that were reloaded
4049 for this insn in order to be stored in
4050 (obeying register constraints). That is correct; such reload
4051 registers ARE still valid. */
4052 forget_marked_reloads (®s_to_forget);
4053 CLEAR_REG_SET (®s_to_forget);
4055 /* There may have been CLOBBER insns placed after INSN. So scan
4056 between INSN and NEXT and use them to forget old reloads. */
4057 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4058 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4059 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4062 /* Likewise for regs altered by auto-increment in this insn.
4063 REG_INC notes have been changed by reloading:
4064 find_reloads_address_1 records substitutions for them,
4065 which have been performed by subst_reloads above. */
4066 for (i = n_reloads - 1; i >= 0; i--)
4068 rtx in_reg = rld[i].in_reg;
4071 enum rtx_code code = GET_CODE (in_reg);
4072 /* PRE_INC / PRE_DEC will have the reload register ending up
4073 with the same value as the stack slot, but that doesn't
4074 hold true for POST_INC / POST_DEC. Either we have to
4075 convert the memory access to a true POST_INC / POST_DEC,
4076 or we can't use the reload register for inheritance. */
4077 if ((code == POST_INC || code == POST_DEC)
4078 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4079 REGNO (rld[i].reg_rtx))
4080 /* Make sure it is the inc/dec pseudo, and not
4081 some other (e.g. output operand) pseudo. */
4082 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4083 == REGNO (XEXP (in_reg, 0))))
4086 rtx reload_reg = rld[i].reg_rtx;
4087 enum machine_mode mode = GET_MODE (reload_reg);
4091 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4093 /* We really want to ignore REG_INC notes here, so
4094 use PATTERN (p) as argument to reg_set_p . */
4095 if (reg_set_p (reload_reg, PATTERN (p)))
4097 n = count_occurrences (PATTERN (p), reload_reg, 0);
4102 n = validate_replace_rtx (reload_reg,
4103 gen_rtx_fmt_e (code,
4108 /* We must also verify that the constraints
4109 are met after the replacement. */
4112 n = constrain_operands (1);
4116 /* If the constraints were not met, then
4117 undo the replacement. */
4120 validate_replace_rtx (gen_rtx_fmt_e (code,
4133 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4135 /* Mark this as having an output reload so that the
4136 REG_INC processing code below won't invalidate
4137 the reload for inheritance. */
4138 SET_HARD_REG_BIT (reg_is_output_reload,
4139 REGNO (reload_reg));
4140 SET_REGNO_REG_SET (®_has_output_reload,
4141 REGNO (XEXP (in_reg, 0)));
4144 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4147 else if ((code == PRE_INC || code == PRE_DEC)
4148 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4149 REGNO (rld[i].reg_rtx))
4150 /* Make sure it is the inc/dec pseudo, and not
4151 some other (e.g. output operand) pseudo. */
4152 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4153 == REGNO (XEXP (in_reg, 0))))
4155 SET_HARD_REG_BIT (reg_is_output_reload,
4156 REGNO (rld[i].reg_rtx));
4157 SET_REGNO_REG_SET (®_has_output_reload,
4158 REGNO (XEXP (in_reg, 0)));
4162 /* If a pseudo that got a hard register is auto-incremented,
4163 we must purge records of copying it into pseudos without
4165 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4166 if (REG_NOTE_KIND (x) == REG_INC)
4168 /* See if this pseudo reg was reloaded in this insn.
4169 If so, its last-reload info is still valid
4170 because it is based on this insn's reload. */
4171 for (i = 0; i < n_reloads; i++)
4172 if (rld[i].out == XEXP (x, 0))
4176 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4180 /* A reload reg's contents are unknown after a label. */
4182 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4184 /* Don't assume a reload reg is still good after a call insn
4185 if it is a call-used reg, or if it contains a value that will
4186 be partially clobbered by the call. */
4187 else if (CALL_P (insn))
4189 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4190 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4195 free (reg_last_reload_reg);
4196 CLEAR_REG_SET (®_has_output_reload);
4199 /* Discard all record of any value reloaded from X,
4200 or reloaded in X from someplace else;
4201 unless X is an output reload reg of the current insn.
4203 X may be a hard reg (the reload reg)
4204 or it may be a pseudo reg that was reloaded from.
4206 When DATA is non-NULL just mark the registers in regset
4207 to be forgotten later. */
4210 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4215 regset regs = (regset) data;
4217 /* note_stores does give us subregs of hard regs,
4218 subreg_regno_offset requires a hard reg. */
4219 while (GET_CODE (x) == SUBREG)
4221 /* We ignore the subreg offset when calculating the regno,
4222 because we are using the entire underlying hard register
4232 if (regno >= FIRST_PSEUDO_REGISTER)
4238 nr = hard_regno_nregs[regno][GET_MODE (x)];
4239 /* Storing into a spilled-reg invalidates its contents.
4240 This can happen if a block-local pseudo is allocated to that reg
4241 and it wasn't spilled because this block's total need is 0.
4242 Then some insn might have an optional reload and use this reg. */
4244 for (i = 0; i < nr; i++)
4245 /* But don't do this if the reg actually serves as an output
4246 reload reg in the current instruction. */
4248 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4250 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4251 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4252 spill_reg_store[regno + i] = 0;
4258 SET_REGNO_REG_SET (regs, regno + nr);
4261 /* Since value of X has changed,
4262 forget any value previously copied from it. */
4265 /* But don't forget a copy if this is the output reload
4266 that establishes the copy's validity. */
4268 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4269 reg_last_reload_reg[regno + nr] = 0;
4273 /* Forget the reloads marked in regset by previous function. */
4275 forget_marked_reloads (regset regs)
4278 reg_set_iterator rsi;
4279 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4281 if (reg < FIRST_PSEUDO_REGISTER
4282 /* But don't do this if the reg actually serves as an output
4283 reload reg in the current instruction. */
4285 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4287 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4288 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, reg);
4289 spill_reg_store[reg] = 0;
4292 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4293 reg_last_reload_reg[reg] = 0;
4297 /* The following HARD_REG_SETs indicate when each hard register is
4298 used for a reload of various parts of the current insn. */
4300 /* If reg is unavailable for all reloads. */
4301 static HARD_REG_SET reload_reg_unavailable;
4302 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4303 static HARD_REG_SET reload_reg_used;
4304 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4305 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4306 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4307 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4308 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4309 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4310 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4311 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4312 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4313 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4314 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4315 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4316 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4317 static HARD_REG_SET reload_reg_used_in_op_addr;
4318 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4319 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4320 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4321 static HARD_REG_SET reload_reg_used_in_insn;
4322 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4323 static HARD_REG_SET reload_reg_used_in_other_addr;
4325 /* If reg is in use as a reload reg for any sort of reload. */
4326 static HARD_REG_SET reload_reg_used_at_all;
4328 /* If reg is use as an inherited reload. We just mark the first register
4330 static HARD_REG_SET reload_reg_used_for_inherit;
4332 /* Records which hard regs are used in any way, either as explicit use or
4333 by being allocated to a pseudo during any point of the current insn. */
4334 static HARD_REG_SET reg_used_in_insn;
4336 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4337 TYPE. MODE is used to indicate how many consecutive regs are
4341 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4342 enum machine_mode mode)
4344 unsigned int nregs = hard_regno_nregs[regno][mode];
4347 for (i = regno; i < nregs + regno; i++)
4352 SET_HARD_REG_BIT (reload_reg_used, i);
4355 case RELOAD_FOR_INPUT_ADDRESS:
4356 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4359 case RELOAD_FOR_INPADDR_ADDRESS:
4360 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4363 case RELOAD_FOR_OUTPUT_ADDRESS:
4364 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4367 case RELOAD_FOR_OUTADDR_ADDRESS:
4368 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4371 case RELOAD_FOR_OPERAND_ADDRESS:
4372 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4375 case RELOAD_FOR_OPADDR_ADDR:
4376 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4379 case RELOAD_FOR_OTHER_ADDRESS:
4380 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4383 case RELOAD_FOR_INPUT:
4384 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4387 case RELOAD_FOR_OUTPUT:
4388 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4391 case RELOAD_FOR_INSN:
4392 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4396 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4400 /* Similarly, but show REGNO is no longer in use for a reload. */
4403 clear_reload_reg_in_use (unsigned int regno, int opnum,
4404 enum reload_type type, enum machine_mode mode)
4406 unsigned int nregs = hard_regno_nregs[regno][mode];
4407 unsigned int start_regno, end_regno, r;
4409 /* A complication is that for some reload types, inheritance might
4410 allow multiple reloads of the same types to share a reload register.
4411 We set check_opnum if we have to check only reloads with the same
4412 operand number, and check_any if we have to check all reloads. */
4413 int check_opnum = 0;
4415 HARD_REG_SET *used_in_set;
4420 used_in_set = &reload_reg_used;
4423 case RELOAD_FOR_INPUT_ADDRESS:
4424 used_in_set = &reload_reg_used_in_input_addr[opnum];
4427 case RELOAD_FOR_INPADDR_ADDRESS:
4429 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4432 case RELOAD_FOR_OUTPUT_ADDRESS:
4433 used_in_set = &reload_reg_used_in_output_addr[opnum];
4436 case RELOAD_FOR_OUTADDR_ADDRESS:
4438 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4441 case RELOAD_FOR_OPERAND_ADDRESS:
4442 used_in_set = &reload_reg_used_in_op_addr;
4445 case RELOAD_FOR_OPADDR_ADDR:
4447 used_in_set = &reload_reg_used_in_op_addr_reload;
4450 case RELOAD_FOR_OTHER_ADDRESS:
4451 used_in_set = &reload_reg_used_in_other_addr;
4455 case RELOAD_FOR_INPUT:
4456 used_in_set = &reload_reg_used_in_input[opnum];
4459 case RELOAD_FOR_OUTPUT:
4460 used_in_set = &reload_reg_used_in_output[opnum];
4463 case RELOAD_FOR_INSN:
4464 used_in_set = &reload_reg_used_in_insn;
4469 /* We resolve conflicts with remaining reloads of the same type by
4470 excluding the intervals of reload registers by them from the
4471 interval of freed reload registers. Since we only keep track of
4472 one set of interval bounds, we might have to exclude somewhat
4473 more than what would be necessary if we used a HARD_REG_SET here.
4474 But this should only happen very infrequently, so there should
4475 be no reason to worry about it. */
4477 start_regno = regno;
4478 end_regno = regno + nregs;
4479 if (check_opnum || check_any)
4481 for (i = n_reloads - 1; i >= 0; i--)
4483 if (rld[i].when_needed == type
4484 && (check_any || rld[i].opnum == opnum)
4487 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4488 unsigned int conflict_end
4490 + hard_regno_nregs[conflict_start][rld[i].mode]);
4492 /* If there is an overlap with the first to-be-freed register,
4493 adjust the interval start. */
4494 if (conflict_start <= start_regno && conflict_end > start_regno)
4495 start_regno = conflict_end;
4496 /* Otherwise, if there is a conflict with one of the other
4497 to-be-freed registers, adjust the interval end. */
4498 if (conflict_start > start_regno && conflict_start < end_regno)
4499 end_regno = conflict_start;
4504 for (r = start_regno; r < end_regno; r++)
4505 CLEAR_HARD_REG_BIT (*used_in_set, r);
4508 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4509 specified by OPNUM and TYPE. */
4512 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4516 /* In use for a RELOAD_OTHER means it's not available for anything. */
4517 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4518 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4524 /* In use for anything means we can't use it for RELOAD_OTHER. */
4525 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4526 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4527 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4528 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4531 for (i = 0; i < reload_n_operands; i++)
4532 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4533 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4534 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4535 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4536 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4537 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4542 case RELOAD_FOR_INPUT:
4543 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4544 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4547 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4550 /* If it is used for some other input, can't use it. */
4551 for (i = 0; i < reload_n_operands; i++)
4552 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4555 /* If it is used in a later operand's address, can't use it. */
4556 for (i = opnum + 1; i < reload_n_operands; i++)
4557 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4558 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4563 case RELOAD_FOR_INPUT_ADDRESS:
4564 /* Can't use a register if it is used for an input address for this
4565 operand or used as an input in an earlier one. */
4566 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4567 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4570 for (i = 0; i < opnum; i++)
4571 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4576 case RELOAD_FOR_INPADDR_ADDRESS:
4577 /* Can't use a register if it is used for an input address
4578 for this operand or used as an input in an earlier
4580 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4583 for (i = 0; i < opnum; i++)
4584 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4589 case RELOAD_FOR_OUTPUT_ADDRESS:
4590 /* Can't use a register if it is used for an output address for this
4591 operand or used as an output in this or a later operand. Note
4592 that multiple output operands are emitted in reverse order, so
4593 the conflicting ones are those with lower indices. */
4594 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4597 for (i = 0; i <= opnum; i++)
4598 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4603 case RELOAD_FOR_OUTADDR_ADDRESS:
4604 /* Can't use a register if it is used for an output address
4605 for this operand or used as an output in this or a
4606 later operand. Note that multiple output operands are
4607 emitted in reverse order, so the conflicting ones are
4608 those with lower indices. */
4609 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4612 for (i = 0; i <= opnum; i++)
4613 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4618 case RELOAD_FOR_OPERAND_ADDRESS:
4619 for (i = 0; i < reload_n_operands; i++)
4620 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4623 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4624 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4626 case RELOAD_FOR_OPADDR_ADDR:
4627 for (i = 0; i < reload_n_operands; i++)
4628 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4631 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4633 case RELOAD_FOR_OUTPUT:
4634 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4635 outputs, or an operand address for this or an earlier output.
4636 Note that multiple output operands are emitted in reverse order,
4637 so the conflicting ones are those with higher indices. */
4638 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4641 for (i = 0; i < reload_n_operands; i++)
4642 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4645 for (i = opnum; i < reload_n_operands; i++)
4646 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4647 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4652 case RELOAD_FOR_INSN:
4653 for (i = 0; i < reload_n_operands; i++)
4654 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4655 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4658 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4659 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4661 case RELOAD_FOR_OTHER_ADDRESS:
4662 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4669 /* Return 1 if the value in reload reg REGNO, as used by a reload
4670 needed for the part of the insn specified by OPNUM and TYPE,
4671 is still available in REGNO at the end of the insn.
4673 We can assume that the reload reg was already tested for availability
4674 at the time it is needed, and we should not check this again,
4675 in case the reg has already been marked in use. */
4678 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4685 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4686 its value must reach the end. */
4689 /* If this use is for part of the insn,
4690 its value reaches if no subsequent part uses the same register.
4691 Just like the above function, don't try to do this with lots
4694 case RELOAD_FOR_OTHER_ADDRESS:
4695 /* Here we check for everything else, since these don't conflict
4696 with anything else and everything comes later. */
4698 for (i = 0; i < reload_n_operands; i++)
4699 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4700 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4701 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4702 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4703 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4704 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4707 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4708 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4709 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4710 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4712 case RELOAD_FOR_INPUT_ADDRESS:
4713 case RELOAD_FOR_INPADDR_ADDRESS:
4714 /* Similar, except that we check only for this and subsequent inputs
4715 and the address of only subsequent inputs and we do not need
4716 to check for RELOAD_OTHER objects since they are known not to
4719 for (i = opnum; i < reload_n_operands; i++)
4720 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4723 for (i = opnum + 1; i < reload_n_operands; i++)
4724 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4725 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4728 for (i = 0; i < reload_n_operands; i++)
4729 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4730 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4731 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4734 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4737 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4738 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4739 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4741 case RELOAD_FOR_INPUT:
4742 /* Similar to input address, except we start at the next operand for
4743 both input and input address and we do not check for
4744 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4747 for (i = opnum + 1; i < reload_n_operands; i++)
4748 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4749 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4750 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4753 /* ... fall through ... */
4755 case RELOAD_FOR_OPERAND_ADDRESS:
4756 /* Check outputs and their addresses. */
4758 for (i = 0; i < reload_n_operands; i++)
4759 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4760 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4761 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4764 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4766 case RELOAD_FOR_OPADDR_ADDR:
4767 for (i = 0; i < reload_n_operands; i++)
4768 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4769 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4770 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4773 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4774 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4775 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4777 case RELOAD_FOR_INSN:
4778 /* These conflict with other outputs with RELOAD_OTHER. So
4779 we need only check for output addresses. */
4781 opnum = reload_n_operands;
4783 /* ... fall through ... */
4785 case RELOAD_FOR_OUTPUT:
4786 case RELOAD_FOR_OUTPUT_ADDRESS:
4787 case RELOAD_FOR_OUTADDR_ADDRESS:
4788 /* We already know these can't conflict with a later output. So the
4789 only thing to check are later output addresses.
4790 Note that multiple output operands are emitted in reverse order,
4791 so the conflicting ones are those with lower indices. */
4792 for (i = 0; i < opnum; i++)
4793 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4794 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4805 /* Returns whether R1 and R2 are uniquely chained: the value of one
4806 is used by the other, and that value is not used by any other
4807 reload for this insn. This is used to partially undo the decision
4808 made in find_reloads when in the case of multiple
4809 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
4810 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
4811 reloads. This code tries to avoid the conflict created by that
4812 change. It might be cleaner to explicitly keep track of which
4813 RELOAD_FOR_OPADDR_ADDR reload is associated with which
4814 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
4815 this after the fact. */
4817 reloads_unique_chain_p (int r1, int r2)
4821 /* We only check input reloads. */
4822 if (! rld[r1].in || ! rld[r2].in)
4825 /* Avoid anything with output reloads. */
4826 if (rld[r1].out || rld[r2].out)
4829 /* "chained" means one reload is a component of the other reload,
4830 not the same as the other reload. */
4831 if (rld[r1].opnum != rld[r2].opnum
4832 || rtx_equal_p (rld[r1].in, rld[r2].in)
4833 || rld[r1].optional || rld[r2].optional
4834 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
4835 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
4838 for (i = 0; i < n_reloads; i ++)
4839 /* Look for input reloads that aren't our two */
4840 if (i != r1 && i != r2 && rld[i].in)
4842 /* If our reload is mentioned at all, it isn't a simple chain. */
4843 if (reg_mentioned_p (rld[r1].in, rld[i].in))
4849 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4852 This function uses the same algorithm as reload_reg_free_p above. */
4855 reloads_conflict (int r1, int r2)
4857 enum reload_type r1_type = rld[r1].when_needed;
4858 enum reload_type r2_type = rld[r2].when_needed;
4859 int r1_opnum = rld[r1].opnum;
4860 int r2_opnum = rld[r2].opnum;
4862 /* RELOAD_OTHER conflicts with everything. */
4863 if (r2_type == RELOAD_OTHER)
4866 /* Otherwise, check conflicts differently for each type. */
4870 case RELOAD_FOR_INPUT:
4871 return (r2_type == RELOAD_FOR_INSN
4872 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4873 || r2_type == RELOAD_FOR_OPADDR_ADDR
4874 || r2_type == RELOAD_FOR_INPUT
4875 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4876 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4877 && r2_opnum > r1_opnum));
4879 case RELOAD_FOR_INPUT_ADDRESS:
4880 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4881 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4883 case RELOAD_FOR_INPADDR_ADDRESS:
4884 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4885 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4887 case RELOAD_FOR_OUTPUT_ADDRESS:
4888 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4889 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4891 case RELOAD_FOR_OUTADDR_ADDRESS:
4892 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4893 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4895 case RELOAD_FOR_OPERAND_ADDRESS:
4896 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4897 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
4898 && !reloads_unique_chain_p (r1, r2)));
4900 case RELOAD_FOR_OPADDR_ADDR:
4901 return (r2_type == RELOAD_FOR_INPUT
4902 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4904 case RELOAD_FOR_OUTPUT:
4905 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4906 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4907 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4908 && r2_opnum >= r1_opnum));
4910 case RELOAD_FOR_INSN:
4911 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4912 || r2_type == RELOAD_FOR_INSN
4913 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4915 case RELOAD_FOR_OTHER_ADDRESS:
4916 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4926 /* Indexed by reload number, 1 if incoming value
4927 inherited from previous insns. */
4928 static char reload_inherited[MAX_RELOADS];
4930 /* For an inherited reload, this is the insn the reload was inherited from,
4931 if we know it. Otherwise, this is 0. */
4932 static rtx reload_inheritance_insn[MAX_RELOADS];
4934 /* If nonzero, this is a place to get the value of the reload,
4935 rather than using reload_in. */
4936 static rtx reload_override_in[MAX_RELOADS];
4938 /* For each reload, the hard register number of the register used,
4939 or -1 if we did not need a register for this reload. */
4940 static int reload_spill_index[MAX_RELOADS];
4942 /* Subroutine of free_for_value_p, used to check a single register.
4943 START_REGNO is the starting regno of the full reload register
4944 (possibly comprising multiple hard registers) that we are considering. */
4947 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4948 enum reload_type type, rtx value, rtx out,
4949 int reloadnum, int ignore_address_reloads)
4952 /* Set if we see an input reload that must not share its reload register
4953 with any new earlyclobber, but might otherwise share the reload
4954 register with an output or input-output reload. */
4955 int check_earlyclobber = 0;
4959 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4962 if (out == const0_rtx)
4968 /* We use some pseudo 'time' value to check if the lifetimes of the
4969 new register use would overlap with the one of a previous reload
4970 that is not read-only or uses a different value.
4971 The 'time' used doesn't have to be linear in any shape or form, just
4973 Some reload types use different 'buckets' for each operand.
4974 So there are MAX_RECOG_OPERANDS different time values for each
4976 We compute TIME1 as the time when the register for the prospective
4977 new reload ceases to be live, and TIME2 for each existing
4978 reload as the time when that the reload register of that reload
4980 Where there is little to be gained by exact lifetime calculations,
4981 we just make conservative assumptions, i.e. a longer lifetime;
4982 this is done in the 'default:' cases. */
4985 case RELOAD_FOR_OTHER_ADDRESS:
4986 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4987 time1 = copy ? 0 : 1;
4990 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4992 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4993 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4994 respectively, to the time values for these, we get distinct time
4995 values. To get distinct time values for each operand, we have to
4996 multiply opnum by at least three. We round that up to four because
4997 multiply by four is often cheaper. */
4998 case RELOAD_FOR_INPADDR_ADDRESS:
4999 time1 = opnum * 4 + 2;
5001 case RELOAD_FOR_INPUT_ADDRESS:
5002 time1 = opnum * 4 + 3;
5004 case RELOAD_FOR_INPUT:
5005 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5006 executes (inclusive). */
5007 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5009 case RELOAD_FOR_OPADDR_ADDR:
5011 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5012 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5014 case RELOAD_FOR_OPERAND_ADDRESS:
5015 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5017 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5019 case RELOAD_FOR_OUTADDR_ADDRESS:
5020 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5022 case RELOAD_FOR_OUTPUT_ADDRESS:
5023 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5026 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5029 for (i = 0; i < n_reloads; i++)
5031 rtx reg = rld[i].reg_rtx;
5032 if (reg && REG_P (reg)
5033 && ((unsigned) regno - true_regnum (reg)
5034 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5037 rtx other_input = rld[i].in;
5039 /* If the other reload loads the same input value, that
5040 will not cause a conflict only if it's loading it into
5041 the same register. */
5042 if (true_regnum (reg) != start_regno)
5043 other_input = NULL_RTX;
5044 if (! other_input || ! rtx_equal_p (other_input, value)
5045 || rld[i].out || out)
5048 switch (rld[i].when_needed)
5050 case RELOAD_FOR_OTHER_ADDRESS:
5053 case RELOAD_FOR_INPADDR_ADDRESS:
5054 /* find_reloads makes sure that a
5055 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5056 by at most one - the first -
5057 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5058 address reload is inherited, the address address reload
5059 goes away, so we can ignore this conflict. */
5060 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5061 && ignore_address_reloads
5062 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5063 Then the address address is still needed to store
5064 back the new address. */
5065 && ! rld[reloadnum].out)
5067 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5068 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5070 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5071 && ignore_address_reloads
5072 /* Unless we are reloading an auto_inc expression. */
5073 && ! rld[reloadnum].out)
5075 time2 = rld[i].opnum * 4 + 2;
5077 case RELOAD_FOR_INPUT_ADDRESS:
5078 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5079 && ignore_address_reloads
5080 && ! rld[reloadnum].out)
5082 time2 = rld[i].opnum * 4 + 3;
5084 case RELOAD_FOR_INPUT:
5085 time2 = rld[i].opnum * 4 + 4;
5086 check_earlyclobber = 1;
5088 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5089 == MAX_RECOG_OPERAND * 4 */
5090 case RELOAD_FOR_OPADDR_ADDR:
5091 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5092 && ignore_address_reloads
5093 && ! rld[reloadnum].out)
5095 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5097 case RELOAD_FOR_OPERAND_ADDRESS:
5098 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5099 check_earlyclobber = 1;
5101 case RELOAD_FOR_INSN:
5102 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5104 case RELOAD_FOR_OUTPUT:
5105 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5106 instruction is executed. */
5107 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5109 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5110 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5112 case RELOAD_FOR_OUTADDR_ADDRESS:
5113 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5114 && ignore_address_reloads
5115 && ! rld[reloadnum].out)
5117 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5119 case RELOAD_FOR_OUTPUT_ADDRESS:
5120 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5123 /* If there is no conflict in the input part, handle this
5124 like an output reload. */
5125 if (! rld[i].in || rtx_equal_p (other_input, value))
5127 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5128 /* Earlyclobbered outputs must conflict with inputs. */
5129 if (earlyclobber_operand_p (rld[i].out))
5130 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5135 /* RELOAD_OTHER might be live beyond instruction execution,
5136 but this is not obvious when we set time2 = 1. So check
5137 here if there might be a problem with the new reload
5138 clobbering the register used by the RELOAD_OTHER. */
5146 && (! rld[i].in || rld[i].out
5147 || ! rtx_equal_p (other_input, value)))
5148 || (out && rld[reloadnum].out_reg
5149 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5155 /* Earlyclobbered outputs must conflict with inputs. */
5156 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5162 /* Return 1 if the value in reload reg REGNO, as used by a reload
5163 needed for the part of the insn specified by OPNUM and TYPE,
5164 may be used to load VALUE into it.
5166 MODE is the mode in which the register is used, this is needed to
5167 determine how many hard regs to test.
5169 Other read-only reloads with the same value do not conflict
5170 unless OUT is nonzero and these other reloads have to live while
5171 output reloads live.
5172 If OUT is CONST0_RTX, this is a special case: it means that the
5173 test should not be for using register REGNO as reload register, but
5174 for copying from register REGNO into the reload register.
5176 RELOADNUM is the number of the reload we want to load this value for;
5177 a reload does not conflict with itself.
5179 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5180 reloads that load an address for the very reload we are considering.
5182 The caller has to make sure that there is no conflict with the return
5186 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5187 enum reload_type type, rtx value, rtx out, int reloadnum,
5188 int ignore_address_reloads)
5190 int nregs = hard_regno_nregs[regno][mode];
5192 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5193 value, out, reloadnum,
5194 ignore_address_reloads))
5199 /* Return nonzero if the rtx X is invariant over the current function. */
5200 /* ??? Actually, the places where we use this expect exactly what is
5201 tested here, and not everything that is function invariant. In
5202 particular, the frame pointer and arg pointer are special cased;
5203 pic_offset_table_rtx is not, and we must not spill these things to
5207 function_invariant_p (rtx x)
5211 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5213 if (GET_CODE (x) == PLUS
5214 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5215 && CONSTANT_P (XEXP (x, 1)))
5220 /* Determine whether the reload reg X overlaps any rtx'es used for
5221 overriding inheritance. Return nonzero if so. */
5224 conflicts_with_override (rtx x)
5227 for (i = 0; i < n_reloads; i++)
5228 if (reload_override_in[i]
5229 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5234 /* Give an error message saying we failed to find a reload for INSN,
5235 and clear out reload R. */
5237 failed_reload (rtx insn, int r)
5239 if (asm_noperands (PATTERN (insn)) < 0)
5240 /* It's the compiler's fault. */
5241 fatal_insn ("could not find a spill register", insn);
5243 /* It's the user's fault; the operand's mode and constraint
5244 don't match. Disable this reload so we don't crash in final. */
5245 error_for_asm (insn,
5246 "%<asm%> operand constraint incompatible with operand size");
5250 rld[r].optional = 1;
5251 rld[r].secondary_p = 1;
5254 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5255 for reload R. If it's valid, get an rtx for it. Return nonzero if
5258 set_reload_reg (int i, int r)
5261 rtx reg = spill_reg_rtx[i];
5263 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5264 spill_reg_rtx[i] = reg
5265 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5267 regno = true_regnum (reg);
5269 /* Detect when the reload reg can't hold the reload mode.
5270 This used to be one `if', but Sequent compiler can't handle that. */
5271 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5273 enum machine_mode test_mode = VOIDmode;
5275 test_mode = GET_MODE (rld[r].in);
5276 /* If rld[r].in has VOIDmode, it means we will load it
5277 in whatever mode the reload reg has: to wit, rld[r].mode.
5278 We have already tested that for validity. */
5279 /* Aside from that, we need to test that the expressions
5280 to reload from or into have modes which are valid for this
5281 reload register. Otherwise the reload insns would be invalid. */
5282 if (! (rld[r].in != 0 && test_mode != VOIDmode
5283 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5284 if (! (rld[r].out != 0
5285 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5287 /* The reg is OK. */
5290 /* Mark as in use for this insn the reload regs we use
5292 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5293 rld[r].when_needed, rld[r].mode);
5295 rld[r].reg_rtx = reg;
5296 reload_spill_index[r] = spill_regs[i];
5303 /* Find a spill register to use as a reload register for reload R.
5304 LAST_RELOAD is nonzero if this is the last reload for the insn being
5307 Set rld[R].reg_rtx to the register allocated.
5309 We return 1 if successful, or 0 if we couldn't find a spill reg and
5310 we didn't change anything. */
5313 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5318 /* If we put this reload ahead, thinking it is a group,
5319 then insist on finding a group. Otherwise we can grab a
5320 reg that some other reload needs.
5321 (That can happen when we have a 68000 DATA_OR_FP_REG
5322 which is a group of data regs or one fp reg.)
5323 We need not be so restrictive if there are no more reloads
5326 ??? Really it would be nicer to have smarter handling
5327 for that kind of reg class, where a problem like this is normal.
5328 Perhaps those classes should be avoided for reloading
5329 by use of more alternatives. */
5331 int force_group = rld[r].nregs > 1 && ! last_reload;
5333 /* If we want a single register and haven't yet found one,
5334 take any reg in the right class and not in use.
5335 If we want a consecutive group, here is where we look for it.
5337 We use two passes so we can first look for reload regs to
5338 reuse, which are already in use for other reloads in this insn,
5339 and only then use additional registers.
5340 I think that maximizing reuse is needed to make sure we don't
5341 run out of reload regs. Suppose we have three reloads, and
5342 reloads A and B can share regs. These need two regs.
5343 Suppose A and B are given different regs.
5344 That leaves none for C. */
5345 for (pass = 0; pass < 2; pass++)
5347 /* I is the index in spill_regs.
5348 We advance it round-robin between insns to use all spill regs
5349 equally, so that inherited reloads have a chance
5350 of leapfrogging each other. */
5354 for (count = 0; count < n_spills; count++)
5356 int class = (int) rld[r].class;
5362 regnum = spill_regs[i];
5364 if ((reload_reg_free_p (regnum, rld[r].opnum,
5367 /* We check reload_reg_used to make sure we
5368 don't clobber the return register. */
5369 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5370 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5371 rld[r].when_needed, rld[r].in,
5373 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5374 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5375 /* Look first for regs to share, then for unshared. But
5376 don't share regs used for inherited reloads; they are
5377 the ones we want to preserve. */
5379 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5381 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5384 int nr = hard_regno_nregs[regnum][rld[r].mode];
5385 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5386 (on 68000) got us two FP regs. If NR is 1,
5387 we would reject both of them. */
5390 /* If we need only one reg, we have already won. */
5393 /* But reject a single reg if we demand a group. */
5398 /* Otherwise check that as many consecutive regs as we need
5399 are available here. */
5402 int regno = regnum + nr - 1;
5403 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5404 && spill_reg_order[regno] >= 0
5405 && reload_reg_free_p (regno, rld[r].opnum,
5406 rld[r].when_needed)))
5415 /* If we found something on pass 1, omit pass 2. */
5416 if (count < n_spills)
5420 /* We should have found a spill register by now. */
5421 if (count >= n_spills)
5424 /* I is the index in SPILL_REG_RTX of the reload register we are to
5425 allocate. Get an rtx for it and find its register number. */
5427 return set_reload_reg (i, r);
5430 /* Initialize all the tables needed to allocate reload registers.
5431 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5432 is the array we use to restore the reg_rtx field for every reload. */
5435 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5439 for (i = 0; i < n_reloads; i++)
5440 rld[i].reg_rtx = save_reload_reg_rtx[i];
5442 memset (reload_inherited, 0, MAX_RELOADS);
5443 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5444 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5446 CLEAR_HARD_REG_SET (reload_reg_used);
5447 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5448 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5449 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5450 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5451 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5453 CLEAR_HARD_REG_SET (reg_used_in_insn);
5456 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5457 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5458 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5459 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5460 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5461 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5464 for (i = 0; i < reload_n_operands; i++)
5466 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5467 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5468 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5469 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5470 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5471 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5474 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5476 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5478 for (i = 0; i < n_reloads; i++)
5479 /* If we have already decided to use a certain register,
5480 don't use it in another way. */
5482 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5483 rld[i].when_needed, rld[i].mode);
5486 /* Assign hard reg targets for the pseudo-registers we must reload
5487 into hard regs for this insn.
5488 Also output the instructions to copy them in and out of the hard regs.
5490 For machines with register classes, we are responsible for
5491 finding a reload reg in the proper class. */
5494 choose_reload_regs (struct insn_chain *chain)
5496 rtx insn = chain->insn;
5498 unsigned int max_group_size = 1;
5499 enum reg_class group_class = NO_REGS;
5500 int pass, win, inheritance;
5502 rtx save_reload_reg_rtx[MAX_RELOADS];
5504 /* In order to be certain of getting the registers we need,
5505 we must sort the reloads into order of increasing register class.
5506 Then our grabbing of reload registers will parallel the process
5507 that provided the reload registers.
5509 Also note whether any of the reloads wants a consecutive group of regs.
5510 If so, record the maximum size of the group desired and what
5511 register class contains all the groups needed by this insn. */
5513 for (j = 0; j < n_reloads; j++)
5515 reload_order[j] = j;
5516 reload_spill_index[j] = -1;
5518 if (rld[j].nregs > 1)
5520 max_group_size = MAX (rld[j].nregs, max_group_size);
5522 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5525 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5529 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5531 /* If -O, try first with inheritance, then turning it off.
5532 If not -O, don't do inheritance.
5533 Using inheritance when not optimizing leads to paradoxes
5534 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5535 because one side of the comparison might be inherited. */
5537 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5539 choose_reload_regs_init (chain, save_reload_reg_rtx);
5541 /* Process the reloads in order of preference just found.
5542 Beyond this point, subregs can be found in reload_reg_rtx.
5544 This used to look for an existing reloaded home for all of the
5545 reloads, and only then perform any new reloads. But that could lose
5546 if the reloads were done out of reg-class order because a later
5547 reload with a looser constraint might have an old home in a register
5548 needed by an earlier reload with a tighter constraint.
5550 To solve this, we make two passes over the reloads, in the order
5551 described above. In the first pass we try to inherit a reload
5552 from a previous insn. If there is a later reload that needs a
5553 class that is a proper subset of the class being processed, we must
5554 also allocate a spill register during the first pass.
5556 Then make a second pass over the reloads to allocate any reloads
5557 that haven't been given registers yet. */
5559 for (j = 0; j < n_reloads; j++)
5561 int r = reload_order[j];
5562 rtx search_equiv = NULL_RTX;
5564 /* Ignore reloads that got marked inoperative. */
5565 if (rld[r].out == 0 && rld[r].in == 0
5566 && ! rld[r].secondary_p)
5569 /* If find_reloads chose to use reload_in or reload_out as a reload
5570 register, we don't need to chose one. Otherwise, try even if it
5571 found one since we might save an insn if we find the value lying
5573 Try also when reload_in is a pseudo without a hard reg. */
5574 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5575 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5576 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5577 && !MEM_P (rld[r].in)
5578 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5581 #if 0 /* No longer needed for correct operation.
5582 It might give better code, or might not; worth an experiment? */
5583 /* If this is an optional reload, we can't inherit from earlier insns
5584 until we are sure that any non-optional reloads have been allocated.
5585 The following code takes advantage of the fact that optional reloads
5586 are at the end of reload_order. */
5587 if (rld[r].optional != 0)
5588 for (i = 0; i < j; i++)
5589 if ((rld[reload_order[i]].out != 0
5590 || rld[reload_order[i]].in != 0
5591 || rld[reload_order[i]].secondary_p)
5592 && ! rld[reload_order[i]].optional
5593 && rld[reload_order[i]].reg_rtx == 0)
5594 allocate_reload_reg (chain, reload_order[i], 0);
5597 /* First see if this pseudo is already available as reloaded
5598 for a previous insn. We cannot try to inherit for reloads
5599 that are smaller than the maximum number of registers needed
5600 for groups unless the register we would allocate cannot be used
5603 We could check here to see if this is a secondary reload for
5604 an object that is already in a register of the desired class.
5605 This would avoid the need for the secondary reload register.
5606 But this is complex because we can't easily determine what
5607 objects might want to be loaded via this reload. So let a
5608 register be allocated here. In `emit_reload_insns' we suppress
5609 one of the loads in the case described above. */
5615 enum machine_mode mode = VOIDmode;
5619 else if (REG_P (rld[r].in))
5621 regno = REGNO (rld[r].in);
5622 mode = GET_MODE (rld[r].in);
5624 else if (REG_P (rld[r].in_reg))
5626 regno = REGNO (rld[r].in_reg);
5627 mode = GET_MODE (rld[r].in_reg);
5629 else if (GET_CODE (rld[r].in_reg) == SUBREG
5630 && REG_P (SUBREG_REG (rld[r].in_reg)))
5632 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5633 if (regno < FIRST_PSEUDO_REGISTER)
5634 regno = subreg_regno (rld[r].in_reg);
5636 byte = SUBREG_BYTE (rld[r].in_reg);
5637 mode = GET_MODE (rld[r].in_reg);
5640 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
5641 && REG_P (XEXP (rld[r].in_reg, 0)))
5643 regno = REGNO (XEXP (rld[r].in_reg, 0));
5644 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5645 rld[r].out = rld[r].in;
5649 /* This won't work, since REGNO can be a pseudo reg number.
5650 Also, it takes much more hair to keep track of all the things
5651 that can invalidate an inherited reload of part of a pseudoreg. */
5652 else if (GET_CODE (rld[r].in) == SUBREG
5653 && REG_P (SUBREG_REG (rld[r].in)))
5654 regno = subreg_regno (rld[r].in);
5658 && reg_last_reload_reg[regno] != 0
5659 #ifdef CANNOT_CHANGE_MODE_CLASS
5660 /* Verify that the register it's in can be used in
5662 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
5663 GET_MODE (reg_last_reload_reg[regno]),
5668 enum reg_class class = rld[r].class, last_class;
5669 rtx last_reg = reg_last_reload_reg[regno];
5670 enum machine_mode need_mode;
5672 i = REGNO (last_reg);
5673 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5674 last_class = REGNO_REG_CLASS (i);
5680 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
5681 + byte * BITS_PER_UNIT,
5682 GET_MODE_CLASS (mode));
5684 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5685 >= GET_MODE_SIZE (need_mode))
5686 && reg_reloaded_contents[i] == regno
5687 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5688 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5689 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5690 /* Even if we can't use this register as a reload
5691 register, we might use it for reload_override_in,
5692 if copying it to the desired class is cheap
5694 || ((REGISTER_MOVE_COST (mode, last_class, class)
5695 < MEMORY_MOVE_COST (mode, class, 1))
5696 && (secondary_reload_class (1, class, mode,
5699 #ifdef SECONDARY_MEMORY_NEEDED
5700 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5705 && (rld[r].nregs == max_group_size
5706 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5708 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5709 rld[r].when_needed, rld[r].in,
5712 /* If a group is needed, verify that all the subsequent
5713 registers still have their values intact. */
5714 int nr = hard_regno_nregs[i][rld[r].mode];
5717 for (k = 1; k < nr; k++)
5718 if (reg_reloaded_contents[i + k] != regno
5719 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5727 last_reg = (GET_MODE (last_reg) == mode
5728 ? last_reg : gen_rtx_REG (mode, i));
5731 for (k = 0; k < nr; k++)
5732 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5735 /* We found a register that contains the
5736 value we need. If this register is the
5737 same as an `earlyclobber' operand of the
5738 current insn, just mark it as a place to
5739 reload from since we can't use it as the
5740 reload register itself. */
5742 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5743 if (reg_overlap_mentioned_for_reload_p
5744 (reg_last_reload_reg[regno],
5745 reload_earlyclobbers[i1]))
5748 if (i1 != n_earlyclobbers
5749 || ! (free_for_value_p (i, rld[r].mode,
5751 rld[r].when_needed, rld[r].in,
5753 /* Don't use it if we'd clobber a pseudo reg. */
5754 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5756 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5757 /* Don't clobber the frame pointer. */
5758 || (i == HARD_FRAME_POINTER_REGNUM
5759 && frame_pointer_needed
5761 /* Don't really use the inherited spill reg
5762 if we need it wider than we've got it. */
5763 || (GET_MODE_SIZE (rld[r].mode)
5764 > GET_MODE_SIZE (mode))
5767 /* If find_reloads chose reload_out as reload
5768 register, stay with it - that leaves the
5769 inherited register for subsequent reloads. */
5770 || (rld[r].out && rld[r].reg_rtx
5771 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5773 if (! rld[r].optional)
5775 reload_override_in[r] = last_reg;
5776 reload_inheritance_insn[r]
5777 = reg_reloaded_insn[i];
5783 /* We can use this as a reload reg. */
5784 /* Mark the register as in use for this part of
5786 mark_reload_reg_in_use (i,
5790 rld[r].reg_rtx = last_reg;
5791 reload_inherited[r] = 1;
5792 reload_inheritance_insn[r]
5793 = reg_reloaded_insn[i];
5794 reload_spill_index[r] = i;
5795 for (k = 0; k < nr; k++)
5796 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5804 /* Here's another way to see if the value is already lying around. */
5807 && ! reload_inherited[r]
5809 && (CONSTANT_P (rld[r].in)
5810 || GET_CODE (rld[r].in) == PLUS
5811 || REG_P (rld[r].in)
5812 || MEM_P (rld[r].in))
5813 && (rld[r].nregs == max_group_size
5814 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5815 search_equiv = rld[r].in;
5816 /* If this is an output reload from a simple move insn, look
5817 if an equivalence for the input is available. */
5818 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5820 rtx set = single_set (insn);
5823 && rtx_equal_p (rld[r].out, SET_DEST (set))
5824 && CONSTANT_P (SET_SRC (set)))
5825 search_equiv = SET_SRC (set);
5831 = find_equiv_reg (search_equiv, insn, rld[r].class,
5832 -1, NULL, 0, rld[r].mode);
5838 regno = REGNO (equiv);
5841 /* This must be a SUBREG of a hard register.
5842 Make a new REG since this might be used in an
5843 address and not all machines support SUBREGs
5845 gcc_assert (GET_CODE (equiv) == SUBREG);
5846 regno = subreg_regno (equiv);
5847 equiv = gen_rtx_REG (rld[r].mode, regno);
5848 /* If we choose EQUIV as the reload register, but the
5849 loop below decides to cancel the inheritance, we'll
5850 end up reloading EQUIV in rld[r].mode, not the mode
5851 it had originally. That isn't safe when EQUIV isn't
5852 available as a spill register since its value might
5853 still be live at this point. */
5854 for (i = regno; i < regno + (int) rld[r].nregs; i++)
5855 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
5860 /* If we found a spill reg, reject it unless it is free
5861 and of the desired class. */
5865 int bad_for_class = 0;
5866 int max_regno = regno + rld[r].nregs;
5868 for (i = regno; i < max_regno; i++)
5870 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5872 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5877 && ! free_for_value_p (regno, rld[r].mode,
5878 rld[r].opnum, rld[r].when_needed,
5879 rld[r].in, rld[r].out, r, 1))
5884 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5887 /* We found a register that contains the value we need.
5888 If this register is the same as an `earlyclobber' operand
5889 of the current insn, just mark it as a place to reload from
5890 since we can't use it as the reload register itself. */
5893 for (i = 0; i < n_earlyclobbers; i++)
5894 if (reg_overlap_mentioned_for_reload_p (equiv,
5895 reload_earlyclobbers[i]))
5897 if (! rld[r].optional)
5898 reload_override_in[r] = equiv;
5903 /* If the equiv register we have found is explicitly clobbered
5904 in the current insn, it depends on the reload type if we
5905 can use it, use it for reload_override_in, or not at all.
5906 In particular, we then can't use EQUIV for a
5907 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5911 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
5912 switch (rld[r].when_needed)
5914 case RELOAD_FOR_OTHER_ADDRESS:
5915 case RELOAD_FOR_INPADDR_ADDRESS:
5916 case RELOAD_FOR_INPUT_ADDRESS:
5917 case RELOAD_FOR_OPADDR_ADDR:
5920 case RELOAD_FOR_INPUT:
5921 case RELOAD_FOR_OPERAND_ADDRESS:
5922 if (! rld[r].optional)
5923 reload_override_in[r] = equiv;
5929 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5930 switch (rld[r].when_needed)
5932 case RELOAD_FOR_OTHER_ADDRESS:
5933 case RELOAD_FOR_INPADDR_ADDRESS:
5934 case RELOAD_FOR_INPUT_ADDRESS:
5935 case RELOAD_FOR_OPADDR_ADDR:
5936 case RELOAD_FOR_OPERAND_ADDRESS:
5937 case RELOAD_FOR_INPUT:
5940 if (! rld[r].optional)
5941 reload_override_in[r] = equiv;
5949 /* If we found an equivalent reg, say no code need be generated
5950 to load it, and use it as our reload reg. */
5952 && (regno != HARD_FRAME_POINTER_REGNUM
5953 || !frame_pointer_needed))
5955 int nr = hard_regno_nregs[regno][rld[r].mode];
5957 rld[r].reg_rtx = equiv;
5958 reload_inherited[r] = 1;
5960 /* If reg_reloaded_valid is not set for this register,
5961 there might be a stale spill_reg_store lying around.
5962 We must clear it, since otherwise emit_reload_insns
5963 might delete the store. */
5964 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5965 spill_reg_store[regno] = NULL_RTX;
5966 /* If any of the hard registers in EQUIV are spill
5967 registers, mark them as in use for this insn. */
5968 for (k = 0; k < nr; k++)
5970 i = spill_reg_order[regno + k];
5973 mark_reload_reg_in_use (regno, rld[r].opnum,
5976 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5983 /* If we found a register to use already, or if this is an optional
5984 reload, we are done. */
5985 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5989 /* No longer needed for correct operation. Might or might
5990 not give better code on the average. Want to experiment? */
5992 /* See if there is a later reload that has a class different from our
5993 class that intersects our class or that requires less register
5994 than our reload. If so, we must allocate a register to this
5995 reload now, since that reload might inherit a previous reload
5996 and take the only available register in our class. Don't do this
5997 for optional reloads since they will force all previous reloads
5998 to be allocated. Also don't do this for reloads that have been
6001 for (i = j + 1; i < n_reloads; i++)
6003 int s = reload_order[i];
6005 if ((rld[s].in == 0 && rld[s].out == 0
6006 && ! rld[s].secondary_p)
6010 if ((rld[s].class != rld[r].class
6011 && reg_classes_intersect_p (rld[r].class,
6013 || rld[s].nregs < rld[r].nregs)
6020 allocate_reload_reg (chain, r, j == n_reloads - 1);
6024 /* Now allocate reload registers for anything non-optional that
6025 didn't get one yet. */
6026 for (j = 0; j < n_reloads; j++)
6028 int r = reload_order[j];
6030 /* Ignore reloads that got marked inoperative. */
6031 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6034 /* Skip reloads that already have a register allocated or are
6036 if (rld[r].reg_rtx != 0 || rld[r].optional)
6039 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6043 /* If that loop got all the way, we have won. */
6050 /* Loop around and try without any inheritance. */
6055 /* First undo everything done by the failed attempt
6056 to allocate with inheritance. */
6057 choose_reload_regs_init (chain, save_reload_reg_rtx);
6059 /* Some sanity tests to verify that the reloads found in the first
6060 pass are identical to the ones we have now. */
6061 gcc_assert (chain->n_reloads == n_reloads);
6063 for (i = 0; i < n_reloads; i++)
6065 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6067 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6068 for (j = 0; j < n_spills; j++)
6069 if (spill_regs[j] == chain->rld[i].regno)
6070 if (! set_reload_reg (j, i))
6071 failed_reload (chain->insn, i);
6075 /* If we thought we could inherit a reload, because it seemed that
6076 nothing else wanted the same reload register earlier in the insn,
6077 verify that assumption, now that all reloads have been assigned.
6078 Likewise for reloads where reload_override_in has been set. */
6080 /* If doing expensive optimizations, do one preliminary pass that doesn't
6081 cancel any inheritance, but removes reloads that have been needed only
6082 for reloads that we know can be inherited. */
6083 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6085 for (j = 0; j < n_reloads; j++)
6087 int r = reload_order[j];
6089 if (reload_inherited[r] && rld[r].reg_rtx)
6090 check_reg = rld[r].reg_rtx;
6091 else if (reload_override_in[r]
6092 && (REG_P (reload_override_in[r])
6093 || GET_CODE (reload_override_in[r]) == SUBREG))
6094 check_reg = reload_override_in[r];
6097 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6098 rld[r].opnum, rld[r].when_needed, rld[r].in,
6099 (reload_inherited[r]
6100 ? rld[r].out : const0_rtx),
6105 reload_inherited[r] = 0;
6106 reload_override_in[r] = 0;
6108 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6109 reload_override_in, then we do not need its related
6110 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6111 likewise for other reload types.
6112 We handle this by removing a reload when its only replacement
6113 is mentioned in reload_in of the reload we are going to inherit.
6114 A special case are auto_inc expressions; even if the input is
6115 inherited, we still need the address for the output. We can
6116 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6117 If we succeeded removing some reload and we are doing a preliminary
6118 pass just to remove such reloads, make another pass, since the
6119 removal of one reload might allow us to inherit another one. */
6121 && rld[r].out != rld[r].in
6122 && remove_address_replacements (rld[r].in) && pass)
6127 /* Now that reload_override_in is known valid,
6128 actually override reload_in. */
6129 for (j = 0; j < n_reloads; j++)
6130 if (reload_override_in[j])
6131 rld[j].in = reload_override_in[j];
6133 /* If this reload won't be done because it has been canceled or is
6134 optional and not inherited, clear reload_reg_rtx so other
6135 routines (such as subst_reloads) don't get confused. */
6136 for (j = 0; j < n_reloads; j++)
6137 if (rld[j].reg_rtx != 0
6138 && ((rld[j].optional && ! reload_inherited[j])
6139 || (rld[j].in == 0 && rld[j].out == 0
6140 && ! rld[j].secondary_p)))
6142 int regno = true_regnum (rld[j].reg_rtx);
6144 if (spill_reg_order[regno] >= 0)
6145 clear_reload_reg_in_use (regno, rld[j].opnum,
6146 rld[j].when_needed, rld[j].mode);
6148 reload_spill_index[j] = -1;
6151 /* Record which pseudos and which spill regs have output reloads. */
6152 for (j = 0; j < n_reloads; j++)
6154 int r = reload_order[j];
6156 i = reload_spill_index[r];
6158 /* I is nonneg if this reload uses a register.
6159 If rld[r].reg_rtx is 0, this is an optional reload
6160 that we opted to ignore. */
6161 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6162 && rld[r].reg_rtx != 0)
6164 int nregno = REGNO (rld[r].out_reg);
6167 if (nregno < FIRST_PSEUDO_REGISTER)
6168 nr = hard_regno_nregs[nregno][rld[r].mode];
6171 SET_REGNO_REG_SET (®_has_output_reload,
6176 nr = hard_regno_nregs[i][rld[r].mode];
6178 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6181 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6182 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6183 || rld[r].when_needed == RELOAD_FOR_INSN);
6188 /* Deallocate the reload register for reload R. This is called from
6189 remove_address_replacements. */
6192 deallocate_reload_reg (int r)
6196 if (! rld[r].reg_rtx)
6198 regno = true_regnum (rld[r].reg_rtx);
6200 if (spill_reg_order[regno] >= 0)
6201 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6203 reload_spill_index[r] = -1;
6206 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6207 reloads of the same item for fear that we might not have enough reload
6208 registers. However, normally they will get the same reload register
6209 and hence actually need not be loaded twice.
6211 Here we check for the most common case of this phenomenon: when we have
6212 a number of reloads for the same object, each of which were allocated
6213 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6214 reload, and is not modified in the insn itself. If we find such,
6215 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6216 This will not increase the number of spill registers needed and will
6217 prevent redundant code. */
6220 merge_assigned_reloads (rtx insn)
6224 /* Scan all the reloads looking for ones that only load values and
6225 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6226 assigned and not modified by INSN. */
6228 for (i = 0; i < n_reloads; i++)
6230 int conflicting_input = 0;
6231 int max_input_address_opnum = -1;
6232 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6234 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6235 || rld[i].out != 0 || rld[i].reg_rtx == 0
6236 || reg_set_p (rld[i].reg_rtx, insn))
6239 /* Look at all other reloads. Ensure that the only use of this
6240 reload_reg_rtx is in a reload that just loads the same value
6241 as we do. Note that any secondary reloads must be of the identical
6242 class since the values, modes, and result registers are the
6243 same, so we need not do anything with any secondary reloads. */
6245 for (j = 0; j < n_reloads; j++)
6247 if (i == j || rld[j].reg_rtx == 0
6248 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6252 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6253 && rld[j].opnum > max_input_address_opnum)
6254 max_input_address_opnum = rld[j].opnum;
6256 /* If the reload regs aren't exactly the same (e.g, different modes)
6257 or if the values are different, we can't merge this reload.
6258 But if it is an input reload, we might still merge
6259 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6261 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6262 || rld[j].out != 0 || rld[j].in == 0
6263 || ! rtx_equal_p (rld[i].in, rld[j].in))
6265 if (rld[j].when_needed != RELOAD_FOR_INPUT
6266 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6267 || rld[i].opnum > rld[j].opnum)
6268 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6270 conflicting_input = 1;
6271 if (min_conflicting_input_opnum > rld[j].opnum)
6272 min_conflicting_input_opnum = rld[j].opnum;
6276 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6277 we, in fact, found any matching reloads. */
6280 && max_input_address_opnum <= min_conflicting_input_opnum)
6282 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6284 for (j = 0; j < n_reloads; j++)
6285 if (i != j && rld[j].reg_rtx != 0
6286 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6287 && (! conflicting_input
6288 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6289 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6291 rld[i].when_needed = RELOAD_OTHER;
6293 reload_spill_index[j] = -1;
6294 transfer_replacements (i, j);
6297 /* If this is now RELOAD_OTHER, look for any reloads that load
6298 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6299 if they were for inputs, RELOAD_OTHER for outputs. Note that
6300 this test is equivalent to looking for reloads for this operand
6302 /* We must take special care with RELOAD_FOR_OUTPUT_ADDRESS; it may
6303 share registers with a RELOAD_FOR_INPUT, so we can not change it
6304 to RELOAD_FOR_OTHER_ADDRESS. We should never need to, since we
6305 do not modify RELOAD_FOR_OUTPUT. */
6307 if (rld[i].when_needed == RELOAD_OTHER)
6308 for (j = 0; j < n_reloads; j++)
6310 && rld[j].when_needed != RELOAD_OTHER
6311 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6312 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6313 && (! conflicting_input
6314 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6315 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6316 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6322 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6323 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6324 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6326 /* Check to see if we accidentally converted two
6327 reloads that use the same reload register with
6328 different inputs to the same type. If so, the
6329 resulting code won't work. */
6331 for (k = 0; k < j; k++)
6332 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6333 || rld[k].when_needed != rld[j].when_needed
6334 || !rtx_equal_p (rld[k].reg_rtx,
6336 || rtx_equal_p (rld[k].in,
6343 /* These arrays are filled by emit_reload_insns and its subroutines. */
6344 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6345 static rtx other_input_address_reload_insns = 0;
6346 static rtx other_input_reload_insns = 0;
6347 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6348 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6349 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6350 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6351 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6352 static rtx operand_reload_insns = 0;
6353 static rtx other_operand_reload_insns = 0;
6354 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6356 /* Values to be put in spill_reg_store are put here first. */
6357 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6358 static HARD_REG_SET reg_reloaded_died;
6360 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6361 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6362 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6363 adjusted register, and return true. Otherwise, return false. */
6365 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6366 enum reg_class new_class,
6367 enum machine_mode new_mode)
6372 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6374 unsigned regno = REGNO (reg);
6376 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6378 if (GET_MODE (reg) != new_mode)
6380 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6382 if (hard_regno_nregs[regno][new_mode]
6383 > hard_regno_nregs[regno][GET_MODE (reg)])
6385 reg = reload_adjust_reg_for_mode (reg, new_mode);
6393 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6394 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6395 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6396 adjusted register, and return true. Otherwise, return false. */
6398 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6399 enum insn_code icode)
6402 enum reg_class new_class = scratch_reload_class (icode);
6403 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6405 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6406 new_class, new_mode);
6409 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6410 has the number J. OLD contains the value to be used as input. */
6413 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6416 rtx insn = chain->insn;
6417 rtx reloadreg = rl->reg_rtx;
6418 rtx oldequiv_reg = 0;
6421 enum machine_mode mode;
6424 /* Determine the mode to reload in.
6425 This is very tricky because we have three to choose from.
6426 There is the mode the insn operand wants (rl->inmode).
6427 There is the mode of the reload register RELOADREG.
6428 There is the intrinsic mode of the operand, which we could find
6429 by stripping some SUBREGs.
6430 It turns out that RELOADREG's mode is irrelevant:
6431 we can change that arbitrarily.
6433 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6434 then the reload reg may not support QImode moves, so use SImode.
6435 If foo is in memory due to spilling a pseudo reg, this is safe,
6436 because the QImode value is in the least significant part of a
6437 slot big enough for a SImode. If foo is some other sort of
6438 memory reference, then it is impossible to reload this case,
6439 so previous passes had better make sure this never happens.
6441 Then consider a one-word union which has SImode and one of its
6442 members is a float, being fetched as (SUBREG:SF union:SI).
6443 We must fetch that as SFmode because we could be loading into
6444 a float-only register. In this case OLD's mode is correct.
6446 Consider an immediate integer: it has VOIDmode. Here we need
6447 to get a mode from something else.
6449 In some cases, there is a fourth mode, the operand's
6450 containing mode. If the insn specifies a containing mode for
6451 this operand, it overrides all others.
6453 I am not sure whether the algorithm here is always right,
6454 but it does the right things in those cases. */
6456 mode = GET_MODE (old);
6457 if (mode == VOIDmode)
6460 /* delete_output_reload is only invoked properly if old contains
6461 the original pseudo register. Since this is replaced with a
6462 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6463 find the pseudo in RELOAD_IN_REG. */
6464 if (reload_override_in[j]
6465 && REG_P (rl->in_reg))
6472 else if (REG_P (oldequiv))
6473 oldequiv_reg = oldequiv;
6474 else if (GET_CODE (oldequiv) == SUBREG)
6475 oldequiv_reg = SUBREG_REG (oldequiv);
6477 /* If we are reloading from a register that was recently stored in
6478 with an output-reload, see if we can prove there was
6479 actually no need to store the old value in it. */
6481 if (optimize && REG_P (oldequiv)
6482 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6483 && spill_reg_store[REGNO (oldequiv)]
6485 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6486 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6488 delete_output_reload (insn, j, REGNO (oldequiv));
6490 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6491 then load RELOADREG from OLDEQUIV. Note that we cannot use
6492 gen_lowpart_common since it can do the wrong thing when
6493 RELOADREG has a multi-word mode. Note that RELOADREG
6494 must always be a REG here. */
6496 if (GET_MODE (reloadreg) != mode)
6497 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6498 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6499 oldequiv = SUBREG_REG (oldequiv);
6500 if (GET_MODE (oldequiv) != VOIDmode
6501 && mode != GET_MODE (oldequiv))
6502 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6504 /* Switch to the right place to emit the reload insns. */
6505 switch (rl->when_needed)
6508 where = &other_input_reload_insns;
6510 case RELOAD_FOR_INPUT:
6511 where = &input_reload_insns[rl->opnum];
6513 case RELOAD_FOR_INPUT_ADDRESS:
6514 where = &input_address_reload_insns[rl->opnum];
6516 case RELOAD_FOR_INPADDR_ADDRESS:
6517 where = &inpaddr_address_reload_insns[rl->opnum];
6519 case RELOAD_FOR_OUTPUT_ADDRESS:
6520 where = &output_address_reload_insns[rl->opnum];
6522 case RELOAD_FOR_OUTADDR_ADDRESS:
6523 where = &outaddr_address_reload_insns[rl->opnum];
6525 case RELOAD_FOR_OPERAND_ADDRESS:
6526 where = &operand_reload_insns;
6528 case RELOAD_FOR_OPADDR_ADDR:
6529 where = &other_operand_reload_insns;
6531 case RELOAD_FOR_OTHER_ADDRESS:
6532 where = &other_input_address_reload_insns;
6538 push_to_sequence (*where);
6540 /* Auto-increment addresses must be reloaded in a special way. */
6541 if (rl->out && ! rl->out_reg)
6543 /* We are not going to bother supporting the case where a
6544 incremented register can't be copied directly from
6545 OLDEQUIV since this seems highly unlikely. */
6546 gcc_assert (rl->secondary_in_reload < 0);
6548 if (reload_inherited[j])
6549 oldequiv = reloadreg;
6551 old = XEXP (rl->in_reg, 0);
6553 if (optimize && REG_P (oldequiv)
6554 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6555 && spill_reg_store[REGNO (oldequiv)]
6557 && (dead_or_set_p (insn,
6558 spill_reg_stored_to[REGNO (oldequiv)])
6559 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6561 delete_output_reload (insn, j, REGNO (oldequiv));
6563 /* Prevent normal processing of this reload. */
6565 /* Output a special code sequence for this case. */
6566 new_spill_reg_store[REGNO (reloadreg)]
6567 = inc_for_reload (reloadreg, oldequiv, rl->out,
6571 /* If we are reloading a pseudo-register that was set by the previous
6572 insn, see if we can get rid of that pseudo-register entirely
6573 by redirecting the previous insn into our reload register. */
6575 else if (optimize && REG_P (old)
6576 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6577 && dead_or_set_p (insn, old)
6578 /* This is unsafe if some other reload
6579 uses the same reg first. */
6580 && ! conflicts_with_override (reloadreg)
6581 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6582 rl->when_needed, old, rl->out, j, 0))
6584 rtx temp = PREV_INSN (insn);
6585 while (temp && NOTE_P (temp))
6586 temp = PREV_INSN (temp);
6588 && NONJUMP_INSN_P (temp)
6589 && GET_CODE (PATTERN (temp)) == SET
6590 && SET_DEST (PATTERN (temp)) == old
6591 /* Make sure we can access insn_operand_constraint. */
6592 && asm_noperands (PATTERN (temp)) < 0
6593 /* This is unsafe if operand occurs more than once in current
6594 insn. Perhaps some occurrences aren't reloaded. */
6595 && count_occurrences (PATTERN (insn), old, 0) == 1)
6597 rtx old = SET_DEST (PATTERN (temp));
6598 /* Store into the reload register instead of the pseudo. */
6599 SET_DEST (PATTERN (temp)) = reloadreg;
6601 /* Verify that resulting insn is valid. */
6602 extract_insn (temp);
6603 if (constrain_operands (1))
6605 /* If the previous insn is an output reload, the source is
6606 a reload register, and its spill_reg_store entry will
6607 contain the previous destination. This is now
6609 if (REG_P (SET_SRC (PATTERN (temp)))
6610 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6612 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6613 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6616 /* If these are the only uses of the pseudo reg,
6617 pretend for GDB it lives in the reload reg we used. */
6618 if (REG_N_DEATHS (REGNO (old)) == 1
6619 && REG_N_SETS (REGNO (old)) == 1)
6621 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6622 alter_reg (REGNO (old), -1);
6628 SET_DEST (PATTERN (temp)) = old;
6633 /* We can't do that, so output an insn to load RELOADREG. */
6635 /* If we have a secondary reload, pick up the secondary register
6636 and icode, if any. If OLDEQUIV and OLD are different or
6637 if this is an in-out reload, recompute whether or not we
6638 still need a secondary register and what the icode should
6639 be. If we still need a secondary register and the class or
6640 icode is different, go back to reloading from OLD if using
6641 OLDEQUIV means that we got the wrong type of register. We
6642 cannot have different class or icode due to an in-out reload
6643 because we don't make such reloads when both the input and
6644 output need secondary reload registers. */
6646 if (! special && rl->secondary_in_reload >= 0)
6648 rtx second_reload_reg = 0;
6649 rtx third_reload_reg = 0;
6650 int secondary_reload = rl->secondary_in_reload;
6651 rtx real_oldequiv = oldequiv;
6654 enum insn_code icode;
6655 enum insn_code tertiary_icode = CODE_FOR_nothing;
6657 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6658 and similarly for OLD.
6659 See comments in get_secondary_reload in reload.c. */
6660 /* If it is a pseudo that cannot be replaced with its
6661 equivalent MEM, we must fall back to reload_in, which
6662 will have all the necessary substitutions registered.
6663 Likewise for a pseudo that can't be replaced with its
6664 equivalent constant.
6666 Take extra care for subregs of such pseudos. Note that
6667 we cannot use reg_equiv_mem in this case because it is
6668 not in the right mode. */
6671 if (GET_CODE (tmp) == SUBREG)
6672 tmp = SUBREG_REG (tmp);
6674 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6675 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6676 || reg_equiv_constant[REGNO (tmp)] != 0))
6678 if (! reg_equiv_mem[REGNO (tmp)]
6679 || num_not_at_initial_offset
6680 || GET_CODE (oldequiv) == SUBREG)
6681 real_oldequiv = rl->in;
6683 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6687 if (GET_CODE (tmp) == SUBREG)
6688 tmp = SUBREG_REG (tmp);
6690 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6691 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6692 || reg_equiv_constant[REGNO (tmp)] != 0))
6694 if (! reg_equiv_mem[REGNO (tmp)]
6695 || num_not_at_initial_offset
6696 || GET_CODE (old) == SUBREG)
6699 real_old = reg_equiv_mem[REGNO (tmp)];
6702 second_reload_reg = rld[secondary_reload].reg_rtx;
6703 if (rld[secondary_reload].secondary_in_reload >= 0)
6705 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
6707 third_reload_reg = rld[tertiary_reload].reg_rtx;
6708 tertiary_icode = rld[secondary_reload].secondary_in_icode;
6709 /* We'd have to add more code for quartary reloads. */
6710 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
6712 icode = rl->secondary_in_icode;
6714 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6715 || (rl->in != 0 && rl->out != 0))
6717 secondary_reload_info sri, sri2;
6718 enum reg_class new_class, new_t_class;
6720 sri.icode = CODE_FOR_nothing;
6721 sri.prev_sri = NULL;
6722 new_class = targetm.secondary_reload (1, real_oldequiv, rl->class,
6725 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
6726 second_reload_reg = 0;
6727 else if (new_class == NO_REGS)
6729 if (reload_adjust_reg_for_icode (&second_reload_reg,
6730 third_reload_reg, sri.icode))
6731 icode = sri.icode, third_reload_reg = 0;
6733 oldequiv = old, real_oldequiv = real_old;
6735 else if (sri.icode != CODE_FOR_nothing)
6736 /* We currently lack a way to express this in reloads. */
6740 sri2.icode = CODE_FOR_nothing;
6741 sri2.prev_sri = &sri;
6742 new_t_class = targetm.secondary_reload (1, real_oldequiv,
6743 new_class, mode, &sri);
6744 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
6746 if (reload_adjust_reg_for_temp (&second_reload_reg,
6749 third_reload_reg = 0, tertiary_icode = sri2.icode;
6751 oldequiv = old, real_oldequiv = real_old;
6753 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
6755 rtx intermediate = second_reload_reg;
6757 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6759 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
6762 second_reload_reg = intermediate;
6763 tertiary_icode = sri2.icode;
6766 oldequiv = old, real_oldequiv = real_old;
6768 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
6770 rtx intermediate = second_reload_reg;
6772 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6774 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
6777 second_reload_reg = intermediate;
6778 tertiary_icode = sri2.icode;
6781 oldequiv = old, real_oldequiv = real_old;
6784 /* This could be handled more intelligently too. */
6785 oldequiv = old, real_oldequiv = real_old;
6789 /* If we still need a secondary reload register, check
6790 to see if it is being used as a scratch or intermediate
6791 register and generate code appropriately. If we need
6792 a scratch register, use REAL_OLDEQUIV since the form of
6793 the insn may depend on the actual address if it is
6796 if (second_reload_reg)
6798 if (icode != CODE_FOR_nothing)
6800 /* We'd have to add extra code to handle this case. */
6801 gcc_assert (!third_reload_reg);
6803 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6804 second_reload_reg));
6809 /* See if we need a scratch register to load the
6810 intermediate register (a tertiary reload). */
6811 if (tertiary_icode != CODE_FOR_nothing)
6813 emit_insn ((GEN_FCN (tertiary_icode)
6814 (second_reload_reg, real_oldequiv,
6815 third_reload_reg)));
6817 else if (third_reload_reg)
6819 gen_reload (third_reload_reg, real_oldequiv,
6822 gen_reload (second_reload_reg, third_reload_reg,
6827 gen_reload (second_reload_reg, real_oldequiv,
6831 oldequiv = second_reload_reg;
6836 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6838 rtx real_oldequiv = oldequiv;
6840 if ((REG_P (oldequiv)
6841 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6842 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6843 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6844 || (GET_CODE (oldequiv) == SUBREG
6845 && REG_P (SUBREG_REG (oldequiv))
6846 && (REGNO (SUBREG_REG (oldequiv))
6847 >= FIRST_PSEUDO_REGISTER)
6848 && ((reg_equiv_memory_loc
6849 [REGNO (SUBREG_REG (oldequiv))] != 0)
6850 || (reg_equiv_constant
6851 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6852 || (CONSTANT_P (oldequiv)
6853 && (PREFERRED_RELOAD_CLASS (oldequiv,
6854 REGNO_REG_CLASS (REGNO (reloadreg)))
6856 real_oldequiv = rl->in;
6857 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6861 if (flag_non_call_exceptions)
6862 copy_eh_notes (insn, get_insns ());
6864 /* End this sequence. */
6865 *where = get_insns ();
6868 /* Update reload_override_in so that delete_address_reloads_1
6869 can see the actual register usage. */
6871 reload_override_in[j] = oldequiv;
6874 /* Generate insns to for the output reload RL, which is for the insn described
6875 by CHAIN and has the number J. */
6877 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6880 rtx reloadreg = rl->reg_rtx;
6881 rtx insn = chain->insn;
6884 enum machine_mode mode = GET_MODE (old);
6887 if (rl->when_needed == RELOAD_OTHER)
6890 push_to_sequence (output_reload_insns[rl->opnum]);
6892 /* Determine the mode to reload in.
6893 See comments above (for input reloading). */
6895 if (mode == VOIDmode)
6897 /* VOIDmode should never happen for an output. */
6898 if (asm_noperands (PATTERN (insn)) < 0)
6899 /* It's the compiler's fault. */
6900 fatal_insn ("VOIDmode on an output", insn);
6901 error_for_asm (insn, "output operand is constant in %<asm%>");
6902 /* Prevent crash--use something we know is valid. */
6904 old = gen_rtx_REG (mode, REGNO (reloadreg));
6907 if (GET_MODE (reloadreg) != mode)
6908 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6910 /* If we need two reload regs, set RELOADREG to the intermediate
6911 one, since it will be stored into OLD. We might need a secondary
6912 register only for an input reload, so check again here. */
6914 if (rl->secondary_out_reload >= 0)
6917 int secondary_reload = rl->secondary_out_reload;
6918 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
6920 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
6921 && reg_equiv_mem[REGNO (old)] != 0)
6922 real_old = reg_equiv_mem[REGNO (old)];
6924 if (secondary_reload_class (0, rl->class, mode, real_old) != NO_REGS)
6926 rtx second_reloadreg = reloadreg;
6927 reloadreg = rld[secondary_reload].reg_rtx;
6929 /* See if RELOADREG is to be used as a scratch register
6930 or as an intermediate register. */
6931 if (rl->secondary_out_icode != CODE_FOR_nothing)
6933 /* We'd have to add extra code to handle this case. */
6934 gcc_assert (tertiary_reload < 0);
6936 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6937 (real_old, second_reloadreg, reloadreg)));
6942 /* See if we need both a scratch and intermediate reload
6945 enum insn_code tertiary_icode
6946 = rld[secondary_reload].secondary_out_icode;
6948 /* We'd have to add more code for quartary reloads. */
6949 gcc_assert (tertiary_reload < 0
6950 || rld[tertiary_reload].secondary_out_reload < 0);
6952 if (GET_MODE (reloadreg) != mode)
6953 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6955 if (tertiary_icode != CODE_FOR_nothing)
6957 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
6960 /* Copy primary reload reg to secondary reload reg.
6961 (Note that these have been swapped above, then
6962 secondary reload reg to OLD using our insn.) */
6964 /* If REAL_OLD is a paradoxical SUBREG, remove it
6965 and try to put the opposite SUBREG on
6967 if (GET_CODE (real_old) == SUBREG
6968 && (GET_MODE_SIZE (GET_MODE (real_old))
6969 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6970 && 0 != (tem = gen_lowpart_common
6971 (GET_MODE (SUBREG_REG (real_old)),
6973 real_old = SUBREG_REG (real_old), reloadreg = tem;
6975 gen_reload (reloadreg, second_reloadreg,
6976 rl->opnum, rl->when_needed);
6977 emit_insn ((GEN_FCN (tertiary_icode)
6978 (real_old, reloadreg, third_reloadreg)));
6984 /* Copy between the reload regs here and then to
6987 gen_reload (reloadreg, second_reloadreg,
6988 rl->opnum, rl->when_needed);
6989 if (tertiary_reload >= 0)
6991 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
6993 gen_reload (third_reloadreg, reloadreg,
6994 rl->opnum, rl->when_needed);
6995 reloadreg = third_reloadreg;
7002 /* Output the last reload insn. */
7007 /* Don't output the last reload if OLD is not the dest of
7008 INSN and is in the src and is clobbered by INSN. */
7009 if (! flag_expensive_optimizations
7011 || !(set = single_set (insn))
7012 || rtx_equal_p (old, SET_DEST (set))
7013 || !reg_mentioned_p (old, SET_SRC (set))
7014 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7015 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7016 gen_reload (old, reloadreg, rl->opnum,
7020 /* Look at all insns we emitted, just to be safe. */
7021 for (p = get_insns (); p; p = NEXT_INSN (p))
7024 rtx pat = PATTERN (p);
7026 /* If this output reload doesn't come from a spill reg,
7027 clear any memory of reloaded copies of the pseudo reg.
7028 If this output reload comes from a spill reg,
7029 reg_has_output_reload will make this do nothing. */
7030 note_stores (pat, forget_old_reloads_1, NULL);
7032 if (reg_mentioned_p (rl->reg_rtx, pat))
7034 rtx set = single_set (insn);
7035 if (reload_spill_index[j] < 0
7037 && SET_SRC (set) == rl->reg_rtx)
7039 int src = REGNO (SET_SRC (set));
7041 reload_spill_index[j] = src;
7042 SET_HARD_REG_BIT (reg_is_output_reload, src);
7043 if (find_regno_note (insn, REG_DEAD, src))
7044 SET_HARD_REG_BIT (reg_reloaded_died, src);
7046 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
7048 int s = rl->secondary_out_reload;
7049 set = single_set (p);
7050 /* If this reload copies only to the secondary reload
7051 register, the secondary reload does the actual
7053 if (s >= 0 && set == NULL_RTX)
7054 /* We can't tell what function the secondary reload
7055 has and where the actual store to the pseudo is
7056 made; leave new_spill_reg_store alone. */
7059 && SET_SRC (set) == rl->reg_rtx
7060 && SET_DEST (set) == rld[s].reg_rtx)
7062 /* Usually the next instruction will be the
7063 secondary reload insn; if we can confirm
7064 that it is, setting new_spill_reg_store to
7065 that insn will allow an extra optimization. */
7066 rtx s_reg = rld[s].reg_rtx;
7067 rtx next = NEXT_INSN (p);
7068 rld[s].out = rl->out;
7069 rld[s].out_reg = rl->out_reg;
7070 set = single_set (next);
7071 if (set && SET_SRC (set) == s_reg
7072 && ! new_spill_reg_store[REGNO (s_reg)])
7074 SET_HARD_REG_BIT (reg_is_output_reload,
7076 new_spill_reg_store[REGNO (s_reg)] = next;
7080 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
7085 if (rl->when_needed == RELOAD_OTHER)
7087 emit_insn (other_output_reload_insns[rl->opnum]);
7088 other_output_reload_insns[rl->opnum] = get_insns ();
7091 output_reload_insns[rl->opnum] = get_insns ();
7093 if (flag_non_call_exceptions)
7094 copy_eh_notes (insn, get_insns ());
7099 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7100 and has the number J. */
7102 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7104 rtx insn = chain->insn;
7105 rtx old = (rl->in && MEM_P (rl->in)
7106 ? rl->in_reg : rl->in);
7109 /* AUTO_INC reloads need to be handled even if inherited. We got an
7110 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7111 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7112 && ! rtx_equal_p (rl->reg_rtx, old)
7113 && rl->reg_rtx != 0)
7114 emit_input_reload_insns (chain, rld + j, old, j);
7116 /* When inheriting a wider reload, we have a MEM in rl->in,
7117 e.g. inheriting a SImode output reload for
7118 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7119 if (optimize && reload_inherited[j] && rl->in
7121 && MEM_P (rl->in_reg)
7122 && reload_spill_index[j] >= 0
7123 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7124 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7126 /* If we are reloading a register that was recently stored in with an
7127 output-reload, see if we can prove there was
7128 actually no need to store the old value in it. */
7131 /* Only attempt this for input reloads; for RELOAD_OTHER we miss
7132 that there may be multiple uses of the previous output reload.
7133 Restricting to RELOAD_FOR_INPUT is mostly paranoia. */
7134 && rl->when_needed == RELOAD_FOR_INPUT
7135 && (reload_inherited[j] || reload_override_in[j])
7137 && REG_P (rl->reg_rtx)
7138 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
7140 /* There doesn't seem to be any reason to restrict this to pseudos
7141 and doing so loses in the case where we are copying from a
7142 register of the wrong class. */
7143 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
7144 >= FIRST_PSEUDO_REGISTER)
7146 /* The insn might have already some references to stackslots
7147 replaced by MEMs, while reload_out_reg still names the
7149 && (dead_or_set_p (insn,
7150 spill_reg_stored_to[REGNO (rl->reg_rtx)])
7151 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
7153 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
7156 /* Do output reloading for reload RL, which is for the insn described by
7157 CHAIN and has the number J.
7158 ??? At some point we need to support handling output reloads of
7159 JUMP_INSNs or insns that set cc0. */
7161 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7164 rtx insn = chain->insn;
7165 /* If this is an output reload that stores something that is
7166 not loaded in this same reload, see if we can eliminate a previous
7168 rtx pseudo = rl->out_reg;
7173 && ! rtx_equal_p (rl->in_reg, pseudo)
7174 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7175 && reg_last_reload_reg[REGNO (pseudo)])
7177 int pseudo_no = REGNO (pseudo);
7178 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7180 /* We don't need to test full validity of last_regno for
7181 inherit here; we only want to know if the store actually
7182 matches the pseudo. */
7183 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7184 && reg_reloaded_contents[last_regno] == pseudo_no
7185 && spill_reg_store[last_regno]
7186 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7187 delete_output_reload (insn, j, last_regno);
7192 || rl->reg_rtx == old
7193 || rl->reg_rtx == 0)
7196 /* An output operand that dies right away does need a reload,
7197 but need not be copied from it. Show the new location in the
7199 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7200 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7202 XEXP (note, 0) = rl->reg_rtx;
7205 /* Likewise for a SUBREG of an operand that dies. */
7206 else if (GET_CODE (old) == SUBREG
7207 && REG_P (SUBREG_REG (old))
7208 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7211 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
7215 else if (GET_CODE (old) == SCRATCH)
7216 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7217 but we don't want to make an output reload. */
7220 /* If is a JUMP_INSN, we can't support output reloads yet. */
7221 gcc_assert (NONJUMP_INSN_P (insn));
7223 emit_output_reload_insns (chain, rld + j, j);
7226 /* Reload number R reloads from or to a group of hard registers starting at
7227 register REGNO. Return true if it can be treated for inheritance purposes
7228 like a group of reloads, each one reloading a single hard register.
7229 The caller has already checked that the spill register and REGNO use
7230 the same number of registers to store the reload value. */
7233 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
7235 #ifdef CANNOT_CHANGE_MODE_CLASS
7236 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
7237 GET_MODE (rld[r].reg_rtx),
7238 reg_raw_mode[reload_spill_index[r]])
7239 && !REG_CANNOT_CHANGE_MODE_P (regno,
7240 GET_MODE (rld[r].reg_rtx),
7241 reg_raw_mode[regno]));
7247 /* Output insns to reload values in and out of the chosen reload regs. */
7250 emit_reload_insns (struct insn_chain *chain)
7252 rtx insn = chain->insn;
7256 CLEAR_HARD_REG_SET (reg_reloaded_died);
7258 for (j = 0; j < reload_n_operands; j++)
7259 input_reload_insns[j] = input_address_reload_insns[j]
7260 = inpaddr_address_reload_insns[j]
7261 = output_reload_insns[j] = output_address_reload_insns[j]
7262 = outaddr_address_reload_insns[j]
7263 = other_output_reload_insns[j] = 0;
7264 other_input_address_reload_insns = 0;
7265 other_input_reload_insns = 0;
7266 operand_reload_insns = 0;
7267 other_operand_reload_insns = 0;
7269 /* Dump reloads into the dump file. */
7272 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7273 debug_reload_to_stream (dump_file);
7276 /* Now output the instructions to copy the data into and out of the
7277 reload registers. Do these in the order that the reloads were reported,
7278 since reloads of base and index registers precede reloads of operands
7279 and the operands may need the base and index registers reloaded. */
7281 for (j = 0; j < n_reloads; j++)
7284 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7285 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7287 do_input_reload (chain, rld + j, j);
7288 do_output_reload (chain, rld + j, j);
7291 /* Now write all the insns we made for reloads in the order expected by
7292 the allocation functions. Prior to the insn being reloaded, we write
7293 the following reloads:
7295 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7297 RELOAD_OTHER reloads.
7299 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7300 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7301 RELOAD_FOR_INPUT reload for the operand.
7303 RELOAD_FOR_OPADDR_ADDRS reloads.
7305 RELOAD_FOR_OPERAND_ADDRESS reloads.
7307 After the insn being reloaded, we write the following:
7309 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7310 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7311 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7312 reloads for the operand. The RELOAD_OTHER output reloads are
7313 output in descending order by reload number. */
7315 emit_insn_before (other_input_address_reload_insns, insn);
7316 emit_insn_before (other_input_reload_insns, insn);
7318 for (j = 0; j < reload_n_operands; j++)
7320 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7321 emit_insn_before (input_address_reload_insns[j], insn);
7322 emit_insn_before (input_reload_insns[j], insn);
7325 emit_insn_before (other_operand_reload_insns, insn);
7326 emit_insn_before (operand_reload_insns, insn);
7328 for (j = 0; j < reload_n_operands; j++)
7330 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7331 x = emit_insn_after (output_address_reload_insns[j], x);
7332 x = emit_insn_after (output_reload_insns[j], x);
7333 emit_insn_after (other_output_reload_insns[j], x);
7336 /* For all the spill regs newly reloaded in this instruction,
7337 record what they were reloaded from, so subsequent instructions
7338 can inherit the reloads.
7340 Update spill_reg_store for the reloads of this insn.
7341 Copy the elements that were updated in the loop above. */
7343 for (j = 0; j < n_reloads; j++)
7345 int r = reload_order[j];
7346 int i = reload_spill_index[r];
7348 /* If this is a non-inherited input reload from a pseudo, we must
7349 clear any memory of a previous store to the same pseudo. Only do
7350 something if there will not be an output reload for the pseudo
7352 if (rld[r].in_reg != 0
7353 && ! (reload_inherited[r] || reload_override_in[r]))
7355 rtx reg = rld[r].in_reg;
7357 if (GET_CODE (reg) == SUBREG)
7358 reg = SUBREG_REG (reg);
7361 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7362 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
7364 int nregno = REGNO (reg);
7366 if (reg_last_reload_reg[nregno])
7368 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7370 if (reg_reloaded_contents[last_regno] == nregno)
7371 spill_reg_store[last_regno] = 0;
7376 /* I is nonneg if this reload used a register.
7377 If rld[r].reg_rtx is 0, this is an optional reload
7378 that we opted to ignore. */
7380 if (i >= 0 && rld[r].reg_rtx != 0)
7382 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7384 int part_reaches_end = 0;
7385 int all_reaches_end = 1;
7387 /* For a multi register reload, we need to check if all or part
7388 of the value lives to the end. */
7389 for (k = 0; k < nr; k++)
7391 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7392 rld[r].when_needed))
7393 part_reaches_end = 1;
7395 all_reaches_end = 0;
7398 /* Ignore reloads that don't reach the end of the insn in
7400 if (all_reaches_end)
7402 /* First, clear out memory of what used to be in this spill reg.
7403 If consecutive registers are used, clear them all. */
7405 for (k = 0; k < nr; k++)
7407 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7408 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7411 /* Maybe the spill reg contains a copy of reload_out. */
7413 && (REG_P (rld[r].out)
7417 || REG_P (rld[r].out_reg)))
7419 rtx out = (REG_P (rld[r].out)
7423 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7424 int nregno = REGNO (out);
7425 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7426 : hard_regno_nregs[nregno]
7427 [GET_MODE (rld[r].reg_rtx)]);
7430 spill_reg_store[i] = new_spill_reg_store[i];
7431 spill_reg_stored_to[i] = out;
7432 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7434 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7436 && inherit_piecemeal_p (r, nregno));
7438 /* If NREGNO is a hard register, it may occupy more than
7439 one register. If it does, say what is in the
7440 rest of the registers assuming that both registers
7441 agree on how many words the object takes. If not,
7442 invalidate the subsequent registers. */
7444 if (nregno < FIRST_PSEUDO_REGISTER)
7445 for (k = 1; k < nnr; k++)
7446 reg_last_reload_reg[nregno + k]
7448 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7451 /* Now do the inverse operation. */
7452 for (k = 0; k < nr; k++)
7454 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7455 reg_reloaded_contents[i + k]
7456 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7459 reg_reloaded_insn[i + k] = insn;
7460 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7461 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7462 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7466 /* Maybe the spill reg contains a copy of reload_in. Only do
7467 something if there will not be an output reload for
7468 the register being reloaded. */
7469 else if (rld[r].out_reg == 0
7471 && ((REG_P (rld[r].in)
7472 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7473 && !REGNO_REG_SET_P (®_has_output_reload,
7475 || (REG_P (rld[r].in_reg)
7476 && !REGNO_REG_SET_P (®_has_output_reload,
7477 REGNO (rld[r].in_reg))))
7478 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7485 if (REG_P (rld[r].in)
7486 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7488 else if (REG_P (rld[r].in_reg))
7491 in = XEXP (rld[r].in_reg, 0);
7492 nregno = REGNO (in);
7494 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7495 : hard_regno_nregs[nregno]
7496 [GET_MODE (rld[r].reg_rtx)]);
7498 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7500 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7502 && inherit_piecemeal_p (r, nregno));
7504 if (nregno < FIRST_PSEUDO_REGISTER)
7505 for (k = 1; k < nnr; k++)
7506 reg_last_reload_reg[nregno + k]
7508 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7511 /* Unless we inherited this reload, show we haven't
7512 recently done a store.
7513 Previous stores of inherited auto_inc expressions
7514 also have to be discarded. */
7515 if (! reload_inherited[r]
7516 || (rld[r].out && ! rld[r].out_reg))
7517 spill_reg_store[i] = 0;
7519 for (k = 0; k < nr; k++)
7521 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7522 reg_reloaded_contents[i + k]
7523 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7526 reg_reloaded_insn[i + k] = insn;
7527 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7528 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7529 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7534 /* However, if part of the reload reaches the end, then we must
7535 invalidate the old info for the part that survives to the end. */
7536 else if (part_reaches_end)
7538 for (k = 0; k < nr; k++)
7539 if (reload_reg_reaches_end_p (i + k,
7541 rld[r].when_needed))
7542 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7546 /* The following if-statement was #if 0'd in 1.34 (or before...).
7547 It's reenabled in 1.35 because supposedly nothing else
7548 deals with this problem. */
7550 /* If a register gets output-reloaded from a non-spill register,
7551 that invalidates any previous reloaded copy of it.
7552 But forget_old_reloads_1 won't get to see it, because
7553 it thinks only about the original insn. So invalidate it here.
7554 Also do the same thing for RELOAD_OTHER constraints where the
7555 output is discarded. */
7557 && ((rld[r].out != 0
7558 && (REG_P (rld[r].out)
7559 || (MEM_P (rld[r].out)
7560 && REG_P (rld[r].out_reg))))
7561 || (rld[r].out == 0 && rld[r].out_reg
7562 && REG_P (rld[r].out_reg))))
7564 rtx out = ((rld[r].out && REG_P (rld[r].out))
7565 ? rld[r].out : rld[r].out_reg);
7566 int nregno = REGNO (out);
7568 /* REG_RTX is now set or clobbered by the main instruction.
7569 As the comment above explains, forget_old_reloads_1 only
7570 sees the original instruction, and there is no guarantee
7571 that the original instruction also clobbered REG_RTX.
7572 For example, if find_reloads sees that the input side of
7573 a matched operand pair dies in this instruction, it may
7574 use the input register as the reload register.
7576 Calling forget_old_reloads_1 is a waste of effort if
7577 REG_RTX is also the output register.
7579 If we know that REG_RTX holds the value of a pseudo
7580 register, the code after the call will record that fact. */
7581 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
7582 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
7584 if (nregno >= FIRST_PSEUDO_REGISTER)
7586 rtx src_reg, store_insn = NULL_RTX;
7588 reg_last_reload_reg[nregno] = 0;
7590 /* If we can find a hard register that is stored, record
7591 the storing insn so that we may delete this insn with
7592 delete_output_reload. */
7593 src_reg = rld[r].reg_rtx;
7595 /* If this is an optional reload, try to find the source reg
7596 from an input reload. */
7599 rtx set = single_set (insn);
7600 if (set && SET_DEST (set) == rld[r].out)
7604 src_reg = SET_SRC (set);
7606 for (k = 0; k < n_reloads; k++)
7608 if (rld[k].in == src_reg)
7610 src_reg = rld[k].reg_rtx;
7617 store_insn = new_spill_reg_store[REGNO (src_reg)];
7618 if (src_reg && REG_P (src_reg)
7619 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7621 int src_regno = REGNO (src_reg);
7622 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7623 /* The place where to find a death note varies with
7624 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7625 necessarily checked exactly in the code that moves
7626 notes, so just check both locations. */
7627 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7628 if (! note && store_insn)
7629 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7632 spill_reg_store[src_regno + nr] = store_insn;
7633 spill_reg_stored_to[src_regno + nr] = out;
7634 reg_reloaded_contents[src_regno + nr] = nregno;
7635 reg_reloaded_insn[src_regno + nr] = store_insn;
7636 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7637 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7638 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7639 GET_MODE (src_reg)))
7640 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7642 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7644 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7646 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7648 reg_last_reload_reg[nregno] = src_reg;
7649 /* We have to set reg_has_output_reload here, or else
7650 forget_old_reloads_1 will clear reg_last_reload_reg
7652 SET_REGNO_REG_SET (®_has_output_reload,
7658 int num_regs = hard_regno_nregs[nregno][GET_MODE (out)];
7660 while (num_regs-- > 0)
7661 reg_last_reload_reg[nregno + num_regs] = 0;
7665 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7668 /* Go through the motions to emit INSN and test if it is strictly valid.
7669 Return the emitted insn if valid, else return NULL. */
7672 emit_insn_if_valid_for_reload (rtx insn)
7674 rtx last = get_last_insn ();
7677 insn = emit_insn (insn);
7678 code = recog_memoized (insn);
7682 extract_insn (insn);
7683 /* We want constrain operands to treat this insn strictly in its
7684 validity determination, i.e., the way it would after reload has
7686 if (constrain_operands (1))
7690 delete_insns_since (last);
7694 /* Emit code to perform a reload from IN (which may be a reload register) to
7695 OUT (which may also be a reload register). IN or OUT is from operand
7696 OPNUM with reload type TYPE.
7698 Returns first insn emitted. */
7701 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7703 rtx last = get_last_insn ();
7706 /* If IN is a paradoxical SUBREG, remove it and try to put the
7707 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7708 if (GET_CODE (in) == SUBREG
7709 && (GET_MODE_SIZE (GET_MODE (in))
7710 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7711 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7712 in = SUBREG_REG (in), out = tem;
7713 else if (GET_CODE (out) == SUBREG
7714 && (GET_MODE_SIZE (GET_MODE (out))
7715 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7716 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7717 out = SUBREG_REG (out), in = tem;
7719 /* How to do this reload can get quite tricky. Normally, we are being
7720 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7721 register that didn't get a hard register. In that case we can just
7722 call emit_move_insn.
7724 We can also be asked to reload a PLUS that adds a register or a MEM to
7725 another register, constant or MEM. This can occur during frame pointer
7726 elimination and while reloading addresses. This case is handled by
7727 trying to emit a single insn to perform the add. If it is not valid,
7728 we use a two insn sequence.
7730 Or we can be asked to reload an unary operand that was a fragment of
7731 an addressing mode, into a register. If it isn't recognized as-is,
7732 we try making the unop operand and the reload-register the same:
7733 (set reg:X (unop:X expr:Y))
7734 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
7736 Finally, we could be called to handle an 'o' constraint by putting
7737 an address into a register. In that case, we first try to do this
7738 with a named pattern of "reload_load_address". If no such pattern
7739 exists, we just emit a SET insn and hope for the best (it will normally
7740 be valid on machines that use 'o').
7742 This entire process is made complex because reload will never
7743 process the insns we generate here and so we must ensure that
7744 they will fit their constraints and also by the fact that parts of
7745 IN might be being reloaded separately and replaced with spill registers.
7746 Because of this, we are, in some sense, just guessing the right approach
7747 here. The one listed above seems to work.
7749 ??? At some point, this whole thing needs to be rethought. */
7751 if (GET_CODE (in) == PLUS
7752 && (REG_P (XEXP (in, 0))
7753 || GET_CODE (XEXP (in, 0)) == SUBREG
7754 || MEM_P (XEXP (in, 0)))
7755 && (REG_P (XEXP (in, 1))
7756 || GET_CODE (XEXP (in, 1)) == SUBREG
7757 || CONSTANT_P (XEXP (in, 1))
7758 || MEM_P (XEXP (in, 1))))
7760 /* We need to compute the sum of a register or a MEM and another
7761 register, constant, or MEM, and put it into the reload
7762 register. The best possible way of doing this is if the machine
7763 has a three-operand ADD insn that accepts the required operands.
7765 The simplest approach is to try to generate such an insn and see if it
7766 is recognized and matches its constraints. If so, it can be used.
7768 It might be better not to actually emit the insn unless it is valid,
7769 but we need to pass the insn as an operand to `recog' and
7770 `extract_insn' and it is simpler to emit and then delete the insn if
7771 not valid than to dummy things up. */
7773 rtx op0, op1, tem, insn;
7776 op0 = find_replacement (&XEXP (in, 0));
7777 op1 = find_replacement (&XEXP (in, 1));
7779 /* Since constraint checking is strict, commutativity won't be
7780 checked, so we need to do that here to avoid spurious failure
7781 if the add instruction is two-address and the second operand
7782 of the add is the same as the reload reg, which is frequently
7783 the case. If the insn would be A = B + A, rearrange it so
7784 it will be A = A + B as constrain_operands expects. */
7786 if (REG_P (XEXP (in, 1))
7787 && REGNO (out) == REGNO (XEXP (in, 1)))
7788 tem = op0, op0 = op1, op1 = tem;
7790 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7791 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7793 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7797 /* If that failed, we must use a conservative two-insn sequence.
7799 Use a move to copy one operand into the reload register. Prefer
7800 to reload a constant, MEM or pseudo since the move patterns can
7801 handle an arbitrary operand. If OP1 is not a constant, MEM or
7802 pseudo and OP1 is not a valid operand for an add instruction, then
7805 After reloading one of the operands into the reload register, add
7806 the reload register to the output register.
7808 If there is another way to do this for a specific machine, a
7809 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7812 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7814 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7816 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7817 || (code != CODE_FOR_nothing
7818 && ! ((*insn_data[code].operand[2].predicate)
7819 (op1, insn_data[code].operand[2].mode))))
7820 tem = op0, op0 = op1, op1 = tem;
7822 gen_reload (out, op0, opnum, type);
7824 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7825 This fixes a problem on the 32K where the stack pointer cannot
7826 be used as an operand of an add insn. */
7828 if (rtx_equal_p (op0, op1))
7831 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
7834 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7835 set_unique_reg_note (insn, REG_EQUIV, in);
7839 /* If that failed, copy the address register to the reload register.
7840 Then add the constant to the reload register. */
7842 gen_reload (out, op1, opnum, type);
7843 insn = emit_insn (gen_add2_insn (out, op0));
7844 set_unique_reg_note (insn, REG_EQUIV, in);
7847 #ifdef SECONDARY_MEMORY_NEEDED
7848 /* If we need a memory location to do the move, do it that way. */
7849 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7850 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7851 && (REG_P (out) || GET_CODE (out) == SUBREG)
7852 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7853 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7854 REGNO_REG_CLASS (reg_or_subregno (out)),
7857 /* Get the memory to use and rewrite both registers to its mode. */
7858 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7860 if (GET_MODE (loc) != GET_MODE (out))
7861 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7863 if (GET_MODE (loc) != GET_MODE (in))
7864 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7866 gen_reload (loc, in, opnum, type);
7867 gen_reload (out, loc, opnum, type);
7870 else if (REG_P (out) && UNARY_P (in))
7877 op1 = find_replacement (&XEXP (in, 0));
7878 if (op1 != XEXP (in, 0))
7879 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
7881 /* First, try a plain SET. */
7882 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7886 /* If that failed, move the inner operand to the reload
7887 register, and try the same unop with the inner expression
7888 replaced with the reload register. */
7890 if (GET_MODE (op1) != GET_MODE (out))
7891 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
7895 gen_reload (out_moded, op1, opnum, type);
7898 = gen_rtx_SET (VOIDmode, out,
7899 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
7901 insn = emit_insn_if_valid_for_reload (insn);
7904 set_unique_reg_note (insn, REG_EQUIV, in);
7908 fatal_insn ("Failure trying to reload:", set);
7910 /* If IN is a simple operand, use gen_move_insn. */
7911 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
7913 tem = emit_insn (gen_move_insn (out, in));
7914 /* IN may contain a LABEL_REF, if so add a REG_LABEL note. */
7915 mark_jump_label (in, tem, 0);
7918 #ifdef HAVE_reload_load_address
7919 else if (HAVE_reload_load_address)
7920 emit_insn (gen_reload_load_address (out, in));
7923 /* Otherwise, just write (set OUT IN) and hope for the best. */
7925 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7927 /* Return the first insn emitted.
7928 We can not just return get_last_insn, because there may have
7929 been multiple instructions emitted. Also note that gen_move_insn may
7930 emit more than one insn itself, so we can not assume that there is one
7931 insn emitted per emit_insn_before call. */
7933 return last ? NEXT_INSN (last) : get_insns ();
7936 /* Delete a previously made output-reload whose result we now believe
7937 is not needed. First we double-check.
7939 INSN is the insn now being processed.
7940 LAST_RELOAD_REG is the hard register number for which we want to delete
7941 the last output reload.
7942 J is the reload-number that originally used REG. The caller has made
7943 certain that reload J doesn't use REG any longer for input. */
7946 delete_output_reload (rtx insn, int j, int last_reload_reg)
7948 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7949 rtx reg = spill_reg_stored_to[last_reload_reg];
7952 int n_inherited = 0;
7956 /* It is possible that this reload has been only used to set another reload
7957 we eliminated earlier and thus deleted this instruction too. */
7958 if (INSN_DELETED_P (output_reload_insn))
7961 /* Get the raw pseudo-register referred to. */
7963 while (GET_CODE (reg) == SUBREG)
7964 reg = SUBREG_REG (reg);
7965 substed = reg_equiv_memory_loc[REGNO (reg)];
7967 /* This is unsafe if the operand occurs more often in the current
7968 insn than it is inherited. */
7969 for (k = n_reloads - 1; k >= 0; k--)
7971 rtx reg2 = rld[k].in;
7974 if (MEM_P (reg2) || reload_override_in[k])
7975 reg2 = rld[k].in_reg;
7977 if (rld[k].out && ! rld[k].out_reg)
7978 reg2 = XEXP (rld[k].in_reg, 0);
7980 while (GET_CODE (reg2) == SUBREG)
7981 reg2 = SUBREG_REG (reg2);
7982 if (rtx_equal_p (reg2, reg))
7984 if (reload_inherited[k] || reload_override_in[k] || k == j)
7987 reg2 = rld[k].out_reg;
7990 while (GET_CODE (reg2) == SUBREG)
7991 reg2 = XEXP (reg2, 0);
7992 if (rtx_equal_p (reg2, reg))
7999 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8000 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8001 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8004 n_occurrences += count_occurrences (PATTERN (insn),
8005 eliminate_regs (substed, 0,
8007 for (i1 = reg_equiv_alt_mem_list [REGNO (reg)]; i1; i1 = XEXP (i1, 1))
8009 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8010 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8012 if (n_occurrences > n_inherited)
8015 /* If the pseudo-reg we are reloading is no longer referenced
8016 anywhere between the store into it and here,
8017 and we're within the same basic block, then the value can only
8018 pass through the reload reg and end up here.
8019 Otherwise, give up--return. */
8020 for (i1 = NEXT_INSN (output_reload_insn);
8021 i1 != insn; i1 = NEXT_INSN (i1))
8023 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8025 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8026 && reg_mentioned_p (reg, PATTERN (i1)))
8028 /* If this is USE in front of INSN, we only have to check that
8029 there are no more references than accounted for by inheritance. */
8030 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8032 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8033 i1 = NEXT_INSN (i1);
8035 if (n_occurrences <= n_inherited && i1 == insn)
8041 /* We will be deleting the insn. Remove the spill reg information. */
8042 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8044 spill_reg_store[last_reload_reg + k] = 0;
8045 spill_reg_stored_to[last_reload_reg + k] = 0;
8048 /* The caller has already checked that REG dies or is set in INSN.
8049 It has also checked that we are optimizing, and thus some
8050 inaccuracies in the debugging information are acceptable.
8051 So we could just delete output_reload_insn. But in some cases
8052 we can improve the debugging information without sacrificing
8053 optimization - maybe even improving the code: See if the pseudo
8054 reg has been completely replaced with reload regs. If so, delete
8055 the store insn and forget we had a stack slot for the pseudo. */
8056 if (rld[j].out != rld[j].in
8057 && REG_N_DEATHS (REGNO (reg)) == 1
8058 && REG_N_SETS (REGNO (reg)) == 1
8059 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
8060 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8064 /* We know that it was used only between here and the beginning of
8065 the current basic block. (We also know that the last use before
8066 INSN was the output reload we are thinking of deleting, but never
8067 mind that.) Search that range; see if any ref remains. */
8068 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8070 rtx set = single_set (i2);
8072 /* Uses which just store in the pseudo don't count,
8073 since if they are the only uses, they are dead. */
8074 if (set != 0 && SET_DEST (set) == reg)
8079 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8080 && reg_mentioned_p (reg, PATTERN (i2)))
8082 /* Some other ref remains; just delete the output reload we
8084 delete_address_reloads (output_reload_insn, insn);
8085 delete_insn (output_reload_insn);
8090 /* Delete the now-dead stores into this pseudo. Note that this
8091 loop also takes care of deleting output_reload_insn. */
8092 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8094 rtx set = single_set (i2);
8096 if (set != 0 && SET_DEST (set) == reg)
8098 delete_address_reloads (i2, insn);
8106 /* For the debugging info, say the pseudo lives in this reload reg. */
8107 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
8108 alter_reg (REGNO (reg), -1);
8112 delete_address_reloads (output_reload_insn, insn);
8113 delete_insn (output_reload_insn);
8117 /* We are going to delete DEAD_INSN. Recursively delete loads of
8118 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8119 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8121 delete_address_reloads (rtx dead_insn, rtx current_insn)
8123 rtx set = single_set (dead_insn);
8124 rtx set2, dst, prev, next;
8127 rtx dst = SET_DEST (set);
8129 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8131 /* If we deleted the store from a reloaded post_{in,de}c expression,
8132 we can delete the matching adds. */
8133 prev = PREV_INSN (dead_insn);
8134 next = NEXT_INSN (dead_insn);
8135 if (! prev || ! next)
8137 set = single_set (next);
8138 set2 = single_set (prev);
8140 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8141 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8142 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8144 dst = SET_DEST (set);
8145 if (! rtx_equal_p (dst, SET_DEST (set2))
8146 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8147 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8148 || (INTVAL (XEXP (SET_SRC (set), 1))
8149 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8151 delete_related_insns (prev);
8152 delete_related_insns (next);
8155 /* Subfunction of delete_address_reloads: process registers found in X. */
8157 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8159 rtx prev, set, dst, i2;
8161 enum rtx_code code = GET_CODE (x);
8165 const char *fmt = GET_RTX_FORMAT (code);
8166 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8169 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8170 else if (fmt[i] == 'E')
8172 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8173 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8180 if (spill_reg_order[REGNO (x)] < 0)
8183 /* Scan backwards for the insn that sets x. This might be a way back due
8185 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8187 code = GET_CODE (prev);
8188 if (code == CODE_LABEL || code == JUMP_INSN)
8192 if (reg_set_p (x, PATTERN (prev)))
8194 if (reg_referenced_p (x, PATTERN (prev)))
8197 if (! prev || INSN_UID (prev) < reload_first_uid)
8199 /* Check that PREV only sets the reload register. */
8200 set = single_set (prev);
8203 dst = SET_DEST (set);
8205 || ! rtx_equal_p (dst, x))
8207 if (! reg_set_p (dst, PATTERN (dead_insn)))
8209 /* Check if DST was used in a later insn -
8210 it might have been inherited. */
8211 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8217 if (reg_referenced_p (dst, PATTERN (i2)))
8219 /* If there is a reference to the register in the current insn,
8220 it might be loaded in a non-inherited reload. If no other
8221 reload uses it, that means the register is set before
8223 if (i2 == current_insn)
8225 for (j = n_reloads - 1; j >= 0; j--)
8226 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8227 || reload_override_in[j] == dst)
8229 for (j = n_reloads - 1; j >= 0; j--)
8230 if (rld[j].in && rld[j].reg_rtx == dst)
8239 /* If DST is still live at CURRENT_INSN, check if it is used for
8240 any reload. Note that even if CURRENT_INSN sets DST, we still
8241 have to check the reloads. */
8242 if (i2 == current_insn)
8244 for (j = n_reloads - 1; j >= 0; j--)
8245 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8246 || reload_override_in[j] == dst)
8248 /* ??? We can't finish the loop here, because dst might be
8249 allocated to a pseudo in this block if no reload in this
8250 block needs any of the classes containing DST - see
8251 spill_hard_reg. There is no easy way to tell this, so we
8252 have to scan till the end of the basic block. */
8254 if (reg_set_p (dst, PATTERN (i2)))
8258 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8259 reg_reloaded_contents[REGNO (dst)] = -1;
8263 /* Output reload-insns to reload VALUE into RELOADREG.
8264 VALUE is an autoincrement or autodecrement RTX whose operand
8265 is a register or memory location;
8266 so reloading involves incrementing that location.
8267 IN is either identical to VALUE, or some cheaper place to reload from.
8269 INC_AMOUNT is the number to increment or decrement by (always positive).
8270 This cannot be deduced from VALUE.
8272 Return the instruction that stores into RELOADREG. */
8275 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8277 /* REG or MEM to be copied and incremented. */
8278 rtx incloc = find_replacement (&XEXP (value, 0));
8279 /* Nonzero if increment after copying. */
8280 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8281 || GET_CODE (value) == POST_MODIFY);
8287 rtx real_in = in == value ? incloc : in;
8289 /* No hard register is equivalent to this register after
8290 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8291 we could inc/dec that register as well (maybe even using it for
8292 the source), but I'm not sure it's worth worrying about. */
8294 reg_last_reload_reg[REGNO (incloc)] = 0;
8296 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8298 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8299 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
8303 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8304 inc_amount = -inc_amount;
8306 inc = GEN_INT (inc_amount);
8309 /* If this is post-increment, first copy the location to the reload reg. */
8310 if (post && real_in != reloadreg)
8311 emit_insn (gen_move_insn (reloadreg, real_in));
8315 /* See if we can directly increment INCLOC. Use a method similar to
8316 that in gen_reload. */
8318 last = get_last_insn ();
8319 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8320 gen_rtx_PLUS (GET_MODE (incloc),
8323 code = recog_memoized (add_insn);
8326 extract_insn (add_insn);
8327 if (constrain_operands (1))
8329 /* If this is a pre-increment and we have incremented the value
8330 where it lives, copy the incremented value to RELOADREG to
8331 be used as an address. */
8334 emit_insn (gen_move_insn (reloadreg, incloc));
8339 delete_insns_since (last);
8342 /* If couldn't do the increment directly, must increment in RELOADREG.
8343 The way we do this depends on whether this is pre- or post-increment.
8344 For pre-increment, copy INCLOC to the reload register, increment it
8345 there, then save back. */
8349 if (in != reloadreg)
8350 emit_insn (gen_move_insn (reloadreg, real_in));
8351 emit_insn (gen_add2_insn (reloadreg, inc));
8352 store = emit_insn (gen_move_insn (incloc, reloadreg));
8357 Because this might be a jump insn or a compare, and because RELOADREG
8358 may not be available after the insn in an input reload, we must do
8359 the incrementation before the insn being reloaded for.
8361 We have already copied IN to RELOADREG. Increment the copy in
8362 RELOADREG, save that back, then decrement RELOADREG so it has
8363 the original value. */
8365 emit_insn (gen_add2_insn (reloadreg, inc));
8366 store = emit_insn (gen_move_insn (incloc, reloadreg));
8367 if (GET_CODE (inc) == CONST_INT)
8368 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
8370 emit_insn (gen_sub2_insn (reloadreg, inc));
8378 add_auto_inc_notes (rtx insn, rtx x)
8380 enum rtx_code code = GET_CODE (x);
8384 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8387 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8391 /* Scan all the operand sub-expressions. */
8392 fmt = GET_RTX_FORMAT (code);
8393 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8396 add_auto_inc_notes (insn, XEXP (x, i));
8397 else if (fmt[i] == 'E')
8398 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8399 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8404 /* Copy EH notes from an insn to its reloads. */
8406 copy_eh_notes (rtx insn, rtx x)
8408 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8411 for (; x != 0; x = NEXT_INSN (x))
8413 if (may_trap_p (PATTERN (x)))
8415 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8421 /* This is used by reload pass, that does emit some instructions after
8422 abnormal calls moving basic block end, but in fact it wants to emit
8423 them on the edge. Looks for abnormal call edges, find backward the
8424 proper call and fix the damage.
8426 Similar handle instructions throwing exceptions internally. */
8428 fixup_abnormal_edges (void)
8430 bool inserted = false;
8438 /* Look for cases we are interested in - calls or instructions causing
8440 FOR_EACH_EDGE (e, ei, bb->succs)
8442 if (e->flags & EDGE_ABNORMAL_CALL)
8444 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8445 == (EDGE_ABNORMAL | EDGE_EH))
8448 if (e && !CALL_P (BB_END (bb))
8449 && !can_throw_internal (BB_END (bb)))
8453 /* Get past the new insns generated. Allow notes, as the insns
8454 may be already deleted. */
8456 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8457 && !can_throw_internal (insn)
8458 && insn != BB_HEAD (bb))
8459 insn = PREV_INSN (insn);
8461 if (CALL_P (insn) || can_throw_internal (insn))
8465 stop = NEXT_INSN (BB_END (bb));
8467 insn = NEXT_INSN (insn);
8469 FOR_EACH_EDGE (e, ei, bb->succs)
8470 if (e->flags & EDGE_FALLTHRU)
8473 while (insn && insn != stop)
8475 next = NEXT_INSN (insn);
8480 /* Sometimes there's still the return value USE.
8481 If it's placed after a trapping call (i.e. that
8482 call is the last insn anyway), we have no fallthru
8483 edge. Simply delete this use and don't try to insert
8484 on the non-existent edge. */
8485 if (GET_CODE (PATTERN (insn)) != USE)
8487 /* We're not deleting it, we're moving it. */
8488 INSN_DELETED_P (insn) = 0;
8489 PREV_INSN (insn) = NULL_RTX;
8490 NEXT_INSN (insn) = NULL_RTX;
8492 insert_insn_on_edge (insn, e);
8500 /* It may be that we don't find any such trapping insn. In this
8501 case we discovered quite late that the insn that had been
8502 marked as can_throw_internal in fact couldn't trap at all.
8503 So we should in fact delete the EH edges out of the block. */
8505 purge_dead_edges (bb);
8509 /* We've possibly turned single trapping insn into multiple ones. */
8510 if (flag_non_call_exceptions)
8513 blocks = sbitmap_alloc (last_basic_block);
8514 sbitmap_ones (blocks);
8515 find_many_sub_basic_blocks (blocks);
8519 commit_edge_insertions ();
8521 #ifdef ENABLE_CHECKING
8522 /* Verify that we didn't turn one trapping insn into many, and that
8523 we found and corrected all of the problems wrt fixups on the
8525 verify_flow_info ();
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