1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 88, 89, 92, 93, 1994 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
25 #include "insn-config.h"
26 #include "insn-flags.h"
27 #include "insn-codes.h"
31 #include "hard-reg-set.h"
34 #include "basic-block.h"
37 /* This file contains the reload pass of the compiler, which is
38 run after register allocation has been done. It checks that
39 each insn is valid (operands required to be in registers really
40 are in registers of the proper class) and fixes up invalid ones
41 by copying values temporarily into registers for the insns
44 The results of register allocation are described by the vector
45 reg_renumber; the insns still contain pseudo regs, but reg_renumber
46 can be used to find which hard reg, if any, a pseudo reg is in.
48 The technique we always use is to free up a few hard regs that are
49 called ``reload regs'', and for each place where a pseudo reg
50 must be in a hard reg, copy it temporarily into one of the reload regs.
52 All the pseudos that were formerly allocated to the hard regs that
53 are now in use as reload regs must be ``spilled''. This means
54 that they go to other hard regs, or to stack slots if no other
55 available hard regs can be found. Spilling can invalidate more
56 insns, requiring additional need for reloads, so we must keep checking
57 until the process stabilizes.
59 For machines with different classes of registers, we must keep track
60 of the register class needed for each reload, and make sure that
61 we allocate enough reload registers of each class.
63 The file reload.c contains the code that checks one insn for
64 validity and reports the reloads that it needs. This file
65 is in charge of scanning the entire rtl code, accumulating the
66 reload needs, spilling, assigning reload registers to use for
67 fixing up each insn, and generating the new insns to copy values
68 into the reload registers. */
71 #ifndef REGISTER_MOVE_COST
72 #define REGISTER_MOVE_COST(x, y) 2
75 #ifndef MEMORY_MOVE_COST
76 #define MEMORY_MOVE_COST(x) 4
79 /* During reload_as_needed, element N contains a REG rtx for the hard reg
80 into which reg N has been reloaded (perhaps for a previous insn). */
81 static rtx *reg_last_reload_reg;
83 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
84 for an output reload that stores into reg N. */
85 static char *reg_has_output_reload;
87 /* Indicates which hard regs are reload-registers for an output reload
88 in the current insn. */
89 static HARD_REG_SET reg_is_output_reload;
91 /* Element N is the constant value to which pseudo reg N is equivalent,
92 or zero if pseudo reg N is not equivalent to a constant.
93 find_reloads looks at this in order to replace pseudo reg N
94 with the constant it stands for. */
95 rtx *reg_equiv_constant;
97 /* Element N is a memory location to which pseudo reg N is equivalent,
98 prior to any register elimination (such as frame pointer to stack
99 pointer). Depending on whether or not it is a valid address, this value
100 is transferred to either reg_equiv_address or reg_equiv_mem. */
101 rtx *reg_equiv_memory_loc;
103 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
104 This is used when the address is not valid as a memory address
105 (because its displacement is too big for the machine.) */
106 rtx *reg_equiv_address;
108 /* Element N is the memory slot to which pseudo reg N is equivalent,
109 or zero if pseudo reg N is not equivalent to a memory slot. */
112 /* Widest width in which each pseudo reg is referred to (via subreg). */
113 static int *reg_max_ref_width;
115 /* Element N is the insn that initialized reg N from its equivalent
116 constant or memory slot. */
117 static rtx *reg_equiv_init;
119 /* During reload_as_needed, element N contains the last pseudo regno
120 reloaded into the Nth reload register. This vector is in parallel
121 with spill_regs. If that pseudo reg occupied more than one register,
122 reg_reloaded_contents points to that pseudo for each spill register in
123 use; all of these must remain set for an inheritance to occur. */
124 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
126 /* During reload_as_needed, element N contains the insn for which
127 the Nth reload register was last used. This vector is in parallel
128 with spill_regs, and its contents are significant only when
129 reg_reloaded_contents is significant. */
130 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
132 /* Number of spill-regs so far; number of valid elements of spill_regs. */
135 /* In parallel with spill_regs, contains REG rtx's for those regs.
136 Holds the last rtx used for any given reg, or 0 if it has never
137 been used for spilling yet. This rtx is reused, provided it has
139 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
141 /* In parallel with spill_regs, contains nonzero for a spill reg
142 that was stored after the last time it was used.
143 The precise value is the insn generated to do the store. */
144 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
146 /* This table is the inverse mapping of spill_regs:
147 indexed by hard reg number,
148 it contains the position of that reg in spill_regs,
149 or -1 for something that is not in spill_regs. */
150 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
152 /* This reg set indicates registers that may not be used for retrying global
153 allocation. The registers that may not be used include all spill registers
154 and the frame pointer (if we are using one). */
155 HARD_REG_SET forbidden_regs;
157 /* This reg set indicates registers that are not good for spill registers.
158 They will not be used to complete groups of spill registers. This includes
159 all fixed registers, registers that may be eliminated, and, if
160 SMALL_REGISTER_CLASSES is not defined, registers explicitly used in the rtl.
162 (spill_reg_order prevents these registers from being used to start a
164 static HARD_REG_SET bad_spill_regs;
166 /* Describes order of use of registers for reloading
167 of spilled pseudo-registers. `spills' is the number of
168 elements that are actually valid; new ones are added at the end. */
169 static short spill_regs[FIRST_PSEUDO_REGISTER];
171 /* Describes order of preference for putting regs into spill_regs.
172 Contains the numbers of all the hard regs, in order most preferred first.
173 This order is different for each function.
174 It is set up by order_regs_for_reload.
175 Empty elements at the end contain -1. */
176 static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
178 /* 1 for a hard register that appears explicitly in the rtl
179 (for example, function value registers, special registers
180 used by insns, structure value pointer registers). */
181 static char regs_explicitly_used[FIRST_PSEUDO_REGISTER];
183 /* Indicates if a register was counted against the need for
184 groups. 0 means it can count against max_nongroup instead. */
185 static HARD_REG_SET counted_for_groups;
187 /* Indicates if a register was counted against the need for
188 non-groups. 0 means it can become part of a new group.
189 During choose_reload_regs, 1 here means don't use this reg
190 as part of a group, even if it seems to be otherwise ok. */
191 static HARD_REG_SET counted_for_nongroups;
193 /* Indexed by pseudo reg number N,
194 says may not delete stores into the real (memory) home of pseudo N.
195 This is set if we already substituted a memory equivalent in some uses,
196 which happens when we have to eliminate the fp from it. */
197 static char *cannot_omit_stores;
199 /* Nonzero if indirect addressing is supported on the machine; this means
200 that spilling (REG n) does not require reloading it into a register in
201 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
202 value indicates the level of indirect addressing supported, e.g., two
203 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
206 static char spill_indirect_levels;
208 /* Nonzero if indirect addressing is supported when the innermost MEM is
209 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
210 which these are valid is the same as spill_indirect_levels, above. */
212 char indirect_symref_ok;
214 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
216 char double_reg_address_ok;
218 /* Record the stack slot for each spilled hard register. */
220 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
222 /* Width allocated so far for that stack slot. */
224 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
226 /* Indexed by register class and basic block number, nonzero if there is
227 any need for a spill register of that class in that basic block.
228 The pointer is 0 if we did stupid allocation and don't know
229 the structure of basic blocks. */
231 char *basic_block_needs[N_REG_CLASSES];
233 /* First uid used by insns created by reload in this function.
234 Used in find_equiv_reg. */
235 int reload_first_uid;
237 /* Flag set by local-alloc or global-alloc if anything is live in
238 a call-clobbered reg across calls. */
240 int caller_save_needed;
242 /* Set to 1 while reload_as_needed is operating.
243 Required by some machines to handle any generated moves differently. */
245 int reload_in_progress = 0;
247 /* These arrays record the insn_code of insns that may be needed to
248 perform input and output reloads of special objects. They provide a
249 place to pass a scratch register. */
251 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
252 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
254 /* This obstack is used for allocation of rtl during register elimination.
255 The allocated storage can be freed once find_reloads has processed the
258 struct obstack reload_obstack;
259 char *reload_firstobj;
261 #define obstack_chunk_alloc xmalloc
262 #define obstack_chunk_free free
264 /* List of labels that must never be deleted. */
265 extern rtx forced_labels;
267 /* This structure is used to record information about register eliminations.
268 Each array entry describes one possible way of eliminating a register
269 in favor of another. If there is more than one way of eliminating a
270 particular register, the most preferred should be specified first. */
272 static struct elim_table
274 int from; /* Register number to be eliminated. */
275 int to; /* Register number used as replacement. */
276 int initial_offset; /* Initial difference between values. */
277 int can_eliminate; /* Non-zero if this elimination can be done. */
278 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
279 insns made by reload. */
280 int offset; /* Current offset between the two regs. */
281 int max_offset; /* Maximum offset between the two regs. */
282 int previous_offset; /* Offset at end of previous insn. */
283 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
284 rtx from_rtx; /* REG rtx for the register to be eliminated.
285 We cannot simply compare the number since
286 we might then spuriously replace a hard
287 register corresponding to a pseudo
288 assigned to the reg to be eliminated. */
289 rtx to_rtx; /* REG rtx for the replacement. */
292 /* If a set of eliminable registers was specified, define the table from it.
293 Otherwise, default to the normal case of the frame pointer being
294 replaced by the stack pointer. */
296 #ifdef ELIMINABLE_REGS
299 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
302 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate / sizeof reg_eliminate[0])
304 /* Record the number of pending eliminations that have an offset not equal
305 to their initial offset. If non-zero, we use a new copy of each
306 replacement result in any insns encountered. */
307 static int num_not_at_initial_offset;
309 /* Count the number of registers that we may be able to eliminate. */
310 static int num_eliminable;
312 /* For each label, we record the offset of each elimination. If we reach
313 a label by more than one path and an offset differs, we cannot do the
314 elimination. This information is indexed by the number of the label.
315 The first table is an array of flags that records whether we have yet
316 encountered a label and the second table is an array of arrays, one
317 entry in the latter array for each elimination. */
319 static char *offsets_known_at;
320 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
322 /* Number of labels in the current function. */
324 static int num_labels;
326 struct hard_reg_n_uses { int regno; int uses; };
328 static int possible_group_p PROTO((int, int *));
329 static void count_possible_groups PROTO((int *, enum machine_mode *,
331 static int modes_equiv_for_class_p PROTO((enum machine_mode,
334 static void spill_failure PROTO((rtx));
335 static int new_spill_reg PROTO((int, int, int *, int *, int,
337 static void delete_dead_insn PROTO((rtx));
338 static void alter_reg PROTO((int, int));
339 static void mark_scratch_live PROTO((rtx));
340 static void set_label_offsets PROTO((rtx, rtx, int));
341 static int eliminate_regs_in_insn PROTO((rtx, int));
342 static void mark_not_eliminable PROTO((rtx, rtx));
343 static int spill_hard_reg PROTO((int, int, FILE *, int));
344 static void scan_paradoxical_subregs PROTO((rtx));
345 static int hard_reg_use_compare PROTO((struct hard_reg_n_uses *,
346 struct hard_reg_n_uses *));
347 static void order_regs_for_reload PROTO((void));
348 static void reload_as_needed PROTO((rtx, int));
349 static void forget_old_reloads_1 PROTO((rtx, rtx));
350 static int reload_reg_class_lower PROTO((short *, short *));
351 static void mark_reload_reg_in_use PROTO((int, int, enum reload_type,
353 static void clear_reload_reg_in_use PROTO((int, int, enum reload_type,
355 static int reload_reg_free_p PROTO((int, int, enum reload_type));
356 static int reload_reg_free_before_p PROTO((int, int, enum reload_type));
357 static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type));
358 static int reloads_conflict PROTO((int, int));
359 static int allocate_reload_reg PROTO((int, rtx, int, int));
360 static void choose_reload_regs PROTO((rtx, rtx));
361 static void merge_assigned_reloads PROTO((rtx));
362 static void emit_reload_insns PROTO((rtx));
363 static void delete_output_reload PROTO((rtx, int, rtx));
364 static void inc_for_reload PROTO((rtx, rtx, int));
365 static int constraint_accepts_reg_p PROTO((char *, rtx));
366 static int count_occurrences PROTO((rtx, rtx));
368 /* Initialize the reload pass once per compilation. */
375 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
376 Set spill_indirect_levels to the number of levels such addressing is
377 permitted, zero if it is not permitted at all. */
380 = gen_rtx (MEM, Pmode,
381 gen_rtx (PLUS, Pmode,
382 gen_rtx (REG, Pmode, LAST_VIRTUAL_REGISTER + 1),
384 spill_indirect_levels = 0;
386 while (memory_address_p (QImode, tem))
388 spill_indirect_levels++;
389 tem = gen_rtx (MEM, Pmode, tem);
392 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
394 tem = gen_rtx (MEM, Pmode, gen_rtx (SYMBOL_REF, Pmode, "foo"));
395 indirect_symref_ok = memory_address_p (QImode, tem);
397 /* See if reg+reg is a valid (and offsettable) address. */
399 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
401 tem = gen_rtx (PLUS, Pmode,
402 gen_rtx (REG, Pmode, HARD_FRAME_POINTER_REGNUM),
403 gen_rtx (REG, Pmode, i));
404 /* This way, we make sure that reg+reg is an offsettable address. */
405 tem = plus_constant (tem, 4);
407 if (memory_address_p (QImode, tem))
409 double_reg_address_ok = 1;
414 /* Initialize obstack for our rtl allocation. */
415 gcc_obstack_init (&reload_obstack);
416 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
419 /* Main entry point for the reload pass.
421 FIRST is the first insn of the function being compiled.
423 GLOBAL nonzero means we were called from global_alloc
424 and should attempt to reallocate any pseudoregs that we
425 displace from hard regs we will use for reloads.
426 If GLOBAL is zero, we do not have enough information to do that,
427 so any pseudo reg that is spilled must go to the stack.
429 DUMPFILE is the global-reg debugging dump file stream, or 0.
430 If it is nonzero, messages are written to it to describe
431 which registers are seized as reload regs, which pseudo regs
432 are spilled from them, and where the pseudo regs are reallocated to.
434 Return value is nonzero if reload failed
435 and we must not do any more for this function. */
438 reload (first, global, dumpfile)
446 register struct elim_table *ep;
448 int something_changed;
449 int something_needs_reloads;
450 int something_needs_elimination;
451 int new_basic_block_needs;
452 enum reg_class caller_save_spill_class = NO_REGS;
453 int caller_save_group_size = 1;
455 /* Nonzero means we couldn't get enough spill regs. */
458 /* The basic block number currently being processed for INSN. */
461 /* Make sure even insns with volatile mem refs are recognizable. */
464 /* Enable find_equiv_reg to distinguish insns made by reload. */
465 reload_first_uid = get_max_uid ();
467 for (i = 0; i < N_REG_CLASSES; i++)
468 basic_block_needs[i] = 0;
470 #ifdef SECONDARY_MEMORY_NEEDED
471 /* Initialize the secondary memory table. */
472 clear_secondary_mem ();
475 /* Remember which hard regs appear explicitly
476 before we merge into `regs_ever_live' the ones in which
477 pseudo regs have been allocated. */
478 bcopy (regs_ever_live, regs_explicitly_used, sizeof regs_ever_live);
480 /* We don't have a stack slot for any spill reg yet. */
481 bzero (spill_stack_slot, sizeof spill_stack_slot);
482 bzero (spill_stack_slot_width, sizeof spill_stack_slot_width);
484 /* Initialize the save area information for caller-save, in case some
488 /* Compute which hard registers are now in use
489 as homes for pseudo registers.
490 This is done here rather than (eg) in global_alloc
491 because this point is reached even if not optimizing. */
493 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
496 for (i = 0; i < scratch_list_length; i++)
498 mark_scratch_live (scratch_list[i]);
500 /* Make sure that the last insn in the chain
501 is not something that needs reloading. */
502 emit_note (NULL_PTR, NOTE_INSN_DELETED);
504 /* Find all the pseudo registers that didn't get hard regs
505 but do have known equivalent constants or memory slots.
506 These include parameters (known equivalent to parameter slots)
507 and cse'd or loop-moved constant memory addresses.
509 Record constant equivalents in reg_equiv_constant
510 so they will be substituted by find_reloads.
511 Record memory equivalents in reg_mem_equiv so they can
512 be substituted eventually by altering the REG-rtx's. */
514 reg_equiv_constant = (rtx *) alloca (max_regno * sizeof (rtx));
515 bzero (reg_equiv_constant, max_regno * sizeof (rtx));
516 reg_equiv_memory_loc = (rtx *) alloca (max_regno * sizeof (rtx));
517 bzero (reg_equiv_memory_loc, max_regno * sizeof (rtx));
518 reg_equiv_mem = (rtx *) alloca (max_regno * sizeof (rtx));
519 bzero (reg_equiv_mem, max_regno * sizeof (rtx));
520 reg_equiv_init = (rtx *) alloca (max_regno * sizeof (rtx));
521 bzero (reg_equiv_init, max_regno * sizeof (rtx));
522 reg_equiv_address = (rtx *) alloca (max_regno * sizeof (rtx));
523 bzero (reg_equiv_address, max_regno * sizeof (rtx));
524 reg_max_ref_width = (int *) alloca (max_regno * sizeof (int));
525 bzero (reg_max_ref_width, max_regno * sizeof (int));
526 cannot_omit_stores = (char *) alloca (max_regno);
527 bzero (cannot_omit_stores, max_regno);
529 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
530 Also find all paradoxical subregs
531 and find largest such for each pseudo. */
533 for (insn = first; insn; insn = NEXT_INSN (insn))
535 rtx set = single_set (insn);
537 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
539 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
541 #ifdef LEGITIMATE_PIC_OPERAND_P
542 && (! CONSTANT_P (XEXP (note, 0)) || ! flag_pic
543 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
547 rtx x = XEXP (note, 0);
548 i = REGNO (SET_DEST (set));
549 if (i > LAST_VIRTUAL_REGISTER)
551 if (GET_CODE (x) == MEM)
552 reg_equiv_memory_loc[i] = x;
553 else if (CONSTANT_P (x))
555 if (LEGITIMATE_CONSTANT_P (x))
556 reg_equiv_constant[i] = x;
558 reg_equiv_memory_loc[i]
559 = force_const_mem (GET_MODE (SET_DEST (set)), x);
564 /* If this register is being made equivalent to a MEM
565 and the MEM is not SET_SRC, the equivalencing insn
566 is one with the MEM as a SET_DEST and it occurs later.
567 So don't mark this insn now. */
568 if (GET_CODE (x) != MEM
569 || rtx_equal_p (SET_SRC (set), x))
570 reg_equiv_init[i] = insn;
575 /* If this insn is setting a MEM from a register equivalent to it,
576 this is the equivalencing insn. */
577 else if (set && GET_CODE (SET_DEST (set)) == MEM
578 && GET_CODE (SET_SRC (set)) == REG
579 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
580 && rtx_equal_p (SET_DEST (set),
581 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
582 reg_equiv_init[REGNO (SET_SRC (set))] = insn;
584 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
585 scan_paradoxical_subregs (PATTERN (insn));
588 /* Does this function require a frame pointer? */
590 frame_pointer_needed = (! flag_omit_frame_pointer
591 #ifdef EXIT_IGNORE_STACK
592 /* ?? If EXIT_IGNORE_STACK is set, we will not save
593 and restore sp for alloca. So we can't eliminate
594 the frame pointer in that case. At some point,
595 we should improve this by emitting the
596 sp-adjusting insns for this case. */
597 || (current_function_calls_alloca
598 && EXIT_IGNORE_STACK)
600 || FRAME_POINTER_REQUIRED);
604 /* Initialize the table of registers to eliminate. The way we do this
605 depends on how the eliminable registers were defined. */
606 #ifdef ELIMINABLE_REGS
607 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
609 ep->can_eliminate = ep->can_eliminate_previous
610 = (CAN_ELIMINATE (ep->from, ep->to)
611 && (ep->from != HARD_FRAME_POINTER_REGNUM
612 || ! frame_pointer_needed));
615 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
616 = ! frame_pointer_needed;
619 /* Count the number of eliminable registers and build the FROM and TO
620 REG rtx's. Note that code in gen_rtx will cause, e.g.,
621 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
622 We depend on this. */
623 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
625 num_eliminable += ep->can_eliminate;
626 ep->from_rtx = gen_rtx (REG, Pmode, ep->from);
627 ep->to_rtx = gen_rtx (REG, Pmode, ep->to);
630 num_labels = max_label_num () - get_first_label_num ();
632 /* Allocate the tables used to store offset information at labels. */
633 offsets_known_at = (char *) alloca (num_labels);
635 = (int (*)[NUM_ELIMINABLE_REGS])
636 alloca (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
638 offsets_known_at -= get_first_label_num ();
639 offsets_at -= get_first_label_num ();
641 /* Alter each pseudo-reg rtx to contain its hard reg number.
642 Assign stack slots to the pseudos that lack hard regs or equivalents.
643 Do not touch virtual registers. */
645 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
648 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done here
649 because the stack size may be a part of the offset computation for
650 register elimination. */
651 assign_stack_local (BLKmode, 0, 0);
653 /* If we have some registers we think can be eliminated, scan all insns to
654 see if there is an insn that sets one of these registers to something
655 other than itself plus a constant. If so, the register cannot be
656 eliminated. Doing this scan here eliminates an extra pass through the
657 main reload loop in the most common case where register elimination
659 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
660 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
661 || GET_CODE (insn) == CALL_INSN)
662 note_stores (PATTERN (insn), mark_not_eliminable);
664 #ifndef REGISTER_CONSTRAINTS
665 /* If all the pseudo regs have hard regs,
666 except for those that are never referenced,
667 we know that no reloads are needed. */
668 /* But that is not true if there are register constraints, since
669 in that case some pseudos might be in the wrong kind of hard reg. */
671 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
672 if (reg_renumber[i] == -1 && reg_n_refs[i] != 0)
675 if (i == max_regno && num_eliminable == 0 && ! caller_save_needed)
679 /* Compute the order of preference for hard registers to spill.
680 Store them by decreasing preference in potential_reload_regs. */
682 order_regs_for_reload ();
684 /* So far, no hard regs have been spilled. */
686 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
687 spill_reg_order[i] = -1;
689 /* On most machines, we can't use any register explicitly used in the
690 rtl as a spill register. But on some, we have to. Those will have
691 taken care to keep the life of hard regs as short as possible. */
693 #ifdef SMALL_REGISTER_CLASSES
694 CLEAR_HARD_REG_SET (forbidden_regs);
696 COPY_HARD_REG_SET (forbidden_regs, bad_spill_regs);
699 /* Spill any hard regs that we know we can't eliminate. */
700 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
701 if (! ep->can_eliminate)
703 spill_hard_reg (ep->from, global, dumpfile, 1);
704 regs_ever_live[ep->from] = 1;
708 for (i = 0; i < N_REG_CLASSES; i++)
710 basic_block_needs[i] = (char *)alloca (n_basic_blocks);
711 bzero (basic_block_needs[i], n_basic_blocks);
714 /* From now on, we need to emit any moves without making new pseudos. */
715 reload_in_progress = 1;
717 /* This loop scans the entire function each go-round
718 and repeats until one repetition spills no additional hard regs. */
720 /* This flag is set when a pseudo reg is spilled,
721 to require another pass. Note that getting an additional reload
722 reg does not necessarily imply any pseudo reg was spilled;
723 sometimes we find a reload reg that no pseudo reg was allocated in. */
724 something_changed = 1;
725 /* This flag is set if there are any insns that require reloading. */
726 something_needs_reloads = 0;
727 /* This flag is set if there are any insns that require register
729 something_needs_elimination = 0;
730 while (something_changed)
734 /* For each class, number of reload regs needed in that class.
735 This is the maximum over all insns of the needs in that class
736 of the individual insn. */
737 int max_needs[N_REG_CLASSES];
738 /* For each class, size of group of consecutive regs
739 that is needed for the reloads of this class. */
740 int group_size[N_REG_CLASSES];
741 /* For each class, max number of consecutive groups needed.
742 (Each group contains group_size[CLASS] consecutive registers.) */
743 int max_groups[N_REG_CLASSES];
744 /* For each class, max number needed of regs that don't belong
745 to any of the groups. */
746 int max_nongroups[N_REG_CLASSES];
747 /* For each class, the machine mode which requires consecutive
748 groups of regs of that class.
749 If two different modes ever require groups of one class,
750 they must be the same size and equally restrictive for that class,
751 otherwise we can't handle the complexity. */
752 enum machine_mode group_mode[N_REG_CLASSES];
753 /* Record the insn where each maximum need is first found. */
754 rtx max_needs_insn[N_REG_CLASSES];
755 rtx max_groups_insn[N_REG_CLASSES];
756 rtx max_nongroups_insn[N_REG_CLASSES];
758 int starting_frame_size = get_frame_size ();
759 static char *reg_class_names[] = REG_CLASS_NAMES;
761 something_changed = 0;
762 bzero (max_needs, sizeof max_needs);
763 bzero (max_groups, sizeof max_groups);
764 bzero (max_nongroups, sizeof max_nongroups);
765 bzero (max_needs_insn, sizeof max_needs_insn);
766 bzero (max_groups_insn, sizeof max_groups_insn);
767 bzero (max_nongroups_insn, sizeof max_nongroups_insn);
768 bzero (group_size, sizeof group_size);
769 for (i = 0; i < N_REG_CLASSES; i++)
770 group_mode[i] = VOIDmode;
772 /* Keep track of which basic blocks are needing the reloads. */
775 /* Remember whether any element of basic_block_needs
776 changes from 0 to 1 in this pass. */
777 new_basic_block_needs = 0;
779 /* Reset all offsets on eliminable registers to their initial values. */
780 #ifdef ELIMINABLE_REGS
781 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
783 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
784 ep->previous_offset = ep->offset
785 = ep->max_offset = ep->initial_offset;
788 #ifdef INITIAL_FRAME_POINTER_OFFSET
789 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
791 if (!FRAME_POINTER_REQUIRED)
793 reg_eliminate[0].initial_offset = 0;
795 reg_eliminate[0].previous_offset = reg_eliminate[0].max_offset
796 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
799 num_not_at_initial_offset = 0;
801 bzero (&offsets_known_at[get_first_label_num ()], num_labels);
803 /* Set a known offset for each forced label to be at the initial offset
804 of each elimination. We do this because we assume that all
805 computed jumps occur from a location where each elimination is
806 at its initial offset. */
808 for (x = forced_labels; x; x = XEXP (x, 1))
810 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
812 /* For each pseudo register that has an equivalent location defined,
813 try to eliminate any eliminable registers (such as the frame pointer)
814 assuming initial offsets for the replacement register, which
817 If the resulting location is directly addressable, substitute
818 the MEM we just got directly for the old REG.
820 If it is not addressable but is a constant or the sum of a hard reg
821 and constant, it is probably not addressable because the constant is
822 out of range, in that case record the address; we will generate
823 hairy code to compute the address in a register each time it is
824 needed. Similarly if it is a hard register, but one that is not
825 valid as an address register.
827 If the location is not addressable, but does not have one of the
828 above forms, assign a stack slot. We have to do this to avoid the
829 potential of producing lots of reloads if, e.g., a location involves
830 a pseudo that didn't get a hard register and has an equivalent memory
831 location that also involves a pseudo that didn't get a hard register.
833 Perhaps at some point we will improve reload_when_needed handling
834 so this problem goes away. But that's very hairy. */
836 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
837 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
839 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
841 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
843 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
844 else if (CONSTANT_P (XEXP (x, 0))
845 || (GET_CODE (XEXP (x, 0)) == REG
846 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
847 || (GET_CODE (XEXP (x, 0)) == PLUS
848 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
849 && (REGNO (XEXP (XEXP (x, 0), 0))
850 < FIRST_PSEUDO_REGISTER)
851 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
852 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
855 /* Make a new stack slot. Then indicate that something
856 changed so we go back and recompute offsets for
857 eliminable registers because the allocation of memory
858 below might change some offset. reg_equiv_{mem,address}
859 will be set up for this pseudo on the next pass around
861 reg_equiv_memory_loc[i] = 0;
862 reg_equiv_init[i] = 0;
864 something_changed = 1;
868 /* If we allocated another pseudo to the stack, redo elimination
870 if (something_changed)
873 /* If caller-saves needs a group, initialize the group to include
874 the size and mode required for caller-saves. */
876 if (caller_save_group_size > 1)
878 group_mode[(int) caller_save_spill_class] = Pmode;
879 group_size[(int) caller_save_spill_class] = caller_save_group_size;
882 /* Compute the most additional registers needed by any instruction.
883 Collect information separately for each class of regs. */
885 for (insn = first; insn; insn = NEXT_INSN (insn))
887 if (global && this_block + 1 < n_basic_blocks
888 && insn == basic_block_head[this_block+1])
891 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which
892 might include REG_LABEL), we need to see what effects this
893 has on the known offsets at labels. */
895 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
896 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
897 && REG_NOTES (insn) != 0))
898 set_label_offsets (insn, insn, 0);
900 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
902 /* Nonzero means don't use a reload reg that overlaps
903 the place where a function value can be returned. */
904 rtx avoid_return_reg = 0;
906 rtx old_body = PATTERN (insn);
907 int old_code = INSN_CODE (insn);
908 rtx old_notes = REG_NOTES (insn);
909 int did_elimination = 0;
910 int max_total_input_groups = 0, max_total_output_groups = 0;
912 /* To compute the number of reload registers of each class
913 needed for an insn, we must similate what choose_reload_regs
914 can do. We do this by splitting an insn into an "input" and
915 an "output" part. RELOAD_OTHER reloads are used in both.
916 The input part uses those reloads, RELOAD_FOR_INPUT reloads,
917 which must be live over the entire input section of reloads,
918 and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
919 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the
922 The registers needed for output are RELOAD_OTHER and
923 RELOAD_FOR_OUTPUT, which are live for the entire output
924 portion, and the maximum of all the RELOAD_FOR_OUTPUT_ADDRESS
925 reloads for each operand.
927 The total number of registers needed is the maximum of the
928 inputs and outputs. */
930 /* These just count RELOAD_OTHER. */
931 int insn_needs[N_REG_CLASSES];
932 int insn_groups[N_REG_CLASSES];
933 int insn_nongroups[N_REG_CLASSES];
934 int insn_total_groups = 0;
936 /* Count RELOAD_FOR_INPUT reloads. */
937 int insn_needs_for_inputs[N_REG_CLASSES];
938 int insn_nongroups_for_inputs[N_REG_CLASSES];
939 int insn_groups_for_inputs[N_REG_CLASSES];
940 int insn_total_groups_for_inputs = 0;
942 /* Count RELOAD_FOR_OUTPUT reloads. */
943 int insn_needs_for_outputs[N_REG_CLASSES];
944 int insn_nongroups_for_outputs[N_REG_CLASSES];
945 int insn_groups_for_outputs[N_REG_CLASSES];
946 int insn_total_groups_for_outputs = 0;
948 /* Count RELOAD_FOR_INSN reloads. */
949 int insn_needs_for_insn[N_REG_CLASSES];
950 int insn_nongroups_for_insn[N_REG_CLASSES];
951 int insn_groups_for_insn[N_REG_CLASSES];
952 int insn_total_groups_for_insn = 0;
954 /* Count RELOAD_FOR_OTHER_ADDRESS reloads. */
955 int insn_needs_for_other_addr[N_REG_CLASSES];
956 int insn_nongroups_for_other_addr[N_REG_CLASSES];
957 int insn_groups_for_other_addr[N_REG_CLASSES];
958 int insn_total_groups_for_other_addr = 0;
960 /* Count RELOAD_FOR_INPUT_ADDRESS reloads. */
961 int insn_needs_for_in_addr[MAX_RECOG_OPERANDS][N_REG_CLASSES];
962 int insn_nongroups_for_in_addr[MAX_RECOG_OPERANDS][N_REG_CLASSES];
963 int insn_groups_for_in_addr[MAX_RECOG_OPERANDS][N_REG_CLASSES];
964 int insn_total_groups_for_in_addr[MAX_RECOG_OPERANDS];
966 /* Count RELOAD_FOR_OUTPUT_ADDRESS reloads. */
967 int insn_needs_for_out_addr[MAX_RECOG_OPERANDS][N_REG_CLASSES];
968 int insn_nongroups_for_out_addr[MAX_RECOG_OPERANDS][N_REG_CLASSES];
969 int insn_groups_for_out_addr[MAX_RECOG_OPERANDS][N_REG_CLASSES];
970 int insn_total_groups_for_out_addr[MAX_RECOG_OPERANDS];
972 /* Count RELOAD_FOR_OPERAND_ADDRESS reloads. */
973 int insn_needs_for_op_addr[N_REG_CLASSES];
974 int insn_nongroups_for_op_addr[N_REG_CLASSES];
975 int insn_groups_for_op_addr[N_REG_CLASSES];
976 int insn_total_groups_for_op_addr = 0;
978 #if 0 /* This wouldn't work nowadays, since optimize_bit_field
979 looks for non-strict memory addresses. */
980 /* Optimization: a bit-field instruction whose field
981 happens to be a byte or halfword in memory
982 can be changed to a move instruction. */
984 if (GET_CODE (PATTERN (insn)) == SET)
986 rtx dest = SET_DEST (PATTERN (insn));
987 rtx src = SET_SRC (PATTERN (insn));
989 if (GET_CODE (dest) == ZERO_EXTRACT
990 || GET_CODE (dest) == SIGN_EXTRACT)
991 optimize_bit_field (PATTERN (insn), insn, reg_equiv_mem);
992 if (GET_CODE (src) == ZERO_EXTRACT
993 || GET_CODE (src) == SIGN_EXTRACT)
994 optimize_bit_field (PATTERN (insn), insn, reg_equiv_mem);
998 /* If needed, eliminate any eliminable registers. */
1000 did_elimination = eliminate_regs_in_insn (insn, 0);
1002 #ifdef SMALL_REGISTER_CLASSES
1003 /* Set avoid_return_reg if this is an insn
1004 that might use the value of a function call. */
1005 if (GET_CODE (insn) == CALL_INSN)
1007 if (GET_CODE (PATTERN (insn)) == SET)
1008 after_call = SET_DEST (PATTERN (insn));
1009 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1010 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1011 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
1015 else if (after_call != 0
1016 && !(GET_CODE (PATTERN (insn)) == SET
1017 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
1019 if (reg_mentioned_p (after_call, PATTERN (insn)))
1020 avoid_return_reg = after_call;
1023 #endif /* SMALL_REGISTER_CLASSES */
1025 /* Analyze the instruction. */
1026 find_reloads (insn, 0, spill_indirect_levels, global,
1029 /* Remember for later shortcuts which insns had any reloads or
1030 register eliminations.
1032 One might think that it would be worthwhile to mark insns
1033 that need register replacements but not reloads, but this is
1034 not safe because find_reloads may do some manipulation of
1035 the insn (such as swapping commutative operands), which would
1036 be lost when we restore the old pattern after register
1037 replacement. So the actions of find_reloads must be redone in
1038 subsequent passes or in reload_as_needed.
1040 However, it is safe to mark insns that need reloads
1041 but not register replacement. */
1043 PUT_MODE (insn, (did_elimination ? QImode
1044 : n_reloads ? HImode
1045 : GET_MODE (insn) == DImode ? DImode
1048 /* Discard any register replacements done. */
1049 if (did_elimination)
1051 obstack_free (&reload_obstack, reload_firstobj);
1052 PATTERN (insn) = old_body;
1053 INSN_CODE (insn) = old_code;
1054 REG_NOTES (insn) = old_notes;
1055 something_needs_elimination = 1;
1058 /* If this insn has no reloads, we need not do anything except
1059 in the case of a CALL_INSN when we have caller-saves and
1060 caller-save needs reloads. */
1063 && ! (GET_CODE (insn) == CALL_INSN
1064 && caller_save_spill_class != NO_REGS))
1067 something_needs_reloads = 1;
1069 for (i = 0; i < N_REG_CLASSES; i++)
1071 insn_needs[i] = 0, insn_nongroups[i] = 0,
1074 insn_needs_for_inputs[i] = 0,
1075 insn_nongroups_for_inputs[i] = 0,
1076 insn_groups_for_inputs[i] = 0;
1078 insn_needs_for_outputs[i] = 0,
1079 insn_nongroups_for_outputs[i] = 0,
1080 insn_groups_for_outputs[i] = 0;
1082 insn_needs_for_insn[i] = 0,
1083 insn_nongroups_for_insn[i] = 0,
1084 insn_groups_for_insn[i] = 0;
1086 insn_needs_for_op_addr[i] = 0,
1087 insn_nongroups_for_op_addr[i] = 0,
1088 insn_groups_for_op_addr[i] = 0;
1090 insn_needs_for_other_addr[i] = 0,
1091 insn_nongroups_for_other_addr[i] = 0,
1092 insn_groups_for_other_addr[i] = 0;
1095 for (i = 0; i < reload_n_operands; i++)
1097 insn_total_groups_for_in_addr[i] = 0;
1098 insn_total_groups_for_out_addr[i] = 0;
1100 for (j = 0; j < N_REG_CLASSES; j++)
1102 insn_needs_for_in_addr[i][j] = 0;
1103 insn_needs_for_out_addr[i][j] = 0;
1104 insn_nongroups_for_in_addr[i][j] = 0;
1105 insn_nongroups_for_out_addr[i][j] = 0;
1106 insn_groups_for_in_addr[i][j] = 0;
1107 insn_groups_for_out_addr[i][j] = 0;
1111 /* Count each reload once in every class
1112 containing the reload's own class. */
1114 for (i = 0; i < n_reloads; i++)
1116 register enum reg_class *p;
1117 enum reg_class class = reload_reg_class[i];
1119 enum machine_mode mode;
1123 int *this_total_groups;
1125 /* Don't count the dummy reloads, for which one of the
1126 regs mentioned in the insn can be used for reloading.
1127 Don't count optional reloads.
1128 Don't count reloads that got combined with others. */
1129 if (reload_reg_rtx[i] != 0
1130 || reload_optional[i] != 0
1131 || (reload_out[i] == 0 && reload_in[i] == 0
1132 && ! reload_secondary_p[i]))
1135 /* Show that a reload register of this class is needed
1136 in this basic block. We do not use insn_needs and
1137 insn_groups because they are overly conservative for
1139 if (global && ! basic_block_needs[(int) class][this_block])
1141 basic_block_needs[(int) class][this_block] = 1;
1142 new_basic_block_needs = 1;
1146 mode = reload_inmode[i];
1147 if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode))
1148 mode = reload_outmode[i];
1149 size = CLASS_MAX_NREGS (class, mode);
1151 /* If this class doesn't want a group determine if
1152 we have a nongroup need or a regular need. We have
1153 a nongroup need if this reload conflicts with a
1154 group reload whose class intersects with this reload's
1159 for (j = 0; j < n_reloads; j++)
1160 if ((CLASS_MAX_NREGS (reload_reg_class[j],
1161 (GET_MODE_SIZE (reload_outmode[j])
1162 > GET_MODE_SIZE (reload_inmode[j]))
1166 && reloads_conflict (i, j)
1167 && reg_classes_intersect_p (class,
1168 reload_reg_class[j]))
1174 /* Decide which time-of-use to count this reload for. */
1175 switch (reload_when_needed[i])
1179 this_needs = insn_nongroups;
1181 this_needs = insn_needs;
1182 this_groups = insn_groups;
1183 this_total_groups = &insn_total_groups;
1186 case RELOAD_FOR_INPUT:
1188 this_needs = insn_nongroups_for_inputs;
1190 this_needs = insn_needs_for_inputs;
1191 this_groups = insn_groups_for_inputs;
1192 this_total_groups = &insn_total_groups_for_inputs;
1195 case RELOAD_FOR_OUTPUT:
1197 this_needs = insn_nongroups_for_outputs;
1199 this_needs = insn_needs_for_outputs;
1200 this_groups = insn_groups_for_outputs;
1201 this_total_groups = &insn_total_groups_for_outputs;
1204 case RELOAD_FOR_INSN:
1206 this_needs = insn_nongroups_for_insn;
1208 this_needs = insn_needs_for_insn;
1209 this_groups = insn_groups_for_insn;
1210 this_total_groups = &insn_total_groups_for_insn;
1213 case RELOAD_FOR_OTHER_ADDRESS:
1215 this_needs = insn_nongroups_for_other_addr;
1217 this_needs = insn_needs_for_other_addr;
1218 this_groups = insn_groups_for_other_addr;
1219 this_total_groups = &insn_total_groups_for_other_addr;
1222 case RELOAD_FOR_INPUT_ADDRESS:
1224 this_needs = insn_nongroups_for_in_addr[reload_opnum[i]];
1226 this_needs = insn_needs_for_in_addr[reload_opnum[i]];
1227 this_groups = insn_groups_for_in_addr[reload_opnum[i]];
1229 = &insn_total_groups_for_in_addr[reload_opnum[i]];
1232 case RELOAD_FOR_OUTPUT_ADDRESS:
1234 this_needs = insn_nongroups_for_out_addr[reload_opnum[i]];
1236 this_needs = insn_needs_for_out_addr[reload_opnum[i]];
1237 this_groups = insn_groups_for_out_addr[reload_opnum[i]];
1239 = &insn_total_groups_for_out_addr[reload_opnum[i]];
1242 case RELOAD_FOR_OPERAND_ADDRESS:
1244 this_needs = insn_nongroups_for_op_addr;
1246 this_needs = insn_needs_for_op_addr;
1247 this_groups = insn_groups_for_op_addr;
1248 this_total_groups = &insn_total_groups_for_op_addr;
1254 enum machine_mode other_mode, allocate_mode;
1256 /* Count number of groups needed separately from
1257 number of individual regs needed. */
1258 this_groups[(int) class]++;
1259 p = reg_class_superclasses[(int) class];
1260 while (*p != LIM_REG_CLASSES)
1261 this_groups[(int) *p++]++;
1262 (*this_total_groups)++;
1264 /* Record size and mode of a group of this class. */
1265 /* If more than one size group is needed,
1266 make all groups the largest needed size. */
1267 if (group_size[(int) class] < size)
1269 other_mode = group_mode[(int) class];
1270 allocate_mode = mode;
1272 group_size[(int) class] = size;
1273 group_mode[(int) class] = mode;
1278 allocate_mode = group_mode[(int) class];
1281 /* Crash if two dissimilar machine modes both need
1282 groups of consecutive regs of the same class. */
1284 if (other_mode != VOIDmode
1285 && other_mode != allocate_mode
1286 && ! modes_equiv_for_class_p (allocate_mode,
1293 this_needs[(int) class] += 1;
1294 p = reg_class_superclasses[(int) class];
1295 while (*p != LIM_REG_CLASSES)
1296 this_needs[(int) *p++] += 1;
1302 /* All reloads have been counted for this insn;
1303 now merge the various times of use.
1304 This sets insn_needs, etc., to the maximum total number
1305 of registers needed at any point in this insn. */
1307 for (i = 0; i < N_REG_CLASSES; i++)
1309 int in_max, out_max;
1311 for (in_max = 0, out_max = 0, j = 0;
1312 j < reload_n_operands; j++)
1314 in_max = MAX (in_max, insn_needs_for_in_addr[j][i]);
1315 out_max = MAX (out_max, insn_needs_for_out_addr[j][i]);
1318 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1319 and operand addresses but not things used to reload them.
1320 Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads don't
1321 conflict with things needed to reload inputs or
1324 in_max = MAX (in_max, insn_needs_for_op_addr[i]);
1325 out_max = MAX (out_max, insn_needs_for_insn[i]);
1327 insn_needs_for_inputs[i]
1328 = MAX (insn_needs_for_inputs[i]
1329 + insn_needs_for_op_addr[i]
1330 + insn_needs_for_insn[i],
1331 in_max + insn_needs_for_inputs[i]);
1333 insn_needs_for_outputs[i] += out_max;
1334 insn_needs[i] += MAX (MAX (insn_needs_for_inputs[i],
1335 insn_needs_for_outputs[i]),
1336 insn_needs_for_other_addr[i]);
1338 for (in_max = 0, out_max = 0, j = 0;
1339 j < reload_n_operands; j++)
1341 in_max = MAX (in_max, insn_nongroups_for_in_addr[j][i]);
1342 out_max = MAX (out_max, insn_nongroups_for_out_addr[j][i]);
1345 in_max = MAX (in_max, insn_nongroups_for_op_addr[i]);
1346 out_max = MAX (out_max, insn_nongroups_for_insn[i]);
1348 insn_nongroups_for_inputs[i]
1349 = MAX (insn_nongroups_for_inputs[i]
1350 + insn_nongroups_for_op_addr[i]
1351 + insn_nongroups_for_insn[i],
1352 in_max + insn_nongroups_for_inputs[i]);
1354 insn_nongroups_for_outputs[i] += out_max;
1355 insn_nongroups[i] += MAX (MAX (insn_nongroups_for_inputs[i],
1356 insn_nongroups_for_outputs[i]),
1357 insn_nongroups_for_other_addr[i]);
1359 for (in_max = 0, out_max = 0, j = 0;
1360 j < reload_n_operands; j++)
1362 in_max = MAX (in_max, insn_groups_for_in_addr[j][i]);
1363 out_max = MAX (out_max, insn_groups_for_out_addr[j][i]);
1366 in_max = MAX (in_max, insn_groups_for_op_addr[i]);
1367 out_max = MAX (out_max, insn_groups_for_insn[i]);
1369 insn_groups_for_inputs[i]
1370 = MAX (insn_groups_for_inputs[i]
1371 + insn_groups_for_op_addr[i]
1372 + insn_groups_for_insn[i],
1373 in_max + insn_groups_for_inputs[i]);
1375 insn_groups_for_outputs[i] += out_max;
1376 insn_groups[i] += MAX (MAX (insn_groups_for_inputs[i],
1377 insn_groups_for_outputs[i]),
1378 insn_groups_for_other_addr[i]);
1381 for (i = 0; i < reload_n_operands; i++)
1383 max_total_input_groups
1384 = MAX (max_total_input_groups,
1385 insn_total_groups_for_in_addr[i]);
1386 max_total_output_groups
1387 = MAX (max_total_output_groups,
1388 insn_total_groups_for_out_addr[i]);
1391 max_total_input_groups = MAX (max_total_input_groups,
1392 insn_total_groups_for_op_addr);
1393 max_total_output_groups = MAX (max_total_output_groups,
1394 insn_total_groups_for_insn);
1396 insn_total_groups_for_inputs
1397 = MAX (max_total_input_groups + insn_total_groups_for_op_addr
1398 + insn_total_groups_for_insn,
1399 max_total_input_groups + insn_total_groups_for_inputs);
1401 insn_total_groups_for_outputs += max_total_output_groups;
1403 insn_total_groups += MAX (MAX (insn_total_groups_for_outputs,
1404 insn_total_groups_for_inputs),
1405 insn_total_groups_for_other_addr);
1407 /* If this is a CALL_INSN and caller-saves will need
1408 a spill register, act as if the spill register is
1409 needed for this insn. However, the spill register
1410 can be used by any reload of this insn, so we only
1411 need do something if no need for that class has
1414 The assumption that every CALL_INSN will trigger a
1415 caller-save is highly conservative, however, the number
1416 of cases where caller-saves will need a spill register but
1417 a block containing a CALL_INSN won't need a spill register
1418 of that class should be quite rare.
1420 If a group is needed, the size and mode of the group will
1421 have been set up at the beginning of this loop. */
1423 if (GET_CODE (insn) == CALL_INSN
1424 && caller_save_spill_class != NO_REGS)
1426 int *caller_save_needs
1427 = (caller_save_group_size > 1 ? insn_groups : insn_needs);
1429 if (caller_save_needs[(int) caller_save_spill_class] == 0)
1431 register enum reg_class *p
1432 = reg_class_superclasses[(int) caller_save_spill_class];
1434 caller_save_needs[(int) caller_save_spill_class]++;
1436 while (*p != LIM_REG_CLASSES)
1437 caller_save_needs[(int) *p++] += 1;
1440 if (caller_save_group_size > 1)
1441 insn_total_groups = MAX (insn_total_groups, 1);
1444 /* Show that this basic block will need a register of
1448 && ! (basic_block_needs[(int) caller_save_spill_class]
1451 basic_block_needs[(int) caller_save_spill_class]
1453 new_basic_block_needs = 1;
1457 #ifdef SMALL_REGISTER_CLASSES
1458 /* If this insn stores the value of a function call,
1459 and that value is in a register that has been spilled,
1460 and if the insn needs a reload in a class
1461 that might use that register as the reload register,
1462 then add add an extra need in that class.
1463 This makes sure we have a register available that does
1464 not overlap the return value. */
1465 if (avoid_return_reg)
1467 int regno = REGNO (avoid_return_reg);
1469 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
1471 int basic_needs[N_REG_CLASSES], basic_groups[N_REG_CLASSES];
1473 /* First compute the "basic needs", which counts a
1474 need only in the smallest class in which it
1477 bcopy (insn_needs, basic_needs, sizeof basic_needs);
1478 bcopy (insn_groups, basic_groups, sizeof basic_groups);
1480 for (i = 0; i < N_REG_CLASSES; i++)
1484 if (basic_needs[i] >= 0)
1485 for (p = reg_class_superclasses[i];
1486 *p != LIM_REG_CLASSES; p++)
1487 basic_needs[(int) *p] -= basic_needs[i];
1489 if (basic_groups[i] >= 0)
1490 for (p = reg_class_superclasses[i];
1491 *p != LIM_REG_CLASSES; p++)
1492 basic_groups[(int) *p] -= basic_groups[i];
1495 /* Now count extra regs if there might be a conflict with
1496 the return value register.
1498 ??? This is not quite correct because we don't properly
1499 handle the case of groups, but if we end up doing
1500 something wrong, it either will end up not mattering or
1501 we will abort elsewhere. */
1503 for (r = regno; r < regno + nregs; r++)
1504 if (spill_reg_order[r] >= 0)
1505 for (i = 0; i < N_REG_CLASSES; i++)
1506 if (TEST_HARD_REG_BIT (reg_class_contents[i], r))
1508 if (basic_needs[i] > 0 || basic_groups[i] > 0)
1513 p = reg_class_superclasses[i];
1514 while (*p != LIM_REG_CLASSES)
1515 insn_needs[(int) *p++]++;
1519 #endif /* SMALL_REGISTER_CLASSES */
1521 /* For each class, collect maximum need of any insn. */
1523 for (i = 0; i < N_REG_CLASSES; i++)
1525 if (max_needs[i] < insn_needs[i])
1527 max_needs[i] = insn_needs[i];
1528 max_needs_insn[i] = insn;
1530 if (max_groups[i] < insn_groups[i])
1532 max_groups[i] = insn_groups[i];
1533 max_groups_insn[i] = insn;
1535 if (max_nongroups[i] < insn_nongroups[i])
1537 max_nongroups[i] = insn_nongroups[i];
1538 max_nongroups_insn[i] = insn;
1542 /* Note that there is a continue statement above. */
1545 /* If we allocated any new memory locations, make another pass
1546 since it might have changed elimination offsets. */
1547 if (starting_frame_size != get_frame_size ())
1548 something_changed = 1;
1551 for (i = 0; i < N_REG_CLASSES; i++)
1553 if (max_needs[i] > 0)
1555 ";; Need %d reg%s of class %s (for insn %d).\n",
1556 max_needs[i], max_needs[i] == 1 ? "" : "s",
1557 reg_class_names[i], INSN_UID (max_needs_insn[i]));
1558 if (max_nongroups[i] > 0)
1560 ";; Need %d nongroup reg%s of class %s (for insn %d).\n",
1561 max_nongroups[i], max_nongroups[i] == 1 ? "" : "s",
1562 reg_class_names[i], INSN_UID (max_nongroups_insn[i]));
1563 if (max_groups[i] > 0)
1565 ";; Need %d group%s (%smode) of class %s (for insn %d).\n",
1566 max_groups[i], max_groups[i] == 1 ? "" : "s",
1567 mode_name[(int) group_mode[i]],
1568 reg_class_names[i], INSN_UID (max_groups_insn[i]));
1571 /* If we have caller-saves, set up the save areas and see if caller-save
1572 will need a spill register. */
1574 if (caller_save_needed
1575 && ! setup_save_areas (&something_changed)
1576 && caller_save_spill_class == NO_REGS)
1578 /* The class we will need depends on whether the machine
1579 supports the sum of two registers for an address; see
1580 find_address_reloads for details. */
1582 caller_save_spill_class
1583 = double_reg_address_ok ? INDEX_REG_CLASS : BASE_REG_CLASS;
1584 caller_save_group_size
1585 = CLASS_MAX_NREGS (caller_save_spill_class, Pmode);
1586 something_changed = 1;
1589 /* See if anything that happened changes which eliminations are valid.
1590 For example, on the Sparc, whether or not the frame pointer can
1591 be eliminated can depend on what registers have been used. We need
1592 not check some conditions again (such as flag_omit_frame_pointer)
1593 since they can't have changed. */
1595 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1596 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
1597 #ifdef ELIMINABLE_REGS
1598 || ! CAN_ELIMINATE (ep->from, ep->to)
1601 ep->can_eliminate = 0;
1603 /* Look for the case where we have discovered that we can't replace
1604 register A with register B and that means that we will now be
1605 trying to replace register A with register C. This means we can
1606 no longer replace register C with register B and we need to disable
1607 such an elimination, if it exists. This occurs often with A == ap,
1608 B == sp, and C == fp. */
1610 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1612 struct elim_table *op;
1613 register int new_to = -1;
1615 if (! ep->can_eliminate && ep->can_eliminate_previous)
1617 /* Find the current elimination for ep->from, if there is a
1619 for (op = reg_eliminate;
1620 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1621 if (op->from == ep->from && op->can_eliminate)
1627 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
1629 for (op = reg_eliminate;
1630 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1631 if (op->from == new_to && op->to == ep->to)
1632 op->can_eliminate = 0;
1636 /* See if any registers that we thought we could eliminate the previous
1637 time are no longer eliminable. If so, something has changed and we
1638 must spill the register. Also, recompute the number of eliminable
1639 registers and see if the frame pointer is needed; it is if there is
1640 no elimination of the frame pointer that we can perform. */
1642 frame_pointer_needed = 1;
1643 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1645 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
1646 && ep->to != HARD_FRAME_POINTER_REGNUM)
1647 frame_pointer_needed = 0;
1649 if (! ep->can_eliminate && ep->can_eliminate_previous)
1651 ep->can_eliminate_previous = 0;
1652 spill_hard_reg (ep->from, global, dumpfile, 1);
1653 regs_ever_live[ep->from] = 1;
1654 something_changed = 1;
1659 /* If all needs are met, we win. */
1661 for (i = 0; i < N_REG_CLASSES; i++)
1662 if (max_needs[i] > 0 || max_groups[i] > 0 || max_nongroups[i] > 0)
1664 if (i == N_REG_CLASSES && !new_basic_block_needs && ! something_changed)
1667 /* Not all needs are met; must spill some hard regs. */
1669 /* Put all registers spilled so far back in potential_reload_regs, but
1670 put them at the front, since we've already spilled most of the
1671 psuedos in them (we might have left some pseudos unspilled if they
1672 were in a block that didn't need any spill registers of a conflicting
1673 class. We used to try to mark off the need for those registers,
1674 but doing so properly is very complex and reallocating them is the
1675 simpler approach. First, "pack" potential_reload_regs by pushing
1676 any nonnegative entries towards the end. That will leave room
1677 for the registers we already spilled.
1679 Also, undo the marking of the spill registers from the last time
1680 around in FORBIDDEN_REGS since we will be probably be allocating
1683 ??? It is theoretically possible that we might end up not using one
1684 of our previously-spilled registers in this allocation, even though
1685 they are at the head of the list. It's not clear what to do about
1686 this, but it was no better before, when we marked off the needs met
1687 by the previously-spilled registers. With the current code, globals
1688 can be allocated into these registers, but locals cannot. */
1692 for (i = j = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
1693 if (potential_reload_regs[i] != -1)
1694 potential_reload_regs[j--] = potential_reload_regs[i];
1696 for (i = 0; i < n_spills; i++)
1698 potential_reload_regs[i] = spill_regs[i];
1699 spill_reg_order[spill_regs[i]] = -1;
1700 CLEAR_HARD_REG_BIT (forbidden_regs, spill_regs[i]);
1706 /* Now find more reload regs to satisfy the remaining need
1707 Do it by ascending class number, since otherwise a reg
1708 might be spilled for a big class and might fail to count
1709 for a smaller class even though it belongs to that class.
1711 Count spilled regs in `spills', and add entries to
1712 `spill_regs' and `spill_reg_order'.
1714 ??? Note there is a problem here.
1715 When there is a need for a group in a high-numbered class,
1716 and also need for non-group regs that come from a lower class,
1717 the non-group regs are chosen first. If there aren't many regs,
1718 they might leave no room for a group.
1720 This was happening on the 386. To fix it, we added the code
1721 that calls possible_group_p, so that the lower class won't
1722 break up the last possible group.
1724 Really fixing the problem would require changes above
1725 in counting the regs already spilled, and in choose_reload_regs.
1726 It might be hard to avoid introducing bugs there. */
1728 CLEAR_HARD_REG_SET (counted_for_groups);
1729 CLEAR_HARD_REG_SET (counted_for_nongroups);
1731 for (class = 0; class < N_REG_CLASSES; class++)
1733 /* First get the groups of registers.
1734 If we got single registers first, we might fragment
1736 while (max_groups[class] > 0)
1738 /* If any single spilled regs happen to form groups,
1739 count them now. Maybe we don't really need
1740 to spill another group. */
1741 count_possible_groups (group_size, group_mode, max_groups);
1743 if (max_groups[class] <= 0)
1746 /* Groups of size 2 (the only groups used on most machines)
1747 are treated specially. */
1748 if (group_size[class] == 2)
1750 /* First, look for a register that will complete a group. */
1751 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1755 j = potential_reload_regs[i];
1756 if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1758 ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1759 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1760 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1761 && HARD_REGNO_MODE_OK (other, group_mode[class])
1762 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1764 /* We don't want one part of another group.
1765 We could get "two groups" that overlap! */
1766 && ! TEST_HARD_REG_BIT (counted_for_groups, other))
1768 (j < FIRST_PSEUDO_REGISTER - 1
1769 && (other = j + 1, spill_reg_order[other] >= 0)
1770 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1771 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1772 && HARD_REGNO_MODE_OK (j, group_mode[class])
1773 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1775 && ! TEST_HARD_REG_BIT (counted_for_groups,
1778 register enum reg_class *p;
1780 /* We have found one that will complete a group,
1781 so count off one group as provided. */
1782 max_groups[class]--;
1783 p = reg_class_superclasses[class];
1784 while (*p != LIM_REG_CLASSES)
1785 max_groups[(int) *p++]--;
1787 /* Indicate both these regs are part of a group. */
1788 SET_HARD_REG_BIT (counted_for_groups, j);
1789 SET_HARD_REG_BIT (counted_for_groups, other);
1793 /* We can't complete a group, so start one. */
1794 #ifdef SMALL_REGISTER_CLASSES
1795 /* Look for a pair neither of which is explicitly used. */
1796 if (i == FIRST_PSEUDO_REGISTER)
1797 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1800 j = potential_reload_regs[i];
1801 /* Verify that J+1 is a potential reload reg. */
1802 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1803 if (potential_reload_regs[k] == j + 1)
1805 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1806 && k < FIRST_PSEUDO_REGISTER
1807 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1808 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1809 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1810 && HARD_REGNO_MODE_OK (j, group_mode[class])
1811 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1813 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1)
1814 /* Reject J at this stage
1815 if J+1 was explicitly used. */
1816 && ! regs_explicitly_used[j + 1])
1820 /* Now try any group at all
1821 whose registers are not in bad_spill_regs. */
1822 if (i == FIRST_PSEUDO_REGISTER)
1823 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1826 j = potential_reload_regs[i];
1827 /* Verify that J+1 is a potential reload reg. */
1828 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1829 if (potential_reload_regs[k] == j + 1)
1831 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1832 && k < FIRST_PSEUDO_REGISTER
1833 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1834 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1835 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1836 && HARD_REGNO_MODE_OK (j, group_mode[class])
1837 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1839 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1))
1843 /* I should be the index in potential_reload_regs
1844 of the new reload reg we have found. */
1846 if (i >= FIRST_PSEUDO_REGISTER)
1848 /* There are no groups left to spill. */
1849 spill_failure (max_groups_insn[class]);
1855 |= new_spill_reg (i, class, max_needs, NULL_PTR,
1860 /* For groups of more than 2 registers,
1861 look for a sufficient sequence of unspilled registers,
1862 and spill them all at once. */
1863 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1867 j = potential_reload_regs[i];
1869 && j + group_size[class] <= FIRST_PSEUDO_REGISTER
1870 && HARD_REGNO_MODE_OK (j, group_mode[class]))
1872 /* Check each reg in the sequence. */
1873 for (k = 0; k < group_size[class]; k++)
1874 if (! (spill_reg_order[j + k] < 0
1875 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1876 && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1878 /* We got a full sequence, so spill them all. */
1879 if (k == group_size[class])
1881 register enum reg_class *p;
1882 for (k = 0; k < group_size[class]; k++)
1885 SET_HARD_REG_BIT (counted_for_groups, j + k);
1886 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1887 if (potential_reload_regs[idx] == j + k)
1890 |= new_spill_reg (idx, class,
1891 max_needs, NULL_PTR,
1895 /* We have found one that will complete a group,
1896 so count off one group as provided. */
1897 max_groups[class]--;
1898 p = reg_class_superclasses[class];
1899 while (*p != LIM_REG_CLASSES)
1900 max_groups[(int) *p++]--;
1906 /* We couldn't find any registers for this reload.
1907 Avoid going into an infinite loop. */
1908 if (i >= FIRST_PSEUDO_REGISTER)
1910 /* There are no groups left. */
1911 spill_failure (max_groups_insn[class]);
1918 /* Now similarly satisfy all need for single registers. */
1920 while (max_needs[class] > 0 || max_nongroups[class] > 0)
1922 #ifdef SMALL_REGISTER_CLASSES
1923 /* This should be right for all machines, but only the 386
1924 is known to need it, so this conditional plays safe.
1925 ??? For 2.5, try making this unconditional. */
1926 /* If we spilled enough regs, but they weren't counted
1927 against the non-group need, see if we can count them now.
1928 If so, we can avoid some actual spilling. */
1929 if (max_needs[class] <= 0 && max_nongroups[class] > 0)
1930 for (i = 0; i < n_spills; i++)
1931 if (TEST_HARD_REG_BIT (reg_class_contents[class],
1933 && !TEST_HARD_REG_BIT (counted_for_groups,
1935 && !TEST_HARD_REG_BIT (counted_for_nongroups,
1937 && max_nongroups[class] > 0)
1939 register enum reg_class *p;
1941 SET_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]);
1942 max_nongroups[class]--;
1943 p = reg_class_superclasses[class];
1944 while (*p != LIM_REG_CLASSES)
1945 max_nongroups[(int) *p++]--;
1947 if (max_needs[class] <= 0 && max_nongroups[class] <= 0)
1951 /* Consider the potential reload regs that aren't
1952 yet in use as reload regs, in order of preference.
1953 Find the most preferred one that's in this class. */
1955 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1956 if (potential_reload_regs[i] >= 0
1957 && TEST_HARD_REG_BIT (reg_class_contents[class],
1958 potential_reload_regs[i])
1959 /* If this reg will not be available for groups,
1960 pick one that does not foreclose possible groups.
1961 This is a kludge, and not very general,
1962 but it should be sufficient to make the 386 work,
1963 and the problem should not occur on machines with
1965 && (max_nongroups[class] == 0
1966 || possible_group_p (potential_reload_regs[i], max_groups)))
1969 /* If we couldn't get a register, try to get one even if we
1970 might foreclose possible groups. This may cause problems
1971 later, but that's better than aborting now, since it is
1972 possible that we will, in fact, be able to form the needed
1973 group even with this allocation. */
1975 if (i >= FIRST_PSEUDO_REGISTER
1976 && (asm_noperands (max_needs[class] > 0
1977 ? max_needs_insn[class]
1978 : max_nongroups_insn[class])
1980 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1981 if (potential_reload_regs[i] >= 0
1982 && TEST_HARD_REG_BIT (reg_class_contents[class],
1983 potential_reload_regs[i]))
1986 /* I should be the index in potential_reload_regs
1987 of the new reload reg we have found. */
1989 if (i >= FIRST_PSEUDO_REGISTER)
1991 /* There are no possible registers left to spill. */
1992 spill_failure (max_needs[class] > 0 ? max_needs_insn[class]
1993 : max_nongroups_insn[class]);
1999 |= new_spill_reg (i, class, max_needs, max_nongroups,
2005 /* If global-alloc was run, notify it of any register eliminations we have
2008 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2009 if (ep->can_eliminate)
2010 mark_elimination (ep->from, ep->to);
2012 /* Insert code to save and restore call-clobbered hard regs
2013 around calls. Tell if what mode to use so that we will process
2014 those insns in reload_as_needed if we have to. */
2016 if (caller_save_needed)
2017 save_call_clobbered_regs (num_eliminable ? QImode
2018 : caller_save_spill_class != NO_REGS ? HImode
2021 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
2022 If that insn didn't set the register (i.e., it copied the register to
2023 memory), just delete that insn instead of the equivalencing insn plus
2024 anything now dead. If we call delete_dead_insn on that insn, we may
2025 delete the insn that actually sets the register if the register die
2026 there and that is incorrect. */
2028 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2029 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0
2030 && GET_CODE (reg_equiv_init[i]) != NOTE)
2032 if (reg_set_p (regno_reg_rtx[i], PATTERN (reg_equiv_init[i])))
2033 delete_dead_insn (reg_equiv_init[i]);
2036 PUT_CODE (reg_equiv_init[i], NOTE);
2037 NOTE_SOURCE_FILE (reg_equiv_init[i]) = 0;
2038 NOTE_LINE_NUMBER (reg_equiv_init[i]) = NOTE_INSN_DELETED;
2042 /* Use the reload registers where necessary
2043 by generating move instructions to move the must-be-register
2044 values into or out of the reload registers. */
2046 if (something_needs_reloads || something_needs_elimination
2047 || (caller_save_needed && num_eliminable)
2048 || caller_save_spill_class != NO_REGS)
2049 reload_as_needed (first, global);
2051 /* If we were able to eliminate the frame pointer, show that it is no
2052 longer live at the start of any basic block. If it ls live by
2053 virtue of being in a pseudo, that pseudo will be marked live
2054 and hence the frame pointer will be known to be live via that
2057 if (! frame_pointer_needed)
2058 for (i = 0; i < n_basic_blocks; i++)
2059 basic_block_live_at_start[i][HARD_FRAME_POINTER_REGNUM / REGSET_ELT_BITS]
2060 &= ~ ((REGSET_ELT_TYPE) 1 << (HARD_FRAME_POINTER_REGNUM
2061 % REGSET_ELT_BITS));
2063 /* Come here (with failure set nonzero) if we can't get enough spill regs
2064 and we decide not to abort about it. */
2067 reload_in_progress = 0;
2069 /* Now eliminate all pseudo regs by modifying them into
2070 their equivalent memory references.
2071 The REG-rtx's for the pseudos are modified in place,
2072 so all insns that used to refer to them now refer to memory.
2074 For a reg that has a reg_equiv_address, all those insns
2075 were changed by reloading so that no insns refer to it any longer;
2076 but the DECL_RTL of a variable decl may refer to it,
2077 and if so this causes the debugging info to mention the variable. */
2079 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2083 if (reg_equiv_mem[i])
2085 addr = XEXP (reg_equiv_mem[i], 0);
2086 in_struct = MEM_IN_STRUCT_P (reg_equiv_mem[i]);
2088 if (reg_equiv_address[i])
2089 addr = reg_equiv_address[i];
2092 if (reg_renumber[i] < 0)
2094 rtx reg = regno_reg_rtx[i];
2095 XEXP (reg, 0) = addr;
2096 REG_USERVAR_P (reg) = 0;
2097 MEM_IN_STRUCT_P (reg) = in_struct;
2098 PUT_CODE (reg, MEM);
2100 else if (reg_equiv_mem[i])
2101 XEXP (reg_equiv_mem[i], 0) = addr;
2105 #ifdef PRESERVE_DEATH_INFO_REGNO_P
2106 /* Make a pass over all the insns and remove death notes for things that
2107 are no longer registers or no longer die in the insn (e.g., an input
2108 and output pseudo being tied). */
2110 for (insn = first; insn; insn = NEXT_INSN (insn))
2111 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
2115 for (note = REG_NOTES (insn); note; note = next)
2117 next = XEXP (note, 1);
2118 if (REG_NOTE_KIND (note) == REG_DEAD
2119 && (GET_CODE (XEXP (note, 0)) != REG
2120 || reg_set_p (XEXP (note, 0), PATTERN (insn))))
2121 remove_note (insn, note);
2126 /* Indicate that we no longer have known memory locations or constants. */
2127 reg_equiv_constant = 0;
2128 reg_equiv_memory_loc = 0;
2131 free (scratch_list);
2134 free (scratch_block);
2140 /* Nonzero if, after spilling reg REGNO for non-groups,
2141 it will still be possible to find a group if we still need one. */
2144 possible_group_p (regno, max_groups)
2149 int class = (int) NO_REGS;
2151 for (i = 0; i < (int) N_REG_CLASSES; i++)
2152 if (max_groups[i] > 0)
2158 if (class == (int) NO_REGS)
2161 /* Consider each pair of consecutive registers. */
2162 for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
2164 /* Ignore pairs that include reg REGNO. */
2165 if (i == regno || i + 1 == regno)
2168 /* Ignore pairs that are outside the class that needs the group.
2169 ??? Here we fail to handle the case where two different classes
2170 independently need groups. But this never happens with our
2171 current machine descriptions. */
2172 if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
2173 && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
2176 /* A pair of consecutive regs we can still spill does the trick. */
2177 if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
2178 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2179 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
2182 /* A pair of one already spilled and one we can spill does it
2183 provided the one already spilled is not otherwise reserved. */
2184 if (spill_reg_order[i] < 0
2185 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2186 && spill_reg_order[i + 1] >= 0
2187 && ! TEST_HARD_REG_BIT (counted_for_groups, i + 1)
2188 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i + 1))
2190 if (spill_reg_order[i + 1] < 0
2191 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
2192 && spill_reg_order[i] >= 0
2193 && ! TEST_HARD_REG_BIT (counted_for_groups, i)
2194 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i))
2201 /* Count any groups that can be formed from the registers recently spilled.
2202 This is done class by class, in order of ascending class number. */
2205 count_possible_groups (group_size, group_mode, max_groups)
2207 enum machine_mode *group_mode;
2211 /* Now find all consecutive groups of spilled registers
2212 and mark each group off against the need for such groups.
2213 But don't count them against ordinary need, yet. */
2215 for (i = 0; i < N_REG_CLASSES; i++)
2216 if (group_size[i] > 1)
2221 CLEAR_HARD_REG_SET (new);
2223 /* Make a mask of all the regs that are spill regs in class I. */
2224 for (j = 0; j < n_spills; j++)
2225 if (TEST_HARD_REG_BIT (reg_class_contents[i], spill_regs[j])
2226 && ! TEST_HARD_REG_BIT (counted_for_groups, spill_regs[j])
2227 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
2229 SET_HARD_REG_BIT (new, spill_regs[j]);
2231 /* Find each consecutive group of them. */
2232 for (j = 0; j < FIRST_PSEUDO_REGISTER && max_groups[i] > 0; j++)
2233 if (TEST_HARD_REG_BIT (new, j)
2234 && j + group_size[i] <= FIRST_PSEUDO_REGISTER
2235 /* Next line in case group-mode for this class
2236 demands an even-odd pair. */
2237 && HARD_REGNO_MODE_OK (j, group_mode[i]))
2240 for (k = 1; k < group_size[i]; k++)
2241 if (! TEST_HARD_REG_BIT (new, j + k))
2243 if (k == group_size[i])
2245 /* We found a group. Mark it off against this class's
2246 need for groups, and against each superclass too. */
2247 register enum reg_class *p;
2249 p = reg_class_superclasses[i];
2250 while (*p != LIM_REG_CLASSES)
2251 max_groups[(int) *p++]--;
2252 /* Don't count these registers again. */
2253 for (k = 0; k < group_size[i]; k++)
2254 SET_HARD_REG_BIT (counted_for_groups, j + k);
2256 /* Skip to the last reg in this group. When j is incremented
2257 above, it will then point to the first reg of the next
2265 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2266 another mode that needs to be reloaded for the same register class CLASS.
2267 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2268 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2270 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2271 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2272 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2273 causes unnecessary failures on machines requiring alignment of register
2274 groups when the two modes are different sizes, because the larger mode has
2275 more strict alignment rules than the smaller mode. */
2278 modes_equiv_for_class_p (allocate_mode, other_mode, class)
2279 enum machine_mode allocate_mode, other_mode;
2280 enum reg_class class;
2283 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2285 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
2286 && HARD_REGNO_MODE_OK (regno, allocate_mode)
2287 && ! HARD_REGNO_MODE_OK (regno, other_mode))
2293 /* Handle the failure to find a register to spill.
2294 INSN should be one of the insns which needed this particular spill reg. */
2297 spill_failure (insn)
2300 if (asm_noperands (PATTERN (insn)) >= 0)
2301 error_for_asm (insn, "`asm' needs too many reloads");
2306 /* Add a new register to the tables of available spill-registers
2307 (as well as spilling all pseudos allocated to the register).
2308 I is the index of this register in potential_reload_regs.
2309 CLASS is the regclass whose need is being satisfied.
2310 MAX_NEEDS and MAX_NONGROUPS are the vectors of needs,
2311 so that this register can count off against them.
2312 MAX_NONGROUPS is 0 if this register is part of a group.
2313 GLOBAL and DUMPFILE are the same as the args that `reload' got. */
2316 new_spill_reg (i, class, max_needs, max_nongroups, global, dumpfile)
2324 register enum reg_class *p;
2326 int regno = potential_reload_regs[i];
2328 if (i >= FIRST_PSEUDO_REGISTER)
2329 abort (); /* Caller failed to find any register. */
2331 if (fixed_regs[regno] || TEST_HARD_REG_BIT (forbidden_regs, regno))
2332 fatal ("fixed or forbidden register was spilled.\n\
2333 This may be due to a compiler bug or to impossible asm statements.");
2335 /* Make reg REGNO an additional reload reg. */
2337 potential_reload_regs[i] = -1;
2338 spill_regs[n_spills] = regno;
2339 spill_reg_order[regno] = n_spills;
2341 fprintf (dumpfile, "Spilling reg %d.\n", spill_regs[n_spills]);
2343 /* Clear off the needs we just satisfied. */
2346 p = reg_class_superclasses[class];
2347 while (*p != LIM_REG_CLASSES)
2348 max_needs[(int) *p++]--;
2350 if (max_nongroups && max_nongroups[class] > 0)
2352 SET_HARD_REG_BIT (counted_for_nongroups, regno);
2353 max_nongroups[class]--;
2354 p = reg_class_superclasses[class];
2355 while (*p != LIM_REG_CLASSES)
2356 max_nongroups[(int) *p++]--;
2359 /* Spill every pseudo reg that was allocated to this reg
2360 or to something that overlaps this reg. */
2362 val = spill_hard_reg (spill_regs[n_spills], global, dumpfile, 0);
2364 /* If there are some registers still to eliminate and this register
2365 wasn't ever used before, additional stack space may have to be
2366 allocated to store this register. Thus, we may have changed the offset
2367 between the stack and frame pointers, so mark that something has changed.
2368 (If new pseudos were spilled, thus requiring more space, VAL would have
2369 been set non-zero by the call to spill_hard_reg above since additional
2370 reloads may be needed in that case.
2372 One might think that we need only set VAL to 1 if this is a call-used
2373 register. However, the set of registers that must be saved by the
2374 prologue is not identical to the call-used set. For example, the
2375 register used by the call insn for the return PC is a call-used register,
2376 but must be saved by the prologue. */
2377 if (num_eliminable && ! regs_ever_live[spill_regs[n_spills]])
2380 regs_ever_live[spill_regs[n_spills]] = 1;
2386 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2387 data that is dead in INSN. */
2390 delete_dead_insn (insn)
2393 rtx prev = prev_real_insn (insn);
2396 /* If the previous insn sets a register that dies in our insn, delete it
2398 if (prev && GET_CODE (PATTERN (prev)) == SET
2399 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
2400 && reg_mentioned_p (prev_dest, PATTERN (insn))
2401 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)))
2402 delete_dead_insn (prev);
2404 PUT_CODE (insn, NOTE);
2405 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2406 NOTE_SOURCE_FILE (insn) = 0;
2409 /* Modify the home of pseudo-reg I.
2410 The new home is present in reg_renumber[I].
2412 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2413 or it may be -1, meaning there is none or it is not relevant.
2414 This is used so that all pseudos spilled from a given hard reg
2415 can share one stack slot. */
2418 alter_reg (i, from_reg)
2422 /* When outputting an inline function, this can happen
2423 for a reg that isn't actually used. */
2424 if (regno_reg_rtx[i] == 0)
2427 /* If the reg got changed to a MEM at rtl-generation time,
2429 if (GET_CODE (regno_reg_rtx[i]) != REG)
2432 /* Modify the reg-rtx to contain the new hard reg
2433 number or else to contain its pseudo reg number. */
2434 REGNO (regno_reg_rtx[i])
2435 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2437 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2438 allocate a stack slot for it. */
2440 if (reg_renumber[i] < 0
2441 && reg_n_refs[i] > 0
2442 && reg_equiv_constant[i] == 0
2443 && reg_equiv_memory_loc[i] == 0)
2446 int inherent_size = PSEUDO_REGNO_BYTES (i);
2447 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2450 /* Each pseudo reg has an inherent size which comes from its own mode,
2451 and a total size which provides room for paradoxical subregs
2452 which refer to the pseudo reg in wider modes.
2454 We can use a slot already allocated if it provides both
2455 enough inherent space and enough total space.
2456 Otherwise, we allocate a new slot, making sure that it has no less
2457 inherent space, and no less total space, then the previous slot. */
2460 /* No known place to spill from => no slot to reuse. */
2461 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size, -1);
2462 #if BYTES_BIG_ENDIAN
2463 /* Cancel the big-endian correction done in assign_stack_local.
2464 Get the address of the beginning of the slot.
2465 This is so we can do a big-endian correction unconditionally
2467 adjust = inherent_size - total_size;
2470 /* Reuse a stack slot if possible. */
2471 else if (spill_stack_slot[from_reg] != 0
2472 && spill_stack_slot_width[from_reg] >= total_size
2473 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2475 x = spill_stack_slot[from_reg];
2476 /* Allocate a bigger slot. */
2479 /* Compute maximum size needed, both for inherent size
2480 and for total size. */
2481 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2482 if (spill_stack_slot[from_reg])
2484 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2486 mode = GET_MODE (spill_stack_slot[from_reg]);
2487 if (spill_stack_slot_width[from_reg] > total_size)
2488 total_size = spill_stack_slot_width[from_reg];
2490 /* Make a slot with that size. */
2491 x = assign_stack_local (mode, total_size, -1);
2492 #if BYTES_BIG_ENDIAN
2493 /* Cancel the big-endian correction done in assign_stack_local.
2494 Get the address of the beginning of the slot.
2495 This is so we can do a big-endian correction unconditionally
2497 adjust = GET_MODE_SIZE (mode) - total_size;
2499 spill_stack_slot[from_reg] = x;
2500 spill_stack_slot_width[from_reg] = total_size;
2503 #if BYTES_BIG_ENDIAN
2504 /* On a big endian machine, the "address" of the slot
2505 is the address of the low part that fits its inherent mode. */
2506 if (inherent_size < total_size)
2507 adjust += (total_size - inherent_size);
2508 #endif /* BYTES_BIG_ENDIAN */
2510 /* If we have any adjustment to make, or if the stack slot is the
2511 wrong mode, make a new stack slot. */
2512 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2514 x = gen_rtx (MEM, GET_MODE (regno_reg_rtx[i]),
2515 plus_constant (XEXP (x, 0), adjust));
2516 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2519 /* Save the stack slot for later. */
2520 reg_equiv_memory_loc[i] = x;
2524 /* Mark the slots in regs_ever_live for the hard regs
2525 used by pseudo-reg number REGNO. */
2528 mark_home_live (regno)
2531 register int i, lim;
2532 i = reg_renumber[regno];
2535 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2537 regs_ever_live[i++] = 1;
2540 /* Mark the registers used in SCRATCH as being live. */
2543 mark_scratch_live (scratch)
2547 int regno = REGNO (scratch);
2548 int lim = regno + HARD_REGNO_NREGS (regno, GET_MODE (scratch));
2550 for (i = regno; i < lim; i++)
2551 regs_ever_live[i] = 1;
2554 /* This function handles the tracking of elimination offsets around branches.
2556 X is a piece of RTL being scanned.
2558 INSN is the insn that it came from, if any.
2560 INITIAL_P is non-zero if we are to set the offset to be the initial
2561 offset and zero if we are setting the offset of the label to be the
2565 set_label_offsets (x, insn, initial_p)
2570 enum rtx_code code = GET_CODE (x);
2573 struct elim_table *p;
2578 if (LABEL_REF_NONLOCAL_P (x))
2583 /* ... fall through ... */
2586 /* If we know nothing about this label, set the desired offsets. Note
2587 that this sets the offset at a label to be the offset before a label
2588 if we don't know anything about the label. This is not correct for
2589 the label after a BARRIER, but is the best guess we can make. If
2590 we guessed wrong, we will suppress an elimination that might have
2591 been possible had we been able to guess correctly. */
2593 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2595 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2596 offsets_at[CODE_LABEL_NUMBER (x)][i]
2597 = (initial_p ? reg_eliminate[i].initial_offset
2598 : reg_eliminate[i].offset);
2599 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2602 /* Otherwise, if this is the definition of a label and it is
2603 preceded by a BARRIER, set our offsets to the known offset of
2607 && (tem = prev_nonnote_insn (insn)) != 0
2608 && GET_CODE (tem) == BARRIER)
2610 num_not_at_initial_offset = 0;
2611 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2613 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
2614 = offsets_at[CODE_LABEL_NUMBER (x)][i];
2615 if (reg_eliminate[i].can_eliminate
2616 && (reg_eliminate[i].offset
2617 != reg_eliminate[i].initial_offset))
2618 num_not_at_initial_offset++;
2623 /* If neither of the above cases is true, compare each offset
2624 with those previously recorded and suppress any eliminations
2625 where the offsets disagree. */
2627 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2628 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2629 != (initial_p ? reg_eliminate[i].initial_offset
2630 : reg_eliminate[i].offset))
2631 reg_eliminate[i].can_eliminate = 0;
2636 set_label_offsets (PATTERN (insn), insn, initial_p);
2638 /* ... fall through ... */
2642 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2643 and hence must have all eliminations at their initial offsets. */
2644 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2645 if (REG_NOTE_KIND (tem) == REG_LABEL)
2646 set_label_offsets (XEXP (tem, 0), insn, 1);
2651 /* Each of the labels in the address vector must be at their initial
2652 offsets. We want the first first for ADDR_VEC and the second
2653 field for ADDR_DIFF_VEC. */
2655 for (i = 0; i < XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2656 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2661 /* We only care about setting PC. If the source is not RETURN,
2662 IF_THEN_ELSE, or a label, disable any eliminations not at
2663 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2664 isn't one of those possibilities. For branches to a label,
2665 call ourselves recursively.
2667 Note that this can disable elimination unnecessarily when we have
2668 a non-local goto since it will look like a non-constant jump to
2669 someplace in the current function. This isn't a significant
2670 problem since such jumps will normally be when all elimination
2671 pairs are back to their initial offsets. */
2673 if (SET_DEST (x) != pc_rtx)
2676 switch (GET_CODE (SET_SRC (x)))
2683 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2687 tem = XEXP (SET_SRC (x), 1);
2688 if (GET_CODE (tem) == LABEL_REF)
2689 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2690 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2693 tem = XEXP (SET_SRC (x), 2);
2694 if (GET_CODE (tem) == LABEL_REF)
2695 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2696 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2701 /* If we reach here, all eliminations must be at their initial
2702 offset because we are doing a jump to a variable address. */
2703 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2704 if (p->offset != p->initial_offset)
2705 p->can_eliminate = 0;
2709 /* Used for communication between the next two function to properly share
2710 the vector for an ASM_OPERANDS. */
2712 static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec;
2714 /* Scan X and replace any eliminable registers (such as fp) with a
2715 replacement (such as sp), plus an offset.
2717 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2718 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2719 MEM, we are allowed to replace a sum of a register and the constant zero
2720 with the register, which we cannot do outside a MEM. In addition, we need
2721 to record the fact that a register is referenced outside a MEM.
2723 If INSN is an insn, it is the insn containing X. If we replace a REG
2724 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2725 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2726 that the REG is being modified.
2728 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2729 That's used when we eliminate in expressions stored in notes.
2730 This means, do not set ref_outside_mem even if the reference
2733 If we see a modification to a register we know about, take the
2734 appropriate action (see case SET, below).
2736 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2737 replacements done assuming all offsets are at their initial values. If
2738 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2739 encounter, return the actual location so that find_reloads will do
2740 the proper thing. */
2743 eliminate_regs (x, mem_mode, insn)
2745 enum machine_mode mem_mode;
2748 enum rtx_code code = GET_CODE (x);
2749 struct elim_table *ep;
2774 /* First handle the case where we encounter a bare register that
2775 is eliminable. Replace it with a PLUS. */
2776 if (regno < FIRST_PSEUDO_REGISTER)
2778 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2780 if (ep->from_rtx == x && ep->can_eliminate)
2783 /* Refs inside notes don't count for this purpose. */
2784 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2785 || GET_CODE (insn) == INSN_LIST)))
2786 ep->ref_outside_mem = 1;
2787 return plus_constant (ep->to_rtx, ep->previous_offset);
2791 else if (reg_equiv_memory_loc && reg_equiv_memory_loc[regno]
2792 && (reg_equiv_address[regno] || num_not_at_initial_offset))
2794 /* In this case, find_reloads would attempt to either use an
2795 incorrect address (if something is not at its initial offset)
2796 or substitute an replaced address into an insn (which loses
2797 if the offset is changed by some later action). So we simply
2798 return the replaced stack slot (assuming it is changed by
2799 elimination) and ignore the fact that this is actually a
2800 reference to the pseudo. Ensure we make a copy of the
2801 address in case it is shared. */
2802 new = eliminate_regs (reg_equiv_memory_loc[regno],
2804 if (new != reg_equiv_memory_loc[regno])
2806 cannot_omit_stores[regno] = 1;
2807 return copy_rtx (new);
2813 /* If this is the sum of an eliminable register and a constant, rework
2815 if (GET_CODE (XEXP (x, 0)) == REG
2816 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2817 && CONSTANT_P (XEXP (x, 1)))
2819 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2821 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2824 /* Refs inside notes don't count for this purpose. */
2825 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2826 || GET_CODE (insn) == INSN_LIST)))
2827 ep->ref_outside_mem = 1;
2829 /* The only time we want to replace a PLUS with a REG (this
2830 occurs when the constant operand of the PLUS is the negative
2831 of the offset) is when we are inside a MEM. We won't want
2832 to do so at other times because that would change the
2833 structure of the insn in a way that reload can't handle.
2834 We special-case the commonest situation in
2835 eliminate_regs_in_insn, so just replace a PLUS with a
2836 PLUS here, unless inside a MEM. */
2837 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2838 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2841 return gen_rtx (PLUS, Pmode, ep->to_rtx,
2842 plus_constant (XEXP (x, 1),
2843 ep->previous_offset));
2846 /* If the register is not eliminable, we are done since the other
2847 operand is a constant. */
2851 /* If this is part of an address, we want to bring any constant to the
2852 outermost PLUS. We will do this by doing register replacement in
2853 our operands and seeing if a constant shows up in one of them.
2855 We assume here this is part of an address (or a "load address" insn)
2856 since an eliminable register is not likely to appear in any other
2859 If we have (plus (eliminable) (reg)), we want to produce
2860 (plus (plus (replacement) (reg) (const))). If this was part of a
2861 normal add insn, (plus (replacement) (reg)) will be pushed as a
2862 reload. This is the desired action. */
2865 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2866 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2868 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2870 /* If one side is a PLUS and the other side is a pseudo that
2871 didn't get a hard register but has a reg_equiv_constant,
2872 we must replace the constant here since it may no longer
2873 be in the position of any operand. */
2874 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2875 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2876 && reg_renumber[REGNO (new1)] < 0
2877 && reg_equiv_constant != 0
2878 && reg_equiv_constant[REGNO (new1)] != 0)
2879 new1 = reg_equiv_constant[REGNO (new1)];
2880 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2881 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2882 && reg_renumber[REGNO (new0)] < 0
2883 && reg_equiv_constant[REGNO (new0)] != 0)
2884 new0 = reg_equiv_constant[REGNO (new0)];
2886 new = form_sum (new0, new1);
2888 /* As above, if we are not inside a MEM we do not want to
2889 turn a PLUS into something else. We might try to do so here
2890 for an addition of 0 if we aren't optimizing. */
2891 if (! mem_mode && GET_CODE (new) != PLUS)
2892 return gen_rtx (PLUS, GET_MODE (x), new, const0_rtx);
2900 /* If this is the product of an eliminable register and a
2901 constant, apply the distribute law and move the constant out
2902 so that we have (plus (mult ..) ..). This is needed in order
2903 to keep load-address insns valid. This case is pathalogical.
2904 We ignore the possibility of overflow here. */
2905 if (GET_CODE (XEXP (x, 0)) == REG
2906 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2907 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2908 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2910 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2913 /* Refs inside notes don't count for this purpose. */
2914 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2915 || GET_CODE (insn) == INSN_LIST)))
2916 ep->ref_outside_mem = 1;
2919 plus_constant (gen_rtx (MULT, Pmode, ep->to_rtx, XEXP (x, 1)),
2920 ep->previous_offset * INTVAL (XEXP (x, 1)));
2923 /* ... fall through ... */
2928 case DIV: case UDIV:
2929 case MOD: case UMOD:
2930 case AND: case IOR: case XOR:
2931 case ROTATERT: case ROTATE:
2932 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2934 case GE: case GT: case GEU: case GTU:
2935 case LE: case LT: case LEU: case LTU:
2937 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2939 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2941 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2942 return gen_rtx (code, GET_MODE (x), new0, new1);
2947 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2950 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2951 if (new != XEXP (x, 0))
2952 x = gen_rtx (EXPR_LIST, REG_NOTE_KIND (x), new, XEXP (x, 1));
2955 /* ... fall through ... */
2958 /* Now do eliminations in the rest of the chain. If this was
2959 an EXPR_LIST, this might result in allocating more memory than is
2960 strictly needed, but it simplifies the code. */
2963 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2964 if (new != XEXP (x, 1))
2965 return gen_rtx (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2973 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2974 if (ep->to_rtx == XEXP (x, 0))
2976 int size = GET_MODE_SIZE (mem_mode);
2978 /* If more bytes than MEM_MODE are pushed, account for them. */
2979 #ifdef PUSH_ROUNDING
2980 if (ep->to_rtx == stack_pointer_rtx)
2981 size = PUSH_ROUNDING (size);
2983 if (code == PRE_DEC || code == POST_DEC)
2989 /* Fall through to generic unary operation case. */
2991 case STRICT_LOW_PART:
2993 case SIGN_EXTEND: case ZERO_EXTEND:
2994 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2995 case FLOAT: case FIX:
2996 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3000 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3001 if (new != XEXP (x, 0))
3002 return gen_rtx (code, GET_MODE (x), new);
3006 /* Similar to above processing, but preserve SUBREG_WORD.
3007 Convert (subreg (mem)) to (mem) if not paradoxical.
3008 Also, if we have a non-paradoxical (subreg (pseudo)) and the
3009 pseudo didn't get a hard reg, we must replace this with the
3010 eliminated version of the memory location because push_reloads
3011 may do the replacement in certain circumstances. */
3012 if (GET_CODE (SUBREG_REG (x)) == REG
3013 && (GET_MODE_SIZE (GET_MODE (x))
3014 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3015 && reg_equiv_memory_loc != 0
3016 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
3018 new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))],
3021 /* If we didn't change anything, we must retain the pseudo. */
3022 if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))])
3025 /* Otherwise, ensure NEW isn't shared in case we have to reload
3027 new = copy_rtx (new);
3030 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
3032 if (new != XEXP (x, 0))
3034 if (GET_CODE (new) == MEM
3035 && (GET_MODE_SIZE (GET_MODE (x))
3036 <= GET_MODE_SIZE (GET_MODE (new)))
3037 #ifdef LOAD_EXTEND_OP
3038 /* On these machines we will be reloading what is
3039 inside the SUBREG if it originally was a pseudo and
3040 the inner and outer modes are both a word or
3041 smaller. So leave the SUBREG then. */
3042 && ! (GET_CODE (SUBREG_REG (x)) == REG
3043 && GET_MODE_SIZE (GET_MODE (x)) <= UNITS_PER_WORD
3044 && GET_MODE_SIZE (GET_MODE (new)) <= UNITS_PER_WORD)
3048 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
3049 enum machine_mode mode = GET_MODE (x);
3051 #if BYTES_BIG_ENDIAN
3052 offset += (MIN (UNITS_PER_WORD,
3053 GET_MODE_SIZE (GET_MODE (new)))
3054 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
3057 PUT_MODE (new, mode);
3058 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
3062 return gen_rtx (SUBREG, GET_MODE (x), new, SUBREG_WORD (x));
3068 /* If clobbering a register that is the replacement register for an
3069 elimination we still think can be performed, note that it cannot
3070 be performed. Otherwise, we need not be concerned about it. */
3071 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3072 if (ep->to_rtx == XEXP (x, 0))
3073 ep->can_eliminate = 0;
3075 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3076 if (new != XEXP (x, 0))
3077 return gen_rtx (code, GET_MODE (x), new);
3083 /* Properly handle sharing input and constraint vectors. */
3084 if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec)
3086 /* When we come to a new vector not seen before,
3087 scan all its elements; keep the old vector if none
3088 of them changes; otherwise, make a copy. */
3089 old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x);
3090 temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx));
3091 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3092 temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i),
3095 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3096 if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i))
3099 if (i == ASM_OPERANDS_INPUT_LENGTH (x))
3100 new_asm_operands_vec = old_asm_operands_vec;
3102 new_asm_operands_vec
3103 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec);
3106 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
3107 if (new_asm_operands_vec == old_asm_operands_vec)
3110 new = gen_rtx (ASM_OPERANDS, VOIDmode, ASM_OPERANDS_TEMPLATE (x),
3111 ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
3112 ASM_OPERANDS_OUTPUT_IDX (x), new_asm_operands_vec,
3113 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x),
3114 ASM_OPERANDS_SOURCE_FILE (x),
3115 ASM_OPERANDS_SOURCE_LINE (x));
3116 new->volatil = x->volatil;
3121 /* Check for setting a register that we know about. */
3122 if (GET_CODE (SET_DEST (x)) == REG)
3124 /* See if this is setting the replacement register for an
3127 If DEST is the hard frame pointer, we do nothing because we
3128 assume that all assignments to the frame pointer are for
3129 non-local gotos and are being done at a time when they are valid
3130 and do not disturb anything else. Some machines want to
3131 eliminate a fake argument pointer (or even a fake frame pointer)
3132 with either the real frame or the stack pointer. Assignments to
3133 the hard frame pointer must not prevent this elimination. */
3135 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3137 if (ep->to_rtx == SET_DEST (x)
3138 && SET_DEST (x) != hard_frame_pointer_rtx)
3140 /* If it is being incremented, adjust the offset. Otherwise,
3141 this elimination can't be done. */
3142 rtx src = SET_SRC (x);
3144 if (GET_CODE (src) == PLUS
3145 && XEXP (src, 0) == SET_DEST (x)
3146 && GET_CODE (XEXP (src, 1)) == CONST_INT)
3147 ep->offset -= INTVAL (XEXP (src, 1));
3149 ep->can_eliminate = 0;
3152 /* Now check to see we are assigning to a register that can be
3153 eliminated. If so, it must be as part of a PARALLEL, since we
3154 will not have been called if this is a single SET. So indicate
3155 that we can no longer eliminate this reg. */
3156 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3158 if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate)
3159 ep->can_eliminate = 0;
3162 /* Now avoid the loop below in this common case. */
3164 rtx new0 = eliminate_regs (SET_DEST (x), 0, insn);
3165 rtx new1 = eliminate_regs (SET_SRC (x), 0, insn);
3167 /* If SET_DEST changed from a REG to a MEM and INSN is an insn,
3168 write a CLOBBER insn. */
3169 if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM
3170 && insn != 0 && GET_CODE (insn) != EXPR_LIST
3171 && GET_CODE (insn) != INSN_LIST)
3172 emit_insn_after (gen_rtx (CLOBBER, VOIDmode, SET_DEST (x)), insn);
3174 if (new0 != SET_DEST (x) || new1 != SET_SRC (x))
3175 return gen_rtx (SET, VOIDmode, new0, new1);
3181 /* Our only special processing is to pass the mode of the MEM to our
3182 recursive call and copy the flags. While we are here, handle this
3183 case more efficiently. */
3184 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
3185 if (new != XEXP (x, 0))
3187 new = gen_rtx (MEM, GET_MODE (x), new);
3188 new->volatil = x->volatil;
3189 new->unchanging = x->unchanging;
3190 new->in_struct = x->in_struct;
3197 /* Process each of our operands recursively. If any have changed, make a
3199 fmt = GET_RTX_FORMAT (code);
3200 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3204 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
3205 if (new != XEXP (x, i) && ! copied)
3207 rtx new_x = rtx_alloc (code);
3208 bcopy (x, new_x, (sizeof (*new_x) - sizeof (new_x->fld)
3209 + (sizeof (new_x->fld[0])
3210 * GET_RTX_LENGTH (code))));
3216 else if (*fmt == 'E')
3219 for (j = 0; j < XVECLEN (x, i); j++)
3221 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
3222 if (new != XVECEXP (x, i, j) && ! copied_vec)
3224 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
3225 &XVECEXP (x, i, 0));
3228 rtx new_x = rtx_alloc (code);
3229 bcopy (x, new_x, (sizeof (*new_x) - sizeof (new_x->fld)
3230 + (sizeof (new_x->fld[0])
3231 * GET_RTX_LENGTH (code))));
3235 XVEC (x, i) = new_v;
3238 XVECEXP (x, i, j) = new;
3246 /* Scan INSN and eliminate all eliminable registers in it.
3248 If REPLACE is nonzero, do the replacement destructively. Also
3249 delete the insn as dead it if it is setting an eliminable register.
3251 If REPLACE is zero, do all our allocations in reload_obstack.
3253 If no eliminations were done and this insn doesn't require any elimination
3254 processing (these are not identical conditions: it might be updating sp,
3255 but not referencing fp; this needs to be seen during reload_as_needed so
3256 that the offset between fp and sp can be taken into consideration), zero
3257 is returned. Otherwise, 1 is returned. */
3260 eliminate_regs_in_insn (insn, replace)
3264 rtx old_body = PATTERN (insn);
3267 struct elim_table *ep;
3270 push_obstacks (&reload_obstack, &reload_obstack);
3272 if (GET_CODE (old_body) == SET && GET_CODE (SET_DEST (old_body)) == REG
3273 && REGNO (SET_DEST (old_body)) < FIRST_PSEUDO_REGISTER)
3275 /* Check for setting an eliminable register. */
3276 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3277 if (ep->from_rtx == SET_DEST (old_body) && ep->can_eliminate)
3279 /* In this case this insn isn't serving a useful purpose. We
3280 will delete it in reload_as_needed once we know that this
3281 elimination is, in fact, being done.
3283 If REPLACE isn't set, we can't delete this insn, but neededn't
3284 process it since it won't be used unless something changes. */
3286 delete_dead_insn (insn);
3291 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3292 in the insn is the negative of the offset in FROM. Substitute
3293 (set (reg) (reg to)) for the insn and change its code.
3295 We have to do this here, rather than in eliminate_regs, do that we can
3296 change the insn code. */
3298 if (GET_CODE (SET_SRC (old_body)) == PLUS
3299 && GET_CODE (XEXP (SET_SRC (old_body), 0)) == REG
3300 && GET_CODE (XEXP (SET_SRC (old_body), 1)) == CONST_INT)
3301 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3303 if (ep->from_rtx == XEXP (SET_SRC (old_body), 0)
3304 && ep->can_eliminate)
3306 /* We must stop at the first elimination that will be used.
3307 If this one would replace the PLUS with a REG, do it
3308 now. Otherwise, quit the loop and let eliminate_regs
3309 do its normal replacement. */
3310 if (ep->offset == - INTVAL (XEXP (SET_SRC (old_body), 1)))
3312 PATTERN (insn) = gen_rtx (SET, VOIDmode,
3313 SET_DEST (old_body), ep->to_rtx);
3314 INSN_CODE (insn) = -1;
3323 old_asm_operands_vec = 0;
3325 /* Replace the body of this insn with a substituted form. If we changed
3326 something, return non-zero.
3328 If we are replacing a body that was a (set X (plus Y Z)), try to
3329 re-recognize the insn. We do this in case we had a simple addition
3330 but now can do this as a load-address. This saves an insn in this
3333 new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX);
3334 if (new_body != old_body)
3336 /* If we aren't replacing things permanently and we changed something,
3337 make another copy to ensure that all the RTL is new. Otherwise
3338 things can go wrong if find_reload swaps commutative operands
3339 and one is inside RTL that has been copied while the other is not. */
3341 /* Don't copy an asm_operands because (1) there's no need and (2)
3342 copy_rtx can't do it properly when there are multiple outputs. */
3343 if (! replace && asm_noperands (old_body) < 0)
3344 new_body = copy_rtx (new_body);
3346 /* If we had a move insn but now we don't, rerecognize it. */
3347 if ((GET_CODE (old_body) == SET && GET_CODE (SET_SRC (old_body)) == REG
3348 && (GET_CODE (new_body) != SET
3349 || GET_CODE (SET_SRC (new_body)) != REG))
3350 /* If this was a load from or store to memory, compare
3351 the MEM in recog_operand to the one in the insn. If they
3352 are not equal, then rerecognize the insn. */
3353 || (GET_CODE (old_body) == SET
3354 && ((GET_CODE (SET_SRC (old_body)) == MEM
3355 && SET_SRC (old_body) != recog_operand[1])
3356 || (GET_CODE (SET_DEST (old_body)) == MEM
3357 && SET_DEST (old_body) != recog_operand[0])))
3358 /* If this was an add insn before, rerecognize. */
3360 (GET_CODE (old_body) == SET
3361 && GET_CODE (SET_SRC (old_body)) == PLUS))
3363 if (! validate_change (insn, &PATTERN (insn), new_body, 0))
3364 /* If recognition fails, store the new body anyway.
3365 It's normal to have recognition failures here
3366 due to bizarre memory addresses; reloading will fix them. */
3367 PATTERN (insn) = new_body;
3370 PATTERN (insn) = new_body;
3375 /* Loop through all elimination pairs. See if any have changed and
3376 recalculate the number not at initial offset.
3378 Compute the maximum offset (minimum offset if the stack does not
3379 grow downward) for each elimination pair.
3381 We also detect a cases where register elimination cannot be done,
3382 namely, if a register would be both changed and referenced outside a MEM
3383 in the resulting insn since such an insn is often undefined and, even if
3384 not, we cannot know what meaning will be given to it. Note that it is
3385 valid to have a register used in an address in an insn that changes it
3386 (presumably with a pre- or post-increment or decrement).
3388 If anything changes, return nonzero. */
3390 num_not_at_initial_offset = 0;
3391 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3393 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3394 ep->can_eliminate = 0;
3396 ep->ref_outside_mem = 0;
3398 if (ep->previous_offset != ep->offset)
3401 ep->previous_offset = ep->offset;
3402 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3403 num_not_at_initial_offset++;
3405 #ifdef STACK_GROWS_DOWNWARD
3406 ep->max_offset = MAX (ep->max_offset, ep->offset);
3408 ep->max_offset = MIN (ep->max_offset, ep->offset);
3413 /* If we changed something, perform elmination in REG_NOTES. This is
3414 needed even when REPLACE is zero because a REG_DEAD note might refer
3415 to a register that we eliminate and could cause a different number
3416 of spill registers to be needed in the final reload pass than in
3418 if (val && REG_NOTES (insn) != 0)
3419 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3427 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3428 replacement we currently believe is valid, mark it as not eliminable if X
3429 modifies DEST in any way other than by adding a constant integer to it.
3431 If DEST is the frame pointer, we do nothing because we assume that
3432 all assignments to the hard frame pointer are nonlocal gotos and are being
3433 done at a time when they are valid and do not disturb anything else.
3434 Some machines want to eliminate a fake argument pointer with either the
3435 frame or stack pointer. Assignments to the hard frame pointer must not
3436 prevent this elimination.
3438 Called via note_stores from reload before starting its passes to scan
3439 the insns of the function. */
3442 mark_not_eliminable (dest, x)
3448 /* A SUBREG of a hard register here is just changing its mode. We should
3449 not see a SUBREG of an eliminable hard register, but check just in
3451 if (GET_CODE (dest) == SUBREG)
3452 dest = SUBREG_REG (dest);
3454 if (dest == hard_frame_pointer_rtx)
3457 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3458 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3459 && (GET_CODE (x) != SET
3460 || GET_CODE (SET_SRC (x)) != PLUS
3461 || XEXP (SET_SRC (x), 0) != dest
3462 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3464 reg_eliminate[i].can_eliminate_previous
3465 = reg_eliminate[i].can_eliminate = 0;
3470 /* Kick all pseudos out of hard register REGNO.
3471 If GLOBAL is nonzero, try to find someplace else to put them.
3472 If DUMPFILE is nonzero, log actions taken on that file.
3474 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3475 because we found we can't eliminate some register. In the case, no pseudos
3476 are allowed to be in the register, even if they are only in a block that
3477 doesn't require spill registers, unlike the case when we are spilling this
3478 hard reg to produce another spill register.
3480 Return nonzero if any pseudos needed to be kicked out. */
3483 spill_hard_reg (regno, global, dumpfile, cant_eliminate)
3489 enum reg_class class = REGNO_REG_CLASS (regno);
3490 int something_changed = 0;
3493 SET_HARD_REG_BIT (forbidden_regs, regno);
3495 /* Spill every pseudo reg that was allocated to this reg
3496 or to something that overlaps this reg. */
3498 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3499 if (reg_renumber[i] >= 0
3500 && reg_renumber[i] <= regno
3502 + HARD_REGNO_NREGS (reg_renumber[i],
3503 PSEUDO_REGNO_MODE (i))
3506 /* If this register belongs solely to a basic block which needed no
3507 spilling of any class that this register is contained in,
3508 leave it be, unless we are spilling this register because
3509 it was a hard register that can't be eliminated. */
3511 if (! cant_eliminate
3512 && basic_block_needs[0]
3513 && reg_basic_block[i] >= 0
3514 && basic_block_needs[(int) class][reg_basic_block[i]] == 0)
3518 for (p = reg_class_superclasses[(int) class];
3519 *p != LIM_REG_CLASSES; p++)
3520 if (basic_block_needs[(int) *p][reg_basic_block[i]] > 0)
3523 if (*p == LIM_REG_CLASSES)
3527 /* Mark it as no longer having a hard register home. */
3528 reg_renumber[i] = -1;
3529 /* We will need to scan everything again. */
3530 something_changed = 1;
3532 retry_global_alloc (i, forbidden_regs);
3534 alter_reg (i, regno);
3537 if (reg_renumber[i] == -1)
3538 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3540 fprintf (dumpfile, " Register %d now in %d.\n\n",
3541 i, reg_renumber[i]);
3544 for (i = 0; i < scratch_list_length; i++)
3546 if (scratch_list[i] && REGNO (scratch_list[i]) == regno)
3548 if (! cant_eliminate && basic_block_needs[0]
3549 && ! basic_block_needs[(int) class][scratch_block[i]])
3553 for (p = reg_class_superclasses[(int) class];
3554 *p != LIM_REG_CLASSES; p++)
3555 if (basic_block_needs[(int) *p][scratch_block[i]] > 0)
3558 if (*p == LIM_REG_CLASSES)
3561 PUT_CODE (scratch_list[i], SCRATCH);
3562 scratch_list[i] = 0;
3563 something_changed = 1;
3568 return something_changed;
3571 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3574 scan_paradoxical_subregs (x)
3579 register enum rtx_code code = GET_CODE (x);
3596 if (GET_CODE (SUBREG_REG (x)) == REG
3597 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3598 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3599 = GET_MODE_SIZE (GET_MODE (x));
3603 fmt = GET_RTX_FORMAT (code);
3604 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3607 scan_paradoxical_subregs (XEXP (x, i));
3608 else if (fmt[i] == 'E')
3611 for (j = XVECLEN (x, i) - 1; j >=0; j--)
3612 scan_paradoxical_subregs (XVECEXP (x, i, j));
3618 hard_reg_use_compare (p1, p2)
3619 struct hard_reg_n_uses *p1, *p2;
3621 int tem = p1->uses - p2->uses;
3622 if (tem != 0) return tem;
3623 /* If regs are equally good, sort by regno,
3624 so that the results of qsort leave nothing to chance. */
3625 return p1->regno - p2->regno;
3628 /* Choose the order to consider regs for use as reload registers
3629 based on how much trouble would be caused by spilling one.
3630 Store them in order of decreasing preference in potential_reload_regs. */
3633 order_regs_for_reload ()
3639 struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
3641 CLEAR_HARD_REG_SET (bad_spill_regs);
3643 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3644 potential_reload_regs[i] = -1;
3646 /* Count number of uses of each hard reg by pseudo regs allocated to it
3647 and then order them by decreasing use. */
3649 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3651 hard_reg_n_uses[i].uses = 0;
3652 hard_reg_n_uses[i].regno = i;
3655 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3657 int regno = reg_renumber[i];
3660 int lim = regno + HARD_REGNO_NREGS (regno, PSEUDO_REGNO_MODE (i));
3662 hard_reg_n_uses[regno++].uses += reg_n_refs[i];
3664 large += reg_n_refs[i];
3667 /* Now fixed registers (which cannot safely be used for reloading)
3668 get a very high use count so they will be considered least desirable.
3669 Registers used explicitly in the rtl code are almost as bad. */
3671 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3675 hard_reg_n_uses[i].uses += 2 * large + 2;
3676 SET_HARD_REG_BIT (bad_spill_regs, i);
3678 else if (regs_explicitly_used[i])
3680 hard_reg_n_uses[i].uses += large + 1;
3681 #ifndef SMALL_REGISTER_CLASSES
3682 /* ??? We are doing this here because of the potential that
3683 bad code may be generated if a register explicitly used in
3684 an insn was used as a spill register for that insn. But
3685 not using these are spill registers may lose on some machine.
3686 We'll have to see how this works out. */
3687 SET_HARD_REG_BIT (bad_spill_regs, i);
3691 hard_reg_n_uses[HARD_FRAME_POINTER_REGNUM].uses += 2 * large + 2;
3692 SET_HARD_REG_BIT (bad_spill_regs, HARD_FRAME_POINTER_REGNUM);
3694 #ifdef ELIMINABLE_REGS
3695 /* If registers other than the frame pointer are eliminable, mark them as
3697 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3699 hard_reg_n_uses[reg_eliminate[i].from].uses += 2 * large + 2;
3700 SET_HARD_REG_BIT (bad_spill_regs, reg_eliminate[i].from);
3704 /* Prefer registers not so far used, for use in temporary loading.
3705 Among them, if REG_ALLOC_ORDER is defined, use that order.
3706 Otherwise, prefer registers not preserved by calls. */
3708 #ifdef REG_ALLOC_ORDER
3709 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3711 int regno = reg_alloc_order[i];
3713 if (hard_reg_n_uses[regno].uses == 0)
3714 potential_reload_regs[o++] = regno;
3717 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3719 if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i])
3720 potential_reload_regs[o++] = i;
3722 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3724 if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i])
3725 potential_reload_regs[o++] = i;
3729 qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
3730 sizeof hard_reg_n_uses[0], hard_reg_use_compare);
3732 /* Now add the regs that are already used,
3733 preferring those used less often. The fixed and otherwise forbidden
3734 registers will be at the end of this list. */
3736 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3737 if (hard_reg_n_uses[i].uses != 0)
3738 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
3741 /* Reload pseudo-registers into hard regs around each insn as needed.
3742 Additional register load insns are output before the insn that needs it
3743 and perhaps store insns after insns that modify the reloaded pseudo reg.
3745 reg_last_reload_reg and reg_reloaded_contents keep track of
3746 which registers are already available in reload registers.
3747 We update these for the reloads that we perform,
3748 as the insns are scanned. */
3751 reload_as_needed (first, live_known)
3761 bzero (spill_reg_rtx, sizeof spill_reg_rtx);
3762 reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
3763 bzero (reg_last_reload_reg, max_regno * sizeof (rtx));
3764 reg_has_output_reload = (char *) alloca (max_regno);
3765 for (i = 0; i < n_spills; i++)
3767 reg_reloaded_contents[i] = -1;
3768 reg_reloaded_insn[i] = 0;
3771 /* Reset all offsets on eliminable registers to their initial values. */
3772 #ifdef ELIMINABLE_REGS
3773 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3775 INITIAL_ELIMINATION_OFFSET (reg_eliminate[i].from, reg_eliminate[i].to,
3776 reg_eliminate[i].initial_offset);
3777 reg_eliminate[i].previous_offset
3778 = reg_eliminate[i].offset = reg_eliminate[i].initial_offset;
3781 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
3782 reg_eliminate[0].previous_offset
3783 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
3786 num_not_at_initial_offset = 0;
3788 for (insn = first; insn;)
3790 register rtx next = NEXT_INSN (insn);
3792 /* Notice when we move to a new basic block. */
3793 if (live_known && this_block + 1 < n_basic_blocks
3794 && insn == basic_block_head[this_block+1])
3797 /* If we pass a label, copy the offsets from the label information
3798 into the current offsets of each elimination. */
3799 if (GET_CODE (insn) == CODE_LABEL)
3801 num_not_at_initial_offset = 0;
3802 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3804 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
3805 = offsets_at[CODE_LABEL_NUMBER (insn)][i];
3806 if (reg_eliminate[i].can_eliminate
3807 && (reg_eliminate[i].offset
3808 != reg_eliminate[i].initial_offset))
3809 num_not_at_initial_offset++;
3813 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
3815 rtx avoid_return_reg = 0;
3817 #ifdef SMALL_REGISTER_CLASSES
3818 /* Set avoid_return_reg if this is an insn
3819 that might use the value of a function call. */
3820 if (GET_CODE (insn) == CALL_INSN)
3822 if (GET_CODE (PATTERN (insn)) == SET)
3823 after_call = SET_DEST (PATTERN (insn));
3824 else if (GET_CODE (PATTERN (insn)) == PARALLEL
3825 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
3826 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
3830 else if (after_call != 0
3831 && !(GET_CODE (PATTERN (insn)) == SET
3832 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
3834 if (reg_mentioned_p (after_call, PATTERN (insn)))
3835 avoid_return_reg = after_call;
3838 #endif /* SMALL_REGISTER_CLASSES */
3840 /* If this is a USE and CLOBBER of a MEM, ensure that any
3841 references to eliminable registers have been removed. */
3843 if ((GET_CODE (PATTERN (insn)) == USE
3844 || GET_CODE (PATTERN (insn)) == CLOBBER)
3845 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3846 XEXP (XEXP (PATTERN (insn), 0), 0)
3847 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3848 GET_MODE (XEXP (PATTERN (insn), 0)), NULL_RTX);
3850 /* If we need to do register elimination processing, do so.
3851 This might delete the insn, in which case we are done. */
3852 if (num_eliminable && GET_MODE (insn) == QImode)
3854 eliminate_regs_in_insn (insn, 1);
3855 if (GET_CODE (insn) == NOTE)
3862 if (GET_MODE (insn) == VOIDmode)
3864 /* First find the pseudo regs that must be reloaded for this insn.
3865 This info is returned in the tables reload_... (see reload.h).
3866 Also modify the body of INSN by substituting RELOAD
3867 rtx's for those pseudo regs. */
3870 bzero (reg_has_output_reload, max_regno);
3871 CLEAR_HARD_REG_SET (reg_is_output_reload);
3873 find_reloads (insn, 1, spill_indirect_levels, live_known,
3879 rtx prev = PREV_INSN (insn), next = NEXT_INSN (insn);
3883 /* If this block has not had spilling done for a
3884 particular clas and we have any non-optionals that need a
3885 spill reg in that class, abort. */
3887 for (class = 0; class < N_REG_CLASSES; class++)
3888 if (basic_block_needs[class] != 0
3889 && basic_block_needs[class][this_block] == 0)
3890 for (i = 0; i < n_reloads; i++)
3891 if (class == (int) reload_reg_class[i]
3892 && reload_reg_rtx[i] == 0
3893 && ! reload_optional[i]
3894 && (reload_in[i] != 0 || reload_out[i] != 0
3895 || reload_secondary_p[i] != 0))
3898 /* Now compute which reload regs to reload them into. Perhaps
3899 reusing reload regs from previous insns, or else output
3900 load insns to reload them. Maybe output store insns too.
3901 Record the choices of reload reg in reload_reg_rtx. */
3902 choose_reload_regs (insn, avoid_return_reg);
3904 #ifdef SMALL_REGISTER_CLASSES
3905 /* Merge any reloads that we didn't combine for fear of
3906 increasing the number of spill registers needed but now
3907 discover can be safely merged. */
3908 merge_assigned_reloads (insn);
3911 /* Generate the insns to reload operands into or out of
3912 their reload regs. */
3913 emit_reload_insns (insn);
3915 /* Substitute the chosen reload regs from reload_reg_rtx
3916 into the insn's body (or perhaps into the bodies of other
3917 load and store insn that we just made for reloading
3918 and that we moved the structure into). */
3921 /* If this was an ASM, make sure that all the reload insns
3922 we have generated are valid. If not, give an error
3925 if (asm_noperands (PATTERN (insn)) >= 0)
3926 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3927 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
3928 && (recog_memoized (p) < 0
3929 || (insn_extract (p),
3930 ! constrain_operands (INSN_CODE (p), 1))))
3932 error_for_asm (insn,
3933 "`asm' operand requires impossible reload");
3935 NOTE_SOURCE_FILE (p) = 0;
3936 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
3939 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3940 is no longer validly lying around to save a future reload.
3941 Note that this does not detect pseudos that were reloaded
3942 for this insn in order to be stored in
3943 (obeying register constraints). That is correct; such reload
3944 registers ARE still valid. */
3945 note_stores (PATTERN (insn), forget_old_reloads_1);
3947 /* There may have been CLOBBER insns placed after INSN. So scan
3948 between INSN and NEXT and use them to forget old reloads. */
3949 for (x = NEXT_INSN (insn); x != next; x = NEXT_INSN (x))
3950 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3951 note_stores (PATTERN (x), forget_old_reloads_1);
3954 /* Likewise for regs altered by auto-increment in this insn.
3955 But note that the reg-notes are not changed by reloading:
3956 they still contain the pseudo-regs, not the spill regs. */
3957 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3958 if (REG_NOTE_KIND (x) == REG_INC)
3960 /* See if this pseudo reg was reloaded in this insn.
3961 If so, its last-reload info is still valid
3962 because it is based on this insn's reload. */
3963 for (i = 0; i < n_reloads; i++)
3964 if (reload_out[i] == XEXP (x, 0))
3968 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX);
3972 /* A reload reg's contents are unknown after a label. */
3973 if (GET_CODE (insn) == CODE_LABEL)
3974 for (i = 0; i < n_spills; i++)
3976 reg_reloaded_contents[i] = -1;
3977 reg_reloaded_insn[i] = 0;
3980 /* Don't assume a reload reg is still good after a call insn
3981 if it is a call-used reg. */
3982 else if (GET_CODE (insn) == CALL_INSN)
3983 for (i = 0; i < n_spills; i++)
3984 if (call_used_regs[spill_regs[i]])
3986 reg_reloaded_contents[i] = -1;
3987 reg_reloaded_insn[i] = 0;
3990 /* In case registers overlap, allow certain insns to invalidate
3991 particular hard registers. */
3993 #ifdef INSN_CLOBBERS_REGNO_P
3994 for (i = 0 ; i < n_spills ; i++)
3995 if (INSN_CLOBBERS_REGNO_P (insn, spill_regs[i]))
3997 reg_reloaded_contents[i] = -1;
3998 reg_reloaded_insn[i] = 0;
4010 /* Discard all record of any value reloaded from X,
4011 or reloaded in X from someplace else;
4012 unless X is an output reload reg of the current insn.
4014 X may be a hard reg (the reload reg)
4015 or it may be a pseudo reg that was reloaded from. */
4018 forget_old_reloads_1 (x, ignored)
4026 /* note_stores does give us subregs of hard regs. */
4027 while (GET_CODE (x) == SUBREG)
4029 offset += SUBREG_WORD (x);
4033 if (GET_CODE (x) != REG)
4036 regno = REGNO (x) + offset;
4038 if (regno >= FIRST_PSEUDO_REGISTER)
4043 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4044 /* Storing into a spilled-reg invalidates its contents.
4045 This can happen if a block-local pseudo is allocated to that reg
4046 and it wasn't spilled because this block's total need is 0.
4047 Then some insn might have an optional reload and use this reg. */
4048 for (i = 0; i < nr; i++)
4049 if (spill_reg_order[regno + i] >= 0
4050 /* But don't do this if the reg actually serves as an output
4051 reload reg in the current instruction. */
4053 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i)))
4055 reg_reloaded_contents[spill_reg_order[regno + i]] = -1;
4056 reg_reloaded_insn[spill_reg_order[regno + i]] = 0;
4060 /* Since value of X has changed,
4061 forget any value previously copied from it. */
4064 /* But don't forget a copy if this is the output reload
4065 that establishes the copy's validity. */
4066 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4067 reg_last_reload_reg[regno + nr] = 0;
4070 /* For each reload, the mode of the reload register. */
4071 static enum machine_mode reload_mode[MAX_RELOADS];
4073 /* For each reload, the largest number of registers it will require. */
4074 static int reload_nregs[MAX_RELOADS];
4076 /* Comparison function for qsort to decide which of two reloads
4077 should be handled first. *P1 and *P2 are the reload numbers. */
4080 reload_reg_class_lower (p1, p2)
4083 register int r1 = *p1, r2 = *p2;
4086 /* Consider required reloads before optional ones. */
4087 t = reload_optional[r1] - reload_optional[r2];
4091 /* Count all solitary classes before non-solitary ones. */
4092 t = ((reg_class_size[(int) reload_reg_class[r2]] == 1)
4093 - (reg_class_size[(int) reload_reg_class[r1]] == 1));
4097 /* Aside from solitaires, consider all multi-reg groups first. */
4098 t = reload_nregs[r2] - reload_nregs[r1];
4102 /* Consider reloads in order of increasing reg-class number. */
4103 t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2];
4107 /* If reloads are equally urgent, sort by reload number,
4108 so that the results of qsort leave nothing to chance. */
4112 /* The following HARD_REG_SETs indicate when each hard register is
4113 used for a reload of various parts of the current insn. */
4115 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4116 static HARD_REG_SET reload_reg_used;
4117 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4118 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4119 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4120 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4121 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4122 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4123 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4124 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4125 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4126 static HARD_REG_SET reload_reg_used_in_op_addr;
4127 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4128 static HARD_REG_SET reload_reg_used_in_insn;
4129 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4130 static HARD_REG_SET reload_reg_used_in_other_addr;
4132 /* If reg is in use as a reload reg for any sort of reload. */
4133 static HARD_REG_SET reload_reg_used_at_all;
4135 /* If reg is use as an inherited reload. We just mark the first register
4137 static HARD_REG_SET reload_reg_used_for_inherit;
4139 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4140 TYPE. MODE is used to indicate how many consecutive regs are
4144 mark_reload_reg_in_use (regno, opnum, type, mode)
4147 enum reload_type type;
4148 enum machine_mode mode;
4150 int nregs = HARD_REGNO_NREGS (regno, mode);
4153 for (i = regno; i < nregs + regno; i++)
4158 SET_HARD_REG_BIT (reload_reg_used, i);
4161 case RELOAD_FOR_INPUT_ADDRESS:
4162 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4165 case RELOAD_FOR_OUTPUT_ADDRESS:
4166 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4169 case RELOAD_FOR_OPERAND_ADDRESS:
4170 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4173 case RELOAD_FOR_OTHER_ADDRESS:
4174 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4177 case RELOAD_FOR_INPUT:
4178 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4181 case RELOAD_FOR_OUTPUT:
4182 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4185 case RELOAD_FOR_INSN:
4186 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4190 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4194 /* Similarly, but show REGNO is no longer in use for a reload. */
4197 clear_reload_reg_in_use (regno, opnum, type, mode)
4200 enum reload_type type;
4201 enum machine_mode mode;
4203 int nregs = HARD_REGNO_NREGS (regno, mode);
4206 for (i = regno; i < nregs + regno; i++)
4211 CLEAR_HARD_REG_BIT (reload_reg_used, i);
4214 case RELOAD_FOR_INPUT_ADDRESS:
4215 CLEAR_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4218 case RELOAD_FOR_OUTPUT_ADDRESS:
4219 CLEAR_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4222 case RELOAD_FOR_OPERAND_ADDRESS:
4223 CLEAR_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4226 case RELOAD_FOR_OTHER_ADDRESS:
4227 CLEAR_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4230 case RELOAD_FOR_INPUT:
4231 CLEAR_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4234 case RELOAD_FOR_OUTPUT:
4235 CLEAR_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4238 case RELOAD_FOR_INSN:
4239 CLEAR_HARD_REG_BIT (reload_reg_used_in_insn, i);
4245 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4246 specified by OPNUM and TYPE. */
4249 reload_reg_free_p (regno, opnum, type)
4252 enum reload_type type;
4256 /* In use for a RELOAD_OTHER means it's not available for anything except
4257 RELOAD_FOR_OTHER_ADDRESS. Recall that RELOAD_FOR_OTHER_ADDRESS is known
4258 to be used only for inputs. */
4260 if (type != RELOAD_FOR_OTHER_ADDRESS
4261 && TEST_HARD_REG_BIT (reload_reg_used, regno))
4267 /* In use for anything means not available for a RELOAD_OTHER. */
4268 return ! TEST_HARD_REG_BIT (reload_reg_used_at_all, regno);
4270 /* The other kinds of use can sometimes share a register. */
4271 case RELOAD_FOR_INPUT:
4272 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4273 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4276 /* If it is used for some other input, can't use it. */
4277 for (i = 0; i < reload_n_operands; i++)
4278 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4281 /* If it is used in a later operand's address, can't use it. */
4282 for (i = opnum + 1; i < reload_n_operands; i++)
4283 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4288 case RELOAD_FOR_INPUT_ADDRESS:
4289 /* Can't use a register if it is used for an input address for this
4290 operand or used as an input in an earlier one. */
4291 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno))
4294 for (i = 0; i < opnum; i++)
4295 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4300 case RELOAD_FOR_OUTPUT_ADDRESS:
4301 /* Can't use a register if it is used for an output address for this
4302 operand or used as an output in this or a later operand. */
4303 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4306 for (i = opnum; i < reload_n_operands; i++)
4307 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4312 case RELOAD_FOR_OPERAND_ADDRESS:
4313 for (i = 0; i < reload_n_operands; i++)
4314 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4317 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4318 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4320 case RELOAD_FOR_OUTPUT:
4321 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4322 outputs, or an operand address for this or an earlier output. */
4323 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4326 for (i = 0; i < reload_n_operands; i++)
4327 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4330 for (i = 0; i <= opnum; i++)
4331 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno))
4336 case RELOAD_FOR_INSN:
4337 for (i = 0; i < reload_n_operands; i++)
4338 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4339 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4342 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4343 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4345 case RELOAD_FOR_OTHER_ADDRESS:
4346 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4351 /* Return 1 if the value in reload reg REGNO, as used by a reload
4352 needed for the part of the insn specified by OPNUM and TYPE,
4353 is not in use for a reload in any prior part of the insn.
4355 We can assume that the reload reg was already tested for availability
4356 at the time it is needed, and we should not check this again,
4357 in case the reg has already been marked in use. */
4360 reload_reg_free_before_p (regno, opnum, type)
4363 enum reload_type type;
4369 case RELOAD_FOR_OTHER_ADDRESS:
4370 /* These always come first. */
4374 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4376 /* If this use is for part of the insn,
4377 check the reg is not in use for any prior part. It is tempting
4378 to try to do this by falling through from objecs that occur
4379 later in the insn to ones that occur earlier, but that will not
4380 correctly take into account the fact that here we MUST ignore
4381 things that would prevent the register from being allocated in
4382 the first place, since we know that it was allocated. */
4384 case RELOAD_FOR_OUTPUT_ADDRESS:
4385 /* Earlier reloads are for earlier outputs or their addresses,
4386 any RELOAD_FOR_INSN reloads, any inputs or their addresses, or any
4387 RELOAD_FOR_OTHER_ADDRESS reloads (we know it can't conflict with
4389 for (i = 0; i < opnum; i++)
4390 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4391 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4394 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4397 for (i = 0; i < reload_n_operands; i++)
4398 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4399 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4402 return (! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4403 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4404 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4406 case RELOAD_FOR_OUTPUT:
4407 /* This can't be used in the output address for this operand and
4408 anything that can't be used for it, except that we've already
4409 tested for RELOAD_FOR_INSN objects. */
4411 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4414 for (i = 0; i < opnum; i++)
4415 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4416 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4419 for (i = 0; i < reload_n_operands; i++)
4420 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4421 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4422 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4425 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4427 case RELOAD_FOR_OPERAND_ADDRESS:
4428 case RELOAD_FOR_INSN:
4429 /* These can't conflict with inputs, or each other, so all we have to
4430 test is input addresses and the addresses of OTHER items. */
4432 for (i = 0; i < reload_n_operands; i++)
4433 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4436 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4438 case RELOAD_FOR_INPUT:
4439 /* The only things earlier are the address for this and
4440 earlier inputs, other inputs (which we know we don't conflict
4441 with), and addresses of RELOAD_OTHER objects. */
4443 for (i = 0; i <= opnum; i++)
4444 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4447 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4449 case RELOAD_FOR_INPUT_ADDRESS:
4450 /* Similarly, all we have to check is for use in earlier inputs'
4452 for (i = 0; i < opnum; i++)
4453 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4456 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4461 /* Return 1 if the value in reload reg REGNO, as used by a reload
4462 needed for the part of the insn specified by OPNUM and TYPE,
4463 is still available in REGNO at the end of the insn.
4465 We can assume that the reload reg was already tested for availability
4466 at the time it is needed, and we should not check this again,
4467 in case the reg has already been marked in use. */
4470 reload_reg_reaches_end_p (regno, opnum, type)
4473 enum reload_type type;
4480 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4481 its value must reach the end. */
4484 /* If this use is for part of the insn,
4485 its value reaches if no subsequent part uses the same register.
4486 Just like the above function, don't try to do this with lots
4489 case RELOAD_FOR_OTHER_ADDRESS:
4490 /* Here we check for everything else, since these don't conflict
4491 with anything else and everything comes later. */
4493 for (i = 0; i < reload_n_operands; i++)
4494 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4495 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4496 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4497 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4500 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4501 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4502 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4504 case RELOAD_FOR_INPUT_ADDRESS:
4505 /* Similar, except that we check only for this and subsequent inputs
4506 and the address of only subsequent inputs and we do not need
4507 to check for RELOAD_OTHER objects since they are known not to
4510 for (i = opnum; i < reload_n_operands; i++)
4511 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4514 for (i = opnum + 1; i < reload_n_operands; i++)
4515 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4518 for (i = 0; i < reload_n_operands; i++)
4519 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4520 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4523 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4524 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4526 case RELOAD_FOR_INPUT:
4527 /* Similar to input address, except we start at the next operand for
4528 both input and input address and we do not check for
4529 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4532 for (i = opnum + 1; i < reload_n_operands; i++)
4533 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4534 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4537 /* ... fall through ... */
4539 case RELOAD_FOR_OPERAND_ADDRESS:
4540 /* Check outputs and their addresses. */
4542 for (i = 0; i < reload_n_operands; i++)
4543 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4544 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4549 case RELOAD_FOR_INSN:
4550 /* These conflict with other outputs with with RELOAD_OTHER. So
4551 we need only check for output addresses. */
4555 /* ... fall through ... */
4557 case RELOAD_FOR_OUTPUT:
4558 case RELOAD_FOR_OUTPUT_ADDRESS:
4559 /* We already know these can't conflict with a later output. So the
4560 only thing to check are later output addresses. */
4561 for (i = opnum + 1; i < reload_n_operands; i++)
4562 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno))
4571 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4574 This function uses the same algorithm as reload_reg_free_p above. */
4577 reloads_conflict (r1, r2)
4580 enum reload_type r1_type = reload_when_needed[r1];
4581 enum reload_type r2_type = reload_when_needed[r2];
4582 int r1_opnum = reload_opnum[r1];
4583 int r2_opnum = reload_opnum[r2];
4585 /* RELOAD_OTHER conflicts with everything except
4586 RELOAD_FOR_OTHER_ADDRESS. */
4588 if ((r1_type == RELOAD_OTHER && r2_type != RELOAD_FOR_OTHER_ADDRESS)
4589 || (r2_type == RELOAD_OTHER && r1_type != RELOAD_FOR_OTHER_ADDRESS))
4592 /* Otherwise, check conflicts differently for each type. */
4596 case RELOAD_FOR_INPUT:
4597 return (r2_type == RELOAD_FOR_INSN
4598 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4599 || r2_type == RELOAD_FOR_INPUT
4600 || (r2_type == RELOAD_FOR_INPUT_ADDRESS && r2_opnum > r1_opnum));
4602 case RELOAD_FOR_INPUT_ADDRESS:
4603 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4604 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4606 case RELOAD_FOR_OUTPUT_ADDRESS:
4607 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4608 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4610 case RELOAD_FOR_OPERAND_ADDRESS:
4611 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4612 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4614 case RELOAD_FOR_OUTPUT:
4615 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4616 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
4617 && r2_opnum >= r1_opnum));
4619 case RELOAD_FOR_INSN:
4620 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4621 || r2_type == RELOAD_FOR_INSN
4622 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4624 case RELOAD_FOR_OTHER_ADDRESS:
4625 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4632 /* Vector of reload-numbers showing the order in which the reloads should
4634 short reload_order[MAX_RELOADS];
4636 /* Indexed by reload number, 1 if incoming value
4637 inherited from previous insns. */
4638 char reload_inherited[MAX_RELOADS];
4640 /* For an inherited reload, this is the insn the reload was inherited from,
4641 if we know it. Otherwise, this is 0. */
4642 rtx reload_inheritance_insn[MAX_RELOADS];
4644 /* If non-zero, this is a place to get the value of the reload,
4645 rather than using reload_in. */
4646 rtx reload_override_in[MAX_RELOADS];
4648 /* For each reload, the index in spill_regs of the spill register used,
4649 or -1 if we did not need one of the spill registers for this reload. */
4650 int reload_spill_index[MAX_RELOADS];
4652 /* Index of last register assigned as a spill register. We allocate in
4653 a round-robin fashio. */
4655 static int last_spill_reg = 0;
4657 /* Find a spill register to use as a reload register for reload R.
4658 LAST_RELOAD is non-zero if this is the last reload for the insn being
4661 Set reload_reg_rtx[R] to the register allocated.
4663 If NOERROR is nonzero, we return 1 if successful,
4664 or 0 if we couldn't find a spill reg and we didn't change anything. */
4667 allocate_reload_reg (r, insn, last_reload, noerror)
4679 /* If we put this reload ahead, thinking it is a group,
4680 then insist on finding a group. Otherwise we can grab a
4681 reg that some other reload needs.
4682 (That can happen when we have a 68000 DATA_OR_FP_REG
4683 which is a group of data regs or one fp reg.)
4684 We need not be so restrictive if there are no more reloads
4687 ??? Really it would be nicer to have smarter handling
4688 for that kind of reg class, where a problem like this is normal.
4689 Perhaps those classes should be avoided for reloading
4690 by use of more alternatives. */
4692 int force_group = reload_nregs[r] > 1 && ! last_reload;
4694 /* If we want a single register and haven't yet found one,
4695 take any reg in the right class and not in use.
4696 If we want a consecutive group, here is where we look for it.
4698 We use two passes so we can first look for reload regs to
4699 reuse, which are already in use for other reloads in this insn,
4700 and only then use additional registers.
4701 I think that maximizing reuse is needed to make sure we don't
4702 run out of reload regs. Suppose we have three reloads, and
4703 reloads A and B can share regs. These need two regs.
4704 Suppose A and B are given different regs.
4705 That leaves none for C. */
4706 for (pass = 0; pass < 2; pass++)
4708 /* I is the index in spill_regs.
4709 We advance it round-robin between insns to use all spill regs
4710 equally, so that inherited reloads have a chance
4711 of leapfrogging each other. */
4713 for (count = 0, i = last_spill_reg; count < n_spills; count++)
4715 int class = (int) reload_reg_class[r];
4717 i = (i + 1) % n_spills;
4719 if (reload_reg_free_p (spill_regs[i], reload_opnum[r],
4720 reload_when_needed[r])
4721 && TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i])
4722 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
4723 /* Look first for regs to share, then for unshared. But
4724 don't share regs used for inherited reloads; they are
4725 the ones we want to preserve. */
4727 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
4729 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
4732 int nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
4733 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
4734 (on 68000) got us two FP regs. If NR is 1,
4735 we would reject both of them. */
4737 nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]);
4738 /* If we need only one reg, we have already won. */
4741 /* But reject a single reg if we demand a group. */
4746 /* Otherwise check that as many consecutive regs as we need
4748 Also, don't use for a group registers that are
4749 needed for nongroups. */
4750 if (! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
4753 regno = spill_regs[i] + nr - 1;
4754 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
4755 && spill_reg_order[regno] >= 0
4756 && reload_reg_free_p (regno, reload_opnum[r],
4757 reload_when_needed[r])
4758 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
4768 /* If we found something on pass 1, omit pass 2. */
4769 if (count < n_spills)
4773 /* We should have found a spill register by now. */
4774 if (count == n_spills)
4781 /* I is the index in SPILL_REG_RTX of the reload register we are to
4782 allocate. Get an rtx for it and find its register number. */
4784 new = spill_reg_rtx[i];
4786 if (new == 0 || GET_MODE (new) != reload_mode[r])
4787 spill_reg_rtx[i] = new
4788 = gen_rtx (REG, reload_mode[r], spill_regs[i]);
4790 regno = true_regnum (new);
4792 /* Detect when the reload reg can't hold the reload mode.
4793 This used to be one `if', but Sequent compiler can't handle that. */
4794 if (HARD_REGNO_MODE_OK (regno, reload_mode[r]))
4796 enum machine_mode test_mode = VOIDmode;
4798 test_mode = GET_MODE (reload_in[r]);
4799 /* If reload_in[r] has VOIDmode, it means we will load it
4800 in whatever mode the reload reg has: to wit, reload_mode[r].
4801 We have already tested that for validity. */
4802 /* Aside from that, we need to test that the expressions
4803 to reload from or into have modes which are valid for this
4804 reload register. Otherwise the reload insns would be invalid. */
4805 if (! (reload_in[r] != 0 && test_mode != VOIDmode
4806 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
4807 if (! (reload_out[r] != 0
4808 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r]))))
4810 /* The reg is OK. */
4813 /* Mark as in use for this insn the reload regs we use
4815 mark_reload_reg_in_use (spill_regs[i], reload_opnum[r],
4816 reload_when_needed[r], reload_mode[r]);
4818 reload_reg_rtx[r] = new;
4819 reload_spill_index[r] = i;
4824 /* The reg is not OK. */
4829 if (asm_noperands (PATTERN (insn)) < 0)
4830 /* It's the compiler's fault. */
4833 /* It's the user's fault; the operand's mode and constraint
4834 don't match. Disable this reload so we don't crash in final. */
4835 error_for_asm (insn,
4836 "`asm' operand constraint incompatible with operand size");
4839 reload_reg_rtx[r] = 0;
4840 reload_optional[r] = 1;
4841 reload_secondary_p[r] = 1;
4846 /* Assign hard reg targets for the pseudo-registers we must reload
4847 into hard regs for this insn.
4848 Also output the instructions to copy them in and out of the hard regs.
4850 For machines with register classes, we are responsible for
4851 finding a reload reg in the proper class. */
4854 choose_reload_regs (insn, avoid_return_reg)
4856 rtx avoid_return_reg;
4859 int max_group_size = 1;
4860 enum reg_class group_class = NO_REGS;
4863 rtx save_reload_reg_rtx[MAX_RELOADS];
4864 char save_reload_inherited[MAX_RELOADS];
4865 rtx save_reload_inheritance_insn[MAX_RELOADS];
4866 rtx save_reload_override_in[MAX_RELOADS];
4867 int save_reload_spill_index[MAX_RELOADS];
4868 HARD_REG_SET save_reload_reg_used;
4869 HARD_REG_SET save_reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4870 HARD_REG_SET save_reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4871 HARD_REG_SET save_reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4872 HARD_REG_SET save_reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4873 HARD_REG_SET save_reload_reg_used_in_op_addr;
4874 HARD_REG_SET save_reload_reg_used_in_insn;
4875 HARD_REG_SET save_reload_reg_used_in_other_addr;
4876 HARD_REG_SET save_reload_reg_used_at_all;
4878 bzero (reload_inherited, MAX_RELOADS);
4879 bzero (reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
4880 bzero (reload_override_in, MAX_RELOADS * sizeof (rtx));
4882 CLEAR_HARD_REG_SET (reload_reg_used);
4883 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
4884 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
4885 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
4886 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
4888 for (i = 0; i < reload_n_operands; i++)
4890 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
4891 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
4892 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
4893 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
4896 #ifdef SMALL_REGISTER_CLASSES
4897 /* Don't bother with avoiding the return reg
4898 if we have no mandatory reload that could use it. */
4899 if (avoid_return_reg)
4902 int regno = REGNO (avoid_return_reg);
4904 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
4907 for (r = regno; r < regno + nregs; r++)
4908 if (spill_reg_order[r] >= 0)
4909 for (j = 0; j < n_reloads; j++)
4910 if (!reload_optional[j] && reload_reg_rtx[j] == 0
4911 && (reload_in[j] != 0 || reload_out[j] != 0
4912 || reload_secondary_p[j])
4914 TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[j]], r))
4917 avoid_return_reg = 0;
4919 #endif /* SMALL_REGISTER_CLASSES */
4921 #if 0 /* Not needed, now that we can always retry without inheritance. */
4922 /* See if we have more mandatory reloads than spill regs.
4923 If so, then we cannot risk optimizations that could prevent
4924 reloads from sharing one spill register.
4926 Since we will try finding a better register than reload_reg_rtx
4927 unless it is equal to reload_in or reload_out, count such reloads. */
4931 #ifdef SMALL_REGISTER_CLASSES
4932 int tem = (avoid_return_reg != 0);
4934 for (j = 0; j < n_reloads; j++)
4935 if (! reload_optional[j]
4936 && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j])
4937 && (reload_reg_rtx[j] == 0
4938 || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j])
4939 && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j]))))
4946 #ifdef SMALL_REGISTER_CLASSES
4947 /* Don't use the subroutine call return reg for a reload
4948 if we are supposed to avoid it. */
4949 if (avoid_return_reg)
4951 int regno = REGNO (avoid_return_reg);
4953 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
4956 for (r = regno; r < regno + nregs; r++)
4957 if (spill_reg_order[r] >= 0)
4958 SET_HARD_REG_BIT (reload_reg_used, r);
4960 #endif /* SMALL_REGISTER_CLASSES */
4962 /* In order to be certain of getting the registers we need,
4963 we must sort the reloads into order of increasing register class.
4964 Then our grabbing of reload registers will parallel the process
4965 that provided the reload registers.
4967 Also note whether any of the reloads wants a consecutive group of regs.
4968 If so, record the maximum size of the group desired and what
4969 register class contains all the groups needed by this insn. */
4971 for (j = 0; j < n_reloads; j++)
4973 reload_order[j] = j;
4974 reload_spill_index[j] = -1;
4977 = (reload_inmode[j] == VOIDmode
4978 || (GET_MODE_SIZE (reload_outmode[j])
4979 > GET_MODE_SIZE (reload_inmode[j])))
4980 ? reload_outmode[j] : reload_inmode[j];
4982 reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]);
4984 if (reload_nregs[j] > 1)
4986 max_group_size = MAX (reload_nregs[j], max_group_size);
4987 group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class];
4990 /* If we have already decided to use a certain register,
4991 don't use it in another way. */
4992 if (reload_reg_rtx[j])
4993 mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]), reload_opnum[j],
4994 reload_when_needed[j], reload_mode[j]);
4998 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5000 bcopy (reload_reg_rtx, save_reload_reg_rtx, sizeof reload_reg_rtx);
5001 bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited);
5002 bcopy (reload_inheritance_insn, save_reload_inheritance_insn,
5003 sizeof reload_inheritance_insn);
5004 bcopy (reload_override_in, save_reload_override_in,
5005 sizeof reload_override_in);
5006 bcopy (reload_spill_index, save_reload_spill_index,
5007 sizeof reload_spill_index);
5008 COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used);
5009 COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all);
5010 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr,
5011 reload_reg_used_in_op_addr);
5012 COPY_HARD_REG_SET (save_reload_reg_used_in_insn,
5013 reload_reg_used_in_insn);
5014 COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr,
5015 reload_reg_used_in_other_addr);
5017 for (i = 0; i < reload_n_operands; i++)
5019 COPY_HARD_REG_SET (save_reload_reg_used_in_output[i],
5020 reload_reg_used_in_output[i]);
5021 COPY_HARD_REG_SET (save_reload_reg_used_in_input[i],
5022 reload_reg_used_in_input[i]);
5023 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr[i],
5024 reload_reg_used_in_input_addr[i]);
5025 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr[i],
5026 reload_reg_used_in_output_addr[i]);
5029 /* If -O, try first with inheritance, then turning it off.
5030 If not -O, don't do inheritance.
5031 Using inheritance when not optimizing leads to paradoxes
5032 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5033 because one side of the comparison might be inherited. */
5035 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5037 /* Process the reloads in order of preference just found.
5038 Beyond this point, subregs can be found in reload_reg_rtx.
5040 This used to look for an existing reloaded home for all
5041 of the reloads, and only then perform any new reloads.
5042 But that could lose if the reloads were done out of reg-class order
5043 because a later reload with a looser constraint might have an old
5044 home in a register needed by an earlier reload with a tighter constraint.
5046 To solve this, we make two passes over the reloads, in the order
5047 described above. In the first pass we try to inherit a reload
5048 from a previous insn. If there is a later reload that needs a
5049 class that is a proper subset of the class being processed, we must
5050 also allocate a spill register during the first pass.
5052 Then make a second pass over the reloads to allocate any reloads
5053 that haven't been given registers yet. */
5055 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5057 for (j = 0; j < n_reloads; j++)
5059 register int r = reload_order[j];
5061 /* Ignore reloads that got marked inoperative. */
5062 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
5065 /* If find_reloads chose a to use reload_in or reload_out as a reload
5066 register, we don't need to chose one. Otherwise, try even if it found
5067 one since we might save an insn if we find the value lying around. */
5068 if (reload_in[r] != 0 && reload_reg_rtx[r] != 0
5069 && (rtx_equal_p (reload_in[r], reload_reg_rtx[r])
5070 || rtx_equal_p (reload_out[r], reload_reg_rtx[r])))
5073 #if 0 /* No longer needed for correct operation.
5074 It might give better code, or might not; worth an experiment? */
5075 /* If this is an optional reload, we can't inherit from earlier insns
5076 until we are sure that any non-optional reloads have been allocated.
5077 The following code takes advantage of the fact that optional reloads
5078 are at the end of reload_order. */
5079 if (reload_optional[r] != 0)
5080 for (i = 0; i < j; i++)
5081 if ((reload_out[reload_order[i]] != 0
5082 || reload_in[reload_order[i]] != 0
5083 || reload_secondary_p[reload_order[i]])
5084 && ! reload_optional[reload_order[i]]
5085 && reload_reg_rtx[reload_order[i]] == 0)
5086 allocate_reload_reg (reload_order[i], insn, 0, inheritance);
5089 /* First see if this pseudo is already available as reloaded
5090 for a previous insn. We cannot try to inherit for reloads
5091 that are smaller than the maximum number of registers needed
5092 for groups unless the register we would allocate cannot be used
5095 We could check here to see if this is a secondary reload for
5096 an object that is already in a register of the desired class.
5097 This would avoid the need for the secondary reload register.
5098 But this is complex because we can't easily determine what
5099 objects might want to be loaded via this reload. So let a register
5100 be allocated here. In `emit_reload_insns' we suppress one of the
5101 loads in the case described above. */
5105 register int regno = -1;
5106 enum machine_mode mode;
5108 if (reload_in[r] == 0)
5110 else if (GET_CODE (reload_in[r]) == REG)
5112 regno = REGNO (reload_in[r]);
5113 mode = GET_MODE (reload_in[r]);
5115 else if (GET_CODE (reload_in_reg[r]) == REG)
5117 regno = REGNO (reload_in_reg[r]);
5118 mode = GET_MODE (reload_in_reg[r]);
5121 /* This won't work, since REGNO can be a pseudo reg number.
5122 Also, it takes much more hair to keep track of all the things
5123 that can invalidate an inherited reload of part of a pseudoreg. */
5124 else if (GET_CODE (reload_in[r]) == SUBREG
5125 && GET_CODE (SUBREG_REG (reload_in[r])) == REG)
5126 regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]);
5129 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5131 i = spill_reg_order[REGNO (reg_last_reload_reg[regno])];
5133 if (reg_reloaded_contents[i] == regno
5134 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno]))
5135 >= GET_MODE_SIZE (mode))
5136 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
5137 && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5139 && (reload_nregs[r] == max_group_size
5140 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5142 && reload_reg_free_p (spill_regs[i], reload_opnum[r],
5143 reload_when_needed[r])
5144 && reload_reg_free_before_p (spill_regs[i],
5146 reload_when_needed[r]))
5148 /* If a group is needed, verify that all the subsequent
5149 registers still have their values intact. */
5151 = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
5154 for (k = 1; k < nr; k++)
5155 if (reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
5163 /* We found a register that contains the
5164 value we need. If this register is the
5165 same as an `earlyclobber' operand of the
5166 current insn, just mark it as a place to
5167 reload from since we can't use it as the
5168 reload register itself. */
5170 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5171 if (reg_overlap_mentioned_for_reload_p
5172 (reg_last_reload_reg[regno],
5173 reload_earlyclobbers[i1]))
5176 if (i1 != n_earlyclobbers
5177 /* Don't really use the inherited spill reg
5178 if we need it wider than we've got it. */
5179 || (GET_MODE_SIZE (reload_mode[r])
5180 > GET_MODE_SIZE (mode)))
5181 reload_override_in[r] = reg_last_reload_reg[regno];
5185 /* We can use this as a reload reg. */
5186 /* Mark the register as in use for this part of
5188 mark_reload_reg_in_use (spill_regs[i],
5190 reload_when_needed[r],
5192 reload_reg_rtx[r] = reg_last_reload_reg[regno];
5193 reload_inherited[r] = 1;
5194 reload_inheritance_insn[r]
5195 = reg_reloaded_insn[i];
5196 reload_spill_index[r] = i;
5197 for (k = 0; k < nr; k++)
5198 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5206 /* Here's another way to see if the value is already lying around. */
5208 && reload_in[r] != 0
5209 && ! reload_inherited[r]
5210 && reload_out[r] == 0
5211 && (CONSTANT_P (reload_in[r])
5212 || GET_CODE (reload_in[r]) == PLUS
5213 || GET_CODE (reload_in[r]) == REG
5214 || GET_CODE (reload_in[r]) == MEM)
5215 && (reload_nregs[r] == max_group_size
5216 || ! reg_classes_intersect_p (reload_reg_class[r], group_class)))
5219 = find_equiv_reg (reload_in[r], insn, reload_reg_class[r],
5220 -1, NULL_PTR, 0, reload_mode[r]);
5225 if (GET_CODE (equiv) == REG)
5226 regno = REGNO (equiv);
5227 else if (GET_CODE (equiv) == SUBREG)
5229 /* This must be a SUBREG of a hard register.
5230 Make a new REG since this might be used in an
5231 address and not all machines support SUBREGs
5233 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
5234 equiv = gen_rtx (REG, reload_mode[r], regno);
5240 /* If we found a spill reg, reject it unless it is free
5241 and of the desired class. */
5243 && ((spill_reg_order[regno] >= 0
5244 && ! reload_reg_free_before_p (regno, reload_opnum[r],
5245 reload_when_needed[r]))
5246 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5250 if (equiv != 0 && TEST_HARD_REG_BIT (reload_reg_used_at_all, regno))
5253 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5256 /* We found a register that contains the value we need.
5257 If this register is the same as an `earlyclobber' operand
5258 of the current insn, just mark it as a place to reload from
5259 since we can't use it as the reload register itself. */
5262 for (i = 0; i < n_earlyclobbers; i++)
5263 if (reg_overlap_mentioned_for_reload_p (equiv,
5264 reload_earlyclobbers[i]))
5266 reload_override_in[r] = equiv;
5271 /* JRV: If the equiv register we have found is explicitly
5272 clobbered in the current insn, mark but don't use, as above. */
5274 if (equiv != 0 && regno_clobbered_p (regno, insn))
5276 reload_override_in[r] = equiv;
5280 /* If we found an equivalent reg, say no code need be generated
5281 to load it, and use it as our reload reg. */
5282 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5284 reload_reg_rtx[r] = equiv;
5285 reload_inherited[r] = 1;
5286 /* If it is a spill reg,
5287 mark the spill reg as in use for this insn. */
5288 i = spill_reg_order[regno];
5291 int nr = HARD_REGNO_NREGS (regno, reload_mode[r]);
5293 mark_reload_reg_in_use (regno, reload_opnum[r],
5294 reload_when_needed[r],
5296 for (k = 0; k < nr; k++)
5297 SET_HARD_REG_BIT (reload_reg_used_for_inherit, regno + k);
5302 /* If we found a register to use already, or if this is an optional
5303 reload, we are done. */
5304 if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0)
5307 #if 0 /* No longer needed for correct operation. Might or might not
5308 give better code on the average. Want to experiment? */
5310 /* See if there is a later reload that has a class different from our
5311 class that intersects our class or that requires less register
5312 than our reload. If so, we must allocate a register to this
5313 reload now, since that reload might inherit a previous reload
5314 and take the only available register in our class. Don't do this
5315 for optional reloads since they will force all previous reloads
5316 to be allocated. Also don't do this for reloads that have been
5319 for (i = j + 1; i < n_reloads; i++)
5321 int s = reload_order[i];
5323 if ((reload_in[s] == 0 && reload_out[s] == 0
5324 && ! reload_secondary_p[s])
5325 || reload_optional[s])
5328 if ((reload_reg_class[s] != reload_reg_class[r]
5329 && reg_classes_intersect_p (reload_reg_class[r],
5330 reload_reg_class[s]))
5331 || reload_nregs[s] < reload_nregs[r])
5338 allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance);
5342 /* Now allocate reload registers for anything non-optional that
5343 didn't get one yet. */
5344 for (j = 0; j < n_reloads; j++)
5346 register int r = reload_order[j];
5348 /* Ignore reloads that got marked inoperative. */
5349 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
5352 /* Skip reloads that already have a register allocated or are
5354 if (reload_reg_rtx[r] != 0 || reload_optional[r])
5357 if (! allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance))
5361 /* If that loop got all the way, we have won. */
5366 /* Loop around and try without any inheritance. */
5367 /* First undo everything done by the failed attempt
5368 to allocate with inheritance. */
5369 bcopy (save_reload_reg_rtx, reload_reg_rtx, sizeof reload_reg_rtx);
5370 bcopy (save_reload_inherited, reload_inherited, sizeof reload_inherited);
5371 bcopy (save_reload_inheritance_insn, reload_inheritance_insn,
5372 sizeof reload_inheritance_insn);
5373 bcopy (save_reload_override_in, reload_override_in,
5374 sizeof reload_override_in);
5375 bcopy (save_reload_spill_index, reload_spill_index,
5376 sizeof reload_spill_index);
5377 COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used);
5378 COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all);
5379 COPY_HARD_REG_SET (reload_reg_used_in_op_addr,
5380 save_reload_reg_used_in_op_addr);
5381 COPY_HARD_REG_SET (reload_reg_used_in_insn,
5382 save_reload_reg_used_in_insn);
5383 COPY_HARD_REG_SET (reload_reg_used_in_other_addr,
5384 save_reload_reg_used_in_other_addr);
5386 for (i = 0; i < reload_n_operands; i++)
5388 COPY_HARD_REG_SET (reload_reg_used_in_input[i],
5389 save_reload_reg_used_in_input[i]);
5390 COPY_HARD_REG_SET (reload_reg_used_in_output[i],
5391 save_reload_reg_used_in_output[i]);
5392 COPY_HARD_REG_SET (reload_reg_used_in_input_addr[i],
5393 save_reload_reg_used_in_input_addr[i]);
5394 COPY_HARD_REG_SET (reload_reg_used_in_output_addr[i],
5395 save_reload_reg_used_in_output_addr[i]);
5399 /* If we thought we could inherit a reload, because it seemed that
5400 nothing else wanted the same reload register earlier in the insn,
5401 verify that assumption, now that all reloads have been assigned. */
5403 for (j = 0; j < n_reloads; j++)
5405 register int r = reload_order[j];
5407 if (reload_inherited[r] && reload_reg_rtx[r] != 0
5408 && ! reload_reg_free_before_p (true_regnum (reload_reg_rtx[r]),
5410 reload_when_needed[r]))
5411 reload_inherited[r] = 0;
5413 /* If we found a better place to reload from,
5414 validate it in the same fashion, if it is a reload reg. */
5415 if (reload_override_in[r]
5416 && (GET_CODE (reload_override_in[r]) == REG
5417 || GET_CODE (reload_override_in[r]) == SUBREG))
5419 int regno = true_regnum (reload_override_in[r]);
5420 if (spill_reg_order[regno] >= 0
5421 && ! reload_reg_free_before_p (regno, reload_opnum[r],
5422 reload_when_needed[r]))
5423 reload_override_in[r] = 0;
5427 /* Now that reload_override_in is known valid,
5428 actually override reload_in. */
5429 for (j = 0; j < n_reloads; j++)
5430 if (reload_override_in[j])
5431 reload_in[j] = reload_override_in[j];
5433 /* If this reload won't be done because it has been cancelled or is
5434 optional and not inherited, clear reload_reg_rtx so other
5435 routines (such as subst_reloads) don't get confused. */
5436 for (j = 0; j < n_reloads; j++)
5437 if (reload_reg_rtx[j] != 0
5438 && ((reload_optional[j] && ! reload_inherited[j])
5439 || (reload_in[j] == 0 && reload_out[j] == 0
5440 && ! reload_secondary_p[j])))
5442 int regno = true_regnum (reload_reg_rtx[j]);
5444 if (spill_reg_order[regno] >= 0)
5445 clear_reload_reg_in_use (regno, reload_opnum[j],
5446 reload_when_needed[j], reload_mode[j]);
5447 reload_reg_rtx[j] = 0;
5450 /* Record which pseudos and which spill regs have output reloads. */
5451 for (j = 0; j < n_reloads; j++)
5453 register int r = reload_order[j];
5455 i = reload_spill_index[r];
5457 /* I is nonneg if this reload used one of the spill regs.
5458 If reload_reg_rtx[r] is 0, this is an optional reload
5459 that we opted to ignore. */
5460 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG
5461 && reload_reg_rtx[r] != 0)
5463 register int nregno = REGNO (reload_out[r]);
5466 if (nregno < FIRST_PSEUDO_REGISTER)
5467 nr = HARD_REGNO_NREGS (nregno, reload_mode[r]);
5470 reg_has_output_reload[nregno + nr] = 1;
5474 nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
5476 SET_HARD_REG_BIT (reg_is_output_reload, spill_regs[i] + nr);
5479 if (reload_when_needed[r] != RELOAD_OTHER
5480 && reload_when_needed[r] != RELOAD_FOR_OUTPUT
5481 && reload_when_needed[r] != RELOAD_FOR_INSN)
5487 /* If SMALL_REGISTER_CLASSES are defined, we may not have merged two
5488 reloads of the same item for fear that we might not have enough reload
5489 registers. However, normally they will get the same reload register
5490 and hence actually need not be loaded twice.
5492 Here we check for the most common case of this phenomenon: when we have
5493 a number of reloads for the same object, each of which were allocated
5494 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5495 reload, and is not modified in the insn itself. If we find such,
5496 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5497 This will not increase the number of spill registers needed and will
5498 prevent redundant code. */
5500 #ifdef SMALL_REGISTER_CLASSES
5503 merge_assigned_reloads (insn)
5508 /* Scan all the reloads looking for ones that only load values and
5509 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5510 assigned and not modified by INSN. */
5512 for (i = 0; i < n_reloads; i++)
5514 if (reload_in[i] == 0 || reload_when_needed[i] == RELOAD_OTHER
5515 || reload_out[i] != 0 || reload_reg_rtx[i] == 0
5516 || reg_set_p (reload_reg_rtx[i], insn))
5519 /* Look at all other reloads. Ensure that the only use of this
5520 reload_reg_rtx is in a reload that just loads the same value
5521 as we do. Note that any secondary reloads must be of the identical
5522 class since the values, modes, and result registers are the
5523 same, so we need not do anything with any secondary reloads. */
5525 for (j = 0; j < n_reloads; j++)
5527 if (i == j || reload_reg_rtx[j] == 0
5528 || ! reg_overlap_mentioned_p (reload_reg_rtx[j],
5532 /* If the reload regs aren't exactly the same (e.g, different modes)
5533 or if the values are different, we can't merge anything with this
5536 if (! rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
5537 || reload_out[j] != 0 || reload_in[j] == 0
5538 || ! rtx_equal_p (reload_in[i], reload_in[j]))
5542 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5543 we, in fact, found any matching reloads. */
5547 for (j = 0; j < n_reloads; j++)
5548 if (i != j && reload_reg_rtx[j] != 0
5549 && rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j]))
5551 reload_when_needed[i] = RELOAD_OTHER;
5553 transfer_replacements (i, j);
5556 /* If this is now RELOAD_OTHER, look for any reloads that load
5557 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
5558 if they were for inputs, RELOAD_OTHER for outputs. Note that
5559 this test is equivalent to looking for reloads for this operand
5562 if (reload_when_needed[i] == RELOAD_OTHER)
5563 for (j = 0; j < n_reloads; j++)
5564 if (reload_in[j] != 0
5565 && reload_when_needed[i] != RELOAD_OTHER
5566 && reg_overlap_mentioned_for_reload_p (reload_in[j],
5568 reload_when_needed[j]
5569 = reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS
5570 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER;
5574 #endif /* SMALL_RELOAD_CLASSES */
5576 /* Output insns to reload values in and out of the chosen reload regs. */
5579 emit_reload_insns (insn)
5583 rtx input_reload_insns[MAX_RECOG_OPERANDS];
5584 rtx other_input_address_reload_insns = 0;
5585 rtx other_input_reload_insns = 0;
5586 rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
5587 rtx output_reload_insns[MAX_RECOG_OPERANDS];
5588 rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
5589 rtx operand_reload_insns = 0;
5590 rtx following_insn = NEXT_INSN (insn);
5591 rtx before_insn = insn;
5593 /* Values to be put in spill_reg_store are put here first. */
5594 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
5596 for (j = 0; j < reload_n_operands; j++)
5597 input_reload_insns[j] = input_address_reload_insns[j]
5598 = output_reload_insns[j] = output_address_reload_insns[j] = 0;
5600 /* If this is a CALL_INSN preceded by USE insns, any reload insns
5601 must go in front of the first USE insn, not in front of INSN. */
5603 if (GET_CODE (insn) == CALL_INSN && GET_CODE (PREV_INSN (insn)) == INSN
5604 && GET_CODE (PATTERN (PREV_INSN (insn))) == USE)
5605 while (GET_CODE (PREV_INSN (before_insn)) == INSN
5606 && GET_CODE (PATTERN (PREV_INSN (before_insn))) == USE)
5607 before_insn = PREV_INSN (before_insn);
5609 /* If INSN is followed by any CLOBBER insns made by find_reloads,
5610 put our reloads after them since they may otherwise be
5613 while (GET_CODE (following_insn) == INSN
5614 && GET_MODE (following_insn) == DImode
5615 && GET_CODE (PATTERN (following_insn)) == CLOBBER
5616 && NEXT_INSN (following_insn) != 0)
5617 following_insn = NEXT_INSN (following_insn);
5619 /* Now output the instructions to copy the data into and out of the
5620 reload registers. Do these in the order that the reloads were reported,
5621 since reloads of base and index registers precede reloads of operands
5622 and the operands may need the base and index registers reloaded. */
5624 for (j = 0; j < n_reloads; j++)
5627 rtx oldequiv_reg = 0;
5631 if (old != 0 && ! reload_inherited[j]
5632 && ! rtx_equal_p (reload_reg_rtx[j], old)
5633 && reload_reg_rtx[j] != 0)
5635 register rtx reloadreg = reload_reg_rtx[j];
5637 enum machine_mode mode;
5640 /* Determine the mode to reload in.
5641 This is very tricky because we have three to choose from.
5642 There is the mode the insn operand wants (reload_inmode[J]).
5643 There is the mode of the reload register RELOADREG.
5644 There is the intrinsic mode of the operand, which we could find
5645 by stripping some SUBREGs.
5646 It turns out that RELOADREG's mode is irrelevant:
5647 we can change that arbitrarily.
5649 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
5650 then the reload reg may not support QImode moves, so use SImode.
5651 If foo is in memory due to spilling a pseudo reg, this is safe,
5652 because the QImode value is in the least significant part of a
5653 slot big enough for a SImode. If foo is some other sort of
5654 memory reference, then it is impossible to reload this case,
5655 so previous passes had better make sure this never happens.
5657 Then consider a one-word union which has SImode and one of its
5658 members is a float, being fetched as (SUBREG:SF union:SI).
5659 We must fetch that as SFmode because we could be loading into
5660 a float-only register. In this case OLD's mode is correct.
5662 Consider an immediate integer: it has VOIDmode. Here we need
5663 to get a mode from something else.
5665 In some cases, there is a fourth mode, the operand's
5666 containing mode. If the insn specifies a containing mode for
5667 this operand, it overrides all others.
5669 I am not sure whether the algorithm here is always right,
5670 but it does the right things in those cases. */
5672 mode = GET_MODE (old);
5673 if (mode == VOIDmode)
5674 mode = reload_inmode[j];
5676 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5677 /* If we need a secondary register for this operation, see if
5678 the value is already in a register in that class. Don't
5679 do this if the secondary register will be used as a scratch
5682 if (reload_secondary_in_reload[j] >= 0
5683 && reload_secondary_in_icode[j] == CODE_FOR_nothing
5686 = find_equiv_reg (old, insn,
5687 reload_reg_class[reload_secondary_in_reload[j]],
5688 -1, NULL_PTR, 0, mode);
5691 /* If reloading from memory, see if there is a register
5692 that already holds the same value. If so, reload from there.
5693 We can pass 0 as the reload_reg_p argument because
5694 any other reload has either already been emitted,
5695 in which case find_equiv_reg will see the reload-insn,
5696 or has yet to be emitted, in which case it doesn't matter
5697 because we will use this equiv reg right away. */
5699 if (oldequiv == 0 && optimize
5700 && (GET_CODE (old) == MEM
5701 || (GET_CODE (old) == REG
5702 && REGNO (old) >= FIRST_PSEUDO_REGISTER
5703 && reg_renumber[REGNO (old)] < 0)))
5704 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
5705 -1, NULL_PTR, 0, mode);
5709 int regno = true_regnum (oldequiv);
5711 /* If OLDEQUIV is a spill register, don't use it for this
5712 if any other reload needs it at an earlier stage of this insn
5713 or at this stage. */
5714 if (spill_reg_order[regno] >= 0
5715 && (! reload_reg_free_p (regno, reload_opnum[j],
5716 reload_when_needed[j])
5717 || ! reload_reg_free_before_p (regno, reload_opnum[j],
5718 reload_when_needed[j])))
5721 /* If OLDEQUIV is not a spill register,
5722 don't use it if any other reload wants it. */
5723 if (spill_reg_order[regno] < 0)
5726 for (k = 0; k < n_reloads; k++)
5727 if (reload_reg_rtx[k] != 0 && k != j
5728 && reg_overlap_mentioned_for_reload_p (reload_reg_rtx[k],
5736 /* If it is no cheaper to copy from OLDEQUIV into the
5737 reload register than it would be to move from memory,
5738 don't use it. Likewise, if we need a secondary register
5742 && ((REGNO_REG_CLASS (regno) != reload_reg_class[j]
5743 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
5744 reload_reg_class[j])
5745 >= MEMORY_MOVE_COST (mode)))
5746 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5747 || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
5751 #ifdef SECONDARY_MEMORY_NEEDED
5752 || SECONDARY_MEMORY_NEEDED (reload_reg_class[j],
5753 REGNO_REG_CLASS (regno),
5762 else if (GET_CODE (oldequiv) == REG)
5763 oldequiv_reg = oldequiv;
5764 else if (GET_CODE (oldequiv) == SUBREG)
5765 oldequiv_reg = SUBREG_REG (oldequiv);
5767 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
5768 then load RELOADREG from OLDEQUIV. Note that we cannot use
5769 gen_lowpart_common since it can do the wrong thing when
5770 RELOADREG has a multi-word mode. Note that RELOADREG
5771 must always be a REG here. */
5773 if (GET_MODE (reloadreg) != mode)
5774 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
5775 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
5776 oldequiv = SUBREG_REG (oldequiv);
5777 if (GET_MODE (oldequiv) != VOIDmode
5778 && mode != GET_MODE (oldequiv))
5779 oldequiv = gen_rtx (SUBREG, mode, oldequiv, 0);
5781 /* Switch to the right place to emit the reload insns. */
5782 switch (reload_when_needed[j])
5785 where = &other_input_reload_insns;
5787 case RELOAD_FOR_INPUT:
5788 where = &input_reload_insns[reload_opnum[j]];
5790 case RELOAD_FOR_INPUT_ADDRESS:
5791 where = &input_address_reload_insns[reload_opnum[j]];
5793 case RELOAD_FOR_OUTPUT_ADDRESS:
5794 where = &output_address_reload_insns[reload_opnum[j]];
5796 case RELOAD_FOR_OPERAND_ADDRESS:
5797 where = &operand_reload_insns;
5799 case RELOAD_FOR_OTHER_ADDRESS:
5800 where = &other_input_address_reload_insns;
5806 push_to_sequence (*where);
5809 /* Auto-increment addresses must be reloaded in a special way. */
5810 if (GET_CODE (oldequiv) == POST_INC
5811 || GET_CODE (oldequiv) == POST_DEC
5812 || GET_CODE (oldequiv) == PRE_INC
5813 || GET_CODE (oldequiv) == PRE_DEC)
5815 /* We are not going to bother supporting the case where a
5816 incremented register can't be copied directly from
5817 OLDEQUIV since this seems highly unlikely. */
5818 if (reload_secondary_in_reload[j] >= 0)
5820 /* Prevent normal processing of this reload. */
5822 /* Output a special code sequence for this case. */
5823 inc_for_reload (reloadreg, oldequiv, reload_inc[j]);
5826 /* If we are reloading a pseudo-register that was set by the previous
5827 insn, see if we can get rid of that pseudo-register entirely
5828 by redirecting the previous insn into our reload register. */
5830 else if (optimize && GET_CODE (old) == REG
5831 && REGNO (old) >= FIRST_PSEUDO_REGISTER
5832 && dead_or_set_p (insn, old)
5833 /* This is unsafe if some other reload
5834 uses the same reg first. */
5835 && reload_reg_free_before_p (REGNO (reloadreg),
5837 reload_when_needed[j]))
5839 rtx temp = PREV_INSN (insn);
5840 while (temp && GET_CODE (temp) == NOTE)
5841 temp = PREV_INSN (temp);
5843 && GET_CODE (temp) == INSN
5844 && GET_CODE (PATTERN (temp)) == SET
5845 && SET_DEST (PATTERN (temp)) == old
5846 /* Make sure we can access insn_operand_constraint. */
5847 && asm_noperands (PATTERN (temp)) < 0
5848 /* This is unsafe if prev insn rejects our reload reg. */
5849 && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0],
5851 /* This is unsafe if operand occurs more than once in current
5852 insn. Perhaps some occurrences aren't reloaded. */
5853 && count_occurrences (PATTERN (insn), old) == 1
5854 /* Don't risk splitting a matching pair of operands. */
5855 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
5857 /* Store into the reload register instead of the pseudo. */
5858 SET_DEST (PATTERN (temp)) = reloadreg;
5859 /* If these are the only uses of the pseudo reg,
5860 pretend for GDB it lives in the reload reg we used. */
5861 if (reg_n_deaths[REGNO (old)] == 1
5862 && reg_n_sets[REGNO (old)] == 1)
5864 reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]);
5865 alter_reg (REGNO (old), -1);
5871 /* We can't do that, so output an insn to load RELOADREG. */
5875 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5876 rtx second_reload_reg = 0;
5877 enum insn_code icode;
5879 /* If we have a secondary reload, pick up the secondary register
5880 and icode, if any. If OLDEQUIV and OLD are different or
5881 if this is an in-out reload, recompute whether or not we
5882 still need a secondary register and what the icode should
5883 be. If we still need a secondary register and the class or
5884 icode is different, go back to reloading from OLD if using
5885 OLDEQUIV means that we got the wrong type of register. We
5886 cannot have different class or icode due to an in-out reload
5887 because we don't make such reloads when both the input and
5888 output need secondary reload registers. */
5890 if (reload_secondary_in_reload[j] >= 0)
5892 int secondary_reload = reload_secondary_in_reload[j];
5893 rtx real_oldequiv = oldequiv;
5896 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
5897 and similarly for OLD.
5898 See comments in get_secondary_reload in reload.c. */
5899 if (GET_CODE (oldequiv) == REG
5900 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
5901 && reg_equiv_mem[REGNO (oldequiv)] != 0)
5902 real_oldequiv = reg_equiv_mem[REGNO (oldequiv)];
5904 if (GET_CODE (old) == REG
5905 && REGNO (old) >= FIRST_PSEUDO_REGISTER
5906 && reg_equiv_mem[REGNO (old)] != 0)
5907 real_old = reg_equiv_mem[REGNO (old)];
5909 second_reload_reg = reload_reg_rtx[secondary_reload];
5910 icode = reload_secondary_in_icode[j];
5912 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
5913 || (reload_in[j] != 0 && reload_out[j] != 0))
5915 enum reg_class new_class
5916 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
5917 mode, real_oldequiv);
5919 if (new_class == NO_REGS)
5920 second_reload_reg = 0;
5923 enum insn_code new_icode;
5924 enum machine_mode new_mode;
5926 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
5927 REGNO (second_reload_reg)))
5928 oldequiv = old, real_oldequiv = real_old;
5931 new_icode = reload_in_optab[(int) mode];
5932 if (new_icode != CODE_FOR_nothing
5933 && ((insn_operand_predicate[(int) new_icode][0]
5934 && ! ((*insn_operand_predicate[(int) new_icode][0])
5936 || (insn_operand_predicate[(int) new_icode][1]
5937 && ! ((*insn_operand_predicate[(int) new_icode][1])
5938 (real_oldequiv, mode)))))
5939 new_icode = CODE_FOR_nothing;
5941 if (new_icode == CODE_FOR_nothing)
5944 new_mode = insn_operand_mode[(int) new_icode][2];
5946 if (GET_MODE (second_reload_reg) != new_mode)
5948 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
5950 oldequiv = old, real_oldequiv = real_old;
5953 = gen_rtx (REG, new_mode,
5954 REGNO (second_reload_reg));
5960 /* If we still need a secondary reload register, check
5961 to see if it is being used as a scratch or intermediate
5962 register and generate code appropriately. If we need
5963 a scratch register, use REAL_OLDEQUIV since the form of
5964 the insn may depend on the actual address if it is
5967 if (second_reload_reg)
5969 if (icode != CODE_FOR_nothing)
5971 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
5972 second_reload_reg));
5977 /* See if we need a scratch register to load the
5978 intermediate register (a tertiary reload). */
5979 enum insn_code tertiary_icode
5980 = reload_secondary_in_icode[secondary_reload];
5982 if (tertiary_icode != CODE_FOR_nothing)
5984 rtx third_reload_reg
5985 = reload_reg_rtx[reload_secondary_in_reload[secondary_reload]];
5987 emit_insn ((GEN_FCN (tertiary_icode)
5988 (second_reload_reg, real_oldequiv,
5989 third_reload_reg)));
5992 gen_input_reload (second_reload_reg, oldequiv,
5994 reload_when_needed[j]);
5996 oldequiv = second_reload_reg;
6002 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6003 gen_input_reload (reloadreg, oldequiv, reload_opnum[j],
6004 reload_when_needed[j]);
6006 #if defined(SECONDARY_INPUT_RELOAD_CLASS) && defined(PRESERVE_DEATH_INFO_REGNO_P)
6007 /* We may have to make a REG_DEAD note for the secondary reload
6008 register in the insns we just made. Find the last insn that
6009 mentioned the register. */
6010 if (! special && second_reload_reg
6011 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reload_reg)))
6015 for (prev = get_last_insn (); prev;
6016 prev = PREV_INSN (prev))
6017 if (GET_RTX_CLASS (GET_CODE (prev) == 'i')
6018 && reg_overlap_mentioned_for_reload_p (second_reload_reg,
6021 REG_NOTES (prev) = gen_rtx (EXPR_LIST, REG_DEAD,
6030 /* End this sequence. */
6031 *where = get_insns ();
6035 /* Add a note saying the input reload reg
6036 dies in this insn, if anyone cares. */
6037 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6039 && reload_reg_rtx[j] != old
6040 && reload_reg_rtx[j] != 0
6041 && reload_out[j] == 0
6042 && ! reload_inherited[j]
6043 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j])))
6045 register rtx reloadreg = reload_reg_rtx[j];
6048 /* We can't abort here because we need to support this for sched.c.
6049 It's not terrible to miss a REG_DEAD note, but we should try
6050 to figure out how to do this correctly. */
6051 /* The code below is incorrect for address-only reloads. */
6052 if (reload_when_needed[j] != RELOAD_OTHER
6053 && reload_when_needed[j] != RELOAD_FOR_INPUT)
6057 /* Add a death note to this insn, for an input reload. */
6059 if ((reload_when_needed[j] == RELOAD_OTHER
6060 || reload_when_needed[j] == RELOAD_FOR_INPUT)
6061 && ! dead_or_set_p (insn, reloadreg))
6063 = gen_rtx (EXPR_LIST, REG_DEAD,
6064 reloadreg, REG_NOTES (insn));
6067 /* When we inherit a reload, the last marked death of the reload reg
6068 may no longer really be a death. */
6069 if (reload_reg_rtx[j] != 0
6070 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j]))
6071 && reload_inherited[j])
6073 /* Handle inheriting an output reload.
6074 Remove the death note from the output reload insn. */
6075 if (reload_spill_index[j] >= 0
6076 && GET_CODE (reload_in[j]) == REG
6077 && spill_reg_store[reload_spill_index[j]] != 0
6078 && find_regno_note (spill_reg_store[reload_spill_index[j]],
6079 REG_DEAD, REGNO (reload_reg_rtx[j])))
6080 remove_death (REGNO (reload_reg_rtx[j]),
6081 spill_reg_store[reload_spill_index[j]]);
6082 /* Likewise for input reloads that were inherited. */
6083 else if (reload_spill_index[j] >= 0
6084 && GET_CODE (reload_in[j]) == REG
6085 && spill_reg_store[reload_spill_index[j]] == 0
6086 && reload_inheritance_insn[j] != 0
6087 && find_regno_note (reload_inheritance_insn[j], REG_DEAD,
6088 REGNO (reload_reg_rtx[j])))
6089 remove_death (REGNO (reload_reg_rtx[j]),
6090 reload_inheritance_insn[j]);
6095 /* We got this register from find_equiv_reg.
6096 Search back for its last death note and get rid of it.
6097 But don't search back too far.
6098 Don't go past a place where this reg is set,
6099 since a death note before that remains valid. */
6100 for (prev = PREV_INSN (insn);
6101 prev && GET_CODE (prev) != CODE_LABEL;
6102 prev = PREV_INSN (prev))
6103 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
6104 && dead_or_set_p (prev, reload_reg_rtx[j]))
6106 if (find_regno_note (prev, REG_DEAD,
6107 REGNO (reload_reg_rtx[j])))
6108 remove_death (REGNO (reload_reg_rtx[j]), prev);
6114 /* We might have used find_equiv_reg above to choose an alternate
6115 place from which to reload. If so, and it died, we need to remove
6116 that death and move it to one of the insns we just made. */
6118 if (oldequiv_reg != 0
6119 && PRESERVE_DEATH_INFO_REGNO_P (true_regnum (oldequiv_reg)))
6123 for (prev = PREV_INSN (insn); prev && GET_CODE (prev) != CODE_LABEL;
6124 prev = PREV_INSN (prev))
6125 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
6126 && dead_or_set_p (prev, oldequiv_reg))
6128 if (find_regno_note (prev, REG_DEAD, REGNO (oldequiv_reg)))
6130 for (prev1 = this_reload_insn;
6131 prev1; prev1 = PREV_INSN (prev1))
6132 if (GET_RTX_CLASS (GET_CODE (prev1) == 'i')
6133 && reg_overlap_mentioned_for_reload_p (oldequiv_reg,
6136 REG_NOTES (prev1) = gen_rtx (EXPR_LIST, REG_DEAD,
6141 remove_death (REGNO (oldequiv_reg), prev);
6148 /* If we are reloading a register that was recently stored in with an
6149 output-reload, see if we can prove there was
6150 actually no need to store the old value in it. */
6152 if (optimize && reload_inherited[j] && reload_spill_index[j] >= 0
6153 && reload_in[j] != 0
6154 && GET_CODE (reload_in[j]) == REG
6156 /* There doesn't seem to be any reason to restrict this to pseudos
6157 and doing so loses in the case where we are copying from a
6158 register of the wrong class. */
6159 && REGNO (reload_in[j]) >= FIRST_PSEUDO_REGISTER
6161 && spill_reg_store[reload_spill_index[j]] != 0
6162 /* This is unsafe if some other reload uses the same reg first. */
6163 && reload_reg_free_before_p (spill_regs[reload_spill_index[j]],
6164 reload_opnum[j], reload_when_needed[j])
6165 && dead_or_set_p (insn, reload_in[j])
6166 /* This is unsafe if operand occurs more than once in current
6167 insn. Perhaps some occurrences weren't reloaded. */
6168 && count_occurrences (PATTERN (insn), reload_in[j]) == 1)
6169 delete_output_reload (insn, j,
6170 spill_reg_store[reload_spill_index[j]]);
6172 /* Input-reloading is done. Now do output-reloading,
6173 storing the value from the reload-register after the main insn
6174 if reload_out[j] is nonzero.
6176 ??? At some point we need to support handling output reloads of
6177 JUMP_INSNs or insns that set cc0. */
6178 old = reload_out[j];
6180 && reload_reg_rtx[j] != old
6181 && reload_reg_rtx[j] != 0)
6183 register rtx reloadreg = reload_reg_rtx[j];
6184 register rtx second_reloadreg = 0;
6186 enum machine_mode mode;
6189 /* An output operand that dies right away does need a reload,
6190 but need not be copied from it. Show the new location in the
6192 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6193 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6195 XEXP (note, 0) = reload_reg_rtx[j];
6198 else if (GET_CODE (old) == SCRATCH)
6199 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6200 but we don't want to make an output reload. */
6204 /* Strip off of OLD any size-increasing SUBREGs such as
6205 (SUBREG:SI foo:QI 0). */
6207 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
6208 && (GET_MODE_SIZE (GET_MODE (old))
6209 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
6210 old = SUBREG_REG (old);
6213 /* If is a JUMP_INSN, we can't support output reloads yet. */
6214 if (GET_CODE (insn) == JUMP_INSN)
6217 push_to_sequence (output_reload_insns[reload_opnum[j]]);
6219 /* Determine the mode to reload in.
6220 See comments above (for input reloading). */
6222 mode = GET_MODE (old);
6223 if (mode == VOIDmode)
6225 /* VOIDmode should never happen for an output. */
6226 if (asm_noperands (PATTERN (insn)) < 0)
6227 /* It's the compiler's fault. */
6229 error_for_asm (insn, "output operand is constant in `asm'");
6230 /* Prevent crash--use something we know is valid. */
6232 old = gen_rtx (REG, mode, REGNO (reloadreg));
6235 if (GET_MODE (reloadreg) != mode)
6236 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
6238 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6240 /* If we need two reload regs, set RELOADREG to the intermediate
6241 one, since it will be stored into OUT. We might need a secondary
6242 register only for an input reload, so check again here. */
6244 if (reload_secondary_out_reload[j] >= 0)
6248 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6249 && reg_equiv_mem[REGNO (old)] != 0)
6250 real_old = reg_equiv_mem[REGNO (old)];
6252 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j],
6256 second_reloadreg = reloadreg;
6257 reloadreg = reload_reg_rtx[reload_secondary_out_reload[j]];
6259 /* See if RELOADREG is to be used as a scratch register
6260 or as an intermediate register. */
6261 if (reload_secondary_out_icode[j] != CODE_FOR_nothing)
6263 emit_insn ((GEN_FCN (reload_secondary_out_icode[j])
6264 (real_old, second_reloadreg, reloadreg)));
6269 /* See if we need both a scratch and intermediate reload
6271 int secondary_reload = reload_secondary_out_reload[j];
6272 enum insn_code tertiary_icode
6273 = reload_secondary_out_icode[secondary_reload];
6276 if (GET_MODE (reloadreg) != mode)
6277 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
6279 if (tertiary_icode != CODE_FOR_nothing)
6282 = reload_reg_rtx[reload_secondary_out_reload[secondary_reload]];
6283 pat = (GEN_FCN (tertiary_icode)
6284 (reloadreg, second_reloadreg, third_reloadreg));
6286 #ifdef SECONDARY_MEMORY_NEEDED
6287 /* If we need a memory location to do the move, do it that way. */
6288 else if (GET_CODE (reloadreg) == REG
6289 && REGNO (reloadreg) < FIRST_PSEUDO_REGISTER
6290 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (reloadreg)),
6291 REGNO_REG_CLASS (REGNO (second_reloadreg)),
6292 GET_MODE (second_reloadreg)))
6294 /* Get the memory to use and rewrite both registers
6297 = get_secondary_mem (reloadreg,
6298 GET_MODE (second_reloadreg),
6300 reload_when_needed[j]);
6303 if (GET_MODE (loc) != GET_MODE (second_reloadreg))
6304 second_reloadreg = gen_rtx (REG, GET_MODE (loc),
6305 REGNO (second_reloadreg));
6307 if (GET_MODE (loc) != GET_MODE (reloadreg))
6308 tmp_reloadreg = gen_rtx (REG, GET_MODE (loc),
6311 tmp_reloadreg = reloadreg;
6313 emit_move_insn (loc, second_reloadreg);
6314 pat = gen_move_insn (tmp_reloadreg, loc);
6318 pat = gen_move_insn (reloadreg, second_reloadreg);
6326 /* Output the last reload insn. */
6329 #ifdef SECONDARY_MEMORY_NEEDED
6330 /* If we need a memory location to do the move, do it that way. */
6331 if (GET_CODE (old) == REG && REGNO (old) < FIRST_PSEUDO_REGISTER
6332 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (old)),
6333 REGNO_REG_CLASS (REGNO (reloadreg)),
6334 GET_MODE (reloadreg)))
6336 /* Get the memory to use and rewrite both registers to
6338 rtx loc = get_secondary_mem (old, GET_MODE (reloadreg),
6340 reload_when_needed[j]);
6342 if (GET_MODE (loc) != GET_MODE (reloadreg))
6343 reloadreg = gen_rtx (REG, GET_MODE (loc),
6346 if (GET_MODE (loc) != GET_MODE (old))
6347 old = gen_rtx (REG, GET_MODE (loc), REGNO (old));
6349 emit_insn (gen_move_insn (loc, reloadreg));
6350 emit_insn (gen_move_insn (old, loc));
6354 emit_insn (gen_move_insn (old, reloadreg));
6357 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6358 /* If final will look at death notes for this reg,
6359 put one on the last output-reload insn to use it. Similarly
6360 for any secondary register. */
6361 if (PRESERVE_DEATH_INFO_REGNO_P (REGNO (reloadreg)))
6362 for (p = get_last_insn (); p; p = PREV_INSN (p))
6363 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
6364 && reg_overlap_mentioned_for_reload_p (reloadreg,
6366 REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
6367 reloadreg, REG_NOTES (p));
6369 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6371 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reloadreg)))
6372 for (p = get_last_insn (); p; p = PREV_INSN (p))
6373 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
6374 && reg_overlap_mentioned_for_reload_p (second_reloadreg,
6376 REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
6377 second_reloadreg, REG_NOTES (p));
6380 /* Look at all insns we emitted, just to be safe. */
6381 for (p = get_insns (); p; p = NEXT_INSN (p))
6382 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
6384 /* If this output reload doesn't come from a spill reg,
6385 clear any memory of reloaded copies of the pseudo reg.
6386 If this output reload comes from a spill reg,
6387 reg_has_output_reload will make this do nothing. */
6388 note_stores (PATTERN (p), forget_old_reloads_1);
6390 if (reg_mentioned_p (reload_reg_rtx[j], PATTERN (p)))
6394 output_reload_insns[reload_opnum[j]] = get_insns ();
6399 if (reload_spill_index[j] >= 0)
6400 new_spill_reg_store[reload_spill_index[j]] = store_insn;
6403 /* Now write all the insns we made for reloads in the order expected by
6404 the allocation functions. Prior to the insn being reloaded, we write
6405 the following reloads:
6407 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6409 RELOAD_OTHER reloads.
6411 For each operand, any RELOAD_FOR_INPUT_ADDRESS reloads followed by
6412 the RELOAD_FOR_INPUT reload for the operand.
6414 RELOAD_FOR_OPERAND_ADDRESS reloads.
6416 After the insn being reloaded, we write the following:
6418 For each operand, any RELOAD_FOR_OUTPUT_ADDRESS reload followed by
6419 the RELOAD_FOR_OUTPUT reload for that operand. */
6421 emit_insns_before (other_input_address_reload_insns, before_insn);
6422 emit_insns_before (other_input_reload_insns, before_insn);
6424 for (j = 0; j < reload_n_operands; j++)
6426 emit_insns_before (input_address_reload_insns[j], before_insn);
6427 emit_insns_before (input_reload_insns[j], before_insn);
6430 emit_insns_before (operand_reload_insns, before_insn);
6432 for (j = 0; j < reload_n_operands; j++)
6434 emit_insns_before (output_address_reload_insns[j], following_insn);
6435 emit_insns_before (output_reload_insns[j], following_insn);
6438 /* Move death notes from INSN
6439 to output-operand-address and output reload insns. */
6440 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6443 /* Loop over those insns, last ones first. */
6444 for (insn1 = PREV_INSN (following_insn); insn1 != insn;
6445 insn1 = PREV_INSN (insn1))
6446 if (GET_CODE (insn1) == INSN && GET_CODE (PATTERN (insn1)) == SET)
6448 rtx source = SET_SRC (PATTERN (insn1));
6449 rtx dest = SET_DEST (PATTERN (insn1));
6451 /* The note we will examine next. */
6452 rtx reg_notes = REG_NOTES (insn);
6453 /* The place that pointed to this note. */
6454 rtx *prev_reg_note = ®_NOTES (insn);
6456 /* If the note is for something used in the source of this
6457 reload insn, or in the output address, move the note. */
6460 rtx next_reg_notes = XEXP (reg_notes, 1);
6461 if (REG_NOTE_KIND (reg_notes) == REG_DEAD
6462 && GET_CODE (XEXP (reg_notes, 0)) == REG
6463 && ((GET_CODE (dest) != REG
6464 && reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
6466 || reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
6469 *prev_reg_note = next_reg_notes;
6470 XEXP (reg_notes, 1) = REG_NOTES (insn1);
6471 REG_NOTES (insn1) = reg_notes;
6474 prev_reg_note = &XEXP (reg_notes, 1);
6476 reg_notes = next_reg_notes;
6482 /* For all the spill regs newly reloaded in this instruction,
6483 record what they were reloaded from, so subsequent instructions
6484 can inherit the reloads.
6486 Update spill_reg_store for the reloads of this insn.
6487 Copy the elements that were updated in the loop above. */
6489 for (j = 0; j < n_reloads; j++)
6491 register int r = reload_order[j];
6492 register int i = reload_spill_index[r];
6494 /* I is nonneg if this reload used one of the spill regs.
6495 If reload_reg_rtx[r] is 0, this is an optional reload
6496 that we opted to ignore.
6498 Also ignore reloads that don't reach the end of the insn,
6499 since we will eventually see the one that does. */
6501 if (i >= 0 && reload_reg_rtx[r] != 0
6502 && reload_reg_reaches_end_p (spill_regs[i], reload_opnum[r],
6503 reload_when_needed[r]))
6505 /* First, clear out memory of what used to be in this spill reg.
6506 If consecutive registers are used, clear them all. */
6508 = HARD_REGNO_NREGS (spill_regs[i], GET_MODE (reload_reg_rtx[r]));
6511 for (k = 0; k < nr; k++)
6513 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] = -1;
6514 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = 0;
6517 /* Maybe the spill reg contains a copy of reload_out. */
6518 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
6520 register int nregno = REGNO (reload_out[r]);
6521 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6522 : HARD_REGNO_NREGS (nregno,
6523 GET_MODE (reload_reg_rtx[r])));
6525 spill_reg_store[i] = new_spill_reg_store[i];
6526 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
6528 /* If NREGNO is a hard register, it may occupy more than
6529 one register. If it does, say what is in the
6530 rest of the registers assuming that both registers
6531 agree on how many words the object takes. If not,
6532 invalidate the subsequent registers. */
6534 if (nregno < FIRST_PSEUDO_REGISTER)
6535 for (k = 1; k < nnr; k++)
6536 reg_last_reload_reg[nregno + k]
6537 = (nr == nnr ? gen_rtx (REG, word_mode,
6538 REGNO (reload_reg_rtx[r]) + k)
6541 /* Now do the inverse operation. */
6542 for (k = 0; k < nr; k++)
6544 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
6545 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr ? nregno
6547 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = insn;
6551 /* Maybe the spill reg contains a copy of reload_in. Only do
6552 something if there will not be an output reload for
6553 the register being reloaded. */
6554 else if (reload_out[r] == 0
6555 && reload_in[r] != 0
6556 && ((GET_CODE (reload_in[r]) == REG
6557 && ! reg_has_output_reload[REGNO (reload_in[r])]
6558 || (GET_CODE (reload_in_reg[r]) == REG
6559 && ! reg_has_output_reload[REGNO (reload_in_reg[r])]))))
6561 register int nregno;
6564 if (GET_CODE (reload_in[r]) == REG)
6565 nregno = REGNO (reload_in[r]);
6567 nregno = REGNO (reload_in_reg[r]);
6569 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6570 : HARD_REGNO_NREGS (nregno,
6571 GET_MODE (reload_reg_rtx[r])));
6573 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
6575 if (nregno < FIRST_PSEUDO_REGISTER)
6576 for (k = 1; k < nnr; k++)
6577 reg_last_reload_reg[nregno + k]
6578 = (nr == nnr ? gen_rtx (REG, word_mode,
6579 REGNO (reload_reg_rtx[r]) + k)
6582 /* Unless we inherited this reload, show we haven't
6583 recently done a store. */
6584 if (! reload_inherited[r])
6585 spill_reg_store[i] = 0;
6587 for (k = 0; k < nr; k++)
6589 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
6590 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr ? nregno
6592 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]]
6598 /* The following if-statement was #if 0'd in 1.34 (or before...).
6599 It's reenabled in 1.35 because supposedly nothing else
6600 deals with this problem. */
6602 /* If a register gets output-reloaded from a non-spill register,
6603 that invalidates any previous reloaded copy of it.
6604 But forget_old_reloads_1 won't get to see it, because
6605 it thinks only about the original insn. So invalidate it here. */
6606 if (i < 0 && reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
6608 register int nregno = REGNO (reload_out[r]);
6609 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (reload_out[r]));
6611 while (num_regs-- > 0)
6612 reg_last_reload_reg[nregno + num_regs] = 0;
6617 /* Emit code to perform an input reload of IN to RELOADREG. IN is from
6618 operand OPNUM with reload type TYPE.
6620 Returns first insn emitted. */
6623 gen_input_reload (reloadreg, in, opnum, type)
6627 enum reload_type type;
6629 rtx last = get_last_insn ();
6631 /* How to do this reload can get quite tricky. Normally, we are being
6632 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
6633 register that didn't get a hard register. In that case we can just
6634 call emit_move_insn.
6636 We can also be asked to reload a PLUS that adds a register or a MEM to
6637 another register, constant or MEM. This can occur during frame pointer
6638 elimination and while reloading addresses. This case is handled by
6639 trying to emit a single insn to perform the add. If it is not valid,
6640 we use a two insn sequence.
6642 Finally, we could be called to handle an 'o' constraint by putting
6643 an address into a register. In that case, we first try to do this
6644 with a named pattern of "reload_load_address". If no such pattern
6645 exists, we just emit a SET insn and hope for the best (it will normally
6646 be valid on machines that use 'o').
6648 This entire process is made complex because reload will never
6649 process the insns we generate here and so we must ensure that
6650 they will fit their constraints and also by the fact that parts of
6651 IN might be being reloaded separately and replaced with spill registers.
6652 Because of this, we are, in some sense, just guessing the right approach
6653 here. The one listed above seems to work.
6655 ??? At some point, this whole thing needs to be rethought. */
6657 if (GET_CODE (in) == PLUS
6658 && (GET_CODE (XEXP (in, 0)) == REG
6659 || GET_CODE (XEXP (in, 0)) == MEM)
6660 && (GET_CODE (XEXP (in, 1)) == REG
6661 || CONSTANT_P (XEXP (in, 1))
6662 || GET_CODE (XEXP (in, 1)) == MEM))
6664 /* We need to compute the sum of a register or a MEM and another
6665 register, constant, or MEM, and put it into the reload
6666 register. The best possible way of doing this is if the machine
6667 has a three-operand ADD insn that accepts the required operands.
6669 The simplest approach is to try to generate such an insn and see if it
6670 is recognized and matches its constraints. If so, it can be used.
6672 It might be better not to actually emit the insn unless it is valid,
6673 but we need to pass the insn as an operand to `recog' and
6674 `insn_extract' and it is simpler to emit and then delete the insn if
6675 not valid than to dummy things up. */
6677 rtx op0, op1, tem, insn;
6680 op0 = find_replacement (&XEXP (in, 0));
6681 op1 = find_replacement (&XEXP (in, 1));
6683 /* Since constraint checking is strict, commutativity won't be
6684 checked, so we need to do that here to avoid spurious failure
6685 if the add instruction is two-address and the second operand
6686 of the add is the same as the reload reg, which is frequently
6687 the case. If the insn would be A = B + A, rearrange it so
6688 it will be A = A + B as constrain_operands expects. */
6690 if (GET_CODE (XEXP (in, 1)) == REG
6691 && REGNO (reloadreg) == REGNO (XEXP (in, 1)))
6692 tem = op0, op0 = op1, op1 = tem;
6694 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
6695 in = gen_rtx (PLUS, GET_MODE (in), op0, op1);
6697 insn = emit_insn (gen_rtx (SET, VOIDmode, reloadreg, in));
6698 code = recog_memoized (insn);
6702 insn_extract (insn);
6703 /* We want constrain operands to treat this insn strictly in
6704 its validity determination, i.e., the way it would after reload
6706 if (constrain_operands (code, 1))
6710 delete_insns_since (last);
6712 /* If that failed, we must use a conservative two-insn sequence.
6713 use move to copy constant, MEM, or pseudo register to the reload
6714 register since "move" will be able to handle an arbitrary operand,
6715 unlike add which can't, in general. Then add the registers.
6717 If there is another way to do this for a specific machine, a
6718 DEFINE_PEEPHOLE should be specified that recognizes the sequence
6721 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM
6722 || (GET_CODE (op1) == REG
6723 && REGNO (op1) >= FIRST_PSEUDO_REGISTER))
6724 tem = op0, op0 = op1, op1 = tem;
6726 emit_insn (gen_move_insn (reloadreg, op0));
6728 /* If OP0 and OP1 are the same, we can use RELOADREG for OP1.
6729 This fixes a problem on the 32K where the stack pointer cannot
6730 be used as an operand of an add insn. */
6732 if (rtx_equal_p (op0, op1))
6735 insn = emit_insn (gen_add2_insn (reloadreg, op1));
6737 /* If that failed, copy the address register to the reload register.
6738 Then add the constant to the reload register. */
6740 code = recog_memoized (insn);
6744 insn_extract (insn);
6745 /* We want constrain operands to treat this insn strictly in
6746 its validity determination, i.e., the way it would after reload
6748 if (constrain_operands (code, 1))
6752 delete_insns_since (last);
6754 emit_insn (gen_move_insn (reloadreg, op1));
6755 emit_insn (gen_add2_insn (reloadreg, op0));
6758 #ifdef SECONDARY_MEMORY_NEEDED
6759 /* If we need a memory location to do the move, do it that way. */
6760 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
6761 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
6762 REGNO_REG_CLASS (REGNO (reloadreg)),
6763 GET_MODE (reloadreg)))
6765 /* Get the memory to use and rewrite both registers to its mode. */
6766 rtx loc = get_secondary_mem (in, GET_MODE (reloadreg), opnum, type);
6768 if (GET_MODE (loc) != GET_MODE (reloadreg))
6769 reloadreg = gen_rtx (REG, GET_MODE (loc), REGNO (reloadreg));
6771 if (GET_MODE (loc) != GET_MODE (in))
6772 in = gen_rtx (REG, GET_MODE (loc), REGNO (in));
6774 emit_insn (gen_move_insn (loc, in));
6775 emit_insn (gen_move_insn (reloadreg, loc));
6779 /* If IN is a simple operand, use gen_move_insn. */
6780 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
6781 emit_insn (gen_move_insn (reloadreg, in));
6783 #ifdef HAVE_reload_load_address
6784 else if (HAVE_reload_load_address)
6785 emit_insn (gen_reload_load_address (reloadreg, in));
6788 /* Otherwise, just write (set REGLOADREG IN) and hope for the best. */
6790 emit_insn (gen_rtx (SET, VOIDmode, reloadreg, in));
6792 /* Return the first insn emitted.
6793 We can not just return get_last_insn, because there may have
6794 been multiple instructions emitted. Also note that gen_move_insn may
6795 emit more than one insn itself, so we can not assume that there is one
6796 insn emitted per emit_insn_before call. */
6798 return last ? NEXT_INSN (last) : get_insns ();
6801 /* Delete a previously made output-reload
6802 whose result we now believe is not needed.
6803 First we double-check.
6805 INSN is the insn now being processed.
6806 OUTPUT_RELOAD_INSN is the insn of the output reload.
6807 J is the reload-number for this insn. */
6810 delete_output_reload (insn, j, output_reload_insn)
6813 rtx output_reload_insn;
6817 /* Get the raw pseudo-register referred to. */
6819 rtx reg = reload_in[j];
6820 while (GET_CODE (reg) == SUBREG)
6821 reg = SUBREG_REG (reg);
6823 /* If the pseudo-reg we are reloading is no longer referenced
6824 anywhere between the store into it and here,
6825 and no jumps or labels intervene, then the value can get
6826 here through the reload reg alone.
6827 Otherwise, give up--return. */
6828 for (i1 = NEXT_INSN (output_reload_insn);
6829 i1 != insn; i1 = NEXT_INSN (i1))
6831 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
6833 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
6834 && reg_mentioned_p (reg, PATTERN (i1)))
6838 if (cannot_omit_stores[REGNO (reg)])
6841 /* If this insn will store in the pseudo again,
6842 the previous store can be removed. */
6843 if (reload_out[j] == reload_in[j])
6844 delete_insn (output_reload_insn);
6846 /* See if the pseudo reg has been completely replaced
6847 with reload regs. If so, delete the store insn
6848 and forget we had a stack slot for the pseudo. */
6849 else if (reg_n_deaths[REGNO (reg)] == 1
6850 && reg_basic_block[REGNO (reg)] >= 0
6851 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
6855 /* We know that it was used only between here
6856 and the beginning of the current basic block.
6857 (We also know that the last use before INSN was
6858 the output reload we are thinking of deleting, but never mind that.)
6859 Search that range; see if any ref remains. */
6860 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
6862 rtx set = single_set (i2);
6864 /* Uses which just store in the pseudo don't count,
6865 since if they are the only uses, they are dead. */
6866 if (set != 0 && SET_DEST (set) == reg)
6868 if (GET_CODE (i2) == CODE_LABEL
6869 || GET_CODE (i2) == JUMP_INSN)
6871 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
6872 && reg_mentioned_p (reg, PATTERN (i2)))
6873 /* Some other ref remains;
6874 we can't do anything. */
6878 /* Delete the now-dead stores into this pseudo. */
6879 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
6881 rtx set = single_set (i2);
6883 if (set != 0 && SET_DEST (set) == reg)
6885 if (GET_CODE (i2) == CODE_LABEL
6886 || GET_CODE (i2) == JUMP_INSN)
6890 /* For the debugging info,
6891 say the pseudo lives in this reload reg. */
6892 reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]);
6893 alter_reg (REGNO (reg), -1);
6897 /* Output reload-insns to reload VALUE into RELOADREG.
6898 VALUE is an autoincrement or autodecrement RTX whose operand
6899 is a register or memory location;
6900 so reloading involves incrementing that location.
6902 INC_AMOUNT is the number to increment or decrement by (always positive).
6903 This cannot be deduced from VALUE. */
6906 inc_for_reload (reloadreg, value, inc_amount)
6911 /* REG or MEM to be copied and incremented. */
6912 rtx incloc = XEXP (value, 0);
6913 /* Nonzero if increment after copying. */
6914 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
6920 /* No hard register is equivalent to this register after
6921 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
6922 we could inc/dec that register as well (maybe even using it for
6923 the source), but I'm not sure it's worth worrying about. */
6924 if (GET_CODE (incloc) == REG)
6925 reg_last_reload_reg[REGNO (incloc)] = 0;
6927 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
6928 inc_amount = - inc_amount;
6930 inc = GEN_INT (inc_amount);
6932 /* If this is post-increment, first copy the location to the reload reg. */
6934 emit_insn (gen_move_insn (reloadreg, incloc));
6936 /* See if we can directly increment INCLOC. Use a method similar to that
6937 in gen_input_reload. */
6939 last = get_last_insn ();
6940 add_insn = emit_insn (gen_rtx (SET, VOIDmode, incloc,
6941 gen_rtx (PLUS, GET_MODE (incloc),
6944 code = recog_memoized (add_insn);
6947 insn_extract (add_insn);
6948 if (constrain_operands (code, 1))
6950 /* If this is a pre-increment and we have incremented the value
6951 where it lives, copy the incremented value to RELOADREG to
6952 be used as an address. */
6955 emit_insn (gen_move_insn (reloadreg, incloc));
6961 delete_insns_since (last);
6963 /* If couldn't do the increment directly, must increment in RELOADREG.
6964 The way we do this depends on whether this is pre- or post-increment.
6965 For pre-increment, copy INCLOC to the reload register, increment it
6966 there, then save back. */
6970 emit_insn (gen_move_insn (reloadreg, incloc));
6971 emit_insn (gen_add2_insn (reloadreg, inc));
6972 emit_insn (gen_move_insn (incloc, reloadreg));
6977 Because this might be a jump insn or a compare, and because RELOADREG
6978 may not be available after the insn in an input reload, we must do
6979 the incrementation before the insn being reloaded for.
6981 We have already copied INCLOC to RELOADREG. Increment the copy in
6982 RELOADREG, save that back, then decrement RELOADREG so it has
6983 the original value. */
6985 emit_insn (gen_add2_insn (reloadreg, inc));
6986 emit_insn (gen_move_insn (incloc, reloadreg));
6987 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
6993 /* Return 1 if we are certain that the constraint-string STRING allows
6994 the hard register REG. Return 0 if we can't be sure of this. */
6997 constraint_accepts_reg_p (string, reg)
7002 int regno = true_regnum (reg);
7005 /* Initialize for first alternative. */
7007 /* Check that each alternative contains `g' or `r'. */
7009 switch (c = *string++)
7012 /* If an alternative lacks `g' or `r', we lose. */
7015 /* If an alternative lacks `g' or `r', we lose. */
7018 /* Initialize for next alternative. */
7023 /* Any general reg wins for this alternative. */
7024 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7028 /* Any reg in specified class wins for this alternative. */
7030 enum reg_class class = REG_CLASS_FROM_LETTER (c);
7032 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
7038 /* Return the number of places FIND appears within X, but don't count
7039 an occurrence if some SET_DEST is FIND. */
7042 count_occurrences (x, find)
7043 register rtx x, find;
7046 register enum rtx_code code;
7047 register char *format_ptr;
7055 code = GET_CODE (x);
7070 if (SET_DEST (x) == find)
7071 return count_occurrences (SET_SRC (x), find);
7075 format_ptr = GET_RTX_FORMAT (code);
7078 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7080 switch (*format_ptr++)
7083 count += count_occurrences (XEXP (x, i), find);
7087 if (XVEC (x, i) != NULL)
7089 for (j = 0; j < XVECLEN (x, i); j++)
7090 count += count_occurrences (XVECEXP (x, i, j), find);
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