1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
48 /* This file contains the reload pass of the compiler, which is
49 run after register allocation has been done. It checks that
50 each insn is valid (operands required to be in registers really
51 are in registers of the proper class) and fixes up invalid ones
52 by copying values temporarily into registers for the insns
55 The results of register allocation are described by the vector
56 reg_renumber; the insns still contain pseudo regs, but reg_renumber
57 can be used to find which hard reg, if any, a pseudo reg is in.
59 The technique we always use is to free up a few hard regs that are
60 called ``reload regs'', and for each place where a pseudo reg
61 must be in a hard reg, copy it temporarily into one of the reload regs.
63 Reload regs are allocated locally for every instruction that needs
64 reloads. When there are pseudos which are allocated to a register that
65 has been chosen as a reload reg, such pseudos must be ``spilled''.
66 This means that they go to other hard regs, or to stack slots if no other
67 available hard regs can be found. Spilling can invalidate more
68 insns, requiring additional need for reloads, so we must keep checking
69 until the process stabilizes.
71 For machines with different classes of registers, we must keep track
72 of the register class needed for each reload, and make sure that
73 we allocate enough reload registers of each class.
75 The file reload.c contains the code that checks one insn for
76 validity and reports the reloads that it needs. This file
77 is in charge of scanning the entire rtl code, accumulating the
78 reload needs, spilling, assigning reload registers to use for
79 fixing up each insn, and generating the new insns to copy values
80 into the reload registers. */
82 #ifndef REGISTER_MOVE_COST
83 #define REGISTER_MOVE_COST(m, x, y) 2
87 #define LOCAL_REGNO(REGNO) 0
90 /* During reload_as_needed, element N contains a REG rtx for the hard reg
91 into which reg N has been reloaded (perhaps for a previous insn). */
92 static rtx *reg_last_reload_reg;
94 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
95 for an output reload that stores into reg N. */
96 static char *reg_has_output_reload;
98 /* Indicates which hard regs are reload-registers for an output reload
99 in the current insn. */
100 static HARD_REG_SET reg_is_output_reload;
102 /* Element N is the constant value to which pseudo reg N is equivalent,
103 or zero if pseudo reg N is not equivalent to a constant.
104 find_reloads looks at this in order to replace pseudo reg N
105 with the constant it stands for. */
106 rtx *reg_equiv_constant;
108 /* Element N is a memory location to which pseudo reg N is equivalent,
109 prior to any register elimination (such as frame pointer to stack
110 pointer). Depending on whether or not it is a valid address, this value
111 is transferred to either reg_equiv_address or reg_equiv_mem. */
112 rtx *reg_equiv_memory_loc;
114 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
115 This is used when the address is not valid as a memory address
116 (because its displacement is too big for the machine.) */
117 rtx *reg_equiv_address;
119 /* Element N is the memory slot to which pseudo reg N is equivalent,
120 or zero if pseudo reg N is not equivalent to a memory slot. */
123 /* Widest width in which each pseudo reg is referred to (via subreg). */
124 static unsigned int *reg_max_ref_width;
126 /* Element N is the list of insns that initialized reg N from its equivalent
127 constant or memory slot. */
128 static rtx *reg_equiv_init;
130 /* Vector to remember old contents of reg_renumber before spilling. */
131 static short *reg_old_renumber;
133 /* During reload_as_needed, element N contains the last pseudo regno reloaded
134 into hard register N. If that pseudo reg occupied more than one register,
135 reg_reloaded_contents points to that pseudo for each spill register in
136 use; all of these must remain set for an inheritance to occur. */
137 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
139 /* During reload_as_needed, element N contains the insn for which
140 hard register N was last used. Its contents are significant only
141 when reg_reloaded_valid is set for this register. */
142 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
144 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
145 static HARD_REG_SET reg_reloaded_valid;
146 /* Indicate if the register was dead at the end of the reload.
147 This is only valid if reg_reloaded_contents is set and valid. */
148 static HARD_REG_SET reg_reloaded_dead;
150 /* Number of spill-regs so far; number of valid elements of spill_regs. */
153 /* In parallel with spill_regs, contains REG rtx's for those regs.
154 Holds the last rtx used for any given reg, or 0 if it has never
155 been used for spilling yet. This rtx is reused, provided it has
157 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
159 /* In parallel with spill_regs, contains nonzero for a spill reg
160 that was stored after the last time it was used.
161 The precise value is the insn generated to do the store. */
162 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
164 /* This is the register that was stored with spill_reg_store. This is a
165 copy of reload_out / reload_out_reg when the value was stored; if
166 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
167 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
169 /* This table is the inverse mapping of spill_regs:
170 indexed by hard reg number,
171 it contains the position of that reg in spill_regs,
172 or -1 for something that is not in spill_regs.
174 ?!? This is no longer accurate. */
175 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
177 /* This reg set indicates registers that can't be used as spill registers for
178 the currently processed insn. These are the hard registers which are live
179 during the insn, but not allocated to pseudos, as well as fixed
181 static HARD_REG_SET bad_spill_regs;
183 /* These are the hard registers that can't be used as spill register for any
184 insn. This includes registers used for user variables and registers that
185 we can't eliminate. A register that appears in this set also can't be used
186 to retry register allocation. */
187 static HARD_REG_SET bad_spill_regs_global;
189 /* Describes order of use of registers for reloading
190 of spilled pseudo-registers. `n_spills' is the number of
191 elements that are actually valid; new ones are added at the end.
193 Both spill_regs and spill_reg_order are used on two occasions:
194 once during find_reload_regs, where they keep track of the spill registers
195 for a single insn, but also during reload_as_needed where they show all
196 the registers ever used by reload. For the latter case, the information
197 is calculated during finish_spills. */
198 static short spill_regs[FIRST_PSEUDO_REGISTER];
200 /* This vector of reg sets indicates, for each pseudo, which hard registers
201 may not be used for retrying global allocation because the register was
202 formerly spilled from one of them. If we allowed reallocating a pseudo to
203 a register that it was already allocated to, reload might not
205 static HARD_REG_SET *pseudo_previous_regs;
207 /* This vector of reg sets indicates, for each pseudo, which hard
208 registers may not be used for retrying global allocation because they
209 are used as spill registers during one of the insns in which the
211 static HARD_REG_SET *pseudo_forbidden_regs;
213 /* All hard regs that have been used as spill registers for any insn are
214 marked in this set. */
215 static HARD_REG_SET used_spill_regs;
217 /* Index of last register assigned as a spill register. We allocate in
218 a round-robin fashion. */
219 static int last_spill_reg;
221 /* Nonzero if indirect addressing is supported on the machine; this means
222 that spilling (REG n) does not require reloading it into a register in
223 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
224 value indicates the level of indirect addressing supported, e.g., two
225 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
227 static char spill_indirect_levels;
229 /* Nonzero if indirect addressing is supported when the innermost MEM is
230 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
231 which these are valid is the same as spill_indirect_levels, above. */
232 char indirect_symref_ok;
234 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
235 char double_reg_address_ok;
237 /* Record the stack slot for each spilled hard register. */
238 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
240 /* Width allocated so far for that stack slot. */
241 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
243 /* Record which pseudos needed to be spilled. */
244 static regset_head spilled_pseudos;
246 /* Used for communication between order_regs_for_reload and count_pseudo.
247 Used to avoid counting one pseudo twice. */
248 static regset_head pseudos_counted;
250 /* First uid used by insns created by reload in this function.
251 Used in find_equiv_reg. */
252 int reload_first_uid;
254 /* Flag set by local-alloc or global-alloc if anything is live in
255 a call-clobbered reg across calls. */
256 int caller_save_needed;
258 /* Set to 1 while reload_as_needed is operating.
259 Required by some machines to handle any generated moves differently. */
260 int reload_in_progress = 0;
262 /* These arrays record the insn_code of insns that may be needed to
263 perform input and output reloads of special objects. They provide a
264 place to pass a scratch register. */
265 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
266 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
268 /* This obstack is used for allocation of rtl during register elimination.
269 The allocated storage can be freed once find_reloads has processed the
271 struct obstack reload_obstack;
273 /* Points to the beginning of the reload_obstack. All insn_chain structures
274 are allocated first. */
275 char *reload_startobj;
277 /* The point after all insn_chain structures. Used to quickly deallocate
278 memory allocated in copy_reloads during calculate_needs_all_insns. */
279 char *reload_firstobj;
281 /* This points before all local rtl generated by register elimination.
282 Used to quickly free all memory after processing one insn. */
283 static char *reload_insn_firstobj;
285 /* List of insn_chain instructions, one for every insn that reload needs to
287 struct insn_chain *reload_insn_chain;
290 extern tree current_function_decl;
292 extern union tree_node *current_function_decl;
295 /* List of all insns needing reloads. */
296 static struct insn_chain *insns_need_reload;
298 /* This structure is used to record information about register eliminations.
299 Each array entry describes one possible way of eliminating a register
300 in favor of another. If there is more than one way of eliminating a
301 particular register, the most preferred should be specified first. */
305 int from; /* Register number to be eliminated. */
306 int to; /* Register number used as replacement. */
307 int initial_offset; /* Initial difference between values. */
308 int can_eliminate; /* Nonzero if this elimination can be done. */
309 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
310 insns made by reload. */
311 int offset; /* Current offset between the two regs. */
312 int previous_offset; /* Offset at end of previous insn. */
313 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
314 rtx from_rtx; /* REG rtx for the register to be eliminated.
315 We cannot simply compare the number since
316 we might then spuriously replace a hard
317 register corresponding to a pseudo
318 assigned to the reg to be eliminated. */
319 rtx to_rtx; /* REG rtx for the replacement. */
322 static struct elim_table *reg_eliminate = 0;
324 /* This is an intermediate structure to initialize the table. It has
325 exactly the members provided by ELIMINABLE_REGS. */
326 static const struct elim_table_1
330 } reg_eliminate_1[] =
332 /* If a set of eliminable registers was specified, define the table from it.
333 Otherwise, default to the normal case of the frame pointer being
334 replaced by the stack pointer. */
336 #ifdef ELIMINABLE_REGS
339 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
342 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
344 /* Record the number of pending eliminations that have an offset not equal
345 to their initial offset. If nonzero, we use a new copy of each
346 replacement result in any insns encountered. */
347 int num_not_at_initial_offset;
349 /* Count the number of registers that we may be able to eliminate. */
350 static int num_eliminable;
351 /* And the number of registers that are equivalent to a constant that
352 can be eliminated to frame_pointer / arg_pointer + constant. */
353 static int num_eliminable_invariants;
355 /* For each label, we record the offset of each elimination. If we reach
356 a label by more than one path and an offset differs, we cannot do the
357 elimination. This information is indexed by the difference of the
358 number of the label and the first label number. We can't offset the
359 pointer itself as this can cause problems on machines with segmented
360 memory. The first table is an array of flags that records whether we
361 have yet encountered a label and the second table is an array of arrays,
362 one entry in the latter array for each elimination. */
364 static int first_label_num;
365 static char *offsets_known_at;
366 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
368 /* Number of labels in the current function. */
370 static int num_labels;
372 static void replace_pseudos_in_call_usage PARAMS ((rtx *,
375 static void maybe_fix_stack_asms PARAMS ((void));
376 static void copy_reloads PARAMS ((struct insn_chain *));
377 static void calculate_needs_all_insns PARAMS ((int));
378 static int find_reg PARAMS ((struct insn_chain *, int));
379 static void find_reload_regs PARAMS ((struct insn_chain *));
380 static void select_reload_regs PARAMS ((void));
381 static void delete_caller_save_insns PARAMS ((void));
383 static void spill_failure PARAMS ((rtx, enum reg_class));
384 static void count_spilled_pseudo PARAMS ((int, int, int));
385 static void delete_dead_insn PARAMS ((rtx));
386 static void alter_reg PARAMS ((int, int));
387 static void set_label_offsets PARAMS ((rtx, rtx, int));
388 static void check_eliminable_occurrences PARAMS ((rtx));
389 static void elimination_effects PARAMS ((rtx, enum machine_mode));
390 static int eliminate_regs_in_insn PARAMS ((rtx, int));
391 static void update_eliminable_offsets PARAMS ((void));
392 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
393 static void set_initial_elim_offsets PARAMS ((void));
394 static void verify_initial_elim_offsets PARAMS ((void));
395 static void set_initial_label_offsets PARAMS ((void));
396 static void set_offsets_for_label PARAMS ((rtx));
397 static void init_elim_table PARAMS ((void));
398 static void update_eliminables PARAMS ((HARD_REG_SET *));
399 static void spill_hard_reg PARAMS ((unsigned int, int));
400 static int finish_spills PARAMS ((int));
401 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
402 static void scan_paradoxical_subregs PARAMS ((rtx));
403 static void count_pseudo PARAMS ((int));
404 static void order_regs_for_reload PARAMS ((struct insn_chain *));
405 static void reload_as_needed PARAMS ((int));
406 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
407 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
408 static void mark_reload_reg_in_use PARAMS ((unsigned int, int,
411 static void clear_reload_reg_in_use PARAMS ((unsigned int, int,
414 static int reload_reg_free_p PARAMS ((unsigned int, int,
416 static int reload_reg_free_for_value_p PARAMS ((int, int, int,
418 rtx, rtx, int, int));
419 static int free_for_value_p PARAMS ((int, enum machine_mode, int,
420 enum reload_type, rtx, rtx,
422 static int reload_reg_reaches_end_p PARAMS ((unsigned int, int,
424 static int allocate_reload_reg PARAMS ((struct insn_chain *, int,
426 static int conflicts_with_override PARAMS ((rtx));
427 static void failed_reload PARAMS ((rtx, int));
428 static int set_reload_reg PARAMS ((int, int));
429 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
430 static void choose_reload_regs PARAMS ((struct insn_chain *));
431 static void merge_assigned_reloads PARAMS ((rtx));
432 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
433 struct reload *, rtx, int));
434 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
435 struct reload *, int));
436 static void do_input_reload PARAMS ((struct insn_chain *,
437 struct reload *, int));
438 static void do_output_reload PARAMS ((struct insn_chain *,
439 struct reload *, int));
440 static void emit_reload_insns PARAMS ((struct insn_chain *));
441 static void delete_output_reload PARAMS ((rtx, int, int));
442 static void delete_address_reloads PARAMS ((rtx, rtx));
443 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
444 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
445 static void reload_cse_regs_1 PARAMS ((rtx));
446 static int reload_cse_noop_set_p PARAMS ((rtx));
447 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
448 static int reload_cse_simplify_operands PARAMS ((rtx, rtx));
449 static void reload_combine PARAMS ((void));
450 static void reload_combine_note_use PARAMS ((rtx *, rtx));
451 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
452 static void reload_cse_move2add PARAMS ((rtx));
453 static void move2add_note_store PARAMS ((rtx, rtx, void *));
455 static void add_auto_inc_notes PARAMS ((rtx, rtx));
457 static void copy_eh_notes PARAMS ((rtx, rtx));
458 static void failed_reload PARAMS ((rtx, int));
459 static int set_reload_reg PARAMS ((int, int));
460 static void reload_cse_simplify PARAMS ((rtx, rtx));
461 void fixup_abnormal_edges PARAMS ((void));
462 extern void dump_needs PARAMS ((struct insn_chain *));
464 /* Initialize the reload pass once per compilation. */
471 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
472 Set spill_indirect_levels to the number of levels such addressing is
473 permitted, zero if it is not permitted at all. */
476 = gen_rtx_MEM (Pmode,
479 LAST_VIRTUAL_REGISTER + 1),
481 spill_indirect_levels = 0;
483 while (memory_address_p (QImode, tem))
485 spill_indirect_levels++;
486 tem = gen_rtx_MEM (Pmode, tem);
489 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
491 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
492 indirect_symref_ok = memory_address_p (QImode, tem);
494 /* See if reg+reg is a valid (and offsettable) address. */
496 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
498 tem = gen_rtx_PLUS (Pmode,
499 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
500 gen_rtx_REG (Pmode, i));
502 /* This way, we make sure that reg+reg is an offsettable address. */
503 tem = plus_constant (tem, 4);
505 if (memory_address_p (QImode, tem))
507 double_reg_address_ok = 1;
512 /* Initialize obstack for our rtl allocation. */
513 gcc_obstack_init (&reload_obstack);
514 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
516 INIT_REG_SET (&spilled_pseudos);
517 INIT_REG_SET (&pseudos_counted);
520 /* List of insn chains that are currently unused. */
521 static struct insn_chain *unused_insn_chains = 0;
523 /* Allocate an empty insn_chain structure. */
527 struct insn_chain *c;
529 if (unused_insn_chains == 0)
531 c = (struct insn_chain *)
532 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
533 INIT_REG_SET (&c->live_throughout);
534 INIT_REG_SET (&c->dead_or_set);
538 c = unused_insn_chains;
539 unused_insn_chains = c->next;
541 c->is_caller_save_insn = 0;
542 c->need_operand_change = 0;
548 /* Small utility function to set all regs in hard reg set TO which are
549 allocated to pseudos in regset FROM. */
552 compute_use_by_pseudos (to, from)
558 EXECUTE_IF_SET_IN_REG_SET
559 (from, FIRST_PSEUDO_REGISTER, regno,
561 int r = reg_renumber[regno];
566 /* reload_combine uses the information from
567 BASIC_BLOCK->global_live_at_start, which might still
568 contain registers that have not actually been allocated
569 since they have an equivalence. */
570 if (! reload_completed)
575 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
577 SET_HARD_REG_BIT (*to, r + nregs);
582 /* Replace all pseudos found in LOC with their corresponding
586 replace_pseudos_in_call_usage (loc, mem_mode, usage)
588 enum machine_mode mem_mode;
602 unsigned int regno = REGNO (x);
604 if (regno < FIRST_PSEUDO_REGISTER)
607 x = eliminate_regs (x, mem_mode, usage);
611 replace_pseudos_in_call_usage (loc, mem_mode, usage);
615 if (reg_equiv_constant[regno])
616 *loc = reg_equiv_constant[regno];
617 else if (reg_equiv_mem[regno])
618 *loc = reg_equiv_mem[regno];
619 else if (reg_equiv_address[regno])
620 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
621 else if (GET_CODE (regno_reg_rtx[regno]) != REG
622 || REGNO (regno_reg_rtx[regno]) != regno)
623 *loc = regno_reg_rtx[regno];
629 else if (code == MEM)
631 replace_pseudos_in_call_usage (& XEXP (x, 0), GET_MODE (x), usage);
635 /* Process each of our operands recursively. */
636 fmt = GET_RTX_FORMAT (code);
637 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
639 replace_pseudos_in_call_usage (&XEXP (x, i), mem_mode, usage);
640 else if (*fmt == 'E')
641 for (j = 0; j < XVECLEN (x, i); j++)
642 replace_pseudos_in_call_usage (& XVECEXP (x, i, j), mem_mode, usage);
646 /* Global variables used by reload and its subroutines. */
648 /* Set during calculate_needs if an insn needs register elimination. */
649 static int something_needs_elimination;
650 /* Set during calculate_needs if an insn needs an operand changed. */
651 int something_needs_operands_changed;
653 /* Nonzero means we couldn't get enough spill regs. */
656 /* Main entry point for the reload pass.
658 FIRST is the first insn of the function being compiled.
660 GLOBAL nonzero means we were called from global_alloc
661 and should attempt to reallocate any pseudoregs that we
662 displace from hard regs we will use for reloads.
663 If GLOBAL is zero, we do not have enough information to do that,
664 so any pseudo reg that is spilled must go to the stack.
666 Return value is nonzero if reload failed
667 and we must not do any more for this function. */
670 reload (first, global)
676 struct elim_table *ep;
679 /* Make sure even insns with volatile mem refs are recognizable. */
684 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
686 /* Make sure that the last insn in the chain
687 is not something that needs reloading. */
688 emit_note (NULL, NOTE_INSN_DELETED);
690 /* Enable find_equiv_reg to distinguish insns made by reload. */
691 reload_first_uid = get_max_uid ();
693 #ifdef SECONDARY_MEMORY_NEEDED
694 /* Initialize the secondary memory table. */
695 clear_secondary_mem ();
698 /* We don't have a stack slot for any spill reg yet. */
699 memset ((char *) spill_stack_slot, 0, sizeof spill_stack_slot);
700 memset ((char *) spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
702 /* Initialize the save area information for caller-save, in case some
706 /* Compute which hard registers are now in use
707 as homes for pseudo registers.
708 This is done here rather than (eg) in global_alloc
709 because this point is reached even if not optimizing. */
710 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
713 /* A function that receives a nonlocal goto must save all call-saved
715 if (current_function_has_nonlocal_label)
716 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
717 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
718 regs_ever_live[i] = 1;
720 /* Find all the pseudo registers that didn't get hard regs
721 but do have known equivalent constants or memory slots.
722 These include parameters (known equivalent to parameter slots)
723 and cse'd or loop-moved constant memory addresses.
725 Record constant equivalents in reg_equiv_constant
726 so they will be substituted by find_reloads.
727 Record memory equivalents in reg_mem_equiv so they can
728 be substituted eventually by altering the REG-rtx's. */
730 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
731 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
732 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
733 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
734 reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int));
735 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
736 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
737 pseudo_forbidden_regs
738 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
740 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
742 CLEAR_HARD_REG_SET (bad_spill_regs_global);
744 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
745 Also find all paradoxical subregs and find largest such for each pseudo.
746 On machines with small register classes, record hard registers that
747 are used for user variables. These can never be used for spills.
748 Also look for a "constant" REG_SETJMP. This means that all
749 caller-saved registers must be marked live. */
751 num_eliminable_invariants = 0;
752 for (insn = first; insn; insn = NEXT_INSN (insn))
754 rtx set = single_set (insn);
756 /* We may introduce USEs that we want to remove at the end, so
757 we'll mark them with QImode. Make sure there are no
758 previously-marked insns left by say regmove. */
759 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
760 && GET_MODE (insn) != VOIDmode)
761 PUT_MODE (insn, VOIDmode);
763 if (GET_CODE (insn) == CALL_INSN
764 && find_reg_note (insn, REG_SETJMP, NULL))
765 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
766 if (! call_used_regs[i])
767 regs_ever_live[i] = 1;
769 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
771 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
773 #ifdef LEGITIMATE_PIC_OPERAND_P
774 && (! function_invariant_p (XEXP (note, 0))
776 /* A function invariant is often CONSTANT_P but may
777 include a register. We promise to only pass
778 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
779 || (CONSTANT_P (XEXP (note, 0))
780 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))))
784 rtx x = XEXP (note, 0);
785 i = REGNO (SET_DEST (set));
786 if (i > LAST_VIRTUAL_REGISTER)
788 /* It can happen that a REG_EQUIV note contains a MEM
789 that is not a legitimate memory operand. As later
790 stages of reload assume that all addresses found
791 in the reg_equiv_* arrays were originally legitimate,
792 we ignore such REG_EQUIV notes. */
793 if (memory_operand (x, VOIDmode))
795 /* Always unshare the equivalence, so we can
796 substitute into this insn without touching the
798 reg_equiv_memory_loc[i] = copy_rtx (x);
800 else if (function_invariant_p (x))
802 if (GET_CODE (x) == PLUS)
804 /* This is PLUS of frame pointer and a constant,
805 and might be shared. Unshare it. */
806 reg_equiv_constant[i] = copy_rtx (x);
807 num_eliminable_invariants++;
809 else if (x == frame_pointer_rtx
810 || x == arg_pointer_rtx)
812 reg_equiv_constant[i] = x;
813 num_eliminable_invariants++;
815 else if (LEGITIMATE_CONSTANT_P (x))
816 reg_equiv_constant[i] = x;
819 reg_equiv_memory_loc[i]
820 = force_const_mem (GET_MODE (SET_DEST (set)), x);
821 if (!reg_equiv_memory_loc[i])
828 /* If this register is being made equivalent to a MEM
829 and the MEM is not SET_SRC, the equivalencing insn
830 is one with the MEM as a SET_DEST and it occurs later.
831 So don't mark this insn now. */
832 if (GET_CODE (x) != MEM
833 || rtx_equal_p (SET_SRC (set), x))
835 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
840 /* If this insn is setting a MEM from a register equivalent to it,
841 this is the equivalencing insn. */
842 else if (set && GET_CODE (SET_DEST (set)) == MEM
843 && GET_CODE (SET_SRC (set)) == REG
844 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
845 && rtx_equal_p (SET_DEST (set),
846 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
847 reg_equiv_init[REGNO (SET_SRC (set))]
848 = gen_rtx_INSN_LIST (VOIDmode, insn,
849 reg_equiv_init[REGNO (SET_SRC (set))]);
852 scan_paradoxical_subregs (PATTERN (insn));
857 first_label_num = get_first_label_num ();
858 num_labels = max_label_num () - first_label_num;
860 /* Allocate the tables used to store offset information at labels. */
861 /* We used to use alloca here, but the size of what it would try to
862 allocate would occasionally cause it to exceed the stack limit and
863 cause a core dump. */
864 offsets_known_at = xmalloc (num_labels);
866 = (int (*)[NUM_ELIMINABLE_REGS])
867 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
869 /* Alter each pseudo-reg rtx to contain its hard reg number.
870 Assign stack slots to the pseudos that lack hard regs or equivalents.
871 Do not touch virtual registers. */
873 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
876 /* If we have some registers we think can be eliminated, scan all insns to
877 see if there is an insn that sets one of these registers to something
878 other than itself plus a constant. If so, the register cannot be
879 eliminated. Doing this scan here eliminates an extra pass through the
880 main reload loop in the most common case where register elimination
882 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
883 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
884 || GET_CODE (insn) == CALL_INSN)
885 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
887 maybe_fix_stack_asms ();
889 insns_need_reload = 0;
890 something_needs_elimination = 0;
892 /* Initialize to -1, which means take the first spill register. */
895 /* Spill any hard regs that we know we can't eliminate. */
896 CLEAR_HARD_REG_SET (used_spill_regs);
897 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
898 if (! ep->can_eliminate)
899 spill_hard_reg (ep->from, 1);
901 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
902 if (frame_pointer_needed)
903 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
905 finish_spills (global);
907 /* From now on, we may need to generate moves differently. We may also
908 allow modifications of insns which cause them to not be recognized.
909 Any such modifications will be cleaned up during reload itself. */
910 reload_in_progress = 1;
912 /* This loop scans the entire function each go-round
913 and repeats until one repetition spills no additional hard regs. */
916 int something_changed;
919 HOST_WIDE_INT starting_frame_size;
921 /* Round size of stack frame to stack_alignment_needed. This must be done
922 here because the stack size may be a part of the offset computation
923 for register elimination, and there might have been new stack slots
924 created in the last iteration of this loop. */
925 if (cfun->stack_alignment_needed)
926 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
928 starting_frame_size = get_frame_size ();
930 set_initial_elim_offsets ();
931 set_initial_label_offsets ();
933 /* For each pseudo register that has an equivalent location defined,
934 try to eliminate any eliminable registers (such as the frame pointer)
935 assuming initial offsets for the replacement register, which
938 If the resulting location is directly addressable, substitute
939 the MEM we just got directly for the old REG.
941 If it is not addressable but is a constant or the sum of a hard reg
942 and constant, it is probably not addressable because the constant is
943 out of range, in that case record the address; we will generate
944 hairy code to compute the address in a register each time it is
945 needed. Similarly if it is a hard register, but one that is not
946 valid as an address register.
948 If the location is not addressable, but does not have one of the
949 above forms, assign a stack slot. We have to do this to avoid the
950 potential of producing lots of reloads if, e.g., a location involves
951 a pseudo that didn't get a hard register and has an equivalent memory
952 location that also involves a pseudo that didn't get a hard register.
954 Perhaps at some point we will improve reload_when_needed handling
955 so this problem goes away. But that's very hairy. */
957 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
958 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
960 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
962 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
964 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
965 else if (CONSTANT_P (XEXP (x, 0))
966 || (GET_CODE (XEXP (x, 0)) == REG
967 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
968 || (GET_CODE (XEXP (x, 0)) == PLUS
969 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
970 && (REGNO (XEXP (XEXP (x, 0), 0))
971 < FIRST_PSEUDO_REGISTER)
972 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
973 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
976 /* Make a new stack slot. Then indicate that something
977 changed so we go back and recompute offsets for
978 eliminable registers because the allocation of memory
979 below might change some offset. reg_equiv_{mem,address}
980 will be set up for this pseudo on the next pass around
982 reg_equiv_memory_loc[i] = 0;
983 reg_equiv_init[i] = 0;
988 if (caller_save_needed)
991 /* If we allocated another stack slot, redo elimination bookkeeping. */
992 if (starting_frame_size != get_frame_size ())
995 if (caller_save_needed)
997 save_call_clobbered_regs ();
998 /* That might have allocated new insn_chain structures. */
999 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1002 calculate_needs_all_insns (global);
1004 CLEAR_REG_SET (&spilled_pseudos);
1007 something_changed = 0;
1009 /* If we allocated any new memory locations, make another pass
1010 since it might have changed elimination offsets. */
1011 if (starting_frame_size != get_frame_size ())
1012 something_changed = 1;
1015 HARD_REG_SET to_spill;
1016 CLEAR_HARD_REG_SET (to_spill);
1017 update_eliminables (&to_spill);
1018 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1019 if (TEST_HARD_REG_BIT (to_spill, i))
1021 spill_hard_reg (i, 1);
1024 /* Regardless of the state of spills, if we previously had
1025 a register that we thought we could eliminate, but now can
1026 not eliminate, we must run another pass.
1028 Consider pseudos which have an entry in reg_equiv_* which
1029 reference an eliminable register. We must make another pass
1030 to update reg_equiv_* so that we do not substitute in the
1031 old value from when we thought the elimination could be
1033 something_changed = 1;
1037 select_reload_regs ();
1041 if (insns_need_reload != 0 || did_spill)
1042 something_changed |= finish_spills (global);
1044 if (! something_changed)
1047 if (caller_save_needed)
1048 delete_caller_save_insns ();
1050 obstack_free (&reload_obstack, reload_firstobj);
1053 /* If global-alloc was run, notify it of any register eliminations we have
1056 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1057 if (ep->can_eliminate)
1058 mark_elimination (ep->from, ep->to);
1060 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1061 If that insn didn't set the register (i.e., it copied the register to
1062 memory), just delete that insn instead of the equivalencing insn plus
1063 anything now dead. If we call delete_dead_insn on that insn, we may
1064 delete the insn that actually sets the register if the register dies
1065 there and that is incorrect. */
1067 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1069 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1072 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1074 rtx equiv_insn = XEXP (list, 0);
1076 /* If we already deleted the insn or if it may trap, we can't
1077 delete it. The latter case shouldn't happen, but can
1078 if an insn has a variable address, gets a REG_EH_REGION
1079 note added to it, and then gets converted into an load
1080 from a constant address. */
1081 if (GET_CODE (equiv_insn) == NOTE
1082 || can_throw_internal (equiv_insn))
1084 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1085 delete_dead_insn (equiv_insn);
1088 PUT_CODE (equiv_insn, NOTE);
1089 NOTE_SOURCE_FILE (equiv_insn) = 0;
1090 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1096 /* Use the reload registers where necessary
1097 by generating move instructions to move the must-be-register
1098 values into or out of the reload registers. */
1100 if (insns_need_reload != 0 || something_needs_elimination
1101 || something_needs_operands_changed)
1103 HOST_WIDE_INT old_frame_size = get_frame_size ();
1105 reload_as_needed (global);
1107 if (old_frame_size != get_frame_size ())
1111 verify_initial_elim_offsets ();
1114 /* If we were able to eliminate the frame pointer, show that it is no
1115 longer live at the start of any basic block. If it ls live by
1116 virtue of being in a pseudo, that pseudo will be marked live
1117 and hence the frame pointer will be known to be live via that
1120 if (! frame_pointer_needed)
1122 CLEAR_REGNO_REG_SET (bb->global_live_at_start,
1123 HARD_FRAME_POINTER_REGNUM);
1125 /* Come here (with failure set nonzero) if we can't get enough spill regs
1126 and we decide not to abort about it. */
1129 CLEAR_REG_SET (&spilled_pseudos);
1130 reload_in_progress = 0;
1132 /* Now eliminate all pseudo regs by modifying them into
1133 their equivalent memory references.
1134 The REG-rtx's for the pseudos are modified in place,
1135 so all insns that used to refer to them now refer to memory.
1137 For a reg that has a reg_equiv_address, all those insns
1138 were changed by reloading so that no insns refer to it any longer;
1139 but the DECL_RTL of a variable decl may refer to it,
1140 and if so this causes the debugging info to mention the variable. */
1142 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1146 if (reg_equiv_mem[i])
1147 addr = XEXP (reg_equiv_mem[i], 0);
1149 if (reg_equiv_address[i])
1150 addr = reg_equiv_address[i];
1154 if (reg_renumber[i] < 0)
1156 rtx reg = regno_reg_rtx[i];
1158 REG_USERVAR_P (reg) = 0;
1159 PUT_CODE (reg, MEM);
1160 XEXP (reg, 0) = addr;
1161 if (reg_equiv_memory_loc[i])
1162 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1165 RTX_UNCHANGING_P (reg) = MEM_IN_STRUCT_P (reg)
1166 = MEM_SCALAR_P (reg) = 0;
1167 MEM_ATTRS (reg) = 0;
1170 else if (reg_equiv_mem[i])
1171 XEXP (reg_equiv_mem[i], 0) = addr;
1175 /* We must set reload_completed now since the cleanup_subreg_operands call
1176 below will re-recognize each insn and reload may have generated insns
1177 which are only valid during and after reload. */
1178 reload_completed = 1;
1180 /* Make a pass over all the insns and delete all USEs which we inserted
1181 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1182 notes. Delete all CLOBBER insns, except those that refer to the return
1183 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1184 from misarranging variable-array code, and simplify (subreg (reg))
1185 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1186 are no longer useful or accurate. Strip and regenerate REG_INC notes
1187 that may have been moved around. */
1189 for (insn = first; insn; insn = NEXT_INSN (insn))
1194 if (GET_CODE (insn) == CALL_INSN)
1195 replace_pseudos_in_call_usage (& CALL_INSN_FUNCTION_USAGE (insn),
1197 CALL_INSN_FUNCTION_USAGE (insn));
1199 if ((GET_CODE (PATTERN (insn)) == USE
1200 /* We mark with QImode USEs introduced by reload itself. */
1201 && (GET_MODE (insn) == QImode
1202 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1203 || (GET_CODE (PATTERN (insn)) == CLOBBER
1204 && (GET_CODE (XEXP (PATTERN (insn), 0)) != MEM
1205 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1206 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1207 && XEXP (XEXP (PATTERN (insn), 0), 0)
1208 != stack_pointer_rtx))
1209 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1210 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1216 pnote = ®_NOTES (insn);
1219 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1220 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1221 || REG_NOTE_KIND (*pnote) == REG_INC
1222 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1223 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1224 *pnote = XEXP (*pnote, 1);
1226 pnote = &XEXP (*pnote, 1);
1230 add_auto_inc_notes (insn, PATTERN (insn));
1233 /* And simplify (subreg (reg)) if it appears as an operand. */
1234 cleanup_subreg_operands (insn);
1237 /* If we are doing stack checking, give a warning if this function's
1238 frame size is larger than we expect. */
1239 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1241 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1242 static int verbose_warned = 0;
1244 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1245 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1246 size += UNITS_PER_WORD;
1248 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1250 warning ("frame size too large for reliable stack checking");
1251 if (! verbose_warned)
1253 warning ("try reducing the number of local variables");
1259 /* Indicate that we no longer have known memory locations or constants. */
1260 if (reg_equiv_constant)
1261 free (reg_equiv_constant);
1262 reg_equiv_constant = 0;
1263 if (reg_equiv_memory_loc)
1264 free (reg_equiv_memory_loc);
1265 reg_equiv_memory_loc = 0;
1267 if (offsets_known_at)
1268 free (offsets_known_at);
1272 free (reg_equiv_mem);
1273 free (reg_equiv_init);
1274 free (reg_equiv_address);
1275 free (reg_max_ref_width);
1276 free (reg_old_renumber);
1277 free (pseudo_previous_regs);
1278 free (pseudo_forbidden_regs);
1280 CLEAR_HARD_REG_SET (used_spill_regs);
1281 for (i = 0; i < n_spills; i++)
1282 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1284 /* Free all the insn_chain structures at once. */
1285 obstack_free (&reload_obstack, reload_startobj);
1286 unused_insn_chains = 0;
1287 fixup_abnormal_edges ();
1289 /* Replacing pseudos with their memory equivalents might have
1290 created shared rtx. Subsequent passes would get confused
1291 by this, so unshare everything here. */
1292 unshare_all_rtl_again (first);
1297 /* Yet another special case. Unfortunately, reg-stack forces people to
1298 write incorrect clobbers in asm statements. These clobbers must not
1299 cause the register to appear in bad_spill_regs, otherwise we'll call
1300 fatal_insn later. We clear the corresponding regnos in the live
1301 register sets to avoid this.
1302 The whole thing is rather sick, I'm afraid. */
1305 maybe_fix_stack_asms ()
1308 const char *constraints[MAX_RECOG_OPERANDS];
1309 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1310 struct insn_chain *chain;
1312 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1315 HARD_REG_SET clobbered, allowed;
1318 if (! INSN_P (chain->insn)
1319 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1321 pat = PATTERN (chain->insn);
1322 if (GET_CODE (pat) != PARALLEL)
1325 CLEAR_HARD_REG_SET (clobbered);
1326 CLEAR_HARD_REG_SET (allowed);
1328 /* First, make a mask of all stack regs that are clobbered. */
1329 for (i = 0; i < XVECLEN (pat, 0); i++)
1331 rtx t = XVECEXP (pat, 0, i);
1332 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1333 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1336 /* Get the operand values and constraints out of the insn. */
1337 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1338 constraints, operand_mode);
1340 /* For every operand, see what registers are allowed. */
1341 for (i = 0; i < noperands; i++)
1343 const char *p = constraints[i];
1344 /* For every alternative, we compute the class of registers allowed
1345 for reloading in CLS, and merge its contents into the reg set
1347 int cls = (int) NO_REGS;
1353 if (c == '\0' || c == ',' || c == '#')
1355 /* End of one alternative - mark the regs in the current
1356 class, and reset the class. */
1357 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1363 } while (c != '\0' && c != ',');
1371 case '=': case '+': case '*': case '%': case '?': case '!':
1372 case '0': case '1': case '2': case '3': case '4': case 'm':
1373 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1374 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1375 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1380 cls = (int) reg_class_subunion[cls]
1381 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1386 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1390 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1391 cls = (int) reg_class_subunion[cls]
1392 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1394 cls = (int) reg_class_subunion[cls]
1395 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1397 p += CONSTRAINT_LEN (c, p);
1400 /* Those of the registers which are clobbered, but allowed by the
1401 constraints, must be usable as reload registers. So clear them
1402 out of the life information. */
1403 AND_HARD_REG_SET (allowed, clobbered);
1404 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1405 if (TEST_HARD_REG_BIT (allowed, i))
1407 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1408 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1415 /* Copy the global variables n_reloads and rld into the corresponding elts
1418 copy_reloads (chain)
1419 struct insn_chain *chain;
1421 chain->n_reloads = n_reloads;
1423 = (struct reload *) obstack_alloc (&reload_obstack,
1424 n_reloads * sizeof (struct reload));
1425 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1426 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1429 /* Walk the chain of insns, and determine for each whether it needs reloads
1430 and/or eliminations. Build the corresponding insns_need_reload list, and
1431 set something_needs_elimination as appropriate. */
1433 calculate_needs_all_insns (global)
1436 struct insn_chain **pprev_reload = &insns_need_reload;
1437 struct insn_chain *chain, *next = 0;
1439 something_needs_elimination = 0;
1441 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1442 for (chain = reload_insn_chain; chain != 0; chain = next)
1444 rtx insn = chain->insn;
1448 /* Clear out the shortcuts. */
1449 chain->n_reloads = 0;
1450 chain->need_elim = 0;
1451 chain->need_reload = 0;
1452 chain->need_operand_change = 0;
1454 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1455 include REG_LABEL), we need to see what effects this has on the
1456 known offsets at labels. */
1458 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1459 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1460 set_label_offsets (insn, insn, 0);
1464 rtx old_body = PATTERN (insn);
1465 int old_code = INSN_CODE (insn);
1466 rtx old_notes = REG_NOTES (insn);
1467 int did_elimination = 0;
1468 int operands_changed = 0;
1469 rtx set = single_set (insn);
1471 /* Skip insns that only set an equivalence. */
1472 if (set && GET_CODE (SET_DEST (set)) == REG
1473 && reg_renumber[REGNO (SET_DEST (set))] < 0
1474 && reg_equiv_constant[REGNO (SET_DEST (set))])
1477 /* If needed, eliminate any eliminable registers. */
1478 if (num_eliminable || num_eliminable_invariants)
1479 did_elimination = eliminate_regs_in_insn (insn, 0);
1481 /* Analyze the instruction. */
1482 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1483 global, spill_reg_order);
1485 /* If a no-op set needs more than one reload, this is likely
1486 to be something that needs input address reloads. We
1487 can't get rid of this cleanly later, and it is of no use
1488 anyway, so discard it now.
1489 We only do this when expensive_optimizations is enabled,
1490 since this complements reload inheritance / output
1491 reload deletion, and it can make debugging harder. */
1492 if (flag_expensive_optimizations && n_reloads > 1)
1494 rtx set = single_set (insn);
1496 && SET_SRC (set) == SET_DEST (set)
1497 && GET_CODE (SET_SRC (set)) == REG
1498 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1501 /* Delete it from the reload chain. */
1503 chain->prev->next = next;
1505 reload_insn_chain = next;
1507 next->prev = chain->prev;
1508 chain->next = unused_insn_chains;
1509 unused_insn_chains = chain;
1514 update_eliminable_offsets ();
1516 /* Remember for later shortcuts which insns had any reloads or
1517 register eliminations. */
1518 chain->need_elim = did_elimination;
1519 chain->need_reload = n_reloads > 0;
1520 chain->need_operand_change = operands_changed;
1522 /* Discard any register replacements done. */
1523 if (did_elimination)
1525 obstack_free (&reload_obstack, reload_insn_firstobj);
1526 PATTERN (insn) = old_body;
1527 INSN_CODE (insn) = old_code;
1528 REG_NOTES (insn) = old_notes;
1529 something_needs_elimination = 1;
1532 something_needs_operands_changed |= operands_changed;
1536 copy_reloads (chain);
1537 *pprev_reload = chain;
1538 pprev_reload = &chain->next_need_reload;
1545 /* Comparison function for qsort to decide which of two reloads
1546 should be handled first. *P1 and *P2 are the reload numbers. */
1549 reload_reg_class_lower (r1p, r2p)
1553 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1556 /* Consider required reloads before optional ones. */
1557 t = rld[r1].optional - rld[r2].optional;
1561 /* Count all solitary classes before non-solitary ones. */
1562 t = ((reg_class_size[(int) rld[r2].class] == 1)
1563 - (reg_class_size[(int) rld[r1].class] == 1));
1567 /* Aside from solitaires, consider all multi-reg groups first. */
1568 t = rld[r2].nregs - rld[r1].nregs;
1572 /* Consider reloads in order of increasing reg-class number. */
1573 t = (int) rld[r1].class - (int) rld[r2].class;
1577 /* If reloads are equally urgent, sort by reload number,
1578 so that the results of qsort leave nothing to chance. */
1582 /* The cost of spilling each hard reg. */
1583 static int spill_cost[FIRST_PSEUDO_REGISTER];
1585 /* When spilling multiple hard registers, we use SPILL_COST for the first
1586 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1587 only the first hard reg for a multi-reg pseudo. */
1588 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1590 /* Update the spill cost arrays, considering that pseudo REG is live. */
1596 int freq = REG_FREQ (reg);
1597 int r = reg_renumber[reg];
1600 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1601 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1604 SET_REGNO_REG_SET (&pseudos_counted, reg);
1609 spill_add_cost[r] += freq;
1611 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1613 spill_cost[r + nregs] += freq;
1616 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1617 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1620 order_regs_for_reload (chain)
1621 struct insn_chain *chain;
1624 HARD_REG_SET used_by_pseudos;
1625 HARD_REG_SET used_by_pseudos2;
1627 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1629 memset (spill_cost, 0, sizeof spill_cost);
1630 memset (spill_add_cost, 0, sizeof spill_add_cost);
1632 /* Count number of uses of each hard reg by pseudo regs allocated to it
1633 and then order them by decreasing use. First exclude hard registers
1634 that are live in or across this insn. */
1636 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1637 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1638 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1639 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1641 /* Now find out which pseudos are allocated to it, and update
1643 CLEAR_REG_SET (&pseudos_counted);
1645 EXECUTE_IF_SET_IN_REG_SET
1646 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1650 EXECUTE_IF_SET_IN_REG_SET
1651 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1655 CLEAR_REG_SET (&pseudos_counted);
1658 /* Vector of reload-numbers showing the order in which the reloads should
1660 static short reload_order[MAX_RELOADS];
1662 /* This is used to keep track of the spill regs used in one insn. */
1663 static HARD_REG_SET used_spill_regs_local;
1665 /* We decided to spill hard register SPILLED, which has a size of
1666 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1667 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1668 update SPILL_COST/SPILL_ADD_COST. */
1671 count_spilled_pseudo (spilled, spilled_nregs, reg)
1672 int spilled, spilled_nregs, reg;
1674 int r = reg_renumber[reg];
1675 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1677 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1678 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1681 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1683 spill_add_cost[r] -= REG_FREQ (reg);
1685 spill_cost[r + nregs] -= REG_FREQ (reg);
1688 /* Find reload register to use for reload number ORDER. */
1691 find_reg (chain, order)
1692 struct insn_chain *chain;
1695 int rnum = reload_order[order];
1696 struct reload *rl = rld + rnum;
1697 int best_cost = INT_MAX;
1701 HARD_REG_SET not_usable;
1702 HARD_REG_SET used_by_other_reload;
1704 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1705 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1706 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1708 CLEAR_HARD_REG_SET (used_by_other_reload);
1709 for (k = 0; k < order; k++)
1711 int other = reload_order[k];
1713 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1714 for (j = 0; j < rld[other].nregs; j++)
1715 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1718 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1720 unsigned int regno = i;
1722 if (! TEST_HARD_REG_BIT (not_usable, regno)
1723 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1724 && HARD_REGNO_MODE_OK (regno, rl->mode))
1726 int this_cost = spill_cost[regno];
1728 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1730 for (j = 1; j < this_nregs; j++)
1732 this_cost += spill_add_cost[regno + j];
1733 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1734 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1739 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1741 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1743 if (this_cost < best_cost
1744 /* Among registers with equal cost, prefer caller-saved ones, or
1745 use REG_ALLOC_ORDER if it is defined. */
1746 || (this_cost == best_cost
1747 #ifdef REG_ALLOC_ORDER
1748 && (inv_reg_alloc_order[regno]
1749 < inv_reg_alloc_order[best_reg])
1751 && call_used_regs[regno]
1752 && ! call_used_regs[best_reg]
1757 best_cost = this_cost;
1765 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1767 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1768 rl->regno = best_reg;
1770 EXECUTE_IF_SET_IN_REG_SET
1771 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1773 count_spilled_pseudo (best_reg, rl->nregs, j);
1776 EXECUTE_IF_SET_IN_REG_SET
1777 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1779 count_spilled_pseudo (best_reg, rl->nregs, j);
1782 for (i = 0; i < rl->nregs; i++)
1784 if (spill_cost[best_reg + i] != 0
1785 || spill_add_cost[best_reg + i] != 0)
1787 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1792 /* Find more reload regs to satisfy the remaining need of an insn, which
1794 Do it by ascending class number, since otherwise a reg
1795 might be spilled for a big class and might fail to count
1796 for a smaller class even though it belongs to that class. */
1799 find_reload_regs (chain)
1800 struct insn_chain *chain;
1804 /* In order to be certain of getting the registers we need,
1805 we must sort the reloads into order of increasing register class.
1806 Then our grabbing of reload registers will parallel the process
1807 that provided the reload registers. */
1808 for (i = 0; i < chain->n_reloads; i++)
1810 /* Show whether this reload already has a hard reg. */
1811 if (chain->rld[i].reg_rtx)
1813 int regno = REGNO (chain->rld[i].reg_rtx);
1814 chain->rld[i].regno = regno;
1816 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1819 chain->rld[i].regno = -1;
1820 reload_order[i] = i;
1823 n_reloads = chain->n_reloads;
1824 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1826 CLEAR_HARD_REG_SET (used_spill_regs_local);
1829 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1831 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1833 /* Compute the order of preference for hard registers to spill. */
1835 order_regs_for_reload (chain);
1837 for (i = 0; i < n_reloads; i++)
1839 int r = reload_order[i];
1841 /* Ignore reloads that got marked inoperative. */
1842 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1843 && ! rld[r].optional
1844 && rld[r].regno == -1)
1845 if (! find_reg (chain, i))
1847 spill_failure (chain->insn, rld[r].class);
1853 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1854 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1856 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1860 select_reload_regs ()
1862 struct insn_chain *chain;
1864 /* Try to satisfy the needs for each insn. */
1865 for (chain = insns_need_reload; chain != 0;
1866 chain = chain->next_need_reload)
1867 find_reload_regs (chain);
1870 /* Delete all insns that were inserted by emit_caller_save_insns during
1873 delete_caller_save_insns ()
1875 struct insn_chain *c = reload_insn_chain;
1879 while (c != 0 && c->is_caller_save_insn)
1881 struct insn_chain *next = c->next;
1884 if (c == reload_insn_chain)
1885 reload_insn_chain = next;
1889 next->prev = c->prev;
1891 c->prev->next = next;
1892 c->next = unused_insn_chains;
1893 unused_insn_chains = c;
1901 /* Handle the failure to find a register to spill.
1902 INSN should be one of the insns which needed this particular spill reg. */
1905 spill_failure (insn, class)
1907 enum reg_class class;
1909 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1910 if (asm_noperands (PATTERN (insn)) >= 0)
1911 error_for_asm (insn, "can't find a register in class `%s' while reloading `asm'",
1912 reg_class_names[class]);
1915 error ("unable to find a register to spill in class `%s'",
1916 reg_class_names[class]);
1917 fatal_insn ("this is the insn:", insn);
1921 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1922 data that is dead in INSN. */
1925 delete_dead_insn (insn)
1928 rtx prev = prev_real_insn (insn);
1931 /* If the previous insn sets a register that dies in our insn, delete it
1933 if (prev && GET_CODE (PATTERN (prev)) == SET
1934 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1935 && reg_mentioned_p (prev_dest, PATTERN (insn))
1936 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1937 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1938 delete_dead_insn (prev);
1940 PUT_CODE (insn, NOTE);
1941 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1942 NOTE_SOURCE_FILE (insn) = 0;
1945 /* Modify the home of pseudo-reg I.
1946 The new home is present in reg_renumber[I].
1948 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1949 or it may be -1, meaning there is none or it is not relevant.
1950 This is used so that all pseudos spilled from a given hard reg
1951 can share one stack slot. */
1954 alter_reg (i, from_reg)
1958 /* When outputting an inline function, this can happen
1959 for a reg that isn't actually used. */
1960 if (regno_reg_rtx[i] == 0)
1963 /* If the reg got changed to a MEM at rtl-generation time,
1965 if (GET_CODE (regno_reg_rtx[i]) != REG)
1968 /* Modify the reg-rtx to contain the new hard reg
1969 number or else to contain its pseudo reg number. */
1970 REGNO (regno_reg_rtx[i])
1971 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1973 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1974 allocate a stack slot for it. */
1976 if (reg_renumber[i] < 0
1977 && REG_N_REFS (i) > 0
1978 && reg_equiv_constant[i] == 0
1979 && reg_equiv_memory_loc[i] == 0)
1982 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1983 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1986 /* Each pseudo reg has an inherent size which comes from its own mode,
1987 and a total size which provides room for paradoxical subregs
1988 which refer to the pseudo reg in wider modes.
1990 We can use a slot already allocated if it provides both
1991 enough inherent space and enough total space.
1992 Otherwise, we allocate a new slot, making sure that it has no less
1993 inherent space, and no less total space, then the previous slot. */
1996 /* No known place to spill from => no slot to reuse. */
1997 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1998 inherent_size == total_size ? 0 : -1);
1999 if (BYTES_BIG_ENDIAN)
2000 /* Cancel the big-endian correction done in assign_stack_local.
2001 Get the address of the beginning of the slot.
2002 This is so we can do a big-endian correction unconditionally
2004 adjust = inherent_size - total_size;
2006 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2008 /* Nothing can alias this slot except this pseudo. */
2009 set_mem_alias_set (x, new_alias_set ());
2012 /* Reuse a stack slot if possible. */
2013 else if (spill_stack_slot[from_reg] != 0
2014 && spill_stack_slot_width[from_reg] >= total_size
2015 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2017 x = spill_stack_slot[from_reg];
2019 /* Allocate a bigger slot. */
2022 /* Compute maximum size needed, both for inherent size
2023 and for total size. */
2024 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2027 if (spill_stack_slot[from_reg])
2029 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2031 mode = GET_MODE (spill_stack_slot[from_reg]);
2032 if (spill_stack_slot_width[from_reg] > total_size)
2033 total_size = spill_stack_slot_width[from_reg];
2036 /* Make a slot with that size. */
2037 x = assign_stack_local (mode, total_size,
2038 inherent_size == total_size ? 0 : -1);
2041 /* All pseudos mapped to this slot can alias each other. */
2042 if (spill_stack_slot[from_reg])
2043 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2045 set_mem_alias_set (x, new_alias_set ());
2047 if (BYTES_BIG_ENDIAN)
2049 /* Cancel the big-endian correction done in assign_stack_local.
2050 Get the address of the beginning of the slot.
2051 This is so we can do a big-endian correction unconditionally
2053 adjust = GET_MODE_SIZE (mode) - total_size;
2056 = adjust_address_nv (x, mode_for_size (total_size
2062 spill_stack_slot[from_reg] = stack_slot;
2063 spill_stack_slot_width[from_reg] = total_size;
2066 /* On a big endian machine, the "address" of the slot
2067 is the address of the low part that fits its inherent mode. */
2068 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2069 adjust += (total_size - inherent_size);
2071 /* If we have any adjustment to make, or if the stack slot is the
2072 wrong mode, make a new stack slot. */
2073 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2075 /* If we have a decl for the original register, set it for the
2076 memory. If this is a shared MEM, make a copy. */
2077 if (REG_EXPR (regno_reg_rtx[i])
2078 && TREE_CODE_CLASS (TREE_CODE (REG_EXPR (regno_reg_rtx[i]))) == 'd')
2080 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2082 /* We can do this only for the DECLs home pseudo, not for
2083 any copies of it, since otherwise when the stack slot
2084 is reused, nonoverlapping_memrefs_p might think they
2086 if (decl && GET_CODE (decl) == REG && REGNO (decl) == (unsigned) i)
2088 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2091 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2095 /* Save the stack slot for later. */
2096 reg_equiv_memory_loc[i] = x;
2100 /* Mark the slots in regs_ever_live for the hard regs
2101 used by pseudo-reg number REGNO. */
2104 mark_home_live (regno)
2109 i = reg_renumber[regno];
2112 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2114 regs_ever_live[i++] = 1;
2117 /* This function handles the tracking of elimination offsets around branches.
2119 X is a piece of RTL being scanned.
2121 INSN is the insn that it came from, if any.
2123 INITIAL_P is nonzero if we are to set the offset to be the initial
2124 offset and zero if we are setting the offset of the label to be the
2128 set_label_offsets (x, insn, initial_p)
2133 enum rtx_code code = GET_CODE (x);
2136 struct elim_table *p;
2141 if (LABEL_REF_NONLOCAL_P (x))
2146 /* ... fall through ... */
2149 /* If we know nothing about this label, set the desired offsets. Note
2150 that this sets the offset at a label to be the offset before a label
2151 if we don't know anything about the label. This is not correct for
2152 the label after a BARRIER, but is the best guess we can make. If
2153 we guessed wrong, we will suppress an elimination that might have
2154 been possible had we been able to guess correctly. */
2156 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2158 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2159 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2160 = (initial_p ? reg_eliminate[i].initial_offset
2161 : reg_eliminate[i].offset);
2162 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2165 /* Otherwise, if this is the definition of a label and it is
2166 preceded by a BARRIER, set our offsets to the known offset of
2170 && (tem = prev_nonnote_insn (insn)) != 0
2171 && GET_CODE (tem) == BARRIER)
2172 set_offsets_for_label (insn);
2174 /* If neither of the above cases is true, compare each offset
2175 with those previously recorded and suppress any eliminations
2176 where the offsets disagree. */
2178 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2179 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2180 != (initial_p ? reg_eliminate[i].initial_offset
2181 : reg_eliminate[i].offset))
2182 reg_eliminate[i].can_eliminate = 0;
2187 set_label_offsets (PATTERN (insn), insn, initial_p);
2189 /* ... fall through ... */
2193 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2194 and hence must have all eliminations at their initial offsets. */
2195 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2196 if (REG_NOTE_KIND (tem) == REG_LABEL)
2197 set_label_offsets (XEXP (tem, 0), insn, 1);
2203 /* Each of the labels in the parallel or address vector must be
2204 at their initial offsets. We want the first field for PARALLEL
2205 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2207 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2208 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2213 /* We only care about setting PC. If the source is not RETURN,
2214 IF_THEN_ELSE, or a label, disable any eliminations not at
2215 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2216 isn't one of those possibilities. For branches to a label,
2217 call ourselves recursively.
2219 Note that this can disable elimination unnecessarily when we have
2220 a non-local goto since it will look like a non-constant jump to
2221 someplace in the current function. This isn't a significant
2222 problem since such jumps will normally be when all elimination
2223 pairs are back to their initial offsets. */
2225 if (SET_DEST (x) != pc_rtx)
2228 switch (GET_CODE (SET_SRC (x)))
2235 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2239 tem = XEXP (SET_SRC (x), 1);
2240 if (GET_CODE (tem) == LABEL_REF)
2241 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2242 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2245 tem = XEXP (SET_SRC (x), 2);
2246 if (GET_CODE (tem) == LABEL_REF)
2247 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2248 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2256 /* If we reach here, all eliminations must be at their initial
2257 offset because we are doing a jump to a variable address. */
2258 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2259 if (p->offset != p->initial_offset)
2260 p->can_eliminate = 0;
2268 /* Scan X and replace any eliminable registers (such as fp) with a
2269 replacement (such as sp), plus an offset.
2271 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2272 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2273 MEM, we are allowed to replace a sum of a register and the constant zero
2274 with the register, which we cannot do outside a MEM. In addition, we need
2275 to record the fact that a register is referenced outside a MEM.
2277 If INSN is an insn, it is the insn containing X. If we replace a REG
2278 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2279 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2280 the REG is being modified.
2282 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2283 That's used when we eliminate in expressions stored in notes.
2284 This means, do not set ref_outside_mem even if the reference
2287 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2288 replacements done assuming all offsets are at their initial values. If
2289 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2290 encounter, return the actual location so that find_reloads will do
2291 the proper thing. */
2294 eliminate_regs (x, mem_mode, insn)
2296 enum machine_mode mem_mode;
2299 enum rtx_code code = GET_CODE (x);
2300 struct elim_table *ep;
2307 if (! current_function_decl)
2327 /* This is only for the benefit of the debugging backends, which call
2328 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2329 removed after CSE. */
2330 new = eliminate_regs (XEXP (x, 0), 0, insn);
2331 if (GET_CODE (new) == MEM)
2332 return XEXP (new, 0);
2338 /* First handle the case where we encounter a bare register that
2339 is eliminable. Replace it with a PLUS. */
2340 if (regno < FIRST_PSEUDO_REGISTER)
2342 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2344 if (ep->from_rtx == x && ep->can_eliminate)
2345 return plus_constant (ep->to_rtx, ep->previous_offset);
2348 else if (reg_renumber && reg_renumber[regno] < 0
2349 && reg_equiv_constant && reg_equiv_constant[regno]
2350 && ! CONSTANT_P (reg_equiv_constant[regno]))
2351 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2355 /* You might think handling MINUS in a manner similar to PLUS is a
2356 good idea. It is not. It has been tried multiple times and every
2357 time the change has had to have been reverted.
2359 Other parts of reload know a PLUS is special (gen_reload for example)
2360 and require special code to handle code a reloaded PLUS operand.
2362 Also consider backends where the flags register is clobbered by a
2363 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2364 lea instruction comes to mind). If we try to reload a MINUS, we
2365 may kill the flags register that was holding a useful value.
2367 So, please before trying to handle MINUS, consider reload as a
2368 whole instead of this little section as well as the backend issues. */
2370 /* If this is the sum of an eliminable register and a constant, rework
2372 if (GET_CODE (XEXP (x, 0)) == REG
2373 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2374 && CONSTANT_P (XEXP (x, 1)))
2376 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2378 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2380 /* The only time we want to replace a PLUS with a REG (this
2381 occurs when the constant operand of the PLUS is the negative
2382 of the offset) is when we are inside a MEM. We won't want
2383 to do so at other times because that would change the
2384 structure of the insn in a way that reload can't handle.
2385 We special-case the commonest situation in
2386 eliminate_regs_in_insn, so just replace a PLUS with a
2387 PLUS here, unless inside a MEM. */
2388 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2389 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2392 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2393 plus_constant (XEXP (x, 1),
2394 ep->previous_offset));
2397 /* If the register is not eliminable, we are done since the other
2398 operand is a constant. */
2402 /* If this is part of an address, we want to bring any constant to the
2403 outermost PLUS. We will do this by doing register replacement in
2404 our operands and seeing if a constant shows up in one of them.
2406 Note that there is no risk of modifying the structure of the insn,
2407 since we only get called for its operands, thus we are either
2408 modifying the address inside a MEM, or something like an address
2409 operand of a load-address insn. */
2412 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2413 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2415 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2417 /* If one side is a PLUS and the other side is a pseudo that
2418 didn't get a hard register but has a reg_equiv_constant,
2419 we must replace the constant here since it may no longer
2420 be in the position of any operand. */
2421 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2422 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2423 && reg_renumber[REGNO (new1)] < 0
2424 && reg_equiv_constant != 0
2425 && reg_equiv_constant[REGNO (new1)] != 0)
2426 new1 = reg_equiv_constant[REGNO (new1)];
2427 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2428 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2429 && reg_renumber[REGNO (new0)] < 0
2430 && reg_equiv_constant[REGNO (new0)] != 0)
2431 new0 = reg_equiv_constant[REGNO (new0)];
2433 new = form_sum (new0, new1);
2435 /* As above, if we are not inside a MEM we do not want to
2436 turn a PLUS into something else. We might try to do so here
2437 for an addition of 0 if we aren't optimizing. */
2438 if (! mem_mode && GET_CODE (new) != PLUS)
2439 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2447 /* If this is the product of an eliminable register and a
2448 constant, apply the distribute law and move the constant out
2449 so that we have (plus (mult ..) ..). This is needed in order
2450 to keep load-address insns valid. This case is pathological.
2451 We ignore the possibility of overflow here. */
2452 if (GET_CODE (XEXP (x, 0)) == REG
2453 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2454 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2455 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2457 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2460 /* Refs inside notes don't count for this purpose. */
2461 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2462 || GET_CODE (insn) == INSN_LIST)))
2463 ep->ref_outside_mem = 1;
2466 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2467 ep->previous_offset * INTVAL (XEXP (x, 1)));
2470 /* ... fall through ... */
2474 /* See comments before PLUS about handling MINUS. */
2476 case DIV: case UDIV:
2477 case MOD: case UMOD:
2478 case AND: case IOR: case XOR:
2479 case ROTATERT: case ROTATE:
2480 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2482 case GE: case GT: case GEU: case GTU:
2483 case LE: case LT: case LEU: case LTU:
2485 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2487 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2489 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2490 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2495 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2498 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2499 if (new != XEXP (x, 0))
2501 /* If this is a REG_DEAD note, it is not valid anymore.
2502 Using the eliminated version could result in creating a
2503 REG_DEAD note for the stack or frame pointer. */
2504 if (GET_MODE (x) == REG_DEAD)
2506 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2509 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2513 /* ... fall through ... */
2516 /* Now do eliminations in the rest of the chain. If this was
2517 an EXPR_LIST, this might result in allocating more memory than is
2518 strictly needed, but it simplifies the code. */
2521 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2522 if (new != XEXP (x, 1))
2524 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2532 case STRICT_LOW_PART:
2534 case SIGN_EXTEND: case ZERO_EXTEND:
2535 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2536 case FLOAT: case FIX:
2537 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2545 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2546 if (new != XEXP (x, 0))
2547 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2551 /* Similar to above processing, but preserve SUBREG_BYTE.
2552 Convert (subreg (mem)) to (mem) if not paradoxical.
2553 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2554 pseudo didn't get a hard reg, we must replace this with the
2555 eliminated version of the memory location because push_reloads
2556 may do the replacement in certain circumstances. */
2557 if (GET_CODE (SUBREG_REG (x)) == REG
2558 && (GET_MODE_SIZE (GET_MODE (x))
2559 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2560 && reg_equiv_memory_loc != 0
2561 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2563 new = SUBREG_REG (x);
2566 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2568 if (new != SUBREG_REG (x))
2570 int x_size = GET_MODE_SIZE (GET_MODE (x));
2571 int new_size = GET_MODE_SIZE (GET_MODE (new));
2573 if (GET_CODE (new) == MEM
2574 && ((x_size < new_size
2575 #ifdef WORD_REGISTER_OPERATIONS
2576 /* On these machines, combine can create rtl of the form
2577 (set (subreg:m1 (reg:m2 R) 0) ...)
2578 where m1 < m2, and expects something interesting to
2579 happen to the entire word. Moreover, it will use the
2580 (reg:m2 R) later, expecting all bits to be preserved.
2581 So if the number of words is the same, preserve the
2582 subreg so that push_reloads can see it. */
2583 && ! ((x_size - 1) / UNITS_PER_WORD
2584 == (new_size -1 ) / UNITS_PER_WORD)
2587 || x_size == new_size)
2589 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2591 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2597 /* This is only for the benefit of the debugging backends, which call
2598 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2599 removed after CSE. */
2600 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2601 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2603 /* Our only special processing is to pass the mode of the MEM to our
2604 recursive call and copy the flags. While we are here, handle this
2605 case more efficiently. */
2607 replace_equiv_address_nv (x,
2608 eliminate_regs (XEXP (x, 0),
2609 GET_MODE (x), insn));
2612 /* Handle insn_list USE that a call to a pure function may generate. */
2613 new = eliminate_regs (XEXP (x, 0), 0, insn);
2614 if (new != XEXP (x, 0))
2615 return gen_rtx_USE (GET_MODE (x), new);
2627 /* Process each of our operands recursively. If any have changed, make a
2629 fmt = GET_RTX_FORMAT (code);
2630 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2634 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2635 if (new != XEXP (x, i) && ! copied)
2637 rtx new_x = rtx_alloc (code);
2639 (sizeof (*new_x) - sizeof (new_x->fld)
2640 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2646 else if (*fmt == 'E')
2649 for (j = 0; j < XVECLEN (x, i); j++)
2651 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2652 if (new != XVECEXP (x, i, j) && ! copied_vec)
2654 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2658 rtx new_x = rtx_alloc (code);
2660 (sizeof (*new_x) - sizeof (new_x->fld)
2661 + (sizeof (new_x->fld[0])
2662 * GET_RTX_LENGTH (code))));
2666 XVEC (x, i) = new_v;
2669 XVECEXP (x, i, j) = new;
2677 /* Scan rtx X for modifications of elimination target registers. Update
2678 the table of eliminables to reflect the changed state. MEM_MODE is
2679 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2682 elimination_effects (x, mem_mode)
2684 enum machine_mode mem_mode;
2687 enum rtx_code code = GET_CODE (x);
2688 struct elim_table *ep;
2715 /* First handle the case where we encounter a bare register that
2716 is eliminable. Replace it with a PLUS. */
2717 if (regno < FIRST_PSEUDO_REGISTER)
2719 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2721 if (ep->from_rtx == x && ep->can_eliminate)
2724 ep->ref_outside_mem = 1;
2729 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2730 && reg_equiv_constant[regno]
2731 && ! function_invariant_p (reg_equiv_constant[regno]))
2732 elimination_effects (reg_equiv_constant[regno], mem_mode);
2741 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2742 if (ep->to_rtx == XEXP (x, 0))
2744 int size = GET_MODE_SIZE (mem_mode);
2746 /* If more bytes than MEM_MODE are pushed, account for them. */
2747 #ifdef PUSH_ROUNDING
2748 if (ep->to_rtx == stack_pointer_rtx)
2749 size = PUSH_ROUNDING (size);
2751 if (code == PRE_DEC || code == POST_DEC)
2753 else if (code == PRE_INC || code == POST_INC)
2755 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2756 && GET_CODE (XEXP (x, 1)) == PLUS
2757 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2758 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2759 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2762 /* These two aren't unary operators. */
2763 if (code == POST_MODIFY || code == PRE_MODIFY)
2766 /* Fall through to generic unary operation case. */
2767 case STRICT_LOW_PART:
2769 case SIGN_EXTEND: case ZERO_EXTEND:
2770 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2771 case FLOAT: case FIX:
2772 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2780 elimination_effects (XEXP (x, 0), mem_mode);
2784 if (GET_CODE (SUBREG_REG (x)) == REG
2785 && (GET_MODE_SIZE (GET_MODE (x))
2786 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2787 && reg_equiv_memory_loc != 0
2788 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2791 elimination_effects (SUBREG_REG (x), mem_mode);
2795 /* If using a register that is the source of an eliminate we still
2796 think can be performed, note it cannot be performed since we don't
2797 know how this register is used. */
2798 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2799 if (ep->from_rtx == XEXP (x, 0))
2800 ep->can_eliminate = 0;
2802 elimination_effects (XEXP (x, 0), mem_mode);
2806 /* If clobbering a register that is the replacement register for an
2807 elimination we still think can be performed, note that it cannot
2808 be performed. Otherwise, we need not be concerned about it. */
2809 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2810 if (ep->to_rtx == XEXP (x, 0))
2811 ep->can_eliminate = 0;
2813 elimination_effects (XEXP (x, 0), mem_mode);
2817 /* Check for setting a register that we know about. */
2818 if (GET_CODE (SET_DEST (x)) == REG)
2820 /* See if this is setting the replacement register for an
2823 If DEST is the hard frame pointer, we do nothing because we
2824 assume that all assignments to the frame pointer are for
2825 non-local gotos and are being done at a time when they are valid
2826 and do not disturb anything else. Some machines want to
2827 eliminate a fake argument pointer (or even a fake frame pointer)
2828 with either the real frame or the stack pointer. Assignments to
2829 the hard frame pointer must not prevent this elimination. */
2831 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2833 if (ep->to_rtx == SET_DEST (x)
2834 && SET_DEST (x) != hard_frame_pointer_rtx)
2836 /* If it is being incremented, adjust the offset. Otherwise,
2837 this elimination can't be done. */
2838 rtx src = SET_SRC (x);
2840 if (GET_CODE (src) == PLUS
2841 && XEXP (src, 0) == SET_DEST (x)
2842 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2843 ep->offset -= INTVAL (XEXP (src, 1));
2845 ep->can_eliminate = 0;
2849 elimination_effects (SET_DEST (x), 0);
2850 elimination_effects (SET_SRC (x), 0);
2854 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2857 /* Our only special processing is to pass the mode of the MEM to our
2859 elimination_effects (XEXP (x, 0), GET_MODE (x));
2866 fmt = GET_RTX_FORMAT (code);
2867 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2870 elimination_effects (XEXP (x, i), mem_mode);
2871 else if (*fmt == 'E')
2872 for (j = 0; j < XVECLEN (x, i); j++)
2873 elimination_effects (XVECEXP (x, i, j), mem_mode);
2877 /* Descend through rtx X and verify that no references to eliminable registers
2878 remain. If any do remain, mark the involved register as not
2882 check_eliminable_occurrences (x)
2892 code = GET_CODE (x);
2894 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2896 struct elim_table *ep;
2898 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2899 if (ep->from_rtx == x && ep->can_eliminate)
2900 ep->can_eliminate = 0;
2904 fmt = GET_RTX_FORMAT (code);
2905 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2908 check_eliminable_occurrences (XEXP (x, i));
2909 else if (*fmt == 'E')
2912 for (j = 0; j < XVECLEN (x, i); j++)
2913 check_eliminable_occurrences (XVECEXP (x, i, j));
2918 /* Scan INSN and eliminate all eliminable registers in it.
2920 If REPLACE is nonzero, do the replacement destructively. Also
2921 delete the insn as dead it if it is setting an eliminable register.
2923 If REPLACE is zero, do all our allocations in reload_obstack.
2925 If no eliminations were done and this insn doesn't require any elimination
2926 processing (these are not identical conditions: it might be updating sp,
2927 but not referencing fp; this needs to be seen during reload_as_needed so
2928 that the offset between fp and sp can be taken into consideration), zero
2929 is returned. Otherwise, 1 is returned. */
2932 eliminate_regs_in_insn (insn, replace)
2936 int icode = recog_memoized (insn);
2937 rtx old_body = PATTERN (insn);
2938 int insn_is_asm = asm_noperands (old_body) >= 0;
2939 rtx old_set = single_set (insn);
2943 rtx substed_operand[MAX_RECOG_OPERANDS];
2944 rtx orig_operand[MAX_RECOG_OPERANDS];
2945 struct elim_table *ep;
2947 if (! insn_is_asm && icode < 0)
2949 if (GET_CODE (PATTERN (insn)) == USE
2950 || GET_CODE (PATTERN (insn)) == CLOBBER
2951 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2952 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2953 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2958 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2959 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2961 /* Check for setting an eliminable register. */
2962 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2963 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2965 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2966 /* If this is setting the frame pointer register to the
2967 hardware frame pointer register and this is an elimination
2968 that will be done (tested above), this insn is really
2969 adjusting the frame pointer downward to compensate for
2970 the adjustment done before a nonlocal goto. */
2971 if (ep->from == FRAME_POINTER_REGNUM
2972 && ep->to == HARD_FRAME_POINTER_REGNUM)
2974 rtx base = SET_SRC (old_set);
2975 rtx base_insn = insn;
2978 while (base != ep->to_rtx)
2980 rtx prev_insn, prev_set;
2982 if (GET_CODE (base) == PLUS
2983 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2985 offset += INTVAL (XEXP (base, 1));
2986 base = XEXP (base, 0);
2988 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2989 && (prev_set = single_set (prev_insn)) != 0
2990 && rtx_equal_p (SET_DEST (prev_set), base))
2992 base = SET_SRC (prev_set);
2993 base_insn = prev_insn;
2999 if (base == ep->to_rtx)
3002 = plus_constant (ep->to_rtx, offset - ep->offset);
3004 new_body = old_body;
3007 new_body = copy_insn (old_body);
3008 if (REG_NOTES (insn))
3009 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3011 PATTERN (insn) = new_body;
3012 old_set = single_set (insn);
3014 /* First see if this insn remains valid when we
3015 make the change. If not, keep the INSN_CODE
3016 the same and let reload fit it up. */
3017 validate_change (insn, &SET_SRC (old_set), src, 1);
3018 validate_change (insn, &SET_DEST (old_set),
3020 if (! apply_change_group ())
3022 SET_SRC (old_set) = src;
3023 SET_DEST (old_set) = ep->to_rtx;
3032 /* In this case this insn isn't serving a useful purpose. We
3033 will delete it in reload_as_needed once we know that this
3034 elimination is, in fact, being done.
3036 If REPLACE isn't set, we can't delete this insn, but needn't
3037 process it since it won't be used unless something changes. */
3040 delete_dead_insn (insn);
3048 /* We allow one special case which happens to work on all machines we
3049 currently support: a single set with the source being a PLUS of an
3050 eliminable register and a constant. */
3052 && GET_CODE (SET_DEST (old_set)) == REG
3053 && GET_CODE (SET_SRC (old_set)) == PLUS
3054 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3055 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
3056 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
3058 rtx reg = XEXP (SET_SRC (old_set), 0);
3059 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
3061 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3062 if (ep->from_rtx == reg && ep->can_eliminate)
3064 offset += ep->offset;
3069 /* We assume here that if we need a PARALLEL with
3070 CLOBBERs for this assignment, we can do with the
3071 MATCH_SCRATCHes that add_clobbers allocates.
3072 There's not much we can do if that doesn't work. */
3073 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3077 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3080 rtvec vec = rtvec_alloc (num_clobbers + 1);
3082 vec->elem[0] = PATTERN (insn);
3083 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3084 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3086 if (INSN_CODE (insn) < 0)
3091 new_body = old_body;
3094 new_body = copy_insn (old_body);
3095 if (REG_NOTES (insn))
3096 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3098 PATTERN (insn) = new_body;
3099 old_set = single_set (insn);
3101 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3102 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3105 /* This can't have an effect on elimination offsets, so skip right
3111 /* Determine the effects of this insn on elimination offsets. */
3112 elimination_effects (old_body, 0);
3114 /* Eliminate all eliminable registers occurring in operands that
3115 can be handled by reload. */
3116 extract_insn (insn);
3117 for (i = 0; i < recog_data.n_operands; i++)
3119 orig_operand[i] = recog_data.operand[i];
3120 substed_operand[i] = recog_data.operand[i];
3122 /* For an asm statement, every operand is eliminable. */
3123 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3125 /* Check for setting a register that we know about. */
3126 if (recog_data.operand_type[i] != OP_IN
3127 && GET_CODE (orig_operand[i]) == REG)
3129 /* If we are assigning to a register that can be eliminated, it
3130 must be as part of a PARALLEL, since the code above handles
3131 single SETs. We must indicate that we can no longer
3132 eliminate this reg. */
3133 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3135 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3136 ep->can_eliminate = 0;
3139 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3140 replace ? insn : NULL_RTX);
3141 if (substed_operand[i] != orig_operand[i])
3143 /* Terminate the search in check_eliminable_occurrences at
3145 *recog_data.operand_loc[i] = 0;
3147 /* If an output operand changed from a REG to a MEM and INSN is an
3148 insn, write a CLOBBER insn. */
3149 if (recog_data.operand_type[i] != OP_IN
3150 && GET_CODE (orig_operand[i]) == REG
3151 && GET_CODE (substed_operand[i]) == MEM
3153 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3158 for (i = 0; i < recog_data.n_dups; i++)
3159 *recog_data.dup_loc[i]
3160 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3162 /* If any eliminable remain, they aren't eliminable anymore. */
3163 check_eliminable_occurrences (old_body);
3165 /* Substitute the operands; the new values are in the substed_operand
3167 for (i = 0; i < recog_data.n_operands; i++)
3168 *recog_data.operand_loc[i] = substed_operand[i];
3169 for (i = 0; i < recog_data.n_dups; i++)
3170 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3172 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3173 re-recognize the insn. We do this in case we had a simple addition
3174 but now can do this as a load-address. This saves an insn in this
3176 If re-recognition fails, the old insn code number will still be used,
3177 and some register operands may have changed into PLUS expressions.
3178 These will be handled by find_reloads by loading them into a register
3183 /* If we aren't replacing things permanently and we changed something,
3184 make another copy to ensure that all the RTL is new. Otherwise
3185 things can go wrong if find_reload swaps commutative operands
3186 and one is inside RTL that has been copied while the other is not. */
3187 new_body = old_body;
3190 new_body = copy_insn (old_body);
3191 if (REG_NOTES (insn))
3192 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3194 PATTERN (insn) = new_body;
3196 /* If we had a move insn but now we don't, rerecognize it. This will
3197 cause spurious re-recognition if the old move had a PARALLEL since
3198 the new one still will, but we can't call single_set without
3199 having put NEW_BODY into the insn and the re-recognition won't
3200 hurt in this rare case. */
3201 /* ??? Why this huge if statement - why don't we just rerecognize the
3205 && ((GET_CODE (SET_SRC (old_set)) == REG
3206 && (GET_CODE (new_body) != SET
3207 || GET_CODE (SET_SRC (new_body)) != REG))
3208 /* If this was a load from or store to memory, compare
3209 the MEM in recog_data.operand to the one in the insn.
3210 If they are not equal, then rerecognize the insn. */
3212 && ((GET_CODE (SET_SRC (old_set)) == MEM
3213 && SET_SRC (old_set) != recog_data.operand[1])
3214 || (GET_CODE (SET_DEST (old_set)) == MEM
3215 && SET_DEST (old_set) != recog_data.operand[0])))
3216 /* If this was an add insn before, rerecognize. */
3217 || GET_CODE (SET_SRC (old_set)) == PLUS))
3219 int new_icode = recog (PATTERN (insn), insn, 0);
3221 INSN_CODE (insn) = icode;
3225 /* Restore the old body. If there were any changes to it, we made a copy
3226 of it while the changes were still in place, so we'll correctly return
3227 a modified insn below. */
3230 /* Restore the old body. */
3231 for (i = 0; i < recog_data.n_operands; i++)
3232 *recog_data.operand_loc[i] = orig_operand[i];
3233 for (i = 0; i < recog_data.n_dups; i++)
3234 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3237 /* Update all elimination pairs to reflect the status after the current
3238 insn. The changes we make were determined by the earlier call to
3239 elimination_effects.
3241 We also detect cases where register elimination cannot be done,
3242 namely, if a register would be both changed and referenced outside a MEM
3243 in the resulting insn since such an insn is often undefined and, even if
3244 not, we cannot know what meaning will be given to it. Note that it is
3245 valid to have a register used in an address in an insn that changes it
3246 (presumably with a pre- or post-increment or decrement).
3248 If anything changes, return nonzero. */
3250 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3252 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3253 ep->can_eliminate = 0;
3255 ep->ref_outside_mem = 0;
3257 if (ep->previous_offset != ep->offset)
3262 /* If we changed something, perform elimination in REG_NOTES. This is
3263 needed even when REPLACE is zero because a REG_DEAD note might refer
3264 to a register that we eliminate and could cause a different number
3265 of spill registers to be needed in the final reload pass than in
3267 if (val && REG_NOTES (insn) != 0)
3268 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3273 /* Loop through all elimination pairs.
3274 Recalculate the number not at initial offset.
3276 Compute the maximum offset (minimum offset if the stack does not
3277 grow downward) for each elimination pair. */
3280 update_eliminable_offsets ()
3282 struct elim_table *ep;
3284 num_not_at_initial_offset = 0;
3285 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3287 ep->previous_offset = ep->offset;
3288 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3289 num_not_at_initial_offset++;
3293 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3294 replacement we currently believe is valid, mark it as not eliminable if X
3295 modifies DEST in any way other than by adding a constant integer to it.
3297 If DEST is the frame pointer, we do nothing because we assume that
3298 all assignments to the hard frame pointer are nonlocal gotos and are being
3299 done at a time when they are valid and do not disturb anything else.
3300 Some machines want to eliminate a fake argument pointer with either the
3301 frame or stack pointer. Assignments to the hard frame pointer must not
3302 prevent this elimination.
3304 Called via note_stores from reload before starting its passes to scan
3305 the insns of the function. */
3308 mark_not_eliminable (dest, x, data)
3311 void *data ATTRIBUTE_UNUSED;
3315 /* A SUBREG of a hard register here is just changing its mode. We should
3316 not see a SUBREG of an eliminable hard register, but check just in
3318 if (GET_CODE (dest) == SUBREG)
3319 dest = SUBREG_REG (dest);
3321 if (dest == hard_frame_pointer_rtx)
3324 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3325 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3326 && (GET_CODE (x) != SET
3327 || GET_CODE (SET_SRC (x)) != PLUS
3328 || XEXP (SET_SRC (x), 0) != dest
3329 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3331 reg_eliminate[i].can_eliminate_previous
3332 = reg_eliminate[i].can_eliminate = 0;
3337 /* Verify that the initial elimination offsets did not change since the
3338 last call to set_initial_elim_offsets. This is used to catch cases
3339 where something illegal happened during reload_as_needed that could
3340 cause incorrect code to be generated if we did not check for it. */
3343 verify_initial_elim_offsets ()
3347 #ifdef ELIMINABLE_REGS
3348 struct elim_table *ep;
3350 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3352 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3353 if (t != ep->initial_offset)
3357 INITIAL_FRAME_POINTER_OFFSET (t);
3358 if (t != reg_eliminate[0].initial_offset)
3363 /* Reset all offsets on eliminable registers to their initial values. */
3366 set_initial_elim_offsets ()
3368 struct elim_table *ep = reg_eliminate;
3370 #ifdef ELIMINABLE_REGS
3371 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3373 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3374 ep->previous_offset = ep->offset = ep->initial_offset;
3377 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3378 ep->previous_offset = ep->offset = ep->initial_offset;
3381 num_not_at_initial_offset = 0;
3384 /* Initialize the known label offsets.
3385 Set a known offset for each forced label to be at the initial offset
3386 of each elimination. We do this because we assume that all
3387 computed jumps occur from a location where each elimination is
3388 at its initial offset.
3389 For all other labels, show that we don't know the offsets. */
3392 set_initial_label_offsets ()
3395 memset (offsets_known_at, 0, num_labels);
3397 for (x = forced_labels; x; x = XEXP (x, 1))
3399 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3402 /* Set all elimination offsets to the known values for the code label given
3406 set_offsets_for_label (insn)
3410 int label_nr = CODE_LABEL_NUMBER (insn);
3411 struct elim_table *ep;
3413 num_not_at_initial_offset = 0;
3414 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3416 ep->offset = ep->previous_offset
3417 = offsets_at[label_nr - first_label_num][i];
3418 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3419 num_not_at_initial_offset++;
3423 /* See if anything that happened changes which eliminations are valid.
3424 For example, on the SPARC, whether or not the frame pointer can
3425 be eliminated can depend on what registers have been used. We need
3426 not check some conditions again (such as flag_omit_frame_pointer)
3427 since they can't have changed. */
3430 update_eliminables (pset)
3433 int previous_frame_pointer_needed = frame_pointer_needed;
3434 struct elim_table *ep;
3436 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3437 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3438 #ifdef ELIMINABLE_REGS
3439 || ! CAN_ELIMINATE (ep->from, ep->to)
3442 ep->can_eliminate = 0;
3444 /* Look for the case where we have discovered that we can't replace
3445 register A with register B and that means that we will now be
3446 trying to replace register A with register C. This means we can
3447 no longer replace register C with register B and we need to disable
3448 such an elimination, if it exists. This occurs often with A == ap,
3449 B == sp, and C == fp. */
3451 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3453 struct elim_table *op;
3456 if (! ep->can_eliminate && ep->can_eliminate_previous)
3458 /* Find the current elimination for ep->from, if there is a
3460 for (op = reg_eliminate;
3461 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3462 if (op->from == ep->from && op->can_eliminate)
3468 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3470 for (op = reg_eliminate;
3471 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3472 if (op->from == new_to && op->to == ep->to)
3473 op->can_eliminate = 0;
3477 /* See if any registers that we thought we could eliminate the previous
3478 time are no longer eliminable. If so, something has changed and we
3479 must spill the register. Also, recompute the number of eliminable
3480 registers and see if the frame pointer is needed; it is if there is
3481 no elimination of the frame pointer that we can perform. */
3483 frame_pointer_needed = 1;
3484 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3486 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3487 && ep->to != HARD_FRAME_POINTER_REGNUM)
3488 frame_pointer_needed = 0;
3490 if (! ep->can_eliminate && ep->can_eliminate_previous)
3492 ep->can_eliminate_previous = 0;
3493 SET_HARD_REG_BIT (*pset, ep->from);
3498 /* If we didn't need a frame pointer last time, but we do now, spill
3499 the hard frame pointer. */
3500 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3501 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3504 /* Initialize the table of registers to eliminate. */
3509 struct elim_table *ep;
3510 #ifdef ELIMINABLE_REGS
3511 const struct elim_table_1 *ep1;
3515 reg_eliminate = (struct elim_table *)
3516 xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3518 /* Does this function require a frame pointer? */
3520 frame_pointer_needed = (! flag_omit_frame_pointer
3521 #ifdef EXIT_IGNORE_STACK
3522 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3523 and restore sp for alloca. So we can't eliminate
3524 the frame pointer in that case. At some point,
3525 we should improve this by emitting the
3526 sp-adjusting insns for this case. */
3527 || (current_function_calls_alloca
3528 && EXIT_IGNORE_STACK)
3530 || FRAME_POINTER_REQUIRED);
3534 #ifdef ELIMINABLE_REGS
3535 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3536 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3538 ep->from = ep1->from;
3540 ep->can_eliminate = ep->can_eliminate_previous
3541 = (CAN_ELIMINATE (ep->from, ep->to)
3542 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3545 reg_eliminate[0].from = reg_eliminate_1[0].from;
3546 reg_eliminate[0].to = reg_eliminate_1[0].to;
3547 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3548 = ! frame_pointer_needed;
3551 /* Count the number of eliminable registers and build the FROM and TO
3552 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3553 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3554 We depend on this. */
3555 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3557 num_eliminable += ep->can_eliminate;
3558 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3559 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3563 /* Kick all pseudos out of hard register REGNO.
3565 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3566 because we found we can't eliminate some register. In the case, no pseudos
3567 are allowed to be in the register, even if they are only in a block that
3568 doesn't require spill registers, unlike the case when we are spilling this
3569 hard reg to produce another spill register.
3571 Return nonzero if any pseudos needed to be kicked out. */
3574 spill_hard_reg (regno, cant_eliminate)
3582 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3583 regs_ever_live[regno] = 1;
3586 /* Spill every pseudo reg that was allocated to this reg
3587 or to something that overlaps this reg. */
3589 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3590 if (reg_renumber[i] >= 0
3591 && (unsigned int) reg_renumber[i] <= regno
3592 && ((unsigned int) reg_renumber[i]
3593 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3594 PSEUDO_REGNO_MODE (i))
3596 SET_REGNO_REG_SET (&spilled_pseudos, i);
3599 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3600 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3603 ior_hard_reg_set (set1, set2)
3604 HARD_REG_SET *set1, *set2;
3606 IOR_HARD_REG_SET (*set1, *set2);
3609 /* After find_reload_regs has been run for all insn that need reloads,
3610 and/or spill_hard_regs was called, this function is used to actually
3611 spill pseudo registers and try to reallocate them. It also sets up the
3612 spill_regs array for use by choose_reload_regs. */
3615 finish_spills (global)
3618 struct insn_chain *chain;
3619 int something_changed = 0;
3622 /* Build the spill_regs array for the function. */
3623 /* If there are some registers still to eliminate and one of the spill regs
3624 wasn't ever used before, additional stack space may have to be
3625 allocated to store this register. Thus, we may have changed the offset
3626 between the stack and frame pointers, so mark that something has changed.
3628 One might think that we need only set VAL to 1 if this is a call-used
3629 register. However, the set of registers that must be saved by the
3630 prologue is not identical to the call-used set. For example, the
3631 register used by the call insn for the return PC is a call-used register,
3632 but must be saved by the prologue. */
3635 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3636 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3638 spill_reg_order[i] = n_spills;
3639 spill_regs[n_spills++] = i;
3640 if (num_eliminable && ! regs_ever_live[i])
3641 something_changed = 1;
3642 regs_ever_live[i] = 1;
3645 spill_reg_order[i] = -1;
3647 EXECUTE_IF_SET_IN_REG_SET
3648 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3650 /* Record the current hard register the pseudo is allocated to in
3651 pseudo_previous_regs so we avoid reallocating it to the same
3652 hard reg in a later pass. */
3653 if (reg_renumber[i] < 0)
3656 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3657 /* Mark it as no longer having a hard register home. */
3658 reg_renumber[i] = -1;
3659 /* We will need to scan everything again. */
3660 something_changed = 1;
3663 /* Retry global register allocation if possible. */
3666 memset ((char *) pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3667 /* For every insn that needs reloads, set the registers used as spill
3668 regs in pseudo_forbidden_regs for every pseudo live across the
3670 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3672 EXECUTE_IF_SET_IN_REG_SET
3673 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3675 ior_hard_reg_set (pseudo_forbidden_regs + i,
3676 &chain->used_spill_regs);
3678 EXECUTE_IF_SET_IN_REG_SET
3679 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3681 ior_hard_reg_set (pseudo_forbidden_regs + i,
3682 &chain->used_spill_regs);
3686 /* Retry allocating the spilled pseudos. For each reg, merge the
3687 various reg sets that indicate which hard regs can't be used,
3688 and call retry_global_alloc.
3689 We change spill_pseudos here to only contain pseudos that did not
3690 get a new hard register. */
3691 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3692 if (reg_old_renumber[i] != reg_renumber[i])
3694 HARD_REG_SET forbidden;
3695 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3696 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3697 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3698 retry_global_alloc (i, forbidden);
3699 if (reg_renumber[i] >= 0)
3700 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3704 /* Fix up the register information in the insn chain.
3705 This involves deleting those of the spilled pseudos which did not get
3706 a new hard register home from the live_{before,after} sets. */
3707 for (chain = reload_insn_chain; chain; chain = chain->next)
3709 HARD_REG_SET used_by_pseudos;
3710 HARD_REG_SET used_by_pseudos2;
3712 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3713 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3715 /* Mark any unallocated hard regs as available for spills. That
3716 makes inheritance work somewhat better. */
3717 if (chain->need_reload)
3719 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3720 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3721 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3723 /* Save the old value for the sanity test below. */
3724 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3726 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3727 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3728 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3729 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3731 /* Make sure we only enlarge the set. */
3732 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3738 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3739 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3741 int regno = reg_renumber[i];
3742 if (reg_old_renumber[i] == regno)
3745 alter_reg (i, reg_old_renumber[i]);
3746 reg_old_renumber[i] = regno;
3750 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3752 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3753 i, reg_renumber[i]);
3757 return something_changed;
3760 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3761 Also mark any hard registers used to store user variables as
3762 forbidden from being used for spill registers. */
3765 scan_paradoxical_subregs (x)
3770 enum rtx_code code = GET_CODE (x);
3776 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3777 && REG_USERVAR_P (x))
3778 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3787 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3795 if (GET_CODE (SUBREG_REG (x)) == REG
3796 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3797 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3798 = GET_MODE_SIZE (GET_MODE (x));
3805 fmt = GET_RTX_FORMAT (code);
3806 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3809 scan_paradoxical_subregs (XEXP (x, i));
3810 else if (fmt[i] == 'E')
3813 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3814 scan_paradoxical_subregs (XVECEXP (x, i, j));
3819 /* Reload pseudo-registers into hard regs around each insn as needed.
3820 Additional register load insns are output before the insn that needs it
3821 and perhaps store insns after insns that modify the reloaded pseudo reg.
3823 reg_last_reload_reg and reg_reloaded_contents keep track of
3824 which registers are already available in reload registers.
3825 We update these for the reloads that we perform,
3826 as the insns are scanned. */
3829 reload_as_needed (live_known)
3832 struct insn_chain *chain;
3833 #if defined (AUTO_INC_DEC)
3838 memset ((char *) spill_reg_rtx, 0, sizeof spill_reg_rtx);
3839 memset ((char *) spill_reg_store, 0, sizeof spill_reg_store);
3840 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3841 reg_has_output_reload = (char *) xmalloc (max_regno);
3842 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3844 set_initial_elim_offsets ();
3846 for (chain = reload_insn_chain; chain; chain = chain->next)
3849 rtx insn = chain->insn;
3850 rtx old_next = NEXT_INSN (insn);
3852 /* If we pass a label, copy the offsets from the label information
3853 into the current offsets of each elimination. */
3854 if (GET_CODE (insn) == CODE_LABEL)
3855 set_offsets_for_label (insn);
3857 else if (INSN_P (insn))
3859 rtx oldpat = copy_rtx (PATTERN (insn));
3861 /* If this is a USE and CLOBBER of a MEM, ensure that any
3862 references to eliminable registers have been removed. */
3864 if ((GET_CODE (PATTERN (insn)) == USE
3865 || GET_CODE (PATTERN (insn)) == CLOBBER)
3866 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3867 XEXP (XEXP (PATTERN (insn), 0), 0)
3868 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3869 GET_MODE (XEXP (PATTERN (insn), 0)),
3872 /* If we need to do register elimination processing, do so.
3873 This might delete the insn, in which case we are done. */
3874 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3876 eliminate_regs_in_insn (insn, 1);
3877 if (GET_CODE (insn) == NOTE)
3879 update_eliminable_offsets ();
3884 /* If need_elim is nonzero but need_reload is zero, one might think
3885 that we could simply set n_reloads to 0. However, find_reloads
3886 could have done some manipulation of the insn (such as swapping
3887 commutative operands), and these manipulations are lost during
3888 the first pass for every insn that needs register elimination.
3889 So the actions of find_reloads must be redone here. */
3891 if (! chain->need_elim && ! chain->need_reload
3892 && ! chain->need_operand_change)
3894 /* First find the pseudo regs that must be reloaded for this insn.
3895 This info is returned in the tables reload_... (see reload.h).
3896 Also modify the body of INSN by substituting RELOAD
3897 rtx's for those pseudo regs. */
3900 memset (reg_has_output_reload, 0, max_regno);
3901 CLEAR_HARD_REG_SET (reg_is_output_reload);
3903 find_reloads (insn, 1, spill_indirect_levels, live_known,
3909 rtx next = NEXT_INSN (insn);
3912 prev = PREV_INSN (insn);
3914 /* Now compute which reload regs to reload them into. Perhaps
3915 reusing reload regs from previous insns, or else output
3916 load insns to reload them. Maybe output store insns too.
3917 Record the choices of reload reg in reload_reg_rtx. */
3918 choose_reload_regs (chain);
3920 /* Merge any reloads that we didn't combine for fear of
3921 increasing the number of spill registers needed but now
3922 discover can be safely merged. */
3923 if (SMALL_REGISTER_CLASSES)
3924 merge_assigned_reloads (insn);
3926 /* Generate the insns to reload operands into or out of
3927 their reload regs. */
3928 emit_reload_insns (chain);
3930 /* Substitute the chosen reload regs from reload_reg_rtx
3931 into the insn's body (or perhaps into the bodies of other
3932 load and store insn that we just made for reloading
3933 and that we moved the structure into). */
3934 subst_reloads (insn);
3936 /* If this was an ASM, make sure that all the reload insns
3937 we have generated are valid. If not, give an error
3940 if (asm_noperands (PATTERN (insn)) >= 0)
3941 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3942 if (p != insn && INSN_P (p)
3943 && GET_CODE (PATTERN (p)) != USE
3944 && (recog_memoized (p) < 0
3945 || (extract_insn (p), ! constrain_operands (1))))
3947 error_for_asm (insn,
3948 "`asm' operand requires impossible reload");
3953 if (num_eliminable && chain->need_elim)
3954 update_eliminable_offsets ();
3956 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3957 is no longer validly lying around to save a future reload.
3958 Note that this does not detect pseudos that were reloaded
3959 for this insn in order to be stored in
3960 (obeying register constraints). That is correct; such reload
3961 registers ARE still valid. */
3962 note_stores (oldpat, forget_old_reloads_1, NULL);
3964 /* There may have been CLOBBER insns placed after INSN. So scan
3965 between INSN and NEXT and use them to forget old reloads. */
3966 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3967 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3968 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3971 /* Likewise for regs altered by auto-increment in this insn.
3972 REG_INC notes have been changed by reloading:
3973 find_reloads_address_1 records substitutions for them,
3974 which have been performed by subst_reloads above. */
3975 for (i = n_reloads - 1; i >= 0; i--)
3977 rtx in_reg = rld[i].in_reg;
3980 enum rtx_code code = GET_CODE (in_reg);
3981 /* PRE_INC / PRE_DEC will have the reload register ending up
3982 with the same value as the stack slot, but that doesn't
3983 hold true for POST_INC / POST_DEC. Either we have to
3984 convert the memory access to a true POST_INC / POST_DEC,
3985 or we can't use the reload register for inheritance. */
3986 if ((code == POST_INC || code == POST_DEC)
3987 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3988 REGNO (rld[i].reg_rtx))
3989 /* Make sure it is the inc/dec pseudo, and not
3990 some other (e.g. output operand) pseudo. */
3991 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3992 == REGNO (XEXP (in_reg, 0))))
3995 rtx reload_reg = rld[i].reg_rtx;
3996 enum machine_mode mode = GET_MODE (reload_reg);
4000 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4002 /* We really want to ignore REG_INC notes here, so
4003 use PATTERN (p) as argument to reg_set_p . */
4004 if (reg_set_p (reload_reg, PATTERN (p)))
4006 n = count_occurrences (PATTERN (p), reload_reg, 0);
4011 n = validate_replace_rtx (reload_reg,
4012 gen_rtx (code, mode,
4016 /* We must also verify that the constraints
4017 are met after the replacement. */
4020 n = constrain_operands (1);
4024 /* If the constraints were not met, then
4025 undo the replacement. */
4028 validate_replace_rtx (gen_rtx (code, mode,
4040 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4042 /* Mark this as having an output reload so that the
4043 REG_INC processing code below won't invalidate
4044 the reload for inheritance. */
4045 SET_HARD_REG_BIT (reg_is_output_reload,
4046 REGNO (reload_reg));
4047 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4050 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4053 else if ((code == PRE_INC || code == PRE_DEC)
4054 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4055 REGNO (rld[i].reg_rtx))
4056 /* Make sure it is the inc/dec pseudo, and not
4057 some other (e.g. output operand) pseudo. */
4058 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4059 == REGNO (XEXP (in_reg, 0))))
4061 SET_HARD_REG_BIT (reg_is_output_reload,
4062 REGNO (rld[i].reg_rtx));
4063 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4067 /* If a pseudo that got a hard register is auto-incremented,
4068 we must purge records of copying it into pseudos without
4070 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4071 if (REG_NOTE_KIND (x) == REG_INC)
4073 /* See if this pseudo reg was reloaded in this insn.
4074 If so, its last-reload info is still valid
4075 because it is based on this insn's reload. */
4076 for (i = 0; i < n_reloads; i++)
4077 if (rld[i].out == XEXP (x, 0))
4081 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4085 /* A reload reg's contents are unknown after a label. */
4086 if (GET_CODE (insn) == CODE_LABEL)
4087 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4089 /* Don't assume a reload reg is still good after a call insn
4090 if it is a call-used reg. */
4091 else if (GET_CODE (insn) == CALL_INSN)
4092 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4096 free (reg_last_reload_reg);
4097 free (reg_has_output_reload);
4100 /* Discard all record of any value reloaded from X,
4101 or reloaded in X from someplace else;
4102 unless X is an output reload reg of the current insn.
4104 X may be a hard reg (the reload reg)
4105 or it may be a pseudo reg that was reloaded from. */
4108 forget_old_reloads_1 (x, ignored, data)
4110 rtx ignored ATTRIBUTE_UNUSED;
4111 void *data ATTRIBUTE_UNUSED;
4116 /* note_stores does give us subregs of hard regs,
4117 subreg_regno_offset will abort if it is not a hard reg. */
4118 while (GET_CODE (x) == SUBREG)
4120 /* We ignore the subreg offset when calculating the regno,
4121 because we are using the entire underlying hard register
4126 if (GET_CODE (x) != REG)
4131 if (regno >= FIRST_PSEUDO_REGISTER)
4137 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4138 /* Storing into a spilled-reg invalidates its contents.
4139 This can happen if a block-local pseudo is allocated to that reg
4140 and it wasn't spilled because this block's total need is 0.
4141 Then some insn might have an optional reload and use this reg. */
4142 for (i = 0; i < nr; i++)
4143 /* But don't do this if the reg actually serves as an output
4144 reload reg in the current instruction. */
4146 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4148 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4149 spill_reg_store[regno + i] = 0;
4153 /* Since value of X has changed,
4154 forget any value previously copied from it. */
4157 /* But don't forget a copy if this is the output reload
4158 that establishes the copy's validity. */
4159 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4160 reg_last_reload_reg[regno + nr] = 0;
4163 /* The following HARD_REG_SETs indicate when each hard register is
4164 used for a reload of various parts of the current insn. */
4166 /* If reg is unavailable for all reloads. */
4167 static HARD_REG_SET reload_reg_unavailable;
4168 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4169 static HARD_REG_SET reload_reg_used;
4170 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4171 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4172 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4173 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4174 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4175 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4176 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4177 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4178 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4179 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4180 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4181 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4182 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4183 static HARD_REG_SET reload_reg_used_in_op_addr;
4184 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4185 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4186 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4187 static HARD_REG_SET reload_reg_used_in_insn;
4188 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4189 static HARD_REG_SET reload_reg_used_in_other_addr;
4191 /* If reg is in use as a reload reg for any sort of reload. */
4192 static HARD_REG_SET reload_reg_used_at_all;
4194 /* If reg is use as an inherited reload. We just mark the first register
4196 static HARD_REG_SET reload_reg_used_for_inherit;
4198 /* Records which hard regs are used in any way, either as explicit use or
4199 by being allocated to a pseudo during any point of the current insn. */
4200 static HARD_REG_SET reg_used_in_insn;
4202 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4203 TYPE. MODE is used to indicate how many consecutive regs are
4207 mark_reload_reg_in_use (regno, opnum, type, mode)
4210 enum reload_type type;
4211 enum machine_mode mode;
4213 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4216 for (i = regno; i < nregs + regno; i++)
4221 SET_HARD_REG_BIT (reload_reg_used, i);
4224 case RELOAD_FOR_INPUT_ADDRESS:
4225 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4228 case RELOAD_FOR_INPADDR_ADDRESS:
4229 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4232 case RELOAD_FOR_OUTPUT_ADDRESS:
4233 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4236 case RELOAD_FOR_OUTADDR_ADDRESS:
4237 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4240 case RELOAD_FOR_OPERAND_ADDRESS:
4241 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4244 case RELOAD_FOR_OPADDR_ADDR:
4245 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4248 case RELOAD_FOR_OTHER_ADDRESS:
4249 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4252 case RELOAD_FOR_INPUT:
4253 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4256 case RELOAD_FOR_OUTPUT:
4257 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4260 case RELOAD_FOR_INSN:
4261 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4265 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4269 /* Similarly, but show REGNO is no longer in use for a reload. */
4272 clear_reload_reg_in_use (regno, opnum, type, mode)
4275 enum reload_type type;
4276 enum machine_mode mode;
4278 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4279 unsigned int start_regno, end_regno, r;
4281 /* A complication is that for some reload types, inheritance might
4282 allow multiple reloads of the same types to share a reload register.
4283 We set check_opnum if we have to check only reloads with the same
4284 operand number, and check_any if we have to check all reloads. */
4285 int check_opnum = 0;
4287 HARD_REG_SET *used_in_set;
4292 used_in_set = &reload_reg_used;
4295 case RELOAD_FOR_INPUT_ADDRESS:
4296 used_in_set = &reload_reg_used_in_input_addr[opnum];
4299 case RELOAD_FOR_INPADDR_ADDRESS:
4301 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4304 case RELOAD_FOR_OUTPUT_ADDRESS:
4305 used_in_set = &reload_reg_used_in_output_addr[opnum];
4308 case RELOAD_FOR_OUTADDR_ADDRESS:
4310 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4313 case RELOAD_FOR_OPERAND_ADDRESS:
4314 used_in_set = &reload_reg_used_in_op_addr;
4317 case RELOAD_FOR_OPADDR_ADDR:
4319 used_in_set = &reload_reg_used_in_op_addr_reload;
4322 case RELOAD_FOR_OTHER_ADDRESS:
4323 used_in_set = &reload_reg_used_in_other_addr;
4327 case RELOAD_FOR_INPUT:
4328 used_in_set = &reload_reg_used_in_input[opnum];
4331 case RELOAD_FOR_OUTPUT:
4332 used_in_set = &reload_reg_used_in_output[opnum];
4335 case RELOAD_FOR_INSN:
4336 used_in_set = &reload_reg_used_in_insn;
4341 /* We resolve conflicts with remaining reloads of the same type by
4342 excluding the intervals of reload registers by them from the
4343 interval of freed reload registers. Since we only keep track of
4344 one set of interval bounds, we might have to exclude somewhat
4345 more than what would be necessary if we used a HARD_REG_SET here.
4346 But this should only happen very infrequently, so there should
4347 be no reason to worry about it. */
4349 start_regno = regno;
4350 end_regno = regno + nregs;
4351 if (check_opnum || check_any)
4353 for (i = n_reloads - 1; i >= 0; i--)
4355 if (rld[i].when_needed == type
4356 && (check_any || rld[i].opnum == opnum)
4359 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4360 unsigned int conflict_end
4362 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4364 /* If there is an overlap with the first to-be-freed register,
4365 adjust the interval start. */
4366 if (conflict_start <= start_regno && conflict_end > start_regno)
4367 start_regno = conflict_end;
4368 /* Otherwise, if there is a conflict with one of the other
4369 to-be-freed registers, adjust the interval end. */
4370 if (conflict_start > start_regno && conflict_start < end_regno)
4371 end_regno = conflict_start;
4376 for (r = start_regno; r < end_regno; r++)
4377 CLEAR_HARD_REG_BIT (*used_in_set, r);
4380 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4381 specified by OPNUM and TYPE. */
4384 reload_reg_free_p (regno, opnum, type)
4387 enum reload_type type;
4391 /* In use for a RELOAD_OTHER means it's not available for anything. */
4392 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4393 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4399 /* In use for anything means we can't use it for RELOAD_OTHER. */
4400 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4401 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4402 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4405 for (i = 0; i < reload_n_operands; i++)
4406 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4407 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4408 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4409 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4410 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4411 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4416 case RELOAD_FOR_INPUT:
4417 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4418 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4421 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4424 /* If it is used for some other input, can't use it. */
4425 for (i = 0; i < reload_n_operands; i++)
4426 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4429 /* If it is used in a later operand's address, can't use it. */
4430 for (i = opnum + 1; i < reload_n_operands; i++)
4431 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4432 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4437 case RELOAD_FOR_INPUT_ADDRESS:
4438 /* Can't use a register if it is used for an input address for this
4439 operand or used as an input in an earlier one. */
4440 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4441 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4444 for (i = 0; i < opnum; i++)
4445 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4450 case RELOAD_FOR_INPADDR_ADDRESS:
4451 /* Can't use a register if it is used for an input address
4452 for this operand or used as an input in an earlier
4454 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4457 for (i = 0; i < opnum; i++)
4458 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4463 case RELOAD_FOR_OUTPUT_ADDRESS:
4464 /* Can't use a register if it is used for an output address for this
4465 operand or used as an output in this or a later operand. Note
4466 that multiple output operands are emitted in reverse order, so
4467 the conflicting ones are those with lower indices. */
4468 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4471 for (i = 0; i <= opnum; i++)
4472 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4477 case RELOAD_FOR_OUTADDR_ADDRESS:
4478 /* Can't use a register if it is used for an output address
4479 for this operand or used as an output in this or a
4480 later operand. Note that multiple output operands are
4481 emitted in reverse order, so the conflicting ones are
4482 those with lower indices. */
4483 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4486 for (i = 0; i <= opnum; i++)
4487 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4492 case RELOAD_FOR_OPERAND_ADDRESS:
4493 for (i = 0; i < reload_n_operands; i++)
4494 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4497 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4498 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4500 case RELOAD_FOR_OPADDR_ADDR:
4501 for (i = 0; i < reload_n_operands; i++)
4502 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4505 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4507 case RELOAD_FOR_OUTPUT:
4508 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4509 outputs, or an operand address for this or an earlier output.
4510 Note that multiple output operands are emitted in reverse order,
4511 so the conflicting ones are those with higher indices. */
4512 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4515 for (i = 0; i < reload_n_operands; i++)
4516 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4519 for (i = opnum; i < reload_n_operands; i++)
4520 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4521 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4526 case RELOAD_FOR_INSN:
4527 for (i = 0; i < reload_n_operands; i++)
4528 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4529 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4532 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4533 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4535 case RELOAD_FOR_OTHER_ADDRESS:
4536 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4541 /* Return 1 if the value in reload reg REGNO, as used by a reload
4542 needed for the part of the insn specified by OPNUM and TYPE,
4543 is still available in REGNO at the end of the insn.
4545 We can assume that the reload reg was already tested for availability
4546 at the time it is needed, and we should not check this again,
4547 in case the reg has already been marked in use. */
4550 reload_reg_reaches_end_p (regno, opnum, type)
4553 enum reload_type type;
4560 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4561 its value must reach the end. */
4564 /* If this use is for part of the insn,
4565 its value reaches if no subsequent part uses the same register.
4566 Just like the above function, don't try to do this with lots
4569 case RELOAD_FOR_OTHER_ADDRESS:
4570 /* Here we check for everything else, since these don't conflict
4571 with anything else and everything comes later. */
4573 for (i = 0; i < reload_n_operands; i++)
4574 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4575 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4576 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4577 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4578 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4579 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4582 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4583 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4584 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4586 case RELOAD_FOR_INPUT_ADDRESS:
4587 case RELOAD_FOR_INPADDR_ADDRESS:
4588 /* Similar, except that we check only for this and subsequent inputs
4589 and the address of only subsequent inputs and we do not need
4590 to check for RELOAD_OTHER objects since they are known not to
4593 for (i = opnum; i < reload_n_operands; i++)
4594 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4597 for (i = opnum + 1; i < reload_n_operands; i++)
4598 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4599 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4602 for (i = 0; i < reload_n_operands; i++)
4603 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4604 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4605 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4608 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4611 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4612 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4613 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4615 case RELOAD_FOR_INPUT:
4616 /* Similar to input address, except we start at the next operand for
4617 both input and input address and we do not check for
4618 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4621 for (i = opnum + 1; i < reload_n_operands; i++)
4622 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4623 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4624 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4627 /* ... fall through ... */
4629 case RELOAD_FOR_OPERAND_ADDRESS:
4630 /* Check outputs and their addresses. */
4632 for (i = 0; i < reload_n_operands; i++)
4633 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4634 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4635 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4638 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4640 case RELOAD_FOR_OPADDR_ADDR:
4641 for (i = 0; i < reload_n_operands; i++)
4642 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4643 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4644 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4647 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4648 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4649 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4651 case RELOAD_FOR_INSN:
4652 /* These conflict with other outputs with RELOAD_OTHER. So
4653 we need only check for output addresses. */
4655 opnum = reload_n_operands;
4657 /* ... fall through ... */
4659 case RELOAD_FOR_OUTPUT:
4660 case RELOAD_FOR_OUTPUT_ADDRESS:
4661 case RELOAD_FOR_OUTADDR_ADDRESS:
4662 /* We already know these can't conflict with a later output. So the
4663 only thing to check are later output addresses.
4664 Note that multiple output operands are emitted in reverse order,
4665 so the conflicting ones are those with lower indices. */
4666 for (i = 0; i < opnum; i++)
4667 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4668 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4677 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4680 This function uses the same algorithm as reload_reg_free_p above. */
4683 reloads_conflict (r1, r2)
4686 enum reload_type r1_type = rld[r1].when_needed;
4687 enum reload_type r2_type = rld[r2].when_needed;
4688 int r1_opnum = rld[r1].opnum;
4689 int r2_opnum = rld[r2].opnum;
4691 /* RELOAD_OTHER conflicts with everything. */
4692 if (r2_type == RELOAD_OTHER)
4695 /* Otherwise, check conflicts differently for each type. */
4699 case RELOAD_FOR_INPUT:
4700 return (r2_type == RELOAD_FOR_INSN
4701 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4702 || r2_type == RELOAD_FOR_OPADDR_ADDR
4703 || r2_type == RELOAD_FOR_INPUT
4704 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4705 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4706 && r2_opnum > r1_opnum));
4708 case RELOAD_FOR_INPUT_ADDRESS:
4709 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4710 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4712 case RELOAD_FOR_INPADDR_ADDRESS:
4713 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4714 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4716 case RELOAD_FOR_OUTPUT_ADDRESS:
4717 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4718 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4720 case RELOAD_FOR_OUTADDR_ADDRESS:
4721 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4722 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4724 case RELOAD_FOR_OPERAND_ADDRESS:
4725 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4726 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4728 case RELOAD_FOR_OPADDR_ADDR:
4729 return (r2_type == RELOAD_FOR_INPUT
4730 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4732 case RELOAD_FOR_OUTPUT:
4733 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4734 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4735 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4736 && r2_opnum >= r1_opnum));
4738 case RELOAD_FOR_INSN:
4739 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4740 || r2_type == RELOAD_FOR_INSN
4741 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4743 case RELOAD_FOR_OTHER_ADDRESS:
4744 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4754 /* Indexed by reload number, 1 if incoming value
4755 inherited from previous insns. */
4756 char reload_inherited[MAX_RELOADS];
4758 /* For an inherited reload, this is the insn the reload was inherited from,
4759 if we know it. Otherwise, this is 0. */
4760 rtx reload_inheritance_insn[MAX_RELOADS];
4762 /* If nonzero, this is a place to get the value of the reload,
4763 rather than using reload_in. */
4764 rtx reload_override_in[MAX_RELOADS];
4766 /* For each reload, the hard register number of the register used,
4767 or -1 if we did not need a register for this reload. */
4768 int reload_spill_index[MAX_RELOADS];
4770 /* Subroutine of free_for_value_p, used to check a single register.
4771 START_REGNO is the starting regno of the full reload register
4772 (possibly comprising multiple hard registers) that we are considering. */
4775 reload_reg_free_for_value_p (start_regno, regno, opnum, type, value, out,
4776 reloadnum, ignore_address_reloads)
4777 int start_regno, regno;
4779 enum reload_type type;
4782 int ignore_address_reloads;
4785 /* Set if we see an input reload that must not share its reload register
4786 with any new earlyclobber, but might otherwise share the reload
4787 register with an output or input-output reload. */
4788 int check_earlyclobber = 0;
4792 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4795 if (out == const0_rtx)
4801 /* We use some pseudo 'time' value to check if the lifetimes of the
4802 new register use would overlap with the one of a previous reload
4803 that is not read-only or uses a different value.
4804 The 'time' used doesn't have to be linear in any shape or form, just
4806 Some reload types use different 'buckets' for each operand.
4807 So there are MAX_RECOG_OPERANDS different time values for each
4809 We compute TIME1 as the time when the register for the prospective
4810 new reload ceases to be live, and TIME2 for each existing
4811 reload as the time when that the reload register of that reload
4813 Where there is little to be gained by exact lifetime calculations,
4814 we just make conservative assumptions, i.e. a longer lifetime;
4815 this is done in the 'default:' cases. */
4818 case RELOAD_FOR_OTHER_ADDRESS:
4819 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4820 time1 = copy ? 0 : 1;
4823 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4825 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4826 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4827 respectively, to the time values for these, we get distinct time
4828 values. To get distinct time values for each operand, we have to
4829 multiply opnum by at least three. We round that up to four because
4830 multiply by four is often cheaper. */
4831 case RELOAD_FOR_INPADDR_ADDRESS:
4832 time1 = opnum * 4 + 2;
4834 case RELOAD_FOR_INPUT_ADDRESS:
4835 time1 = opnum * 4 + 3;
4837 case RELOAD_FOR_INPUT:
4838 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4839 executes (inclusive). */
4840 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4842 case RELOAD_FOR_OPADDR_ADDR:
4844 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4845 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4847 case RELOAD_FOR_OPERAND_ADDRESS:
4848 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4850 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4852 case RELOAD_FOR_OUTADDR_ADDRESS:
4853 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4855 case RELOAD_FOR_OUTPUT_ADDRESS:
4856 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4859 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4862 for (i = 0; i < n_reloads; i++)
4864 rtx reg = rld[i].reg_rtx;
4865 if (reg && GET_CODE (reg) == REG
4866 && ((unsigned) regno - true_regnum (reg)
4867 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned) 1)
4870 rtx other_input = rld[i].in;
4872 /* If the other reload loads the same input value, that
4873 will not cause a conflict only if it's loading it into
4874 the same register. */
4875 if (true_regnum (reg) != start_regno)
4876 other_input = NULL_RTX;
4877 if (! other_input || ! rtx_equal_p (other_input, value)
4878 || rld[i].out || out)
4881 switch (rld[i].when_needed)
4883 case RELOAD_FOR_OTHER_ADDRESS:
4886 case RELOAD_FOR_INPADDR_ADDRESS:
4887 /* find_reloads makes sure that a
4888 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4889 by at most one - the first -
4890 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4891 address reload is inherited, the address address reload
4892 goes away, so we can ignore this conflict. */
4893 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4894 && ignore_address_reloads
4895 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4896 Then the address address is still needed to store
4897 back the new address. */
4898 && ! rld[reloadnum].out)
4900 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4901 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4903 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4904 && ignore_address_reloads
4905 /* Unless we are reloading an auto_inc expression. */
4906 && ! rld[reloadnum].out)
4908 time2 = rld[i].opnum * 4 + 2;
4910 case RELOAD_FOR_INPUT_ADDRESS:
4911 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4912 && ignore_address_reloads
4913 && ! rld[reloadnum].out)
4915 time2 = rld[i].opnum * 4 + 3;
4917 case RELOAD_FOR_INPUT:
4918 time2 = rld[i].opnum * 4 + 4;
4919 check_earlyclobber = 1;
4921 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4922 == MAX_RECOG_OPERAND * 4 */
4923 case RELOAD_FOR_OPADDR_ADDR:
4924 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4925 && ignore_address_reloads
4926 && ! rld[reloadnum].out)
4928 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4930 case RELOAD_FOR_OPERAND_ADDRESS:
4931 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4932 check_earlyclobber = 1;
4934 case RELOAD_FOR_INSN:
4935 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4937 case RELOAD_FOR_OUTPUT:
4938 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4939 instruction is executed. */
4940 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4942 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4943 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4945 case RELOAD_FOR_OUTADDR_ADDRESS:
4946 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4947 && ignore_address_reloads
4948 && ! rld[reloadnum].out)
4950 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4952 case RELOAD_FOR_OUTPUT_ADDRESS:
4953 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4956 /* If there is no conflict in the input part, handle this
4957 like an output reload. */
4958 if (! rld[i].in || rtx_equal_p (other_input, value))
4960 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4961 /* Earlyclobbered outputs must conflict with inputs. */
4962 if (earlyclobber_operand_p (rld[i].out))
4963 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4968 /* RELOAD_OTHER might be live beyond instruction execution,
4969 but this is not obvious when we set time2 = 1. So check
4970 here if there might be a problem with the new reload
4971 clobbering the register used by the RELOAD_OTHER. */
4979 && (! rld[i].in || rld[i].out
4980 || ! rtx_equal_p (other_input, value)))
4981 || (out && rld[reloadnum].out_reg
4982 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4988 /* Earlyclobbered outputs must conflict with inputs. */
4989 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4995 /* Return 1 if the value in reload reg REGNO, as used by a reload
4996 needed for the part of the insn specified by OPNUM and TYPE,
4997 may be used to load VALUE into it.
4999 MODE is the mode in which the register is used, this is needed to
5000 determine how many hard regs to test.
5002 Other read-only reloads with the same value do not conflict
5003 unless OUT is nonzero and these other reloads have to live while
5004 output reloads live.
5005 If OUT is CONST0_RTX, this is a special case: it means that the
5006 test should not be for using register REGNO as reload register, but
5007 for copying from register REGNO into the reload register.
5009 RELOADNUM is the number of the reload we want to load this value for;
5010 a reload does not conflict with itself.
5012 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5013 reloads that load an address for the very reload we are considering.
5015 The caller has to make sure that there is no conflict with the return
5019 free_for_value_p (regno, mode, opnum, type, value, out, reloadnum,
5020 ignore_address_reloads)
5022 enum machine_mode mode;
5024 enum reload_type type;
5027 int ignore_address_reloads;
5029 int nregs = HARD_REGNO_NREGS (regno, mode);
5031 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5032 value, out, reloadnum,
5033 ignore_address_reloads))
5038 /* Determine whether the reload reg X overlaps any rtx'es used for
5039 overriding inheritance. Return nonzero if so. */
5042 conflicts_with_override (x)
5046 for (i = 0; i < n_reloads; i++)
5047 if (reload_override_in[i]
5048 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5053 /* Give an error message saying we failed to find a reload for INSN,
5054 and clear out reload R. */
5056 failed_reload (insn, r)
5060 if (asm_noperands (PATTERN (insn)) < 0)
5061 /* It's the compiler's fault. */
5062 fatal_insn ("could not find a spill register", insn);
5064 /* It's the user's fault; the operand's mode and constraint
5065 don't match. Disable this reload so we don't crash in final. */
5066 error_for_asm (insn,
5067 "`asm' operand constraint incompatible with operand size");
5071 rld[r].optional = 1;
5072 rld[r].secondary_p = 1;
5075 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5076 for reload R. If it's valid, get an rtx for it. Return nonzero if
5079 set_reload_reg (i, r)
5083 rtx reg = spill_reg_rtx[i];
5085 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5086 spill_reg_rtx[i] = reg
5087 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5089 regno = true_regnum (reg);
5091 /* Detect when the reload reg can't hold the reload mode.
5092 This used to be one `if', but Sequent compiler can't handle that. */
5093 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5095 enum machine_mode test_mode = VOIDmode;
5097 test_mode = GET_MODE (rld[r].in);
5098 /* If rld[r].in has VOIDmode, it means we will load it
5099 in whatever mode the reload reg has: to wit, rld[r].mode.
5100 We have already tested that for validity. */
5101 /* Aside from that, we need to test that the expressions
5102 to reload from or into have modes which are valid for this
5103 reload register. Otherwise the reload insns would be invalid. */
5104 if (! (rld[r].in != 0 && test_mode != VOIDmode
5105 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5106 if (! (rld[r].out != 0
5107 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5109 /* The reg is OK. */
5112 /* Mark as in use for this insn the reload regs we use
5114 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5115 rld[r].when_needed, rld[r].mode);
5117 rld[r].reg_rtx = reg;
5118 reload_spill_index[r] = spill_regs[i];
5125 /* Find a spill register to use as a reload register for reload R.
5126 LAST_RELOAD is nonzero if this is the last reload for the insn being
5129 Set rld[R].reg_rtx to the register allocated.
5131 We return 1 if successful, or 0 if we couldn't find a spill reg and
5132 we didn't change anything. */
5135 allocate_reload_reg (chain, r, last_reload)
5136 struct insn_chain *chain ATTRIBUTE_UNUSED;
5142 /* If we put this reload ahead, thinking it is a group,
5143 then insist on finding a group. Otherwise we can grab a
5144 reg that some other reload needs.
5145 (That can happen when we have a 68000 DATA_OR_FP_REG
5146 which is a group of data regs or one fp reg.)
5147 We need not be so restrictive if there are no more reloads
5150 ??? Really it would be nicer to have smarter handling
5151 for that kind of reg class, where a problem like this is normal.
5152 Perhaps those classes should be avoided for reloading
5153 by use of more alternatives. */
5155 int force_group = rld[r].nregs > 1 && ! last_reload;
5157 /* If we want a single register and haven't yet found one,
5158 take any reg in the right class and not in use.
5159 If we want a consecutive group, here is where we look for it.
5161 We use two passes so we can first look for reload regs to
5162 reuse, which are already in use for other reloads in this insn,
5163 and only then use additional registers.
5164 I think that maximizing reuse is needed to make sure we don't
5165 run out of reload regs. Suppose we have three reloads, and
5166 reloads A and B can share regs. These need two regs.
5167 Suppose A and B are given different regs.
5168 That leaves none for C. */
5169 for (pass = 0; pass < 2; pass++)
5171 /* I is the index in spill_regs.
5172 We advance it round-robin between insns to use all spill regs
5173 equally, so that inherited reloads have a chance
5174 of leapfrogging each other. */
5178 for (count = 0; count < n_spills; count++)
5180 int class = (int) rld[r].class;
5186 regnum = spill_regs[i];
5188 if ((reload_reg_free_p (regnum, rld[r].opnum,
5191 /* We check reload_reg_used to make sure we
5192 don't clobber the return register. */
5193 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5194 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5195 rld[r].when_needed, rld[r].in,
5197 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5198 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5199 /* Look first for regs to share, then for unshared. But
5200 don't share regs used for inherited reloads; they are
5201 the ones we want to preserve. */
5203 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5205 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5208 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5209 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5210 (on 68000) got us two FP regs. If NR is 1,
5211 we would reject both of them. */
5214 /* If we need only one reg, we have already won. */
5217 /* But reject a single reg if we demand a group. */
5222 /* Otherwise check that as many consecutive regs as we need
5223 are available here. */
5226 int regno = regnum + nr - 1;
5227 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5228 && spill_reg_order[regno] >= 0
5229 && reload_reg_free_p (regno, rld[r].opnum,
5230 rld[r].when_needed)))
5239 /* If we found something on pass 1, omit pass 2. */
5240 if (count < n_spills)
5244 /* We should have found a spill register by now. */
5245 if (count >= n_spills)
5248 /* I is the index in SPILL_REG_RTX of the reload register we are to
5249 allocate. Get an rtx for it and find its register number. */
5251 return set_reload_reg (i, r);
5254 /* Initialize all the tables needed to allocate reload registers.
5255 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5256 is the array we use to restore the reg_rtx field for every reload. */
5259 choose_reload_regs_init (chain, save_reload_reg_rtx)
5260 struct insn_chain *chain;
5261 rtx *save_reload_reg_rtx;
5265 for (i = 0; i < n_reloads; i++)
5266 rld[i].reg_rtx = save_reload_reg_rtx[i];
5268 memset (reload_inherited, 0, MAX_RELOADS);
5269 memset ((char *) reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5270 memset ((char *) reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5272 CLEAR_HARD_REG_SET (reload_reg_used);
5273 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5274 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5275 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5276 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5277 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5279 CLEAR_HARD_REG_SET (reg_used_in_insn);
5282 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5283 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5284 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5285 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5286 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5287 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5290 for (i = 0; i < reload_n_operands; i++)
5292 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5293 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5294 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5295 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5296 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5297 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5300 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5302 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5304 for (i = 0; i < n_reloads; i++)
5305 /* If we have already decided to use a certain register,
5306 don't use it in another way. */
5308 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5309 rld[i].when_needed, rld[i].mode);
5312 /* Assign hard reg targets for the pseudo-registers we must reload
5313 into hard regs for this insn.
5314 Also output the instructions to copy them in and out of the hard regs.
5316 For machines with register classes, we are responsible for
5317 finding a reload reg in the proper class. */
5320 choose_reload_regs (chain)
5321 struct insn_chain *chain;
5323 rtx insn = chain->insn;
5325 unsigned int max_group_size = 1;
5326 enum reg_class group_class = NO_REGS;
5327 int pass, win, inheritance;
5329 rtx save_reload_reg_rtx[MAX_RELOADS];
5331 /* In order to be certain of getting the registers we need,
5332 we must sort the reloads into order of increasing register class.
5333 Then our grabbing of reload registers will parallel the process
5334 that provided the reload registers.
5336 Also note whether any of the reloads wants a consecutive group of regs.
5337 If so, record the maximum size of the group desired and what
5338 register class contains all the groups needed by this insn. */
5340 for (j = 0; j < n_reloads; j++)
5342 reload_order[j] = j;
5343 reload_spill_index[j] = -1;
5345 if (rld[j].nregs > 1)
5347 max_group_size = MAX (rld[j].nregs, max_group_size);
5349 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5352 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5356 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5358 /* If -O, try first with inheritance, then turning it off.
5359 If not -O, don't do inheritance.
5360 Using inheritance when not optimizing leads to paradoxes
5361 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5362 because one side of the comparison might be inherited. */
5364 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5366 choose_reload_regs_init (chain, save_reload_reg_rtx);
5368 /* Process the reloads in order of preference just found.
5369 Beyond this point, subregs can be found in reload_reg_rtx.
5371 This used to look for an existing reloaded home for all of the
5372 reloads, and only then perform any new reloads. But that could lose
5373 if the reloads were done out of reg-class order because a later
5374 reload with a looser constraint might have an old home in a register
5375 needed by an earlier reload with a tighter constraint.
5377 To solve this, we make two passes over the reloads, in the order
5378 described above. In the first pass we try to inherit a reload
5379 from a previous insn. If there is a later reload that needs a
5380 class that is a proper subset of the class being processed, we must
5381 also allocate a spill register during the first pass.
5383 Then make a second pass over the reloads to allocate any reloads
5384 that haven't been given registers yet. */
5386 for (j = 0; j < n_reloads; j++)
5388 int r = reload_order[j];
5389 rtx search_equiv = NULL_RTX;
5391 /* Ignore reloads that got marked inoperative. */
5392 if (rld[r].out == 0 && rld[r].in == 0
5393 && ! rld[r].secondary_p)
5396 /* If find_reloads chose to use reload_in or reload_out as a reload
5397 register, we don't need to chose one. Otherwise, try even if it
5398 found one since we might save an insn if we find the value lying
5400 Try also when reload_in is a pseudo without a hard reg. */
5401 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5402 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5403 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5404 && GET_CODE (rld[r].in) != MEM
5405 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5408 #if 0 /* No longer needed for correct operation.
5409 It might give better code, or might not; worth an experiment? */
5410 /* If this is an optional reload, we can't inherit from earlier insns
5411 until we are sure that any non-optional reloads have been allocated.
5412 The following code takes advantage of the fact that optional reloads
5413 are at the end of reload_order. */
5414 if (rld[r].optional != 0)
5415 for (i = 0; i < j; i++)
5416 if ((rld[reload_order[i]].out != 0
5417 || rld[reload_order[i]].in != 0
5418 || rld[reload_order[i]].secondary_p)
5419 && ! rld[reload_order[i]].optional
5420 && rld[reload_order[i]].reg_rtx == 0)
5421 allocate_reload_reg (chain, reload_order[i], 0);
5424 /* First see if this pseudo is already available as reloaded
5425 for a previous insn. We cannot try to inherit for reloads
5426 that are smaller than the maximum number of registers needed
5427 for groups unless the register we would allocate cannot be used
5430 We could check here to see if this is a secondary reload for
5431 an object that is already in a register of the desired class.
5432 This would avoid the need for the secondary reload register.
5433 But this is complex because we can't easily determine what
5434 objects might want to be loaded via this reload. So let a
5435 register be allocated here. In `emit_reload_insns' we suppress
5436 one of the loads in the case described above. */
5442 enum machine_mode mode = VOIDmode;
5446 else if (GET_CODE (rld[r].in) == REG)
5448 regno = REGNO (rld[r].in);
5449 mode = GET_MODE (rld[r].in);
5451 else if (GET_CODE (rld[r].in_reg) == REG)
5453 regno = REGNO (rld[r].in_reg);
5454 mode = GET_MODE (rld[r].in_reg);
5456 else if (GET_CODE (rld[r].in_reg) == SUBREG
5457 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5459 byte = SUBREG_BYTE (rld[r].in_reg);
5460 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5461 if (regno < FIRST_PSEUDO_REGISTER)
5462 regno = subreg_regno (rld[r].in_reg);
5463 mode = GET_MODE (rld[r].in_reg);
5466 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5467 || GET_CODE (rld[r].in_reg) == PRE_DEC
5468 || GET_CODE (rld[r].in_reg) == POST_INC
5469 || GET_CODE (rld[r].in_reg) == POST_DEC)
5470 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5472 regno = REGNO (XEXP (rld[r].in_reg, 0));
5473 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5474 rld[r].out = rld[r].in;
5478 /* This won't work, since REGNO can be a pseudo reg number.
5479 Also, it takes much more hair to keep track of all the things
5480 that can invalidate an inherited reload of part of a pseudoreg. */
5481 else if (GET_CODE (rld[r].in) == SUBREG
5482 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5483 regno = subreg_regno (rld[r].in);
5486 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5488 enum reg_class class = rld[r].class, last_class;
5489 rtx last_reg = reg_last_reload_reg[regno];
5490 enum machine_mode need_mode;
5492 i = REGNO (last_reg);
5493 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5494 last_class = REGNO_REG_CLASS (i);
5500 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5501 GET_MODE_CLASS (mode));
5504 #ifdef CANNOT_CHANGE_MODE_CLASS
5505 (!REG_CANNOT_CHANGE_MODE_P (i, GET_MODE (last_reg),
5509 (GET_MODE_SIZE (GET_MODE (last_reg))
5510 >= GET_MODE_SIZE (need_mode))
5511 #ifdef CANNOT_CHANGE_MODE_CLASS
5514 && reg_reloaded_contents[i] == regno
5515 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5516 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5517 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5518 /* Even if we can't use this register as a reload
5519 register, we might use it for reload_override_in,
5520 if copying it to the desired class is cheap
5522 || ((REGISTER_MOVE_COST (mode, last_class, class)
5523 < MEMORY_MOVE_COST (mode, class, 1))
5524 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5525 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5529 #ifdef SECONDARY_MEMORY_NEEDED
5530 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5535 && (rld[r].nregs == max_group_size
5536 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5538 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5539 rld[r].when_needed, rld[r].in,
5542 /* If a group is needed, verify that all the subsequent
5543 registers still have their values intact. */
5544 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5547 for (k = 1; k < nr; k++)
5548 if (reg_reloaded_contents[i + k] != regno
5549 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5557 last_reg = (GET_MODE (last_reg) == mode
5558 ? last_reg : gen_rtx_REG (mode, i));
5561 for (k = 0; k < nr; k++)
5562 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5565 /* We found a register that contains the
5566 value we need. If this register is the
5567 same as an `earlyclobber' operand of the
5568 current insn, just mark it as a place to
5569 reload from since we can't use it as the
5570 reload register itself. */
5572 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5573 if (reg_overlap_mentioned_for_reload_p
5574 (reg_last_reload_reg[regno],
5575 reload_earlyclobbers[i1]))
5578 if (i1 != n_earlyclobbers
5579 || ! (free_for_value_p (i, rld[r].mode,
5581 rld[r].when_needed, rld[r].in,
5583 /* Don't use it if we'd clobber a pseudo reg. */
5584 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5586 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5587 /* Don't clobber the frame pointer. */
5588 || (i == HARD_FRAME_POINTER_REGNUM
5589 && frame_pointer_needed
5591 /* Don't really use the inherited spill reg
5592 if we need it wider than we've got it. */
5593 || (GET_MODE_SIZE (rld[r].mode)
5594 > GET_MODE_SIZE (mode))
5597 /* If find_reloads chose reload_out as reload
5598 register, stay with it - that leaves the
5599 inherited register for subsequent reloads. */
5600 || (rld[r].out && rld[r].reg_rtx
5601 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5603 if (! rld[r].optional)
5605 reload_override_in[r] = last_reg;
5606 reload_inheritance_insn[r]
5607 = reg_reloaded_insn[i];
5613 /* We can use this as a reload reg. */
5614 /* Mark the register as in use for this part of
5616 mark_reload_reg_in_use (i,
5620 rld[r].reg_rtx = last_reg;
5621 reload_inherited[r] = 1;
5622 reload_inheritance_insn[r]
5623 = reg_reloaded_insn[i];
5624 reload_spill_index[r] = i;
5625 for (k = 0; k < nr; k++)
5626 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5634 /* Here's another way to see if the value is already lying around. */
5637 && ! reload_inherited[r]
5639 && (CONSTANT_P (rld[r].in)
5640 || GET_CODE (rld[r].in) == PLUS
5641 || GET_CODE (rld[r].in) == REG
5642 || GET_CODE (rld[r].in) == MEM)
5643 && (rld[r].nregs == max_group_size
5644 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5645 search_equiv = rld[r].in;
5646 /* If this is an output reload from a simple move insn, look
5647 if an equivalence for the input is available. */
5648 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5650 rtx set = single_set (insn);
5653 && rtx_equal_p (rld[r].out, SET_DEST (set))
5654 && CONSTANT_P (SET_SRC (set)))
5655 search_equiv = SET_SRC (set);
5661 = find_equiv_reg (search_equiv, insn, rld[r].class,
5662 -1, NULL, 0, rld[r].mode);
5667 if (GET_CODE (equiv) == REG)
5668 regno = REGNO (equiv);
5669 else if (GET_CODE (equiv) == SUBREG)
5671 /* This must be a SUBREG of a hard register.
5672 Make a new REG since this might be used in an
5673 address and not all machines support SUBREGs
5675 regno = subreg_regno (equiv);
5676 equiv = gen_rtx_REG (rld[r].mode, regno);
5682 /* If we found a spill reg, reject it unless it is free
5683 and of the desired class. */
5685 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5686 && ! free_for_value_p (regno, rld[r].mode,
5687 rld[r].opnum, rld[r].when_needed,
5688 rld[r].in, rld[r].out, r, 1))
5689 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5693 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5696 /* We found a register that contains the value we need.
5697 If this register is the same as an `earlyclobber' operand
5698 of the current insn, just mark it as a place to reload from
5699 since we can't use it as the reload register itself. */
5702 for (i = 0; i < n_earlyclobbers; i++)
5703 if (reg_overlap_mentioned_for_reload_p (equiv,
5704 reload_earlyclobbers[i]))
5706 if (! rld[r].optional)
5707 reload_override_in[r] = equiv;
5712 /* If the equiv register we have found is explicitly clobbered
5713 in the current insn, it depends on the reload type if we
5714 can use it, use it for reload_override_in, or not at all.
5715 In particular, we then can't use EQUIV for a
5716 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5720 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5721 switch (rld[r].when_needed)
5723 case RELOAD_FOR_OTHER_ADDRESS:
5724 case RELOAD_FOR_INPADDR_ADDRESS:
5725 case RELOAD_FOR_INPUT_ADDRESS:
5726 case RELOAD_FOR_OPADDR_ADDR:
5729 case RELOAD_FOR_INPUT:
5730 case RELOAD_FOR_OPERAND_ADDRESS:
5731 if (! rld[r].optional)
5732 reload_override_in[r] = equiv;
5738 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5739 switch (rld[r].when_needed)
5741 case RELOAD_FOR_OTHER_ADDRESS:
5742 case RELOAD_FOR_INPADDR_ADDRESS:
5743 case RELOAD_FOR_INPUT_ADDRESS:
5744 case RELOAD_FOR_OPADDR_ADDR:
5745 case RELOAD_FOR_OPERAND_ADDRESS:
5746 case RELOAD_FOR_INPUT:
5749 if (! rld[r].optional)
5750 reload_override_in[r] = equiv;
5758 /* If we found an equivalent reg, say no code need be generated
5759 to load it, and use it as our reload reg. */
5761 && (regno != HARD_FRAME_POINTER_REGNUM
5762 || !frame_pointer_needed))
5764 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5766 rld[r].reg_rtx = equiv;
5767 reload_inherited[r] = 1;
5769 /* If reg_reloaded_valid is not set for this register,
5770 there might be a stale spill_reg_store lying around.
5771 We must clear it, since otherwise emit_reload_insns
5772 might delete the store. */
5773 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5774 spill_reg_store[regno] = NULL_RTX;
5775 /* If any of the hard registers in EQUIV are spill
5776 registers, mark them as in use for this insn. */
5777 for (k = 0; k < nr; k++)
5779 i = spill_reg_order[regno + k];
5782 mark_reload_reg_in_use (regno, rld[r].opnum,
5785 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5792 /* If we found a register to use already, or if this is an optional
5793 reload, we are done. */
5794 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5798 /* No longer needed for correct operation. Might or might
5799 not give better code on the average. Want to experiment? */
5801 /* See if there is a later reload that has a class different from our
5802 class that intersects our class or that requires less register
5803 than our reload. If so, we must allocate a register to this
5804 reload now, since that reload might inherit a previous reload
5805 and take the only available register in our class. Don't do this
5806 for optional reloads since they will force all previous reloads
5807 to be allocated. Also don't do this for reloads that have been
5810 for (i = j + 1; i < n_reloads; i++)
5812 int s = reload_order[i];
5814 if ((rld[s].in == 0 && rld[s].out == 0
5815 && ! rld[s].secondary_p)
5819 if ((rld[s].class != rld[r].class
5820 && reg_classes_intersect_p (rld[r].class,
5822 || rld[s].nregs < rld[r].nregs)
5829 allocate_reload_reg (chain, r, j == n_reloads - 1);
5833 /* Now allocate reload registers for anything non-optional that
5834 didn't get one yet. */
5835 for (j = 0; j < n_reloads; j++)
5837 int r = reload_order[j];
5839 /* Ignore reloads that got marked inoperative. */
5840 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5843 /* Skip reloads that already have a register allocated or are
5845 if (rld[r].reg_rtx != 0 || rld[r].optional)
5848 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5852 /* If that loop got all the way, we have won. */
5859 /* Loop around and try without any inheritance. */
5864 /* First undo everything done by the failed attempt
5865 to allocate with inheritance. */
5866 choose_reload_regs_init (chain, save_reload_reg_rtx);
5868 /* Some sanity tests to verify that the reloads found in the first
5869 pass are identical to the ones we have now. */
5870 if (chain->n_reloads != n_reloads)
5873 for (i = 0; i < n_reloads; i++)
5875 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5877 if (chain->rld[i].when_needed != rld[i].when_needed)
5879 for (j = 0; j < n_spills; j++)
5880 if (spill_regs[j] == chain->rld[i].regno)
5881 if (! set_reload_reg (j, i))
5882 failed_reload (chain->insn, i);
5886 /* If we thought we could inherit a reload, because it seemed that
5887 nothing else wanted the same reload register earlier in the insn,
5888 verify that assumption, now that all reloads have been assigned.
5889 Likewise for reloads where reload_override_in has been set. */
5891 /* If doing expensive optimizations, do one preliminary pass that doesn't
5892 cancel any inheritance, but removes reloads that have been needed only
5893 for reloads that we know can be inherited. */
5894 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5896 for (j = 0; j < n_reloads; j++)
5898 int r = reload_order[j];
5900 if (reload_inherited[r] && rld[r].reg_rtx)
5901 check_reg = rld[r].reg_rtx;
5902 else if (reload_override_in[r]
5903 && (GET_CODE (reload_override_in[r]) == REG
5904 || GET_CODE (reload_override_in[r]) == SUBREG))
5905 check_reg = reload_override_in[r];
5908 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5909 rld[r].opnum, rld[r].when_needed, rld[r].in,
5910 (reload_inherited[r]
5911 ? rld[r].out : const0_rtx),
5916 reload_inherited[r] = 0;
5917 reload_override_in[r] = 0;
5919 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5920 reload_override_in, then we do not need its related
5921 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5922 likewise for other reload types.
5923 We handle this by removing a reload when its only replacement
5924 is mentioned in reload_in of the reload we are going to inherit.
5925 A special case are auto_inc expressions; even if the input is
5926 inherited, we still need the address for the output. We can
5927 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5928 If we succeeded removing some reload and we are doing a preliminary
5929 pass just to remove such reloads, make another pass, since the
5930 removal of one reload might allow us to inherit another one. */
5932 && rld[r].out != rld[r].in
5933 && remove_address_replacements (rld[r].in) && pass)
5938 /* Now that reload_override_in is known valid,
5939 actually override reload_in. */
5940 for (j = 0; j < n_reloads; j++)
5941 if (reload_override_in[j])
5942 rld[j].in = reload_override_in[j];
5944 /* If this reload won't be done because it has been canceled or is
5945 optional and not inherited, clear reload_reg_rtx so other
5946 routines (such as subst_reloads) don't get confused. */
5947 for (j = 0; j < n_reloads; j++)
5948 if (rld[j].reg_rtx != 0
5949 && ((rld[j].optional && ! reload_inherited[j])
5950 || (rld[j].in == 0 && rld[j].out == 0
5951 && ! rld[j].secondary_p)))
5953 int regno = true_regnum (rld[j].reg_rtx);
5955 if (spill_reg_order[regno] >= 0)
5956 clear_reload_reg_in_use (regno, rld[j].opnum,
5957 rld[j].when_needed, rld[j].mode);
5959 reload_spill_index[j] = -1;
5962 /* Record which pseudos and which spill regs have output reloads. */
5963 for (j = 0; j < n_reloads; j++)
5965 int r = reload_order[j];
5967 i = reload_spill_index[r];
5969 /* I is nonneg if this reload uses a register.
5970 If rld[r].reg_rtx is 0, this is an optional reload
5971 that we opted to ignore. */
5972 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5973 && rld[r].reg_rtx != 0)
5975 int nregno = REGNO (rld[r].out_reg);
5978 if (nregno < FIRST_PSEUDO_REGISTER)
5979 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5982 reg_has_output_reload[nregno + nr] = 1;
5986 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5988 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5991 if (rld[r].when_needed != RELOAD_OTHER
5992 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5993 && rld[r].when_needed != RELOAD_FOR_INSN)
5999 /* Deallocate the reload register for reload R. This is called from
6000 remove_address_replacements. */
6003 deallocate_reload_reg (r)
6008 if (! rld[r].reg_rtx)
6010 regno = true_regnum (rld[r].reg_rtx);
6012 if (spill_reg_order[regno] >= 0)
6013 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6015 reload_spill_index[r] = -1;
6018 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6019 reloads of the same item for fear that we might not have enough reload
6020 registers. However, normally they will get the same reload register
6021 and hence actually need not be loaded twice.
6023 Here we check for the most common case of this phenomenon: when we have
6024 a number of reloads for the same object, each of which were allocated
6025 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6026 reload, and is not modified in the insn itself. If we find such,
6027 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6028 This will not increase the number of spill registers needed and will
6029 prevent redundant code. */
6032 merge_assigned_reloads (insn)
6037 /* Scan all the reloads looking for ones that only load values and
6038 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6039 assigned and not modified by INSN. */
6041 for (i = 0; i < n_reloads; i++)
6043 int conflicting_input = 0;
6044 int max_input_address_opnum = -1;
6045 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6047 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6048 || rld[i].out != 0 || rld[i].reg_rtx == 0
6049 || reg_set_p (rld[i].reg_rtx, insn))
6052 /* Look at all other reloads. Ensure that the only use of this
6053 reload_reg_rtx is in a reload that just loads the same value
6054 as we do. Note that any secondary reloads must be of the identical
6055 class since the values, modes, and result registers are the
6056 same, so we need not do anything with any secondary reloads. */
6058 for (j = 0; j < n_reloads; j++)
6060 if (i == j || rld[j].reg_rtx == 0
6061 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6065 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6066 && rld[j].opnum > max_input_address_opnum)
6067 max_input_address_opnum = rld[j].opnum;
6069 /* If the reload regs aren't exactly the same (e.g, different modes)
6070 or if the values are different, we can't merge this reload.
6071 But if it is an input reload, we might still merge
6072 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6074 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6075 || rld[j].out != 0 || rld[j].in == 0
6076 || ! rtx_equal_p (rld[i].in, rld[j].in))
6078 if (rld[j].when_needed != RELOAD_FOR_INPUT
6079 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6080 || rld[i].opnum > rld[j].opnum)
6081 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6083 conflicting_input = 1;
6084 if (min_conflicting_input_opnum > rld[j].opnum)
6085 min_conflicting_input_opnum = rld[j].opnum;
6089 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6090 we, in fact, found any matching reloads. */
6093 && max_input_address_opnum <= min_conflicting_input_opnum)
6095 for (j = 0; j < n_reloads; j++)
6096 if (i != j && rld[j].reg_rtx != 0
6097 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6098 && (! conflicting_input
6099 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6100 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6102 rld[i].when_needed = RELOAD_OTHER;
6104 reload_spill_index[j] = -1;
6105 transfer_replacements (i, j);
6108 /* If this is now RELOAD_OTHER, look for any reloads that load
6109 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6110 if they were for inputs, RELOAD_OTHER for outputs. Note that
6111 this test is equivalent to looking for reloads for this operand
6113 /* We must take special care when there are two or more reloads to
6114 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6115 same value or a part of it; we must not change its type if there
6116 is a conflicting input. */
6118 if (rld[i].when_needed == RELOAD_OTHER)
6119 for (j = 0; j < n_reloads; j++)
6121 && rld[j].when_needed != RELOAD_OTHER
6122 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6123 && (! conflicting_input
6124 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6125 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6126 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6132 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6133 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6134 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6136 /* Check to see if we accidentally converted two reloads
6137 that use the same reload register to the same type.
6138 If so, the resulting code won't work, so abort. */
6140 for (k = 0; k < j; k++)
6141 if (rld[k].in != 0 && rld[k].reg_rtx != 0
6142 && rld[k].when_needed == rld[j].when_needed
6143 && rtx_equal_p (rld[k].reg_rtx, rld[j].reg_rtx))
6150 /* These arrays are filled by emit_reload_insns and its subroutines. */
6151 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6152 static rtx other_input_address_reload_insns = 0;
6153 static rtx other_input_reload_insns = 0;
6154 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6155 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6156 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6157 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6158 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6159 static rtx operand_reload_insns = 0;
6160 static rtx other_operand_reload_insns = 0;
6161 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6163 /* Values to be put in spill_reg_store are put here first. */
6164 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6165 static HARD_REG_SET reg_reloaded_died;
6167 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6168 has the number J. OLD contains the value to be used as input. */
6171 emit_input_reload_insns (chain, rl, old, j)
6172 struct insn_chain *chain;
6177 rtx insn = chain->insn;
6178 rtx reloadreg = rl->reg_rtx;
6179 rtx oldequiv_reg = 0;
6182 enum machine_mode mode;
6185 /* Determine the mode to reload in.
6186 This is very tricky because we have three to choose from.
6187 There is the mode the insn operand wants (rl->inmode).
6188 There is the mode of the reload register RELOADREG.
6189 There is the intrinsic mode of the operand, which we could find
6190 by stripping some SUBREGs.
6191 It turns out that RELOADREG's mode is irrelevant:
6192 we can change that arbitrarily.
6194 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6195 then the reload reg may not support QImode moves, so use SImode.
6196 If foo is in memory due to spilling a pseudo reg, this is safe,
6197 because the QImode value is in the least significant part of a
6198 slot big enough for a SImode. If foo is some other sort of
6199 memory reference, then it is impossible to reload this case,
6200 so previous passes had better make sure this never happens.
6202 Then consider a one-word union which has SImode and one of its
6203 members is a float, being fetched as (SUBREG:SF union:SI).
6204 We must fetch that as SFmode because we could be loading into
6205 a float-only register. In this case OLD's mode is correct.
6207 Consider an immediate integer: it has VOIDmode. Here we need
6208 to get a mode from something else.
6210 In some cases, there is a fourth mode, the operand's
6211 containing mode. If the insn specifies a containing mode for
6212 this operand, it overrides all others.
6214 I am not sure whether the algorithm here is always right,
6215 but it does the right things in those cases. */
6217 mode = GET_MODE (old);
6218 if (mode == VOIDmode)
6221 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6222 /* If we need a secondary register for this operation, see if
6223 the value is already in a register in that class. Don't
6224 do this if the secondary register will be used as a scratch
6227 if (rl->secondary_in_reload >= 0
6228 && rl->secondary_in_icode == CODE_FOR_nothing
6231 = find_equiv_reg (old, insn,
6232 rld[rl->secondary_in_reload].class,
6236 /* If reloading from memory, see if there is a register
6237 that already holds the same value. If so, reload from there.
6238 We can pass 0 as the reload_reg_p argument because
6239 any other reload has either already been emitted,
6240 in which case find_equiv_reg will see the reload-insn,
6241 or has yet to be emitted, in which case it doesn't matter
6242 because we will use this equiv reg right away. */
6244 if (oldequiv == 0 && optimize
6245 && (GET_CODE (old) == MEM
6246 || (GET_CODE (old) == REG
6247 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6248 && reg_renumber[REGNO (old)] < 0)))
6249 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6253 unsigned int regno = true_regnum (oldequiv);
6255 /* Don't use OLDEQUIV if any other reload changes it at an
6256 earlier stage of this insn or at this stage. */
6257 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6258 rl->in, const0_rtx, j, 0))
6261 /* If it is no cheaper to copy from OLDEQUIV into the
6262 reload register than it would be to move from memory,
6263 don't use it. Likewise, if we need a secondary register
6267 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6268 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6270 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6271 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6272 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6276 #ifdef SECONDARY_MEMORY_NEEDED
6277 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6285 /* delete_output_reload is only invoked properly if old contains
6286 the original pseudo register. Since this is replaced with a
6287 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6288 find the pseudo in RELOAD_IN_REG. */
6290 && reload_override_in[j]
6291 && GET_CODE (rl->in_reg) == REG)
6298 else if (GET_CODE (oldequiv) == REG)
6299 oldequiv_reg = oldequiv;
6300 else if (GET_CODE (oldequiv) == SUBREG)
6301 oldequiv_reg = SUBREG_REG (oldequiv);
6303 /* If we are reloading from a register that was recently stored in
6304 with an output-reload, see if we can prove there was
6305 actually no need to store the old value in it. */
6307 if (optimize && GET_CODE (oldequiv) == REG
6308 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6309 && spill_reg_store[REGNO (oldequiv)]
6310 && GET_CODE (old) == REG
6311 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6312 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6314 delete_output_reload (insn, j, REGNO (oldequiv));
6316 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6317 then load RELOADREG from OLDEQUIV. Note that we cannot use
6318 gen_lowpart_common since it can do the wrong thing when
6319 RELOADREG has a multi-word mode. Note that RELOADREG
6320 must always be a REG here. */
6322 if (GET_MODE (reloadreg) != mode)
6323 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6324 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6325 oldequiv = SUBREG_REG (oldequiv);
6326 if (GET_MODE (oldequiv) != VOIDmode
6327 && mode != GET_MODE (oldequiv))
6328 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6330 /* Switch to the right place to emit the reload insns. */
6331 switch (rl->when_needed)
6334 where = &other_input_reload_insns;
6336 case RELOAD_FOR_INPUT:
6337 where = &input_reload_insns[rl->opnum];
6339 case RELOAD_FOR_INPUT_ADDRESS:
6340 where = &input_address_reload_insns[rl->opnum];
6342 case RELOAD_FOR_INPADDR_ADDRESS:
6343 where = &inpaddr_address_reload_insns[rl->opnum];
6345 case RELOAD_FOR_OUTPUT_ADDRESS:
6346 where = &output_address_reload_insns[rl->opnum];
6348 case RELOAD_FOR_OUTADDR_ADDRESS:
6349 where = &outaddr_address_reload_insns[rl->opnum];
6351 case RELOAD_FOR_OPERAND_ADDRESS:
6352 where = &operand_reload_insns;
6354 case RELOAD_FOR_OPADDR_ADDR:
6355 where = &other_operand_reload_insns;
6357 case RELOAD_FOR_OTHER_ADDRESS:
6358 where = &other_input_address_reload_insns;
6364 push_to_sequence (*where);
6366 /* Auto-increment addresses must be reloaded in a special way. */
6367 if (rl->out && ! rl->out_reg)
6369 /* We are not going to bother supporting the case where a
6370 incremented register can't be copied directly from
6371 OLDEQUIV since this seems highly unlikely. */
6372 if (rl->secondary_in_reload >= 0)
6375 if (reload_inherited[j])
6376 oldequiv = reloadreg;
6378 old = XEXP (rl->in_reg, 0);
6380 if (optimize && GET_CODE (oldequiv) == REG
6381 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6382 && spill_reg_store[REGNO (oldequiv)]
6383 && GET_CODE (old) == REG
6384 && (dead_or_set_p (insn,
6385 spill_reg_stored_to[REGNO (oldequiv)])
6386 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6388 delete_output_reload (insn, j, REGNO (oldequiv));
6390 /* Prevent normal processing of this reload. */
6392 /* Output a special code sequence for this case. */
6393 new_spill_reg_store[REGNO (reloadreg)]
6394 = inc_for_reload (reloadreg, oldequiv, rl->out,
6398 /* If we are reloading a pseudo-register that was set by the previous
6399 insn, see if we can get rid of that pseudo-register entirely
6400 by redirecting the previous insn into our reload register. */
6402 else if (optimize && GET_CODE (old) == REG
6403 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6404 && dead_or_set_p (insn, old)
6405 /* This is unsafe if some other reload
6406 uses the same reg first. */
6407 && ! conflicts_with_override (reloadreg)
6408 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6409 rl->when_needed, old, rl->out, j, 0))
6411 rtx temp = PREV_INSN (insn);
6412 while (temp && GET_CODE (temp) == NOTE)
6413 temp = PREV_INSN (temp);
6415 && GET_CODE (temp) == INSN
6416 && GET_CODE (PATTERN (temp)) == SET
6417 && SET_DEST (PATTERN (temp)) == old
6418 /* Make sure we can access insn_operand_constraint. */
6419 && asm_noperands (PATTERN (temp)) < 0
6420 /* This is unsafe if operand occurs more than once in current
6421 insn. Perhaps some occurrences aren't reloaded. */
6422 && count_occurrences (PATTERN (insn), old, 0) == 1)
6424 rtx old = SET_DEST (PATTERN (temp));
6425 /* Store into the reload register instead of the pseudo. */
6426 SET_DEST (PATTERN (temp)) = reloadreg;
6428 /* Verify that resulting insn is valid. */
6429 extract_insn (temp);
6430 if (constrain_operands (1))
6432 /* If the previous insn is an output reload, the source is
6433 a reload register, and its spill_reg_store entry will
6434 contain the previous destination. This is now
6436 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6437 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6439 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6440 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6443 /* If these are the only uses of the pseudo reg,
6444 pretend for GDB it lives in the reload reg we used. */
6445 if (REG_N_DEATHS (REGNO (old)) == 1
6446 && REG_N_SETS (REGNO (old)) == 1)
6448 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6449 alter_reg (REGNO (old), -1);
6455 SET_DEST (PATTERN (temp)) = old;
6460 /* We can't do that, so output an insn to load RELOADREG. */
6462 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6463 /* If we have a secondary reload, pick up the secondary register
6464 and icode, if any. If OLDEQUIV and OLD are different or
6465 if this is an in-out reload, recompute whether or not we
6466 still need a secondary register and what the icode should
6467 be. If we still need a secondary register and the class or
6468 icode is different, go back to reloading from OLD if using
6469 OLDEQUIV means that we got the wrong type of register. We
6470 cannot have different class or icode due to an in-out reload
6471 because we don't make such reloads when both the input and
6472 output need secondary reload registers. */
6474 if (! special && rl->secondary_in_reload >= 0)
6476 rtx second_reload_reg = 0;
6477 int secondary_reload = rl->secondary_in_reload;
6478 rtx real_oldequiv = oldequiv;
6481 enum insn_code icode;
6483 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6484 and similarly for OLD.
6485 See comments in get_secondary_reload in reload.c. */
6486 /* If it is a pseudo that cannot be replaced with its
6487 equivalent MEM, we must fall back to reload_in, which
6488 will have all the necessary substitutions registered.
6489 Likewise for a pseudo that can't be replaced with its
6490 equivalent constant.
6492 Take extra care for subregs of such pseudos. Note that
6493 we cannot use reg_equiv_mem in this case because it is
6494 not in the right mode. */
6497 if (GET_CODE (tmp) == SUBREG)
6498 tmp = SUBREG_REG (tmp);
6499 if (GET_CODE (tmp) == REG
6500 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6501 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6502 || reg_equiv_constant[REGNO (tmp)] != 0))
6504 if (! reg_equiv_mem[REGNO (tmp)]
6505 || num_not_at_initial_offset
6506 || GET_CODE (oldequiv) == SUBREG)
6507 real_oldequiv = rl->in;
6509 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6513 if (GET_CODE (tmp) == SUBREG)
6514 tmp = SUBREG_REG (tmp);
6515 if (GET_CODE (tmp) == REG
6516 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6517 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6518 || reg_equiv_constant[REGNO (tmp)] != 0))
6520 if (! reg_equiv_mem[REGNO (tmp)]
6521 || num_not_at_initial_offset
6522 || GET_CODE (old) == SUBREG)
6525 real_old = reg_equiv_mem[REGNO (tmp)];
6528 second_reload_reg = rld[secondary_reload].reg_rtx;
6529 icode = rl->secondary_in_icode;
6531 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6532 || (rl->in != 0 && rl->out != 0))
6534 enum reg_class new_class
6535 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6536 mode, real_oldequiv);
6538 if (new_class == NO_REGS)
6539 second_reload_reg = 0;
6542 enum insn_code new_icode;
6543 enum machine_mode new_mode;
6545 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6546 REGNO (second_reload_reg)))
6547 oldequiv = old, real_oldequiv = real_old;
6550 new_icode = reload_in_optab[(int) mode];
6551 if (new_icode != CODE_FOR_nothing
6552 && ((insn_data[(int) new_icode].operand[0].predicate
6553 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6555 || (insn_data[(int) new_icode].operand[1].predicate
6556 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6557 (real_oldequiv, mode)))))
6558 new_icode = CODE_FOR_nothing;
6560 if (new_icode == CODE_FOR_nothing)
6563 new_mode = insn_data[(int) new_icode].operand[2].mode;
6565 if (GET_MODE (second_reload_reg) != new_mode)
6567 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6569 oldequiv = old, real_oldequiv = real_old;
6572 = reload_adjust_reg_for_mode (second_reload_reg,
6579 /* If we still need a secondary reload register, check
6580 to see if it is being used as a scratch or intermediate
6581 register and generate code appropriately. If we need
6582 a scratch register, use REAL_OLDEQUIV since the form of
6583 the insn may depend on the actual address if it is
6586 if (second_reload_reg)
6588 if (icode != CODE_FOR_nothing)
6590 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6591 second_reload_reg));
6596 /* See if we need a scratch register to load the
6597 intermediate register (a tertiary reload). */
6598 enum insn_code tertiary_icode
6599 = rld[secondary_reload].secondary_in_icode;
6601 if (tertiary_icode != CODE_FOR_nothing)
6603 rtx third_reload_reg
6604 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6606 emit_insn ((GEN_FCN (tertiary_icode)
6607 (second_reload_reg, real_oldequiv,
6608 third_reload_reg)));
6611 gen_reload (second_reload_reg, real_oldequiv,
6615 oldequiv = second_reload_reg;
6621 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6623 rtx real_oldequiv = oldequiv;
6625 if ((GET_CODE (oldequiv) == REG
6626 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6627 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6628 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6629 || (GET_CODE (oldequiv) == SUBREG
6630 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6631 && (REGNO (SUBREG_REG (oldequiv))
6632 >= FIRST_PSEUDO_REGISTER)
6633 && ((reg_equiv_memory_loc
6634 [REGNO (SUBREG_REG (oldequiv))] != 0)
6635 || (reg_equiv_constant
6636 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6637 || (CONSTANT_P (oldequiv)
6638 && (PREFERRED_RELOAD_CLASS (oldequiv,
6639 REGNO_REG_CLASS (REGNO (reloadreg)))
6641 real_oldequiv = rl->in;
6642 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6646 if (flag_non_call_exceptions)
6647 copy_eh_notes (insn, get_insns ());
6649 /* End this sequence. */
6650 *where = get_insns ();
6653 /* Update reload_override_in so that delete_address_reloads_1
6654 can see the actual register usage. */
6656 reload_override_in[j] = oldequiv;
6659 /* Generate insns to for the output reload RL, which is for the insn described
6660 by CHAIN and has the number J. */
6662 emit_output_reload_insns (chain, rl, j)
6663 struct insn_chain *chain;
6667 rtx reloadreg = rl->reg_rtx;
6668 rtx insn = chain->insn;
6671 enum machine_mode mode = GET_MODE (old);
6674 if (rl->when_needed == RELOAD_OTHER)
6677 push_to_sequence (output_reload_insns[rl->opnum]);
6679 /* Determine the mode to reload in.
6680 See comments above (for input reloading). */
6682 if (mode == VOIDmode)
6684 /* VOIDmode should never happen for an output. */
6685 if (asm_noperands (PATTERN (insn)) < 0)
6686 /* It's the compiler's fault. */
6687 fatal_insn ("VOIDmode on an output", insn);
6688 error_for_asm (insn, "output operand is constant in `asm'");
6689 /* Prevent crash--use something we know is valid. */
6691 old = gen_rtx_REG (mode, REGNO (reloadreg));
6694 if (GET_MODE (reloadreg) != mode)
6695 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6697 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6699 /* If we need two reload regs, set RELOADREG to the intermediate
6700 one, since it will be stored into OLD. We might need a secondary
6701 register only for an input reload, so check again here. */
6703 if (rl->secondary_out_reload >= 0)
6707 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6708 && reg_equiv_mem[REGNO (old)] != 0)
6709 real_old = reg_equiv_mem[REGNO (old)];
6711 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6715 rtx second_reloadreg = reloadreg;
6716 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6718 /* See if RELOADREG is to be used as a scratch register
6719 or as an intermediate register. */
6720 if (rl->secondary_out_icode != CODE_FOR_nothing)
6722 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6723 (real_old, second_reloadreg, reloadreg)));
6728 /* See if we need both a scratch and intermediate reload
6731 int secondary_reload = rl->secondary_out_reload;
6732 enum insn_code tertiary_icode
6733 = rld[secondary_reload].secondary_out_icode;
6735 if (GET_MODE (reloadreg) != mode)
6736 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6738 if (tertiary_icode != CODE_FOR_nothing)
6741 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6744 /* Copy primary reload reg to secondary reload reg.
6745 (Note that these have been swapped above, then
6746 secondary reload reg to OLD using our insn.) */
6748 /* If REAL_OLD is a paradoxical SUBREG, remove it
6749 and try to put the opposite SUBREG on
6751 if (GET_CODE (real_old) == SUBREG
6752 && (GET_MODE_SIZE (GET_MODE (real_old))
6753 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6754 && 0 != (tem = gen_lowpart_common
6755 (GET_MODE (SUBREG_REG (real_old)),
6757 real_old = SUBREG_REG (real_old), reloadreg = tem;
6759 gen_reload (reloadreg, second_reloadreg,
6760 rl->opnum, rl->when_needed);
6761 emit_insn ((GEN_FCN (tertiary_icode)
6762 (real_old, reloadreg, third_reloadreg)));
6767 /* Copy between the reload regs here and then to
6770 gen_reload (reloadreg, second_reloadreg,
6771 rl->opnum, rl->when_needed);
6777 /* Output the last reload insn. */
6782 /* Don't output the last reload if OLD is not the dest of
6783 INSN and is in the src and is clobbered by INSN. */
6784 if (! flag_expensive_optimizations
6785 || GET_CODE (old) != REG
6786 || !(set = single_set (insn))
6787 || rtx_equal_p (old, SET_DEST (set))
6788 || !reg_mentioned_p (old, SET_SRC (set))
6789 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6790 gen_reload (old, reloadreg, rl->opnum,
6794 /* Look at all insns we emitted, just to be safe. */
6795 for (p = get_insns (); p; p = NEXT_INSN (p))
6798 rtx pat = PATTERN (p);
6800 /* If this output reload doesn't come from a spill reg,
6801 clear any memory of reloaded copies of the pseudo reg.
6802 If this output reload comes from a spill reg,
6803 reg_has_output_reload will make this do nothing. */
6804 note_stores (pat, forget_old_reloads_1, NULL);
6806 if (reg_mentioned_p (rl->reg_rtx, pat))
6808 rtx set = single_set (insn);
6809 if (reload_spill_index[j] < 0
6811 && SET_SRC (set) == rl->reg_rtx)
6813 int src = REGNO (SET_SRC (set));
6815 reload_spill_index[j] = src;
6816 SET_HARD_REG_BIT (reg_is_output_reload, src);
6817 if (find_regno_note (insn, REG_DEAD, src))
6818 SET_HARD_REG_BIT (reg_reloaded_died, src);
6820 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6822 int s = rl->secondary_out_reload;
6823 set = single_set (p);
6824 /* If this reload copies only to the secondary reload
6825 register, the secondary reload does the actual
6827 if (s >= 0 && set == NULL_RTX)
6828 /* We can't tell what function the secondary reload
6829 has and where the actual store to the pseudo is
6830 made; leave new_spill_reg_store alone. */
6833 && SET_SRC (set) == rl->reg_rtx
6834 && SET_DEST (set) == rld[s].reg_rtx)
6836 /* Usually the next instruction will be the
6837 secondary reload insn; if we can confirm
6838 that it is, setting new_spill_reg_store to
6839 that insn will allow an extra optimization. */
6840 rtx s_reg = rld[s].reg_rtx;
6841 rtx next = NEXT_INSN (p);
6842 rld[s].out = rl->out;
6843 rld[s].out_reg = rl->out_reg;
6844 set = single_set (next);
6845 if (set && SET_SRC (set) == s_reg
6846 && ! new_spill_reg_store[REGNO (s_reg)])
6848 SET_HARD_REG_BIT (reg_is_output_reload,
6850 new_spill_reg_store[REGNO (s_reg)] = next;
6854 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6859 if (rl->when_needed == RELOAD_OTHER)
6861 emit_insn (other_output_reload_insns[rl->opnum]);
6862 other_output_reload_insns[rl->opnum] = get_insns ();
6865 output_reload_insns[rl->opnum] = get_insns ();
6867 if (flag_non_call_exceptions)
6868 copy_eh_notes (insn, get_insns ());
6873 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6874 and has the number J. */
6876 do_input_reload (chain, rl, j)
6877 struct insn_chain *chain;
6881 rtx insn = chain->insn;
6882 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6883 ? rl->in_reg : rl->in);
6886 /* AUTO_INC reloads need to be handled even if inherited. We got an
6887 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6888 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6889 && ! rtx_equal_p (rl->reg_rtx, old)
6890 && rl->reg_rtx != 0)
6891 emit_input_reload_insns (chain, rld + j, old, j);
6893 /* When inheriting a wider reload, we have a MEM in rl->in,
6894 e.g. inheriting a SImode output reload for
6895 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6896 if (optimize && reload_inherited[j] && rl->in
6897 && GET_CODE (rl->in) == MEM
6898 && GET_CODE (rl->in_reg) == MEM
6899 && reload_spill_index[j] >= 0
6900 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6901 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6903 /* If we are reloading a register that was recently stored in with an
6904 output-reload, see if we can prove there was
6905 actually no need to store the old value in it. */
6908 && (reload_inherited[j] || reload_override_in[j])
6910 && GET_CODE (rl->reg_rtx) == REG
6911 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6913 /* There doesn't seem to be any reason to restrict this to pseudos
6914 and doing so loses in the case where we are copying from a
6915 register of the wrong class. */
6916 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6917 >= FIRST_PSEUDO_REGISTER)
6919 /* The insn might have already some references to stackslots
6920 replaced by MEMs, while reload_out_reg still names the
6922 && (dead_or_set_p (insn,
6923 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6924 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6926 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6929 /* Do output reloading for reload RL, which is for the insn described by
6930 CHAIN and has the number J.
6931 ??? At some point we need to support handling output reloads of
6932 JUMP_INSNs or insns that set cc0. */
6934 do_output_reload (chain, rl, j)
6935 struct insn_chain *chain;
6940 rtx insn = chain->insn;
6941 /* If this is an output reload that stores something that is
6942 not loaded in this same reload, see if we can eliminate a previous
6944 rtx pseudo = rl->out_reg;
6948 && GET_CODE (pseudo) == REG
6949 && ! rtx_equal_p (rl->in_reg, pseudo)
6950 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6951 && reg_last_reload_reg[REGNO (pseudo)])
6953 int pseudo_no = REGNO (pseudo);
6954 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6956 /* We don't need to test full validity of last_regno for
6957 inherit here; we only want to know if the store actually
6958 matches the pseudo. */
6959 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6960 && reg_reloaded_contents[last_regno] == pseudo_no
6961 && spill_reg_store[last_regno]
6962 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6963 delete_output_reload (insn, j, last_regno);
6968 || rl->reg_rtx == old
6969 || rl->reg_rtx == 0)
6972 /* An output operand that dies right away does need a reload,
6973 but need not be copied from it. Show the new location in the
6975 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6976 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6978 XEXP (note, 0) = rl->reg_rtx;
6981 /* Likewise for a SUBREG of an operand that dies. */
6982 else if (GET_CODE (old) == SUBREG
6983 && GET_CODE (SUBREG_REG (old)) == REG
6984 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6987 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6991 else if (GET_CODE (old) == SCRATCH)
6992 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6993 but we don't want to make an output reload. */
6996 /* If is a JUMP_INSN, we can't support output reloads yet. */
6997 if (GET_CODE (insn) == JUMP_INSN)
7000 emit_output_reload_insns (chain, rld + j, j);
7003 /* Output insns to reload values in and out of the chosen reload regs. */
7006 emit_reload_insns (chain)
7007 struct insn_chain *chain;
7009 rtx insn = chain->insn;
7013 CLEAR_HARD_REG_SET (reg_reloaded_died);
7015 for (j = 0; j < reload_n_operands; j++)
7016 input_reload_insns[j] = input_address_reload_insns[j]
7017 = inpaddr_address_reload_insns[j]
7018 = output_reload_insns[j] = output_address_reload_insns[j]
7019 = outaddr_address_reload_insns[j]
7020 = other_output_reload_insns[j] = 0;
7021 other_input_address_reload_insns = 0;
7022 other_input_reload_insns = 0;
7023 operand_reload_insns = 0;
7024 other_operand_reload_insns = 0;
7026 /* Dump reloads into the dump file. */
7029 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7030 debug_reload_to_stream (rtl_dump_file);
7033 /* Now output the instructions to copy the data into and out of the
7034 reload registers. Do these in the order that the reloads were reported,
7035 since reloads of base and index registers precede reloads of operands
7036 and the operands may need the base and index registers reloaded. */
7038 for (j = 0; j < n_reloads; j++)
7041 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7042 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7044 do_input_reload (chain, rld + j, j);
7045 do_output_reload (chain, rld + j, j);
7048 /* Now write all the insns we made for reloads in the order expected by
7049 the allocation functions. Prior to the insn being reloaded, we write
7050 the following reloads:
7052 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7054 RELOAD_OTHER reloads.
7056 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7057 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7058 RELOAD_FOR_INPUT reload for the operand.
7060 RELOAD_FOR_OPADDR_ADDRS reloads.
7062 RELOAD_FOR_OPERAND_ADDRESS reloads.
7064 After the insn being reloaded, we write the following:
7066 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7067 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7068 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7069 reloads for the operand. The RELOAD_OTHER output reloads are
7070 output in descending order by reload number. */
7072 emit_insn_before (other_input_address_reload_insns, insn);
7073 emit_insn_before (other_input_reload_insns, insn);
7075 for (j = 0; j < reload_n_operands; j++)
7077 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7078 emit_insn_before (input_address_reload_insns[j], insn);
7079 emit_insn_before (input_reload_insns[j], insn);
7082 emit_insn_before (other_operand_reload_insns, insn);
7083 emit_insn_before (operand_reload_insns, insn);
7085 for (j = 0; j < reload_n_operands; j++)
7087 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7088 x = emit_insn_after (output_address_reload_insns[j], x);
7089 x = emit_insn_after (output_reload_insns[j], x);
7090 emit_insn_after (other_output_reload_insns[j], x);
7093 /* For all the spill regs newly reloaded in this instruction,
7094 record what they were reloaded from, so subsequent instructions
7095 can inherit the reloads.
7097 Update spill_reg_store for the reloads of this insn.
7098 Copy the elements that were updated in the loop above. */
7100 for (j = 0; j < n_reloads; j++)
7102 int r = reload_order[j];
7103 int i = reload_spill_index[r];
7105 /* If this is a non-inherited input reload from a pseudo, we must
7106 clear any memory of a previous store to the same pseudo. Only do
7107 something if there will not be an output reload for the pseudo
7109 if (rld[r].in_reg != 0
7110 && ! (reload_inherited[r] || reload_override_in[r]))
7112 rtx reg = rld[r].in_reg;
7114 if (GET_CODE (reg) == SUBREG)
7115 reg = SUBREG_REG (reg);
7117 if (GET_CODE (reg) == REG
7118 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7119 && ! reg_has_output_reload[REGNO (reg)])
7121 int nregno = REGNO (reg);
7123 if (reg_last_reload_reg[nregno])
7125 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7127 if (reg_reloaded_contents[last_regno] == nregno)
7128 spill_reg_store[last_regno] = 0;
7133 /* I is nonneg if this reload used a register.
7134 If rld[r].reg_rtx is 0, this is an optional reload
7135 that we opted to ignore. */
7137 if (i >= 0 && rld[r].reg_rtx != 0)
7139 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
7141 int part_reaches_end = 0;
7142 int all_reaches_end = 1;
7144 /* For a multi register reload, we need to check if all or part
7145 of the value lives to the end. */
7146 for (k = 0; k < nr; k++)
7148 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7149 rld[r].when_needed))
7150 part_reaches_end = 1;
7152 all_reaches_end = 0;
7155 /* Ignore reloads that don't reach the end of the insn in
7157 if (all_reaches_end)
7159 /* First, clear out memory of what used to be in this spill reg.
7160 If consecutive registers are used, clear them all. */
7162 for (k = 0; k < nr; k++)
7163 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7165 /* Maybe the spill reg contains a copy of reload_out. */
7167 && (GET_CODE (rld[r].out) == REG
7171 || GET_CODE (rld[r].out_reg) == REG))
7173 rtx out = (GET_CODE (rld[r].out) == REG
7177 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7178 int nregno = REGNO (out);
7179 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7180 : HARD_REGNO_NREGS (nregno,
7181 GET_MODE (rld[r].reg_rtx)));
7183 spill_reg_store[i] = new_spill_reg_store[i];
7184 spill_reg_stored_to[i] = out;
7185 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7187 /* If NREGNO is a hard register, it may occupy more than
7188 one register. If it does, say what is in the
7189 rest of the registers assuming that both registers
7190 agree on how many words the object takes. If not,
7191 invalidate the subsequent registers. */
7193 if (nregno < FIRST_PSEUDO_REGISTER)
7194 for (k = 1; k < nnr; k++)
7195 reg_last_reload_reg[nregno + k]
7197 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7200 /* Now do the inverse operation. */
7201 for (k = 0; k < nr; k++)
7203 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7204 reg_reloaded_contents[i + k]
7205 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7208 reg_reloaded_insn[i + k] = insn;
7209 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7213 /* Maybe the spill reg contains a copy of reload_in. Only do
7214 something if there will not be an output reload for
7215 the register being reloaded. */
7216 else if (rld[r].out_reg == 0
7218 && ((GET_CODE (rld[r].in) == REG
7219 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7220 && ! reg_has_output_reload[REGNO (rld[r].in)])
7221 || (GET_CODE (rld[r].in_reg) == REG
7222 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7223 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7228 if (GET_CODE (rld[r].in) == REG
7229 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7230 nregno = REGNO (rld[r].in);
7231 else if (GET_CODE (rld[r].in_reg) == REG)
7232 nregno = REGNO (rld[r].in_reg);
7234 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7236 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7237 : HARD_REGNO_NREGS (nregno,
7238 GET_MODE (rld[r].reg_rtx)));
7240 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7242 if (nregno < FIRST_PSEUDO_REGISTER)
7243 for (k = 1; k < nnr; k++)
7244 reg_last_reload_reg[nregno + k]
7246 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7249 /* Unless we inherited this reload, show we haven't
7250 recently done a store.
7251 Previous stores of inherited auto_inc expressions
7252 also have to be discarded. */
7253 if (! reload_inherited[r]
7254 || (rld[r].out && ! rld[r].out_reg))
7255 spill_reg_store[i] = 0;
7257 for (k = 0; k < nr; k++)
7259 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7260 reg_reloaded_contents[i + k]
7261 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7264 reg_reloaded_insn[i + k] = insn;
7265 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7270 /* However, if part of the reload reaches the end, then we must
7271 invalidate the old info for the part that survives to the end. */
7272 else if (part_reaches_end)
7274 for (k = 0; k < nr; k++)
7275 if (reload_reg_reaches_end_p (i + k,
7277 rld[r].when_needed))
7278 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7282 /* The following if-statement was #if 0'd in 1.34 (or before...).
7283 It's reenabled in 1.35 because supposedly nothing else
7284 deals with this problem. */
7286 /* If a register gets output-reloaded from a non-spill register,
7287 that invalidates any previous reloaded copy of it.
7288 But forget_old_reloads_1 won't get to see it, because
7289 it thinks only about the original insn. So invalidate it here. */
7290 if (i < 0 && rld[r].out != 0
7291 && (GET_CODE (rld[r].out) == REG
7292 || (GET_CODE (rld[r].out) == MEM
7293 && GET_CODE (rld[r].out_reg) == REG)))
7295 rtx out = (GET_CODE (rld[r].out) == REG
7296 ? rld[r].out : rld[r].out_reg);
7297 int nregno = REGNO (out);
7298 if (nregno >= FIRST_PSEUDO_REGISTER)
7300 rtx src_reg, store_insn = NULL_RTX;
7302 reg_last_reload_reg[nregno] = 0;
7304 /* If we can find a hard register that is stored, record
7305 the storing insn so that we may delete this insn with
7306 delete_output_reload. */
7307 src_reg = rld[r].reg_rtx;
7309 /* If this is an optional reload, try to find the source reg
7310 from an input reload. */
7313 rtx set = single_set (insn);
7314 if (set && SET_DEST (set) == rld[r].out)
7318 src_reg = SET_SRC (set);
7320 for (k = 0; k < n_reloads; k++)
7322 if (rld[k].in == src_reg)
7324 src_reg = rld[k].reg_rtx;
7331 store_insn = new_spill_reg_store[REGNO (src_reg)];
7332 if (src_reg && GET_CODE (src_reg) == REG
7333 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7335 int src_regno = REGNO (src_reg);
7336 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7337 /* The place where to find a death note varies with
7338 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7339 necessarily checked exactly in the code that moves
7340 notes, so just check both locations. */
7341 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7342 if (! note && store_insn)
7343 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7346 spill_reg_store[src_regno + nr] = store_insn;
7347 spill_reg_stored_to[src_regno + nr] = out;
7348 reg_reloaded_contents[src_regno + nr] = nregno;
7349 reg_reloaded_insn[src_regno + nr] = store_insn;
7350 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7351 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7352 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7354 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7356 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7358 reg_last_reload_reg[nregno] = src_reg;
7363 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7365 while (num_regs-- > 0)
7366 reg_last_reload_reg[nregno + num_regs] = 0;
7370 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7373 /* Emit code to perform a reload from IN (which may be a reload register) to
7374 OUT (which may also be a reload register). IN or OUT is from operand
7375 OPNUM with reload type TYPE.
7377 Returns first insn emitted. */
7380 gen_reload (out, in, opnum, type)
7384 enum reload_type type;
7386 rtx last = get_last_insn ();
7389 /* If IN is a paradoxical SUBREG, remove it and try to put the
7390 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7391 if (GET_CODE (in) == SUBREG
7392 && (GET_MODE_SIZE (GET_MODE (in))
7393 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7394 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7395 in = SUBREG_REG (in), out = tem;
7396 else if (GET_CODE (out) == SUBREG
7397 && (GET_MODE_SIZE (GET_MODE (out))
7398 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7399 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7400 out = SUBREG_REG (out), in = tem;
7402 /* How to do this reload can get quite tricky. Normally, we are being
7403 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7404 register that didn't get a hard register. In that case we can just
7405 call emit_move_insn.
7407 We can also be asked to reload a PLUS that adds a register or a MEM to
7408 another register, constant or MEM. This can occur during frame pointer
7409 elimination and while reloading addresses. This case is handled by
7410 trying to emit a single insn to perform the add. If it is not valid,
7411 we use a two insn sequence.
7413 Finally, we could be called to handle an 'o' constraint by putting
7414 an address into a register. In that case, we first try to do this
7415 with a named pattern of "reload_load_address". If no such pattern
7416 exists, we just emit a SET insn and hope for the best (it will normally
7417 be valid on machines that use 'o').
7419 This entire process is made complex because reload will never
7420 process the insns we generate here and so we must ensure that
7421 they will fit their constraints and also by the fact that parts of
7422 IN might be being reloaded separately and replaced with spill registers.
7423 Because of this, we are, in some sense, just guessing the right approach
7424 here. The one listed above seems to work.
7426 ??? At some point, this whole thing needs to be rethought. */
7428 if (GET_CODE (in) == PLUS
7429 && (GET_CODE (XEXP (in, 0)) == REG
7430 || GET_CODE (XEXP (in, 0)) == SUBREG
7431 || GET_CODE (XEXP (in, 0)) == MEM)
7432 && (GET_CODE (XEXP (in, 1)) == REG
7433 || GET_CODE (XEXP (in, 1)) == SUBREG
7434 || CONSTANT_P (XEXP (in, 1))
7435 || GET_CODE (XEXP (in, 1)) == MEM))
7437 /* We need to compute the sum of a register or a MEM and another
7438 register, constant, or MEM, and put it into the reload
7439 register. The best possible way of doing this is if the machine
7440 has a three-operand ADD insn that accepts the required operands.
7442 The simplest approach is to try to generate such an insn and see if it
7443 is recognized and matches its constraints. If so, it can be used.
7445 It might be better not to actually emit the insn unless it is valid,
7446 but we need to pass the insn as an operand to `recog' and
7447 `extract_insn' and it is simpler to emit and then delete the insn if
7448 not valid than to dummy things up. */
7450 rtx op0, op1, tem, insn;
7453 op0 = find_replacement (&XEXP (in, 0));
7454 op1 = find_replacement (&XEXP (in, 1));
7456 /* Since constraint checking is strict, commutativity won't be
7457 checked, so we need to do that here to avoid spurious failure
7458 if the add instruction is two-address and the second operand
7459 of the add is the same as the reload reg, which is frequently
7460 the case. If the insn would be A = B + A, rearrange it so
7461 it will be A = A + B as constrain_operands expects. */
7463 if (GET_CODE (XEXP (in, 1)) == REG
7464 && REGNO (out) == REGNO (XEXP (in, 1)))
7465 tem = op0, op0 = op1, op1 = tem;
7467 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7468 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7470 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7471 code = recog_memoized (insn);
7475 extract_insn (insn);
7476 /* We want constrain operands to treat this insn strictly in
7477 its validity determination, i.e., the way it would after reload
7479 if (constrain_operands (1))
7483 delete_insns_since (last);
7485 /* If that failed, we must use a conservative two-insn sequence.
7487 Use a move to copy one operand into the reload register. Prefer
7488 to reload a constant, MEM or pseudo since the move patterns can
7489 handle an arbitrary operand. If OP1 is not a constant, MEM or
7490 pseudo and OP1 is not a valid operand for an add instruction, then
7493 After reloading one of the operands into the reload register, add
7494 the reload register to the output register.
7496 If there is another way to do this for a specific machine, a
7497 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7500 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7502 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7503 || (GET_CODE (op1) == REG
7504 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7505 || (code != CODE_FOR_nothing
7506 && ! ((*insn_data[code].operand[2].predicate)
7507 (op1, insn_data[code].operand[2].mode))))
7508 tem = op0, op0 = op1, op1 = tem;
7510 gen_reload (out, op0, opnum, type);
7512 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7513 This fixes a problem on the 32K where the stack pointer cannot
7514 be used as an operand of an add insn. */
7516 if (rtx_equal_p (op0, op1))
7519 insn = emit_insn (gen_add2_insn (out, op1));
7521 /* If that failed, copy the address register to the reload register.
7522 Then add the constant to the reload register. */
7524 code = recog_memoized (insn);
7528 extract_insn (insn);
7529 /* We want constrain operands to treat this insn strictly in
7530 its validity determination, i.e., the way it would after reload
7532 if (constrain_operands (1))
7534 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7536 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7541 delete_insns_since (last);
7543 gen_reload (out, op1, opnum, type);
7544 insn = emit_insn (gen_add2_insn (out, op0));
7545 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7548 #ifdef SECONDARY_MEMORY_NEEDED
7549 /* If we need a memory location to do the move, do it that way. */
7550 else if ((GET_CODE (in) == REG || GET_CODE (in) == SUBREG)
7551 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7552 && (GET_CODE (out) == REG || GET_CODE (out) == SUBREG)
7553 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7554 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7555 REGNO_REG_CLASS (reg_or_subregno (out)),
7558 /* Get the memory to use and rewrite both registers to its mode. */
7559 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7561 if (GET_MODE (loc) != GET_MODE (out))
7562 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7564 if (GET_MODE (loc) != GET_MODE (in))
7565 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7567 gen_reload (loc, in, opnum, type);
7568 gen_reload (out, loc, opnum, type);
7572 /* If IN is a simple operand, use gen_move_insn. */
7573 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7574 emit_insn (gen_move_insn (out, in));
7576 #ifdef HAVE_reload_load_address
7577 else if (HAVE_reload_load_address)
7578 emit_insn (gen_reload_load_address (out, in));
7581 /* Otherwise, just write (set OUT IN) and hope for the best. */
7583 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7585 /* Return the first insn emitted.
7586 We can not just return get_last_insn, because there may have
7587 been multiple instructions emitted. Also note that gen_move_insn may
7588 emit more than one insn itself, so we can not assume that there is one
7589 insn emitted per emit_insn_before call. */
7591 return last ? NEXT_INSN (last) : get_insns ();
7594 /* Delete a previously made output-reload whose result we now believe
7595 is not needed. First we double-check.
7597 INSN is the insn now being processed.
7598 LAST_RELOAD_REG is the hard register number for which we want to delete
7599 the last output reload.
7600 J is the reload-number that originally used REG. The caller has made
7601 certain that reload J doesn't use REG any longer for input. */
7604 delete_output_reload (insn, j, last_reload_reg)
7607 int last_reload_reg;
7609 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7610 rtx reg = spill_reg_stored_to[last_reload_reg];
7613 int n_inherited = 0;
7617 /* It is possible that this reload has been only used to set another reload
7618 we eliminated earlier and thus deleted this instruction too. */
7619 if (INSN_DELETED_P (output_reload_insn))
7622 /* Get the raw pseudo-register referred to. */
7624 while (GET_CODE (reg) == SUBREG)
7625 reg = SUBREG_REG (reg);
7626 substed = reg_equiv_memory_loc[REGNO (reg)];
7628 /* This is unsafe if the operand occurs more often in the current
7629 insn than it is inherited. */
7630 for (k = n_reloads - 1; k >= 0; k--)
7632 rtx reg2 = rld[k].in;
7635 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7636 reg2 = rld[k].in_reg;
7638 if (rld[k].out && ! rld[k].out_reg)
7639 reg2 = XEXP (rld[k].in_reg, 0);
7641 while (GET_CODE (reg2) == SUBREG)
7642 reg2 = SUBREG_REG (reg2);
7643 if (rtx_equal_p (reg2, reg))
7645 if (reload_inherited[k] || reload_override_in[k] || k == j)
7648 reg2 = rld[k].out_reg;
7651 while (GET_CODE (reg2) == SUBREG)
7652 reg2 = XEXP (reg2, 0);
7653 if (rtx_equal_p (reg2, reg))
7660 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7662 n_occurrences += count_occurrences (PATTERN (insn),
7663 eliminate_regs (substed, 0,
7665 if (n_occurrences > n_inherited)
7668 /* If the pseudo-reg we are reloading is no longer referenced
7669 anywhere between the store into it and here,
7670 and no jumps or labels intervene, then the value can get
7671 here through the reload reg alone.
7672 Otherwise, give up--return. */
7673 for (i1 = NEXT_INSN (output_reload_insn);
7674 i1 != insn; i1 = NEXT_INSN (i1))
7676 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7678 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7679 && reg_mentioned_p (reg, PATTERN (i1)))
7681 /* If this is USE in front of INSN, we only have to check that
7682 there are no more references than accounted for by inheritance. */
7683 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7685 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7686 i1 = NEXT_INSN (i1);
7688 if (n_occurrences <= n_inherited && i1 == insn)
7694 /* We will be deleting the insn. Remove the spill reg information. */
7695 for (k = HARD_REGNO_NREGS (last_reload_reg, GET_MODE (reg)); k-- > 0; )
7697 spill_reg_store[last_reload_reg + k] = 0;
7698 spill_reg_stored_to[last_reload_reg + k] = 0;
7701 /* The caller has already checked that REG dies or is set in INSN.
7702 It has also checked that we are optimizing, and thus some
7703 inaccuracies in the debugging information are acceptable.
7704 So we could just delete output_reload_insn. But in some cases
7705 we can improve the debugging information without sacrificing
7706 optimization - maybe even improving the code: See if the pseudo
7707 reg has been completely replaced with reload regs. If so, delete
7708 the store insn and forget we had a stack slot for the pseudo. */
7709 if (rld[j].out != rld[j].in
7710 && REG_N_DEATHS (REGNO (reg)) == 1
7711 && REG_N_SETS (REGNO (reg)) == 1
7712 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7713 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7717 /* We know that it was used only between here and the beginning of
7718 the current basic block. (We also know that the last use before
7719 INSN was the output reload we are thinking of deleting, but never
7720 mind that.) Search that range; see if any ref remains. */
7721 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7723 rtx set = single_set (i2);
7725 /* Uses which just store in the pseudo don't count,
7726 since if they are the only uses, they are dead. */
7727 if (set != 0 && SET_DEST (set) == reg)
7729 if (GET_CODE (i2) == CODE_LABEL
7730 || GET_CODE (i2) == JUMP_INSN)
7732 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7733 && reg_mentioned_p (reg, PATTERN (i2)))
7735 /* Some other ref remains; just delete the output reload we
7737 delete_address_reloads (output_reload_insn, insn);
7738 delete_insn (output_reload_insn);
7743 /* Delete the now-dead stores into this pseudo. Note that this
7744 loop also takes care of deleting output_reload_insn. */
7745 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7747 rtx set = single_set (i2);
7749 if (set != 0 && SET_DEST (set) == reg)
7751 delete_address_reloads (i2, insn);
7754 if (GET_CODE (i2) == CODE_LABEL
7755 || GET_CODE (i2) == JUMP_INSN)
7759 /* For the debugging info, say the pseudo lives in this reload reg. */
7760 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7761 alter_reg (REGNO (reg), -1);
7765 delete_address_reloads (output_reload_insn, insn);
7766 delete_insn (output_reload_insn);
7770 /* We are going to delete DEAD_INSN. Recursively delete loads of
7771 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7772 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7774 delete_address_reloads (dead_insn, current_insn)
7775 rtx dead_insn, current_insn;
7777 rtx set = single_set (dead_insn);
7778 rtx set2, dst, prev, next;
7781 rtx dst = SET_DEST (set);
7782 if (GET_CODE (dst) == MEM)
7783 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7785 /* If we deleted the store from a reloaded post_{in,de}c expression,
7786 we can delete the matching adds. */
7787 prev = PREV_INSN (dead_insn);
7788 next = NEXT_INSN (dead_insn);
7789 if (! prev || ! next)
7791 set = single_set (next);
7792 set2 = single_set (prev);
7794 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7795 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7796 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7798 dst = SET_DEST (set);
7799 if (! rtx_equal_p (dst, SET_DEST (set2))
7800 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7801 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7802 || (INTVAL (XEXP (SET_SRC (set), 1))
7803 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7805 delete_related_insns (prev);
7806 delete_related_insns (next);
7809 /* Subfunction of delete_address_reloads: process registers found in X. */
7811 delete_address_reloads_1 (dead_insn, x, current_insn)
7812 rtx dead_insn, x, current_insn;
7814 rtx prev, set, dst, i2;
7816 enum rtx_code code = GET_CODE (x);
7820 const char *fmt = GET_RTX_FORMAT (code);
7821 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7824 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7825 else if (fmt[i] == 'E')
7827 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7828 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7835 if (spill_reg_order[REGNO (x)] < 0)
7838 /* Scan backwards for the insn that sets x. This might be a way back due
7840 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7842 code = GET_CODE (prev);
7843 if (code == CODE_LABEL || code == JUMP_INSN)
7845 if (GET_RTX_CLASS (code) != 'i')
7847 if (reg_set_p (x, PATTERN (prev)))
7849 if (reg_referenced_p (x, PATTERN (prev)))
7852 if (! prev || INSN_UID (prev) < reload_first_uid)
7854 /* Check that PREV only sets the reload register. */
7855 set = single_set (prev);
7858 dst = SET_DEST (set);
7859 if (GET_CODE (dst) != REG
7860 || ! rtx_equal_p (dst, x))
7862 if (! reg_set_p (dst, PATTERN (dead_insn)))
7864 /* Check if DST was used in a later insn -
7865 it might have been inherited. */
7866 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7868 if (GET_CODE (i2) == CODE_LABEL)
7872 if (reg_referenced_p (dst, PATTERN (i2)))
7874 /* If there is a reference to the register in the current insn,
7875 it might be loaded in a non-inherited reload. If no other
7876 reload uses it, that means the register is set before
7878 if (i2 == current_insn)
7880 for (j = n_reloads - 1; j >= 0; j--)
7881 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7882 || reload_override_in[j] == dst)
7884 for (j = n_reloads - 1; j >= 0; j--)
7885 if (rld[j].in && rld[j].reg_rtx == dst)
7892 if (GET_CODE (i2) == JUMP_INSN)
7894 /* If DST is still live at CURRENT_INSN, check if it is used for
7895 any reload. Note that even if CURRENT_INSN sets DST, we still
7896 have to check the reloads. */
7897 if (i2 == current_insn)
7899 for (j = n_reloads - 1; j >= 0; j--)
7900 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7901 || reload_override_in[j] == dst)
7903 /* ??? We can't finish the loop here, because dst might be
7904 allocated to a pseudo in this block if no reload in this
7905 block needs any of the classes containing DST - see
7906 spill_hard_reg. There is no easy way to tell this, so we
7907 have to scan till the end of the basic block. */
7909 if (reg_set_p (dst, PATTERN (i2)))
7913 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7914 reg_reloaded_contents[REGNO (dst)] = -1;
7918 /* Output reload-insns to reload VALUE into RELOADREG.
7919 VALUE is an autoincrement or autodecrement RTX whose operand
7920 is a register or memory location;
7921 so reloading involves incrementing that location.
7922 IN is either identical to VALUE, or some cheaper place to reload from.
7924 INC_AMOUNT is the number to increment or decrement by (always positive).
7925 This cannot be deduced from VALUE.
7927 Return the instruction that stores into RELOADREG. */
7930 inc_for_reload (reloadreg, in, value, inc_amount)
7935 /* REG or MEM to be copied and incremented. */
7936 rtx incloc = XEXP (value, 0);
7937 /* Nonzero if increment after copying. */
7938 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7944 rtx real_in = in == value ? XEXP (in, 0) : in;
7946 /* No hard register is equivalent to this register after
7947 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7948 we could inc/dec that register as well (maybe even using it for
7949 the source), but I'm not sure it's worth worrying about. */
7950 if (GET_CODE (incloc) == REG)
7951 reg_last_reload_reg[REGNO (incloc)] = 0;
7953 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7954 inc_amount = -inc_amount;
7956 inc = GEN_INT (inc_amount);
7958 /* If this is post-increment, first copy the location to the reload reg. */
7959 if (post && real_in != reloadreg)
7960 emit_insn (gen_move_insn (reloadreg, real_in));
7964 /* See if we can directly increment INCLOC. Use a method similar to
7965 that in gen_reload. */
7967 last = get_last_insn ();
7968 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7969 gen_rtx_PLUS (GET_MODE (incloc),
7972 code = recog_memoized (add_insn);
7975 extract_insn (add_insn);
7976 if (constrain_operands (1))
7978 /* If this is a pre-increment and we have incremented the value
7979 where it lives, copy the incremented value to RELOADREG to
7980 be used as an address. */
7983 emit_insn (gen_move_insn (reloadreg, incloc));
7988 delete_insns_since (last);
7991 /* If couldn't do the increment directly, must increment in RELOADREG.
7992 The way we do this depends on whether this is pre- or post-increment.
7993 For pre-increment, copy INCLOC to the reload register, increment it
7994 there, then save back. */
7998 if (in != reloadreg)
7999 emit_insn (gen_move_insn (reloadreg, real_in));
8000 emit_insn (gen_add2_insn (reloadreg, inc));
8001 store = emit_insn (gen_move_insn (incloc, reloadreg));
8006 Because this might be a jump insn or a compare, and because RELOADREG
8007 may not be available after the insn in an input reload, we must do
8008 the incrementation before the insn being reloaded for.
8010 We have already copied IN to RELOADREG. Increment the copy in
8011 RELOADREG, save that back, then decrement RELOADREG so it has
8012 the original value. */
8014 emit_insn (gen_add2_insn (reloadreg, inc));
8015 store = emit_insn (gen_move_insn (incloc, reloadreg));
8016 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8023 /* See whether a single set SET is a noop. */
8025 reload_cse_noop_set_p (set)
8028 if (cselib_reg_set_mode (SET_DEST (set)) != GET_MODE (SET_DEST (set)))
8031 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
8034 /* Try to simplify INSN. */
8036 reload_cse_simplify (insn, testreg)
8040 rtx body = PATTERN (insn);
8042 if (GET_CODE (body) == SET)
8046 /* Simplify even if we may think it is a no-op.
8047 We may think a memory load of a value smaller than WORD_SIZE
8048 is redundant because we haven't taken into account possible
8049 implicit extension. reload_cse_simplify_set() will bring
8050 this out, so it's safer to simplify before we delete. */
8051 count += reload_cse_simplify_set (body, insn);
8053 if (!count && reload_cse_noop_set_p (body))
8055 rtx value = SET_DEST (body);
8057 && ! REG_FUNCTION_VALUE_P (value))
8059 delete_insn_and_edges (insn);
8064 apply_change_group ();
8066 reload_cse_simplify_operands (insn, testreg);
8068 else if (GET_CODE (body) == PARALLEL)
8072 rtx value = NULL_RTX;
8074 /* If every action in a PARALLEL is a noop, we can delete
8075 the entire PARALLEL. */
8076 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8078 rtx part = XVECEXP (body, 0, i);
8079 if (GET_CODE (part) == SET)
8081 if (! reload_cse_noop_set_p (part))
8083 if (REG_P (SET_DEST (part))
8084 && REG_FUNCTION_VALUE_P (SET_DEST (part)))
8088 value = SET_DEST (part);
8091 else if (GET_CODE (part) != CLOBBER)
8097 delete_insn_and_edges (insn);
8098 /* We're done with this insn. */
8102 /* It's not a no-op, but we can try to simplify it. */
8103 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8104 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8105 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8108 apply_change_group ();
8110 reload_cse_simplify_operands (insn, testreg);
8114 /* Do a very simple CSE pass over the hard registers.
8116 This function detects no-op moves where we happened to assign two
8117 different pseudo-registers to the same hard register, and then
8118 copied one to the other. Reload will generate a useless
8119 instruction copying a register to itself.
8121 This function also detects cases where we load a value from memory
8122 into two different registers, and (if memory is more expensive than
8123 registers) changes it to simply copy the first register into the
8126 Another optimization is performed that scans the operands of each
8127 instruction to see whether the value is already available in a
8128 hard register. It then replaces the operand with the hard register
8129 if possible, much like an optional reload would. */
8132 reload_cse_regs_1 (first)
8136 rtx testreg = gen_rtx_REG (VOIDmode, -1);
8139 init_alias_analysis ();
8141 for (insn = first; insn; insn = NEXT_INSN (insn))
8144 reload_cse_simplify (insn, testreg);
8146 cselib_process_insn (insn);
8150 end_alias_analysis ();
8154 /* Call cse / combine like post-reload optimization phases.
8155 FIRST is the first instruction. */
8157 reload_cse_regs (first)
8160 reload_cse_regs_1 (first);
8162 reload_cse_move2add (first);
8163 if (flag_expensive_optimizations)
8164 reload_cse_regs_1 (first);
8167 /* Try to simplify a single SET instruction. SET is the set pattern.
8168 INSN is the instruction it came from.
8169 This function only handles one case: if we set a register to a value
8170 which is not a register, we try to find that value in some other register
8171 and change the set into a register copy. */
8174 reload_cse_simplify_set (set, insn)
8181 enum reg_class dclass;
8184 struct elt_loc_list *l;
8185 #ifdef LOAD_EXTEND_OP
8186 enum rtx_code extend_op = NIL;
8189 dreg = true_regnum (SET_DEST (set));
8193 src = SET_SRC (set);
8194 if (side_effects_p (src) || true_regnum (src) >= 0)
8197 dclass = REGNO_REG_CLASS (dreg);
8199 #ifdef LOAD_EXTEND_OP
8200 /* When replacing a memory with a register, we need to honor assumptions
8201 that combine made wrt the contents of sign bits. We'll do this by
8202 generating an extend instruction instead of a reg->reg copy. Thus
8203 the destination must be a register that we can widen. */
8204 if (GET_CODE (src) == MEM
8205 && GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD
8206 && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != NIL
8207 && GET_CODE (SET_DEST (set)) != REG)
8211 /* If memory loads are cheaper than register copies, don't change them. */
8212 if (GET_CODE (src) == MEM)
8213 old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
8214 else if (CONSTANT_P (src))
8215 old_cost = rtx_cost (src, SET);
8216 else if (GET_CODE (src) == REG)
8217 old_cost = REGISTER_MOVE_COST (GET_MODE (src),
8218 REGNO_REG_CLASS (REGNO (src)), dclass);
8221 old_cost = rtx_cost (src, SET);
8223 val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0);
8226 for (l = val->locs; l; l = l->next)
8228 rtx this_rtx = l->loc;
8231 if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0))
8233 #ifdef LOAD_EXTEND_OP
8234 if (extend_op != NIL)
8236 HOST_WIDE_INT this_val;
8238 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
8239 constants, such as SYMBOL_REF, cannot be extended. */
8240 if (GET_CODE (this_rtx) != CONST_INT)
8243 this_val = INTVAL (this_rtx);
8247 this_val &= GET_MODE_MASK (GET_MODE (src));
8250 /* ??? In theory we're already extended. */
8251 if (this_val == trunc_int_for_mode (this_val, GET_MODE (src)))
8256 this_rtx = GEN_INT (this_val);
8259 this_cost = rtx_cost (this_rtx, SET);
8261 else if (GET_CODE (this_rtx) == REG)
8263 #ifdef LOAD_EXTEND_OP
8264 if (extend_op != NIL)
8266 this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx);
8267 this_cost = rtx_cost (this_rtx, SET);
8271 this_cost = REGISTER_MOVE_COST (GET_MODE (this_rtx),
8272 REGNO_REG_CLASS (REGNO (this_rtx)),
8278 /* If equal costs, prefer registers over anything else. That
8279 tends to lead to smaller instructions on some machines. */
8280 if (this_cost < old_cost
8281 || (this_cost == old_cost
8282 && GET_CODE (this_rtx) == REG
8283 && GET_CODE (SET_SRC (set)) != REG))
8285 #ifdef LOAD_EXTEND_OP
8286 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD
8288 #ifdef CANNOT_CHANGE_MODE_CLASS
8289 && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set)),
8291 REGNO_REG_CLASS (REGNO (SET_DEST (set))))
8295 rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set)));
8296 ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set));
8297 validate_change (insn, &SET_DEST (set), wide_dest, 1);
8301 validate_change (insn, &SET_SRC (set), copy_rtx (this_rtx), 1);
8302 old_cost = this_cost, did_change = 1;
8309 /* Try to replace operands in INSN with equivalent values that are already
8310 in registers. This can be viewed as optional reloading.
8312 For each non-register operand in the insn, see if any hard regs are
8313 known to be equivalent to that operand. Record the alternatives which
8314 can accept these hard registers. Among all alternatives, select the
8315 ones which are better or equal to the one currently matching, where
8316 "better" is in terms of '?' and '!' constraints. Among the remaining
8317 alternatives, select the one which replaces most operands with
8321 reload_cse_simplify_operands (insn, testreg)
8327 /* For each operand, all registers that are equivalent to it. */
8328 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
8330 const char *constraints[MAX_RECOG_OPERANDS];
8332 /* Vector recording how bad an alternative is. */
8333 int *alternative_reject;
8334 /* Vector recording how many registers can be introduced by choosing
8335 this alternative. */
8336 int *alternative_nregs;
8337 /* Array of vectors recording, for each operand and each alternative,
8338 which hard register to substitute, or -1 if the operand should be
8340 int *op_alt_regno[MAX_RECOG_OPERANDS];
8341 /* Array of alternatives, sorted in order of decreasing desirability. */
8342 int *alternative_order;
8344 extract_insn (insn);
8346 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8349 /* Figure out which alternative currently matches. */
8350 if (! constrain_operands (1))
8351 fatal_insn_not_found (insn);
8353 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8354 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8355 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8356 memset ((char *) alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
8357 memset ((char *) alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
8359 /* For each operand, find out which regs are equivalent. */
8360 for (i = 0; i < recog_data.n_operands; i++)
8363 struct elt_loc_list *l;
8365 CLEAR_HARD_REG_SET (equiv_regs[i]);
8367 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8368 right, so avoid the problem here. Likewise if we have a constant
8369 and the insn pattern doesn't tell us the mode we need. */
8370 if (GET_CODE (recog_data.operand[i]) == CODE_LABEL
8371 || (CONSTANT_P (recog_data.operand[i])
8372 && recog_data.operand_mode[i] == VOIDmode))
8375 v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0);
8379 for (l = v->locs; l; l = l->next)
8380 if (GET_CODE (l->loc) == REG)
8381 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
8384 for (i = 0; i < recog_data.n_operands; i++)
8386 enum machine_mode mode;
8390 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8391 for (j = 0; j < recog_data.n_alternatives; j++)
8392 op_alt_regno[i][j] = -1;
8394 p = constraints[i] = recog_data.constraints[i];
8395 mode = recog_data.operand_mode[i];
8397 /* Add the reject values for each alternative given by the constraints
8398 for this operand. */
8406 alternative_reject[j] += 3;
8408 alternative_reject[j] += 300;
8411 /* We won't change operands which are already registers. We
8412 also don't want to modify output operands. */
8413 regno = true_regnum (recog_data.operand[i]);
8415 || constraints[i][0] == '='
8416 || constraints[i][0] == '+')
8419 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8421 int class = (int) NO_REGS;
8423 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
8426 REGNO (testreg) = regno;
8427 PUT_MODE (testreg, mode);
8429 /* We found a register equal to this operand. Now look for all
8430 alternatives that can accept this register and have not been
8431 assigned a register they can use yet. */
8440 case '=': case '+': case '?':
8441 case '#': case '&': case '!':
8443 case '0': case '1': case '2': case '3': case '4':
8444 case '5': case '6': case '7': case '8': case '9':
8445 case 'm': case '<': case '>': case 'V': case 'o':
8446 case 'E': case 'F': case 'G': case 'H':
8447 case 's': case 'i': case 'n':
8448 case 'I': case 'J': case 'K': case 'L':
8449 case 'M': case 'N': case 'O': case 'P':
8451 /* These don't say anything we care about. */
8455 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8460 = (reg_class_subunion
8462 [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c, p)]);
8465 case ',': case '\0':
8466 /* See if REGNO fits this alternative, and set it up as the
8467 replacement register if we don't have one for this
8468 alternative yet and the operand being replaced is not
8469 a cheap CONST_INT. */
8470 if (op_alt_regno[i][j] == -1
8471 && reg_fits_class_p (testreg, class, 0, mode)
8472 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8473 || (rtx_cost (recog_data.operand[i], SET)
8474 > rtx_cost (testreg, SET))))
8476 alternative_nregs[j]++;
8477 op_alt_regno[i][j] = regno;
8482 p += CONSTRAINT_LEN (c, p);
8490 /* Record all alternatives which are better or equal to the currently
8491 matching one in the alternative_order array. */
8492 for (i = j = 0; i < recog_data.n_alternatives; i++)
8493 if (alternative_reject[i] <= alternative_reject[which_alternative])
8494 alternative_order[j++] = i;
8495 recog_data.n_alternatives = j;
8497 /* Sort it. Given a small number of alternatives, a dumb algorithm
8498 won't hurt too much. */
8499 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8502 int best_reject = alternative_reject[alternative_order[i]];
8503 int best_nregs = alternative_nregs[alternative_order[i]];
8506 for (j = i + 1; j < recog_data.n_alternatives; j++)
8508 int this_reject = alternative_reject[alternative_order[j]];
8509 int this_nregs = alternative_nregs[alternative_order[j]];
8511 if (this_reject < best_reject
8512 || (this_reject == best_reject && this_nregs < best_nregs))
8515 best_reject = this_reject;
8516 best_nregs = this_nregs;
8520 tmp = alternative_order[best];
8521 alternative_order[best] = alternative_order[i];
8522 alternative_order[i] = tmp;
8525 /* Substitute the operands as determined by op_alt_regno for the best
8527 j = alternative_order[0];
8529 for (i = 0; i < recog_data.n_operands; i++)
8531 enum machine_mode mode = recog_data.operand_mode[i];
8532 if (op_alt_regno[i][j] == -1)
8535 validate_change (insn, recog_data.operand_loc[i],
8536 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8539 for (i = recog_data.n_dups - 1; i >= 0; i--)
8541 int op = recog_data.dup_num[i];
8542 enum machine_mode mode = recog_data.operand_mode[op];
8544 if (op_alt_regno[op][j] == -1)
8547 validate_change (insn, recog_data.dup_loc[i],
8548 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8551 return apply_change_group ();
8554 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8556 This code might also be useful when reload gave up on reg+reg addressing
8557 because of clashes between the return register and INDEX_REG_CLASS. */
8559 /* The maximum number of uses of a register we can keep track of to
8560 replace them with reg+reg addressing. */
8561 #define RELOAD_COMBINE_MAX_USES 6
8563 /* INSN is the insn where a register has ben used, and USEP points to the
8564 location of the register within the rtl. */
8565 struct reg_use { rtx insn, *usep; };
8567 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8568 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8569 indicates where it becomes live again.
8570 Otherwise, USE_INDEX is the index of the last encountered use of the
8571 register (which is first among these we have seen since we scan backwards),
8572 OFFSET contains the constant offset that is added to the register in
8573 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8574 last, of these uses.
8575 STORE_RUID is always meaningful if we only want to use a value in a
8576 register in a different place: it denotes the next insn in the insn
8577 stream (i.e. the last encountered) that sets or clobbers the register. */
8580 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8585 } reg_state[FIRST_PSEUDO_REGISTER];
8587 /* Reverse linear uid. This is increased in reload_combine while scanning
8588 the instructions from last to first. It is used to set last_label_ruid
8589 and the store_ruid / use_ruid fields in reg_state. */
8590 static int reload_combine_ruid;
8592 #define LABEL_LIVE(LABEL) \
8593 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8599 int first_index_reg = -1;
8600 int last_index_reg = 0;
8604 int last_label_ruid;
8605 int min_labelno, n_labels;
8606 HARD_REG_SET ever_live_at_start, *label_live;
8608 /* If reg+reg can be used in offsetable memory addresses, the main chunk of
8609 reload has already used it where appropriate, so there is no use in
8610 trying to generate it now. */
8611 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8614 /* To avoid wasting too much time later searching for an index register,
8615 determine the minimum and maximum index register numbers. */
8616 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8617 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
8619 if (first_index_reg == -1)
8620 first_index_reg = r;
8625 /* If no index register is available, we can quit now. */
8626 if (first_index_reg == -1)
8629 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8630 information is a bit fuzzy immediately after reload, but it's
8631 still good enough to determine which registers are live at a jump
8633 min_labelno = get_first_label_num ();
8634 n_labels = max_label_num () - min_labelno;
8635 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8636 CLEAR_HARD_REG_SET (ever_live_at_start);
8638 FOR_EACH_BB_REVERSE (bb)
8641 if (GET_CODE (insn) == CODE_LABEL)
8645 REG_SET_TO_HARD_REG_SET (live,
8646 bb->global_live_at_start);
8647 compute_use_by_pseudos (&live,
8648 bb->global_live_at_start);
8649 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8650 IOR_HARD_REG_SET (ever_live_at_start, live);
8654 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8655 last_label_ruid = reload_combine_ruid = 0;
8656 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8658 reg_state[r].store_ruid = reload_combine_ruid;
8660 reg_state[r].use_index = -1;
8662 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8665 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8669 /* We cannot do our optimization across labels. Invalidating all the use
8670 information we have would be costly, so we just note where the label
8671 is and then later disable any optimization that would cross it. */
8672 if (GET_CODE (insn) == CODE_LABEL)
8673 last_label_ruid = reload_combine_ruid;
8674 else if (GET_CODE (insn) == BARRIER)
8675 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8676 if (! fixed_regs[r])
8677 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8679 if (! INSN_P (insn))
8682 reload_combine_ruid++;
8684 /* Look for (set (REGX) (CONST_INT))
8685 (set (REGX) (PLUS (REGX) (REGY)))
8687 ... (MEM (REGX)) ...
8689 (set (REGZ) (CONST_INT))
8691 ... (MEM (PLUS (REGZ) (REGY)))... .
8693 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8694 and that we know all uses of REGX before it dies. */
8695 set = single_set (insn);
8697 && GET_CODE (SET_DEST (set)) == REG
8698 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
8699 GET_MODE (SET_DEST (set)))
8701 && GET_CODE (SET_SRC (set)) == PLUS
8702 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
8703 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
8704 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
8706 rtx reg = SET_DEST (set);
8707 rtx plus = SET_SRC (set);
8708 rtx base = XEXP (plus, 1);
8709 rtx prev = prev_nonnote_insn (insn);
8710 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
8711 unsigned int regno = REGNO (reg);
8712 rtx const_reg = NULL_RTX;
8713 rtx reg_sum = NULL_RTX;
8715 /* Now, we need an index register.
8716 We'll set index_reg to this index register, const_reg to the
8717 register that is to be loaded with the constant
8718 (denoted as REGZ in the substitution illustration above),
8719 and reg_sum to the register-register that we want to use to
8720 substitute uses of REG (typically in MEMs) with.
8721 First check REG and BASE for being index registers;
8722 we can use them even if they are not dead. */
8723 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
8724 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8732 /* Otherwise, look for a free index register. Since we have
8733 checked above that neiter REG nor BASE are index registers,
8734 if we find anything at all, it will be different from these
8736 for (i = first_index_reg; i <= last_index_reg; i++)
8738 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8740 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
8741 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
8742 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
8744 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
8746 const_reg = index_reg;
8747 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
8753 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8754 (REGY), i.e. BASE, is not clobbered before the last use we'll
8757 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
8758 && rtx_equal_p (SET_DEST (prev_set), reg)
8759 && reg_state[regno].use_index >= 0
8760 && (reg_state[REGNO (base)].store_ruid
8761 <= reg_state[regno].use_ruid)
8766 /* Change destination register and, if necessary, the
8767 constant value in PREV, the constant loading instruction. */
8768 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
8769 if (reg_state[regno].offset != const0_rtx)
8770 validate_change (prev,
8771 &SET_SRC (prev_set),
8772 GEN_INT (INTVAL (SET_SRC (prev_set))
8773 + INTVAL (reg_state[regno].offset)),
8776 /* Now for every use of REG that we have recorded, replace REG
8778 for (i = reg_state[regno].use_index;
8779 i < RELOAD_COMBINE_MAX_USES; i++)
8780 validate_change (reg_state[regno].reg_use[i].insn,
8781 reg_state[regno].reg_use[i].usep,
8782 /* Each change must have its own
8784 copy_rtx (reg_sum), 1);
8786 if (apply_change_group ())
8790 /* Delete the reg-reg addition. */
8793 if (reg_state[regno].offset != const0_rtx)
8794 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8796 for (np = ®_NOTES (prev); *np;)
8798 if (REG_NOTE_KIND (*np) == REG_EQUAL
8799 || REG_NOTE_KIND (*np) == REG_EQUIV)
8800 *np = XEXP (*np, 1);
8802 np = &XEXP (*np, 1);
8805 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8806 reg_state[REGNO (const_reg)].store_ruid
8807 = reload_combine_ruid;
8813 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
8815 if (GET_CODE (insn) == CALL_INSN)
8819 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8820 if (call_used_regs[r])
8822 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8823 reg_state[r].store_ruid = reload_combine_ruid;
8826 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
8827 link = XEXP (link, 1))
8829 rtx usage_rtx = XEXP (XEXP (link, 0), 0);
8830 if (GET_CODE (usage_rtx) == REG)
8833 unsigned int start_reg = REGNO (usage_rtx);
8834 unsigned int num_regs =
8835 HARD_REGNO_NREGS (start_reg, GET_MODE (usage_rtx));
8836 unsigned int end_reg = start_reg + num_regs - 1;
8837 for (i = start_reg; i <= end_reg; i++)
8838 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
8840 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8841 reg_state[i].store_ruid = reload_combine_ruid;
8844 reg_state[i].use_index = -1;
8849 else if (GET_CODE (insn) == JUMP_INSN
8850 && GET_CODE (PATTERN (insn)) != RETURN)
8852 /* Non-spill registers might be used at the call destination in
8853 some unknown fashion, so we have to mark the unknown use. */
8856 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
8857 && JUMP_LABEL (insn))
8858 live = &LABEL_LIVE (JUMP_LABEL (insn));
8860 live = &ever_live_at_start;
8862 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8863 if (TEST_HARD_REG_BIT (*live, i))
8864 reg_state[i].use_index = -1;
8867 reload_combine_note_use (&PATTERN (insn), insn);
8868 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8870 if (REG_NOTE_KIND (note) == REG_INC
8871 && GET_CODE (XEXP (note, 0)) == REG)
8873 int regno = REGNO (XEXP (note, 0));
8875 reg_state[regno].store_ruid = reload_combine_ruid;
8876 reg_state[regno].use_index = -1;
8884 /* Check if DST is a register or a subreg of a register; if it is,
8885 update reg_state[regno].store_ruid and reg_state[regno].use_index
8886 accordingly. Called via note_stores from reload_combine. */
8889 reload_combine_note_store (dst, set, data)
8891 void *data ATTRIBUTE_UNUSED;
8895 enum machine_mode mode = GET_MODE (dst);
8897 if (GET_CODE (dst) == SUBREG)
8899 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
8900 GET_MODE (SUBREG_REG (dst)),
8903 dst = SUBREG_REG (dst);
8905 if (GET_CODE (dst) != REG)
8907 regno += REGNO (dst);
8909 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8910 careful with registers / register parts that are not full words.
8912 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8913 if (GET_CODE (set) != SET
8914 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
8915 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
8916 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
8918 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8920 reg_state[i].use_index = -1;
8921 reg_state[i].store_ruid = reload_combine_ruid;
8926 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8928 reg_state[i].store_ruid = reload_combine_ruid;
8929 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8934 /* XP points to a piece of rtl that has to be checked for any uses of
8936 *XP is the pattern of INSN, or a part of it.
8937 Called from reload_combine, and recursively by itself. */
8939 reload_combine_note_use (xp, insn)
8943 enum rtx_code code = x->code;
8946 rtx offset = const0_rtx; /* For the REG case below. */
8951 if (GET_CODE (SET_DEST (x)) == REG)
8953 reload_combine_note_use (&SET_SRC (x), insn);
8959 /* If this is the USE of a return value, we can't change it. */
8960 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
8962 /* Mark the return register as used in an unknown fashion. */
8963 rtx reg = XEXP (x, 0);
8964 int regno = REGNO (reg);
8965 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
8967 while (--nregs >= 0)
8968 reg_state[regno + nregs].use_index = -1;
8974 if (GET_CODE (SET_DEST (x)) == REG)
8976 /* No spurious CLOBBERs of pseudo registers may remain. */
8977 if (REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER)
8984 /* We are interested in (plus (reg) (const_int)) . */
8985 if (GET_CODE (XEXP (x, 0)) != REG
8986 || GET_CODE (XEXP (x, 1)) != CONST_INT)
8988 offset = XEXP (x, 1);
8993 int regno = REGNO (x);
8997 /* No spurious USEs of pseudo registers may remain. */
8998 if (regno >= FIRST_PSEUDO_REGISTER)
9001 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x));
9003 /* We can't substitute into multi-hard-reg uses. */
9006 while (--nregs >= 0)
9007 reg_state[regno + nregs].use_index = -1;
9011 /* If this register is already used in some unknown fashion, we
9013 If we decrement the index from zero to -1, we can't store more
9014 uses, so this register becomes used in an unknown fashion. */
9015 use_index = --reg_state[regno].use_index;
9019 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
9021 /* We have found another use for a register that is already
9022 used later. Check if the offsets match; if not, mark the
9023 register as used in an unknown fashion. */
9024 if (! rtx_equal_p (offset, reg_state[regno].offset))
9026 reg_state[regno].use_index = -1;
9032 /* This is the first use of this register we have seen since we
9033 marked it as dead. */
9034 reg_state[regno].offset = offset;
9035 reg_state[regno].use_ruid = reload_combine_ruid;
9037 reg_state[regno].reg_use[use_index].insn = insn;
9038 reg_state[regno].reg_use[use_index].usep = xp;
9046 /* Recursively process the components of X. */
9047 fmt = GET_RTX_FORMAT (code);
9048 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9051 reload_combine_note_use (&XEXP (x, i), insn);
9052 else if (fmt[i] == 'E')
9054 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9055 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9060 /* See if we can reduce the cost of a constant by replacing a move
9061 with an add. We track situations in which a register is set to a
9062 constant or to a register plus a constant. */
9063 /* We cannot do our optimization across labels. Invalidating all the
9064 information about register contents we have would be costly, so we
9065 use move2add_last_label_luid to note where the label is and then
9066 later disable any optimization that would cross it.
9067 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9068 reg_set_luid[n] is greater than last_label_luid[n] . */
9069 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9071 /* If reg_base_reg[n] is negative, register n has been set to
9072 reg_offset[n] in mode reg_mode[n] .
9073 If reg_base_reg[n] is non-negative, register n has been set to the
9074 sum of reg_offset[n] and the value of register reg_base_reg[n]
9075 before reg_set_luid[n], calculated in mode reg_mode[n] . */
9076 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
9077 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9078 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9080 /* move2add_luid is linearly increased while scanning the instructions
9081 from first to last. It is used to set reg_set_luid in
9082 reload_cse_move2add and move2add_note_store. */
9083 static int move2add_luid;
9085 /* move2add_last_label_luid is set whenever a label is found. Labels
9086 invalidate all previously collected reg_offset data. */
9087 static int move2add_last_label_luid;
9089 /* ??? We don't know how zero / sign extension is handled, hence we
9090 can't go from a narrower to a wider mode. */
9091 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
9092 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
9093 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
9094 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \
9095 GET_MODE_BITSIZE (INMODE))))
9098 reload_cse_move2add (first)
9104 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9105 reg_set_luid[i] = 0;
9107 move2add_last_label_luid = 0;
9109 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
9113 if (GET_CODE (insn) == CODE_LABEL)
9115 move2add_last_label_luid = move2add_luid;
9116 /* We're going to increment move2add_luid twice after a
9117 label, so that we can use move2add_last_label_luid + 1 as
9118 the luid for constants. */
9122 if (! INSN_P (insn))
9124 pat = PATTERN (insn);
9125 /* For simplicity, we only perform this optimization on
9126 straightforward SETs. */
9127 if (GET_CODE (pat) == SET
9128 && GET_CODE (SET_DEST (pat)) == REG)
9130 rtx reg = SET_DEST (pat);
9131 int regno = REGNO (reg);
9132 rtx src = SET_SRC (pat);
9134 /* Check if we have valid information on the contents of this
9135 register in the mode of REG. */
9136 if (reg_set_luid[regno] > move2add_last_label_luid
9137 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno]))
9139 /* Try to transform (set (REGX) (CONST_INT A))
9141 (set (REGX) (CONST_INT B))
9143 (set (REGX) (CONST_INT A))
9145 (set (REGX) (plus (REGX) (CONST_INT B-A)))
9147 (set (REGX) (CONST_INT A))
9149 (set (STRICT_LOW_PART (REGX)) (CONST_INT B))
9152 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
9155 GEN_INT (trunc_int_for_mode (INTVAL (src)
9156 - reg_offset[regno],
9158 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9159 use (set (reg) (reg)) instead.
9160 We don't delete this insn, nor do we convert it into a
9161 note, to avoid losing register notes or the return
9162 value flag. jump2 already knows how to get rid of
9164 if (new_src == const0_rtx)
9165 validate_change (insn, &SET_SRC (pat), reg, 0);
9166 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
9167 && have_add2_insn (reg, new_src))
9169 rtx newpat = gen_add2_insn (reg, new_src);
9170 if (INSN_P (newpat) && NEXT_INSN (newpat) == NULL_RTX)
9171 newpat = PATTERN (newpat);
9172 /* If it was the first insn of a sequence or
9173 some other emitted insn, validate_change will
9175 validate_change (insn, &PATTERN (insn),
9180 enum machine_mode narrow_mode;
9181 for (narrow_mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
9182 narrow_mode != GET_MODE (reg);
9183 narrow_mode = GET_MODE_WIDER_MODE (narrow_mode))
9185 if (have_insn_for (STRICT_LOW_PART, narrow_mode)
9186 && ((reg_offset[regno]
9187 & ~GET_MODE_MASK (narrow_mode))
9189 & ~GET_MODE_MASK (narrow_mode))))
9191 rtx narrow_reg = gen_rtx_REG (narrow_mode,
9194 GEN_INT (trunc_int_for_mode (INTVAL (src),
9197 gen_rtx_SET (VOIDmode,
9198 gen_rtx_STRICT_LOW_PART (VOIDmode,
9201 if (validate_change (insn, &PATTERN (insn),
9207 reg_set_luid[regno] = move2add_luid;
9208 reg_mode[regno] = GET_MODE (reg);
9209 reg_offset[regno] = INTVAL (src);
9213 /* Try to transform (set (REGX) (REGY))
9214 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9217 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9220 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9222 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9223 else if (GET_CODE (src) == REG
9224 && reg_set_luid[regno] == reg_set_luid[REGNO (src)]
9225 && reg_base_reg[regno] == reg_base_reg[REGNO (src)]
9226 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg),
9227 reg_mode[REGNO (src)]))
9229 rtx next = next_nonnote_insn (insn);
9232 set = single_set (next);
9234 && SET_DEST (set) == reg
9235 && GET_CODE (SET_SRC (set)) == PLUS
9236 && XEXP (SET_SRC (set), 0) == reg
9237 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9239 rtx src3 = XEXP (SET_SRC (set), 1);
9240 HOST_WIDE_INT added_offset = INTVAL (src3);
9241 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)];
9242 HOST_WIDE_INT regno_offset = reg_offset[regno];
9244 GEN_INT (trunc_int_for_mode (added_offset
9250 if (new_src == const0_rtx)
9251 /* See above why we create (set (reg) (reg)) here. */
9253 = validate_change (next, &SET_SRC (set), reg, 0);
9254 else if ((rtx_cost (new_src, PLUS)
9255 < COSTS_N_INSNS (1) + rtx_cost (src3, SET))
9256 && have_add2_insn (reg, new_src))
9258 rtx newpat = gen_add2_insn (reg, new_src);
9260 && NEXT_INSN (newpat) == NULL_RTX)
9261 newpat = PATTERN (newpat);
9263 = validate_change (next, &PATTERN (next),
9269 reg_mode[regno] = GET_MODE (reg);
9271 trunc_int_for_mode (added_offset + base_offset,
9279 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9281 if (REG_NOTE_KIND (note) == REG_INC
9282 && GET_CODE (XEXP (note, 0)) == REG)
9284 /* Reset the information about this register. */
9285 int regno = REGNO (XEXP (note, 0));
9286 if (regno < FIRST_PSEUDO_REGISTER)
9287 reg_set_luid[regno] = 0;
9290 note_stores (PATTERN (insn), move2add_note_store, NULL);
9291 /* If this is a CALL_INSN, all call used registers are stored with
9293 if (GET_CODE (insn) == CALL_INSN)
9295 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9297 if (call_used_regs[i])
9298 /* Reset the information about this register. */
9299 reg_set_luid[i] = 0;
9305 /* SET is a SET or CLOBBER that sets DST.
9306 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9307 Called from reload_cse_move2add via note_stores. */
9310 move2add_note_store (dst, set, data)
9312 void *data ATTRIBUTE_UNUSED;
9314 unsigned int regno = 0;
9316 enum machine_mode mode = GET_MODE (dst);
9318 if (GET_CODE (dst) == SUBREG)
9320 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
9321 GET_MODE (SUBREG_REG (dst)),
9324 dst = SUBREG_REG (dst);
9327 /* Some targets do argument pushes without adding REG_INC notes. */
9329 if (GET_CODE (dst) == MEM)
9331 dst = XEXP (dst, 0);
9332 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC
9333 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC)
9334 reg_set_luid[REGNO (XEXP (dst, 0))] = 0;
9337 if (GET_CODE (dst) != REG)
9340 regno += REGNO (dst);
9342 if (SCALAR_INT_MODE_P (mode)
9343 && HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9344 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9345 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9346 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9348 rtx src = SET_SRC (set);
9350 HOST_WIDE_INT offset;
9352 /* This may be different from mode, if SET_DEST (set) is a
9354 enum machine_mode dst_mode = GET_MODE (dst);
9356 switch (GET_CODE (src))
9359 if (GET_CODE (XEXP (src, 0)) == REG)
9361 base_reg = XEXP (src, 0);
9363 if (GET_CODE (XEXP (src, 1)) == CONST_INT)
9364 offset = INTVAL (XEXP (src, 1));
9365 else if (GET_CODE (XEXP (src, 1)) == REG
9366 && (reg_set_luid[REGNO (XEXP (src, 1))]
9367 > move2add_last_label_luid)
9368 && (MODES_OK_FOR_MOVE2ADD
9369 (dst_mode, reg_mode[REGNO (XEXP (src, 1))])))
9371 if (reg_base_reg[REGNO (XEXP (src, 1))] < 0)
9372 offset = reg_offset[REGNO (XEXP (src, 1))];
9373 /* Maybe the first register is known to be a
9375 else if (reg_set_luid[REGNO (base_reg)]
9376 > move2add_last_label_luid
9377 && (MODES_OK_FOR_MOVE2ADD
9378 (dst_mode, reg_mode[REGNO (XEXP (src, 1))]))
9379 && reg_base_reg[REGNO (base_reg)] < 0)
9381 offset = reg_offset[REGNO (base_reg)];
9382 base_reg = XEXP (src, 1);
9401 /* Start tracking the register as a constant. */
9402 reg_base_reg[regno] = -1;
9403 reg_offset[regno] = INTVAL (SET_SRC (set));
9404 /* We assign the same luid to all registers set to constants. */
9405 reg_set_luid[regno] = move2add_last_label_luid + 1;
9406 reg_mode[regno] = mode;
9411 /* Invalidate the contents of the register. */
9412 reg_set_luid[regno] = 0;
9416 base_regno = REGNO (base_reg);
9417 /* If information about the base register is not valid, set it
9418 up as a new base register, pretending its value is known
9419 starting from the current insn. */
9420 if (reg_set_luid[base_regno] <= move2add_last_label_luid)
9422 reg_base_reg[base_regno] = base_regno;
9423 reg_offset[base_regno] = 0;
9424 reg_set_luid[base_regno] = move2add_luid;
9425 reg_mode[base_regno] = mode;
9427 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode,
9428 reg_mode[base_regno]))
9431 reg_mode[regno] = mode;
9433 /* Copy base information from our base register. */
9434 reg_set_luid[regno] = reg_set_luid[base_regno];
9435 reg_base_reg[regno] = reg_base_reg[base_regno];
9437 /* Compute the sum of the offsets or constants. */
9438 reg_offset[regno] = trunc_int_for_mode (offset
9439 + reg_offset[base_regno],
9444 unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode);
9446 for (i = regno; i < endregno; i++)
9447 /* Reset the information about this register. */
9448 reg_set_luid[i] = 0;
9454 add_auto_inc_notes (insn, x)
9458 enum rtx_code code = GET_CODE (x);
9462 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9465 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9469 /* Scan all the operand sub-expressions. */
9470 fmt = GET_RTX_FORMAT (code);
9471 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9474 add_auto_inc_notes (insn, XEXP (x, i));
9475 else if (fmt[i] == 'E')
9476 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9477 add_auto_inc_notes (insn, XVECEXP (x, i, j));
9482 /* Copy EH notes from an insn to its reloads. */
9484 copy_eh_notes (insn, x)
9488 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
9491 for (; x != 0; x = NEXT_INSN (x))
9493 if (may_trap_p (PATTERN (x)))
9495 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
9501 /* This is used by reload pass, that does emit some instructions after
9502 abnormal calls moving basic block end, but in fact it wants to emit
9503 them on the edge. Looks for abnormal call edges, find backward the
9504 proper call and fix the damage.
9506 Similar handle instructions throwing exceptions internally. */
9508 fixup_abnormal_edges ()
9510 bool inserted = false;
9517 /* Look for cases we are interested in - calls or instructions causing
9519 for (e = bb->succ; e; e = e->succ_next)
9521 if (e->flags & EDGE_ABNORMAL_CALL)
9523 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
9524 == (EDGE_ABNORMAL | EDGE_EH))
9527 if (e && GET_CODE (bb->end) != CALL_INSN && !can_throw_internal (bb->end))
9529 rtx insn = bb->end, stop = NEXT_INSN (bb->end);
9531 for (e = bb->succ; e; e = e->succ_next)
9532 if (e->flags & EDGE_FALLTHRU)
9534 /* Get past the new insns generated. Allow notes, as the insns may
9535 be already deleted. */
9536 while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE)
9537 && !can_throw_internal (insn)
9538 && insn != bb->head)
9539 insn = PREV_INSN (insn);
9540 if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn))
9544 insn = NEXT_INSN (insn);
9545 while (insn && insn != stop)
9547 next = NEXT_INSN (insn);
9552 /* Sometimes there's still the return value USE.
9553 If it's placed after a trapping call (i.e. that
9554 call is the last insn anyway), we have no fallthru
9555 edge. Simply delete this use and don't try to insert
9556 on the non-existent edge. */
9557 if (GET_CODE (PATTERN (insn)) != USE)
9559 /* We're not deleting it, we're moving it. */
9560 INSN_DELETED_P (insn) = 0;
9561 PREV_INSN (insn) = NULL_RTX;
9562 NEXT_INSN (insn) = NULL_RTX;
9564 insert_insn_on_edge (insn, e);
9571 /* We've possibly turned single trapping insn into multiple ones. */
9572 if (flag_non_call_exceptions)
9575 blocks = sbitmap_alloc (last_basic_block);
9576 sbitmap_ones (blocks);
9577 find_many_sub_basic_blocks (blocks);
9580 commit_edge_insertions ();
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