1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
48 /* This file contains the reload pass of the compiler, which is
49 run after register allocation has been done. It checks that
50 each insn is valid (operands required to be in registers really
51 are in registers of the proper class) and fixes up invalid ones
52 by copying values temporarily into registers for the insns
55 The results of register allocation are described by the vector
56 reg_renumber; the insns still contain pseudo regs, but reg_renumber
57 can be used to find which hard reg, if any, a pseudo reg is in.
59 The technique we always use is to free up a few hard regs that are
60 called ``reload regs'', and for each place where a pseudo reg
61 must be in a hard reg, copy it temporarily into one of the reload regs.
63 Reload regs are allocated locally for every instruction that needs
64 reloads. When there are pseudos which are allocated to a register that
65 has been chosen as a reload reg, such pseudos must be ``spilled''.
66 This means that they go to other hard regs, or to stack slots if no other
67 available hard regs can be found. Spilling can invalidate more
68 insns, requiring additional need for reloads, so we must keep checking
69 until the process stabilizes.
71 For machines with different classes of registers, we must keep track
72 of the register class needed for each reload, and make sure that
73 we allocate enough reload registers of each class.
75 The file reload.c contains the code that checks one insn for
76 validity and reports the reloads that it needs. This file
77 is in charge of scanning the entire rtl code, accumulating the
78 reload needs, spilling, assigning reload registers to use for
79 fixing up each insn, and generating the new insns to copy values
80 into the reload registers. */
82 #ifndef REGISTER_MOVE_COST
83 #define REGISTER_MOVE_COST(m, x, y) 2
87 #define LOCAL_REGNO(REGNO) 0
90 /* During reload_as_needed, element N contains a REG rtx for the hard reg
91 into which reg N has been reloaded (perhaps for a previous insn). */
92 static rtx *reg_last_reload_reg;
94 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
95 for an output reload that stores into reg N. */
96 static char *reg_has_output_reload;
98 /* Indicates which hard regs are reload-registers for an output reload
99 in the current insn. */
100 static HARD_REG_SET reg_is_output_reload;
102 /* Element N is the constant value to which pseudo reg N is equivalent,
103 or zero if pseudo reg N is not equivalent to a constant.
104 find_reloads looks at this in order to replace pseudo reg N
105 with the constant it stands for. */
106 rtx *reg_equiv_constant;
108 /* Element N is a memory location to which pseudo reg N is equivalent,
109 prior to any register elimination (such as frame pointer to stack
110 pointer). Depending on whether or not it is a valid address, this value
111 is transferred to either reg_equiv_address or reg_equiv_mem. */
112 rtx *reg_equiv_memory_loc;
114 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
115 This is used when the address is not valid as a memory address
116 (because its displacement is too big for the machine.) */
117 rtx *reg_equiv_address;
119 /* Element N is the memory slot to which pseudo reg N is equivalent,
120 or zero if pseudo reg N is not equivalent to a memory slot. */
123 /* Widest width in which each pseudo reg is referred to (via subreg). */
124 static unsigned int *reg_max_ref_width;
126 /* Element N is the list of insns that initialized reg N from its equivalent
127 constant or memory slot. */
128 static rtx *reg_equiv_init;
130 /* Vector to remember old contents of reg_renumber before spilling. */
131 static short *reg_old_renumber;
133 /* During reload_as_needed, element N contains the last pseudo regno reloaded
134 into hard register N. If that pseudo reg occupied more than one register,
135 reg_reloaded_contents points to that pseudo for each spill register in
136 use; all of these must remain set for an inheritance to occur. */
137 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
139 /* During reload_as_needed, element N contains the insn for which
140 hard register N was last used. Its contents are significant only
141 when reg_reloaded_valid is set for this register. */
142 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
144 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
145 static HARD_REG_SET reg_reloaded_valid;
146 /* Indicate if the register was dead at the end of the reload.
147 This is only valid if reg_reloaded_contents is set and valid. */
148 static HARD_REG_SET reg_reloaded_dead;
150 /* Number of spill-regs so far; number of valid elements of spill_regs. */
153 /* In parallel with spill_regs, contains REG rtx's for those regs.
154 Holds the last rtx used for any given reg, or 0 if it has never
155 been used for spilling yet. This rtx is reused, provided it has
157 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
159 /* In parallel with spill_regs, contains nonzero for a spill reg
160 that was stored after the last time it was used.
161 The precise value is the insn generated to do the store. */
162 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
164 /* This is the register that was stored with spill_reg_store. This is a
165 copy of reload_out / reload_out_reg when the value was stored; if
166 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
167 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
169 /* This table is the inverse mapping of spill_regs:
170 indexed by hard reg number,
171 it contains the position of that reg in spill_regs,
172 or -1 for something that is not in spill_regs.
174 ?!? This is no longer accurate. */
175 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
177 /* This reg set indicates registers that can't be used as spill registers for
178 the currently processed insn. These are the hard registers which are live
179 during the insn, but not allocated to pseudos, as well as fixed
181 static HARD_REG_SET bad_spill_regs;
183 /* These are the hard registers that can't be used as spill register for any
184 insn. This includes registers used for user variables and registers that
185 we can't eliminate. A register that appears in this set also can't be used
186 to retry register allocation. */
187 static HARD_REG_SET bad_spill_regs_global;
189 /* Describes order of use of registers for reloading
190 of spilled pseudo-registers. `n_spills' is the number of
191 elements that are actually valid; new ones are added at the end.
193 Both spill_regs and spill_reg_order are used on two occasions:
194 once during find_reload_regs, where they keep track of the spill registers
195 for a single insn, but also during reload_as_needed where they show all
196 the registers ever used by reload. For the latter case, the information
197 is calculated during finish_spills. */
198 static short spill_regs[FIRST_PSEUDO_REGISTER];
200 /* This vector of reg sets indicates, for each pseudo, which hard registers
201 may not be used for retrying global allocation because the register was
202 formerly spilled from one of them. If we allowed reallocating a pseudo to
203 a register that it was already allocated to, reload might not
205 static HARD_REG_SET *pseudo_previous_regs;
207 /* This vector of reg sets indicates, for each pseudo, which hard
208 registers may not be used for retrying global allocation because they
209 are used as spill registers during one of the insns in which the
211 static HARD_REG_SET *pseudo_forbidden_regs;
213 /* All hard regs that have been used as spill registers for any insn are
214 marked in this set. */
215 static HARD_REG_SET used_spill_regs;
217 /* Index of last register assigned as a spill register. We allocate in
218 a round-robin fashion. */
219 static int last_spill_reg;
221 /* Nonzero if indirect addressing is supported on the machine; this means
222 that spilling (REG n) does not require reloading it into a register in
223 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
224 value indicates the level of indirect addressing supported, e.g., two
225 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
227 static char spill_indirect_levels;
229 /* Nonzero if indirect addressing is supported when the innermost MEM is
230 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
231 which these are valid is the same as spill_indirect_levels, above. */
232 char indirect_symref_ok;
234 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
235 char double_reg_address_ok;
237 /* Record the stack slot for each spilled hard register. */
238 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
240 /* Width allocated so far for that stack slot. */
241 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
243 /* Record which pseudos needed to be spilled. */
244 static regset_head spilled_pseudos;
246 /* Used for communication between order_regs_for_reload and count_pseudo.
247 Used to avoid counting one pseudo twice. */
248 static regset_head pseudos_counted;
250 /* First uid used by insns created by reload in this function.
251 Used in find_equiv_reg. */
252 int reload_first_uid;
254 /* Flag set by local-alloc or global-alloc if anything is live in
255 a call-clobbered reg across calls. */
256 int caller_save_needed;
258 /* Set to 1 while reload_as_needed is operating.
259 Required by some machines to handle any generated moves differently. */
260 int reload_in_progress = 0;
262 /* These arrays record the insn_code of insns that may be needed to
263 perform input and output reloads of special objects. They provide a
264 place to pass a scratch register. */
265 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
266 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
268 /* This obstack is used for allocation of rtl during register elimination.
269 The allocated storage can be freed once find_reloads has processed the
271 struct obstack reload_obstack;
273 /* Points to the beginning of the reload_obstack. All insn_chain structures
274 are allocated first. */
275 char *reload_startobj;
277 /* The point after all insn_chain structures. Used to quickly deallocate
278 memory allocated in copy_reloads during calculate_needs_all_insns. */
279 char *reload_firstobj;
281 /* This points before all local rtl generated by register elimination.
282 Used to quickly free all memory after processing one insn. */
283 static char *reload_insn_firstobj;
285 /* List of insn_chain instructions, one for every insn that reload needs to
287 struct insn_chain *reload_insn_chain;
290 extern tree current_function_decl;
292 extern union tree_node *current_function_decl;
295 /* List of all insns needing reloads. */
296 static struct insn_chain *insns_need_reload;
298 /* This structure is used to record information about register eliminations.
299 Each array entry describes one possible way of eliminating a register
300 in favor of another. If there is more than one way of eliminating a
301 particular register, the most preferred should be specified first. */
305 int from; /* Register number to be eliminated. */
306 int to; /* Register number used as replacement. */
307 int initial_offset; /* Initial difference between values. */
308 int can_eliminate; /* Nonzero if this elimination can be done. */
309 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
310 insns made by reload. */
311 int offset; /* Current offset between the two regs. */
312 int previous_offset; /* Offset at end of previous insn. */
313 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
314 rtx from_rtx; /* REG rtx for the register to be eliminated.
315 We cannot simply compare the number since
316 we might then spuriously replace a hard
317 register corresponding to a pseudo
318 assigned to the reg to be eliminated. */
319 rtx to_rtx; /* REG rtx for the replacement. */
322 static struct elim_table *reg_eliminate = 0;
324 /* This is an intermediate structure to initialize the table. It has
325 exactly the members provided by ELIMINABLE_REGS. */
326 static const struct elim_table_1
330 } reg_eliminate_1[] =
332 /* If a set of eliminable registers was specified, define the table from it.
333 Otherwise, default to the normal case of the frame pointer being
334 replaced by the stack pointer. */
336 #ifdef ELIMINABLE_REGS
339 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
342 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
344 /* Record the number of pending eliminations that have an offset not equal
345 to their initial offset. If nonzero, we use a new copy of each
346 replacement result in any insns encountered. */
347 int num_not_at_initial_offset;
349 /* Count the number of registers that we may be able to eliminate. */
350 static int num_eliminable;
351 /* And the number of registers that are equivalent to a constant that
352 can be eliminated to frame_pointer / arg_pointer + constant. */
353 static int num_eliminable_invariants;
355 /* For each label, we record the offset of each elimination. If we reach
356 a label by more than one path and an offset differs, we cannot do the
357 elimination. This information is indexed by the difference of the
358 number of the label and the first label number. We can't offset the
359 pointer itself as this can cause problems on machines with segmented
360 memory. The first table is an array of flags that records whether we
361 have yet encountered a label and the second table is an array of arrays,
362 one entry in the latter array for each elimination. */
364 static int first_label_num;
365 static char *offsets_known_at;
366 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
368 /* Number of labels in the current function. */
370 static int num_labels;
372 static void replace_pseudos_in_call_usage PARAMS ((rtx *,
375 static void maybe_fix_stack_asms PARAMS ((void));
376 static void copy_reloads PARAMS ((struct insn_chain *));
377 static void calculate_needs_all_insns PARAMS ((int));
378 static int find_reg PARAMS ((struct insn_chain *, int));
379 static void find_reload_regs PARAMS ((struct insn_chain *));
380 static void select_reload_regs PARAMS ((void));
381 static void delete_caller_save_insns PARAMS ((void));
383 static void spill_failure PARAMS ((rtx, enum reg_class));
384 static void count_spilled_pseudo PARAMS ((int, int, int));
385 static void delete_dead_insn PARAMS ((rtx));
386 static void alter_reg PARAMS ((int, int));
387 static void set_label_offsets PARAMS ((rtx, rtx, int));
388 static void check_eliminable_occurrences PARAMS ((rtx));
389 static void elimination_effects PARAMS ((rtx, enum machine_mode));
390 static int eliminate_regs_in_insn PARAMS ((rtx, int));
391 static void update_eliminable_offsets PARAMS ((void));
392 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
393 static void set_initial_elim_offsets PARAMS ((void));
394 static void verify_initial_elim_offsets PARAMS ((void));
395 static void set_initial_label_offsets PARAMS ((void));
396 static void set_offsets_for_label PARAMS ((rtx));
397 static void init_elim_table PARAMS ((void));
398 static void update_eliminables PARAMS ((HARD_REG_SET *));
399 static void spill_hard_reg PARAMS ((unsigned int, int));
400 static int finish_spills PARAMS ((int));
401 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
402 static void scan_paradoxical_subregs PARAMS ((rtx));
403 static void count_pseudo PARAMS ((int));
404 static void order_regs_for_reload PARAMS ((struct insn_chain *));
405 static void reload_as_needed PARAMS ((int));
406 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
407 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
408 static void mark_reload_reg_in_use PARAMS ((unsigned int, int,
411 static void clear_reload_reg_in_use PARAMS ((unsigned int, int,
414 static int reload_reg_free_p PARAMS ((unsigned int, int,
416 static int reload_reg_free_for_value_p PARAMS ((int, int, int,
418 rtx, rtx, int, int));
419 static int free_for_value_p PARAMS ((int, enum machine_mode, int,
420 enum reload_type, rtx, rtx,
422 static int reload_reg_reaches_end_p PARAMS ((unsigned int, int,
424 static int allocate_reload_reg PARAMS ((struct insn_chain *, int,
426 static int conflicts_with_override PARAMS ((rtx));
427 static void failed_reload PARAMS ((rtx, int));
428 static int set_reload_reg PARAMS ((int, int));
429 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
430 static void choose_reload_regs PARAMS ((struct insn_chain *));
431 static void merge_assigned_reloads PARAMS ((rtx));
432 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
433 struct reload *, rtx, int));
434 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
435 struct reload *, int));
436 static void do_input_reload PARAMS ((struct insn_chain *,
437 struct reload *, int));
438 static void do_output_reload PARAMS ((struct insn_chain *,
439 struct reload *, int));
440 static void emit_reload_insns PARAMS ((struct insn_chain *));
441 static void delete_output_reload PARAMS ((rtx, int, int));
442 static void delete_address_reloads PARAMS ((rtx, rtx));
443 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
444 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
445 static void reload_cse_regs_1 PARAMS ((rtx));
446 static int reload_cse_noop_set_p PARAMS ((rtx));
447 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
448 static int reload_cse_simplify_operands PARAMS ((rtx, rtx));
449 static void reload_combine PARAMS ((void));
450 static void reload_combine_note_use PARAMS ((rtx *, rtx));
451 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
452 static void reload_cse_move2add PARAMS ((rtx));
453 static void move2add_note_store PARAMS ((rtx, rtx, void *));
455 static void add_auto_inc_notes PARAMS ((rtx, rtx));
457 static void copy_eh_notes PARAMS ((rtx, rtx));
458 static HOST_WIDE_INT sext_for_mode PARAMS ((enum machine_mode,
460 static void failed_reload PARAMS ((rtx, int));
461 static int set_reload_reg PARAMS ((int, int));
462 static void reload_cse_simplify PARAMS ((rtx, rtx));
463 void fixup_abnormal_edges PARAMS ((void));
464 extern void dump_needs PARAMS ((struct insn_chain *));
466 /* Initialize the reload pass once per compilation. */
473 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
474 Set spill_indirect_levels to the number of levels such addressing is
475 permitted, zero if it is not permitted at all. */
478 = gen_rtx_MEM (Pmode,
481 LAST_VIRTUAL_REGISTER + 1),
483 spill_indirect_levels = 0;
485 while (memory_address_p (QImode, tem))
487 spill_indirect_levels++;
488 tem = gen_rtx_MEM (Pmode, tem);
491 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
493 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
494 indirect_symref_ok = memory_address_p (QImode, tem);
496 /* See if reg+reg is a valid (and offsettable) address. */
498 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
500 tem = gen_rtx_PLUS (Pmode,
501 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
502 gen_rtx_REG (Pmode, i));
504 /* This way, we make sure that reg+reg is an offsettable address. */
505 tem = plus_constant (tem, 4);
507 if (memory_address_p (QImode, tem))
509 double_reg_address_ok = 1;
514 /* Initialize obstack for our rtl allocation. */
515 gcc_obstack_init (&reload_obstack);
516 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
518 INIT_REG_SET (&spilled_pseudos);
519 INIT_REG_SET (&pseudos_counted);
522 /* List of insn chains that are currently unused. */
523 static struct insn_chain *unused_insn_chains = 0;
525 /* Allocate an empty insn_chain structure. */
529 struct insn_chain *c;
531 if (unused_insn_chains == 0)
533 c = (struct insn_chain *)
534 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
535 INIT_REG_SET (&c->live_throughout);
536 INIT_REG_SET (&c->dead_or_set);
540 c = unused_insn_chains;
541 unused_insn_chains = c->next;
543 c->is_caller_save_insn = 0;
544 c->need_operand_change = 0;
550 /* Small utility function to set all regs in hard reg set TO which are
551 allocated to pseudos in regset FROM. */
554 compute_use_by_pseudos (to, from)
560 EXECUTE_IF_SET_IN_REG_SET
561 (from, FIRST_PSEUDO_REGISTER, regno,
563 int r = reg_renumber[regno];
568 /* reload_combine uses the information from
569 BASIC_BLOCK->global_live_at_start, which might still
570 contain registers that have not actually been allocated
571 since they have an equivalence. */
572 if (! reload_completed)
577 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
579 SET_HARD_REG_BIT (*to, r + nregs);
584 /* Replace all pseudos found in LOC with their corresponding
588 replace_pseudos_in_call_usage (loc, mem_mode, usage)
590 enum machine_mode mem_mode;
604 unsigned int regno = REGNO (x);
606 if (regno < FIRST_PSEUDO_REGISTER)
609 x = eliminate_regs (x, mem_mode, usage);
613 replace_pseudos_in_call_usage (loc, mem_mode, usage);
617 if (reg_equiv_constant[regno])
618 *loc = reg_equiv_constant[regno];
619 else if (reg_equiv_mem[regno])
620 *loc = reg_equiv_mem[regno];
621 else if (reg_equiv_address[regno])
622 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
623 else if (GET_CODE (regno_reg_rtx[regno]) != REG
624 || REGNO (regno_reg_rtx[regno]) != regno)
625 *loc = regno_reg_rtx[regno];
631 else if (code == MEM)
633 replace_pseudos_in_call_usage (& XEXP (x, 0), GET_MODE (x), usage);
637 /* Process each of our operands recursively. */
638 fmt = GET_RTX_FORMAT (code);
639 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
641 replace_pseudos_in_call_usage (&XEXP (x, i), mem_mode, usage);
642 else if (*fmt == 'E')
643 for (j = 0; j < XVECLEN (x, i); j++)
644 replace_pseudos_in_call_usage (& XVECEXP (x, i, j), mem_mode, usage);
648 /* Global variables used by reload and its subroutines. */
650 /* Set during calculate_needs if an insn needs register elimination. */
651 static int something_needs_elimination;
652 /* Set during calculate_needs if an insn needs an operand changed. */
653 int something_needs_operands_changed;
655 /* Nonzero means we couldn't get enough spill regs. */
658 /* Main entry point for the reload pass.
660 FIRST is the first insn of the function being compiled.
662 GLOBAL nonzero means we were called from global_alloc
663 and should attempt to reallocate any pseudoregs that we
664 displace from hard regs we will use for reloads.
665 If GLOBAL is zero, we do not have enough information to do that,
666 so any pseudo reg that is spilled must go to the stack.
668 Return value is nonzero if reload failed
669 and we must not do any more for this function. */
672 reload (first, global)
678 struct elim_table *ep;
681 /* Make sure even insns with volatile mem refs are recognizable. */
686 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
688 /* Make sure that the last insn in the chain
689 is not something that needs reloading. */
690 emit_note (NULL, NOTE_INSN_DELETED);
692 /* Enable find_equiv_reg to distinguish insns made by reload. */
693 reload_first_uid = get_max_uid ();
695 #ifdef SECONDARY_MEMORY_NEEDED
696 /* Initialize the secondary memory table. */
697 clear_secondary_mem ();
700 /* We don't have a stack slot for any spill reg yet. */
701 memset ((char *) spill_stack_slot, 0, sizeof spill_stack_slot);
702 memset ((char *) spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
704 /* Initialize the save area information for caller-save, in case some
708 /* Compute which hard registers are now in use
709 as homes for pseudo registers.
710 This is done here rather than (eg) in global_alloc
711 because this point is reached even if not optimizing. */
712 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
715 /* A function that receives a nonlocal goto must save all call-saved
717 if (current_function_has_nonlocal_label)
718 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
719 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
720 regs_ever_live[i] = 1;
722 /* Find all the pseudo registers that didn't get hard regs
723 but do have known equivalent constants or memory slots.
724 These include parameters (known equivalent to parameter slots)
725 and cse'd or loop-moved constant memory addresses.
727 Record constant equivalents in reg_equiv_constant
728 so they will be substituted by find_reloads.
729 Record memory equivalents in reg_mem_equiv so they can
730 be substituted eventually by altering the REG-rtx's. */
732 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
733 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
734 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
735 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
736 reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int));
737 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
738 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
739 pseudo_forbidden_regs
740 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
742 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
744 CLEAR_HARD_REG_SET (bad_spill_regs_global);
746 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
747 Also find all paradoxical subregs and find largest such for each pseudo.
748 On machines with small register classes, record hard registers that
749 are used for user variables. These can never be used for spills.
750 Also look for a "constant" REG_SETJMP. This means that all
751 caller-saved registers must be marked live. */
753 num_eliminable_invariants = 0;
754 for (insn = first; insn; insn = NEXT_INSN (insn))
756 rtx set = single_set (insn);
758 /* We may introduce USEs that we want to remove at the end, so
759 we'll mark them with QImode. Make sure there are no
760 previously-marked insns left by say regmove. */
761 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
762 && GET_MODE (insn) != VOIDmode)
763 PUT_MODE (insn, VOIDmode);
765 if (GET_CODE (insn) == CALL_INSN
766 && find_reg_note (insn, REG_SETJMP, NULL))
767 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
768 if (! call_used_regs[i])
769 regs_ever_live[i] = 1;
771 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
773 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
775 #ifdef LEGITIMATE_PIC_OPERAND_P
776 && (! function_invariant_p (XEXP (note, 0))
778 /* A function invariant is often CONSTANT_P but may
779 include a register. We promise to only pass
780 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
781 || (CONSTANT_P (XEXP (note, 0))
782 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))))
786 rtx x = XEXP (note, 0);
787 i = REGNO (SET_DEST (set));
788 if (i > LAST_VIRTUAL_REGISTER)
790 /* It can happen that a REG_EQUIV note contains a MEM
791 that is not a legitimate memory operand. As later
792 stages of reload assume that all addresses found
793 in the reg_equiv_* arrays were originally legitimate,
794 we ignore such REG_EQUIV notes. */
795 if (memory_operand (x, VOIDmode))
797 /* Always unshare the equivalence, so we can
798 substitute into this insn without touching the
800 reg_equiv_memory_loc[i] = copy_rtx (x);
802 else if (function_invariant_p (x))
804 if (GET_CODE (x) == PLUS)
806 /* This is PLUS of frame pointer and a constant,
807 and might be shared. Unshare it. */
808 reg_equiv_constant[i] = copy_rtx (x);
809 num_eliminable_invariants++;
811 else if (x == frame_pointer_rtx
812 || x == arg_pointer_rtx)
814 reg_equiv_constant[i] = x;
815 num_eliminable_invariants++;
817 else if (LEGITIMATE_CONSTANT_P (x))
818 reg_equiv_constant[i] = x;
821 reg_equiv_memory_loc[i]
822 = force_const_mem (GET_MODE (SET_DEST (set)), x);
823 if (!reg_equiv_memory_loc[i])
830 /* If this register is being made equivalent to a MEM
831 and the MEM is not SET_SRC, the equivalencing insn
832 is one with the MEM as a SET_DEST and it occurs later.
833 So don't mark this insn now. */
834 if (GET_CODE (x) != MEM
835 || rtx_equal_p (SET_SRC (set), x))
837 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
842 /* If this insn is setting a MEM from a register equivalent to it,
843 this is the equivalencing insn. */
844 else if (set && GET_CODE (SET_DEST (set)) == MEM
845 && GET_CODE (SET_SRC (set)) == REG
846 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
847 && rtx_equal_p (SET_DEST (set),
848 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
849 reg_equiv_init[REGNO (SET_SRC (set))]
850 = gen_rtx_INSN_LIST (VOIDmode, insn,
851 reg_equiv_init[REGNO (SET_SRC (set))]);
854 scan_paradoxical_subregs (PATTERN (insn));
859 first_label_num = get_first_label_num ();
860 num_labels = max_label_num () - first_label_num;
862 /* Allocate the tables used to store offset information at labels. */
863 /* We used to use alloca here, but the size of what it would try to
864 allocate would occasionally cause it to exceed the stack limit and
865 cause a core dump. */
866 offsets_known_at = xmalloc (num_labels);
868 = (int (*)[NUM_ELIMINABLE_REGS])
869 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
871 /* Alter each pseudo-reg rtx to contain its hard reg number.
872 Assign stack slots to the pseudos that lack hard regs or equivalents.
873 Do not touch virtual registers. */
875 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
878 /* If we have some registers we think can be eliminated, scan all insns to
879 see if there is an insn that sets one of these registers to something
880 other than itself plus a constant. If so, the register cannot be
881 eliminated. Doing this scan here eliminates an extra pass through the
882 main reload loop in the most common case where register elimination
884 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
885 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
886 || GET_CODE (insn) == CALL_INSN)
887 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
889 maybe_fix_stack_asms ();
891 insns_need_reload = 0;
892 something_needs_elimination = 0;
894 /* Initialize to -1, which means take the first spill register. */
897 /* Spill any hard regs that we know we can't eliminate. */
898 CLEAR_HARD_REG_SET (used_spill_regs);
899 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
900 if (! ep->can_eliminate)
901 spill_hard_reg (ep->from, 1);
903 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
904 if (frame_pointer_needed)
905 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
907 finish_spills (global);
909 /* From now on, we may need to generate moves differently. We may also
910 allow modifications of insns which cause them to not be recognized.
911 Any such modifications will be cleaned up during reload itself. */
912 reload_in_progress = 1;
914 /* This loop scans the entire function each go-round
915 and repeats until one repetition spills no additional hard regs. */
918 int something_changed;
921 HOST_WIDE_INT starting_frame_size;
923 /* Round size of stack frame to stack_alignment_needed. This must be done
924 here because the stack size may be a part of the offset computation
925 for register elimination, and there might have been new stack slots
926 created in the last iteration of this loop. */
927 if (cfun->stack_alignment_needed)
928 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
930 starting_frame_size = get_frame_size ();
932 set_initial_elim_offsets ();
933 set_initial_label_offsets ();
935 /* For each pseudo register that has an equivalent location defined,
936 try to eliminate any eliminable registers (such as the frame pointer)
937 assuming initial offsets for the replacement register, which
940 If the resulting location is directly addressable, substitute
941 the MEM we just got directly for the old REG.
943 If it is not addressable but is a constant or the sum of a hard reg
944 and constant, it is probably not addressable because the constant is
945 out of range, in that case record the address; we will generate
946 hairy code to compute the address in a register each time it is
947 needed. Similarly if it is a hard register, but one that is not
948 valid as an address register.
950 If the location is not addressable, but does not have one of the
951 above forms, assign a stack slot. We have to do this to avoid the
952 potential of producing lots of reloads if, e.g., a location involves
953 a pseudo that didn't get a hard register and has an equivalent memory
954 location that also involves a pseudo that didn't get a hard register.
956 Perhaps at some point we will improve reload_when_needed handling
957 so this problem goes away. But that's very hairy. */
959 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
960 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
962 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
964 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
966 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
967 else if (CONSTANT_P (XEXP (x, 0))
968 || (GET_CODE (XEXP (x, 0)) == REG
969 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
970 || (GET_CODE (XEXP (x, 0)) == PLUS
971 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
972 && (REGNO (XEXP (XEXP (x, 0), 0))
973 < FIRST_PSEUDO_REGISTER)
974 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
975 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
978 /* Make a new stack slot. Then indicate that something
979 changed so we go back and recompute offsets for
980 eliminable registers because the allocation of memory
981 below might change some offset. reg_equiv_{mem,address}
982 will be set up for this pseudo on the next pass around
984 reg_equiv_memory_loc[i] = 0;
985 reg_equiv_init[i] = 0;
990 if (caller_save_needed)
993 /* If we allocated another stack slot, redo elimination bookkeeping. */
994 if (starting_frame_size != get_frame_size ())
997 if (caller_save_needed)
999 save_call_clobbered_regs ();
1000 /* That might have allocated new insn_chain structures. */
1001 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1004 calculate_needs_all_insns (global);
1006 CLEAR_REG_SET (&spilled_pseudos);
1009 something_changed = 0;
1011 /* If we allocated any new memory locations, make another pass
1012 since it might have changed elimination offsets. */
1013 if (starting_frame_size != get_frame_size ())
1014 something_changed = 1;
1017 HARD_REG_SET to_spill;
1018 CLEAR_HARD_REG_SET (to_spill);
1019 update_eliminables (&to_spill);
1020 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1021 if (TEST_HARD_REG_BIT (to_spill, i))
1023 spill_hard_reg (i, 1);
1026 /* Regardless of the state of spills, if we previously had
1027 a register that we thought we could eliminate, but now can
1028 not eliminate, we must run another pass.
1030 Consider pseudos which have an entry in reg_equiv_* which
1031 reference an eliminable register. We must make another pass
1032 to update reg_equiv_* so that we do not substitute in the
1033 old value from when we thought the elimination could be
1035 something_changed = 1;
1039 select_reload_regs ();
1043 if (insns_need_reload != 0 || did_spill)
1044 something_changed |= finish_spills (global);
1046 if (! something_changed)
1049 if (caller_save_needed)
1050 delete_caller_save_insns ();
1052 obstack_free (&reload_obstack, reload_firstobj);
1055 /* If global-alloc was run, notify it of any register eliminations we have
1058 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1059 if (ep->can_eliminate)
1060 mark_elimination (ep->from, ep->to);
1062 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1063 If that insn didn't set the register (i.e., it copied the register to
1064 memory), just delete that insn instead of the equivalencing insn plus
1065 anything now dead. If we call delete_dead_insn on that insn, we may
1066 delete the insn that actually sets the register if the register dies
1067 there and that is incorrect. */
1069 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1071 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1074 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1076 rtx equiv_insn = XEXP (list, 0);
1078 /* If we already deleted the insn or if it may trap, we can't
1079 delete it. The latter case shouldn't happen, but can
1080 if an insn has a variable address, gets a REG_EH_REGION
1081 note added to it, and then gets converted into an load
1082 from a constant address. */
1083 if (GET_CODE (equiv_insn) == NOTE
1084 || can_throw_internal (equiv_insn))
1086 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1087 delete_dead_insn (equiv_insn);
1090 PUT_CODE (equiv_insn, NOTE);
1091 NOTE_SOURCE_FILE (equiv_insn) = 0;
1092 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1098 /* Use the reload registers where necessary
1099 by generating move instructions to move the must-be-register
1100 values into or out of the reload registers. */
1102 if (insns_need_reload != 0 || something_needs_elimination
1103 || something_needs_operands_changed)
1105 HOST_WIDE_INT old_frame_size = get_frame_size ();
1107 reload_as_needed (global);
1109 if (old_frame_size != get_frame_size ())
1113 verify_initial_elim_offsets ();
1116 /* If we were able to eliminate the frame pointer, show that it is no
1117 longer live at the start of any basic block. If it ls live by
1118 virtue of being in a pseudo, that pseudo will be marked live
1119 and hence the frame pointer will be known to be live via that
1122 if (! frame_pointer_needed)
1124 CLEAR_REGNO_REG_SET (bb->global_live_at_start,
1125 HARD_FRAME_POINTER_REGNUM);
1127 /* Come here (with failure set nonzero) if we can't get enough spill regs
1128 and we decide not to abort about it. */
1131 CLEAR_REG_SET (&spilled_pseudos);
1132 reload_in_progress = 0;
1134 /* Now eliminate all pseudo regs by modifying them into
1135 their equivalent memory references.
1136 The REG-rtx's for the pseudos are modified in place,
1137 so all insns that used to refer to them now refer to memory.
1139 For a reg that has a reg_equiv_address, all those insns
1140 were changed by reloading so that no insns refer to it any longer;
1141 but the DECL_RTL of a variable decl may refer to it,
1142 and if so this causes the debugging info to mention the variable. */
1144 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1148 if (reg_equiv_mem[i])
1149 addr = XEXP (reg_equiv_mem[i], 0);
1151 if (reg_equiv_address[i])
1152 addr = reg_equiv_address[i];
1156 if (reg_renumber[i] < 0)
1158 rtx reg = regno_reg_rtx[i];
1160 REG_USERVAR_P (reg) = 0;
1161 PUT_CODE (reg, MEM);
1162 XEXP (reg, 0) = addr;
1163 if (reg_equiv_memory_loc[i])
1164 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1167 RTX_UNCHANGING_P (reg) = MEM_IN_STRUCT_P (reg)
1168 = MEM_SCALAR_P (reg) = 0;
1169 MEM_ATTRS (reg) = 0;
1172 else if (reg_equiv_mem[i])
1173 XEXP (reg_equiv_mem[i], 0) = addr;
1177 /* We must set reload_completed now since the cleanup_subreg_operands call
1178 below will re-recognize each insn and reload may have generated insns
1179 which are only valid during and after reload. */
1180 reload_completed = 1;
1182 /* Make a pass over all the insns and delete all USEs which we inserted
1183 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1184 notes. Delete all CLOBBER insns, except those that refer to the return
1185 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1186 from misarranging variable-array code, and simplify (subreg (reg))
1187 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1188 are no longer useful or accurate. Strip and regenerate REG_INC notes
1189 that may have been moved around. */
1191 for (insn = first; insn; insn = NEXT_INSN (insn))
1196 if (GET_CODE (insn) == CALL_INSN)
1197 replace_pseudos_in_call_usage (& CALL_INSN_FUNCTION_USAGE (insn),
1199 CALL_INSN_FUNCTION_USAGE (insn));
1201 if ((GET_CODE (PATTERN (insn)) == USE
1202 /* We mark with QImode USEs introduced by reload itself. */
1203 && (GET_MODE (insn) == QImode
1204 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1205 || (GET_CODE (PATTERN (insn)) == CLOBBER
1206 && (GET_CODE (XEXP (PATTERN (insn), 0)) != MEM
1207 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1208 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1209 && XEXP (XEXP (PATTERN (insn), 0), 0)
1210 != stack_pointer_rtx))
1211 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1212 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1218 pnote = ®_NOTES (insn);
1221 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1222 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1223 || REG_NOTE_KIND (*pnote) == REG_INC
1224 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1225 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1226 *pnote = XEXP (*pnote, 1);
1228 pnote = &XEXP (*pnote, 1);
1232 add_auto_inc_notes (insn, PATTERN (insn));
1235 /* And simplify (subreg (reg)) if it appears as an operand. */
1236 cleanup_subreg_operands (insn);
1239 /* If we are doing stack checking, give a warning if this function's
1240 frame size is larger than we expect. */
1241 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1243 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1244 static int verbose_warned = 0;
1246 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1247 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1248 size += UNITS_PER_WORD;
1250 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1252 warning ("frame size too large for reliable stack checking");
1253 if (! verbose_warned)
1255 warning ("try reducing the number of local variables");
1261 /* Indicate that we no longer have known memory locations or constants. */
1262 if (reg_equiv_constant)
1263 free (reg_equiv_constant);
1264 reg_equiv_constant = 0;
1265 if (reg_equiv_memory_loc)
1266 free (reg_equiv_memory_loc);
1267 reg_equiv_memory_loc = 0;
1269 if (offsets_known_at)
1270 free (offsets_known_at);
1274 free (reg_equiv_mem);
1275 free (reg_equiv_init);
1276 free (reg_equiv_address);
1277 free (reg_max_ref_width);
1278 free (reg_old_renumber);
1279 free (pseudo_previous_regs);
1280 free (pseudo_forbidden_regs);
1282 CLEAR_HARD_REG_SET (used_spill_regs);
1283 for (i = 0; i < n_spills; i++)
1284 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1286 /* Free all the insn_chain structures at once. */
1287 obstack_free (&reload_obstack, reload_startobj);
1288 unused_insn_chains = 0;
1289 fixup_abnormal_edges ();
1291 /* Replacing pseudos with their memory equivalents might have
1292 created shared rtx. Subsequent passes would get confused
1293 by this, so unshare everything here. */
1294 unshare_all_rtl_again (first);
1299 /* Yet another special case. Unfortunately, reg-stack forces people to
1300 write incorrect clobbers in asm statements. These clobbers must not
1301 cause the register to appear in bad_spill_regs, otherwise we'll call
1302 fatal_insn later. We clear the corresponding regnos in the live
1303 register sets to avoid this.
1304 The whole thing is rather sick, I'm afraid. */
1307 maybe_fix_stack_asms ()
1310 const char *constraints[MAX_RECOG_OPERANDS];
1311 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1312 struct insn_chain *chain;
1314 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1317 HARD_REG_SET clobbered, allowed;
1320 if (! INSN_P (chain->insn)
1321 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1323 pat = PATTERN (chain->insn);
1324 if (GET_CODE (pat) != PARALLEL)
1327 CLEAR_HARD_REG_SET (clobbered);
1328 CLEAR_HARD_REG_SET (allowed);
1330 /* First, make a mask of all stack regs that are clobbered. */
1331 for (i = 0; i < XVECLEN (pat, 0); i++)
1333 rtx t = XVECEXP (pat, 0, i);
1334 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1335 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1338 /* Get the operand values and constraints out of the insn. */
1339 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1340 constraints, operand_mode);
1342 /* For every operand, see what registers are allowed. */
1343 for (i = 0; i < noperands; i++)
1345 const char *p = constraints[i];
1346 /* For every alternative, we compute the class of registers allowed
1347 for reloading in CLS, and merge its contents into the reg set
1349 int cls = (int) NO_REGS;
1355 if (c == '\0' || c == ',' || c == '#')
1357 /* End of one alternative - mark the regs in the current
1358 class, and reset the class. */
1359 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1365 } while (c != '\0' && c != ',');
1373 case '=': case '+': case '*': case '%': case '?': case '!':
1374 case '0': case '1': case '2': case '3': case '4': case 'm':
1375 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1376 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1377 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1382 cls = (int) reg_class_subunion[cls]
1383 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1388 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1392 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1393 cls = (int) reg_class_subunion[cls]
1394 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1396 cls = (int) reg_class_subunion[cls]
1397 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1399 p += CONSTRAINT_LEN (c, p);
1402 /* Those of the registers which are clobbered, but allowed by the
1403 constraints, must be usable as reload registers. So clear them
1404 out of the life information. */
1405 AND_HARD_REG_SET (allowed, clobbered);
1406 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1407 if (TEST_HARD_REG_BIT (allowed, i))
1409 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1410 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1417 /* Copy the global variables n_reloads and rld into the corresponding elts
1420 copy_reloads (chain)
1421 struct insn_chain *chain;
1423 chain->n_reloads = n_reloads;
1425 = (struct reload *) obstack_alloc (&reload_obstack,
1426 n_reloads * sizeof (struct reload));
1427 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1428 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1431 /* Walk the chain of insns, and determine for each whether it needs reloads
1432 and/or eliminations. Build the corresponding insns_need_reload list, and
1433 set something_needs_elimination as appropriate. */
1435 calculate_needs_all_insns (global)
1438 struct insn_chain **pprev_reload = &insns_need_reload;
1439 struct insn_chain *chain, *next = 0;
1441 something_needs_elimination = 0;
1443 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1444 for (chain = reload_insn_chain; chain != 0; chain = next)
1446 rtx insn = chain->insn;
1450 /* Clear out the shortcuts. */
1451 chain->n_reloads = 0;
1452 chain->need_elim = 0;
1453 chain->need_reload = 0;
1454 chain->need_operand_change = 0;
1456 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1457 include REG_LABEL), we need to see what effects this has on the
1458 known offsets at labels. */
1460 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1461 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1462 set_label_offsets (insn, insn, 0);
1466 rtx old_body = PATTERN (insn);
1467 int old_code = INSN_CODE (insn);
1468 rtx old_notes = REG_NOTES (insn);
1469 int did_elimination = 0;
1470 int operands_changed = 0;
1471 rtx set = single_set (insn);
1473 /* Skip insns that only set an equivalence. */
1474 if (set && GET_CODE (SET_DEST (set)) == REG
1475 && reg_renumber[REGNO (SET_DEST (set))] < 0
1476 && reg_equiv_constant[REGNO (SET_DEST (set))])
1479 /* If needed, eliminate any eliminable registers. */
1480 if (num_eliminable || num_eliminable_invariants)
1481 did_elimination = eliminate_regs_in_insn (insn, 0);
1483 /* Analyze the instruction. */
1484 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1485 global, spill_reg_order);
1487 /* If a no-op set needs more than one reload, this is likely
1488 to be something that needs input address reloads. We
1489 can't get rid of this cleanly later, and it is of no use
1490 anyway, so discard it now.
1491 We only do this when expensive_optimizations is enabled,
1492 since this complements reload inheritance / output
1493 reload deletion, and it can make debugging harder. */
1494 if (flag_expensive_optimizations && n_reloads > 1)
1496 rtx set = single_set (insn);
1498 && SET_SRC (set) == SET_DEST (set)
1499 && GET_CODE (SET_SRC (set)) == REG
1500 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1503 /* Delete it from the reload chain. */
1505 chain->prev->next = next;
1507 reload_insn_chain = next;
1509 next->prev = chain->prev;
1510 chain->next = unused_insn_chains;
1511 unused_insn_chains = chain;
1516 update_eliminable_offsets ();
1518 /* Remember for later shortcuts which insns had any reloads or
1519 register eliminations. */
1520 chain->need_elim = did_elimination;
1521 chain->need_reload = n_reloads > 0;
1522 chain->need_operand_change = operands_changed;
1524 /* Discard any register replacements done. */
1525 if (did_elimination)
1527 obstack_free (&reload_obstack, reload_insn_firstobj);
1528 PATTERN (insn) = old_body;
1529 INSN_CODE (insn) = old_code;
1530 REG_NOTES (insn) = old_notes;
1531 something_needs_elimination = 1;
1534 something_needs_operands_changed |= operands_changed;
1538 copy_reloads (chain);
1539 *pprev_reload = chain;
1540 pprev_reload = &chain->next_need_reload;
1547 /* Comparison function for qsort to decide which of two reloads
1548 should be handled first. *P1 and *P2 are the reload numbers. */
1551 reload_reg_class_lower (r1p, r2p)
1555 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1558 /* Consider required reloads before optional ones. */
1559 t = rld[r1].optional - rld[r2].optional;
1563 /* Count all solitary classes before non-solitary ones. */
1564 t = ((reg_class_size[(int) rld[r2].class] == 1)
1565 - (reg_class_size[(int) rld[r1].class] == 1));
1569 /* Aside from solitaires, consider all multi-reg groups first. */
1570 t = rld[r2].nregs - rld[r1].nregs;
1574 /* Consider reloads in order of increasing reg-class number. */
1575 t = (int) rld[r1].class - (int) rld[r2].class;
1579 /* If reloads are equally urgent, sort by reload number,
1580 so that the results of qsort leave nothing to chance. */
1584 /* The cost of spilling each hard reg. */
1585 static int spill_cost[FIRST_PSEUDO_REGISTER];
1587 /* When spilling multiple hard registers, we use SPILL_COST for the first
1588 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1589 only the first hard reg for a multi-reg pseudo. */
1590 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1592 /* Update the spill cost arrays, considering that pseudo REG is live. */
1598 int freq = REG_FREQ (reg);
1599 int r = reg_renumber[reg];
1602 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1603 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1606 SET_REGNO_REG_SET (&pseudos_counted, reg);
1611 spill_add_cost[r] += freq;
1613 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1615 spill_cost[r + nregs] += freq;
1618 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1619 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1622 order_regs_for_reload (chain)
1623 struct insn_chain *chain;
1626 HARD_REG_SET used_by_pseudos;
1627 HARD_REG_SET used_by_pseudos2;
1629 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1631 memset (spill_cost, 0, sizeof spill_cost);
1632 memset (spill_add_cost, 0, sizeof spill_add_cost);
1634 /* Count number of uses of each hard reg by pseudo regs allocated to it
1635 and then order them by decreasing use. First exclude hard registers
1636 that are live in or across this insn. */
1638 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1639 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1640 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1641 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1643 /* Now find out which pseudos are allocated to it, and update
1645 CLEAR_REG_SET (&pseudos_counted);
1647 EXECUTE_IF_SET_IN_REG_SET
1648 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1652 EXECUTE_IF_SET_IN_REG_SET
1653 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1657 CLEAR_REG_SET (&pseudos_counted);
1660 /* Vector of reload-numbers showing the order in which the reloads should
1662 static short reload_order[MAX_RELOADS];
1664 /* This is used to keep track of the spill regs used in one insn. */
1665 static HARD_REG_SET used_spill_regs_local;
1667 /* We decided to spill hard register SPILLED, which has a size of
1668 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1669 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1670 update SPILL_COST/SPILL_ADD_COST. */
1673 count_spilled_pseudo (spilled, spilled_nregs, reg)
1674 int spilled, spilled_nregs, reg;
1676 int r = reg_renumber[reg];
1677 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1679 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1680 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1683 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1685 spill_add_cost[r] -= REG_FREQ (reg);
1687 spill_cost[r + nregs] -= REG_FREQ (reg);
1690 /* Find reload register to use for reload number ORDER. */
1693 find_reg (chain, order)
1694 struct insn_chain *chain;
1697 int rnum = reload_order[order];
1698 struct reload *rl = rld + rnum;
1699 int best_cost = INT_MAX;
1703 HARD_REG_SET not_usable;
1704 HARD_REG_SET used_by_other_reload;
1706 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1707 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1708 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1710 CLEAR_HARD_REG_SET (used_by_other_reload);
1711 for (k = 0; k < order; k++)
1713 int other = reload_order[k];
1715 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1716 for (j = 0; j < rld[other].nregs; j++)
1717 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1720 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1722 unsigned int regno = i;
1724 if (! TEST_HARD_REG_BIT (not_usable, regno)
1725 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1726 && HARD_REGNO_MODE_OK (regno, rl->mode))
1728 int this_cost = spill_cost[regno];
1730 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1732 for (j = 1; j < this_nregs; j++)
1734 this_cost += spill_add_cost[regno + j];
1735 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1736 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1741 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1743 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1745 if (this_cost < best_cost
1746 /* Among registers with equal cost, prefer caller-saved ones, or
1747 use REG_ALLOC_ORDER if it is defined. */
1748 || (this_cost == best_cost
1749 #ifdef REG_ALLOC_ORDER
1750 && (inv_reg_alloc_order[regno]
1751 < inv_reg_alloc_order[best_reg])
1753 && call_used_regs[regno]
1754 && ! call_used_regs[best_reg]
1759 best_cost = this_cost;
1767 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1769 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1770 rl->regno = best_reg;
1772 EXECUTE_IF_SET_IN_REG_SET
1773 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1775 count_spilled_pseudo (best_reg, rl->nregs, j);
1778 EXECUTE_IF_SET_IN_REG_SET
1779 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1781 count_spilled_pseudo (best_reg, rl->nregs, j);
1784 for (i = 0; i < rl->nregs; i++)
1786 if (spill_cost[best_reg + i] != 0
1787 || spill_add_cost[best_reg + i] != 0)
1789 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1794 /* Find more reload regs to satisfy the remaining need of an insn, which
1796 Do it by ascending class number, since otherwise a reg
1797 might be spilled for a big class and might fail to count
1798 for a smaller class even though it belongs to that class. */
1801 find_reload_regs (chain)
1802 struct insn_chain *chain;
1806 /* In order to be certain of getting the registers we need,
1807 we must sort the reloads into order of increasing register class.
1808 Then our grabbing of reload registers will parallel the process
1809 that provided the reload registers. */
1810 for (i = 0; i < chain->n_reloads; i++)
1812 /* Show whether this reload already has a hard reg. */
1813 if (chain->rld[i].reg_rtx)
1815 int regno = REGNO (chain->rld[i].reg_rtx);
1816 chain->rld[i].regno = regno;
1818 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1821 chain->rld[i].regno = -1;
1822 reload_order[i] = i;
1825 n_reloads = chain->n_reloads;
1826 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1828 CLEAR_HARD_REG_SET (used_spill_regs_local);
1831 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1833 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1835 /* Compute the order of preference for hard registers to spill. */
1837 order_regs_for_reload (chain);
1839 for (i = 0; i < n_reloads; i++)
1841 int r = reload_order[i];
1843 /* Ignore reloads that got marked inoperative. */
1844 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1845 && ! rld[r].optional
1846 && rld[r].regno == -1)
1847 if (! find_reg (chain, i))
1849 spill_failure (chain->insn, rld[r].class);
1855 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1856 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1858 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1862 select_reload_regs ()
1864 struct insn_chain *chain;
1866 /* Try to satisfy the needs for each insn. */
1867 for (chain = insns_need_reload; chain != 0;
1868 chain = chain->next_need_reload)
1869 find_reload_regs (chain);
1872 /* Delete all insns that were inserted by emit_caller_save_insns during
1875 delete_caller_save_insns ()
1877 struct insn_chain *c = reload_insn_chain;
1881 while (c != 0 && c->is_caller_save_insn)
1883 struct insn_chain *next = c->next;
1886 if (c == reload_insn_chain)
1887 reload_insn_chain = next;
1891 next->prev = c->prev;
1893 c->prev->next = next;
1894 c->next = unused_insn_chains;
1895 unused_insn_chains = c;
1903 /* Handle the failure to find a register to spill.
1904 INSN should be one of the insns which needed this particular spill reg. */
1907 spill_failure (insn, class)
1909 enum reg_class class;
1911 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1912 if (asm_noperands (PATTERN (insn)) >= 0)
1913 error_for_asm (insn, "can't find a register in class `%s' while reloading `asm'",
1914 reg_class_names[class]);
1917 error ("unable to find a register to spill in class `%s'",
1918 reg_class_names[class]);
1919 fatal_insn ("this is the insn:", insn);
1923 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1924 data that is dead in INSN. */
1927 delete_dead_insn (insn)
1930 rtx prev = prev_real_insn (insn);
1933 /* If the previous insn sets a register that dies in our insn, delete it
1935 if (prev && GET_CODE (PATTERN (prev)) == SET
1936 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1937 && reg_mentioned_p (prev_dest, PATTERN (insn))
1938 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1939 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1940 delete_dead_insn (prev);
1942 PUT_CODE (insn, NOTE);
1943 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1944 NOTE_SOURCE_FILE (insn) = 0;
1947 /* Modify the home of pseudo-reg I.
1948 The new home is present in reg_renumber[I].
1950 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1951 or it may be -1, meaning there is none or it is not relevant.
1952 This is used so that all pseudos spilled from a given hard reg
1953 can share one stack slot. */
1956 alter_reg (i, from_reg)
1960 /* When outputting an inline function, this can happen
1961 for a reg that isn't actually used. */
1962 if (regno_reg_rtx[i] == 0)
1965 /* If the reg got changed to a MEM at rtl-generation time,
1967 if (GET_CODE (regno_reg_rtx[i]) != REG)
1970 /* Modify the reg-rtx to contain the new hard reg
1971 number or else to contain its pseudo reg number. */
1972 REGNO (regno_reg_rtx[i])
1973 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1975 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1976 allocate a stack slot for it. */
1978 if (reg_renumber[i] < 0
1979 && REG_N_REFS (i) > 0
1980 && reg_equiv_constant[i] == 0
1981 && reg_equiv_memory_loc[i] == 0)
1984 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1985 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1988 /* Each pseudo reg has an inherent size which comes from its own mode,
1989 and a total size which provides room for paradoxical subregs
1990 which refer to the pseudo reg in wider modes.
1992 We can use a slot already allocated if it provides both
1993 enough inherent space and enough total space.
1994 Otherwise, we allocate a new slot, making sure that it has no less
1995 inherent space, and no less total space, then the previous slot. */
1998 /* No known place to spill from => no slot to reuse. */
1999 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
2000 inherent_size == total_size ? 0 : -1);
2001 if (BYTES_BIG_ENDIAN)
2002 /* Cancel the big-endian correction done in assign_stack_local.
2003 Get the address of the beginning of the slot.
2004 This is so we can do a big-endian correction unconditionally
2006 adjust = inherent_size - total_size;
2008 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2010 /* Nothing can alias this slot except this pseudo. */
2011 set_mem_alias_set (x, new_alias_set ());
2014 /* Reuse a stack slot if possible. */
2015 else if (spill_stack_slot[from_reg] != 0
2016 && spill_stack_slot_width[from_reg] >= total_size
2017 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2019 x = spill_stack_slot[from_reg];
2021 /* Allocate a bigger slot. */
2024 /* Compute maximum size needed, both for inherent size
2025 and for total size. */
2026 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2029 if (spill_stack_slot[from_reg])
2031 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2033 mode = GET_MODE (spill_stack_slot[from_reg]);
2034 if (spill_stack_slot_width[from_reg] > total_size)
2035 total_size = spill_stack_slot_width[from_reg];
2038 /* Make a slot with that size. */
2039 x = assign_stack_local (mode, total_size,
2040 inherent_size == total_size ? 0 : -1);
2043 /* All pseudos mapped to this slot can alias each other. */
2044 if (spill_stack_slot[from_reg])
2045 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2047 set_mem_alias_set (x, new_alias_set ());
2049 if (BYTES_BIG_ENDIAN)
2051 /* Cancel the big-endian correction done in assign_stack_local.
2052 Get the address of the beginning of the slot.
2053 This is so we can do a big-endian correction unconditionally
2055 adjust = GET_MODE_SIZE (mode) - total_size;
2058 = adjust_address_nv (x, mode_for_size (total_size
2064 spill_stack_slot[from_reg] = stack_slot;
2065 spill_stack_slot_width[from_reg] = total_size;
2068 /* On a big endian machine, the "address" of the slot
2069 is the address of the low part that fits its inherent mode. */
2070 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2071 adjust += (total_size - inherent_size);
2073 /* If we have any adjustment to make, or if the stack slot is the
2074 wrong mode, make a new stack slot. */
2075 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2077 /* If we have a decl for the original register, set it for the
2078 memory. If this is a shared MEM, make a copy. */
2079 if (REG_EXPR (regno_reg_rtx[i])
2080 && TREE_CODE_CLASS (TREE_CODE (REG_EXPR (regno_reg_rtx[i]))) == 'd')
2082 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2084 /* We can do this only for the DECLs home pseudo, not for
2085 any copies of it, since otherwise when the stack slot
2086 is reused, nonoverlapping_memrefs_p might think they
2088 if (decl && GET_CODE (decl) == REG && REGNO (decl) == (unsigned) i)
2090 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2093 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2097 /* Save the stack slot for later. */
2098 reg_equiv_memory_loc[i] = x;
2102 /* Mark the slots in regs_ever_live for the hard regs
2103 used by pseudo-reg number REGNO. */
2106 mark_home_live (regno)
2111 i = reg_renumber[regno];
2114 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2116 regs_ever_live[i++] = 1;
2119 /* This function handles the tracking of elimination offsets around branches.
2121 X is a piece of RTL being scanned.
2123 INSN is the insn that it came from, if any.
2125 INITIAL_P is nonzero if we are to set the offset to be the initial
2126 offset and zero if we are setting the offset of the label to be the
2130 set_label_offsets (x, insn, initial_p)
2135 enum rtx_code code = GET_CODE (x);
2138 struct elim_table *p;
2143 if (LABEL_REF_NONLOCAL_P (x))
2148 /* ... fall through ... */
2151 /* If we know nothing about this label, set the desired offsets. Note
2152 that this sets the offset at a label to be the offset before a label
2153 if we don't know anything about the label. This is not correct for
2154 the label after a BARRIER, but is the best guess we can make. If
2155 we guessed wrong, we will suppress an elimination that might have
2156 been possible had we been able to guess correctly. */
2158 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2160 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2161 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2162 = (initial_p ? reg_eliminate[i].initial_offset
2163 : reg_eliminate[i].offset);
2164 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2167 /* Otherwise, if this is the definition of a label and it is
2168 preceded by a BARRIER, set our offsets to the known offset of
2172 && (tem = prev_nonnote_insn (insn)) != 0
2173 && GET_CODE (tem) == BARRIER)
2174 set_offsets_for_label (insn);
2176 /* If neither of the above cases is true, compare each offset
2177 with those previously recorded and suppress any eliminations
2178 where the offsets disagree. */
2180 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2181 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2182 != (initial_p ? reg_eliminate[i].initial_offset
2183 : reg_eliminate[i].offset))
2184 reg_eliminate[i].can_eliminate = 0;
2189 set_label_offsets (PATTERN (insn), insn, initial_p);
2191 /* ... fall through ... */
2195 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2196 and hence must have all eliminations at their initial offsets. */
2197 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2198 if (REG_NOTE_KIND (tem) == REG_LABEL)
2199 set_label_offsets (XEXP (tem, 0), insn, 1);
2205 /* Each of the labels in the parallel or address vector must be
2206 at their initial offsets. We want the first field for PARALLEL
2207 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2209 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2210 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2215 /* We only care about setting PC. If the source is not RETURN,
2216 IF_THEN_ELSE, or a label, disable any eliminations not at
2217 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2218 isn't one of those possibilities. For branches to a label,
2219 call ourselves recursively.
2221 Note that this can disable elimination unnecessarily when we have
2222 a non-local goto since it will look like a non-constant jump to
2223 someplace in the current function. This isn't a significant
2224 problem since such jumps will normally be when all elimination
2225 pairs are back to their initial offsets. */
2227 if (SET_DEST (x) != pc_rtx)
2230 switch (GET_CODE (SET_SRC (x)))
2237 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2241 tem = XEXP (SET_SRC (x), 1);
2242 if (GET_CODE (tem) == LABEL_REF)
2243 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2244 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2247 tem = XEXP (SET_SRC (x), 2);
2248 if (GET_CODE (tem) == LABEL_REF)
2249 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2250 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2258 /* If we reach here, all eliminations must be at their initial
2259 offset because we are doing a jump to a variable address. */
2260 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2261 if (p->offset != p->initial_offset)
2262 p->can_eliminate = 0;
2270 /* Scan X and replace any eliminable registers (such as fp) with a
2271 replacement (such as sp), plus an offset.
2273 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2274 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2275 MEM, we are allowed to replace a sum of a register and the constant zero
2276 with the register, which we cannot do outside a MEM. In addition, we need
2277 to record the fact that a register is referenced outside a MEM.
2279 If INSN is an insn, it is the insn containing X. If we replace a REG
2280 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2281 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2282 the REG is being modified.
2284 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2285 That's used when we eliminate in expressions stored in notes.
2286 This means, do not set ref_outside_mem even if the reference
2289 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2290 replacements done assuming all offsets are at their initial values. If
2291 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2292 encounter, return the actual location so that find_reloads will do
2293 the proper thing. */
2296 eliminate_regs (x, mem_mode, insn)
2298 enum machine_mode mem_mode;
2301 enum rtx_code code = GET_CODE (x);
2302 struct elim_table *ep;
2309 if (! current_function_decl)
2329 /* This is only for the benefit of the debugging backends, which call
2330 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2331 removed after CSE. */
2332 new = eliminate_regs (XEXP (x, 0), 0, insn);
2333 if (GET_CODE (new) == MEM)
2334 return XEXP (new, 0);
2340 /* First handle the case where we encounter a bare register that
2341 is eliminable. Replace it with a PLUS. */
2342 if (regno < FIRST_PSEUDO_REGISTER)
2344 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2346 if (ep->from_rtx == x && ep->can_eliminate)
2347 return plus_constant (ep->to_rtx, ep->previous_offset);
2350 else if (reg_renumber && reg_renumber[regno] < 0
2351 && reg_equiv_constant && reg_equiv_constant[regno]
2352 && ! CONSTANT_P (reg_equiv_constant[regno]))
2353 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2357 /* You might think handling MINUS in a manner similar to PLUS is a
2358 good idea. It is not. It has been tried multiple times and every
2359 time the change has had to have been reverted.
2361 Other parts of reload know a PLUS is special (gen_reload for example)
2362 and require special code to handle code a reloaded PLUS operand.
2364 Also consider backends where the flags register is clobbered by a
2365 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2366 lea instruction comes to mind). If we try to reload a MINUS, we
2367 may kill the flags register that was holding a useful value.
2369 So, please before trying to handle MINUS, consider reload as a
2370 whole instead of this little section as well as the backend issues. */
2372 /* If this is the sum of an eliminable register and a constant, rework
2374 if (GET_CODE (XEXP (x, 0)) == REG
2375 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2376 && CONSTANT_P (XEXP (x, 1)))
2378 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2380 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2382 /* The only time we want to replace a PLUS with a REG (this
2383 occurs when the constant operand of the PLUS is the negative
2384 of the offset) is when we are inside a MEM. We won't want
2385 to do so at other times because that would change the
2386 structure of the insn in a way that reload can't handle.
2387 We special-case the commonest situation in
2388 eliminate_regs_in_insn, so just replace a PLUS with a
2389 PLUS here, unless inside a MEM. */
2390 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2391 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2394 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2395 plus_constant (XEXP (x, 1),
2396 ep->previous_offset));
2399 /* If the register is not eliminable, we are done since the other
2400 operand is a constant. */
2404 /* If this is part of an address, we want to bring any constant to the
2405 outermost PLUS. We will do this by doing register replacement in
2406 our operands and seeing if a constant shows up in one of them.
2408 Note that there is no risk of modifying the structure of the insn,
2409 since we only get called for its operands, thus we are either
2410 modifying the address inside a MEM, or something like an address
2411 operand of a load-address insn. */
2414 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2415 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2417 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2419 /* If one side is a PLUS and the other side is a pseudo that
2420 didn't get a hard register but has a reg_equiv_constant,
2421 we must replace the constant here since it may no longer
2422 be in the position of any operand. */
2423 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2424 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2425 && reg_renumber[REGNO (new1)] < 0
2426 && reg_equiv_constant != 0
2427 && reg_equiv_constant[REGNO (new1)] != 0)
2428 new1 = reg_equiv_constant[REGNO (new1)];
2429 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2430 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2431 && reg_renumber[REGNO (new0)] < 0
2432 && reg_equiv_constant[REGNO (new0)] != 0)
2433 new0 = reg_equiv_constant[REGNO (new0)];
2435 new = form_sum (new0, new1);
2437 /* As above, if we are not inside a MEM we do not want to
2438 turn a PLUS into something else. We might try to do so here
2439 for an addition of 0 if we aren't optimizing. */
2440 if (! mem_mode && GET_CODE (new) != PLUS)
2441 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2449 /* If this is the product of an eliminable register and a
2450 constant, apply the distribute law and move the constant out
2451 so that we have (plus (mult ..) ..). This is needed in order
2452 to keep load-address insns valid. This case is pathological.
2453 We ignore the possibility of overflow here. */
2454 if (GET_CODE (XEXP (x, 0)) == REG
2455 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2456 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2457 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2459 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2462 /* Refs inside notes don't count for this purpose. */
2463 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2464 || GET_CODE (insn) == INSN_LIST)))
2465 ep->ref_outside_mem = 1;
2468 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2469 ep->previous_offset * INTVAL (XEXP (x, 1)));
2472 /* ... fall through ... */
2476 /* See comments before PLUS about handling MINUS. */
2478 case DIV: case UDIV:
2479 case MOD: case UMOD:
2480 case AND: case IOR: case XOR:
2481 case ROTATERT: case ROTATE:
2482 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2484 case GE: case GT: case GEU: case GTU:
2485 case LE: case LT: case LEU: case LTU:
2487 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2489 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2491 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2492 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2497 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2500 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2501 if (new != XEXP (x, 0))
2503 /* If this is a REG_DEAD note, it is not valid anymore.
2504 Using the eliminated version could result in creating a
2505 REG_DEAD note for the stack or frame pointer. */
2506 if (GET_MODE (x) == REG_DEAD)
2508 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2511 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2515 /* ... fall through ... */
2518 /* Now do eliminations in the rest of the chain. If this was
2519 an EXPR_LIST, this might result in allocating more memory than is
2520 strictly needed, but it simplifies the code. */
2523 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2524 if (new != XEXP (x, 1))
2526 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2534 case STRICT_LOW_PART:
2536 case SIGN_EXTEND: case ZERO_EXTEND:
2537 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2538 case FLOAT: case FIX:
2539 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2547 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2548 if (new != XEXP (x, 0))
2549 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2553 /* Similar to above processing, but preserve SUBREG_BYTE.
2554 Convert (subreg (mem)) to (mem) if not paradoxical.
2555 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2556 pseudo didn't get a hard reg, we must replace this with the
2557 eliminated version of the memory location because push_reloads
2558 may do the replacement in certain circumstances. */
2559 if (GET_CODE (SUBREG_REG (x)) == REG
2560 && (GET_MODE_SIZE (GET_MODE (x))
2561 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2562 && reg_equiv_memory_loc != 0
2563 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2565 new = SUBREG_REG (x);
2568 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2570 if (new != SUBREG_REG (x))
2572 int x_size = GET_MODE_SIZE (GET_MODE (x));
2573 int new_size = GET_MODE_SIZE (GET_MODE (new));
2575 if (GET_CODE (new) == MEM
2576 && ((x_size < new_size
2577 #ifdef WORD_REGISTER_OPERATIONS
2578 /* On these machines, combine can create rtl of the form
2579 (set (subreg:m1 (reg:m2 R) 0) ...)
2580 where m1 < m2, and expects something interesting to
2581 happen to the entire word. Moreover, it will use the
2582 (reg:m2 R) later, expecting all bits to be preserved.
2583 So if the number of words is the same, preserve the
2584 subreg so that push_reloads can see it. */
2585 && ! ((x_size - 1) / UNITS_PER_WORD
2586 == (new_size -1 ) / UNITS_PER_WORD)
2589 || x_size == new_size)
2591 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2593 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2599 /* This is only for the benefit of the debugging backends, which call
2600 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2601 removed after CSE. */
2602 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2603 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2605 /* Our only special processing is to pass the mode of the MEM to our
2606 recursive call and copy the flags. While we are here, handle this
2607 case more efficiently. */
2609 replace_equiv_address_nv (x,
2610 eliminate_regs (XEXP (x, 0),
2611 GET_MODE (x), insn));
2614 /* Handle insn_list USE that a call to a pure function may generate. */
2615 new = eliminate_regs (XEXP (x, 0), 0, insn);
2616 if (new != XEXP (x, 0))
2617 return gen_rtx_USE (GET_MODE (x), new);
2629 /* Process each of our operands recursively. If any have changed, make a
2631 fmt = GET_RTX_FORMAT (code);
2632 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2636 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2637 if (new != XEXP (x, i) && ! copied)
2639 rtx new_x = rtx_alloc (code);
2641 (sizeof (*new_x) - sizeof (new_x->fld)
2642 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2648 else if (*fmt == 'E')
2651 for (j = 0; j < XVECLEN (x, i); j++)
2653 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2654 if (new != XVECEXP (x, i, j) && ! copied_vec)
2656 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2660 rtx new_x = rtx_alloc (code);
2662 (sizeof (*new_x) - sizeof (new_x->fld)
2663 + (sizeof (new_x->fld[0])
2664 * GET_RTX_LENGTH (code))));
2668 XVEC (x, i) = new_v;
2671 XVECEXP (x, i, j) = new;
2679 /* Scan rtx X for modifications of elimination target registers. Update
2680 the table of eliminables to reflect the changed state. MEM_MODE is
2681 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2684 elimination_effects (x, mem_mode)
2686 enum machine_mode mem_mode;
2689 enum rtx_code code = GET_CODE (x);
2690 struct elim_table *ep;
2717 /* First handle the case where we encounter a bare register that
2718 is eliminable. Replace it with a PLUS. */
2719 if (regno < FIRST_PSEUDO_REGISTER)
2721 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2723 if (ep->from_rtx == x && ep->can_eliminate)
2726 ep->ref_outside_mem = 1;
2731 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2732 && reg_equiv_constant[regno]
2733 && ! function_invariant_p (reg_equiv_constant[regno]))
2734 elimination_effects (reg_equiv_constant[regno], mem_mode);
2743 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2744 if (ep->to_rtx == XEXP (x, 0))
2746 int size = GET_MODE_SIZE (mem_mode);
2748 /* If more bytes than MEM_MODE are pushed, account for them. */
2749 #ifdef PUSH_ROUNDING
2750 if (ep->to_rtx == stack_pointer_rtx)
2751 size = PUSH_ROUNDING (size);
2753 if (code == PRE_DEC || code == POST_DEC)
2755 else if (code == PRE_INC || code == POST_INC)
2757 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2758 && GET_CODE (XEXP (x, 1)) == PLUS
2759 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2760 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2761 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2764 /* These two aren't unary operators. */
2765 if (code == POST_MODIFY || code == PRE_MODIFY)
2768 /* Fall through to generic unary operation case. */
2769 case STRICT_LOW_PART:
2771 case SIGN_EXTEND: case ZERO_EXTEND:
2772 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2773 case FLOAT: case FIX:
2774 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2782 elimination_effects (XEXP (x, 0), mem_mode);
2786 if (GET_CODE (SUBREG_REG (x)) == REG
2787 && (GET_MODE_SIZE (GET_MODE (x))
2788 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2789 && reg_equiv_memory_loc != 0
2790 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2793 elimination_effects (SUBREG_REG (x), mem_mode);
2797 /* If using a register that is the source of an eliminate we still
2798 think can be performed, note it cannot be performed since we don't
2799 know how this register is used. */
2800 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2801 if (ep->from_rtx == XEXP (x, 0))
2802 ep->can_eliminate = 0;
2804 elimination_effects (XEXP (x, 0), mem_mode);
2808 /* If clobbering a register that is the replacement register for an
2809 elimination we still think can be performed, note that it cannot
2810 be performed. Otherwise, we need not be concerned about it. */
2811 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2812 if (ep->to_rtx == XEXP (x, 0))
2813 ep->can_eliminate = 0;
2815 elimination_effects (XEXP (x, 0), mem_mode);
2819 /* Check for setting a register that we know about. */
2820 if (GET_CODE (SET_DEST (x)) == REG)
2822 /* See if this is setting the replacement register for an
2825 If DEST is the hard frame pointer, we do nothing because we
2826 assume that all assignments to the frame pointer are for
2827 non-local gotos and are being done at a time when they are valid
2828 and do not disturb anything else. Some machines want to
2829 eliminate a fake argument pointer (or even a fake frame pointer)
2830 with either the real frame or the stack pointer. Assignments to
2831 the hard frame pointer must not prevent this elimination. */
2833 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2835 if (ep->to_rtx == SET_DEST (x)
2836 && SET_DEST (x) != hard_frame_pointer_rtx)
2838 /* If it is being incremented, adjust the offset. Otherwise,
2839 this elimination can't be done. */
2840 rtx src = SET_SRC (x);
2842 if (GET_CODE (src) == PLUS
2843 && XEXP (src, 0) == SET_DEST (x)
2844 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2845 ep->offset -= INTVAL (XEXP (src, 1));
2847 ep->can_eliminate = 0;
2851 elimination_effects (SET_DEST (x), 0);
2852 elimination_effects (SET_SRC (x), 0);
2856 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2859 /* Our only special processing is to pass the mode of the MEM to our
2861 elimination_effects (XEXP (x, 0), GET_MODE (x));
2868 fmt = GET_RTX_FORMAT (code);
2869 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2872 elimination_effects (XEXP (x, i), mem_mode);
2873 else if (*fmt == 'E')
2874 for (j = 0; j < XVECLEN (x, i); j++)
2875 elimination_effects (XVECEXP (x, i, j), mem_mode);
2879 /* Descend through rtx X and verify that no references to eliminable registers
2880 remain. If any do remain, mark the involved register as not
2884 check_eliminable_occurrences (x)
2894 code = GET_CODE (x);
2896 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2898 struct elim_table *ep;
2900 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2901 if (ep->from_rtx == x && ep->can_eliminate)
2902 ep->can_eliminate = 0;
2906 fmt = GET_RTX_FORMAT (code);
2907 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2910 check_eliminable_occurrences (XEXP (x, i));
2911 else if (*fmt == 'E')
2914 for (j = 0; j < XVECLEN (x, i); j++)
2915 check_eliminable_occurrences (XVECEXP (x, i, j));
2920 /* Scan INSN and eliminate all eliminable registers in it.
2922 If REPLACE is nonzero, do the replacement destructively. Also
2923 delete the insn as dead it if it is setting an eliminable register.
2925 If REPLACE is zero, do all our allocations in reload_obstack.
2927 If no eliminations were done and this insn doesn't require any elimination
2928 processing (these are not identical conditions: it might be updating sp,
2929 but not referencing fp; this needs to be seen during reload_as_needed so
2930 that the offset between fp and sp can be taken into consideration), zero
2931 is returned. Otherwise, 1 is returned. */
2934 eliminate_regs_in_insn (insn, replace)
2938 int icode = recog_memoized (insn);
2939 rtx old_body = PATTERN (insn);
2940 int insn_is_asm = asm_noperands (old_body) >= 0;
2941 rtx old_set = single_set (insn);
2945 rtx substed_operand[MAX_RECOG_OPERANDS];
2946 rtx orig_operand[MAX_RECOG_OPERANDS];
2947 struct elim_table *ep;
2949 if (! insn_is_asm && icode < 0)
2951 if (GET_CODE (PATTERN (insn)) == USE
2952 || GET_CODE (PATTERN (insn)) == CLOBBER
2953 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2954 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2955 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2960 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2961 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2963 /* Check for setting an eliminable register. */
2964 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2965 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2967 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2968 /* If this is setting the frame pointer register to the
2969 hardware frame pointer register and this is an elimination
2970 that will be done (tested above), this insn is really
2971 adjusting the frame pointer downward to compensate for
2972 the adjustment done before a nonlocal goto. */
2973 if (ep->from == FRAME_POINTER_REGNUM
2974 && ep->to == HARD_FRAME_POINTER_REGNUM)
2976 rtx base = SET_SRC (old_set);
2977 rtx base_insn = insn;
2980 while (base != ep->to_rtx)
2982 rtx prev_insn, prev_set;
2984 if (GET_CODE (base) == PLUS
2985 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2987 offset += INTVAL (XEXP (base, 1));
2988 base = XEXP (base, 0);
2990 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2991 && (prev_set = single_set (prev_insn)) != 0
2992 && rtx_equal_p (SET_DEST (prev_set), base))
2994 base = SET_SRC (prev_set);
2995 base_insn = prev_insn;
3001 if (base == ep->to_rtx)
3004 = plus_constant (ep->to_rtx, offset - ep->offset);
3006 new_body = old_body;
3009 new_body = copy_insn (old_body);
3010 if (REG_NOTES (insn))
3011 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3013 PATTERN (insn) = new_body;
3014 old_set = single_set (insn);
3016 /* First see if this insn remains valid when we
3017 make the change. If not, keep the INSN_CODE
3018 the same and let reload fit it up. */
3019 validate_change (insn, &SET_SRC (old_set), src, 1);
3020 validate_change (insn, &SET_DEST (old_set),
3022 if (! apply_change_group ())
3024 SET_SRC (old_set) = src;
3025 SET_DEST (old_set) = ep->to_rtx;
3034 /* In this case this insn isn't serving a useful purpose. We
3035 will delete it in reload_as_needed once we know that this
3036 elimination is, in fact, being done.
3038 If REPLACE isn't set, we can't delete this insn, but needn't
3039 process it since it won't be used unless something changes. */
3042 delete_dead_insn (insn);
3050 /* We allow one special case which happens to work on all machines we
3051 currently support: a single set with the source being a PLUS of an
3052 eliminable register and a constant. */
3054 && GET_CODE (SET_DEST (old_set)) == REG
3055 && GET_CODE (SET_SRC (old_set)) == PLUS
3056 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3057 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
3058 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
3060 rtx reg = XEXP (SET_SRC (old_set), 0);
3061 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
3063 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3064 if (ep->from_rtx == reg && ep->can_eliminate)
3066 offset += ep->offset;
3071 /* We assume here that if we need a PARALLEL with
3072 CLOBBERs for this assignment, we can do with the
3073 MATCH_SCRATCHes that add_clobbers allocates.
3074 There's not much we can do if that doesn't work. */
3075 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3079 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3082 rtvec vec = rtvec_alloc (num_clobbers + 1);
3084 vec->elem[0] = PATTERN (insn);
3085 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3086 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3088 if (INSN_CODE (insn) < 0)
3093 new_body = old_body;
3096 new_body = copy_insn (old_body);
3097 if (REG_NOTES (insn))
3098 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3100 PATTERN (insn) = new_body;
3101 old_set = single_set (insn);
3103 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3104 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3107 /* This can't have an effect on elimination offsets, so skip right
3113 /* Determine the effects of this insn on elimination offsets. */
3114 elimination_effects (old_body, 0);
3116 /* Eliminate all eliminable registers occurring in operands that
3117 can be handled by reload. */
3118 extract_insn (insn);
3119 for (i = 0; i < recog_data.n_operands; i++)
3121 orig_operand[i] = recog_data.operand[i];
3122 substed_operand[i] = recog_data.operand[i];
3124 /* For an asm statement, every operand is eliminable. */
3125 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3127 /* Check for setting a register that we know about. */
3128 if (recog_data.operand_type[i] != OP_IN
3129 && GET_CODE (orig_operand[i]) == REG)
3131 /* If we are assigning to a register that can be eliminated, it
3132 must be as part of a PARALLEL, since the code above handles
3133 single SETs. We must indicate that we can no longer
3134 eliminate this reg. */
3135 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3137 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3138 ep->can_eliminate = 0;
3141 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3142 replace ? insn : NULL_RTX);
3143 if (substed_operand[i] != orig_operand[i])
3145 /* Terminate the search in check_eliminable_occurrences at
3147 *recog_data.operand_loc[i] = 0;
3149 /* If an output operand changed from a REG to a MEM and INSN is an
3150 insn, write a CLOBBER insn. */
3151 if (recog_data.operand_type[i] != OP_IN
3152 && GET_CODE (orig_operand[i]) == REG
3153 && GET_CODE (substed_operand[i]) == MEM
3155 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3160 for (i = 0; i < recog_data.n_dups; i++)
3161 *recog_data.dup_loc[i]
3162 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3164 /* If any eliminable remain, they aren't eliminable anymore. */
3165 check_eliminable_occurrences (old_body);
3167 /* Substitute the operands; the new values are in the substed_operand
3169 for (i = 0; i < recog_data.n_operands; i++)
3170 *recog_data.operand_loc[i] = substed_operand[i];
3171 for (i = 0; i < recog_data.n_dups; i++)
3172 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3174 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3175 re-recognize the insn. We do this in case we had a simple addition
3176 but now can do this as a load-address. This saves an insn in this
3178 If re-recognition fails, the old insn code number will still be used,
3179 and some register operands may have changed into PLUS expressions.
3180 These will be handled by find_reloads by loading them into a register
3185 /* If we aren't replacing things permanently and we changed something,
3186 make another copy to ensure that all the RTL is new. Otherwise
3187 things can go wrong if find_reload swaps commutative operands
3188 and one is inside RTL that has been copied while the other is not. */
3189 new_body = old_body;
3192 new_body = copy_insn (old_body);
3193 if (REG_NOTES (insn))
3194 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3196 PATTERN (insn) = new_body;
3198 /* If we had a move insn but now we don't, rerecognize it. This will
3199 cause spurious re-recognition if the old move had a PARALLEL since
3200 the new one still will, but we can't call single_set without
3201 having put NEW_BODY into the insn and the re-recognition won't
3202 hurt in this rare case. */
3203 /* ??? Why this huge if statement - why don't we just rerecognize the
3207 && ((GET_CODE (SET_SRC (old_set)) == REG
3208 && (GET_CODE (new_body) != SET
3209 || GET_CODE (SET_SRC (new_body)) != REG))
3210 /* If this was a load from or store to memory, compare
3211 the MEM in recog_data.operand to the one in the insn.
3212 If they are not equal, then rerecognize the insn. */
3214 && ((GET_CODE (SET_SRC (old_set)) == MEM
3215 && SET_SRC (old_set) != recog_data.operand[1])
3216 || (GET_CODE (SET_DEST (old_set)) == MEM
3217 && SET_DEST (old_set) != recog_data.operand[0])))
3218 /* If this was an add insn before, rerecognize. */
3219 || GET_CODE (SET_SRC (old_set)) == PLUS))
3221 int new_icode = recog (PATTERN (insn), insn, 0);
3223 INSN_CODE (insn) = icode;
3227 /* Restore the old body. If there were any changes to it, we made a copy
3228 of it while the changes were still in place, so we'll correctly return
3229 a modified insn below. */
3232 /* Restore the old body. */
3233 for (i = 0; i < recog_data.n_operands; i++)
3234 *recog_data.operand_loc[i] = orig_operand[i];
3235 for (i = 0; i < recog_data.n_dups; i++)
3236 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3239 /* Update all elimination pairs to reflect the status after the current
3240 insn. The changes we make were determined by the earlier call to
3241 elimination_effects.
3243 We also detect cases where register elimination cannot be done,
3244 namely, if a register would be both changed and referenced outside a MEM
3245 in the resulting insn since such an insn is often undefined and, even if
3246 not, we cannot know what meaning will be given to it. Note that it is
3247 valid to have a register used in an address in an insn that changes it
3248 (presumably with a pre- or post-increment or decrement).
3250 If anything changes, return nonzero. */
3252 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3254 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3255 ep->can_eliminate = 0;
3257 ep->ref_outside_mem = 0;
3259 if (ep->previous_offset != ep->offset)
3264 /* If we changed something, perform elimination in REG_NOTES. This is
3265 needed even when REPLACE is zero because a REG_DEAD note might refer
3266 to a register that we eliminate and could cause a different number
3267 of spill registers to be needed in the final reload pass than in
3269 if (val && REG_NOTES (insn) != 0)
3270 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3275 /* Loop through all elimination pairs.
3276 Recalculate the number not at initial offset.
3278 Compute the maximum offset (minimum offset if the stack does not
3279 grow downward) for each elimination pair. */
3282 update_eliminable_offsets ()
3284 struct elim_table *ep;
3286 num_not_at_initial_offset = 0;
3287 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3289 ep->previous_offset = ep->offset;
3290 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3291 num_not_at_initial_offset++;
3295 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3296 replacement we currently believe is valid, mark it as not eliminable if X
3297 modifies DEST in any way other than by adding a constant integer to it.
3299 If DEST is the frame pointer, we do nothing because we assume that
3300 all assignments to the hard frame pointer are nonlocal gotos and are being
3301 done at a time when they are valid and do not disturb anything else.
3302 Some machines want to eliminate a fake argument pointer with either the
3303 frame or stack pointer. Assignments to the hard frame pointer must not
3304 prevent this elimination.
3306 Called via note_stores from reload before starting its passes to scan
3307 the insns of the function. */
3310 mark_not_eliminable (dest, x, data)
3313 void *data ATTRIBUTE_UNUSED;
3317 /* A SUBREG of a hard register here is just changing its mode. We should
3318 not see a SUBREG of an eliminable hard register, but check just in
3320 if (GET_CODE (dest) == SUBREG)
3321 dest = SUBREG_REG (dest);
3323 if (dest == hard_frame_pointer_rtx)
3326 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3327 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3328 && (GET_CODE (x) != SET
3329 || GET_CODE (SET_SRC (x)) != PLUS
3330 || XEXP (SET_SRC (x), 0) != dest
3331 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3333 reg_eliminate[i].can_eliminate_previous
3334 = reg_eliminate[i].can_eliminate = 0;
3339 /* Verify that the initial elimination offsets did not change since the
3340 last call to set_initial_elim_offsets. This is used to catch cases
3341 where something illegal happened during reload_as_needed that could
3342 cause incorrect code to be generated if we did not check for it. */
3345 verify_initial_elim_offsets ()
3349 #ifdef ELIMINABLE_REGS
3350 struct elim_table *ep;
3352 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3354 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3355 if (t != ep->initial_offset)
3359 INITIAL_FRAME_POINTER_OFFSET (t);
3360 if (t != reg_eliminate[0].initial_offset)
3365 /* Reset all offsets on eliminable registers to their initial values. */
3368 set_initial_elim_offsets ()
3370 struct elim_table *ep = reg_eliminate;
3372 #ifdef ELIMINABLE_REGS
3373 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3375 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3376 ep->previous_offset = ep->offset = ep->initial_offset;
3379 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3380 ep->previous_offset = ep->offset = ep->initial_offset;
3383 num_not_at_initial_offset = 0;
3386 /* Initialize the known label offsets.
3387 Set a known offset for each forced label to be at the initial offset
3388 of each elimination. We do this because we assume that all
3389 computed jumps occur from a location where each elimination is
3390 at its initial offset.
3391 For all other labels, show that we don't know the offsets. */
3394 set_initial_label_offsets ()
3397 memset (offsets_known_at, 0, num_labels);
3399 for (x = forced_labels; x; x = XEXP (x, 1))
3401 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3404 /* Set all elimination offsets to the known values for the code label given
3408 set_offsets_for_label (insn)
3412 int label_nr = CODE_LABEL_NUMBER (insn);
3413 struct elim_table *ep;
3415 num_not_at_initial_offset = 0;
3416 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3418 ep->offset = ep->previous_offset
3419 = offsets_at[label_nr - first_label_num][i];
3420 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3421 num_not_at_initial_offset++;
3425 /* See if anything that happened changes which eliminations are valid.
3426 For example, on the SPARC, whether or not the frame pointer can
3427 be eliminated can depend on what registers have been used. We need
3428 not check some conditions again (such as flag_omit_frame_pointer)
3429 since they can't have changed. */
3432 update_eliminables (pset)
3435 int previous_frame_pointer_needed = frame_pointer_needed;
3436 struct elim_table *ep;
3438 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3439 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3440 #ifdef ELIMINABLE_REGS
3441 || ! CAN_ELIMINATE (ep->from, ep->to)
3444 ep->can_eliminate = 0;
3446 /* Look for the case where we have discovered that we can't replace
3447 register A with register B and that means that we will now be
3448 trying to replace register A with register C. This means we can
3449 no longer replace register C with register B and we need to disable
3450 such an elimination, if it exists. This occurs often with A == ap,
3451 B == sp, and C == fp. */
3453 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3455 struct elim_table *op;
3458 if (! ep->can_eliminate && ep->can_eliminate_previous)
3460 /* Find the current elimination for ep->from, if there is a
3462 for (op = reg_eliminate;
3463 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3464 if (op->from == ep->from && op->can_eliminate)
3470 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3472 for (op = reg_eliminate;
3473 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3474 if (op->from == new_to && op->to == ep->to)
3475 op->can_eliminate = 0;
3479 /* See if any registers that we thought we could eliminate the previous
3480 time are no longer eliminable. If so, something has changed and we
3481 must spill the register. Also, recompute the number of eliminable
3482 registers and see if the frame pointer is needed; it is if there is
3483 no elimination of the frame pointer that we can perform. */
3485 frame_pointer_needed = 1;
3486 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3488 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3489 && ep->to != HARD_FRAME_POINTER_REGNUM)
3490 frame_pointer_needed = 0;
3492 if (! ep->can_eliminate && ep->can_eliminate_previous)
3494 ep->can_eliminate_previous = 0;
3495 SET_HARD_REG_BIT (*pset, ep->from);
3500 /* If we didn't need a frame pointer last time, but we do now, spill
3501 the hard frame pointer. */
3502 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3503 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3506 /* Initialize the table of registers to eliminate. */
3511 struct elim_table *ep;
3512 #ifdef ELIMINABLE_REGS
3513 const struct elim_table_1 *ep1;
3517 reg_eliminate = (struct elim_table *)
3518 xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3520 /* Does this function require a frame pointer? */
3522 frame_pointer_needed = (! flag_omit_frame_pointer
3523 #ifdef EXIT_IGNORE_STACK
3524 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3525 and restore sp for alloca. So we can't eliminate
3526 the frame pointer in that case. At some point,
3527 we should improve this by emitting the
3528 sp-adjusting insns for this case. */
3529 || (current_function_calls_alloca
3530 && EXIT_IGNORE_STACK)
3532 || FRAME_POINTER_REQUIRED);
3536 #ifdef ELIMINABLE_REGS
3537 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3538 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3540 ep->from = ep1->from;
3542 ep->can_eliminate = ep->can_eliminate_previous
3543 = (CAN_ELIMINATE (ep->from, ep->to)
3544 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3547 reg_eliminate[0].from = reg_eliminate_1[0].from;
3548 reg_eliminate[0].to = reg_eliminate_1[0].to;
3549 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3550 = ! frame_pointer_needed;
3553 /* Count the number of eliminable registers and build the FROM and TO
3554 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3555 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3556 We depend on this. */
3557 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3559 num_eliminable += ep->can_eliminate;
3560 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3561 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3565 /* Kick all pseudos out of hard register REGNO.
3567 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3568 because we found we can't eliminate some register. In the case, no pseudos
3569 are allowed to be in the register, even if they are only in a block that
3570 doesn't require spill registers, unlike the case when we are spilling this
3571 hard reg to produce another spill register.
3573 Return nonzero if any pseudos needed to be kicked out. */
3576 spill_hard_reg (regno, cant_eliminate)
3584 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3585 regs_ever_live[regno] = 1;
3588 /* Spill every pseudo reg that was allocated to this reg
3589 or to something that overlaps this reg. */
3591 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3592 if (reg_renumber[i] >= 0
3593 && (unsigned int) reg_renumber[i] <= regno
3594 && ((unsigned int) reg_renumber[i]
3595 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3596 PSEUDO_REGNO_MODE (i))
3598 SET_REGNO_REG_SET (&spilled_pseudos, i);
3601 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3602 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3605 ior_hard_reg_set (set1, set2)
3606 HARD_REG_SET *set1, *set2;
3608 IOR_HARD_REG_SET (*set1, *set2);
3611 /* After find_reload_regs has been run for all insn that need reloads,
3612 and/or spill_hard_regs was called, this function is used to actually
3613 spill pseudo registers and try to reallocate them. It also sets up the
3614 spill_regs array for use by choose_reload_regs. */
3617 finish_spills (global)
3620 struct insn_chain *chain;
3621 int something_changed = 0;
3624 /* Build the spill_regs array for the function. */
3625 /* If there are some registers still to eliminate and one of the spill regs
3626 wasn't ever used before, additional stack space may have to be
3627 allocated to store this register. Thus, we may have changed the offset
3628 between the stack and frame pointers, so mark that something has changed.
3630 One might think that we need only set VAL to 1 if this is a call-used
3631 register. However, the set of registers that must be saved by the
3632 prologue is not identical to the call-used set. For example, the
3633 register used by the call insn for the return PC is a call-used register,
3634 but must be saved by the prologue. */
3637 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3638 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3640 spill_reg_order[i] = n_spills;
3641 spill_regs[n_spills++] = i;
3642 if (num_eliminable && ! regs_ever_live[i])
3643 something_changed = 1;
3644 regs_ever_live[i] = 1;
3647 spill_reg_order[i] = -1;
3649 EXECUTE_IF_SET_IN_REG_SET
3650 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3652 /* Record the current hard register the pseudo is allocated to in
3653 pseudo_previous_regs so we avoid reallocating it to the same
3654 hard reg in a later pass. */
3655 if (reg_renumber[i] < 0)
3658 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3659 /* Mark it as no longer having a hard register home. */
3660 reg_renumber[i] = -1;
3661 /* We will need to scan everything again. */
3662 something_changed = 1;
3665 /* Retry global register allocation if possible. */
3668 memset ((char *) pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3669 /* For every insn that needs reloads, set the registers used as spill
3670 regs in pseudo_forbidden_regs for every pseudo live across the
3672 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3674 EXECUTE_IF_SET_IN_REG_SET
3675 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3677 ior_hard_reg_set (pseudo_forbidden_regs + i,
3678 &chain->used_spill_regs);
3680 EXECUTE_IF_SET_IN_REG_SET
3681 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3683 ior_hard_reg_set (pseudo_forbidden_regs + i,
3684 &chain->used_spill_regs);
3688 /* Retry allocating the spilled pseudos. For each reg, merge the
3689 various reg sets that indicate which hard regs can't be used,
3690 and call retry_global_alloc.
3691 We change spill_pseudos here to only contain pseudos that did not
3692 get a new hard register. */
3693 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3694 if (reg_old_renumber[i] != reg_renumber[i])
3696 HARD_REG_SET forbidden;
3697 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3698 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3699 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3700 retry_global_alloc (i, forbidden);
3701 if (reg_renumber[i] >= 0)
3702 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3706 /* Fix up the register information in the insn chain.
3707 This involves deleting those of the spilled pseudos which did not get
3708 a new hard register home from the live_{before,after} sets. */
3709 for (chain = reload_insn_chain; chain; chain = chain->next)
3711 HARD_REG_SET used_by_pseudos;
3712 HARD_REG_SET used_by_pseudos2;
3714 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3715 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3717 /* Mark any unallocated hard regs as available for spills. That
3718 makes inheritance work somewhat better. */
3719 if (chain->need_reload)
3721 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3722 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3723 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3725 /* Save the old value for the sanity test below. */
3726 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3728 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3729 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3730 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3731 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3733 /* Make sure we only enlarge the set. */
3734 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3740 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3741 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3743 int regno = reg_renumber[i];
3744 if (reg_old_renumber[i] == regno)
3747 alter_reg (i, reg_old_renumber[i]);
3748 reg_old_renumber[i] = regno;
3752 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3754 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3755 i, reg_renumber[i]);
3759 return something_changed;
3762 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3763 Also mark any hard registers used to store user variables as
3764 forbidden from being used for spill registers. */
3767 scan_paradoxical_subregs (x)
3772 enum rtx_code code = GET_CODE (x);
3778 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3779 && REG_USERVAR_P (x))
3780 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3789 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3797 if (GET_CODE (SUBREG_REG (x)) == REG
3798 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3799 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3800 = GET_MODE_SIZE (GET_MODE (x));
3807 fmt = GET_RTX_FORMAT (code);
3808 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3811 scan_paradoxical_subregs (XEXP (x, i));
3812 else if (fmt[i] == 'E')
3815 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3816 scan_paradoxical_subregs (XVECEXP (x, i, j));
3821 /* Reload pseudo-registers into hard regs around each insn as needed.
3822 Additional register load insns are output before the insn that needs it
3823 and perhaps store insns after insns that modify the reloaded pseudo reg.
3825 reg_last_reload_reg and reg_reloaded_contents keep track of
3826 which registers are already available in reload registers.
3827 We update these for the reloads that we perform,
3828 as the insns are scanned. */
3831 reload_as_needed (live_known)
3834 struct insn_chain *chain;
3835 #if defined (AUTO_INC_DEC)
3840 memset ((char *) spill_reg_rtx, 0, sizeof spill_reg_rtx);
3841 memset ((char *) spill_reg_store, 0, sizeof spill_reg_store);
3842 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3843 reg_has_output_reload = (char *) xmalloc (max_regno);
3844 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3846 set_initial_elim_offsets ();
3848 for (chain = reload_insn_chain; chain; chain = chain->next)
3851 rtx insn = chain->insn;
3852 rtx old_next = NEXT_INSN (insn);
3854 /* If we pass a label, copy the offsets from the label information
3855 into the current offsets of each elimination. */
3856 if (GET_CODE (insn) == CODE_LABEL)
3857 set_offsets_for_label (insn);
3859 else if (INSN_P (insn))
3861 rtx oldpat = copy_rtx (PATTERN (insn));
3863 /* If this is a USE and CLOBBER of a MEM, ensure that any
3864 references to eliminable registers have been removed. */
3866 if ((GET_CODE (PATTERN (insn)) == USE
3867 || GET_CODE (PATTERN (insn)) == CLOBBER)
3868 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3869 XEXP (XEXP (PATTERN (insn), 0), 0)
3870 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3871 GET_MODE (XEXP (PATTERN (insn), 0)),
3874 /* If we need to do register elimination processing, do so.
3875 This might delete the insn, in which case we are done. */
3876 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3878 eliminate_regs_in_insn (insn, 1);
3879 if (GET_CODE (insn) == NOTE)
3881 update_eliminable_offsets ();
3886 /* If need_elim is nonzero but need_reload is zero, one might think
3887 that we could simply set n_reloads to 0. However, find_reloads
3888 could have done some manipulation of the insn (such as swapping
3889 commutative operands), and these manipulations are lost during
3890 the first pass for every insn that needs register elimination.
3891 So the actions of find_reloads must be redone here. */
3893 if (! chain->need_elim && ! chain->need_reload
3894 && ! chain->need_operand_change)
3896 /* First find the pseudo regs that must be reloaded for this insn.
3897 This info is returned in the tables reload_... (see reload.h).
3898 Also modify the body of INSN by substituting RELOAD
3899 rtx's for those pseudo regs. */
3902 memset (reg_has_output_reload, 0, max_regno);
3903 CLEAR_HARD_REG_SET (reg_is_output_reload);
3905 find_reloads (insn, 1, spill_indirect_levels, live_known,
3911 rtx next = NEXT_INSN (insn);
3914 prev = PREV_INSN (insn);
3916 /* Now compute which reload regs to reload them into. Perhaps
3917 reusing reload regs from previous insns, or else output
3918 load insns to reload them. Maybe output store insns too.
3919 Record the choices of reload reg in reload_reg_rtx. */
3920 choose_reload_regs (chain);
3922 /* Merge any reloads that we didn't combine for fear of
3923 increasing the number of spill registers needed but now
3924 discover can be safely merged. */
3925 if (SMALL_REGISTER_CLASSES)
3926 merge_assigned_reloads (insn);
3928 /* Generate the insns to reload operands into or out of
3929 their reload regs. */
3930 emit_reload_insns (chain);
3932 /* Substitute the chosen reload regs from reload_reg_rtx
3933 into the insn's body (or perhaps into the bodies of other
3934 load and store insn that we just made for reloading
3935 and that we moved the structure into). */
3936 subst_reloads (insn);
3938 /* If this was an ASM, make sure that all the reload insns
3939 we have generated are valid. If not, give an error
3942 if (asm_noperands (PATTERN (insn)) >= 0)
3943 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3944 if (p != insn && INSN_P (p)
3945 && (recog_memoized (p) < 0
3946 || (extract_insn (p), ! constrain_operands (1))))
3948 error_for_asm (insn,
3949 "`asm' operand requires impossible reload");
3954 if (num_eliminable && chain->need_elim)
3955 update_eliminable_offsets ();
3957 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3958 is no longer validly lying around to save a future reload.
3959 Note that this does not detect pseudos that were reloaded
3960 for this insn in order to be stored in
3961 (obeying register constraints). That is correct; such reload
3962 registers ARE still valid. */
3963 note_stores (oldpat, forget_old_reloads_1, NULL);
3965 /* There may have been CLOBBER insns placed after INSN. So scan
3966 between INSN and NEXT and use them to forget old reloads. */
3967 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3968 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3969 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3972 /* Likewise for regs altered by auto-increment in this insn.
3973 REG_INC notes have been changed by reloading:
3974 find_reloads_address_1 records substitutions for them,
3975 which have been performed by subst_reloads above. */
3976 for (i = n_reloads - 1; i >= 0; i--)
3978 rtx in_reg = rld[i].in_reg;
3981 enum rtx_code code = GET_CODE (in_reg);
3982 /* PRE_INC / PRE_DEC will have the reload register ending up
3983 with the same value as the stack slot, but that doesn't
3984 hold true for POST_INC / POST_DEC. Either we have to
3985 convert the memory access to a true POST_INC / POST_DEC,
3986 or we can't use the reload register for inheritance. */
3987 if ((code == POST_INC || code == POST_DEC)
3988 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3989 REGNO (rld[i].reg_rtx))
3990 /* Make sure it is the inc/dec pseudo, and not
3991 some other (e.g. output operand) pseudo. */
3992 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3993 == REGNO (XEXP (in_reg, 0))))
3996 rtx reload_reg = rld[i].reg_rtx;
3997 enum machine_mode mode = GET_MODE (reload_reg);
4001 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4003 /* We really want to ignore REG_INC notes here, so
4004 use PATTERN (p) as argument to reg_set_p . */
4005 if (reg_set_p (reload_reg, PATTERN (p)))
4007 n = count_occurrences (PATTERN (p), reload_reg, 0);
4012 n = validate_replace_rtx (reload_reg,
4013 gen_rtx (code, mode,
4017 /* We must also verify that the constraints
4018 are met after the replacement. */
4021 n = constrain_operands (1);
4025 /* If the constraints were not met, then
4026 undo the replacement. */
4029 validate_replace_rtx (gen_rtx (code, mode,
4041 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4043 /* Mark this as having an output reload so that the
4044 REG_INC processing code below won't invalidate
4045 the reload for inheritance. */
4046 SET_HARD_REG_BIT (reg_is_output_reload,
4047 REGNO (reload_reg));
4048 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4051 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4054 else if ((code == PRE_INC || code == PRE_DEC)
4055 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4056 REGNO (rld[i].reg_rtx))
4057 /* Make sure it is the inc/dec pseudo, and not
4058 some other (e.g. output operand) pseudo. */
4059 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4060 == REGNO (XEXP (in_reg, 0))))
4062 SET_HARD_REG_BIT (reg_is_output_reload,
4063 REGNO (rld[i].reg_rtx));
4064 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4068 /* If a pseudo that got a hard register is auto-incremented,
4069 we must purge records of copying it into pseudos without
4071 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4072 if (REG_NOTE_KIND (x) == REG_INC)
4074 /* See if this pseudo reg was reloaded in this insn.
4075 If so, its last-reload info is still valid
4076 because it is based on this insn's reload. */
4077 for (i = 0; i < n_reloads; i++)
4078 if (rld[i].out == XEXP (x, 0))
4082 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4086 /* A reload reg's contents are unknown after a label. */
4087 if (GET_CODE (insn) == CODE_LABEL)
4088 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4090 /* Don't assume a reload reg is still good after a call insn
4091 if it is a call-used reg. */
4092 else if (GET_CODE (insn) == CALL_INSN)
4093 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4097 free (reg_last_reload_reg);
4098 free (reg_has_output_reload);
4101 /* Discard all record of any value reloaded from X,
4102 or reloaded in X from someplace else;
4103 unless X is an output reload reg of the current insn.
4105 X may be a hard reg (the reload reg)
4106 or it may be a pseudo reg that was reloaded from. */
4109 forget_old_reloads_1 (x, ignored, data)
4111 rtx ignored ATTRIBUTE_UNUSED;
4112 void *data ATTRIBUTE_UNUSED;
4117 /* note_stores does give us subregs of hard regs,
4118 subreg_regno_offset will abort if it is not a hard reg. */
4119 while (GET_CODE (x) == SUBREG)
4121 /* We ignore the subreg offset when calculating the regno,
4122 because we are using the entire underlying hard register
4127 if (GET_CODE (x) != REG)
4132 if (regno >= FIRST_PSEUDO_REGISTER)
4138 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4139 /* Storing into a spilled-reg invalidates its contents.
4140 This can happen if a block-local pseudo is allocated to that reg
4141 and it wasn't spilled because this block's total need is 0.
4142 Then some insn might have an optional reload and use this reg. */
4143 for (i = 0; i < nr; i++)
4144 /* But don't do this if the reg actually serves as an output
4145 reload reg in the current instruction. */
4147 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4149 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4150 spill_reg_store[regno + i] = 0;
4154 /* Since value of X has changed,
4155 forget any value previously copied from it. */
4158 /* But don't forget a copy if this is the output reload
4159 that establishes the copy's validity. */
4160 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4161 reg_last_reload_reg[regno + nr] = 0;
4164 /* The following HARD_REG_SETs indicate when each hard register is
4165 used for a reload of various parts of the current insn. */
4167 /* If reg is unavailable for all reloads. */
4168 static HARD_REG_SET reload_reg_unavailable;
4169 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4170 static HARD_REG_SET reload_reg_used;
4171 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4172 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4173 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4174 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4175 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4176 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4177 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4178 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4179 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4180 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4181 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4182 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4183 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4184 static HARD_REG_SET reload_reg_used_in_op_addr;
4185 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4186 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4187 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4188 static HARD_REG_SET reload_reg_used_in_insn;
4189 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4190 static HARD_REG_SET reload_reg_used_in_other_addr;
4192 /* If reg is in use as a reload reg for any sort of reload. */
4193 static HARD_REG_SET reload_reg_used_at_all;
4195 /* If reg is use as an inherited reload. We just mark the first register
4197 static HARD_REG_SET reload_reg_used_for_inherit;
4199 /* Records which hard regs are used in any way, either as explicit use or
4200 by being allocated to a pseudo during any point of the current insn. */
4201 static HARD_REG_SET reg_used_in_insn;
4203 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4204 TYPE. MODE is used to indicate how many consecutive regs are
4208 mark_reload_reg_in_use (regno, opnum, type, mode)
4211 enum reload_type type;
4212 enum machine_mode mode;
4214 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4217 for (i = regno; i < nregs + regno; i++)
4222 SET_HARD_REG_BIT (reload_reg_used, i);
4225 case RELOAD_FOR_INPUT_ADDRESS:
4226 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4229 case RELOAD_FOR_INPADDR_ADDRESS:
4230 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4233 case RELOAD_FOR_OUTPUT_ADDRESS:
4234 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4237 case RELOAD_FOR_OUTADDR_ADDRESS:
4238 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4241 case RELOAD_FOR_OPERAND_ADDRESS:
4242 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4245 case RELOAD_FOR_OPADDR_ADDR:
4246 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4249 case RELOAD_FOR_OTHER_ADDRESS:
4250 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4253 case RELOAD_FOR_INPUT:
4254 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4257 case RELOAD_FOR_OUTPUT:
4258 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4261 case RELOAD_FOR_INSN:
4262 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4266 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4270 /* Similarly, but show REGNO is no longer in use for a reload. */
4273 clear_reload_reg_in_use (regno, opnum, type, mode)
4276 enum reload_type type;
4277 enum machine_mode mode;
4279 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4280 unsigned int start_regno, end_regno, r;
4282 /* A complication is that for some reload types, inheritance might
4283 allow multiple reloads of the same types to share a reload register.
4284 We set check_opnum if we have to check only reloads with the same
4285 operand number, and check_any if we have to check all reloads. */
4286 int check_opnum = 0;
4288 HARD_REG_SET *used_in_set;
4293 used_in_set = &reload_reg_used;
4296 case RELOAD_FOR_INPUT_ADDRESS:
4297 used_in_set = &reload_reg_used_in_input_addr[opnum];
4300 case RELOAD_FOR_INPADDR_ADDRESS:
4302 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4305 case RELOAD_FOR_OUTPUT_ADDRESS:
4306 used_in_set = &reload_reg_used_in_output_addr[opnum];
4309 case RELOAD_FOR_OUTADDR_ADDRESS:
4311 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4314 case RELOAD_FOR_OPERAND_ADDRESS:
4315 used_in_set = &reload_reg_used_in_op_addr;
4318 case RELOAD_FOR_OPADDR_ADDR:
4320 used_in_set = &reload_reg_used_in_op_addr_reload;
4323 case RELOAD_FOR_OTHER_ADDRESS:
4324 used_in_set = &reload_reg_used_in_other_addr;
4328 case RELOAD_FOR_INPUT:
4329 used_in_set = &reload_reg_used_in_input[opnum];
4332 case RELOAD_FOR_OUTPUT:
4333 used_in_set = &reload_reg_used_in_output[opnum];
4336 case RELOAD_FOR_INSN:
4337 used_in_set = &reload_reg_used_in_insn;
4342 /* We resolve conflicts with remaining reloads of the same type by
4343 excluding the intervals of reload registers by them from the
4344 interval of freed reload registers. Since we only keep track of
4345 one set of interval bounds, we might have to exclude somewhat
4346 more than what would be necessary if we used a HARD_REG_SET here.
4347 But this should only happen very infrequently, so there should
4348 be no reason to worry about it. */
4350 start_regno = regno;
4351 end_regno = regno + nregs;
4352 if (check_opnum || check_any)
4354 for (i = n_reloads - 1; i >= 0; i--)
4356 if (rld[i].when_needed == type
4357 && (check_any || rld[i].opnum == opnum)
4360 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4361 unsigned int conflict_end
4363 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4365 /* If there is an overlap with the first to-be-freed register,
4366 adjust the interval start. */
4367 if (conflict_start <= start_regno && conflict_end > start_regno)
4368 start_regno = conflict_end;
4369 /* Otherwise, if there is a conflict with one of the other
4370 to-be-freed registers, adjust the interval end. */
4371 if (conflict_start > start_regno && conflict_start < end_regno)
4372 end_regno = conflict_start;
4377 for (r = start_regno; r < end_regno; r++)
4378 CLEAR_HARD_REG_BIT (*used_in_set, r);
4381 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4382 specified by OPNUM and TYPE. */
4385 reload_reg_free_p (regno, opnum, type)
4388 enum reload_type type;
4392 /* In use for a RELOAD_OTHER means it's not available for anything. */
4393 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4394 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4400 /* In use for anything means we can't use it for RELOAD_OTHER. */
4401 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4402 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4403 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4406 for (i = 0; i < reload_n_operands; i++)
4407 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4408 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4409 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4410 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4411 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4412 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4417 case RELOAD_FOR_INPUT:
4418 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4419 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4422 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4425 /* If it is used for some other input, can't use it. */
4426 for (i = 0; i < reload_n_operands; i++)
4427 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4430 /* If it is used in a later operand's address, can't use it. */
4431 for (i = opnum + 1; i < reload_n_operands; i++)
4432 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4433 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4438 case RELOAD_FOR_INPUT_ADDRESS:
4439 /* Can't use a register if it is used for an input address for this
4440 operand or used as an input in an earlier one. */
4441 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4442 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4445 for (i = 0; i < opnum; i++)
4446 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4451 case RELOAD_FOR_INPADDR_ADDRESS:
4452 /* Can't use a register if it is used for an input address
4453 for this operand or used as an input in an earlier
4455 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4458 for (i = 0; i < opnum; i++)
4459 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4464 case RELOAD_FOR_OUTPUT_ADDRESS:
4465 /* Can't use a register if it is used for an output address for this
4466 operand or used as an output in this or a later operand. Note
4467 that multiple output operands are emitted in reverse order, so
4468 the conflicting ones are those with lower indices. */
4469 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4472 for (i = 0; i <= opnum; i++)
4473 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4478 case RELOAD_FOR_OUTADDR_ADDRESS:
4479 /* Can't use a register if it is used for an output address
4480 for this operand or used as an output in this or a
4481 later operand. Note that multiple output operands are
4482 emitted in reverse order, so the conflicting ones are
4483 those with lower indices. */
4484 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4487 for (i = 0; i <= opnum; i++)
4488 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4493 case RELOAD_FOR_OPERAND_ADDRESS:
4494 for (i = 0; i < reload_n_operands; i++)
4495 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4498 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4499 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4501 case RELOAD_FOR_OPADDR_ADDR:
4502 for (i = 0; i < reload_n_operands; i++)
4503 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4506 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4508 case RELOAD_FOR_OUTPUT:
4509 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4510 outputs, or an operand address for this or an earlier output.
4511 Note that multiple output operands are emitted in reverse order,
4512 so the conflicting ones are those with higher indices. */
4513 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4516 for (i = 0; i < reload_n_operands; i++)
4517 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4520 for (i = opnum; i < reload_n_operands; i++)
4521 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4522 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4527 case RELOAD_FOR_INSN:
4528 for (i = 0; i < reload_n_operands; i++)
4529 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4530 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4533 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4534 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4536 case RELOAD_FOR_OTHER_ADDRESS:
4537 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4542 /* Return 1 if the value in reload reg REGNO, as used by a reload
4543 needed for the part of the insn specified by OPNUM and TYPE,
4544 is still available in REGNO at the end of the insn.
4546 We can assume that the reload reg was already tested for availability
4547 at the time it is needed, and we should not check this again,
4548 in case the reg has already been marked in use. */
4551 reload_reg_reaches_end_p (regno, opnum, type)
4554 enum reload_type type;
4561 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4562 its value must reach the end. */
4565 /* If this use is for part of the insn,
4566 its value reaches if no subsequent part uses the same register.
4567 Just like the above function, don't try to do this with lots
4570 case RELOAD_FOR_OTHER_ADDRESS:
4571 /* Here we check for everything else, since these don't conflict
4572 with anything else and everything comes later. */
4574 for (i = 0; i < reload_n_operands; i++)
4575 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4576 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4577 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4578 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4579 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4580 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4583 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4584 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4585 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4587 case RELOAD_FOR_INPUT_ADDRESS:
4588 case RELOAD_FOR_INPADDR_ADDRESS:
4589 /* Similar, except that we check only for this and subsequent inputs
4590 and the address of only subsequent inputs and we do not need
4591 to check for RELOAD_OTHER objects since they are known not to
4594 for (i = opnum; i < reload_n_operands; i++)
4595 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4598 for (i = opnum + 1; i < reload_n_operands; i++)
4599 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4600 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4603 for (i = 0; i < reload_n_operands; i++)
4604 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4605 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4606 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4609 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4612 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4613 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4614 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4616 case RELOAD_FOR_INPUT:
4617 /* Similar to input address, except we start at the next operand for
4618 both input and input address and we do not check for
4619 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4622 for (i = opnum + 1; i < reload_n_operands; i++)
4623 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4624 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4625 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4628 /* ... fall through ... */
4630 case RELOAD_FOR_OPERAND_ADDRESS:
4631 /* Check outputs and their addresses. */
4633 for (i = 0; i < reload_n_operands; i++)
4634 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4635 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4636 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4639 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4641 case RELOAD_FOR_OPADDR_ADDR:
4642 for (i = 0; i < reload_n_operands; i++)
4643 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4644 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4645 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4648 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4649 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4650 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4652 case RELOAD_FOR_INSN:
4653 /* These conflict with other outputs with RELOAD_OTHER. So
4654 we need only check for output addresses. */
4656 opnum = reload_n_operands;
4658 /* ... fall through ... */
4660 case RELOAD_FOR_OUTPUT:
4661 case RELOAD_FOR_OUTPUT_ADDRESS:
4662 case RELOAD_FOR_OUTADDR_ADDRESS:
4663 /* We already know these can't conflict with a later output. So the
4664 only thing to check are later output addresses.
4665 Note that multiple output operands are emitted in reverse order,
4666 so the conflicting ones are those with lower indices. */
4667 for (i = 0; i < opnum; i++)
4668 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4669 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4678 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4681 This function uses the same algorithm as reload_reg_free_p above. */
4684 reloads_conflict (r1, r2)
4687 enum reload_type r1_type = rld[r1].when_needed;
4688 enum reload_type r2_type = rld[r2].when_needed;
4689 int r1_opnum = rld[r1].opnum;
4690 int r2_opnum = rld[r2].opnum;
4692 /* RELOAD_OTHER conflicts with everything. */
4693 if (r2_type == RELOAD_OTHER)
4696 /* Otherwise, check conflicts differently for each type. */
4700 case RELOAD_FOR_INPUT:
4701 return (r2_type == RELOAD_FOR_INSN
4702 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4703 || r2_type == RELOAD_FOR_OPADDR_ADDR
4704 || r2_type == RELOAD_FOR_INPUT
4705 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4706 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4707 && r2_opnum > r1_opnum));
4709 case RELOAD_FOR_INPUT_ADDRESS:
4710 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4711 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4713 case RELOAD_FOR_INPADDR_ADDRESS:
4714 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4715 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4717 case RELOAD_FOR_OUTPUT_ADDRESS:
4718 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4719 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4721 case RELOAD_FOR_OUTADDR_ADDRESS:
4722 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4723 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4725 case RELOAD_FOR_OPERAND_ADDRESS:
4726 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4727 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4729 case RELOAD_FOR_OPADDR_ADDR:
4730 return (r2_type == RELOAD_FOR_INPUT
4731 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4733 case RELOAD_FOR_OUTPUT:
4734 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4735 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4736 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4737 && r2_opnum >= r1_opnum));
4739 case RELOAD_FOR_INSN:
4740 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4741 || r2_type == RELOAD_FOR_INSN
4742 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4744 case RELOAD_FOR_OTHER_ADDRESS:
4745 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4755 /* Indexed by reload number, 1 if incoming value
4756 inherited from previous insns. */
4757 char reload_inherited[MAX_RELOADS];
4759 /* For an inherited reload, this is the insn the reload was inherited from,
4760 if we know it. Otherwise, this is 0. */
4761 rtx reload_inheritance_insn[MAX_RELOADS];
4763 /* If nonzero, this is a place to get the value of the reload,
4764 rather than using reload_in. */
4765 rtx reload_override_in[MAX_RELOADS];
4767 /* For each reload, the hard register number of the register used,
4768 or -1 if we did not need a register for this reload. */
4769 int reload_spill_index[MAX_RELOADS];
4771 /* Subroutine of free_for_value_p, used to check a single register.
4772 START_REGNO is the starting regno of the full reload register
4773 (possibly comprising multiple hard registers) that we are considering. */
4776 reload_reg_free_for_value_p (start_regno, regno, opnum, type, value, out,
4777 reloadnum, ignore_address_reloads)
4778 int start_regno, regno;
4780 enum reload_type type;
4783 int ignore_address_reloads;
4786 /* Set if we see an input reload that must not share its reload register
4787 with any new earlyclobber, but might otherwise share the reload
4788 register with an output or input-output reload. */
4789 int check_earlyclobber = 0;
4793 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4796 if (out == const0_rtx)
4802 /* We use some pseudo 'time' value to check if the lifetimes of the
4803 new register use would overlap with the one of a previous reload
4804 that is not read-only or uses a different value.
4805 The 'time' used doesn't have to be linear in any shape or form, just
4807 Some reload types use different 'buckets' for each operand.
4808 So there are MAX_RECOG_OPERANDS different time values for each
4810 We compute TIME1 as the time when the register for the prospective
4811 new reload ceases to be live, and TIME2 for each existing
4812 reload as the time when that the reload register of that reload
4814 Where there is little to be gained by exact lifetime calculations,
4815 we just make conservative assumptions, i.e. a longer lifetime;
4816 this is done in the 'default:' cases. */
4819 case RELOAD_FOR_OTHER_ADDRESS:
4820 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4821 time1 = copy ? 0 : 1;
4824 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4826 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4827 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4828 respectively, to the time values for these, we get distinct time
4829 values. To get distinct time values for each operand, we have to
4830 multiply opnum by at least three. We round that up to four because
4831 multiply by four is often cheaper. */
4832 case RELOAD_FOR_INPADDR_ADDRESS:
4833 time1 = opnum * 4 + 2;
4835 case RELOAD_FOR_INPUT_ADDRESS:
4836 time1 = opnum * 4 + 3;
4838 case RELOAD_FOR_INPUT:
4839 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4840 executes (inclusive). */
4841 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4843 case RELOAD_FOR_OPADDR_ADDR:
4845 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4846 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4848 case RELOAD_FOR_OPERAND_ADDRESS:
4849 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4851 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4853 case RELOAD_FOR_OUTADDR_ADDRESS:
4854 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4856 case RELOAD_FOR_OUTPUT_ADDRESS:
4857 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4860 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4863 for (i = 0; i < n_reloads; i++)
4865 rtx reg = rld[i].reg_rtx;
4866 if (reg && GET_CODE (reg) == REG
4867 && ((unsigned) regno - true_regnum (reg)
4868 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned) 1)
4871 rtx other_input = rld[i].in;
4873 /* If the other reload loads the same input value, that
4874 will not cause a conflict only if it's loading it into
4875 the same register. */
4876 if (true_regnum (reg) != start_regno)
4877 other_input = NULL_RTX;
4878 if (! other_input || ! rtx_equal_p (other_input, value)
4879 || rld[i].out || out)
4882 switch (rld[i].when_needed)
4884 case RELOAD_FOR_OTHER_ADDRESS:
4887 case RELOAD_FOR_INPADDR_ADDRESS:
4888 /* find_reloads makes sure that a
4889 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4890 by at most one - the first -
4891 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4892 address reload is inherited, the address address reload
4893 goes away, so we can ignore this conflict. */
4894 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4895 && ignore_address_reloads
4896 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4897 Then the address address is still needed to store
4898 back the new address. */
4899 && ! rld[reloadnum].out)
4901 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4902 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4904 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4905 && ignore_address_reloads
4906 /* Unless we are reloading an auto_inc expression. */
4907 && ! rld[reloadnum].out)
4909 time2 = rld[i].opnum * 4 + 2;
4911 case RELOAD_FOR_INPUT_ADDRESS:
4912 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4913 && ignore_address_reloads
4914 && ! rld[reloadnum].out)
4916 time2 = rld[i].opnum * 4 + 3;
4918 case RELOAD_FOR_INPUT:
4919 time2 = rld[i].opnum * 4 + 4;
4920 check_earlyclobber = 1;
4922 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4923 == MAX_RECOG_OPERAND * 4 */
4924 case RELOAD_FOR_OPADDR_ADDR:
4925 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4926 && ignore_address_reloads
4927 && ! rld[reloadnum].out)
4929 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4931 case RELOAD_FOR_OPERAND_ADDRESS:
4932 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4933 check_earlyclobber = 1;
4935 case RELOAD_FOR_INSN:
4936 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4938 case RELOAD_FOR_OUTPUT:
4939 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4940 instruction is executed. */
4941 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4943 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4944 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4946 case RELOAD_FOR_OUTADDR_ADDRESS:
4947 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4948 && ignore_address_reloads
4949 && ! rld[reloadnum].out)
4951 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4953 case RELOAD_FOR_OUTPUT_ADDRESS:
4954 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4957 /* If there is no conflict in the input part, handle this
4958 like an output reload. */
4959 if (! rld[i].in || rtx_equal_p (other_input, value))
4961 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4962 /* Earlyclobbered outputs must conflict with inputs. */
4963 if (earlyclobber_operand_p (rld[i].out))
4964 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4969 /* RELOAD_OTHER might be live beyond instruction execution,
4970 but this is not obvious when we set time2 = 1. So check
4971 here if there might be a problem with the new reload
4972 clobbering the register used by the RELOAD_OTHER. */
4980 && (! rld[i].in || rld[i].out
4981 || ! rtx_equal_p (other_input, value)))
4982 || (out && rld[reloadnum].out_reg
4983 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4989 /* Earlyclobbered outputs must conflict with inputs. */
4990 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4996 /* Return 1 if the value in reload reg REGNO, as used by a reload
4997 needed for the part of the insn specified by OPNUM and TYPE,
4998 may be used to load VALUE into it.
5000 MODE is the mode in which the register is used, this is needed to
5001 determine how many hard regs to test.
5003 Other read-only reloads with the same value do not conflict
5004 unless OUT is nonzero and these other reloads have to live while
5005 output reloads live.
5006 If OUT is CONST0_RTX, this is a special case: it means that the
5007 test should not be for using register REGNO as reload register, but
5008 for copying from register REGNO into the reload register.
5010 RELOADNUM is the number of the reload we want to load this value for;
5011 a reload does not conflict with itself.
5013 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5014 reloads that load an address for the very reload we are considering.
5016 The caller has to make sure that there is no conflict with the return
5020 free_for_value_p (regno, mode, opnum, type, value, out, reloadnum,
5021 ignore_address_reloads)
5023 enum machine_mode mode;
5025 enum reload_type type;
5028 int ignore_address_reloads;
5030 int nregs = HARD_REGNO_NREGS (regno, mode);
5032 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5033 value, out, reloadnum,
5034 ignore_address_reloads))
5039 /* Determine whether the reload reg X overlaps any rtx'es used for
5040 overriding inheritance. Return nonzero if so. */
5043 conflicts_with_override (x)
5047 for (i = 0; i < n_reloads; i++)
5048 if (reload_override_in[i]
5049 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5054 /* Give an error message saying we failed to find a reload for INSN,
5055 and clear out reload R. */
5057 failed_reload (insn, r)
5061 if (asm_noperands (PATTERN (insn)) < 0)
5062 /* It's the compiler's fault. */
5063 fatal_insn ("could not find a spill register", insn);
5065 /* It's the user's fault; the operand's mode and constraint
5066 don't match. Disable this reload so we don't crash in final. */
5067 error_for_asm (insn,
5068 "`asm' operand constraint incompatible with operand size");
5072 rld[r].optional = 1;
5073 rld[r].secondary_p = 1;
5076 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5077 for reload R. If it's valid, get an rtx for it. Return nonzero if
5080 set_reload_reg (i, r)
5084 rtx reg = spill_reg_rtx[i];
5086 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5087 spill_reg_rtx[i] = reg
5088 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5090 regno = true_regnum (reg);
5092 /* Detect when the reload reg can't hold the reload mode.
5093 This used to be one `if', but Sequent compiler can't handle that. */
5094 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5096 enum machine_mode test_mode = VOIDmode;
5098 test_mode = GET_MODE (rld[r].in);
5099 /* If rld[r].in has VOIDmode, it means we will load it
5100 in whatever mode the reload reg has: to wit, rld[r].mode.
5101 We have already tested that for validity. */
5102 /* Aside from that, we need to test that the expressions
5103 to reload from or into have modes which are valid for this
5104 reload register. Otherwise the reload insns would be invalid. */
5105 if (! (rld[r].in != 0 && test_mode != VOIDmode
5106 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5107 if (! (rld[r].out != 0
5108 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5110 /* The reg is OK. */
5113 /* Mark as in use for this insn the reload regs we use
5115 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5116 rld[r].when_needed, rld[r].mode);
5118 rld[r].reg_rtx = reg;
5119 reload_spill_index[r] = spill_regs[i];
5126 /* Find a spill register to use as a reload register for reload R.
5127 LAST_RELOAD is nonzero if this is the last reload for the insn being
5130 Set rld[R].reg_rtx to the register allocated.
5132 We return 1 if successful, or 0 if we couldn't find a spill reg and
5133 we didn't change anything. */
5136 allocate_reload_reg (chain, r, last_reload)
5137 struct insn_chain *chain ATTRIBUTE_UNUSED;
5143 /* If we put this reload ahead, thinking it is a group,
5144 then insist on finding a group. Otherwise we can grab a
5145 reg that some other reload needs.
5146 (That can happen when we have a 68000 DATA_OR_FP_REG
5147 which is a group of data regs or one fp reg.)
5148 We need not be so restrictive if there are no more reloads
5151 ??? Really it would be nicer to have smarter handling
5152 for that kind of reg class, where a problem like this is normal.
5153 Perhaps those classes should be avoided for reloading
5154 by use of more alternatives. */
5156 int force_group = rld[r].nregs > 1 && ! last_reload;
5158 /* If we want a single register and haven't yet found one,
5159 take any reg in the right class and not in use.
5160 If we want a consecutive group, here is where we look for it.
5162 We use two passes so we can first look for reload regs to
5163 reuse, which are already in use for other reloads in this insn,
5164 and only then use additional registers.
5165 I think that maximizing reuse is needed to make sure we don't
5166 run out of reload regs. Suppose we have three reloads, and
5167 reloads A and B can share regs. These need two regs.
5168 Suppose A and B are given different regs.
5169 That leaves none for C. */
5170 for (pass = 0; pass < 2; pass++)
5172 /* I is the index in spill_regs.
5173 We advance it round-robin between insns to use all spill regs
5174 equally, so that inherited reloads have a chance
5175 of leapfrogging each other. */
5179 for (count = 0; count < n_spills; count++)
5181 int class = (int) rld[r].class;
5187 regnum = spill_regs[i];
5189 if ((reload_reg_free_p (regnum, rld[r].opnum,
5192 /* We check reload_reg_used to make sure we
5193 don't clobber the return register. */
5194 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5195 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5196 rld[r].when_needed, rld[r].in,
5198 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5199 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5200 /* Look first for regs to share, then for unshared. But
5201 don't share regs used for inherited reloads; they are
5202 the ones we want to preserve. */
5204 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5206 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5209 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5210 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5211 (on 68000) got us two FP regs. If NR is 1,
5212 we would reject both of them. */
5215 /* If we need only one reg, we have already won. */
5218 /* But reject a single reg if we demand a group. */
5223 /* Otherwise check that as many consecutive regs as we need
5224 are available here. */
5227 int regno = regnum + nr - 1;
5228 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5229 && spill_reg_order[regno] >= 0
5230 && reload_reg_free_p (regno, rld[r].opnum,
5231 rld[r].when_needed)))
5240 /* If we found something on pass 1, omit pass 2. */
5241 if (count < n_spills)
5245 /* We should have found a spill register by now. */
5246 if (count >= n_spills)
5249 /* I is the index in SPILL_REG_RTX of the reload register we are to
5250 allocate. Get an rtx for it and find its register number. */
5252 return set_reload_reg (i, r);
5255 /* Initialize all the tables needed to allocate reload registers.
5256 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5257 is the array we use to restore the reg_rtx field for every reload. */
5260 choose_reload_regs_init (chain, save_reload_reg_rtx)
5261 struct insn_chain *chain;
5262 rtx *save_reload_reg_rtx;
5266 for (i = 0; i < n_reloads; i++)
5267 rld[i].reg_rtx = save_reload_reg_rtx[i];
5269 memset (reload_inherited, 0, MAX_RELOADS);
5270 memset ((char *) reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5271 memset ((char *) reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5273 CLEAR_HARD_REG_SET (reload_reg_used);
5274 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5275 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5276 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5277 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5278 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5280 CLEAR_HARD_REG_SET (reg_used_in_insn);
5283 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5284 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5285 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5286 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5287 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5288 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5291 for (i = 0; i < reload_n_operands; i++)
5293 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5294 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5295 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5296 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5297 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5298 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5301 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5303 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5305 for (i = 0; i < n_reloads; i++)
5306 /* If we have already decided to use a certain register,
5307 don't use it in another way. */
5309 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5310 rld[i].when_needed, rld[i].mode);
5313 /* Assign hard reg targets for the pseudo-registers we must reload
5314 into hard regs for this insn.
5315 Also output the instructions to copy them in and out of the hard regs.
5317 For machines with register classes, we are responsible for
5318 finding a reload reg in the proper class. */
5321 choose_reload_regs (chain)
5322 struct insn_chain *chain;
5324 rtx insn = chain->insn;
5326 unsigned int max_group_size = 1;
5327 enum reg_class group_class = NO_REGS;
5328 int pass, win, inheritance;
5330 rtx save_reload_reg_rtx[MAX_RELOADS];
5332 /* In order to be certain of getting the registers we need,
5333 we must sort the reloads into order of increasing register class.
5334 Then our grabbing of reload registers will parallel the process
5335 that provided the reload registers.
5337 Also note whether any of the reloads wants a consecutive group of regs.
5338 If so, record the maximum size of the group desired and what
5339 register class contains all the groups needed by this insn. */
5341 for (j = 0; j < n_reloads; j++)
5343 reload_order[j] = j;
5344 reload_spill_index[j] = -1;
5346 if (rld[j].nregs > 1)
5348 max_group_size = MAX (rld[j].nregs, max_group_size);
5350 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5353 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5357 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5359 /* If -O, try first with inheritance, then turning it off.
5360 If not -O, don't do inheritance.
5361 Using inheritance when not optimizing leads to paradoxes
5362 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5363 because one side of the comparison might be inherited. */
5365 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5367 choose_reload_regs_init (chain, save_reload_reg_rtx);
5369 /* Process the reloads in order of preference just found.
5370 Beyond this point, subregs can be found in reload_reg_rtx.
5372 This used to look for an existing reloaded home for all of the
5373 reloads, and only then perform any new reloads. But that could lose
5374 if the reloads were done out of reg-class order because a later
5375 reload with a looser constraint might have an old home in a register
5376 needed by an earlier reload with a tighter constraint.
5378 To solve this, we make two passes over the reloads, in the order
5379 described above. In the first pass we try to inherit a reload
5380 from a previous insn. If there is a later reload that needs a
5381 class that is a proper subset of the class being processed, we must
5382 also allocate a spill register during the first pass.
5384 Then make a second pass over the reloads to allocate any reloads
5385 that haven't been given registers yet. */
5387 for (j = 0; j < n_reloads; j++)
5389 int r = reload_order[j];
5390 rtx search_equiv = NULL_RTX;
5392 /* Ignore reloads that got marked inoperative. */
5393 if (rld[r].out == 0 && rld[r].in == 0
5394 && ! rld[r].secondary_p)
5397 /* If find_reloads chose to use reload_in or reload_out as a reload
5398 register, we don't need to chose one. Otherwise, try even if it
5399 found one since we might save an insn if we find the value lying
5401 Try also when reload_in is a pseudo without a hard reg. */
5402 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5403 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5404 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5405 && GET_CODE (rld[r].in) != MEM
5406 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5409 #if 0 /* No longer needed for correct operation.
5410 It might give better code, or might not; worth an experiment? */
5411 /* If this is an optional reload, we can't inherit from earlier insns
5412 until we are sure that any non-optional reloads have been allocated.
5413 The following code takes advantage of the fact that optional reloads
5414 are at the end of reload_order. */
5415 if (rld[r].optional != 0)
5416 for (i = 0; i < j; i++)
5417 if ((rld[reload_order[i]].out != 0
5418 || rld[reload_order[i]].in != 0
5419 || rld[reload_order[i]].secondary_p)
5420 && ! rld[reload_order[i]].optional
5421 && rld[reload_order[i]].reg_rtx == 0)
5422 allocate_reload_reg (chain, reload_order[i], 0);
5425 /* First see if this pseudo is already available as reloaded
5426 for a previous insn. We cannot try to inherit for reloads
5427 that are smaller than the maximum number of registers needed
5428 for groups unless the register we would allocate cannot be used
5431 We could check here to see if this is a secondary reload for
5432 an object that is already in a register of the desired class.
5433 This would avoid the need for the secondary reload register.
5434 But this is complex because we can't easily determine what
5435 objects might want to be loaded via this reload. So let a
5436 register be allocated here. In `emit_reload_insns' we suppress
5437 one of the loads in the case described above. */
5443 enum machine_mode mode = VOIDmode;
5447 else if (GET_CODE (rld[r].in) == REG)
5449 regno = REGNO (rld[r].in);
5450 mode = GET_MODE (rld[r].in);
5452 else if (GET_CODE (rld[r].in_reg) == REG)
5454 regno = REGNO (rld[r].in_reg);
5455 mode = GET_MODE (rld[r].in_reg);
5457 else if (GET_CODE (rld[r].in_reg) == SUBREG
5458 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5460 byte = SUBREG_BYTE (rld[r].in_reg);
5461 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5462 if (regno < FIRST_PSEUDO_REGISTER)
5463 regno = subreg_regno (rld[r].in_reg);
5464 mode = GET_MODE (rld[r].in_reg);
5467 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5468 || GET_CODE (rld[r].in_reg) == PRE_DEC
5469 || GET_CODE (rld[r].in_reg) == POST_INC
5470 || GET_CODE (rld[r].in_reg) == POST_DEC)
5471 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5473 regno = REGNO (XEXP (rld[r].in_reg, 0));
5474 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5475 rld[r].out = rld[r].in;
5479 /* This won't work, since REGNO can be a pseudo reg number.
5480 Also, it takes much more hair to keep track of all the things
5481 that can invalidate an inherited reload of part of a pseudoreg. */
5482 else if (GET_CODE (rld[r].in) == SUBREG
5483 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5484 regno = subreg_regno (rld[r].in);
5487 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5489 enum reg_class class = rld[r].class, last_class;
5490 rtx last_reg = reg_last_reload_reg[regno];
5491 enum machine_mode need_mode;
5493 i = REGNO (last_reg);
5494 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5495 last_class = REGNO_REG_CLASS (i);
5501 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5502 GET_MODE_CLASS (mode));
5505 #ifdef CANNOT_CHANGE_MODE_CLASS
5506 (!REG_CANNOT_CHANGE_MODE_P (i, GET_MODE (last_reg),
5510 (GET_MODE_SIZE (GET_MODE (last_reg))
5511 >= GET_MODE_SIZE (need_mode))
5512 #ifdef CANNOT_CHANGE_MODE_CLASS
5515 && reg_reloaded_contents[i] == regno
5516 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5517 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5518 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5519 /* Even if we can't use this register as a reload
5520 register, we might use it for reload_override_in,
5521 if copying it to the desired class is cheap
5523 || ((REGISTER_MOVE_COST (mode, last_class, class)
5524 < MEMORY_MOVE_COST (mode, class, 1))
5525 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5526 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5530 #ifdef SECONDARY_MEMORY_NEEDED
5531 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5536 && (rld[r].nregs == max_group_size
5537 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5539 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5540 rld[r].when_needed, rld[r].in,
5543 /* If a group is needed, verify that all the subsequent
5544 registers still have their values intact. */
5545 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5548 for (k = 1; k < nr; k++)
5549 if (reg_reloaded_contents[i + k] != regno
5550 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5558 last_reg = (GET_MODE (last_reg) == mode
5559 ? last_reg : gen_rtx_REG (mode, i));
5562 for (k = 0; k < nr; k++)
5563 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5566 /* We found a register that contains the
5567 value we need. If this register is the
5568 same as an `earlyclobber' operand of the
5569 current insn, just mark it as a place to
5570 reload from since we can't use it as the
5571 reload register itself. */
5573 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5574 if (reg_overlap_mentioned_for_reload_p
5575 (reg_last_reload_reg[regno],
5576 reload_earlyclobbers[i1]))
5579 if (i1 != n_earlyclobbers
5580 || ! (free_for_value_p (i, rld[r].mode,
5582 rld[r].when_needed, rld[r].in,
5584 /* Don't use it if we'd clobber a pseudo reg. */
5585 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5587 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5588 /* Don't clobber the frame pointer. */
5589 || (i == HARD_FRAME_POINTER_REGNUM
5590 && frame_pointer_needed
5592 /* Don't really use the inherited spill reg
5593 if we need it wider than we've got it. */
5594 || (GET_MODE_SIZE (rld[r].mode)
5595 > GET_MODE_SIZE (mode))
5598 /* If find_reloads chose reload_out as reload
5599 register, stay with it - that leaves the
5600 inherited register for subsequent reloads. */
5601 || (rld[r].out && rld[r].reg_rtx
5602 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5604 if (! rld[r].optional)
5606 reload_override_in[r] = last_reg;
5607 reload_inheritance_insn[r]
5608 = reg_reloaded_insn[i];
5614 /* We can use this as a reload reg. */
5615 /* Mark the register as in use for this part of
5617 mark_reload_reg_in_use (i,
5621 rld[r].reg_rtx = last_reg;
5622 reload_inherited[r] = 1;
5623 reload_inheritance_insn[r]
5624 = reg_reloaded_insn[i];
5625 reload_spill_index[r] = i;
5626 for (k = 0; k < nr; k++)
5627 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5635 /* Here's another way to see if the value is already lying around. */
5638 && ! reload_inherited[r]
5640 && (CONSTANT_P (rld[r].in)
5641 || GET_CODE (rld[r].in) == PLUS
5642 || GET_CODE (rld[r].in) == REG
5643 || GET_CODE (rld[r].in) == MEM)
5644 && (rld[r].nregs == max_group_size
5645 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5646 search_equiv = rld[r].in;
5647 /* If this is an output reload from a simple move insn, look
5648 if an equivalence for the input is available. */
5649 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5651 rtx set = single_set (insn);
5654 && rtx_equal_p (rld[r].out, SET_DEST (set))
5655 && CONSTANT_P (SET_SRC (set)))
5656 search_equiv = SET_SRC (set);
5662 = find_equiv_reg (search_equiv, insn, rld[r].class,
5663 -1, NULL, 0, rld[r].mode);
5668 if (GET_CODE (equiv) == REG)
5669 regno = REGNO (equiv);
5670 else if (GET_CODE (equiv) == SUBREG)
5672 /* This must be a SUBREG of a hard register.
5673 Make a new REG since this might be used in an
5674 address and not all machines support SUBREGs
5676 regno = subreg_regno (equiv);
5677 equiv = gen_rtx_REG (rld[r].mode, regno);
5683 /* If we found a spill reg, reject it unless it is free
5684 and of the desired class. */
5686 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5687 && ! free_for_value_p (regno, rld[r].mode,
5688 rld[r].opnum, rld[r].when_needed,
5689 rld[r].in, rld[r].out, r, 1))
5690 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5694 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5697 /* We found a register that contains the value we need.
5698 If this register is the same as an `earlyclobber' operand
5699 of the current insn, just mark it as a place to reload from
5700 since we can't use it as the reload register itself. */
5703 for (i = 0; i < n_earlyclobbers; i++)
5704 if (reg_overlap_mentioned_for_reload_p (equiv,
5705 reload_earlyclobbers[i]))
5707 if (! rld[r].optional)
5708 reload_override_in[r] = equiv;
5713 /* If the equiv register we have found is explicitly clobbered
5714 in the current insn, it depends on the reload type if we
5715 can use it, use it for reload_override_in, or not at all.
5716 In particular, we then can't use EQUIV for a
5717 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5721 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5722 switch (rld[r].when_needed)
5724 case RELOAD_FOR_OTHER_ADDRESS:
5725 case RELOAD_FOR_INPADDR_ADDRESS:
5726 case RELOAD_FOR_INPUT_ADDRESS:
5727 case RELOAD_FOR_OPADDR_ADDR:
5730 case RELOAD_FOR_INPUT:
5731 case RELOAD_FOR_OPERAND_ADDRESS:
5732 if (! rld[r].optional)
5733 reload_override_in[r] = equiv;
5739 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5740 switch (rld[r].when_needed)
5742 case RELOAD_FOR_OTHER_ADDRESS:
5743 case RELOAD_FOR_INPADDR_ADDRESS:
5744 case RELOAD_FOR_INPUT_ADDRESS:
5745 case RELOAD_FOR_OPADDR_ADDR:
5746 case RELOAD_FOR_OPERAND_ADDRESS:
5747 case RELOAD_FOR_INPUT:
5750 if (! rld[r].optional)
5751 reload_override_in[r] = equiv;
5759 /* If we found an equivalent reg, say no code need be generated
5760 to load it, and use it as our reload reg. */
5762 && (regno != HARD_FRAME_POINTER_REGNUM
5763 || !frame_pointer_needed))
5765 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5767 rld[r].reg_rtx = equiv;
5768 reload_inherited[r] = 1;
5770 /* If reg_reloaded_valid is not set for this register,
5771 there might be a stale spill_reg_store lying around.
5772 We must clear it, since otherwise emit_reload_insns
5773 might delete the store. */
5774 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5775 spill_reg_store[regno] = NULL_RTX;
5776 /* If any of the hard registers in EQUIV are spill
5777 registers, mark them as in use for this insn. */
5778 for (k = 0; k < nr; k++)
5780 i = spill_reg_order[regno + k];
5783 mark_reload_reg_in_use (regno, rld[r].opnum,
5786 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5793 /* If we found a register to use already, or if this is an optional
5794 reload, we are done. */
5795 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5799 /* No longer needed for correct operation. Might or might
5800 not give better code on the average. Want to experiment? */
5802 /* See if there is a later reload that has a class different from our
5803 class that intersects our class or that requires less register
5804 than our reload. If so, we must allocate a register to this
5805 reload now, since that reload might inherit a previous reload
5806 and take the only available register in our class. Don't do this
5807 for optional reloads since they will force all previous reloads
5808 to be allocated. Also don't do this for reloads that have been
5811 for (i = j + 1; i < n_reloads; i++)
5813 int s = reload_order[i];
5815 if ((rld[s].in == 0 && rld[s].out == 0
5816 && ! rld[s].secondary_p)
5820 if ((rld[s].class != rld[r].class
5821 && reg_classes_intersect_p (rld[r].class,
5823 || rld[s].nregs < rld[r].nregs)
5830 allocate_reload_reg (chain, r, j == n_reloads - 1);
5834 /* Now allocate reload registers for anything non-optional that
5835 didn't get one yet. */
5836 for (j = 0; j < n_reloads; j++)
5838 int r = reload_order[j];
5840 /* Ignore reloads that got marked inoperative. */
5841 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5844 /* Skip reloads that already have a register allocated or are
5846 if (rld[r].reg_rtx != 0 || rld[r].optional)
5849 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5853 /* If that loop got all the way, we have won. */
5860 /* Loop around and try without any inheritance. */
5865 /* First undo everything done by the failed attempt
5866 to allocate with inheritance. */
5867 choose_reload_regs_init (chain, save_reload_reg_rtx);
5869 /* Some sanity tests to verify that the reloads found in the first
5870 pass are identical to the ones we have now. */
5871 if (chain->n_reloads != n_reloads)
5874 for (i = 0; i < n_reloads; i++)
5876 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5878 if (chain->rld[i].when_needed != rld[i].when_needed)
5880 for (j = 0; j < n_spills; j++)
5881 if (spill_regs[j] == chain->rld[i].regno)
5882 if (! set_reload_reg (j, i))
5883 failed_reload (chain->insn, i);
5887 /* If we thought we could inherit a reload, because it seemed that
5888 nothing else wanted the same reload register earlier in the insn,
5889 verify that assumption, now that all reloads have been assigned.
5890 Likewise for reloads where reload_override_in has been set. */
5892 /* If doing expensive optimizations, do one preliminary pass that doesn't
5893 cancel any inheritance, but removes reloads that have been needed only
5894 for reloads that we know can be inherited. */
5895 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5897 for (j = 0; j < n_reloads; j++)
5899 int r = reload_order[j];
5901 if (reload_inherited[r] && rld[r].reg_rtx)
5902 check_reg = rld[r].reg_rtx;
5903 else if (reload_override_in[r]
5904 && (GET_CODE (reload_override_in[r]) == REG
5905 || GET_CODE (reload_override_in[r]) == SUBREG))
5906 check_reg = reload_override_in[r];
5909 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5910 rld[r].opnum, rld[r].when_needed, rld[r].in,
5911 (reload_inherited[r]
5912 ? rld[r].out : const0_rtx),
5917 reload_inherited[r] = 0;
5918 reload_override_in[r] = 0;
5920 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5921 reload_override_in, then we do not need its related
5922 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5923 likewise for other reload types.
5924 We handle this by removing a reload when its only replacement
5925 is mentioned in reload_in of the reload we are going to inherit.
5926 A special case are auto_inc expressions; even if the input is
5927 inherited, we still need the address for the output. We can
5928 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5929 If we succeeded removing some reload and we are doing a preliminary
5930 pass just to remove such reloads, make another pass, since the
5931 removal of one reload might allow us to inherit another one. */
5933 && rld[r].out != rld[r].in
5934 && remove_address_replacements (rld[r].in) && pass)
5939 /* Now that reload_override_in is known valid,
5940 actually override reload_in. */
5941 for (j = 0; j < n_reloads; j++)
5942 if (reload_override_in[j])
5943 rld[j].in = reload_override_in[j];
5945 /* If this reload won't be done because it has been canceled or is
5946 optional and not inherited, clear reload_reg_rtx so other
5947 routines (such as subst_reloads) don't get confused. */
5948 for (j = 0; j < n_reloads; j++)
5949 if (rld[j].reg_rtx != 0
5950 && ((rld[j].optional && ! reload_inherited[j])
5951 || (rld[j].in == 0 && rld[j].out == 0
5952 && ! rld[j].secondary_p)))
5954 int regno = true_regnum (rld[j].reg_rtx);
5956 if (spill_reg_order[regno] >= 0)
5957 clear_reload_reg_in_use (regno, rld[j].opnum,
5958 rld[j].when_needed, rld[j].mode);
5960 reload_spill_index[j] = -1;
5963 /* Record which pseudos and which spill regs have output reloads. */
5964 for (j = 0; j < n_reloads; j++)
5966 int r = reload_order[j];
5968 i = reload_spill_index[r];
5970 /* I is nonneg if this reload uses a register.
5971 If rld[r].reg_rtx is 0, this is an optional reload
5972 that we opted to ignore. */
5973 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5974 && rld[r].reg_rtx != 0)
5976 int nregno = REGNO (rld[r].out_reg);
5979 if (nregno < FIRST_PSEUDO_REGISTER)
5980 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5983 reg_has_output_reload[nregno + nr] = 1;
5987 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5989 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5992 if (rld[r].when_needed != RELOAD_OTHER
5993 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5994 && rld[r].when_needed != RELOAD_FOR_INSN)
6000 /* Deallocate the reload register for reload R. This is called from
6001 remove_address_replacements. */
6004 deallocate_reload_reg (r)
6009 if (! rld[r].reg_rtx)
6011 regno = true_regnum (rld[r].reg_rtx);
6013 if (spill_reg_order[regno] >= 0)
6014 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6016 reload_spill_index[r] = -1;
6019 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6020 reloads of the same item for fear that we might not have enough reload
6021 registers. However, normally they will get the same reload register
6022 and hence actually need not be loaded twice.
6024 Here we check for the most common case of this phenomenon: when we have
6025 a number of reloads for the same object, each of which were allocated
6026 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6027 reload, and is not modified in the insn itself. If we find such,
6028 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6029 This will not increase the number of spill registers needed and will
6030 prevent redundant code. */
6033 merge_assigned_reloads (insn)
6038 /* Scan all the reloads looking for ones that only load values and
6039 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6040 assigned and not modified by INSN. */
6042 for (i = 0; i < n_reloads; i++)
6044 int conflicting_input = 0;
6045 int max_input_address_opnum = -1;
6046 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6048 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6049 || rld[i].out != 0 || rld[i].reg_rtx == 0
6050 || reg_set_p (rld[i].reg_rtx, insn))
6053 /* Look at all other reloads. Ensure that the only use of this
6054 reload_reg_rtx is in a reload that just loads the same value
6055 as we do. Note that any secondary reloads must be of the identical
6056 class since the values, modes, and result registers are the
6057 same, so we need not do anything with any secondary reloads. */
6059 for (j = 0; j < n_reloads; j++)
6061 if (i == j || rld[j].reg_rtx == 0
6062 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6066 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6067 && rld[j].opnum > max_input_address_opnum)
6068 max_input_address_opnum = rld[j].opnum;
6070 /* If the reload regs aren't exactly the same (e.g, different modes)
6071 or if the values are different, we can't merge this reload.
6072 But if it is an input reload, we might still merge
6073 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6075 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6076 || rld[j].out != 0 || rld[j].in == 0
6077 || ! rtx_equal_p (rld[i].in, rld[j].in))
6079 if (rld[j].when_needed != RELOAD_FOR_INPUT
6080 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6081 || rld[i].opnum > rld[j].opnum)
6082 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6084 conflicting_input = 1;
6085 if (min_conflicting_input_opnum > rld[j].opnum)
6086 min_conflicting_input_opnum = rld[j].opnum;
6090 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6091 we, in fact, found any matching reloads. */
6094 && max_input_address_opnum <= min_conflicting_input_opnum)
6096 for (j = 0; j < n_reloads; j++)
6097 if (i != j && rld[j].reg_rtx != 0
6098 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6099 && (! conflicting_input
6100 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6101 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6103 rld[i].when_needed = RELOAD_OTHER;
6105 reload_spill_index[j] = -1;
6106 transfer_replacements (i, j);
6109 /* If this is now RELOAD_OTHER, look for any reloads that load
6110 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6111 if they were for inputs, RELOAD_OTHER for outputs. Note that
6112 this test is equivalent to looking for reloads for this operand
6114 /* We must take special care when there are two or more reloads to
6115 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6116 same value or a part of it; we must not change its type if there
6117 is a conflicting input. */
6119 if (rld[i].when_needed == RELOAD_OTHER)
6120 for (j = 0; j < n_reloads; j++)
6122 && rld[j].when_needed != RELOAD_OTHER
6123 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6124 && (! conflicting_input
6125 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6126 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6127 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6133 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6134 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6135 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6137 /* Check to see if we accidentally converted two reloads
6138 that use the same reload register to the same type.
6139 If so, the resulting code won't work, so abort. */
6141 for (k = 0; k < j; k++)
6142 if (rld[k].in != 0 && rld[k].reg_rtx != 0
6143 && rld[k].when_needed == rld[j].when_needed
6144 && rtx_equal_p (rld[k].reg_rtx, rld[j].reg_rtx))
6151 /* These arrays are filled by emit_reload_insns and its subroutines. */
6152 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6153 static rtx other_input_address_reload_insns = 0;
6154 static rtx other_input_reload_insns = 0;
6155 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6156 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6157 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6158 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6159 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6160 static rtx operand_reload_insns = 0;
6161 static rtx other_operand_reload_insns = 0;
6162 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6164 /* Values to be put in spill_reg_store are put here first. */
6165 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6166 static HARD_REG_SET reg_reloaded_died;
6168 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6169 has the number J. OLD contains the value to be used as input. */
6172 emit_input_reload_insns (chain, rl, old, j)
6173 struct insn_chain *chain;
6178 rtx insn = chain->insn;
6179 rtx reloadreg = rl->reg_rtx;
6180 rtx oldequiv_reg = 0;
6183 enum machine_mode mode;
6186 /* Determine the mode to reload in.
6187 This is very tricky because we have three to choose from.
6188 There is the mode the insn operand wants (rl->inmode).
6189 There is the mode of the reload register RELOADREG.
6190 There is the intrinsic mode of the operand, which we could find
6191 by stripping some SUBREGs.
6192 It turns out that RELOADREG's mode is irrelevant:
6193 we can change that arbitrarily.
6195 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6196 then the reload reg may not support QImode moves, so use SImode.
6197 If foo is in memory due to spilling a pseudo reg, this is safe,
6198 because the QImode value is in the least significant part of a
6199 slot big enough for a SImode. If foo is some other sort of
6200 memory reference, then it is impossible to reload this case,
6201 so previous passes had better make sure this never happens.
6203 Then consider a one-word union which has SImode and one of its
6204 members is a float, being fetched as (SUBREG:SF union:SI).
6205 We must fetch that as SFmode because we could be loading into
6206 a float-only register. In this case OLD's mode is correct.
6208 Consider an immediate integer: it has VOIDmode. Here we need
6209 to get a mode from something else.
6211 In some cases, there is a fourth mode, the operand's
6212 containing mode. If the insn specifies a containing mode for
6213 this operand, it overrides all others.
6215 I am not sure whether the algorithm here is always right,
6216 but it does the right things in those cases. */
6218 mode = GET_MODE (old);
6219 if (mode == VOIDmode)
6222 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6223 /* If we need a secondary register for this operation, see if
6224 the value is already in a register in that class. Don't
6225 do this if the secondary register will be used as a scratch
6228 if (rl->secondary_in_reload >= 0
6229 && rl->secondary_in_icode == CODE_FOR_nothing
6232 = find_equiv_reg (old, insn,
6233 rld[rl->secondary_in_reload].class,
6237 /* If reloading from memory, see if there is a register
6238 that already holds the same value. If so, reload from there.
6239 We can pass 0 as the reload_reg_p argument because
6240 any other reload has either already been emitted,
6241 in which case find_equiv_reg will see the reload-insn,
6242 or has yet to be emitted, in which case it doesn't matter
6243 because we will use this equiv reg right away. */
6245 if (oldequiv == 0 && optimize
6246 && (GET_CODE (old) == MEM
6247 || (GET_CODE (old) == REG
6248 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6249 && reg_renumber[REGNO (old)] < 0)))
6250 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6254 unsigned int regno = true_regnum (oldequiv);
6256 /* Don't use OLDEQUIV if any other reload changes it at an
6257 earlier stage of this insn or at this stage. */
6258 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6259 rl->in, const0_rtx, j, 0))
6262 /* If it is no cheaper to copy from OLDEQUIV into the
6263 reload register than it would be to move from memory,
6264 don't use it. Likewise, if we need a secondary register
6268 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6269 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6271 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6272 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6273 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6277 #ifdef SECONDARY_MEMORY_NEEDED
6278 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6286 /* delete_output_reload is only invoked properly if old contains
6287 the original pseudo register. Since this is replaced with a
6288 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6289 find the pseudo in RELOAD_IN_REG. */
6291 && reload_override_in[j]
6292 && GET_CODE (rl->in_reg) == REG)
6299 else if (GET_CODE (oldequiv) == REG)
6300 oldequiv_reg = oldequiv;
6301 else if (GET_CODE (oldequiv) == SUBREG)
6302 oldequiv_reg = SUBREG_REG (oldequiv);
6304 /* If we are reloading from a register that was recently stored in
6305 with an output-reload, see if we can prove there was
6306 actually no need to store the old value in it. */
6308 if (optimize && GET_CODE (oldequiv) == REG
6309 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6310 && spill_reg_store[REGNO (oldequiv)]
6311 && GET_CODE (old) == REG
6312 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6313 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6315 delete_output_reload (insn, j, REGNO (oldequiv));
6317 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6318 then load RELOADREG from OLDEQUIV. Note that we cannot use
6319 gen_lowpart_common since it can do the wrong thing when
6320 RELOADREG has a multi-word mode. Note that RELOADREG
6321 must always be a REG here. */
6323 if (GET_MODE (reloadreg) != mode)
6324 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6325 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6326 oldequiv = SUBREG_REG (oldequiv);
6327 if (GET_MODE (oldequiv) != VOIDmode
6328 && mode != GET_MODE (oldequiv))
6329 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6331 /* Switch to the right place to emit the reload insns. */
6332 switch (rl->when_needed)
6335 where = &other_input_reload_insns;
6337 case RELOAD_FOR_INPUT:
6338 where = &input_reload_insns[rl->opnum];
6340 case RELOAD_FOR_INPUT_ADDRESS:
6341 where = &input_address_reload_insns[rl->opnum];
6343 case RELOAD_FOR_INPADDR_ADDRESS:
6344 where = &inpaddr_address_reload_insns[rl->opnum];
6346 case RELOAD_FOR_OUTPUT_ADDRESS:
6347 where = &output_address_reload_insns[rl->opnum];
6349 case RELOAD_FOR_OUTADDR_ADDRESS:
6350 where = &outaddr_address_reload_insns[rl->opnum];
6352 case RELOAD_FOR_OPERAND_ADDRESS:
6353 where = &operand_reload_insns;
6355 case RELOAD_FOR_OPADDR_ADDR:
6356 where = &other_operand_reload_insns;
6358 case RELOAD_FOR_OTHER_ADDRESS:
6359 where = &other_input_address_reload_insns;
6365 push_to_sequence (*where);
6367 /* Auto-increment addresses must be reloaded in a special way. */
6368 if (rl->out && ! rl->out_reg)
6370 /* We are not going to bother supporting the case where a
6371 incremented register can't be copied directly from
6372 OLDEQUIV since this seems highly unlikely. */
6373 if (rl->secondary_in_reload >= 0)
6376 if (reload_inherited[j])
6377 oldequiv = reloadreg;
6379 old = XEXP (rl->in_reg, 0);
6381 if (optimize && GET_CODE (oldequiv) == REG
6382 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6383 && spill_reg_store[REGNO (oldequiv)]
6384 && GET_CODE (old) == REG
6385 && (dead_or_set_p (insn,
6386 spill_reg_stored_to[REGNO (oldequiv)])
6387 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6389 delete_output_reload (insn, j, REGNO (oldequiv));
6391 /* Prevent normal processing of this reload. */
6393 /* Output a special code sequence for this case. */
6394 new_spill_reg_store[REGNO (reloadreg)]
6395 = inc_for_reload (reloadreg, oldequiv, rl->out,
6399 /* If we are reloading a pseudo-register that was set by the previous
6400 insn, see if we can get rid of that pseudo-register entirely
6401 by redirecting the previous insn into our reload register. */
6403 else if (optimize && GET_CODE (old) == REG
6404 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6405 && dead_or_set_p (insn, old)
6406 /* This is unsafe if some other reload
6407 uses the same reg first. */
6408 && ! conflicts_with_override (reloadreg)
6409 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6410 rl->when_needed, old, rl->out, j, 0))
6412 rtx temp = PREV_INSN (insn);
6413 while (temp && GET_CODE (temp) == NOTE)
6414 temp = PREV_INSN (temp);
6416 && GET_CODE (temp) == INSN
6417 && GET_CODE (PATTERN (temp)) == SET
6418 && SET_DEST (PATTERN (temp)) == old
6419 /* Make sure we can access insn_operand_constraint. */
6420 && asm_noperands (PATTERN (temp)) < 0
6421 /* This is unsafe if operand occurs more than once in current
6422 insn. Perhaps some occurrences aren't reloaded. */
6423 && count_occurrences (PATTERN (insn), old, 0) == 1)
6425 rtx old = SET_DEST (PATTERN (temp));
6426 /* Store into the reload register instead of the pseudo. */
6427 SET_DEST (PATTERN (temp)) = reloadreg;
6429 /* Verify that resulting insn is valid. */
6430 extract_insn (temp);
6431 if (constrain_operands (1))
6433 /* If the previous insn is an output reload, the source is
6434 a reload register, and its spill_reg_store entry will
6435 contain the previous destination. This is now
6437 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6438 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6440 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6441 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6444 /* If these are the only uses of the pseudo reg,
6445 pretend for GDB it lives in the reload reg we used. */
6446 if (REG_N_DEATHS (REGNO (old)) == 1
6447 && REG_N_SETS (REGNO (old)) == 1)
6449 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6450 alter_reg (REGNO (old), -1);
6456 SET_DEST (PATTERN (temp)) = old;
6461 /* We can't do that, so output an insn to load RELOADREG. */
6463 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6464 /* If we have a secondary reload, pick up the secondary register
6465 and icode, if any. If OLDEQUIV and OLD are different or
6466 if this is an in-out reload, recompute whether or not we
6467 still need a secondary register and what the icode should
6468 be. If we still need a secondary register and the class or
6469 icode is different, go back to reloading from OLD if using
6470 OLDEQUIV means that we got the wrong type of register. We
6471 cannot have different class or icode due to an in-out reload
6472 because we don't make such reloads when both the input and
6473 output need secondary reload registers. */
6475 if (! special && rl->secondary_in_reload >= 0)
6477 rtx second_reload_reg = 0;
6478 int secondary_reload = rl->secondary_in_reload;
6479 rtx real_oldequiv = oldequiv;
6482 enum insn_code icode;
6484 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6485 and similarly for OLD.
6486 See comments in get_secondary_reload in reload.c. */
6487 /* If it is a pseudo that cannot be replaced with its
6488 equivalent MEM, we must fall back to reload_in, which
6489 will have all the necessary substitutions registered.
6490 Likewise for a pseudo that can't be replaced with its
6491 equivalent constant.
6493 Take extra care for subregs of such pseudos. Note that
6494 we cannot use reg_equiv_mem in this case because it is
6495 not in the right mode. */
6498 if (GET_CODE (tmp) == SUBREG)
6499 tmp = SUBREG_REG (tmp);
6500 if (GET_CODE (tmp) == REG
6501 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6502 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6503 || reg_equiv_constant[REGNO (tmp)] != 0))
6505 if (! reg_equiv_mem[REGNO (tmp)]
6506 || num_not_at_initial_offset
6507 || GET_CODE (oldequiv) == SUBREG)
6508 real_oldequiv = rl->in;
6510 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6514 if (GET_CODE (tmp) == SUBREG)
6515 tmp = SUBREG_REG (tmp);
6516 if (GET_CODE (tmp) == REG
6517 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6518 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6519 || reg_equiv_constant[REGNO (tmp)] != 0))
6521 if (! reg_equiv_mem[REGNO (tmp)]
6522 || num_not_at_initial_offset
6523 || GET_CODE (old) == SUBREG)
6526 real_old = reg_equiv_mem[REGNO (tmp)];
6529 second_reload_reg = rld[secondary_reload].reg_rtx;
6530 icode = rl->secondary_in_icode;
6532 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6533 || (rl->in != 0 && rl->out != 0))
6535 enum reg_class new_class
6536 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6537 mode, real_oldequiv);
6539 if (new_class == NO_REGS)
6540 second_reload_reg = 0;
6543 enum insn_code new_icode;
6544 enum machine_mode new_mode;
6546 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6547 REGNO (second_reload_reg)))
6548 oldequiv = old, real_oldequiv = real_old;
6551 new_icode = reload_in_optab[(int) mode];
6552 if (new_icode != CODE_FOR_nothing
6553 && ((insn_data[(int) new_icode].operand[0].predicate
6554 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6556 || (insn_data[(int) new_icode].operand[1].predicate
6557 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6558 (real_oldequiv, mode)))))
6559 new_icode = CODE_FOR_nothing;
6561 if (new_icode == CODE_FOR_nothing)
6564 new_mode = insn_data[(int) new_icode].operand[2].mode;
6566 if (GET_MODE (second_reload_reg) != new_mode)
6568 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6570 oldequiv = old, real_oldequiv = real_old;
6573 = gen_rtx_REG (new_mode,
6574 REGNO (second_reload_reg));
6580 /* If we still need a secondary reload register, check
6581 to see if it is being used as a scratch or intermediate
6582 register and generate code appropriately. If we need
6583 a scratch register, use REAL_OLDEQUIV since the form of
6584 the insn may depend on the actual address if it is
6587 if (second_reload_reg)
6589 if (icode != CODE_FOR_nothing)
6591 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6592 second_reload_reg));
6597 /* See if we need a scratch register to load the
6598 intermediate register (a tertiary reload). */
6599 enum insn_code tertiary_icode
6600 = rld[secondary_reload].secondary_in_icode;
6602 if (tertiary_icode != CODE_FOR_nothing)
6604 rtx third_reload_reg
6605 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6607 emit_insn ((GEN_FCN (tertiary_icode)
6608 (second_reload_reg, real_oldequiv,
6609 third_reload_reg)));
6612 gen_reload (second_reload_reg, real_oldequiv,
6616 oldequiv = second_reload_reg;
6622 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6624 rtx real_oldequiv = oldequiv;
6626 if ((GET_CODE (oldequiv) == REG
6627 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6628 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6629 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6630 || (GET_CODE (oldequiv) == SUBREG
6631 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6632 && (REGNO (SUBREG_REG (oldequiv))
6633 >= FIRST_PSEUDO_REGISTER)
6634 && ((reg_equiv_memory_loc
6635 [REGNO (SUBREG_REG (oldequiv))] != 0)
6636 || (reg_equiv_constant
6637 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6638 || (CONSTANT_P (oldequiv)
6639 && (PREFERRED_RELOAD_CLASS (oldequiv,
6640 REGNO_REG_CLASS (REGNO (reloadreg)))
6642 real_oldequiv = rl->in;
6643 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6647 if (flag_non_call_exceptions)
6648 copy_eh_notes (insn, get_insns ());
6650 /* End this sequence. */
6651 *where = get_insns ();
6654 /* Update reload_override_in so that delete_address_reloads_1
6655 can see the actual register usage. */
6657 reload_override_in[j] = oldequiv;
6660 /* Generate insns to for the output reload RL, which is for the insn described
6661 by CHAIN and has the number J. */
6663 emit_output_reload_insns (chain, rl, j)
6664 struct insn_chain *chain;
6668 rtx reloadreg = rl->reg_rtx;
6669 rtx insn = chain->insn;
6672 enum machine_mode mode = GET_MODE (old);
6675 if (rl->when_needed == RELOAD_OTHER)
6678 push_to_sequence (output_reload_insns[rl->opnum]);
6680 /* Determine the mode to reload in.
6681 See comments above (for input reloading). */
6683 if (mode == VOIDmode)
6685 /* VOIDmode should never happen for an output. */
6686 if (asm_noperands (PATTERN (insn)) < 0)
6687 /* It's the compiler's fault. */
6688 fatal_insn ("VOIDmode on an output", insn);
6689 error_for_asm (insn, "output operand is constant in `asm'");
6690 /* Prevent crash--use something we know is valid. */
6692 old = gen_rtx_REG (mode, REGNO (reloadreg));
6695 if (GET_MODE (reloadreg) != mode)
6696 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6698 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6700 /* If we need two reload regs, set RELOADREG to the intermediate
6701 one, since it will be stored into OLD. We might need a secondary
6702 register only for an input reload, so check again here. */
6704 if (rl->secondary_out_reload >= 0)
6708 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6709 && reg_equiv_mem[REGNO (old)] != 0)
6710 real_old = reg_equiv_mem[REGNO (old)];
6712 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6716 rtx second_reloadreg = reloadreg;
6717 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6719 /* See if RELOADREG is to be used as a scratch register
6720 or as an intermediate register. */
6721 if (rl->secondary_out_icode != CODE_FOR_nothing)
6723 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6724 (real_old, second_reloadreg, reloadreg)));
6729 /* See if we need both a scratch and intermediate reload
6732 int secondary_reload = rl->secondary_out_reload;
6733 enum insn_code tertiary_icode
6734 = rld[secondary_reload].secondary_out_icode;
6736 if (GET_MODE (reloadreg) != mode)
6737 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6739 if (tertiary_icode != CODE_FOR_nothing)
6742 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6745 /* Copy primary reload reg to secondary reload reg.
6746 (Note that these have been swapped above, then
6747 secondary reload reg to OLD using our insn.) */
6749 /* If REAL_OLD is a paradoxical SUBREG, remove it
6750 and try to put the opposite SUBREG on
6752 if (GET_CODE (real_old) == SUBREG
6753 && (GET_MODE_SIZE (GET_MODE (real_old))
6754 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6755 && 0 != (tem = gen_lowpart_common
6756 (GET_MODE (SUBREG_REG (real_old)),
6758 real_old = SUBREG_REG (real_old), reloadreg = tem;
6760 gen_reload (reloadreg, second_reloadreg,
6761 rl->opnum, rl->when_needed);
6762 emit_insn ((GEN_FCN (tertiary_icode)
6763 (real_old, reloadreg, third_reloadreg)));
6768 /* Copy between the reload regs here and then to
6771 gen_reload (reloadreg, second_reloadreg,
6772 rl->opnum, rl->when_needed);
6778 /* Output the last reload insn. */
6783 /* Don't output the last reload if OLD is not the dest of
6784 INSN and is in the src and is clobbered by INSN. */
6785 if (! flag_expensive_optimizations
6786 || GET_CODE (old) != REG
6787 || !(set = single_set (insn))
6788 || rtx_equal_p (old, SET_DEST (set))
6789 || !reg_mentioned_p (old, SET_SRC (set))
6790 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6791 gen_reload (old, reloadreg, rl->opnum,
6795 /* Look at all insns we emitted, just to be safe. */
6796 for (p = get_insns (); p; p = NEXT_INSN (p))
6799 rtx pat = PATTERN (p);
6801 /* If this output reload doesn't come from a spill reg,
6802 clear any memory of reloaded copies of the pseudo reg.
6803 If this output reload comes from a spill reg,
6804 reg_has_output_reload will make this do nothing. */
6805 note_stores (pat, forget_old_reloads_1, NULL);
6807 if (reg_mentioned_p (rl->reg_rtx, pat))
6809 rtx set = single_set (insn);
6810 if (reload_spill_index[j] < 0
6812 && SET_SRC (set) == rl->reg_rtx)
6814 int src = REGNO (SET_SRC (set));
6816 reload_spill_index[j] = src;
6817 SET_HARD_REG_BIT (reg_is_output_reload, src);
6818 if (find_regno_note (insn, REG_DEAD, src))
6819 SET_HARD_REG_BIT (reg_reloaded_died, src);
6821 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6823 int s = rl->secondary_out_reload;
6824 set = single_set (p);
6825 /* If this reload copies only to the secondary reload
6826 register, the secondary reload does the actual
6828 if (s >= 0 && set == NULL_RTX)
6829 /* We can't tell what function the secondary reload
6830 has and where the actual store to the pseudo is
6831 made; leave new_spill_reg_store alone. */
6834 && SET_SRC (set) == rl->reg_rtx
6835 && SET_DEST (set) == rld[s].reg_rtx)
6837 /* Usually the next instruction will be the
6838 secondary reload insn; if we can confirm
6839 that it is, setting new_spill_reg_store to
6840 that insn will allow an extra optimization. */
6841 rtx s_reg = rld[s].reg_rtx;
6842 rtx next = NEXT_INSN (p);
6843 rld[s].out = rl->out;
6844 rld[s].out_reg = rl->out_reg;
6845 set = single_set (next);
6846 if (set && SET_SRC (set) == s_reg
6847 && ! new_spill_reg_store[REGNO (s_reg)])
6849 SET_HARD_REG_BIT (reg_is_output_reload,
6851 new_spill_reg_store[REGNO (s_reg)] = next;
6855 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6860 if (rl->when_needed == RELOAD_OTHER)
6862 emit_insn (other_output_reload_insns[rl->opnum]);
6863 other_output_reload_insns[rl->opnum] = get_insns ();
6866 output_reload_insns[rl->opnum] = get_insns ();
6868 if (flag_non_call_exceptions)
6869 copy_eh_notes (insn, get_insns ());
6874 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6875 and has the number J. */
6877 do_input_reload (chain, rl, j)
6878 struct insn_chain *chain;
6882 rtx insn = chain->insn;
6883 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6884 ? rl->in_reg : rl->in);
6887 /* AUTO_INC reloads need to be handled even if inherited. We got an
6888 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6889 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6890 && ! rtx_equal_p (rl->reg_rtx, old)
6891 && rl->reg_rtx != 0)
6892 emit_input_reload_insns (chain, rld + j, old, j);
6894 /* When inheriting a wider reload, we have a MEM in rl->in,
6895 e.g. inheriting a SImode output reload for
6896 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6897 if (optimize && reload_inherited[j] && rl->in
6898 && GET_CODE (rl->in) == MEM
6899 && GET_CODE (rl->in_reg) == MEM
6900 && reload_spill_index[j] >= 0
6901 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6902 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6904 /* If we are reloading a register that was recently stored in with an
6905 output-reload, see if we can prove there was
6906 actually no need to store the old value in it. */
6909 && (reload_inherited[j] || reload_override_in[j])
6911 && GET_CODE (rl->reg_rtx) == REG
6912 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6914 /* There doesn't seem to be any reason to restrict this to pseudos
6915 and doing so loses in the case where we are copying from a
6916 register of the wrong class. */
6917 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6918 >= FIRST_PSEUDO_REGISTER)
6920 /* The insn might have already some references to stackslots
6921 replaced by MEMs, while reload_out_reg still names the
6923 && (dead_or_set_p (insn,
6924 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6925 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6927 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6930 /* Do output reloading for reload RL, which is for the insn described by
6931 CHAIN and has the number J.
6932 ??? At some point we need to support handling output reloads of
6933 JUMP_INSNs or insns that set cc0. */
6935 do_output_reload (chain, rl, j)
6936 struct insn_chain *chain;
6941 rtx insn = chain->insn;
6942 /* If this is an output reload that stores something that is
6943 not loaded in this same reload, see if we can eliminate a previous
6945 rtx pseudo = rl->out_reg;
6949 && GET_CODE (pseudo) == REG
6950 && ! rtx_equal_p (rl->in_reg, pseudo)
6951 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6952 && reg_last_reload_reg[REGNO (pseudo)])
6954 int pseudo_no = REGNO (pseudo);
6955 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6957 /* We don't need to test full validity of last_regno for
6958 inherit here; we only want to know if the store actually
6959 matches the pseudo. */
6960 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6961 && reg_reloaded_contents[last_regno] == pseudo_no
6962 && spill_reg_store[last_regno]
6963 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6964 delete_output_reload (insn, j, last_regno);
6969 || rl->reg_rtx == old
6970 || rl->reg_rtx == 0)
6973 /* An output operand that dies right away does need a reload,
6974 but need not be copied from it. Show the new location in the
6976 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6977 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6979 XEXP (note, 0) = rl->reg_rtx;
6982 /* Likewise for a SUBREG of an operand that dies. */
6983 else if (GET_CODE (old) == SUBREG
6984 && GET_CODE (SUBREG_REG (old)) == REG
6985 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6988 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6992 else if (GET_CODE (old) == SCRATCH)
6993 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6994 but we don't want to make an output reload. */
6997 /* If is a JUMP_INSN, we can't support output reloads yet. */
6998 if (GET_CODE (insn) == JUMP_INSN)
7001 emit_output_reload_insns (chain, rld + j, j);
7004 /* Output insns to reload values in and out of the chosen reload regs. */
7007 emit_reload_insns (chain)
7008 struct insn_chain *chain;
7010 rtx insn = chain->insn;
7014 CLEAR_HARD_REG_SET (reg_reloaded_died);
7016 for (j = 0; j < reload_n_operands; j++)
7017 input_reload_insns[j] = input_address_reload_insns[j]
7018 = inpaddr_address_reload_insns[j]
7019 = output_reload_insns[j] = output_address_reload_insns[j]
7020 = outaddr_address_reload_insns[j]
7021 = other_output_reload_insns[j] = 0;
7022 other_input_address_reload_insns = 0;
7023 other_input_reload_insns = 0;
7024 operand_reload_insns = 0;
7025 other_operand_reload_insns = 0;
7027 /* Dump reloads into the dump file. */
7030 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7031 debug_reload_to_stream (rtl_dump_file);
7034 /* Now output the instructions to copy the data into and out of the
7035 reload registers. Do these in the order that the reloads were reported,
7036 since reloads of base and index registers precede reloads of operands
7037 and the operands may need the base and index registers reloaded. */
7039 for (j = 0; j < n_reloads; j++)
7042 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7043 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7045 do_input_reload (chain, rld + j, j);
7046 do_output_reload (chain, rld + j, j);
7049 /* Now write all the insns we made for reloads in the order expected by
7050 the allocation functions. Prior to the insn being reloaded, we write
7051 the following reloads:
7053 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7055 RELOAD_OTHER reloads.
7057 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7058 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7059 RELOAD_FOR_INPUT reload for the operand.
7061 RELOAD_FOR_OPADDR_ADDRS reloads.
7063 RELOAD_FOR_OPERAND_ADDRESS reloads.
7065 After the insn being reloaded, we write the following:
7067 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7068 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7069 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7070 reloads for the operand. The RELOAD_OTHER output reloads are
7071 output in descending order by reload number. */
7073 emit_insn_before (other_input_address_reload_insns, insn);
7074 emit_insn_before (other_input_reload_insns, insn);
7076 for (j = 0; j < reload_n_operands; j++)
7078 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7079 emit_insn_before (input_address_reload_insns[j], insn);
7080 emit_insn_before (input_reload_insns[j], insn);
7083 emit_insn_before (other_operand_reload_insns, insn);
7084 emit_insn_before (operand_reload_insns, insn);
7086 for (j = 0; j < reload_n_operands; j++)
7088 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7089 x = emit_insn_after (output_address_reload_insns[j], x);
7090 x = emit_insn_after (output_reload_insns[j], x);
7091 emit_insn_after (other_output_reload_insns[j], x);
7094 /* For all the spill regs newly reloaded in this instruction,
7095 record what they were reloaded from, so subsequent instructions
7096 can inherit the reloads.
7098 Update spill_reg_store for the reloads of this insn.
7099 Copy the elements that were updated in the loop above. */
7101 for (j = 0; j < n_reloads; j++)
7103 int r = reload_order[j];
7104 int i = reload_spill_index[r];
7106 /* If this is a non-inherited input reload from a pseudo, we must
7107 clear any memory of a previous store to the same pseudo. Only do
7108 something if there will not be an output reload for the pseudo
7110 if (rld[r].in_reg != 0
7111 && ! (reload_inherited[r] || reload_override_in[r]))
7113 rtx reg = rld[r].in_reg;
7115 if (GET_CODE (reg) == SUBREG)
7116 reg = SUBREG_REG (reg);
7118 if (GET_CODE (reg) == REG
7119 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7120 && ! reg_has_output_reload[REGNO (reg)])
7122 int nregno = REGNO (reg);
7124 if (reg_last_reload_reg[nregno])
7126 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7128 if (reg_reloaded_contents[last_regno] == nregno)
7129 spill_reg_store[last_regno] = 0;
7134 /* I is nonneg if this reload used a register.
7135 If rld[r].reg_rtx is 0, this is an optional reload
7136 that we opted to ignore. */
7138 if (i >= 0 && rld[r].reg_rtx != 0)
7140 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
7142 int part_reaches_end = 0;
7143 int all_reaches_end = 1;
7145 /* For a multi register reload, we need to check if all or part
7146 of the value lives to the end. */
7147 for (k = 0; k < nr; k++)
7149 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7150 rld[r].when_needed))
7151 part_reaches_end = 1;
7153 all_reaches_end = 0;
7156 /* Ignore reloads that don't reach the end of the insn in
7158 if (all_reaches_end)
7160 /* First, clear out memory of what used to be in this spill reg.
7161 If consecutive registers are used, clear them all. */
7163 for (k = 0; k < nr; k++)
7164 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7166 /* Maybe the spill reg contains a copy of reload_out. */
7168 && (GET_CODE (rld[r].out) == REG
7172 || GET_CODE (rld[r].out_reg) == REG))
7174 rtx out = (GET_CODE (rld[r].out) == REG
7178 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7179 int nregno = REGNO (out);
7180 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7181 : HARD_REGNO_NREGS (nregno,
7182 GET_MODE (rld[r].reg_rtx)));
7184 spill_reg_store[i] = new_spill_reg_store[i];
7185 spill_reg_stored_to[i] = out;
7186 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7188 /* If NREGNO is a hard register, it may occupy more than
7189 one register. If it does, say what is in the
7190 rest of the registers assuming that both registers
7191 agree on how many words the object takes. If not,
7192 invalidate the subsequent registers. */
7194 if (nregno < FIRST_PSEUDO_REGISTER)
7195 for (k = 1; k < nnr; k++)
7196 reg_last_reload_reg[nregno + k]
7198 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7201 /* Now do the inverse operation. */
7202 for (k = 0; k < nr; k++)
7204 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7205 reg_reloaded_contents[i + k]
7206 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7209 reg_reloaded_insn[i + k] = insn;
7210 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7214 /* Maybe the spill reg contains a copy of reload_in. Only do
7215 something if there will not be an output reload for
7216 the register being reloaded. */
7217 else if (rld[r].out_reg == 0
7219 && ((GET_CODE (rld[r].in) == REG
7220 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7221 && ! reg_has_output_reload[REGNO (rld[r].in)])
7222 || (GET_CODE (rld[r].in_reg) == REG
7223 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7224 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7229 if (GET_CODE (rld[r].in) == REG
7230 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7231 nregno = REGNO (rld[r].in);
7232 else if (GET_CODE (rld[r].in_reg) == REG)
7233 nregno = REGNO (rld[r].in_reg);
7235 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7237 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7238 : HARD_REGNO_NREGS (nregno,
7239 GET_MODE (rld[r].reg_rtx)));
7241 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7243 if (nregno < FIRST_PSEUDO_REGISTER)
7244 for (k = 1; k < nnr; k++)
7245 reg_last_reload_reg[nregno + k]
7247 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7250 /* Unless we inherited this reload, show we haven't
7251 recently done a store.
7252 Previous stores of inherited auto_inc expressions
7253 also have to be discarded. */
7254 if (! reload_inherited[r]
7255 || (rld[r].out && ! rld[r].out_reg))
7256 spill_reg_store[i] = 0;
7258 for (k = 0; k < nr; k++)
7260 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7261 reg_reloaded_contents[i + k]
7262 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7265 reg_reloaded_insn[i + k] = insn;
7266 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7271 /* However, if part of the reload reaches the end, then we must
7272 invalidate the old info for the part that survives to the end. */
7273 else if (part_reaches_end)
7275 for (k = 0; k < nr; k++)
7276 if (reload_reg_reaches_end_p (i + k,
7278 rld[r].when_needed))
7279 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7283 /* The following if-statement was #if 0'd in 1.34 (or before...).
7284 It's reenabled in 1.35 because supposedly nothing else
7285 deals with this problem. */
7287 /* If a register gets output-reloaded from a non-spill register,
7288 that invalidates any previous reloaded copy of it.
7289 But forget_old_reloads_1 won't get to see it, because
7290 it thinks only about the original insn. So invalidate it here. */
7291 if (i < 0 && rld[r].out != 0
7292 && (GET_CODE (rld[r].out) == REG
7293 || (GET_CODE (rld[r].out) == MEM
7294 && GET_CODE (rld[r].out_reg) == REG)))
7296 rtx out = (GET_CODE (rld[r].out) == REG
7297 ? rld[r].out : rld[r].out_reg);
7298 int nregno = REGNO (out);
7299 if (nregno >= FIRST_PSEUDO_REGISTER)
7301 rtx src_reg, store_insn = NULL_RTX;
7303 reg_last_reload_reg[nregno] = 0;
7305 /* If we can find a hard register that is stored, record
7306 the storing insn so that we may delete this insn with
7307 delete_output_reload. */
7308 src_reg = rld[r].reg_rtx;
7310 /* If this is an optional reload, try to find the source reg
7311 from an input reload. */
7314 rtx set = single_set (insn);
7315 if (set && SET_DEST (set) == rld[r].out)
7319 src_reg = SET_SRC (set);
7321 for (k = 0; k < n_reloads; k++)
7323 if (rld[k].in == src_reg)
7325 src_reg = rld[k].reg_rtx;
7332 store_insn = new_spill_reg_store[REGNO (src_reg)];
7333 if (src_reg && GET_CODE (src_reg) == REG
7334 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7336 int src_regno = REGNO (src_reg);
7337 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7338 /* The place where to find a death note varies with
7339 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7340 necessarily checked exactly in the code that moves
7341 notes, so just check both locations. */
7342 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7343 if (! note && store_insn)
7344 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7347 spill_reg_store[src_regno + nr] = store_insn;
7348 spill_reg_stored_to[src_regno + nr] = out;
7349 reg_reloaded_contents[src_regno + nr] = nregno;
7350 reg_reloaded_insn[src_regno + nr] = store_insn;
7351 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7352 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7353 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7355 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7357 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7359 reg_last_reload_reg[nregno] = src_reg;
7364 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7366 while (num_regs-- > 0)
7367 reg_last_reload_reg[nregno + num_regs] = 0;
7371 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7374 /* Emit code to perform a reload from IN (which may be a reload register) to
7375 OUT (which may also be a reload register). IN or OUT is from operand
7376 OPNUM with reload type TYPE.
7378 Returns first insn emitted. */
7381 gen_reload (out, in, opnum, type)
7385 enum reload_type type;
7387 rtx last = get_last_insn ();
7390 /* If IN is a paradoxical SUBREG, remove it and try to put the
7391 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7392 if (GET_CODE (in) == SUBREG
7393 && (GET_MODE_SIZE (GET_MODE (in))
7394 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7395 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7396 in = SUBREG_REG (in), out = tem;
7397 else if (GET_CODE (out) == SUBREG
7398 && (GET_MODE_SIZE (GET_MODE (out))
7399 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7400 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7401 out = SUBREG_REG (out), in = tem;
7403 /* How to do this reload can get quite tricky. Normally, we are being
7404 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7405 register that didn't get a hard register. In that case we can just
7406 call emit_move_insn.
7408 We can also be asked to reload a PLUS that adds a register or a MEM to
7409 another register, constant or MEM. This can occur during frame pointer
7410 elimination and while reloading addresses. This case is handled by
7411 trying to emit a single insn to perform the add. If it is not valid,
7412 we use a two insn sequence.
7414 Finally, we could be called to handle an 'o' constraint by putting
7415 an address into a register. In that case, we first try to do this
7416 with a named pattern of "reload_load_address". If no such pattern
7417 exists, we just emit a SET insn and hope for the best (it will normally
7418 be valid on machines that use 'o').
7420 This entire process is made complex because reload will never
7421 process the insns we generate here and so we must ensure that
7422 they will fit their constraints and also by the fact that parts of
7423 IN might be being reloaded separately and replaced with spill registers.
7424 Because of this, we are, in some sense, just guessing the right approach
7425 here. The one listed above seems to work.
7427 ??? At some point, this whole thing needs to be rethought. */
7429 if (GET_CODE (in) == PLUS
7430 && (GET_CODE (XEXP (in, 0)) == REG
7431 || GET_CODE (XEXP (in, 0)) == SUBREG
7432 || GET_CODE (XEXP (in, 0)) == MEM)
7433 && (GET_CODE (XEXP (in, 1)) == REG
7434 || GET_CODE (XEXP (in, 1)) == SUBREG
7435 || CONSTANT_P (XEXP (in, 1))
7436 || GET_CODE (XEXP (in, 1)) == MEM))
7438 /* We need to compute the sum of a register or a MEM and another
7439 register, constant, or MEM, and put it into the reload
7440 register. The best possible way of doing this is if the machine
7441 has a three-operand ADD insn that accepts the required operands.
7443 The simplest approach is to try to generate such an insn and see if it
7444 is recognized and matches its constraints. If so, it can be used.
7446 It might be better not to actually emit the insn unless it is valid,
7447 but we need to pass the insn as an operand to `recog' and
7448 `extract_insn' and it is simpler to emit and then delete the insn if
7449 not valid than to dummy things up. */
7451 rtx op0, op1, tem, insn;
7454 op0 = find_replacement (&XEXP (in, 0));
7455 op1 = find_replacement (&XEXP (in, 1));
7457 /* Since constraint checking is strict, commutativity won't be
7458 checked, so we need to do that here to avoid spurious failure
7459 if the add instruction is two-address and the second operand
7460 of the add is the same as the reload reg, which is frequently
7461 the case. If the insn would be A = B + A, rearrange it so
7462 it will be A = A + B as constrain_operands expects. */
7464 if (GET_CODE (XEXP (in, 1)) == REG
7465 && REGNO (out) == REGNO (XEXP (in, 1)))
7466 tem = op0, op0 = op1, op1 = tem;
7468 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7469 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7471 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7472 code = recog_memoized (insn);
7476 extract_insn (insn);
7477 /* We want constrain operands to treat this insn strictly in
7478 its validity determination, i.e., the way it would after reload
7480 if (constrain_operands (1))
7484 delete_insns_since (last);
7486 /* If that failed, we must use a conservative two-insn sequence.
7488 Use a move to copy one operand into the reload register. Prefer
7489 to reload a constant, MEM or pseudo since the move patterns can
7490 handle an arbitrary operand. If OP1 is not a constant, MEM or
7491 pseudo and OP1 is not a valid operand for an add instruction, then
7494 After reloading one of the operands into the reload register, add
7495 the reload register to the output register.
7497 If there is another way to do this for a specific machine, a
7498 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7501 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7503 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7504 || (GET_CODE (op1) == REG
7505 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7506 || (code != CODE_FOR_nothing
7507 && ! ((*insn_data[code].operand[2].predicate)
7508 (op1, insn_data[code].operand[2].mode))))
7509 tem = op0, op0 = op1, op1 = tem;
7511 gen_reload (out, op0, opnum, type);
7513 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7514 This fixes a problem on the 32K where the stack pointer cannot
7515 be used as an operand of an add insn. */
7517 if (rtx_equal_p (op0, op1))
7520 insn = emit_insn (gen_add2_insn (out, op1));
7522 /* If that failed, copy the address register to the reload register.
7523 Then add the constant to the reload register. */
7525 code = recog_memoized (insn);
7529 extract_insn (insn);
7530 /* We want constrain operands to treat this insn strictly in
7531 its validity determination, i.e., the way it would after reload
7533 if (constrain_operands (1))
7535 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7537 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7542 delete_insns_since (last);
7544 gen_reload (out, op1, opnum, type);
7545 insn = emit_insn (gen_add2_insn (out, op0));
7546 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7549 #ifdef SECONDARY_MEMORY_NEEDED
7550 /* If we need a memory location to do the move, do it that way. */
7551 else if ((GET_CODE (in) == REG || GET_CODE (in) == SUBREG)
7552 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7553 && (GET_CODE (out) == REG || GET_CODE (out) == SUBREG)
7554 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7555 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7556 REGNO_REG_CLASS (reg_or_subregno (out)),
7559 /* Get the memory to use and rewrite both registers to its mode. */
7560 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7562 if (GET_MODE (loc) != GET_MODE (out))
7563 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7565 if (GET_MODE (loc) != GET_MODE (in))
7566 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7568 gen_reload (loc, in, opnum, type);
7569 gen_reload (out, loc, opnum, type);
7573 /* If IN is a simple operand, use gen_move_insn. */
7574 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7575 emit_insn (gen_move_insn (out, in));
7577 #ifdef HAVE_reload_load_address
7578 else if (HAVE_reload_load_address)
7579 emit_insn (gen_reload_load_address (out, in));
7582 /* Otherwise, just write (set OUT IN) and hope for the best. */
7584 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7586 /* Return the first insn emitted.
7587 We can not just return get_last_insn, because there may have
7588 been multiple instructions emitted. Also note that gen_move_insn may
7589 emit more than one insn itself, so we can not assume that there is one
7590 insn emitted per emit_insn_before call. */
7592 return last ? NEXT_INSN (last) : get_insns ();
7595 /* Delete a previously made output-reload whose result we now believe
7596 is not needed. First we double-check.
7598 INSN is the insn now being processed.
7599 LAST_RELOAD_REG is the hard register number for which we want to delete
7600 the last output reload.
7601 J is the reload-number that originally used REG. The caller has made
7602 certain that reload J doesn't use REG any longer for input. */
7605 delete_output_reload (insn, j, last_reload_reg)
7608 int last_reload_reg;
7610 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7611 rtx reg = spill_reg_stored_to[last_reload_reg];
7614 int n_inherited = 0;
7618 /* It is possible that this reload has been only used to set another reload
7619 we eliminated earlier and thus deleted this instruction too. */
7620 if (INSN_DELETED_P (output_reload_insn))
7623 /* Get the raw pseudo-register referred to. */
7625 while (GET_CODE (reg) == SUBREG)
7626 reg = SUBREG_REG (reg);
7627 substed = reg_equiv_memory_loc[REGNO (reg)];
7629 /* This is unsafe if the operand occurs more often in the current
7630 insn than it is inherited. */
7631 for (k = n_reloads - 1; k >= 0; k--)
7633 rtx reg2 = rld[k].in;
7636 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7637 reg2 = rld[k].in_reg;
7639 if (rld[k].out && ! rld[k].out_reg)
7640 reg2 = XEXP (rld[k].in_reg, 0);
7642 while (GET_CODE (reg2) == SUBREG)
7643 reg2 = SUBREG_REG (reg2);
7644 if (rtx_equal_p (reg2, reg))
7646 if (reload_inherited[k] || reload_override_in[k] || k == j)
7649 reg2 = rld[k].out_reg;
7652 while (GET_CODE (reg2) == SUBREG)
7653 reg2 = XEXP (reg2, 0);
7654 if (rtx_equal_p (reg2, reg))
7661 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7663 n_occurrences += count_occurrences (PATTERN (insn),
7664 eliminate_regs (substed, 0,
7666 if (n_occurrences > n_inherited)
7669 /* If the pseudo-reg we are reloading is no longer referenced
7670 anywhere between the store into it and here,
7671 and no jumps or labels intervene, then the value can get
7672 here through the reload reg alone.
7673 Otherwise, give up--return. */
7674 for (i1 = NEXT_INSN (output_reload_insn);
7675 i1 != insn; i1 = NEXT_INSN (i1))
7677 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7679 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7680 && reg_mentioned_p (reg, PATTERN (i1)))
7682 /* If this is USE in front of INSN, we only have to check that
7683 there are no more references than accounted for by inheritance. */
7684 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7686 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7687 i1 = NEXT_INSN (i1);
7689 if (n_occurrences <= n_inherited && i1 == insn)
7695 /* We will be deleting the insn. Remove the spill reg information. */
7696 for (k = HARD_REGNO_NREGS (last_reload_reg, GET_MODE (reg)); k-- > 0; )
7698 spill_reg_store[last_reload_reg + k] = 0;
7699 spill_reg_stored_to[last_reload_reg + k] = 0;
7702 /* The caller has already checked that REG dies or is set in INSN.
7703 It has also checked that we are optimizing, and thus some
7704 inaccuracies in the debugging information are acceptable.
7705 So we could just delete output_reload_insn. But in some cases
7706 we can improve the debugging information without sacrificing
7707 optimization - maybe even improving the code: See if the pseudo
7708 reg has been completely replaced with reload regs. If so, delete
7709 the store insn and forget we had a stack slot for the pseudo. */
7710 if (rld[j].out != rld[j].in
7711 && REG_N_DEATHS (REGNO (reg)) == 1
7712 && REG_N_SETS (REGNO (reg)) == 1
7713 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7714 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7718 /* We know that it was used only between here and the beginning of
7719 the current basic block. (We also know that the last use before
7720 INSN was the output reload we are thinking of deleting, but never
7721 mind that.) Search that range; see if any ref remains. */
7722 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7724 rtx set = single_set (i2);
7726 /* Uses which just store in the pseudo don't count,
7727 since if they are the only uses, they are dead. */
7728 if (set != 0 && SET_DEST (set) == reg)
7730 if (GET_CODE (i2) == CODE_LABEL
7731 || GET_CODE (i2) == JUMP_INSN)
7733 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7734 && reg_mentioned_p (reg, PATTERN (i2)))
7736 /* Some other ref remains; just delete the output reload we
7738 delete_address_reloads (output_reload_insn, insn);
7739 delete_insn (output_reload_insn);
7744 /* Delete the now-dead stores into this pseudo. Note that this
7745 loop also takes care of deleting output_reload_insn. */
7746 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7748 rtx set = single_set (i2);
7750 if (set != 0 && SET_DEST (set) == reg)
7752 delete_address_reloads (i2, insn);
7755 if (GET_CODE (i2) == CODE_LABEL
7756 || GET_CODE (i2) == JUMP_INSN)
7760 /* For the debugging info, say the pseudo lives in this reload reg. */
7761 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7762 alter_reg (REGNO (reg), -1);
7766 delete_address_reloads (output_reload_insn, insn);
7767 delete_insn (output_reload_insn);
7771 /* We are going to delete DEAD_INSN. Recursively delete loads of
7772 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7773 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7775 delete_address_reloads (dead_insn, current_insn)
7776 rtx dead_insn, current_insn;
7778 rtx set = single_set (dead_insn);
7779 rtx set2, dst, prev, next;
7782 rtx dst = SET_DEST (set);
7783 if (GET_CODE (dst) == MEM)
7784 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7786 /* If we deleted the store from a reloaded post_{in,de}c expression,
7787 we can delete the matching adds. */
7788 prev = PREV_INSN (dead_insn);
7789 next = NEXT_INSN (dead_insn);
7790 if (! prev || ! next)
7792 set = single_set (next);
7793 set2 = single_set (prev);
7795 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7796 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7797 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7799 dst = SET_DEST (set);
7800 if (! rtx_equal_p (dst, SET_DEST (set2))
7801 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7802 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7803 || (INTVAL (XEXP (SET_SRC (set), 1))
7804 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7806 delete_related_insns (prev);
7807 delete_related_insns (next);
7810 /* Subfunction of delete_address_reloads: process registers found in X. */
7812 delete_address_reloads_1 (dead_insn, x, current_insn)
7813 rtx dead_insn, x, current_insn;
7815 rtx prev, set, dst, i2;
7817 enum rtx_code code = GET_CODE (x);
7821 const char *fmt = GET_RTX_FORMAT (code);
7822 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7825 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7826 else if (fmt[i] == 'E')
7828 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7829 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7836 if (spill_reg_order[REGNO (x)] < 0)
7839 /* Scan backwards for the insn that sets x. This might be a way back due
7841 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7843 code = GET_CODE (prev);
7844 if (code == CODE_LABEL || code == JUMP_INSN)
7846 if (GET_RTX_CLASS (code) != 'i')
7848 if (reg_set_p (x, PATTERN (prev)))
7850 if (reg_referenced_p (x, PATTERN (prev)))
7853 if (! prev || INSN_UID (prev) < reload_first_uid)
7855 /* Check that PREV only sets the reload register. */
7856 set = single_set (prev);
7859 dst = SET_DEST (set);
7860 if (GET_CODE (dst) != REG
7861 || ! rtx_equal_p (dst, x))
7863 if (! reg_set_p (dst, PATTERN (dead_insn)))
7865 /* Check if DST was used in a later insn -
7866 it might have been inherited. */
7867 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7869 if (GET_CODE (i2) == CODE_LABEL)
7873 if (reg_referenced_p (dst, PATTERN (i2)))
7875 /* If there is a reference to the register in the current insn,
7876 it might be loaded in a non-inherited reload. If no other
7877 reload uses it, that means the register is set before
7879 if (i2 == current_insn)
7881 for (j = n_reloads - 1; j >= 0; j--)
7882 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7883 || reload_override_in[j] == dst)
7885 for (j = n_reloads - 1; j >= 0; j--)
7886 if (rld[j].in && rld[j].reg_rtx == dst)
7893 if (GET_CODE (i2) == JUMP_INSN)
7895 /* If DST is still live at CURRENT_INSN, check if it is used for
7896 any reload. Note that even if CURRENT_INSN sets DST, we still
7897 have to check the reloads. */
7898 if (i2 == current_insn)
7900 for (j = n_reloads - 1; j >= 0; j--)
7901 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7902 || reload_override_in[j] == dst)
7904 /* ??? We can't finish the loop here, because dst might be
7905 allocated to a pseudo in this block if no reload in this
7906 block needs any of the classes containing DST - see
7907 spill_hard_reg. There is no easy way to tell this, so we
7908 have to scan till the end of the basic block. */
7910 if (reg_set_p (dst, PATTERN (i2)))
7914 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7915 reg_reloaded_contents[REGNO (dst)] = -1;
7919 /* Output reload-insns to reload VALUE into RELOADREG.
7920 VALUE is an autoincrement or autodecrement RTX whose operand
7921 is a register or memory location;
7922 so reloading involves incrementing that location.
7923 IN is either identical to VALUE, or some cheaper place to reload from.
7925 INC_AMOUNT is the number to increment or decrement by (always positive).
7926 This cannot be deduced from VALUE.
7928 Return the instruction that stores into RELOADREG. */
7931 inc_for_reload (reloadreg, in, value, inc_amount)
7936 /* REG or MEM to be copied and incremented. */
7937 rtx incloc = XEXP (value, 0);
7938 /* Nonzero if increment after copying. */
7939 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7945 rtx real_in = in == value ? XEXP (in, 0) : in;
7947 /* No hard register is equivalent to this register after
7948 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7949 we could inc/dec that register as well (maybe even using it for
7950 the source), but I'm not sure it's worth worrying about. */
7951 if (GET_CODE (incloc) == REG)
7952 reg_last_reload_reg[REGNO (incloc)] = 0;
7954 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7955 inc_amount = -inc_amount;
7957 inc = GEN_INT (inc_amount);
7959 /* If this is post-increment, first copy the location to the reload reg. */
7960 if (post && real_in != reloadreg)
7961 emit_insn (gen_move_insn (reloadreg, real_in));
7965 /* See if we can directly increment INCLOC. Use a method similar to
7966 that in gen_reload. */
7968 last = get_last_insn ();
7969 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7970 gen_rtx_PLUS (GET_MODE (incloc),
7973 code = recog_memoized (add_insn);
7976 extract_insn (add_insn);
7977 if (constrain_operands (1))
7979 /* If this is a pre-increment and we have incremented the value
7980 where it lives, copy the incremented value to RELOADREG to
7981 be used as an address. */
7984 emit_insn (gen_move_insn (reloadreg, incloc));
7989 delete_insns_since (last);
7992 /* If couldn't do the increment directly, must increment in RELOADREG.
7993 The way we do this depends on whether this is pre- or post-increment.
7994 For pre-increment, copy INCLOC to the reload register, increment it
7995 there, then save back. */
7999 if (in != reloadreg)
8000 emit_insn (gen_move_insn (reloadreg, real_in));
8001 emit_insn (gen_add2_insn (reloadreg, inc));
8002 store = emit_insn (gen_move_insn (incloc, reloadreg));
8007 Because this might be a jump insn or a compare, and because RELOADREG
8008 may not be available after the insn in an input reload, we must do
8009 the incrementation before the insn being reloaded for.
8011 We have already copied IN to RELOADREG. Increment the copy in
8012 RELOADREG, save that back, then decrement RELOADREG so it has
8013 the original value. */
8015 emit_insn (gen_add2_insn (reloadreg, inc));
8016 store = emit_insn (gen_move_insn (incloc, reloadreg));
8017 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8024 /* See whether a single set SET is a noop. */
8026 reload_cse_noop_set_p (set)
8029 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
8032 /* Try to simplify INSN. */
8034 reload_cse_simplify (insn, testreg)
8038 rtx body = PATTERN (insn);
8040 if (GET_CODE (body) == SET)
8044 /* Simplify even if we may think it is a no-op.
8045 We may think a memory load of a value smaller than WORD_SIZE
8046 is redundant because we haven't taken into account possible
8047 implicit extension. reload_cse_simplify_set() will bring
8048 this out, so it's safer to simplify before we delete. */
8049 count += reload_cse_simplify_set (body, insn);
8051 if (!count && reload_cse_noop_set_p (body))
8053 rtx value = SET_DEST (body);
8055 && ! REG_FUNCTION_VALUE_P (value))
8057 delete_insn_and_edges (insn);
8062 apply_change_group ();
8064 reload_cse_simplify_operands (insn, testreg);
8066 else if (GET_CODE (body) == PARALLEL)
8070 rtx value = NULL_RTX;
8072 /* If every action in a PARALLEL is a noop, we can delete
8073 the entire PARALLEL. */
8074 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8076 rtx part = XVECEXP (body, 0, i);
8077 if (GET_CODE (part) == SET)
8079 if (! reload_cse_noop_set_p (part))
8081 if (REG_P (SET_DEST (part))
8082 && REG_FUNCTION_VALUE_P (SET_DEST (part)))
8086 value = SET_DEST (part);
8089 else if (GET_CODE (part) != CLOBBER)
8095 delete_insn_and_edges (insn);
8096 /* We're done with this insn. */
8100 /* It's not a no-op, but we can try to simplify it. */
8101 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8102 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8103 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8106 apply_change_group ();
8108 reload_cse_simplify_operands (insn, testreg);
8112 /* Do a very simple CSE pass over the hard registers.
8114 This function detects no-op moves where we happened to assign two
8115 different pseudo-registers to the same hard register, and then
8116 copied one to the other. Reload will generate a useless
8117 instruction copying a register to itself.
8119 This function also detects cases where we load a value from memory
8120 into two different registers, and (if memory is more expensive than
8121 registers) changes it to simply copy the first register into the
8124 Another optimization is performed that scans the operands of each
8125 instruction to see whether the value is already available in a
8126 hard register. It then replaces the operand with the hard register
8127 if possible, much like an optional reload would. */
8130 reload_cse_regs_1 (first)
8134 rtx testreg = gen_rtx_REG (VOIDmode, -1);
8137 init_alias_analysis ();
8139 for (insn = first; insn; insn = NEXT_INSN (insn))
8142 reload_cse_simplify (insn, testreg);
8144 cselib_process_insn (insn);
8148 end_alias_analysis ();
8152 /* Call cse / combine like post-reload optimization phases.
8153 FIRST is the first instruction. */
8155 reload_cse_regs (first)
8158 reload_cse_regs_1 (first);
8160 reload_cse_move2add (first);
8161 if (flag_expensive_optimizations)
8162 reload_cse_regs_1 (first);
8165 /* Try to simplify a single SET instruction. SET is the set pattern.
8166 INSN is the instruction it came from.
8167 This function only handles one case: if we set a register to a value
8168 which is not a register, we try to find that value in some other register
8169 and change the set into a register copy. */
8172 reload_cse_simplify_set (set, insn)
8179 enum reg_class dclass;
8182 struct elt_loc_list *l;
8183 #ifdef LOAD_EXTEND_OP
8184 enum rtx_code extend_op = NIL;
8187 dreg = true_regnum (SET_DEST (set));
8191 src = SET_SRC (set);
8192 if (side_effects_p (src) || true_regnum (src) >= 0)
8195 dclass = REGNO_REG_CLASS (dreg);
8197 #ifdef LOAD_EXTEND_OP
8198 /* When replacing a memory with a register, we need to honor assumptions
8199 that combine made wrt the contents of sign bits. We'll do this by
8200 generating an extend instruction instead of a reg->reg copy. Thus
8201 the destination must be a register that we can widen. */
8202 if (GET_CODE (src) == MEM
8203 && GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD
8204 && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != NIL
8205 && GET_CODE (SET_DEST (set)) != REG)
8209 /* If memory loads are cheaper than register copies, don't change them. */
8210 if (GET_CODE (src) == MEM)
8211 old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
8212 else if (CONSTANT_P (src))
8213 old_cost = rtx_cost (src, SET);
8214 else if (GET_CODE (src) == REG)
8215 old_cost = REGISTER_MOVE_COST (GET_MODE (src),
8216 REGNO_REG_CLASS (REGNO (src)), dclass);
8219 old_cost = rtx_cost (src, SET);
8221 val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0);
8224 for (l = val->locs; l; l = l->next)
8226 rtx this_rtx = l->loc;
8229 if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0))
8231 #ifdef LOAD_EXTEND_OP
8232 if (extend_op != NIL)
8234 HOST_WIDE_INT this_val;
8236 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
8237 constants, such as SYMBOL_REF, cannot be extended. */
8238 if (GET_CODE (this_rtx) != CONST_INT)
8241 this_val = INTVAL (this_rtx);
8245 this_val &= GET_MODE_MASK (GET_MODE (src));
8248 /* ??? In theory we're already extended. */
8249 if (this_val == trunc_int_for_mode (this_val, GET_MODE (src)))
8254 this_rtx = GEN_INT (this_val);
8257 this_cost = rtx_cost (this_rtx, SET);
8259 else if (GET_CODE (this_rtx) == REG)
8261 #ifdef LOAD_EXTEND_OP
8262 if (extend_op != NIL)
8264 this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx);
8265 this_cost = rtx_cost (this_rtx, SET);
8269 this_cost = REGISTER_MOVE_COST (GET_MODE (this_rtx),
8270 REGNO_REG_CLASS (REGNO (this_rtx)),
8276 /* If equal costs, prefer registers over anything else. That
8277 tends to lead to smaller instructions on some machines. */
8278 if (this_cost < old_cost
8279 || (this_cost == old_cost
8280 && GET_CODE (this_rtx) == REG
8281 && GET_CODE (SET_SRC (set)) != REG))
8283 #ifdef LOAD_EXTEND_OP
8284 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD
8285 && extend_op != NIL)
8287 rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set)));
8288 ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set));
8289 validate_change (insn, &SET_DEST (set), wide_dest, 1);
8293 validate_change (insn, &SET_SRC (set), copy_rtx (this_rtx), 1);
8294 old_cost = this_cost, did_change = 1;
8301 /* Try to replace operands in INSN with equivalent values that are already
8302 in registers. This can be viewed as optional reloading.
8304 For each non-register operand in the insn, see if any hard regs are
8305 known to be equivalent to that operand. Record the alternatives which
8306 can accept these hard registers. Among all alternatives, select the
8307 ones which are better or equal to the one currently matching, where
8308 "better" is in terms of '?' and '!' constraints. Among the remaining
8309 alternatives, select the one which replaces most operands with
8313 reload_cse_simplify_operands (insn, testreg)
8319 /* For each operand, all registers that are equivalent to it. */
8320 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
8322 const char *constraints[MAX_RECOG_OPERANDS];
8324 /* Vector recording how bad an alternative is. */
8325 int *alternative_reject;
8326 /* Vector recording how many registers can be introduced by choosing
8327 this alternative. */
8328 int *alternative_nregs;
8329 /* Array of vectors recording, for each operand and each alternative,
8330 which hard register to substitute, or -1 if the operand should be
8332 int *op_alt_regno[MAX_RECOG_OPERANDS];
8333 /* Array of alternatives, sorted in order of decreasing desirability. */
8334 int *alternative_order;
8336 extract_insn (insn);
8338 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8341 /* Figure out which alternative currently matches. */
8342 if (! constrain_operands (1))
8343 fatal_insn_not_found (insn);
8345 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8346 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8347 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8348 memset ((char *) alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
8349 memset ((char *) alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
8351 /* For each operand, find out which regs are equivalent. */
8352 for (i = 0; i < recog_data.n_operands; i++)
8355 struct elt_loc_list *l;
8357 CLEAR_HARD_REG_SET (equiv_regs[i]);
8359 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8360 right, so avoid the problem here. Likewise if we have a constant
8361 and the insn pattern doesn't tell us the mode we need. */
8362 if (GET_CODE (recog_data.operand[i]) == CODE_LABEL
8363 || (CONSTANT_P (recog_data.operand[i])
8364 && recog_data.operand_mode[i] == VOIDmode))
8367 v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0);
8371 for (l = v->locs; l; l = l->next)
8372 if (GET_CODE (l->loc) == REG)
8373 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
8376 for (i = 0; i < recog_data.n_operands; i++)
8378 enum machine_mode mode;
8382 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8383 for (j = 0; j < recog_data.n_alternatives; j++)
8384 op_alt_regno[i][j] = -1;
8386 p = constraints[i] = recog_data.constraints[i];
8387 mode = recog_data.operand_mode[i];
8389 /* Add the reject values for each alternative given by the constraints
8390 for this operand. */
8398 alternative_reject[j] += 3;
8400 alternative_reject[j] += 300;
8403 /* We won't change operands which are already registers. We
8404 also don't want to modify output operands. */
8405 regno = true_regnum (recog_data.operand[i]);
8407 || constraints[i][0] == '='
8408 || constraints[i][0] == '+')
8411 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8413 int class = (int) NO_REGS;
8415 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
8418 REGNO (testreg) = regno;
8419 PUT_MODE (testreg, mode);
8421 /* We found a register equal to this operand. Now look for all
8422 alternatives that can accept this register and have not been
8423 assigned a register they can use yet. */
8432 case '=': case '+': case '?':
8433 case '#': case '&': case '!':
8435 case '0': case '1': case '2': case '3': case '4':
8436 case '5': case '6': case '7': case '8': case '9':
8437 case 'm': case '<': case '>': case 'V': case 'o':
8438 case 'E': case 'F': case 'G': case 'H':
8439 case 's': case 'i': case 'n':
8440 case 'I': case 'J': case 'K': case 'L':
8441 case 'M': case 'N': case 'O': case 'P':
8443 /* These don't say anything we care about. */
8447 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8452 = (reg_class_subunion
8454 [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c, p)]);
8457 case ',': case '\0':
8458 /* See if REGNO fits this alternative, and set it up as the
8459 replacement register if we don't have one for this
8460 alternative yet and the operand being replaced is not
8461 a cheap CONST_INT. */
8462 if (op_alt_regno[i][j] == -1
8463 && reg_fits_class_p (testreg, class, 0, mode)
8464 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8465 || (rtx_cost (recog_data.operand[i], SET)
8466 > rtx_cost (testreg, SET))))
8468 alternative_nregs[j]++;
8469 op_alt_regno[i][j] = regno;
8474 p += CONSTRAINT_LEN (c, p);
8482 /* Record all alternatives which are better or equal to the currently
8483 matching one in the alternative_order array. */
8484 for (i = j = 0; i < recog_data.n_alternatives; i++)
8485 if (alternative_reject[i] <= alternative_reject[which_alternative])
8486 alternative_order[j++] = i;
8487 recog_data.n_alternatives = j;
8489 /* Sort it. Given a small number of alternatives, a dumb algorithm
8490 won't hurt too much. */
8491 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8494 int best_reject = alternative_reject[alternative_order[i]];
8495 int best_nregs = alternative_nregs[alternative_order[i]];
8498 for (j = i + 1; j < recog_data.n_alternatives; j++)
8500 int this_reject = alternative_reject[alternative_order[j]];
8501 int this_nregs = alternative_nregs[alternative_order[j]];
8503 if (this_reject < best_reject
8504 || (this_reject == best_reject && this_nregs < best_nregs))
8507 best_reject = this_reject;
8508 best_nregs = this_nregs;
8512 tmp = alternative_order[best];
8513 alternative_order[best] = alternative_order[i];
8514 alternative_order[i] = tmp;
8517 /* Substitute the operands as determined by op_alt_regno for the best
8519 j = alternative_order[0];
8521 for (i = 0; i < recog_data.n_operands; i++)
8523 enum machine_mode mode = recog_data.operand_mode[i];
8524 if (op_alt_regno[i][j] == -1)
8527 validate_change (insn, recog_data.operand_loc[i],
8528 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8531 for (i = recog_data.n_dups - 1; i >= 0; i--)
8533 int op = recog_data.dup_num[i];
8534 enum machine_mode mode = recog_data.operand_mode[op];
8536 if (op_alt_regno[op][j] == -1)
8539 validate_change (insn, recog_data.dup_loc[i],
8540 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8543 return apply_change_group ();
8546 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8548 This code might also be useful when reload gave up on reg+reg addressing
8549 because of clashes between the return register and INDEX_REG_CLASS. */
8551 /* The maximum number of uses of a register we can keep track of to
8552 replace them with reg+reg addressing. */
8553 #define RELOAD_COMBINE_MAX_USES 6
8555 /* INSN is the insn where a register has ben used, and USEP points to the
8556 location of the register within the rtl. */
8557 struct reg_use { rtx insn, *usep; };
8559 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8560 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8561 indicates where it becomes live again.
8562 Otherwise, USE_INDEX is the index of the last encountered use of the
8563 register (which is first among these we have seen since we scan backwards),
8564 OFFSET contains the constant offset that is added to the register in
8565 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8566 last, of these uses.
8567 STORE_RUID is always meaningful if we only want to use a value in a
8568 register in a different place: it denotes the next insn in the insn
8569 stream (i.e. the last encountered) that sets or clobbers the register. */
8572 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8577 } reg_state[FIRST_PSEUDO_REGISTER];
8579 /* Reverse linear uid. This is increased in reload_combine while scanning
8580 the instructions from last to first. It is used to set last_label_ruid
8581 and the store_ruid / use_ruid fields in reg_state. */
8582 static int reload_combine_ruid;
8584 #define LABEL_LIVE(LABEL) \
8585 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8591 int first_index_reg = -1;
8592 int last_index_reg = 0;
8596 int last_label_ruid;
8597 int min_labelno, n_labels;
8598 HARD_REG_SET ever_live_at_start, *label_live;
8600 /* If reg+reg can be used in offsetable memory addresses, the main chunk of
8601 reload has already used it where appropriate, so there is no use in
8602 trying to generate it now. */
8603 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8606 /* To avoid wasting too much time later searching for an index register,
8607 determine the minimum and maximum index register numbers. */
8608 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8609 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
8611 if (first_index_reg == -1)
8612 first_index_reg = r;
8617 /* If no index register is available, we can quit now. */
8618 if (first_index_reg == -1)
8621 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8622 information is a bit fuzzy immediately after reload, but it's
8623 still good enough to determine which registers are live at a jump
8625 min_labelno = get_first_label_num ();
8626 n_labels = max_label_num () - min_labelno;
8627 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8628 CLEAR_HARD_REG_SET (ever_live_at_start);
8630 FOR_EACH_BB_REVERSE (bb)
8633 if (GET_CODE (insn) == CODE_LABEL)
8637 REG_SET_TO_HARD_REG_SET (live,
8638 bb->global_live_at_start);
8639 compute_use_by_pseudos (&live,
8640 bb->global_live_at_start);
8641 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8642 IOR_HARD_REG_SET (ever_live_at_start, live);
8646 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8647 last_label_ruid = reload_combine_ruid = 0;
8648 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8650 reg_state[r].store_ruid = reload_combine_ruid;
8652 reg_state[r].use_index = -1;
8654 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8657 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8661 /* We cannot do our optimization across labels. Invalidating all the use
8662 information we have would be costly, so we just note where the label
8663 is and then later disable any optimization that would cross it. */
8664 if (GET_CODE (insn) == CODE_LABEL)
8665 last_label_ruid = reload_combine_ruid;
8666 else if (GET_CODE (insn) == BARRIER)
8667 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8668 if (! fixed_regs[r])
8669 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8671 if (! INSN_P (insn))
8674 reload_combine_ruid++;
8676 /* Look for (set (REGX) (CONST_INT))
8677 (set (REGX) (PLUS (REGX) (REGY)))
8679 ... (MEM (REGX)) ...
8681 (set (REGZ) (CONST_INT))
8683 ... (MEM (PLUS (REGZ) (REGY)))... .
8685 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8686 and that we know all uses of REGX before it dies. */
8687 set = single_set (insn);
8689 && GET_CODE (SET_DEST (set)) == REG
8690 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
8691 GET_MODE (SET_DEST (set)))
8693 && GET_CODE (SET_SRC (set)) == PLUS
8694 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
8695 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
8696 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
8698 rtx reg = SET_DEST (set);
8699 rtx plus = SET_SRC (set);
8700 rtx base = XEXP (plus, 1);
8701 rtx prev = prev_nonnote_insn (insn);
8702 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
8703 unsigned int regno = REGNO (reg);
8704 rtx const_reg = NULL_RTX;
8705 rtx reg_sum = NULL_RTX;
8707 /* Now, we need an index register.
8708 We'll set index_reg to this index register, const_reg to the
8709 register that is to be loaded with the constant
8710 (denoted as REGZ in the substitution illustration above),
8711 and reg_sum to the register-register that we want to use to
8712 substitute uses of REG (typically in MEMs) with.
8713 First check REG and BASE for being index registers;
8714 we can use them even if they are not dead. */
8715 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
8716 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8724 /* Otherwise, look for a free index register. Since we have
8725 checked above that neiter REG nor BASE are index registers,
8726 if we find anything at all, it will be different from these
8728 for (i = first_index_reg; i <= last_index_reg; i++)
8730 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8732 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
8733 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
8734 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
8736 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
8738 const_reg = index_reg;
8739 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
8745 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8746 (REGY), i.e. BASE, is not clobbered before the last use we'll
8749 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
8750 && rtx_equal_p (SET_DEST (prev_set), reg)
8751 && reg_state[regno].use_index >= 0
8752 && (reg_state[REGNO (base)].store_ruid
8753 <= reg_state[regno].use_ruid)
8758 /* Change destination register and, if necessary, the
8759 constant value in PREV, the constant loading instruction. */
8760 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
8761 if (reg_state[regno].offset != const0_rtx)
8762 validate_change (prev,
8763 &SET_SRC (prev_set),
8764 GEN_INT (INTVAL (SET_SRC (prev_set))
8765 + INTVAL (reg_state[regno].offset)),
8768 /* Now for every use of REG that we have recorded, replace REG
8770 for (i = reg_state[regno].use_index;
8771 i < RELOAD_COMBINE_MAX_USES; i++)
8772 validate_change (reg_state[regno].reg_use[i].insn,
8773 reg_state[regno].reg_use[i].usep,
8774 /* Each change must have its own
8776 copy_rtx (reg_sum), 1);
8778 if (apply_change_group ())
8782 /* Delete the reg-reg addition. */
8785 if (reg_state[regno].offset != const0_rtx)
8786 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8788 for (np = ®_NOTES (prev); *np;)
8790 if (REG_NOTE_KIND (*np) == REG_EQUAL
8791 || REG_NOTE_KIND (*np) == REG_EQUIV)
8792 *np = XEXP (*np, 1);
8794 np = &XEXP (*np, 1);
8797 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8798 reg_state[REGNO (const_reg)].store_ruid
8799 = reload_combine_ruid;
8805 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
8807 if (GET_CODE (insn) == CALL_INSN)
8811 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8812 if (call_used_regs[r])
8814 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8815 reg_state[r].store_ruid = reload_combine_ruid;
8818 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
8819 link = XEXP (link, 1))
8821 rtx usage_rtx = XEXP (XEXP (link, 0), 0);
8822 if (GET_CODE (usage_rtx) == REG)
8825 unsigned int start_reg = REGNO (usage_rtx);
8826 unsigned int num_regs =
8827 HARD_REGNO_NREGS (start_reg, GET_MODE (usage_rtx));
8828 unsigned int end_reg = start_reg + num_regs - 1;
8829 for (i = start_reg; i <= end_reg; i++)
8830 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
8832 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8833 reg_state[i].store_ruid = reload_combine_ruid;
8836 reg_state[i].use_index = -1;
8841 else if (GET_CODE (insn) == JUMP_INSN
8842 && GET_CODE (PATTERN (insn)) != RETURN)
8844 /* Non-spill registers might be used at the call destination in
8845 some unknown fashion, so we have to mark the unknown use. */
8848 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
8849 && JUMP_LABEL (insn))
8850 live = &LABEL_LIVE (JUMP_LABEL (insn));
8852 live = &ever_live_at_start;
8854 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8855 if (TEST_HARD_REG_BIT (*live, i))
8856 reg_state[i].use_index = -1;
8859 reload_combine_note_use (&PATTERN (insn), insn);
8860 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8862 if (REG_NOTE_KIND (note) == REG_INC
8863 && GET_CODE (XEXP (note, 0)) == REG)
8865 int regno = REGNO (XEXP (note, 0));
8867 reg_state[regno].store_ruid = reload_combine_ruid;
8868 reg_state[regno].use_index = -1;
8876 /* Check if DST is a register or a subreg of a register; if it is,
8877 update reg_state[regno].store_ruid and reg_state[regno].use_index
8878 accordingly. Called via note_stores from reload_combine. */
8881 reload_combine_note_store (dst, set, data)
8883 void *data ATTRIBUTE_UNUSED;
8887 enum machine_mode mode = GET_MODE (dst);
8889 if (GET_CODE (dst) == SUBREG)
8891 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
8892 GET_MODE (SUBREG_REG (dst)),
8895 dst = SUBREG_REG (dst);
8897 if (GET_CODE (dst) != REG)
8899 regno += REGNO (dst);
8901 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8902 careful with registers / register parts that are not full words.
8904 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8905 if (GET_CODE (set) != SET
8906 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
8907 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
8908 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
8910 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8912 reg_state[i].use_index = -1;
8913 reg_state[i].store_ruid = reload_combine_ruid;
8918 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8920 reg_state[i].store_ruid = reload_combine_ruid;
8921 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8926 /* XP points to a piece of rtl that has to be checked for any uses of
8928 *XP is the pattern of INSN, or a part of it.
8929 Called from reload_combine, and recursively by itself. */
8931 reload_combine_note_use (xp, insn)
8935 enum rtx_code code = x->code;
8938 rtx offset = const0_rtx; /* For the REG case below. */
8943 if (GET_CODE (SET_DEST (x)) == REG)
8945 reload_combine_note_use (&SET_SRC (x), insn);
8951 /* If this is the USE of a return value, we can't change it. */
8952 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
8954 /* Mark the return register as used in an unknown fashion. */
8955 rtx reg = XEXP (x, 0);
8956 int regno = REGNO (reg);
8957 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
8959 while (--nregs >= 0)
8960 reg_state[regno + nregs].use_index = -1;
8966 if (GET_CODE (SET_DEST (x)) == REG)
8968 /* No spurious CLOBBERs of pseudo registers may remain. */
8969 if (REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER)
8976 /* We are interested in (plus (reg) (const_int)) . */
8977 if (GET_CODE (XEXP (x, 0)) != REG
8978 || GET_CODE (XEXP (x, 1)) != CONST_INT)
8980 offset = XEXP (x, 1);
8985 int regno = REGNO (x);
8989 /* No spurious USEs of pseudo registers may remain. */
8990 if (regno >= FIRST_PSEUDO_REGISTER)
8993 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x));
8995 /* We can't substitute into multi-hard-reg uses. */
8998 while (--nregs >= 0)
8999 reg_state[regno + nregs].use_index = -1;
9003 /* If this register is already used in some unknown fashion, we
9005 If we decrement the index from zero to -1, we can't store more
9006 uses, so this register becomes used in an unknown fashion. */
9007 use_index = --reg_state[regno].use_index;
9011 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
9013 /* We have found another use for a register that is already
9014 used later. Check if the offsets match; if not, mark the
9015 register as used in an unknown fashion. */
9016 if (! rtx_equal_p (offset, reg_state[regno].offset))
9018 reg_state[regno].use_index = -1;
9024 /* This is the first use of this register we have seen since we
9025 marked it as dead. */
9026 reg_state[regno].offset = offset;
9027 reg_state[regno].use_ruid = reload_combine_ruid;
9029 reg_state[regno].reg_use[use_index].insn = insn;
9030 reg_state[regno].reg_use[use_index].usep = xp;
9038 /* Recursively process the components of X. */
9039 fmt = GET_RTX_FORMAT (code);
9040 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9043 reload_combine_note_use (&XEXP (x, i), insn);
9044 else if (fmt[i] == 'E')
9046 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9047 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9052 /* See if we can reduce the cost of a constant by replacing a move
9053 with an add. We track situations in which a register is set to a
9054 constant or to a register plus a constant. */
9055 /* We cannot do our optimization across labels. Invalidating all the
9056 information about register contents we have would be costly, so we
9057 use move2add_last_label_luid to note where the label is and then
9058 later disable any optimization that would cross it.
9059 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9060 reg_set_luid[n] is greater than last_label_luid[n] . */
9061 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9063 /* If reg_base_reg[n] is negative, register n has been set to
9064 reg_offset[n] in mode reg_mode[n] .
9065 If reg_base_reg[n] is non-negative, register n has been set to the
9066 sum of reg_offset[n] and the value of register reg_base_reg[n]
9067 before reg_set_luid[n], calculated in mode reg_mode[n] . */
9068 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
9069 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9070 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9072 /* move2add_luid is linearly increased while scanning the instructions
9073 from first to last. It is used to set reg_set_luid in
9074 reload_cse_move2add and move2add_note_store. */
9075 static int move2add_luid;
9077 /* move2add_last_label_luid is set whenever a label is found. Labels
9078 invalidate all previously collected reg_offset data. */
9079 static int move2add_last_label_luid;
9081 /* Generate a CONST_INT and force it in the range of MODE. */
9083 static HOST_WIDE_INT
9084 sext_for_mode (mode, value)
9085 enum machine_mode mode;
9086 HOST_WIDE_INT value;
9088 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
9089 int width = GET_MODE_BITSIZE (mode);
9091 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
9093 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
9094 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
9095 cval |= (HOST_WIDE_INT) -1 << width;
9100 /* ??? We don't know how zero / sign extension is handled, hence we
9101 can't go from a narrower to a wider mode. */
9102 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
9103 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
9104 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
9105 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \
9106 GET_MODE_BITSIZE (INMODE))))
9109 reload_cse_move2add (first)
9115 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9116 reg_set_luid[i] = 0;
9118 move2add_last_label_luid = 0;
9120 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
9124 if (GET_CODE (insn) == CODE_LABEL)
9126 move2add_last_label_luid = move2add_luid;
9127 /* We're going to increment move2add_luid twice after a
9128 label, so that we can use move2add_last_label_luid + 1 as
9129 the luid for constants. */
9133 if (! INSN_P (insn))
9135 pat = PATTERN (insn);
9136 /* For simplicity, we only perform this optimization on
9137 straightforward SETs. */
9138 if (GET_CODE (pat) == SET
9139 && GET_CODE (SET_DEST (pat)) == REG)
9141 rtx reg = SET_DEST (pat);
9142 int regno = REGNO (reg);
9143 rtx src = SET_SRC (pat);
9145 /* Check if we have valid information on the contents of this
9146 register in the mode of REG. */
9147 if (reg_set_luid[regno] > move2add_last_label_luid
9148 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno]))
9150 /* Try to transform (set (REGX) (CONST_INT A))
9152 (set (REGX) (CONST_INT B))
9154 (set (REGX) (CONST_INT A))
9156 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9158 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
9161 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9163 - reg_offset[regno]));
9164 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9165 use (set (reg) (reg)) instead.
9166 We don't delete this insn, nor do we convert it into a
9167 note, to avoid losing register notes or the return
9168 value flag. jump2 already knows how to get rid of
9170 if (new_src == const0_rtx)
9171 success = validate_change (insn, &SET_SRC (pat), reg, 0);
9172 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
9173 && have_add2_insn (reg, new_src))
9174 success = validate_change (insn, &PATTERN (insn),
9175 gen_add2_insn (reg, new_src), 0);
9176 reg_set_luid[regno] = move2add_luid;
9177 reg_mode[regno] = GET_MODE (reg);
9178 reg_offset[regno] = INTVAL (src);
9182 /* Try to transform (set (REGX) (REGY))
9183 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9186 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9189 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9191 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9192 else if (GET_CODE (src) == REG
9193 && reg_set_luid[regno] == reg_set_luid[REGNO (src)]
9194 && reg_base_reg[regno] == reg_base_reg[REGNO (src)]
9195 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg),
9196 reg_mode[REGNO (src)]))
9198 rtx next = next_nonnote_insn (insn);
9201 set = single_set (next);
9203 && SET_DEST (set) == reg
9204 && GET_CODE (SET_SRC (set)) == PLUS
9205 && XEXP (SET_SRC (set), 0) == reg
9206 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9208 rtx src3 = XEXP (SET_SRC (set), 1);
9209 HOST_WIDE_INT added_offset = INTVAL (src3);
9210 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)];
9211 HOST_WIDE_INT regno_offset = reg_offset[regno];
9212 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9218 if (new_src == const0_rtx)
9219 /* See above why we create (set (reg) (reg)) here. */
9221 = validate_change (next, &SET_SRC (set), reg, 0);
9222 else if ((rtx_cost (new_src, PLUS)
9223 < COSTS_N_INSNS (1) + rtx_cost (src3, SET))
9224 && have_add2_insn (reg, new_src))
9226 = validate_change (next, &PATTERN (next),
9227 gen_add2_insn (reg, new_src), 0);
9231 reg_mode[regno] = GET_MODE (reg);
9232 reg_offset[regno] = sext_for_mode (GET_MODE (reg),
9241 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9243 if (REG_NOTE_KIND (note) == REG_INC
9244 && GET_CODE (XEXP (note, 0)) == REG)
9246 /* Reset the information about this register. */
9247 int regno = REGNO (XEXP (note, 0));
9248 if (regno < FIRST_PSEUDO_REGISTER)
9249 reg_set_luid[regno] = 0;
9252 note_stores (PATTERN (insn), move2add_note_store, NULL);
9253 /* If this is a CALL_INSN, all call used registers are stored with
9255 if (GET_CODE (insn) == CALL_INSN)
9257 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9259 if (call_used_regs[i])
9260 /* Reset the information about this register. */
9261 reg_set_luid[i] = 0;
9267 /* SET is a SET or CLOBBER that sets DST.
9268 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9269 Called from reload_cse_move2add via note_stores. */
9272 move2add_note_store (dst, set, data)
9274 void *data ATTRIBUTE_UNUSED;
9276 unsigned int regno = 0;
9278 enum machine_mode mode = GET_MODE (dst);
9280 if (GET_CODE (dst) == SUBREG)
9282 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
9283 GET_MODE (SUBREG_REG (dst)),
9286 dst = SUBREG_REG (dst);
9289 /* Some targets do argument pushes without adding REG_INC notes. */
9291 if (GET_CODE (dst) == MEM)
9293 dst = XEXP (dst, 0);
9294 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC
9295 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC)
9296 reg_set_luid[REGNO (XEXP (dst, 0))] = 0;
9299 if (GET_CODE (dst) != REG)
9302 regno += REGNO (dst);
9304 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9305 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9306 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9307 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9309 rtx src = SET_SRC (set);
9311 HOST_WIDE_INT offset;
9313 /* This may be different from mode, if SET_DEST (set) is a
9315 enum machine_mode dst_mode = GET_MODE (dst);
9317 switch (GET_CODE (src))
9320 if (GET_CODE (XEXP (src, 0)) == REG)
9322 base_reg = XEXP (src, 0);
9324 if (GET_CODE (XEXP (src, 1)) == CONST_INT)
9325 offset = INTVAL (XEXP (src, 1));
9326 else if (GET_CODE (XEXP (src, 1)) == REG
9327 && (reg_set_luid[REGNO (XEXP (src, 1))]
9328 > move2add_last_label_luid)
9329 && (MODES_OK_FOR_MOVE2ADD
9330 (dst_mode, reg_mode[REGNO (XEXP (src, 1))])))
9332 if (reg_base_reg[REGNO (XEXP (src, 1))] < 0)
9333 offset = reg_offset[REGNO (XEXP (src, 1))];
9334 /* Maybe the first register is known to be a
9336 else if (reg_set_luid[REGNO (base_reg)]
9337 > move2add_last_label_luid
9338 && (MODES_OK_FOR_MOVE2ADD
9339 (dst_mode, reg_mode[REGNO (XEXP (src, 1))]))
9340 && reg_base_reg[REGNO (base_reg)] < 0)
9342 offset = reg_offset[REGNO (base_reg)];
9343 base_reg = XEXP (src, 1);
9362 /* Start tracking the register as a constant. */
9363 reg_base_reg[regno] = -1;
9364 reg_offset[regno] = INTVAL (SET_SRC (set));
9365 /* We assign the same luid to all registers set to constants. */
9366 reg_set_luid[regno] = move2add_last_label_luid + 1;
9367 reg_mode[regno] = mode;
9372 /* Invalidate the contents of the register. */
9373 reg_set_luid[regno] = 0;
9377 base_regno = REGNO (base_reg);
9378 /* If information about the base register is not valid, set it
9379 up as a new base register, pretending its value is known
9380 starting from the current insn. */
9381 if (reg_set_luid[base_regno] <= move2add_last_label_luid)
9383 reg_base_reg[base_regno] = base_regno;
9384 reg_offset[base_regno] = 0;
9385 reg_set_luid[base_regno] = move2add_luid;
9386 reg_mode[base_regno] = mode;
9388 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode,
9389 reg_mode[base_regno]))
9392 reg_mode[regno] = mode;
9394 /* Copy base information from our base register. */
9395 reg_set_luid[regno] = reg_set_luid[base_regno];
9396 reg_base_reg[regno] = reg_base_reg[base_regno];
9398 /* Compute the sum of the offsets or constants. */
9399 reg_offset[regno] = sext_for_mode (dst_mode,
9401 + reg_offset[base_regno]);
9405 unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode);
9407 for (i = regno; i < endregno; i++)
9408 /* Reset the information about this register. */
9409 reg_set_luid[i] = 0;
9415 add_auto_inc_notes (insn, x)
9419 enum rtx_code code = GET_CODE (x);
9423 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9426 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9430 /* Scan all the operand sub-expressions. */
9431 fmt = GET_RTX_FORMAT (code);
9432 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9435 add_auto_inc_notes (insn, XEXP (x, i));
9436 else if (fmt[i] == 'E')
9437 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9438 add_auto_inc_notes (insn, XVECEXP (x, i, j));
9443 /* Copy EH notes from an insn to its reloads. */
9445 copy_eh_notes (insn, x)
9449 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
9452 for (; x != 0; x = NEXT_INSN (x))
9454 if (may_trap_p (PATTERN (x)))
9456 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
9462 /* This is used by reload pass, that does emit some instructions after
9463 abnormal calls moving basic block end, but in fact it wants to emit
9464 them on the edge. Looks for abnormal call edges, find backward the
9465 proper call and fix the damage.
9467 Similar handle instructions throwing exceptions internally. */
9469 fixup_abnormal_edges ()
9471 bool inserted = false;
9478 /* Look for cases we are interested in - calls or instructions causing
9480 for (e = bb->succ; e; e = e->succ_next)
9482 if (e->flags & EDGE_ABNORMAL_CALL)
9484 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
9485 == (EDGE_ABNORMAL | EDGE_EH))
9488 if (e && GET_CODE (bb->end) != CALL_INSN && !can_throw_internal (bb->end))
9490 rtx insn = bb->end, stop = NEXT_INSN (bb->end);
9492 for (e = bb->succ; e; e = e->succ_next)
9493 if (e->flags & EDGE_FALLTHRU)
9495 /* Get past the new insns generated. Allow notes, as the insns may
9496 be already deleted. */
9497 while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE)
9498 && !can_throw_internal (insn)
9499 && insn != bb->head)
9500 insn = PREV_INSN (insn);
9501 if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn))
9505 insn = NEXT_INSN (insn);
9506 while (insn && insn != stop)
9508 next = NEXT_INSN (insn);
9513 /* Sometimes there's still the return value USE.
9514 If it's placed after a trapping call (i.e. that
9515 call is the last insn anyway), we have no fallthru
9516 edge. Simply delete this use and don't try to insert
9517 on the non-existent edge. */
9518 if (GET_CODE (PATTERN (insn)) != USE)
9520 /* We're not deleting it, we're moving it. */
9521 INSN_DELETED_P (insn) = 0;
9522 PREV_INSN (insn) = NULL_RTX;
9523 NEXT_INSN (insn) = NULL_RTX;
9525 insert_insn_on_edge (insn, e);
9532 /* We've possibly turned single trapping insn into multiple ones. */
9533 if (flag_non_call_exceptions)
9536 blocks = sbitmap_alloc (last_basic_block);
9537 sbitmap_ones (blocks);
9538 find_many_sub_basic_blocks (blocks);
9541 commit_edge_insertions ();
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