1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is an invariant value to which pseudo reg N is equivalent.
100 eliminate_regs_in_insn uses this to replace pseudos in particular
102 rtx *reg_equiv_invariant;
104 /* Element N is a memory location to which pseudo reg N is equivalent,
105 prior to any register elimination (such as frame pointer to stack
106 pointer). Depending on whether or not it is a valid address, this value
107 is transferred to either reg_equiv_address or reg_equiv_mem. */
108 rtx *reg_equiv_memory_loc;
110 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
111 collector can keep track of what is inside. */
112 varray_type reg_equiv_memory_loc_varray;
114 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
115 This is used when the address is not valid as a memory address
116 (because its displacement is too big for the machine.) */
117 rtx *reg_equiv_address;
119 /* Element N is the memory slot to which pseudo reg N is equivalent,
120 or zero if pseudo reg N is not equivalent to a memory slot. */
123 /* Widest width in which each pseudo reg is referred to (via subreg). */
124 static unsigned int *reg_max_ref_width;
126 /* Element N is the list of insns that initialized reg N from its equivalent
127 constant or memory slot. */
129 int reg_equiv_init_size;
131 /* Vector to remember old contents of reg_renumber before spilling. */
132 static short *reg_old_renumber;
134 /* During reload_as_needed, element N contains the last pseudo regno reloaded
135 into hard register N. If that pseudo reg occupied more than one register,
136 reg_reloaded_contents points to that pseudo for each spill register in
137 use; all of these must remain set for an inheritance to occur. */
138 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
140 /* During reload_as_needed, element N contains the insn for which
141 hard register N was last used. Its contents are significant only
142 when reg_reloaded_valid is set for this register. */
143 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
145 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
146 static HARD_REG_SET reg_reloaded_valid;
147 /* Indicate if the register was dead at the end of the reload.
148 This is only valid if reg_reloaded_contents is set and valid. */
149 static HARD_REG_SET reg_reloaded_dead;
151 /* Indicate whether the register's current value is one that is not
152 safe to retain across a call, even for registers that are normally
154 static HARD_REG_SET reg_reloaded_call_part_clobbered;
156 /* Number of spill-regs so far; number of valid elements of spill_regs. */
159 /* In parallel with spill_regs, contains REG rtx's for those regs.
160 Holds the last rtx used for any given reg, or 0 if it has never
161 been used for spilling yet. This rtx is reused, provided it has
163 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
165 /* In parallel with spill_regs, contains nonzero for a spill reg
166 that was stored after the last time it was used.
167 The precise value is the insn generated to do the store. */
168 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
170 /* This is the register that was stored with spill_reg_store. This is a
171 copy of reload_out / reload_out_reg when the value was stored; if
172 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
173 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
175 /* This table is the inverse mapping of spill_regs:
176 indexed by hard reg number,
177 it contains the position of that reg in spill_regs,
178 or -1 for something that is not in spill_regs.
180 ?!? This is no longer accurate. */
181 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
183 /* This reg set indicates registers that can't be used as spill registers for
184 the currently processed insn. These are the hard registers which are live
185 during the insn, but not allocated to pseudos, as well as fixed
187 static HARD_REG_SET bad_spill_regs;
189 /* These are the hard registers that can't be used as spill register for any
190 insn. This includes registers used for user variables and registers that
191 we can't eliminate. A register that appears in this set also can't be used
192 to retry register allocation. */
193 static HARD_REG_SET bad_spill_regs_global;
195 /* Describes order of use of registers for reloading
196 of spilled pseudo-registers. `n_spills' is the number of
197 elements that are actually valid; new ones are added at the end.
199 Both spill_regs and spill_reg_order are used on two occasions:
200 once during find_reload_regs, where they keep track of the spill registers
201 for a single insn, but also during reload_as_needed where they show all
202 the registers ever used by reload. For the latter case, the information
203 is calculated during finish_spills. */
204 static short spill_regs[FIRST_PSEUDO_REGISTER];
206 /* This vector of reg sets indicates, for each pseudo, which hard registers
207 may not be used for retrying global allocation because the register was
208 formerly spilled from one of them. If we allowed reallocating a pseudo to
209 a register that it was already allocated to, reload might not
211 static HARD_REG_SET *pseudo_previous_regs;
213 /* This vector of reg sets indicates, for each pseudo, which hard
214 registers may not be used for retrying global allocation because they
215 are used as spill registers during one of the insns in which the
217 static HARD_REG_SET *pseudo_forbidden_regs;
219 /* All hard regs that have been used as spill registers for any insn are
220 marked in this set. */
221 static HARD_REG_SET used_spill_regs;
223 /* Index of last register assigned as a spill register. We allocate in
224 a round-robin fashion. */
225 static int last_spill_reg;
227 /* Nonzero if indirect addressing is supported on the machine; this means
228 that spilling (REG n) does not require reloading it into a register in
229 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
230 value indicates the level of indirect addressing supported, e.g., two
231 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
233 static char spill_indirect_levels;
235 /* Nonzero if indirect addressing is supported when the innermost MEM is
236 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
237 which these are valid is the same as spill_indirect_levels, above. */
238 char indirect_symref_ok;
240 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
241 char double_reg_address_ok;
243 /* Record the stack slot for each spilled hard register. */
244 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
246 /* Width allocated so far for that stack slot. */
247 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
249 /* Record which pseudos needed to be spilled. */
250 static regset_head spilled_pseudos;
252 /* Used for communication between order_regs_for_reload and count_pseudo.
253 Used to avoid counting one pseudo twice. */
254 static regset_head pseudos_counted;
256 /* First uid used by insns created by reload in this function.
257 Used in find_equiv_reg. */
258 int reload_first_uid;
260 /* Flag set by local-alloc or global-alloc if anything is live in
261 a call-clobbered reg across calls. */
262 int caller_save_needed;
264 /* Set to 1 while reload_as_needed is operating.
265 Required by some machines to handle any generated moves differently. */
266 int reload_in_progress = 0;
268 /* These arrays record the insn_code of insns that may be needed to
269 perform input and output reloads of special objects. They provide a
270 place to pass a scratch register. */
271 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
272 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
274 /* This obstack is used for allocation of rtl during register elimination.
275 The allocated storage can be freed once find_reloads has processed the
277 static struct obstack reload_obstack;
279 /* Points to the beginning of the reload_obstack. All insn_chain structures
280 are allocated first. */
281 static char *reload_startobj;
283 /* The point after all insn_chain structures. Used to quickly deallocate
284 memory allocated in copy_reloads during calculate_needs_all_insns. */
285 static char *reload_firstobj;
287 /* This points before all local rtl generated by register elimination.
288 Used to quickly free all memory after processing one insn. */
289 static char *reload_insn_firstobj;
291 /* List of insn_chain instructions, one for every insn that reload needs to
293 struct insn_chain *reload_insn_chain;
295 /* List of all insns needing reloads. */
296 static struct insn_chain *insns_need_reload;
298 /* This structure is used to record information about register eliminations.
299 Each array entry describes one possible way of eliminating a register
300 in favor of another. If there is more than one way of eliminating a
301 particular register, the most preferred should be specified first. */
305 int from; /* Register number to be eliminated. */
306 int to; /* Register number used as replacement. */
307 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
308 int can_eliminate; /* Nonzero if this elimination can be done. */
309 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
310 insns made by reload. */
311 HOST_WIDE_INT offset; /* Current offset between the two regs. */
312 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
313 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
314 rtx from_rtx; /* REG rtx for the register to be eliminated.
315 We cannot simply compare the number since
316 we might then spuriously replace a hard
317 register corresponding to a pseudo
318 assigned to the reg to be eliminated. */
319 rtx to_rtx; /* REG rtx for the replacement. */
322 static struct elim_table *reg_eliminate = 0;
324 /* This is an intermediate structure to initialize the table. It has
325 exactly the members provided by ELIMINABLE_REGS. */
326 static const struct elim_table_1
330 } reg_eliminate_1[] =
332 /* If a set of eliminable registers was specified, define the table from it.
333 Otherwise, default to the normal case of the frame pointer being
334 replaced by the stack pointer. */
336 #ifdef ELIMINABLE_REGS
339 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
342 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
344 /* Record the number of pending eliminations that have an offset not equal
345 to their initial offset. If nonzero, we use a new copy of each
346 replacement result in any insns encountered. */
347 int num_not_at_initial_offset;
349 /* Count the number of registers that we may be able to eliminate. */
350 static int num_eliminable;
351 /* And the number of registers that are equivalent to a constant that
352 can be eliminated to frame_pointer / arg_pointer + constant. */
353 static int num_eliminable_invariants;
355 /* For each label, we record the offset of each elimination. If we reach
356 a label by more than one path and an offset differs, we cannot do the
357 elimination. This information is indexed by the difference of the
358 number of the label and the first label number. We can't offset the
359 pointer itself as this can cause problems on machines with segmented
360 memory. The first table is an array of flags that records whether we
361 have yet encountered a label and the second table is an array of arrays,
362 one entry in the latter array for each elimination. */
364 static int first_label_num;
365 static char *offsets_known_at;
366 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
368 /* Number of labels in the current function. */
370 static int num_labels;
372 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
373 static void maybe_fix_stack_asms (void);
374 static void copy_reloads (struct insn_chain *);
375 static void calculate_needs_all_insns (int);
376 static int find_reg (struct insn_chain *, int);
377 static void find_reload_regs (struct insn_chain *);
378 static void select_reload_regs (void);
379 static void delete_caller_save_insns (void);
381 static void spill_failure (rtx, enum reg_class);
382 static void count_spilled_pseudo (int, int, int);
383 static void delete_dead_insn (rtx);
384 static void alter_reg (int, int);
385 static void set_label_offsets (rtx, rtx, int);
386 static void check_eliminable_occurrences (rtx);
387 static void elimination_effects (rtx, enum machine_mode);
388 static int eliminate_regs_in_insn (rtx, int);
389 static void update_eliminable_offsets (void);
390 static void mark_not_eliminable (rtx, rtx, void *);
391 static void set_initial_elim_offsets (void);
392 static bool verify_initial_elim_offsets (void);
393 static void set_initial_label_offsets (void);
394 static void set_offsets_for_label (rtx);
395 static void init_elim_table (void);
396 static void update_eliminables (HARD_REG_SET *);
397 static void spill_hard_reg (unsigned int, int);
398 static int finish_spills (int);
399 static void scan_paradoxical_subregs (rtx);
400 static void count_pseudo (int);
401 static void order_regs_for_reload (struct insn_chain *);
402 static void reload_as_needed (int);
403 static void forget_old_reloads_1 (rtx, rtx, void *);
404 static int reload_reg_class_lower (const void *, const void *);
405 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
407 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
409 static int reload_reg_free_p (unsigned int, int, enum reload_type);
410 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
412 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
414 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
415 static int allocate_reload_reg (struct insn_chain *, int, int);
416 static int conflicts_with_override (rtx);
417 static void failed_reload (rtx, int);
418 static int set_reload_reg (int, int);
419 static void choose_reload_regs_init (struct insn_chain *, rtx *);
420 static void choose_reload_regs (struct insn_chain *);
421 static void merge_assigned_reloads (rtx);
422 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
424 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
426 static void do_input_reload (struct insn_chain *, struct reload *, int);
427 static void do_output_reload (struct insn_chain *, struct reload *, int);
428 static bool inherit_piecemeal_p (int, int);
429 static void emit_reload_insns (struct insn_chain *);
430 static void delete_output_reload (rtx, int, int);
431 static void delete_address_reloads (rtx, rtx);
432 static void delete_address_reloads_1 (rtx, rtx, rtx);
433 static rtx inc_for_reload (rtx, rtx, rtx, int);
435 static void add_auto_inc_notes (rtx, rtx);
437 static void copy_eh_notes (rtx, rtx);
438 static int reloads_conflict (int, int);
439 static rtx gen_reload (rtx, rtx, int, enum reload_type);
441 /* Initialize the reload pass once per compilation. */
448 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
449 Set spill_indirect_levels to the number of levels such addressing is
450 permitted, zero if it is not permitted at all. */
453 = gen_rtx_MEM (Pmode,
456 LAST_VIRTUAL_REGISTER + 1),
458 spill_indirect_levels = 0;
460 while (memory_address_p (QImode, tem))
462 spill_indirect_levels++;
463 tem = gen_rtx_MEM (Pmode, tem);
466 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
468 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
469 indirect_symref_ok = memory_address_p (QImode, tem);
471 /* See if reg+reg is a valid (and offsettable) address. */
473 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
475 tem = gen_rtx_PLUS (Pmode,
476 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
477 gen_rtx_REG (Pmode, i));
479 /* This way, we make sure that reg+reg is an offsettable address. */
480 tem = plus_constant (tem, 4);
482 if (memory_address_p (QImode, tem))
484 double_reg_address_ok = 1;
489 /* Initialize obstack for our rtl allocation. */
490 gcc_obstack_init (&reload_obstack);
491 reload_startobj = obstack_alloc (&reload_obstack, 0);
493 INIT_REG_SET (&spilled_pseudos);
494 INIT_REG_SET (&pseudos_counted);
495 VARRAY_RTX_INIT (reg_equiv_memory_loc_varray, 0, "reg_equiv_memory_loc");
498 /* List of insn chains that are currently unused. */
499 static struct insn_chain *unused_insn_chains = 0;
501 /* Allocate an empty insn_chain structure. */
503 new_insn_chain (void)
505 struct insn_chain *c;
507 if (unused_insn_chains == 0)
509 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
510 INIT_REG_SET (&c->live_throughout);
511 INIT_REG_SET (&c->dead_or_set);
515 c = unused_insn_chains;
516 unused_insn_chains = c->next;
518 c->is_caller_save_insn = 0;
519 c->need_operand_change = 0;
525 /* Small utility function to set all regs in hard reg set TO which are
526 allocated to pseudos in regset FROM. */
529 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
532 reg_set_iterator rsi;
534 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
536 int r = reg_renumber[regno];
541 /* reload_combine uses the information from
542 BASIC_BLOCK->global_live_at_start, which might still
543 contain registers that have not actually been allocated
544 since they have an equivalence. */
545 gcc_assert (reload_completed);
549 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)];
551 SET_HARD_REG_BIT (*to, r + nregs);
556 /* Replace all pseudos found in LOC with their corresponding
560 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
573 unsigned int regno = REGNO (x);
575 if (regno < FIRST_PSEUDO_REGISTER)
578 x = eliminate_regs (x, mem_mode, usage);
582 replace_pseudos_in (loc, mem_mode, usage);
586 if (reg_equiv_constant[regno])
587 *loc = reg_equiv_constant[regno];
588 else if (reg_equiv_mem[regno])
589 *loc = reg_equiv_mem[regno];
590 else if (reg_equiv_address[regno])
591 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
594 gcc_assert (!REG_P (regno_reg_rtx[regno])
595 || REGNO (regno_reg_rtx[regno]) != regno);
596 *loc = regno_reg_rtx[regno];
601 else if (code == MEM)
603 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
607 /* Process each of our operands recursively. */
608 fmt = GET_RTX_FORMAT (code);
609 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
611 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
612 else if (*fmt == 'E')
613 for (j = 0; j < XVECLEN (x, i); j++)
614 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
618 /* Global variables used by reload and its subroutines. */
620 /* Set during calculate_needs if an insn needs register elimination. */
621 static int something_needs_elimination;
622 /* Set during calculate_needs if an insn needs an operand changed. */
623 static int something_needs_operands_changed;
625 /* Nonzero means we couldn't get enough spill regs. */
628 /* Main entry point for the reload pass.
630 FIRST is the first insn of the function being compiled.
632 GLOBAL nonzero means we were called from global_alloc
633 and should attempt to reallocate any pseudoregs that we
634 displace from hard regs we will use for reloads.
635 If GLOBAL is zero, we do not have enough information to do that,
636 so any pseudo reg that is spilled must go to the stack.
638 Return value is nonzero if reload failed
639 and we must not do any more for this function. */
642 reload (rtx first, int global)
646 struct elim_table *ep;
649 /* Make sure even insns with volatile mem refs are recognizable. */
654 reload_firstobj = obstack_alloc (&reload_obstack, 0);
656 /* Make sure that the last insn in the chain
657 is not something that needs reloading. */
658 emit_note (NOTE_INSN_DELETED);
660 /* Enable find_equiv_reg to distinguish insns made by reload. */
661 reload_first_uid = get_max_uid ();
663 #ifdef SECONDARY_MEMORY_NEEDED
664 /* Initialize the secondary memory table. */
665 clear_secondary_mem ();
668 /* We don't have a stack slot for any spill reg yet. */
669 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
670 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
672 /* Initialize the save area information for caller-save, in case some
676 /* Compute which hard registers are now in use
677 as homes for pseudo registers.
678 This is done here rather than (eg) in global_alloc
679 because this point is reached even if not optimizing. */
680 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
683 /* A function that receives a nonlocal goto must save all call-saved
685 if (current_function_has_nonlocal_label)
686 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
687 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
688 regs_ever_live[i] = 1;
690 /* Find all the pseudo registers that didn't get hard regs
691 but do have known equivalent constants or memory slots.
692 These include parameters (known equivalent to parameter slots)
693 and cse'd or loop-moved constant memory addresses.
695 Record constant equivalents in reg_equiv_constant
696 so they will be substituted by find_reloads.
697 Record memory equivalents in reg_mem_equiv so they can
698 be substituted eventually by altering the REG-rtx's. */
700 reg_equiv_constant = xcalloc (max_regno, sizeof (rtx));
701 reg_equiv_invariant = xcalloc (max_regno, sizeof (rtx));
702 reg_equiv_mem = xcalloc (max_regno, sizeof (rtx));
703 reg_equiv_address = xcalloc (max_regno, sizeof (rtx));
704 reg_max_ref_width = xcalloc (max_regno, sizeof (int));
705 reg_old_renumber = xcalloc (max_regno, sizeof (short));
706 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
707 pseudo_forbidden_regs = xmalloc (max_regno * sizeof (HARD_REG_SET));
708 pseudo_previous_regs = xcalloc (max_regno, sizeof (HARD_REG_SET));
710 CLEAR_HARD_REG_SET (bad_spill_regs_global);
712 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
713 to. Also find all paradoxical subregs and find largest such for
716 num_eliminable_invariants = 0;
717 for (insn = first; insn; insn = NEXT_INSN (insn))
719 rtx set = single_set (insn);
721 /* We may introduce USEs that we want to remove at the end, so
722 we'll mark them with QImode. Make sure there are no
723 previously-marked insns left by say regmove. */
724 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
725 && GET_MODE (insn) != VOIDmode)
726 PUT_MODE (insn, VOIDmode);
729 scan_paradoxical_subregs (PATTERN (insn));
731 if (set != 0 && REG_P (SET_DEST (set)))
733 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
739 i = REGNO (SET_DEST (set));
742 if (i <= LAST_VIRTUAL_REGISTER)
745 if (! function_invariant_p (x)
747 /* A function invariant is often CONSTANT_P but may
748 include a register. We promise to only pass
749 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
751 && LEGITIMATE_PIC_OPERAND_P (x)))
753 /* It can happen that a REG_EQUIV note contains a MEM
754 that is not a legitimate memory operand. As later
755 stages of reload assume that all addresses found
756 in the reg_equiv_* arrays were originally legitimate,
757 we ignore such REG_EQUIV notes. */
758 if (memory_operand (x, VOIDmode))
760 /* Always unshare the equivalence, so we can
761 substitute into this insn without touching the
763 reg_equiv_memory_loc[i] = copy_rtx (x);
765 else if (function_invariant_p (x))
767 if (GET_CODE (x) == PLUS)
769 /* This is PLUS of frame pointer and a constant,
770 and might be shared. Unshare it. */
771 reg_equiv_invariant[i] = copy_rtx (x);
772 num_eliminable_invariants++;
774 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
776 reg_equiv_invariant[i] = x;
777 num_eliminable_invariants++;
779 else if (LEGITIMATE_CONSTANT_P (x))
780 reg_equiv_constant[i] = x;
783 reg_equiv_memory_loc[i]
784 = force_const_mem (GET_MODE (SET_DEST (set)), x);
785 if (! reg_equiv_memory_loc[i])
786 reg_equiv_init[i] = NULL_RTX;
791 reg_equiv_init[i] = NULL_RTX;
796 reg_equiv_init[i] = NULL_RTX;
801 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
802 if (reg_equiv_init[i])
804 fprintf (dump_file, "init_insns for %u: ", i);
805 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
806 fprintf (dump_file, "\n");
811 first_label_num = get_first_label_num ();
812 num_labels = max_label_num () - first_label_num;
814 /* Allocate the tables used to store offset information at labels. */
815 /* We used to use alloca here, but the size of what it would try to
816 allocate would occasionally cause it to exceed the stack limit and
817 cause a core dump. */
818 offsets_known_at = xmalloc (num_labels);
819 offsets_at = xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
821 /* Alter each pseudo-reg rtx to contain its hard reg number.
822 Assign stack slots to the pseudos that lack hard regs or equivalents.
823 Do not touch virtual registers. */
825 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
828 /* If we have some registers we think can be eliminated, scan all insns to
829 see if there is an insn that sets one of these registers to something
830 other than itself plus a constant. If so, the register cannot be
831 eliminated. Doing this scan here eliminates an extra pass through the
832 main reload loop in the most common case where register elimination
834 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
836 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
838 maybe_fix_stack_asms ();
840 insns_need_reload = 0;
841 something_needs_elimination = 0;
843 /* Initialize to -1, which means take the first spill register. */
846 /* Spill any hard regs that we know we can't eliminate. */
847 CLEAR_HARD_REG_SET (used_spill_regs);
848 /* There can be multiple ways to eliminate a register;
849 they should be listed adjacently.
850 Elimination for any register fails only if all possible ways fail. */
851 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
854 int can_eliminate = 0;
857 can_eliminate |= ep->can_eliminate;
860 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
862 spill_hard_reg (from, 1);
865 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
866 if (frame_pointer_needed)
867 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
869 finish_spills (global);
871 /* From now on, we may need to generate moves differently. We may also
872 allow modifications of insns which cause them to not be recognized.
873 Any such modifications will be cleaned up during reload itself. */
874 reload_in_progress = 1;
876 /* This loop scans the entire function each go-round
877 and repeats until one repetition spills no additional hard regs. */
880 int something_changed;
883 HOST_WIDE_INT starting_frame_size;
885 /* Round size of stack frame to stack_alignment_needed. This must be done
886 here because the stack size may be a part of the offset computation
887 for register elimination, and there might have been new stack slots
888 created in the last iteration of this loop. */
889 if (cfun->stack_alignment_needed)
890 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
892 starting_frame_size = get_frame_size ();
894 set_initial_elim_offsets ();
895 set_initial_label_offsets ();
897 /* For each pseudo register that has an equivalent location defined,
898 try to eliminate any eliminable registers (such as the frame pointer)
899 assuming initial offsets for the replacement register, which
902 If the resulting location is directly addressable, substitute
903 the MEM we just got directly for the old REG.
905 If it is not addressable but is a constant or the sum of a hard reg
906 and constant, it is probably not addressable because the constant is
907 out of range, in that case record the address; we will generate
908 hairy code to compute the address in a register each time it is
909 needed. Similarly if it is a hard register, but one that is not
910 valid as an address register.
912 If the location is not addressable, but does not have one of the
913 above forms, assign a stack slot. We have to do this to avoid the
914 potential of producing lots of reloads if, e.g., a location involves
915 a pseudo that didn't get a hard register and has an equivalent memory
916 location that also involves a pseudo that didn't get a hard register.
918 Perhaps at some point we will improve reload_when_needed handling
919 so this problem goes away. But that's very hairy. */
921 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
922 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
924 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
926 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
928 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
929 else if (CONSTANT_P (XEXP (x, 0))
930 || (REG_P (XEXP (x, 0))
931 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
932 || (GET_CODE (XEXP (x, 0)) == PLUS
933 && REG_P (XEXP (XEXP (x, 0), 0))
934 && (REGNO (XEXP (XEXP (x, 0), 0))
935 < FIRST_PSEUDO_REGISTER)
936 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
937 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
940 /* Make a new stack slot. Then indicate that something
941 changed so we go back and recompute offsets for
942 eliminable registers because the allocation of memory
943 below might change some offset. reg_equiv_{mem,address}
944 will be set up for this pseudo on the next pass around
946 reg_equiv_memory_loc[i] = 0;
947 reg_equiv_init[i] = 0;
952 if (caller_save_needed)
955 /* If we allocated another stack slot, redo elimination bookkeeping. */
956 if (starting_frame_size != get_frame_size ())
959 if (caller_save_needed)
961 save_call_clobbered_regs ();
962 /* That might have allocated new insn_chain structures. */
963 reload_firstobj = obstack_alloc (&reload_obstack, 0);
966 calculate_needs_all_insns (global);
968 CLEAR_REG_SET (&spilled_pseudos);
971 something_changed = 0;
973 /* If we allocated any new memory locations, make another pass
974 since it might have changed elimination offsets. */
975 if (starting_frame_size != get_frame_size ())
976 something_changed = 1;
978 /* Even if the frame size remained the same, we might still have
979 changed elimination offsets, e.g. if find_reloads called
980 force_const_mem requiring the back end to allocate a constant
981 pool base register that needs to be saved on the stack. */
982 else if (!verify_initial_elim_offsets ())
983 something_changed = 1;
986 HARD_REG_SET to_spill;
987 CLEAR_HARD_REG_SET (to_spill);
988 update_eliminables (&to_spill);
989 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
990 if (TEST_HARD_REG_BIT (to_spill, i))
992 spill_hard_reg (i, 1);
995 /* Regardless of the state of spills, if we previously had
996 a register that we thought we could eliminate, but now can
997 not eliminate, we must run another pass.
999 Consider pseudos which have an entry in reg_equiv_* which
1000 reference an eliminable register. We must make another pass
1001 to update reg_equiv_* so that we do not substitute in the
1002 old value from when we thought the elimination could be
1004 something_changed = 1;
1008 select_reload_regs ();
1012 if (insns_need_reload != 0 || did_spill)
1013 something_changed |= finish_spills (global);
1015 if (! something_changed)
1018 if (caller_save_needed)
1019 delete_caller_save_insns ();
1021 obstack_free (&reload_obstack, reload_firstobj);
1024 /* If global-alloc was run, notify it of any register eliminations we have
1027 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1028 if (ep->can_eliminate)
1029 mark_elimination (ep->from, ep->to);
1031 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1032 If that insn didn't set the register (i.e., it copied the register to
1033 memory), just delete that insn instead of the equivalencing insn plus
1034 anything now dead. If we call delete_dead_insn on that insn, we may
1035 delete the insn that actually sets the register if the register dies
1036 there and that is incorrect. */
1038 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1040 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1043 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1045 rtx equiv_insn = XEXP (list, 0);
1047 /* If we already deleted the insn or if it may trap, we can't
1048 delete it. The latter case shouldn't happen, but can
1049 if an insn has a variable address, gets a REG_EH_REGION
1050 note added to it, and then gets converted into a load
1051 from a constant address. */
1052 if (NOTE_P (equiv_insn)
1053 || can_throw_internal (equiv_insn))
1055 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1056 delete_dead_insn (equiv_insn);
1058 SET_INSN_DELETED (equiv_insn);
1063 /* Use the reload registers where necessary
1064 by generating move instructions to move the must-be-register
1065 values into or out of the reload registers. */
1067 if (insns_need_reload != 0 || something_needs_elimination
1068 || something_needs_operands_changed)
1070 HOST_WIDE_INT old_frame_size = get_frame_size ();
1072 reload_as_needed (global);
1074 gcc_assert (old_frame_size == get_frame_size ());
1076 gcc_assert (verify_initial_elim_offsets ());
1079 /* If we were able to eliminate the frame pointer, show that it is no
1080 longer live at the start of any basic block. If it ls live by
1081 virtue of being in a pseudo, that pseudo will be marked live
1082 and hence the frame pointer will be known to be live via that
1085 if (! frame_pointer_needed)
1087 CLEAR_REGNO_REG_SET (bb->il.rtl->global_live_at_start,
1088 HARD_FRAME_POINTER_REGNUM);
1090 /* Come here (with failure set nonzero) if we can't get enough spill
1094 CLEAR_REG_SET (&spilled_pseudos);
1095 reload_in_progress = 0;
1097 /* Now eliminate all pseudo regs by modifying them into
1098 their equivalent memory references.
1099 The REG-rtx's for the pseudos are modified in place,
1100 so all insns that used to refer to them now refer to memory.
1102 For a reg that has a reg_equiv_address, all those insns
1103 were changed by reloading so that no insns refer to it any longer;
1104 but the DECL_RTL of a variable decl may refer to it,
1105 and if so this causes the debugging info to mention the variable. */
1107 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1111 if (reg_equiv_mem[i])
1112 addr = XEXP (reg_equiv_mem[i], 0);
1114 if (reg_equiv_address[i])
1115 addr = reg_equiv_address[i];
1119 if (reg_renumber[i] < 0)
1121 rtx reg = regno_reg_rtx[i];
1123 REG_USERVAR_P (reg) = 0;
1124 PUT_CODE (reg, MEM);
1125 XEXP (reg, 0) = addr;
1126 if (reg_equiv_memory_loc[i])
1127 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1130 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1131 MEM_ATTRS (reg) = 0;
1133 MEM_NOTRAP_P (reg) = 1;
1135 else if (reg_equiv_mem[i])
1136 XEXP (reg_equiv_mem[i], 0) = addr;
1140 /* We must set reload_completed now since the cleanup_subreg_operands call
1141 below will re-recognize each insn and reload may have generated insns
1142 which are only valid during and after reload. */
1143 reload_completed = 1;
1145 /* Make a pass over all the insns and delete all USEs which we inserted
1146 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1147 notes. Delete all CLOBBER insns, except those that refer to the return
1148 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1149 from misarranging variable-array code, and simplify (subreg (reg))
1150 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1151 are no longer useful or accurate. Strip and regenerate REG_INC notes
1152 that may have been moved around. */
1154 for (insn = first; insn; insn = NEXT_INSN (insn))
1160 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1161 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1163 if ((GET_CODE (PATTERN (insn)) == USE
1164 /* We mark with QImode USEs introduced by reload itself. */
1165 && (GET_MODE (insn) == QImode
1166 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1167 || (GET_CODE (PATTERN (insn)) == CLOBBER
1168 && (!MEM_P (XEXP (PATTERN (insn), 0))
1169 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1170 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1171 && XEXP (XEXP (PATTERN (insn), 0), 0)
1172 != stack_pointer_rtx))
1173 && (!REG_P (XEXP (PATTERN (insn), 0))
1174 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1180 /* Some CLOBBERs may survive until here and still reference unassigned
1181 pseudos with const equivalent, which may in turn cause ICE in later
1182 passes if the reference remains in place. */
1183 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1184 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1185 VOIDmode, PATTERN (insn));
1187 /* Discard obvious no-ops, even without -O. This optimization
1188 is fast and doesn't interfere with debugging. */
1189 if (NONJUMP_INSN_P (insn)
1190 && GET_CODE (PATTERN (insn)) == SET
1191 && REG_P (SET_SRC (PATTERN (insn)))
1192 && REG_P (SET_DEST (PATTERN (insn)))
1193 && (REGNO (SET_SRC (PATTERN (insn)))
1194 == REGNO (SET_DEST (PATTERN (insn)))))
1200 pnote = ®_NOTES (insn);
1203 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1204 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1205 || REG_NOTE_KIND (*pnote) == REG_INC
1206 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1207 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1208 *pnote = XEXP (*pnote, 1);
1210 pnote = &XEXP (*pnote, 1);
1214 add_auto_inc_notes (insn, PATTERN (insn));
1217 /* And simplify (subreg (reg)) if it appears as an operand. */
1218 cleanup_subreg_operands (insn);
1221 /* If we are doing stack checking, give a warning if this function's
1222 frame size is larger than we expect. */
1223 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1225 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1226 static int verbose_warned = 0;
1228 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1229 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1230 size += UNITS_PER_WORD;
1232 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1234 warning (0, "frame size too large for reliable stack checking");
1235 if (! verbose_warned)
1237 warning (0, "try reducing the number of local variables");
1243 /* Indicate that we no longer have known memory locations or constants. */
1244 if (reg_equiv_constant)
1245 free (reg_equiv_constant);
1246 if (reg_equiv_invariant)
1247 free (reg_equiv_invariant);
1248 reg_equiv_constant = 0;
1249 reg_equiv_invariant = 0;
1250 VARRAY_GROW (reg_equiv_memory_loc_varray, 0);
1251 reg_equiv_memory_loc = 0;
1253 if (offsets_known_at)
1254 free (offsets_known_at);
1258 free (reg_equiv_mem);
1260 free (reg_equiv_address);
1261 free (reg_max_ref_width);
1262 free (reg_old_renumber);
1263 free (pseudo_previous_regs);
1264 free (pseudo_forbidden_regs);
1266 CLEAR_HARD_REG_SET (used_spill_regs);
1267 for (i = 0; i < n_spills; i++)
1268 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1270 /* Free all the insn_chain structures at once. */
1271 obstack_free (&reload_obstack, reload_startobj);
1272 unused_insn_chains = 0;
1273 fixup_abnormal_edges ();
1275 /* Replacing pseudos with their memory equivalents might have
1276 created shared rtx. Subsequent passes would get confused
1277 by this, so unshare everything here. */
1278 unshare_all_rtl_again (first);
1280 #ifdef STACK_BOUNDARY
1281 /* init_emit has set the alignment of the hard frame pointer
1282 to STACK_BOUNDARY. It is very likely no longer valid if
1283 the hard frame pointer was used for register allocation. */
1284 if (!frame_pointer_needed)
1285 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1291 /* Yet another special case. Unfortunately, reg-stack forces people to
1292 write incorrect clobbers in asm statements. These clobbers must not
1293 cause the register to appear in bad_spill_regs, otherwise we'll call
1294 fatal_insn later. We clear the corresponding regnos in the live
1295 register sets to avoid this.
1296 The whole thing is rather sick, I'm afraid. */
1299 maybe_fix_stack_asms (void)
1302 const char *constraints[MAX_RECOG_OPERANDS];
1303 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1304 struct insn_chain *chain;
1306 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1309 HARD_REG_SET clobbered, allowed;
1312 if (! INSN_P (chain->insn)
1313 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1315 pat = PATTERN (chain->insn);
1316 if (GET_CODE (pat) != PARALLEL)
1319 CLEAR_HARD_REG_SET (clobbered);
1320 CLEAR_HARD_REG_SET (allowed);
1322 /* First, make a mask of all stack regs that are clobbered. */
1323 for (i = 0; i < XVECLEN (pat, 0); i++)
1325 rtx t = XVECEXP (pat, 0, i);
1326 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1327 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1330 /* Get the operand values and constraints out of the insn. */
1331 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1332 constraints, operand_mode);
1334 /* For every operand, see what registers are allowed. */
1335 for (i = 0; i < noperands; i++)
1337 const char *p = constraints[i];
1338 /* For every alternative, we compute the class of registers allowed
1339 for reloading in CLS, and merge its contents into the reg set
1341 int cls = (int) NO_REGS;
1347 if (c == '\0' || c == ',' || c == '#')
1349 /* End of one alternative - mark the regs in the current
1350 class, and reset the class. */
1351 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1357 } while (c != '\0' && c != ',');
1365 case '=': case '+': case '*': case '%': case '?': case '!':
1366 case '0': case '1': case '2': case '3': case '4': case 'm':
1367 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1368 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1369 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1374 cls = (int) reg_class_subunion[cls]
1375 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1380 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1384 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1385 cls = (int) reg_class_subunion[cls]
1386 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1388 cls = (int) reg_class_subunion[cls]
1389 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1391 p += CONSTRAINT_LEN (c, p);
1394 /* Those of the registers which are clobbered, but allowed by the
1395 constraints, must be usable as reload registers. So clear them
1396 out of the life information. */
1397 AND_HARD_REG_SET (allowed, clobbered);
1398 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1399 if (TEST_HARD_REG_BIT (allowed, i))
1401 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1402 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1409 /* Copy the global variables n_reloads and rld into the corresponding elts
1412 copy_reloads (struct insn_chain *chain)
1414 chain->n_reloads = n_reloads;
1415 chain->rld = obstack_alloc (&reload_obstack,
1416 n_reloads * sizeof (struct reload));
1417 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1418 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1421 /* Walk the chain of insns, and determine for each whether it needs reloads
1422 and/or eliminations. Build the corresponding insns_need_reload list, and
1423 set something_needs_elimination as appropriate. */
1425 calculate_needs_all_insns (int global)
1427 struct insn_chain **pprev_reload = &insns_need_reload;
1428 struct insn_chain *chain, *next = 0;
1430 something_needs_elimination = 0;
1432 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1433 for (chain = reload_insn_chain; chain != 0; chain = next)
1435 rtx insn = chain->insn;
1439 /* Clear out the shortcuts. */
1440 chain->n_reloads = 0;
1441 chain->need_elim = 0;
1442 chain->need_reload = 0;
1443 chain->need_operand_change = 0;
1445 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1446 include REG_LABEL), we need to see what effects this has on the
1447 known offsets at labels. */
1449 if (LABEL_P (insn) || JUMP_P (insn)
1450 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1451 set_label_offsets (insn, insn, 0);
1455 rtx old_body = PATTERN (insn);
1456 int old_code = INSN_CODE (insn);
1457 rtx old_notes = REG_NOTES (insn);
1458 int did_elimination = 0;
1459 int operands_changed = 0;
1460 rtx set = single_set (insn);
1462 /* Skip insns that only set an equivalence. */
1463 if (set && REG_P (SET_DEST (set))
1464 && reg_renumber[REGNO (SET_DEST (set))] < 0
1465 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1466 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1467 && reg_equiv_init[REGNO (SET_DEST (set))])
1470 /* If needed, eliminate any eliminable registers. */
1471 if (num_eliminable || num_eliminable_invariants)
1472 did_elimination = eliminate_regs_in_insn (insn, 0);
1474 /* Analyze the instruction. */
1475 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1476 global, spill_reg_order);
1478 /* If a no-op set needs more than one reload, this is likely
1479 to be something that needs input address reloads. We
1480 can't get rid of this cleanly later, and it is of no use
1481 anyway, so discard it now.
1482 We only do this when expensive_optimizations is enabled,
1483 since this complements reload inheritance / output
1484 reload deletion, and it can make debugging harder. */
1485 if (flag_expensive_optimizations && n_reloads > 1)
1487 rtx set = single_set (insn);
1489 && SET_SRC (set) == SET_DEST (set)
1490 && REG_P (SET_SRC (set))
1491 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1494 /* Delete it from the reload chain. */
1496 chain->prev->next = next;
1498 reload_insn_chain = next;
1500 next->prev = chain->prev;
1501 chain->next = unused_insn_chains;
1502 unused_insn_chains = chain;
1507 update_eliminable_offsets ();
1509 /* Remember for later shortcuts which insns had any reloads or
1510 register eliminations. */
1511 chain->need_elim = did_elimination;
1512 chain->need_reload = n_reloads > 0;
1513 chain->need_operand_change = operands_changed;
1515 /* Discard any register replacements done. */
1516 if (did_elimination)
1518 obstack_free (&reload_obstack, reload_insn_firstobj);
1519 PATTERN (insn) = old_body;
1520 INSN_CODE (insn) = old_code;
1521 REG_NOTES (insn) = old_notes;
1522 something_needs_elimination = 1;
1525 something_needs_operands_changed |= operands_changed;
1529 copy_reloads (chain);
1530 *pprev_reload = chain;
1531 pprev_reload = &chain->next_need_reload;
1538 /* Comparison function for qsort to decide which of two reloads
1539 should be handled first. *P1 and *P2 are the reload numbers. */
1542 reload_reg_class_lower (const void *r1p, const void *r2p)
1544 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1547 /* Consider required reloads before optional ones. */
1548 t = rld[r1].optional - rld[r2].optional;
1552 /* Count all solitary classes before non-solitary ones. */
1553 t = ((reg_class_size[(int) rld[r2].class] == 1)
1554 - (reg_class_size[(int) rld[r1].class] == 1));
1558 /* Aside from solitaires, consider all multi-reg groups first. */
1559 t = rld[r2].nregs - rld[r1].nregs;
1563 /* Consider reloads in order of increasing reg-class number. */
1564 t = (int) rld[r1].class - (int) rld[r2].class;
1568 /* If reloads are equally urgent, sort by reload number,
1569 so that the results of qsort leave nothing to chance. */
1573 /* The cost of spilling each hard reg. */
1574 static int spill_cost[FIRST_PSEUDO_REGISTER];
1576 /* When spilling multiple hard registers, we use SPILL_COST for the first
1577 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1578 only the first hard reg for a multi-reg pseudo. */
1579 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1581 /* Update the spill cost arrays, considering that pseudo REG is live. */
1584 count_pseudo (int reg)
1586 int freq = REG_FREQ (reg);
1587 int r = reg_renumber[reg];
1590 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1591 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1594 SET_REGNO_REG_SET (&pseudos_counted, reg);
1596 gcc_assert (r >= 0);
1598 spill_add_cost[r] += freq;
1600 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1602 spill_cost[r + nregs] += freq;
1605 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1606 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1609 order_regs_for_reload (struct insn_chain *chain)
1612 HARD_REG_SET used_by_pseudos;
1613 HARD_REG_SET used_by_pseudos2;
1614 reg_set_iterator rsi;
1616 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1618 memset (spill_cost, 0, sizeof spill_cost);
1619 memset (spill_add_cost, 0, sizeof spill_add_cost);
1621 /* Count number of uses of each hard reg by pseudo regs allocated to it
1622 and then order them by decreasing use. First exclude hard registers
1623 that are live in or across this insn. */
1625 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1626 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1627 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1628 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1630 /* Now find out which pseudos are allocated to it, and update
1632 CLEAR_REG_SET (&pseudos_counted);
1634 EXECUTE_IF_SET_IN_REG_SET
1635 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1639 EXECUTE_IF_SET_IN_REG_SET
1640 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1644 CLEAR_REG_SET (&pseudos_counted);
1647 /* Vector of reload-numbers showing the order in which the reloads should
1649 static short reload_order[MAX_RELOADS];
1651 /* This is used to keep track of the spill regs used in one insn. */
1652 static HARD_REG_SET used_spill_regs_local;
1654 /* We decided to spill hard register SPILLED, which has a size of
1655 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1656 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1657 update SPILL_COST/SPILL_ADD_COST. */
1660 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1662 int r = reg_renumber[reg];
1663 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1665 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1666 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1669 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1671 spill_add_cost[r] -= REG_FREQ (reg);
1673 spill_cost[r + nregs] -= REG_FREQ (reg);
1676 /* Find reload register to use for reload number ORDER. */
1679 find_reg (struct insn_chain *chain, int order)
1681 int rnum = reload_order[order];
1682 struct reload *rl = rld + rnum;
1683 int best_cost = INT_MAX;
1687 HARD_REG_SET not_usable;
1688 HARD_REG_SET used_by_other_reload;
1689 reg_set_iterator rsi;
1691 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1692 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1693 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1695 CLEAR_HARD_REG_SET (used_by_other_reload);
1696 for (k = 0; k < order; k++)
1698 int other = reload_order[k];
1700 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1701 for (j = 0; j < rld[other].nregs; j++)
1702 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1705 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1707 unsigned int regno = i;
1709 if (! TEST_HARD_REG_BIT (not_usable, regno)
1710 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1711 && HARD_REGNO_MODE_OK (regno, rl->mode))
1713 int this_cost = spill_cost[regno];
1715 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1717 for (j = 1; j < this_nregs; j++)
1719 this_cost += spill_add_cost[regno + j];
1720 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1721 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1726 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1728 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1730 if (this_cost < best_cost
1731 /* Among registers with equal cost, prefer caller-saved ones, or
1732 use REG_ALLOC_ORDER if it is defined. */
1733 || (this_cost == best_cost
1734 #ifdef REG_ALLOC_ORDER
1735 && (inv_reg_alloc_order[regno]
1736 < inv_reg_alloc_order[best_reg])
1738 && call_used_regs[regno]
1739 && ! call_used_regs[best_reg]
1744 best_cost = this_cost;
1752 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1754 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1755 rl->regno = best_reg;
1757 EXECUTE_IF_SET_IN_REG_SET
1758 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1760 count_spilled_pseudo (best_reg, rl->nregs, j);
1763 EXECUTE_IF_SET_IN_REG_SET
1764 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1766 count_spilled_pseudo (best_reg, rl->nregs, j);
1769 for (i = 0; i < rl->nregs; i++)
1771 gcc_assert (spill_cost[best_reg + i] == 0);
1772 gcc_assert (spill_add_cost[best_reg + i] == 0);
1773 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1778 /* Find more reload regs to satisfy the remaining need of an insn, which
1780 Do it by ascending class number, since otherwise a reg
1781 might be spilled for a big class and might fail to count
1782 for a smaller class even though it belongs to that class. */
1785 find_reload_regs (struct insn_chain *chain)
1789 /* In order to be certain of getting the registers we need,
1790 we must sort the reloads into order of increasing register class.
1791 Then our grabbing of reload registers will parallel the process
1792 that provided the reload registers. */
1793 for (i = 0; i < chain->n_reloads; i++)
1795 /* Show whether this reload already has a hard reg. */
1796 if (chain->rld[i].reg_rtx)
1798 int regno = REGNO (chain->rld[i].reg_rtx);
1799 chain->rld[i].regno = regno;
1801 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1804 chain->rld[i].regno = -1;
1805 reload_order[i] = i;
1808 n_reloads = chain->n_reloads;
1809 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1811 CLEAR_HARD_REG_SET (used_spill_regs_local);
1814 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1816 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1818 /* Compute the order of preference for hard registers to spill. */
1820 order_regs_for_reload (chain);
1822 for (i = 0; i < n_reloads; i++)
1824 int r = reload_order[i];
1826 /* Ignore reloads that got marked inoperative. */
1827 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1828 && ! rld[r].optional
1829 && rld[r].regno == -1)
1830 if (! find_reg (chain, i))
1832 spill_failure (chain->insn, rld[r].class);
1838 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1839 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1841 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1845 select_reload_regs (void)
1847 struct insn_chain *chain;
1849 /* Try to satisfy the needs for each insn. */
1850 for (chain = insns_need_reload; chain != 0;
1851 chain = chain->next_need_reload)
1852 find_reload_regs (chain);
1855 /* Delete all insns that were inserted by emit_caller_save_insns during
1858 delete_caller_save_insns (void)
1860 struct insn_chain *c = reload_insn_chain;
1864 while (c != 0 && c->is_caller_save_insn)
1866 struct insn_chain *next = c->next;
1869 if (c == reload_insn_chain)
1870 reload_insn_chain = next;
1874 next->prev = c->prev;
1876 c->prev->next = next;
1877 c->next = unused_insn_chains;
1878 unused_insn_chains = c;
1886 /* Handle the failure to find a register to spill.
1887 INSN should be one of the insns which needed this particular spill reg. */
1890 spill_failure (rtx insn, enum reg_class class)
1892 if (asm_noperands (PATTERN (insn)) >= 0)
1893 error_for_asm (insn, "can't find a register in class %qs while "
1894 "reloading %<asm%>",
1895 reg_class_names[class]);
1898 error ("unable to find a register to spill in class %qs",
1899 reg_class_names[class]);
1900 fatal_insn ("this is the insn:", insn);
1904 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1905 data that is dead in INSN. */
1908 delete_dead_insn (rtx insn)
1910 rtx prev = prev_real_insn (insn);
1913 /* If the previous insn sets a register that dies in our insn, delete it
1915 if (prev && GET_CODE (PATTERN (prev)) == SET
1916 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
1917 && reg_mentioned_p (prev_dest, PATTERN (insn))
1918 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1919 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1920 delete_dead_insn (prev);
1922 SET_INSN_DELETED (insn);
1925 /* Modify the home of pseudo-reg I.
1926 The new home is present in reg_renumber[I].
1928 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1929 or it may be -1, meaning there is none or it is not relevant.
1930 This is used so that all pseudos spilled from a given hard reg
1931 can share one stack slot. */
1934 alter_reg (int i, int from_reg)
1936 /* When outputting an inline function, this can happen
1937 for a reg that isn't actually used. */
1938 if (regno_reg_rtx[i] == 0)
1941 /* If the reg got changed to a MEM at rtl-generation time,
1943 if (!REG_P (regno_reg_rtx[i]))
1946 /* Modify the reg-rtx to contain the new hard reg
1947 number or else to contain its pseudo reg number. */
1948 REGNO (regno_reg_rtx[i])
1949 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1951 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1952 allocate a stack slot for it. */
1954 if (reg_renumber[i] < 0
1955 && REG_N_REFS (i) > 0
1956 && reg_equiv_constant[i] == 0
1957 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
1958 && reg_equiv_memory_loc[i] == 0)
1961 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1962 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1965 /* Each pseudo reg has an inherent size which comes from its own mode,
1966 and a total size which provides room for paradoxical subregs
1967 which refer to the pseudo reg in wider modes.
1969 We can use a slot already allocated if it provides both
1970 enough inherent space and enough total space.
1971 Otherwise, we allocate a new slot, making sure that it has no less
1972 inherent space, and no less total space, then the previous slot. */
1975 /* No known place to spill from => no slot to reuse. */
1976 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1977 inherent_size == total_size ? 0 : -1);
1978 if (BYTES_BIG_ENDIAN)
1979 /* Cancel the big-endian correction done in assign_stack_local.
1980 Get the address of the beginning of the slot.
1981 This is so we can do a big-endian correction unconditionally
1983 adjust = inherent_size - total_size;
1985 /* Nothing can alias this slot except this pseudo. */
1986 set_mem_alias_set (x, new_alias_set ());
1989 /* Reuse a stack slot if possible. */
1990 else if (spill_stack_slot[from_reg] != 0
1991 && spill_stack_slot_width[from_reg] >= total_size
1992 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1994 x = spill_stack_slot[from_reg];
1996 /* Allocate a bigger slot. */
1999 /* Compute maximum size needed, both for inherent size
2000 and for total size. */
2001 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2004 if (spill_stack_slot[from_reg])
2006 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2008 mode = GET_MODE (spill_stack_slot[from_reg]);
2009 if (spill_stack_slot_width[from_reg] > total_size)
2010 total_size = spill_stack_slot_width[from_reg];
2013 /* Make a slot with that size. */
2014 x = assign_stack_local (mode, total_size,
2015 inherent_size == total_size ? 0 : -1);
2018 /* All pseudos mapped to this slot can alias each other. */
2019 if (spill_stack_slot[from_reg])
2020 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2022 set_mem_alias_set (x, new_alias_set ());
2024 if (BYTES_BIG_ENDIAN)
2026 /* Cancel the big-endian correction done in assign_stack_local.
2027 Get the address of the beginning of the slot.
2028 This is so we can do a big-endian correction unconditionally
2030 adjust = GET_MODE_SIZE (mode) - total_size;
2033 = adjust_address_nv (x, mode_for_size (total_size
2039 spill_stack_slot[from_reg] = stack_slot;
2040 spill_stack_slot_width[from_reg] = total_size;
2043 /* On a big endian machine, the "address" of the slot
2044 is the address of the low part that fits its inherent mode. */
2045 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2046 adjust += (total_size - inherent_size);
2048 /* If we have any adjustment to make, or if the stack slot is the
2049 wrong mode, make a new stack slot. */
2050 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2052 /* If we have a decl for the original register, set it for the
2053 memory. If this is a shared MEM, make a copy. */
2054 if (REG_EXPR (regno_reg_rtx[i])
2055 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2057 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2059 /* We can do this only for the DECLs home pseudo, not for
2060 any copies of it, since otherwise when the stack slot
2061 is reused, nonoverlapping_memrefs_p might think they
2063 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2065 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2068 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2072 /* Save the stack slot for later. */
2073 reg_equiv_memory_loc[i] = x;
2077 /* Mark the slots in regs_ever_live for the hard regs
2078 used by pseudo-reg number REGNO. */
2081 mark_home_live (int regno)
2085 i = reg_renumber[regno];
2088 lim = i + hard_regno_nregs[i][PSEUDO_REGNO_MODE (regno)];
2090 regs_ever_live[i++] = 1;
2093 /* This function handles the tracking of elimination offsets around branches.
2095 X is a piece of RTL being scanned.
2097 INSN is the insn that it came from, if any.
2099 INITIAL_P is nonzero if we are to set the offset to be the initial
2100 offset and zero if we are setting the offset of the label to be the
2104 set_label_offsets (rtx x, rtx insn, int initial_p)
2106 enum rtx_code code = GET_CODE (x);
2109 struct elim_table *p;
2114 if (LABEL_REF_NONLOCAL_P (x))
2119 /* ... fall through ... */
2122 /* If we know nothing about this label, set the desired offsets. Note
2123 that this sets the offset at a label to be the offset before a label
2124 if we don't know anything about the label. This is not correct for
2125 the label after a BARRIER, but is the best guess we can make. If
2126 we guessed wrong, we will suppress an elimination that might have
2127 been possible had we been able to guess correctly. */
2129 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2131 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2132 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2133 = (initial_p ? reg_eliminate[i].initial_offset
2134 : reg_eliminate[i].offset);
2135 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2138 /* Otherwise, if this is the definition of a label and it is
2139 preceded by a BARRIER, set our offsets to the known offset of
2143 && (tem = prev_nonnote_insn (insn)) != 0
2145 set_offsets_for_label (insn);
2147 /* If neither of the above cases is true, compare each offset
2148 with those previously recorded and suppress any eliminations
2149 where the offsets disagree. */
2151 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2152 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2153 != (initial_p ? reg_eliminate[i].initial_offset
2154 : reg_eliminate[i].offset))
2155 reg_eliminate[i].can_eliminate = 0;
2160 set_label_offsets (PATTERN (insn), insn, initial_p);
2162 /* ... fall through ... */
2166 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2167 and hence must have all eliminations at their initial offsets. */
2168 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2169 if (REG_NOTE_KIND (tem) == REG_LABEL)
2170 set_label_offsets (XEXP (tem, 0), insn, 1);
2176 /* Each of the labels in the parallel or address vector must be
2177 at their initial offsets. We want the first field for PARALLEL
2178 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2180 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2181 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2186 /* We only care about setting PC. If the source is not RETURN,
2187 IF_THEN_ELSE, or a label, disable any eliminations not at
2188 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2189 isn't one of those possibilities. For branches to a label,
2190 call ourselves recursively.
2192 Note that this can disable elimination unnecessarily when we have
2193 a non-local goto since it will look like a non-constant jump to
2194 someplace in the current function. This isn't a significant
2195 problem since such jumps will normally be when all elimination
2196 pairs are back to their initial offsets. */
2198 if (SET_DEST (x) != pc_rtx)
2201 switch (GET_CODE (SET_SRC (x)))
2208 set_label_offsets (SET_SRC (x), insn, initial_p);
2212 tem = XEXP (SET_SRC (x), 1);
2213 if (GET_CODE (tem) == LABEL_REF)
2214 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2215 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2218 tem = XEXP (SET_SRC (x), 2);
2219 if (GET_CODE (tem) == LABEL_REF)
2220 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2221 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2229 /* If we reach here, all eliminations must be at their initial
2230 offset because we are doing a jump to a variable address. */
2231 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2232 if (p->offset != p->initial_offset)
2233 p->can_eliminate = 0;
2241 /* Scan X and replace any eliminable registers (such as fp) with a
2242 replacement (such as sp), plus an offset.
2244 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2245 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2246 MEM, we are allowed to replace a sum of a register and the constant zero
2247 with the register, which we cannot do outside a MEM. In addition, we need
2248 to record the fact that a register is referenced outside a MEM.
2250 If INSN is an insn, it is the insn containing X. If we replace a REG
2251 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2252 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2253 the REG is being modified.
2255 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2256 That's used when we eliminate in expressions stored in notes.
2257 This means, do not set ref_outside_mem even if the reference
2260 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2261 replacements done assuming all offsets are at their initial values. If
2262 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2263 encounter, return the actual location so that find_reloads will do
2264 the proper thing. */
2267 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2268 bool may_use_invariant)
2270 enum rtx_code code = GET_CODE (x);
2271 struct elim_table *ep;
2278 if (! current_function_decl)
2300 /* First handle the case where we encounter a bare register that
2301 is eliminable. Replace it with a PLUS. */
2302 if (regno < FIRST_PSEUDO_REGISTER)
2304 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2306 if (ep->from_rtx == x && ep->can_eliminate)
2307 return plus_constant (ep->to_rtx, ep->previous_offset);
2310 else if (reg_renumber && reg_renumber[regno] < 0
2311 && reg_equiv_invariant && reg_equiv_invariant[regno])
2313 if (may_use_invariant)
2314 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2315 mem_mode, insn, true);
2316 /* There exists at least one use of REGNO that cannot be
2317 eliminated. Prevent the defining insn from being deleted. */
2318 reg_equiv_init[regno] = NULL_RTX;
2319 alter_reg (regno, -1);
2323 /* You might think handling MINUS in a manner similar to PLUS is a
2324 good idea. It is not. It has been tried multiple times and every
2325 time the change has had to have been reverted.
2327 Other parts of reload know a PLUS is special (gen_reload for example)
2328 and require special code to handle code a reloaded PLUS operand.
2330 Also consider backends where the flags register is clobbered by a
2331 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2332 lea instruction comes to mind). If we try to reload a MINUS, we
2333 may kill the flags register that was holding a useful value.
2335 So, please before trying to handle MINUS, consider reload as a
2336 whole instead of this little section as well as the backend issues. */
2338 /* If this is the sum of an eliminable register and a constant, rework
2340 if (REG_P (XEXP (x, 0))
2341 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2342 && CONSTANT_P (XEXP (x, 1)))
2344 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2346 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2348 /* The only time we want to replace a PLUS with a REG (this
2349 occurs when the constant operand of the PLUS is the negative
2350 of the offset) is when we are inside a MEM. We won't want
2351 to do so at other times because that would change the
2352 structure of the insn in a way that reload can't handle.
2353 We special-case the commonest situation in
2354 eliminate_regs_in_insn, so just replace a PLUS with a
2355 PLUS here, unless inside a MEM. */
2356 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2357 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2360 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2361 plus_constant (XEXP (x, 1),
2362 ep->previous_offset));
2365 /* If the register is not eliminable, we are done since the other
2366 operand is a constant. */
2370 /* If this is part of an address, we want to bring any constant to the
2371 outermost PLUS. We will do this by doing register replacement in
2372 our operands and seeing if a constant shows up in one of them.
2374 Note that there is no risk of modifying the structure of the insn,
2375 since we only get called for its operands, thus we are either
2376 modifying the address inside a MEM, or something like an address
2377 operand of a load-address insn. */
2380 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2381 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2383 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2385 /* If one side is a PLUS and the other side is a pseudo that
2386 didn't get a hard register but has a reg_equiv_constant,
2387 we must replace the constant here since it may no longer
2388 be in the position of any operand. */
2389 if (GET_CODE (new0) == PLUS && REG_P (new1)
2390 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2391 && reg_renumber[REGNO (new1)] < 0
2392 && reg_equiv_constant != 0
2393 && reg_equiv_constant[REGNO (new1)] != 0)
2394 new1 = reg_equiv_constant[REGNO (new1)];
2395 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2396 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2397 && reg_renumber[REGNO (new0)] < 0
2398 && reg_equiv_constant[REGNO (new0)] != 0)
2399 new0 = reg_equiv_constant[REGNO (new0)];
2401 new = form_sum (new0, new1);
2403 /* As above, if we are not inside a MEM we do not want to
2404 turn a PLUS into something else. We might try to do so here
2405 for an addition of 0 if we aren't optimizing. */
2406 if (! mem_mode && GET_CODE (new) != PLUS)
2407 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2415 /* If this is the product of an eliminable register and a
2416 constant, apply the distribute law and move the constant out
2417 so that we have (plus (mult ..) ..). This is needed in order
2418 to keep load-address insns valid. This case is pathological.
2419 We ignore the possibility of overflow here. */
2420 if (REG_P (XEXP (x, 0))
2421 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2422 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2423 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2425 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2428 /* Refs inside notes don't count for this purpose. */
2429 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2430 || GET_CODE (insn) == INSN_LIST)))
2431 ep->ref_outside_mem = 1;
2434 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2435 ep->previous_offset * INTVAL (XEXP (x, 1)));
2438 /* ... fall through ... */
2442 /* See comments before PLUS about handling MINUS. */
2444 case DIV: case UDIV:
2445 case MOD: case UMOD:
2446 case AND: case IOR: case XOR:
2447 case ROTATERT: case ROTATE:
2448 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2450 case GE: case GT: case GEU: case GTU:
2451 case LE: case LT: case LEU: case LTU:
2453 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2454 rtx new1 = XEXP (x, 1)
2455 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2457 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2458 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2463 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2466 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2467 if (new != XEXP (x, 0))
2469 /* If this is a REG_DEAD note, it is not valid anymore.
2470 Using the eliminated version could result in creating a
2471 REG_DEAD note for the stack or frame pointer. */
2472 if (GET_MODE (x) == REG_DEAD)
2474 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2477 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2481 /* ... fall through ... */
2484 /* Now do eliminations in the rest of the chain. If this was
2485 an EXPR_LIST, this might result in allocating more memory than is
2486 strictly needed, but it simplifies the code. */
2489 new = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2490 if (new != XEXP (x, 1))
2492 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2500 case STRICT_LOW_PART:
2502 case SIGN_EXTEND: case ZERO_EXTEND:
2503 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2504 case FLOAT: case FIX:
2505 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2513 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2514 if (new != XEXP (x, 0))
2515 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2519 /* Similar to above processing, but preserve SUBREG_BYTE.
2520 Convert (subreg (mem)) to (mem) if not paradoxical.
2521 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2522 pseudo didn't get a hard reg, we must replace this with the
2523 eliminated version of the memory location because push_reload
2524 may do the replacement in certain circumstances. */
2525 if (REG_P (SUBREG_REG (x))
2526 && (GET_MODE_SIZE (GET_MODE (x))
2527 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2528 && reg_equiv_memory_loc != 0
2529 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2531 new = SUBREG_REG (x);
2534 new = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2536 if (new != SUBREG_REG (x))
2538 int x_size = GET_MODE_SIZE (GET_MODE (x));
2539 int new_size = GET_MODE_SIZE (GET_MODE (new));
2542 && ((x_size < new_size
2543 #ifdef WORD_REGISTER_OPERATIONS
2544 /* On these machines, combine can create rtl of the form
2545 (set (subreg:m1 (reg:m2 R) 0) ...)
2546 where m1 < m2, and expects something interesting to
2547 happen to the entire word. Moreover, it will use the
2548 (reg:m2 R) later, expecting all bits to be preserved.
2549 So if the number of words is the same, preserve the
2550 subreg so that push_reload can see it. */
2551 && ! ((x_size - 1) / UNITS_PER_WORD
2552 == (new_size -1 ) / UNITS_PER_WORD)
2555 || x_size == new_size)
2557 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2559 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2565 /* Our only special processing is to pass the mode of the MEM to our
2566 recursive call and copy the flags. While we are here, handle this
2567 case more efficiently. */
2569 replace_equiv_address_nv (x,
2570 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2574 /* Handle insn_list USE that a call to a pure function may generate. */
2575 new = eliminate_regs_1 (XEXP (x, 0), 0, insn, false);
2576 if (new != XEXP (x, 0))
2577 return gen_rtx_USE (GET_MODE (x), new);
2589 /* Process each of our operands recursively. If any have changed, make a
2591 fmt = GET_RTX_FORMAT (code);
2592 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2596 new = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2597 if (new != XEXP (x, i) && ! copied)
2599 rtx new_x = rtx_alloc (code);
2600 memcpy (new_x, x, RTX_SIZE (code));
2606 else if (*fmt == 'E')
2609 for (j = 0; j < XVECLEN (x, i); j++)
2611 new = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2612 if (new != XVECEXP (x, i, j) && ! copied_vec)
2614 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2618 rtx new_x = rtx_alloc (code);
2619 memcpy (new_x, x, RTX_SIZE (code));
2623 XVEC (x, i) = new_v;
2626 XVECEXP (x, i, j) = new;
2635 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2637 return eliminate_regs_1 (x, mem_mode, insn, false);
2640 /* Scan rtx X for modifications of elimination target registers. Update
2641 the table of eliminables to reflect the changed state. MEM_MODE is
2642 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2645 elimination_effects (rtx x, enum machine_mode mem_mode)
2647 enum rtx_code code = GET_CODE (x);
2648 struct elim_table *ep;
2672 /* First handle the case where we encounter a bare register that
2673 is eliminable. Replace it with a PLUS. */
2674 if (regno < FIRST_PSEUDO_REGISTER)
2676 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2678 if (ep->from_rtx == x && ep->can_eliminate)
2681 ep->ref_outside_mem = 1;
2686 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2687 && reg_equiv_constant[regno]
2688 && ! function_invariant_p (reg_equiv_constant[regno]))
2689 elimination_effects (reg_equiv_constant[regno], mem_mode);
2698 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2699 if (ep->to_rtx == XEXP (x, 0))
2701 int size = GET_MODE_SIZE (mem_mode);
2703 /* If more bytes than MEM_MODE are pushed, account for them. */
2704 #ifdef PUSH_ROUNDING
2705 if (ep->to_rtx == stack_pointer_rtx)
2706 size = PUSH_ROUNDING (size);
2708 if (code == PRE_DEC || code == POST_DEC)
2710 else if (code == PRE_INC || code == POST_INC)
2712 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2713 && GET_CODE (XEXP (x, 1)) == PLUS
2714 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2715 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2716 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2719 /* These two aren't unary operators. */
2720 if (code == POST_MODIFY || code == PRE_MODIFY)
2723 /* Fall through to generic unary operation case. */
2724 case STRICT_LOW_PART:
2726 case SIGN_EXTEND: case ZERO_EXTEND:
2727 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2728 case FLOAT: case FIX:
2729 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2737 elimination_effects (XEXP (x, 0), mem_mode);
2741 if (REG_P (SUBREG_REG (x))
2742 && (GET_MODE_SIZE (GET_MODE (x))
2743 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2744 && reg_equiv_memory_loc != 0
2745 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2748 elimination_effects (SUBREG_REG (x), mem_mode);
2752 /* If using a register that is the source of an eliminate we still
2753 think can be performed, note it cannot be performed since we don't
2754 know how this register is used. */
2755 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2756 if (ep->from_rtx == XEXP (x, 0))
2757 ep->can_eliminate = 0;
2759 elimination_effects (XEXP (x, 0), mem_mode);
2763 /* If clobbering a register that is the replacement register for an
2764 elimination we still think can be performed, note that it cannot
2765 be performed. Otherwise, we need not be concerned about it. */
2766 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2767 if (ep->to_rtx == XEXP (x, 0))
2768 ep->can_eliminate = 0;
2770 elimination_effects (XEXP (x, 0), mem_mode);
2774 /* Check for setting a register that we know about. */
2775 if (REG_P (SET_DEST (x)))
2777 /* See if this is setting the replacement register for an
2780 If DEST is the hard frame pointer, we do nothing because we
2781 assume that all assignments to the frame pointer are for
2782 non-local gotos and are being done at a time when they are valid
2783 and do not disturb anything else. Some machines want to
2784 eliminate a fake argument pointer (or even a fake frame pointer)
2785 with either the real frame or the stack pointer. Assignments to
2786 the hard frame pointer must not prevent this elimination. */
2788 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2790 if (ep->to_rtx == SET_DEST (x)
2791 && SET_DEST (x) != hard_frame_pointer_rtx)
2793 /* If it is being incremented, adjust the offset. Otherwise,
2794 this elimination can't be done. */
2795 rtx src = SET_SRC (x);
2797 if (GET_CODE (src) == PLUS
2798 && XEXP (src, 0) == SET_DEST (x)
2799 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2800 ep->offset -= INTVAL (XEXP (src, 1));
2802 ep->can_eliminate = 0;
2806 elimination_effects (SET_DEST (x), 0);
2807 elimination_effects (SET_SRC (x), 0);
2811 /* Our only special processing is to pass the mode of the MEM to our
2813 elimination_effects (XEXP (x, 0), GET_MODE (x));
2820 fmt = GET_RTX_FORMAT (code);
2821 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2824 elimination_effects (XEXP (x, i), mem_mode);
2825 else if (*fmt == 'E')
2826 for (j = 0; j < XVECLEN (x, i); j++)
2827 elimination_effects (XVECEXP (x, i, j), mem_mode);
2831 /* Descend through rtx X and verify that no references to eliminable registers
2832 remain. If any do remain, mark the involved register as not
2836 check_eliminable_occurrences (rtx x)
2845 code = GET_CODE (x);
2847 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2849 struct elim_table *ep;
2851 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2852 if (ep->from_rtx == x)
2853 ep->can_eliminate = 0;
2857 fmt = GET_RTX_FORMAT (code);
2858 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2861 check_eliminable_occurrences (XEXP (x, i));
2862 else if (*fmt == 'E')
2865 for (j = 0; j < XVECLEN (x, i); j++)
2866 check_eliminable_occurrences (XVECEXP (x, i, j));
2871 /* Scan INSN and eliminate all eliminable registers in it.
2873 If REPLACE is nonzero, do the replacement destructively. Also
2874 delete the insn as dead it if it is setting an eliminable register.
2876 If REPLACE is zero, do all our allocations in reload_obstack.
2878 If no eliminations were done and this insn doesn't require any elimination
2879 processing (these are not identical conditions: it might be updating sp,
2880 but not referencing fp; this needs to be seen during reload_as_needed so
2881 that the offset between fp and sp can be taken into consideration), zero
2882 is returned. Otherwise, 1 is returned. */
2885 eliminate_regs_in_insn (rtx insn, int replace)
2887 int icode = recog_memoized (insn);
2888 rtx old_body = PATTERN (insn);
2889 int insn_is_asm = asm_noperands (old_body) >= 0;
2890 rtx old_set = single_set (insn);
2894 rtx substed_operand[MAX_RECOG_OPERANDS];
2895 rtx orig_operand[MAX_RECOG_OPERANDS];
2896 struct elim_table *ep;
2897 rtx plus_src, plus_cst_src;
2899 if (! insn_is_asm && icode < 0)
2901 gcc_assert (GET_CODE (PATTERN (insn)) == USE
2902 || GET_CODE (PATTERN (insn)) == CLOBBER
2903 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2904 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2905 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
2909 if (old_set != 0 && REG_P (SET_DEST (old_set))
2910 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2912 /* Check for setting an eliminable register. */
2913 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2914 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2916 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2917 /* If this is setting the frame pointer register to the
2918 hardware frame pointer register and this is an elimination
2919 that will be done (tested above), this insn is really
2920 adjusting the frame pointer downward to compensate for
2921 the adjustment done before a nonlocal goto. */
2922 if (ep->from == FRAME_POINTER_REGNUM
2923 && ep->to == HARD_FRAME_POINTER_REGNUM)
2925 rtx base = SET_SRC (old_set);
2926 rtx base_insn = insn;
2927 HOST_WIDE_INT offset = 0;
2929 while (base != ep->to_rtx)
2931 rtx prev_insn, prev_set;
2933 if (GET_CODE (base) == PLUS
2934 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2936 offset += INTVAL (XEXP (base, 1));
2937 base = XEXP (base, 0);
2939 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2940 && (prev_set = single_set (prev_insn)) != 0
2941 && rtx_equal_p (SET_DEST (prev_set), base))
2943 base = SET_SRC (prev_set);
2944 base_insn = prev_insn;
2950 if (base == ep->to_rtx)
2953 = plus_constant (ep->to_rtx, offset - ep->offset);
2955 new_body = old_body;
2958 new_body = copy_insn (old_body);
2959 if (REG_NOTES (insn))
2960 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2962 PATTERN (insn) = new_body;
2963 old_set = single_set (insn);
2965 /* First see if this insn remains valid when we
2966 make the change. If not, keep the INSN_CODE
2967 the same and let reload fit it up. */
2968 validate_change (insn, &SET_SRC (old_set), src, 1);
2969 validate_change (insn, &SET_DEST (old_set),
2971 if (! apply_change_group ())
2973 SET_SRC (old_set) = src;
2974 SET_DEST (old_set) = ep->to_rtx;
2983 /* In this case this insn isn't serving a useful purpose. We
2984 will delete it in reload_as_needed once we know that this
2985 elimination is, in fact, being done.
2987 If REPLACE isn't set, we can't delete this insn, but needn't
2988 process it since it won't be used unless something changes. */
2991 delete_dead_insn (insn);
2999 /* We allow one special case which happens to work on all machines we
3000 currently support: a single set with the source or a REG_EQUAL
3001 note being a PLUS of an eliminable register and a constant. */
3002 plus_src = plus_cst_src = 0;
3003 if (old_set && REG_P (SET_DEST (old_set)))
3005 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3006 plus_src = SET_SRC (old_set);
3007 /* First see if the source is of the form (plus (reg) CST). */
3009 && REG_P (XEXP (plus_src, 0))
3010 && GET_CODE (XEXP (plus_src, 1)) == CONST_INT
3011 && REGNO (XEXP (plus_src, 0)) < FIRST_PSEUDO_REGISTER)
3012 plus_cst_src = plus_src;
3013 else if (REG_P (SET_SRC (old_set))
3016 /* Otherwise, see if we have a REG_EQUAL note of the form
3017 (plus (reg) CST). */
3019 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3021 if (REG_NOTE_KIND (links) == REG_EQUAL
3022 && GET_CODE (XEXP (links, 0)) == PLUS
3023 && REG_P (XEXP (XEXP (links, 0), 0))
3024 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT
3025 && REGNO (XEXP (XEXP (links, 0), 0)) < FIRST_PSEUDO_REGISTER)
3027 plus_cst_src = XEXP (links, 0);
3035 rtx reg = XEXP (plus_cst_src, 0);
3036 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3038 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3039 if (ep->from_rtx == reg && ep->can_eliminate)
3041 offset += ep->offset;
3046 /* We assume here that if we need a PARALLEL with
3047 CLOBBERs for this assignment, we can do with the
3048 MATCH_SCRATCHes that add_clobbers allocates.
3049 There's not much we can do if that doesn't work. */
3050 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3054 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3057 rtvec vec = rtvec_alloc (num_clobbers + 1);
3059 vec->elem[0] = PATTERN (insn);
3060 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3061 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3063 gcc_assert (INSN_CODE (insn) >= 0);
3065 /* If we have a nonzero offset, and the source is already
3066 a simple REG, the following transformation would
3067 increase the cost of the insn by replacing a simple REG
3068 with (plus (reg sp) CST). So try only when we already
3069 had a PLUS before. */
3072 new_body = old_body;
3075 new_body = copy_insn (old_body);
3076 if (REG_NOTES (insn))
3077 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3079 PATTERN (insn) = new_body;
3080 old_set = single_set (insn);
3082 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3083 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3089 /* This can't have an effect on elimination offsets, so skip right
3095 /* Determine the effects of this insn on elimination offsets. */
3096 elimination_effects (old_body, 0);
3098 /* Eliminate all eliminable registers occurring in operands that
3099 can be handled by reload. */
3100 extract_insn (insn);
3101 for (i = 0; i < recog_data.n_operands; i++)
3103 orig_operand[i] = recog_data.operand[i];
3104 substed_operand[i] = recog_data.operand[i];
3106 /* For an asm statement, every operand is eliminable. */
3107 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3109 bool is_set_src, in_plus;
3111 /* Check for setting a register that we know about. */
3112 if (recog_data.operand_type[i] != OP_IN
3113 && REG_P (orig_operand[i]))
3115 /* If we are assigning to a register that can be eliminated, it
3116 must be as part of a PARALLEL, since the code above handles
3117 single SETs. We must indicate that we can no longer
3118 eliminate this reg. */
3119 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3121 if (ep->from_rtx == orig_operand[i])
3122 ep->can_eliminate = 0;
3125 /* Companion to the above plus substitution, we can allow
3126 invariants as the source of a plain move. */
3128 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3132 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3133 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3137 = eliminate_regs_1 (recog_data.operand[i], 0,
3138 replace ? insn : NULL_RTX,
3139 is_set_src || in_plus);
3140 if (substed_operand[i] != orig_operand[i])
3142 /* Terminate the search in check_eliminable_occurrences at
3144 *recog_data.operand_loc[i] = 0;
3146 /* If an output operand changed from a REG to a MEM and INSN is an
3147 insn, write a CLOBBER insn. */
3148 if (recog_data.operand_type[i] != OP_IN
3149 && REG_P (orig_operand[i])
3150 && MEM_P (substed_operand[i])
3152 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3157 for (i = 0; i < recog_data.n_dups; i++)
3158 *recog_data.dup_loc[i]
3159 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3161 /* If any eliminable remain, they aren't eliminable anymore. */
3162 check_eliminable_occurrences (old_body);
3164 /* Substitute the operands; the new values are in the substed_operand
3166 for (i = 0; i < recog_data.n_operands; i++)
3167 *recog_data.operand_loc[i] = substed_operand[i];
3168 for (i = 0; i < recog_data.n_dups; i++)
3169 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3171 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3172 re-recognize the insn. We do this in case we had a simple addition
3173 but now can do this as a load-address. This saves an insn in this
3175 If re-recognition fails, the old insn code number will still be used,
3176 and some register operands may have changed into PLUS expressions.
3177 These will be handled by find_reloads by loading them into a register
3182 /* If we aren't replacing things permanently and we changed something,
3183 make another copy to ensure that all the RTL is new. Otherwise
3184 things can go wrong if find_reload swaps commutative operands
3185 and one is inside RTL that has been copied while the other is not. */
3186 new_body = old_body;
3189 new_body = copy_insn (old_body);
3190 if (REG_NOTES (insn))
3191 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3193 PATTERN (insn) = new_body;
3195 /* If we had a move insn but now we don't, rerecognize it. This will
3196 cause spurious re-recognition if the old move had a PARALLEL since
3197 the new one still will, but we can't call single_set without
3198 having put NEW_BODY into the insn and the re-recognition won't
3199 hurt in this rare case. */
3200 /* ??? Why this huge if statement - why don't we just rerecognize the
3204 && ((REG_P (SET_SRC (old_set))
3205 && (GET_CODE (new_body) != SET
3206 || !REG_P (SET_SRC (new_body))))
3207 /* If this was a load from or store to memory, compare
3208 the MEM in recog_data.operand to the one in the insn.
3209 If they are not equal, then rerecognize the insn. */
3211 && ((MEM_P (SET_SRC (old_set))
3212 && SET_SRC (old_set) != recog_data.operand[1])
3213 || (MEM_P (SET_DEST (old_set))
3214 && SET_DEST (old_set) != recog_data.operand[0])))
3215 /* If this was an add insn before, rerecognize. */
3216 || GET_CODE (SET_SRC (old_set)) == PLUS))
3218 int new_icode = recog (PATTERN (insn), insn, 0);
3220 INSN_CODE (insn) = icode;
3224 /* Restore the old body. If there were any changes to it, we made a copy
3225 of it while the changes were still in place, so we'll correctly return
3226 a modified insn below. */
3229 /* Restore the old body. */
3230 for (i = 0; i < recog_data.n_operands; i++)
3231 *recog_data.operand_loc[i] = orig_operand[i];
3232 for (i = 0; i < recog_data.n_dups; i++)
3233 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3236 /* Update all elimination pairs to reflect the status after the current
3237 insn. The changes we make were determined by the earlier call to
3238 elimination_effects.
3240 We also detect cases where register elimination cannot be done,
3241 namely, if a register would be both changed and referenced outside a MEM
3242 in the resulting insn since such an insn is often undefined and, even if
3243 not, we cannot know what meaning will be given to it. Note that it is
3244 valid to have a register used in an address in an insn that changes it
3245 (presumably with a pre- or post-increment or decrement).
3247 If anything changes, return nonzero. */
3249 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3251 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3252 ep->can_eliminate = 0;
3254 ep->ref_outside_mem = 0;
3256 if (ep->previous_offset != ep->offset)
3261 /* If we changed something, perform elimination in REG_NOTES. This is
3262 needed even when REPLACE is zero because a REG_DEAD note might refer
3263 to a register that we eliminate and could cause a different number
3264 of spill registers to be needed in the final reload pass than in
3266 if (val && REG_NOTES (insn) != 0)
3268 = eliminate_regs_1 (REG_NOTES (insn), 0, REG_NOTES (insn), true);
3273 /* Loop through all elimination pairs.
3274 Recalculate the number not at initial offset.
3276 Compute the maximum offset (minimum offset if the stack does not
3277 grow downward) for each elimination pair. */
3280 update_eliminable_offsets (void)
3282 struct elim_table *ep;
3284 num_not_at_initial_offset = 0;
3285 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3287 ep->previous_offset = ep->offset;
3288 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3289 num_not_at_initial_offset++;
3293 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3294 replacement we currently believe is valid, mark it as not eliminable if X
3295 modifies DEST in any way other than by adding a constant integer to it.
3297 If DEST is the frame pointer, we do nothing because we assume that
3298 all assignments to the hard frame pointer are nonlocal gotos and are being
3299 done at a time when they are valid and do not disturb anything else.
3300 Some machines want to eliminate a fake argument pointer with either the
3301 frame or stack pointer. Assignments to the hard frame pointer must not
3302 prevent this elimination.
3304 Called via note_stores from reload before starting its passes to scan
3305 the insns of the function. */
3308 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3312 /* A SUBREG of a hard register here is just changing its mode. We should
3313 not see a SUBREG of an eliminable hard register, but check just in
3315 if (GET_CODE (dest) == SUBREG)
3316 dest = SUBREG_REG (dest);
3318 if (dest == hard_frame_pointer_rtx)
3321 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3322 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3323 && (GET_CODE (x) != SET
3324 || GET_CODE (SET_SRC (x)) != PLUS
3325 || XEXP (SET_SRC (x), 0) != dest
3326 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3328 reg_eliminate[i].can_eliminate_previous
3329 = reg_eliminate[i].can_eliminate = 0;
3334 /* Verify that the initial elimination offsets did not change since the
3335 last call to set_initial_elim_offsets. This is used to catch cases
3336 where something illegal happened during reload_as_needed that could
3337 cause incorrect code to be generated if we did not check for it. */
3340 verify_initial_elim_offsets (void)
3344 if (!num_eliminable)
3347 #ifdef ELIMINABLE_REGS
3349 struct elim_table *ep;
3351 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3353 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3354 if (t != ep->initial_offset)
3359 INITIAL_FRAME_POINTER_OFFSET (t);
3360 if (t != reg_eliminate[0].initial_offset)
3367 /* Reset all offsets on eliminable registers to their initial values. */
3370 set_initial_elim_offsets (void)
3372 struct elim_table *ep = reg_eliminate;
3374 #ifdef ELIMINABLE_REGS
3375 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3377 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3378 ep->previous_offset = ep->offset = ep->initial_offset;
3381 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3382 ep->previous_offset = ep->offset = ep->initial_offset;
3385 num_not_at_initial_offset = 0;
3388 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3391 set_initial_eh_label_offset (rtx label)
3393 set_label_offsets (label, NULL_RTX, 1);
3396 /* Initialize the known label offsets.
3397 Set a known offset for each forced label to be at the initial offset
3398 of each elimination. We do this because we assume that all
3399 computed jumps occur from a location where each elimination is
3400 at its initial offset.
3401 For all other labels, show that we don't know the offsets. */
3404 set_initial_label_offsets (void)
3407 memset (offsets_known_at, 0, num_labels);
3409 for (x = forced_labels; x; x = XEXP (x, 1))
3411 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3413 for_each_eh_label (set_initial_eh_label_offset);
3416 /* Set all elimination offsets to the known values for the code label given
3420 set_offsets_for_label (rtx insn)
3423 int label_nr = CODE_LABEL_NUMBER (insn);
3424 struct elim_table *ep;
3426 num_not_at_initial_offset = 0;
3427 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3429 ep->offset = ep->previous_offset
3430 = offsets_at[label_nr - first_label_num][i];
3431 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3432 num_not_at_initial_offset++;
3436 /* See if anything that happened changes which eliminations are valid.
3437 For example, on the SPARC, whether or not the frame pointer can
3438 be eliminated can depend on what registers have been used. We need
3439 not check some conditions again (such as flag_omit_frame_pointer)
3440 since they can't have changed. */
3443 update_eliminables (HARD_REG_SET *pset)
3445 int previous_frame_pointer_needed = frame_pointer_needed;
3446 struct elim_table *ep;
3448 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3449 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3450 #ifdef ELIMINABLE_REGS
3451 || ! CAN_ELIMINATE (ep->from, ep->to)
3454 ep->can_eliminate = 0;
3456 /* Look for the case where we have discovered that we can't replace
3457 register A with register B and that means that we will now be
3458 trying to replace register A with register C. This means we can
3459 no longer replace register C with register B and we need to disable
3460 such an elimination, if it exists. This occurs often with A == ap,
3461 B == sp, and C == fp. */
3463 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3465 struct elim_table *op;
3468 if (! ep->can_eliminate && ep->can_eliminate_previous)
3470 /* Find the current elimination for ep->from, if there is a
3472 for (op = reg_eliminate;
3473 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3474 if (op->from == ep->from && op->can_eliminate)
3480 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3482 for (op = reg_eliminate;
3483 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3484 if (op->from == new_to && op->to == ep->to)
3485 op->can_eliminate = 0;
3489 /* See if any registers that we thought we could eliminate the previous
3490 time are no longer eliminable. If so, something has changed and we
3491 must spill the register. Also, recompute the number of eliminable
3492 registers and see if the frame pointer is needed; it is if there is
3493 no elimination of the frame pointer that we can perform. */
3495 frame_pointer_needed = 1;
3496 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3498 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3499 && ep->to != HARD_FRAME_POINTER_REGNUM)
3500 frame_pointer_needed = 0;
3502 if (! ep->can_eliminate && ep->can_eliminate_previous)
3504 ep->can_eliminate_previous = 0;
3505 SET_HARD_REG_BIT (*pset, ep->from);
3510 /* If we didn't need a frame pointer last time, but we do now, spill
3511 the hard frame pointer. */
3512 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3513 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3516 /* Initialize the table of registers to eliminate. */
3519 init_elim_table (void)
3521 struct elim_table *ep;
3522 #ifdef ELIMINABLE_REGS
3523 const struct elim_table_1 *ep1;
3527 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3529 /* Does this function require a frame pointer? */
3531 frame_pointer_needed = (! flag_omit_frame_pointer
3532 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3533 and restore sp for alloca. So we can't eliminate
3534 the frame pointer in that case. At some point,
3535 we should improve this by emitting the
3536 sp-adjusting insns for this case. */
3537 || (current_function_calls_alloca
3538 && EXIT_IGNORE_STACK)
3539 || current_function_accesses_prior_frames
3540 || FRAME_POINTER_REQUIRED);
3544 #ifdef ELIMINABLE_REGS
3545 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3546 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3548 ep->from = ep1->from;
3550 ep->can_eliminate = ep->can_eliminate_previous
3551 = (CAN_ELIMINATE (ep->from, ep->to)
3552 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3555 reg_eliminate[0].from = reg_eliminate_1[0].from;
3556 reg_eliminate[0].to = reg_eliminate_1[0].to;
3557 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3558 = ! frame_pointer_needed;
3561 /* Count the number of eliminable registers and build the FROM and TO
3562 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3563 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3564 We depend on this. */
3565 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3567 num_eliminable += ep->can_eliminate;
3568 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3569 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3573 /* Kick all pseudos out of hard register REGNO.
3575 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3576 because we found we can't eliminate some register. In the case, no pseudos
3577 are allowed to be in the register, even if they are only in a block that
3578 doesn't require spill registers, unlike the case when we are spilling this
3579 hard reg to produce another spill register.
3581 Return nonzero if any pseudos needed to be kicked out. */
3584 spill_hard_reg (unsigned int regno, int cant_eliminate)
3590 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3591 regs_ever_live[regno] = 1;
3594 /* Spill every pseudo reg that was allocated to this reg
3595 or to something that overlaps this reg. */
3597 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3598 if (reg_renumber[i] >= 0
3599 && (unsigned int) reg_renumber[i] <= regno
3600 && ((unsigned int) reg_renumber[i]
3601 + hard_regno_nregs[(unsigned int) reg_renumber[i]]
3602 [PSEUDO_REGNO_MODE (i)]
3604 SET_REGNO_REG_SET (&spilled_pseudos, i);
3607 /* After find_reload_regs has been run for all insn that need reloads,
3608 and/or spill_hard_regs was called, this function is used to actually
3609 spill pseudo registers and try to reallocate them. It also sets up the
3610 spill_regs array for use by choose_reload_regs. */
3613 finish_spills (int global)
3615 struct insn_chain *chain;
3616 int something_changed = 0;
3618 reg_set_iterator rsi;
3620 /* Build the spill_regs array for the function. */
3621 /* If there are some registers still to eliminate and one of the spill regs
3622 wasn't ever used before, additional stack space may have to be
3623 allocated to store this register. Thus, we may have changed the offset
3624 between the stack and frame pointers, so mark that something has changed.
3626 One might think that we need only set VAL to 1 if this is a call-used
3627 register. However, the set of registers that must be saved by the
3628 prologue is not identical to the call-used set. For example, the
3629 register used by the call insn for the return PC is a call-used register,
3630 but must be saved by the prologue. */
3633 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3634 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3636 spill_reg_order[i] = n_spills;
3637 spill_regs[n_spills++] = i;
3638 if (num_eliminable && ! regs_ever_live[i])
3639 something_changed = 1;
3640 regs_ever_live[i] = 1;
3643 spill_reg_order[i] = -1;
3645 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3647 /* Record the current hard register the pseudo is allocated to in
3648 pseudo_previous_regs so we avoid reallocating it to the same
3649 hard reg in a later pass. */
3650 gcc_assert (reg_renumber[i] >= 0);
3652 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3653 /* Mark it as no longer having a hard register home. */
3654 reg_renumber[i] = -1;
3655 /* We will need to scan everything again. */
3656 something_changed = 1;
3659 /* Retry global register allocation if possible. */
3662 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3663 /* For every insn that needs reloads, set the registers used as spill
3664 regs in pseudo_forbidden_regs for every pseudo live across the
3666 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3668 EXECUTE_IF_SET_IN_REG_SET
3669 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3671 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3672 chain->used_spill_regs);
3674 EXECUTE_IF_SET_IN_REG_SET
3675 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3677 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3678 chain->used_spill_regs);
3682 /* Retry allocating the spilled pseudos. For each reg, merge the
3683 various reg sets that indicate which hard regs can't be used,
3684 and call retry_global_alloc.
3685 We change spill_pseudos here to only contain pseudos that did not
3686 get a new hard register. */
3687 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3688 if (reg_old_renumber[i] != reg_renumber[i])
3690 HARD_REG_SET forbidden;
3691 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3692 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3693 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3694 retry_global_alloc (i, forbidden);
3695 if (reg_renumber[i] >= 0)
3696 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3700 /* Fix up the register information in the insn chain.
3701 This involves deleting those of the spilled pseudos which did not get
3702 a new hard register home from the live_{before,after} sets. */
3703 for (chain = reload_insn_chain; chain; chain = chain->next)
3705 HARD_REG_SET used_by_pseudos;
3706 HARD_REG_SET used_by_pseudos2;
3708 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3709 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3711 /* Mark any unallocated hard regs as available for spills. That
3712 makes inheritance work somewhat better. */
3713 if (chain->need_reload)
3715 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3716 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3717 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3719 /* Save the old value for the sanity test below. */
3720 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3722 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3723 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3724 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3725 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3727 /* Make sure we only enlarge the set. */
3728 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3734 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3735 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3737 int regno = reg_renumber[i];
3738 if (reg_old_renumber[i] == regno)
3741 alter_reg (i, reg_old_renumber[i]);
3742 reg_old_renumber[i] = regno;
3746 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3748 fprintf (dump_file, " Register %d now in %d.\n\n",
3749 i, reg_renumber[i]);
3753 return something_changed;
3756 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3759 scan_paradoxical_subregs (rtx x)
3763 enum rtx_code code = GET_CODE (x);
3773 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3781 if (REG_P (SUBREG_REG (x))
3782 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3783 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3784 = GET_MODE_SIZE (GET_MODE (x));
3791 fmt = GET_RTX_FORMAT (code);
3792 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3795 scan_paradoxical_subregs (XEXP (x, i));
3796 else if (fmt[i] == 'E')
3799 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3800 scan_paradoxical_subregs (XVECEXP (x, i, j));
3805 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
3806 examine all of the reload insns between PREV and NEXT exclusive, and
3807 annotate all that may trap. */
3810 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
3812 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
3813 unsigned int trap_count;
3819 if (may_trap_p (PATTERN (insn)))
3823 remove_note (insn, note);
3827 for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i))
3828 if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i)))
3832 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (note, 0), REG_NOTES (i));
3836 /* Reload pseudo-registers into hard regs around each insn as needed.
3837 Additional register load insns are output before the insn that needs it
3838 and perhaps store insns after insns that modify the reloaded pseudo reg.
3840 reg_last_reload_reg and reg_reloaded_contents keep track of
3841 which registers are already available in reload registers.
3842 We update these for the reloads that we perform,
3843 as the insns are scanned. */
3846 reload_as_needed (int live_known)
3848 struct insn_chain *chain;
3849 #if defined (AUTO_INC_DEC)
3854 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3855 memset (spill_reg_store, 0, sizeof spill_reg_store);
3856 reg_last_reload_reg = xcalloc (max_regno, sizeof (rtx));
3857 reg_has_output_reload = xmalloc (max_regno);
3858 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3859 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
3861 set_initial_elim_offsets ();
3863 for (chain = reload_insn_chain; chain; chain = chain->next)
3866 rtx insn = chain->insn;
3867 rtx old_next = NEXT_INSN (insn);
3869 /* If we pass a label, copy the offsets from the label information
3870 into the current offsets of each elimination. */
3872 set_offsets_for_label (insn);
3874 else if (INSN_P (insn))
3876 rtx oldpat = copy_rtx (PATTERN (insn));
3878 /* If this is a USE and CLOBBER of a MEM, ensure that any
3879 references to eliminable registers have been removed. */
3881 if ((GET_CODE (PATTERN (insn)) == USE
3882 || GET_CODE (PATTERN (insn)) == CLOBBER)
3883 && MEM_P (XEXP (PATTERN (insn), 0)))
3884 XEXP (XEXP (PATTERN (insn), 0), 0)
3885 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3886 GET_MODE (XEXP (PATTERN (insn), 0)),
3889 /* If we need to do register elimination processing, do so.
3890 This might delete the insn, in which case we are done. */
3891 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3893 eliminate_regs_in_insn (insn, 1);
3896 update_eliminable_offsets ();
3901 /* If need_elim is nonzero but need_reload is zero, one might think
3902 that we could simply set n_reloads to 0. However, find_reloads
3903 could have done some manipulation of the insn (such as swapping
3904 commutative operands), and these manipulations are lost during
3905 the first pass for every insn that needs register elimination.
3906 So the actions of find_reloads must be redone here. */
3908 if (! chain->need_elim && ! chain->need_reload
3909 && ! chain->need_operand_change)
3911 /* First find the pseudo regs that must be reloaded for this insn.
3912 This info is returned in the tables reload_... (see reload.h).
3913 Also modify the body of INSN by substituting RELOAD
3914 rtx's for those pseudo regs. */
3917 memset (reg_has_output_reload, 0, max_regno);
3918 CLEAR_HARD_REG_SET (reg_is_output_reload);
3920 find_reloads (insn, 1, spill_indirect_levels, live_known,
3926 rtx next = NEXT_INSN (insn);
3929 prev = PREV_INSN (insn);
3931 /* Now compute which reload regs to reload them into. Perhaps
3932 reusing reload regs from previous insns, or else output
3933 load insns to reload them. Maybe output store insns too.
3934 Record the choices of reload reg in reload_reg_rtx. */
3935 choose_reload_regs (chain);
3937 /* Merge any reloads that we didn't combine for fear of
3938 increasing the number of spill registers needed but now
3939 discover can be safely merged. */
3940 if (SMALL_REGISTER_CLASSES)
3941 merge_assigned_reloads (insn);
3943 /* Generate the insns to reload operands into or out of
3944 their reload regs. */
3945 emit_reload_insns (chain);
3947 /* Substitute the chosen reload regs from reload_reg_rtx
3948 into the insn's body (or perhaps into the bodies of other
3949 load and store insn that we just made for reloading
3950 and that we moved the structure into). */
3951 subst_reloads (insn);
3953 /* Adjust the exception region notes for loads and stores. */
3954 if (flag_non_call_exceptions && !CALL_P (insn))
3955 fixup_eh_region_note (insn, prev, next);
3957 /* If this was an ASM, make sure that all the reload insns
3958 we have generated are valid. If not, give an error
3960 if (asm_noperands (PATTERN (insn)) >= 0)
3961 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3962 if (p != insn && INSN_P (p)
3963 && GET_CODE (PATTERN (p)) != USE
3964 && (recog_memoized (p) < 0
3965 || (extract_insn (p), ! constrain_operands (1))))
3967 error_for_asm (insn,
3968 "%<asm%> operand requires "
3969 "impossible reload");
3974 if (num_eliminable && chain->need_elim)
3975 update_eliminable_offsets ();
3977 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3978 is no longer validly lying around to save a future reload.
3979 Note that this does not detect pseudos that were reloaded
3980 for this insn in order to be stored in
3981 (obeying register constraints). That is correct; such reload
3982 registers ARE still valid. */
3983 note_stores (oldpat, forget_old_reloads_1, NULL);
3985 /* There may have been CLOBBER insns placed after INSN. So scan
3986 between INSN and NEXT and use them to forget old reloads. */
3987 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3988 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
3989 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3992 /* Likewise for regs altered by auto-increment in this insn.
3993 REG_INC notes have been changed by reloading:
3994 find_reloads_address_1 records substitutions for them,
3995 which have been performed by subst_reloads above. */
3996 for (i = n_reloads - 1; i >= 0; i--)
3998 rtx in_reg = rld[i].in_reg;
4001 enum rtx_code code = GET_CODE (in_reg);
4002 /* PRE_INC / PRE_DEC will have the reload register ending up
4003 with the same value as the stack slot, but that doesn't
4004 hold true for POST_INC / POST_DEC. Either we have to
4005 convert the memory access to a true POST_INC / POST_DEC,
4006 or we can't use the reload register for inheritance. */
4007 if ((code == POST_INC || code == POST_DEC)
4008 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4009 REGNO (rld[i].reg_rtx))
4010 /* Make sure it is the inc/dec pseudo, and not
4011 some other (e.g. output operand) pseudo. */
4012 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4013 == REGNO (XEXP (in_reg, 0))))
4016 rtx reload_reg = rld[i].reg_rtx;
4017 enum machine_mode mode = GET_MODE (reload_reg);
4021 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4023 /* We really want to ignore REG_INC notes here, so
4024 use PATTERN (p) as argument to reg_set_p . */
4025 if (reg_set_p (reload_reg, PATTERN (p)))
4027 n = count_occurrences (PATTERN (p), reload_reg, 0);
4032 n = validate_replace_rtx (reload_reg,
4033 gen_rtx_fmt_e (code,
4038 /* We must also verify that the constraints
4039 are met after the replacement. */
4042 n = constrain_operands (1);
4046 /* If the constraints were not met, then
4047 undo the replacement. */
4050 validate_replace_rtx (gen_rtx_fmt_e (code,
4063 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4065 /* Mark this as having an output reload so that the
4066 REG_INC processing code below won't invalidate
4067 the reload for inheritance. */
4068 SET_HARD_REG_BIT (reg_is_output_reload,
4069 REGNO (reload_reg));
4070 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4073 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4076 else if ((code == PRE_INC || code == PRE_DEC)
4077 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4078 REGNO (rld[i].reg_rtx))
4079 /* Make sure it is the inc/dec pseudo, and not
4080 some other (e.g. output operand) pseudo. */
4081 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4082 == REGNO (XEXP (in_reg, 0))))
4084 SET_HARD_REG_BIT (reg_is_output_reload,
4085 REGNO (rld[i].reg_rtx));
4086 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4090 /* If a pseudo that got a hard register is auto-incremented,
4091 we must purge records of copying it into pseudos without
4093 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4094 if (REG_NOTE_KIND (x) == REG_INC)
4096 /* See if this pseudo reg was reloaded in this insn.
4097 If so, its last-reload info is still valid
4098 because it is based on this insn's reload. */
4099 for (i = 0; i < n_reloads; i++)
4100 if (rld[i].out == XEXP (x, 0))
4104 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4108 /* A reload reg's contents are unknown after a label. */
4110 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4112 /* Don't assume a reload reg is still good after a call insn
4113 if it is a call-used reg, or if it contains a value that will
4114 be partially clobbered by the call. */
4115 else if (CALL_P (insn))
4117 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4118 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4123 free (reg_last_reload_reg);
4124 free (reg_has_output_reload);
4127 /* Discard all record of any value reloaded from X,
4128 or reloaded in X from someplace else;
4129 unless X is an output reload reg of the current insn.
4131 X may be a hard reg (the reload reg)
4132 or it may be a pseudo reg that was reloaded from. */
4135 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4136 void *data ATTRIBUTE_UNUSED)
4141 /* note_stores does give us subregs of hard regs,
4142 subreg_regno_offset requires a hard reg. */
4143 while (GET_CODE (x) == SUBREG)
4145 /* We ignore the subreg offset when calculating the regno,
4146 because we are using the entire underlying hard register
4156 if (regno >= FIRST_PSEUDO_REGISTER)
4162 nr = hard_regno_nregs[regno][GET_MODE (x)];
4163 /* Storing into a spilled-reg invalidates its contents.
4164 This can happen if a block-local pseudo is allocated to that reg
4165 and it wasn't spilled because this block's total need is 0.
4166 Then some insn might have an optional reload and use this reg. */
4167 for (i = 0; i < nr; i++)
4168 /* But don't do this if the reg actually serves as an output
4169 reload reg in the current instruction. */
4171 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4173 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4174 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4175 spill_reg_store[regno + i] = 0;
4179 /* Since value of X has changed,
4180 forget any value previously copied from it. */
4183 /* But don't forget a copy if this is the output reload
4184 that establishes the copy's validity. */
4185 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4186 reg_last_reload_reg[regno + nr] = 0;
4189 /* The following HARD_REG_SETs indicate when each hard register is
4190 used for a reload of various parts of the current insn. */
4192 /* If reg is unavailable for all reloads. */
4193 static HARD_REG_SET reload_reg_unavailable;
4194 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4195 static HARD_REG_SET reload_reg_used;
4196 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4197 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4198 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4199 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4200 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4201 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4202 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4203 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4204 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4205 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4206 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4207 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4208 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4209 static HARD_REG_SET reload_reg_used_in_op_addr;
4210 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4211 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4212 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4213 static HARD_REG_SET reload_reg_used_in_insn;
4214 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4215 static HARD_REG_SET reload_reg_used_in_other_addr;
4217 /* If reg is in use as a reload reg for any sort of reload. */
4218 static HARD_REG_SET reload_reg_used_at_all;
4220 /* If reg is use as an inherited reload. We just mark the first register
4222 static HARD_REG_SET reload_reg_used_for_inherit;
4224 /* Records which hard regs are used in any way, either as explicit use or
4225 by being allocated to a pseudo during any point of the current insn. */
4226 static HARD_REG_SET reg_used_in_insn;
4228 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4229 TYPE. MODE is used to indicate how many consecutive regs are
4233 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4234 enum machine_mode mode)
4236 unsigned int nregs = hard_regno_nregs[regno][mode];
4239 for (i = regno; i < nregs + regno; i++)
4244 SET_HARD_REG_BIT (reload_reg_used, i);
4247 case RELOAD_FOR_INPUT_ADDRESS:
4248 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4251 case RELOAD_FOR_INPADDR_ADDRESS:
4252 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4255 case RELOAD_FOR_OUTPUT_ADDRESS:
4256 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4259 case RELOAD_FOR_OUTADDR_ADDRESS:
4260 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4263 case RELOAD_FOR_OPERAND_ADDRESS:
4264 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4267 case RELOAD_FOR_OPADDR_ADDR:
4268 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4271 case RELOAD_FOR_OTHER_ADDRESS:
4272 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4275 case RELOAD_FOR_INPUT:
4276 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4279 case RELOAD_FOR_OUTPUT:
4280 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4283 case RELOAD_FOR_INSN:
4284 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4288 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4292 /* Similarly, but show REGNO is no longer in use for a reload. */
4295 clear_reload_reg_in_use (unsigned int regno, int opnum,
4296 enum reload_type type, enum machine_mode mode)
4298 unsigned int nregs = hard_regno_nregs[regno][mode];
4299 unsigned int start_regno, end_regno, r;
4301 /* A complication is that for some reload types, inheritance might
4302 allow multiple reloads of the same types to share a reload register.
4303 We set check_opnum if we have to check only reloads with the same
4304 operand number, and check_any if we have to check all reloads. */
4305 int check_opnum = 0;
4307 HARD_REG_SET *used_in_set;
4312 used_in_set = &reload_reg_used;
4315 case RELOAD_FOR_INPUT_ADDRESS:
4316 used_in_set = &reload_reg_used_in_input_addr[opnum];
4319 case RELOAD_FOR_INPADDR_ADDRESS:
4321 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4324 case RELOAD_FOR_OUTPUT_ADDRESS:
4325 used_in_set = &reload_reg_used_in_output_addr[opnum];
4328 case RELOAD_FOR_OUTADDR_ADDRESS:
4330 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4333 case RELOAD_FOR_OPERAND_ADDRESS:
4334 used_in_set = &reload_reg_used_in_op_addr;
4337 case RELOAD_FOR_OPADDR_ADDR:
4339 used_in_set = &reload_reg_used_in_op_addr_reload;
4342 case RELOAD_FOR_OTHER_ADDRESS:
4343 used_in_set = &reload_reg_used_in_other_addr;
4347 case RELOAD_FOR_INPUT:
4348 used_in_set = &reload_reg_used_in_input[opnum];
4351 case RELOAD_FOR_OUTPUT:
4352 used_in_set = &reload_reg_used_in_output[opnum];
4355 case RELOAD_FOR_INSN:
4356 used_in_set = &reload_reg_used_in_insn;
4361 /* We resolve conflicts with remaining reloads of the same type by
4362 excluding the intervals of reload registers by them from the
4363 interval of freed reload registers. Since we only keep track of
4364 one set of interval bounds, we might have to exclude somewhat
4365 more than what would be necessary if we used a HARD_REG_SET here.
4366 But this should only happen very infrequently, so there should
4367 be no reason to worry about it. */
4369 start_regno = regno;
4370 end_regno = regno + nregs;
4371 if (check_opnum || check_any)
4373 for (i = n_reloads - 1; i >= 0; i--)
4375 if (rld[i].when_needed == type
4376 && (check_any || rld[i].opnum == opnum)
4379 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4380 unsigned int conflict_end
4382 + hard_regno_nregs[conflict_start][rld[i].mode]);
4384 /* If there is an overlap with the first to-be-freed register,
4385 adjust the interval start. */
4386 if (conflict_start <= start_regno && conflict_end > start_regno)
4387 start_regno = conflict_end;
4388 /* Otherwise, if there is a conflict with one of the other
4389 to-be-freed registers, adjust the interval end. */
4390 if (conflict_start > start_regno && conflict_start < end_regno)
4391 end_regno = conflict_start;
4396 for (r = start_regno; r < end_regno; r++)
4397 CLEAR_HARD_REG_BIT (*used_in_set, r);
4400 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4401 specified by OPNUM and TYPE. */
4404 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4408 /* In use for a RELOAD_OTHER means it's not available for anything. */
4409 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4410 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4416 /* In use for anything means we can't use it for RELOAD_OTHER. */
4417 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4418 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4419 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4420 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4423 for (i = 0; i < reload_n_operands; i++)
4424 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4425 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4426 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4427 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4428 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4429 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4434 case RELOAD_FOR_INPUT:
4435 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4436 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4439 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4442 /* If it is used for some other input, can't use it. */
4443 for (i = 0; i < reload_n_operands; i++)
4444 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4447 /* If it is used in a later operand's address, can't use it. */
4448 for (i = opnum + 1; i < reload_n_operands; i++)
4449 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4450 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4455 case RELOAD_FOR_INPUT_ADDRESS:
4456 /* Can't use a register if it is used for an input address for this
4457 operand or used as an input in an earlier one. */
4458 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4459 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4462 for (i = 0; i < opnum; i++)
4463 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4468 case RELOAD_FOR_INPADDR_ADDRESS:
4469 /* Can't use a register if it is used for an input address
4470 for this operand or used as an input in an earlier
4472 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4475 for (i = 0; i < opnum; i++)
4476 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4481 case RELOAD_FOR_OUTPUT_ADDRESS:
4482 /* Can't use a register if it is used for an output address for this
4483 operand or used as an output in this or a later operand. Note
4484 that multiple output operands are emitted in reverse order, so
4485 the conflicting ones are those with lower indices. */
4486 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4489 for (i = 0; i <= opnum; i++)
4490 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4495 case RELOAD_FOR_OUTADDR_ADDRESS:
4496 /* Can't use a register if it is used for an output address
4497 for this operand or used as an output in this or a
4498 later operand. Note that multiple output operands are
4499 emitted in reverse order, so the conflicting ones are
4500 those with lower indices. */
4501 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4504 for (i = 0; i <= opnum; i++)
4505 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4510 case RELOAD_FOR_OPERAND_ADDRESS:
4511 for (i = 0; i < reload_n_operands; i++)
4512 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4515 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4516 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4518 case RELOAD_FOR_OPADDR_ADDR:
4519 for (i = 0; i < reload_n_operands; i++)
4520 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4523 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4525 case RELOAD_FOR_OUTPUT:
4526 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4527 outputs, or an operand address for this or an earlier output.
4528 Note that multiple output operands are emitted in reverse order,
4529 so the conflicting ones are those with higher indices. */
4530 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4533 for (i = 0; i < reload_n_operands; i++)
4534 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4537 for (i = opnum; i < reload_n_operands; i++)
4538 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4539 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4544 case RELOAD_FOR_INSN:
4545 for (i = 0; i < reload_n_operands; i++)
4546 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4547 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4550 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4551 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4553 case RELOAD_FOR_OTHER_ADDRESS:
4554 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4561 /* Return 1 if the value in reload reg REGNO, as used by a reload
4562 needed for the part of the insn specified by OPNUM and TYPE,
4563 is still available in REGNO at the end of the insn.
4565 We can assume that the reload reg was already tested for availability
4566 at the time it is needed, and we should not check this again,
4567 in case the reg has already been marked in use. */
4570 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4577 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4578 its value must reach the end. */
4581 /* If this use is for part of the insn,
4582 its value reaches if no subsequent part uses the same register.
4583 Just like the above function, don't try to do this with lots
4586 case RELOAD_FOR_OTHER_ADDRESS:
4587 /* Here we check for everything else, since these don't conflict
4588 with anything else and everything comes later. */
4590 for (i = 0; i < reload_n_operands; i++)
4591 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4592 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4593 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4594 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4595 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4596 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4599 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4600 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4601 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4602 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4604 case RELOAD_FOR_INPUT_ADDRESS:
4605 case RELOAD_FOR_INPADDR_ADDRESS:
4606 /* Similar, except that we check only for this and subsequent inputs
4607 and the address of only subsequent inputs and we do not need
4608 to check for RELOAD_OTHER objects since they are known not to
4611 for (i = opnum; i < reload_n_operands; i++)
4612 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4615 for (i = opnum + 1; i < reload_n_operands; i++)
4616 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4617 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4620 for (i = 0; i < reload_n_operands; i++)
4621 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4622 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4623 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4626 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4629 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4630 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4631 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4633 case RELOAD_FOR_INPUT:
4634 /* Similar to input address, except we start at the next operand for
4635 both input and input address and we do not check for
4636 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4639 for (i = opnum + 1; i < reload_n_operands; i++)
4640 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4641 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4642 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4645 /* ... fall through ... */
4647 case RELOAD_FOR_OPERAND_ADDRESS:
4648 /* Check outputs and their addresses. */
4650 for (i = 0; i < reload_n_operands; i++)
4651 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4652 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4653 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4656 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4658 case RELOAD_FOR_OPADDR_ADDR:
4659 for (i = 0; i < reload_n_operands; i++)
4660 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4661 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4662 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4665 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4666 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4667 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4669 case RELOAD_FOR_INSN:
4670 /* These conflict with other outputs with RELOAD_OTHER. So
4671 we need only check for output addresses. */
4673 opnum = reload_n_operands;
4675 /* ... fall through ... */
4677 case RELOAD_FOR_OUTPUT:
4678 case RELOAD_FOR_OUTPUT_ADDRESS:
4679 case RELOAD_FOR_OUTADDR_ADDRESS:
4680 /* We already know these can't conflict with a later output. So the
4681 only thing to check are later output addresses.
4682 Note that multiple output operands are emitted in reverse order,
4683 so the conflicting ones are those with lower indices. */
4684 for (i = 0; i < opnum; i++)
4685 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4686 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4696 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4699 This function uses the same algorithm as reload_reg_free_p above. */
4702 reloads_conflict (int r1, int r2)
4704 enum reload_type r1_type = rld[r1].when_needed;
4705 enum reload_type r2_type = rld[r2].when_needed;
4706 int r1_opnum = rld[r1].opnum;
4707 int r2_opnum = rld[r2].opnum;
4709 /* RELOAD_OTHER conflicts with everything. */
4710 if (r2_type == RELOAD_OTHER)
4713 /* Otherwise, check conflicts differently for each type. */
4717 case RELOAD_FOR_INPUT:
4718 return (r2_type == RELOAD_FOR_INSN
4719 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4720 || r2_type == RELOAD_FOR_OPADDR_ADDR
4721 || r2_type == RELOAD_FOR_INPUT
4722 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4723 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4724 && r2_opnum > r1_opnum));
4726 case RELOAD_FOR_INPUT_ADDRESS:
4727 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4728 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4730 case RELOAD_FOR_INPADDR_ADDRESS:
4731 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4732 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4734 case RELOAD_FOR_OUTPUT_ADDRESS:
4735 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4736 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4738 case RELOAD_FOR_OUTADDR_ADDRESS:
4739 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4740 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4742 case RELOAD_FOR_OPERAND_ADDRESS:
4743 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4744 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4746 case RELOAD_FOR_OPADDR_ADDR:
4747 return (r2_type == RELOAD_FOR_INPUT
4748 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4750 case RELOAD_FOR_OUTPUT:
4751 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4752 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4753 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4754 && r2_opnum >= r1_opnum));
4756 case RELOAD_FOR_INSN:
4757 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4758 || r2_type == RELOAD_FOR_INSN
4759 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4761 case RELOAD_FOR_OTHER_ADDRESS:
4762 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4772 /* Indexed by reload number, 1 if incoming value
4773 inherited from previous insns. */
4774 static char reload_inherited[MAX_RELOADS];
4776 /* For an inherited reload, this is the insn the reload was inherited from,
4777 if we know it. Otherwise, this is 0. */
4778 static rtx reload_inheritance_insn[MAX_RELOADS];
4780 /* If nonzero, this is a place to get the value of the reload,
4781 rather than using reload_in. */
4782 static rtx reload_override_in[MAX_RELOADS];
4784 /* For each reload, the hard register number of the register used,
4785 or -1 if we did not need a register for this reload. */
4786 static int reload_spill_index[MAX_RELOADS];
4788 /* Subroutine of free_for_value_p, used to check a single register.
4789 START_REGNO is the starting regno of the full reload register
4790 (possibly comprising multiple hard registers) that we are considering. */
4793 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4794 enum reload_type type, rtx value, rtx out,
4795 int reloadnum, int ignore_address_reloads)
4798 /* Set if we see an input reload that must not share its reload register
4799 with any new earlyclobber, but might otherwise share the reload
4800 register with an output or input-output reload. */
4801 int check_earlyclobber = 0;
4805 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4808 if (out == const0_rtx)
4814 /* We use some pseudo 'time' value to check if the lifetimes of the
4815 new register use would overlap with the one of a previous reload
4816 that is not read-only or uses a different value.
4817 The 'time' used doesn't have to be linear in any shape or form, just
4819 Some reload types use different 'buckets' for each operand.
4820 So there are MAX_RECOG_OPERANDS different time values for each
4822 We compute TIME1 as the time when the register for the prospective
4823 new reload ceases to be live, and TIME2 for each existing
4824 reload as the time when that the reload register of that reload
4826 Where there is little to be gained by exact lifetime calculations,
4827 we just make conservative assumptions, i.e. a longer lifetime;
4828 this is done in the 'default:' cases. */
4831 case RELOAD_FOR_OTHER_ADDRESS:
4832 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4833 time1 = copy ? 0 : 1;
4836 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4838 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4839 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4840 respectively, to the time values for these, we get distinct time
4841 values. To get distinct time values for each operand, we have to
4842 multiply opnum by at least three. We round that up to four because
4843 multiply by four is often cheaper. */
4844 case RELOAD_FOR_INPADDR_ADDRESS:
4845 time1 = opnum * 4 + 2;
4847 case RELOAD_FOR_INPUT_ADDRESS:
4848 time1 = opnum * 4 + 3;
4850 case RELOAD_FOR_INPUT:
4851 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4852 executes (inclusive). */
4853 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4855 case RELOAD_FOR_OPADDR_ADDR:
4857 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4858 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4860 case RELOAD_FOR_OPERAND_ADDRESS:
4861 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4863 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4865 case RELOAD_FOR_OUTADDR_ADDRESS:
4866 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4868 case RELOAD_FOR_OUTPUT_ADDRESS:
4869 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4872 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4875 for (i = 0; i < n_reloads; i++)
4877 rtx reg = rld[i].reg_rtx;
4878 if (reg && REG_P (reg)
4879 && ((unsigned) regno - true_regnum (reg)
4880 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
4883 rtx other_input = rld[i].in;
4885 /* If the other reload loads the same input value, that
4886 will not cause a conflict only if it's loading it into
4887 the same register. */
4888 if (true_regnum (reg) != start_regno)
4889 other_input = NULL_RTX;
4890 if (! other_input || ! rtx_equal_p (other_input, value)
4891 || rld[i].out || out)
4894 switch (rld[i].when_needed)
4896 case RELOAD_FOR_OTHER_ADDRESS:
4899 case RELOAD_FOR_INPADDR_ADDRESS:
4900 /* find_reloads makes sure that a
4901 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4902 by at most one - the first -
4903 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4904 address reload is inherited, the address address reload
4905 goes away, so we can ignore this conflict. */
4906 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4907 && ignore_address_reloads
4908 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4909 Then the address address is still needed to store
4910 back the new address. */
4911 && ! rld[reloadnum].out)
4913 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4914 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4916 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4917 && ignore_address_reloads
4918 /* Unless we are reloading an auto_inc expression. */
4919 && ! rld[reloadnum].out)
4921 time2 = rld[i].opnum * 4 + 2;
4923 case RELOAD_FOR_INPUT_ADDRESS:
4924 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4925 && ignore_address_reloads
4926 && ! rld[reloadnum].out)
4928 time2 = rld[i].opnum * 4 + 3;
4930 case RELOAD_FOR_INPUT:
4931 time2 = rld[i].opnum * 4 + 4;
4932 check_earlyclobber = 1;
4934 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4935 == MAX_RECOG_OPERAND * 4 */
4936 case RELOAD_FOR_OPADDR_ADDR:
4937 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4938 && ignore_address_reloads
4939 && ! rld[reloadnum].out)
4941 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4943 case RELOAD_FOR_OPERAND_ADDRESS:
4944 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4945 check_earlyclobber = 1;
4947 case RELOAD_FOR_INSN:
4948 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4950 case RELOAD_FOR_OUTPUT:
4951 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4952 instruction is executed. */
4953 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4955 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4956 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4958 case RELOAD_FOR_OUTADDR_ADDRESS:
4959 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4960 && ignore_address_reloads
4961 && ! rld[reloadnum].out)
4963 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4965 case RELOAD_FOR_OUTPUT_ADDRESS:
4966 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4969 /* If there is no conflict in the input part, handle this
4970 like an output reload. */
4971 if (! rld[i].in || rtx_equal_p (other_input, value))
4973 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4974 /* Earlyclobbered outputs must conflict with inputs. */
4975 if (earlyclobber_operand_p (rld[i].out))
4976 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4981 /* RELOAD_OTHER might be live beyond instruction execution,
4982 but this is not obvious when we set time2 = 1. So check
4983 here if there might be a problem with the new reload
4984 clobbering the register used by the RELOAD_OTHER. */
4992 && (! rld[i].in || rld[i].out
4993 || ! rtx_equal_p (other_input, value)))
4994 || (out && rld[reloadnum].out_reg
4995 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5001 /* Earlyclobbered outputs must conflict with inputs. */
5002 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5008 /* Return 1 if the value in reload reg REGNO, as used by a reload
5009 needed for the part of the insn specified by OPNUM and TYPE,
5010 may be used to load VALUE into it.
5012 MODE is the mode in which the register is used, this is needed to
5013 determine how many hard regs to test.
5015 Other read-only reloads with the same value do not conflict
5016 unless OUT is nonzero and these other reloads have to live while
5017 output reloads live.
5018 If OUT is CONST0_RTX, this is a special case: it means that the
5019 test should not be for using register REGNO as reload register, but
5020 for copying from register REGNO into the reload register.
5022 RELOADNUM is the number of the reload we want to load this value for;
5023 a reload does not conflict with itself.
5025 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5026 reloads that load an address for the very reload we are considering.
5028 The caller has to make sure that there is no conflict with the return
5032 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5033 enum reload_type type, rtx value, rtx out, int reloadnum,
5034 int ignore_address_reloads)
5036 int nregs = hard_regno_nregs[regno][mode];
5038 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5039 value, out, reloadnum,
5040 ignore_address_reloads))
5045 /* Return nonzero if the rtx X is invariant over the current function. */
5046 /* ??? Actually, the places where we use this expect exactly what is
5047 tested here, and not everything that is function invariant. In
5048 particular, the frame pointer and arg pointer are special cased;
5049 pic_offset_table_rtx is not, and we must not spill these things to
5053 function_invariant_p (rtx x)
5057 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5059 if (GET_CODE (x) == PLUS
5060 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5061 && CONSTANT_P (XEXP (x, 1)))
5066 /* Determine whether the reload reg X overlaps any rtx'es used for
5067 overriding inheritance. Return nonzero if so. */
5070 conflicts_with_override (rtx x)
5073 for (i = 0; i < n_reloads; i++)
5074 if (reload_override_in[i]
5075 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5080 /* Give an error message saying we failed to find a reload for INSN,
5081 and clear out reload R. */
5083 failed_reload (rtx insn, int r)
5085 if (asm_noperands (PATTERN (insn)) < 0)
5086 /* It's the compiler's fault. */
5087 fatal_insn ("could not find a spill register", insn);
5089 /* It's the user's fault; the operand's mode and constraint
5090 don't match. Disable this reload so we don't crash in final. */
5091 error_for_asm (insn,
5092 "%<asm%> operand constraint incompatible with operand size");
5096 rld[r].optional = 1;
5097 rld[r].secondary_p = 1;
5100 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5101 for reload R. If it's valid, get an rtx for it. Return nonzero if
5104 set_reload_reg (int i, int r)
5107 rtx reg = spill_reg_rtx[i];
5109 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5110 spill_reg_rtx[i] = reg
5111 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5113 regno = true_regnum (reg);
5115 /* Detect when the reload reg can't hold the reload mode.
5116 This used to be one `if', but Sequent compiler can't handle that. */
5117 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5119 enum machine_mode test_mode = VOIDmode;
5121 test_mode = GET_MODE (rld[r].in);
5122 /* If rld[r].in has VOIDmode, it means we will load it
5123 in whatever mode the reload reg has: to wit, rld[r].mode.
5124 We have already tested that for validity. */
5125 /* Aside from that, we need to test that the expressions
5126 to reload from or into have modes which are valid for this
5127 reload register. Otherwise the reload insns would be invalid. */
5128 if (! (rld[r].in != 0 && test_mode != VOIDmode
5129 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5130 if (! (rld[r].out != 0
5131 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5133 /* The reg is OK. */
5136 /* Mark as in use for this insn the reload regs we use
5138 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5139 rld[r].when_needed, rld[r].mode);
5141 rld[r].reg_rtx = reg;
5142 reload_spill_index[r] = spill_regs[i];
5149 /* Find a spill register to use as a reload register for reload R.
5150 LAST_RELOAD is nonzero if this is the last reload for the insn being
5153 Set rld[R].reg_rtx to the register allocated.
5155 We return 1 if successful, or 0 if we couldn't find a spill reg and
5156 we didn't change anything. */
5159 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5164 /* If we put this reload ahead, thinking it is a group,
5165 then insist on finding a group. Otherwise we can grab a
5166 reg that some other reload needs.
5167 (That can happen when we have a 68000 DATA_OR_FP_REG
5168 which is a group of data regs or one fp reg.)
5169 We need not be so restrictive if there are no more reloads
5172 ??? Really it would be nicer to have smarter handling
5173 for that kind of reg class, where a problem like this is normal.
5174 Perhaps those classes should be avoided for reloading
5175 by use of more alternatives. */
5177 int force_group = rld[r].nregs > 1 && ! last_reload;
5179 /* If we want a single register and haven't yet found one,
5180 take any reg in the right class and not in use.
5181 If we want a consecutive group, here is where we look for it.
5183 We use two passes so we can first look for reload regs to
5184 reuse, which are already in use for other reloads in this insn,
5185 and only then use additional registers.
5186 I think that maximizing reuse is needed to make sure we don't
5187 run out of reload regs. Suppose we have three reloads, and
5188 reloads A and B can share regs. These need two regs.
5189 Suppose A and B are given different regs.
5190 That leaves none for C. */
5191 for (pass = 0; pass < 2; pass++)
5193 /* I is the index in spill_regs.
5194 We advance it round-robin between insns to use all spill regs
5195 equally, so that inherited reloads have a chance
5196 of leapfrogging each other. */
5200 for (count = 0; count < n_spills; count++)
5202 int class = (int) rld[r].class;
5208 regnum = spill_regs[i];
5210 if ((reload_reg_free_p (regnum, rld[r].opnum,
5213 /* We check reload_reg_used to make sure we
5214 don't clobber the return register. */
5215 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5216 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5217 rld[r].when_needed, rld[r].in,
5219 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5220 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5221 /* Look first for regs to share, then for unshared. But
5222 don't share regs used for inherited reloads; they are
5223 the ones we want to preserve. */
5225 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5227 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5230 int nr = hard_regno_nregs[regnum][rld[r].mode];
5231 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5232 (on 68000) got us two FP regs. If NR is 1,
5233 we would reject both of them. */
5236 /* If we need only one reg, we have already won. */
5239 /* But reject a single reg if we demand a group. */
5244 /* Otherwise check that as many consecutive regs as we need
5245 are available here. */
5248 int regno = regnum + nr - 1;
5249 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5250 && spill_reg_order[regno] >= 0
5251 && reload_reg_free_p (regno, rld[r].opnum,
5252 rld[r].when_needed)))
5261 /* If we found something on pass 1, omit pass 2. */
5262 if (count < n_spills)
5266 /* We should have found a spill register by now. */
5267 if (count >= n_spills)
5270 /* I is the index in SPILL_REG_RTX of the reload register we are to
5271 allocate. Get an rtx for it and find its register number. */
5273 return set_reload_reg (i, r);
5276 /* Initialize all the tables needed to allocate reload registers.
5277 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5278 is the array we use to restore the reg_rtx field for every reload. */
5281 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5285 for (i = 0; i < n_reloads; i++)
5286 rld[i].reg_rtx = save_reload_reg_rtx[i];
5288 memset (reload_inherited, 0, MAX_RELOADS);
5289 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5290 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5292 CLEAR_HARD_REG_SET (reload_reg_used);
5293 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5294 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5295 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5296 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5297 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5299 CLEAR_HARD_REG_SET (reg_used_in_insn);
5302 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5303 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5304 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5305 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5306 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5307 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5310 for (i = 0; i < reload_n_operands; i++)
5312 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5313 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5314 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5315 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5316 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5317 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5320 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5322 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5324 for (i = 0; i < n_reloads; i++)
5325 /* If we have already decided to use a certain register,
5326 don't use it in another way. */
5328 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5329 rld[i].when_needed, rld[i].mode);
5332 /* Assign hard reg targets for the pseudo-registers we must reload
5333 into hard regs for this insn.
5334 Also output the instructions to copy them in and out of the hard regs.
5336 For machines with register classes, we are responsible for
5337 finding a reload reg in the proper class. */
5340 choose_reload_regs (struct insn_chain *chain)
5342 rtx insn = chain->insn;
5344 unsigned int max_group_size = 1;
5345 enum reg_class group_class = NO_REGS;
5346 int pass, win, inheritance;
5348 rtx save_reload_reg_rtx[MAX_RELOADS];
5350 /* In order to be certain of getting the registers we need,
5351 we must sort the reloads into order of increasing register class.
5352 Then our grabbing of reload registers will parallel the process
5353 that provided the reload registers.
5355 Also note whether any of the reloads wants a consecutive group of regs.
5356 If so, record the maximum size of the group desired and what
5357 register class contains all the groups needed by this insn. */
5359 for (j = 0; j < n_reloads; j++)
5361 reload_order[j] = j;
5362 reload_spill_index[j] = -1;
5364 if (rld[j].nregs > 1)
5366 max_group_size = MAX (rld[j].nregs, max_group_size);
5368 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5371 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5375 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5377 /* If -O, try first with inheritance, then turning it off.
5378 If not -O, don't do inheritance.
5379 Using inheritance when not optimizing leads to paradoxes
5380 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5381 because one side of the comparison might be inherited. */
5383 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5385 choose_reload_regs_init (chain, save_reload_reg_rtx);
5387 /* Process the reloads in order of preference just found.
5388 Beyond this point, subregs can be found in reload_reg_rtx.
5390 This used to look for an existing reloaded home for all of the
5391 reloads, and only then perform any new reloads. But that could lose
5392 if the reloads were done out of reg-class order because a later
5393 reload with a looser constraint might have an old home in a register
5394 needed by an earlier reload with a tighter constraint.
5396 To solve this, we make two passes over the reloads, in the order
5397 described above. In the first pass we try to inherit a reload
5398 from a previous insn. If there is a later reload that needs a
5399 class that is a proper subset of the class being processed, we must
5400 also allocate a spill register during the first pass.
5402 Then make a second pass over the reloads to allocate any reloads
5403 that haven't been given registers yet. */
5405 for (j = 0; j < n_reloads; j++)
5407 int r = reload_order[j];
5408 rtx search_equiv = NULL_RTX;
5410 /* Ignore reloads that got marked inoperative. */
5411 if (rld[r].out == 0 && rld[r].in == 0
5412 && ! rld[r].secondary_p)
5415 /* If find_reloads chose to use reload_in or reload_out as a reload
5416 register, we don't need to chose one. Otherwise, try even if it
5417 found one since we might save an insn if we find the value lying
5419 Try also when reload_in is a pseudo without a hard reg. */
5420 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5421 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5422 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5423 && !MEM_P (rld[r].in)
5424 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5427 #if 0 /* No longer needed for correct operation.
5428 It might give better code, or might not; worth an experiment? */
5429 /* If this is an optional reload, we can't inherit from earlier insns
5430 until we are sure that any non-optional reloads have been allocated.
5431 The following code takes advantage of the fact that optional reloads
5432 are at the end of reload_order. */
5433 if (rld[r].optional != 0)
5434 for (i = 0; i < j; i++)
5435 if ((rld[reload_order[i]].out != 0
5436 || rld[reload_order[i]].in != 0
5437 || rld[reload_order[i]].secondary_p)
5438 && ! rld[reload_order[i]].optional
5439 && rld[reload_order[i]].reg_rtx == 0)
5440 allocate_reload_reg (chain, reload_order[i], 0);
5443 /* First see if this pseudo is already available as reloaded
5444 for a previous insn. We cannot try to inherit for reloads
5445 that are smaller than the maximum number of registers needed
5446 for groups unless the register we would allocate cannot be used
5449 We could check here to see if this is a secondary reload for
5450 an object that is already in a register of the desired class.
5451 This would avoid the need for the secondary reload register.
5452 But this is complex because we can't easily determine what
5453 objects might want to be loaded via this reload. So let a
5454 register be allocated here. In `emit_reload_insns' we suppress
5455 one of the loads in the case described above. */
5461 enum machine_mode mode = VOIDmode;
5465 else if (REG_P (rld[r].in))
5467 regno = REGNO (rld[r].in);
5468 mode = GET_MODE (rld[r].in);
5470 else if (REG_P (rld[r].in_reg))
5472 regno = REGNO (rld[r].in_reg);
5473 mode = GET_MODE (rld[r].in_reg);
5475 else if (GET_CODE (rld[r].in_reg) == SUBREG
5476 && REG_P (SUBREG_REG (rld[r].in_reg)))
5478 byte = SUBREG_BYTE (rld[r].in_reg);
5479 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5480 if (regno < FIRST_PSEUDO_REGISTER)
5481 regno = subreg_regno (rld[r].in_reg);
5482 mode = GET_MODE (rld[r].in_reg);
5485 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5486 || GET_CODE (rld[r].in_reg) == PRE_DEC
5487 || GET_CODE (rld[r].in_reg) == POST_INC
5488 || GET_CODE (rld[r].in_reg) == POST_DEC)
5489 && REG_P (XEXP (rld[r].in_reg, 0)))
5491 regno = REGNO (XEXP (rld[r].in_reg, 0));
5492 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5493 rld[r].out = rld[r].in;
5497 /* This won't work, since REGNO can be a pseudo reg number.
5498 Also, it takes much more hair to keep track of all the things
5499 that can invalidate an inherited reload of part of a pseudoreg. */
5500 else if (GET_CODE (rld[r].in) == SUBREG
5501 && REG_P (SUBREG_REG (rld[r].in)))
5502 regno = subreg_regno (rld[r].in);
5505 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5507 enum reg_class class = rld[r].class, last_class;
5508 rtx last_reg = reg_last_reload_reg[regno];
5509 enum machine_mode need_mode;
5511 i = REGNO (last_reg);
5512 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5513 last_class = REGNO_REG_CLASS (i);
5519 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
5520 + byte * BITS_PER_UNIT,
5521 GET_MODE_CLASS (mode));
5523 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5524 >= GET_MODE_SIZE (need_mode))
5525 #ifdef CANNOT_CHANGE_MODE_CLASS
5526 /* Verify that the register in "i" can be obtained
5528 && !REG_CANNOT_CHANGE_MODE_P (REGNO (last_reg),
5529 GET_MODE (last_reg),
5532 && reg_reloaded_contents[i] == regno
5533 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5534 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5535 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5536 /* Even if we can't use this register as a reload
5537 register, we might use it for reload_override_in,
5538 if copying it to the desired class is cheap
5540 || ((REGISTER_MOVE_COST (mode, last_class, class)
5541 < MEMORY_MOVE_COST (mode, class, 1))
5542 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5543 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5547 #ifdef SECONDARY_MEMORY_NEEDED
5548 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5553 && (rld[r].nregs == max_group_size
5554 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5556 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5557 rld[r].when_needed, rld[r].in,
5560 /* If a group is needed, verify that all the subsequent
5561 registers still have their values intact. */
5562 int nr = hard_regno_nregs[i][rld[r].mode];
5565 for (k = 1; k < nr; k++)
5566 if (reg_reloaded_contents[i + k] != regno
5567 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5575 last_reg = (GET_MODE (last_reg) == mode
5576 ? last_reg : gen_rtx_REG (mode, i));
5579 for (k = 0; k < nr; k++)
5580 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5583 /* We found a register that contains the
5584 value we need. If this register is the
5585 same as an `earlyclobber' operand of the
5586 current insn, just mark it as a place to
5587 reload from since we can't use it as the
5588 reload register itself. */
5590 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5591 if (reg_overlap_mentioned_for_reload_p
5592 (reg_last_reload_reg[regno],
5593 reload_earlyclobbers[i1]))
5596 if (i1 != n_earlyclobbers
5597 || ! (free_for_value_p (i, rld[r].mode,
5599 rld[r].when_needed, rld[r].in,
5601 /* Don't use it if we'd clobber a pseudo reg. */
5602 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5604 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5605 /* Don't clobber the frame pointer. */
5606 || (i == HARD_FRAME_POINTER_REGNUM
5607 && frame_pointer_needed
5609 /* Don't really use the inherited spill reg
5610 if we need it wider than we've got it. */
5611 || (GET_MODE_SIZE (rld[r].mode)
5612 > GET_MODE_SIZE (mode))
5615 /* If find_reloads chose reload_out as reload
5616 register, stay with it - that leaves the
5617 inherited register for subsequent reloads. */
5618 || (rld[r].out && rld[r].reg_rtx
5619 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5621 if (! rld[r].optional)
5623 reload_override_in[r] = last_reg;
5624 reload_inheritance_insn[r]
5625 = reg_reloaded_insn[i];
5631 /* We can use this as a reload reg. */
5632 /* Mark the register as in use for this part of
5634 mark_reload_reg_in_use (i,
5638 rld[r].reg_rtx = last_reg;
5639 reload_inherited[r] = 1;
5640 reload_inheritance_insn[r]
5641 = reg_reloaded_insn[i];
5642 reload_spill_index[r] = i;
5643 for (k = 0; k < nr; k++)
5644 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5652 /* Here's another way to see if the value is already lying around. */
5655 && ! reload_inherited[r]
5657 && (CONSTANT_P (rld[r].in)
5658 || GET_CODE (rld[r].in) == PLUS
5659 || REG_P (rld[r].in)
5660 || MEM_P (rld[r].in))
5661 && (rld[r].nregs == max_group_size
5662 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5663 search_equiv = rld[r].in;
5664 /* If this is an output reload from a simple move insn, look
5665 if an equivalence for the input is available. */
5666 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5668 rtx set = single_set (insn);
5671 && rtx_equal_p (rld[r].out, SET_DEST (set))
5672 && CONSTANT_P (SET_SRC (set)))
5673 search_equiv = SET_SRC (set);
5679 = find_equiv_reg (search_equiv, insn, rld[r].class,
5680 -1, NULL, 0, rld[r].mode);
5686 regno = REGNO (equiv);
5689 /* This must be a SUBREG of a hard register.
5690 Make a new REG since this might be used in an
5691 address and not all machines support SUBREGs
5693 gcc_assert (GET_CODE (equiv) == SUBREG);
5694 regno = subreg_regno (equiv);
5695 equiv = gen_rtx_REG (rld[r].mode, regno);
5696 /* If we choose EQUIV as the reload register, but the
5697 loop below decides to cancel the inheritance, we'll
5698 end up reloading EQUIV in rld[r].mode, not the mode
5699 it had originally. That isn't safe when EQUIV isn't
5700 available as a spill register since its value might
5701 still be live at this point. */
5702 for (i = regno; i < regno + (int) rld[r].nregs; i++)
5703 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
5708 /* If we found a spill reg, reject it unless it is free
5709 and of the desired class. */
5713 int bad_for_class = 0;
5714 int max_regno = regno + rld[r].nregs;
5716 for (i = regno; i < max_regno; i++)
5718 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5720 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5725 && ! free_for_value_p (regno, rld[r].mode,
5726 rld[r].opnum, rld[r].when_needed,
5727 rld[r].in, rld[r].out, r, 1))
5732 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5735 /* We found a register that contains the value we need.
5736 If this register is the same as an `earlyclobber' operand
5737 of the current insn, just mark it as a place to reload from
5738 since we can't use it as the reload register itself. */
5741 for (i = 0; i < n_earlyclobbers; i++)
5742 if (reg_overlap_mentioned_for_reload_p (equiv,
5743 reload_earlyclobbers[i]))
5745 if (! rld[r].optional)
5746 reload_override_in[r] = equiv;
5751 /* If the equiv register we have found is explicitly clobbered
5752 in the current insn, it depends on the reload type if we
5753 can use it, use it for reload_override_in, or not at all.
5754 In particular, we then can't use EQUIV for a
5755 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5759 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5760 switch (rld[r].when_needed)
5762 case RELOAD_FOR_OTHER_ADDRESS:
5763 case RELOAD_FOR_INPADDR_ADDRESS:
5764 case RELOAD_FOR_INPUT_ADDRESS:
5765 case RELOAD_FOR_OPADDR_ADDR:
5768 case RELOAD_FOR_INPUT:
5769 case RELOAD_FOR_OPERAND_ADDRESS:
5770 if (! rld[r].optional)
5771 reload_override_in[r] = equiv;
5777 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5778 switch (rld[r].when_needed)
5780 case RELOAD_FOR_OTHER_ADDRESS:
5781 case RELOAD_FOR_INPADDR_ADDRESS:
5782 case RELOAD_FOR_INPUT_ADDRESS:
5783 case RELOAD_FOR_OPADDR_ADDR:
5784 case RELOAD_FOR_OPERAND_ADDRESS:
5785 case RELOAD_FOR_INPUT:
5788 if (! rld[r].optional)
5789 reload_override_in[r] = equiv;
5797 /* If we found an equivalent reg, say no code need be generated
5798 to load it, and use it as our reload reg. */
5800 && (regno != HARD_FRAME_POINTER_REGNUM
5801 || !frame_pointer_needed))
5803 int nr = hard_regno_nregs[regno][rld[r].mode];
5805 rld[r].reg_rtx = equiv;
5806 reload_inherited[r] = 1;
5808 /* If reg_reloaded_valid is not set for this register,
5809 there might be a stale spill_reg_store lying around.
5810 We must clear it, since otherwise emit_reload_insns
5811 might delete the store. */
5812 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5813 spill_reg_store[regno] = NULL_RTX;
5814 /* If any of the hard registers in EQUIV are spill
5815 registers, mark them as in use for this insn. */
5816 for (k = 0; k < nr; k++)
5818 i = spill_reg_order[regno + k];
5821 mark_reload_reg_in_use (regno, rld[r].opnum,
5824 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5831 /* If we found a register to use already, or if this is an optional
5832 reload, we are done. */
5833 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5837 /* No longer needed for correct operation. Might or might
5838 not give better code on the average. Want to experiment? */
5840 /* See if there is a later reload that has a class different from our
5841 class that intersects our class or that requires less register
5842 than our reload. If so, we must allocate a register to this
5843 reload now, since that reload might inherit a previous reload
5844 and take the only available register in our class. Don't do this
5845 for optional reloads since they will force all previous reloads
5846 to be allocated. Also don't do this for reloads that have been
5849 for (i = j + 1; i < n_reloads; i++)
5851 int s = reload_order[i];
5853 if ((rld[s].in == 0 && rld[s].out == 0
5854 && ! rld[s].secondary_p)
5858 if ((rld[s].class != rld[r].class
5859 && reg_classes_intersect_p (rld[r].class,
5861 || rld[s].nregs < rld[r].nregs)
5868 allocate_reload_reg (chain, r, j == n_reloads - 1);
5872 /* Now allocate reload registers for anything non-optional that
5873 didn't get one yet. */
5874 for (j = 0; j < n_reloads; j++)
5876 int r = reload_order[j];
5878 /* Ignore reloads that got marked inoperative. */
5879 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5882 /* Skip reloads that already have a register allocated or are
5884 if (rld[r].reg_rtx != 0 || rld[r].optional)
5887 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5891 /* If that loop got all the way, we have won. */
5898 /* Loop around and try without any inheritance. */
5903 /* First undo everything done by the failed attempt
5904 to allocate with inheritance. */
5905 choose_reload_regs_init (chain, save_reload_reg_rtx);
5907 /* Some sanity tests to verify that the reloads found in the first
5908 pass are identical to the ones we have now. */
5909 gcc_assert (chain->n_reloads == n_reloads);
5911 for (i = 0; i < n_reloads; i++)
5913 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5915 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
5916 for (j = 0; j < n_spills; j++)
5917 if (spill_regs[j] == chain->rld[i].regno)
5918 if (! set_reload_reg (j, i))
5919 failed_reload (chain->insn, i);
5923 /* If we thought we could inherit a reload, because it seemed that
5924 nothing else wanted the same reload register earlier in the insn,
5925 verify that assumption, now that all reloads have been assigned.
5926 Likewise for reloads where reload_override_in has been set. */
5928 /* If doing expensive optimizations, do one preliminary pass that doesn't
5929 cancel any inheritance, but removes reloads that have been needed only
5930 for reloads that we know can be inherited. */
5931 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5933 for (j = 0; j < n_reloads; j++)
5935 int r = reload_order[j];
5937 if (reload_inherited[r] && rld[r].reg_rtx)
5938 check_reg = rld[r].reg_rtx;
5939 else if (reload_override_in[r]
5940 && (REG_P (reload_override_in[r])
5941 || GET_CODE (reload_override_in[r]) == SUBREG))
5942 check_reg = reload_override_in[r];
5945 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5946 rld[r].opnum, rld[r].when_needed, rld[r].in,
5947 (reload_inherited[r]
5948 ? rld[r].out : const0_rtx),
5953 reload_inherited[r] = 0;
5954 reload_override_in[r] = 0;
5956 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5957 reload_override_in, then we do not need its related
5958 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5959 likewise for other reload types.
5960 We handle this by removing a reload when its only replacement
5961 is mentioned in reload_in of the reload we are going to inherit.
5962 A special case are auto_inc expressions; even if the input is
5963 inherited, we still need the address for the output. We can
5964 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5965 If we succeeded removing some reload and we are doing a preliminary
5966 pass just to remove such reloads, make another pass, since the
5967 removal of one reload might allow us to inherit another one. */
5969 && rld[r].out != rld[r].in
5970 && remove_address_replacements (rld[r].in) && pass)
5975 /* Now that reload_override_in is known valid,
5976 actually override reload_in. */
5977 for (j = 0; j < n_reloads; j++)
5978 if (reload_override_in[j])
5979 rld[j].in = reload_override_in[j];
5981 /* If this reload won't be done because it has been canceled or is
5982 optional and not inherited, clear reload_reg_rtx so other
5983 routines (such as subst_reloads) don't get confused. */
5984 for (j = 0; j < n_reloads; j++)
5985 if (rld[j].reg_rtx != 0
5986 && ((rld[j].optional && ! reload_inherited[j])
5987 || (rld[j].in == 0 && rld[j].out == 0
5988 && ! rld[j].secondary_p)))
5990 int regno = true_regnum (rld[j].reg_rtx);
5992 if (spill_reg_order[regno] >= 0)
5993 clear_reload_reg_in_use (regno, rld[j].opnum,
5994 rld[j].when_needed, rld[j].mode);
5996 reload_spill_index[j] = -1;
5999 /* Record which pseudos and which spill regs have output reloads. */
6000 for (j = 0; j < n_reloads; j++)
6002 int r = reload_order[j];
6004 i = reload_spill_index[r];
6006 /* I is nonneg if this reload uses a register.
6007 If rld[r].reg_rtx is 0, this is an optional reload
6008 that we opted to ignore. */
6009 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6010 && rld[r].reg_rtx != 0)
6012 int nregno = REGNO (rld[r].out_reg);
6015 if (nregno < FIRST_PSEUDO_REGISTER)
6016 nr = hard_regno_nregs[nregno][rld[r].mode];
6019 reg_has_output_reload[nregno + nr] = 1;
6023 nr = hard_regno_nregs[i][rld[r].mode];
6025 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6028 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6029 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6030 || rld[r].when_needed == RELOAD_FOR_INSN);
6035 /* Deallocate the reload register for reload R. This is called from
6036 remove_address_replacements. */
6039 deallocate_reload_reg (int r)
6043 if (! rld[r].reg_rtx)
6045 regno = true_regnum (rld[r].reg_rtx);
6047 if (spill_reg_order[regno] >= 0)
6048 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6050 reload_spill_index[r] = -1;
6053 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6054 reloads of the same item for fear that we might not have enough reload
6055 registers. However, normally they will get the same reload register
6056 and hence actually need not be loaded twice.
6058 Here we check for the most common case of this phenomenon: when we have
6059 a number of reloads for the same object, each of which were allocated
6060 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6061 reload, and is not modified in the insn itself. If we find such,
6062 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6063 This will not increase the number of spill registers needed and will
6064 prevent redundant code. */
6067 merge_assigned_reloads (rtx insn)
6071 /* Scan all the reloads looking for ones that only load values and
6072 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6073 assigned and not modified by INSN. */
6075 for (i = 0; i < n_reloads; i++)
6077 int conflicting_input = 0;
6078 int max_input_address_opnum = -1;
6079 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6081 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6082 || rld[i].out != 0 || rld[i].reg_rtx == 0
6083 || reg_set_p (rld[i].reg_rtx, insn))
6086 /* Look at all other reloads. Ensure that the only use of this
6087 reload_reg_rtx is in a reload that just loads the same value
6088 as we do. Note that any secondary reloads must be of the identical
6089 class since the values, modes, and result registers are the
6090 same, so we need not do anything with any secondary reloads. */
6092 for (j = 0; j < n_reloads; j++)
6094 if (i == j || rld[j].reg_rtx == 0
6095 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6099 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6100 && rld[j].opnum > max_input_address_opnum)
6101 max_input_address_opnum = rld[j].opnum;
6103 /* If the reload regs aren't exactly the same (e.g, different modes)
6104 or if the values are different, we can't merge this reload.
6105 But if it is an input reload, we might still merge
6106 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6108 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6109 || rld[j].out != 0 || rld[j].in == 0
6110 || ! rtx_equal_p (rld[i].in, rld[j].in))
6112 if (rld[j].when_needed != RELOAD_FOR_INPUT
6113 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6114 || rld[i].opnum > rld[j].opnum)
6115 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6117 conflicting_input = 1;
6118 if (min_conflicting_input_opnum > rld[j].opnum)
6119 min_conflicting_input_opnum = rld[j].opnum;
6123 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6124 we, in fact, found any matching reloads. */
6127 && max_input_address_opnum <= min_conflicting_input_opnum)
6129 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6131 for (j = 0; j < n_reloads; j++)
6132 if (i != j && rld[j].reg_rtx != 0
6133 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6134 && (! conflicting_input
6135 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6136 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6138 rld[i].when_needed = RELOAD_OTHER;
6140 reload_spill_index[j] = -1;
6141 transfer_replacements (i, j);
6144 /* If this is now RELOAD_OTHER, look for any reloads that load
6145 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6146 if they were for inputs, RELOAD_OTHER for outputs. Note that
6147 this test is equivalent to looking for reloads for this operand
6149 /* We must take special care with RELOAD_FOR_OUTPUT_ADDRESS; it may
6150 share registers with a RELOAD_FOR_INPUT, so we can not change it
6151 to RELOAD_FOR_OTHER_ADDRESS. We should never need to, since we
6152 do not modify RELOAD_FOR_OUTPUT. */
6154 if (rld[i].when_needed == RELOAD_OTHER)
6155 for (j = 0; j < n_reloads; j++)
6157 && rld[j].when_needed != RELOAD_OTHER
6158 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6159 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6160 && (! conflicting_input
6161 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6162 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6163 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6169 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6170 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6171 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6173 /* Check to see if we accidentally converted two
6174 reloads that use the same reload register with
6175 different inputs to the same type. If so, the
6176 resulting code won't work. */
6178 for (k = 0; k < j; k++)
6179 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6180 || rld[k].when_needed != rld[j].when_needed
6181 || !rtx_equal_p (rld[k].reg_rtx,
6183 || rtx_equal_p (rld[k].in,
6190 /* These arrays are filled by emit_reload_insns and its subroutines. */
6191 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6192 static rtx other_input_address_reload_insns = 0;
6193 static rtx other_input_reload_insns = 0;
6194 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6195 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6196 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6197 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6198 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6199 static rtx operand_reload_insns = 0;
6200 static rtx other_operand_reload_insns = 0;
6201 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6203 /* Values to be put in spill_reg_store are put here first. */
6204 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6205 static HARD_REG_SET reg_reloaded_died;
6207 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6208 has the number J. OLD contains the value to be used as input. */
6211 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6214 rtx insn = chain->insn;
6215 rtx reloadreg = rl->reg_rtx;
6216 rtx oldequiv_reg = 0;
6219 enum machine_mode mode;
6222 /* Determine the mode to reload in.
6223 This is very tricky because we have three to choose from.
6224 There is the mode the insn operand wants (rl->inmode).
6225 There is the mode of the reload register RELOADREG.
6226 There is the intrinsic mode of the operand, which we could find
6227 by stripping some SUBREGs.
6228 It turns out that RELOADREG's mode is irrelevant:
6229 we can change that arbitrarily.
6231 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6232 then the reload reg may not support QImode moves, so use SImode.
6233 If foo is in memory due to spilling a pseudo reg, this is safe,
6234 because the QImode value is in the least significant part of a
6235 slot big enough for a SImode. If foo is some other sort of
6236 memory reference, then it is impossible to reload this case,
6237 so previous passes had better make sure this never happens.
6239 Then consider a one-word union which has SImode and one of its
6240 members is a float, being fetched as (SUBREG:SF union:SI).
6241 We must fetch that as SFmode because we could be loading into
6242 a float-only register. In this case OLD's mode is correct.
6244 Consider an immediate integer: it has VOIDmode. Here we need
6245 to get a mode from something else.
6247 In some cases, there is a fourth mode, the operand's
6248 containing mode. If the insn specifies a containing mode for
6249 this operand, it overrides all others.
6251 I am not sure whether the algorithm here is always right,
6252 but it does the right things in those cases. */
6254 mode = GET_MODE (old);
6255 if (mode == VOIDmode)
6258 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6259 /* If we need a secondary register for this operation, see if
6260 the value is already in a register in that class. Don't
6261 do this if the secondary register will be used as a scratch
6264 if (rl->secondary_in_reload >= 0
6265 && rl->secondary_in_icode == CODE_FOR_nothing
6268 = find_equiv_reg (old, insn,
6269 rld[rl->secondary_in_reload].class,
6273 /* If reloading from memory, see if there is a register
6274 that already holds the same value. If so, reload from there.
6275 We can pass 0 as the reload_reg_p argument because
6276 any other reload has either already been emitted,
6277 in which case find_equiv_reg will see the reload-insn,
6278 or has yet to be emitted, in which case it doesn't matter
6279 because we will use this equiv reg right away. */
6281 if (oldequiv == 0 && optimize
6284 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6285 && reg_renumber[REGNO (old)] < 0)))
6286 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6290 unsigned int regno = true_regnum (oldequiv);
6292 /* Don't use OLDEQUIV if any other reload changes it at an
6293 earlier stage of this insn or at this stage. */
6294 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6295 rl->in, const0_rtx, j, 0))
6298 /* If it is no cheaper to copy from OLDEQUIV into the
6299 reload register than it would be to move from memory,
6300 don't use it. Likewise, if we need a secondary register
6304 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6305 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6307 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6308 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6309 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6313 #ifdef SECONDARY_MEMORY_NEEDED
6314 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6322 /* delete_output_reload is only invoked properly if old contains
6323 the original pseudo register. Since this is replaced with a
6324 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6325 find the pseudo in RELOAD_IN_REG. */
6327 && reload_override_in[j]
6328 && REG_P (rl->in_reg))
6335 else if (REG_P (oldequiv))
6336 oldequiv_reg = oldequiv;
6337 else if (GET_CODE (oldequiv) == SUBREG)
6338 oldequiv_reg = SUBREG_REG (oldequiv);
6340 /* If we are reloading from a register that was recently stored in
6341 with an output-reload, see if we can prove there was
6342 actually no need to store the old value in it. */
6344 if (optimize && REG_P (oldequiv)
6345 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6346 && spill_reg_store[REGNO (oldequiv)]
6348 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6349 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6351 delete_output_reload (insn, j, REGNO (oldequiv));
6353 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6354 then load RELOADREG from OLDEQUIV. Note that we cannot use
6355 gen_lowpart_common since it can do the wrong thing when
6356 RELOADREG has a multi-word mode. Note that RELOADREG
6357 must always be a REG here. */
6359 if (GET_MODE (reloadreg) != mode)
6360 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6361 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6362 oldequiv = SUBREG_REG (oldequiv);
6363 if (GET_MODE (oldequiv) != VOIDmode
6364 && mode != GET_MODE (oldequiv))
6365 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6367 /* Switch to the right place to emit the reload insns. */
6368 switch (rl->when_needed)
6371 where = &other_input_reload_insns;
6373 case RELOAD_FOR_INPUT:
6374 where = &input_reload_insns[rl->opnum];
6376 case RELOAD_FOR_INPUT_ADDRESS:
6377 where = &input_address_reload_insns[rl->opnum];
6379 case RELOAD_FOR_INPADDR_ADDRESS:
6380 where = &inpaddr_address_reload_insns[rl->opnum];
6382 case RELOAD_FOR_OUTPUT_ADDRESS:
6383 where = &output_address_reload_insns[rl->opnum];
6385 case RELOAD_FOR_OUTADDR_ADDRESS:
6386 where = &outaddr_address_reload_insns[rl->opnum];
6388 case RELOAD_FOR_OPERAND_ADDRESS:
6389 where = &operand_reload_insns;
6391 case RELOAD_FOR_OPADDR_ADDR:
6392 where = &other_operand_reload_insns;
6394 case RELOAD_FOR_OTHER_ADDRESS:
6395 where = &other_input_address_reload_insns;
6401 push_to_sequence (*where);
6403 /* Auto-increment addresses must be reloaded in a special way. */
6404 if (rl->out && ! rl->out_reg)
6406 /* We are not going to bother supporting the case where a
6407 incremented register can't be copied directly from
6408 OLDEQUIV since this seems highly unlikely. */
6409 gcc_assert (rl->secondary_in_reload < 0);
6411 if (reload_inherited[j])
6412 oldequiv = reloadreg;
6414 old = XEXP (rl->in_reg, 0);
6416 if (optimize && REG_P (oldequiv)
6417 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6418 && spill_reg_store[REGNO (oldequiv)]
6420 && (dead_or_set_p (insn,
6421 spill_reg_stored_to[REGNO (oldequiv)])
6422 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6424 delete_output_reload (insn, j, REGNO (oldequiv));
6426 /* Prevent normal processing of this reload. */
6428 /* Output a special code sequence for this case. */
6429 new_spill_reg_store[REGNO (reloadreg)]
6430 = inc_for_reload (reloadreg, oldequiv, rl->out,
6434 /* If we are reloading a pseudo-register that was set by the previous
6435 insn, see if we can get rid of that pseudo-register entirely
6436 by redirecting the previous insn into our reload register. */
6438 else if (optimize && REG_P (old)
6439 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6440 && dead_or_set_p (insn, old)
6441 /* This is unsafe if some other reload
6442 uses the same reg first. */
6443 && ! conflicts_with_override (reloadreg)
6444 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6445 rl->when_needed, old, rl->out, j, 0))
6447 rtx temp = PREV_INSN (insn);
6448 while (temp && NOTE_P (temp))
6449 temp = PREV_INSN (temp);
6451 && NONJUMP_INSN_P (temp)
6452 && GET_CODE (PATTERN (temp)) == SET
6453 && SET_DEST (PATTERN (temp)) == old
6454 /* Make sure we can access insn_operand_constraint. */
6455 && asm_noperands (PATTERN (temp)) < 0
6456 /* This is unsafe if operand occurs more than once in current
6457 insn. Perhaps some occurrences aren't reloaded. */
6458 && count_occurrences (PATTERN (insn), old, 0) == 1)
6460 rtx old = SET_DEST (PATTERN (temp));
6461 /* Store into the reload register instead of the pseudo. */
6462 SET_DEST (PATTERN (temp)) = reloadreg;
6464 /* Verify that resulting insn is valid. */
6465 extract_insn (temp);
6466 if (constrain_operands (1))
6468 /* If the previous insn is an output reload, the source is
6469 a reload register, and its spill_reg_store entry will
6470 contain the previous destination. This is now
6472 if (REG_P (SET_SRC (PATTERN (temp)))
6473 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6475 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6476 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6479 /* If these are the only uses of the pseudo reg,
6480 pretend for GDB it lives in the reload reg we used. */
6481 if (REG_N_DEATHS (REGNO (old)) == 1
6482 && REG_N_SETS (REGNO (old)) == 1)
6484 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6485 alter_reg (REGNO (old), -1);
6491 SET_DEST (PATTERN (temp)) = old;
6496 /* We can't do that, so output an insn to load RELOADREG. */
6498 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6499 /* If we have a secondary reload, pick up the secondary register
6500 and icode, if any. If OLDEQUIV and OLD are different or
6501 if this is an in-out reload, recompute whether or not we
6502 still need a secondary register and what the icode should
6503 be. If we still need a secondary register and the class or
6504 icode is different, go back to reloading from OLD if using
6505 OLDEQUIV means that we got the wrong type of register. We
6506 cannot have different class or icode due to an in-out reload
6507 because we don't make such reloads when both the input and
6508 output need secondary reload registers. */
6510 if (! special && rl->secondary_in_reload >= 0)
6512 rtx second_reload_reg = 0;
6513 int secondary_reload = rl->secondary_in_reload;
6514 rtx real_oldequiv = oldequiv;
6517 enum insn_code icode;
6519 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6520 and similarly for OLD.
6521 See comments in get_secondary_reload in reload.c. */
6522 /* If it is a pseudo that cannot be replaced with its
6523 equivalent MEM, we must fall back to reload_in, which
6524 will have all the necessary substitutions registered.
6525 Likewise for a pseudo that can't be replaced with its
6526 equivalent constant.
6528 Take extra care for subregs of such pseudos. Note that
6529 we cannot use reg_equiv_mem in this case because it is
6530 not in the right mode. */
6533 if (GET_CODE (tmp) == SUBREG)
6534 tmp = SUBREG_REG (tmp);
6536 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6537 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6538 || reg_equiv_constant[REGNO (tmp)] != 0))
6540 if (! reg_equiv_mem[REGNO (tmp)]
6541 || num_not_at_initial_offset
6542 || GET_CODE (oldequiv) == SUBREG)
6543 real_oldequiv = rl->in;
6545 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6549 if (GET_CODE (tmp) == SUBREG)
6550 tmp = SUBREG_REG (tmp);
6552 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6553 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6554 || reg_equiv_constant[REGNO (tmp)] != 0))
6556 if (! reg_equiv_mem[REGNO (tmp)]
6557 || num_not_at_initial_offset
6558 || GET_CODE (old) == SUBREG)
6561 real_old = reg_equiv_mem[REGNO (tmp)];
6564 second_reload_reg = rld[secondary_reload].reg_rtx;
6565 icode = rl->secondary_in_icode;
6567 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6568 || (rl->in != 0 && rl->out != 0))
6570 enum reg_class new_class
6571 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6572 mode, real_oldequiv);
6574 if (new_class == NO_REGS)
6575 second_reload_reg = 0;
6578 enum insn_code new_icode;
6579 enum machine_mode new_mode;
6581 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6582 REGNO (second_reload_reg)))
6583 oldequiv = old, real_oldequiv = real_old;
6586 new_icode = reload_in_optab[(int) mode];
6587 if (new_icode != CODE_FOR_nothing
6588 && ((insn_data[(int) new_icode].operand[0].predicate
6589 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6591 || (insn_data[(int) new_icode].operand[1].predicate
6592 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6593 (real_oldequiv, mode)))))
6594 new_icode = CODE_FOR_nothing;
6596 if (new_icode == CODE_FOR_nothing)
6599 new_mode = insn_data[(int) new_icode].operand[2].mode;
6601 if (GET_MODE (second_reload_reg) != new_mode)
6603 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6605 oldequiv = old, real_oldequiv = real_old;
6608 = reload_adjust_reg_for_mode (second_reload_reg,
6615 /* If we still need a secondary reload register, check
6616 to see if it is being used as a scratch or intermediate
6617 register and generate code appropriately. If we need
6618 a scratch register, use REAL_OLDEQUIV since the form of
6619 the insn may depend on the actual address if it is
6622 if (second_reload_reg)
6624 if (icode != CODE_FOR_nothing)
6626 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6627 second_reload_reg));
6632 /* See if we need a scratch register to load the
6633 intermediate register (a tertiary reload). */
6634 enum insn_code tertiary_icode
6635 = rld[secondary_reload].secondary_in_icode;
6637 if (tertiary_icode != CODE_FOR_nothing)
6639 rtx third_reload_reg
6640 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6642 emit_insn ((GEN_FCN (tertiary_icode)
6643 (second_reload_reg, real_oldequiv,
6644 third_reload_reg)));
6647 gen_reload (second_reload_reg, real_oldequiv,
6651 oldequiv = second_reload_reg;
6657 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6659 rtx real_oldequiv = oldequiv;
6661 if ((REG_P (oldequiv)
6662 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6663 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6664 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6665 || (GET_CODE (oldequiv) == SUBREG
6666 && REG_P (SUBREG_REG (oldequiv))
6667 && (REGNO (SUBREG_REG (oldequiv))
6668 >= FIRST_PSEUDO_REGISTER)
6669 && ((reg_equiv_memory_loc
6670 [REGNO (SUBREG_REG (oldequiv))] != 0)
6671 || (reg_equiv_constant
6672 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6673 || (CONSTANT_P (oldequiv)
6674 && (PREFERRED_RELOAD_CLASS (oldequiv,
6675 REGNO_REG_CLASS (REGNO (reloadreg)))
6677 real_oldequiv = rl->in;
6678 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6682 if (flag_non_call_exceptions)
6683 copy_eh_notes (insn, get_insns ());
6685 /* End this sequence. */
6686 *where = get_insns ();
6689 /* Update reload_override_in so that delete_address_reloads_1
6690 can see the actual register usage. */
6692 reload_override_in[j] = oldequiv;
6695 /* Generate insns to for the output reload RL, which is for the insn described
6696 by CHAIN and has the number J. */
6698 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6701 rtx reloadreg = rl->reg_rtx;
6702 rtx insn = chain->insn;
6705 enum machine_mode mode = GET_MODE (old);
6708 if (rl->when_needed == RELOAD_OTHER)
6711 push_to_sequence (output_reload_insns[rl->opnum]);
6713 /* Determine the mode to reload in.
6714 See comments above (for input reloading). */
6716 if (mode == VOIDmode)
6718 /* VOIDmode should never happen for an output. */
6719 if (asm_noperands (PATTERN (insn)) < 0)
6720 /* It's the compiler's fault. */
6721 fatal_insn ("VOIDmode on an output", insn);
6722 error_for_asm (insn, "output operand is constant in %<asm%>");
6723 /* Prevent crash--use something we know is valid. */
6725 old = gen_rtx_REG (mode, REGNO (reloadreg));
6728 if (GET_MODE (reloadreg) != mode)
6729 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6731 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6733 /* If we need two reload regs, set RELOADREG to the intermediate
6734 one, since it will be stored into OLD. We might need a secondary
6735 register only for an input reload, so check again here. */
6737 if (rl->secondary_out_reload >= 0)
6741 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
6742 && reg_equiv_mem[REGNO (old)] != 0)
6743 real_old = reg_equiv_mem[REGNO (old)];
6745 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6749 rtx second_reloadreg = reloadreg;
6750 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6752 /* See if RELOADREG is to be used as a scratch register
6753 or as an intermediate register. */
6754 if (rl->secondary_out_icode != CODE_FOR_nothing)
6756 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6757 (real_old, second_reloadreg, reloadreg)));
6762 /* See if we need both a scratch and intermediate reload
6765 int secondary_reload = rl->secondary_out_reload;
6766 enum insn_code tertiary_icode
6767 = rld[secondary_reload].secondary_out_icode;
6769 if (GET_MODE (reloadreg) != mode)
6770 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6772 if (tertiary_icode != CODE_FOR_nothing)
6775 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6778 /* Copy primary reload reg to secondary reload reg.
6779 (Note that these have been swapped above, then
6780 secondary reload reg to OLD using our insn.) */
6782 /* If REAL_OLD is a paradoxical SUBREG, remove it
6783 and try to put the opposite SUBREG on
6785 if (GET_CODE (real_old) == SUBREG
6786 && (GET_MODE_SIZE (GET_MODE (real_old))
6787 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6788 && 0 != (tem = gen_lowpart_common
6789 (GET_MODE (SUBREG_REG (real_old)),
6791 real_old = SUBREG_REG (real_old), reloadreg = tem;
6793 gen_reload (reloadreg, second_reloadreg,
6794 rl->opnum, rl->when_needed);
6795 emit_insn ((GEN_FCN (tertiary_icode)
6796 (real_old, reloadreg, third_reloadreg)));
6801 /* Copy between the reload regs here and then to
6804 gen_reload (reloadreg, second_reloadreg,
6805 rl->opnum, rl->when_needed);
6811 /* Output the last reload insn. */
6816 /* Don't output the last reload if OLD is not the dest of
6817 INSN and is in the src and is clobbered by INSN. */
6818 if (! flag_expensive_optimizations
6820 || !(set = single_set (insn))
6821 || rtx_equal_p (old, SET_DEST (set))
6822 || !reg_mentioned_p (old, SET_SRC (set))
6823 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
6824 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
6825 gen_reload (old, reloadreg, rl->opnum,
6829 /* Look at all insns we emitted, just to be safe. */
6830 for (p = get_insns (); p; p = NEXT_INSN (p))
6833 rtx pat = PATTERN (p);
6835 /* If this output reload doesn't come from a spill reg,
6836 clear any memory of reloaded copies of the pseudo reg.
6837 If this output reload comes from a spill reg,
6838 reg_has_output_reload will make this do nothing. */
6839 note_stores (pat, forget_old_reloads_1, NULL);
6841 if (reg_mentioned_p (rl->reg_rtx, pat))
6843 rtx set = single_set (insn);
6844 if (reload_spill_index[j] < 0
6846 && SET_SRC (set) == rl->reg_rtx)
6848 int src = REGNO (SET_SRC (set));
6850 reload_spill_index[j] = src;
6851 SET_HARD_REG_BIT (reg_is_output_reload, src);
6852 if (find_regno_note (insn, REG_DEAD, src))
6853 SET_HARD_REG_BIT (reg_reloaded_died, src);
6855 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6857 int s = rl->secondary_out_reload;
6858 set = single_set (p);
6859 /* If this reload copies only to the secondary reload
6860 register, the secondary reload does the actual
6862 if (s >= 0 && set == NULL_RTX)
6863 /* We can't tell what function the secondary reload
6864 has and where the actual store to the pseudo is
6865 made; leave new_spill_reg_store alone. */
6868 && SET_SRC (set) == rl->reg_rtx
6869 && SET_DEST (set) == rld[s].reg_rtx)
6871 /* Usually the next instruction will be the
6872 secondary reload insn; if we can confirm
6873 that it is, setting new_spill_reg_store to
6874 that insn will allow an extra optimization. */
6875 rtx s_reg = rld[s].reg_rtx;
6876 rtx next = NEXT_INSN (p);
6877 rld[s].out = rl->out;
6878 rld[s].out_reg = rl->out_reg;
6879 set = single_set (next);
6880 if (set && SET_SRC (set) == s_reg
6881 && ! new_spill_reg_store[REGNO (s_reg)])
6883 SET_HARD_REG_BIT (reg_is_output_reload,
6885 new_spill_reg_store[REGNO (s_reg)] = next;
6889 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6894 if (rl->when_needed == RELOAD_OTHER)
6896 emit_insn (other_output_reload_insns[rl->opnum]);
6897 other_output_reload_insns[rl->opnum] = get_insns ();
6900 output_reload_insns[rl->opnum] = get_insns ();
6902 if (flag_non_call_exceptions)
6903 copy_eh_notes (insn, get_insns ());
6908 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6909 and has the number J. */
6911 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
6913 rtx insn = chain->insn;
6914 rtx old = (rl->in && MEM_P (rl->in)
6915 ? rl->in_reg : rl->in);
6918 /* AUTO_INC reloads need to be handled even if inherited. We got an
6919 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6920 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6921 && ! rtx_equal_p (rl->reg_rtx, old)
6922 && rl->reg_rtx != 0)
6923 emit_input_reload_insns (chain, rld + j, old, j);
6925 /* When inheriting a wider reload, we have a MEM in rl->in,
6926 e.g. inheriting a SImode output reload for
6927 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6928 if (optimize && reload_inherited[j] && rl->in
6930 && MEM_P (rl->in_reg)
6931 && reload_spill_index[j] >= 0
6932 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6933 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6935 /* If we are reloading a register that was recently stored in with an
6936 output-reload, see if we can prove there was
6937 actually no need to store the old value in it. */
6940 /* Only attempt this for input reloads; for RELOAD_OTHER we miss
6941 that there may be multiple uses of the previous output reload.
6942 Restricting to RELOAD_FOR_INPUT is mostly paranoia. */
6943 && rl->when_needed == RELOAD_FOR_INPUT
6944 && (reload_inherited[j] || reload_override_in[j])
6946 && REG_P (rl->reg_rtx)
6947 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6949 /* There doesn't seem to be any reason to restrict this to pseudos
6950 and doing so loses in the case where we are copying from a
6951 register of the wrong class. */
6952 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6953 >= FIRST_PSEUDO_REGISTER)
6955 /* The insn might have already some references to stackslots
6956 replaced by MEMs, while reload_out_reg still names the
6958 && (dead_or_set_p (insn,
6959 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6960 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6962 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6965 /* Do output reloading for reload RL, which is for the insn described by
6966 CHAIN and has the number J.
6967 ??? At some point we need to support handling output reloads of
6968 JUMP_INSNs or insns that set cc0. */
6970 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
6973 rtx insn = chain->insn;
6974 /* If this is an output reload that stores something that is
6975 not loaded in this same reload, see if we can eliminate a previous
6977 rtx pseudo = rl->out_reg;
6982 && ! rtx_equal_p (rl->in_reg, pseudo)
6983 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6984 && reg_last_reload_reg[REGNO (pseudo)])
6986 int pseudo_no = REGNO (pseudo);
6987 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6989 /* We don't need to test full validity of last_regno for
6990 inherit here; we only want to know if the store actually
6991 matches the pseudo. */
6992 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6993 && reg_reloaded_contents[last_regno] == pseudo_no
6994 && spill_reg_store[last_regno]
6995 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6996 delete_output_reload (insn, j, last_regno);
7001 || rl->reg_rtx == old
7002 || rl->reg_rtx == 0)
7005 /* An output operand that dies right away does need a reload,
7006 but need not be copied from it. Show the new location in the
7008 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7009 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7011 XEXP (note, 0) = rl->reg_rtx;
7014 /* Likewise for a SUBREG of an operand that dies. */
7015 else if (GET_CODE (old) == SUBREG
7016 && REG_P (SUBREG_REG (old))
7017 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7020 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
7024 else if (GET_CODE (old) == SCRATCH)
7025 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7026 but we don't want to make an output reload. */
7029 /* If is a JUMP_INSN, we can't support output reloads yet. */
7030 gcc_assert (!JUMP_P (insn));
7032 emit_output_reload_insns (chain, rld + j, j);
7035 /* Reload number R reloads from or to a group of hard registers starting at
7036 register REGNO. Return true if it can be treated for inheritance purposes
7037 like a group of reloads, each one reloading a single hard register.
7038 The caller has already checked that the spill register and REGNO use
7039 the same number of registers to store the reload value. */
7042 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
7044 #ifdef CANNOT_CHANGE_MODE_CLASS
7045 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
7046 GET_MODE (rld[r].reg_rtx),
7047 reg_raw_mode[reload_spill_index[r]])
7048 && !REG_CANNOT_CHANGE_MODE_P (regno,
7049 GET_MODE (rld[r].reg_rtx),
7050 reg_raw_mode[regno]));
7056 /* Output insns to reload values in and out of the chosen reload regs. */
7059 emit_reload_insns (struct insn_chain *chain)
7061 rtx insn = chain->insn;
7065 CLEAR_HARD_REG_SET (reg_reloaded_died);
7067 for (j = 0; j < reload_n_operands; j++)
7068 input_reload_insns[j] = input_address_reload_insns[j]
7069 = inpaddr_address_reload_insns[j]
7070 = output_reload_insns[j] = output_address_reload_insns[j]
7071 = outaddr_address_reload_insns[j]
7072 = other_output_reload_insns[j] = 0;
7073 other_input_address_reload_insns = 0;
7074 other_input_reload_insns = 0;
7075 operand_reload_insns = 0;
7076 other_operand_reload_insns = 0;
7078 /* Dump reloads into the dump file. */
7081 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7082 debug_reload_to_stream (dump_file);
7085 /* Now output the instructions to copy the data into and out of the
7086 reload registers. Do these in the order that the reloads were reported,
7087 since reloads of base and index registers precede reloads of operands
7088 and the operands may need the base and index registers reloaded. */
7090 for (j = 0; j < n_reloads; j++)
7093 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7094 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7096 do_input_reload (chain, rld + j, j);
7097 do_output_reload (chain, rld + j, j);
7100 /* Now write all the insns we made for reloads in the order expected by
7101 the allocation functions. Prior to the insn being reloaded, we write
7102 the following reloads:
7104 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7106 RELOAD_OTHER reloads.
7108 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7109 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7110 RELOAD_FOR_INPUT reload for the operand.
7112 RELOAD_FOR_OPADDR_ADDRS reloads.
7114 RELOAD_FOR_OPERAND_ADDRESS reloads.
7116 After the insn being reloaded, we write the following:
7118 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7119 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7120 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7121 reloads for the operand. The RELOAD_OTHER output reloads are
7122 output in descending order by reload number. */
7124 emit_insn_before (other_input_address_reload_insns, insn);
7125 emit_insn_before (other_input_reload_insns, insn);
7127 for (j = 0; j < reload_n_operands; j++)
7129 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7130 emit_insn_before (input_address_reload_insns[j], insn);
7131 emit_insn_before (input_reload_insns[j], insn);
7134 emit_insn_before (other_operand_reload_insns, insn);
7135 emit_insn_before (operand_reload_insns, insn);
7137 for (j = 0; j < reload_n_operands; j++)
7139 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7140 x = emit_insn_after (output_address_reload_insns[j], x);
7141 x = emit_insn_after (output_reload_insns[j], x);
7142 emit_insn_after (other_output_reload_insns[j], x);
7145 /* For all the spill regs newly reloaded in this instruction,
7146 record what they were reloaded from, so subsequent instructions
7147 can inherit the reloads.
7149 Update spill_reg_store for the reloads of this insn.
7150 Copy the elements that were updated in the loop above. */
7152 for (j = 0; j < n_reloads; j++)
7154 int r = reload_order[j];
7155 int i = reload_spill_index[r];
7157 /* If this is a non-inherited input reload from a pseudo, we must
7158 clear any memory of a previous store to the same pseudo. Only do
7159 something if there will not be an output reload for the pseudo
7161 if (rld[r].in_reg != 0
7162 && ! (reload_inherited[r] || reload_override_in[r]))
7164 rtx reg = rld[r].in_reg;
7166 if (GET_CODE (reg) == SUBREG)
7167 reg = SUBREG_REG (reg);
7170 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7171 && ! reg_has_output_reload[REGNO (reg)])
7173 int nregno = REGNO (reg);
7175 if (reg_last_reload_reg[nregno])
7177 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7179 if (reg_reloaded_contents[last_regno] == nregno)
7180 spill_reg_store[last_regno] = 0;
7185 /* I is nonneg if this reload used a register.
7186 If rld[r].reg_rtx is 0, this is an optional reload
7187 that we opted to ignore. */
7189 if (i >= 0 && rld[r].reg_rtx != 0)
7191 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7193 int part_reaches_end = 0;
7194 int all_reaches_end = 1;
7196 /* For a multi register reload, we need to check if all or part
7197 of the value lives to the end. */
7198 for (k = 0; k < nr; k++)
7200 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7201 rld[r].when_needed))
7202 part_reaches_end = 1;
7204 all_reaches_end = 0;
7207 /* Ignore reloads that don't reach the end of the insn in
7209 if (all_reaches_end)
7211 /* First, clear out memory of what used to be in this spill reg.
7212 If consecutive registers are used, clear them all. */
7214 for (k = 0; k < nr; k++)
7216 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7217 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7220 /* Maybe the spill reg contains a copy of reload_out. */
7222 && (REG_P (rld[r].out)
7226 || REG_P (rld[r].out_reg)))
7228 rtx out = (REG_P (rld[r].out)
7232 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7233 int nregno = REGNO (out);
7234 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7235 : hard_regno_nregs[nregno]
7236 [GET_MODE (rld[r].reg_rtx)]);
7239 spill_reg_store[i] = new_spill_reg_store[i];
7240 spill_reg_stored_to[i] = out;
7241 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7243 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7245 && inherit_piecemeal_p (r, nregno));
7247 /* If NREGNO is a hard register, it may occupy more than
7248 one register. If it does, say what is in the
7249 rest of the registers assuming that both registers
7250 agree on how many words the object takes. If not,
7251 invalidate the subsequent registers. */
7253 if (nregno < FIRST_PSEUDO_REGISTER)
7254 for (k = 1; k < nnr; k++)
7255 reg_last_reload_reg[nregno + k]
7257 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7260 /* Now do the inverse operation. */
7261 for (k = 0; k < nr; k++)
7263 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7264 reg_reloaded_contents[i + k]
7265 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7268 reg_reloaded_insn[i + k] = insn;
7269 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7270 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7271 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7275 /* Maybe the spill reg contains a copy of reload_in. Only do
7276 something if there will not be an output reload for
7277 the register being reloaded. */
7278 else if (rld[r].out_reg == 0
7280 && ((REG_P (rld[r].in)
7281 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7282 && ! reg_has_output_reload[REGNO (rld[r].in)])
7283 || (REG_P (rld[r].in_reg)
7284 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7285 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7292 if (REG_P (rld[r].in)
7293 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7295 else if (REG_P (rld[r].in_reg))
7298 in = XEXP (rld[r].in_reg, 0);
7299 nregno = REGNO (in);
7301 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7302 : hard_regno_nregs[nregno]
7303 [GET_MODE (rld[r].reg_rtx)]);
7305 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7307 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7309 && inherit_piecemeal_p (r, nregno));
7311 if (nregno < FIRST_PSEUDO_REGISTER)
7312 for (k = 1; k < nnr; k++)
7313 reg_last_reload_reg[nregno + k]
7315 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7318 /* Unless we inherited this reload, show we haven't
7319 recently done a store.
7320 Previous stores of inherited auto_inc expressions
7321 also have to be discarded. */
7322 if (! reload_inherited[r]
7323 || (rld[r].out && ! rld[r].out_reg))
7324 spill_reg_store[i] = 0;
7326 for (k = 0; k < nr; k++)
7328 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7329 reg_reloaded_contents[i + k]
7330 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7333 reg_reloaded_insn[i + k] = insn;
7334 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7335 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7336 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7341 /* However, if part of the reload reaches the end, then we must
7342 invalidate the old info for the part that survives to the end. */
7343 else if (part_reaches_end)
7345 for (k = 0; k < nr; k++)
7346 if (reload_reg_reaches_end_p (i + k,
7348 rld[r].when_needed))
7349 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7353 /* The following if-statement was #if 0'd in 1.34 (or before...).
7354 It's reenabled in 1.35 because supposedly nothing else
7355 deals with this problem. */
7357 /* If a register gets output-reloaded from a non-spill register,
7358 that invalidates any previous reloaded copy of it.
7359 But forget_old_reloads_1 won't get to see it, because
7360 it thinks only about the original insn. So invalidate it here. */
7361 if (i < 0 && rld[r].out != 0
7362 && (REG_P (rld[r].out)
7363 || (MEM_P (rld[r].out)
7364 && REG_P (rld[r].out_reg))))
7366 rtx out = (REG_P (rld[r].out)
7367 ? rld[r].out : rld[r].out_reg);
7368 int nregno = REGNO (out);
7369 if (nregno >= FIRST_PSEUDO_REGISTER)
7371 rtx src_reg, store_insn = NULL_RTX;
7373 reg_last_reload_reg[nregno] = 0;
7375 /* If we can find a hard register that is stored, record
7376 the storing insn so that we may delete this insn with
7377 delete_output_reload. */
7378 src_reg = rld[r].reg_rtx;
7380 /* If this is an optional reload, try to find the source reg
7381 from an input reload. */
7384 rtx set = single_set (insn);
7385 if (set && SET_DEST (set) == rld[r].out)
7389 src_reg = SET_SRC (set);
7391 for (k = 0; k < n_reloads; k++)
7393 if (rld[k].in == src_reg)
7395 src_reg = rld[k].reg_rtx;
7402 store_insn = new_spill_reg_store[REGNO (src_reg)];
7403 if (src_reg && REG_P (src_reg)
7404 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7406 int src_regno = REGNO (src_reg);
7407 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7408 /* The place where to find a death note varies with
7409 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7410 necessarily checked exactly in the code that moves
7411 notes, so just check both locations. */
7412 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7413 if (! note && store_insn)
7414 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7417 spill_reg_store[src_regno + nr] = store_insn;
7418 spill_reg_stored_to[src_regno + nr] = out;
7419 reg_reloaded_contents[src_regno + nr] = nregno;
7420 reg_reloaded_insn[src_regno + nr] = store_insn;
7421 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7422 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7423 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7424 GET_MODE (src_reg)))
7425 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7427 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7429 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7431 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7433 reg_last_reload_reg[nregno] = src_reg;
7434 /* We have to set reg_has_output_reload here, or else
7435 forget_old_reloads_1 will clear reg_last_reload_reg
7437 reg_has_output_reload[nregno] = 1;
7442 int num_regs = hard_regno_nregs[nregno][GET_MODE (rld[r].out)];
7444 while (num_regs-- > 0)
7445 reg_last_reload_reg[nregno + num_regs] = 0;
7449 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7452 /* Emit code to perform a reload from IN (which may be a reload register) to
7453 OUT (which may also be a reload register). IN or OUT is from operand
7454 OPNUM with reload type TYPE.
7456 Returns first insn emitted. */
7459 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7461 rtx last = get_last_insn ();
7464 /* If IN is a paradoxical SUBREG, remove it and try to put the
7465 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7466 if (GET_CODE (in) == SUBREG
7467 && (GET_MODE_SIZE (GET_MODE (in))
7468 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7469 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7470 in = SUBREG_REG (in), out = tem;
7471 else if (GET_CODE (out) == SUBREG
7472 && (GET_MODE_SIZE (GET_MODE (out))
7473 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7474 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7475 out = SUBREG_REG (out), in = tem;
7477 /* How to do this reload can get quite tricky. Normally, we are being
7478 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7479 register that didn't get a hard register. In that case we can just
7480 call emit_move_insn.
7482 We can also be asked to reload a PLUS that adds a register or a MEM to
7483 another register, constant or MEM. This can occur during frame pointer
7484 elimination and while reloading addresses. This case is handled by
7485 trying to emit a single insn to perform the add. If it is not valid,
7486 we use a two insn sequence.
7488 Finally, we could be called to handle an 'o' constraint by putting
7489 an address into a register. In that case, we first try to do this
7490 with a named pattern of "reload_load_address". If no such pattern
7491 exists, we just emit a SET insn and hope for the best (it will normally
7492 be valid on machines that use 'o').
7494 This entire process is made complex because reload will never
7495 process the insns we generate here and so we must ensure that
7496 they will fit their constraints and also by the fact that parts of
7497 IN might be being reloaded separately and replaced with spill registers.
7498 Because of this, we are, in some sense, just guessing the right approach
7499 here. The one listed above seems to work.
7501 ??? At some point, this whole thing needs to be rethought. */
7503 if (GET_CODE (in) == PLUS
7504 && (REG_P (XEXP (in, 0))
7505 || GET_CODE (XEXP (in, 0)) == SUBREG
7506 || MEM_P (XEXP (in, 0)))
7507 && (REG_P (XEXP (in, 1))
7508 || GET_CODE (XEXP (in, 1)) == SUBREG
7509 || CONSTANT_P (XEXP (in, 1))
7510 || MEM_P (XEXP (in, 1))))
7512 /* We need to compute the sum of a register or a MEM and another
7513 register, constant, or MEM, and put it into the reload
7514 register. The best possible way of doing this is if the machine
7515 has a three-operand ADD insn that accepts the required operands.
7517 The simplest approach is to try to generate such an insn and see if it
7518 is recognized and matches its constraints. If so, it can be used.
7520 It might be better not to actually emit the insn unless it is valid,
7521 but we need to pass the insn as an operand to `recog' and
7522 `extract_insn' and it is simpler to emit and then delete the insn if
7523 not valid than to dummy things up. */
7525 rtx op0, op1, tem, insn;
7528 op0 = find_replacement (&XEXP (in, 0));
7529 op1 = find_replacement (&XEXP (in, 1));
7531 /* Since constraint checking is strict, commutativity won't be
7532 checked, so we need to do that here to avoid spurious failure
7533 if the add instruction is two-address and the second operand
7534 of the add is the same as the reload reg, which is frequently
7535 the case. If the insn would be A = B + A, rearrange it so
7536 it will be A = A + B as constrain_operands expects. */
7538 if (REG_P (XEXP (in, 1))
7539 && REGNO (out) == REGNO (XEXP (in, 1)))
7540 tem = op0, op0 = op1, op1 = tem;
7542 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7543 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7545 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7546 code = recog_memoized (insn);
7550 extract_insn (insn);
7551 /* We want constrain operands to treat this insn strictly in
7552 its validity determination, i.e., the way it would after reload
7554 if (constrain_operands (1))
7558 delete_insns_since (last);
7560 /* If that failed, we must use a conservative two-insn sequence.
7562 Use a move to copy one operand into the reload register. Prefer
7563 to reload a constant, MEM or pseudo since the move patterns can
7564 handle an arbitrary operand. If OP1 is not a constant, MEM or
7565 pseudo and OP1 is not a valid operand for an add instruction, then
7568 After reloading one of the operands into the reload register, add
7569 the reload register to the output register.
7571 If there is another way to do this for a specific machine, a
7572 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7575 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7577 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7579 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7580 || (code != CODE_FOR_nothing
7581 && ! ((*insn_data[code].operand[2].predicate)
7582 (op1, insn_data[code].operand[2].mode))))
7583 tem = op0, op0 = op1, op1 = tem;
7585 gen_reload (out, op0, opnum, type);
7587 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7588 This fixes a problem on the 32K where the stack pointer cannot
7589 be used as an operand of an add insn. */
7591 if (rtx_equal_p (op0, op1))
7594 insn = emit_insn (gen_add2_insn (out, op1));
7596 /* If that failed, copy the address register to the reload register.
7597 Then add the constant to the reload register. */
7599 code = recog_memoized (insn);
7603 extract_insn (insn);
7604 /* We want constrain operands to treat this insn strictly in
7605 its validity determination, i.e., the way it would after reload
7607 if (constrain_operands (1))
7609 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7611 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7616 delete_insns_since (last);
7618 gen_reload (out, op1, opnum, type);
7619 insn = emit_insn (gen_add2_insn (out, op0));
7620 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7623 #ifdef SECONDARY_MEMORY_NEEDED
7624 /* If we need a memory location to do the move, do it that way. */
7625 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7626 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7627 && (REG_P (out) || GET_CODE (out) == SUBREG)
7628 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7629 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7630 REGNO_REG_CLASS (reg_or_subregno (out)),
7633 /* Get the memory to use and rewrite both registers to its mode. */
7634 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7636 if (GET_MODE (loc) != GET_MODE (out))
7637 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7639 if (GET_MODE (loc) != GET_MODE (in))
7640 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7642 gen_reload (loc, in, opnum, type);
7643 gen_reload (out, loc, opnum, type);
7647 /* If IN is a simple operand, use gen_move_insn. */
7648 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
7649 emit_insn (gen_move_insn (out, in));
7651 #ifdef HAVE_reload_load_address
7652 else if (HAVE_reload_load_address)
7653 emit_insn (gen_reload_load_address (out, in));
7656 /* Otherwise, just write (set OUT IN) and hope for the best. */
7658 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7660 /* Return the first insn emitted.
7661 We can not just return get_last_insn, because there may have
7662 been multiple instructions emitted. Also note that gen_move_insn may
7663 emit more than one insn itself, so we can not assume that there is one
7664 insn emitted per emit_insn_before call. */
7666 return last ? NEXT_INSN (last) : get_insns ();
7669 /* Delete a previously made output-reload whose result we now believe
7670 is not needed. First we double-check.
7672 INSN is the insn now being processed.
7673 LAST_RELOAD_REG is the hard register number for which we want to delete
7674 the last output reload.
7675 J is the reload-number that originally used REG. The caller has made
7676 certain that reload J doesn't use REG any longer for input. */
7679 delete_output_reload (rtx insn, int j, int last_reload_reg)
7681 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7682 rtx reg = spill_reg_stored_to[last_reload_reg];
7685 int n_inherited = 0;
7689 /* It is possible that this reload has been only used to set another reload
7690 we eliminated earlier and thus deleted this instruction too. */
7691 if (INSN_DELETED_P (output_reload_insn))
7694 /* Get the raw pseudo-register referred to. */
7696 while (GET_CODE (reg) == SUBREG)
7697 reg = SUBREG_REG (reg);
7698 substed = reg_equiv_memory_loc[REGNO (reg)];
7700 /* This is unsafe if the operand occurs more often in the current
7701 insn than it is inherited. */
7702 for (k = n_reloads - 1; k >= 0; k--)
7704 rtx reg2 = rld[k].in;
7707 if (MEM_P (reg2) || reload_override_in[k])
7708 reg2 = rld[k].in_reg;
7710 if (rld[k].out && ! rld[k].out_reg)
7711 reg2 = XEXP (rld[k].in_reg, 0);
7713 while (GET_CODE (reg2) == SUBREG)
7714 reg2 = SUBREG_REG (reg2);
7715 if (rtx_equal_p (reg2, reg))
7717 if (reload_inherited[k] || reload_override_in[k] || k == j)
7720 reg2 = rld[k].out_reg;
7723 while (GET_CODE (reg2) == SUBREG)
7724 reg2 = XEXP (reg2, 0);
7725 if (rtx_equal_p (reg2, reg))
7732 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7734 n_occurrences += count_occurrences (PATTERN (insn),
7735 eliminate_regs (substed, 0,
7737 if (n_occurrences > n_inherited)
7740 /* If the pseudo-reg we are reloading is no longer referenced
7741 anywhere between the store into it and here,
7742 and we're within the same basic block, then the value can only
7743 pass through the reload reg and end up here.
7744 Otherwise, give up--return. */
7745 for (i1 = NEXT_INSN (output_reload_insn);
7746 i1 != insn; i1 = NEXT_INSN (i1))
7748 if (NOTE_INSN_BASIC_BLOCK_P (i1))
7750 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
7751 && reg_mentioned_p (reg, PATTERN (i1)))
7753 /* If this is USE in front of INSN, we only have to check that
7754 there are no more references than accounted for by inheritance. */
7755 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
7757 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7758 i1 = NEXT_INSN (i1);
7760 if (n_occurrences <= n_inherited && i1 == insn)
7766 /* We will be deleting the insn. Remove the spill reg information. */
7767 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
7769 spill_reg_store[last_reload_reg + k] = 0;
7770 spill_reg_stored_to[last_reload_reg + k] = 0;
7773 /* The caller has already checked that REG dies or is set in INSN.
7774 It has also checked that we are optimizing, and thus some
7775 inaccuracies in the debugging information are acceptable.
7776 So we could just delete output_reload_insn. But in some cases
7777 we can improve the debugging information without sacrificing
7778 optimization - maybe even improving the code: See if the pseudo
7779 reg has been completely replaced with reload regs. If so, delete
7780 the store insn and forget we had a stack slot for the pseudo. */
7781 if (rld[j].out != rld[j].in
7782 && REG_N_DEATHS (REGNO (reg)) == 1
7783 && REG_N_SETS (REGNO (reg)) == 1
7784 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7785 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7789 /* We know that it was used only between here and the beginning of
7790 the current basic block. (We also know that the last use before
7791 INSN was the output reload we are thinking of deleting, but never
7792 mind that.) Search that range; see if any ref remains. */
7793 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7795 rtx set = single_set (i2);
7797 /* Uses which just store in the pseudo don't count,
7798 since if they are the only uses, they are dead. */
7799 if (set != 0 && SET_DEST (set) == reg)
7804 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
7805 && reg_mentioned_p (reg, PATTERN (i2)))
7807 /* Some other ref remains; just delete the output reload we
7809 delete_address_reloads (output_reload_insn, insn);
7810 delete_insn (output_reload_insn);
7815 /* Delete the now-dead stores into this pseudo. Note that this
7816 loop also takes care of deleting output_reload_insn. */
7817 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7819 rtx set = single_set (i2);
7821 if (set != 0 && SET_DEST (set) == reg)
7823 delete_address_reloads (i2, insn);
7831 /* For the debugging info, say the pseudo lives in this reload reg. */
7832 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7833 alter_reg (REGNO (reg), -1);
7837 delete_address_reloads (output_reload_insn, insn);
7838 delete_insn (output_reload_insn);
7842 /* We are going to delete DEAD_INSN. Recursively delete loads of
7843 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7844 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7846 delete_address_reloads (rtx dead_insn, rtx current_insn)
7848 rtx set = single_set (dead_insn);
7849 rtx set2, dst, prev, next;
7852 rtx dst = SET_DEST (set);
7854 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7856 /* If we deleted the store from a reloaded post_{in,de}c expression,
7857 we can delete the matching adds. */
7858 prev = PREV_INSN (dead_insn);
7859 next = NEXT_INSN (dead_insn);
7860 if (! prev || ! next)
7862 set = single_set (next);
7863 set2 = single_set (prev);
7865 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7866 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7867 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7869 dst = SET_DEST (set);
7870 if (! rtx_equal_p (dst, SET_DEST (set2))
7871 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7872 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7873 || (INTVAL (XEXP (SET_SRC (set), 1))
7874 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7876 delete_related_insns (prev);
7877 delete_related_insns (next);
7880 /* Subfunction of delete_address_reloads: process registers found in X. */
7882 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
7884 rtx prev, set, dst, i2;
7886 enum rtx_code code = GET_CODE (x);
7890 const char *fmt = GET_RTX_FORMAT (code);
7891 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7894 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7895 else if (fmt[i] == 'E')
7897 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7898 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7905 if (spill_reg_order[REGNO (x)] < 0)
7908 /* Scan backwards for the insn that sets x. This might be a way back due
7910 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7912 code = GET_CODE (prev);
7913 if (code == CODE_LABEL || code == JUMP_INSN)
7917 if (reg_set_p (x, PATTERN (prev)))
7919 if (reg_referenced_p (x, PATTERN (prev)))
7922 if (! prev || INSN_UID (prev) < reload_first_uid)
7924 /* Check that PREV only sets the reload register. */
7925 set = single_set (prev);
7928 dst = SET_DEST (set);
7930 || ! rtx_equal_p (dst, x))
7932 if (! reg_set_p (dst, PATTERN (dead_insn)))
7934 /* Check if DST was used in a later insn -
7935 it might have been inherited. */
7936 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7942 if (reg_referenced_p (dst, PATTERN (i2)))
7944 /* If there is a reference to the register in the current insn,
7945 it might be loaded in a non-inherited reload. If no other
7946 reload uses it, that means the register is set before
7948 if (i2 == current_insn)
7950 for (j = n_reloads - 1; j >= 0; j--)
7951 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7952 || reload_override_in[j] == dst)
7954 for (j = n_reloads - 1; j >= 0; j--)
7955 if (rld[j].in && rld[j].reg_rtx == dst)
7964 /* If DST is still live at CURRENT_INSN, check if it is used for
7965 any reload. Note that even if CURRENT_INSN sets DST, we still
7966 have to check the reloads. */
7967 if (i2 == current_insn)
7969 for (j = n_reloads - 1; j >= 0; j--)
7970 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7971 || reload_override_in[j] == dst)
7973 /* ??? We can't finish the loop here, because dst might be
7974 allocated to a pseudo in this block if no reload in this
7975 block needs any of the classes containing DST - see
7976 spill_hard_reg. There is no easy way to tell this, so we
7977 have to scan till the end of the basic block. */
7979 if (reg_set_p (dst, PATTERN (i2)))
7983 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7984 reg_reloaded_contents[REGNO (dst)] = -1;
7988 /* Output reload-insns to reload VALUE into RELOADREG.
7989 VALUE is an autoincrement or autodecrement RTX whose operand
7990 is a register or memory location;
7991 so reloading involves incrementing that location.
7992 IN is either identical to VALUE, or some cheaper place to reload from.
7994 INC_AMOUNT is the number to increment or decrement by (always positive).
7995 This cannot be deduced from VALUE.
7997 Return the instruction that stores into RELOADREG. */
8000 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8002 /* REG or MEM to be copied and incremented. */
8003 rtx incloc = XEXP (value, 0);
8004 /* Nonzero if increment after copying. */
8005 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
8011 rtx real_in = in == value ? XEXP (in, 0) : in;
8013 /* No hard register is equivalent to this register after
8014 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8015 we could inc/dec that register as well (maybe even using it for
8016 the source), but I'm not sure it's worth worrying about. */
8018 reg_last_reload_reg[REGNO (incloc)] = 0;
8020 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8021 inc_amount = -inc_amount;
8023 inc = GEN_INT (inc_amount);
8025 /* If this is post-increment, first copy the location to the reload reg. */
8026 if (post && real_in != reloadreg)
8027 emit_insn (gen_move_insn (reloadreg, real_in));
8031 /* See if we can directly increment INCLOC. Use a method similar to
8032 that in gen_reload. */
8034 last = get_last_insn ();
8035 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8036 gen_rtx_PLUS (GET_MODE (incloc),
8039 code = recog_memoized (add_insn);
8042 extract_insn (add_insn);
8043 if (constrain_operands (1))
8045 /* If this is a pre-increment and we have incremented the value
8046 where it lives, copy the incremented value to RELOADREG to
8047 be used as an address. */
8050 emit_insn (gen_move_insn (reloadreg, incloc));
8055 delete_insns_since (last);
8058 /* If couldn't do the increment directly, must increment in RELOADREG.
8059 The way we do this depends on whether this is pre- or post-increment.
8060 For pre-increment, copy INCLOC to the reload register, increment it
8061 there, then save back. */
8065 if (in != reloadreg)
8066 emit_insn (gen_move_insn (reloadreg, real_in));
8067 emit_insn (gen_add2_insn (reloadreg, inc));
8068 store = emit_insn (gen_move_insn (incloc, reloadreg));
8073 Because this might be a jump insn or a compare, and because RELOADREG
8074 may not be available after the insn in an input reload, we must do
8075 the incrementation before the insn being reloaded for.
8077 We have already copied IN to RELOADREG. Increment the copy in
8078 RELOADREG, save that back, then decrement RELOADREG so it has
8079 the original value. */
8081 emit_insn (gen_add2_insn (reloadreg, inc));
8082 store = emit_insn (gen_move_insn (incloc, reloadreg));
8083 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8091 add_auto_inc_notes (rtx insn, rtx x)
8093 enum rtx_code code = GET_CODE (x);
8097 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8100 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8104 /* Scan all the operand sub-expressions. */
8105 fmt = GET_RTX_FORMAT (code);
8106 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8109 add_auto_inc_notes (insn, XEXP (x, i));
8110 else if (fmt[i] == 'E')
8111 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8112 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8117 /* Copy EH notes from an insn to its reloads. */
8119 copy_eh_notes (rtx insn, rtx x)
8121 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8124 for (; x != 0; x = NEXT_INSN (x))
8126 if (may_trap_p (PATTERN (x)))
8128 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8134 /* This is used by reload pass, that does emit some instructions after
8135 abnormal calls moving basic block end, but in fact it wants to emit
8136 them on the edge. Looks for abnormal call edges, find backward the
8137 proper call and fix the damage.
8139 Similar handle instructions throwing exceptions internally. */
8141 fixup_abnormal_edges (void)
8143 bool inserted = false;
8151 /* Look for cases we are interested in - calls or instructions causing
8153 FOR_EACH_EDGE (e, ei, bb->succs)
8155 if (e->flags & EDGE_ABNORMAL_CALL)
8157 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8158 == (EDGE_ABNORMAL | EDGE_EH))
8161 if (e && !CALL_P (BB_END (bb))
8162 && !can_throw_internal (BB_END (bb)))
8166 /* Get past the new insns generated. Allow notes, as the insns
8167 may be already deleted. */
8169 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8170 && !can_throw_internal (insn)
8171 && insn != BB_HEAD (bb))
8172 insn = PREV_INSN (insn);
8174 if (CALL_P (insn) || can_throw_internal (insn))
8178 stop = NEXT_INSN (BB_END (bb));
8180 insn = NEXT_INSN (insn);
8182 FOR_EACH_EDGE (e, ei, bb->succs)
8183 if (e->flags & EDGE_FALLTHRU)
8186 while (insn && insn != stop)
8188 next = NEXT_INSN (insn);
8193 /* Sometimes there's still the return value USE.
8194 If it's placed after a trapping call (i.e. that
8195 call is the last insn anyway), we have no fallthru
8196 edge. Simply delete this use and don't try to insert
8197 on the non-existent edge. */
8198 if (GET_CODE (PATTERN (insn)) != USE)
8200 /* We're not deleting it, we're moving it. */
8201 INSN_DELETED_P (insn) = 0;
8202 PREV_INSN (insn) = NULL_RTX;
8203 NEXT_INSN (insn) = NULL_RTX;
8205 insert_insn_on_edge (insn, e);
8213 /* It may be that we don't find any such trapping insn. In this
8214 case we discovered quite late that the insn that had been
8215 marked as can_throw_internal in fact couldn't trap at all.
8216 So we should in fact delete the EH edges out of the block. */
8218 purge_dead_edges (bb);
8222 /* We've possibly turned single trapping insn into multiple ones. */
8223 if (flag_non_call_exceptions)
8226 blocks = sbitmap_alloc (last_basic_block);
8227 sbitmap_ones (blocks);
8228 find_many_sub_basic_blocks (blocks);
8232 commit_edge_insertions ();
8234 #ifdef ENABLE_CHECKING
8235 /* Verify that we didn't turn one trapping insn into many, and that
8236 we found and corrected all of the problems wrt fixups on the
8238 verify_flow_info ();
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