1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation,
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
33 #include "insn-config.h"
39 #include "addresses.h"
40 #include "basic-block.h"
50 /* This file contains the reload pass of the compiler, which is
51 run after register allocation has been done. It checks that
52 each insn is valid (operands required to be in registers really
53 are in registers of the proper class) and fixes up invalid ones
54 by copying values temporarily into registers for the insns
57 The results of register allocation are described by the vector
58 reg_renumber; the insns still contain pseudo regs, but reg_renumber
59 can be used to find which hard reg, if any, a pseudo reg is in.
61 The technique we always use is to free up a few hard regs that are
62 called ``reload regs'', and for each place where a pseudo reg
63 must be in a hard reg, copy it temporarily into one of the reload regs.
65 Reload regs are allocated locally for every instruction that needs
66 reloads. When there are pseudos which are allocated to a register that
67 has been chosen as a reload reg, such pseudos must be ``spilled''.
68 This means that they go to other hard regs, or to stack slots if no other
69 available hard regs can be found. Spilling can invalidate more
70 insns, requiring additional need for reloads, so we must keep checking
71 until the process stabilizes.
73 For machines with different classes of registers, we must keep track
74 of the register class needed for each reload, and make sure that
75 we allocate enough reload registers of each class.
77 The file reload.c contains the code that checks one insn for
78 validity and reports the reloads that it needs. This file
79 is in charge of scanning the entire rtl code, accumulating the
80 reload needs, spilling, assigning reload registers to use for
81 fixing up each insn, and generating the new insns to copy values
82 into the reload registers. */
84 /* During reload_as_needed, element N contains a REG rtx for the hard reg
85 into which reg N has been reloaded (perhaps for a previous insn). */
86 static rtx *reg_last_reload_reg;
88 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
89 for an output reload that stores into reg N. */
90 static regset_head reg_has_output_reload;
92 /* Indicates which hard regs are reload-registers for an output reload
93 in the current insn. */
94 static HARD_REG_SET reg_is_output_reload;
96 /* Element N is the constant value to which pseudo reg N is equivalent,
97 or zero if pseudo reg N is not equivalent to a constant.
98 find_reloads looks at this in order to replace pseudo reg N
99 with the constant it stands for. */
100 rtx *reg_equiv_constant;
102 /* Element N is an invariant value to which pseudo reg N is equivalent.
103 eliminate_regs_in_insn uses this to replace pseudos in particular
105 rtx *reg_equiv_invariant;
107 /* Element N is a memory location to which pseudo reg N is equivalent,
108 prior to any register elimination (such as frame pointer to stack
109 pointer). Depending on whether or not it is a valid address, this value
110 is transferred to either reg_equiv_address or reg_equiv_mem. */
111 rtx *reg_equiv_memory_loc;
113 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
114 collector can keep track of what is inside. */
115 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
117 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
118 This is used when the address is not valid as a memory address
119 (because its displacement is too big for the machine.) */
120 rtx *reg_equiv_address;
122 /* Element N is the memory slot to which pseudo reg N is equivalent,
123 or zero if pseudo reg N is not equivalent to a memory slot. */
126 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
127 alternate representations of the location of pseudo reg N. */
128 rtx *reg_equiv_alt_mem_list;
130 /* Widest width in which each pseudo reg is referred to (via subreg). */
131 static unsigned int *reg_max_ref_width;
133 /* Element N is the list of insns that initialized reg N from its equivalent
134 constant or memory slot. */
136 int reg_equiv_init_size;
138 /* Vector to remember old contents of reg_renumber before spilling. */
139 static short *reg_old_renumber;
141 /* During reload_as_needed, element N contains the last pseudo regno reloaded
142 into hard register N. If that pseudo reg occupied more than one register,
143 reg_reloaded_contents points to that pseudo for each spill register in
144 use; all of these must remain set for an inheritance to occur. */
145 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
147 /* During reload_as_needed, element N contains the insn for which
148 hard register N was last used. Its contents are significant only
149 when reg_reloaded_valid is set for this register. */
150 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
152 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
153 static HARD_REG_SET reg_reloaded_valid;
154 /* Indicate if the register was dead at the end of the reload.
155 This is only valid if reg_reloaded_contents is set and valid. */
156 static HARD_REG_SET reg_reloaded_dead;
158 /* Indicate whether the register's current value is one that is not
159 safe to retain across a call, even for registers that are normally
161 static HARD_REG_SET reg_reloaded_call_part_clobbered;
163 /* Number of spill-regs so far; number of valid elements of spill_regs. */
166 /* In parallel with spill_regs, contains REG rtx's for those regs.
167 Holds the last rtx used for any given reg, or 0 if it has never
168 been used for spilling yet. This rtx is reused, provided it has
170 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
172 /* In parallel with spill_regs, contains nonzero for a spill reg
173 that was stored after the last time it was used.
174 The precise value is the insn generated to do the store. */
175 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
177 /* This is the register that was stored with spill_reg_store. This is a
178 copy of reload_out / reload_out_reg when the value was stored; if
179 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
180 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
182 /* This table is the inverse mapping of spill_regs:
183 indexed by hard reg number,
184 it contains the position of that reg in spill_regs,
185 or -1 for something that is not in spill_regs.
187 ?!? This is no longer accurate. */
188 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
190 /* This reg set indicates registers that can't be used as spill registers for
191 the currently processed insn. These are the hard registers which are live
192 during the insn, but not allocated to pseudos, as well as fixed
194 static HARD_REG_SET bad_spill_regs;
196 /* These are the hard registers that can't be used as spill register for any
197 insn. This includes registers used for user variables and registers that
198 we can't eliminate. A register that appears in this set also can't be used
199 to retry register allocation. */
200 static HARD_REG_SET bad_spill_regs_global;
202 /* Describes order of use of registers for reloading
203 of spilled pseudo-registers. `n_spills' is the number of
204 elements that are actually valid; new ones are added at the end.
206 Both spill_regs and spill_reg_order are used on two occasions:
207 once during find_reload_regs, where they keep track of the spill registers
208 for a single insn, but also during reload_as_needed where they show all
209 the registers ever used by reload. For the latter case, the information
210 is calculated during finish_spills. */
211 static short spill_regs[FIRST_PSEUDO_REGISTER];
213 /* This vector of reg sets indicates, for each pseudo, which hard registers
214 may not be used for retrying global allocation because the register was
215 formerly spilled from one of them. If we allowed reallocating a pseudo to
216 a register that it was already allocated to, reload might not
218 static HARD_REG_SET *pseudo_previous_regs;
220 /* This vector of reg sets indicates, for each pseudo, which hard
221 registers may not be used for retrying global allocation because they
222 are used as spill registers during one of the insns in which the
224 static HARD_REG_SET *pseudo_forbidden_regs;
226 /* All hard regs that have been used as spill registers for any insn are
227 marked in this set. */
228 static HARD_REG_SET used_spill_regs;
230 /* Index of last register assigned as a spill register. We allocate in
231 a round-robin fashion. */
232 static int last_spill_reg;
234 /* Nonzero if indirect addressing is supported on the machine; this means
235 that spilling (REG n) does not require reloading it into a register in
236 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
237 value indicates the level of indirect addressing supported, e.g., two
238 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
240 static char spill_indirect_levels;
242 /* Nonzero if indirect addressing is supported when the innermost MEM is
243 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
244 which these are valid is the same as spill_indirect_levels, above. */
245 char indirect_symref_ok;
247 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
248 char double_reg_address_ok;
250 /* Record the stack slot for each spilled hard register. */
251 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
253 /* Width allocated so far for that stack slot. */
254 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
256 /* Record which pseudos needed to be spilled. */
257 static regset_head spilled_pseudos;
259 /* Used for communication between order_regs_for_reload and count_pseudo.
260 Used to avoid counting one pseudo twice. */
261 static regset_head pseudos_counted;
263 /* First uid used by insns created by reload in this function.
264 Used in find_equiv_reg. */
265 int reload_first_uid;
267 /* Flag set by local-alloc or global-alloc if anything is live in
268 a call-clobbered reg across calls. */
269 int caller_save_needed;
271 /* Set to 1 while reload_as_needed is operating.
272 Required by some machines to handle any generated moves differently. */
273 int reload_in_progress = 0;
275 /* These arrays record the insn_code of insns that may be needed to
276 perform input and output reloads of special objects. They provide a
277 place to pass a scratch register. */
278 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
279 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
281 /* This obstack is used for allocation of rtl during register elimination.
282 The allocated storage can be freed once find_reloads has processed the
284 static struct obstack reload_obstack;
286 /* Points to the beginning of the reload_obstack. All insn_chain structures
287 are allocated first. */
288 static char *reload_startobj;
290 /* The point after all insn_chain structures. Used to quickly deallocate
291 memory allocated in copy_reloads during calculate_needs_all_insns. */
292 static char *reload_firstobj;
294 /* This points before all local rtl generated by register elimination.
295 Used to quickly free all memory after processing one insn. */
296 static char *reload_insn_firstobj;
298 /* List of insn_chain instructions, one for every insn that reload needs to
300 struct insn_chain *reload_insn_chain;
302 /* List of all insns needing reloads. */
303 static struct insn_chain *insns_need_reload;
305 /* This structure is used to record information about register eliminations.
306 Each array entry describes one possible way of eliminating a register
307 in favor of another. If there is more than one way of eliminating a
308 particular register, the most preferred should be specified first. */
312 int from; /* Register number to be eliminated. */
313 int to; /* Register number used as replacement. */
314 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
315 int can_eliminate; /* Nonzero if this elimination can be done. */
316 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
317 insns made by reload. */
318 HOST_WIDE_INT offset; /* Current offset between the two regs. */
319 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
320 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
321 rtx from_rtx; /* REG rtx for the register to be eliminated.
322 We cannot simply compare the number since
323 we might then spuriously replace a hard
324 register corresponding to a pseudo
325 assigned to the reg to be eliminated. */
326 rtx to_rtx; /* REG rtx for the replacement. */
329 static struct elim_table *reg_eliminate = 0;
331 /* This is an intermediate structure to initialize the table. It has
332 exactly the members provided by ELIMINABLE_REGS. */
333 static const struct elim_table_1
337 } reg_eliminate_1[] =
339 /* If a set of eliminable registers was specified, define the table from it.
340 Otherwise, default to the normal case of the frame pointer being
341 replaced by the stack pointer. */
343 #ifdef ELIMINABLE_REGS
346 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
349 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
351 /* Record the number of pending eliminations that have an offset not equal
352 to their initial offset. If nonzero, we use a new copy of each
353 replacement result in any insns encountered. */
354 int num_not_at_initial_offset;
356 /* Count the number of registers that we may be able to eliminate. */
357 static int num_eliminable;
358 /* And the number of registers that are equivalent to a constant that
359 can be eliminated to frame_pointer / arg_pointer + constant. */
360 static int num_eliminable_invariants;
362 /* For each label, we record the offset of each elimination. If we reach
363 a label by more than one path and an offset differs, we cannot do the
364 elimination. This information is indexed by the difference of the
365 number of the label and the first label number. We can't offset the
366 pointer itself as this can cause problems on machines with segmented
367 memory. The first table is an array of flags that records whether we
368 have yet encountered a label and the second table is an array of arrays,
369 one entry in the latter array for each elimination. */
371 static int first_label_num;
372 static char *offsets_known_at;
373 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
375 /* Number of labels in the current function. */
377 static int num_labels;
379 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
380 static void maybe_fix_stack_asms (void);
381 static void copy_reloads (struct insn_chain *);
382 static void calculate_needs_all_insns (int);
383 static int find_reg (struct insn_chain *, int);
384 static void find_reload_regs (struct insn_chain *);
385 static void select_reload_regs (void);
386 static void delete_caller_save_insns (void);
388 static void spill_failure (rtx, enum reg_class);
389 static void count_spilled_pseudo (int, int, int);
390 static void delete_dead_insn (rtx);
391 static void alter_reg (int, int);
392 static void set_label_offsets (rtx, rtx, int);
393 static void check_eliminable_occurrences (rtx);
394 static void elimination_effects (rtx, enum machine_mode);
395 static int eliminate_regs_in_insn (rtx, int);
396 static void update_eliminable_offsets (void);
397 static void mark_not_eliminable (rtx, rtx, void *);
398 static void set_initial_elim_offsets (void);
399 static bool verify_initial_elim_offsets (void);
400 static void set_initial_label_offsets (void);
401 static void set_offsets_for_label (rtx);
402 static void init_elim_table (void);
403 static void update_eliminables (HARD_REG_SET *);
404 static void spill_hard_reg (unsigned int, int);
405 static int finish_spills (int);
406 static void scan_paradoxical_subregs (rtx);
407 static void count_pseudo (int);
408 static void order_regs_for_reload (struct insn_chain *);
409 static void reload_as_needed (int);
410 static void forget_old_reloads_1 (rtx, rtx, void *);
411 static void forget_marked_reloads (regset);
412 static int reload_reg_class_lower (const void *, const void *);
413 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
415 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
417 static int reload_reg_free_p (unsigned int, int, enum reload_type);
418 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
420 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
422 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
423 static int allocate_reload_reg (struct insn_chain *, int, int);
424 static int conflicts_with_override (rtx);
425 static void failed_reload (rtx, int);
426 static int set_reload_reg (int, int);
427 static void choose_reload_regs_init (struct insn_chain *, rtx *);
428 static void choose_reload_regs (struct insn_chain *);
429 static void merge_assigned_reloads (rtx);
430 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
432 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
434 static void do_input_reload (struct insn_chain *, struct reload *, int);
435 static void do_output_reload (struct insn_chain *, struct reload *, int);
436 static bool inherit_piecemeal_p (int, int);
437 static void emit_reload_insns (struct insn_chain *);
438 static void delete_output_reload (rtx, int, int);
439 static void delete_address_reloads (rtx, rtx);
440 static void delete_address_reloads_1 (rtx, rtx, rtx);
441 static rtx inc_for_reload (rtx, rtx, rtx, int);
443 static void add_auto_inc_notes (rtx, rtx);
445 static void copy_eh_notes (rtx, rtx);
446 static int reloads_conflict (int, int);
447 static rtx gen_reload (rtx, rtx, int, enum reload_type);
448 static rtx emit_insn_if_valid_for_reload (rtx);
450 /* Initialize the reload pass once per compilation. */
457 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
458 Set spill_indirect_levels to the number of levels such addressing is
459 permitted, zero if it is not permitted at all. */
462 = gen_rtx_MEM (Pmode,
465 LAST_VIRTUAL_REGISTER + 1),
467 spill_indirect_levels = 0;
469 while (memory_address_p (QImode, tem))
471 spill_indirect_levels++;
472 tem = gen_rtx_MEM (Pmode, tem);
475 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
477 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
478 indirect_symref_ok = memory_address_p (QImode, tem);
480 /* See if reg+reg is a valid (and offsettable) address. */
482 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
484 tem = gen_rtx_PLUS (Pmode,
485 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
486 gen_rtx_REG (Pmode, i));
488 /* This way, we make sure that reg+reg is an offsettable address. */
489 tem = plus_constant (tem, 4);
491 if (memory_address_p (QImode, tem))
493 double_reg_address_ok = 1;
498 /* Initialize obstack for our rtl allocation. */
499 gcc_obstack_init (&reload_obstack);
500 reload_startobj = obstack_alloc (&reload_obstack, 0);
502 INIT_REG_SET (&spilled_pseudos);
503 INIT_REG_SET (&pseudos_counted);
506 /* List of insn chains that are currently unused. */
507 static struct insn_chain *unused_insn_chains = 0;
509 /* Allocate an empty insn_chain structure. */
511 new_insn_chain (void)
513 struct insn_chain *c;
515 if (unused_insn_chains == 0)
517 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
518 INIT_REG_SET (&c->live_throughout);
519 INIT_REG_SET (&c->dead_or_set);
523 c = unused_insn_chains;
524 unused_insn_chains = c->next;
526 c->is_caller_save_insn = 0;
527 c->need_operand_change = 0;
533 /* Small utility function to set all regs in hard reg set TO which are
534 allocated to pseudos in regset FROM. */
537 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
540 reg_set_iterator rsi;
542 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
544 int r = reg_renumber[regno];
549 /* reload_combine uses the information from
550 BASIC_BLOCK->global_live_at_start, which might still
551 contain registers that have not actually been allocated
552 since they have an equivalence. */
553 gcc_assert (reload_completed);
557 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)];
559 SET_HARD_REG_BIT (*to, r + nregs);
564 /* Replace all pseudos found in LOC with their corresponding
568 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
581 unsigned int regno = REGNO (x);
583 if (regno < FIRST_PSEUDO_REGISTER)
586 x = eliminate_regs (x, mem_mode, usage);
590 replace_pseudos_in (loc, mem_mode, usage);
594 if (reg_equiv_constant[regno])
595 *loc = reg_equiv_constant[regno];
596 else if (reg_equiv_mem[regno])
597 *loc = reg_equiv_mem[regno];
598 else if (reg_equiv_address[regno])
599 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
602 gcc_assert (!REG_P (regno_reg_rtx[regno])
603 || REGNO (regno_reg_rtx[regno]) != regno);
604 *loc = regno_reg_rtx[regno];
609 else if (code == MEM)
611 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
615 /* Process each of our operands recursively. */
616 fmt = GET_RTX_FORMAT (code);
617 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
619 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
620 else if (*fmt == 'E')
621 for (j = 0; j < XVECLEN (x, i); j++)
622 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
626 /* Global variables used by reload and its subroutines. */
628 /* Set during calculate_needs if an insn needs register elimination. */
629 static int something_needs_elimination;
630 /* Set during calculate_needs if an insn needs an operand changed. */
631 static int something_needs_operands_changed;
633 /* Nonzero means we couldn't get enough spill regs. */
636 /* Main entry point for the reload pass.
638 FIRST is the first insn of the function being compiled.
640 GLOBAL nonzero means we were called from global_alloc
641 and should attempt to reallocate any pseudoregs that we
642 displace from hard regs we will use for reloads.
643 If GLOBAL is zero, we do not have enough information to do that,
644 so any pseudo reg that is spilled must go to the stack.
646 Return value is nonzero if reload failed
647 and we must not do any more for this function. */
650 reload (rtx first, int global)
654 struct elim_table *ep;
657 /* Make sure even insns with volatile mem refs are recognizable. */
662 reload_firstobj = obstack_alloc (&reload_obstack, 0);
664 /* Make sure that the last insn in the chain
665 is not something that needs reloading. */
666 emit_note (NOTE_INSN_DELETED);
668 /* Enable find_equiv_reg to distinguish insns made by reload. */
669 reload_first_uid = get_max_uid ();
671 #ifdef SECONDARY_MEMORY_NEEDED
672 /* Initialize the secondary memory table. */
673 clear_secondary_mem ();
676 /* We don't have a stack slot for any spill reg yet. */
677 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
678 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
680 /* Initialize the save area information for caller-save, in case some
684 /* Compute which hard registers are now in use
685 as homes for pseudo registers.
686 This is done here rather than (eg) in global_alloc
687 because this point is reached even if not optimizing. */
688 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
691 /* A function that receives a nonlocal goto must save all call-saved
693 if (current_function_has_nonlocal_label)
694 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
695 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
696 regs_ever_live[i] = 1;
698 /* Find all the pseudo registers that didn't get hard regs
699 but do have known equivalent constants or memory slots.
700 These include parameters (known equivalent to parameter slots)
701 and cse'd or loop-moved constant memory addresses.
703 Record constant equivalents in reg_equiv_constant
704 so they will be substituted by find_reloads.
705 Record memory equivalents in reg_mem_equiv so they can
706 be substituted eventually by altering the REG-rtx's. */
708 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
709 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
710 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
711 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
712 reg_equiv_address = XCNEWVEC (rtx, max_regno);
713 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
714 reg_old_renumber = XCNEWVEC (short, max_regno);
715 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
716 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
717 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
719 CLEAR_HARD_REG_SET (bad_spill_regs_global);
721 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
722 to. Also find all paradoxical subregs and find largest such for
725 num_eliminable_invariants = 0;
726 for (insn = first; insn; insn = NEXT_INSN (insn))
728 rtx set = single_set (insn);
730 /* We may introduce USEs that we want to remove at the end, so
731 we'll mark them with QImode. Make sure there are no
732 previously-marked insns left by say regmove. */
733 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
734 && GET_MODE (insn) != VOIDmode)
735 PUT_MODE (insn, VOIDmode);
738 scan_paradoxical_subregs (PATTERN (insn));
740 if (set != 0 && REG_P (SET_DEST (set)))
742 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
748 i = REGNO (SET_DEST (set));
751 if (i <= LAST_VIRTUAL_REGISTER)
754 if (! function_invariant_p (x)
756 /* A function invariant is often CONSTANT_P but may
757 include a register. We promise to only pass
758 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
760 && LEGITIMATE_PIC_OPERAND_P (x)))
762 /* It can happen that a REG_EQUIV note contains a MEM
763 that is not a legitimate memory operand. As later
764 stages of reload assume that all addresses found
765 in the reg_equiv_* arrays were originally legitimate,
766 we ignore such REG_EQUIV notes. */
767 if (memory_operand (x, VOIDmode))
769 /* Always unshare the equivalence, so we can
770 substitute into this insn without touching the
772 reg_equiv_memory_loc[i] = copy_rtx (x);
774 else if (function_invariant_p (x))
776 if (GET_CODE (x) == PLUS)
778 /* This is PLUS of frame pointer and a constant,
779 and might be shared. Unshare it. */
780 reg_equiv_invariant[i] = copy_rtx (x);
781 num_eliminable_invariants++;
783 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
785 reg_equiv_invariant[i] = x;
786 num_eliminable_invariants++;
788 else if (LEGITIMATE_CONSTANT_P (x))
789 reg_equiv_constant[i] = x;
792 reg_equiv_memory_loc[i]
793 = force_const_mem (GET_MODE (SET_DEST (set)), x);
794 if (! reg_equiv_memory_loc[i])
795 reg_equiv_init[i] = NULL_RTX;
800 reg_equiv_init[i] = NULL_RTX;
805 reg_equiv_init[i] = NULL_RTX;
810 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
811 if (reg_equiv_init[i])
813 fprintf (dump_file, "init_insns for %u: ", i);
814 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
815 fprintf (dump_file, "\n");
820 first_label_num = get_first_label_num ();
821 num_labels = max_label_num () - first_label_num;
823 /* Allocate the tables used to store offset information at labels. */
824 /* We used to use alloca here, but the size of what it would try to
825 allocate would occasionally cause it to exceed the stack limit and
826 cause a core dump. */
827 offsets_known_at = XNEWVEC (char, num_labels);
828 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
830 /* Alter each pseudo-reg rtx to contain its hard reg number.
831 Assign stack slots to the pseudos that lack hard regs or equivalents.
832 Do not touch virtual registers. */
834 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
837 /* If we have some registers we think can be eliminated, scan all insns to
838 see if there is an insn that sets one of these registers to something
839 other than itself plus a constant. If so, the register cannot be
840 eliminated. Doing this scan here eliminates an extra pass through the
841 main reload loop in the most common case where register elimination
843 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
845 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
847 maybe_fix_stack_asms ();
849 insns_need_reload = 0;
850 something_needs_elimination = 0;
852 /* Initialize to -1, which means take the first spill register. */
855 /* Spill any hard regs that we know we can't eliminate. */
856 CLEAR_HARD_REG_SET (used_spill_regs);
857 /* There can be multiple ways to eliminate a register;
858 they should be listed adjacently.
859 Elimination for any register fails only if all possible ways fail. */
860 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
863 int can_eliminate = 0;
866 can_eliminate |= ep->can_eliminate;
869 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
871 spill_hard_reg (from, 1);
874 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
875 if (frame_pointer_needed)
876 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
878 finish_spills (global);
880 /* From now on, we may need to generate moves differently. We may also
881 allow modifications of insns which cause them to not be recognized.
882 Any such modifications will be cleaned up during reload itself. */
883 reload_in_progress = 1;
885 /* This loop scans the entire function each go-round
886 and repeats until one repetition spills no additional hard regs. */
889 int something_changed;
892 HOST_WIDE_INT starting_frame_size;
894 /* Round size of stack frame to stack_alignment_needed. This must be done
895 here because the stack size may be a part of the offset computation
896 for register elimination, and there might have been new stack slots
897 created in the last iteration of this loop. */
898 if (cfun->stack_alignment_needed)
899 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
901 starting_frame_size = get_frame_size ();
903 set_initial_elim_offsets ();
904 set_initial_label_offsets ();
906 /* For each pseudo register that has an equivalent location defined,
907 try to eliminate any eliminable registers (such as the frame pointer)
908 assuming initial offsets for the replacement register, which
911 If the resulting location is directly addressable, substitute
912 the MEM we just got directly for the old REG.
914 If it is not addressable but is a constant or the sum of a hard reg
915 and constant, it is probably not addressable because the constant is
916 out of range, in that case record the address; we will generate
917 hairy code to compute the address in a register each time it is
918 needed. Similarly if it is a hard register, but one that is not
919 valid as an address register.
921 If the location is not addressable, but does not have one of the
922 above forms, assign a stack slot. We have to do this to avoid the
923 potential of producing lots of reloads if, e.g., a location involves
924 a pseudo that didn't get a hard register and has an equivalent memory
925 location that also involves a pseudo that didn't get a hard register.
927 Perhaps at some point we will improve reload_when_needed handling
928 so this problem goes away. But that's very hairy. */
930 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
931 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
933 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
935 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
937 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
938 else if (CONSTANT_P (XEXP (x, 0))
939 || (REG_P (XEXP (x, 0))
940 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
941 || (GET_CODE (XEXP (x, 0)) == PLUS
942 && REG_P (XEXP (XEXP (x, 0), 0))
943 && (REGNO (XEXP (XEXP (x, 0), 0))
944 < FIRST_PSEUDO_REGISTER)
945 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
946 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
949 /* Make a new stack slot. Then indicate that something
950 changed so we go back and recompute offsets for
951 eliminable registers because the allocation of memory
952 below might change some offset. reg_equiv_{mem,address}
953 will be set up for this pseudo on the next pass around
955 reg_equiv_memory_loc[i] = 0;
956 reg_equiv_init[i] = 0;
961 if (caller_save_needed)
964 /* If we allocated another stack slot, redo elimination bookkeeping. */
965 if (starting_frame_size != get_frame_size ())
968 if (caller_save_needed)
970 save_call_clobbered_regs ();
971 /* That might have allocated new insn_chain structures. */
972 reload_firstobj = obstack_alloc (&reload_obstack, 0);
975 calculate_needs_all_insns (global);
977 CLEAR_REG_SET (&spilled_pseudos);
980 something_changed = 0;
982 /* If we allocated any new memory locations, make another pass
983 since it might have changed elimination offsets. */
984 if (starting_frame_size != get_frame_size ())
985 something_changed = 1;
987 /* Even if the frame size remained the same, we might still have
988 changed elimination offsets, e.g. if find_reloads called
989 force_const_mem requiring the back end to allocate a constant
990 pool base register that needs to be saved on the stack. */
991 else if (!verify_initial_elim_offsets ())
992 something_changed = 1;
995 HARD_REG_SET to_spill;
996 CLEAR_HARD_REG_SET (to_spill);
997 update_eliminables (&to_spill);
998 AND_COMPL_HARD_REG_SET(used_spill_regs, to_spill);
1000 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1001 if (TEST_HARD_REG_BIT (to_spill, i))
1003 spill_hard_reg (i, 1);
1006 /* Regardless of the state of spills, if we previously had
1007 a register that we thought we could eliminate, but now can
1008 not eliminate, we must run another pass.
1010 Consider pseudos which have an entry in reg_equiv_* which
1011 reference an eliminable register. We must make another pass
1012 to update reg_equiv_* so that we do not substitute in the
1013 old value from when we thought the elimination could be
1015 something_changed = 1;
1019 select_reload_regs ();
1023 if (insns_need_reload != 0 || did_spill)
1024 something_changed |= finish_spills (global);
1026 if (! something_changed)
1029 if (caller_save_needed)
1030 delete_caller_save_insns ();
1032 obstack_free (&reload_obstack, reload_firstobj);
1035 /* If global-alloc was run, notify it of any register eliminations we have
1038 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1039 if (ep->can_eliminate)
1040 mark_elimination (ep->from, ep->to);
1042 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1043 If that insn didn't set the register (i.e., it copied the register to
1044 memory), just delete that insn instead of the equivalencing insn plus
1045 anything now dead. If we call delete_dead_insn on that insn, we may
1046 delete the insn that actually sets the register if the register dies
1047 there and that is incorrect. */
1049 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1051 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1054 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1056 rtx equiv_insn = XEXP (list, 0);
1058 /* If we already deleted the insn or if it may trap, we can't
1059 delete it. The latter case shouldn't happen, but can
1060 if an insn has a variable address, gets a REG_EH_REGION
1061 note added to it, and then gets converted into a load
1062 from a constant address. */
1063 if (NOTE_P (equiv_insn)
1064 || can_throw_internal (equiv_insn))
1066 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1067 delete_dead_insn (equiv_insn);
1069 SET_INSN_DELETED (equiv_insn);
1074 /* Use the reload registers where necessary
1075 by generating move instructions to move the must-be-register
1076 values into or out of the reload registers. */
1078 if (insns_need_reload != 0 || something_needs_elimination
1079 || something_needs_operands_changed)
1081 HOST_WIDE_INT old_frame_size = get_frame_size ();
1083 reload_as_needed (global);
1085 gcc_assert (old_frame_size == get_frame_size ());
1087 gcc_assert (verify_initial_elim_offsets ());
1090 /* If we were able to eliminate the frame pointer, show that it is no
1091 longer live at the start of any basic block. If it ls live by
1092 virtue of being in a pseudo, that pseudo will be marked live
1093 and hence the frame pointer will be known to be live via that
1096 if (! frame_pointer_needed)
1098 CLEAR_REGNO_REG_SET (bb->il.rtl->global_live_at_start,
1099 HARD_FRAME_POINTER_REGNUM);
1101 /* Come here (with failure set nonzero) if we can't get enough spill
1105 CLEAR_REG_SET (&spilled_pseudos);
1106 reload_in_progress = 0;
1108 /* Now eliminate all pseudo regs by modifying them into
1109 their equivalent memory references.
1110 The REG-rtx's for the pseudos are modified in place,
1111 so all insns that used to refer to them now refer to memory.
1113 For a reg that has a reg_equiv_address, all those insns
1114 were changed by reloading so that no insns refer to it any longer;
1115 but the DECL_RTL of a variable decl may refer to it,
1116 and if so this causes the debugging info to mention the variable. */
1118 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1122 if (reg_equiv_mem[i])
1123 addr = XEXP (reg_equiv_mem[i], 0);
1125 if (reg_equiv_address[i])
1126 addr = reg_equiv_address[i];
1130 if (reg_renumber[i] < 0)
1132 rtx reg = regno_reg_rtx[i];
1134 REG_USERVAR_P (reg) = 0;
1135 PUT_CODE (reg, MEM);
1136 XEXP (reg, 0) = addr;
1137 if (reg_equiv_memory_loc[i])
1138 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1141 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1142 MEM_ATTRS (reg) = 0;
1144 MEM_NOTRAP_P (reg) = 1;
1146 else if (reg_equiv_mem[i])
1147 XEXP (reg_equiv_mem[i], 0) = addr;
1151 /* We must set reload_completed now since the cleanup_subreg_operands call
1152 below will re-recognize each insn and reload may have generated insns
1153 which are only valid during and after reload. */
1154 reload_completed = 1;
1156 /* Make a pass over all the insns and delete all USEs which we inserted
1157 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1158 notes. Delete all CLOBBER insns, except those that refer to the return
1159 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1160 from misarranging variable-array code, and simplify (subreg (reg))
1161 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1162 are no longer useful or accurate. Strip and regenerate REG_INC notes
1163 that may have been moved around. */
1165 for (insn = first; insn; insn = NEXT_INSN (insn))
1171 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1172 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1174 if ((GET_CODE (PATTERN (insn)) == USE
1175 /* We mark with QImode USEs introduced by reload itself. */
1176 && (GET_MODE (insn) == QImode
1177 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1178 || (GET_CODE (PATTERN (insn)) == CLOBBER
1179 && (!MEM_P (XEXP (PATTERN (insn), 0))
1180 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1181 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1182 && XEXP (XEXP (PATTERN (insn), 0), 0)
1183 != stack_pointer_rtx))
1184 && (!REG_P (XEXP (PATTERN (insn), 0))
1185 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1191 /* Some CLOBBERs may survive until here and still reference unassigned
1192 pseudos with const equivalent, which may in turn cause ICE in later
1193 passes if the reference remains in place. */
1194 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1195 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1196 VOIDmode, PATTERN (insn));
1198 /* Discard obvious no-ops, even without -O. This optimization
1199 is fast and doesn't interfere with debugging. */
1200 if (NONJUMP_INSN_P (insn)
1201 && GET_CODE (PATTERN (insn)) == SET
1202 && REG_P (SET_SRC (PATTERN (insn)))
1203 && REG_P (SET_DEST (PATTERN (insn)))
1204 && (REGNO (SET_SRC (PATTERN (insn)))
1205 == REGNO (SET_DEST (PATTERN (insn)))))
1211 pnote = ®_NOTES (insn);
1214 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1215 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1216 || REG_NOTE_KIND (*pnote) == REG_INC
1217 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1218 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1219 *pnote = XEXP (*pnote, 1);
1221 pnote = &XEXP (*pnote, 1);
1225 add_auto_inc_notes (insn, PATTERN (insn));
1228 /* And simplify (subreg (reg)) if it appears as an operand. */
1229 cleanup_subreg_operands (insn);
1232 /* If we are doing stack checking, give a warning if this function's
1233 frame size is larger than we expect. */
1234 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1236 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1237 static int verbose_warned = 0;
1239 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1240 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1241 size += UNITS_PER_WORD;
1243 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1245 warning (0, "frame size too large for reliable stack checking");
1246 if (! verbose_warned)
1248 warning (0, "try reducing the number of local variables");
1254 /* Indicate that we no longer have known memory locations or constants. */
1255 if (reg_equiv_constant)
1256 free (reg_equiv_constant);
1257 if (reg_equiv_invariant)
1258 free (reg_equiv_invariant);
1259 reg_equiv_constant = 0;
1260 reg_equiv_invariant = 0;
1261 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
1262 reg_equiv_memory_loc = 0;
1264 if (offsets_known_at)
1265 free (offsets_known_at);
1269 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1270 if (reg_equiv_alt_mem_list[i])
1271 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
1272 free (reg_equiv_alt_mem_list);
1274 free (reg_equiv_mem);
1276 free (reg_equiv_address);
1277 free (reg_max_ref_width);
1278 free (reg_old_renumber);
1279 free (pseudo_previous_regs);
1280 free (pseudo_forbidden_regs);
1282 CLEAR_HARD_REG_SET (used_spill_regs);
1283 for (i = 0; i < n_spills; i++)
1284 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1286 /* Free all the insn_chain structures at once. */
1287 obstack_free (&reload_obstack, reload_startobj);
1288 unused_insn_chains = 0;
1289 fixup_abnormal_edges ();
1291 /* Replacing pseudos with their memory equivalents might have
1292 created shared rtx. Subsequent passes would get confused
1293 by this, so unshare everything here. */
1294 unshare_all_rtl_again (first);
1296 #ifdef STACK_BOUNDARY
1297 /* init_emit has set the alignment of the hard frame pointer
1298 to STACK_BOUNDARY. It is very likely no longer valid if
1299 the hard frame pointer was used for register allocation. */
1300 if (!frame_pointer_needed)
1301 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1307 /* Yet another special case. Unfortunately, reg-stack forces people to
1308 write incorrect clobbers in asm statements. These clobbers must not
1309 cause the register to appear in bad_spill_regs, otherwise we'll call
1310 fatal_insn later. We clear the corresponding regnos in the live
1311 register sets to avoid this.
1312 The whole thing is rather sick, I'm afraid. */
1315 maybe_fix_stack_asms (void)
1318 const char *constraints[MAX_RECOG_OPERANDS];
1319 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1320 struct insn_chain *chain;
1322 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1325 HARD_REG_SET clobbered, allowed;
1328 if (! INSN_P (chain->insn)
1329 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1331 pat = PATTERN (chain->insn);
1332 if (GET_CODE (pat) != PARALLEL)
1335 CLEAR_HARD_REG_SET (clobbered);
1336 CLEAR_HARD_REG_SET (allowed);
1338 /* First, make a mask of all stack regs that are clobbered. */
1339 for (i = 0; i < XVECLEN (pat, 0); i++)
1341 rtx t = XVECEXP (pat, 0, i);
1342 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1343 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1346 /* Get the operand values and constraints out of the insn. */
1347 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1348 constraints, operand_mode);
1350 /* For every operand, see what registers are allowed. */
1351 for (i = 0; i < noperands; i++)
1353 const char *p = constraints[i];
1354 /* For every alternative, we compute the class of registers allowed
1355 for reloading in CLS, and merge its contents into the reg set
1357 int cls = (int) NO_REGS;
1363 if (c == '\0' || c == ',' || c == '#')
1365 /* End of one alternative - mark the regs in the current
1366 class, and reset the class. */
1367 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1373 } while (c != '\0' && c != ',');
1381 case '=': case '+': case '*': case '%': case '?': case '!':
1382 case '0': case '1': case '2': case '3': case '4': case 'm':
1383 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1384 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1385 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1390 cls = (int) reg_class_subunion[cls]
1391 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1396 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1400 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1401 cls = (int) reg_class_subunion[cls]
1402 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1404 cls = (int) reg_class_subunion[cls]
1405 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1407 p += CONSTRAINT_LEN (c, p);
1410 /* Those of the registers which are clobbered, but allowed by the
1411 constraints, must be usable as reload registers. So clear them
1412 out of the life information. */
1413 AND_HARD_REG_SET (allowed, clobbered);
1414 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1415 if (TEST_HARD_REG_BIT (allowed, i))
1417 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1418 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1425 /* Copy the global variables n_reloads and rld into the corresponding elts
1428 copy_reloads (struct insn_chain *chain)
1430 chain->n_reloads = n_reloads;
1431 chain->rld = obstack_alloc (&reload_obstack,
1432 n_reloads * sizeof (struct reload));
1433 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1434 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1437 /* Walk the chain of insns, and determine for each whether it needs reloads
1438 and/or eliminations. Build the corresponding insns_need_reload list, and
1439 set something_needs_elimination as appropriate. */
1441 calculate_needs_all_insns (int global)
1443 struct insn_chain **pprev_reload = &insns_need_reload;
1444 struct insn_chain *chain, *next = 0;
1446 something_needs_elimination = 0;
1448 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1449 for (chain = reload_insn_chain; chain != 0; chain = next)
1451 rtx insn = chain->insn;
1455 /* Clear out the shortcuts. */
1456 chain->n_reloads = 0;
1457 chain->need_elim = 0;
1458 chain->need_reload = 0;
1459 chain->need_operand_change = 0;
1461 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1462 include REG_LABEL), we need to see what effects this has on the
1463 known offsets at labels. */
1465 if (LABEL_P (insn) || JUMP_P (insn)
1466 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1467 set_label_offsets (insn, insn, 0);
1471 rtx old_body = PATTERN (insn);
1472 int old_code = INSN_CODE (insn);
1473 rtx old_notes = REG_NOTES (insn);
1474 int did_elimination = 0;
1475 int operands_changed = 0;
1476 rtx set = single_set (insn);
1478 /* Skip insns that only set an equivalence. */
1479 if (set && REG_P (SET_DEST (set))
1480 && reg_renumber[REGNO (SET_DEST (set))] < 0
1481 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1482 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1483 && reg_equiv_init[REGNO (SET_DEST (set))])
1486 /* If needed, eliminate any eliminable registers. */
1487 if (num_eliminable || num_eliminable_invariants)
1488 did_elimination = eliminate_regs_in_insn (insn, 0);
1490 /* Analyze the instruction. */
1491 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1492 global, spill_reg_order);
1494 /* If a no-op set needs more than one reload, this is likely
1495 to be something that needs input address reloads. We
1496 can't get rid of this cleanly later, and it is of no use
1497 anyway, so discard it now.
1498 We only do this when expensive_optimizations is enabled,
1499 since this complements reload inheritance / output
1500 reload deletion, and it can make debugging harder. */
1501 if (flag_expensive_optimizations && n_reloads > 1)
1503 rtx set = single_set (insn);
1505 && SET_SRC (set) == SET_DEST (set)
1506 && REG_P (SET_SRC (set))
1507 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1510 /* Delete it from the reload chain. */
1512 chain->prev->next = next;
1514 reload_insn_chain = next;
1516 next->prev = chain->prev;
1517 chain->next = unused_insn_chains;
1518 unused_insn_chains = chain;
1523 update_eliminable_offsets ();
1525 /* Remember for later shortcuts which insns had any reloads or
1526 register eliminations. */
1527 chain->need_elim = did_elimination;
1528 chain->need_reload = n_reloads > 0;
1529 chain->need_operand_change = operands_changed;
1531 /* Discard any register replacements done. */
1532 if (did_elimination)
1534 obstack_free (&reload_obstack, reload_insn_firstobj);
1535 PATTERN (insn) = old_body;
1536 INSN_CODE (insn) = old_code;
1537 REG_NOTES (insn) = old_notes;
1538 something_needs_elimination = 1;
1541 something_needs_operands_changed |= operands_changed;
1545 copy_reloads (chain);
1546 *pprev_reload = chain;
1547 pprev_reload = &chain->next_need_reload;
1554 /* Comparison function for qsort to decide which of two reloads
1555 should be handled first. *P1 and *P2 are the reload numbers. */
1558 reload_reg_class_lower (const void *r1p, const void *r2p)
1560 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1563 /* Consider required reloads before optional ones. */
1564 t = rld[r1].optional - rld[r2].optional;
1568 /* Count all solitary classes before non-solitary ones. */
1569 t = ((reg_class_size[(int) rld[r2].class] == 1)
1570 - (reg_class_size[(int) rld[r1].class] == 1));
1574 /* Aside from solitaires, consider all multi-reg groups first. */
1575 t = rld[r2].nregs - rld[r1].nregs;
1579 /* Consider reloads in order of increasing reg-class number. */
1580 t = (int) rld[r1].class - (int) rld[r2].class;
1584 /* If reloads are equally urgent, sort by reload number,
1585 so that the results of qsort leave nothing to chance. */
1589 /* The cost of spilling each hard reg. */
1590 static int spill_cost[FIRST_PSEUDO_REGISTER];
1592 /* When spilling multiple hard registers, we use SPILL_COST for the first
1593 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1594 only the first hard reg for a multi-reg pseudo. */
1595 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1597 /* Update the spill cost arrays, considering that pseudo REG is live. */
1600 count_pseudo (int reg)
1602 int freq = REG_FREQ (reg);
1603 int r = reg_renumber[reg];
1606 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1607 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1610 SET_REGNO_REG_SET (&pseudos_counted, reg);
1612 gcc_assert (r >= 0);
1614 spill_add_cost[r] += freq;
1616 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1618 spill_cost[r + nregs] += freq;
1621 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1622 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1625 order_regs_for_reload (struct insn_chain *chain)
1628 HARD_REG_SET used_by_pseudos;
1629 HARD_REG_SET used_by_pseudos2;
1630 reg_set_iterator rsi;
1632 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1634 memset (spill_cost, 0, sizeof spill_cost);
1635 memset (spill_add_cost, 0, sizeof spill_add_cost);
1637 /* Count number of uses of each hard reg by pseudo regs allocated to it
1638 and then order them by decreasing use. First exclude hard registers
1639 that are live in or across this insn. */
1641 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1642 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1643 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1644 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1646 /* Now find out which pseudos are allocated to it, and update
1648 CLEAR_REG_SET (&pseudos_counted);
1650 EXECUTE_IF_SET_IN_REG_SET
1651 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1655 EXECUTE_IF_SET_IN_REG_SET
1656 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1660 CLEAR_REG_SET (&pseudos_counted);
1663 /* Vector of reload-numbers showing the order in which the reloads should
1665 static short reload_order[MAX_RELOADS];
1667 /* This is used to keep track of the spill regs used in one insn. */
1668 static HARD_REG_SET used_spill_regs_local;
1670 /* We decided to spill hard register SPILLED, which has a size of
1671 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1672 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1673 update SPILL_COST/SPILL_ADD_COST. */
1676 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1678 int r = reg_renumber[reg];
1679 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1681 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1682 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1685 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1687 spill_add_cost[r] -= REG_FREQ (reg);
1689 spill_cost[r + nregs] -= REG_FREQ (reg);
1692 /* Find reload register to use for reload number ORDER. */
1695 find_reg (struct insn_chain *chain, int order)
1697 int rnum = reload_order[order];
1698 struct reload *rl = rld + rnum;
1699 int best_cost = INT_MAX;
1703 HARD_REG_SET not_usable;
1704 HARD_REG_SET used_by_other_reload;
1705 reg_set_iterator rsi;
1707 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1708 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1709 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1711 CLEAR_HARD_REG_SET (used_by_other_reload);
1712 for (k = 0; k < order; k++)
1714 int other = reload_order[k];
1716 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1717 for (j = 0; j < rld[other].nregs; j++)
1718 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1721 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1723 unsigned int regno = i;
1725 if (! TEST_HARD_REG_BIT (not_usable, regno)
1726 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1727 && HARD_REGNO_MODE_OK (regno, rl->mode))
1729 int this_cost = spill_cost[regno];
1731 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1733 for (j = 1; j < this_nregs; j++)
1735 this_cost += spill_add_cost[regno + j];
1736 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1737 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1742 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1744 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1746 if (this_cost < best_cost
1747 /* Among registers with equal cost, prefer caller-saved ones, or
1748 use REG_ALLOC_ORDER if it is defined. */
1749 || (this_cost == best_cost
1750 #ifdef REG_ALLOC_ORDER
1751 && (inv_reg_alloc_order[regno]
1752 < inv_reg_alloc_order[best_reg])
1754 && call_used_regs[regno]
1755 && ! call_used_regs[best_reg]
1760 best_cost = this_cost;
1768 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1770 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1771 rl->regno = best_reg;
1773 EXECUTE_IF_SET_IN_REG_SET
1774 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1776 count_spilled_pseudo (best_reg, rl->nregs, j);
1779 EXECUTE_IF_SET_IN_REG_SET
1780 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1782 count_spilled_pseudo (best_reg, rl->nregs, j);
1785 for (i = 0; i < rl->nregs; i++)
1787 gcc_assert (spill_cost[best_reg + i] == 0);
1788 gcc_assert (spill_add_cost[best_reg + i] == 0);
1789 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1794 /* Find more reload regs to satisfy the remaining need of an insn, which
1796 Do it by ascending class number, since otherwise a reg
1797 might be spilled for a big class and might fail to count
1798 for a smaller class even though it belongs to that class. */
1801 find_reload_regs (struct insn_chain *chain)
1805 /* In order to be certain of getting the registers we need,
1806 we must sort the reloads into order of increasing register class.
1807 Then our grabbing of reload registers will parallel the process
1808 that provided the reload registers. */
1809 for (i = 0; i < chain->n_reloads; i++)
1811 /* Show whether this reload already has a hard reg. */
1812 if (chain->rld[i].reg_rtx)
1814 int regno = REGNO (chain->rld[i].reg_rtx);
1815 chain->rld[i].regno = regno;
1817 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1820 chain->rld[i].regno = -1;
1821 reload_order[i] = i;
1824 n_reloads = chain->n_reloads;
1825 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1827 CLEAR_HARD_REG_SET (used_spill_regs_local);
1830 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1832 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1834 /* Compute the order of preference for hard registers to spill. */
1836 order_regs_for_reload (chain);
1838 for (i = 0; i < n_reloads; i++)
1840 int r = reload_order[i];
1842 /* Ignore reloads that got marked inoperative. */
1843 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1844 && ! rld[r].optional
1845 && rld[r].regno == -1)
1846 if (! find_reg (chain, i))
1849 fprintf(dump_file, "reload failure for reload %d\n", r);
1850 spill_failure (chain->insn, rld[r].class);
1856 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1857 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1859 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1863 select_reload_regs (void)
1865 struct insn_chain *chain;
1867 /* Try to satisfy the needs for each insn. */
1868 for (chain = insns_need_reload; chain != 0;
1869 chain = chain->next_need_reload)
1870 find_reload_regs (chain);
1873 /* Delete all insns that were inserted by emit_caller_save_insns during
1876 delete_caller_save_insns (void)
1878 struct insn_chain *c = reload_insn_chain;
1882 while (c != 0 && c->is_caller_save_insn)
1884 struct insn_chain *next = c->next;
1887 if (c == reload_insn_chain)
1888 reload_insn_chain = next;
1892 next->prev = c->prev;
1894 c->prev->next = next;
1895 c->next = unused_insn_chains;
1896 unused_insn_chains = c;
1904 /* Handle the failure to find a register to spill.
1905 INSN should be one of the insns which needed this particular spill reg. */
1908 spill_failure (rtx insn, enum reg_class class)
1910 if (asm_noperands (PATTERN (insn)) >= 0)
1911 error_for_asm (insn, "can't find a register in class %qs while "
1912 "reloading %<asm%>",
1913 reg_class_names[class]);
1916 error ("unable to find a register to spill in class %qs",
1917 reg_class_names[class]);
1921 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
1922 debug_reload_to_stream (dump_file);
1924 fatal_insn ("this is the insn:", insn);
1928 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1929 data that is dead in INSN. */
1932 delete_dead_insn (rtx insn)
1934 rtx prev = prev_real_insn (insn);
1937 /* If the previous insn sets a register that dies in our insn, delete it
1939 if (prev && GET_CODE (PATTERN (prev)) == SET
1940 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
1941 && reg_mentioned_p (prev_dest, PATTERN (insn))
1942 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1943 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1944 delete_dead_insn (prev);
1946 SET_INSN_DELETED (insn);
1949 /* Modify the home of pseudo-reg I.
1950 The new home is present in reg_renumber[I].
1952 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1953 or it may be -1, meaning there is none or it is not relevant.
1954 This is used so that all pseudos spilled from a given hard reg
1955 can share one stack slot. */
1958 alter_reg (int i, int from_reg)
1960 /* When outputting an inline function, this can happen
1961 for a reg that isn't actually used. */
1962 if (regno_reg_rtx[i] == 0)
1965 /* If the reg got changed to a MEM at rtl-generation time,
1967 if (!REG_P (regno_reg_rtx[i]))
1970 /* Modify the reg-rtx to contain the new hard reg
1971 number or else to contain its pseudo reg number. */
1972 REGNO (regno_reg_rtx[i])
1973 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1975 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1976 allocate a stack slot for it. */
1978 if (reg_renumber[i] < 0
1979 && REG_N_REFS (i) > 0
1980 && reg_equiv_constant[i] == 0
1981 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
1982 && reg_equiv_memory_loc[i] == 0)
1985 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1986 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1989 /* Each pseudo reg has an inherent size which comes from its own mode,
1990 and a total size which provides room for paradoxical subregs
1991 which refer to the pseudo reg in wider modes.
1993 We can use a slot already allocated if it provides both
1994 enough inherent space and enough total space.
1995 Otherwise, we allocate a new slot, making sure that it has no less
1996 inherent space, and no less total space, then the previous slot. */
1999 /* No known place to spill from => no slot to reuse. */
2000 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
2001 inherent_size == total_size ? 0 : -1);
2002 if (BYTES_BIG_ENDIAN)
2003 /* Cancel the big-endian correction done in assign_stack_local.
2004 Get the address of the beginning of the slot.
2005 This is so we can do a big-endian correction unconditionally
2007 adjust = inherent_size - total_size;
2009 /* Nothing can alias this slot except this pseudo. */
2010 set_mem_alias_set (x, new_alias_set ());
2013 /* Reuse a stack slot if possible. */
2014 else if (spill_stack_slot[from_reg] != 0
2015 && spill_stack_slot_width[from_reg] >= total_size
2016 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2018 x = spill_stack_slot[from_reg];
2020 /* Allocate a bigger slot. */
2023 /* Compute maximum size needed, both for inherent size
2024 and for total size. */
2025 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2028 if (spill_stack_slot[from_reg])
2030 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2032 mode = GET_MODE (spill_stack_slot[from_reg]);
2033 if (spill_stack_slot_width[from_reg] > total_size)
2034 total_size = spill_stack_slot_width[from_reg];
2037 /* Make a slot with that size. */
2038 x = assign_stack_local (mode, total_size,
2039 inherent_size == total_size ? 0 : -1);
2042 /* All pseudos mapped to this slot can alias each other. */
2043 if (spill_stack_slot[from_reg])
2044 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2046 set_mem_alias_set (x, new_alias_set ());
2048 if (BYTES_BIG_ENDIAN)
2050 /* Cancel the big-endian correction done in assign_stack_local.
2051 Get the address of the beginning of the slot.
2052 This is so we can do a big-endian correction unconditionally
2054 adjust = GET_MODE_SIZE (mode) - total_size;
2057 = adjust_address_nv (x, mode_for_size (total_size
2063 spill_stack_slot[from_reg] = stack_slot;
2064 spill_stack_slot_width[from_reg] = total_size;
2067 /* On a big endian machine, the "address" of the slot
2068 is the address of the low part that fits its inherent mode. */
2069 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2070 adjust += (total_size - inherent_size);
2072 /* If we have any adjustment to make, or if the stack slot is the
2073 wrong mode, make a new stack slot. */
2074 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2076 /* If we have a decl for the original register, set it for the
2077 memory. If this is a shared MEM, make a copy. */
2078 if (REG_EXPR (regno_reg_rtx[i])
2079 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2081 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2083 /* We can do this only for the DECLs home pseudo, not for
2084 any copies of it, since otherwise when the stack slot
2085 is reused, nonoverlapping_memrefs_p might think they
2087 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2089 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2092 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2096 /* Save the stack slot for later. */
2097 reg_equiv_memory_loc[i] = x;
2101 /* Mark the slots in regs_ever_live for the hard regs
2102 used by pseudo-reg number REGNO. */
2105 mark_home_live (int regno)
2109 i = reg_renumber[regno];
2112 lim = i + hard_regno_nregs[i][PSEUDO_REGNO_MODE (regno)];
2114 regs_ever_live[i++] = 1;
2117 /* This function handles the tracking of elimination offsets around branches.
2119 X is a piece of RTL being scanned.
2121 INSN is the insn that it came from, if any.
2123 INITIAL_P is nonzero if we are to set the offset to be the initial
2124 offset and zero if we are setting the offset of the label to be the
2128 set_label_offsets (rtx x, rtx insn, int initial_p)
2130 enum rtx_code code = GET_CODE (x);
2133 struct elim_table *p;
2138 if (LABEL_REF_NONLOCAL_P (x))
2143 /* ... fall through ... */
2146 /* If we know nothing about this label, set the desired offsets. Note
2147 that this sets the offset at a label to be the offset before a label
2148 if we don't know anything about the label. This is not correct for
2149 the label after a BARRIER, but is the best guess we can make. If
2150 we guessed wrong, we will suppress an elimination that might have
2151 been possible had we been able to guess correctly. */
2153 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2155 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2156 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2157 = (initial_p ? reg_eliminate[i].initial_offset
2158 : reg_eliminate[i].offset);
2159 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2162 /* Otherwise, if this is the definition of a label and it is
2163 preceded by a BARRIER, set our offsets to the known offset of
2167 && (tem = prev_nonnote_insn (insn)) != 0
2169 set_offsets_for_label (insn);
2171 /* If neither of the above cases is true, compare each offset
2172 with those previously recorded and suppress any eliminations
2173 where the offsets disagree. */
2175 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2176 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2177 != (initial_p ? reg_eliminate[i].initial_offset
2178 : reg_eliminate[i].offset))
2179 reg_eliminate[i].can_eliminate = 0;
2184 set_label_offsets (PATTERN (insn), insn, initial_p);
2186 /* ... fall through ... */
2190 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2191 and hence must have all eliminations at their initial offsets. */
2192 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2193 if (REG_NOTE_KIND (tem) == REG_LABEL)
2194 set_label_offsets (XEXP (tem, 0), insn, 1);
2200 /* Each of the labels in the parallel or address vector must be
2201 at their initial offsets. We want the first field for PARALLEL
2202 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2204 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2205 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2210 /* We only care about setting PC. If the source is not RETURN,
2211 IF_THEN_ELSE, or a label, disable any eliminations not at
2212 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2213 isn't one of those possibilities. For branches to a label,
2214 call ourselves recursively.
2216 Note that this can disable elimination unnecessarily when we have
2217 a non-local goto since it will look like a non-constant jump to
2218 someplace in the current function. This isn't a significant
2219 problem since such jumps will normally be when all elimination
2220 pairs are back to their initial offsets. */
2222 if (SET_DEST (x) != pc_rtx)
2225 switch (GET_CODE (SET_SRC (x)))
2232 set_label_offsets (SET_SRC (x), insn, initial_p);
2236 tem = XEXP (SET_SRC (x), 1);
2237 if (GET_CODE (tem) == LABEL_REF)
2238 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2239 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2242 tem = XEXP (SET_SRC (x), 2);
2243 if (GET_CODE (tem) == LABEL_REF)
2244 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2245 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2253 /* If we reach here, all eliminations must be at their initial
2254 offset because we are doing a jump to a variable address. */
2255 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2256 if (p->offset != p->initial_offset)
2257 p->can_eliminate = 0;
2265 /* Scan X and replace any eliminable registers (such as fp) with a
2266 replacement (such as sp), plus an offset.
2268 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2269 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2270 MEM, we are allowed to replace a sum of a register and the constant zero
2271 with the register, which we cannot do outside a MEM. In addition, we need
2272 to record the fact that a register is referenced outside a MEM.
2274 If INSN is an insn, it is the insn containing X. If we replace a REG
2275 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2276 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2277 the REG is being modified.
2279 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2280 That's used when we eliminate in expressions stored in notes.
2281 This means, do not set ref_outside_mem even if the reference
2284 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2285 replacements done assuming all offsets are at their initial values. If
2286 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2287 encounter, return the actual location so that find_reloads will do
2288 the proper thing. */
2291 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2292 bool may_use_invariant)
2294 enum rtx_code code = GET_CODE (x);
2295 struct elim_table *ep;
2302 if (! current_function_decl)
2324 /* First handle the case where we encounter a bare register that
2325 is eliminable. Replace it with a PLUS. */
2326 if (regno < FIRST_PSEUDO_REGISTER)
2328 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2330 if (ep->from_rtx == x && ep->can_eliminate)
2331 return plus_constant (ep->to_rtx, ep->previous_offset);
2334 else if (reg_renumber && reg_renumber[regno] < 0
2335 && reg_equiv_invariant && reg_equiv_invariant[regno])
2337 if (may_use_invariant)
2338 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2339 mem_mode, insn, true);
2340 /* There exists at least one use of REGNO that cannot be
2341 eliminated. Prevent the defining insn from being deleted. */
2342 reg_equiv_init[regno] = NULL_RTX;
2343 alter_reg (regno, -1);
2347 /* You might think handling MINUS in a manner similar to PLUS is a
2348 good idea. It is not. It has been tried multiple times and every
2349 time the change has had to have been reverted.
2351 Other parts of reload know a PLUS is special (gen_reload for example)
2352 and require special code to handle code a reloaded PLUS operand.
2354 Also consider backends where the flags register is clobbered by a
2355 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2356 lea instruction comes to mind). If we try to reload a MINUS, we
2357 may kill the flags register that was holding a useful value.
2359 So, please before trying to handle MINUS, consider reload as a
2360 whole instead of this little section as well as the backend issues. */
2362 /* If this is the sum of an eliminable register and a constant, rework
2364 if (REG_P (XEXP (x, 0))
2365 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2366 && CONSTANT_P (XEXP (x, 1)))
2368 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2370 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2372 /* The only time we want to replace a PLUS with a REG (this
2373 occurs when the constant operand of the PLUS is the negative
2374 of the offset) is when we are inside a MEM. We won't want
2375 to do so at other times because that would change the
2376 structure of the insn in a way that reload can't handle.
2377 We special-case the commonest situation in
2378 eliminate_regs_in_insn, so just replace a PLUS with a
2379 PLUS here, unless inside a MEM. */
2380 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2381 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2384 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2385 plus_constant (XEXP (x, 1),
2386 ep->previous_offset));
2389 /* If the register is not eliminable, we are done since the other
2390 operand is a constant. */
2394 /* If this is part of an address, we want to bring any constant to the
2395 outermost PLUS. We will do this by doing register replacement in
2396 our operands and seeing if a constant shows up in one of them.
2398 Note that there is no risk of modifying the structure of the insn,
2399 since we only get called for its operands, thus we are either
2400 modifying the address inside a MEM, or something like an address
2401 operand of a load-address insn. */
2404 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2405 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2407 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2409 /* If one side is a PLUS and the other side is a pseudo that
2410 didn't get a hard register but has a reg_equiv_constant,
2411 we must replace the constant here since it may no longer
2412 be in the position of any operand. */
2413 if (GET_CODE (new0) == PLUS && REG_P (new1)
2414 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2415 && reg_renumber[REGNO (new1)] < 0
2416 && reg_equiv_constant != 0
2417 && reg_equiv_constant[REGNO (new1)] != 0)
2418 new1 = reg_equiv_constant[REGNO (new1)];
2419 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2420 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2421 && reg_renumber[REGNO (new0)] < 0
2422 && reg_equiv_constant[REGNO (new0)] != 0)
2423 new0 = reg_equiv_constant[REGNO (new0)];
2425 new = form_sum (new0, new1);
2427 /* As above, if we are not inside a MEM we do not want to
2428 turn a PLUS into something else. We might try to do so here
2429 for an addition of 0 if we aren't optimizing. */
2430 if (! mem_mode && GET_CODE (new) != PLUS)
2431 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2439 /* If this is the product of an eliminable register and a
2440 constant, apply the distribute law and move the constant out
2441 so that we have (plus (mult ..) ..). This is needed in order
2442 to keep load-address insns valid. This case is pathological.
2443 We ignore the possibility of overflow here. */
2444 if (REG_P (XEXP (x, 0))
2445 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2446 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2447 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2449 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2452 /* Refs inside notes don't count for this purpose. */
2453 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2454 || GET_CODE (insn) == INSN_LIST)))
2455 ep->ref_outside_mem = 1;
2458 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2459 ep->previous_offset * INTVAL (XEXP (x, 1)));
2462 /* ... fall through ... */
2466 /* See comments before PLUS about handling MINUS. */
2468 case DIV: case UDIV:
2469 case MOD: case UMOD:
2470 case AND: case IOR: case XOR:
2471 case ROTATERT: case ROTATE:
2472 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2474 case GE: case GT: case GEU: case GTU:
2475 case LE: case LT: case LEU: case LTU:
2477 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2478 rtx new1 = XEXP (x, 1)
2479 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2481 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2482 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2487 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2490 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2491 if (new != XEXP (x, 0))
2493 /* If this is a REG_DEAD note, it is not valid anymore.
2494 Using the eliminated version could result in creating a
2495 REG_DEAD note for the stack or frame pointer. */
2496 if (GET_MODE (x) == REG_DEAD)
2498 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2501 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2505 /* ... fall through ... */
2508 /* Now do eliminations in the rest of the chain. If this was
2509 an EXPR_LIST, this might result in allocating more memory than is
2510 strictly needed, but it simplifies the code. */
2513 new = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2514 if (new != XEXP (x, 1))
2516 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2524 case STRICT_LOW_PART:
2526 case SIGN_EXTEND: case ZERO_EXTEND:
2527 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2528 case FLOAT: case FIX:
2529 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2537 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2538 if (new != XEXP (x, 0))
2539 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2543 /* Similar to above processing, but preserve SUBREG_BYTE.
2544 Convert (subreg (mem)) to (mem) if not paradoxical.
2545 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2546 pseudo didn't get a hard reg, we must replace this with the
2547 eliminated version of the memory location because push_reload
2548 may do the replacement in certain circumstances. */
2549 if (REG_P (SUBREG_REG (x))
2550 && (GET_MODE_SIZE (GET_MODE (x))
2551 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2552 && reg_equiv_memory_loc != 0
2553 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2555 new = SUBREG_REG (x);
2558 new = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2560 if (new != SUBREG_REG (x))
2562 int x_size = GET_MODE_SIZE (GET_MODE (x));
2563 int new_size = GET_MODE_SIZE (GET_MODE (new));
2566 && ((x_size < new_size
2567 #ifdef WORD_REGISTER_OPERATIONS
2568 /* On these machines, combine can create rtl of the form
2569 (set (subreg:m1 (reg:m2 R) 0) ...)
2570 where m1 < m2, and expects something interesting to
2571 happen to the entire word. Moreover, it will use the
2572 (reg:m2 R) later, expecting all bits to be preserved.
2573 So if the number of words is the same, preserve the
2574 subreg so that push_reload can see it. */
2575 && ! ((x_size - 1) / UNITS_PER_WORD
2576 == (new_size -1 ) / UNITS_PER_WORD)
2579 || x_size == new_size)
2581 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2583 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2589 /* Our only special processing is to pass the mode of the MEM to our
2590 recursive call and copy the flags. While we are here, handle this
2591 case more efficiently. */
2593 replace_equiv_address_nv (x,
2594 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2598 /* Handle insn_list USE that a call to a pure function may generate. */
2599 new = eliminate_regs_1 (XEXP (x, 0), 0, insn, false);
2600 if (new != XEXP (x, 0))
2601 return gen_rtx_USE (GET_MODE (x), new);
2613 /* Process each of our operands recursively. If any have changed, make a
2615 fmt = GET_RTX_FORMAT (code);
2616 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2620 new = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2621 if (new != XEXP (x, i) && ! copied)
2623 x = shallow_copy_rtx (x);
2628 else if (*fmt == 'E')
2631 for (j = 0; j < XVECLEN (x, i); j++)
2633 new = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2634 if (new != XVECEXP (x, i, j) && ! copied_vec)
2636 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2640 x = shallow_copy_rtx (x);
2643 XVEC (x, i) = new_v;
2646 XVECEXP (x, i, j) = new;
2655 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2657 return eliminate_regs_1 (x, mem_mode, insn, false);
2660 /* Scan rtx X for modifications of elimination target registers. Update
2661 the table of eliminables to reflect the changed state. MEM_MODE is
2662 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2665 elimination_effects (rtx x, enum machine_mode mem_mode)
2667 enum rtx_code code = GET_CODE (x);
2668 struct elim_table *ep;
2692 /* First handle the case where we encounter a bare register that
2693 is eliminable. Replace it with a PLUS. */
2694 if (regno < FIRST_PSEUDO_REGISTER)
2696 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2698 if (ep->from_rtx == x && ep->can_eliminate)
2701 ep->ref_outside_mem = 1;
2706 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2707 && reg_equiv_constant[regno]
2708 && ! function_invariant_p (reg_equiv_constant[regno]))
2709 elimination_effects (reg_equiv_constant[regno], mem_mode);
2718 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2719 if (ep->to_rtx == XEXP (x, 0))
2721 int size = GET_MODE_SIZE (mem_mode);
2723 /* If more bytes than MEM_MODE are pushed, account for them. */
2724 #ifdef PUSH_ROUNDING
2725 if (ep->to_rtx == stack_pointer_rtx)
2726 size = PUSH_ROUNDING (size);
2728 if (code == PRE_DEC || code == POST_DEC)
2730 else if (code == PRE_INC || code == POST_INC)
2732 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2733 && GET_CODE (XEXP (x, 1)) == PLUS
2734 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2735 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2736 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2739 /* These two aren't unary operators. */
2740 if (code == POST_MODIFY || code == PRE_MODIFY)
2743 /* Fall through to generic unary operation case. */
2744 case STRICT_LOW_PART:
2746 case SIGN_EXTEND: case ZERO_EXTEND:
2747 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2748 case FLOAT: case FIX:
2749 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2757 elimination_effects (XEXP (x, 0), mem_mode);
2761 if (REG_P (SUBREG_REG (x))
2762 && (GET_MODE_SIZE (GET_MODE (x))
2763 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2764 && reg_equiv_memory_loc != 0
2765 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2768 elimination_effects (SUBREG_REG (x), mem_mode);
2772 /* If using a register that is the source of an eliminate we still
2773 think can be performed, note it cannot be performed since we don't
2774 know how this register is used. */
2775 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2776 if (ep->from_rtx == XEXP (x, 0))
2777 ep->can_eliminate = 0;
2779 elimination_effects (XEXP (x, 0), mem_mode);
2783 /* If clobbering a register that is the replacement register for an
2784 elimination we still think can be performed, note that it cannot
2785 be performed. Otherwise, we need not be concerned about it. */
2786 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2787 if (ep->to_rtx == XEXP (x, 0))
2788 ep->can_eliminate = 0;
2790 elimination_effects (XEXP (x, 0), mem_mode);
2794 /* Check for setting a register that we know about. */
2795 if (REG_P (SET_DEST (x)))
2797 /* See if this is setting the replacement register for an
2800 If DEST is the hard frame pointer, we do nothing because we
2801 assume that all assignments to the frame pointer are for
2802 non-local gotos and are being done at a time when they are valid
2803 and do not disturb anything else. Some machines want to
2804 eliminate a fake argument pointer (or even a fake frame pointer)
2805 with either the real frame or the stack pointer. Assignments to
2806 the hard frame pointer must not prevent this elimination. */
2808 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2810 if (ep->to_rtx == SET_DEST (x)
2811 && SET_DEST (x) != hard_frame_pointer_rtx)
2813 /* If it is being incremented, adjust the offset. Otherwise,
2814 this elimination can't be done. */
2815 rtx src = SET_SRC (x);
2817 if (GET_CODE (src) == PLUS
2818 && XEXP (src, 0) == SET_DEST (x)
2819 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2820 ep->offset -= INTVAL (XEXP (src, 1));
2822 ep->can_eliminate = 0;
2826 elimination_effects (SET_DEST (x), 0);
2827 elimination_effects (SET_SRC (x), 0);
2831 /* Our only special processing is to pass the mode of the MEM to our
2833 elimination_effects (XEXP (x, 0), GET_MODE (x));
2840 fmt = GET_RTX_FORMAT (code);
2841 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2844 elimination_effects (XEXP (x, i), mem_mode);
2845 else if (*fmt == 'E')
2846 for (j = 0; j < XVECLEN (x, i); j++)
2847 elimination_effects (XVECEXP (x, i, j), mem_mode);
2851 /* Descend through rtx X and verify that no references to eliminable registers
2852 remain. If any do remain, mark the involved register as not
2856 check_eliminable_occurrences (rtx x)
2865 code = GET_CODE (x);
2867 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2869 struct elim_table *ep;
2871 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2872 if (ep->from_rtx == x)
2873 ep->can_eliminate = 0;
2877 fmt = GET_RTX_FORMAT (code);
2878 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2881 check_eliminable_occurrences (XEXP (x, i));
2882 else if (*fmt == 'E')
2885 for (j = 0; j < XVECLEN (x, i); j++)
2886 check_eliminable_occurrences (XVECEXP (x, i, j));
2891 /* Scan INSN and eliminate all eliminable registers in it.
2893 If REPLACE is nonzero, do the replacement destructively. Also
2894 delete the insn as dead it if it is setting an eliminable register.
2896 If REPLACE is zero, do all our allocations in reload_obstack.
2898 If no eliminations were done and this insn doesn't require any elimination
2899 processing (these are not identical conditions: it might be updating sp,
2900 but not referencing fp; this needs to be seen during reload_as_needed so
2901 that the offset between fp and sp can be taken into consideration), zero
2902 is returned. Otherwise, 1 is returned. */
2905 eliminate_regs_in_insn (rtx insn, int replace)
2907 int icode = recog_memoized (insn);
2908 rtx old_body = PATTERN (insn);
2909 int insn_is_asm = asm_noperands (old_body) >= 0;
2910 rtx old_set = single_set (insn);
2914 rtx substed_operand[MAX_RECOG_OPERANDS];
2915 rtx orig_operand[MAX_RECOG_OPERANDS];
2916 struct elim_table *ep;
2917 rtx plus_src, plus_cst_src;
2919 if (! insn_is_asm && icode < 0)
2921 gcc_assert (GET_CODE (PATTERN (insn)) == USE
2922 || GET_CODE (PATTERN (insn)) == CLOBBER
2923 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2924 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2925 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
2929 if (old_set != 0 && REG_P (SET_DEST (old_set))
2930 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2932 /* Check for setting an eliminable register. */
2933 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2934 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2936 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2937 /* If this is setting the frame pointer register to the
2938 hardware frame pointer register and this is an elimination
2939 that will be done (tested above), this insn is really
2940 adjusting the frame pointer downward to compensate for
2941 the adjustment done before a nonlocal goto. */
2942 if (ep->from == FRAME_POINTER_REGNUM
2943 && ep->to == HARD_FRAME_POINTER_REGNUM)
2945 rtx base = SET_SRC (old_set);
2946 rtx base_insn = insn;
2947 HOST_WIDE_INT offset = 0;
2949 while (base != ep->to_rtx)
2951 rtx prev_insn, prev_set;
2953 if (GET_CODE (base) == PLUS
2954 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2956 offset += INTVAL (XEXP (base, 1));
2957 base = XEXP (base, 0);
2959 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2960 && (prev_set = single_set (prev_insn)) != 0
2961 && rtx_equal_p (SET_DEST (prev_set), base))
2963 base = SET_SRC (prev_set);
2964 base_insn = prev_insn;
2970 if (base == ep->to_rtx)
2973 = plus_constant (ep->to_rtx, offset - ep->offset);
2975 new_body = old_body;
2978 new_body = copy_insn (old_body);
2979 if (REG_NOTES (insn))
2980 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2982 PATTERN (insn) = new_body;
2983 old_set = single_set (insn);
2985 /* First see if this insn remains valid when we
2986 make the change. If not, keep the INSN_CODE
2987 the same and let reload fit it up. */
2988 validate_change (insn, &SET_SRC (old_set), src, 1);
2989 validate_change (insn, &SET_DEST (old_set),
2991 if (! apply_change_group ())
2993 SET_SRC (old_set) = src;
2994 SET_DEST (old_set) = ep->to_rtx;
3003 /* In this case this insn isn't serving a useful purpose. We
3004 will delete it in reload_as_needed once we know that this
3005 elimination is, in fact, being done.
3007 If REPLACE isn't set, we can't delete this insn, but needn't
3008 process it since it won't be used unless something changes. */
3011 delete_dead_insn (insn);
3019 /* We allow one special case which happens to work on all machines we
3020 currently support: a single set with the source or a REG_EQUAL
3021 note being a PLUS of an eliminable register and a constant. */
3022 plus_src = plus_cst_src = 0;
3023 if (old_set && REG_P (SET_DEST (old_set)))
3025 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3026 plus_src = SET_SRC (old_set);
3027 /* First see if the source is of the form (plus (...) CST). */
3029 && GET_CODE (XEXP (plus_src, 1)) == CONST_INT)
3030 plus_cst_src = plus_src;
3031 else if (REG_P (SET_SRC (old_set))
3034 /* Otherwise, see if we have a REG_EQUAL note of the form
3035 (plus (...) CST). */
3037 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3039 if (REG_NOTE_KIND (links) == REG_EQUAL
3040 && GET_CODE (XEXP (links, 0)) == PLUS
3041 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT)
3043 plus_cst_src = XEXP (links, 0);
3049 /* Check that the first operand of the PLUS is a hard reg or
3050 the lowpart subreg of one. */
3053 rtx reg = XEXP (plus_cst_src, 0);
3054 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3055 reg = SUBREG_REG (reg);
3057 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3063 rtx reg = XEXP (plus_cst_src, 0);
3064 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3066 if (GET_CODE (reg) == SUBREG)
3067 reg = SUBREG_REG (reg);
3069 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3070 if (ep->from_rtx == reg && ep->can_eliminate)
3072 rtx to_rtx = ep->to_rtx;
3073 offset += ep->offset;
3075 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3076 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3081 /* We assume here that if we need a PARALLEL with
3082 CLOBBERs for this assignment, we can do with the
3083 MATCH_SCRATCHes that add_clobbers allocates.
3084 There's not much we can do if that doesn't work. */
3085 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3089 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3092 rtvec vec = rtvec_alloc (num_clobbers + 1);
3094 vec->elem[0] = PATTERN (insn);
3095 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3096 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3098 gcc_assert (INSN_CODE (insn) >= 0);
3100 /* If we have a nonzero offset, and the source is already
3101 a simple REG, the following transformation would
3102 increase the cost of the insn by replacing a simple REG
3103 with (plus (reg sp) CST). So try only when we already
3104 had a PLUS before. */
3107 new_body = old_body;
3110 new_body = copy_insn (old_body);
3111 if (REG_NOTES (insn))
3112 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3114 PATTERN (insn) = new_body;
3115 old_set = single_set (insn);
3117 XEXP (SET_SRC (old_set), 0) = to_rtx;
3118 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3124 /* This can't have an effect on elimination offsets, so skip right
3130 /* Determine the effects of this insn on elimination offsets. */
3131 elimination_effects (old_body, 0);
3133 /* Eliminate all eliminable registers occurring in operands that
3134 can be handled by reload. */
3135 extract_insn (insn);
3136 for (i = 0; i < recog_data.n_operands; i++)
3138 orig_operand[i] = recog_data.operand[i];
3139 substed_operand[i] = recog_data.operand[i];
3141 /* For an asm statement, every operand is eliminable. */
3142 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3144 bool is_set_src, in_plus;
3146 /* Check for setting a register that we know about. */
3147 if (recog_data.operand_type[i] != OP_IN
3148 && REG_P (orig_operand[i]))
3150 /* If we are assigning to a register that can be eliminated, it
3151 must be as part of a PARALLEL, since the code above handles
3152 single SETs. We must indicate that we can no longer
3153 eliminate this reg. */
3154 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3156 if (ep->from_rtx == orig_operand[i])
3157 ep->can_eliminate = 0;
3160 /* Companion to the above plus substitution, we can allow
3161 invariants as the source of a plain move. */
3163 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3167 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3168 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3172 = eliminate_regs_1 (recog_data.operand[i], 0,
3173 replace ? insn : NULL_RTX,
3174 is_set_src || in_plus);
3175 if (substed_operand[i] != orig_operand[i])
3177 /* Terminate the search in check_eliminable_occurrences at
3179 *recog_data.operand_loc[i] = 0;
3181 /* If an output operand changed from a REG to a MEM and INSN is an
3182 insn, write a CLOBBER insn. */
3183 if (recog_data.operand_type[i] != OP_IN
3184 && REG_P (orig_operand[i])
3185 && MEM_P (substed_operand[i])
3187 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3192 for (i = 0; i < recog_data.n_dups; i++)
3193 *recog_data.dup_loc[i]
3194 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3196 /* If any eliminable remain, they aren't eliminable anymore. */
3197 check_eliminable_occurrences (old_body);
3199 /* Substitute the operands; the new values are in the substed_operand
3201 for (i = 0; i < recog_data.n_operands; i++)
3202 *recog_data.operand_loc[i] = substed_operand[i];
3203 for (i = 0; i < recog_data.n_dups; i++)
3204 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3206 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3207 re-recognize the insn. We do this in case we had a simple addition
3208 but now can do this as a load-address. This saves an insn in this
3210 If re-recognition fails, the old insn code number will still be used,
3211 and some register operands may have changed into PLUS expressions.
3212 These will be handled by find_reloads by loading them into a register
3217 /* If we aren't replacing things permanently and we changed something,
3218 make another copy to ensure that all the RTL is new. Otherwise
3219 things can go wrong if find_reload swaps commutative operands
3220 and one is inside RTL that has been copied while the other is not. */
3221 new_body = old_body;
3224 new_body = copy_insn (old_body);
3225 if (REG_NOTES (insn))
3226 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3228 PATTERN (insn) = new_body;
3230 /* If we had a move insn but now we don't, rerecognize it. This will
3231 cause spurious re-recognition if the old move had a PARALLEL since
3232 the new one still will, but we can't call single_set without
3233 having put NEW_BODY into the insn and the re-recognition won't
3234 hurt in this rare case. */
3235 /* ??? Why this huge if statement - why don't we just rerecognize the
3239 && ((REG_P (SET_SRC (old_set))
3240 && (GET_CODE (new_body) != SET
3241 || !REG_P (SET_SRC (new_body))))
3242 /* If this was a load from or store to memory, compare
3243 the MEM in recog_data.operand to the one in the insn.
3244 If they are not equal, then rerecognize the insn. */
3246 && ((MEM_P (SET_SRC (old_set))
3247 && SET_SRC (old_set) != recog_data.operand[1])
3248 || (MEM_P (SET_DEST (old_set))
3249 && SET_DEST (old_set) != recog_data.operand[0])))
3250 /* If this was an add insn before, rerecognize. */
3251 || GET_CODE (SET_SRC (old_set)) == PLUS))
3253 int new_icode = recog (PATTERN (insn), insn, 0);
3255 INSN_CODE (insn) = new_icode;
3259 /* Restore the old body. If there were any changes to it, we made a copy
3260 of it while the changes were still in place, so we'll correctly return
3261 a modified insn below. */
3264 /* Restore the old body. */
3265 for (i = 0; i < recog_data.n_operands; i++)
3266 *recog_data.operand_loc[i] = orig_operand[i];
3267 for (i = 0; i < recog_data.n_dups; i++)
3268 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3271 /* Update all elimination pairs to reflect the status after the current
3272 insn. The changes we make were determined by the earlier call to
3273 elimination_effects.
3275 We also detect cases where register elimination cannot be done,
3276 namely, if a register would be both changed and referenced outside a MEM
3277 in the resulting insn since such an insn is often undefined and, even if
3278 not, we cannot know what meaning will be given to it. Note that it is
3279 valid to have a register used in an address in an insn that changes it
3280 (presumably with a pre- or post-increment or decrement).
3282 If anything changes, return nonzero. */
3284 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3286 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3287 ep->can_eliminate = 0;
3289 ep->ref_outside_mem = 0;
3291 if (ep->previous_offset != ep->offset)
3296 /* If we changed something, perform elimination in REG_NOTES. This is
3297 needed even when REPLACE is zero because a REG_DEAD note might refer
3298 to a register that we eliminate and could cause a different number
3299 of spill registers to be needed in the final reload pass than in
3301 if (val && REG_NOTES (insn) != 0)
3303 = eliminate_regs_1 (REG_NOTES (insn), 0, REG_NOTES (insn), true);
3308 /* Loop through all elimination pairs.
3309 Recalculate the number not at initial offset.
3311 Compute the maximum offset (minimum offset if the stack does not
3312 grow downward) for each elimination pair. */
3315 update_eliminable_offsets (void)
3317 struct elim_table *ep;
3319 num_not_at_initial_offset = 0;
3320 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3322 ep->previous_offset = ep->offset;
3323 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3324 num_not_at_initial_offset++;
3328 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3329 replacement we currently believe is valid, mark it as not eliminable if X
3330 modifies DEST in any way other than by adding a constant integer to it.
3332 If DEST is the frame pointer, we do nothing because we assume that
3333 all assignments to the hard frame pointer are nonlocal gotos and are being
3334 done at a time when they are valid and do not disturb anything else.
3335 Some machines want to eliminate a fake argument pointer with either the
3336 frame or stack pointer. Assignments to the hard frame pointer must not
3337 prevent this elimination.
3339 Called via note_stores from reload before starting its passes to scan
3340 the insns of the function. */
3343 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3347 /* A SUBREG of a hard register here is just changing its mode. We should
3348 not see a SUBREG of an eliminable hard register, but check just in
3350 if (GET_CODE (dest) == SUBREG)
3351 dest = SUBREG_REG (dest);
3353 if (dest == hard_frame_pointer_rtx)
3356 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3357 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3358 && (GET_CODE (x) != SET
3359 || GET_CODE (SET_SRC (x)) != PLUS
3360 || XEXP (SET_SRC (x), 0) != dest
3361 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3363 reg_eliminate[i].can_eliminate_previous
3364 = reg_eliminate[i].can_eliminate = 0;
3369 /* Verify that the initial elimination offsets did not change since the
3370 last call to set_initial_elim_offsets. This is used to catch cases
3371 where something illegal happened during reload_as_needed that could
3372 cause incorrect code to be generated if we did not check for it. */
3375 verify_initial_elim_offsets (void)
3379 if (!num_eliminable)
3382 #ifdef ELIMINABLE_REGS
3384 struct elim_table *ep;
3386 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3388 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3389 if (t != ep->initial_offset)
3394 INITIAL_FRAME_POINTER_OFFSET (t);
3395 if (t != reg_eliminate[0].initial_offset)
3402 /* Reset all offsets on eliminable registers to their initial values. */
3405 set_initial_elim_offsets (void)
3407 struct elim_table *ep = reg_eliminate;
3409 #ifdef ELIMINABLE_REGS
3410 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3412 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3413 ep->previous_offset = ep->offset = ep->initial_offset;
3416 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3417 ep->previous_offset = ep->offset = ep->initial_offset;
3420 num_not_at_initial_offset = 0;
3423 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3426 set_initial_eh_label_offset (rtx label)
3428 set_label_offsets (label, NULL_RTX, 1);
3431 /* Initialize the known label offsets.
3432 Set a known offset for each forced label to be at the initial offset
3433 of each elimination. We do this because we assume that all
3434 computed jumps occur from a location where each elimination is
3435 at its initial offset.
3436 For all other labels, show that we don't know the offsets. */
3439 set_initial_label_offsets (void)
3442 memset (offsets_known_at, 0, num_labels);
3444 for (x = forced_labels; x; x = XEXP (x, 1))
3446 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3448 for_each_eh_label (set_initial_eh_label_offset);
3451 /* Set all elimination offsets to the known values for the code label given
3455 set_offsets_for_label (rtx insn)
3458 int label_nr = CODE_LABEL_NUMBER (insn);
3459 struct elim_table *ep;
3461 num_not_at_initial_offset = 0;
3462 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3464 ep->offset = ep->previous_offset
3465 = offsets_at[label_nr - first_label_num][i];
3466 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3467 num_not_at_initial_offset++;
3471 /* See if anything that happened changes which eliminations are valid.
3472 For example, on the SPARC, whether or not the frame pointer can
3473 be eliminated can depend on what registers have been used. We need
3474 not check some conditions again (such as flag_omit_frame_pointer)
3475 since they can't have changed. */
3478 update_eliminables (HARD_REG_SET *pset)
3480 int previous_frame_pointer_needed = frame_pointer_needed;
3481 struct elim_table *ep;
3483 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3484 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3485 #ifdef ELIMINABLE_REGS
3486 || ! CAN_ELIMINATE (ep->from, ep->to)
3489 ep->can_eliminate = 0;
3491 /* Look for the case where we have discovered that we can't replace
3492 register A with register B and that means that we will now be
3493 trying to replace register A with register C. This means we can
3494 no longer replace register C with register B and we need to disable
3495 such an elimination, if it exists. This occurs often with A == ap,
3496 B == sp, and C == fp. */
3498 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3500 struct elim_table *op;
3503 if (! ep->can_eliminate && ep->can_eliminate_previous)
3505 /* Find the current elimination for ep->from, if there is a
3507 for (op = reg_eliminate;
3508 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3509 if (op->from == ep->from && op->can_eliminate)
3515 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3517 for (op = reg_eliminate;
3518 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3519 if (op->from == new_to && op->to == ep->to)
3520 op->can_eliminate = 0;
3524 /* See if any registers that we thought we could eliminate the previous
3525 time are no longer eliminable. If so, something has changed and we
3526 must spill the register. Also, recompute the number of eliminable
3527 registers and see if the frame pointer is needed; it is if there is
3528 no elimination of the frame pointer that we can perform. */
3530 frame_pointer_needed = 1;
3531 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3533 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3534 && ep->to != HARD_FRAME_POINTER_REGNUM)
3535 frame_pointer_needed = 0;
3537 if (! ep->can_eliminate && ep->can_eliminate_previous)
3539 ep->can_eliminate_previous = 0;
3540 SET_HARD_REG_BIT (*pset, ep->from);
3545 /* If we didn't need a frame pointer last time, but we do now, spill
3546 the hard frame pointer. */
3547 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3548 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3551 /* Initialize the table of registers to eliminate. */
3554 init_elim_table (void)
3556 struct elim_table *ep;
3557 #ifdef ELIMINABLE_REGS
3558 const struct elim_table_1 *ep1;
3562 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3564 /* Does this function require a frame pointer? */
3566 frame_pointer_needed = (! flag_omit_frame_pointer
3567 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3568 and restore sp for alloca. So we can't eliminate
3569 the frame pointer in that case. At some point,
3570 we should improve this by emitting the
3571 sp-adjusting insns for this case. */
3572 || (current_function_calls_alloca
3573 && EXIT_IGNORE_STACK)
3574 || current_function_accesses_prior_frames
3575 || FRAME_POINTER_REQUIRED);
3579 #ifdef ELIMINABLE_REGS
3580 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3581 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3583 ep->from = ep1->from;
3585 ep->can_eliminate = ep->can_eliminate_previous
3586 = (CAN_ELIMINATE (ep->from, ep->to)
3587 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3590 reg_eliminate[0].from = reg_eliminate_1[0].from;
3591 reg_eliminate[0].to = reg_eliminate_1[0].to;
3592 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3593 = ! frame_pointer_needed;
3596 /* Count the number of eliminable registers and build the FROM and TO
3597 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3598 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3599 We depend on this. */
3600 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3602 num_eliminable += ep->can_eliminate;
3603 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3604 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3608 /* Kick all pseudos out of hard register REGNO.
3610 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3611 because we found we can't eliminate some register. In the case, no pseudos
3612 are allowed to be in the register, even if they are only in a block that
3613 doesn't require spill registers, unlike the case when we are spilling this
3614 hard reg to produce another spill register.
3616 Return nonzero if any pseudos needed to be kicked out. */
3619 spill_hard_reg (unsigned int regno, int cant_eliminate)
3625 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3626 regs_ever_live[regno] = 1;
3629 /* Spill every pseudo reg that was allocated to this reg
3630 or to something that overlaps this reg. */
3632 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3633 if (reg_renumber[i] >= 0
3634 && (unsigned int) reg_renumber[i] <= regno
3635 && ((unsigned int) reg_renumber[i]
3636 + hard_regno_nregs[(unsigned int) reg_renumber[i]]
3637 [PSEUDO_REGNO_MODE (i)]
3639 SET_REGNO_REG_SET (&spilled_pseudos, i);
3642 /* After find_reload_regs has been run for all insn that need reloads,
3643 and/or spill_hard_regs was called, this function is used to actually
3644 spill pseudo registers and try to reallocate them. It also sets up the
3645 spill_regs array for use by choose_reload_regs. */
3648 finish_spills (int global)
3650 struct insn_chain *chain;
3651 int something_changed = 0;
3653 reg_set_iterator rsi;
3655 /* Build the spill_regs array for the function. */
3656 /* If there are some registers still to eliminate and one of the spill regs
3657 wasn't ever used before, additional stack space may have to be
3658 allocated to store this register. Thus, we may have changed the offset
3659 between the stack and frame pointers, so mark that something has changed.
3661 One might think that we need only set VAL to 1 if this is a call-used
3662 register. However, the set of registers that must be saved by the
3663 prologue is not identical to the call-used set. For example, the
3664 register used by the call insn for the return PC is a call-used register,
3665 but must be saved by the prologue. */
3668 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3669 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3671 spill_reg_order[i] = n_spills;
3672 spill_regs[n_spills++] = i;
3673 if (num_eliminable && ! regs_ever_live[i])
3674 something_changed = 1;
3675 regs_ever_live[i] = 1;
3678 spill_reg_order[i] = -1;
3680 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3682 /* Record the current hard register the pseudo is allocated to in
3683 pseudo_previous_regs so we avoid reallocating it to the same
3684 hard reg in a later pass. */
3685 gcc_assert (reg_renumber[i] >= 0);
3687 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3688 /* Mark it as no longer having a hard register home. */
3689 reg_renumber[i] = -1;
3690 /* We will need to scan everything again. */
3691 something_changed = 1;
3694 /* Retry global register allocation if possible. */
3697 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3698 /* For every insn that needs reloads, set the registers used as spill
3699 regs in pseudo_forbidden_regs for every pseudo live across the
3701 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3703 EXECUTE_IF_SET_IN_REG_SET
3704 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3706 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3707 chain->used_spill_regs);
3709 EXECUTE_IF_SET_IN_REG_SET
3710 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3712 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3713 chain->used_spill_regs);
3717 /* Retry allocating the spilled pseudos. For each reg, merge the
3718 various reg sets that indicate which hard regs can't be used,
3719 and call retry_global_alloc.
3720 We change spill_pseudos here to only contain pseudos that did not
3721 get a new hard register. */
3722 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3723 if (reg_old_renumber[i] != reg_renumber[i])
3725 HARD_REG_SET forbidden;
3726 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3727 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3728 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3729 retry_global_alloc (i, forbidden);
3730 if (reg_renumber[i] >= 0)
3731 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3735 /* Fix up the register information in the insn chain.
3736 This involves deleting those of the spilled pseudos which did not get
3737 a new hard register home from the live_{before,after} sets. */
3738 for (chain = reload_insn_chain; chain; chain = chain->next)
3740 HARD_REG_SET used_by_pseudos;
3741 HARD_REG_SET used_by_pseudos2;
3743 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3744 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3746 /* Mark any unallocated hard regs as available for spills. That
3747 makes inheritance work somewhat better. */
3748 if (chain->need_reload)
3750 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3751 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3752 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3754 /* Save the old value for the sanity test below. */
3755 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3757 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3758 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3759 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3760 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3762 /* Make sure we only enlarge the set. */
3763 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3769 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3770 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3772 int regno = reg_renumber[i];
3773 if (reg_old_renumber[i] == regno)
3776 alter_reg (i, reg_old_renumber[i]);
3777 reg_old_renumber[i] = regno;
3781 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3783 fprintf (dump_file, " Register %d now in %d.\n\n",
3784 i, reg_renumber[i]);
3788 return something_changed;
3791 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3794 scan_paradoxical_subregs (rtx x)
3798 enum rtx_code code = GET_CODE (x);
3808 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3816 if (REG_P (SUBREG_REG (x))
3817 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3818 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3819 = GET_MODE_SIZE (GET_MODE (x));
3826 fmt = GET_RTX_FORMAT (code);
3827 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3830 scan_paradoxical_subregs (XEXP (x, i));
3831 else if (fmt[i] == 'E')
3834 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3835 scan_paradoxical_subregs (XVECEXP (x, i, j));
3840 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
3841 examine all of the reload insns between PREV and NEXT exclusive, and
3842 annotate all that may trap. */
3845 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
3847 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
3848 unsigned int trap_count;
3854 if (may_trap_p (PATTERN (insn)))
3858 remove_note (insn, note);
3862 for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i))
3863 if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i)))
3867 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (note, 0), REG_NOTES (i));
3871 /* Reload pseudo-registers into hard regs around each insn as needed.
3872 Additional register load insns are output before the insn that needs it
3873 and perhaps store insns after insns that modify the reloaded pseudo reg.
3875 reg_last_reload_reg and reg_reloaded_contents keep track of
3876 which registers are already available in reload registers.
3877 We update these for the reloads that we perform,
3878 as the insns are scanned. */
3881 reload_as_needed (int live_known)
3883 struct insn_chain *chain;
3884 #if defined (AUTO_INC_DEC)
3889 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3890 memset (spill_reg_store, 0, sizeof spill_reg_store);
3891 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
3892 INIT_REG_SET (®_has_output_reload);
3893 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3894 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
3896 set_initial_elim_offsets ();
3898 for (chain = reload_insn_chain; chain; chain = chain->next)
3901 rtx insn = chain->insn;
3902 rtx old_next = NEXT_INSN (insn);
3904 /* If we pass a label, copy the offsets from the label information
3905 into the current offsets of each elimination. */
3907 set_offsets_for_label (insn);
3909 else if (INSN_P (insn))
3911 regset_head regs_to_forget;
3912 INIT_REG_SET (®s_to_forget);
3913 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
3915 /* If this is a USE and CLOBBER of a MEM, ensure that any
3916 references to eliminable registers have been removed. */
3918 if ((GET_CODE (PATTERN (insn)) == USE
3919 || GET_CODE (PATTERN (insn)) == CLOBBER)
3920 && MEM_P (XEXP (PATTERN (insn), 0)))
3921 XEXP (XEXP (PATTERN (insn), 0), 0)
3922 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3923 GET_MODE (XEXP (PATTERN (insn), 0)),
3926 /* If we need to do register elimination processing, do so.
3927 This might delete the insn, in which case we are done. */
3928 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3930 eliminate_regs_in_insn (insn, 1);
3933 update_eliminable_offsets ();
3934 CLEAR_REG_SET (®s_to_forget);
3939 /* If need_elim is nonzero but need_reload is zero, one might think
3940 that we could simply set n_reloads to 0. However, find_reloads
3941 could have done some manipulation of the insn (such as swapping
3942 commutative operands), and these manipulations are lost during
3943 the first pass for every insn that needs register elimination.
3944 So the actions of find_reloads must be redone here. */
3946 if (! chain->need_elim && ! chain->need_reload
3947 && ! chain->need_operand_change)
3949 /* First find the pseudo regs that must be reloaded for this insn.
3950 This info is returned in the tables reload_... (see reload.h).
3951 Also modify the body of INSN by substituting RELOAD
3952 rtx's for those pseudo regs. */
3955 CLEAR_REG_SET (®_has_output_reload);
3956 CLEAR_HARD_REG_SET (reg_is_output_reload);
3958 find_reloads (insn, 1, spill_indirect_levels, live_known,
3964 rtx next = NEXT_INSN (insn);
3967 prev = PREV_INSN (insn);
3969 /* Now compute which reload regs to reload them into. Perhaps
3970 reusing reload regs from previous insns, or else output
3971 load insns to reload them. Maybe output store insns too.
3972 Record the choices of reload reg in reload_reg_rtx. */
3973 choose_reload_regs (chain);
3975 /* Merge any reloads that we didn't combine for fear of
3976 increasing the number of spill registers needed but now
3977 discover can be safely merged. */
3978 if (SMALL_REGISTER_CLASSES)
3979 merge_assigned_reloads (insn);
3981 /* Generate the insns to reload operands into or out of
3982 their reload regs. */
3983 emit_reload_insns (chain);
3985 /* Substitute the chosen reload regs from reload_reg_rtx
3986 into the insn's body (or perhaps into the bodies of other
3987 load and store insn that we just made for reloading
3988 and that we moved the structure into). */
3989 subst_reloads (insn);
3991 /* Adjust the exception region notes for loads and stores. */
3992 if (flag_non_call_exceptions && !CALL_P (insn))
3993 fixup_eh_region_note (insn, prev, next);
3995 /* If this was an ASM, make sure that all the reload insns
3996 we have generated are valid. If not, give an error
3998 if (asm_noperands (PATTERN (insn)) >= 0)
3999 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4000 if (p != insn && INSN_P (p)
4001 && GET_CODE (PATTERN (p)) != USE
4002 && (recog_memoized (p) < 0
4003 || (extract_insn (p), ! constrain_operands (1))))
4005 error_for_asm (insn,
4006 "%<asm%> operand requires "
4007 "impossible reload");
4012 if (num_eliminable && chain->need_elim)
4013 update_eliminable_offsets ();
4015 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4016 is no longer validly lying around to save a future reload.
4017 Note that this does not detect pseudos that were reloaded
4018 for this insn in order to be stored in
4019 (obeying register constraints). That is correct; such reload
4020 registers ARE still valid. */
4021 forget_marked_reloads (®s_to_forget);
4022 CLEAR_REG_SET (®s_to_forget);
4024 /* There may have been CLOBBER insns placed after INSN. So scan
4025 between INSN and NEXT and use them to forget old reloads. */
4026 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4027 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4028 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4031 /* Likewise for regs altered by auto-increment in this insn.
4032 REG_INC notes have been changed by reloading:
4033 find_reloads_address_1 records substitutions for them,
4034 which have been performed by subst_reloads above. */
4035 for (i = n_reloads - 1; i >= 0; i--)
4037 rtx in_reg = rld[i].in_reg;
4040 enum rtx_code code = GET_CODE (in_reg);
4041 /* PRE_INC / PRE_DEC will have the reload register ending up
4042 with the same value as the stack slot, but that doesn't
4043 hold true for POST_INC / POST_DEC. Either we have to
4044 convert the memory access to a true POST_INC / POST_DEC,
4045 or we can't use the reload register for inheritance. */
4046 if ((code == POST_INC || code == POST_DEC)
4047 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4048 REGNO (rld[i].reg_rtx))
4049 /* Make sure it is the inc/dec pseudo, and not
4050 some other (e.g. output operand) pseudo. */
4051 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4052 == REGNO (XEXP (in_reg, 0))))
4055 rtx reload_reg = rld[i].reg_rtx;
4056 enum machine_mode mode = GET_MODE (reload_reg);
4060 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4062 /* We really want to ignore REG_INC notes here, so
4063 use PATTERN (p) as argument to reg_set_p . */
4064 if (reg_set_p (reload_reg, PATTERN (p)))
4066 n = count_occurrences (PATTERN (p), reload_reg, 0);
4071 n = validate_replace_rtx (reload_reg,
4072 gen_rtx_fmt_e (code,
4077 /* We must also verify that the constraints
4078 are met after the replacement. */
4081 n = constrain_operands (1);
4085 /* If the constraints were not met, then
4086 undo the replacement. */
4089 validate_replace_rtx (gen_rtx_fmt_e (code,
4102 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4104 /* Mark this as having an output reload so that the
4105 REG_INC processing code below won't invalidate
4106 the reload for inheritance. */
4107 SET_HARD_REG_BIT (reg_is_output_reload,
4108 REGNO (reload_reg));
4109 SET_REGNO_REG_SET (®_has_output_reload,
4110 REGNO (XEXP (in_reg, 0)));
4113 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4116 else if ((code == PRE_INC || code == PRE_DEC)
4117 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4118 REGNO (rld[i].reg_rtx))
4119 /* Make sure it is the inc/dec pseudo, and not
4120 some other (e.g. output operand) pseudo. */
4121 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4122 == REGNO (XEXP (in_reg, 0))))
4124 SET_HARD_REG_BIT (reg_is_output_reload,
4125 REGNO (rld[i].reg_rtx));
4126 SET_REGNO_REG_SET (®_has_output_reload,
4127 REGNO (XEXP (in_reg, 0)));
4131 /* If a pseudo that got a hard register is auto-incremented,
4132 we must purge records of copying it into pseudos without
4134 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4135 if (REG_NOTE_KIND (x) == REG_INC)
4137 /* See if this pseudo reg was reloaded in this insn.
4138 If so, its last-reload info is still valid
4139 because it is based on this insn's reload. */
4140 for (i = 0; i < n_reloads; i++)
4141 if (rld[i].out == XEXP (x, 0))
4145 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4149 /* A reload reg's contents are unknown after a label. */
4151 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4153 /* Don't assume a reload reg is still good after a call insn
4154 if it is a call-used reg, or if it contains a value that will
4155 be partially clobbered by the call. */
4156 else if (CALL_P (insn))
4158 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4159 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4164 free (reg_last_reload_reg);
4165 CLEAR_REG_SET (®_has_output_reload);
4168 /* Discard all record of any value reloaded from X,
4169 or reloaded in X from someplace else;
4170 unless X is an output reload reg of the current insn.
4172 X may be a hard reg (the reload reg)
4173 or it may be a pseudo reg that was reloaded from.
4175 When DATA is non-NULL just mark the registers in regset
4176 to be forgotten later. */
4179 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4184 regset regs = (regset) data;
4186 /* note_stores does give us subregs of hard regs,
4187 subreg_regno_offset requires a hard reg. */
4188 while (GET_CODE (x) == SUBREG)
4190 /* We ignore the subreg offset when calculating the regno,
4191 because we are using the entire underlying hard register
4201 if (regno >= FIRST_PSEUDO_REGISTER)
4207 nr = hard_regno_nregs[regno][GET_MODE (x)];
4208 /* Storing into a spilled-reg invalidates its contents.
4209 This can happen if a block-local pseudo is allocated to that reg
4210 and it wasn't spilled because this block's total need is 0.
4211 Then some insn might have an optional reload and use this reg. */
4213 for (i = 0; i < nr; i++)
4214 /* But don't do this if the reg actually serves as an output
4215 reload reg in the current instruction. */
4217 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4219 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4220 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4221 spill_reg_store[regno + i] = 0;
4227 SET_REGNO_REG_SET (regs, regno + nr);
4230 /* Since value of X has changed,
4231 forget any value previously copied from it. */
4234 /* But don't forget a copy if this is the output reload
4235 that establishes the copy's validity. */
4237 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4238 reg_last_reload_reg[regno + nr] = 0;
4242 /* Forget the reloads marked in regset by previous function. */
4244 forget_marked_reloads (regset regs)
4247 reg_set_iterator rsi;
4248 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4250 if (reg < FIRST_PSEUDO_REGISTER
4251 /* But don't do this if the reg actually serves as an output
4252 reload reg in the current instruction. */
4254 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4256 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4257 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, reg);
4258 spill_reg_store[reg] = 0;
4261 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4262 reg_last_reload_reg[reg] = 0;
4266 /* The following HARD_REG_SETs indicate when each hard register is
4267 used for a reload of various parts of the current insn. */
4269 /* If reg is unavailable for all reloads. */
4270 static HARD_REG_SET reload_reg_unavailable;
4271 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4272 static HARD_REG_SET reload_reg_used;
4273 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4274 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4275 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4276 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4277 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4278 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4279 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4280 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4281 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4282 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4283 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4284 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4285 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4286 static HARD_REG_SET reload_reg_used_in_op_addr;
4287 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4288 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4289 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4290 static HARD_REG_SET reload_reg_used_in_insn;
4291 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4292 static HARD_REG_SET reload_reg_used_in_other_addr;
4294 /* If reg is in use as a reload reg for any sort of reload. */
4295 static HARD_REG_SET reload_reg_used_at_all;
4297 /* If reg is use as an inherited reload. We just mark the first register
4299 static HARD_REG_SET reload_reg_used_for_inherit;
4301 /* Records which hard regs are used in any way, either as explicit use or
4302 by being allocated to a pseudo during any point of the current insn. */
4303 static HARD_REG_SET reg_used_in_insn;
4305 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4306 TYPE. MODE is used to indicate how many consecutive regs are
4310 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4311 enum machine_mode mode)
4313 unsigned int nregs = hard_regno_nregs[regno][mode];
4316 for (i = regno; i < nregs + regno; i++)
4321 SET_HARD_REG_BIT (reload_reg_used, i);
4324 case RELOAD_FOR_INPUT_ADDRESS:
4325 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4328 case RELOAD_FOR_INPADDR_ADDRESS:
4329 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4332 case RELOAD_FOR_OUTPUT_ADDRESS:
4333 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4336 case RELOAD_FOR_OUTADDR_ADDRESS:
4337 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4340 case RELOAD_FOR_OPERAND_ADDRESS:
4341 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4344 case RELOAD_FOR_OPADDR_ADDR:
4345 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4348 case RELOAD_FOR_OTHER_ADDRESS:
4349 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4352 case RELOAD_FOR_INPUT:
4353 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4356 case RELOAD_FOR_OUTPUT:
4357 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4360 case RELOAD_FOR_INSN:
4361 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4365 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4369 /* Similarly, but show REGNO is no longer in use for a reload. */
4372 clear_reload_reg_in_use (unsigned int regno, int opnum,
4373 enum reload_type type, enum machine_mode mode)
4375 unsigned int nregs = hard_regno_nregs[regno][mode];
4376 unsigned int start_regno, end_regno, r;
4378 /* A complication is that for some reload types, inheritance might
4379 allow multiple reloads of the same types to share a reload register.
4380 We set check_opnum if we have to check only reloads with the same
4381 operand number, and check_any if we have to check all reloads. */
4382 int check_opnum = 0;
4384 HARD_REG_SET *used_in_set;
4389 used_in_set = &reload_reg_used;
4392 case RELOAD_FOR_INPUT_ADDRESS:
4393 used_in_set = &reload_reg_used_in_input_addr[opnum];
4396 case RELOAD_FOR_INPADDR_ADDRESS:
4398 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4401 case RELOAD_FOR_OUTPUT_ADDRESS:
4402 used_in_set = &reload_reg_used_in_output_addr[opnum];
4405 case RELOAD_FOR_OUTADDR_ADDRESS:
4407 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4410 case RELOAD_FOR_OPERAND_ADDRESS:
4411 used_in_set = &reload_reg_used_in_op_addr;
4414 case RELOAD_FOR_OPADDR_ADDR:
4416 used_in_set = &reload_reg_used_in_op_addr_reload;
4419 case RELOAD_FOR_OTHER_ADDRESS:
4420 used_in_set = &reload_reg_used_in_other_addr;
4424 case RELOAD_FOR_INPUT:
4425 used_in_set = &reload_reg_used_in_input[opnum];
4428 case RELOAD_FOR_OUTPUT:
4429 used_in_set = &reload_reg_used_in_output[opnum];
4432 case RELOAD_FOR_INSN:
4433 used_in_set = &reload_reg_used_in_insn;
4438 /* We resolve conflicts with remaining reloads of the same type by
4439 excluding the intervals of reload registers by them from the
4440 interval of freed reload registers. Since we only keep track of
4441 one set of interval bounds, we might have to exclude somewhat
4442 more than what would be necessary if we used a HARD_REG_SET here.
4443 But this should only happen very infrequently, so there should
4444 be no reason to worry about it. */
4446 start_regno = regno;
4447 end_regno = regno + nregs;
4448 if (check_opnum || check_any)
4450 for (i = n_reloads - 1; i >= 0; i--)
4452 if (rld[i].when_needed == type
4453 && (check_any || rld[i].opnum == opnum)
4456 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4457 unsigned int conflict_end
4459 + hard_regno_nregs[conflict_start][rld[i].mode]);
4461 /* If there is an overlap with the first to-be-freed register,
4462 adjust the interval start. */
4463 if (conflict_start <= start_regno && conflict_end > start_regno)
4464 start_regno = conflict_end;
4465 /* Otherwise, if there is a conflict with one of the other
4466 to-be-freed registers, adjust the interval end. */
4467 if (conflict_start > start_regno && conflict_start < end_regno)
4468 end_regno = conflict_start;
4473 for (r = start_regno; r < end_regno; r++)
4474 CLEAR_HARD_REG_BIT (*used_in_set, r);
4477 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4478 specified by OPNUM and TYPE. */
4481 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4485 /* In use for a RELOAD_OTHER means it's not available for anything. */
4486 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4487 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4493 /* In use for anything means we can't use it for RELOAD_OTHER. */
4494 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4495 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4496 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4497 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4500 for (i = 0; i < reload_n_operands; i++)
4501 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4502 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4503 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4504 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4505 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4506 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4511 case RELOAD_FOR_INPUT:
4512 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4513 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4516 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4519 /* If it is used for some other input, can't use it. */
4520 for (i = 0; i < reload_n_operands; i++)
4521 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4524 /* If it is used in a later operand's address, can't use it. */
4525 for (i = opnum + 1; i < reload_n_operands; i++)
4526 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4527 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4532 case RELOAD_FOR_INPUT_ADDRESS:
4533 /* Can't use a register if it is used for an input address for this
4534 operand or used as an input in an earlier one. */
4535 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4536 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4539 for (i = 0; i < opnum; i++)
4540 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4545 case RELOAD_FOR_INPADDR_ADDRESS:
4546 /* Can't use a register if it is used for an input address
4547 for this operand or used as an input in an earlier
4549 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4552 for (i = 0; i < opnum; i++)
4553 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4558 case RELOAD_FOR_OUTPUT_ADDRESS:
4559 /* Can't use a register if it is used for an output address for this
4560 operand or used as an output in this or a later operand. Note
4561 that multiple output operands are emitted in reverse order, so
4562 the conflicting ones are those with lower indices. */
4563 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4566 for (i = 0; i <= opnum; i++)
4567 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4572 case RELOAD_FOR_OUTADDR_ADDRESS:
4573 /* Can't use a register if it is used for an output address
4574 for this operand or used as an output in this or a
4575 later operand. Note that multiple output operands are
4576 emitted in reverse order, so the conflicting ones are
4577 those with lower indices. */
4578 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4581 for (i = 0; i <= opnum; i++)
4582 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4587 case RELOAD_FOR_OPERAND_ADDRESS:
4588 for (i = 0; i < reload_n_operands; i++)
4589 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4592 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4593 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4595 case RELOAD_FOR_OPADDR_ADDR:
4596 for (i = 0; i < reload_n_operands; i++)
4597 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4600 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4602 case RELOAD_FOR_OUTPUT:
4603 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4604 outputs, or an operand address for this or an earlier output.
4605 Note that multiple output operands are emitted in reverse order,
4606 so the conflicting ones are those with higher indices. */
4607 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4610 for (i = 0; i < reload_n_operands; i++)
4611 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4614 for (i = opnum; i < reload_n_operands; i++)
4615 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4616 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4621 case RELOAD_FOR_INSN:
4622 for (i = 0; i < reload_n_operands; i++)
4623 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4624 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4627 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4628 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4630 case RELOAD_FOR_OTHER_ADDRESS:
4631 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4638 /* Return 1 if the value in reload reg REGNO, as used by a reload
4639 needed for the part of the insn specified by OPNUM and TYPE,
4640 is still available in REGNO at the end of the insn.
4642 We can assume that the reload reg was already tested for availability
4643 at the time it is needed, and we should not check this again,
4644 in case the reg has already been marked in use. */
4647 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4654 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4655 its value must reach the end. */
4658 /* If this use is for part of the insn,
4659 its value reaches if no subsequent part uses the same register.
4660 Just like the above function, don't try to do this with lots
4663 case RELOAD_FOR_OTHER_ADDRESS:
4664 /* Here we check for everything else, since these don't conflict
4665 with anything else and everything comes later. */
4667 for (i = 0; i < reload_n_operands; i++)
4668 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4669 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4670 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4671 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4672 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4673 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4676 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4677 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4678 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4679 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4681 case RELOAD_FOR_INPUT_ADDRESS:
4682 case RELOAD_FOR_INPADDR_ADDRESS:
4683 /* Similar, except that we check only for this and subsequent inputs
4684 and the address of only subsequent inputs and we do not need
4685 to check for RELOAD_OTHER objects since they are known not to
4688 for (i = opnum; i < reload_n_operands; i++)
4689 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4692 for (i = opnum + 1; i < reload_n_operands; i++)
4693 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4694 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4697 for (i = 0; i < reload_n_operands; i++)
4698 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4699 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4700 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4703 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4706 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4707 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4708 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4710 case RELOAD_FOR_INPUT:
4711 /* Similar to input address, except we start at the next operand for
4712 both input and input address and we do not check for
4713 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4716 for (i = opnum + 1; i < reload_n_operands; i++)
4717 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4718 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4719 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4722 /* ... fall through ... */
4724 case RELOAD_FOR_OPERAND_ADDRESS:
4725 /* Check outputs and their addresses. */
4727 for (i = 0; i < reload_n_operands; i++)
4728 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4729 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4730 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4733 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4735 case RELOAD_FOR_OPADDR_ADDR:
4736 for (i = 0; i < reload_n_operands; i++)
4737 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4738 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4739 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4742 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4743 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4744 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4746 case RELOAD_FOR_INSN:
4747 /* These conflict with other outputs with RELOAD_OTHER. So
4748 we need only check for output addresses. */
4750 opnum = reload_n_operands;
4752 /* ... fall through ... */
4754 case RELOAD_FOR_OUTPUT:
4755 case RELOAD_FOR_OUTPUT_ADDRESS:
4756 case RELOAD_FOR_OUTADDR_ADDRESS:
4757 /* We already know these can't conflict with a later output. So the
4758 only thing to check are later output addresses.
4759 Note that multiple output operands are emitted in reverse order,
4760 so the conflicting ones are those with lower indices. */
4761 for (i = 0; i < opnum; i++)
4762 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4763 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4773 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4776 This function uses the same algorithm as reload_reg_free_p above. */
4779 reloads_conflict (int r1, int r2)
4781 enum reload_type r1_type = rld[r1].when_needed;
4782 enum reload_type r2_type = rld[r2].when_needed;
4783 int r1_opnum = rld[r1].opnum;
4784 int r2_opnum = rld[r2].opnum;
4786 /* RELOAD_OTHER conflicts with everything. */
4787 if (r2_type == RELOAD_OTHER)
4790 /* Otherwise, check conflicts differently for each type. */
4794 case RELOAD_FOR_INPUT:
4795 return (r2_type == RELOAD_FOR_INSN
4796 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4797 || r2_type == RELOAD_FOR_OPADDR_ADDR
4798 || r2_type == RELOAD_FOR_INPUT
4799 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4800 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4801 && r2_opnum > r1_opnum));
4803 case RELOAD_FOR_INPUT_ADDRESS:
4804 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4805 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4807 case RELOAD_FOR_INPADDR_ADDRESS:
4808 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4809 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4811 case RELOAD_FOR_OUTPUT_ADDRESS:
4812 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4813 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4815 case RELOAD_FOR_OUTADDR_ADDRESS:
4816 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4817 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4819 case RELOAD_FOR_OPERAND_ADDRESS:
4820 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4821 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4823 case RELOAD_FOR_OPADDR_ADDR:
4824 return (r2_type == RELOAD_FOR_INPUT
4825 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4827 case RELOAD_FOR_OUTPUT:
4828 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4829 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4830 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4831 && r2_opnum >= r1_opnum));
4833 case RELOAD_FOR_INSN:
4834 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4835 || r2_type == RELOAD_FOR_INSN
4836 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4838 case RELOAD_FOR_OTHER_ADDRESS:
4839 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4849 /* Indexed by reload number, 1 if incoming value
4850 inherited from previous insns. */
4851 static char reload_inherited[MAX_RELOADS];
4853 /* For an inherited reload, this is the insn the reload was inherited from,
4854 if we know it. Otherwise, this is 0. */
4855 static rtx reload_inheritance_insn[MAX_RELOADS];
4857 /* If nonzero, this is a place to get the value of the reload,
4858 rather than using reload_in. */
4859 static rtx reload_override_in[MAX_RELOADS];
4861 /* For each reload, the hard register number of the register used,
4862 or -1 if we did not need a register for this reload. */
4863 static int reload_spill_index[MAX_RELOADS];
4865 /* Subroutine of free_for_value_p, used to check a single register.
4866 START_REGNO is the starting regno of the full reload register
4867 (possibly comprising multiple hard registers) that we are considering. */
4870 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4871 enum reload_type type, rtx value, rtx out,
4872 int reloadnum, int ignore_address_reloads)
4875 /* Set if we see an input reload that must not share its reload register
4876 with any new earlyclobber, but might otherwise share the reload
4877 register with an output or input-output reload. */
4878 int check_earlyclobber = 0;
4882 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4885 if (out == const0_rtx)
4891 /* We use some pseudo 'time' value to check if the lifetimes of the
4892 new register use would overlap with the one of a previous reload
4893 that is not read-only or uses a different value.
4894 The 'time' used doesn't have to be linear in any shape or form, just
4896 Some reload types use different 'buckets' for each operand.
4897 So there are MAX_RECOG_OPERANDS different time values for each
4899 We compute TIME1 as the time when the register for the prospective
4900 new reload ceases to be live, and TIME2 for each existing
4901 reload as the time when that the reload register of that reload
4903 Where there is little to be gained by exact lifetime calculations,
4904 we just make conservative assumptions, i.e. a longer lifetime;
4905 this is done in the 'default:' cases. */
4908 case RELOAD_FOR_OTHER_ADDRESS:
4909 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4910 time1 = copy ? 0 : 1;
4913 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4915 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4916 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4917 respectively, to the time values for these, we get distinct time
4918 values. To get distinct time values for each operand, we have to
4919 multiply opnum by at least three. We round that up to four because
4920 multiply by four is often cheaper. */
4921 case RELOAD_FOR_INPADDR_ADDRESS:
4922 time1 = opnum * 4 + 2;
4924 case RELOAD_FOR_INPUT_ADDRESS:
4925 time1 = opnum * 4 + 3;
4927 case RELOAD_FOR_INPUT:
4928 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4929 executes (inclusive). */
4930 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4932 case RELOAD_FOR_OPADDR_ADDR:
4934 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4935 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4937 case RELOAD_FOR_OPERAND_ADDRESS:
4938 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4940 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4942 case RELOAD_FOR_OUTADDR_ADDRESS:
4943 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4945 case RELOAD_FOR_OUTPUT_ADDRESS:
4946 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4949 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4952 for (i = 0; i < n_reloads; i++)
4954 rtx reg = rld[i].reg_rtx;
4955 if (reg && REG_P (reg)
4956 && ((unsigned) regno - true_regnum (reg)
4957 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
4960 rtx other_input = rld[i].in;
4962 /* If the other reload loads the same input value, that
4963 will not cause a conflict only if it's loading it into
4964 the same register. */
4965 if (true_regnum (reg) != start_regno)
4966 other_input = NULL_RTX;
4967 if (! other_input || ! rtx_equal_p (other_input, value)
4968 || rld[i].out || out)
4971 switch (rld[i].when_needed)
4973 case RELOAD_FOR_OTHER_ADDRESS:
4976 case RELOAD_FOR_INPADDR_ADDRESS:
4977 /* find_reloads makes sure that a
4978 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4979 by at most one - the first -
4980 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4981 address reload is inherited, the address address reload
4982 goes away, so we can ignore this conflict. */
4983 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4984 && ignore_address_reloads
4985 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4986 Then the address address is still needed to store
4987 back the new address. */
4988 && ! rld[reloadnum].out)
4990 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4991 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4993 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4994 && ignore_address_reloads
4995 /* Unless we are reloading an auto_inc expression. */
4996 && ! rld[reloadnum].out)
4998 time2 = rld[i].opnum * 4 + 2;
5000 case RELOAD_FOR_INPUT_ADDRESS:
5001 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5002 && ignore_address_reloads
5003 && ! rld[reloadnum].out)
5005 time2 = rld[i].opnum * 4 + 3;
5007 case RELOAD_FOR_INPUT:
5008 time2 = rld[i].opnum * 4 + 4;
5009 check_earlyclobber = 1;
5011 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5012 == MAX_RECOG_OPERAND * 4 */
5013 case RELOAD_FOR_OPADDR_ADDR:
5014 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5015 && ignore_address_reloads
5016 && ! rld[reloadnum].out)
5018 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5020 case RELOAD_FOR_OPERAND_ADDRESS:
5021 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5022 check_earlyclobber = 1;
5024 case RELOAD_FOR_INSN:
5025 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5027 case RELOAD_FOR_OUTPUT:
5028 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5029 instruction is executed. */
5030 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5032 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5033 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5035 case RELOAD_FOR_OUTADDR_ADDRESS:
5036 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5037 && ignore_address_reloads
5038 && ! rld[reloadnum].out)
5040 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5042 case RELOAD_FOR_OUTPUT_ADDRESS:
5043 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5046 /* If there is no conflict in the input part, handle this
5047 like an output reload. */
5048 if (! rld[i].in || rtx_equal_p (other_input, value))
5050 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5051 /* Earlyclobbered outputs must conflict with inputs. */
5052 if (earlyclobber_operand_p (rld[i].out))
5053 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5058 /* RELOAD_OTHER might be live beyond instruction execution,
5059 but this is not obvious when we set time2 = 1. So check
5060 here if there might be a problem with the new reload
5061 clobbering the register used by the RELOAD_OTHER. */
5069 && (! rld[i].in || rld[i].out
5070 || ! rtx_equal_p (other_input, value)))
5071 || (out && rld[reloadnum].out_reg
5072 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5078 /* Earlyclobbered outputs must conflict with inputs. */
5079 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5085 /* Return 1 if the value in reload reg REGNO, as used by a reload
5086 needed for the part of the insn specified by OPNUM and TYPE,
5087 may be used to load VALUE into it.
5089 MODE is the mode in which the register is used, this is needed to
5090 determine how many hard regs to test.
5092 Other read-only reloads with the same value do not conflict
5093 unless OUT is nonzero and these other reloads have to live while
5094 output reloads live.
5095 If OUT is CONST0_RTX, this is a special case: it means that the
5096 test should not be for using register REGNO as reload register, but
5097 for copying from register REGNO into the reload register.
5099 RELOADNUM is the number of the reload we want to load this value for;
5100 a reload does not conflict with itself.
5102 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5103 reloads that load an address for the very reload we are considering.
5105 The caller has to make sure that there is no conflict with the return
5109 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5110 enum reload_type type, rtx value, rtx out, int reloadnum,
5111 int ignore_address_reloads)
5113 int nregs = hard_regno_nregs[regno][mode];
5115 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5116 value, out, reloadnum,
5117 ignore_address_reloads))
5122 /* Return nonzero if the rtx X is invariant over the current function. */
5123 /* ??? Actually, the places where we use this expect exactly what is
5124 tested here, and not everything that is function invariant. In
5125 particular, the frame pointer and arg pointer are special cased;
5126 pic_offset_table_rtx is not, and we must not spill these things to
5130 function_invariant_p (rtx x)
5134 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5136 if (GET_CODE (x) == PLUS
5137 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5138 && CONSTANT_P (XEXP (x, 1)))
5143 /* Determine whether the reload reg X overlaps any rtx'es used for
5144 overriding inheritance. Return nonzero if so. */
5147 conflicts_with_override (rtx x)
5150 for (i = 0; i < n_reloads; i++)
5151 if (reload_override_in[i]
5152 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5157 /* Give an error message saying we failed to find a reload for INSN,
5158 and clear out reload R. */
5160 failed_reload (rtx insn, int r)
5162 if (asm_noperands (PATTERN (insn)) < 0)
5163 /* It's the compiler's fault. */
5164 fatal_insn ("could not find a spill register", insn);
5166 /* It's the user's fault; the operand's mode and constraint
5167 don't match. Disable this reload so we don't crash in final. */
5168 error_for_asm (insn,
5169 "%<asm%> operand constraint incompatible with operand size");
5173 rld[r].optional = 1;
5174 rld[r].secondary_p = 1;
5177 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5178 for reload R. If it's valid, get an rtx for it. Return nonzero if
5181 set_reload_reg (int i, int r)
5184 rtx reg = spill_reg_rtx[i];
5186 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5187 spill_reg_rtx[i] = reg
5188 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5190 regno = true_regnum (reg);
5192 /* Detect when the reload reg can't hold the reload mode.
5193 This used to be one `if', but Sequent compiler can't handle that. */
5194 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5196 enum machine_mode test_mode = VOIDmode;
5198 test_mode = GET_MODE (rld[r].in);
5199 /* If rld[r].in has VOIDmode, it means we will load it
5200 in whatever mode the reload reg has: to wit, rld[r].mode.
5201 We have already tested that for validity. */
5202 /* Aside from that, we need to test that the expressions
5203 to reload from or into have modes which are valid for this
5204 reload register. Otherwise the reload insns would be invalid. */
5205 if (! (rld[r].in != 0 && test_mode != VOIDmode
5206 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5207 if (! (rld[r].out != 0
5208 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5210 /* The reg is OK. */
5213 /* Mark as in use for this insn the reload regs we use
5215 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5216 rld[r].when_needed, rld[r].mode);
5218 rld[r].reg_rtx = reg;
5219 reload_spill_index[r] = spill_regs[i];
5226 /* Find a spill register to use as a reload register for reload R.
5227 LAST_RELOAD is nonzero if this is the last reload for the insn being
5230 Set rld[R].reg_rtx to the register allocated.
5232 We return 1 if successful, or 0 if we couldn't find a spill reg and
5233 we didn't change anything. */
5236 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5241 /* If we put this reload ahead, thinking it is a group,
5242 then insist on finding a group. Otherwise we can grab a
5243 reg that some other reload needs.
5244 (That can happen when we have a 68000 DATA_OR_FP_REG
5245 which is a group of data regs or one fp reg.)
5246 We need not be so restrictive if there are no more reloads
5249 ??? Really it would be nicer to have smarter handling
5250 for that kind of reg class, where a problem like this is normal.
5251 Perhaps those classes should be avoided for reloading
5252 by use of more alternatives. */
5254 int force_group = rld[r].nregs > 1 && ! last_reload;
5256 /* If we want a single register and haven't yet found one,
5257 take any reg in the right class and not in use.
5258 If we want a consecutive group, here is where we look for it.
5260 We use two passes so we can first look for reload regs to
5261 reuse, which are already in use for other reloads in this insn,
5262 and only then use additional registers.
5263 I think that maximizing reuse is needed to make sure we don't
5264 run out of reload regs. Suppose we have three reloads, and
5265 reloads A and B can share regs. These need two regs.
5266 Suppose A and B are given different regs.
5267 That leaves none for C. */
5268 for (pass = 0; pass < 2; pass++)
5270 /* I is the index in spill_regs.
5271 We advance it round-robin between insns to use all spill regs
5272 equally, so that inherited reloads have a chance
5273 of leapfrogging each other. */
5277 for (count = 0; count < n_spills; count++)
5279 int class = (int) rld[r].class;
5285 regnum = spill_regs[i];
5287 if ((reload_reg_free_p (regnum, rld[r].opnum,
5290 /* We check reload_reg_used to make sure we
5291 don't clobber the return register. */
5292 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5293 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5294 rld[r].when_needed, rld[r].in,
5296 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5297 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5298 /* Look first for regs to share, then for unshared. But
5299 don't share regs used for inherited reloads; they are
5300 the ones we want to preserve. */
5302 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5304 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5307 int nr = hard_regno_nregs[regnum][rld[r].mode];
5308 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5309 (on 68000) got us two FP regs. If NR is 1,
5310 we would reject both of them. */
5313 /* If we need only one reg, we have already won. */
5316 /* But reject a single reg if we demand a group. */
5321 /* Otherwise check that as many consecutive regs as we need
5322 are available here. */
5325 int regno = regnum + nr - 1;
5326 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5327 && spill_reg_order[regno] >= 0
5328 && reload_reg_free_p (regno, rld[r].opnum,
5329 rld[r].when_needed)))
5338 /* If we found something on pass 1, omit pass 2. */
5339 if (count < n_spills)
5343 /* We should have found a spill register by now. */
5344 if (count >= n_spills)
5347 /* I is the index in SPILL_REG_RTX of the reload register we are to
5348 allocate. Get an rtx for it and find its register number. */
5350 return set_reload_reg (i, r);
5353 /* Initialize all the tables needed to allocate reload registers.
5354 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5355 is the array we use to restore the reg_rtx field for every reload. */
5358 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5362 for (i = 0; i < n_reloads; i++)
5363 rld[i].reg_rtx = save_reload_reg_rtx[i];
5365 memset (reload_inherited, 0, MAX_RELOADS);
5366 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5367 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5369 CLEAR_HARD_REG_SET (reload_reg_used);
5370 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5371 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5372 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5373 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5374 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5376 CLEAR_HARD_REG_SET (reg_used_in_insn);
5379 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5380 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5381 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5382 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5383 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5384 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5387 for (i = 0; i < reload_n_operands; i++)
5389 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5390 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5391 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5392 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5393 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5394 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5397 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5399 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5401 for (i = 0; i < n_reloads; i++)
5402 /* If we have already decided to use a certain register,
5403 don't use it in another way. */
5405 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5406 rld[i].when_needed, rld[i].mode);
5409 /* Assign hard reg targets for the pseudo-registers we must reload
5410 into hard regs for this insn.
5411 Also output the instructions to copy them in and out of the hard regs.
5413 For machines with register classes, we are responsible for
5414 finding a reload reg in the proper class. */
5417 choose_reload_regs (struct insn_chain *chain)
5419 rtx insn = chain->insn;
5421 unsigned int max_group_size = 1;
5422 enum reg_class group_class = NO_REGS;
5423 int pass, win, inheritance;
5425 rtx save_reload_reg_rtx[MAX_RELOADS];
5427 /* In order to be certain of getting the registers we need,
5428 we must sort the reloads into order of increasing register class.
5429 Then our grabbing of reload registers will parallel the process
5430 that provided the reload registers.
5432 Also note whether any of the reloads wants a consecutive group of regs.
5433 If so, record the maximum size of the group desired and what
5434 register class contains all the groups needed by this insn. */
5436 for (j = 0; j < n_reloads; j++)
5438 reload_order[j] = j;
5439 reload_spill_index[j] = -1;
5441 if (rld[j].nregs > 1)
5443 max_group_size = MAX (rld[j].nregs, max_group_size);
5445 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5448 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5452 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5454 /* If -O, try first with inheritance, then turning it off.
5455 If not -O, don't do inheritance.
5456 Using inheritance when not optimizing leads to paradoxes
5457 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5458 because one side of the comparison might be inherited. */
5460 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5462 choose_reload_regs_init (chain, save_reload_reg_rtx);
5464 /* Process the reloads in order of preference just found.
5465 Beyond this point, subregs can be found in reload_reg_rtx.
5467 This used to look for an existing reloaded home for all of the
5468 reloads, and only then perform any new reloads. But that could lose
5469 if the reloads were done out of reg-class order because a later
5470 reload with a looser constraint might have an old home in a register
5471 needed by an earlier reload with a tighter constraint.
5473 To solve this, we make two passes over the reloads, in the order
5474 described above. In the first pass we try to inherit a reload
5475 from a previous insn. If there is a later reload that needs a
5476 class that is a proper subset of the class being processed, we must
5477 also allocate a spill register during the first pass.
5479 Then make a second pass over the reloads to allocate any reloads
5480 that haven't been given registers yet. */
5482 for (j = 0; j < n_reloads; j++)
5484 int r = reload_order[j];
5485 rtx search_equiv = NULL_RTX;
5487 /* Ignore reloads that got marked inoperative. */
5488 if (rld[r].out == 0 && rld[r].in == 0
5489 && ! rld[r].secondary_p)
5492 /* If find_reloads chose to use reload_in or reload_out as a reload
5493 register, we don't need to chose one. Otherwise, try even if it
5494 found one since we might save an insn if we find the value lying
5496 Try also when reload_in is a pseudo without a hard reg. */
5497 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5498 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5499 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5500 && !MEM_P (rld[r].in)
5501 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5504 #if 0 /* No longer needed for correct operation.
5505 It might give better code, or might not; worth an experiment? */
5506 /* If this is an optional reload, we can't inherit from earlier insns
5507 until we are sure that any non-optional reloads have been allocated.
5508 The following code takes advantage of the fact that optional reloads
5509 are at the end of reload_order. */
5510 if (rld[r].optional != 0)
5511 for (i = 0; i < j; i++)
5512 if ((rld[reload_order[i]].out != 0
5513 || rld[reload_order[i]].in != 0
5514 || rld[reload_order[i]].secondary_p)
5515 && ! rld[reload_order[i]].optional
5516 && rld[reload_order[i]].reg_rtx == 0)
5517 allocate_reload_reg (chain, reload_order[i], 0);
5520 /* First see if this pseudo is already available as reloaded
5521 for a previous insn. We cannot try to inherit for reloads
5522 that are smaller than the maximum number of registers needed
5523 for groups unless the register we would allocate cannot be used
5526 We could check here to see if this is a secondary reload for
5527 an object that is already in a register of the desired class.
5528 This would avoid the need for the secondary reload register.
5529 But this is complex because we can't easily determine what
5530 objects might want to be loaded via this reload. So let a
5531 register be allocated here. In `emit_reload_insns' we suppress
5532 one of the loads in the case described above. */
5538 enum machine_mode mode = VOIDmode;
5542 else if (REG_P (rld[r].in))
5544 regno = REGNO (rld[r].in);
5545 mode = GET_MODE (rld[r].in);
5547 else if (REG_P (rld[r].in_reg))
5549 regno = REGNO (rld[r].in_reg);
5550 mode = GET_MODE (rld[r].in_reg);
5552 else if (GET_CODE (rld[r].in_reg) == SUBREG
5553 && REG_P (SUBREG_REG (rld[r].in_reg)))
5555 byte = SUBREG_BYTE (rld[r].in_reg);
5556 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5557 if (regno < FIRST_PSEUDO_REGISTER)
5558 regno = subreg_regno (rld[r].in_reg);
5559 mode = GET_MODE (rld[r].in_reg);
5562 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
5563 && REG_P (XEXP (rld[r].in_reg, 0)))
5565 regno = REGNO (XEXP (rld[r].in_reg, 0));
5566 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5567 rld[r].out = rld[r].in;
5571 /* This won't work, since REGNO can be a pseudo reg number.
5572 Also, it takes much more hair to keep track of all the things
5573 that can invalidate an inherited reload of part of a pseudoreg. */
5574 else if (GET_CODE (rld[r].in) == SUBREG
5575 && REG_P (SUBREG_REG (rld[r].in)))
5576 regno = subreg_regno (rld[r].in);
5579 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5581 enum reg_class class = rld[r].class, last_class;
5582 rtx last_reg = reg_last_reload_reg[regno];
5583 enum machine_mode need_mode;
5585 i = REGNO (last_reg);
5586 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5587 last_class = REGNO_REG_CLASS (i);
5593 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
5594 + byte * BITS_PER_UNIT,
5595 GET_MODE_CLASS (mode));
5597 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5598 >= GET_MODE_SIZE (need_mode))
5599 #ifdef CANNOT_CHANGE_MODE_CLASS
5600 /* Verify that the register in "i" can be obtained
5602 && !REG_CANNOT_CHANGE_MODE_P (REGNO (last_reg),
5603 GET_MODE (last_reg),
5606 && reg_reloaded_contents[i] == regno
5607 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5608 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5609 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5610 /* Even if we can't use this register as a reload
5611 register, we might use it for reload_override_in,
5612 if copying it to the desired class is cheap
5614 || ((REGISTER_MOVE_COST (mode, last_class, class)
5615 < MEMORY_MOVE_COST (mode, class, 1))
5616 && (secondary_reload_class (1, class, mode,
5619 #ifdef SECONDARY_MEMORY_NEEDED
5620 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5625 && (rld[r].nregs == max_group_size
5626 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5628 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5629 rld[r].when_needed, rld[r].in,
5632 /* If a group is needed, verify that all the subsequent
5633 registers still have their values intact. */
5634 int nr = hard_regno_nregs[i][rld[r].mode];
5637 for (k = 1; k < nr; k++)
5638 if (reg_reloaded_contents[i + k] != regno
5639 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5647 last_reg = (GET_MODE (last_reg) == mode
5648 ? last_reg : gen_rtx_REG (mode, i));
5651 for (k = 0; k < nr; k++)
5652 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5655 /* We found a register that contains the
5656 value we need. If this register is the
5657 same as an `earlyclobber' operand of the
5658 current insn, just mark it as a place to
5659 reload from since we can't use it as the
5660 reload register itself. */
5662 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5663 if (reg_overlap_mentioned_for_reload_p
5664 (reg_last_reload_reg[regno],
5665 reload_earlyclobbers[i1]))
5668 if (i1 != n_earlyclobbers
5669 || ! (free_for_value_p (i, rld[r].mode,
5671 rld[r].when_needed, rld[r].in,
5673 /* Don't use it if we'd clobber a pseudo reg. */
5674 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5676 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5677 /* Don't clobber the frame pointer. */
5678 || (i == HARD_FRAME_POINTER_REGNUM
5679 && frame_pointer_needed
5681 /* Don't really use the inherited spill reg
5682 if we need it wider than we've got it. */
5683 || (GET_MODE_SIZE (rld[r].mode)
5684 > GET_MODE_SIZE (mode))
5687 /* If find_reloads chose reload_out as reload
5688 register, stay with it - that leaves the
5689 inherited register for subsequent reloads. */
5690 || (rld[r].out && rld[r].reg_rtx
5691 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5693 if (! rld[r].optional)
5695 reload_override_in[r] = last_reg;
5696 reload_inheritance_insn[r]
5697 = reg_reloaded_insn[i];
5703 /* We can use this as a reload reg. */
5704 /* Mark the register as in use for this part of
5706 mark_reload_reg_in_use (i,
5710 rld[r].reg_rtx = last_reg;
5711 reload_inherited[r] = 1;
5712 reload_inheritance_insn[r]
5713 = reg_reloaded_insn[i];
5714 reload_spill_index[r] = i;
5715 for (k = 0; k < nr; k++)
5716 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5724 /* Here's another way to see if the value is already lying around. */
5727 && ! reload_inherited[r]
5729 && (CONSTANT_P (rld[r].in)
5730 || GET_CODE (rld[r].in) == PLUS
5731 || REG_P (rld[r].in)
5732 || MEM_P (rld[r].in))
5733 && (rld[r].nregs == max_group_size
5734 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5735 search_equiv = rld[r].in;
5736 /* If this is an output reload from a simple move insn, look
5737 if an equivalence for the input is available. */
5738 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5740 rtx set = single_set (insn);
5743 && rtx_equal_p (rld[r].out, SET_DEST (set))
5744 && CONSTANT_P (SET_SRC (set)))
5745 search_equiv = SET_SRC (set);
5751 = find_equiv_reg (search_equiv, insn, rld[r].class,
5752 -1, NULL, 0, rld[r].mode);
5758 regno = REGNO (equiv);
5761 /* This must be a SUBREG of a hard register.
5762 Make a new REG since this might be used in an
5763 address and not all machines support SUBREGs
5765 gcc_assert (GET_CODE (equiv) == SUBREG);
5766 regno = subreg_regno (equiv);
5767 equiv = gen_rtx_REG (rld[r].mode, regno);
5768 /* If we choose EQUIV as the reload register, but the
5769 loop below decides to cancel the inheritance, we'll
5770 end up reloading EQUIV in rld[r].mode, not the mode
5771 it had originally. That isn't safe when EQUIV isn't
5772 available as a spill register since its value might
5773 still be live at this point. */
5774 for (i = regno; i < regno + (int) rld[r].nregs; i++)
5775 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
5780 /* If we found a spill reg, reject it unless it is free
5781 and of the desired class. */
5785 int bad_for_class = 0;
5786 int max_regno = regno + rld[r].nregs;
5788 for (i = regno; i < max_regno; i++)
5790 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5792 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5797 && ! free_for_value_p (regno, rld[r].mode,
5798 rld[r].opnum, rld[r].when_needed,
5799 rld[r].in, rld[r].out, r, 1))
5804 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5807 /* We found a register that contains the value we need.
5808 If this register is the same as an `earlyclobber' operand
5809 of the current insn, just mark it as a place to reload from
5810 since we can't use it as the reload register itself. */
5813 for (i = 0; i < n_earlyclobbers; i++)
5814 if (reg_overlap_mentioned_for_reload_p (equiv,
5815 reload_earlyclobbers[i]))
5817 if (! rld[r].optional)
5818 reload_override_in[r] = equiv;
5823 /* If the equiv register we have found is explicitly clobbered
5824 in the current insn, it depends on the reload type if we
5825 can use it, use it for reload_override_in, or not at all.
5826 In particular, we then can't use EQUIV for a
5827 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5831 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
5832 switch (rld[r].when_needed)
5834 case RELOAD_FOR_OTHER_ADDRESS:
5835 case RELOAD_FOR_INPADDR_ADDRESS:
5836 case RELOAD_FOR_INPUT_ADDRESS:
5837 case RELOAD_FOR_OPADDR_ADDR:
5840 case RELOAD_FOR_INPUT:
5841 case RELOAD_FOR_OPERAND_ADDRESS:
5842 if (! rld[r].optional)
5843 reload_override_in[r] = equiv;
5849 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5850 switch (rld[r].when_needed)
5852 case RELOAD_FOR_OTHER_ADDRESS:
5853 case RELOAD_FOR_INPADDR_ADDRESS:
5854 case RELOAD_FOR_INPUT_ADDRESS:
5855 case RELOAD_FOR_OPADDR_ADDR:
5856 case RELOAD_FOR_OPERAND_ADDRESS:
5857 case RELOAD_FOR_INPUT:
5860 if (! rld[r].optional)
5861 reload_override_in[r] = equiv;
5869 /* If we found an equivalent reg, say no code need be generated
5870 to load it, and use it as our reload reg. */
5872 && (regno != HARD_FRAME_POINTER_REGNUM
5873 || !frame_pointer_needed))
5875 int nr = hard_regno_nregs[regno][rld[r].mode];
5877 rld[r].reg_rtx = equiv;
5878 reload_inherited[r] = 1;
5880 /* If reg_reloaded_valid is not set for this register,
5881 there might be a stale spill_reg_store lying around.
5882 We must clear it, since otherwise emit_reload_insns
5883 might delete the store. */
5884 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5885 spill_reg_store[regno] = NULL_RTX;
5886 /* If any of the hard registers in EQUIV are spill
5887 registers, mark them as in use for this insn. */
5888 for (k = 0; k < nr; k++)
5890 i = spill_reg_order[regno + k];
5893 mark_reload_reg_in_use (regno, rld[r].opnum,
5896 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5903 /* If we found a register to use already, or if this is an optional
5904 reload, we are done. */
5905 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5909 /* No longer needed for correct operation. Might or might
5910 not give better code on the average. Want to experiment? */
5912 /* See if there is a later reload that has a class different from our
5913 class that intersects our class or that requires less register
5914 than our reload. If so, we must allocate a register to this
5915 reload now, since that reload might inherit a previous reload
5916 and take the only available register in our class. Don't do this
5917 for optional reloads since they will force all previous reloads
5918 to be allocated. Also don't do this for reloads that have been
5921 for (i = j + 1; i < n_reloads; i++)
5923 int s = reload_order[i];
5925 if ((rld[s].in == 0 && rld[s].out == 0
5926 && ! rld[s].secondary_p)
5930 if ((rld[s].class != rld[r].class
5931 && reg_classes_intersect_p (rld[r].class,
5933 || rld[s].nregs < rld[r].nregs)
5940 allocate_reload_reg (chain, r, j == n_reloads - 1);
5944 /* Now allocate reload registers for anything non-optional that
5945 didn't get one yet. */
5946 for (j = 0; j < n_reloads; j++)
5948 int r = reload_order[j];
5950 /* Ignore reloads that got marked inoperative. */
5951 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5954 /* Skip reloads that already have a register allocated or are
5956 if (rld[r].reg_rtx != 0 || rld[r].optional)
5959 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5963 /* If that loop got all the way, we have won. */
5970 /* Loop around and try without any inheritance. */
5975 /* First undo everything done by the failed attempt
5976 to allocate with inheritance. */
5977 choose_reload_regs_init (chain, save_reload_reg_rtx);
5979 /* Some sanity tests to verify that the reloads found in the first
5980 pass are identical to the ones we have now. */
5981 gcc_assert (chain->n_reloads == n_reloads);
5983 for (i = 0; i < n_reloads; i++)
5985 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5987 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
5988 for (j = 0; j < n_spills; j++)
5989 if (spill_regs[j] == chain->rld[i].regno)
5990 if (! set_reload_reg (j, i))
5991 failed_reload (chain->insn, i);
5995 /* If we thought we could inherit a reload, because it seemed that
5996 nothing else wanted the same reload register earlier in the insn,
5997 verify that assumption, now that all reloads have been assigned.
5998 Likewise for reloads where reload_override_in has been set. */
6000 /* If doing expensive optimizations, do one preliminary pass that doesn't
6001 cancel any inheritance, but removes reloads that have been needed only
6002 for reloads that we know can be inherited. */
6003 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6005 for (j = 0; j < n_reloads; j++)
6007 int r = reload_order[j];
6009 if (reload_inherited[r] && rld[r].reg_rtx)
6010 check_reg = rld[r].reg_rtx;
6011 else if (reload_override_in[r]
6012 && (REG_P (reload_override_in[r])
6013 || GET_CODE (reload_override_in[r]) == SUBREG))
6014 check_reg = reload_override_in[r];
6017 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6018 rld[r].opnum, rld[r].when_needed, rld[r].in,
6019 (reload_inherited[r]
6020 ? rld[r].out : const0_rtx),
6025 reload_inherited[r] = 0;
6026 reload_override_in[r] = 0;
6028 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6029 reload_override_in, then we do not need its related
6030 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6031 likewise for other reload types.
6032 We handle this by removing a reload when its only replacement
6033 is mentioned in reload_in of the reload we are going to inherit.
6034 A special case are auto_inc expressions; even if the input is
6035 inherited, we still need the address for the output. We can
6036 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6037 If we succeeded removing some reload and we are doing a preliminary
6038 pass just to remove such reloads, make another pass, since the
6039 removal of one reload might allow us to inherit another one. */
6041 && rld[r].out != rld[r].in
6042 && remove_address_replacements (rld[r].in) && pass)
6047 /* Now that reload_override_in is known valid,
6048 actually override reload_in. */
6049 for (j = 0; j < n_reloads; j++)
6050 if (reload_override_in[j])
6051 rld[j].in = reload_override_in[j];
6053 /* If this reload won't be done because it has been canceled or is
6054 optional and not inherited, clear reload_reg_rtx so other
6055 routines (such as subst_reloads) don't get confused. */
6056 for (j = 0; j < n_reloads; j++)
6057 if (rld[j].reg_rtx != 0
6058 && ((rld[j].optional && ! reload_inherited[j])
6059 || (rld[j].in == 0 && rld[j].out == 0
6060 && ! rld[j].secondary_p)))
6062 int regno = true_regnum (rld[j].reg_rtx);
6064 if (spill_reg_order[regno] >= 0)
6065 clear_reload_reg_in_use (regno, rld[j].opnum,
6066 rld[j].when_needed, rld[j].mode);
6068 reload_spill_index[j] = -1;
6071 /* Record which pseudos and which spill regs have output reloads. */
6072 for (j = 0; j < n_reloads; j++)
6074 int r = reload_order[j];
6076 i = reload_spill_index[r];
6078 /* I is nonneg if this reload uses a register.
6079 If rld[r].reg_rtx is 0, this is an optional reload
6080 that we opted to ignore. */
6081 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6082 && rld[r].reg_rtx != 0)
6084 int nregno = REGNO (rld[r].out_reg);
6087 if (nregno < FIRST_PSEUDO_REGISTER)
6088 nr = hard_regno_nregs[nregno][rld[r].mode];
6091 SET_REGNO_REG_SET (®_has_output_reload,
6096 nr = hard_regno_nregs[i][rld[r].mode];
6098 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6101 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6102 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6103 || rld[r].when_needed == RELOAD_FOR_INSN);
6108 /* Deallocate the reload register for reload R. This is called from
6109 remove_address_replacements. */
6112 deallocate_reload_reg (int r)
6116 if (! rld[r].reg_rtx)
6118 regno = true_regnum (rld[r].reg_rtx);
6120 if (spill_reg_order[regno] >= 0)
6121 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6123 reload_spill_index[r] = -1;
6126 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6127 reloads of the same item for fear that we might not have enough reload
6128 registers. However, normally they will get the same reload register
6129 and hence actually need not be loaded twice.
6131 Here we check for the most common case of this phenomenon: when we have
6132 a number of reloads for the same object, each of which were allocated
6133 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6134 reload, and is not modified in the insn itself. If we find such,
6135 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6136 This will not increase the number of spill registers needed and will
6137 prevent redundant code. */
6140 merge_assigned_reloads (rtx insn)
6144 /* Scan all the reloads looking for ones that only load values and
6145 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6146 assigned and not modified by INSN. */
6148 for (i = 0; i < n_reloads; i++)
6150 int conflicting_input = 0;
6151 int max_input_address_opnum = -1;
6152 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6154 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6155 || rld[i].out != 0 || rld[i].reg_rtx == 0
6156 || reg_set_p (rld[i].reg_rtx, insn))
6159 /* Look at all other reloads. Ensure that the only use of this
6160 reload_reg_rtx is in a reload that just loads the same value
6161 as we do. Note that any secondary reloads must be of the identical
6162 class since the values, modes, and result registers are the
6163 same, so we need not do anything with any secondary reloads. */
6165 for (j = 0; j < n_reloads; j++)
6167 if (i == j || rld[j].reg_rtx == 0
6168 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6172 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6173 && rld[j].opnum > max_input_address_opnum)
6174 max_input_address_opnum = rld[j].opnum;
6176 /* If the reload regs aren't exactly the same (e.g, different modes)
6177 or if the values are different, we can't merge this reload.
6178 But if it is an input reload, we might still merge
6179 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6181 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6182 || rld[j].out != 0 || rld[j].in == 0
6183 || ! rtx_equal_p (rld[i].in, rld[j].in))
6185 if (rld[j].when_needed != RELOAD_FOR_INPUT
6186 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6187 || rld[i].opnum > rld[j].opnum)
6188 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6190 conflicting_input = 1;
6191 if (min_conflicting_input_opnum > rld[j].opnum)
6192 min_conflicting_input_opnum = rld[j].opnum;
6196 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6197 we, in fact, found any matching reloads. */
6200 && max_input_address_opnum <= min_conflicting_input_opnum)
6202 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6204 for (j = 0; j < n_reloads; j++)
6205 if (i != j && rld[j].reg_rtx != 0
6206 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6207 && (! conflicting_input
6208 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6209 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6211 rld[i].when_needed = RELOAD_OTHER;
6213 reload_spill_index[j] = -1;
6214 transfer_replacements (i, j);
6217 /* If this is now RELOAD_OTHER, look for any reloads that load
6218 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6219 if they were for inputs, RELOAD_OTHER for outputs. Note that
6220 this test is equivalent to looking for reloads for this operand
6222 /* We must take special care with RELOAD_FOR_OUTPUT_ADDRESS; it may
6223 share registers with a RELOAD_FOR_INPUT, so we can not change it
6224 to RELOAD_FOR_OTHER_ADDRESS. We should never need to, since we
6225 do not modify RELOAD_FOR_OUTPUT. */
6227 if (rld[i].when_needed == RELOAD_OTHER)
6228 for (j = 0; j < n_reloads; j++)
6230 && rld[j].when_needed != RELOAD_OTHER
6231 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6232 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6233 && (! conflicting_input
6234 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6235 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6236 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6242 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6243 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6244 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6246 /* Check to see if we accidentally converted two
6247 reloads that use the same reload register with
6248 different inputs to the same type. If so, the
6249 resulting code won't work. */
6251 for (k = 0; k < j; k++)
6252 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6253 || rld[k].when_needed != rld[j].when_needed
6254 || !rtx_equal_p (rld[k].reg_rtx,
6256 || rtx_equal_p (rld[k].in,
6263 /* These arrays are filled by emit_reload_insns and its subroutines. */
6264 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6265 static rtx other_input_address_reload_insns = 0;
6266 static rtx other_input_reload_insns = 0;
6267 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6268 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6269 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6270 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6271 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6272 static rtx operand_reload_insns = 0;
6273 static rtx other_operand_reload_insns = 0;
6274 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6276 /* Values to be put in spill_reg_store are put here first. */
6277 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6278 static HARD_REG_SET reg_reloaded_died;
6280 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6281 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6282 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6283 adjusted register, and return true. Otherwise, return false. */
6285 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6286 enum reg_class new_class,
6287 enum machine_mode new_mode)
6292 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6294 unsigned regno = REGNO (reg);
6296 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6298 if (GET_MODE (reg) != new_mode)
6300 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6302 if (hard_regno_nregs[regno][new_mode]
6303 > hard_regno_nregs[regno][GET_MODE (reg)])
6305 reg = reload_adjust_reg_for_mode (reg, new_mode);
6313 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6314 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6315 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6316 adjusted register, and return true. Otherwise, return false. */
6318 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6319 enum insn_code icode)
6322 enum reg_class new_class = scratch_reload_class (icode);
6323 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6325 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6326 new_class, new_mode);
6329 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6330 has the number J. OLD contains the value to be used as input. */
6333 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6336 rtx insn = chain->insn;
6337 rtx reloadreg = rl->reg_rtx;
6338 rtx oldequiv_reg = 0;
6341 enum machine_mode mode;
6344 /* Determine the mode to reload in.
6345 This is very tricky because we have three to choose from.
6346 There is the mode the insn operand wants (rl->inmode).
6347 There is the mode of the reload register RELOADREG.
6348 There is the intrinsic mode of the operand, which we could find
6349 by stripping some SUBREGs.
6350 It turns out that RELOADREG's mode is irrelevant:
6351 we can change that arbitrarily.
6353 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6354 then the reload reg may not support QImode moves, so use SImode.
6355 If foo is in memory due to spilling a pseudo reg, this is safe,
6356 because the QImode value is in the least significant part of a
6357 slot big enough for a SImode. If foo is some other sort of
6358 memory reference, then it is impossible to reload this case,
6359 so previous passes had better make sure this never happens.
6361 Then consider a one-word union which has SImode and one of its
6362 members is a float, being fetched as (SUBREG:SF union:SI).
6363 We must fetch that as SFmode because we could be loading into
6364 a float-only register. In this case OLD's mode is correct.
6366 Consider an immediate integer: it has VOIDmode. Here we need
6367 to get a mode from something else.
6369 In some cases, there is a fourth mode, the operand's
6370 containing mode. If the insn specifies a containing mode for
6371 this operand, it overrides all others.
6373 I am not sure whether the algorithm here is always right,
6374 but it does the right things in those cases. */
6376 mode = GET_MODE (old);
6377 if (mode == VOIDmode)
6380 /* delete_output_reload is only invoked properly if old contains
6381 the original pseudo register. Since this is replaced with a
6382 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6383 find the pseudo in RELOAD_IN_REG. */
6384 if (reload_override_in[j]
6385 && REG_P (rl->in_reg))
6392 else if (REG_P (oldequiv))
6393 oldequiv_reg = oldequiv;
6394 else if (GET_CODE (oldequiv) == SUBREG)
6395 oldequiv_reg = SUBREG_REG (oldequiv);
6397 /* If we are reloading from a register that was recently stored in
6398 with an output-reload, see if we can prove there was
6399 actually no need to store the old value in it. */
6401 if (optimize && REG_P (oldequiv)
6402 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6403 && spill_reg_store[REGNO (oldequiv)]
6405 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6406 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6408 delete_output_reload (insn, j, REGNO (oldequiv));
6410 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6411 then load RELOADREG from OLDEQUIV. Note that we cannot use
6412 gen_lowpart_common since it can do the wrong thing when
6413 RELOADREG has a multi-word mode. Note that RELOADREG
6414 must always be a REG here. */
6416 if (GET_MODE (reloadreg) != mode)
6417 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6418 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6419 oldequiv = SUBREG_REG (oldequiv);
6420 if (GET_MODE (oldequiv) != VOIDmode
6421 && mode != GET_MODE (oldequiv))
6422 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6424 /* Switch to the right place to emit the reload insns. */
6425 switch (rl->when_needed)
6428 where = &other_input_reload_insns;
6430 case RELOAD_FOR_INPUT:
6431 where = &input_reload_insns[rl->opnum];
6433 case RELOAD_FOR_INPUT_ADDRESS:
6434 where = &input_address_reload_insns[rl->opnum];
6436 case RELOAD_FOR_INPADDR_ADDRESS:
6437 where = &inpaddr_address_reload_insns[rl->opnum];
6439 case RELOAD_FOR_OUTPUT_ADDRESS:
6440 where = &output_address_reload_insns[rl->opnum];
6442 case RELOAD_FOR_OUTADDR_ADDRESS:
6443 where = &outaddr_address_reload_insns[rl->opnum];
6445 case RELOAD_FOR_OPERAND_ADDRESS:
6446 where = &operand_reload_insns;
6448 case RELOAD_FOR_OPADDR_ADDR:
6449 where = &other_operand_reload_insns;
6451 case RELOAD_FOR_OTHER_ADDRESS:
6452 where = &other_input_address_reload_insns;
6458 push_to_sequence (*where);
6460 /* Auto-increment addresses must be reloaded in a special way. */
6461 if (rl->out && ! rl->out_reg)
6463 /* We are not going to bother supporting the case where a
6464 incremented register can't be copied directly from
6465 OLDEQUIV since this seems highly unlikely. */
6466 gcc_assert (rl->secondary_in_reload < 0);
6468 if (reload_inherited[j])
6469 oldequiv = reloadreg;
6471 old = XEXP (rl->in_reg, 0);
6473 if (optimize && REG_P (oldequiv)
6474 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6475 && spill_reg_store[REGNO (oldequiv)]
6477 && (dead_or_set_p (insn,
6478 spill_reg_stored_to[REGNO (oldequiv)])
6479 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6481 delete_output_reload (insn, j, REGNO (oldequiv));
6483 /* Prevent normal processing of this reload. */
6485 /* Output a special code sequence for this case. */
6486 new_spill_reg_store[REGNO (reloadreg)]
6487 = inc_for_reload (reloadreg, oldequiv, rl->out,
6491 /* If we are reloading a pseudo-register that was set by the previous
6492 insn, see if we can get rid of that pseudo-register entirely
6493 by redirecting the previous insn into our reload register. */
6495 else if (optimize && REG_P (old)
6496 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6497 && dead_or_set_p (insn, old)
6498 /* This is unsafe if some other reload
6499 uses the same reg first. */
6500 && ! conflicts_with_override (reloadreg)
6501 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6502 rl->when_needed, old, rl->out, j, 0))
6504 rtx temp = PREV_INSN (insn);
6505 while (temp && NOTE_P (temp))
6506 temp = PREV_INSN (temp);
6508 && NONJUMP_INSN_P (temp)
6509 && GET_CODE (PATTERN (temp)) == SET
6510 && SET_DEST (PATTERN (temp)) == old
6511 /* Make sure we can access insn_operand_constraint. */
6512 && asm_noperands (PATTERN (temp)) < 0
6513 /* This is unsafe if operand occurs more than once in current
6514 insn. Perhaps some occurrences aren't reloaded. */
6515 && count_occurrences (PATTERN (insn), old, 0) == 1)
6517 rtx old = SET_DEST (PATTERN (temp));
6518 /* Store into the reload register instead of the pseudo. */
6519 SET_DEST (PATTERN (temp)) = reloadreg;
6521 /* Verify that resulting insn is valid. */
6522 extract_insn (temp);
6523 if (constrain_operands (1))
6525 /* If the previous insn is an output reload, the source is
6526 a reload register, and its spill_reg_store entry will
6527 contain the previous destination. This is now
6529 if (REG_P (SET_SRC (PATTERN (temp)))
6530 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6532 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6533 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6536 /* If these are the only uses of the pseudo reg,
6537 pretend for GDB it lives in the reload reg we used. */
6538 if (REG_N_DEATHS (REGNO (old)) == 1
6539 && REG_N_SETS (REGNO (old)) == 1)
6541 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6542 alter_reg (REGNO (old), -1);
6548 SET_DEST (PATTERN (temp)) = old;
6553 /* We can't do that, so output an insn to load RELOADREG. */
6555 /* If we have a secondary reload, pick up the secondary register
6556 and icode, if any. If OLDEQUIV and OLD are different or
6557 if this is an in-out reload, recompute whether or not we
6558 still need a secondary register and what the icode should
6559 be. If we still need a secondary register and the class or
6560 icode is different, go back to reloading from OLD if using
6561 OLDEQUIV means that we got the wrong type of register. We
6562 cannot have different class or icode due to an in-out reload
6563 because we don't make such reloads when both the input and
6564 output need secondary reload registers. */
6566 if (! special && rl->secondary_in_reload >= 0)
6568 rtx second_reload_reg = 0;
6569 rtx third_reload_reg = 0;
6570 int secondary_reload = rl->secondary_in_reload;
6571 rtx real_oldequiv = oldequiv;
6574 enum insn_code icode;
6575 enum insn_code tertiary_icode = CODE_FOR_nothing;
6577 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6578 and similarly for OLD.
6579 See comments in get_secondary_reload in reload.c. */
6580 /* If it is a pseudo that cannot be replaced with its
6581 equivalent MEM, we must fall back to reload_in, which
6582 will have all the necessary substitutions registered.
6583 Likewise for a pseudo that can't be replaced with its
6584 equivalent constant.
6586 Take extra care for subregs of such pseudos. Note that
6587 we cannot use reg_equiv_mem in this case because it is
6588 not in the right mode. */
6591 if (GET_CODE (tmp) == SUBREG)
6592 tmp = SUBREG_REG (tmp);
6594 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6595 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6596 || reg_equiv_constant[REGNO (tmp)] != 0))
6598 if (! reg_equiv_mem[REGNO (tmp)]
6599 || num_not_at_initial_offset
6600 || GET_CODE (oldequiv) == SUBREG)
6601 real_oldequiv = rl->in;
6603 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6607 if (GET_CODE (tmp) == SUBREG)
6608 tmp = SUBREG_REG (tmp);
6610 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6611 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6612 || reg_equiv_constant[REGNO (tmp)] != 0))
6614 if (! reg_equiv_mem[REGNO (tmp)]
6615 || num_not_at_initial_offset
6616 || GET_CODE (old) == SUBREG)
6619 real_old = reg_equiv_mem[REGNO (tmp)];
6622 second_reload_reg = rld[secondary_reload].reg_rtx;
6623 if (rld[secondary_reload].secondary_in_reload >= 0)
6625 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
6627 third_reload_reg = rld[tertiary_reload].reg_rtx;
6628 tertiary_icode = rld[secondary_reload].secondary_in_icode;
6629 /* We'd have to add more code for quartary reloads. */
6630 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
6632 icode = rl->secondary_in_icode;
6634 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6635 || (rl->in != 0 && rl->out != 0))
6637 secondary_reload_info sri, sri2;
6638 enum reg_class new_class, new_t_class;
6640 sri.icode = CODE_FOR_nothing;
6641 sri.prev_sri = NULL;
6642 new_class = targetm.secondary_reload (1, real_oldequiv, rl->class,
6645 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
6646 second_reload_reg = 0;
6647 else if (new_class == NO_REGS)
6649 if (reload_adjust_reg_for_icode (&second_reload_reg,
6650 third_reload_reg, sri.icode))
6651 icode = sri.icode, third_reload_reg = 0;
6653 oldequiv = old, real_oldequiv = real_old;
6655 else if (sri.icode != CODE_FOR_nothing)
6656 /* We currently lack a way to express this in reloads. */
6660 sri2.icode = CODE_FOR_nothing;
6661 sri2.prev_sri = &sri;
6662 new_t_class = targetm.secondary_reload (1, real_oldequiv,
6663 new_class, mode, &sri);
6664 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
6666 if (reload_adjust_reg_for_temp (&second_reload_reg,
6669 third_reload_reg = 0, tertiary_icode = sri2.icode;
6671 oldequiv = old, real_oldequiv = real_old;
6673 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
6675 rtx intermediate = second_reload_reg;
6677 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6679 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
6682 second_reload_reg = intermediate;
6683 tertiary_icode = sri2.icode;
6686 oldequiv = old, real_oldequiv = real_old;
6688 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
6690 rtx intermediate = second_reload_reg;
6692 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6694 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
6697 second_reload_reg = intermediate;
6698 tertiary_icode = sri2.icode;
6701 oldequiv = old, real_oldequiv = real_old;
6704 /* This could be handled more intelligently too. */
6705 oldequiv = old, real_oldequiv = real_old;
6709 /* If we still need a secondary reload register, check
6710 to see if it is being used as a scratch or intermediate
6711 register and generate code appropriately. If we need
6712 a scratch register, use REAL_OLDEQUIV since the form of
6713 the insn may depend on the actual address if it is
6716 if (second_reload_reg)
6718 if (icode != CODE_FOR_nothing)
6720 /* We'd have to add extra code to handle this case. */
6721 gcc_assert (!third_reload_reg);
6723 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6724 second_reload_reg));
6729 /* See if we need a scratch register to load the
6730 intermediate register (a tertiary reload). */
6731 if (tertiary_icode != CODE_FOR_nothing)
6733 emit_insn ((GEN_FCN (tertiary_icode)
6734 (second_reload_reg, real_oldequiv,
6735 third_reload_reg)));
6737 else if (third_reload_reg)
6739 gen_reload (third_reload_reg, real_oldequiv,
6742 gen_reload (second_reload_reg, third_reload_reg,
6747 gen_reload (second_reload_reg, real_oldequiv,
6751 oldequiv = second_reload_reg;
6756 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6758 rtx real_oldequiv = oldequiv;
6760 if ((REG_P (oldequiv)
6761 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6762 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6763 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6764 || (GET_CODE (oldequiv) == SUBREG
6765 && REG_P (SUBREG_REG (oldequiv))
6766 && (REGNO (SUBREG_REG (oldequiv))
6767 >= FIRST_PSEUDO_REGISTER)
6768 && ((reg_equiv_memory_loc
6769 [REGNO (SUBREG_REG (oldequiv))] != 0)
6770 || (reg_equiv_constant
6771 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6772 || (CONSTANT_P (oldequiv)
6773 && (PREFERRED_RELOAD_CLASS (oldequiv,
6774 REGNO_REG_CLASS (REGNO (reloadreg)))
6776 real_oldequiv = rl->in;
6777 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6781 if (flag_non_call_exceptions)
6782 copy_eh_notes (insn, get_insns ());
6784 /* End this sequence. */
6785 *where = get_insns ();
6788 /* Update reload_override_in so that delete_address_reloads_1
6789 can see the actual register usage. */
6791 reload_override_in[j] = oldequiv;
6794 /* Generate insns to for the output reload RL, which is for the insn described
6795 by CHAIN and has the number J. */
6797 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6800 rtx reloadreg = rl->reg_rtx;
6801 rtx insn = chain->insn;
6804 enum machine_mode mode = GET_MODE (old);
6807 if (rl->when_needed == RELOAD_OTHER)
6810 push_to_sequence (output_reload_insns[rl->opnum]);
6812 /* Determine the mode to reload in.
6813 See comments above (for input reloading). */
6815 if (mode == VOIDmode)
6817 /* VOIDmode should never happen for an output. */
6818 if (asm_noperands (PATTERN (insn)) < 0)
6819 /* It's the compiler's fault. */
6820 fatal_insn ("VOIDmode on an output", insn);
6821 error_for_asm (insn, "output operand is constant in %<asm%>");
6822 /* Prevent crash--use something we know is valid. */
6824 old = gen_rtx_REG (mode, REGNO (reloadreg));
6827 if (GET_MODE (reloadreg) != mode)
6828 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6830 /* If we need two reload regs, set RELOADREG to the intermediate
6831 one, since it will be stored into OLD. We might need a secondary
6832 register only for an input reload, so check again here. */
6834 if (rl->secondary_out_reload >= 0)
6837 int secondary_reload = rl->secondary_out_reload;
6838 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
6840 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
6841 && reg_equiv_mem[REGNO (old)] != 0)
6842 real_old = reg_equiv_mem[REGNO (old)];
6844 if (secondary_reload_class (0, rl->class, mode, real_old) != NO_REGS)
6846 rtx second_reloadreg = reloadreg;
6847 reloadreg = rld[secondary_reload].reg_rtx;
6849 /* See if RELOADREG is to be used as a scratch register
6850 or as an intermediate register. */
6851 if (rl->secondary_out_icode != CODE_FOR_nothing)
6853 /* We'd have to add extra code to handle this case. */
6854 gcc_assert (tertiary_reload < 0);
6856 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6857 (real_old, second_reloadreg, reloadreg)));
6862 /* See if we need both a scratch and intermediate reload
6865 enum insn_code tertiary_icode
6866 = rld[secondary_reload].secondary_out_icode;
6868 /* We'd have to add more code for quartary reloads. */
6869 gcc_assert (tertiary_reload < 0
6870 || rld[tertiary_reload].secondary_out_reload < 0);
6872 if (GET_MODE (reloadreg) != mode)
6873 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6875 if (tertiary_icode != CODE_FOR_nothing)
6877 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
6880 /* Copy primary reload reg to secondary reload reg.
6881 (Note that these have been swapped above, then
6882 secondary reload reg to OLD using our insn.) */
6884 /* If REAL_OLD is a paradoxical SUBREG, remove it
6885 and try to put the opposite SUBREG on
6887 if (GET_CODE (real_old) == SUBREG
6888 && (GET_MODE_SIZE (GET_MODE (real_old))
6889 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6890 && 0 != (tem = gen_lowpart_common
6891 (GET_MODE (SUBREG_REG (real_old)),
6893 real_old = SUBREG_REG (real_old), reloadreg = tem;
6895 gen_reload (reloadreg, second_reloadreg,
6896 rl->opnum, rl->when_needed);
6897 emit_insn ((GEN_FCN (tertiary_icode)
6898 (real_old, reloadreg, third_reloadreg)));
6904 /* Copy between the reload regs here and then to
6907 gen_reload (reloadreg, second_reloadreg,
6908 rl->opnum, rl->when_needed);
6909 if (tertiary_reload >= 0)
6911 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
6913 gen_reload (third_reloadreg, reloadreg,
6914 rl->opnum, rl->when_needed);
6915 reloadreg = third_reloadreg;
6922 /* Output the last reload insn. */
6927 /* Don't output the last reload if OLD is not the dest of
6928 INSN and is in the src and is clobbered by INSN. */
6929 if (! flag_expensive_optimizations
6931 || !(set = single_set (insn))
6932 || rtx_equal_p (old, SET_DEST (set))
6933 || !reg_mentioned_p (old, SET_SRC (set))
6934 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
6935 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
6936 gen_reload (old, reloadreg, rl->opnum,
6940 /* Look at all insns we emitted, just to be safe. */
6941 for (p = get_insns (); p; p = NEXT_INSN (p))
6944 rtx pat = PATTERN (p);
6946 /* If this output reload doesn't come from a spill reg,
6947 clear any memory of reloaded copies of the pseudo reg.
6948 If this output reload comes from a spill reg,
6949 reg_has_output_reload will make this do nothing. */
6950 note_stores (pat, forget_old_reloads_1, NULL);
6952 if (reg_mentioned_p (rl->reg_rtx, pat))
6954 rtx set = single_set (insn);
6955 if (reload_spill_index[j] < 0
6957 && SET_SRC (set) == rl->reg_rtx)
6959 int src = REGNO (SET_SRC (set));
6961 reload_spill_index[j] = src;
6962 SET_HARD_REG_BIT (reg_is_output_reload, src);
6963 if (find_regno_note (insn, REG_DEAD, src))
6964 SET_HARD_REG_BIT (reg_reloaded_died, src);
6966 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6968 int s = rl->secondary_out_reload;
6969 set = single_set (p);
6970 /* If this reload copies only to the secondary reload
6971 register, the secondary reload does the actual
6973 if (s >= 0 && set == NULL_RTX)
6974 /* We can't tell what function the secondary reload
6975 has and where the actual store to the pseudo is
6976 made; leave new_spill_reg_store alone. */
6979 && SET_SRC (set) == rl->reg_rtx
6980 && SET_DEST (set) == rld[s].reg_rtx)
6982 /* Usually the next instruction will be the
6983 secondary reload insn; if we can confirm
6984 that it is, setting new_spill_reg_store to
6985 that insn will allow an extra optimization. */
6986 rtx s_reg = rld[s].reg_rtx;
6987 rtx next = NEXT_INSN (p);
6988 rld[s].out = rl->out;
6989 rld[s].out_reg = rl->out_reg;
6990 set = single_set (next);
6991 if (set && SET_SRC (set) == s_reg
6992 && ! new_spill_reg_store[REGNO (s_reg)])
6994 SET_HARD_REG_BIT (reg_is_output_reload,
6996 new_spill_reg_store[REGNO (s_reg)] = next;
7000 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
7005 if (rl->when_needed == RELOAD_OTHER)
7007 emit_insn (other_output_reload_insns[rl->opnum]);
7008 other_output_reload_insns[rl->opnum] = get_insns ();
7011 output_reload_insns[rl->opnum] = get_insns ();
7013 if (flag_non_call_exceptions)
7014 copy_eh_notes (insn, get_insns ());
7019 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7020 and has the number J. */
7022 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7024 rtx insn = chain->insn;
7025 rtx old = (rl->in && MEM_P (rl->in)
7026 ? rl->in_reg : rl->in);
7029 /* AUTO_INC reloads need to be handled even if inherited. We got an
7030 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7031 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7032 && ! rtx_equal_p (rl->reg_rtx, old)
7033 && rl->reg_rtx != 0)
7034 emit_input_reload_insns (chain, rld + j, old, j);
7036 /* When inheriting a wider reload, we have a MEM in rl->in,
7037 e.g. inheriting a SImode output reload for
7038 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7039 if (optimize && reload_inherited[j] && rl->in
7041 && MEM_P (rl->in_reg)
7042 && reload_spill_index[j] >= 0
7043 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7044 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7046 /* If we are reloading a register that was recently stored in with an
7047 output-reload, see if we can prove there was
7048 actually no need to store the old value in it. */
7051 /* Only attempt this for input reloads; for RELOAD_OTHER we miss
7052 that there may be multiple uses of the previous output reload.
7053 Restricting to RELOAD_FOR_INPUT is mostly paranoia. */
7054 && rl->when_needed == RELOAD_FOR_INPUT
7055 && (reload_inherited[j] || reload_override_in[j])
7057 && REG_P (rl->reg_rtx)
7058 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
7060 /* There doesn't seem to be any reason to restrict this to pseudos
7061 and doing so loses in the case where we are copying from a
7062 register of the wrong class. */
7063 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
7064 >= FIRST_PSEUDO_REGISTER)
7066 /* The insn might have already some references to stackslots
7067 replaced by MEMs, while reload_out_reg still names the
7069 && (dead_or_set_p (insn,
7070 spill_reg_stored_to[REGNO (rl->reg_rtx)])
7071 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
7073 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
7076 /* Do output reloading for reload RL, which is for the insn described by
7077 CHAIN and has the number J.
7078 ??? At some point we need to support handling output reloads of
7079 JUMP_INSNs or insns that set cc0. */
7081 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7084 rtx insn = chain->insn;
7085 /* If this is an output reload that stores something that is
7086 not loaded in this same reload, see if we can eliminate a previous
7088 rtx pseudo = rl->out_reg;
7093 && ! rtx_equal_p (rl->in_reg, pseudo)
7094 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7095 && reg_last_reload_reg[REGNO (pseudo)])
7097 int pseudo_no = REGNO (pseudo);
7098 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7100 /* We don't need to test full validity of last_regno for
7101 inherit here; we only want to know if the store actually
7102 matches the pseudo. */
7103 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7104 && reg_reloaded_contents[last_regno] == pseudo_no
7105 && spill_reg_store[last_regno]
7106 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7107 delete_output_reload (insn, j, last_regno);
7112 || rl->reg_rtx == old
7113 || rl->reg_rtx == 0)
7116 /* An output operand that dies right away does need a reload,
7117 but need not be copied from it. Show the new location in the
7119 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7120 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7122 XEXP (note, 0) = rl->reg_rtx;
7125 /* Likewise for a SUBREG of an operand that dies. */
7126 else if (GET_CODE (old) == SUBREG
7127 && REG_P (SUBREG_REG (old))
7128 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7131 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
7135 else if (GET_CODE (old) == SCRATCH)
7136 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7137 but we don't want to make an output reload. */
7140 /* If is a JUMP_INSN, we can't support output reloads yet. */
7141 gcc_assert (NONJUMP_INSN_P (insn));
7143 emit_output_reload_insns (chain, rld + j, j);
7146 /* Reload number R reloads from or to a group of hard registers starting at
7147 register REGNO. Return true if it can be treated for inheritance purposes
7148 like a group of reloads, each one reloading a single hard register.
7149 The caller has already checked that the spill register and REGNO use
7150 the same number of registers to store the reload value. */
7153 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
7155 #ifdef CANNOT_CHANGE_MODE_CLASS
7156 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
7157 GET_MODE (rld[r].reg_rtx),
7158 reg_raw_mode[reload_spill_index[r]])
7159 && !REG_CANNOT_CHANGE_MODE_P (regno,
7160 GET_MODE (rld[r].reg_rtx),
7161 reg_raw_mode[regno]));
7167 /* Output insns to reload values in and out of the chosen reload regs. */
7170 emit_reload_insns (struct insn_chain *chain)
7172 rtx insn = chain->insn;
7176 CLEAR_HARD_REG_SET (reg_reloaded_died);
7178 for (j = 0; j < reload_n_operands; j++)
7179 input_reload_insns[j] = input_address_reload_insns[j]
7180 = inpaddr_address_reload_insns[j]
7181 = output_reload_insns[j] = output_address_reload_insns[j]
7182 = outaddr_address_reload_insns[j]
7183 = other_output_reload_insns[j] = 0;
7184 other_input_address_reload_insns = 0;
7185 other_input_reload_insns = 0;
7186 operand_reload_insns = 0;
7187 other_operand_reload_insns = 0;
7189 /* Dump reloads into the dump file. */
7192 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7193 debug_reload_to_stream (dump_file);
7196 /* Now output the instructions to copy the data into and out of the
7197 reload registers. Do these in the order that the reloads were reported,
7198 since reloads of base and index registers precede reloads of operands
7199 and the operands may need the base and index registers reloaded. */
7201 for (j = 0; j < n_reloads; j++)
7204 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7205 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7207 do_input_reload (chain, rld + j, j);
7208 do_output_reload (chain, rld + j, j);
7211 /* Now write all the insns we made for reloads in the order expected by
7212 the allocation functions. Prior to the insn being reloaded, we write
7213 the following reloads:
7215 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7217 RELOAD_OTHER reloads.
7219 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7220 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7221 RELOAD_FOR_INPUT reload for the operand.
7223 RELOAD_FOR_OPADDR_ADDRS reloads.
7225 RELOAD_FOR_OPERAND_ADDRESS reloads.
7227 After the insn being reloaded, we write the following:
7229 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7230 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7231 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7232 reloads for the operand. The RELOAD_OTHER output reloads are
7233 output in descending order by reload number. */
7235 emit_insn_before (other_input_address_reload_insns, insn);
7236 emit_insn_before (other_input_reload_insns, insn);
7238 for (j = 0; j < reload_n_operands; j++)
7240 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7241 emit_insn_before (input_address_reload_insns[j], insn);
7242 emit_insn_before (input_reload_insns[j], insn);
7245 emit_insn_before (other_operand_reload_insns, insn);
7246 emit_insn_before (operand_reload_insns, insn);
7248 for (j = 0; j < reload_n_operands; j++)
7250 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7251 x = emit_insn_after (output_address_reload_insns[j], x);
7252 x = emit_insn_after (output_reload_insns[j], x);
7253 emit_insn_after (other_output_reload_insns[j], x);
7256 /* For all the spill regs newly reloaded in this instruction,
7257 record what they were reloaded from, so subsequent instructions
7258 can inherit the reloads.
7260 Update spill_reg_store for the reloads of this insn.
7261 Copy the elements that were updated in the loop above. */
7263 for (j = 0; j < n_reloads; j++)
7265 int r = reload_order[j];
7266 int i = reload_spill_index[r];
7268 /* If this is a non-inherited input reload from a pseudo, we must
7269 clear any memory of a previous store to the same pseudo. Only do
7270 something if there will not be an output reload for the pseudo
7272 if (rld[r].in_reg != 0
7273 && ! (reload_inherited[r] || reload_override_in[r]))
7275 rtx reg = rld[r].in_reg;
7277 if (GET_CODE (reg) == SUBREG)
7278 reg = SUBREG_REG (reg);
7281 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7282 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
7284 int nregno = REGNO (reg);
7286 if (reg_last_reload_reg[nregno])
7288 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7290 if (reg_reloaded_contents[last_regno] == nregno)
7291 spill_reg_store[last_regno] = 0;
7296 /* I is nonneg if this reload used a register.
7297 If rld[r].reg_rtx is 0, this is an optional reload
7298 that we opted to ignore. */
7300 if (i >= 0 && rld[r].reg_rtx != 0)
7302 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7304 int part_reaches_end = 0;
7305 int all_reaches_end = 1;
7307 /* For a multi register reload, we need to check if all or part
7308 of the value lives to the end. */
7309 for (k = 0; k < nr; k++)
7311 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7312 rld[r].when_needed))
7313 part_reaches_end = 1;
7315 all_reaches_end = 0;
7318 /* Ignore reloads that don't reach the end of the insn in
7320 if (all_reaches_end)
7322 /* First, clear out memory of what used to be in this spill reg.
7323 If consecutive registers are used, clear them all. */
7325 for (k = 0; k < nr; k++)
7327 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7328 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7331 /* Maybe the spill reg contains a copy of reload_out. */
7333 && (REG_P (rld[r].out)
7337 || REG_P (rld[r].out_reg)))
7339 rtx out = (REG_P (rld[r].out)
7343 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7344 int nregno = REGNO (out);
7345 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7346 : hard_regno_nregs[nregno]
7347 [GET_MODE (rld[r].reg_rtx)]);
7350 spill_reg_store[i] = new_spill_reg_store[i];
7351 spill_reg_stored_to[i] = out;
7352 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7354 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7356 && inherit_piecemeal_p (r, nregno));
7358 /* If NREGNO is a hard register, it may occupy more than
7359 one register. If it does, say what is in the
7360 rest of the registers assuming that both registers
7361 agree on how many words the object takes. If not,
7362 invalidate the subsequent registers. */
7364 if (nregno < FIRST_PSEUDO_REGISTER)
7365 for (k = 1; k < nnr; k++)
7366 reg_last_reload_reg[nregno + k]
7368 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7371 /* Now do the inverse operation. */
7372 for (k = 0; k < nr; k++)
7374 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7375 reg_reloaded_contents[i + k]
7376 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7379 reg_reloaded_insn[i + k] = insn;
7380 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7381 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7382 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7386 /* Maybe the spill reg contains a copy of reload_in. Only do
7387 something if there will not be an output reload for
7388 the register being reloaded. */
7389 else if (rld[r].out_reg == 0
7391 && ((REG_P (rld[r].in)
7392 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7393 && !REGNO_REG_SET_P (®_has_output_reload,
7395 || (REG_P (rld[r].in_reg)
7396 && !REGNO_REG_SET_P (®_has_output_reload,
7397 REGNO (rld[r].in_reg))))
7398 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7405 if (REG_P (rld[r].in)
7406 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7408 else if (REG_P (rld[r].in_reg))
7411 in = XEXP (rld[r].in_reg, 0);
7412 nregno = REGNO (in);
7414 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7415 : hard_regno_nregs[nregno]
7416 [GET_MODE (rld[r].reg_rtx)]);
7418 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7420 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7422 && inherit_piecemeal_p (r, nregno));
7424 if (nregno < FIRST_PSEUDO_REGISTER)
7425 for (k = 1; k < nnr; k++)
7426 reg_last_reload_reg[nregno + k]
7428 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7431 /* Unless we inherited this reload, show we haven't
7432 recently done a store.
7433 Previous stores of inherited auto_inc expressions
7434 also have to be discarded. */
7435 if (! reload_inherited[r]
7436 || (rld[r].out && ! rld[r].out_reg))
7437 spill_reg_store[i] = 0;
7439 for (k = 0; k < nr; k++)
7441 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7442 reg_reloaded_contents[i + k]
7443 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7446 reg_reloaded_insn[i + k] = insn;
7447 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7448 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7449 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7454 /* However, if part of the reload reaches the end, then we must
7455 invalidate the old info for the part that survives to the end. */
7456 else if (part_reaches_end)
7458 for (k = 0; k < nr; k++)
7459 if (reload_reg_reaches_end_p (i + k,
7461 rld[r].when_needed))
7462 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7466 /* The following if-statement was #if 0'd in 1.34 (or before...).
7467 It's reenabled in 1.35 because supposedly nothing else
7468 deals with this problem. */
7470 /* If a register gets output-reloaded from a non-spill register,
7471 that invalidates any previous reloaded copy of it.
7472 But forget_old_reloads_1 won't get to see it, because
7473 it thinks only about the original insn. So invalidate it here.
7474 Also do the same thing for RELOAD_OTHER constraints where the
7475 output is discarded. */
7477 && ((rld[r].out != 0
7478 && (REG_P (rld[r].out)
7479 || (MEM_P (rld[r].out)
7480 && REG_P (rld[r].out_reg))))
7481 || (rld[r].out == 0 && rld[r].out_reg
7482 && REG_P (rld[r].out_reg))))
7484 rtx out = ((rld[r].out && REG_P (rld[r].out))
7485 ? rld[r].out : rld[r].out_reg);
7486 int nregno = REGNO (out);
7487 if (nregno >= FIRST_PSEUDO_REGISTER)
7489 rtx src_reg, store_insn = NULL_RTX;
7491 reg_last_reload_reg[nregno] = 0;
7493 /* If we can find a hard register that is stored, record
7494 the storing insn so that we may delete this insn with
7495 delete_output_reload. */
7496 src_reg = rld[r].reg_rtx;
7498 /* If this is an optional reload, try to find the source reg
7499 from an input reload. */
7502 rtx set = single_set (insn);
7503 if (set && SET_DEST (set) == rld[r].out)
7507 src_reg = SET_SRC (set);
7509 for (k = 0; k < n_reloads; k++)
7511 if (rld[k].in == src_reg)
7513 src_reg = rld[k].reg_rtx;
7520 store_insn = new_spill_reg_store[REGNO (src_reg)];
7521 if (src_reg && REG_P (src_reg)
7522 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7524 int src_regno = REGNO (src_reg);
7525 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7526 /* The place where to find a death note varies with
7527 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7528 necessarily checked exactly in the code that moves
7529 notes, so just check both locations. */
7530 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7531 if (! note && store_insn)
7532 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7535 spill_reg_store[src_regno + nr] = store_insn;
7536 spill_reg_stored_to[src_regno + nr] = out;
7537 reg_reloaded_contents[src_regno + nr] = nregno;
7538 reg_reloaded_insn[src_regno + nr] = store_insn;
7539 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7540 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7541 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7542 GET_MODE (src_reg)))
7543 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7545 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7547 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7549 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7551 reg_last_reload_reg[nregno] = src_reg;
7552 /* We have to set reg_has_output_reload here, or else
7553 forget_old_reloads_1 will clear reg_last_reload_reg
7555 SET_REGNO_REG_SET (®_has_output_reload,
7561 int num_regs = hard_regno_nregs[nregno][GET_MODE (out)];
7563 while (num_regs-- > 0)
7564 reg_last_reload_reg[nregno + num_regs] = 0;
7568 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7571 /* Go through the motions to emit INSN and test if it is strictly valid.
7572 Return the emitted insn if valid, else return NULL. */
7575 emit_insn_if_valid_for_reload (rtx insn)
7577 rtx last = get_last_insn ();
7580 insn = emit_insn (insn);
7581 code = recog_memoized (insn);
7585 extract_insn (insn);
7586 /* We want constrain operands to treat this insn strictly in its
7587 validity determination, i.e., the way it would after reload has
7589 if (constrain_operands (1))
7593 delete_insns_since (last);
7597 /* Emit code to perform a reload from IN (which may be a reload register) to
7598 OUT (which may also be a reload register). IN or OUT is from operand
7599 OPNUM with reload type TYPE.
7601 Returns first insn emitted. */
7604 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7606 rtx last = get_last_insn ();
7609 /* If IN is a paradoxical SUBREG, remove it and try to put the
7610 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7611 if (GET_CODE (in) == SUBREG
7612 && (GET_MODE_SIZE (GET_MODE (in))
7613 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7614 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7615 in = SUBREG_REG (in), out = tem;
7616 else if (GET_CODE (out) == SUBREG
7617 && (GET_MODE_SIZE (GET_MODE (out))
7618 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7619 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7620 out = SUBREG_REG (out), in = tem;
7622 /* How to do this reload can get quite tricky. Normally, we are being
7623 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7624 register that didn't get a hard register. In that case we can just
7625 call emit_move_insn.
7627 We can also be asked to reload a PLUS that adds a register or a MEM to
7628 another register, constant or MEM. This can occur during frame pointer
7629 elimination and while reloading addresses. This case is handled by
7630 trying to emit a single insn to perform the add. If it is not valid,
7631 we use a two insn sequence.
7633 Or we can be asked to reload an unary operand that was a fragment of
7634 an addressing mode, into a register. If it isn't recognized as-is,
7635 we try making the unop operand and the reload-register the same:
7636 (set reg:X (unop:X expr:Y))
7637 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
7639 Finally, we could be called to handle an 'o' constraint by putting
7640 an address into a register. In that case, we first try to do this
7641 with a named pattern of "reload_load_address". If no such pattern
7642 exists, we just emit a SET insn and hope for the best (it will normally
7643 be valid on machines that use 'o').
7645 This entire process is made complex because reload will never
7646 process the insns we generate here and so we must ensure that
7647 they will fit their constraints and also by the fact that parts of
7648 IN might be being reloaded separately and replaced with spill registers.
7649 Because of this, we are, in some sense, just guessing the right approach
7650 here. The one listed above seems to work.
7652 ??? At some point, this whole thing needs to be rethought. */
7654 if (GET_CODE (in) == PLUS
7655 && (REG_P (XEXP (in, 0))
7656 || GET_CODE (XEXP (in, 0)) == SUBREG
7657 || MEM_P (XEXP (in, 0)))
7658 && (REG_P (XEXP (in, 1))
7659 || GET_CODE (XEXP (in, 1)) == SUBREG
7660 || CONSTANT_P (XEXP (in, 1))
7661 || MEM_P (XEXP (in, 1))))
7663 /* We need to compute the sum of a register or a MEM and another
7664 register, constant, or MEM, and put it into the reload
7665 register. The best possible way of doing this is if the machine
7666 has a three-operand ADD insn that accepts the required operands.
7668 The simplest approach is to try to generate such an insn and see if it
7669 is recognized and matches its constraints. If so, it can be used.
7671 It might be better not to actually emit the insn unless it is valid,
7672 but we need to pass the insn as an operand to `recog' and
7673 `extract_insn' and it is simpler to emit and then delete the insn if
7674 not valid than to dummy things up. */
7676 rtx op0, op1, tem, insn;
7679 op0 = find_replacement (&XEXP (in, 0));
7680 op1 = find_replacement (&XEXP (in, 1));
7682 /* Since constraint checking is strict, commutativity won't be
7683 checked, so we need to do that here to avoid spurious failure
7684 if the add instruction is two-address and the second operand
7685 of the add is the same as the reload reg, which is frequently
7686 the case. If the insn would be A = B + A, rearrange it so
7687 it will be A = A + B as constrain_operands expects. */
7689 if (REG_P (XEXP (in, 1))
7690 && REGNO (out) == REGNO (XEXP (in, 1)))
7691 tem = op0, op0 = op1, op1 = tem;
7693 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7694 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7696 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7700 /* If that failed, we must use a conservative two-insn sequence.
7702 Use a move to copy one operand into the reload register. Prefer
7703 to reload a constant, MEM or pseudo since the move patterns can
7704 handle an arbitrary operand. If OP1 is not a constant, MEM or
7705 pseudo and OP1 is not a valid operand for an add instruction, then
7708 After reloading one of the operands into the reload register, add
7709 the reload register to the output register.
7711 If there is another way to do this for a specific machine, a
7712 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7715 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7717 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7719 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7720 || (code != CODE_FOR_nothing
7721 && ! ((*insn_data[code].operand[2].predicate)
7722 (op1, insn_data[code].operand[2].mode))))
7723 tem = op0, op0 = op1, op1 = tem;
7725 gen_reload (out, op0, opnum, type);
7727 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7728 This fixes a problem on the 32K where the stack pointer cannot
7729 be used as an operand of an add insn. */
7731 if (rtx_equal_p (op0, op1))
7734 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
7737 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7739 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7743 /* If that failed, copy the address register to the reload register.
7744 Then add the constant to the reload register. */
7746 gen_reload (out, op1, opnum, type);
7747 insn = emit_insn (gen_add2_insn (out, op0));
7748 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7751 #ifdef SECONDARY_MEMORY_NEEDED
7752 /* If we need a memory location to do the move, do it that way. */
7753 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7754 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7755 && (REG_P (out) || GET_CODE (out) == SUBREG)
7756 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7757 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7758 REGNO_REG_CLASS (reg_or_subregno (out)),
7761 /* Get the memory to use and rewrite both registers to its mode. */
7762 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7764 if (GET_MODE (loc) != GET_MODE (out))
7765 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7767 if (GET_MODE (loc) != GET_MODE (in))
7768 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7770 gen_reload (loc, in, opnum, type);
7771 gen_reload (out, loc, opnum, type);
7774 else if (REG_P (out) && UNARY_P (in))
7781 op1 = find_replacement (&XEXP (in, 0));
7782 if (op1 != XEXP (in, 0))
7783 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
7785 /* First, try a plain SET. */
7786 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7790 /* If that failed, move the inner operand to the reload
7791 register, and try the same unop with the inner expression
7792 replaced with the reload register. */
7794 if (GET_MODE (op1) != GET_MODE (out))
7795 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
7799 gen_reload (out_moded, op1, opnum, type);
7802 = gen_rtx_SET (VOIDmode, out,
7803 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
7805 insn = emit_insn_if_valid_for_reload (insn);
7809 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7813 fatal_insn ("Failure trying to reload:", set);
7815 /* If IN is a simple operand, use gen_move_insn. */
7816 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
7818 tem = emit_insn (gen_move_insn (out, in));
7819 /* IN may contain a LABEL_REF, if so add a REG_LABEL note. */
7820 mark_jump_label (in, tem, 0);
7823 #ifdef HAVE_reload_load_address
7824 else if (HAVE_reload_load_address)
7825 emit_insn (gen_reload_load_address (out, in));
7828 /* Otherwise, just write (set OUT IN) and hope for the best. */
7830 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7832 /* Return the first insn emitted.
7833 We can not just return get_last_insn, because there may have
7834 been multiple instructions emitted. Also note that gen_move_insn may
7835 emit more than one insn itself, so we can not assume that there is one
7836 insn emitted per emit_insn_before call. */
7838 return last ? NEXT_INSN (last) : get_insns ();
7841 /* Delete a previously made output-reload whose result we now believe
7842 is not needed. First we double-check.
7844 INSN is the insn now being processed.
7845 LAST_RELOAD_REG is the hard register number for which we want to delete
7846 the last output reload.
7847 J is the reload-number that originally used REG. The caller has made
7848 certain that reload J doesn't use REG any longer for input. */
7851 delete_output_reload (rtx insn, int j, int last_reload_reg)
7853 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7854 rtx reg = spill_reg_stored_to[last_reload_reg];
7857 int n_inherited = 0;
7861 /* It is possible that this reload has been only used to set another reload
7862 we eliminated earlier and thus deleted this instruction too. */
7863 if (INSN_DELETED_P (output_reload_insn))
7866 /* Get the raw pseudo-register referred to. */
7868 while (GET_CODE (reg) == SUBREG)
7869 reg = SUBREG_REG (reg);
7870 substed = reg_equiv_memory_loc[REGNO (reg)];
7872 /* This is unsafe if the operand occurs more often in the current
7873 insn than it is inherited. */
7874 for (k = n_reloads - 1; k >= 0; k--)
7876 rtx reg2 = rld[k].in;
7879 if (MEM_P (reg2) || reload_override_in[k])
7880 reg2 = rld[k].in_reg;
7882 if (rld[k].out && ! rld[k].out_reg)
7883 reg2 = XEXP (rld[k].in_reg, 0);
7885 while (GET_CODE (reg2) == SUBREG)
7886 reg2 = SUBREG_REG (reg2);
7887 if (rtx_equal_p (reg2, reg))
7889 if (reload_inherited[k] || reload_override_in[k] || k == j)
7892 reg2 = rld[k].out_reg;
7895 while (GET_CODE (reg2) == SUBREG)
7896 reg2 = XEXP (reg2, 0);
7897 if (rtx_equal_p (reg2, reg))
7904 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7906 n_occurrences += count_occurrences (PATTERN (insn),
7907 eliminate_regs (substed, 0,
7909 for (i1 = reg_equiv_alt_mem_list [REGNO (reg)]; i1; i1 = XEXP (i1, 1))
7911 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
7912 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
7914 if (n_occurrences > n_inherited)
7917 /* If the pseudo-reg we are reloading is no longer referenced
7918 anywhere between the store into it and here,
7919 and we're within the same basic block, then the value can only
7920 pass through the reload reg and end up here.
7921 Otherwise, give up--return. */
7922 for (i1 = NEXT_INSN (output_reload_insn);
7923 i1 != insn; i1 = NEXT_INSN (i1))
7925 if (NOTE_INSN_BASIC_BLOCK_P (i1))
7927 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
7928 && reg_mentioned_p (reg, PATTERN (i1)))
7930 /* If this is USE in front of INSN, we only have to check that
7931 there are no more references than accounted for by inheritance. */
7932 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
7934 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7935 i1 = NEXT_INSN (i1);
7937 if (n_occurrences <= n_inherited && i1 == insn)
7943 /* We will be deleting the insn. Remove the spill reg information. */
7944 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
7946 spill_reg_store[last_reload_reg + k] = 0;
7947 spill_reg_stored_to[last_reload_reg + k] = 0;
7950 /* The caller has already checked that REG dies or is set in INSN.
7951 It has also checked that we are optimizing, and thus some
7952 inaccuracies in the debugging information are acceptable.
7953 So we could just delete output_reload_insn. But in some cases
7954 we can improve the debugging information without sacrificing
7955 optimization - maybe even improving the code: See if the pseudo
7956 reg has been completely replaced with reload regs. If so, delete
7957 the store insn and forget we had a stack slot for the pseudo. */
7958 if (rld[j].out != rld[j].in
7959 && REG_N_DEATHS (REGNO (reg)) == 1
7960 && REG_N_SETS (REGNO (reg)) == 1
7961 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7962 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7966 /* We know that it was used only between here and the beginning of
7967 the current basic block. (We also know that the last use before
7968 INSN was the output reload we are thinking of deleting, but never
7969 mind that.) Search that range; see if any ref remains. */
7970 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7972 rtx set = single_set (i2);
7974 /* Uses which just store in the pseudo don't count,
7975 since if they are the only uses, they are dead. */
7976 if (set != 0 && SET_DEST (set) == reg)
7981 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
7982 && reg_mentioned_p (reg, PATTERN (i2)))
7984 /* Some other ref remains; just delete the output reload we
7986 delete_address_reloads (output_reload_insn, insn);
7987 delete_insn (output_reload_insn);
7992 /* Delete the now-dead stores into this pseudo. Note that this
7993 loop also takes care of deleting output_reload_insn. */
7994 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7996 rtx set = single_set (i2);
7998 if (set != 0 && SET_DEST (set) == reg)
8000 delete_address_reloads (i2, insn);
8008 /* For the debugging info, say the pseudo lives in this reload reg. */
8009 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
8010 alter_reg (REGNO (reg), -1);
8014 delete_address_reloads (output_reload_insn, insn);
8015 delete_insn (output_reload_insn);
8019 /* We are going to delete DEAD_INSN. Recursively delete loads of
8020 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8021 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8023 delete_address_reloads (rtx dead_insn, rtx current_insn)
8025 rtx set = single_set (dead_insn);
8026 rtx set2, dst, prev, next;
8029 rtx dst = SET_DEST (set);
8031 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8033 /* If we deleted the store from a reloaded post_{in,de}c expression,
8034 we can delete the matching adds. */
8035 prev = PREV_INSN (dead_insn);
8036 next = NEXT_INSN (dead_insn);
8037 if (! prev || ! next)
8039 set = single_set (next);
8040 set2 = single_set (prev);
8042 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8043 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8044 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8046 dst = SET_DEST (set);
8047 if (! rtx_equal_p (dst, SET_DEST (set2))
8048 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8049 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8050 || (INTVAL (XEXP (SET_SRC (set), 1))
8051 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8053 delete_related_insns (prev);
8054 delete_related_insns (next);
8057 /* Subfunction of delete_address_reloads: process registers found in X. */
8059 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8061 rtx prev, set, dst, i2;
8063 enum rtx_code code = GET_CODE (x);
8067 const char *fmt = GET_RTX_FORMAT (code);
8068 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8071 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8072 else if (fmt[i] == 'E')
8074 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8075 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8082 if (spill_reg_order[REGNO (x)] < 0)
8085 /* Scan backwards for the insn that sets x. This might be a way back due
8087 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8089 code = GET_CODE (prev);
8090 if (code == CODE_LABEL || code == JUMP_INSN)
8094 if (reg_set_p (x, PATTERN (prev)))
8096 if (reg_referenced_p (x, PATTERN (prev)))
8099 if (! prev || INSN_UID (prev) < reload_first_uid)
8101 /* Check that PREV only sets the reload register. */
8102 set = single_set (prev);
8105 dst = SET_DEST (set);
8107 || ! rtx_equal_p (dst, x))
8109 if (! reg_set_p (dst, PATTERN (dead_insn)))
8111 /* Check if DST was used in a later insn -
8112 it might have been inherited. */
8113 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8119 if (reg_referenced_p (dst, PATTERN (i2)))
8121 /* If there is a reference to the register in the current insn,
8122 it might be loaded in a non-inherited reload. If no other
8123 reload uses it, that means the register is set before
8125 if (i2 == current_insn)
8127 for (j = n_reloads - 1; j >= 0; j--)
8128 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8129 || reload_override_in[j] == dst)
8131 for (j = n_reloads - 1; j >= 0; j--)
8132 if (rld[j].in && rld[j].reg_rtx == dst)
8141 /* If DST is still live at CURRENT_INSN, check if it is used for
8142 any reload. Note that even if CURRENT_INSN sets DST, we still
8143 have to check the reloads. */
8144 if (i2 == current_insn)
8146 for (j = n_reloads - 1; j >= 0; j--)
8147 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8148 || reload_override_in[j] == dst)
8150 /* ??? We can't finish the loop here, because dst might be
8151 allocated to a pseudo in this block if no reload in this
8152 block needs any of the classes containing DST - see
8153 spill_hard_reg. There is no easy way to tell this, so we
8154 have to scan till the end of the basic block. */
8156 if (reg_set_p (dst, PATTERN (i2)))
8160 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8161 reg_reloaded_contents[REGNO (dst)] = -1;
8165 /* Output reload-insns to reload VALUE into RELOADREG.
8166 VALUE is an autoincrement or autodecrement RTX whose operand
8167 is a register or memory location;
8168 so reloading involves incrementing that location.
8169 IN is either identical to VALUE, or some cheaper place to reload from.
8171 INC_AMOUNT is the number to increment or decrement by (always positive).
8172 This cannot be deduced from VALUE.
8174 Return the instruction that stores into RELOADREG. */
8177 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8179 /* REG or MEM to be copied and incremented. */
8180 rtx incloc = find_replacement (&XEXP (value, 0));
8181 /* Nonzero if increment after copying. */
8182 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8183 || GET_CODE (value) == POST_MODIFY);
8189 rtx real_in = in == value ? incloc : in;
8191 /* No hard register is equivalent to this register after
8192 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8193 we could inc/dec that register as well (maybe even using it for
8194 the source), but I'm not sure it's worth worrying about. */
8196 reg_last_reload_reg[REGNO (incloc)] = 0;
8198 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8200 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8201 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
8205 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8206 inc_amount = -inc_amount;
8208 inc = GEN_INT (inc_amount);
8211 /* If this is post-increment, first copy the location to the reload reg. */
8212 if (post && real_in != reloadreg)
8213 emit_insn (gen_move_insn (reloadreg, real_in));
8217 /* See if we can directly increment INCLOC. Use a method similar to
8218 that in gen_reload. */
8220 last = get_last_insn ();
8221 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8222 gen_rtx_PLUS (GET_MODE (incloc),
8225 code = recog_memoized (add_insn);
8228 extract_insn (add_insn);
8229 if (constrain_operands (1))
8231 /* If this is a pre-increment and we have incremented the value
8232 where it lives, copy the incremented value to RELOADREG to
8233 be used as an address. */
8236 emit_insn (gen_move_insn (reloadreg, incloc));
8241 delete_insns_since (last);
8244 /* If couldn't do the increment directly, must increment in RELOADREG.
8245 The way we do this depends on whether this is pre- or post-increment.
8246 For pre-increment, copy INCLOC to the reload register, increment it
8247 there, then save back. */
8251 if (in != reloadreg)
8252 emit_insn (gen_move_insn (reloadreg, real_in));
8253 emit_insn (gen_add2_insn (reloadreg, inc));
8254 store = emit_insn (gen_move_insn (incloc, reloadreg));
8259 Because this might be a jump insn or a compare, and because RELOADREG
8260 may not be available after the insn in an input reload, we must do
8261 the incrementation before the insn being reloaded for.
8263 We have already copied IN to RELOADREG. Increment the copy in
8264 RELOADREG, save that back, then decrement RELOADREG so it has
8265 the original value. */
8267 emit_insn (gen_add2_insn (reloadreg, inc));
8268 store = emit_insn (gen_move_insn (incloc, reloadreg));
8269 if (GET_CODE (inc) == CONST_INT)
8270 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL(inc))));
8272 emit_insn (gen_sub2_insn (reloadreg, inc));
8280 add_auto_inc_notes (rtx insn, rtx x)
8282 enum rtx_code code = GET_CODE (x);
8286 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8289 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8293 /* Scan all the operand sub-expressions. */
8294 fmt = GET_RTX_FORMAT (code);
8295 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8298 add_auto_inc_notes (insn, XEXP (x, i));
8299 else if (fmt[i] == 'E')
8300 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8301 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8306 /* Copy EH notes from an insn to its reloads. */
8308 copy_eh_notes (rtx insn, rtx x)
8310 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8313 for (; x != 0; x = NEXT_INSN (x))
8315 if (may_trap_p (PATTERN (x)))
8317 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8323 /* This is used by reload pass, that does emit some instructions after
8324 abnormal calls moving basic block end, but in fact it wants to emit
8325 them on the edge. Looks for abnormal call edges, find backward the
8326 proper call and fix the damage.
8328 Similar handle instructions throwing exceptions internally. */
8330 fixup_abnormal_edges (void)
8332 bool inserted = false;
8340 /* Look for cases we are interested in - calls or instructions causing
8342 FOR_EACH_EDGE (e, ei, bb->succs)
8344 if (e->flags & EDGE_ABNORMAL_CALL)
8346 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8347 == (EDGE_ABNORMAL | EDGE_EH))
8350 if (e && !CALL_P (BB_END (bb))
8351 && !can_throw_internal (BB_END (bb)))
8355 /* Get past the new insns generated. Allow notes, as the insns
8356 may be already deleted. */
8358 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8359 && !can_throw_internal (insn)
8360 && insn != BB_HEAD (bb))
8361 insn = PREV_INSN (insn);
8363 if (CALL_P (insn) || can_throw_internal (insn))
8367 stop = NEXT_INSN (BB_END (bb));
8369 insn = NEXT_INSN (insn);
8371 FOR_EACH_EDGE (e, ei, bb->succs)
8372 if (e->flags & EDGE_FALLTHRU)
8375 while (insn && insn != stop)
8377 next = NEXT_INSN (insn);
8382 /* Sometimes there's still the return value USE.
8383 If it's placed after a trapping call (i.e. that
8384 call is the last insn anyway), we have no fallthru
8385 edge. Simply delete this use and don't try to insert
8386 on the non-existent edge. */
8387 if (GET_CODE (PATTERN (insn)) != USE)
8389 /* We're not deleting it, we're moving it. */
8390 INSN_DELETED_P (insn) = 0;
8391 PREV_INSN (insn) = NULL_RTX;
8392 NEXT_INSN (insn) = NULL_RTX;
8394 insert_insn_on_edge (insn, e);
8402 /* It may be that we don't find any such trapping insn. In this
8403 case we discovered quite late that the insn that had been
8404 marked as can_throw_internal in fact couldn't trap at all.
8405 So we should in fact delete the EH edges out of the block. */
8407 purge_dead_edges (bb);
8411 /* We've possibly turned single trapping insn into multiple ones. */
8412 if (flag_non_call_exceptions)
8415 blocks = sbitmap_alloc (last_basic_block);
8416 sbitmap_ones (blocks);
8417 find_many_sub_basic_blocks (blocks);
8421 commit_edge_insertions ();
8423 #ifdef ENABLE_CHECKING
8424 /* Verify that we didn't turn one trapping insn into many, and that
8425 we found and corrected all of the problems wrt fixups on the
8427 verify_flow_info ();
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