1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
48 /* This file contains the reload pass of the compiler, which is
49 run after register allocation has been done. It checks that
50 each insn is valid (operands required to be in registers really
51 are in registers of the proper class) and fixes up invalid ones
52 by copying values temporarily into registers for the insns
55 The results of register allocation are described by the vector
56 reg_renumber; the insns still contain pseudo regs, but reg_renumber
57 can be used to find which hard reg, if any, a pseudo reg is in.
59 The technique we always use is to free up a few hard regs that are
60 called ``reload regs'', and for each place where a pseudo reg
61 must be in a hard reg, copy it temporarily into one of the reload regs.
63 Reload regs are allocated locally for every instruction that needs
64 reloads. When there are pseudos which are allocated to a register that
65 has been chosen as a reload reg, such pseudos must be ``spilled''.
66 This means that they go to other hard regs, or to stack slots if no other
67 available hard regs can be found. Spilling can invalidate more
68 insns, requiring additional need for reloads, so we must keep checking
69 until the process stabilizes.
71 For machines with different classes of registers, we must keep track
72 of the register class needed for each reload, and make sure that
73 we allocate enough reload registers of each class.
75 The file reload.c contains the code that checks one insn for
76 validity and reports the reloads that it needs. This file
77 is in charge of scanning the entire rtl code, accumulating the
78 reload needs, spilling, assigning reload registers to use for
79 fixing up each insn, and generating the new insns to copy values
80 into the reload registers. */
82 /* During reload_as_needed, element N contains a REG rtx for the hard reg
83 into which reg N has been reloaded (perhaps for a previous insn). */
84 static rtx *reg_last_reload_reg;
86 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
87 for an output reload that stores into reg N. */
88 static char *reg_has_output_reload;
90 /* Indicates which hard regs are reload-registers for an output reload
91 in the current insn. */
92 static HARD_REG_SET reg_is_output_reload;
94 /* Element N is the constant value to which pseudo reg N is equivalent,
95 or zero if pseudo reg N is not equivalent to a constant.
96 find_reloads looks at this in order to replace pseudo reg N
97 with the constant it stands for. */
98 rtx *reg_equiv_constant;
100 /* Element N is an invariant value to which pseudo reg N is equivalent.
101 eliminate_regs_in_insn uses this to replace pseudos in particular
103 rtx *reg_equiv_invariant;
105 /* Element N is a memory location to which pseudo reg N is equivalent,
106 prior to any register elimination (such as frame pointer to stack
107 pointer). Depending on whether or not it is a valid address, this value
108 is transferred to either reg_equiv_address or reg_equiv_mem. */
109 rtx *reg_equiv_memory_loc;
111 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
112 collector can keep track of what is inside. */
113 varray_type reg_equiv_memory_loc_varray;
115 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
116 This is used when the address is not valid as a memory address
117 (because its displacement is too big for the machine.) */
118 rtx *reg_equiv_address;
120 /* Element N is the memory slot to which pseudo reg N is equivalent,
121 or zero if pseudo reg N is not equivalent to a memory slot. */
124 /* Widest width in which each pseudo reg is referred to (via subreg). */
125 static unsigned int *reg_max_ref_width;
127 /* Element N is the list of insns that initialized reg N from its equivalent
128 constant or memory slot. */
130 int reg_equiv_init_size;
132 /* Vector to remember old contents of reg_renumber before spilling. */
133 static short *reg_old_renumber;
135 /* During reload_as_needed, element N contains the last pseudo regno reloaded
136 into hard register N. If that pseudo reg occupied more than one register,
137 reg_reloaded_contents points to that pseudo for each spill register in
138 use; all of these must remain set for an inheritance to occur. */
139 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
141 /* During reload_as_needed, element N contains the insn for which
142 hard register N was last used. Its contents are significant only
143 when reg_reloaded_valid is set for this register. */
144 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
146 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
147 static HARD_REG_SET reg_reloaded_valid;
148 /* Indicate if the register was dead at the end of the reload.
149 This is only valid if reg_reloaded_contents is set and valid. */
150 static HARD_REG_SET reg_reloaded_dead;
152 /* Indicate whether the register's current value is one that is not
153 safe to retain across a call, even for registers that are normally
155 static HARD_REG_SET reg_reloaded_call_part_clobbered;
157 /* Number of spill-regs so far; number of valid elements of spill_regs. */
160 /* In parallel with spill_regs, contains REG rtx's for those regs.
161 Holds the last rtx used for any given reg, or 0 if it has never
162 been used for spilling yet. This rtx is reused, provided it has
164 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
166 /* In parallel with spill_regs, contains nonzero for a spill reg
167 that was stored after the last time it was used.
168 The precise value is the insn generated to do the store. */
169 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
171 /* This is the register that was stored with spill_reg_store. This is a
172 copy of reload_out / reload_out_reg when the value was stored; if
173 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
174 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
176 /* This table is the inverse mapping of spill_regs:
177 indexed by hard reg number,
178 it contains the position of that reg in spill_regs,
179 or -1 for something that is not in spill_regs.
181 ?!? This is no longer accurate. */
182 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
184 /* This reg set indicates registers that can't be used as spill registers for
185 the currently processed insn. These are the hard registers which are live
186 during the insn, but not allocated to pseudos, as well as fixed
188 static HARD_REG_SET bad_spill_regs;
190 /* These are the hard registers that can't be used as spill register for any
191 insn. This includes registers used for user variables and registers that
192 we can't eliminate. A register that appears in this set also can't be used
193 to retry register allocation. */
194 static HARD_REG_SET bad_spill_regs_global;
196 /* Describes order of use of registers for reloading
197 of spilled pseudo-registers. `n_spills' is the number of
198 elements that are actually valid; new ones are added at the end.
200 Both spill_regs and spill_reg_order are used on two occasions:
201 once during find_reload_regs, where they keep track of the spill registers
202 for a single insn, but also during reload_as_needed where they show all
203 the registers ever used by reload. For the latter case, the information
204 is calculated during finish_spills. */
205 static short spill_regs[FIRST_PSEUDO_REGISTER];
207 /* This vector of reg sets indicates, for each pseudo, which hard registers
208 may not be used for retrying global allocation because the register was
209 formerly spilled from one of them. If we allowed reallocating a pseudo to
210 a register that it was already allocated to, reload might not
212 static HARD_REG_SET *pseudo_previous_regs;
214 /* This vector of reg sets indicates, for each pseudo, which hard
215 registers may not be used for retrying global allocation because they
216 are used as spill registers during one of the insns in which the
218 static HARD_REG_SET *pseudo_forbidden_regs;
220 /* All hard regs that have been used as spill registers for any insn are
221 marked in this set. */
222 static HARD_REG_SET used_spill_regs;
224 /* Index of last register assigned as a spill register. We allocate in
225 a round-robin fashion. */
226 static int last_spill_reg;
228 /* Nonzero if indirect addressing is supported on the machine; this means
229 that spilling (REG n) does not require reloading it into a register in
230 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
231 value indicates the level of indirect addressing supported, e.g., two
232 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
234 static char spill_indirect_levels;
236 /* Nonzero if indirect addressing is supported when the innermost MEM is
237 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
238 which these are valid is the same as spill_indirect_levels, above. */
239 char indirect_symref_ok;
241 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
242 char double_reg_address_ok;
244 /* Record the stack slot for each spilled hard register. */
245 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
247 /* Width allocated so far for that stack slot. */
248 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
250 /* Record which pseudos needed to be spilled. */
251 static regset_head spilled_pseudos;
253 /* Used for communication between order_regs_for_reload and count_pseudo.
254 Used to avoid counting one pseudo twice. */
255 static regset_head pseudos_counted;
257 /* First uid used by insns created by reload in this function.
258 Used in find_equiv_reg. */
259 int reload_first_uid;
261 /* Flag set by local-alloc or global-alloc if anything is live in
262 a call-clobbered reg across calls. */
263 int caller_save_needed;
265 /* Set to 1 while reload_as_needed is operating.
266 Required by some machines to handle any generated moves differently. */
267 int reload_in_progress = 0;
269 /* These arrays record the insn_code of insns that may be needed to
270 perform input and output reloads of special objects. They provide a
271 place to pass a scratch register. */
272 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
273 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
275 /* This obstack is used for allocation of rtl during register elimination.
276 The allocated storage can be freed once find_reloads has processed the
278 static struct obstack reload_obstack;
280 /* Points to the beginning of the reload_obstack. All insn_chain structures
281 are allocated first. */
282 static char *reload_startobj;
284 /* The point after all insn_chain structures. Used to quickly deallocate
285 memory allocated in copy_reloads during calculate_needs_all_insns. */
286 static char *reload_firstobj;
288 /* This points before all local rtl generated by register elimination.
289 Used to quickly free all memory after processing one insn. */
290 static char *reload_insn_firstobj;
292 /* List of insn_chain instructions, one for every insn that reload needs to
294 struct insn_chain *reload_insn_chain;
296 /* List of all insns needing reloads. */
297 static struct insn_chain *insns_need_reload;
299 /* This structure is used to record information about register eliminations.
300 Each array entry describes one possible way of eliminating a register
301 in favor of another. If there is more than one way of eliminating a
302 particular register, the most preferred should be specified first. */
306 int from; /* Register number to be eliminated. */
307 int to; /* Register number used as replacement. */
308 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
309 int can_eliminate; /* Nonzero if this elimination can be done. */
310 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
311 insns made by reload. */
312 HOST_WIDE_INT offset; /* Current offset between the two regs. */
313 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
314 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
315 rtx from_rtx; /* REG rtx for the register to be eliminated.
316 We cannot simply compare the number since
317 we might then spuriously replace a hard
318 register corresponding to a pseudo
319 assigned to the reg to be eliminated. */
320 rtx to_rtx; /* REG rtx for the replacement. */
323 static struct elim_table *reg_eliminate = 0;
325 /* This is an intermediate structure to initialize the table. It has
326 exactly the members provided by ELIMINABLE_REGS. */
327 static const struct elim_table_1
331 } reg_eliminate_1[] =
333 /* If a set of eliminable registers was specified, define the table from it.
334 Otherwise, default to the normal case of the frame pointer being
335 replaced by the stack pointer. */
337 #ifdef ELIMINABLE_REGS
340 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
343 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
345 /* Record the number of pending eliminations that have an offset not equal
346 to their initial offset. If nonzero, we use a new copy of each
347 replacement result in any insns encountered. */
348 int num_not_at_initial_offset;
350 /* Count the number of registers that we may be able to eliminate. */
351 static int num_eliminable;
352 /* And the number of registers that are equivalent to a constant that
353 can be eliminated to frame_pointer / arg_pointer + constant. */
354 static int num_eliminable_invariants;
356 /* For each label, we record the offset of each elimination. If we reach
357 a label by more than one path and an offset differs, we cannot do the
358 elimination. This information is indexed by the difference of the
359 number of the label and the first label number. We can't offset the
360 pointer itself as this can cause problems on machines with segmented
361 memory. The first table is an array of flags that records whether we
362 have yet encountered a label and the second table is an array of arrays,
363 one entry in the latter array for each elimination. */
365 static int first_label_num;
366 static char *offsets_known_at;
367 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
369 /* Number of labels in the current function. */
371 static int num_labels;
373 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
374 static void maybe_fix_stack_asms (void);
375 static void copy_reloads (struct insn_chain *);
376 static void calculate_needs_all_insns (int);
377 static int find_reg (struct insn_chain *, int);
378 static void find_reload_regs (struct insn_chain *);
379 static void select_reload_regs (void);
380 static void delete_caller_save_insns (void);
382 static void spill_failure (rtx, enum reg_class);
383 static void count_spilled_pseudo (int, int, int);
384 static void delete_dead_insn (rtx);
385 static void alter_reg (int, int);
386 static void set_label_offsets (rtx, rtx, int);
387 static void check_eliminable_occurrences (rtx);
388 static void elimination_effects (rtx, enum machine_mode);
389 static int eliminate_regs_in_insn (rtx, int);
390 static void update_eliminable_offsets (void);
391 static void mark_not_eliminable (rtx, rtx, void *);
392 static void set_initial_elim_offsets (void);
393 static bool verify_initial_elim_offsets (void);
394 static void set_initial_label_offsets (void);
395 static void set_offsets_for_label (rtx);
396 static void init_elim_table (void);
397 static void update_eliminables (HARD_REG_SET *);
398 static void spill_hard_reg (unsigned int, int);
399 static int finish_spills (int);
400 static void scan_paradoxical_subregs (rtx);
401 static void count_pseudo (int);
402 static void order_regs_for_reload (struct insn_chain *);
403 static void reload_as_needed (int);
404 static void forget_old_reloads_1 (rtx, rtx, void *);
405 static int reload_reg_class_lower (const void *, const void *);
406 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
408 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
410 static int reload_reg_free_p (unsigned int, int, enum reload_type);
411 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
413 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
415 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
416 static int allocate_reload_reg (struct insn_chain *, int, int);
417 static int conflicts_with_override (rtx);
418 static void failed_reload (rtx, int);
419 static int set_reload_reg (int, int);
420 static void choose_reload_regs_init (struct insn_chain *, rtx *);
421 static void choose_reload_regs (struct insn_chain *);
422 static void merge_assigned_reloads (rtx);
423 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
425 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
427 static void do_input_reload (struct insn_chain *, struct reload *, int);
428 static void do_output_reload (struct insn_chain *, struct reload *, int);
429 static bool inherit_piecemeal_p (int, int);
430 static void emit_reload_insns (struct insn_chain *);
431 static void delete_output_reload (rtx, int, int);
432 static void delete_address_reloads (rtx, rtx);
433 static void delete_address_reloads_1 (rtx, rtx, rtx);
434 static rtx inc_for_reload (rtx, rtx, rtx, int);
436 static void add_auto_inc_notes (rtx, rtx);
438 static void copy_eh_notes (rtx, rtx);
439 static int reloads_conflict (int, int);
440 static rtx gen_reload (rtx, rtx, int, enum reload_type);
441 static rtx emit_insn_if_valid_for_reload (rtx);
443 /* Initialize the reload pass once per compilation. */
450 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
451 Set spill_indirect_levels to the number of levels such addressing is
452 permitted, zero if it is not permitted at all. */
455 = gen_rtx_MEM (Pmode,
458 LAST_VIRTUAL_REGISTER + 1),
460 spill_indirect_levels = 0;
462 while (memory_address_p (QImode, tem))
464 spill_indirect_levels++;
465 tem = gen_rtx_MEM (Pmode, tem);
468 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
470 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
471 indirect_symref_ok = memory_address_p (QImode, tem);
473 /* See if reg+reg is a valid (and offsettable) address. */
475 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
477 tem = gen_rtx_PLUS (Pmode,
478 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
479 gen_rtx_REG (Pmode, i));
481 /* This way, we make sure that reg+reg is an offsettable address. */
482 tem = plus_constant (tem, 4);
484 if (memory_address_p (QImode, tem))
486 double_reg_address_ok = 1;
491 /* Initialize obstack for our rtl allocation. */
492 gcc_obstack_init (&reload_obstack);
493 reload_startobj = obstack_alloc (&reload_obstack, 0);
495 INIT_REG_SET (&spilled_pseudos);
496 INIT_REG_SET (&pseudos_counted);
497 VARRAY_RTX_INIT (reg_equiv_memory_loc_varray, 0, "reg_equiv_memory_loc");
500 /* List of insn chains that are currently unused. */
501 static struct insn_chain *unused_insn_chains = 0;
503 /* Allocate an empty insn_chain structure. */
505 new_insn_chain (void)
507 struct insn_chain *c;
509 if (unused_insn_chains == 0)
511 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
512 INIT_REG_SET (&c->live_throughout);
513 INIT_REG_SET (&c->dead_or_set);
517 c = unused_insn_chains;
518 unused_insn_chains = c->next;
520 c->is_caller_save_insn = 0;
521 c->need_operand_change = 0;
527 /* Small utility function to set all regs in hard reg set TO which are
528 allocated to pseudos in regset FROM. */
531 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
534 reg_set_iterator rsi;
536 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
538 int r = reg_renumber[regno];
543 /* reload_combine uses the information from
544 BASIC_BLOCK->global_live_at_start, which might still
545 contain registers that have not actually been allocated
546 since they have an equivalence. */
547 gcc_assert (reload_completed);
551 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)];
553 SET_HARD_REG_BIT (*to, r + nregs);
558 /* Replace all pseudos found in LOC with their corresponding
562 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
575 unsigned int regno = REGNO (x);
577 if (regno < FIRST_PSEUDO_REGISTER)
580 x = eliminate_regs (x, mem_mode, usage);
584 replace_pseudos_in (loc, mem_mode, usage);
588 if (reg_equiv_constant[regno])
589 *loc = reg_equiv_constant[regno];
590 else if (reg_equiv_mem[regno])
591 *loc = reg_equiv_mem[regno];
592 else if (reg_equiv_address[regno])
593 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
596 gcc_assert (!REG_P (regno_reg_rtx[regno])
597 || REGNO (regno_reg_rtx[regno]) != regno);
598 *loc = regno_reg_rtx[regno];
603 else if (code == MEM)
605 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
609 /* Process each of our operands recursively. */
610 fmt = GET_RTX_FORMAT (code);
611 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
613 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
614 else if (*fmt == 'E')
615 for (j = 0; j < XVECLEN (x, i); j++)
616 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
620 /* Global variables used by reload and its subroutines. */
622 /* Set during calculate_needs if an insn needs register elimination. */
623 static int something_needs_elimination;
624 /* Set during calculate_needs if an insn needs an operand changed. */
625 static int something_needs_operands_changed;
627 /* Nonzero means we couldn't get enough spill regs. */
630 /* Main entry point for the reload pass.
632 FIRST is the first insn of the function being compiled.
634 GLOBAL nonzero means we were called from global_alloc
635 and should attempt to reallocate any pseudoregs that we
636 displace from hard regs we will use for reloads.
637 If GLOBAL is zero, we do not have enough information to do that,
638 so any pseudo reg that is spilled must go to the stack.
640 Return value is nonzero if reload failed
641 and we must not do any more for this function. */
644 reload (rtx first, int global)
648 struct elim_table *ep;
651 /* Make sure even insns with volatile mem refs are recognizable. */
656 reload_firstobj = obstack_alloc (&reload_obstack, 0);
658 /* Make sure that the last insn in the chain
659 is not something that needs reloading. */
660 emit_note (NOTE_INSN_DELETED);
662 /* Enable find_equiv_reg to distinguish insns made by reload. */
663 reload_first_uid = get_max_uid ();
665 #ifdef SECONDARY_MEMORY_NEEDED
666 /* Initialize the secondary memory table. */
667 clear_secondary_mem ();
670 /* We don't have a stack slot for any spill reg yet. */
671 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
672 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
674 /* Initialize the save area information for caller-save, in case some
678 /* Compute which hard registers are now in use
679 as homes for pseudo registers.
680 This is done here rather than (eg) in global_alloc
681 because this point is reached even if not optimizing. */
682 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
685 /* A function that receives a nonlocal goto must save all call-saved
687 if (current_function_has_nonlocal_label)
688 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
689 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
690 regs_ever_live[i] = 1;
692 /* Find all the pseudo registers that didn't get hard regs
693 but do have known equivalent constants or memory slots.
694 These include parameters (known equivalent to parameter slots)
695 and cse'd or loop-moved constant memory addresses.
697 Record constant equivalents in reg_equiv_constant
698 so they will be substituted by find_reloads.
699 Record memory equivalents in reg_mem_equiv so they can
700 be substituted eventually by altering the REG-rtx's. */
702 reg_equiv_constant = xcalloc (max_regno, sizeof (rtx));
703 reg_equiv_invariant = xcalloc (max_regno, sizeof (rtx));
704 reg_equiv_mem = xcalloc (max_regno, sizeof (rtx));
705 reg_equiv_address = xcalloc (max_regno, sizeof (rtx));
706 reg_max_ref_width = xcalloc (max_regno, sizeof (int));
707 reg_old_renumber = xcalloc (max_regno, sizeof (short));
708 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
709 pseudo_forbidden_regs = xmalloc (max_regno * sizeof (HARD_REG_SET));
710 pseudo_previous_regs = xcalloc (max_regno, sizeof (HARD_REG_SET));
712 CLEAR_HARD_REG_SET (bad_spill_regs_global);
714 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
715 to. Also find all paradoxical subregs and find largest such for
718 num_eliminable_invariants = 0;
719 for (insn = first; insn; insn = NEXT_INSN (insn))
721 rtx set = single_set (insn);
723 /* We may introduce USEs that we want to remove at the end, so
724 we'll mark them with QImode. Make sure there are no
725 previously-marked insns left by say regmove. */
726 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
727 && GET_MODE (insn) != VOIDmode)
728 PUT_MODE (insn, VOIDmode);
731 scan_paradoxical_subregs (PATTERN (insn));
733 if (set != 0 && REG_P (SET_DEST (set)))
735 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
741 i = REGNO (SET_DEST (set));
744 if (i <= LAST_VIRTUAL_REGISTER)
747 if (! function_invariant_p (x)
749 /* A function invariant is often CONSTANT_P but may
750 include a register. We promise to only pass
751 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
753 && LEGITIMATE_PIC_OPERAND_P (x)))
755 /* It can happen that a REG_EQUIV note contains a MEM
756 that is not a legitimate memory operand. As later
757 stages of reload assume that all addresses found
758 in the reg_equiv_* arrays were originally legitimate,
759 we ignore such REG_EQUIV notes. */
760 if (memory_operand (x, VOIDmode))
762 /* Always unshare the equivalence, so we can
763 substitute into this insn without touching the
765 reg_equiv_memory_loc[i] = copy_rtx (x);
767 else if (function_invariant_p (x))
769 if (GET_CODE (x) == PLUS)
771 /* This is PLUS of frame pointer and a constant,
772 and might be shared. Unshare it. */
773 reg_equiv_invariant[i] = copy_rtx (x);
774 num_eliminable_invariants++;
776 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
778 reg_equiv_invariant[i] = x;
779 num_eliminable_invariants++;
781 else if (LEGITIMATE_CONSTANT_P (x))
782 reg_equiv_constant[i] = x;
785 reg_equiv_memory_loc[i]
786 = force_const_mem (GET_MODE (SET_DEST (set)), x);
787 if (! reg_equiv_memory_loc[i])
788 reg_equiv_init[i] = NULL_RTX;
793 reg_equiv_init[i] = NULL_RTX;
798 reg_equiv_init[i] = NULL_RTX;
803 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
804 if (reg_equiv_init[i])
806 fprintf (dump_file, "init_insns for %u: ", i);
807 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
808 fprintf (dump_file, "\n");
813 first_label_num = get_first_label_num ();
814 num_labels = max_label_num () - first_label_num;
816 /* Allocate the tables used to store offset information at labels. */
817 /* We used to use alloca here, but the size of what it would try to
818 allocate would occasionally cause it to exceed the stack limit and
819 cause a core dump. */
820 offsets_known_at = xmalloc (num_labels);
821 offsets_at = xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
823 /* Alter each pseudo-reg rtx to contain its hard reg number.
824 Assign stack slots to the pseudos that lack hard regs or equivalents.
825 Do not touch virtual registers. */
827 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
830 /* If we have some registers we think can be eliminated, scan all insns to
831 see if there is an insn that sets one of these registers to something
832 other than itself plus a constant. If so, the register cannot be
833 eliminated. Doing this scan here eliminates an extra pass through the
834 main reload loop in the most common case where register elimination
836 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
838 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
840 maybe_fix_stack_asms ();
842 insns_need_reload = 0;
843 something_needs_elimination = 0;
845 /* Initialize to -1, which means take the first spill register. */
848 /* Spill any hard regs that we know we can't eliminate. */
849 CLEAR_HARD_REG_SET (used_spill_regs);
850 /* There can be multiple ways to eliminate a register;
851 they should be listed adjacently.
852 Elimination for any register fails only if all possible ways fail. */
853 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
856 int can_eliminate = 0;
859 can_eliminate |= ep->can_eliminate;
862 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
864 spill_hard_reg (from, 1);
867 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
868 if (frame_pointer_needed)
869 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
871 finish_spills (global);
873 /* From now on, we may need to generate moves differently. We may also
874 allow modifications of insns which cause them to not be recognized.
875 Any such modifications will be cleaned up during reload itself. */
876 reload_in_progress = 1;
878 /* This loop scans the entire function each go-round
879 and repeats until one repetition spills no additional hard regs. */
882 int something_changed;
885 HOST_WIDE_INT starting_frame_size;
887 /* Round size of stack frame to stack_alignment_needed. This must be done
888 here because the stack size may be a part of the offset computation
889 for register elimination, and there might have been new stack slots
890 created in the last iteration of this loop. */
891 if (cfun->stack_alignment_needed)
892 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
894 starting_frame_size = get_frame_size ();
896 set_initial_elim_offsets ();
897 set_initial_label_offsets ();
899 /* For each pseudo register that has an equivalent location defined,
900 try to eliminate any eliminable registers (such as the frame pointer)
901 assuming initial offsets for the replacement register, which
904 If the resulting location is directly addressable, substitute
905 the MEM we just got directly for the old REG.
907 If it is not addressable but is a constant or the sum of a hard reg
908 and constant, it is probably not addressable because the constant is
909 out of range, in that case record the address; we will generate
910 hairy code to compute the address in a register each time it is
911 needed. Similarly if it is a hard register, but one that is not
912 valid as an address register.
914 If the location is not addressable, but does not have one of the
915 above forms, assign a stack slot. We have to do this to avoid the
916 potential of producing lots of reloads if, e.g., a location involves
917 a pseudo that didn't get a hard register and has an equivalent memory
918 location that also involves a pseudo that didn't get a hard register.
920 Perhaps at some point we will improve reload_when_needed handling
921 so this problem goes away. But that's very hairy. */
923 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
924 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
926 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
928 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
930 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
931 else if (CONSTANT_P (XEXP (x, 0))
932 || (REG_P (XEXP (x, 0))
933 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
934 || (GET_CODE (XEXP (x, 0)) == PLUS
935 && REG_P (XEXP (XEXP (x, 0), 0))
936 && (REGNO (XEXP (XEXP (x, 0), 0))
937 < FIRST_PSEUDO_REGISTER)
938 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
939 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
942 /* Make a new stack slot. Then indicate that something
943 changed so we go back and recompute offsets for
944 eliminable registers because the allocation of memory
945 below might change some offset. reg_equiv_{mem,address}
946 will be set up for this pseudo on the next pass around
948 reg_equiv_memory_loc[i] = 0;
949 reg_equiv_init[i] = 0;
954 if (caller_save_needed)
957 /* If we allocated another stack slot, redo elimination bookkeeping. */
958 if (starting_frame_size != get_frame_size ())
961 if (caller_save_needed)
963 save_call_clobbered_regs ();
964 /* That might have allocated new insn_chain structures. */
965 reload_firstobj = obstack_alloc (&reload_obstack, 0);
968 calculate_needs_all_insns (global);
970 CLEAR_REG_SET (&spilled_pseudos);
973 something_changed = 0;
975 /* If we allocated any new memory locations, make another pass
976 since it might have changed elimination offsets. */
977 if (starting_frame_size != get_frame_size ())
978 something_changed = 1;
980 /* Even if the frame size remained the same, we might still have
981 changed elimination offsets, e.g. if find_reloads called
982 force_const_mem requiring the back end to allocate a constant
983 pool base register that needs to be saved on the stack. */
984 else if (!verify_initial_elim_offsets ())
985 something_changed = 1;
988 HARD_REG_SET to_spill;
989 CLEAR_HARD_REG_SET (to_spill);
990 update_eliminables (&to_spill);
991 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
992 if (TEST_HARD_REG_BIT (to_spill, i))
994 spill_hard_reg (i, 1);
997 /* Regardless of the state of spills, if we previously had
998 a register that we thought we could eliminate, but now can
999 not eliminate, we must run another pass.
1001 Consider pseudos which have an entry in reg_equiv_* which
1002 reference an eliminable register. We must make another pass
1003 to update reg_equiv_* so that we do not substitute in the
1004 old value from when we thought the elimination could be
1006 something_changed = 1;
1010 select_reload_regs ();
1014 if (insns_need_reload != 0 || did_spill)
1015 something_changed |= finish_spills (global);
1017 if (! something_changed)
1020 if (caller_save_needed)
1021 delete_caller_save_insns ();
1023 obstack_free (&reload_obstack, reload_firstobj);
1026 /* If global-alloc was run, notify it of any register eliminations we have
1029 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1030 if (ep->can_eliminate)
1031 mark_elimination (ep->from, ep->to);
1033 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1034 If that insn didn't set the register (i.e., it copied the register to
1035 memory), just delete that insn instead of the equivalencing insn plus
1036 anything now dead. If we call delete_dead_insn on that insn, we may
1037 delete the insn that actually sets the register if the register dies
1038 there and that is incorrect. */
1040 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1042 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1045 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1047 rtx equiv_insn = XEXP (list, 0);
1049 /* If we already deleted the insn or if it may trap, we can't
1050 delete it. The latter case shouldn't happen, but can
1051 if an insn has a variable address, gets a REG_EH_REGION
1052 note added to it, and then gets converted into a load
1053 from a constant address. */
1054 if (NOTE_P (equiv_insn)
1055 || can_throw_internal (equiv_insn))
1057 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1058 delete_dead_insn (equiv_insn);
1060 SET_INSN_DELETED (equiv_insn);
1065 /* Use the reload registers where necessary
1066 by generating move instructions to move the must-be-register
1067 values into or out of the reload registers. */
1069 if (insns_need_reload != 0 || something_needs_elimination
1070 || something_needs_operands_changed)
1072 HOST_WIDE_INT old_frame_size = get_frame_size ();
1074 reload_as_needed (global);
1076 gcc_assert (old_frame_size == get_frame_size ());
1078 gcc_assert (verify_initial_elim_offsets ());
1081 /* If we were able to eliminate the frame pointer, show that it is no
1082 longer live at the start of any basic block. If it ls live by
1083 virtue of being in a pseudo, that pseudo will be marked live
1084 and hence the frame pointer will be known to be live via that
1087 if (! frame_pointer_needed)
1089 CLEAR_REGNO_REG_SET (bb->il.rtl->global_live_at_start,
1090 HARD_FRAME_POINTER_REGNUM);
1092 /* Come here (with failure set nonzero) if we can't get enough spill
1096 CLEAR_REG_SET (&spilled_pseudos);
1097 reload_in_progress = 0;
1099 /* Now eliminate all pseudo regs by modifying them into
1100 their equivalent memory references.
1101 The REG-rtx's for the pseudos are modified in place,
1102 so all insns that used to refer to them now refer to memory.
1104 For a reg that has a reg_equiv_address, all those insns
1105 were changed by reloading so that no insns refer to it any longer;
1106 but the DECL_RTL of a variable decl may refer to it,
1107 and if so this causes the debugging info to mention the variable. */
1109 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1113 if (reg_equiv_mem[i])
1114 addr = XEXP (reg_equiv_mem[i], 0);
1116 if (reg_equiv_address[i])
1117 addr = reg_equiv_address[i];
1121 if (reg_renumber[i] < 0)
1123 rtx reg = regno_reg_rtx[i];
1125 REG_USERVAR_P (reg) = 0;
1126 PUT_CODE (reg, MEM);
1127 XEXP (reg, 0) = addr;
1128 if (reg_equiv_memory_loc[i])
1129 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1132 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1133 MEM_ATTRS (reg) = 0;
1135 MEM_NOTRAP_P (reg) = 1;
1137 else if (reg_equiv_mem[i])
1138 XEXP (reg_equiv_mem[i], 0) = addr;
1142 /* We must set reload_completed now since the cleanup_subreg_operands call
1143 below will re-recognize each insn and reload may have generated insns
1144 which are only valid during and after reload. */
1145 reload_completed = 1;
1147 /* Make a pass over all the insns and delete all USEs which we inserted
1148 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1149 notes. Delete all CLOBBER insns, except those that refer to the return
1150 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1151 from misarranging variable-array code, and simplify (subreg (reg))
1152 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1153 are no longer useful or accurate. Strip and regenerate REG_INC notes
1154 that may have been moved around. */
1156 for (insn = first; insn; insn = NEXT_INSN (insn))
1162 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1163 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1165 if ((GET_CODE (PATTERN (insn)) == USE
1166 /* We mark with QImode USEs introduced by reload itself. */
1167 && (GET_MODE (insn) == QImode
1168 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1169 || (GET_CODE (PATTERN (insn)) == CLOBBER
1170 && (!MEM_P (XEXP (PATTERN (insn), 0))
1171 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1172 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1173 && XEXP (XEXP (PATTERN (insn), 0), 0)
1174 != stack_pointer_rtx))
1175 && (!REG_P (XEXP (PATTERN (insn), 0))
1176 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1182 /* Some CLOBBERs may survive until here and still reference unassigned
1183 pseudos with const equivalent, which may in turn cause ICE in later
1184 passes if the reference remains in place. */
1185 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1186 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1187 VOIDmode, PATTERN (insn));
1189 /* Discard obvious no-ops, even without -O. This optimization
1190 is fast and doesn't interfere with debugging. */
1191 if (NONJUMP_INSN_P (insn)
1192 && GET_CODE (PATTERN (insn)) == SET
1193 && REG_P (SET_SRC (PATTERN (insn)))
1194 && REG_P (SET_DEST (PATTERN (insn)))
1195 && (REGNO (SET_SRC (PATTERN (insn)))
1196 == REGNO (SET_DEST (PATTERN (insn)))))
1202 pnote = ®_NOTES (insn);
1205 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1206 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1207 || REG_NOTE_KIND (*pnote) == REG_INC
1208 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1209 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1210 *pnote = XEXP (*pnote, 1);
1212 pnote = &XEXP (*pnote, 1);
1216 add_auto_inc_notes (insn, PATTERN (insn));
1219 /* And simplify (subreg (reg)) if it appears as an operand. */
1220 cleanup_subreg_operands (insn);
1223 /* If we are doing stack checking, give a warning if this function's
1224 frame size is larger than we expect. */
1225 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1227 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1228 static int verbose_warned = 0;
1230 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1231 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1232 size += UNITS_PER_WORD;
1234 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1236 warning (0, "frame size too large for reliable stack checking");
1237 if (! verbose_warned)
1239 warning (0, "try reducing the number of local variables");
1245 /* Indicate that we no longer have known memory locations or constants. */
1246 if (reg_equiv_constant)
1247 free (reg_equiv_constant);
1248 if (reg_equiv_invariant)
1249 free (reg_equiv_invariant);
1250 reg_equiv_constant = 0;
1251 reg_equiv_invariant = 0;
1252 VARRAY_GROW (reg_equiv_memory_loc_varray, 0);
1253 reg_equiv_memory_loc = 0;
1255 if (offsets_known_at)
1256 free (offsets_known_at);
1260 free (reg_equiv_mem);
1262 free (reg_equiv_address);
1263 free (reg_max_ref_width);
1264 free (reg_old_renumber);
1265 free (pseudo_previous_regs);
1266 free (pseudo_forbidden_regs);
1268 CLEAR_HARD_REG_SET (used_spill_regs);
1269 for (i = 0; i < n_spills; i++)
1270 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1272 /* Free all the insn_chain structures at once. */
1273 obstack_free (&reload_obstack, reload_startobj);
1274 unused_insn_chains = 0;
1275 fixup_abnormal_edges ();
1277 /* Replacing pseudos with their memory equivalents might have
1278 created shared rtx. Subsequent passes would get confused
1279 by this, so unshare everything here. */
1280 unshare_all_rtl_again (first);
1282 #ifdef STACK_BOUNDARY
1283 /* init_emit has set the alignment of the hard frame pointer
1284 to STACK_BOUNDARY. It is very likely no longer valid if
1285 the hard frame pointer was used for register allocation. */
1286 if (!frame_pointer_needed)
1287 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1293 /* Yet another special case. Unfortunately, reg-stack forces people to
1294 write incorrect clobbers in asm statements. These clobbers must not
1295 cause the register to appear in bad_spill_regs, otherwise we'll call
1296 fatal_insn later. We clear the corresponding regnos in the live
1297 register sets to avoid this.
1298 The whole thing is rather sick, I'm afraid. */
1301 maybe_fix_stack_asms (void)
1304 const char *constraints[MAX_RECOG_OPERANDS];
1305 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1306 struct insn_chain *chain;
1308 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1311 HARD_REG_SET clobbered, allowed;
1314 if (! INSN_P (chain->insn)
1315 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1317 pat = PATTERN (chain->insn);
1318 if (GET_CODE (pat) != PARALLEL)
1321 CLEAR_HARD_REG_SET (clobbered);
1322 CLEAR_HARD_REG_SET (allowed);
1324 /* First, make a mask of all stack regs that are clobbered. */
1325 for (i = 0; i < XVECLEN (pat, 0); i++)
1327 rtx t = XVECEXP (pat, 0, i);
1328 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1329 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1332 /* Get the operand values and constraints out of the insn. */
1333 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1334 constraints, operand_mode);
1336 /* For every operand, see what registers are allowed. */
1337 for (i = 0; i < noperands; i++)
1339 const char *p = constraints[i];
1340 /* For every alternative, we compute the class of registers allowed
1341 for reloading in CLS, and merge its contents into the reg set
1343 int cls = (int) NO_REGS;
1349 if (c == '\0' || c == ',' || c == '#')
1351 /* End of one alternative - mark the regs in the current
1352 class, and reset the class. */
1353 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1359 } while (c != '\0' && c != ',');
1367 case '=': case '+': case '*': case '%': case '?': case '!':
1368 case '0': case '1': case '2': case '3': case '4': case 'm':
1369 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1370 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1371 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1376 cls = (int) reg_class_subunion[cls]
1377 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1382 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1386 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1387 cls = (int) reg_class_subunion[cls]
1388 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1390 cls = (int) reg_class_subunion[cls]
1391 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1393 p += CONSTRAINT_LEN (c, p);
1396 /* Those of the registers which are clobbered, but allowed by the
1397 constraints, must be usable as reload registers. So clear them
1398 out of the life information. */
1399 AND_HARD_REG_SET (allowed, clobbered);
1400 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1401 if (TEST_HARD_REG_BIT (allowed, i))
1403 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1404 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1411 /* Copy the global variables n_reloads and rld into the corresponding elts
1414 copy_reloads (struct insn_chain *chain)
1416 chain->n_reloads = n_reloads;
1417 chain->rld = obstack_alloc (&reload_obstack,
1418 n_reloads * sizeof (struct reload));
1419 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1420 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1423 /* Walk the chain of insns, and determine for each whether it needs reloads
1424 and/or eliminations. Build the corresponding insns_need_reload list, and
1425 set something_needs_elimination as appropriate. */
1427 calculate_needs_all_insns (int global)
1429 struct insn_chain **pprev_reload = &insns_need_reload;
1430 struct insn_chain *chain, *next = 0;
1432 something_needs_elimination = 0;
1434 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1435 for (chain = reload_insn_chain; chain != 0; chain = next)
1437 rtx insn = chain->insn;
1441 /* Clear out the shortcuts. */
1442 chain->n_reloads = 0;
1443 chain->need_elim = 0;
1444 chain->need_reload = 0;
1445 chain->need_operand_change = 0;
1447 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1448 include REG_LABEL), we need to see what effects this has on the
1449 known offsets at labels. */
1451 if (LABEL_P (insn) || JUMP_P (insn)
1452 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1453 set_label_offsets (insn, insn, 0);
1457 rtx old_body = PATTERN (insn);
1458 int old_code = INSN_CODE (insn);
1459 rtx old_notes = REG_NOTES (insn);
1460 int did_elimination = 0;
1461 int operands_changed = 0;
1462 rtx set = single_set (insn);
1464 /* Skip insns that only set an equivalence. */
1465 if (set && REG_P (SET_DEST (set))
1466 && reg_renumber[REGNO (SET_DEST (set))] < 0
1467 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1468 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1469 && reg_equiv_init[REGNO (SET_DEST (set))])
1472 /* If needed, eliminate any eliminable registers. */
1473 if (num_eliminable || num_eliminable_invariants)
1474 did_elimination = eliminate_regs_in_insn (insn, 0);
1476 /* Analyze the instruction. */
1477 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1478 global, spill_reg_order);
1480 /* If a no-op set needs more than one reload, this is likely
1481 to be something that needs input address reloads. We
1482 can't get rid of this cleanly later, and it is of no use
1483 anyway, so discard it now.
1484 We only do this when expensive_optimizations is enabled,
1485 since this complements reload inheritance / output
1486 reload deletion, and it can make debugging harder. */
1487 if (flag_expensive_optimizations && n_reloads > 1)
1489 rtx set = single_set (insn);
1491 && SET_SRC (set) == SET_DEST (set)
1492 && REG_P (SET_SRC (set))
1493 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1496 /* Delete it from the reload chain. */
1498 chain->prev->next = next;
1500 reload_insn_chain = next;
1502 next->prev = chain->prev;
1503 chain->next = unused_insn_chains;
1504 unused_insn_chains = chain;
1509 update_eliminable_offsets ();
1511 /* Remember for later shortcuts which insns had any reloads or
1512 register eliminations. */
1513 chain->need_elim = did_elimination;
1514 chain->need_reload = n_reloads > 0;
1515 chain->need_operand_change = operands_changed;
1517 /* Discard any register replacements done. */
1518 if (did_elimination)
1520 obstack_free (&reload_obstack, reload_insn_firstobj);
1521 PATTERN (insn) = old_body;
1522 INSN_CODE (insn) = old_code;
1523 REG_NOTES (insn) = old_notes;
1524 something_needs_elimination = 1;
1527 something_needs_operands_changed |= operands_changed;
1531 copy_reloads (chain);
1532 *pprev_reload = chain;
1533 pprev_reload = &chain->next_need_reload;
1540 /* Comparison function for qsort to decide which of two reloads
1541 should be handled first. *P1 and *P2 are the reload numbers. */
1544 reload_reg_class_lower (const void *r1p, const void *r2p)
1546 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1549 /* Consider required reloads before optional ones. */
1550 t = rld[r1].optional - rld[r2].optional;
1554 /* Count all solitary classes before non-solitary ones. */
1555 t = ((reg_class_size[(int) rld[r2].class] == 1)
1556 - (reg_class_size[(int) rld[r1].class] == 1));
1560 /* Aside from solitaires, consider all multi-reg groups first. */
1561 t = rld[r2].nregs - rld[r1].nregs;
1565 /* Consider reloads in order of increasing reg-class number. */
1566 t = (int) rld[r1].class - (int) rld[r2].class;
1570 /* If reloads are equally urgent, sort by reload number,
1571 so that the results of qsort leave nothing to chance. */
1575 /* The cost of spilling each hard reg. */
1576 static int spill_cost[FIRST_PSEUDO_REGISTER];
1578 /* When spilling multiple hard registers, we use SPILL_COST for the first
1579 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1580 only the first hard reg for a multi-reg pseudo. */
1581 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1583 /* Update the spill cost arrays, considering that pseudo REG is live. */
1586 count_pseudo (int reg)
1588 int freq = REG_FREQ (reg);
1589 int r = reg_renumber[reg];
1592 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1593 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1596 SET_REGNO_REG_SET (&pseudos_counted, reg);
1598 gcc_assert (r >= 0);
1600 spill_add_cost[r] += freq;
1602 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1604 spill_cost[r + nregs] += freq;
1607 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1608 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1611 order_regs_for_reload (struct insn_chain *chain)
1614 HARD_REG_SET used_by_pseudos;
1615 HARD_REG_SET used_by_pseudos2;
1616 reg_set_iterator rsi;
1618 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1620 memset (spill_cost, 0, sizeof spill_cost);
1621 memset (spill_add_cost, 0, sizeof spill_add_cost);
1623 /* Count number of uses of each hard reg by pseudo regs allocated to it
1624 and then order them by decreasing use. First exclude hard registers
1625 that are live in or across this insn. */
1627 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1628 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1629 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1630 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1632 /* Now find out which pseudos are allocated to it, and update
1634 CLEAR_REG_SET (&pseudos_counted);
1636 EXECUTE_IF_SET_IN_REG_SET
1637 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1641 EXECUTE_IF_SET_IN_REG_SET
1642 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1646 CLEAR_REG_SET (&pseudos_counted);
1649 /* Vector of reload-numbers showing the order in which the reloads should
1651 static short reload_order[MAX_RELOADS];
1653 /* This is used to keep track of the spill regs used in one insn. */
1654 static HARD_REG_SET used_spill_regs_local;
1656 /* We decided to spill hard register SPILLED, which has a size of
1657 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1658 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1659 update SPILL_COST/SPILL_ADD_COST. */
1662 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1664 int r = reg_renumber[reg];
1665 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1667 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1668 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1671 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1673 spill_add_cost[r] -= REG_FREQ (reg);
1675 spill_cost[r + nregs] -= REG_FREQ (reg);
1678 /* Find reload register to use for reload number ORDER. */
1681 find_reg (struct insn_chain *chain, int order)
1683 int rnum = reload_order[order];
1684 struct reload *rl = rld + rnum;
1685 int best_cost = INT_MAX;
1689 HARD_REG_SET not_usable;
1690 HARD_REG_SET used_by_other_reload;
1691 reg_set_iterator rsi;
1693 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1694 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1695 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1697 CLEAR_HARD_REG_SET (used_by_other_reload);
1698 for (k = 0; k < order; k++)
1700 int other = reload_order[k];
1702 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1703 for (j = 0; j < rld[other].nregs; j++)
1704 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1707 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1709 unsigned int regno = i;
1711 if (! TEST_HARD_REG_BIT (not_usable, regno)
1712 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1713 && HARD_REGNO_MODE_OK (regno, rl->mode))
1715 int this_cost = spill_cost[regno];
1717 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1719 for (j = 1; j < this_nregs; j++)
1721 this_cost += spill_add_cost[regno + j];
1722 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1723 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1728 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1730 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1732 if (this_cost < best_cost
1733 /* Among registers with equal cost, prefer caller-saved ones, or
1734 use REG_ALLOC_ORDER if it is defined. */
1735 || (this_cost == best_cost
1736 #ifdef REG_ALLOC_ORDER
1737 && (inv_reg_alloc_order[regno]
1738 < inv_reg_alloc_order[best_reg])
1740 && call_used_regs[regno]
1741 && ! call_used_regs[best_reg]
1746 best_cost = this_cost;
1754 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1756 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1757 rl->regno = best_reg;
1759 EXECUTE_IF_SET_IN_REG_SET
1760 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1762 count_spilled_pseudo (best_reg, rl->nregs, j);
1765 EXECUTE_IF_SET_IN_REG_SET
1766 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1768 count_spilled_pseudo (best_reg, rl->nregs, j);
1771 for (i = 0; i < rl->nregs; i++)
1773 gcc_assert (spill_cost[best_reg + i] == 0);
1774 gcc_assert (spill_add_cost[best_reg + i] == 0);
1775 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1780 /* Find more reload regs to satisfy the remaining need of an insn, which
1782 Do it by ascending class number, since otherwise a reg
1783 might be spilled for a big class and might fail to count
1784 for a smaller class even though it belongs to that class. */
1787 find_reload_regs (struct insn_chain *chain)
1791 /* In order to be certain of getting the registers we need,
1792 we must sort the reloads into order of increasing register class.
1793 Then our grabbing of reload registers will parallel the process
1794 that provided the reload registers. */
1795 for (i = 0; i < chain->n_reloads; i++)
1797 /* Show whether this reload already has a hard reg. */
1798 if (chain->rld[i].reg_rtx)
1800 int regno = REGNO (chain->rld[i].reg_rtx);
1801 chain->rld[i].regno = regno;
1803 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1806 chain->rld[i].regno = -1;
1807 reload_order[i] = i;
1810 n_reloads = chain->n_reloads;
1811 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1813 CLEAR_HARD_REG_SET (used_spill_regs_local);
1816 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1818 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1820 /* Compute the order of preference for hard registers to spill. */
1822 order_regs_for_reload (chain);
1824 for (i = 0; i < n_reloads; i++)
1826 int r = reload_order[i];
1828 /* Ignore reloads that got marked inoperative. */
1829 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1830 && ! rld[r].optional
1831 && rld[r].regno == -1)
1832 if (! find_reg (chain, i))
1834 spill_failure (chain->insn, rld[r].class);
1840 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1841 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1843 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1847 select_reload_regs (void)
1849 struct insn_chain *chain;
1851 /* Try to satisfy the needs for each insn. */
1852 for (chain = insns_need_reload; chain != 0;
1853 chain = chain->next_need_reload)
1854 find_reload_regs (chain);
1857 /* Delete all insns that were inserted by emit_caller_save_insns during
1860 delete_caller_save_insns (void)
1862 struct insn_chain *c = reload_insn_chain;
1866 while (c != 0 && c->is_caller_save_insn)
1868 struct insn_chain *next = c->next;
1871 if (c == reload_insn_chain)
1872 reload_insn_chain = next;
1876 next->prev = c->prev;
1878 c->prev->next = next;
1879 c->next = unused_insn_chains;
1880 unused_insn_chains = c;
1888 /* Handle the failure to find a register to spill.
1889 INSN should be one of the insns which needed this particular spill reg. */
1892 spill_failure (rtx insn, enum reg_class class)
1894 if (asm_noperands (PATTERN (insn)) >= 0)
1895 error_for_asm (insn, "can't find a register in class %qs while "
1896 "reloading %<asm%>",
1897 reg_class_names[class]);
1900 error ("unable to find a register to spill in class %qs",
1901 reg_class_names[class]);
1902 fatal_insn ("this is the insn:", insn);
1906 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1907 data that is dead in INSN. */
1910 delete_dead_insn (rtx insn)
1912 rtx prev = prev_real_insn (insn);
1915 /* If the previous insn sets a register that dies in our insn, delete it
1917 if (prev && GET_CODE (PATTERN (prev)) == SET
1918 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
1919 && reg_mentioned_p (prev_dest, PATTERN (insn))
1920 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1921 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1922 delete_dead_insn (prev);
1924 SET_INSN_DELETED (insn);
1927 /* Modify the home of pseudo-reg I.
1928 The new home is present in reg_renumber[I].
1930 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1931 or it may be -1, meaning there is none or it is not relevant.
1932 This is used so that all pseudos spilled from a given hard reg
1933 can share one stack slot. */
1936 alter_reg (int i, int from_reg)
1938 /* When outputting an inline function, this can happen
1939 for a reg that isn't actually used. */
1940 if (regno_reg_rtx[i] == 0)
1943 /* If the reg got changed to a MEM at rtl-generation time,
1945 if (!REG_P (regno_reg_rtx[i]))
1948 /* Modify the reg-rtx to contain the new hard reg
1949 number or else to contain its pseudo reg number. */
1950 REGNO (regno_reg_rtx[i])
1951 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1953 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1954 allocate a stack slot for it. */
1956 if (reg_renumber[i] < 0
1957 && REG_N_REFS (i) > 0
1958 && reg_equiv_constant[i] == 0
1959 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
1960 && reg_equiv_memory_loc[i] == 0)
1963 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1964 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1967 /* Each pseudo reg has an inherent size which comes from its own mode,
1968 and a total size which provides room for paradoxical subregs
1969 which refer to the pseudo reg in wider modes.
1971 We can use a slot already allocated if it provides both
1972 enough inherent space and enough total space.
1973 Otherwise, we allocate a new slot, making sure that it has no less
1974 inherent space, and no less total space, then the previous slot. */
1977 /* No known place to spill from => no slot to reuse. */
1978 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1979 inherent_size == total_size ? 0 : -1);
1980 if (BYTES_BIG_ENDIAN)
1981 /* Cancel the big-endian correction done in assign_stack_local.
1982 Get the address of the beginning of the slot.
1983 This is so we can do a big-endian correction unconditionally
1985 adjust = inherent_size - total_size;
1987 /* Nothing can alias this slot except this pseudo. */
1988 set_mem_alias_set (x, new_alias_set ());
1991 /* Reuse a stack slot if possible. */
1992 else if (spill_stack_slot[from_reg] != 0
1993 && spill_stack_slot_width[from_reg] >= total_size
1994 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1996 x = spill_stack_slot[from_reg];
1998 /* Allocate a bigger slot. */
2001 /* Compute maximum size needed, both for inherent size
2002 and for total size. */
2003 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2006 if (spill_stack_slot[from_reg])
2008 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2010 mode = GET_MODE (spill_stack_slot[from_reg]);
2011 if (spill_stack_slot_width[from_reg] > total_size)
2012 total_size = spill_stack_slot_width[from_reg];
2015 /* Make a slot with that size. */
2016 x = assign_stack_local (mode, total_size,
2017 inherent_size == total_size ? 0 : -1);
2020 /* All pseudos mapped to this slot can alias each other. */
2021 if (spill_stack_slot[from_reg])
2022 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2024 set_mem_alias_set (x, new_alias_set ());
2026 if (BYTES_BIG_ENDIAN)
2028 /* Cancel the big-endian correction done in assign_stack_local.
2029 Get the address of the beginning of the slot.
2030 This is so we can do a big-endian correction unconditionally
2032 adjust = GET_MODE_SIZE (mode) - total_size;
2035 = adjust_address_nv (x, mode_for_size (total_size
2041 spill_stack_slot[from_reg] = stack_slot;
2042 spill_stack_slot_width[from_reg] = total_size;
2045 /* On a big endian machine, the "address" of the slot
2046 is the address of the low part that fits its inherent mode. */
2047 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2048 adjust += (total_size - inherent_size);
2050 /* If we have any adjustment to make, or if the stack slot is the
2051 wrong mode, make a new stack slot. */
2052 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2054 /* If we have a decl for the original register, set it for the
2055 memory. If this is a shared MEM, make a copy. */
2056 if (REG_EXPR (regno_reg_rtx[i])
2057 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2059 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2061 /* We can do this only for the DECLs home pseudo, not for
2062 any copies of it, since otherwise when the stack slot
2063 is reused, nonoverlapping_memrefs_p might think they
2065 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2067 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2070 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2074 /* Save the stack slot for later. */
2075 reg_equiv_memory_loc[i] = x;
2079 /* Mark the slots in regs_ever_live for the hard regs
2080 used by pseudo-reg number REGNO. */
2083 mark_home_live (int regno)
2087 i = reg_renumber[regno];
2090 lim = i + hard_regno_nregs[i][PSEUDO_REGNO_MODE (regno)];
2092 regs_ever_live[i++] = 1;
2095 /* This function handles the tracking of elimination offsets around branches.
2097 X is a piece of RTL being scanned.
2099 INSN is the insn that it came from, if any.
2101 INITIAL_P is nonzero if we are to set the offset to be the initial
2102 offset and zero if we are setting the offset of the label to be the
2106 set_label_offsets (rtx x, rtx insn, int initial_p)
2108 enum rtx_code code = GET_CODE (x);
2111 struct elim_table *p;
2116 if (LABEL_REF_NONLOCAL_P (x))
2121 /* ... fall through ... */
2124 /* If we know nothing about this label, set the desired offsets. Note
2125 that this sets the offset at a label to be the offset before a label
2126 if we don't know anything about the label. This is not correct for
2127 the label after a BARRIER, but is the best guess we can make. If
2128 we guessed wrong, we will suppress an elimination that might have
2129 been possible had we been able to guess correctly. */
2131 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2133 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2134 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2135 = (initial_p ? reg_eliminate[i].initial_offset
2136 : reg_eliminate[i].offset);
2137 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2140 /* Otherwise, if this is the definition of a label and it is
2141 preceded by a BARRIER, set our offsets to the known offset of
2145 && (tem = prev_nonnote_insn (insn)) != 0
2147 set_offsets_for_label (insn);
2149 /* If neither of the above cases is true, compare each offset
2150 with those previously recorded and suppress any eliminations
2151 where the offsets disagree. */
2153 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2154 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2155 != (initial_p ? reg_eliminate[i].initial_offset
2156 : reg_eliminate[i].offset))
2157 reg_eliminate[i].can_eliminate = 0;
2162 set_label_offsets (PATTERN (insn), insn, initial_p);
2164 /* ... fall through ... */
2168 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2169 and hence must have all eliminations at their initial offsets. */
2170 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2171 if (REG_NOTE_KIND (tem) == REG_LABEL)
2172 set_label_offsets (XEXP (tem, 0), insn, 1);
2178 /* Each of the labels in the parallel or address vector must be
2179 at their initial offsets. We want the first field for PARALLEL
2180 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2182 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2183 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2188 /* We only care about setting PC. If the source is not RETURN,
2189 IF_THEN_ELSE, or a label, disable any eliminations not at
2190 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2191 isn't one of those possibilities. For branches to a label,
2192 call ourselves recursively.
2194 Note that this can disable elimination unnecessarily when we have
2195 a non-local goto since it will look like a non-constant jump to
2196 someplace in the current function. This isn't a significant
2197 problem since such jumps will normally be when all elimination
2198 pairs are back to their initial offsets. */
2200 if (SET_DEST (x) != pc_rtx)
2203 switch (GET_CODE (SET_SRC (x)))
2210 set_label_offsets (SET_SRC (x), insn, initial_p);
2214 tem = XEXP (SET_SRC (x), 1);
2215 if (GET_CODE (tem) == LABEL_REF)
2216 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2217 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2220 tem = XEXP (SET_SRC (x), 2);
2221 if (GET_CODE (tem) == LABEL_REF)
2222 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2223 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2231 /* If we reach here, all eliminations must be at their initial
2232 offset because we are doing a jump to a variable address. */
2233 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2234 if (p->offset != p->initial_offset)
2235 p->can_eliminate = 0;
2243 /* Scan X and replace any eliminable registers (such as fp) with a
2244 replacement (such as sp), plus an offset.
2246 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2247 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2248 MEM, we are allowed to replace a sum of a register and the constant zero
2249 with the register, which we cannot do outside a MEM. In addition, we need
2250 to record the fact that a register is referenced outside a MEM.
2252 If INSN is an insn, it is the insn containing X. If we replace a REG
2253 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2254 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2255 the REG is being modified.
2257 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2258 That's used when we eliminate in expressions stored in notes.
2259 This means, do not set ref_outside_mem even if the reference
2262 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2263 replacements done assuming all offsets are at their initial values. If
2264 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2265 encounter, return the actual location so that find_reloads will do
2266 the proper thing. */
2269 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2270 bool may_use_invariant)
2272 enum rtx_code code = GET_CODE (x);
2273 struct elim_table *ep;
2280 if (! current_function_decl)
2302 /* First handle the case where we encounter a bare register that
2303 is eliminable. Replace it with a PLUS. */
2304 if (regno < FIRST_PSEUDO_REGISTER)
2306 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2308 if (ep->from_rtx == x && ep->can_eliminate)
2309 return plus_constant (ep->to_rtx, ep->previous_offset);
2312 else if (reg_renumber && reg_renumber[regno] < 0
2313 && reg_equiv_invariant && reg_equiv_invariant[regno])
2315 if (may_use_invariant)
2316 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2317 mem_mode, insn, true);
2318 /* There exists at least one use of REGNO that cannot be
2319 eliminated. Prevent the defining insn from being deleted. */
2320 reg_equiv_init[regno] = NULL_RTX;
2321 alter_reg (regno, -1);
2325 /* You might think handling MINUS in a manner similar to PLUS is a
2326 good idea. It is not. It has been tried multiple times and every
2327 time the change has had to have been reverted.
2329 Other parts of reload know a PLUS is special (gen_reload for example)
2330 and require special code to handle code a reloaded PLUS operand.
2332 Also consider backends where the flags register is clobbered by a
2333 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2334 lea instruction comes to mind). If we try to reload a MINUS, we
2335 may kill the flags register that was holding a useful value.
2337 So, please before trying to handle MINUS, consider reload as a
2338 whole instead of this little section as well as the backend issues. */
2340 /* If this is the sum of an eliminable register and a constant, rework
2342 if (REG_P (XEXP (x, 0))
2343 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2344 && CONSTANT_P (XEXP (x, 1)))
2346 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2348 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2350 /* The only time we want to replace a PLUS with a REG (this
2351 occurs when the constant operand of the PLUS is the negative
2352 of the offset) is when we are inside a MEM. We won't want
2353 to do so at other times because that would change the
2354 structure of the insn in a way that reload can't handle.
2355 We special-case the commonest situation in
2356 eliminate_regs_in_insn, so just replace a PLUS with a
2357 PLUS here, unless inside a MEM. */
2358 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2359 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2362 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2363 plus_constant (XEXP (x, 1),
2364 ep->previous_offset));
2367 /* If the register is not eliminable, we are done since the other
2368 operand is a constant. */
2372 /* If this is part of an address, we want to bring any constant to the
2373 outermost PLUS. We will do this by doing register replacement in
2374 our operands and seeing if a constant shows up in one of them.
2376 Note that there is no risk of modifying the structure of the insn,
2377 since we only get called for its operands, thus we are either
2378 modifying the address inside a MEM, or something like an address
2379 operand of a load-address insn. */
2382 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2383 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2385 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2387 /* If one side is a PLUS and the other side is a pseudo that
2388 didn't get a hard register but has a reg_equiv_constant,
2389 we must replace the constant here since it may no longer
2390 be in the position of any operand. */
2391 if (GET_CODE (new0) == PLUS && REG_P (new1)
2392 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2393 && reg_renumber[REGNO (new1)] < 0
2394 && reg_equiv_constant != 0
2395 && reg_equiv_constant[REGNO (new1)] != 0)
2396 new1 = reg_equiv_constant[REGNO (new1)];
2397 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2398 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2399 && reg_renumber[REGNO (new0)] < 0
2400 && reg_equiv_constant[REGNO (new0)] != 0)
2401 new0 = reg_equiv_constant[REGNO (new0)];
2403 new = form_sum (new0, new1);
2405 /* As above, if we are not inside a MEM we do not want to
2406 turn a PLUS into something else. We might try to do so here
2407 for an addition of 0 if we aren't optimizing. */
2408 if (! mem_mode && GET_CODE (new) != PLUS)
2409 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2417 /* If this is the product of an eliminable register and a
2418 constant, apply the distribute law and move the constant out
2419 so that we have (plus (mult ..) ..). This is needed in order
2420 to keep load-address insns valid. This case is pathological.
2421 We ignore the possibility of overflow here. */
2422 if (REG_P (XEXP (x, 0))
2423 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2424 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2425 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2427 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2430 /* Refs inside notes don't count for this purpose. */
2431 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2432 || GET_CODE (insn) == INSN_LIST)))
2433 ep->ref_outside_mem = 1;
2436 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2437 ep->previous_offset * INTVAL (XEXP (x, 1)));
2440 /* ... fall through ... */
2444 /* See comments before PLUS about handling MINUS. */
2446 case DIV: case UDIV:
2447 case MOD: case UMOD:
2448 case AND: case IOR: case XOR:
2449 case ROTATERT: case ROTATE:
2450 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2452 case GE: case GT: case GEU: case GTU:
2453 case LE: case LT: case LEU: case LTU:
2455 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2456 rtx new1 = XEXP (x, 1)
2457 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2459 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2460 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2465 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2468 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2469 if (new != XEXP (x, 0))
2471 /* If this is a REG_DEAD note, it is not valid anymore.
2472 Using the eliminated version could result in creating a
2473 REG_DEAD note for the stack or frame pointer. */
2474 if (GET_MODE (x) == REG_DEAD)
2476 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2479 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2483 /* ... fall through ... */
2486 /* Now do eliminations in the rest of the chain. If this was
2487 an EXPR_LIST, this might result in allocating more memory than is
2488 strictly needed, but it simplifies the code. */
2491 new = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2492 if (new != XEXP (x, 1))
2494 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2502 case STRICT_LOW_PART:
2504 case SIGN_EXTEND: case ZERO_EXTEND:
2505 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2506 case FLOAT: case FIX:
2507 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2515 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2516 if (new != XEXP (x, 0))
2517 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2521 /* Similar to above processing, but preserve SUBREG_BYTE.
2522 Convert (subreg (mem)) to (mem) if not paradoxical.
2523 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2524 pseudo didn't get a hard reg, we must replace this with the
2525 eliminated version of the memory location because push_reload
2526 may do the replacement in certain circumstances. */
2527 if (REG_P (SUBREG_REG (x))
2528 && (GET_MODE_SIZE (GET_MODE (x))
2529 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2530 && reg_equiv_memory_loc != 0
2531 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2533 new = SUBREG_REG (x);
2536 new = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2538 if (new != SUBREG_REG (x))
2540 int x_size = GET_MODE_SIZE (GET_MODE (x));
2541 int new_size = GET_MODE_SIZE (GET_MODE (new));
2544 && ((x_size < new_size
2545 #ifdef WORD_REGISTER_OPERATIONS
2546 /* On these machines, combine can create rtl of the form
2547 (set (subreg:m1 (reg:m2 R) 0) ...)
2548 where m1 < m2, and expects something interesting to
2549 happen to the entire word. Moreover, it will use the
2550 (reg:m2 R) later, expecting all bits to be preserved.
2551 So if the number of words is the same, preserve the
2552 subreg so that push_reload can see it. */
2553 && ! ((x_size - 1) / UNITS_PER_WORD
2554 == (new_size -1 ) / UNITS_PER_WORD)
2557 || x_size == new_size)
2559 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2561 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2567 /* Our only special processing is to pass the mode of the MEM to our
2568 recursive call and copy the flags. While we are here, handle this
2569 case more efficiently. */
2571 replace_equiv_address_nv (x,
2572 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2576 /* Handle insn_list USE that a call to a pure function may generate. */
2577 new = eliminate_regs_1 (XEXP (x, 0), 0, insn, false);
2578 if (new != XEXP (x, 0))
2579 return gen_rtx_USE (GET_MODE (x), new);
2591 /* Process each of our operands recursively. If any have changed, make a
2593 fmt = GET_RTX_FORMAT (code);
2594 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2598 new = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2599 if (new != XEXP (x, i) && ! copied)
2601 rtx new_x = rtx_alloc (code);
2602 memcpy (new_x, x, RTX_SIZE (code));
2608 else if (*fmt == 'E')
2611 for (j = 0; j < XVECLEN (x, i); j++)
2613 new = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2614 if (new != XVECEXP (x, i, j) && ! copied_vec)
2616 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2620 rtx new_x = rtx_alloc (code);
2621 memcpy (new_x, x, RTX_SIZE (code));
2625 XVEC (x, i) = new_v;
2628 XVECEXP (x, i, j) = new;
2637 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2639 return eliminate_regs_1 (x, mem_mode, insn, false);
2642 /* Scan rtx X for modifications of elimination target registers. Update
2643 the table of eliminables to reflect the changed state. MEM_MODE is
2644 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2647 elimination_effects (rtx x, enum machine_mode mem_mode)
2649 enum rtx_code code = GET_CODE (x);
2650 struct elim_table *ep;
2674 /* First handle the case where we encounter a bare register that
2675 is eliminable. Replace it with a PLUS. */
2676 if (regno < FIRST_PSEUDO_REGISTER)
2678 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2680 if (ep->from_rtx == x && ep->can_eliminate)
2683 ep->ref_outside_mem = 1;
2688 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2689 && reg_equiv_constant[regno]
2690 && ! function_invariant_p (reg_equiv_constant[regno]))
2691 elimination_effects (reg_equiv_constant[regno], mem_mode);
2700 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2701 if (ep->to_rtx == XEXP (x, 0))
2703 int size = GET_MODE_SIZE (mem_mode);
2705 /* If more bytes than MEM_MODE are pushed, account for them. */
2706 #ifdef PUSH_ROUNDING
2707 if (ep->to_rtx == stack_pointer_rtx)
2708 size = PUSH_ROUNDING (size);
2710 if (code == PRE_DEC || code == POST_DEC)
2712 else if (code == PRE_INC || code == POST_INC)
2714 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2715 && GET_CODE (XEXP (x, 1)) == PLUS
2716 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2717 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2718 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2721 /* These two aren't unary operators. */
2722 if (code == POST_MODIFY || code == PRE_MODIFY)
2725 /* Fall through to generic unary operation case. */
2726 case STRICT_LOW_PART:
2728 case SIGN_EXTEND: case ZERO_EXTEND:
2729 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2730 case FLOAT: case FIX:
2731 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2739 elimination_effects (XEXP (x, 0), mem_mode);
2743 if (REG_P (SUBREG_REG (x))
2744 && (GET_MODE_SIZE (GET_MODE (x))
2745 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2746 && reg_equiv_memory_loc != 0
2747 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2750 elimination_effects (SUBREG_REG (x), mem_mode);
2754 /* If using a register that is the source of an eliminate we still
2755 think can be performed, note it cannot be performed since we don't
2756 know how this register is used. */
2757 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2758 if (ep->from_rtx == XEXP (x, 0))
2759 ep->can_eliminate = 0;
2761 elimination_effects (XEXP (x, 0), mem_mode);
2765 /* If clobbering a register that is the replacement register for an
2766 elimination we still think can be performed, note that it cannot
2767 be performed. Otherwise, we need not be concerned about it. */
2768 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2769 if (ep->to_rtx == XEXP (x, 0))
2770 ep->can_eliminate = 0;
2772 elimination_effects (XEXP (x, 0), mem_mode);
2776 /* Check for setting a register that we know about. */
2777 if (REG_P (SET_DEST (x)))
2779 /* See if this is setting the replacement register for an
2782 If DEST is the hard frame pointer, we do nothing because we
2783 assume that all assignments to the frame pointer are for
2784 non-local gotos and are being done at a time when they are valid
2785 and do not disturb anything else. Some machines want to
2786 eliminate a fake argument pointer (or even a fake frame pointer)
2787 with either the real frame or the stack pointer. Assignments to
2788 the hard frame pointer must not prevent this elimination. */
2790 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2792 if (ep->to_rtx == SET_DEST (x)
2793 && SET_DEST (x) != hard_frame_pointer_rtx)
2795 /* If it is being incremented, adjust the offset. Otherwise,
2796 this elimination can't be done. */
2797 rtx src = SET_SRC (x);
2799 if (GET_CODE (src) == PLUS
2800 && XEXP (src, 0) == SET_DEST (x)
2801 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2802 ep->offset -= INTVAL (XEXP (src, 1));
2804 ep->can_eliminate = 0;
2808 elimination_effects (SET_DEST (x), 0);
2809 elimination_effects (SET_SRC (x), 0);
2813 /* Our only special processing is to pass the mode of the MEM to our
2815 elimination_effects (XEXP (x, 0), GET_MODE (x));
2822 fmt = GET_RTX_FORMAT (code);
2823 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2826 elimination_effects (XEXP (x, i), mem_mode);
2827 else if (*fmt == 'E')
2828 for (j = 0; j < XVECLEN (x, i); j++)
2829 elimination_effects (XVECEXP (x, i, j), mem_mode);
2833 /* Descend through rtx X and verify that no references to eliminable registers
2834 remain. If any do remain, mark the involved register as not
2838 check_eliminable_occurrences (rtx x)
2847 code = GET_CODE (x);
2849 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2851 struct elim_table *ep;
2853 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2854 if (ep->from_rtx == x)
2855 ep->can_eliminate = 0;
2859 fmt = GET_RTX_FORMAT (code);
2860 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2863 check_eliminable_occurrences (XEXP (x, i));
2864 else if (*fmt == 'E')
2867 for (j = 0; j < XVECLEN (x, i); j++)
2868 check_eliminable_occurrences (XVECEXP (x, i, j));
2873 /* Scan INSN and eliminate all eliminable registers in it.
2875 If REPLACE is nonzero, do the replacement destructively. Also
2876 delete the insn as dead it if it is setting an eliminable register.
2878 If REPLACE is zero, do all our allocations in reload_obstack.
2880 If no eliminations were done and this insn doesn't require any elimination
2881 processing (these are not identical conditions: it might be updating sp,
2882 but not referencing fp; this needs to be seen during reload_as_needed so
2883 that the offset between fp and sp can be taken into consideration), zero
2884 is returned. Otherwise, 1 is returned. */
2887 eliminate_regs_in_insn (rtx insn, int replace)
2889 int icode = recog_memoized (insn);
2890 rtx old_body = PATTERN (insn);
2891 int insn_is_asm = asm_noperands (old_body) >= 0;
2892 rtx old_set = single_set (insn);
2896 rtx substed_operand[MAX_RECOG_OPERANDS];
2897 rtx orig_operand[MAX_RECOG_OPERANDS];
2898 struct elim_table *ep;
2899 rtx plus_src, plus_cst_src;
2901 if (! insn_is_asm && icode < 0)
2903 gcc_assert (GET_CODE (PATTERN (insn)) == USE
2904 || GET_CODE (PATTERN (insn)) == CLOBBER
2905 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2906 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2907 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
2911 if (old_set != 0 && REG_P (SET_DEST (old_set))
2912 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2914 /* Check for setting an eliminable register. */
2915 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2916 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2918 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2919 /* If this is setting the frame pointer register to the
2920 hardware frame pointer register and this is an elimination
2921 that will be done (tested above), this insn is really
2922 adjusting the frame pointer downward to compensate for
2923 the adjustment done before a nonlocal goto. */
2924 if (ep->from == FRAME_POINTER_REGNUM
2925 && ep->to == HARD_FRAME_POINTER_REGNUM)
2927 rtx base = SET_SRC (old_set);
2928 rtx base_insn = insn;
2929 HOST_WIDE_INT offset = 0;
2931 while (base != ep->to_rtx)
2933 rtx prev_insn, prev_set;
2935 if (GET_CODE (base) == PLUS
2936 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2938 offset += INTVAL (XEXP (base, 1));
2939 base = XEXP (base, 0);
2941 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2942 && (prev_set = single_set (prev_insn)) != 0
2943 && rtx_equal_p (SET_DEST (prev_set), base))
2945 base = SET_SRC (prev_set);
2946 base_insn = prev_insn;
2952 if (base == ep->to_rtx)
2955 = plus_constant (ep->to_rtx, offset - ep->offset);
2957 new_body = old_body;
2960 new_body = copy_insn (old_body);
2961 if (REG_NOTES (insn))
2962 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2964 PATTERN (insn) = new_body;
2965 old_set = single_set (insn);
2967 /* First see if this insn remains valid when we
2968 make the change. If not, keep the INSN_CODE
2969 the same and let reload fit it up. */
2970 validate_change (insn, &SET_SRC (old_set), src, 1);
2971 validate_change (insn, &SET_DEST (old_set),
2973 if (! apply_change_group ())
2975 SET_SRC (old_set) = src;
2976 SET_DEST (old_set) = ep->to_rtx;
2985 /* In this case this insn isn't serving a useful purpose. We
2986 will delete it in reload_as_needed once we know that this
2987 elimination is, in fact, being done.
2989 If REPLACE isn't set, we can't delete this insn, but needn't
2990 process it since it won't be used unless something changes. */
2993 delete_dead_insn (insn);
3001 /* We allow one special case which happens to work on all machines we
3002 currently support: a single set with the source or a REG_EQUAL
3003 note being a PLUS of an eliminable register and a constant. */
3004 plus_src = plus_cst_src = 0;
3005 if (old_set && REG_P (SET_DEST (old_set)))
3007 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3008 plus_src = SET_SRC (old_set);
3009 /* First see if the source is of the form (plus (...) CST). */
3011 && GET_CODE (XEXP (plus_src, 1)) == CONST_INT)
3012 plus_cst_src = plus_src;
3013 else if (REG_P (SET_SRC (old_set))
3016 /* Otherwise, see if we have a REG_EQUAL note of the form
3017 (plus (...) CST). */
3019 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3021 if (REG_NOTE_KIND (links) == REG_EQUAL
3022 && GET_CODE (XEXP (links, 0)) == PLUS
3023 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT)
3025 plus_cst_src = XEXP (links, 0);
3031 /* Check that the first operand of the PLUS is a hard reg or
3032 the lowpart subreg of one. */
3035 rtx reg = XEXP (plus_cst_src, 0);
3036 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3037 reg = SUBREG_REG (reg);
3039 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3045 rtx reg = XEXP (plus_cst_src, 0);
3046 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3048 if (GET_CODE (reg) == SUBREG)
3049 reg = SUBREG_REG (reg);
3051 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3052 if (ep->from_rtx == reg && ep->can_eliminate)
3054 rtx to_rtx = ep->to_rtx;
3055 offset += ep->offset;
3057 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3058 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3063 /* We assume here that if we need a PARALLEL with
3064 CLOBBERs for this assignment, we can do with the
3065 MATCH_SCRATCHes that add_clobbers allocates.
3066 There's not much we can do if that doesn't work. */
3067 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3071 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3074 rtvec vec = rtvec_alloc (num_clobbers + 1);
3076 vec->elem[0] = PATTERN (insn);
3077 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3078 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3080 gcc_assert (INSN_CODE (insn) >= 0);
3082 /* If we have a nonzero offset, and the source is already
3083 a simple REG, the following transformation would
3084 increase the cost of the insn by replacing a simple REG
3085 with (plus (reg sp) CST). So try only when we already
3086 had a PLUS before. */
3089 new_body = old_body;
3092 new_body = copy_insn (old_body);
3093 if (REG_NOTES (insn))
3094 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3096 PATTERN (insn) = new_body;
3097 old_set = single_set (insn);
3099 XEXP (SET_SRC (old_set), 0) = to_rtx;
3100 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3106 /* This can't have an effect on elimination offsets, so skip right
3112 /* Determine the effects of this insn on elimination offsets. */
3113 elimination_effects (old_body, 0);
3115 /* Eliminate all eliminable registers occurring in operands that
3116 can be handled by reload. */
3117 extract_insn (insn);
3118 for (i = 0; i < recog_data.n_operands; i++)
3120 orig_operand[i] = recog_data.operand[i];
3121 substed_operand[i] = recog_data.operand[i];
3123 /* For an asm statement, every operand is eliminable. */
3124 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3126 bool is_set_src, in_plus;
3128 /* Check for setting a register that we know about. */
3129 if (recog_data.operand_type[i] != OP_IN
3130 && REG_P (orig_operand[i]))
3132 /* If we are assigning to a register that can be eliminated, it
3133 must be as part of a PARALLEL, since the code above handles
3134 single SETs. We must indicate that we can no longer
3135 eliminate this reg. */
3136 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3138 if (ep->from_rtx == orig_operand[i])
3139 ep->can_eliminate = 0;
3142 /* Companion to the above plus substitution, we can allow
3143 invariants as the source of a plain move. */
3145 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3149 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3150 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3154 = eliminate_regs_1 (recog_data.operand[i], 0,
3155 replace ? insn : NULL_RTX,
3156 is_set_src || in_plus);
3157 if (substed_operand[i] != orig_operand[i])
3159 /* Terminate the search in check_eliminable_occurrences at
3161 *recog_data.operand_loc[i] = 0;
3163 /* If an output operand changed from a REG to a MEM and INSN is an
3164 insn, write a CLOBBER insn. */
3165 if (recog_data.operand_type[i] != OP_IN
3166 && REG_P (orig_operand[i])
3167 && MEM_P (substed_operand[i])
3169 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3174 for (i = 0; i < recog_data.n_dups; i++)
3175 *recog_data.dup_loc[i]
3176 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3178 /* If any eliminable remain, they aren't eliminable anymore. */
3179 check_eliminable_occurrences (old_body);
3181 /* Substitute the operands; the new values are in the substed_operand
3183 for (i = 0; i < recog_data.n_operands; i++)
3184 *recog_data.operand_loc[i] = substed_operand[i];
3185 for (i = 0; i < recog_data.n_dups; i++)
3186 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3188 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3189 re-recognize the insn. We do this in case we had a simple addition
3190 but now can do this as a load-address. This saves an insn in this
3192 If re-recognition fails, the old insn code number will still be used,
3193 and some register operands may have changed into PLUS expressions.
3194 These will be handled by find_reloads by loading them into a register
3199 /* If we aren't replacing things permanently and we changed something,
3200 make another copy to ensure that all the RTL is new. Otherwise
3201 things can go wrong if find_reload swaps commutative operands
3202 and one is inside RTL that has been copied while the other is not. */
3203 new_body = old_body;
3206 new_body = copy_insn (old_body);
3207 if (REG_NOTES (insn))
3208 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3210 PATTERN (insn) = new_body;
3212 /* If we had a move insn but now we don't, rerecognize it. This will
3213 cause spurious re-recognition if the old move had a PARALLEL since
3214 the new one still will, but we can't call single_set without
3215 having put NEW_BODY into the insn and the re-recognition won't
3216 hurt in this rare case. */
3217 /* ??? Why this huge if statement - why don't we just rerecognize the
3221 && ((REG_P (SET_SRC (old_set))
3222 && (GET_CODE (new_body) != SET
3223 || !REG_P (SET_SRC (new_body))))
3224 /* If this was a load from or store to memory, compare
3225 the MEM in recog_data.operand to the one in the insn.
3226 If they are not equal, then rerecognize the insn. */
3228 && ((MEM_P (SET_SRC (old_set))
3229 && SET_SRC (old_set) != recog_data.operand[1])
3230 || (MEM_P (SET_DEST (old_set))
3231 && SET_DEST (old_set) != recog_data.operand[0])))
3232 /* If this was an add insn before, rerecognize. */
3233 || GET_CODE (SET_SRC (old_set)) == PLUS))
3235 int new_icode = recog (PATTERN (insn), insn, 0);
3237 INSN_CODE (insn) = new_icode;
3241 /* Restore the old body. If there were any changes to it, we made a copy
3242 of it while the changes were still in place, so we'll correctly return
3243 a modified insn below. */
3246 /* Restore the old body. */
3247 for (i = 0; i < recog_data.n_operands; i++)
3248 *recog_data.operand_loc[i] = orig_operand[i];
3249 for (i = 0; i < recog_data.n_dups; i++)
3250 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3253 /* Update all elimination pairs to reflect the status after the current
3254 insn. The changes we make were determined by the earlier call to
3255 elimination_effects.
3257 We also detect cases where register elimination cannot be done,
3258 namely, if a register would be both changed and referenced outside a MEM
3259 in the resulting insn since such an insn is often undefined and, even if
3260 not, we cannot know what meaning will be given to it. Note that it is
3261 valid to have a register used in an address in an insn that changes it
3262 (presumably with a pre- or post-increment or decrement).
3264 If anything changes, return nonzero. */
3266 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3268 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3269 ep->can_eliminate = 0;
3271 ep->ref_outside_mem = 0;
3273 if (ep->previous_offset != ep->offset)
3278 /* If we changed something, perform elimination in REG_NOTES. This is
3279 needed even when REPLACE is zero because a REG_DEAD note might refer
3280 to a register that we eliminate and could cause a different number
3281 of spill registers to be needed in the final reload pass than in
3283 if (val && REG_NOTES (insn) != 0)
3285 = eliminate_regs_1 (REG_NOTES (insn), 0, REG_NOTES (insn), true);
3290 /* Loop through all elimination pairs.
3291 Recalculate the number not at initial offset.
3293 Compute the maximum offset (minimum offset if the stack does not
3294 grow downward) for each elimination pair. */
3297 update_eliminable_offsets (void)
3299 struct elim_table *ep;
3301 num_not_at_initial_offset = 0;
3302 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3304 ep->previous_offset = ep->offset;
3305 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3306 num_not_at_initial_offset++;
3310 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3311 replacement we currently believe is valid, mark it as not eliminable if X
3312 modifies DEST in any way other than by adding a constant integer to it.
3314 If DEST is the frame pointer, we do nothing because we assume that
3315 all assignments to the hard frame pointer are nonlocal gotos and are being
3316 done at a time when they are valid and do not disturb anything else.
3317 Some machines want to eliminate a fake argument pointer with either the
3318 frame or stack pointer. Assignments to the hard frame pointer must not
3319 prevent this elimination.
3321 Called via note_stores from reload before starting its passes to scan
3322 the insns of the function. */
3325 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3329 /* A SUBREG of a hard register here is just changing its mode. We should
3330 not see a SUBREG of an eliminable hard register, but check just in
3332 if (GET_CODE (dest) == SUBREG)
3333 dest = SUBREG_REG (dest);
3335 if (dest == hard_frame_pointer_rtx)
3338 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3339 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3340 && (GET_CODE (x) != SET
3341 || GET_CODE (SET_SRC (x)) != PLUS
3342 || XEXP (SET_SRC (x), 0) != dest
3343 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3345 reg_eliminate[i].can_eliminate_previous
3346 = reg_eliminate[i].can_eliminate = 0;
3351 /* Verify that the initial elimination offsets did not change since the
3352 last call to set_initial_elim_offsets. This is used to catch cases
3353 where something illegal happened during reload_as_needed that could
3354 cause incorrect code to be generated if we did not check for it. */
3357 verify_initial_elim_offsets (void)
3361 if (!num_eliminable)
3364 #ifdef ELIMINABLE_REGS
3366 struct elim_table *ep;
3368 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3370 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3371 if (t != ep->initial_offset)
3376 INITIAL_FRAME_POINTER_OFFSET (t);
3377 if (t != reg_eliminate[0].initial_offset)
3384 /* Reset all offsets on eliminable registers to their initial values. */
3387 set_initial_elim_offsets (void)
3389 struct elim_table *ep = reg_eliminate;
3391 #ifdef ELIMINABLE_REGS
3392 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3394 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3395 ep->previous_offset = ep->offset = ep->initial_offset;
3398 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3399 ep->previous_offset = ep->offset = ep->initial_offset;
3402 num_not_at_initial_offset = 0;
3405 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3408 set_initial_eh_label_offset (rtx label)
3410 set_label_offsets (label, NULL_RTX, 1);
3413 /* Initialize the known label offsets.
3414 Set a known offset for each forced label to be at the initial offset
3415 of each elimination. We do this because we assume that all
3416 computed jumps occur from a location where each elimination is
3417 at its initial offset.
3418 For all other labels, show that we don't know the offsets. */
3421 set_initial_label_offsets (void)
3424 memset (offsets_known_at, 0, num_labels);
3426 for (x = forced_labels; x; x = XEXP (x, 1))
3428 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3430 for_each_eh_label (set_initial_eh_label_offset);
3433 /* Set all elimination offsets to the known values for the code label given
3437 set_offsets_for_label (rtx insn)
3440 int label_nr = CODE_LABEL_NUMBER (insn);
3441 struct elim_table *ep;
3443 num_not_at_initial_offset = 0;
3444 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3446 ep->offset = ep->previous_offset
3447 = offsets_at[label_nr - first_label_num][i];
3448 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3449 num_not_at_initial_offset++;
3453 /* See if anything that happened changes which eliminations are valid.
3454 For example, on the SPARC, whether or not the frame pointer can
3455 be eliminated can depend on what registers have been used. We need
3456 not check some conditions again (such as flag_omit_frame_pointer)
3457 since they can't have changed. */
3460 update_eliminables (HARD_REG_SET *pset)
3462 int previous_frame_pointer_needed = frame_pointer_needed;
3463 struct elim_table *ep;
3465 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3466 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3467 #ifdef ELIMINABLE_REGS
3468 || ! CAN_ELIMINATE (ep->from, ep->to)
3471 ep->can_eliminate = 0;
3473 /* Look for the case where we have discovered that we can't replace
3474 register A with register B and that means that we will now be
3475 trying to replace register A with register C. This means we can
3476 no longer replace register C with register B and we need to disable
3477 such an elimination, if it exists. This occurs often with A == ap,
3478 B == sp, and C == fp. */
3480 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3482 struct elim_table *op;
3485 if (! ep->can_eliminate && ep->can_eliminate_previous)
3487 /* Find the current elimination for ep->from, if there is a
3489 for (op = reg_eliminate;
3490 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3491 if (op->from == ep->from && op->can_eliminate)
3497 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3499 for (op = reg_eliminate;
3500 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3501 if (op->from == new_to && op->to == ep->to)
3502 op->can_eliminate = 0;
3506 /* See if any registers that we thought we could eliminate the previous
3507 time are no longer eliminable. If so, something has changed and we
3508 must spill the register. Also, recompute the number of eliminable
3509 registers and see if the frame pointer is needed; it is if there is
3510 no elimination of the frame pointer that we can perform. */
3512 frame_pointer_needed = 1;
3513 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3515 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3516 && ep->to != HARD_FRAME_POINTER_REGNUM)
3517 frame_pointer_needed = 0;
3519 if (! ep->can_eliminate && ep->can_eliminate_previous)
3521 ep->can_eliminate_previous = 0;
3522 SET_HARD_REG_BIT (*pset, ep->from);
3527 /* If we didn't need a frame pointer last time, but we do now, spill
3528 the hard frame pointer. */
3529 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3530 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3533 /* Initialize the table of registers to eliminate. */
3536 init_elim_table (void)
3538 struct elim_table *ep;
3539 #ifdef ELIMINABLE_REGS
3540 const struct elim_table_1 *ep1;
3544 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3546 /* Does this function require a frame pointer? */
3548 frame_pointer_needed = (! flag_omit_frame_pointer
3549 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3550 and restore sp for alloca. So we can't eliminate
3551 the frame pointer in that case. At some point,
3552 we should improve this by emitting the
3553 sp-adjusting insns for this case. */
3554 || (current_function_calls_alloca
3555 && EXIT_IGNORE_STACK)
3556 || current_function_accesses_prior_frames
3557 || FRAME_POINTER_REQUIRED);
3561 #ifdef ELIMINABLE_REGS
3562 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3563 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3565 ep->from = ep1->from;
3567 ep->can_eliminate = ep->can_eliminate_previous
3568 = (CAN_ELIMINATE (ep->from, ep->to)
3569 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3572 reg_eliminate[0].from = reg_eliminate_1[0].from;
3573 reg_eliminate[0].to = reg_eliminate_1[0].to;
3574 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3575 = ! frame_pointer_needed;
3578 /* Count the number of eliminable registers and build the FROM and TO
3579 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3580 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3581 We depend on this. */
3582 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3584 num_eliminable += ep->can_eliminate;
3585 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3586 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3590 /* Kick all pseudos out of hard register REGNO.
3592 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3593 because we found we can't eliminate some register. In the case, no pseudos
3594 are allowed to be in the register, even if they are only in a block that
3595 doesn't require spill registers, unlike the case when we are spilling this
3596 hard reg to produce another spill register.
3598 Return nonzero if any pseudos needed to be kicked out. */
3601 spill_hard_reg (unsigned int regno, int cant_eliminate)
3607 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3608 regs_ever_live[regno] = 1;
3611 /* Spill every pseudo reg that was allocated to this reg
3612 or to something that overlaps this reg. */
3614 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3615 if (reg_renumber[i] >= 0
3616 && (unsigned int) reg_renumber[i] <= regno
3617 && ((unsigned int) reg_renumber[i]
3618 + hard_regno_nregs[(unsigned int) reg_renumber[i]]
3619 [PSEUDO_REGNO_MODE (i)]
3621 SET_REGNO_REG_SET (&spilled_pseudos, i);
3624 /* After find_reload_regs has been run for all insn that need reloads,
3625 and/or spill_hard_regs was called, this function is used to actually
3626 spill pseudo registers and try to reallocate them. It also sets up the
3627 spill_regs array for use by choose_reload_regs. */
3630 finish_spills (int global)
3632 struct insn_chain *chain;
3633 int something_changed = 0;
3635 reg_set_iterator rsi;
3637 /* Build the spill_regs array for the function. */
3638 /* If there are some registers still to eliminate and one of the spill regs
3639 wasn't ever used before, additional stack space may have to be
3640 allocated to store this register. Thus, we may have changed the offset
3641 between the stack and frame pointers, so mark that something has changed.
3643 One might think that we need only set VAL to 1 if this is a call-used
3644 register. However, the set of registers that must be saved by the
3645 prologue is not identical to the call-used set. For example, the
3646 register used by the call insn for the return PC is a call-used register,
3647 but must be saved by the prologue. */
3650 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3651 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3653 spill_reg_order[i] = n_spills;
3654 spill_regs[n_spills++] = i;
3655 if (num_eliminable && ! regs_ever_live[i])
3656 something_changed = 1;
3657 regs_ever_live[i] = 1;
3660 spill_reg_order[i] = -1;
3662 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3664 /* Record the current hard register the pseudo is allocated to in
3665 pseudo_previous_regs so we avoid reallocating it to the same
3666 hard reg in a later pass. */
3667 gcc_assert (reg_renumber[i] >= 0);
3669 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3670 /* Mark it as no longer having a hard register home. */
3671 reg_renumber[i] = -1;
3672 /* We will need to scan everything again. */
3673 something_changed = 1;
3676 /* Retry global register allocation if possible. */
3679 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3680 /* For every insn that needs reloads, set the registers used as spill
3681 regs in pseudo_forbidden_regs for every pseudo live across the
3683 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3685 EXECUTE_IF_SET_IN_REG_SET
3686 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3688 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3689 chain->used_spill_regs);
3691 EXECUTE_IF_SET_IN_REG_SET
3692 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3694 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3695 chain->used_spill_regs);
3699 /* Retry allocating the spilled pseudos. For each reg, merge the
3700 various reg sets that indicate which hard regs can't be used,
3701 and call retry_global_alloc.
3702 We change spill_pseudos here to only contain pseudos that did not
3703 get a new hard register. */
3704 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3705 if (reg_old_renumber[i] != reg_renumber[i])
3707 HARD_REG_SET forbidden;
3708 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3709 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3710 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3711 retry_global_alloc (i, forbidden);
3712 if (reg_renumber[i] >= 0)
3713 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3717 /* Fix up the register information in the insn chain.
3718 This involves deleting those of the spilled pseudos which did not get
3719 a new hard register home from the live_{before,after} sets. */
3720 for (chain = reload_insn_chain; chain; chain = chain->next)
3722 HARD_REG_SET used_by_pseudos;
3723 HARD_REG_SET used_by_pseudos2;
3725 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3726 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3728 /* Mark any unallocated hard regs as available for spills. That
3729 makes inheritance work somewhat better. */
3730 if (chain->need_reload)
3732 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3733 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3734 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3736 /* Save the old value for the sanity test below. */
3737 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3739 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3740 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3741 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3742 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3744 /* Make sure we only enlarge the set. */
3745 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3751 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3752 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3754 int regno = reg_renumber[i];
3755 if (reg_old_renumber[i] == regno)
3758 alter_reg (i, reg_old_renumber[i]);
3759 reg_old_renumber[i] = regno;
3763 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3765 fprintf (dump_file, " Register %d now in %d.\n\n",
3766 i, reg_renumber[i]);
3770 return something_changed;
3773 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3776 scan_paradoxical_subregs (rtx x)
3780 enum rtx_code code = GET_CODE (x);
3790 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3798 if (REG_P (SUBREG_REG (x))
3799 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3800 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3801 = GET_MODE_SIZE (GET_MODE (x));
3808 fmt = GET_RTX_FORMAT (code);
3809 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3812 scan_paradoxical_subregs (XEXP (x, i));
3813 else if (fmt[i] == 'E')
3816 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3817 scan_paradoxical_subregs (XVECEXP (x, i, j));
3822 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
3823 examine all of the reload insns between PREV and NEXT exclusive, and
3824 annotate all that may trap. */
3827 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
3829 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
3830 unsigned int trap_count;
3836 if (may_trap_p (PATTERN (insn)))
3840 remove_note (insn, note);
3844 for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i))
3845 if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i)))
3849 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (note, 0), REG_NOTES (i));
3853 /* Reload pseudo-registers into hard regs around each insn as needed.
3854 Additional register load insns are output before the insn that needs it
3855 and perhaps store insns after insns that modify the reloaded pseudo reg.
3857 reg_last_reload_reg and reg_reloaded_contents keep track of
3858 which registers are already available in reload registers.
3859 We update these for the reloads that we perform,
3860 as the insns are scanned. */
3863 reload_as_needed (int live_known)
3865 struct insn_chain *chain;
3866 #if defined (AUTO_INC_DEC)
3871 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3872 memset (spill_reg_store, 0, sizeof spill_reg_store);
3873 reg_last_reload_reg = xcalloc (max_regno, sizeof (rtx));
3874 reg_has_output_reload = xmalloc (max_regno);
3875 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3876 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
3878 set_initial_elim_offsets ();
3880 for (chain = reload_insn_chain; chain; chain = chain->next)
3883 rtx insn = chain->insn;
3884 rtx old_next = NEXT_INSN (insn);
3886 /* If we pass a label, copy the offsets from the label information
3887 into the current offsets of each elimination. */
3889 set_offsets_for_label (insn);
3891 else if (INSN_P (insn))
3893 rtx oldpat = copy_rtx (PATTERN (insn));
3895 /* If this is a USE and CLOBBER of a MEM, ensure that any
3896 references to eliminable registers have been removed. */
3898 if ((GET_CODE (PATTERN (insn)) == USE
3899 || GET_CODE (PATTERN (insn)) == CLOBBER)
3900 && MEM_P (XEXP (PATTERN (insn), 0)))
3901 XEXP (XEXP (PATTERN (insn), 0), 0)
3902 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3903 GET_MODE (XEXP (PATTERN (insn), 0)),
3906 /* If we need to do register elimination processing, do so.
3907 This might delete the insn, in which case we are done. */
3908 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3910 eliminate_regs_in_insn (insn, 1);
3913 update_eliminable_offsets ();
3918 /* If need_elim is nonzero but need_reload is zero, one might think
3919 that we could simply set n_reloads to 0. However, find_reloads
3920 could have done some manipulation of the insn (such as swapping
3921 commutative operands), and these manipulations are lost during
3922 the first pass for every insn that needs register elimination.
3923 So the actions of find_reloads must be redone here. */
3925 if (! chain->need_elim && ! chain->need_reload
3926 && ! chain->need_operand_change)
3928 /* First find the pseudo regs that must be reloaded for this insn.
3929 This info is returned in the tables reload_... (see reload.h).
3930 Also modify the body of INSN by substituting RELOAD
3931 rtx's for those pseudo regs. */
3934 memset (reg_has_output_reload, 0, max_regno);
3935 CLEAR_HARD_REG_SET (reg_is_output_reload);
3937 find_reloads (insn, 1, spill_indirect_levels, live_known,
3943 rtx next = NEXT_INSN (insn);
3946 prev = PREV_INSN (insn);
3948 /* Now compute which reload regs to reload them into. Perhaps
3949 reusing reload regs from previous insns, or else output
3950 load insns to reload them. Maybe output store insns too.
3951 Record the choices of reload reg in reload_reg_rtx. */
3952 choose_reload_regs (chain);
3954 /* Merge any reloads that we didn't combine for fear of
3955 increasing the number of spill registers needed but now
3956 discover can be safely merged. */
3957 if (SMALL_REGISTER_CLASSES)
3958 merge_assigned_reloads (insn);
3960 /* Generate the insns to reload operands into or out of
3961 their reload regs. */
3962 emit_reload_insns (chain);
3964 /* Substitute the chosen reload regs from reload_reg_rtx
3965 into the insn's body (or perhaps into the bodies of other
3966 load and store insn that we just made for reloading
3967 and that we moved the structure into). */
3968 subst_reloads (insn);
3970 /* Adjust the exception region notes for loads and stores. */
3971 if (flag_non_call_exceptions && !CALL_P (insn))
3972 fixup_eh_region_note (insn, prev, next);
3974 /* If this was an ASM, make sure that all the reload insns
3975 we have generated are valid. If not, give an error
3977 if (asm_noperands (PATTERN (insn)) >= 0)
3978 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3979 if (p != insn && INSN_P (p)
3980 && GET_CODE (PATTERN (p)) != USE
3981 && (recog_memoized (p) < 0
3982 || (extract_insn (p), ! constrain_operands (1))))
3984 error_for_asm (insn,
3985 "%<asm%> operand requires "
3986 "impossible reload");
3991 if (num_eliminable && chain->need_elim)
3992 update_eliminable_offsets ();
3994 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3995 is no longer validly lying around to save a future reload.
3996 Note that this does not detect pseudos that were reloaded
3997 for this insn in order to be stored in
3998 (obeying register constraints). That is correct; such reload
3999 registers ARE still valid. */
4000 note_stores (oldpat, forget_old_reloads_1, NULL);
4002 /* There may have been CLOBBER insns placed after INSN. So scan
4003 between INSN and NEXT and use them to forget old reloads. */
4004 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4005 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4006 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4009 /* Likewise for regs altered by auto-increment in this insn.
4010 REG_INC notes have been changed by reloading:
4011 find_reloads_address_1 records substitutions for them,
4012 which have been performed by subst_reloads above. */
4013 for (i = n_reloads - 1; i >= 0; i--)
4015 rtx in_reg = rld[i].in_reg;
4018 enum rtx_code code = GET_CODE (in_reg);
4019 /* PRE_INC / PRE_DEC will have the reload register ending up
4020 with the same value as the stack slot, but that doesn't
4021 hold true for POST_INC / POST_DEC. Either we have to
4022 convert the memory access to a true POST_INC / POST_DEC,
4023 or we can't use the reload register for inheritance. */
4024 if ((code == POST_INC || code == POST_DEC)
4025 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4026 REGNO (rld[i].reg_rtx))
4027 /* Make sure it is the inc/dec pseudo, and not
4028 some other (e.g. output operand) pseudo. */
4029 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4030 == REGNO (XEXP (in_reg, 0))))
4033 rtx reload_reg = rld[i].reg_rtx;
4034 enum machine_mode mode = GET_MODE (reload_reg);
4038 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4040 /* We really want to ignore REG_INC notes here, so
4041 use PATTERN (p) as argument to reg_set_p . */
4042 if (reg_set_p (reload_reg, PATTERN (p)))
4044 n = count_occurrences (PATTERN (p), reload_reg, 0);
4049 n = validate_replace_rtx (reload_reg,
4050 gen_rtx_fmt_e (code,
4055 /* We must also verify that the constraints
4056 are met after the replacement. */
4059 n = constrain_operands (1);
4063 /* If the constraints were not met, then
4064 undo the replacement. */
4067 validate_replace_rtx (gen_rtx_fmt_e (code,
4080 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4082 /* Mark this as having an output reload so that the
4083 REG_INC processing code below won't invalidate
4084 the reload for inheritance. */
4085 SET_HARD_REG_BIT (reg_is_output_reload,
4086 REGNO (reload_reg));
4087 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4090 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4093 else if ((code == PRE_INC || code == PRE_DEC)
4094 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4095 REGNO (rld[i].reg_rtx))
4096 /* Make sure it is the inc/dec pseudo, and not
4097 some other (e.g. output operand) pseudo. */
4098 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4099 == REGNO (XEXP (in_reg, 0))))
4101 SET_HARD_REG_BIT (reg_is_output_reload,
4102 REGNO (rld[i].reg_rtx));
4103 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4107 /* If a pseudo that got a hard register is auto-incremented,
4108 we must purge records of copying it into pseudos without
4110 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4111 if (REG_NOTE_KIND (x) == REG_INC)
4113 /* See if this pseudo reg was reloaded in this insn.
4114 If so, its last-reload info is still valid
4115 because it is based on this insn's reload. */
4116 for (i = 0; i < n_reloads; i++)
4117 if (rld[i].out == XEXP (x, 0))
4121 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4125 /* A reload reg's contents are unknown after a label. */
4127 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4129 /* Don't assume a reload reg is still good after a call insn
4130 if it is a call-used reg, or if it contains a value that will
4131 be partially clobbered by the call. */
4132 else if (CALL_P (insn))
4134 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4135 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4140 free (reg_last_reload_reg);
4141 free (reg_has_output_reload);
4144 /* Discard all record of any value reloaded from X,
4145 or reloaded in X from someplace else;
4146 unless X is an output reload reg of the current insn.
4148 X may be a hard reg (the reload reg)
4149 or it may be a pseudo reg that was reloaded from. */
4152 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4153 void *data ATTRIBUTE_UNUSED)
4158 /* note_stores does give us subregs of hard regs,
4159 subreg_regno_offset requires a hard reg. */
4160 while (GET_CODE (x) == SUBREG)
4162 /* We ignore the subreg offset when calculating the regno,
4163 because we are using the entire underlying hard register
4173 if (regno >= FIRST_PSEUDO_REGISTER)
4179 nr = hard_regno_nregs[regno][GET_MODE (x)];
4180 /* Storing into a spilled-reg invalidates its contents.
4181 This can happen if a block-local pseudo is allocated to that reg
4182 and it wasn't spilled because this block's total need is 0.
4183 Then some insn might have an optional reload and use this reg. */
4184 for (i = 0; i < nr; i++)
4185 /* But don't do this if the reg actually serves as an output
4186 reload reg in the current instruction. */
4188 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4190 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4191 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4192 spill_reg_store[regno + i] = 0;
4196 /* Since value of X has changed,
4197 forget any value previously copied from it. */
4200 /* But don't forget a copy if this is the output reload
4201 that establishes the copy's validity. */
4202 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4203 reg_last_reload_reg[regno + nr] = 0;
4206 /* The following HARD_REG_SETs indicate when each hard register is
4207 used for a reload of various parts of the current insn. */
4209 /* If reg is unavailable for all reloads. */
4210 static HARD_REG_SET reload_reg_unavailable;
4211 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4212 static HARD_REG_SET reload_reg_used;
4213 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4214 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4215 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4216 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4217 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4218 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4219 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4220 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4221 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4222 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4223 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4224 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4225 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4226 static HARD_REG_SET reload_reg_used_in_op_addr;
4227 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4228 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4229 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4230 static HARD_REG_SET reload_reg_used_in_insn;
4231 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4232 static HARD_REG_SET reload_reg_used_in_other_addr;
4234 /* If reg is in use as a reload reg for any sort of reload. */
4235 static HARD_REG_SET reload_reg_used_at_all;
4237 /* If reg is use as an inherited reload. We just mark the first register
4239 static HARD_REG_SET reload_reg_used_for_inherit;
4241 /* Records which hard regs are used in any way, either as explicit use or
4242 by being allocated to a pseudo during any point of the current insn. */
4243 static HARD_REG_SET reg_used_in_insn;
4245 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4246 TYPE. MODE is used to indicate how many consecutive regs are
4250 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4251 enum machine_mode mode)
4253 unsigned int nregs = hard_regno_nregs[regno][mode];
4256 for (i = regno; i < nregs + regno; i++)
4261 SET_HARD_REG_BIT (reload_reg_used, i);
4264 case RELOAD_FOR_INPUT_ADDRESS:
4265 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4268 case RELOAD_FOR_INPADDR_ADDRESS:
4269 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4272 case RELOAD_FOR_OUTPUT_ADDRESS:
4273 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4276 case RELOAD_FOR_OUTADDR_ADDRESS:
4277 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4280 case RELOAD_FOR_OPERAND_ADDRESS:
4281 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4284 case RELOAD_FOR_OPADDR_ADDR:
4285 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4288 case RELOAD_FOR_OTHER_ADDRESS:
4289 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4292 case RELOAD_FOR_INPUT:
4293 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4296 case RELOAD_FOR_OUTPUT:
4297 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4300 case RELOAD_FOR_INSN:
4301 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4305 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4309 /* Similarly, but show REGNO is no longer in use for a reload. */
4312 clear_reload_reg_in_use (unsigned int regno, int opnum,
4313 enum reload_type type, enum machine_mode mode)
4315 unsigned int nregs = hard_regno_nregs[regno][mode];
4316 unsigned int start_regno, end_regno, r;
4318 /* A complication is that for some reload types, inheritance might
4319 allow multiple reloads of the same types to share a reload register.
4320 We set check_opnum if we have to check only reloads with the same
4321 operand number, and check_any if we have to check all reloads. */
4322 int check_opnum = 0;
4324 HARD_REG_SET *used_in_set;
4329 used_in_set = &reload_reg_used;
4332 case RELOAD_FOR_INPUT_ADDRESS:
4333 used_in_set = &reload_reg_used_in_input_addr[opnum];
4336 case RELOAD_FOR_INPADDR_ADDRESS:
4338 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4341 case RELOAD_FOR_OUTPUT_ADDRESS:
4342 used_in_set = &reload_reg_used_in_output_addr[opnum];
4345 case RELOAD_FOR_OUTADDR_ADDRESS:
4347 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4350 case RELOAD_FOR_OPERAND_ADDRESS:
4351 used_in_set = &reload_reg_used_in_op_addr;
4354 case RELOAD_FOR_OPADDR_ADDR:
4356 used_in_set = &reload_reg_used_in_op_addr_reload;
4359 case RELOAD_FOR_OTHER_ADDRESS:
4360 used_in_set = &reload_reg_used_in_other_addr;
4364 case RELOAD_FOR_INPUT:
4365 used_in_set = &reload_reg_used_in_input[opnum];
4368 case RELOAD_FOR_OUTPUT:
4369 used_in_set = &reload_reg_used_in_output[opnum];
4372 case RELOAD_FOR_INSN:
4373 used_in_set = &reload_reg_used_in_insn;
4378 /* We resolve conflicts with remaining reloads of the same type by
4379 excluding the intervals of reload registers by them from the
4380 interval of freed reload registers. Since we only keep track of
4381 one set of interval bounds, we might have to exclude somewhat
4382 more than what would be necessary if we used a HARD_REG_SET here.
4383 But this should only happen very infrequently, so there should
4384 be no reason to worry about it. */
4386 start_regno = regno;
4387 end_regno = regno + nregs;
4388 if (check_opnum || check_any)
4390 for (i = n_reloads - 1; i >= 0; i--)
4392 if (rld[i].when_needed == type
4393 && (check_any || rld[i].opnum == opnum)
4396 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4397 unsigned int conflict_end
4399 + hard_regno_nregs[conflict_start][rld[i].mode]);
4401 /* If there is an overlap with the first to-be-freed register,
4402 adjust the interval start. */
4403 if (conflict_start <= start_regno && conflict_end > start_regno)
4404 start_regno = conflict_end;
4405 /* Otherwise, if there is a conflict with one of the other
4406 to-be-freed registers, adjust the interval end. */
4407 if (conflict_start > start_regno && conflict_start < end_regno)
4408 end_regno = conflict_start;
4413 for (r = start_regno; r < end_regno; r++)
4414 CLEAR_HARD_REG_BIT (*used_in_set, r);
4417 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4418 specified by OPNUM and TYPE. */
4421 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4425 /* In use for a RELOAD_OTHER means it's not available for anything. */
4426 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4427 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4433 /* In use for anything means we can't use it for RELOAD_OTHER. */
4434 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4435 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4436 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4437 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4440 for (i = 0; i < reload_n_operands; i++)
4441 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4442 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4443 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4444 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4445 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4446 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4451 case RELOAD_FOR_INPUT:
4452 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4453 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4456 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4459 /* If it is used for some other input, can't use it. */
4460 for (i = 0; i < reload_n_operands; i++)
4461 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4464 /* If it is used in a later operand's address, can't use it. */
4465 for (i = opnum + 1; i < reload_n_operands; i++)
4466 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4467 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4472 case RELOAD_FOR_INPUT_ADDRESS:
4473 /* Can't use a register if it is used for an input address for this
4474 operand or used as an input in an earlier one. */
4475 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4476 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4479 for (i = 0; i < opnum; i++)
4480 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4485 case RELOAD_FOR_INPADDR_ADDRESS:
4486 /* Can't use a register if it is used for an input address
4487 for this operand or used as an input in an earlier
4489 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4492 for (i = 0; i < opnum; i++)
4493 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4498 case RELOAD_FOR_OUTPUT_ADDRESS:
4499 /* Can't use a register if it is used for an output address for this
4500 operand or used as an output in this or a later operand. Note
4501 that multiple output operands are emitted in reverse order, so
4502 the conflicting ones are those with lower indices. */
4503 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4506 for (i = 0; i <= opnum; i++)
4507 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4512 case RELOAD_FOR_OUTADDR_ADDRESS:
4513 /* Can't use a register if it is used for an output address
4514 for this operand or used as an output in this or a
4515 later operand. Note that multiple output operands are
4516 emitted in reverse order, so the conflicting ones are
4517 those with lower indices. */
4518 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4521 for (i = 0; i <= opnum; i++)
4522 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4527 case RELOAD_FOR_OPERAND_ADDRESS:
4528 for (i = 0; i < reload_n_operands; i++)
4529 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4532 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4533 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4535 case RELOAD_FOR_OPADDR_ADDR:
4536 for (i = 0; i < reload_n_operands; i++)
4537 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4540 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4542 case RELOAD_FOR_OUTPUT:
4543 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4544 outputs, or an operand address for this or an earlier output.
4545 Note that multiple output operands are emitted in reverse order,
4546 so the conflicting ones are those with higher indices. */
4547 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4550 for (i = 0; i < reload_n_operands; i++)
4551 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4554 for (i = opnum; i < reload_n_operands; i++)
4555 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4556 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4561 case RELOAD_FOR_INSN:
4562 for (i = 0; i < reload_n_operands; i++)
4563 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4564 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4567 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4568 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4570 case RELOAD_FOR_OTHER_ADDRESS:
4571 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4578 /* Return 1 if the value in reload reg REGNO, as used by a reload
4579 needed for the part of the insn specified by OPNUM and TYPE,
4580 is still available in REGNO at the end of the insn.
4582 We can assume that the reload reg was already tested for availability
4583 at the time it is needed, and we should not check this again,
4584 in case the reg has already been marked in use. */
4587 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4594 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4595 its value must reach the end. */
4598 /* If this use is for part of the insn,
4599 its value reaches if no subsequent part uses the same register.
4600 Just like the above function, don't try to do this with lots
4603 case RELOAD_FOR_OTHER_ADDRESS:
4604 /* Here we check for everything else, since these don't conflict
4605 with anything else and everything comes later. */
4607 for (i = 0; i < reload_n_operands; i++)
4608 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4609 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4610 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4611 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4612 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4613 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4616 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4617 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4618 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4619 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4621 case RELOAD_FOR_INPUT_ADDRESS:
4622 case RELOAD_FOR_INPADDR_ADDRESS:
4623 /* Similar, except that we check only for this and subsequent inputs
4624 and the address of only subsequent inputs and we do not need
4625 to check for RELOAD_OTHER objects since they are known not to
4628 for (i = opnum; i < reload_n_operands; i++)
4629 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4632 for (i = opnum + 1; i < reload_n_operands; i++)
4633 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4634 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4637 for (i = 0; i < reload_n_operands; i++)
4638 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4639 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4640 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4643 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4646 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4647 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4648 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4650 case RELOAD_FOR_INPUT:
4651 /* Similar to input address, except we start at the next operand for
4652 both input and input address and we do not check for
4653 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4656 for (i = opnum + 1; i < reload_n_operands; i++)
4657 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4658 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4659 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4662 /* ... fall through ... */
4664 case RELOAD_FOR_OPERAND_ADDRESS:
4665 /* Check outputs and their addresses. */
4667 for (i = 0; i < reload_n_operands; i++)
4668 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4669 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4670 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4673 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4675 case RELOAD_FOR_OPADDR_ADDR:
4676 for (i = 0; i < reload_n_operands; i++)
4677 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4678 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4679 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4682 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4683 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4684 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4686 case RELOAD_FOR_INSN:
4687 /* These conflict with other outputs with RELOAD_OTHER. So
4688 we need only check for output addresses. */
4690 opnum = reload_n_operands;
4692 /* ... fall through ... */
4694 case RELOAD_FOR_OUTPUT:
4695 case RELOAD_FOR_OUTPUT_ADDRESS:
4696 case RELOAD_FOR_OUTADDR_ADDRESS:
4697 /* We already know these can't conflict with a later output. So the
4698 only thing to check are later output addresses.
4699 Note that multiple output operands are emitted in reverse order,
4700 so the conflicting ones are those with lower indices. */
4701 for (i = 0; i < opnum; i++)
4702 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4703 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4713 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4716 This function uses the same algorithm as reload_reg_free_p above. */
4719 reloads_conflict (int r1, int r2)
4721 enum reload_type r1_type = rld[r1].when_needed;
4722 enum reload_type r2_type = rld[r2].when_needed;
4723 int r1_opnum = rld[r1].opnum;
4724 int r2_opnum = rld[r2].opnum;
4726 /* RELOAD_OTHER conflicts with everything. */
4727 if (r2_type == RELOAD_OTHER)
4730 /* Otherwise, check conflicts differently for each type. */
4734 case RELOAD_FOR_INPUT:
4735 return (r2_type == RELOAD_FOR_INSN
4736 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4737 || r2_type == RELOAD_FOR_OPADDR_ADDR
4738 || r2_type == RELOAD_FOR_INPUT
4739 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4740 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4741 && r2_opnum > r1_opnum));
4743 case RELOAD_FOR_INPUT_ADDRESS:
4744 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4745 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4747 case RELOAD_FOR_INPADDR_ADDRESS:
4748 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4749 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4751 case RELOAD_FOR_OUTPUT_ADDRESS:
4752 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4753 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4755 case RELOAD_FOR_OUTADDR_ADDRESS:
4756 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4757 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4759 case RELOAD_FOR_OPERAND_ADDRESS:
4760 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4761 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4763 case RELOAD_FOR_OPADDR_ADDR:
4764 return (r2_type == RELOAD_FOR_INPUT
4765 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4767 case RELOAD_FOR_OUTPUT:
4768 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4769 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4770 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4771 && r2_opnum >= r1_opnum));
4773 case RELOAD_FOR_INSN:
4774 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4775 || r2_type == RELOAD_FOR_INSN
4776 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4778 case RELOAD_FOR_OTHER_ADDRESS:
4779 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4789 /* Indexed by reload number, 1 if incoming value
4790 inherited from previous insns. */
4791 static char reload_inherited[MAX_RELOADS];
4793 /* For an inherited reload, this is the insn the reload was inherited from,
4794 if we know it. Otherwise, this is 0. */
4795 static rtx reload_inheritance_insn[MAX_RELOADS];
4797 /* If nonzero, this is a place to get the value of the reload,
4798 rather than using reload_in. */
4799 static rtx reload_override_in[MAX_RELOADS];
4801 /* For each reload, the hard register number of the register used,
4802 or -1 if we did not need a register for this reload. */
4803 static int reload_spill_index[MAX_RELOADS];
4805 /* Subroutine of free_for_value_p, used to check a single register.
4806 START_REGNO is the starting regno of the full reload register
4807 (possibly comprising multiple hard registers) that we are considering. */
4810 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4811 enum reload_type type, rtx value, rtx out,
4812 int reloadnum, int ignore_address_reloads)
4815 /* Set if we see an input reload that must not share its reload register
4816 with any new earlyclobber, but might otherwise share the reload
4817 register with an output or input-output reload. */
4818 int check_earlyclobber = 0;
4822 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4825 if (out == const0_rtx)
4831 /* We use some pseudo 'time' value to check if the lifetimes of the
4832 new register use would overlap with the one of a previous reload
4833 that is not read-only or uses a different value.
4834 The 'time' used doesn't have to be linear in any shape or form, just
4836 Some reload types use different 'buckets' for each operand.
4837 So there are MAX_RECOG_OPERANDS different time values for each
4839 We compute TIME1 as the time when the register for the prospective
4840 new reload ceases to be live, and TIME2 for each existing
4841 reload as the time when that the reload register of that reload
4843 Where there is little to be gained by exact lifetime calculations,
4844 we just make conservative assumptions, i.e. a longer lifetime;
4845 this is done in the 'default:' cases. */
4848 case RELOAD_FOR_OTHER_ADDRESS:
4849 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4850 time1 = copy ? 0 : 1;
4853 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4855 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4856 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4857 respectively, to the time values for these, we get distinct time
4858 values. To get distinct time values for each operand, we have to
4859 multiply opnum by at least three. We round that up to four because
4860 multiply by four is often cheaper. */
4861 case RELOAD_FOR_INPADDR_ADDRESS:
4862 time1 = opnum * 4 + 2;
4864 case RELOAD_FOR_INPUT_ADDRESS:
4865 time1 = opnum * 4 + 3;
4867 case RELOAD_FOR_INPUT:
4868 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4869 executes (inclusive). */
4870 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4872 case RELOAD_FOR_OPADDR_ADDR:
4874 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4875 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4877 case RELOAD_FOR_OPERAND_ADDRESS:
4878 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4880 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4882 case RELOAD_FOR_OUTADDR_ADDRESS:
4883 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4885 case RELOAD_FOR_OUTPUT_ADDRESS:
4886 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4889 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4892 for (i = 0; i < n_reloads; i++)
4894 rtx reg = rld[i].reg_rtx;
4895 if (reg && REG_P (reg)
4896 && ((unsigned) regno - true_regnum (reg)
4897 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
4900 rtx other_input = rld[i].in;
4902 /* If the other reload loads the same input value, that
4903 will not cause a conflict only if it's loading it into
4904 the same register. */
4905 if (true_regnum (reg) != start_regno)
4906 other_input = NULL_RTX;
4907 if (! other_input || ! rtx_equal_p (other_input, value)
4908 || rld[i].out || out)
4911 switch (rld[i].when_needed)
4913 case RELOAD_FOR_OTHER_ADDRESS:
4916 case RELOAD_FOR_INPADDR_ADDRESS:
4917 /* find_reloads makes sure that a
4918 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4919 by at most one - the first -
4920 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4921 address reload is inherited, the address address reload
4922 goes away, so we can ignore this conflict. */
4923 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4924 && ignore_address_reloads
4925 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4926 Then the address address is still needed to store
4927 back the new address. */
4928 && ! rld[reloadnum].out)
4930 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4931 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4933 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4934 && ignore_address_reloads
4935 /* Unless we are reloading an auto_inc expression. */
4936 && ! rld[reloadnum].out)
4938 time2 = rld[i].opnum * 4 + 2;
4940 case RELOAD_FOR_INPUT_ADDRESS:
4941 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4942 && ignore_address_reloads
4943 && ! rld[reloadnum].out)
4945 time2 = rld[i].opnum * 4 + 3;
4947 case RELOAD_FOR_INPUT:
4948 time2 = rld[i].opnum * 4 + 4;
4949 check_earlyclobber = 1;
4951 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4952 == MAX_RECOG_OPERAND * 4 */
4953 case RELOAD_FOR_OPADDR_ADDR:
4954 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4955 && ignore_address_reloads
4956 && ! rld[reloadnum].out)
4958 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4960 case RELOAD_FOR_OPERAND_ADDRESS:
4961 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4962 check_earlyclobber = 1;
4964 case RELOAD_FOR_INSN:
4965 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4967 case RELOAD_FOR_OUTPUT:
4968 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4969 instruction is executed. */
4970 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4972 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4973 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4975 case RELOAD_FOR_OUTADDR_ADDRESS:
4976 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4977 && ignore_address_reloads
4978 && ! rld[reloadnum].out)
4980 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4982 case RELOAD_FOR_OUTPUT_ADDRESS:
4983 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4986 /* If there is no conflict in the input part, handle this
4987 like an output reload. */
4988 if (! rld[i].in || rtx_equal_p (other_input, value))
4990 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4991 /* Earlyclobbered outputs must conflict with inputs. */
4992 if (earlyclobber_operand_p (rld[i].out))
4993 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4998 /* RELOAD_OTHER might be live beyond instruction execution,
4999 but this is not obvious when we set time2 = 1. So check
5000 here if there might be a problem with the new reload
5001 clobbering the register used by the RELOAD_OTHER. */
5009 && (! rld[i].in || rld[i].out
5010 || ! rtx_equal_p (other_input, value)))
5011 || (out && rld[reloadnum].out_reg
5012 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5018 /* Earlyclobbered outputs must conflict with inputs. */
5019 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5025 /* Return 1 if the value in reload reg REGNO, as used by a reload
5026 needed for the part of the insn specified by OPNUM and TYPE,
5027 may be used to load VALUE into it.
5029 MODE is the mode in which the register is used, this is needed to
5030 determine how many hard regs to test.
5032 Other read-only reloads with the same value do not conflict
5033 unless OUT is nonzero and these other reloads have to live while
5034 output reloads live.
5035 If OUT is CONST0_RTX, this is a special case: it means that the
5036 test should not be for using register REGNO as reload register, but
5037 for copying from register REGNO into the reload register.
5039 RELOADNUM is the number of the reload we want to load this value for;
5040 a reload does not conflict with itself.
5042 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5043 reloads that load an address for the very reload we are considering.
5045 The caller has to make sure that there is no conflict with the return
5049 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5050 enum reload_type type, rtx value, rtx out, int reloadnum,
5051 int ignore_address_reloads)
5053 int nregs = hard_regno_nregs[regno][mode];
5055 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5056 value, out, reloadnum,
5057 ignore_address_reloads))
5062 /* Return nonzero if the rtx X is invariant over the current function. */
5063 /* ??? Actually, the places where we use this expect exactly what is
5064 tested here, and not everything that is function invariant. In
5065 particular, the frame pointer and arg pointer are special cased;
5066 pic_offset_table_rtx is not, and we must not spill these things to
5070 function_invariant_p (rtx x)
5074 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5076 if (GET_CODE (x) == PLUS
5077 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5078 && CONSTANT_P (XEXP (x, 1)))
5083 /* Determine whether the reload reg X overlaps any rtx'es used for
5084 overriding inheritance. Return nonzero if so. */
5087 conflicts_with_override (rtx x)
5090 for (i = 0; i < n_reloads; i++)
5091 if (reload_override_in[i]
5092 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5097 /* Give an error message saying we failed to find a reload for INSN,
5098 and clear out reload R. */
5100 failed_reload (rtx insn, int r)
5102 if (asm_noperands (PATTERN (insn)) < 0)
5103 /* It's the compiler's fault. */
5104 fatal_insn ("could not find a spill register", insn);
5106 /* It's the user's fault; the operand's mode and constraint
5107 don't match. Disable this reload so we don't crash in final. */
5108 error_for_asm (insn,
5109 "%<asm%> operand constraint incompatible with operand size");
5113 rld[r].optional = 1;
5114 rld[r].secondary_p = 1;
5117 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5118 for reload R. If it's valid, get an rtx for it. Return nonzero if
5121 set_reload_reg (int i, int r)
5124 rtx reg = spill_reg_rtx[i];
5126 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5127 spill_reg_rtx[i] = reg
5128 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5130 regno = true_regnum (reg);
5132 /* Detect when the reload reg can't hold the reload mode.
5133 This used to be one `if', but Sequent compiler can't handle that. */
5134 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5136 enum machine_mode test_mode = VOIDmode;
5138 test_mode = GET_MODE (rld[r].in);
5139 /* If rld[r].in has VOIDmode, it means we will load it
5140 in whatever mode the reload reg has: to wit, rld[r].mode.
5141 We have already tested that for validity. */
5142 /* Aside from that, we need to test that the expressions
5143 to reload from or into have modes which are valid for this
5144 reload register. Otherwise the reload insns would be invalid. */
5145 if (! (rld[r].in != 0 && test_mode != VOIDmode
5146 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5147 if (! (rld[r].out != 0
5148 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5150 /* The reg is OK. */
5153 /* Mark as in use for this insn the reload regs we use
5155 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5156 rld[r].when_needed, rld[r].mode);
5158 rld[r].reg_rtx = reg;
5159 reload_spill_index[r] = spill_regs[i];
5166 /* Find a spill register to use as a reload register for reload R.
5167 LAST_RELOAD is nonzero if this is the last reload for the insn being
5170 Set rld[R].reg_rtx to the register allocated.
5172 We return 1 if successful, or 0 if we couldn't find a spill reg and
5173 we didn't change anything. */
5176 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5181 /* If we put this reload ahead, thinking it is a group,
5182 then insist on finding a group. Otherwise we can grab a
5183 reg that some other reload needs.
5184 (That can happen when we have a 68000 DATA_OR_FP_REG
5185 which is a group of data regs or one fp reg.)
5186 We need not be so restrictive if there are no more reloads
5189 ??? Really it would be nicer to have smarter handling
5190 for that kind of reg class, where a problem like this is normal.
5191 Perhaps those classes should be avoided for reloading
5192 by use of more alternatives. */
5194 int force_group = rld[r].nregs > 1 && ! last_reload;
5196 /* If we want a single register and haven't yet found one,
5197 take any reg in the right class and not in use.
5198 If we want a consecutive group, here is where we look for it.
5200 We use two passes so we can first look for reload regs to
5201 reuse, which are already in use for other reloads in this insn,
5202 and only then use additional registers.
5203 I think that maximizing reuse is needed to make sure we don't
5204 run out of reload regs. Suppose we have three reloads, and
5205 reloads A and B can share regs. These need two regs.
5206 Suppose A and B are given different regs.
5207 That leaves none for C. */
5208 for (pass = 0; pass < 2; pass++)
5210 /* I is the index in spill_regs.
5211 We advance it round-robin between insns to use all spill regs
5212 equally, so that inherited reloads have a chance
5213 of leapfrogging each other. */
5217 for (count = 0; count < n_spills; count++)
5219 int class = (int) rld[r].class;
5225 regnum = spill_regs[i];
5227 if ((reload_reg_free_p (regnum, rld[r].opnum,
5230 /* We check reload_reg_used to make sure we
5231 don't clobber the return register. */
5232 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5233 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5234 rld[r].when_needed, rld[r].in,
5236 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5237 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5238 /* Look first for regs to share, then for unshared. But
5239 don't share regs used for inherited reloads; they are
5240 the ones we want to preserve. */
5242 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5244 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5247 int nr = hard_regno_nregs[regnum][rld[r].mode];
5248 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5249 (on 68000) got us two FP regs. If NR is 1,
5250 we would reject both of them. */
5253 /* If we need only one reg, we have already won. */
5256 /* But reject a single reg if we demand a group. */
5261 /* Otherwise check that as many consecutive regs as we need
5262 are available here. */
5265 int regno = regnum + nr - 1;
5266 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5267 && spill_reg_order[regno] >= 0
5268 && reload_reg_free_p (regno, rld[r].opnum,
5269 rld[r].when_needed)))
5278 /* If we found something on pass 1, omit pass 2. */
5279 if (count < n_spills)
5283 /* We should have found a spill register by now. */
5284 if (count >= n_spills)
5287 /* I is the index in SPILL_REG_RTX of the reload register we are to
5288 allocate. Get an rtx for it and find its register number. */
5290 return set_reload_reg (i, r);
5293 /* Initialize all the tables needed to allocate reload registers.
5294 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5295 is the array we use to restore the reg_rtx field for every reload. */
5298 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5302 for (i = 0; i < n_reloads; i++)
5303 rld[i].reg_rtx = save_reload_reg_rtx[i];
5305 memset (reload_inherited, 0, MAX_RELOADS);
5306 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5307 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5309 CLEAR_HARD_REG_SET (reload_reg_used);
5310 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5311 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5312 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5313 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5314 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5316 CLEAR_HARD_REG_SET (reg_used_in_insn);
5319 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5320 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5321 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5322 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5323 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5324 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5327 for (i = 0; i < reload_n_operands; i++)
5329 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5330 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5331 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5332 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5333 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5334 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5337 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5339 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5341 for (i = 0; i < n_reloads; i++)
5342 /* If we have already decided to use a certain register,
5343 don't use it in another way. */
5345 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5346 rld[i].when_needed, rld[i].mode);
5349 /* Assign hard reg targets for the pseudo-registers we must reload
5350 into hard regs for this insn.
5351 Also output the instructions to copy them in and out of the hard regs.
5353 For machines with register classes, we are responsible for
5354 finding a reload reg in the proper class. */
5357 choose_reload_regs (struct insn_chain *chain)
5359 rtx insn = chain->insn;
5361 unsigned int max_group_size = 1;
5362 enum reg_class group_class = NO_REGS;
5363 int pass, win, inheritance;
5365 rtx save_reload_reg_rtx[MAX_RELOADS];
5367 /* In order to be certain of getting the registers we need,
5368 we must sort the reloads into order of increasing register class.
5369 Then our grabbing of reload registers will parallel the process
5370 that provided the reload registers.
5372 Also note whether any of the reloads wants a consecutive group of regs.
5373 If so, record the maximum size of the group desired and what
5374 register class contains all the groups needed by this insn. */
5376 for (j = 0; j < n_reloads; j++)
5378 reload_order[j] = j;
5379 reload_spill_index[j] = -1;
5381 if (rld[j].nregs > 1)
5383 max_group_size = MAX (rld[j].nregs, max_group_size);
5385 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5388 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5392 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5394 /* If -O, try first with inheritance, then turning it off.
5395 If not -O, don't do inheritance.
5396 Using inheritance when not optimizing leads to paradoxes
5397 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5398 because one side of the comparison might be inherited. */
5400 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5402 choose_reload_regs_init (chain, save_reload_reg_rtx);
5404 /* Process the reloads in order of preference just found.
5405 Beyond this point, subregs can be found in reload_reg_rtx.
5407 This used to look for an existing reloaded home for all of the
5408 reloads, and only then perform any new reloads. But that could lose
5409 if the reloads were done out of reg-class order because a later
5410 reload with a looser constraint might have an old home in a register
5411 needed by an earlier reload with a tighter constraint.
5413 To solve this, we make two passes over the reloads, in the order
5414 described above. In the first pass we try to inherit a reload
5415 from a previous insn. If there is a later reload that needs a
5416 class that is a proper subset of the class being processed, we must
5417 also allocate a spill register during the first pass.
5419 Then make a second pass over the reloads to allocate any reloads
5420 that haven't been given registers yet. */
5422 for (j = 0; j < n_reloads; j++)
5424 int r = reload_order[j];
5425 rtx search_equiv = NULL_RTX;
5427 /* Ignore reloads that got marked inoperative. */
5428 if (rld[r].out == 0 && rld[r].in == 0
5429 && ! rld[r].secondary_p)
5432 /* If find_reloads chose to use reload_in or reload_out as a reload
5433 register, we don't need to chose one. Otherwise, try even if it
5434 found one since we might save an insn if we find the value lying
5436 Try also when reload_in is a pseudo without a hard reg. */
5437 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5438 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5439 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5440 && !MEM_P (rld[r].in)
5441 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5444 #if 0 /* No longer needed for correct operation.
5445 It might give better code, or might not; worth an experiment? */
5446 /* If this is an optional reload, we can't inherit from earlier insns
5447 until we are sure that any non-optional reloads have been allocated.
5448 The following code takes advantage of the fact that optional reloads
5449 are at the end of reload_order. */
5450 if (rld[r].optional != 0)
5451 for (i = 0; i < j; i++)
5452 if ((rld[reload_order[i]].out != 0
5453 || rld[reload_order[i]].in != 0
5454 || rld[reload_order[i]].secondary_p)
5455 && ! rld[reload_order[i]].optional
5456 && rld[reload_order[i]].reg_rtx == 0)
5457 allocate_reload_reg (chain, reload_order[i], 0);
5460 /* First see if this pseudo is already available as reloaded
5461 for a previous insn. We cannot try to inherit for reloads
5462 that are smaller than the maximum number of registers needed
5463 for groups unless the register we would allocate cannot be used
5466 We could check here to see if this is a secondary reload for
5467 an object that is already in a register of the desired class.
5468 This would avoid the need for the secondary reload register.
5469 But this is complex because we can't easily determine what
5470 objects might want to be loaded via this reload. So let a
5471 register be allocated here. In `emit_reload_insns' we suppress
5472 one of the loads in the case described above. */
5478 enum machine_mode mode = VOIDmode;
5482 else if (REG_P (rld[r].in))
5484 regno = REGNO (rld[r].in);
5485 mode = GET_MODE (rld[r].in);
5487 else if (REG_P (rld[r].in_reg))
5489 regno = REGNO (rld[r].in_reg);
5490 mode = GET_MODE (rld[r].in_reg);
5492 else if (GET_CODE (rld[r].in_reg) == SUBREG
5493 && REG_P (SUBREG_REG (rld[r].in_reg)))
5495 byte = SUBREG_BYTE (rld[r].in_reg);
5496 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5497 if (regno < FIRST_PSEUDO_REGISTER)
5498 regno = subreg_regno (rld[r].in_reg);
5499 mode = GET_MODE (rld[r].in_reg);
5502 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5503 || GET_CODE (rld[r].in_reg) == PRE_DEC
5504 || GET_CODE (rld[r].in_reg) == POST_INC
5505 || GET_CODE (rld[r].in_reg) == POST_DEC)
5506 && REG_P (XEXP (rld[r].in_reg, 0)))
5508 regno = REGNO (XEXP (rld[r].in_reg, 0));
5509 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5510 rld[r].out = rld[r].in;
5514 /* This won't work, since REGNO can be a pseudo reg number.
5515 Also, it takes much more hair to keep track of all the things
5516 that can invalidate an inherited reload of part of a pseudoreg. */
5517 else if (GET_CODE (rld[r].in) == SUBREG
5518 && REG_P (SUBREG_REG (rld[r].in)))
5519 regno = subreg_regno (rld[r].in);
5522 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5524 enum reg_class class = rld[r].class, last_class;
5525 rtx last_reg = reg_last_reload_reg[regno];
5526 enum machine_mode need_mode;
5528 i = REGNO (last_reg);
5529 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5530 last_class = REGNO_REG_CLASS (i);
5536 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
5537 + byte * BITS_PER_UNIT,
5538 GET_MODE_CLASS (mode));
5540 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5541 >= GET_MODE_SIZE (need_mode))
5542 #ifdef CANNOT_CHANGE_MODE_CLASS
5543 /* Verify that the register in "i" can be obtained
5545 && !REG_CANNOT_CHANGE_MODE_P (REGNO (last_reg),
5546 GET_MODE (last_reg),
5549 && reg_reloaded_contents[i] == regno
5550 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5551 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5552 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5553 /* Even if we can't use this register as a reload
5554 register, we might use it for reload_override_in,
5555 if copying it to the desired class is cheap
5557 || ((REGISTER_MOVE_COST (mode, last_class, class)
5558 < MEMORY_MOVE_COST (mode, class, 1))
5559 && (secondary_reload_class (1, class, mode,
5562 #ifdef SECONDARY_MEMORY_NEEDED
5563 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5568 && (rld[r].nregs == max_group_size
5569 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5571 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5572 rld[r].when_needed, rld[r].in,
5575 /* If a group is needed, verify that all the subsequent
5576 registers still have their values intact. */
5577 int nr = hard_regno_nregs[i][rld[r].mode];
5580 for (k = 1; k < nr; k++)
5581 if (reg_reloaded_contents[i + k] != regno
5582 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5590 last_reg = (GET_MODE (last_reg) == mode
5591 ? last_reg : gen_rtx_REG (mode, i));
5594 for (k = 0; k < nr; k++)
5595 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5598 /* We found a register that contains the
5599 value we need. If this register is the
5600 same as an `earlyclobber' operand of the
5601 current insn, just mark it as a place to
5602 reload from since we can't use it as the
5603 reload register itself. */
5605 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5606 if (reg_overlap_mentioned_for_reload_p
5607 (reg_last_reload_reg[regno],
5608 reload_earlyclobbers[i1]))
5611 if (i1 != n_earlyclobbers
5612 || ! (free_for_value_p (i, rld[r].mode,
5614 rld[r].when_needed, rld[r].in,
5616 /* Don't use it if we'd clobber a pseudo reg. */
5617 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5619 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5620 /* Don't clobber the frame pointer. */
5621 || (i == HARD_FRAME_POINTER_REGNUM
5622 && frame_pointer_needed
5624 /* Don't really use the inherited spill reg
5625 if we need it wider than we've got it. */
5626 || (GET_MODE_SIZE (rld[r].mode)
5627 > GET_MODE_SIZE (mode))
5630 /* If find_reloads chose reload_out as reload
5631 register, stay with it - that leaves the
5632 inherited register for subsequent reloads. */
5633 || (rld[r].out && rld[r].reg_rtx
5634 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5636 if (! rld[r].optional)
5638 reload_override_in[r] = last_reg;
5639 reload_inheritance_insn[r]
5640 = reg_reloaded_insn[i];
5646 /* We can use this as a reload reg. */
5647 /* Mark the register as in use for this part of
5649 mark_reload_reg_in_use (i,
5653 rld[r].reg_rtx = last_reg;
5654 reload_inherited[r] = 1;
5655 reload_inheritance_insn[r]
5656 = reg_reloaded_insn[i];
5657 reload_spill_index[r] = i;
5658 for (k = 0; k < nr; k++)
5659 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5667 /* Here's another way to see if the value is already lying around. */
5670 && ! reload_inherited[r]
5672 && (CONSTANT_P (rld[r].in)
5673 || GET_CODE (rld[r].in) == PLUS
5674 || REG_P (rld[r].in)
5675 || MEM_P (rld[r].in))
5676 && (rld[r].nregs == max_group_size
5677 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5678 search_equiv = rld[r].in;
5679 /* If this is an output reload from a simple move insn, look
5680 if an equivalence for the input is available. */
5681 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5683 rtx set = single_set (insn);
5686 && rtx_equal_p (rld[r].out, SET_DEST (set))
5687 && CONSTANT_P (SET_SRC (set)))
5688 search_equiv = SET_SRC (set);
5694 = find_equiv_reg (search_equiv, insn, rld[r].class,
5695 -1, NULL, 0, rld[r].mode);
5701 regno = REGNO (equiv);
5704 /* This must be a SUBREG of a hard register.
5705 Make a new REG since this might be used in an
5706 address and not all machines support SUBREGs
5708 gcc_assert (GET_CODE (equiv) == SUBREG);
5709 regno = subreg_regno (equiv);
5710 equiv = gen_rtx_REG (rld[r].mode, regno);
5711 /* If we choose EQUIV as the reload register, but the
5712 loop below decides to cancel the inheritance, we'll
5713 end up reloading EQUIV in rld[r].mode, not the mode
5714 it had originally. That isn't safe when EQUIV isn't
5715 available as a spill register since its value might
5716 still be live at this point. */
5717 for (i = regno; i < regno + (int) rld[r].nregs; i++)
5718 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
5723 /* If we found a spill reg, reject it unless it is free
5724 and of the desired class. */
5728 int bad_for_class = 0;
5729 int max_regno = regno + rld[r].nregs;
5731 for (i = regno; i < max_regno; i++)
5733 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5735 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5740 && ! free_for_value_p (regno, rld[r].mode,
5741 rld[r].opnum, rld[r].when_needed,
5742 rld[r].in, rld[r].out, r, 1))
5747 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5750 /* We found a register that contains the value we need.
5751 If this register is the same as an `earlyclobber' operand
5752 of the current insn, just mark it as a place to reload from
5753 since we can't use it as the reload register itself. */
5756 for (i = 0; i < n_earlyclobbers; i++)
5757 if (reg_overlap_mentioned_for_reload_p (equiv,
5758 reload_earlyclobbers[i]))
5760 if (! rld[r].optional)
5761 reload_override_in[r] = equiv;
5766 /* If the equiv register we have found is explicitly clobbered
5767 in the current insn, it depends on the reload type if we
5768 can use it, use it for reload_override_in, or not at all.
5769 In particular, we then can't use EQUIV for a
5770 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5774 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5775 switch (rld[r].when_needed)
5777 case RELOAD_FOR_OTHER_ADDRESS:
5778 case RELOAD_FOR_INPADDR_ADDRESS:
5779 case RELOAD_FOR_INPUT_ADDRESS:
5780 case RELOAD_FOR_OPADDR_ADDR:
5783 case RELOAD_FOR_INPUT:
5784 case RELOAD_FOR_OPERAND_ADDRESS:
5785 if (! rld[r].optional)
5786 reload_override_in[r] = equiv;
5792 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5793 switch (rld[r].when_needed)
5795 case RELOAD_FOR_OTHER_ADDRESS:
5796 case RELOAD_FOR_INPADDR_ADDRESS:
5797 case RELOAD_FOR_INPUT_ADDRESS:
5798 case RELOAD_FOR_OPADDR_ADDR:
5799 case RELOAD_FOR_OPERAND_ADDRESS:
5800 case RELOAD_FOR_INPUT:
5803 if (! rld[r].optional)
5804 reload_override_in[r] = equiv;
5812 /* If we found an equivalent reg, say no code need be generated
5813 to load it, and use it as our reload reg. */
5815 && (regno != HARD_FRAME_POINTER_REGNUM
5816 || !frame_pointer_needed))
5818 int nr = hard_regno_nregs[regno][rld[r].mode];
5820 rld[r].reg_rtx = equiv;
5821 reload_inherited[r] = 1;
5823 /* If reg_reloaded_valid is not set for this register,
5824 there might be a stale spill_reg_store lying around.
5825 We must clear it, since otherwise emit_reload_insns
5826 might delete the store. */
5827 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5828 spill_reg_store[regno] = NULL_RTX;
5829 /* If any of the hard registers in EQUIV are spill
5830 registers, mark them as in use for this insn. */
5831 for (k = 0; k < nr; k++)
5833 i = spill_reg_order[regno + k];
5836 mark_reload_reg_in_use (regno, rld[r].opnum,
5839 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5846 /* If we found a register to use already, or if this is an optional
5847 reload, we are done. */
5848 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5852 /* No longer needed for correct operation. Might or might
5853 not give better code on the average. Want to experiment? */
5855 /* See if there is a later reload that has a class different from our
5856 class that intersects our class or that requires less register
5857 than our reload. If so, we must allocate a register to this
5858 reload now, since that reload might inherit a previous reload
5859 and take the only available register in our class. Don't do this
5860 for optional reloads since they will force all previous reloads
5861 to be allocated. Also don't do this for reloads that have been
5864 for (i = j + 1; i < n_reloads; i++)
5866 int s = reload_order[i];
5868 if ((rld[s].in == 0 && rld[s].out == 0
5869 && ! rld[s].secondary_p)
5873 if ((rld[s].class != rld[r].class
5874 && reg_classes_intersect_p (rld[r].class,
5876 || rld[s].nregs < rld[r].nregs)
5883 allocate_reload_reg (chain, r, j == n_reloads - 1);
5887 /* Now allocate reload registers for anything non-optional that
5888 didn't get one yet. */
5889 for (j = 0; j < n_reloads; j++)
5891 int r = reload_order[j];
5893 /* Ignore reloads that got marked inoperative. */
5894 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5897 /* Skip reloads that already have a register allocated or are
5899 if (rld[r].reg_rtx != 0 || rld[r].optional)
5902 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5906 /* If that loop got all the way, we have won. */
5913 /* Loop around and try without any inheritance. */
5918 /* First undo everything done by the failed attempt
5919 to allocate with inheritance. */
5920 choose_reload_regs_init (chain, save_reload_reg_rtx);
5922 /* Some sanity tests to verify that the reloads found in the first
5923 pass are identical to the ones we have now. */
5924 gcc_assert (chain->n_reloads == n_reloads);
5926 for (i = 0; i < n_reloads; i++)
5928 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5930 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
5931 for (j = 0; j < n_spills; j++)
5932 if (spill_regs[j] == chain->rld[i].regno)
5933 if (! set_reload_reg (j, i))
5934 failed_reload (chain->insn, i);
5938 /* If we thought we could inherit a reload, because it seemed that
5939 nothing else wanted the same reload register earlier in the insn,
5940 verify that assumption, now that all reloads have been assigned.
5941 Likewise for reloads where reload_override_in has been set. */
5943 /* If doing expensive optimizations, do one preliminary pass that doesn't
5944 cancel any inheritance, but removes reloads that have been needed only
5945 for reloads that we know can be inherited. */
5946 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5948 for (j = 0; j < n_reloads; j++)
5950 int r = reload_order[j];
5952 if (reload_inherited[r] && rld[r].reg_rtx)
5953 check_reg = rld[r].reg_rtx;
5954 else if (reload_override_in[r]
5955 && (REG_P (reload_override_in[r])
5956 || GET_CODE (reload_override_in[r]) == SUBREG))
5957 check_reg = reload_override_in[r];
5960 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5961 rld[r].opnum, rld[r].when_needed, rld[r].in,
5962 (reload_inherited[r]
5963 ? rld[r].out : const0_rtx),
5968 reload_inherited[r] = 0;
5969 reload_override_in[r] = 0;
5971 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5972 reload_override_in, then we do not need its related
5973 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5974 likewise for other reload types.
5975 We handle this by removing a reload when its only replacement
5976 is mentioned in reload_in of the reload we are going to inherit.
5977 A special case are auto_inc expressions; even if the input is
5978 inherited, we still need the address for the output. We can
5979 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5980 If we succeeded removing some reload and we are doing a preliminary
5981 pass just to remove such reloads, make another pass, since the
5982 removal of one reload might allow us to inherit another one. */
5984 && rld[r].out != rld[r].in
5985 && remove_address_replacements (rld[r].in) && pass)
5990 /* Now that reload_override_in is known valid,
5991 actually override reload_in. */
5992 for (j = 0; j < n_reloads; j++)
5993 if (reload_override_in[j])
5994 rld[j].in = reload_override_in[j];
5996 /* If this reload won't be done because it has been canceled or is
5997 optional and not inherited, clear reload_reg_rtx so other
5998 routines (such as subst_reloads) don't get confused. */
5999 for (j = 0; j < n_reloads; j++)
6000 if (rld[j].reg_rtx != 0
6001 && ((rld[j].optional && ! reload_inherited[j])
6002 || (rld[j].in == 0 && rld[j].out == 0
6003 && ! rld[j].secondary_p)))
6005 int regno = true_regnum (rld[j].reg_rtx);
6007 if (spill_reg_order[regno] >= 0)
6008 clear_reload_reg_in_use (regno, rld[j].opnum,
6009 rld[j].when_needed, rld[j].mode);
6011 reload_spill_index[j] = -1;
6014 /* Record which pseudos and which spill regs have output reloads. */
6015 for (j = 0; j < n_reloads; j++)
6017 int r = reload_order[j];
6019 i = reload_spill_index[r];
6021 /* I is nonneg if this reload uses a register.
6022 If rld[r].reg_rtx is 0, this is an optional reload
6023 that we opted to ignore. */
6024 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6025 && rld[r].reg_rtx != 0)
6027 int nregno = REGNO (rld[r].out_reg);
6030 if (nregno < FIRST_PSEUDO_REGISTER)
6031 nr = hard_regno_nregs[nregno][rld[r].mode];
6034 reg_has_output_reload[nregno + nr] = 1;
6038 nr = hard_regno_nregs[i][rld[r].mode];
6040 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6043 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6044 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6045 || rld[r].when_needed == RELOAD_FOR_INSN);
6050 /* Deallocate the reload register for reload R. This is called from
6051 remove_address_replacements. */
6054 deallocate_reload_reg (int r)
6058 if (! rld[r].reg_rtx)
6060 regno = true_regnum (rld[r].reg_rtx);
6062 if (spill_reg_order[regno] >= 0)
6063 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6065 reload_spill_index[r] = -1;
6068 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6069 reloads of the same item for fear that we might not have enough reload
6070 registers. However, normally they will get the same reload register
6071 and hence actually need not be loaded twice.
6073 Here we check for the most common case of this phenomenon: when we have
6074 a number of reloads for the same object, each of which were allocated
6075 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6076 reload, and is not modified in the insn itself. If we find such,
6077 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6078 This will not increase the number of spill registers needed and will
6079 prevent redundant code. */
6082 merge_assigned_reloads (rtx insn)
6086 /* Scan all the reloads looking for ones that only load values and
6087 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6088 assigned and not modified by INSN. */
6090 for (i = 0; i < n_reloads; i++)
6092 int conflicting_input = 0;
6093 int max_input_address_opnum = -1;
6094 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6096 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6097 || rld[i].out != 0 || rld[i].reg_rtx == 0
6098 || reg_set_p (rld[i].reg_rtx, insn))
6101 /* Look at all other reloads. Ensure that the only use of this
6102 reload_reg_rtx is in a reload that just loads the same value
6103 as we do. Note that any secondary reloads must be of the identical
6104 class since the values, modes, and result registers are the
6105 same, so we need not do anything with any secondary reloads. */
6107 for (j = 0; j < n_reloads; j++)
6109 if (i == j || rld[j].reg_rtx == 0
6110 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6114 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6115 && rld[j].opnum > max_input_address_opnum)
6116 max_input_address_opnum = rld[j].opnum;
6118 /* If the reload regs aren't exactly the same (e.g, different modes)
6119 or if the values are different, we can't merge this reload.
6120 But if it is an input reload, we might still merge
6121 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6123 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6124 || rld[j].out != 0 || rld[j].in == 0
6125 || ! rtx_equal_p (rld[i].in, rld[j].in))
6127 if (rld[j].when_needed != RELOAD_FOR_INPUT
6128 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6129 || rld[i].opnum > rld[j].opnum)
6130 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6132 conflicting_input = 1;
6133 if (min_conflicting_input_opnum > rld[j].opnum)
6134 min_conflicting_input_opnum = rld[j].opnum;
6138 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6139 we, in fact, found any matching reloads. */
6142 && max_input_address_opnum <= min_conflicting_input_opnum)
6144 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6146 for (j = 0; j < n_reloads; j++)
6147 if (i != j && rld[j].reg_rtx != 0
6148 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6149 && (! conflicting_input
6150 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6151 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6153 rld[i].when_needed = RELOAD_OTHER;
6155 reload_spill_index[j] = -1;
6156 transfer_replacements (i, j);
6159 /* If this is now RELOAD_OTHER, look for any reloads that load
6160 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6161 if they were for inputs, RELOAD_OTHER for outputs. Note that
6162 this test is equivalent to looking for reloads for this operand
6164 /* We must take special care with RELOAD_FOR_OUTPUT_ADDRESS; it may
6165 share registers with a RELOAD_FOR_INPUT, so we can not change it
6166 to RELOAD_FOR_OTHER_ADDRESS. We should never need to, since we
6167 do not modify RELOAD_FOR_OUTPUT. */
6169 if (rld[i].when_needed == RELOAD_OTHER)
6170 for (j = 0; j < n_reloads; j++)
6172 && rld[j].when_needed != RELOAD_OTHER
6173 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6174 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6175 && (! conflicting_input
6176 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6177 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6178 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6184 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6185 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6186 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6188 /* Check to see if we accidentally converted two
6189 reloads that use the same reload register with
6190 different inputs to the same type. If so, the
6191 resulting code won't work. */
6193 for (k = 0; k < j; k++)
6194 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6195 || rld[k].when_needed != rld[j].when_needed
6196 || !rtx_equal_p (rld[k].reg_rtx,
6198 || rtx_equal_p (rld[k].in,
6205 /* These arrays are filled by emit_reload_insns and its subroutines. */
6206 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6207 static rtx other_input_address_reload_insns = 0;
6208 static rtx other_input_reload_insns = 0;
6209 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6210 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6211 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6212 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6213 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6214 static rtx operand_reload_insns = 0;
6215 static rtx other_operand_reload_insns = 0;
6216 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6218 /* Values to be put in spill_reg_store are put here first. */
6219 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6220 static HARD_REG_SET reg_reloaded_died;
6222 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6223 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6224 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6225 adjusted register, and return true. Otherwise, return false. */
6227 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6228 enum reg_class new_class,
6229 enum machine_mode new_mode)
6234 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6236 unsigned regno = REGNO (reg);
6238 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6240 if (GET_MODE (reg) != new_mode)
6242 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6244 if (hard_regno_nregs[regno][new_mode]
6245 > hard_regno_nregs[regno][GET_MODE (reg)])
6247 reg = reload_adjust_reg_for_mode (reg, new_mode);
6255 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6256 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6257 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6258 adjusted register, and return true. Otherwise, return false. */
6260 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6261 enum insn_code icode)
6264 enum reg_class new_class = scratch_reload_class (icode);
6265 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6267 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6268 new_class, new_mode);
6271 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6272 has the number J. OLD contains the value to be used as input. */
6275 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6278 rtx insn = chain->insn;
6279 rtx reloadreg = rl->reg_rtx;
6280 rtx oldequiv_reg = 0;
6283 enum machine_mode mode;
6286 /* Determine the mode to reload in.
6287 This is very tricky because we have three to choose from.
6288 There is the mode the insn operand wants (rl->inmode).
6289 There is the mode of the reload register RELOADREG.
6290 There is the intrinsic mode of the operand, which we could find
6291 by stripping some SUBREGs.
6292 It turns out that RELOADREG's mode is irrelevant:
6293 we can change that arbitrarily.
6295 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6296 then the reload reg may not support QImode moves, so use SImode.
6297 If foo is in memory due to spilling a pseudo reg, this is safe,
6298 because the QImode value is in the least significant part of a
6299 slot big enough for a SImode. If foo is some other sort of
6300 memory reference, then it is impossible to reload this case,
6301 so previous passes had better make sure this never happens.
6303 Then consider a one-word union which has SImode and one of its
6304 members is a float, being fetched as (SUBREG:SF union:SI).
6305 We must fetch that as SFmode because we could be loading into
6306 a float-only register. In this case OLD's mode is correct.
6308 Consider an immediate integer: it has VOIDmode. Here we need
6309 to get a mode from something else.
6311 In some cases, there is a fourth mode, the operand's
6312 containing mode. If the insn specifies a containing mode for
6313 this operand, it overrides all others.
6315 I am not sure whether the algorithm here is always right,
6316 but it does the right things in those cases. */
6318 mode = GET_MODE (old);
6319 if (mode == VOIDmode)
6322 /* If we need a secondary register for this operation, see if
6323 the value is already in a register in that class. Don't
6324 do this if the secondary register will be used as a scratch
6327 if (rl->secondary_in_reload >= 0
6328 && rl->secondary_in_icode == CODE_FOR_nothing
6331 = find_equiv_reg (old, insn,
6332 rld[rl->secondary_in_reload].class,
6335 /* If reloading from memory, see if there is a register
6336 that already holds the same value. If so, reload from there.
6337 We can pass 0 as the reload_reg_p argument because
6338 any other reload has either already been emitted,
6339 in which case find_equiv_reg will see the reload-insn,
6340 or has yet to be emitted, in which case it doesn't matter
6341 because we will use this equiv reg right away. */
6343 if (oldequiv == 0 && optimize
6346 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6347 && reg_renumber[REGNO (old)] < 0)))
6348 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6352 unsigned int regno = true_regnum (oldequiv);
6354 /* Don't use OLDEQUIV if any other reload changes it at an
6355 earlier stage of this insn or at this stage. */
6356 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6357 rl->in, const0_rtx, j, 0))
6360 /* If it is no cheaper to copy from OLDEQUIV into the
6361 reload register than it would be to move from memory,
6362 don't use it. Likewise, if we need a secondary register
6366 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6367 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6369 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6370 || (secondary_reload_class (1, rl->class, mode, oldequiv)
6372 #ifdef SECONDARY_MEMORY_NEEDED
6373 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6381 /* delete_output_reload is only invoked properly if old contains
6382 the original pseudo register. Since this is replaced with a
6383 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6384 find the pseudo in RELOAD_IN_REG. */
6386 && reload_override_in[j]
6387 && REG_P (rl->in_reg))
6394 else if (REG_P (oldequiv))
6395 oldequiv_reg = oldequiv;
6396 else if (GET_CODE (oldequiv) == SUBREG)
6397 oldequiv_reg = SUBREG_REG (oldequiv);
6399 /* If we are reloading from a register that was recently stored in
6400 with an output-reload, see if we can prove there was
6401 actually no need to store the old value in it. */
6403 if (optimize && REG_P (oldequiv)
6404 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6405 && spill_reg_store[REGNO (oldequiv)]
6407 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6408 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6410 delete_output_reload (insn, j, REGNO (oldequiv));
6412 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6413 then load RELOADREG from OLDEQUIV. Note that we cannot use
6414 gen_lowpart_common since it can do the wrong thing when
6415 RELOADREG has a multi-word mode. Note that RELOADREG
6416 must always be a REG here. */
6418 if (GET_MODE (reloadreg) != mode)
6419 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6420 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6421 oldequiv = SUBREG_REG (oldequiv);
6422 if (GET_MODE (oldequiv) != VOIDmode
6423 && mode != GET_MODE (oldequiv))
6424 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6426 /* Switch to the right place to emit the reload insns. */
6427 switch (rl->when_needed)
6430 where = &other_input_reload_insns;
6432 case RELOAD_FOR_INPUT:
6433 where = &input_reload_insns[rl->opnum];
6435 case RELOAD_FOR_INPUT_ADDRESS:
6436 where = &input_address_reload_insns[rl->opnum];
6438 case RELOAD_FOR_INPADDR_ADDRESS:
6439 where = &inpaddr_address_reload_insns[rl->opnum];
6441 case RELOAD_FOR_OUTPUT_ADDRESS:
6442 where = &output_address_reload_insns[rl->opnum];
6444 case RELOAD_FOR_OUTADDR_ADDRESS:
6445 where = &outaddr_address_reload_insns[rl->opnum];
6447 case RELOAD_FOR_OPERAND_ADDRESS:
6448 where = &operand_reload_insns;
6450 case RELOAD_FOR_OPADDR_ADDR:
6451 where = &other_operand_reload_insns;
6453 case RELOAD_FOR_OTHER_ADDRESS:
6454 where = &other_input_address_reload_insns;
6460 push_to_sequence (*where);
6462 /* Auto-increment addresses must be reloaded in a special way. */
6463 if (rl->out && ! rl->out_reg)
6465 /* We are not going to bother supporting the case where a
6466 incremented register can't be copied directly from
6467 OLDEQUIV since this seems highly unlikely. */
6468 gcc_assert (rl->secondary_in_reload < 0);
6470 if (reload_inherited[j])
6471 oldequiv = reloadreg;
6473 old = XEXP (rl->in_reg, 0);
6475 if (optimize && REG_P (oldequiv)
6476 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6477 && spill_reg_store[REGNO (oldequiv)]
6479 && (dead_or_set_p (insn,
6480 spill_reg_stored_to[REGNO (oldequiv)])
6481 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6483 delete_output_reload (insn, j, REGNO (oldequiv));
6485 /* Prevent normal processing of this reload. */
6487 /* Output a special code sequence for this case. */
6488 new_spill_reg_store[REGNO (reloadreg)]
6489 = inc_for_reload (reloadreg, oldequiv, rl->out,
6493 /* If we are reloading a pseudo-register that was set by the previous
6494 insn, see if we can get rid of that pseudo-register entirely
6495 by redirecting the previous insn into our reload register. */
6497 else if (optimize && REG_P (old)
6498 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6499 && dead_or_set_p (insn, old)
6500 /* This is unsafe if some other reload
6501 uses the same reg first. */
6502 && ! conflicts_with_override (reloadreg)
6503 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6504 rl->when_needed, old, rl->out, j, 0))
6506 rtx temp = PREV_INSN (insn);
6507 while (temp && NOTE_P (temp))
6508 temp = PREV_INSN (temp);
6510 && NONJUMP_INSN_P (temp)
6511 && GET_CODE (PATTERN (temp)) == SET
6512 && SET_DEST (PATTERN (temp)) == old
6513 /* Make sure we can access insn_operand_constraint. */
6514 && asm_noperands (PATTERN (temp)) < 0
6515 /* This is unsafe if operand occurs more than once in current
6516 insn. Perhaps some occurrences aren't reloaded. */
6517 && count_occurrences (PATTERN (insn), old, 0) == 1)
6519 rtx old = SET_DEST (PATTERN (temp));
6520 /* Store into the reload register instead of the pseudo. */
6521 SET_DEST (PATTERN (temp)) = reloadreg;
6523 /* Verify that resulting insn is valid. */
6524 extract_insn (temp);
6525 if (constrain_operands (1))
6527 /* If the previous insn is an output reload, the source is
6528 a reload register, and its spill_reg_store entry will
6529 contain the previous destination. This is now
6531 if (REG_P (SET_SRC (PATTERN (temp)))
6532 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6534 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6535 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6538 /* If these are the only uses of the pseudo reg,
6539 pretend for GDB it lives in the reload reg we used. */
6540 if (REG_N_DEATHS (REGNO (old)) == 1
6541 && REG_N_SETS (REGNO (old)) == 1)
6543 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6544 alter_reg (REGNO (old), -1);
6550 SET_DEST (PATTERN (temp)) = old;
6555 /* We can't do that, so output an insn to load RELOADREG. */
6557 /* If we have a secondary reload, pick up the secondary register
6558 and icode, if any. If OLDEQUIV and OLD are different or
6559 if this is an in-out reload, recompute whether or not we
6560 still need a secondary register and what the icode should
6561 be. If we still need a secondary register and the class or
6562 icode is different, go back to reloading from OLD if using
6563 OLDEQUIV means that we got the wrong type of register. We
6564 cannot have different class or icode due to an in-out reload
6565 because we don't make such reloads when both the input and
6566 output need secondary reload registers. */
6568 if (! special && rl->secondary_in_reload >= 0)
6570 rtx second_reload_reg = 0;
6571 rtx third_reload_reg = 0;
6572 int secondary_reload = rl->secondary_in_reload;
6573 rtx real_oldequiv = oldequiv;
6576 enum insn_code icode;
6577 enum insn_code tertiary_icode = CODE_FOR_nothing;
6579 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6580 and similarly for OLD.
6581 See comments in get_secondary_reload in reload.c. */
6582 /* If it is a pseudo that cannot be replaced with its
6583 equivalent MEM, we must fall back to reload_in, which
6584 will have all the necessary substitutions registered.
6585 Likewise for a pseudo that can't be replaced with its
6586 equivalent constant.
6588 Take extra care for subregs of such pseudos. Note that
6589 we cannot use reg_equiv_mem in this case because it is
6590 not in the right mode. */
6593 if (GET_CODE (tmp) == SUBREG)
6594 tmp = SUBREG_REG (tmp);
6596 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6597 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6598 || reg_equiv_constant[REGNO (tmp)] != 0))
6600 if (! reg_equiv_mem[REGNO (tmp)]
6601 || num_not_at_initial_offset
6602 || GET_CODE (oldequiv) == SUBREG)
6603 real_oldequiv = rl->in;
6605 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6609 if (GET_CODE (tmp) == SUBREG)
6610 tmp = SUBREG_REG (tmp);
6612 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6613 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6614 || reg_equiv_constant[REGNO (tmp)] != 0))
6616 if (! reg_equiv_mem[REGNO (tmp)]
6617 || num_not_at_initial_offset
6618 || GET_CODE (old) == SUBREG)
6621 real_old = reg_equiv_mem[REGNO (tmp)];
6624 second_reload_reg = rld[secondary_reload].reg_rtx;
6625 if (rld[secondary_reload].secondary_in_reload >= 0)
6627 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
6629 third_reload_reg = rld[tertiary_reload].reg_rtx;
6630 tertiary_icode = rld[secondary_reload].secondary_in_icode;
6631 /* We'd have to add more code for quartary reloads. */
6632 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
6634 icode = rl->secondary_in_icode;
6636 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6637 || (rl->in != 0 && rl->out != 0))
6639 secondary_reload_info sri, sri2;
6640 enum reg_class new_class, new_t_class;
6642 sri.icode = CODE_FOR_nothing;
6643 sri.prev_sri = NULL;
6644 new_class = targetm.secondary_reload (1, real_oldequiv, rl->class,
6647 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
6648 second_reload_reg = 0;
6649 else if (new_class == NO_REGS)
6651 if (reload_adjust_reg_for_icode (&second_reload_reg,
6652 third_reload_reg, sri.icode))
6653 icode = sri.icode, third_reload_reg = 0;
6655 oldequiv = old, real_oldequiv = real_old;
6657 else if (sri.icode != CODE_FOR_nothing)
6658 /* We currently lack a way to express this in reloads. */
6662 sri2.icode = CODE_FOR_nothing;
6663 sri2.prev_sri = &sri;
6664 new_t_class = targetm.secondary_reload (1, real_oldequiv,
6665 new_class, mode, &sri);
6666 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
6668 if (reload_adjust_reg_for_temp (&second_reload_reg,
6671 third_reload_reg = 0, tertiary_icode = sri2.icode;
6673 oldequiv = old, real_oldequiv = real_old;
6675 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
6677 rtx intermediate = second_reload_reg;
6679 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6681 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
6684 second_reload_reg = intermediate;
6685 tertiary_icode = sri2.icode;
6688 oldequiv = old, real_oldequiv = real_old;
6690 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
6692 rtx intermediate = second_reload_reg;
6694 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6696 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
6699 second_reload_reg = intermediate;
6700 tertiary_icode = sri2.icode;
6703 oldequiv = old, real_oldequiv = real_old;
6706 /* This could be handled more intelligently too. */
6707 oldequiv = old, real_oldequiv = real_old;
6711 /* If we still need a secondary reload register, check
6712 to see if it is being used as a scratch or intermediate
6713 register and generate code appropriately. If we need
6714 a scratch register, use REAL_OLDEQUIV since the form of
6715 the insn may depend on the actual address if it is
6718 if (second_reload_reg)
6720 if (icode != CODE_FOR_nothing)
6722 /* We'd have to add extra code to handle this case. */
6723 gcc_assert (!third_reload_reg);
6725 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6726 second_reload_reg));
6731 /* See if we need a scratch register to load the
6732 intermediate register (a tertiary reload). */
6733 if (tertiary_icode != CODE_FOR_nothing)
6735 emit_insn ((GEN_FCN (tertiary_icode)
6736 (second_reload_reg, real_oldequiv,
6737 third_reload_reg)));
6739 else if (third_reload_reg)
6741 gen_reload (third_reload_reg, real_oldequiv,
6744 gen_reload (second_reload_reg, third_reload_reg,
6749 gen_reload (second_reload_reg, real_oldequiv,
6753 oldequiv = second_reload_reg;
6758 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6760 rtx real_oldequiv = oldequiv;
6762 if ((REG_P (oldequiv)
6763 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6764 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6765 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6766 || (GET_CODE (oldequiv) == SUBREG
6767 && REG_P (SUBREG_REG (oldequiv))
6768 && (REGNO (SUBREG_REG (oldequiv))
6769 >= FIRST_PSEUDO_REGISTER)
6770 && ((reg_equiv_memory_loc
6771 [REGNO (SUBREG_REG (oldequiv))] != 0)
6772 || (reg_equiv_constant
6773 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6774 || (CONSTANT_P (oldequiv)
6775 && (PREFERRED_RELOAD_CLASS (oldequiv,
6776 REGNO_REG_CLASS (REGNO (reloadreg)))
6778 real_oldequiv = rl->in;
6779 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6783 if (flag_non_call_exceptions)
6784 copy_eh_notes (insn, get_insns ());
6786 /* End this sequence. */
6787 *where = get_insns ();
6790 /* Update reload_override_in so that delete_address_reloads_1
6791 can see the actual register usage. */
6793 reload_override_in[j] = oldequiv;
6796 /* Generate insns to for the output reload RL, which is for the insn described
6797 by CHAIN and has the number J. */
6799 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6802 rtx reloadreg = rl->reg_rtx;
6803 rtx insn = chain->insn;
6806 enum machine_mode mode = GET_MODE (old);
6809 if (rl->when_needed == RELOAD_OTHER)
6812 push_to_sequence (output_reload_insns[rl->opnum]);
6814 /* Determine the mode to reload in.
6815 See comments above (for input reloading). */
6817 if (mode == VOIDmode)
6819 /* VOIDmode should never happen for an output. */
6820 if (asm_noperands (PATTERN (insn)) < 0)
6821 /* It's the compiler's fault. */
6822 fatal_insn ("VOIDmode on an output", insn);
6823 error_for_asm (insn, "output operand is constant in %<asm%>");
6824 /* Prevent crash--use something we know is valid. */
6826 old = gen_rtx_REG (mode, REGNO (reloadreg));
6829 if (GET_MODE (reloadreg) != mode)
6830 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6832 /* If we need two reload regs, set RELOADREG to the intermediate
6833 one, since it will be stored into OLD. We might need a secondary
6834 register only for an input reload, so check again here. */
6836 if (rl->secondary_out_reload >= 0)
6839 int secondary_reload = rl->secondary_out_reload;
6840 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
6842 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
6843 && reg_equiv_mem[REGNO (old)] != 0)
6844 real_old = reg_equiv_mem[REGNO (old)];
6846 if (secondary_reload_class (0, rl->class, mode, real_old) != NO_REGS)
6848 rtx second_reloadreg = reloadreg;
6849 reloadreg = rld[secondary_reload].reg_rtx;
6851 /* See if RELOADREG is to be used as a scratch register
6852 or as an intermediate register. */
6853 if (rl->secondary_out_icode != CODE_FOR_nothing)
6855 /* We'd have to add extra code to handle this case. */
6856 gcc_assert (tertiary_reload < 0);
6858 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6859 (real_old, second_reloadreg, reloadreg)));
6864 /* See if we need both a scratch and intermediate reload
6867 enum insn_code tertiary_icode
6868 = rld[secondary_reload].secondary_out_icode;
6870 /* We'd have to add more code for quartary reloads. */
6871 gcc_assert (tertiary_reload < 0
6872 || rld[tertiary_reload].secondary_out_reload < 0);
6874 if (GET_MODE (reloadreg) != mode)
6875 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6877 if (tertiary_icode != CODE_FOR_nothing)
6879 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
6882 /* Copy primary reload reg to secondary reload reg.
6883 (Note that these have been swapped above, then
6884 secondary reload reg to OLD using our insn.) */
6886 /* If REAL_OLD is a paradoxical SUBREG, remove it
6887 and try to put the opposite SUBREG on
6889 if (GET_CODE (real_old) == SUBREG
6890 && (GET_MODE_SIZE (GET_MODE (real_old))
6891 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6892 && 0 != (tem = gen_lowpart_common
6893 (GET_MODE (SUBREG_REG (real_old)),
6895 real_old = SUBREG_REG (real_old), reloadreg = tem;
6897 gen_reload (reloadreg, second_reloadreg,
6898 rl->opnum, rl->when_needed);
6899 emit_insn ((GEN_FCN (tertiary_icode)
6900 (real_old, reloadreg, third_reloadreg)));
6906 /* Copy between the reload regs here and then to
6909 gen_reload (reloadreg, second_reloadreg,
6910 rl->opnum, rl->when_needed);
6911 if (tertiary_reload >= 0)
6913 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
6915 gen_reload (third_reloadreg, reloadreg,
6916 rl->opnum, rl->when_needed);
6917 reloadreg = third_reloadreg;
6924 /* Output the last reload insn. */
6929 /* Don't output the last reload if OLD is not the dest of
6930 INSN and is in the src and is clobbered by INSN. */
6931 if (! flag_expensive_optimizations
6933 || !(set = single_set (insn))
6934 || rtx_equal_p (old, SET_DEST (set))
6935 || !reg_mentioned_p (old, SET_SRC (set))
6936 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
6937 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
6938 gen_reload (old, reloadreg, rl->opnum,
6942 /* Look at all insns we emitted, just to be safe. */
6943 for (p = get_insns (); p; p = NEXT_INSN (p))
6946 rtx pat = PATTERN (p);
6948 /* If this output reload doesn't come from a spill reg,
6949 clear any memory of reloaded copies of the pseudo reg.
6950 If this output reload comes from a spill reg,
6951 reg_has_output_reload will make this do nothing. */
6952 note_stores (pat, forget_old_reloads_1, NULL);
6954 if (reg_mentioned_p (rl->reg_rtx, pat))
6956 rtx set = single_set (insn);
6957 if (reload_spill_index[j] < 0
6959 && SET_SRC (set) == rl->reg_rtx)
6961 int src = REGNO (SET_SRC (set));
6963 reload_spill_index[j] = src;
6964 SET_HARD_REG_BIT (reg_is_output_reload, src);
6965 if (find_regno_note (insn, REG_DEAD, src))
6966 SET_HARD_REG_BIT (reg_reloaded_died, src);
6968 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6970 int s = rl->secondary_out_reload;
6971 set = single_set (p);
6972 /* If this reload copies only to the secondary reload
6973 register, the secondary reload does the actual
6975 if (s >= 0 && set == NULL_RTX)
6976 /* We can't tell what function the secondary reload
6977 has and where the actual store to the pseudo is
6978 made; leave new_spill_reg_store alone. */
6981 && SET_SRC (set) == rl->reg_rtx
6982 && SET_DEST (set) == rld[s].reg_rtx)
6984 /* Usually the next instruction will be the
6985 secondary reload insn; if we can confirm
6986 that it is, setting new_spill_reg_store to
6987 that insn will allow an extra optimization. */
6988 rtx s_reg = rld[s].reg_rtx;
6989 rtx next = NEXT_INSN (p);
6990 rld[s].out = rl->out;
6991 rld[s].out_reg = rl->out_reg;
6992 set = single_set (next);
6993 if (set && SET_SRC (set) == s_reg
6994 && ! new_spill_reg_store[REGNO (s_reg)])
6996 SET_HARD_REG_BIT (reg_is_output_reload,
6998 new_spill_reg_store[REGNO (s_reg)] = next;
7002 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
7007 if (rl->when_needed == RELOAD_OTHER)
7009 emit_insn (other_output_reload_insns[rl->opnum]);
7010 other_output_reload_insns[rl->opnum] = get_insns ();
7013 output_reload_insns[rl->opnum] = get_insns ();
7015 if (flag_non_call_exceptions)
7016 copy_eh_notes (insn, get_insns ());
7021 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7022 and has the number J. */
7024 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7026 rtx insn = chain->insn;
7027 rtx old = (rl->in && MEM_P (rl->in)
7028 ? rl->in_reg : rl->in);
7031 /* AUTO_INC reloads need to be handled even if inherited. We got an
7032 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7033 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7034 && ! rtx_equal_p (rl->reg_rtx, old)
7035 && rl->reg_rtx != 0)
7036 emit_input_reload_insns (chain, rld + j, old, j);
7038 /* When inheriting a wider reload, we have a MEM in rl->in,
7039 e.g. inheriting a SImode output reload for
7040 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7041 if (optimize && reload_inherited[j] && rl->in
7043 && MEM_P (rl->in_reg)
7044 && reload_spill_index[j] >= 0
7045 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7046 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7048 /* If we are reloading a register that was recently stored in with an
7049 output-reload, see if we can prove there was
7050 actually no need to store the old value in it. */
7053 /* Only attempt this for input reloads; for RELOAD_OTHER we miss
7054 that there may be multiple uses of the previous output reload.
7055 Restricting to RELOAD_FOR_INPUT is mostly paranoia. */
7056 && rl->when_needed == RELOAD_FOR_INPUT
7057 && (reload_inherited[j] || reload_override_in[j])
7059 && REG_P (rl->reg_rtx)
7060 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
7062 /* There doesn't seem to be any reason to restrict this to pseudos
7063 and doing so loses in the case where we are copying from a
7064 register of the wrong class. */
7065 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
7066 >= FIRST_PSEUDO_REGISTER)
7068 /* The insn might have already some references to stackslots
7069 replaced by MEMs, while reload_out_reg still names the
7071 && (dead_or_set_p (insn,
7072 spill_reg_stored_to[REGNO (rl->reg_rtx)])
7073 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
7075 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
7078 /* Do output reloading for reload RL, which is for the insn described by
7079 CHAIN and has the number J.
7080 ??? At some point we need to support handling output reloads of
7081 JUMP_INSNs or insns that set cc0. */
7083 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7086 rtx insn = chain->insn;
7087 /* If this is an output reload that stores something that is
7088 not loaded in this same reload, see if we can eliminate a previous
7090 rtx pseudo = rl->out_reg;
7095 && ! rtx_equal_p (rl->in_reg, pseudo)
7096 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7097 && reg_last_reload_reg[REGNO (pseudo)])
7099 int pseudo_no = REGNO (pseudo);
7100 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7102 /* We don't need to test full validity of last_regno for
7103 inherit here; we only want to know if the store actually
7104 matches the pseudo. */
7105 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7106 && reg_reloaded_contents[last_regno] == pseudo_no
7107 && spill_reg_store[last_regno]
7108 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7109 delete_output_reload (insn, j, last_regno);
7114 || rl->reg_rtx == old
7115 || rl->reg_rtx == 0)
7118 /* An output operand that dies right away does need a reload,
7119 but need not be copied from it. Show the new location in the
7121 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7122 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7124 XEXP (note, 0) = rl->reg_rtx;
7127 /* Likewise for a SUBREG of an operand that dies. */
7128 else if (GET_CODE (old) == SUBREG
7129 && REG_P (SUBREG_REG (old))
7130 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7133 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
7137 else if (GET_CODE (old) == SCRATCH)
7138 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7139 but we don't want to make an output reload. */
7142 /* If is a JUMP_INSN, we can't support output reloads yet. */
7143 gcc_assert (!JUMP_P (insn));
7145 emit_output_reload_insns (chain, rld + j, j);
7148 /* Reload number R reloads from or to a group of hard registers starting at
7149 register REGNO. Return true if it can be treated for inheritance purposes
7150 like a group of reloads, each one reloading a single hard register.
7151 The caller has already checked that the spill register and REGNO use
7152 the same number of registers to store the reload value. */
7155 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
7157 #ifdef CANNOT_CHANGE_MODE_CLASS
7158 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
7159 GET_MODE (rld[r].reg_rtx),
7160 reg_raw_mode[reload_spill_index[r]])
7161 && !REG_CANNOT_CHANGE_MODE_P (regno,
7162 GET_MODE (rld[r].reg_rtx),
7163 reg_raw_mode[regno]));
7169 /* Output insns to reload values in and out of the chosen reload regs. */
7172 emit_reload_insns (struct insn_chain *chain)
7174 rtx insn = chain->insn;
7178 CLEAR_HARD_REG_SET (reg_reloaded_died);
7180 for (j = 0; j < reload_n_operands; j++)
7181 input_reload_insns[j] = input_address_reload_insns[j]
7182 = inpaddr_address_reload_insns[j]
7183 = output_reload_insns[j] = output_address_reload_insns[j]
7184 = outaddr_address_reload_insns[j]
7185 = other_output_reload_insns[j] = 0;
7186 other_input_address_reload_insns = 0;
7187 other_input_reload_insns = 0;
7188 operand_reload_insns = 0;
7189 other_operand_reload_insns = 0;
7191 /* Dump reloads into the dump file. */
7194 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7195 debug_reload_to_stream (dump_file);
7198 /* Now output the instructions to copy the data into and out of the
7199 reload registers. Do these in the order that the reloads were reported,
7200 since reloads of base and index registers precede reloads of operands
7201 and the operands may need the base and index registers reloaded. */
7203 for (j = 0; j < n_reloads; j++)
7206 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7207 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7209 do_input_reload (chain, rld + j, j);
7210 do_output_reload (chain, rld + j, j);
7213 /* Now write all the insns we made for reloads in the order expected by
7214 the allocation functions. Prior to the insn being reloaded, we write
7215 the following reloads:
7217 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7219 RELOAD_OTHER reloads.
7221 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7222 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7223 RELOAD_FOR_INPUT reload for the operand.
7225 RELOAD_FOR_OPADDR_ADDRS reloads.
7227 RELOAD_FOR_OPERAND_ADDRESS reloads.
7229 After the insn being reloaded, we write the following:
7231 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7232 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7233 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7234 reloads for the operand. The RELOAD_OTHER output reloads are
7235 output in descending order by reload number. */
7237 emit_insn_before (other_input_address_reload_insns, insn);
7238 emit_insn_before (other_input_reload_insns, insn);
7240 for (j = 0; j < reload_n_operands; j++)
7242 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7243 emit_insn_before (input_address_reload_insns[j], insn);
7244 emit_insn_before (input_reload_insns[j], insn);
7247 emit_insn_before (other_operand_reload_insns, insn);
7248 emit_insn_before (operand_reload_insns, insn);
7250 for (j = 0; j < reload_n_operands; j++)
7252 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7253 x = emit_insn_after (output_address_reload_insns[j], x);
7254 x = emit_insn_after (output_reload_insns[j], x);
7255 emit_insn_after (other_output_reload_insns[j], x);
7258 /* For all the spill regs newly reloaded in this instruction,
7259 record what they were reloaded from, so subsequent instructions
7260 can inherit the reloads.
7262 Update spill_reg_store for the reloads of this insn.
7263 Copy the elements that were updated in the loop above. */
7265 for (j = 0; j < n_reloads; j++)
7267 int r = reload_order[j];
7268 int i = reload_spill_index[r];
7270 /* If this is a non-inherited input reload from a pseudo, we must
7271 clear any memory of a previous store to the same pseudo. Only do
7272 something if there will not be an output reload for the pseudo
7274 if (rld[r].in_reg != 0
7275 && ! (reload_inherited[r] || reload_override_in[r]))
7277 rtx reg = rld[r].in_reg;
7279 if (GET_CODE (reg) == SUBREG)
7280 reg = SUBREG_REG (reg);
7283 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7284 && ! reg_has_output_reload[REGNO (reg)])
7286 int nregno = REGNO (reg);
7288 if (reg_last_reload_reg[nregno])
7290 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7292 if (reg_reloaded_contents[last_regno] == nregno)
7293 spill_reg_store[last_regno] = 0;
7298 /* I is nonneg if this reload used a register.
7299 If rld[r].reg_rtx is 0, this is an optional reload
7300 that we opted to ignore. */
7302 if (i >= 0 && rld[r].reg_rtx != 0)
7304 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7306 int part_reaches_end = 0;
7307 int all_reaches_end = 1;
7309 /* For a multi register reload, we need to check if all or part
7310 of the value lives to the end. */
7311 for (k = 0; k < nr; k++)
7313 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7314 rld[r].when_needed))
7315 part_reaches_end = 1;
7317 all_reaches_end = 0;
7320 /* Ignore reloads that don't reach the end of the insn in
7322 if (all_reaches_end)
7324 /* First, clear out memory of what used to be in this spill reg.
7325 If consecutive registers are used, clear them all. */
7327 for (k = 0; k < nr; k++)
7329 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7330 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7333 /* Maybe the spill reg contains a copy of reload_out. */
7335 && (REG_P (rld[r].out)
7339 || REG_P (rld[r].out_reg)))
7341 rtx out = (REG_P (rld[r].out)
7345 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7346 int nregno = REGNO (out);
7347 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7348 : hard_regno_nregs[nregno]
7349 [GET_MODE (rld[r].reg_rtx)]);
7352 spill_reg_store[i] = new_spill_reg_store[i];
7353 spill_reg_stored_to[i] = out;
7354 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7356 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7358 && inherit_piecemeal_p (r, nregno));
7360 /* If NREGNO is a hard register, it may occupy more than
7361 one register. If it does, say what is in the
7362 rest of the registers assuming that both registers
7363 agree on how many words the object takes. If not,
7364 invalidate the subsequent registers. */
7366 if (nregno < FIRST_PSEUDO_REGISTER)
7367 for (k = 1; k < nnr; k++)
7368 reg_last_reload_reg[nregno + k]
7370 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7373 /* Now do the inverse operation. */
7374 for (k = 0; k < nr; k++)
7376 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7377 reg_reloaded_contents[i + k]
7378 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7381 reg_reloaded_insn[i + k] = insn;
7382 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7383 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7384 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7388 /* Maybe the spill reg contains a copy of reload_in. Only do
7389 something if there will not be an output reload for
7390 the register being reloaded. */
7391 else if (rld[r].out_reg == 0
7393 && ((REG_P (rld[r].in)
7394 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7395 && ! reg_has_output_reload[REGNO (rld[r].in)])
7396 || (REG_P (rld[r].in_reg)
7397 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7398 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7405 if (REG_P (rld[r].in)
7406 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7408 else if (REG_P (rld[r].in_reg))
7411 in = XEXP (rld[r].in_reg, 0);
7412 nregno = REGNO (in);
7414 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7415 : hard_regno_nregs[nregno]
7416 [GET_MODE (rld[r].reg_rtx)]);
7418 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7420 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7422 && inherit_piecemeal_p (r, nregno));
7424 if (nregno < FIRST_PSEUDO_REGISTER)
7425 for (k = 1; k < nnr; k++)
7426 reg_last_reload_reg[nregno + k]
7428 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7431 /* Unless we inherited this reload, show we haven't
7432 recently done a store.
7433 Previous stores of inherited auto_inc expressions
7434 also have to be discarded. */
7435 if (! reload_inherited[r]
7436 || (rld[r].out && ! rld[r].out_reg))
7437 spill_reg_store[i] = 0;
7439 for (k = 0; k < nr; k++)
7441 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7442 reg_reloaded_contents[i + k]
7443 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7446 reg_reloaded_insn[i + k] = insn;
7447 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7448 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7449 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7454 /* However, if part of the reload reaches the end, then we must
7455 invalidate the old info for the part that survives to the end. */
7456 else if (part_reaches_end)
7458 for (k = 0; k < nr; k++)
7459 if (reload_reg_reaches_end_p (i + k,
7461 rld[r].when_needed))
7462 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7466 /* The following if-statement was #if 0'd in 1.34 (or before...).
7467 It's reenabled in 1.35 because supposedly nothing else
7468 deals with this problem. */
7470 /* If a register gets output-reloaded from a non-spill register,
7471 that invalidates any previous reloaded copy of it.
7472 But forget_old_reloads_1 won't get to see it, because
7473 it thinks only about the original insn. So invalidate it here. */
7474 if (i < 0 && rld[r].out != 0
7475 && (REG_P (rld[r].out)
7476 || (MEM_P (rld[r].out)
7477 && REG_P (rld[r].out_reg))))
7479 rtx out = (REG_P (rld[r].out)
7480 ? rld[r].out : rld[r].out_reg);
7481 int nregno = REGNO (out);
7482 if (nregno >= FIRST_PSEUDO_REGISTER)
7484 rtx src_reg, store_insn = NULL_RTX;
7486 reg_last_reload_reg[nregno] = 0;
7488 /* If we can find a hard register that is stored, record
7489 the storing insn so that we may delete this insn with
7490 delete_output_reload. */
7491 src_reg = rld[r].reg_rtx;
7493 /* If this is an optional reload, try to find the source reg
7494 from an input reload. */
7497 rtx set = single_set (insn);
7498 if (set && SET_DEST (set) == rld[r].out)
7502 src_reg = SET_SRC (set);
7504 for (k = 0; k < n_reloads; k++)
7506 if (rld[k].in == src_reg)
7508 src_reg = rld[k].reg_rtx;
7515 store_insn = new_spill_reg_store[REGNO (src_reg)];
7516 if (src_reg && REG_P (src_reg)
7517 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7519 int src_regno = REGNO (src_reg);
7520 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7521 /* The place where to find a death note varies with
7522 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7523 necessarily checked exactly in the code that moves
7524 notes, so just check both locations. */
7525 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7526 if (! note && store_insn)
7527 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7530 spill_reg_store[src_regno + nr] = store_insn;
7531 spill_reg_stored_to[src_regno + nr] = out;
7532 reg_reloaded_contents[src_regno + nr] = nregno;
7533 reg_reloaded_insn[src_regno + nr] = store_insn;
7534 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7535 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7536 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7537 GET_MODE (src_reg)))
7538 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7540 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7542 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7544 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7546 reg_last_reload_reg[nregno] = src_reg;
7547 /* We have to set reg_has_output_reload here, or else
7548 forget_old_reloads_1 will clear reg_last_reload_reg
7550 reg_has_output_reload[nregno] = 1;
7555 int num_regs = hard_regno_nregs[nregno][GET_MODE (rld[r].out)];
7557 while (num_regs-- > 0)
7558 reg_last_reload_reg[nregno + num_regs] = 0;
7562 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7565 /* Go through the motions to emit INSN and test if it is strictly valid.
7566 Return the emitted insn if valid, else return NULL. */
7569 emit_insn_if_valid_for_reload (rtx insn)
7571 rtx last = get_last_insn ();
7574 insn = emit_insn (insn);
7575 code = recog_memoized (insn);
7579 extract_insn (insn);
7580 /* We want constrain operands to treat this insn strictly in its
7581 validity determination, i.e., the way it would after reload has
7583 if (constrain_operands (1))
7587 delete_insns_since (last);
7591 /* Emit code to perform a reload from IN (which may be a reload register) to
7592 OUT (which may also be a reload register). IN or OUT is from operand
7593 OPNUM with reload type TYPE.
7595 Returns first insn emitted. */
7598 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7600 rtx last = get_last_insn ();
7603 /* If IN is a paradoxical SUBREG, remove it and try to put the
7604 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7605 if (GET_CODE (in) == SUBREG
7606 && (GET_MODE_SIZE (GET_MODE (in))
7607 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7608 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7609 in = SUBREG_REG (in), out = tem;
7610 else if (GET_CODE (out) == SUBREG
7611 && (GET_MODE_SIZE (GET_MODE (out))
7612 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7613 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7614 out = SUBREG_REG (out), in = tem;
7616 /* How to do this reload can get quite tricky. Normally, we are being
7617 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7618 register that didn't get a hard register. In that case we can just
7619 call emit_move_insn.
7621 We can also be asked to reload a PLUS that adds a register or a MEM to
7622 another register, constant or MEM. This can occur during frame pointer
7623 elimination and while reloading addresses. This case is handled by
7624 trying to emit a single insn to perform the add. If it is not valid,
7625 we use a two insn sequence.
7627 Or we can be asked to reload an unary operand that was a fragment of
7628 an addressing mode, into a register. If it isn't recognized as-is,
7629 we try making the unop operand and the reload-register the same:
7630 (set reg:X (unop:X expr:Y))
7631 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
7633 Finally, we could be called to handle an 'o' constraint by putting
7634 an address into a register. In that case, we first try to do this
7635 with a named pattern of "reload_load_address". If no such pattern
7636 exists, we just emit a SET insn and hope for the best (it will normally
7637 be valid on machines that use 'o').
7639 This entire process is made complex because reload will never
7640 process the insns we generate here and so we must ensure that
7641 they will fit their constraints and also by the fact that parts of
7642 IN might be being reloaded separately and replaced with spill registers.
7643 Because of this, we are, in some sense, just guessing the right approach
7644 here. The one listed above seems to work.
7646 ??? At some point, this whole thing needs to be rethought. */
7648 if (GET_CODE (in) == PLUS
7649 && (REG_P (XEXP (in, 0))
7650 || GET_CODE (XEXP (in, 0)) == SUBREG
7651 || MEM_P (XEXP (in, 0)))
7652 && (REG_P (XEXP (in, 1))
7653 || GET_CODE (XEXP (in, 1)) == SUBREG
7654 || CONSTANT_P (XEXP (in, 1))
7655 || MEM_P (XEXP (in, 1))))
7657 /* We need to compute the sum of a register or a MEM and another
7658 register, constant, or MEM, and put it into the reload
7659 register. The best possible way of doing this is if the machine
7660 has a three-operand ADD insn that accepts the required operands.
7662 The simplest approach is to try to generate such an insn and see if it
7663 is recognized and matches its constraints. If so, it can be used.
7665 It might be better not to actually emit the insn unless it is valid,
7666 but we need to pass the insn as an operand to `recog' and
7667 `extract_insn' and it is simpler to emit and then delete the insn if
7668 not valid than to dummy things up. */
7670 rtx op0, op1, tem, insn;
7673 op0 = find_replacement (&XEXP (in, 0));
7674 op1 = find_replacement (&XEXP (in, 1));
7676 /* Since constraint checking is strict, commutativity won't be
7677 checked, so we need to do that here to avoid spurious failure
7678 if the add instruction is two-address and the second operand
7679 of the add is the same as the reload reg, which is frequently
7680 the case. If the insn would be A = B + A, rearrange it so
7681 it will be A = A + B as constrain_operands expects. */
7683 if (REG_P (XEXP (in, 1))
7684 && REGNO (out) == REGNO (XEXP (in, 1)))
7685 tem = op0, op0 = op1, op1 = tem;
7687 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7688 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7690 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7694 /* If that failed, we must use a conservative two-insn sequence.
7696 Use a move to copy one operand into the reload register. Prefer
7697 to reload a constant, MEM or pseudo since the move patterns can
7698 handle an arbitrary operand. If OP1 is not a constant, MEM or
7699 pseudo and OP1 is not a valid operand for an add instruction, then
7702 After reloading one of the operands into the reload register, add
7703 the reload register to the output register.
7705 If there is another way to do this for a specific machine, a
7706 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7709 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7711 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7713 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7714 || (code != CODE_FOR_nothing
7715 && ! ((*insn_data[code].operand[2].predicate)
7716 (op1, insn_data[code].operand[2].mode))))
7717 tem = op0, op0 = op1, op1 = tem;
7719 gen_reload (out, op0, opnum, type);
7721 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7722 This fixes a problem on the 32K where the stack pointer cannot
7723 be used as an operand of an add insn. */
7725 if (rtx_equal_p (op0, op1))
7728 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
7731 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7733 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7737 /* If that failed, copy the address register to the reload register.
7738 Then add the constant to the reload register. */
7740 gen_reload (out, op1, opnum, type);
7741 insn = emit_insn (gen_add2_insn (out, op0));
7742 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7745 #ifdef SECONDARY_MEMORY_NEEDED
7746 /* If we need a memory location to do the move, do it that way. */
7747 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7748 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7749 && (REG_P (out) || GET_CODE (out) == SUBREG)
7750 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7751 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7752 REGNO_REG_CLASS (reg_or_subregno (out)),
7755 /* Get the memory to use and rewrite both registers to its mode. */
7756 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7758 if (GET_MODE (loc) != GET_MODE (out))
7759 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7761 if (GET_MODE (loc) != GET_MODE (in))
7762 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7764 gen_reload (loc, in, opnum, type);
7765 gen_reload (out, loc, opnum, type);
7768 else if (REG_P (out) && UNARY_P (in))
7775 /* First, try a plain SET. */
7776 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7780 /* If that failed, move the inner operand to the reload
7781 register, and try the same unop with the inner expression
7782 replaced with the reload register. */
7785 if (GET_MODE (op1) != GET_MODE (out))
7786 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
7790 gen_reload (out_moded, op1, opnum, type);
7793 = gen_rtx_SET (VOIDmode, out,
7794 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
7796 insn = emit_insn_if_valid_for_reload (insn);
7800 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7804 fatal_insn ("Failure trying to reload:", set);
7806 /* If IN is a simple operand, use gen_move_insn. */
7807 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
7808 emit_insn (gen_move_insn (out, in));
7810 #ifdef HAVE_reload_load_address
7811 else if (HAVE_reload_load_address)
7812 emit_insn (gen_reload_load_address (out, in));
7815 /* Otherwise, just write (set OUT IN) and hope for the best. */
7817 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7819 /* Return the first insn emitted.
7820 We can not just return get_last_insn, because there may have
7821 been multiple instructions emitted. Also note that gen_move_insn may
7822 emit more than one insn itself, so we can not assume that there is one
7823 insn emitted per emit_insn_before call. */
7825 return last ? NEXT_INSN (last) : get_insns ();
7828 /* Delete a previously made output-reload whose result we now believe
7829 is not needed. First we double-check.
7831 INSN is the insn now being processed.
7832 LAST_RELOAD_REG is the hard register number for which we want to delete
7833 the last output reload.
7834 J is the reload-number that originally used REG. The caller has made
7835 certain that reload J doesn't use REG any longer for input. */
7838 delete_output_reload (rtx insn, int j, int last_reload_reg)
7840 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7841 rtx reg = spill_reg_stored_to[last_reload_reg];
7844 int n_inherited = 0;
7848 /* It is possible that this reload has been only used to set another reload
7849 we eliminated earlier and thus deleted this instruction too. */
7850 if (INSN_DELETED_P (output_reload_insn))
7853 /* Get the raw pseudo-register referred to. */
7855 while (GET_CODE (reg) == SUBREG)
7856 reg = SUBREG_REG (reg);
7857 substed = reg_equiv_memory_loc[REGNO (reg)];
7859 /* This is unsafe if the operand occurs more often in the current
7860 insn than it is inherited. */
7861 for (k = n_reloads - 1; k >= 0; k--)
7863 rtx reg2 = rld[k].in;
7866 if (MEM_P (reg2) || reload_override_in[k])
7867 reg2 = rld[k].in_reg;
7869 if (rld[k].out && ! rld[k].out_reg)
7870 reg2 = XEXP (rld[k].in_reg, 0);
7872 while (GET_CODE (reg2) == SUBREG)
7873 reg2 = SUBREG_REG (reg2);
7874 if (rtx_equal_p (reg2, reg))
7876 if (reload_inherited[k] || reload_override_in[k] || k == j)
7879 reg2 = rld[k].out_reg;
7882 while (GET_CODE (reg2) == SUBREG)
7883 reg2 = XEXP (reg2, 0);
7884 if (rtx_equal_p (reg2, reg))
7891 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7893 n_occurrences += count_occurrences (PATTERN (insn),
7894 eliminate_regs (substed, 0,
7896 if (n_occurrences > n_inherited)
7899 /* If the pseudo-reg we are reloading is no longer referenced
7900 anywhere between the store into it and here,
7901 and we're within the same basic block, then the value can only
7902 pass through the reload reg and end up here.
7903 Otherwise, give up--return. */
7904 for (i1 = NEXT_INSN (output_reload_insn);
7905 i1 != insn; i1 = NEXT_INSN (i1))
7907 if (NOTE_INSN_BASIC_BLOCK_P (i1))
7909 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
7910 && reg_mentioned_p (reg, PATTERN (i1)))
7912 /* If this is USE in front of INSN, we only have to check that
7913 there are no more references than accounted for by inheritance. */
7914 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
7916 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7917 i1 = NEXT_INSN (i1);
7919 if (n_occurrences <= n_inherited && i1 == insn)
7925 /* We will be deleting the insn. Remove the spill reg information. */
7926 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
7928 spill_reg_store[last_reload_reg + k] = 0;
7929 spill_reg_stored_to[last_reload_reg + k] = 0;
7932 /* The caller has already checked that REG dies or is set in INSN.
7933 It has also checked that we are optimizing, and thus some
7934 inaccuracies in the debugging information are acceptable.
7935 So we could just delete output_reload_insn. But in some cases
7936 we can improve the debugging information without sacrificing
7937 optimization - maybe even improving the code: See if the pseudo
7938 reg has been completely replaced with reload regs. If so, delete
7939 the store insn and forget we had a stack slot for the pseudo. */
7940 if (rld[j].out != rld[j].in
7941 && REG_N_DEATHS (REGNO (reg)) == 1
7942 && REG_N_SETS (REGNO (reg)) == 1
7943 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7944 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7948 /* We know that it was used only between here and the beginning of
7949 the current basic block. (We also know that the last use before
7950 INSN was the output reload we are thinking of deleting, but never
7951 mind that.) Search that range; see if any ref remains. */
7952 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7954 rtx set = single_set (i2);
7956 /* Uses which just store in the pseudo don't count,
7957 since if they are the only uses, they are dead. */
7958 if (set != 0 && SET_DEST (set) == reg)
7963 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
7964 && reg_mentioned_p (reg, PATTERN (i2)))
7966 /* Some other ref remains; just delete the output reload we
7968 delete_address_reloads (output_reload_insn, insn);
7969 delete_insn (output_reload_insn);
7974 /* Delete the now-dead stores into this pseudo. Note that this
7975 loop also takes care of deleting output_reload_insn. */
7976 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7978 rtx set = single_set (i2);
7980 if (set != 0 && SET_DEST (set) == reg)
7982 delete_address_reloads (i2, insn);
7990 /* For the debugging info, say the pseudo lives in this reload reg. */
7991 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7992 alter_reg (REGNO (reg), -1);
7996 delete_address_reloads (output_reload_insn, insn);
7997 delete_insn (output_reload_insn);
8001 /* We are going to delete DEAD_INSN. Recursively delete loads of
8002 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8003 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8005 delete_address_reloads (rtx dead_insn, rtx current_insn)
8007 rtx set = single_set (dead_insn);
8008 rtx set2, dst, prev, next;
8011 rtx dst = SET_DEST (set);
8013 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8015 /* If we deleted the store from a reloaded post_{in,de}c expression,
8016 we can delete the matching adds. */
8017 prev = PREV_INSN (dead_insn);
8018 next = NEXT_INSN (dead_insn);
8019 if (! prev || ! next)
8021 set = single_set (next);
8022 set2 = single_set (prev);
8024 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8025 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8026 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8028 dst = SET_DEST (set);
8029 if (! rtx_equal_p (dst, SET_DEST (set2))
8030 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8031 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8032 || (INTVAL (XEXP (SET_SRC (set), 1))
8033 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8035 delete_related_insns (prev);
8036 delete_related_insns (next);
8039 /* Subfunction of delete_address_reloads: process registers found in X. */
8041 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8043 rtx prev, set, dst, i2;
8045 enum rtx_code code = GET_CODE (x);
8049 const char *fmt = GET_RTX_FORMAT (code);
8050 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8053 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8054 else if (fmt[i] == 'E')
8056 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8057 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8064 if (spill_reg_order[REGNO (x)] < 0)
8067 /* Scan backwards for the insn that sets x. This might be a way back due
8069 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8071 code = GET_CODE (prev);
8072 if (code == CODE_LABEL || code == JUMP_INSN)
8076 if (reg_set_p (x, PATTERN (prev)))
8078 if (reg_referenced_p (x, PATTERN (prev)))
8081 if (! prev || INSN_UID (prev) < reload_first_uid)
8083 /* Check that PREV only sets the reload register. */
8084 set = single_set (prev);
8087 dst = SET_DEST (set);
8089 || ! rtx_equal_p (dst, x))
8091 if (! reg_set_p (dst, PATTERN (dead_insn)))
8093 /* Check if DST was used in a later insn -
8094 it might have been inherited. */
8095 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8101 if (reg_referenced_p (dst, PATTERN (i2)))
8103 /* If there is a reference to the register in the current insn,
8104 it might be loaded in a non-inherited reload. If no other
8105 reload uses it, that means the register is set before
8107 if (i2 == current_insn)
8109 for (j = n_reloads - 1; j >= 0; j--)
8110 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8111 || reload_override_in[j] == dst)
8113 for (j = n_reloads - 1; j >= 0; j--)
8114 if (rld[j].in && rld[j].reg_rtx == dst)
8123 /* If DST is still live at CURRENT_INSN, check if it is used for
8124 any reload. Note that even if CURRENT_INSN sets DST, we still
8125 have to check the reloads. */
8126 if (i2 == current_insn)
8128 for (j = n_reloads - 1; j >= 0; j--)
8129 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8130 || reload_override_in[j] == dst)
8132 /* ??? We can't finish the loop here, because dst might be
8133 allocated to a pseudo in this block if no reload in this
8134 block needs any of the classes containing DST - see
8135 spill_hard_reg. There is no easy way to tell this, so we
8136 have to scan till the end of the basic block. */
8138 if (reg_set_p (dst, PATTERN (i2)))
8142 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8143 reg_reloaded_contents[REGNO (dst)] = -1;
8147 /* Output reload-insns to reload VALUE into RELOADREG.
8148 VALUE is an autoincrement or autodecrement RTX whose operand
8149 is a register or memory location;
8150 so reloading involves incrementing that location.
8151 IN is either identical to VALUE, or some cheaper place to reload from.
8153 INC_AMOUNT is the number to increment or decrement by (always positive).
8154 This cannot be deduced from VALUE.
8156 Return the instruction that stores into RELOADREG. */
8159 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8161 /* REG or MEM to be copied and incremented. */
8162 rtx incloc = XEXP (value, 0);
8163 /* Nonzero if increment after copying. */
8164 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
8170 rtx real_in = in == value ? XEXP (in, 0) : in;
8172 /* No hard register is equivalent to this register after
8173 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8174 we could inc/dec that register as well (maybe even using it for
8175 the source), but I'm not sure it's worth worrying about. */
8177 reg_last_reload_reg[REGNO (incloc)] = 0;
8179 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8180 inc_amount = -inc_amount;
8182 inc = GEN_INT (inc_amount);
8184 /* If this is post-increment, first copy the location to the reload reg. */
8185 if (post && real_in != reloadreg)
8186 emit_insn (gen_move_insn (reloadreg, real_in));
8190 /* See if we can directly increment INCLOC. Use a method similar to
8191 that in gen_reload. */
8193 last = get_last_insn ();
8194 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8195 gen_rtx_PLUS (GET_MODE (incloc),
8198 code = recog_memoized (add_insn);
8201 extract_insn (add_insn);
8202 if (constrain_operands (1))
8204 /* If this is a pre-increment and we have incremented the value
8205 where it lives, copy the incremented value to RELOADREG to
8206 be used as an address. */
8209 emit_insn (gen_move_insn (reloadreg, incloc));
8214 delete_insns_since (last);
8217 /* If couldn't do the increment directly, must increment in RELOADREG.
8218 The way we do this depends on whether this is pre- or post-increment.
8219 For pre-increment, copy INCLOC to the reload register, increment it
8220 there, then save back. */
8224 if (in != reloadreg)
8225 emit_insn (gen_move_insn (reloadreg, real_in));
8226 emit_insn (gen_add2_insn (reloadreg, inc));
8227 store = emit_insn (gen_move_insn (incloc, reloadreg));
8232 Because this might be a jump insn or a compare, and because RELOADREG
8233 may not be available after the insn in an input reload, we must do
8234 the incrementation before the insn being reloaded for.
8236 We have already copied IN to RELOADREG. Increment the copy in
8237 RELOADREG, save that back, then decrement RELOADREG so it has
8238 the original value. */
8240 emit_insn (gen_add2_insn (reloadreg, inc));
8241 store = emit_insn (gen_move_insn (incloc, reloadreg));
8242 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8250 add_auto_inc_notes (rtx insn, rtx x)
8252 enum rtx_code code = GET_CODE (x);
8256 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8259 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8263 /* Scan all the operand sub-expressions. */
8264 fmt = GET_RTX_FORMAT (code);
8265 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8268 add_auto_inc_notes (insn, XEXP (x, i));
8269 else if (fmt[i] == 'E')
8270 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8271 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8276 /* Copy EH notes from an insn to its reloads. */
8278 copy_eh_notes (rtx insn, rtx x)
8280 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8283 for (; x != 0; x = NEXT_INSN (x))
8285 if (may_trap_p (PATTERN (x)))
8287 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8293 /* This is used by reload pass, that does emit some instructions after
8294 abnormal calls moving basic block end, but in fact it wants to emit
8295 them on the edge. Looks for abnormal call edges, find backward the
8296 proper call and fix the damage.
8298 Similar handle instructions throwing exceptions internally. */
8300 fixup_abnormal_edges (void)
8302 bool inserted = false;
8310 /* Look for cases we are interested in - calls or instructions causing
8312 FOR_EACH_EDGE (e, ei, bb->succs)
8314 if (e->flags & EDGE_ABNORMAL_CALL)
8316 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8317 == (EDGE_ABNORMAL | EDGE_EH))
8320 if (e && !CALL_P (BB_END (bb))
8321 && !can_throw_internal (BB_END (bb)))
8325 /* Get past the new insns generated. Allow notes, as the insns
8326 may be already deleted. */
8328 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8329 && !can_throw_internal (insn)
8330 && insn != BB_HEAD (bb))
8331 insn = PREV_INSN (insn);
8333 if (CALL_P (insn) || can_throw_internal (insn))
8337 stop = NEXT_INSN (BB_END (bb));
8339 insn = NEXT_INSN (insn);
8341 FOR_EACH_EDGE (e, ei, bb->succs)
8342 if (e->flags & EDGE_FALLTHRU)
8345 while (insn && insn != stop)
8347 next = NEXT_INSN (insn);
8352 /* Sometimes there's still the return value USE.
8353 If it's placed after a trapping call (i.e. that
8354 call is the last insn anyway), we have no fallthru
8355 edge. Simply delete this use and don't try to insert
8356 on the non-existent edge. */
8357 if (GET_CODE (PATTERN (insn)) != USE)
8359 /* We're not deleting it, we're moving it. */
8360 INSN_DELETED_P (insn) = 0;
8361 PREV_INSN (insn) = NULL_RTX;
8362 NEXT_INSN (insn) = NULL_RTX;
8364 insert_insn_on_edge (insn, e);
8372 /* It may be that we don't find any such trapping insn. In this
8373 case we discovered quite late that the insn that had been
8374 marked as can_throw_internal in fact couldn't trap at all.
8375 So we should in fact delete the EH edges out of the block. */
8377 purge_dead_edges (bb);
8381 /* We've possibly turned single trapping insn into multiple ones. */
8382 if (flag_non_call_exceptions)
8385 blocks = sbitmap_alloc (last_basic_block);
8386 sbitmap_ones (blocks);
8387 find_many_sub_basic_blocks (blocks);
8391 commit_edge_insertions ();
8393 #ifdef ENABLE_CHECKING
8394 /* Verify that we didn't turn one trapping insn into many, and that
8395 we found and corrected all of the problems wrt fixups on the
8397 verify_flow_info ();
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