1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "addresses.h"
39 #include "basic-block.h"
52 /* This file contains the reload pass of the compiler, which is
53 run after register allocation has been done. It checks that
54 each insn is valid (operands required to be in registers really
55 are in registers of the proper class) and fixes up invalid ones
56 by copying values temporarily into registers for the insns
59 The results of register allocation are described by the vector
60 reg_renumber; the insns still contain pseudo regs, but reg_renumber
61 can be used to find which hard reg, if any, a pseudo reg is in.
63 The technique we always use is to free up a few hard regs that are
64 called ``reload regs'', and for each place where a pseudo reg
65 must be in a hard reg, copy it temporarily into one of the reload regs.
67 Reload regs are allocated locally for every instruction that needs
68 reloads. When there are pseudos which are allocated to a register that
69 has been chosen as a reload reg, such pseudos must be ``spilled''.
70 This means that they go to other hard regs, or to stack slots if no other
71 available hard regs can be found. Spilling can invalidate more
72 insns, requiring additional need for reloads, so we must keep checking
73 until the process stabilizes.
75 For machines with different classes of registers, we must keep track
76 of the register class needed for each reload, and make sure that
77 we allocate enough reload registers of each class.
79 The file reload.c contains the code that checks one insn for
80 validity and reports the reloads that it needs. This file
81 is in charge of scanning the entire rtl code, accumulating the
82 reload needs, spilling, assigning reload registers to use for
83 fixing up each insn, and generating the new insns to copy values
84 into the reload registers. */
86 /* During reload_as_needed, element N contains a REG rtx for the hard reg
87 into which reg N has been reloaded (perhaps for a previous insn). */
88 static rtx *reg_last_reload_reg;
90 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
91 for an output reload that stores into reg N. */
92 static regset_head reg_has_output_reload;
94 /* Indicates which hard regs are reload-registers for an output reload
95 in the current insn. */
96 static HARD_REG_SET reg_is_output_reload;
98 /* Element N is the constant value to which pseudo reg N is equivalent,
99 or zero if pseudo reg N is not equivalent to a constant.
100 find_reloads looks at this in order to replace pseudo reg N
101 with the constant it stands for. */
102 rtx *reg_equiv_constant;
104 /* Element N is an invariant value to which pseudo reg N is equivalent.
105 eliminate_regs_in_insn uses this to replace pseudos in particular
107 rtx *reg_equiv_invariant;
109 /* Element N is a memory location to which pseudo reg N is equivalent,
110 prior to any register elimination (such as frame pointer to stack
111 pointer). Depending on whether or not it is a valid address, this value
112 is transferred to either reg_equiv_address or reg_equiv_mem. */
113 rtx *reg_equiv_memory_loc;
115 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
116 collector can keep track of what is inside. */
117 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
119 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
120 This is used when the address is not valid as a memory address
121 (because its displacement is too big for the machine.) */
122 rtx *reg_equiv_address;
124 /* Element N is the memory slot to which pseudo reg N is equivalent,
125 or zero if pseudo reg N is not equivalent to a memory slot. */
128 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
129 alternate representations of the location of pseudo reg N. */
130 rtx *reg_equiv_alt_mem_list;
132 /* Widest width in which each pseudo reg is referred to (via subreg). */
133 static unsigned int *reg_max_ref_width;
135 /* Element N is the list of insns that initialized reg N from its equivalent
136 constant or memory slot. */
138 int reg_equiv_init_size;
140 /* Vector to remember old contents of reg_renumber before spilling. */
141 static short *reg_old_renumber;
143 /* During reload_as_needed, element N contains the last pseudo regno reloaded
144 into hard register N. If that pseudo reg occupied more than one register,
145 reg_reloaded_contents points to that pseudo for each spill register in
146 use; all of these must remain set for an inheritance to occur. */
147 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
149 /* During reload_as_needed, element N contains the insn for which
150 hard register N was last used. Its contents are significant only
151 when reg_reloaded_valid is set for this register. */
152 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
154 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
155 static HARD_REG_SET reg_reloaded_valid;
156 /* Indicate if the register was dead at the end of the reload.
157 This is only valid if reg_reloaded_contents is set and valid. */
158 static HARD_REG_SET reg_reloaded_dead;
160 /* Indicate whether the register's current value is one that is not
161 safe to retain across a call, even for registers that are normally
162 call-saved. This is only meaningful for members of reg_reloaded_valid. */
163 static HARD_REG_SET reg_reloaded_call_part_clobbered;
165 /* Number of spill-regs so far; number of valid elements of spill_regs. */
168 /* In parallel with spill_regs, contains REG rtx's for those regs.
169 Holds the last rtx used for any given reg, or 0 if it has never
170 been used for spilling yet. This rtx is reused, provided it has
172 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
174 /* In parallel with spill_regs, contains nonzero for a spill reg
175 that was stored after the last time it was used.
176 The precise value is the insn generated to do the store. */
177 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
179 /* This is the register that was stored with spill_reg_store. This is a
180 copy of reload_out / reload_out_reg when the value was stored; if
181 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
182 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
184 /* This table is the inverse mapping of spill_regs:
185 indexed by hard reg number,
186 it contains the position of that reg in spill_regs,
187 or -1 for something that is not in spill_regs.
189 ?!? This is no longer accurate. */
190 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
192 /* This reg set indicates registers that can't be used as spill registers for
193 the currently processed insn. These are the hard registers which are live
194 during the insn, but not allocated to pseudos, as well as fixed
196 static HARD_REG_SET bad_spill_regs;
198 /* These are the hard registers that can't be used as spill register for any
199 insn. This includes registers used for user variables and registers that
200 we can't eliminate. A register that appears in this set also can't be used
201 to retry register allocation. */
202 static HARD_REG_SET bad_spill_regs_global;
204 /* Describes order of use of registers for reloading
205 of spilled pseudo-registers. `n_spills' is the number of
206 elements that are actually valid; new ones are added at the end.
208 Both spill_regs and spill_reg_order are used on two occasions:
209 once during find_reload_regs, where they keep track of the spill registers
210 for a single insn, but also during reload_as_needed where they show all
211 the registers ever used by reload. For the latter case, the information
212 is calculated during finish_spills. */
213 static short spill_regs[FIRST_PSEUDO_REGISTER];
215 /* This vector of reg sets indicates, for each pseudo, which hard registers
216 may not be used for retrying global allocation because the register was
217 formerly spilled from one of them. If we allowed reallocating a pseudo to
218 a register that it was already allocated to, reload might not
220 static HARD_REG_SET *pseudo_previous_regs;
222 /* This vector of reg sets indicates, for each pseudo, which hard
223 registers may not be used for retrying global allocation because they
224 are used as spill registers during one of the insns in which the
226 static HARD_REG_SET *pseudo_forbidden_regs;
228 /* All hard regs that have been used as spill registers for any insn are
229 marked in this set. */
230 static HARD_REG_SET used_spill_regs;
232 /* Index of last register assigned as a spill register. We allocate in
233 a round-robin fashion. */
234 static int last_spill_reg;
236 /* Nonzero if indirect addressing is supported on the machine; this means
237 that spilling (REG n) does not require reloading it into a register in
238 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
239 value indicates the level of indirect addressing supported, e.g., two
240 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
242 static char spill_indirect_levels;
244 /* Nonzero if indirect addressing is supported when the innermost MEM is
245 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
246 which these are valid is the same as spill_indirect_levels, above. */
247 char indirect_symref_ok;
249 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
250 char double_reg_address_ok;
252 /* Record the stack slot for each spilled hard register. */
253 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
255 /* Width allocated so far for that stack slot. */
256 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
258 /* Record which pseudos needed to be spilled. */
259 static regset_head spilled_pseudos;
261 /* Record which pseudos changed their allocation in finish_spills. */
262 static regset_head changed_allocation_pseudos;
264 /* Used for communication between order_regs_for_reload and count_pseudo.
265 Used to avoid counting one pseudo twice. */
266 static regset_head pseudos_counted;
268 /* First uid used by insns created by reload in this function.
269 Used in find_equiv_reg. */
270 int reload_first_uid;
272 /* Flag set by local-alloc or global-alloc if anything is live in
273 a call-clobbered reg across calls. */
274 int caller_save_needed;
276 /* Set to 1 while reload_as_needed is operating.
277 Required by some machines to handle any generated moves differently. */
278 int reload_in_progress = 0;
280 /* These arrays record the insn_code of insns that may be needed to
281 perform input and output reloads of special objects. They provide a
282 place to pass a scratch register. */
283 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
284 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
286 /* This obstack is used for allocation of rtl during register elimination.
287 The allocated storage can be freed once find_reloads has processed the
289 static struct obstack reload_obstack;
291 /* Points to the beginning of the reload_obstack. All insn_chain structures
292 are allocated first. */
293 static char *reload_startobj;
295 /* The point after all insn_chain structures. Used to quickly deallocate
296 memory allocated in copy_reloads during calculate_needs_all_insns. */
297 static char *reload_firstobj;
299 /* This points before all local rtl generated by register elimination.
300 Used to quickly free all memory after processing one insn. */
301 static char *reload_insn_firstobj;
303 /* List of insn_chain instructions, one for every insn that reload needs to
305 struct insn_chain *reload_insn_chain;
307 /* List of all insns needing reloads. */
308 static struct insn_chain *insns_need_reload;
310 /* This structure is used to record information about register eliminations.
311 Each array entry describes one possible way of eliminating a register
312 in favor of another. If there is more than one way of eliminating a
313 particular register, the most preferred should be specified first. */
317 int from; /* Register number to be eliminated. */
318 int to; /* Register number used as replacement. */
319 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
320 int can_eliminate; /* Nonzero if this elimination can be done. */
321 int can_eliminate_previous; /* Value returned by TARGET_CAN_ELIMINATE
322 target hook in previous scan over insns
324 HOST_WIDE_INT offset; /* Current offset between the two regs. */
325 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
326 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
327 rtx from_rtx; /* REG rtx for the register to be eliminated.
328 We cannot simply compare the number since
329 we might then spuriously replace a hard
330 register corresponding to a pseudo
331 assigned to the reg to be eliminated. */
332 rtx to_rtx; /* REG rtx for the replacement. */
335 static struct elim_table *reg_eliminate = 0;
337 /* This is an intermediate structure to initialize the table. It has
338 exactly the members provided by ELIMINABLE_REGS. */
339 static const struct elim_table_1
343 } reg_eliminate_1[] =
345 /* If a set of eliminable registers was specified, define the table from it.
346 Otherwise, default to the normal case of the frame pointer being
347 replaced by the stack pointer. */
349 #ifdef ELIMINABLE_REGS
352 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
355 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
357 /* Record the number of pending eliminations that have an offset not equal
358 to their initial offset. If nonzero, we use a new copy of each
359 replacement result in any insns encountered. */
360 int num_not_at_initial_offset;
362 /* Count the number of registers that we may be able to eliminate. */
363 static int num_eliminable;
364 /* And the number of registers that are equivalent to a constant that
365 can be eliminated to frame_pointer / arg_pointer + constant. */
366 static int num_eliminable_invariants;
368 /* For each label, we record the offset of each elimination. If we reach
369 a label by more than one path and an offset differs, we cannot do the
370 elimination. This information is indexed by the difference of the
371 number of the label and the first label number. We can't offset the
372 pointer itself as this can cause problems on machines with segmented
373 memory. The first table is an array of flags that records whether we
374 have yet encountered a label and the second table is an array of arrays,
375 one entry in the latter array for each elimination. */
377 static int first_label_num;
378 static char *offsets_known_at;
379 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
381 /* Number of labels in the current function. */
383 static int num_labels;
385 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
386 static void maybe_fix_stack_asms (void);
387 static void copy_reloads (struct insn_chain *);
388 static void calculate_needs_all_insns (int);
389 static int find_reg (struct insn_chain *, int);
390 static void find_reload_regs (struct insn_chain *);
391 static void select_reload_regs (void);
392 static void delete_caller_save_insns (void);
394 static void spill_failure (rtx, enum reg_class);
395 static void count_spilled_pseudo (int, int, int);
396 static void delete_dead_insn (rtx);
397 static void alter_reg (int, int, bool);
398 static void set_label_offsets (rtx, rtx, int);
399 static void check_eliminable_occurrences (rtx);
400 static void elimination_effects (rtx, enum machine_mode);
401 static int eliminate_regs_in_insn (rtx, int);
402 static void update_eliminable_offsets (void);
403 static void mark_not_eliminable (rtx, const_rtx, void *);
404 static void set_initial_elim_offsets (void);
405 static bool verify_initial_elim_offsets (void);
406 static void set_initial_label_offsets (void);
407 static void set_offsets_for_label (rtx);
408 static void init_elim_table (void);
409 static void update_eliminables (HARD_REG_SET *);
410 static void spill_hard_reg (unsigned int, int);
411 static int finish_spills (int);
412 static void scan_paradoxical_subregs (rtx);
413 static void count_pseudo (int);
414 static void order_regs_for_reload (struct insn_chain *);
415 static void reload_as_needed (int);
416 static void forget_old_reloads_1 (rtx, const_rtx, void *);
417 static void forget_marked_reloads (regset);
418 static int reload_reg_class_lower (const void *, const void *);
419 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
421 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
423 static int reload_reg_free_p (unsigned int, int, enum reload_type);
424 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
426 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
428 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
429 static int allocate_reload_reg (struct insn_chain *, int, int);
430 static int conflicts_with_override (rtx);
431 static void failed_reload (rtx, int);
432 static int set_reload_reg (int, int);
433 static void choose_reload_regs_init (struct insn_chain *, rtx *);
434 static void choose_reload_regs (struct insn_chain *);
435 static void merge_assigned_reloads (rtx);
436 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
438 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
440 static void do_input_reload (struct insn_chain *, struct reload *, int);
441 static void do_output_reload (struct insn_chain *, struct reload *, int);
442 static void emit_reload_insns (struct insn_chain *);
443 static void delete_output_reload (rtx, int, int, rtx);
444 static void delete_address_reloads (rtx, rtx);
445 static void delete_address_reloads_1 (rtx, rtx, rtx);
446 static rtx inc_for_reload (rtx, rtx, rtx, int);
448 static void add_auto_inc_notes (rtx, rtx);
450 static void substitute (rtx *, const_rtx, rtx);
451 static bool gen_reload_chain_without_interm_reg_p (int, int);
452 static int reloads_conflict (int, int);
453 static rtx gen_reload (rtx, rtx, int, enum reload_type);
454 static rtx emit_insn_if_valid_for_reload (rtx);
456 /* Initialize the reload pass. This is called at the beginning of compilation
457 and may be called again if the target is reinitialized. */
464 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
465 Set spill_indirect_levels to the number of levels such addressing is
466 permitted, zero if it is not permitted at all. */
469 = gen_rtx_MEM (Pmode,
472 LAST_VIRTUAL_REGISTER + 1),
474 spill_indirect_levels = 0;
476 while (memory_address_p (QImode, tem))
478 spill_indirect_levels++;
479 tem = gen_rtx_MEM (Pmode, tem);
482 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
484 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
485 indirect_symref_ok = memory_address_p (QImode, tem);
487 /* See if reg+reg is a valid (and offsettable) address. */
489 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
491 tem = gen_rtx_PLUS (Pmode,
492 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
493 gen_rtx_REG (Pmode, i));
495 /* This way, we make sure that reg+reg is an offsettable address. */
496 tem = plus_constant (tem, 4);
498 if (memory_address_p (QImode, tem))
500 double_reg_address_ok = 1;
505 /* Initialize obstack for our rtl allocation. */
506 gcc_obstack_init (&reload_obstack);
507 reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
509 INIT_REG_SET (&spilled_pseudos);
510 INIT_REG_SET (&changed_allocation_pseudos);
511 INIT_REG_SET (&pseudos_counted);
514 /* List of insn chains that are currently unused. */
515 static struct insn_chain *unused_insn_chains = 0;
517 /* Allocate an empty insn_chain structure. */
519 new_insn_chain (void)
521 struct insn_chain *c;
523 if (unused_insn_chains == 0)
525 c = XOBNEW (&reload_obstack, struct insn_chain);
526 INIT_REG_SET (&c->live_throughout);
527 INIT_REG_SET (&c->dead_or_set);
531 c = unused_insn_chains;
532 unused_insn_chains = c->next;
534 c->is_caller_save_insn = 0;
535 c->need_operand_change = 0;
541 /* Small utility function to set all regs in hard reg set TO which are
542 allocated to pseudos in regset FROM. */
545 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
548 reg_set_iterator rsi;
550 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
552 int r = reg_renumber[regno];
556 /* reload_combine uses the information from DF_LIVE_IN,
557 which might still contain registers that have not
558 actually been allocated since they have an
560 gcc_assert (ira_conflicts_p || reload_completed);
563 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
567 /* Replace all pseudos found in LOC with their corresponding
571 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
584 unsigned int regno = REGNO (x);
586 if (regno < FIRST_PSEUDO_REGISTER)
589 x = eliminate_regs (x, mem_mode, usage);
593 replace_pseudos_in (loc, mem_mode, usage);
597 if (reg_equiv_constant[regno])
598 *loc = reg_equiv_constant[regno];
599 else if (reg_equiv_mem[regno])
600 *loc = reg_equiv_mem[regno];
601 else if (reg_equiv_address[regno])
602 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
605 gcc_assert (!REG_P (regno_reg_rtx[regno])
606 || REGNO (regno_reg_rtx[regno]) != regno);
607 *loc = regno_reg_rtx[regno];
612 else if (code == MEM)
614 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
618 /* Process each of our operands recursively. */
619 fmt = GET_RTX_FORMAT (code);
620 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
622 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
623 else if (*fmt == 'E')
624 for (j = 0; j < XVECLEN (x, i); j++)
625 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
628 /* Determine if the current function has an exception receiver block
629 that reaches the exit block via non-exceptional edges */
632 has_nonexceptional_receiver (void)
636 basic_block *tos, *worklist, bb;
638 /* If we're not optimizing, then just err on the safe side. */
642 /* First determine which blocks can reach exit via normal paths. */
643 tos = worklist = XNEWVEC (basic_block, n_basic_blocks + 1);
646 bb->flags &= ~BB_REACHABLE;
648 /* Place the exit block on our worklist. */
649 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
650 *tos++ = EXIT_BLOCK_PTR;
652 /* Iterate: find everything reachable from what we've already seen. */
653 while (tos != worklist)
657 FOR_EACH_EDGE (e, ei, bb->preds)
658 if (!(e->flags & EDGE_ABNORMAL))
660 basic_block src = e->src;
662 if (!(src->flags & BB_REACHABLE))
664 src->flags |= BB_REACHABLE;
671 /* Now see if there's a reachable block with an exceptional incoming
674 if (bb->flags & BB_REACHABLE)
675 FOR_EACH_EDGE (e, ei, bb->preds)
676 if (e->flags & EDGE_ABNORMAL)
679 /* No exceptional block reached exit unexceptionally. */
684 /* Global variables used by reload and its subroutines. */
686 /* Set during calculate_needs if an insn needs register elimination. */
687 static int something_needs_elimination;
688 /* Set during calculate_needs if an insn needs an operand changed. */
689 static int something_needs_operands_changed;
691 /* Nonzero means we couldn't get enough spill regs. */
694 /* Temporary array of pseudo-register number. */
695 static int *temp_pseudo_reg_arr;
697 /* Main entry point for the reload pass.
699 FIRST is the first insn of the function being compiled.
701 GLOBAL nonzero means we were called from global_alloc
702 and should attempt to reallocate any pseudoregs that we
703 displace from hard regs we will use for reloads.
704 If GLOBAL is zero, we do not have enough information to do that,
705 so any pseudo reg that is spilled must go to the stack.
707 Return value is nonzero if reload failed
708 and we must not do any more for this function. */
711 reload (rtx first, int global)
715 struct elim_table *ep;
718 /* Make sure even insns with volatile mem refs are recognizable. */
723 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
725 /* Make sure that the last insn in the chain
726 is not something that needs reloading. */
727 emit_note (NOTE_INSN_DELETED);
729 /* Enable find_equiv_reg to distinguish insns made by reload. */
730 reload_first_uid = get_max_uid ();
732 #ifdef SECONDARY_MEMORY_NEEDED
733 /* Initialize the secondary memory table. */
734 clear_secondary_mem ();
737 /* We don't have a stack slot for any spill reg yet. */
738 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
739 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
741 /* Initialize the save area information for caller-save, in case some
745 /* Compute which hard registers are now in use
746 as homes for pseudo registers.
747 This is done here rather than (eg) in global_alloc
748 because this point is reached even if not optimizing. */
749 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
752 /* A function that has a nonlocal label that can reach the exit
753 block via non-exceptional paths must save all call-saved
755 if (cfun->has_nonlocal_label
756 && has_nonexceptional_receiver ())
757 crtl->saves_all_registers = 1;
759 if (crtl->saves_all_registers)
760 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
761 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
762 df_set_regs_ever_live (i, true);
764 /* Find all the pseudo registers that didn't get hard regs
765 but do have known equivalent constants or memory slots.
766 These include parameters (known equivalent to parameter slots)
767 and cse'd or loop-moved constant memory addresses.
769 Record constant equivalents in reg_equiv_constant
770 so they will be substituted by find_reloads.
771 Record memory equivalents in reg_mem_equiv so they can
772 be substituted eventually by altering the REG-rtx's. */
774 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
775 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
776 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
777 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
778 reg_equiv_address = XCNEWVEC (rtx, max_regno);
779 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
780 reg_old_renumber = XCNEWVEC (short, max_regno);
781 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
782 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
783 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
785 CLEAR_HARD_REG_SET (bad_spill_regs_global);
787 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
788 to. Also find all paradoxical subregs and find largest such for
791 num_eliminable_invariants = 0;
792 for (insn = first; insn; insn = NEXT_INSN (insn))
794 rtx set = single_set (insn);
796 /* We may introduce USEs that we want to remove at the end, so
797 we'll mark them with QImode. Make sure there are no
798 previously-marked insns left by say regmove. */
799 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
800 && GET_MODE (insn) != VOIDmode)
801 PUT_MODE (insn, VOIDmode);
803 if (NONDEBUG_INSN_P (insn))
804 scan_paradoxical_subregs (PATTERN (insn));
806 if (set != 0 && REG_P (SET_DEST (set)))
808 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
814 i = REGNO (SET_DEST (set));
817 if (i <= LAST_VIRTUAL_REGISTER)
820 if (! function_invariant_p (x)
822 /* A function invariant is often CONSTANT_P but may
823 include a register. We promise to only pass
824 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
826 && LEGITIMATE_PIC_OPERAND_P (x)))
828 /* It can happen that a REG_EQUIV note contains a MEM
829 that is not a legitimate memory operand. As later
830 stages of reload assume that all addresses found
831 in the reg_equiv_* arrays were originally legitimate,
832 we ignore such REG_EQUIV notes. */
833 if (memory_operand (x, VOIDmode))
835 /* Always unshare the equivalence, so we can
836 substitute into this insn without touching the
838 reg_equiv_memory_loc[i] = copy_rtx (x);
840 else if (function_invariant_p (x))
842 if (GET_CODE (x) == PLUS)
844 /* This is PLUS of frame pointer and a constant,
845 and might be shared. Unshare it. */
846 reg_equiv_invariant[i] = copy_rtx (x);
847 num_eliminable_invariants++;
849 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
851 reg_equiv_invariant[i] = x;
852 num_eliminable_invariants++;
854 else if (LEGITIMATE_CONSTANT_P (x))
855 reg_equiv_constant[i] = x;
858 reg_equiv_memory_loc[i]
859 = force_const_mem (GET_MODE (SET_DEST (set)), x);
860 if (! reg_equiv_memory_loc[i])
861 reg_equiv_init[i] = NULL_RTX;
866 reg_equiv_init[i] = NULL_RTX;
871 reg_equiv_init[i] = NULL_RTX;
876 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
877 if (reg_equiv_init[i])
879 fprintf (dump_file, "init_insns for %u: ", i);
880 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
881 fprintf (dump_file, "\n");
886 first_label_num = get_first_label_num ();
887 num_labels = max_label_num () - first_label_num;
889 /* Allocate the tables used to store offset information at labels. */
890 /* We used to use alloca here, but the size of what it would try to
891 allocate would occasionally cause it to exceed the stack limit and
892 cause a core dump. */
893 offsets_known_at = XNEWVEC (char, num_labels);
894 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
896 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
897 stack slots to the pseudos that lack hard regs or equivalents.
898 Do not touch virtual registers. */
900 temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
901 for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
902 temp_pseudo_reg_arr[n++] = i;
905 /* Ask IRA to order pseudo-registers for better stack slot
907 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width);
909 for (i = 0; i < n; i++)
910 alter_reg (temp_pseudo_reg_arr[i], -1, false);
912 /* If we have some registers we think can be eliminated, scan all insns to
913 see if there is an insn that sets one of these registers to something
914 other than itself plus a constant. If so, the register cannot be
915 eliminated. Doing this scan here eliminates an extra pass through the
916 main reload loop in the most common case where register elimination
918 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
920 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
922 maybe_fix_stack_asms ();
924 insns_need_reload = 0;
925 something_needs_elimination = 0;
927 /* Initialize to -1, which means take the first spill register. */
930 /* Spill any hard regs that we know we can't eliminate. */
931 CLEAR_HARD_REG_SET (used_spill_regs);
932 /* There can be multiple ways to eliminate a register;
933 they should be listed adjacently.
934 Elimination for any register fails only if all possible ways fail. */
935 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
938 int can_eliminate = 0;
941 can_eliminate |= ep->can_eliminate;
944 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
946 spill_hard_reg (from, 1);
949 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
950 if (frame_pointer_needed)
951 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
953 finish_spills (global);
955 /* From now on, we may need to generate moves differently. We may also
956 allow modifications of insns which cause them to not be recognized.
957 Any such modifications will be cleaned up during reload itself. */
958 reload_in_progress = 1;
960 /* This loop scans the entire function each go-round
961 and repeats until one repetition spills no additional hard regs. */
964 int something_changed;
966 HOST_WIDE_INT starting_frame_size;
968 starting_frame_size = get_frame_size ();
970 set_initial_elim_offsets ();
971 set_initial_label_offsets ();
973 /* For each pseudo register that has an equivalent location defined,
974 try to eliminate any eliminable registers (such as the frame pointer)
975 assuming initial offsets for the replacement register, which
978 If the resulting location is directly addressable, substitute
979 the MEM we just got directly for the old REG.
981 If it is not addressable but is a constant or the sum of a hard reg
982 and constant, it is probably not addressable because the constant is
983 out of range, in that case record the address; we will generate
984 hairy code to compute the address in a register each time it is
985 needed. Similarly if it is a hard register, but one that is not
986 valid as an address register.
988 If the location is not addressable, but does not have one of the
989 above forms, assign a stack slot. We have to do this to avoid the
990 potential of producing lots of reloads if, e.g., a location involves
991 a pseudo that didn't get a hard register and has an equivalent memory
992 location that also involves a pseudo that didn't get a hard register.
994 Perhaps at some point we will improve reload_when_needed handling
995 so this problem goes away. But that's very hairy. */
997 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
998 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
1000 rtx x = eliminate_regs (reg_equiv_memory_loc[i], VOIDmode,
1003 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
1005 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
1006 else if (CONSTANT_P (XEXP (x, 0))
1007 || (REG_P (XEXP (x, 0))
1008 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
1009 || (GET_CODE (XEXP (x, 0)) == PLUS
1010 && REG_P (XEXP (XEXP (x, 0), 0))
1011 && (REGNO (XEXP (XEXP (x, 0), 0))
1012 < FIRST_PSEUDO_REGISTER)
1013 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
1014 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
1017 /* Make a new stack slot. Then indicate that something
1018 changed so we go back and recompute offsets for
1019 eliminable registers because the allocation of memory
1020 below might change some offset. reg_equiv_{mem,address}
1021 will be set up for this pseudo on the next pass around
1023 reg_equiv_memory_loc[i] = 0;
1024 reg_equiv_init[i] = 0;
1025 alter_reg (i, -1, true);
1029 if (caller_save_needed)
1030 setup_save_areas ();
1032 /* If we allocated another stack slot, redo elimination bookkeeping. */
1033 if (starting_frame_size != get_frame_size ())
1035 if (starting_frame_size && crtl->stack_alignment_needed)
1037 /* If we have a stack frame, we must align it now. The
1038 stack size may be a part of the offset computation for
1039 register elimination. So if this changes the stack size,
1040 then repeat the elimination bookkeeping. We don't
1041 realign when there is no stack, as that will cause a
1042 stack frame when none is needed should
1043 STARTING_FRAME_OFFSET not be already aligned to
1045 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
1046 if (starting_frame_size != get_frame_size ())
1050 if (caller_save_needed)
1052 save_call_clobbered_regs ();
1053 /* That might have allocated new insn_chain structures. */
1054 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1057 calculate_needs_all_insns (global);
1059 if (! ira_conflicts_p)
1060 /* Don't do it for IRA. We need this info because we don't
1061 change live_throughout and dead_or_set for chains when IRA
1063 CLEAR_REG_SET (&spilled_pseudos);
1067 something_changed = 0;
1069 /* If we allocated any new memory locations, make another pass
1070 since it might have changed elimination offsets. */
1071 if (starting_frame_size != get_frame_size ())
1072 something_changed = 1;
1074 /* Even if the frame size remained the same, we might still have
1075 changed elimination offsets, e.g. if find_reloads called
1076 force_const_mem requiring the back end to allocate a constant
1077 pool base register that needs to be saved on the stack. */
1078 else if (!verify_initial_elim_offsets ())
1079 something_changed = 1;
1082 HARD_REG_SET to_spill;
1083 CLEAR_HARD_REG_SET (to_spill);
1084 update_eliminables (&to_spill);
1085 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
1087 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1088 if (TEST_HARD_REG_BIT (to_spill, i))
1090 spill_hard_reg (i, 1);
1093 /* Regardless of the state of spills, if we previously had
1094 a register that we thought we could eliminate, but now can
1095 not eliminate, we must run another pass.
1097 Consider pseudos which have an entry in reg_equiv_* which
1098 reference an eliminable register. We must make another pass
1099 to update reg_equiv_* so that we do not substitute in the
1100 old value from when we thought the elimination could be
1102 something_changed = 1;
1106 select_reload_regs ();
1110 if (insns_need_reload != 0 || did_spill)
1111 something_changed |= finish_spills (global);
1113 if (! something_changed)
1116 if (caller_save_needed)
1117 delete_caller_save_insns ();
1119 obstack_free (&reload_obstack, reload_firstobj);
1122 /* If global-alloc was run, notify it of any register eliminations we have
1125 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1126 if (ep->can_eliminate)
1127 mark_elimination (ep->from, ep->to);
1129 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1130 If that insn didn't set the register (i.e., it copied the register to
1131 memory), just delete that insn instead of the equivalencing insn plus
1132 anything now dead. If we call delete_dead_insn on that insn, we may
1133 delete the insn that actually sets the register if the register dies
1134 there and that is incorrect. */
1136 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1138 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1141 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1143 rtx equiv_insn = XEXP (list, 0);
1145 /* If we already deleted the insn or if it may trap, we can't
1146 delete it. The latter case shouldn't happen, but can
1147 if an insn has a variable address, gets a REG_EH_REGION
1148 note added to it, and then gets converted into a load
1149 from a constant address. */
1150 if (NOTE_P (equiv_insn)
1151 || can_throw_internal (equiv_insn))
1153 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1154 delete_dead_insn (equiv_insn);
1156 SET_INSN_DELETED (equiv_insn);
1161 /* Use the reload registers where necessary
1162 by generating move instructions to move the must-be-register
1163 values into or out of the reload registers. */
1165 if (insns_need_reload != 0 || something_needs_elimination
1166 || something_needs_operands_changed)
1168 HOST_WIDE_INT old_frame_size = get_frame_size ();
1170 reload_as_needed (global);
1172 gcc_assert (old_frame_size == get_frame_size ());
1174 gcc_assert (verify_initial_elim_offsets ());
1177 /* If we were able to eliminate the frame pointer, show that it is no
1178 longer live at the start of any basic block. If it ls live by
1179 virtue of being in a pseudo, that pseudo will be marked live
1180 and hence the frame pointer will be known to be live via that
1183 if (! frame_pointer_needed)
1185 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1187 /* Come here (with failure set nonzero) if we can't get enough spill
1191 CLEAR_REG_SET (&changed_allocation_pseudos);
1192 CLEAR_REG_SET (&spilled_pseudos);
1193 reload_in_progress = 0;
1195 /* Now eliminate all pseudo regs by modifying them into
1196 their equivalent memory references.
1197 The REG-rtx's for the pseudos are modified in place,
1198 so all insns that used to refer to them now refer to memory.
1200 For a reg that has a reg_equiv_address, all those insns
1201 were changed by reloading so that no insns refer to it any longer;
1202 but the DECL_RTL of a variable decl may refer to it,
1203 and if so this causes the debugging info to mention the variable. */
1205 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1209 if (reg_equiv_mem[i])
1210 addr = XEXP (reg_equiv_mem[i], 0);
1212 if (reg_equiv_address[i])
1213 addr = reg_equiv_address[i];
1217 if (reg_renumber[i] < 0)
1219 rtx reg = regno_reg_rtx[i];
1221 REG_USERVAR_P (reg) = 0;
1222 PUT_CODE (reg, MEM);
1223 XEXP (reg, 0) = addr;
1224 if (reg_equiv_memory_loc[i])
1225 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1228 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1229 MEM_ATTRS (reg) = 0;
1231 MEM_NOTRAP_P (reg) = 1;
1233 else if (reg_equiv_mem[i])
1234 XEXP (reg_equiv_mem[i], 0) = addr;
1237 /* We don't want complex addressing modes in debug insns
1238 if simpler ones will do, so delegitimize equivalences
1240 if (MAY_HAVE_DEBUG_INSNS && reg_renumber[i] < 0)
1242 rtx reg = regno_reg_rtx[i];
1246 if (reg_equiv_constant[i])
1247 equiv = reg_equiv_constant[i];
1248 else if (reg_equiv_invariant[i])
1249 equiv = reg_equiv_invariant[i];
1250 else if (reg && MEM_P (reg))
1251 equiv = targetm.delegitimize_address (reg);
1252 else if (reg && REG_P (reg) && (int)REGNO (reg) != i)
1258 for (use = DF_REG_USE_CHAIN (i); use; use = next)
1260 insn = DF_REF_INSN (use);
1262 /* Make sure the next ref is for a different instruction,
1263 so that we're not affected by the rescan. */
1264 next = DF_REF_NEXT_REG (use);
1265 while (next && DF_REF_INSN (next) == insn)
1266 next = DF_REF_NEXT_REG (next);
1268 if (DEBUG_INSN_P (insn))
1272 INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
1273 df_insn_rescan_debug_internal (insn);
1276 INSN_VAR_LOCATION_LOC (insn)
1277 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn),
1284 /* We must set reload_completed now since the cleanup_subreg_operands call
1285 below will re-recognize each insn and reload may have generated insns
1286 which are only valid during and after reload. */
1287 reload_completed = 1;
1289 /* Make a pass over all the insns and delete all USEs which we inserted
1290 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1291 notes. Delete all CLOBBER insns, except those that refer to the return
1292 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1293 from misarranging variable-array code, and simplify (subreg (reg))
1294 operands. Strip and regenerate REG_INC notes that may have been moved
1297 for (insn = first; insn; insn = NEXT_INSN (insn))
1303 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1304 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1306 if ((GET_CODE (PATTERN (insn)) == USE
1307 /* We mark with QImode USEs introduced by reload itself. */
1308 && (GET_MODE (insn) == QImode
1309 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1310 || (GET_CODE (PATTERN (insn)) == CLOBBER
1311 && (!MEM_P (XEXP (PATTERN (insn), 0))
1312 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1313 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1314 && XEXP (XEXP (PATTERN (insn), 0), 0)
1315 != stack_pointer_rtx))
1316 && (!REG_P (XEXP (PATTERN (insn), 0))
1317 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1323 /* Some CLOBBERs may survive until here and still reference unassigned
1324 pseudos with const equivalent, which may in turn cause ICE in later
1325 passes if the reference remains in place. */
1326 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1327 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1328 VOIDmode, PATTERN (insn));
1330 /* Discard obvious no-ops, even without -O. This optimization
1331 is fast and doesn't interfere with debugging. */
1332 if (NONJUMP_INSN_P (insn)
1333 && GET_CODE (PATTERN (insn)) == SET
1334 && REG_P (SET_SRC (PATTERN (insn)))
1335 && REG_P (SET_DEST (PATTERN (insn)))
1336 && (REGNO (SET_SRC (PATTERN (insn)))
1337 == REGNO (SET_DEST (PATTERN (insn)))))
1343 pnote = ®_NOTES (insn);
1346 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1347 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1348 || REG_NOTE_KIND (*pnote) == REG_INC)
1349 *pnote = XEXP (*pnote, 1);
1351 pnote = &XEXP (*pnote, 1);
1355 add_auto_inc_notes (insn, PATTERN (insn));
1358 /* Simplify (subreg (reg)) if it appears as an operand. */
1359 cleanup_subreg_operands (insn);
1361 /* Clean up invalid ASMs so that they don't confuse later passes.
1363 if (asm_noperands (PATTERN (insn)) >= 0)
1365 extract_insn (insn);
1366 if (!constrain_operands (1))
1368 error_for_asm (insn,
1369 "%<asm%> operand has impossible constraints");
1376 /* If we are doing generic stack checking, give a warning if this
1377 function's frame size is larger than we expect. */
1378 if (flag_stack_check == GENERIC_STACK_CHECK)
1380 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1381 static int verbose_warned = 0;
1383 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1384 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1385 size += UNITS_PER_WORD;
1387 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1389 warning (0, "frame size too large for reliable stack checking");
1390 if (! verbose_warned)
1392 warning (0, "try reducing the number of local variables");
1398 /* Indicate that we no longer have known memory locations or constants. */
1399 if (reg_equiv_constant)
1400 free (reg_equiv_constant);
1401 if (reg_equiv_invariant)
1402 free (reg_equiv_invariant);
1403 reg_equiv_constant = 0;
1404 reg_equiv_invariant = 0;
1405 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
1406 reg_equiv_memory_loc = 0;
1408 free (temp_pseudo_reg_arr);
1410 if (offsets_known_at)
1411 free (offsets_known_at);
1415 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1416 if (reg_equiv_alt_mem_list[i])
1417 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
1418 free (reg_equiv_alt_mem_list);
1420 free (reg_equiv_mem);
1422 free (reg_equiv_address);
1423 free (reg_max_ref_width);
1424 free (reg_old_renumber);
1425 free (pseudo_previous_regs);
1426 free (pseudo_forbidden_regs);
1428 CLEAR_HARD_REG_SET (used_spill_regs);
1429 for (i = 0; i < n_spills; i++)
1430 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1432 /* Free all the insn_chain structures at once. */
1433 obstack_free (&reload_obstack, reload_startobj);
1434 unused_insn_chains = 0;
1435 fixup_abnormal_edges ();
1437 /* Replacing pseudos with their memory equivalents might have
1438 created shared rtx. Subsequent passes would get confused
1439 by this, so unshare everything here. */
1440 unshare_all_rtl_again (first);
1442 #ifdef STACK_BOUNDARY
1443 /* init_emit has set the alignment of the hard frame pointer
1444 to STACK_BOUNDARY. It is very likely no longer valid if
1445 the hard frame pointer was used for register allocation. */
1446 if (!frame_pointer_needed)
1447 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1453 /* Yet another special case. Unfortunately, reg-stack forces people to
1454 write incorrect clobbers in asm statements. These clobbers must not
1455 cause the register to appear in bad_spill_regs, otherwise we'll call
1456 fatal_insn later. We clear the corresponding regnos in the live
1457 register sets to avoid this.
1458 The whole thing is rather sick, I'm afraid. */
1461 maybe_fix_stack_asms (void)
1464 const char *constraints[MAX_RECOG_OPERANDS];
1465 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1466 struct insn_chain *chain;
1468 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1471 HARD_REG_SET clobbered, allowed;
1474 if (! INSN_P (chain->insn)
1475 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1477 pat = PATTERN (chain->insn);
1478 if (GET_CODE (pat) != PARALLEL)
1481 CLEAR_HARD_REG_SET (clobbered);
1482 CLEAR_HARD_REG_SET (allowed);
1484 /* First, make a mask of all stack regs that are clobbered. */
1485 for (i = 0; i < XVECLEN (pat, 0); i++)
1487 rtx t = XVECEXP (pat, 0, i);
1488 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1489 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1492 /* Get the operand values and constraints out of the insn. */
1493 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1494 constraints, operand_mode, NULL);
1496 /* For every operand, see what registers are allowed. */
1497 for (i = 0; i < noperands; i++)
1499 const char *p = constraints[i];
1500 /* For every alternative, we compute the class of registers allowed
1501 for reloading in CLS, and merge its contents into the reg set
1503 int cls = (int) NO_REGS;
1509 if (c == '\0' || c == ',' || c == '#')
1511 /* End of one alternative - mark the regs in the current
1512 class, and reset the class. */
1513 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1519 } while (c != '\0' && c != ',');
1527 case '=': case '+': case '*': case '%': case '?': case '!':
1528 case '0': case '1': case '2': case '3': case '4': case '<':
1529 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1530 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1531 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1532 case TARGET_MEM_CONSTRAINT:
1536 cls = (int) reg_class_subunion[cls]
1537 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1542 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1546 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1547 cls = (int) reg_class_subunion[cls]
1548 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1550 cls = (int) reg_class_subunion[cls]
1551 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1553 p += CONSTRAINT_LEN (c, p);
1556 /* Those of the registers which are clobbered, but allowed by the
1557 constraints, must be usable as reload registers. So clear them
1558 out of the life information. */
1559 AND_HARD_REG_SET (allowed, clobbered);
1560 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1561 if (TEST_HARD_REG_BIT (allowed, i))
1563 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1564 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1571 /* Copy the global variables n_reloads and rld into the corresponding elts
1574 copy_reloads (struct insn_chain *chain)
1576 chain->n_reloads = n_reloads;
1577 chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1578 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1579 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1582 /* Walk the chain of insns, and determine for each whether it needs reloads
1583 and/or eliminations. Build the corresponding insns_need_reload list, and
1584 set something_needs_elimination as appropriate. */
1586 calculate_needs_all_insns (int global)
1588 struct insn_chain **pprev_reload = &insns_need_reload;
1589 struct insn_chain *chain, *next = 0;
1591 something_needs_elimination = 0;
1593 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1594 for (chain = reload_insn_chain; chain != 0; chain = next)
1596 rtx insn = chain->insn;
1600 /* Clear out the shortcuts. */
1601 chain->n_reloads = 0;
1602 chain->need_elim = 0;
1603 chain->need_reload = 0;
1604 chain->need_operand_change = 0;
1606 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1607 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1608 what effects this has on the known offsets at labels. */
1610 if (LABEL_P (insn) || JUMP_P (insn)
1611 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1612 set_label_offsets (insn, insn, 0);
1616 rtx old_body = PATTERN (insn);
1617 int old_code = INSN_CODE (insn);
1618 rtx old_notes = REG_NOTES (insn);
1619 int did_elimination = 0;
1620 int operands_changed = 0;
1621 rtx set = single_set (insn);
1623 /* Skip insns that only set an equivalence. */
1624 if (set && REG_P (SET_DEST (set))
1625 && reg_renumber[REGNO (SET_DEST (set))] < 0
1626 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1627 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1628 && reg_equiv_init[REGNO (SET_DEST (set))])
1631 /* If needed, eliminate any eliminable registers. */
1632 if (num_eliminable || num_eliminable_invariants)
1633 did_elimination = eliminate_regs_in_insn (insn, 0);
1635 /* Analyze the instruction. */
1636 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1637 global, spill_reg_order);
1639 /* If a no-op set needs more than one reload, this is likely
1640 to be something that needs input address reloads. We
1641 can't get rid of this cleanly later, and it is of no use
1642 anyway, so discard it now.
1643 We only do this when expensive_optimizations is enabled,
1644 since this complements reload inheritance / output
1645 reload deletion, and it can make debugging harder. */
1646 if (flag_expensive_optimizations && n_reloads > 1)
1648 rtx set = single_set (insn);
1651 ((SET_SRC (set) == SET_DEST (set)
1652 && REG_P (SET_SRC (set))
1653 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1654 || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1655 && reg_renumber[REGNO (SET_SRC (set))] < 0
1656 && reg_renumber[REGNO (SET_DEST (set))] < 0
1657 && reg_equiv_memory_loc[REGNO (SET_SRC (set))] != NULL
1658 && reg_equiv_memory_loc[REGNO (SET_DEST (set))] != NULL
1659 && rtx_equal_p (reg_equiv_memory_loc
1660 [REGNO (SET_SRC (set))],
1661 reg_equiv_memory_loc
1662 [REGNO (SET_DEST (set))]))))
1664 if (ira_conflicts_p)
1665 /* Inform IRA about the insn deletion. */
1666 ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1667 REGNO (SET_SRC (set)));
1669 /* Delete it from the reload chain. */
1671 chain->prev->next = next;
1673 reload_insn_chain = next;
1675 next->prev = chain->prev;
1676 chain->next = unused_insn_chains;
1677 unused_insn_chains = chain;
1682 update_eliminable_offsets ();
1684 /* Remember for later shortcuts which insns had any reloads or
1685 register eliminations. */
1686 chain->need_elim = did_elimination;
1687 chain->need_reload = n_reloads > 0;
1688 chain->need_operand_change = operands_changed;
1690 /* Discard any register replacements done. */
1691 if (did_elimination)
1693 obstack_free (&reload_obstack, reload_insn_firstobj);
1694 PATTERN (insn) = old_body;
1695 INSN_CODE (insn) = old_code;
1696 REG_NOTES (insn) = old_notes;
1697 something_needs_elimination = 1;
1700 something_needs_operands_changed |= operands_changed;
1704 copy_reloads (chain);
1705 *pprev_reload = chain;
1706 pprev_reload = &chain->next_need_reload;
1713 /* Comparison function for qsort to decide which of two reloads
1714 should be handled first. *P1 and *P2 are the reload numbers. */
1717 reload_reg_class_lower (const void *r1p, const void *r2p)
1719 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1722 /* Consider required reloads before optional ones. */
1723 t = rld[r1].optional - rld[r2].optional;
1727 /* Count all solitary classes before non-solitary ones. */
1728 t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1729 - (reg_class_size[(int) rld[r1].rclass] == 1));
1733 /* Aside from solitaires, consider all multi-reg groups first. */
1734 t = rld[r2].nregs - rld[r1].nregs;
1738 /* Consider reloads in order of increasing reg-class number. */
1739 t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1743 /* If reloads are equally urgent, sort by reload number,
1744 so that the results of qsort leave nothing to chance. */
1748 /* The cost of spilling each hard reg. */
1749 static int spill_cost[FIRST_PSEUDO_REGISTER];
1751 /* When spilling multiple hard registers, we use SPILL_COST for the first
1752 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1753 only the first hard reg for a multi-reg pseudo. */
1754 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1756 /* Map of hard regno to pseudo regno currently occupying the hard
1758 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1760 /* Update the spill cost arrays, considering that pseudo REG is live. */
1763 count_pseudo (int reg)
1765 int freq = REG_FREQ (reg);
1766 int r = reg_renumber[reg];
1769 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1770 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1771 /* Ignore spilled pseudo-registers which can be here only if IRA
1773 || (ira_conflicts_p && r < 0))
1776 SET_REGNO_REG_SET (&pseudos_counted, reg);
1778 gcc_assert (r >= 0);
1780 spill_add_cost[r] += freq;
1781 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1784 hard_regno_to_pseudo_regno[r + nregs] = reg;
1785 spill_cost[r + nregs] += freq;
1789 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1790 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1793 order_regs_for_reload (struct insn_chain *chain)
1796 HARD_REG_SET used_by_pseudos;
1797 HARD_REG_SET used_by_pseudos2;
1798 reg_set_iterator rsi;
1800 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1802 memset (spill_cost, 0, sizeof spill_cost);
1803 memset (spill_add_cost, 0, sizeof spill_add_cost);
1804 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1805 hard_regno_to_pseudo_regno[i] = -1;
1807 /* Count number of uses of each hard reg by pseudo regs allocated to it
1808 and then order them by decreasing use. First exclude hard registers
1809 that are live in or across this insn. */
1811 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1812 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1813 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1814 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1816 /* Now find out which pseudos are allocated to it, and update
1818 CLEAR_REG_SET (&pseudos_counted);
1820 EXECUTE_IF_SET_IN_REG_SET
1821 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1825 EXECUTE_IF_SET_IN_REG_SET
1826 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1830 CLEAR_REG_SET (&pseudos_counted);
1833 /* Vector of reload-numbers showing the order in which the reloads should
1835 static short reload_order[MAX_RELOADS];
1837 /* This is used to keep track of the spill regs used in one insn. */
1838 static HARD_REG_SET used_spill_regs_local;
1840 /* We decided to spill hard register SPILLED, which has a size of
1841 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1842 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1843 update SPILL_COST/SPILL_ADD_COST. */
1846 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1848 int freq = REG_FREQ (reg);
1849 int r = reg_renumber[reg];
1850 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1852 /* Ignore spilled pseudo-registers which can be here only if IRA is
1854 if ((ira_conflicts_p && r < 0)
1855 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1856 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1859 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1861 spill_add_cost[r] -= freq;
1864 hard_regno_to_pseudo_regno[r + nregs] = -1;
1865 spill_cost[r + nregs] -= freq;
1869 /* Find reload register to use for reload number ORDER. */
1872 find_reg (struct insn_chain *chain, int order)
1874 int rnum = reload_order[order];
1875 struct reload *rl = rld + rnum;
1876 int best_cost = INT_MAX;
1878 unsigned int i, j, n;
1880 HARD_REG_SET not_usable;
1881 HARD_REG_SET used_by_other_reload;
1882 reg_set_iterator rsi;
1883 static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1884 static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1886 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1887 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1888 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
1890 CLEAR_HARD_REG_SET (used_by_other_reload);
1891 for (k = 0; k < order; k++)
1893 int other = reload_order[k];
1895 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1896 for (j = 0; j < rld[other].nregs; j++)
1897 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1900 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1902 #ifdef REG_ALLOC_ORDER
1903 unsigned int regno = reg_alloc_order[i];
1905 unsigned int regno = i;
1908 if (! TEST_HARD_REG_BIT (not_usable, regno)
1909 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1910 && HARD_REGNO_MODE_OK (regno, rl->mode))
1912 int this_cost = spill_cost[regno];
1914 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1916 for (j = 1; j < this_nregs; j++)
1918 this_cost += spill_add_cost[regno + j];
1919 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1920 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1926 if (ira_conflicts_p)
1928 /* Ask IRA to find a better pseudo-register for
1930 for (n = j = 0; j < this_nregs; j++)
1932 int r = hard_regno_to_pseudo_regno[regno + j];
1936 if (n == 0 || regno_pseudo_regs[n - 1] != r)
1937 regno_pseudo_regs[n++] = r;
1939 regno_pseudo_regs[n++] = -1;
1941 || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1942 best_regno_pseudo_regs,
1949 best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1950 if (regno_pseudo_regs[j] < 0)
1957 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1959 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1961 if (this_cost < best_cost
1962 /* Among registers with equal cost, prefer caller-saved ones, or
1963 use REG_ALLOC_ORDER if it is defined. */
1964 || (this_cost == best_cost
1965 #ifdef REG_ALLOC_ORDER
1966 && (inv_reg_alloc_order[regno]
1967 < inv_reg_alloc_order[best_reg])
1969 && call_used_regs[regno]
1970 && ! call_used_regs[best_reg]
1975 best_cost = this_cost;
1983 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1985 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1986 rl->regno = best_reg;
1988 EXECUTE_IF_SET_IN_REG_SET
1989 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1991 count_spilled_pseudo (best_reg, rl->nregs, j);
1994 EXECUTE_IF_SET_IN_REG_SET
1995 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1997 count_spilled_pseudo (best_reg, rl->nregs, j);
2000 for (i = 0; i < rl->nregs; i++)
2002 gcc_assert (spill_cost[best_reg + i] == 0);
2003 gcc_assert (spill_add_cost[best_reg + i] == 0);
2004 gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
2005 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
2010 /* Find more reload regs to satisfy the remaining need of an insn, which
2012 Do it by ascending class number, since otherwise a reg
2013 might be spilled for a big class and might fail to count
2014 for a smaller class even though it belongs to that class. */
2017 find_reload_regs (struct insn_chain *chain)
2021 /* In order to be certain of getting the registers we need,
2022 we must sort the reloads into order of increasing register class.
2023 Then our grabbing of reload registers will parallel the process
2024 that provided the reload registers. */
2025 for (i = 0; i < chain->n_reloads; i++)
2027 /* Show whether this reload already has a hard reg. */
2028 if (chain->rld[i].reg_rtx)
2030 int regno = REGNO (chain->rld[i].reg_rtx);
2031 chain->rld[i].regno = regno;
2033 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
2036 chain->rld[i].regno = -1;
2037 reload_order[i] = i;
2040 n_reloads = chain->n_reloads;
2041 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
2043 CLEAR_HARD_REG_SET (used_spill_regs_local);
2046 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
2048 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
2050 /* Compute the order of preference for hard registers to spill. */
2052 order_regs_for_reload (chain);
2054 for (i = 0; i < n_reloads; i++)
2056 int r = reload_order[i];
2058 /* Ignore reloads that got marked inoperative. */
2059 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
2060 && ! rld[r].optional
2061 && rld[r].regno == -1)
2062 if (! find_reg (chain, i))
2065 fprintf (dump_file, "reload failure for reload %d\n", r);
2066 spill_failure (chain->insn, rld[r].rclass);
2072 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
2073 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
2075 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2079 select_reload_regs (void)
2081 struct insn_chain *chain;
2083 /* Try to satisfy the needs for each insn. */
2084 for (chain = insns_need_reload; chain != 0;
2085 chain = chain->next_need_reload)
2086 find_reload_regs (chain);
2089 /* Delete all insns that were inserted by emit_caller_save_insns during
2092 delete_caller_save_insns (void)
2094 struct insn_chain *c = reload_insn_chain;
2098 while (c != 0 && c->is_caller_save_insn)
2100 struct insn_chain *next = c->next;
2103 if (c == reload_insn_chain)
2104 reload_insn_chain = next;
2108 next->prev = c->prev;
2110 c->prev->next = next;
2111 c->next = unused_insn_chains;
2112 unused_insn_chains = c;
2120 /* Handle the failure to find a register to spill.
2121 INSN should be one of the insns which needed this particular spill reg. */
2124 spill_failure (rtx insn, enum reg_class rclass)
2126 if (asm_noperands (PATTERN (insn)) >= 0)
2127 error_for_asm (insn, "can't find a register in class %qs while "
2128 "reloading %<asm%>",
2129 reg_class_names[rclass]);
2132 error ("unable to find a register to spill in class %qs",
2133 reg_class_names[rclass]);
2137 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2138 debug_reload_to_stream (dump_file);
2140 fatal_insn ("this is the insn:", insn);
2144 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2145 data that is dead in INSN. */
2148 delete_dead_insn (rtx insn)
2150 rtx prev = prev_real_insn (insn);
2153 /* If the previous insn sets a register that dies in our insn, delete it
2155 if (prev && GET_CODE (PATTERN (prev)) == SET
2156 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2157 && reg_mentioned_p (prev_dest, PATTERN (insn))
2158 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2159 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2160 delete_dead_insn (prev);
2162 SET_INSN_DELETED (insn);
2165 /* Modify the home of pseudo-reg I.
2166 The new home is present in reg_renumber[I].
2168 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2169 or it may be -1, meaning there is none or it is not relevant.
2170 This is used so that all pseudos spilled from a given hard reg
2171 can share one stack slot. */
2174 alter_reg (int i, int from_reg, bool dont_share_p)
2176 /* When outputting an inline function, this can happen
2177 for a reg that isn't actually used. */
2178 if (regno_reg_rtx[i] == 0)
2181 /* If the reg got changed to a MEM at rtl-generation time,
2183 if (!REG_P (regno_reg_rtx[i]))
2186 /* Modify the reg-rtx to contain the new hard reg
2187 number or else to contain its pseudo reg number. */
2188 SET_REGNO (regno_reg_rtx[i],
2189 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2191 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2192 allocate a stack slot for it. */
2194 if (reg_renumber[i] < 0
2195 && REG_N_REFS (i) > 0
2196 && reg_equiv_constant[i] == 0
2197 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
2198 && reg_equiv_memory_loc[i] == 0)
2201 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2202 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2203 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2204 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2205 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2208 if (ira_conflicts_p)
2210 /* Mark the spill for IRA. */
2211 SET_REGNO_REG_SET (&spilled_pseudos, i);
2213 x = ira_reuse_stack_slot (i, inherent_size, total_size);
2219 /* Each pseudo reg has an inherent size which comes from its own mode,
2220 and a total size which provides room for paradoxical subregs
2221 which refer to the pseudo reg in wider modes.
2223 We can use a slot already allocated if it provides both
2224 enough inherent space and enough total space.
2225 Otherwise, we allocate a new slot, making sure that it has no less
2226 inherent space, and no less total space, then the previous slot. */
2227 else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
2231 /* No known place to spill from => no slot to reuse. */
2232 x = assign_stack_local (mode, total_size,
2233 min_align > inherent_align
2234 || total_size > inherent_size ? -1 : 0);
2238 /* Cancel the big-endian correction done in assign_stack_local.
2239 Get the address of the beginning of the slot. This is so we
2240 can do a big-endian correction unconditionally below. */
2241 if (BYTES_BIG_ENDIAN)
2243 adjust = inherent_size - total_size;
2246 = adjust_address_nv (x, mode_for_size (total_size
2252 if (! dont_share_p && ira_conflicts_p)
2253 /* Inform IRA about allocation a new stack slot. */
2254 ira_mark_new_stack_slot (stack_slot, i, total_size);
2257 /* Reuse a stack slot if possible. */
2258 else if (spill_stack_slot[from_reg] != 0
2259 && spill_stack_slot_width[from_reg] >= total_size
2260 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2262 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2263 x = spill_stack_slot[from_reg];
2265 /* Allocate a bigger slot. */
2268 /* Compute maximum size needed, both for inherent size
2269 and for total size. */
2272 if (spill_stack_slot[from_reg])
2274 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2276 mode = GET_MODE (spill_stack_slot[from_reg]);
2277 if (spill_stack_slot_width[from_reg] > total_size)
2278 total_size = spill_stack_slot_width[from_reg];
2279 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2280 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2283 /* Make a slot with that size. */
2284 x = assign_stack_local (mode, total_size,
2285 min_align > inherent_align
2286 || total_size > inherent_size ? -1 : 0);
2289 /* Cancel the big-endian correction done in assign_stack_local.
2290 Get the address of the beginning of the slot. This is so we
2291 can do a big-endian correction unconditionally below. */
2292 if (BYTES_BIG_ENDIAN)
2294 adjust = GET_MODE_SIZE (mode) - total_size;
2297 = adjust_address_nv (x, mode_for_size (total_size
2303 spill_stack_slot[from_reg] = stack_slot;
2304 spill_stack_slot_width[from_reg] = total_size;
2307 /* On a big endian machine, the "address" of the slot
2308 is the address of the low part that fits its inherent mode. */
2309 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2310 adjust += (total_size - inherent_size);
2312 /* If we have any adjustment to make, or if the stack slot is the
2313 wrong mode, make a new stack slot. */
2314 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2316 /* Set all of the memory attributes as appropriate for a spill. */
2317 set_mem_attrs_for_spill (x);
2319 /* Save the stack slot for later. */
2320 reg_equiv_memory_loc[i] = x;
2324 /* Mark the slots in regs_ever_live for the hard regs used by
2325 pseudo-reg number REGNO, accessed in MODE. */
2328 mark_home_live_1 (int regno, enum machine_mode mode)
2332 i = reg_renumber[regno];
2335 lim = end_hard_regno (mode, i);
2337 df_set_regs_ever_live(i++, true);
2340 /* Mark the slots in regs_ever_live for the hard regs
2341 used by pseudo-reg number REGNO. */
2344 mark_home_live (int regno)
2346 if (reg_renumber[regno] >= 0)
2347 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2350 /* This function handles the tracking of elimination offsets around branches.
2352 X is a piece of RTL being scanned.
2354 INSN is the insn that it came from, if any.
2356 INITIAL_P is nonzero if we are to set the offset to be the initial
2357 offset and zero if we are setting the offset of the label to be the
2361 set_label_offsets (rtx x, rtx insn, int initial_p)
2363 enum rtx_code code = GET_CODE (x);
2366 struct elim_table *p;
2371 if (LABEL_REF_NONLOCAL_P (x))
2376 /* ... fall through ... */
2379 /* If we know nothing about this label, set the desired offsets. Note
2380 that this sets the offset at a label to be the offset before a label
2381 if we don't know anything about the label. This is not correct for
2382 the label after a BARRIER, but is the best guess we can make. If
2383 we guessed wrong, we will suppress an elimination that might have
2384 been possible had we been able to guess correctly. */
2386 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2388 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2389 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2390 = (initial_p ? reg_eliminate[i].initial_offset
2391 : reg_eliminate[i].offset);
2392 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2395 /* Otherwise, if this is the definition of a label and it is
2396 preceded by a BARRIER, set our offsets to the known offset of
2400 && (tem = prev_nonnote_insn (insn)) != 0
2402 set_offsets_for_label (insn);
2404 /* If neither of the above cases is true, compare each offset
2405 with those previously recorded and suppress any eliminations
2406 where the offsets disagree. */
2408 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2409 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2410 != (initial_p ? reg_eliminate[i].initial_offset
2411 : reg_eliminate[i].offset))
2412 reg_eliminate[i].can_eliminate = 0;
2417 set_label_offsets (PATTERN (insn), insn, initial_p);
2419 /* ... fall through ... */
2423 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2424 to indirectly and hence must have all eliminations at their
2426 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2427 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2428 set_label_offsets (XEXP (tem, 0), insn, 1);
2434 /* Each of the labels in the parallel or address vector must be
2435 at their initial offsets. We want the first field for PARALLEL
2436 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2438 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2439 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2444 /* We only care about setting PC. If the source is not RETURN,
2445 IF_THEN_ELSE, or a label, disable any eliminations not at
2446 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2447 isn't one of those possibilities. For branches to a label,
2448 call ourselves recursively.
2450 Note that this can disable elimination unnecessarily when we have
2451 a non-local goto since it will look like a non-constant jump to
2452 someplace in the current function. This isn't a significant
2453 problem since such jumps will normally be when all elimination
2454 pairs are back to their initial offsets. */
2456 if (SET_DEST (x) != pc_rtx)
2459 switch (GET_CODE (SET_SRC (x)))
2466 set_label_offsets (SET_SRC (x), insn, initial_p);
2470 tem = XEXP (SET_SRC (x), 1);
2471 if (GET_CODE (tem) == LABEL_REF)
2472 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2473 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2476 tem = XEXP (SET_SRC (x), 2);
2477 if (GET_CODE (tem) == LABEL_REF)
2478 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2479 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2487 /* If we reach here, all eliminations must be at their initial
2488 offset because we are doing a jump to a variable address. */
2489 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2490 if (p->offset != p->initial_offset)
2491 p->can_eliminate = 0;
2499 /* Scan X and replace any eliminable registers (such as fp) with a
2500 replacement (such as sp), plus an offset.
2502 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2503 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2504 MEM, we are allowed to replace a sum of a register and the constant zero
2505 with the register, which we cannot do outside a MEM. In addition, we need
2506 to record the fact that a register is referenced outside a MEM.
2508 If INSN is an insn, it is the insn containing X. If we replace a REG
2509 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2510 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2511 the REG is being modified.
2513 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2514 That's used when we eliminate in expressions stored in notes.
2515 This means, do not set ref_outside_mem even if the reference
2518 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2519 replacements done assuming all offsets are at their initial values. If
2520 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2521 encounter, return the actual location so that find_reloads will do
2522 the proper thing. */
2525 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2526 bool may_use_invariant)
2528 enum rtx_code code = GET_CODE (x);
2529 struct elim_table *ep;
2536 if (! current_function_decl)
2559 /* First handle the case where we encounter a bare register that
2560 is eliminable. Replace it with a PLUS. */
2561 if (regno < FIRST_PSEUDO_REGISTER)
2563 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2565 if (ep->from_rtx == x && ep->can_eliminate)
2566 return plus_constant (ep->to_rtx, ep->previous_offset);
2569 else if (reg_renumber && reg_renumber[regno] < 0
2570 && reg_equiv_invariant && reg_equiv_invariant[regno])
2572 if (may_use_invariant)
2573 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2574 mem_mode, insn, true);
2575 /* There exists at least one use of REGNO that cannot be
2576 eliminated. Prevent the defining insn from being deleted. */
2577 reg_equiv_init[regno] = NULL_RTX;
2578 alter_reg (regno, -1, true);
2582 /* You might think handling MINUS in a manner similar to PLUS is a
2583 good idea. It is not. It has been tried multiple times and every
2584 time the change has had to have been reverted.
2586 Other parts of reload know a PLUS is special (gen_reload for example)
2587 and require special code to handle code a reloaded PLUS operand.
2589 Also consider backends where the flags register is clobbered by a
2590 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2591 lea instruction comes to mind). If we try to reload a MINUS, we
2592 may kill the flags register that was holding a useful value.
2594 So, please before trying to handle MINUS, consider reload as a
2595 whole instead of this little section as well as the backend issues. */
2597 /* If this is the sum of an eliminable register and a constant, rework
2599 if (REG_P (XEXP (x, 0))
2600 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2601 && CONSTANT_P (XEXP (x, 1)))
2603 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2605 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2607 /* The only time we want to replace a PLUS with a REG (this
2608 occurs when the constant operand of the PLUS is the negative
2609 of the offset) is when we are inside a MEM. We won't want
2610 to do so at other times because that would change the
2611 structure of the insn in a way that reload can't handle.
2612 We special-case the commonest situation in
2613 eliminate_regs_in_insn, so just replace a PLUS with a
2614 PLUS here, unless inside a MEM. */
2615 if (mem_mode != 0 && CONST_INT_P (XEXP (x, 1))
2616 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2619 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2620 plus_constant (XEXP (x, 1),
2621 ep->previous_offset));
2624 /* If the register is not eliminable, we are done since the other
2625 operand is a constant. */
2629 /* If this is part of an address, we want to bring any constant to the
2630 outermost PLUS. We will do this by doing register replacement in
2631 our operands and seeing if a constant shows up in one of them.
2633 Note that there is no risk of modifying the structure of the insn,
2634 since we only get called for its operands, thus we are either
2635 modifying the address inside a MEM, or something like an address
2636 operand of a load-address insn. */
2639 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2640 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2642 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2644 /* If one side is a PLUS and the other side is a pseudo that
2645 didn't get a hard register but has a reg_equiv_constant,
2646 we must replace the constant here since it may no longer
2647 be in the position of any operand. */
2648 if (GET_CODE (new0) == PLUS && REG_P (new1)
2649 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2650 && reg_renumber[REGNO (new1)] < 0
2651 && reg_equiv_constant != 0
2652 && reg_equiv_constant[REGNO (new1)] != 0)
2653 new1 = reg_equiv_constant[REGNO (new1)];
2654 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2655 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2656 && reg_renumber[REGNO (new0)] < 0
2657 && reg_equiv_constant[REGNO (new0)] != 0)
2658 new0 = reg_equiv_constant[REGNO (new0)];
2660 new_rtx = form_sum (new0, new1);
2662 /* As above, if we are not inside a MEM we do not want to
2663 turn a PLUS into something else. We might try to do so here
2664 for an addition of 0 if we aren't optimizing. */
2665 if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2666 return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2674 /* If this is the product of an eliminable register and a
2675 constant, apply the distribute law and move the constant out
2676 so that we have (plus (mult ..) ..). This is needed in order
2677 to keep load-address insns valid. This case is pathological.
2678 We ignore the possibility of overflow here. */
2679 if (REG_P (XEXP (x, 0))
2680 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2681 && CONST_INT_P (XEXP (x, 1)))
2682 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2684 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2687 /* Refs inside notes don't count for this purpose. */
2688 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2689 || GET_CODE (insn) == INSN_LIST)))
2690 ep->ref_outside_mem = 1;
2693 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2694 ep->previous_offset * INTVAL (XEXP (x, 1)));
2697 /* ... fall through ... */
2701 /* See comments before PLUS about handling MINUS. */
2703 case DIV: case UDIV:
2704 case MOD: case UMOD:
2705 case AND: case IOR: case XOR:
2706 case ROTATERT: case ROTATE:
2707 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2709 case GE: case GT: case GEU: case GTU:
2710 case LE: case LT: case LEU: case LTU:
2712 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2713 rtx new1 = XEXP (x, 1)
2714 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2716 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2717 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2722 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2725 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2726 if (new_rtx != XEXP (x, 0))
2728 /* If this is a REG_DEAD note, it is not valid anymore.
2729 Using the eliminated version could result in creating a
2730 REG_DEAD note for the stack or frame pointer. */
2731 if (REG_NOTE_KIND (x) == REG_DEAD)
2733 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2736 x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2740 /* ... fall through ... */
2743 /* Now do eliminations in the rest of the chain. If this was
2744 an EXPR_LIST, this might result in allocating more memory than is
2745 strictly needed, but it simplifies the code. */
2748 new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2749 if (new_rtx != XEXP (x, 1))
2751 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2759 /* We do not support elimination of a register that is modified.
2760 elimination_effects has already make sure that this does not
2766 /* We do not support elimination of a register that is modified.
2767 elimination_effects has already make sure that this does not
2768 happen. The only remaining case we need to consider here is
2769 that the increment value may be an eliminable register. */
2770 if (GET_CODE (XEXP (x, 1)) == PLUS
2771 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2773 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2776 if (new_rtx != XEXP (XEXP (x, 1), 1))
2777 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2778 gen_rtx_PLUS (GET_MODE (x),
2779 XEXP (x, 0), new_rtx));
2783 case STRICT_LOW_PART:
2785 case SIGN_EXTEND: case ZERO_EXTEND:
2786 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2787 case FLOAT: case FIX:
2788 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2797 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2798 if (new_rtx != XEXP (x, 0))
2799 return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2803 /* Similar to above processing, but preserve SUBREG_BYTE.
2804 Convert (subreg (mem)) to (mem) if not paradoxical.
2805 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2806 pseudo didn't get a hard reg, we must replace this with the
2807 eliminated version of the memory location because push_reload
2808 may do the replacement in certain circumstances. */
2809 if (REG_P (SUBREG_REG (x))
2810 && (GET_MODE_SIZE (GET_MODE (x))
2811 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2812 && reg_equiv_memory_loc != 0
2813 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2815 new_rtx = SUBREG_REG (x);
2818 new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2820 if (new_rtx != SUBREG_REG (x))
2822 int x_size = GET_MODE_SIZE (GET_MODE (x));
2823 int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2826 && ((x_size < new_size
2827 #ifdef WORD_REGISTER_OPERATIONS
2828 /* On these machines, combine can create rtl of the form
2829 (set (subreg:m1 (reg:m2 R) 0) ...)
2830 where m1 < m2, and expects something interesting to
2831 happen to the entire word. Moreover, it will use the
2832 (reg:m2 R) later, expecting all bits to be preserved.
2833 So if the number of words is the same, preserve the
2834 subreg so that push_reload can see it. */
2835 && ! ((x_size - 1) / UNITS_PER_WORD
2836 == (new_size -1 ) / UNITS_PER_WORD)
2839 || x_size == new_size)
2841 return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2843 return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2849 /* Our only special processing is to pass the mode of the MEM to our
2850 recursive call and copy the flags. While we are here, handle this
2851 case more efficiently. */
2853 replace_equiv_address_nv (x,
2854 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2858 /* Handle insn_list USE that a call to a pure function may generate. */
2859 new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false);
2860 if (new_rtx != XEXP (x, 0))
2861 return gen_rtx_USE (GET_MODE (x), new_rtx);
2873 /* Process each of our operands recursively. If any have changed, make a
2875 fmt = GET_RTX_FORMAT (code);
2876 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2880 new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2881 if (new_rtx != XEXP (x, i) && ! copied)
2883 x = shallow_copy_rtx (x);
2886 XEXP (x, i) = new_rtx;
2888 else if (*fmt == 'E')
2891 for (j = 0; j < XVECLEN (x, i); j++)
2893 new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2894 if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2896 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2900 x = shallow_copy_rtx (x);
2903 XVEC (x, i) = new_v;
2906 XVECEXP (x, i, j) = new_rtx;
2915 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2917 return eliminate_regs_1 (x, mem_mode, insn, false);
2920 /* Scan rtx X for modifications of elimination target registers. Update
2921 the table of eliminables to reflect the changed state. MEM_MODE is
2922 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2925 elimination_effects (rtx x, enum machine_mode mem_mode)
2927 enum rtx_code code = GET_CODE (x);
2928 struct elim_table *ep;
2953 /* First handle the case where we encounter a bare register that
2954 is eliminable. Replace it with a PLUS. */
2955 if (regno < FIRST_PSEUDO_REGISTER)
2957 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2959 if (ep->from_rtx == x && ep->can_eliminate)
2962 ep->ref_outside_mem = 1;
2967 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2968 && reg_equiv_constant[regno]
2969 && ! function_invariant_p (reg_equiv_constant[regno]))
2970 elimination_effects (reg_equiv_constant[regno], mem_mode);
2979 /* If we modify the source of an elimination rule, disable it. */
2980 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2981 if (ep->from_rtx == XEXP (x, 0))
2982 ep->can_eliminate = 0;
2984 /* If we modify the target of an elimination rule by adding a constant,
2985 update its offset. If we modify the target in any other way, we'll
2986 have to disable the rule as well. */
2987 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2988 if (ep->to_rtx == XEXP (x, 0))
2990 int size = GET_MODE_SIZE (mem_mode);
2992 /* If more bytes than MEM_MODE are pushed, account for them. */
2993 #ifdef PUSH_ROUNDING
2994 if (ep->to_rtx == stack_pointer_rtx)
2995 size = PUSH_ROUNDING (size);
2997 if (code == PRE_DEC || code == POST_DEC)
2999 else if (code == PRE_INC || code == POST_INC)
3001 else if (code == PRE_MODIFY || code == POST_MODIFY)
3003 if (GET_CODE (XEXP (x, 1)) == PLUS
3004 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
3005 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
3006 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
3008 ep->can_eliminate = 0;
3012 /* These two aren't unary operators. */
3013 if (code == POST_MODIFY || code == PRE_MODIFY)
3016 /* Fall through to generic unary operation case. */
3017 case STRICT_LOW_PART:
3019 case SIGN_EXTEND: case ZERO_EXTEND:
3020 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3021 case FLOAT: case FIX:
3022 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3031 elimination_effects (XEXP (x, 0), mem_mode);
3035 if (REG_P (SUBREG_REG (x))
3036 && (GET_MODE_SIZE (GET_MODE (x))
3037 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3038 && reg_equiv_memory_loc != 0
3039 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
3042 elimination_effects (SUBREG_REG (x), mem_mode);
3046 /* If using a register that is the source of an eliminate we still
3047 think can be performed, note it cannot be performed since we don't
3048 know how this register is used. */
3049 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3050 if (ep->from_rtx == XEXP (x, 0))
3051 ep->can_eliminate = 0;
3053 elimination_effects (XEXP (x, 0), mem_mode);
3057 /* If clobbering a register that is the replacement register for an
3058 elimination we still think can be performed, note that it cannot
3059 be performed. Otherwise, we need not be concerned about it. */
3060 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3061 if (ep->to_rtx == XEXP (x, 0))
3062 ep->can_eliminate = 0;
3064 elimination_effects (XEXP (x, 0), mem_mode);
3068 /* Check for setting a register that we know about. */
3069 if (REG_P (SET_DEST (x)))
3071 /* See if this is setting the replacement register for an
3074 If DEST is the hard frame pointer, we do nothing because we
3075 assume that all assignments to the frame pointer are for
3076 non-local gotos and are being done at a time when they are valid
3077 and do not disturb anything else. Some machines want to
3078 eliminate a fake argument pointer (or even a fake frame pointer)
3079 with either the real frame or the stack pointer. Assignments to
3080 the hard frame pointer must not prevent this elimination. */
3082 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3084 if (ep->to_rtx == SET_DEST (x)
3085 && SET_DEST (x) != hard_frame_pointer_rtx)
3087 /* If it is being incremented, adjust the offset. Otherwise,
3088 this elimination can't be done. */
3089 rtx src = SET_SRC (x);
3091 if (GET_CODE (src) == PLUS
3092 && XEXP (src, 0) == SET_DEST (x)
3093 && CONST_INT_P (XEXP (src, 1)))
3094 ep->offset -= INTVAL (XEXP (src, 1));
3096 ep->can_eliminate = 0;
3100 elimination_effects (SET_DEST (x), VOIDmode);
3101 elimination_effects (SET_SRC (x), VOIDmode);
3105 /* Our only special processing is to pass the mode of the MEM to our
3107 elimination_effects (XEXP (x, 0), GET_MODE (x));
3114 fmt = GET_RTX_FORMAT (code);
3115 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3118 elimination_effects (XEXP (x, i), mem_mode);
3119 else if (*fmt == 'E')
3120 for (j = 0; j < XVECLEN (x, i); j++)
3121 elimination_effects (XVECEXP (x, i, j), mem_mode);
3125 /* Descend through rtx X and verify that no references to eliminable registers
3126 remain. If any do remain, mark the involved register as not
3130 check_eliminable_occurrences (rtx x)
3139 code = GET_CODE (x);
3141 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3143 struct elim_table *ep;
3145 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3146 if (ep->from_rtx == x)
3147 ep->can_eliminate = 0;
3151 fmt = GET_RTX_FORMAT (code);
3152 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3155 check_eliminable_occurrences (XEXP (x, i));
3156 else if (*fmt == 'E')
3159 for (j = 0; j < XVECLEN (x, i); j++)
3160 check_eliminable_occurrences (XVECEXP (x, i, j));
3165 /* Scan INSN and eliminate all eliminable registers in it.
3167 If REPLACE is nonzero, do the replacement destructively. Also
3168 delete the insn as dead it if it is setting an eliminable register.
3170 If REPLACE is zero, do all our allocations in reload_obstack.
3172 If no eliminations were done and this insn doesn't require any elimination
3173 processing (these are not identical conditions: it might be updating sp,
3174 but not referencing fp; this needs to be seen during reload_as_needed so
3175 that the offset between fp and sp can be taken into consideration), zero
3176 is returned. Otherwise, 1 is returned. */
3179 eliminate_regs_in_insn (rtx insn, int replace)
3181 int icode = recog_memoized (insn);
3182 rtx old_body = PATTERN (insn);
3183 int insn_is_asm = asm_noperands (old_body) >= 0;
3184 rtx old_set = single_set (insn);
3188 rtx substed_operand[MAX_RECOG_OPERANDS];
3189 rtx orig_operand[MAX_RECOG_OPERANDS];
3190 struct elim_table *ep;
3191 rtx plus_src, plus_cst_src;
3193 if (! insn_is_asm && icode < 0)
3195 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3196 || GET_CODE (PATTERN (insn)) == CLOBBER
3197 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3198 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3199 || GET_CODE (PATTERN (insn)) == ASM_INPUT
3200 || DEBUG_INSN_P (insn));
3204 if (old_set != 0 && REG_P (SET_DEST (old_set))
3205 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3207 /* Check for setting an eliminable register. */
3208 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3209 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3211 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3212 /* If this is setting the frame pointer register to the
3213 hardware frame pointer register and this is an elimination
3214 that will be done (tested above), this insn is really
3215 adjusting the frame pointer downward to compensate for
3216 the adjustment done before a nonlocal goto. */
3217 if (ep->from == FRAME_POINTER_REGNUM
3218 && ep->to == HARD_FRAME_POINTER_REGNUM)
3220 rtx base = SET_SRC (old_set);
3221 rtx base_insn = insn;
3222 HOST_WIDE_INT offset = 0;
3224 while (base != ep->to_rtx)
3226 rtx prev_insn, prev_set;
3228 if (GET_CODE (base) == PLUS
3229 && CONST_INT_P (XEXP (base, 1)))
3231 offset += INTVAL (XEXP (base, 1));
3232 base = XEXP (base, 0);
3234 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3235 && (prev_set = single_set (prev_insn)) != 0
3236 && rtx_equal_p (SET_DEST (prev_set), base))
3238 base = SET_SRC (prev_set);
3239 base_insn = prev_insn;
3245 if (base == ep->to_rtx)
3248 = plus_constant (ep->to_rtx, offset - ep->offset);
3250 new_body = old_body;
3253 new_body = copy_insn (old_body);
3254 if (REG_NOTES (insn))
3255 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3257 PATTERN (insn) = new_body;
3258 old_set = single_set (insn);
3260 /* First see if this insn remains valid when we
3261 make the change. If not, keep the INSN_CODE
3262 the same and let reload fit it up. */
3263 validate_change (insn, &SET_SRC (old_set), src, 1);
3264 validate_change (insn, &SET_DEST (old_set),
3266 if (! apply_change_group ())
3268 SET_SRC (old_set) = src;
3269 SET_DEST (old_set) = ep->to_rtx;
3278 /* In this case this insn isn't serving a useful purpose. We
3279 will delete it in reload_as_needed once we know that this
3280 elimination is, in fact, being done.
3282 If REPLACE isn't set, we can't delete this insn, but needn't
3283 process it since it won't be used unless something changes. */
3286 delete_dead_insn (insn);
3294 /* We allow one special case which happens to work on all machines we
3295 currently support: a single set with the source or a REG_EQUAL
3296 note being a PLUS of an eliminable register and a constant. */
3297 plus_src = plus_cst_src = 0;
3298 if (old_set && REG_P (SET_DEST (old_set)))
3300 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3301 plus_src = SET_SRC (old_set);
3302 /* First see if the source is of the form (plus (...) CST). */
3304 && CONST_INT_P (XEXP (plus_src, 1)))
3305 plus_cst_src = plus_src;
3306 else if (REG_P (SET_SRC (old_set))
3309 /* Otherwise, see if we have a REG_EQUAL note of the form
3310 (plus (...) CST). */
3312 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3314 if ((REG_NOTE_KIND (links) == REG_EQUAL
3315 || REG_NOTE_KIND (links) == REG_EQUIV)
3316 && GET_CODE (XEXP (links, 0)) == PLUS
3317 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3319 plus_cst_src = XEXP (links, 0);
3325 /* Check that the first operand of the PLUS is a hard reg or
3326 the lowpart subreg of one. */
3329 rtx reg = XEXP (plus_cst_src, 0);
3330 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3331 reg = SUBREG_REG (reg);
3333 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3339 rtx reg = XEXP (plus_cst_src, 0);
3340 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3342 if (GET_CODE (reg) == SUBREG)
3343 reg = SUBREG_REG (reg);
3345 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3346 if (ep->from_rtx == reg && ep->can_eliminate)
3348 rtx to_rtx = ep->to_rtx;
3349 offset += ep->offset;
3350 offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
3352 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3353 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3355 /* If we have a nonzero offset, and the source is already
3356 a simple REG, the following transformation would
3357 increase the cost of the insn by replacing a simple REG
3358 with (plus (reg sp) CST). So try only when we already
3359 had a PLUS before. */
3360 if (offset == 0 || plus_src)
3362 rtx new_src = plus_constant (to_rtx, offset);
3364 new_body = old_body;
3367 new_body = copy_insn (old_body);
3368 if (REG_NOTES (insn))
3369 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3371 PATTERN (insn) = new_body;
3372 old_set = single_set (insn);
3374 /* First see if this insn remains valid when we make the
3375 change. If not, try to replace the whole pattern with
3376 a simple set (this may help if the original insn was a
3377 PARALLEL that was only recognized as single_set due to
3378 REG_UNUSED notes). If this isn't valid either, keep
3379 the INSN_CODE the same and let reload fix it up. */
3380 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3382 rtx new_pat = gen_rtx_SET (VOIDmode,
3383 SET_DEST (old_set), new_src);
3385 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3386 SET_SRC (old_set) = new_src;
3393 /* This can't have an effect on elimination offsets, so skip right
3399 /* Determine the effects of this insn on elimination offsets. */
3400 elimination_effects (old_body, VOIDmode);
3402 /* Eliminate all eliminable registers occurring in operands that
3403 can be handled by reload. */
3404 extract_insn (insn);
3405 for (i = 0; i < recog_data.n_operands; i++)
3407 orig_operand[i] = recog_data.operand[i];
3408 substed_operand[i] = recog_data.operand[i];
3410 /* For an asm statement, every operand is eliminable. */
3411 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3413 bool is_set_src, in_plus;
3415 /* Check for setting a register that we know about. */
3416 if (recog_data.operand_type[i] != OP_IN
3417 && REG_P (orig_operand[i]))
3419 /* If we are assigning to a register that can be eliminated, it
3420 must be as part of a PARALLEL, since the code above handles
3421 single SETs. We must indicate that we can no longer
3422 eliminate this reg. */
3423 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3425 if (ep->from_rtx == orig_operand[i])
3426 ep->can_eliminate = 0;
3429 /* Companion to the above plus substitution, we can allow
3430 invariants as the source of a plain move. */
3432 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3436 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3437 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3441 = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3442 replace ? insn : NULL_RTX,
3443 is_set_src || in_plus);
3444 if (substed_operand[i] != orig_operand[i])
3446 /* Terminate the search in check_eliminable_occurrences at
3448 *recog_data.operand_loc[i] = 0;
3450 /* If an output operand changed from a REG to a MEM and INSN is an
3451 insn, write a CLOBBER insn. */
3452 if (recog_data.operand_type[i] != OP_IN
3453 && REG_P (orig_operand[i])
3454 && MEM_P (substed_operand[i])
3456 emit_insn_after (gen_clobber (orig_operand[i]), insn);
3460 for (i = 0; i < recog_data.n_dups; i++)
3461 *recog_data.dup_loc[i]
3462 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3464 /* If any eliminable remain, they aren't eliminable anymore. */
3465 check_eliminable_occurrences (old_body);
3467 /* Substitute the operands; the new values are in the substed_operand
3469 for (i = 0; i < recog_data.n_operands; i++)
3470 *recog_data.operand_loc[i] = substed_operand[i];
3471 for (i = 0; i < recog_data.n_dups; i++)
3472 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3474 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3475 re-recognize the insn. We do this in case we had a simple addition
3476 but now can do this as a load-address. This saves an insn in this
3478 If re-recognition fails, the old insn code number will still be used,
3479 and some register operands may have changed into PLUS expressions.
3480 These will be handled by find_reloads by loading them into a register
3485 /* If we aren't replacing things permanently and we changed something,
3486 make another copy to ensure that all the RTL is new. Otherwise
3487 things can go wrong if find_reload swaps commutative operands
3488 and one is inside RTL that has been copied while the other is not. */
3489 new_body = old_body;
3492 new_body = copy_insn (old_body);
3493 if (REG_NOTES (insn))
3494 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3496 PATTERN (insn) = new_body;
3498 /* If we had a move insn but now we don't, rerecognize it. This will
3499 cause spurious re-recognition if the old move had a PARALLEL since
3500 the new one still will, but we can't call single_set without
3501 having put NEW_BODY into the insn and the re-recognition won't
3502 hurt in this rare case. */
3503 /* ??? Why this huge if statement - why don't we just rerecognize the
3507 && ((REG_P (SET_SRC (old_set))
3508 && (GET_CODE (new_body) != SET
3509 || !REG_P (SET_SRC (new_body))))
3510 /* If this was a load from or store to memory, compare
3511 the MEM in recog_data.operand to the one in the insn.
3512 If they are not equal, then rerecognize the insn. */
3514 && ((MEM_P (SET_SRC (old_set))
3515 && SET_SRC (old_set) != recog_data.operand[1])
3516 || (MEM_P (SET_DEST (old_set))
3517 && SET_DEST (old_set) != recog_data.operand[0])))
3518 /* If this was an add insn before, rerecognize. */
3519 || GET_CODE (SET_SRC (old_set)) == PLUS))
3521 int new_icode = recog (PATTERN (insn), insn, 0);
3523 INSN_CODE (insn) = new_icode;
3527 /* Restore the old body. If there were any changes to it, we made a copy
3528 of it while the changes were still in place, so we'll correctly return
3529 a modified insn below. */
3532 /* Restore the old body. */
3533 for (i = 0; i < recog_data.n_operands; i++)
3534 *recog_data.operand_loc[i] = orig_operand[i];
3535 for (i = 0; i < recog_data.n_dups; i++)
3536 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3539 /* Update all elimination pairs to reflect the status after the current
3540 insn. The changes we make were determined by the earlier call to
3541 elimination_effects.
3543 We also detect cases where register elimination cannot be done,
3544 namely, if a register would be both changed and referenced outside a MEM
3545 in the resulting insn since such an insn is often undefined and, even if
3546 not, we cannot know what meaning will be given to it. Note that it is
3547 valid to have a register used in an address in an insn that changes it
3548 (presumably with a pre- or post-increment or decrement).
3550 If anything changes, return nonzero. */
3552 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3554 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3555 ep->can_eliminate = 0;
3557 ep->ref_outside_mem = 0;
3559 if (ep->previous_offset != ep->offset)
3564 /* If we changed something, perform elimination in REG_NOTES. This is
3565 needed even when REPLACE is zero because a REG_DEAD note might refer
3566 to a register that we eliminate and could cause a different number
3567 of spill registers to be needed in the final reload pass than in
3569 if (val && REG_NOTES (insn) != 0)
3571 = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true);
3576 /* Loop through all elimination pairs.
3577 Recalculate the number not at initial offset.
3579 Compute the maximum offset (minimum offset if the stack does not
3580 grow downward) for each elimination pair. */
3583 update_eliminable_offsets (void)
3585 struct elim_table *ep;
3587 num_not_at_initial_offset = 0;
3588 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3590 ep->previous_offset = ep->offset;
3591 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3592 num_not_at_initial_offset++;
3596 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3597 replacement we currently believe is valid, mark it as not eliminable if X
3598 modifies DEST in any way other than by adding a constant integer to it.
3600 If DEST is the frame pointer, we do nothing because we assume that
3601 all assignments to the hard frame pointer are nonlocal gotos and are being
3602 done at a time when they are valid and do not disturb anything else.
3603 Some machines want to eliminate a fake argument pointer with either the
3604 frame or stack pointer. Assignments to the hard frame pointer must not
3605 prevent this elimination.
3607 Called via note_stores from reload before starting its passes to scan
3608 the insns of the function. */
3611 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3615 /* A SUBREG of a hard register here is just changing its mode. We should
3616 not see a SUBREG of an eliminable hard register, but check just in
3618 if (GET_CODE (dest) == SUBREG)
3619 dest = SUBREG_REG (dest);
3621 if (dest == hard_frame_pointer_rtx)
3624 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3625 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3626 && (GET_CODE (x) != SET
3627 || GET_CODE (SET_SRC (x)) != PLUS
3628 || XEXP (SET_SRC (x), 0) != dest
3629 || !CONST_INT_P (XEXP (SET_SRC (x), 1))))
3631 reg_eliminate[i].can_eliminate_previous
3632 = reg_eliminate[i].can_eliminate = 0;
3637 /* Verify that the initial elimination offsets did not change since the
3638 last call to set_initial_elim_offsets. This is used to catch cases
3639 where something illegal happened during reload_as_needed that could
3640 cause incorrect code to be generated if we did not check for it. */
3643 verify_initial_elim_offsets (void)
3647 if (!num_eliminable)
3650 #ifdef ELIMINABLE_REGS
3652 struct elim_table *ep;
3654 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3656 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3657 if (t != ep->initial_offset)
3662 INITIAL_FRAME_POINTER_OFFSET (t);
3663 if (t != reg_eliminate[0].initial_offset)
3670 /* Reset all offsets on eliminable registers to their initial values. */
3673 set_initial_elim_offsets (void)
3675 struct elim_table *ep = reg_eliminate;
3677 #ifdef ELIMINABLE_REGS
3678 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3680 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3681 ep->previous_offset = ep->offset = ep->initial_offset;
3684 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3685 ep->previous_offset = ep->offset = ep->initial_offset;
3688 num_not_at_initial_offset = 0;
3691 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3694 set_initial_eh_label_offset (rtx label)
3696 set_label_offsets (label, NULL_RTX, 1);
3699 /* Initialize the known label offsets.
3700 Set a known offset for each forced label to be at the initial offset
3701 of each elimination. We do this because we assume that all
3702 computed jumps occur from a location where each elimination is
3703 at its initial offset.
3704 For all other labels, show that we don't know the offsets. */
3707 set_initial_label_offsets (void)
3710 memset (offsets_known_at, 0, num_labels);
3712 for (x = forced_labels; x; x = XEXP (x, 1))
3714 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3716 for_each_eh_label (set_initial_eh_label_offset);
3719 /* Set all elimination offsets to the known values for the code label given
3723 set_offsets_for_label (rtx insn)
3726 int label_nr = CODE_LABEL_NUMBER (insn);
3727 struct elim_table *ep;
3729 num_not_at_initial_offset = 0;
3730 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3732 ep->offset = ep->previous_offset
3733 = offsets_at[label_nr - first_label_num][i];
3734 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3735 num_not_at_initial_offset++;
3739 /* See if anything that happened changes which eliminations are valid.
3740 For example, on the SPARC, whether or not the frame pointer can
3741 be eliminated can depend on what registers have been used. We need
3742 not check some conditions again (such as flag_omit_frame_pointer)
3743 since they can't have changed. */
3746 update_eliminables (HARD_REG_SET *pset)
3748 int previous_frame_pointer_needed = frame_pointer_needed;
3749 struct elim_table *ep;
3751 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3752 if ((ep->from == HARD_FRAME_POINTER_REGNUM
3753 && targetm.frame_pointer_required ())
3754 #ifdef ELIMINABLE_REGS
3755 || ! targetm.can_eliminate (ep->from, ep->to)
3758 ep->can_eliminate = 0;
3760 /* Look for the case where we have discovered that we can't replace
3761 register A with register B and that means that we will now be
3762 trying to replace register A with register C. This means we can
3763 no longer replace register C with register B and we need to disable
3764 such an elimination, if it exists. This occurs often with A == ap,
3765 B == sp, and C == fp. */
3767 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3769 struct elim_table *op;
3772 if (! ep->can_eliminate && ep->can_eliminate_previous)
3774 /* Find the current elimination for ep->from, if there is a
3776 for (op = reg_eliminate;
3777 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3778 if (op->from == ep->from && op->can_eliminate)
3784 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3786 for (op = reg_eliminate;
3787 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3788 if (op->from == new_to && op->to == ep->to)
3789 op->can_eliminate = 0;
3793 /* See if any registers that we thought we could eliminate the previous
3794 time are no longer eliminable. If so, something has changed and we
3795 must spill the register. Also, recompute the number of eliminable
3796 registers and see if the frame pointer is needed; it is if there is
3797 no elimination of the frame pointer that we can perform. */
3799 frame_pointer_needed = 1;
3800 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3802 if (ep->can_eliminate
3803 && ep->from == FRAME_POINTER_REGNUM
3804 && ep->to != HARD_FRAME_POINTER_REGNUM
3805 && (! SUPPORTS_STACK_ALIGNMENT
3806 || ! crtl->stack_realign_needed))
3807 frame_pointer_needed = 0;
3809 if (! ep->can_eliminate && ep->can_eliminate_previous)
3811 ep->can_eliminate_previous = 0;
3812 SET_HARD_REG_BIT (*pset, ep->from);
3817 /* If we didn't need a frame pointer last time, but we do now, spill
3818 the hard frame pointer. */
3819 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3820 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3823 /* Return true if X is used as the target register of an elimination. */
3826 elimination_target_reg_p (rtx x)
3828 struct elim_table *ep;
3830 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3831 if (ep->to_rtx == x && ep->can_eliminate)
3837 /* Initialize the table of registers to eliminate.
3838 Pre-condition: global flag frame_pointer_needed has been set before
3839 calling this function. */
3842 init_elim_table (void)
3844 struct elim_table *ep;
3845 #ifdef ELIMINABLE_REGS
3846 const struct elim_table_1 *ep1;
3850 reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
3854 #ifdef ELIMINABLE_REGS
3855 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3856 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3858 ep->from = ep1->from;
3860 ep->can_eliminate = ep->can_eliminate_previous
3861 = (targetm.can_eliminate (ep->from, ep->to)
3862 && ! (ep->to == STACK_POINTER_REGNUM
3863 && frame_pointer_needed
3864 && (! SUPPORTS_STACK_ALIGNMENT
3865 || ! stack_realign_fp)));
3868 reg_eliminate[0].from = reg_eliminate_1[0].from;
3869 reg_eliminate[0].to = reg_eliminate_1[0].to;
3870 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3871 = ! frame_pointer_needed;
3874 /* Count the number of eliminable registers and build the FROM and TO
3875 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3876 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3877 We depend on this. */
3878 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3880 num_eliminable += ep->can_eliminate;
3881 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3882 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3886 /* Kick all pseudos out of hard register REGNO.
3888 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3889 because we found we can't eliminate some register. In the case, no pseudos
3890 are allowed to be in the register, even if they are only in a block that
3891 doesn't require spill registers, unlike the case when we are spilling this
3892 hard reg to produce another spill register.
3894 Return nonzero if any pseudos needed to be kicked out. */
3897 spill_hard_reg (unsigned int regno, int cant_eliminate)
3903 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3904 df_set_regs_ever_live (regno, true);
3907 /* Spill every pseudo reg that was allocated to this reg
3908 or to something that overlaps this reg. */
3910 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3911 if (reg_renumber[i] >= 0
3912 && (unsigned int) reg_renumber[i] <= regno
3913 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
3914 SET_REGNO_REG_SET (&spilled_pseudos, i);
3917 /* After find_reload_regs has been run for all insn that need reloads,
3918 and/or spill_hard_regs was called, this function is used to actually
3919 spill pseudo registers and try to reallocate them. It also sets up the
3920 spill_regs array for use by choose_reload_regs. */
3923 finish_spills (int global)
3925 struct insn_chain *chain;
3926 int something_changed = 0;
3928 reg_set_iterator rsi;
3930 /* Build the spill_regs array for the function. */
3931 /* If there are some registers still to eliminate and one of the spill regs
3932 wasn't ever used before, additional stack space may have to be
3933 allocated to store this register. Thus, we may have changed the offset
3934 between the stack and frame pointers, so mark that something has changed.
3936 One might think that we need only set VAL to 1 if this is a call-used
3937 register. However, the set of registers that must be saved by the
3938 prologue is not identical to the call-used set. For example, the
3939 register used by the call insn for the return PC is a call-used register,
3940 but must be saved by the prologue. */
3943 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3944 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3946 spill_reg_order[i] = n_spills;
3947 spill_regs[n_spills++] = i;
3948 if (num_eliminable && ! df_regs_ever_live_p (i))
3949 something_changed = 1;
3950 df_set_regs_ever_live (i, true);
3953 spill_reg_order[i] = -1;
3955 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3956 if (! ira_conflicts_p || reg_renumber[i] >= 0)
3958 /* Record the current hard register the pseudo is allocated to
3959 in pseudo_previous_regs so we avoid reallocating it to the
3960 same hard reg in a later pass. */
3961 gcc_assert (reg_renumber[i] >= 0);
3963 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3964 /* Mark it as no longer having a hard register home. */
3965 reg_renumber[i] = -1;
3966 if (ira_conflicts_p)
3967 /* Inform IRA about the change. */
3968 ira_mark_allocation_change (i);
3969 /* We will need to scan everything again. */
3970 something_changed = 1;
3973 /* Retry global register allocation if possible. */
3974 if (global && ira_conflicts_p)
3978 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3979 /* For every insn that needs reloads, set the registers used as spill
3980 regs in pseudo_forbidden_regs for every pseudo live across the
3982 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3984 EXECUTE_IF_SET_IN_REG_SET
3985 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3987 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3988 chain->used_spill_regs);
3990 EXECUTE_IF_SET_IN_REG_SET
3991 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3993 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3994 chain->used_spill_regs);
3998 /* Retry allocating the pseudos spilled in IRA and the
3999 reload. For each reg, merge the various reg sets that
4000 indicate which hard regs can't be used, and call
4001 ira_reassign_pseudos. */
4002 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
4003 if (reg_old_renumber[i] != reg_renumber[i])
4005 if (reg_renumber[i] < 0)
4006 temp_pseudo_reg_arr[n++] = i;
4008 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4010 if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
4011 bad_spill_regs_global,
4012 pseudo_forbidden_regs, pseudo_previous_regs,
4014 something_changed = 1;
4016 /* Fix up the register information in the insn chain.
4017 This involves deleting those of the spilled pseudos which did not get
4018 a new hard register home from the live_{before,after} sets. */
4019 for (chain = reload_insn_chain; chain; chain = chain->next)
4021 HARD_REG_SET used_by_pseudos;
4022 HARD_REG_SET used_by_pseudos2;
4024 if (! ira_conflicts_p)
4026 /* Don't do it for IRA because IRA and the reload still can
4027 assign hard registers to the spilled pseudos on next
4028 reload iterations. */
4029 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
4030 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
4032 /* Mark any unallocated hard regs as available for spills. That
4033 makes inheritance work somewhat better. */
4034 if (chain->need_reload)
4036 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
4037 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
4038 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
4040 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
4041 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
4042 /* Value of chain->used_spill_regs from previous iteration
4043 may be not included in the value calculated here because
4044 of possible removing caller-saves insns (see function
4045 delete_caller_save_insns. */
4046 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
4047 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4051 CLEAR_REG_SET (&changed_allocation_pseudos);
4052 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4053 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4055 int regno = reg_renumber[i];
4056 if (reg_old_renumber[i] == regno)
4059 SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4061 alter_reg (i, reg_old_renumber[i], false);
4062 reg_old_renumber[i] = regno;
4066 fprintf (dump_file, " Register %d now on stack.\n\n", i);
4068 fprintf (dump_file, " Register %d now in %d.\n\n",
4069 i, reg_renumber[i]);
4073 return something_changed;
4076 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4079 scan_paradoxical_subregs (rtx x)
4083 enum rtx_code code = GET_CODE (x);
4094 case CONST_VECTOR: /* shouldn't happen, but just in case. */
4102 if (REG_P (SUBREG_REG (x))
4103 && (GET_MODE_SIZE (GET_MODE (x))
4104 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
4106 reg_max_ref_width[REGNO (SUBREG_REG (x))]
4107 = GET_MODE_SIZE (GET_MODE (x));
4108 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
4116 fmt = GET_RTX_FORMAT (code);
4117 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4120 scan_paradoxical_subregs (XEXP (x, i));
4121 else if (fmt[i] == 'E')
4124 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4125 scan_paradoxical_subregs (XVECEXP (x, i, j));
4130 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4131 examine all of the reload insns between PREV and NEXT exclusive, and
4132 annotate all that may trap. */
4135 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
4137 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4140 if (!insn_could_throw_p (insn))
4141 remove_note (insn, note);
4142 copy_reg_eh_region_note_forward (note, NEXT_INSN (prev), next);
4145 /* Reload pseudo-registers into hard regs around each insn as needed.
4146 Additional register load insns are output before the insn that needs it
4147 and perhaps store insns after insns that modify the reloaded pseudo reg.
4149 reg_last_reload_reg and reg_reloaded_contents keep track of
4150 which registers are already available in reload registers.
4151 We update these for the reloads that we perform,
4152 as the insns are scanned. */
4155 reload_as_needed (int live_known)
4157 struct insn_chain *chain;
4158 #if defined (AUTO_INC_DEC)
4163 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4164 memset (spill_reg_store, 0, sizeof spill_reg_store);
4165 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4166 INIT_REG_SET (®_has_output_reload);
4167 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4168 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4170 set_initial_elim_offsets ();
4172 for (chain = reload_insn_chain; chain; chain = chain->next)
4175 rtx insn = chain->insn;
4176 rtx old_next = NEXT_INSN (insn);
4178 rtx old_prev = PREV_INSN (insn);
4181 /* If we pass a label, copy the offsets from the label information
4182 into the current offsets of each elimination. */
4184 set_offsets_for_label (insn);
4186 else if (INSN_P (insn))
4188 regset_head regs_to_forget;
4189 INIT_REG_SET (®s_to_forget);
4190 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4192 /* If this is a USE and CLOBBER of a MEM, ensure that any
4193 references to eliminable registers have been removed. */
4195 if ((GET_CODE (PATTERN (insn)) == USE
4196 || GET_CODE (PATTERN (insn)) == CLOBBER)
4197 && MEM_P (XEXP (PATTERN (insn), 0)))
4198 XEXP (XEXP (PATTERN (insn), 0), 0)
4199 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4200 GET_MODE (XEXP (PATTERN (insn), 0)),
4203 /* If we need to do register elimination processing, do so.
4204 This might delete the insn, in which case we are done. */
4205 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4207 eliminate_regs_in_insn (insn, 1);
4210 update_eliminable_offsets ();
4211 CLEAR_REG_SET (®s_to_forget);
4216 /* If need_elim is nonzero but need_reload is zero, one might think
4217 that we could simply set n_reloads to 0. However, find_reloads
4218 could have done some manipulation of the insn (such as swapping
4219 commutative operands), and these manipulations are lost during
4220 the first pass for every insn that needs register elimination.
4221 So the actions of find_reloads must be redone here. */
4223 if (! chain->need_elim && ! chain->need_reload
4224 && ! chain->need_operand_change)
4226 /* First find the pseudo regs that must be reloaded for this insn.
4227 This info is returned in the tables reload_... (see reload.h).
4228 Also modify the body of INSN by substituting RELOAD
4229 rtx's for those pseudo regs. */
4232 CLEAR_REG_SET (®_has_output_reload);
4233 CLEAR_HARD_REG_SET (reg_is_output_reload);
4235 find_reloads (insn, 1, spill_indirect_levels, live_known,
4241 rtx next = NEXT_INSN (insn);
4244 prev = PREV_INSN (insn);
4246 /* Now compute which reload regs to reload them into. Perhaps
4247 reusing reload regs from previous insns, or else output
4248 load insns to reload them. Maybe output store insns too.
4249 Record the choices of reload reg in reload_reg_rtx. */
4250 choose_reload_regs (chain);
4252 /* Merge any reloads that we didn't combine for fear of
4253 increasing the number of spill registers needed but now
4254 discover can be safely merged. */
4255 if (SMALL_REGISTER_CLASSES)
4256 merge_assigned_reloads (insn);
4258 /* Generate the insns to reload operands into or out of
4259 their reload regs. */
4260 emit_reload_insns (chain);
4262 /* Substitute the chosen reload regs from reload_reg_rtx
4263 into the insn's body (or perhaps into the bodies of other
4264 load and store insn that we just made for reloading
4265 and that we moved the structure into). */
4266 subst_reloads (insn);
4268 /* Adjust the exception region notes for loads and stores. */
4269 if (flag_non_call_exceptions && !CALL_P (insn))
4270 fixup_eh_region_note (insn, prev, next);
4272 /* If this was an ASM, make sure that all the reload insns
4273 we have generated are valid. If not, give an error
4275 if (asm_noperands (PATTERN (insn)) >= 0)
4276 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4277 if (p != insn && INSN_P (p)
4278 && GET_CODE (PATTERN (p)) != USE
4279 && (recog_memoized (p) < 0
4280 || (extract_insn (p), ! constrain_operands (1))))
4282 error_for_asm (insn,
4283 "%<asm%> operand requires "
4284 "impossible reload");
4289 if (num_eliminable && chain->need_elim)
4290 update_eliminable_offsets ();
4292 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4293 is no longer validly lying around to save a future reload.
4294 Note that this does not detect pseudos that were reloaded
4295 for this insn in order to be stored in
4296 (obeying register constraints). That is correct; such reload
4297 registers ARE still valid. */
4298 forget_marked_reloads (®s_to_forget);
4299 CLEAR_REG_SET (®s_to_forget);
4301 /* There may have been CLOBBER insns placed after INSN. So scan
4302 between INSN and NEXT and use them to forget old reloads. */
4303 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4304 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4305 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4308 /* Likewise for regs altered by auto-increment in this insn.
4309 REG_INC notes have been changed by reloading:
4310 find_reloads_address_1 records substitutions for them,
4311 which have been performed by subst_reloads above. */
4312 for (i = n_reloads - 1; i >= 0; i--)
4314 rtx in_reg = rld[i].in_reg;
4317 enum rtx_code code = GET_CODE (in_reg);
4318 /* PRE_INC / PRE_DEC will have the reload register ending up
4319 with the same value as the stack slot, but that doesn't
4320 hold true for POST_INC / POST_DEC. Either we have to
4321 convert the memory access to a true POST_INC / POST_DEC,
4322 or we can't use the reload register for inheritance. */
4323 if ((code == POST_INC || code == POST_DEC)
4324 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4325 REGNO (rld[i].reg_rtx))
4326 /* Make sure it is the inc/dec pseudo, and not
4327 some other (e.g. output operand) pseudo. */
4328 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4329 == REGNO (XEXP (in_reg, 0))))
4332 rtx reload_reg = rld[i].reg_rtx;
4333 enum machine_mode mode = GET_MODE (reload_reg);
4337 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4339 /* We really want to ignore REG_INC notes here, so
4340 use PATTERN (p) as argument to reg_set_p . */
4341 if (reg_set_p (reload_reg, PATTERN (p)))
4343 n = count_occurrences (PATTERN (p), reload_reg, 0);
4349 = gen_rtx_fmt_e (code, mode, reload_reg);
4351 validate_replace_rtx_group (reload_reg,
4353 n = verify_changes (0);
4355 /* We must also verify that the constraints
4356 are met after the replacement. Make sure
4357 extract_insn is only called for an insn
4358 where the replacements were found to be
4363 n = constrain_operands (1);
4366 /* If the constraints were not met, then
4367 undo the replacement, else confirm it. */
4371 confirm_change_group ();
4377 add_reg_note (p, REG_INC, reload_reg);
4378 /* Mark this as having an output reload so that the
4379 REG_INC processing code below won't invalidate
4380 the reload for inheritance. */
4381 SET_HARD_REG_BIT (reg_is_output_reload,
4382 REGNO (reload_reg));
4383 SET_REGNO_REG_SET (®_has_output_reload,
4384 REGNO (XEXP (in_reg, 0)));
4387 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4390 else if ((code == PRE_INC || code == PRE_DEC)
4391 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4392 REGNO (rld[i].reg_rtx))
4393 /* Make sure it is the inc/dec pseudo, and not
4394 some other (e.g. output operand) pseudo. */
4395 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4396 == REGNO (XEXP (in_reg, 0))))
4398 SET_HARD_REG_BIT (reg_is_output_reload,
4399 REGNO (rld[i].reg_rtx));
4400 SET_REGNO_REG_SET (®_has_output_reload,
4401 REGNO (XEXP (in_reg, 0)));
4403 else if (code == PRE_INC || code == PRE_DEC
4404 || code == POST_INC || code == POST_DEC)
4406 int in_regno = REGNO (XEXP (in_reg, 0));
4408 if (reg_last_reload_reg[in_regno] != NULL_RTX)
4411 bool forget_p = true;
4413 in_hard_regno = REGNO (reg_last_reload_reg[in_regno]);
4414 if (TEST_HARD_REG_BIT (reg_reloaded_valid,
4417 for (x = old_prev ? NEXT_INSN (old_prev) : insn;
4420 if (x == reg_reloaded_insn[in_hard_regno])
4426 /* If for some reasons, we didn't set up
4427 reg_last_reload_reg in this insn,
4428 invalidate inheritance from previous
4429 insns for the incremented/decremented
4430 register. Such registers will be not in
4431 reg_has_output_reload. Invalidate it
4432 also if the corresponding element in
4433 reg_reloaded_insn is also
4436 forget_old_reloads_1 (XEXP (in_reg, 0),
4442 /* If a pseudo that got a hard register is auto-incremented,
4443 we must purge records of copying it into pseudos without
4445 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4446 if (REG_NOTE_KIND (x) == REG_INC)
4448 /* See if this pseudo reg was reloaded in this insn.
4449 If so, its last-reload info is still valid
4450 because it is based on this insn's reload. */
4451 for (i = 0; i < n_reloads; i++)
4452 if (rld[i].out == XEXP (x, 0))
4456 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4460 /* A reload reg's contents are unknown after a label. */
4462 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4464 /* Don't assume a reload reg is still good after a call insn
4465 if it is a call-used reg, or if it contains a value that will
4466 be partially clobbered by the call. */
4467 else if (CALL_P (insn))
4469 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4470 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4475 free (reg_last_reload_reg);
4476 CLEAR_REG_SET (®_has_output_reload);
4479 /* Discard all record of any value reloaded from X,
4480 or reloaded in X from someplace else;
4481 unless X is an output reload reg of the current insn.
4483 X may be a hard reg (the reload reg)
4484 or it may be a pseudo reg that was reloaded from.
4486 When DATA is non-NULL just mark the registers in regset
4487 to be forgotten later. */
4490 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4495 regset regs = (regset) data;
4497 /* note_stores does give us subregs of hard regs,
4498 subreg_regno_offset requires a hard reg. */
4499 while (GET_CODE (x) == SUBREG)
4501 /* We ignore the subreg offset when calculating the regno,
4502 because we are using the entire underlying hard register
4512 if (regno >= FIRST_PSEUDO_REGISTER)
4518 nr = hard_regno_nregs[regno][GET_MODE (x)];
4519 /* Storing into a spilled-reg invalidates its contents.
4520 This can happen if a block-local pseudo is allocated to that reg
4521 and it wasn't spilled because this block's total need is 0.
4522 Then some insn might have an optional reload and use this reg. */
4524 for (i = 0; i < nr; i++)
4525 /* But don't do this if the reg actually serves as an output
4526 reload reg in the current instruction. */
4528 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4530 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4531 spill_reg_store[regno + i] = 0;
4537 SET_REGNO_REG_SET (regs, regno + nr);
4540 /* Since value of X has changed,
4541 forget any value previously copied from it. */
4544 /* But don't forget a copy if this is the output reload
4545 that establishes the copy's validity. */
4547 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4548 reg_last_reload_reg[regno + nr] = 0;
4552 /* Forget the reloads marked in regset by previous function. */
4554 forget_marked_reloads (regset regs)
4557 reg_set_iterator rsi;
4558 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4560 if (reg < FIRST_PSEUDO_REGISTER
4561 /* But don't do this if the reg actually serves as an output
4562 reload reg in the current instruction. */
4564 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4566 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4567 spill_reg_store[reg] = 0;
4570 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4571 reg_last_reload_reg[reg] = 0;
4575 /* The following HARD_REG_SETs indicate when each hard register is
4576 used for a reload of various parts of the current insn. */
4578 /* If reg is unavailable for all reloads. */
4579 static HARD_REG_SET reload_reg_unavailable;
4580 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4581 static HARD_REG_SET reload_reg_used;
4582 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4583 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4584 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4585 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4586 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4587 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4588 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4589 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4590 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4591 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4592 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4593 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4594 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4595 static HARD_REG_SET reload_reg_used_in_op_addr;
4596 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4597 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4598 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4599 static HARD_REG_SET reload_reg_used_in_insn;
4600 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4601 static HARD_REG_SET reload_reg_used_in_other_addr;
4603 /* If reg is in use as a reload reg for any sort of reload. */
4604 static HARD_REG_SET reload_reg_used_at_all;
4606 /* If reg is use as an inherited reload. We just mark the first register
4608 static HARD_REG_SET reload_reg_used_for_inherit;
4610 /* Records which hard regs are used in any way, either as explicit use or
4611 by being allocated to a pseudo during any point of the current insn. */
4612 static HARD_REG_SET reg_used_in_insn;
4614 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4615 TYPE. MODE is used to indicate how many consecutive regs are
4619 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4620 enum machine_mode mode)
4622 unsigned int nregs = hard_regno_nregs[regno][mode];
4625 for (i = regno; i < nregs + regno; i++)
4630 SET_HARD_REG_BIT (reload_reg_used, i);
4633 case RELOAD_FOR_INPUT_ADDRESS:
4634 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4637 case RELOAD_FOR_INPADDR_ADDRESS:
4638 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4641 case RELOAD_FOR_OUTPUT_ADDRESS:
4642 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4645 case RELOAD_FOR_OUTADDR_ADDRESS:
4646 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4649 case RELOAD_FOR_OPERAND_ADDRESS:
4650 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4653 case RELOAD_FOR_OPADDR_ADDR:
4654 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4657 case RELOAD_FOR_OTHER_ADDRESS:
4658 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4661 case RELOAD_FOR_INPUT:
4662 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4665 case RELOAD_FOR_OUTPUT:
4666 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4669 case RELOAD_FOR_INSN:
4670 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4674 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4678 /* Similarly, but show REGNO is no longer in use for a reload. */
4681 clear_reload_reg_in_use (unsigned int regno, int opnum,
4682 enum reload_type type, enum machine_mode mode)
4684 unsigned int nregs = hard_regno_nregs[regno][mode];
4685 unsigned int start_regno, end_regno, r;
4687 /* A complication is that for some reload types, inheritance might
4688 allow multiple reloads of the same types to share a reload register.
4689 We set check_opnum if we have to check only reloads with the same
4690 operand number, and check_any if we have to check all reloads. */
4691 int check_opnum = 0;
4693 HARD_REG_SET *used_in_set;
4698 used_in_set = &reload_reg_used;
4701 case RELOAD_FOR_INPUT_ADDRESS:
4702 used_in_set = &reload_reg_used_in_input_addr[opnum];
4705 case RELOAD_FOR_INPADDR_ADDRESS:
4707 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4710 case RELOAD_FOR_OUTPUT_ADDRESS:
4711 used_in_set = &reload_reg_used_in_output_addr[opnum];
4714 case RELOAD_FOR_OUTADDR_ADDRESS:
4716 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4719 case RELOAD_FOR_OPERAND_ADDRESS:
4720 used_in_set = &reload_reg_used_in_op_addr;
4723 case RELOAD_FOR_OPADDR_ADDR:
4725 used_in_set = &reload_reg_used_in_op_addr_reload;
4728 case RELOAD_FOR_OTHER_ADDRESS:
4729 used_in_set = &reload_reg_used_in_other_addr;
4733 case RELOAD_FOR_INPUT:
4734 used_in_set = &reload_reg_used_in_input[opnum];
4737 case RELOAD_FOR_OUTPUT:
4738 used_in_set = &reload_reg_used_in_output[opnum];
4741 case RELOAD_FOR_INSN:
4742 used_in_set = &reload_reg_used_in_insn;
4747 /* We resolve conflicts with remaining reloads of the same type by
4748 excluding the intervals of reload registers by them from the
4749 interval of freed reload registers. Since we only keep track of
4750 one set of interval bounds, we might have to exclude somewhat
4751 more than what would be necessary if we used a HARD_REG_SET here.
4752 But this should only happen very infrequently, so there should
4753 be no reason to worry about it. */
4755 start_regno = regno;
4756 end_regno = regno + nregs;
4757 if (check_opnum || check_any)
4759 for (i = n_reloads - 1; i >= 0; i--)
4761 if (rld[i].when_needed == type
4762 && (check_any || rld[i].opnum == opnum)
4765 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4766 unsigned int conflict_end
4767 = end_hard_regno (rld[i].mode, conflict_start);
4769 /* If there is an overlap with the first to-be-freed register,
4770 adjust the interval start. */
4771 if (conflict_start <= start_regno && conflict_end > start_regno)
4772 start_regno = conflict_end;
4773 /* Otherwise, if there is a conflict with one of the other
4774 to-be-freed registers, adjust the interval end. */
4775 if (conflict_start > start_regno && conflict_start < end_regno)
4776 end_regno = conflict_start;
4781 for (r = start_regno; r < end_regno; r++)
4782 CLEAR_HARD_REG_BIT (*used_in_set, r);
4785 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4786 specified by OPNUM and TYPE. */
4789 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4793 /* In use for a RELOAD_OTHER means it's not available for anything. */
4794 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4795 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4801 /* In use for anything means we can't use it for RELOAD_OTHER. */
4802 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4803 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4804 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4805 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4808 for (i = 0; i < reload_n_operands; i++)
4809 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4810 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4811 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4812 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4813 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4814 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4819 case RELOAD_FOR_INPUT:
4820 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4821 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4824 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4827 /* If it is used for some other input, can't use it. */
4828 for (i = 0; i < reload_n_operands; i++)
4829 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4832 /* If it is used in a later operand's address, can't use it. */
4833 for (i = opnum + 1; i < reload_n_operands; i++)
4834 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4835 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4840 case RELOAD_FOR_INPUT_ADDRESS:
4841 /* Can't use a register if it is used for an input address for this
4842 operand or used as an input in an earlier one. */
4843 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4844 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4847 for (i = 0; i < opnum; i++)
4848 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4853 case RELOAD_FOR_INPADDR_ADDRESS:
4854 /* Can't use a register if it is used for an input address
4855 for this operand or used as an input in an earlier
4857 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4860 for (i = 0; i < opnum; i++)
4861 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4866 case RELOAD_FOR_OUTPUT_ADDRESS:
4867 /* Can't use a register if it is used for an output address for this
4868 operand or used as an output in this or a later operand. Note
4869 that multiple output operands are emitted in reverse order, so
4870 the conflicting ones are those with lower indices. */
4871 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4874 for (i = 0; i <= opnum; i++)
4875 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4880 case RELOAD_FOR_OUTADDR_ADDRESS:
4881 /* Can't use a register if it is used for an output address
4882 for this operand or used as an output in this or a
4883 later operand. Note that multiple output operands are
4884 emitted in reverse order, so the conflicting ones are
4885 those with lower indices. */
4886 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4889 for (i = 0; i <= opnum; i++)
4890 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4895 case RELOAD_FOR_OPERAND_ADDRESS:
4896 for (i = 0; i < reload_n_operands; i++)
4897 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4900 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4901 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4903 case RELOAD_FOR_OPADDR_ADDR:
4904 for (i = 0; i < reload_n_operands; i++)
4905 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4908 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4910 case RELOAD_FOR_OUTPUT:
4911 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4912 outputs, or an operand address for this or an earlier output.
4913 Note that multiple output operands are emitted in reverse order,
4914 so the conflicting ones are those with higher indices. */
4915 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4918 for (i = 0; i < reload_n_operands; i++)
4919 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4922 for (i = opnum; i < reload_n_operands; i++)
4923 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4924 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4929 case RELOAD_FOR_INSN:
4930 for (i = 0; i < reload_n_operands; i++)
4931 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4932 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4935 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4936 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4938 case RELOAD_FOR_OTHER_ADDRESS:
4939 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4946 /* Return 1 if the value in reload reg REGNO, as used by a reload
4947 needed for the part of the insn specified by OPNUM and TYPE,
4948 is still available in REGNO at the end of the insn.
4950 We can assume that the reload reg was already tested for availability
4951 at the time it is needed, and we should not check this again,
4952 in case the reg has already been marked in use. */
4955 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4962 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4963 its value must reach the end. */
4966 /* If this use is for part of the insn,
4967 its value reaches if no subsequent part uses the same register.
4968 Just like the above function, don't try to do this with lots
4971 case RELOAD_FOR_OTHER_ADDRESS:
4972 /* Here we check for everything else, since these don't conflict
4973 with anything else and everything comes later. */
4975 for (i = 0; i < reload_n_operands; i++)
4976 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4977 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4978 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4979 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4980 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4981 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4984 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4985 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4986 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4987 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4989 case RELOAD_FOR_INPUT_ADDRESS:
4990 case RELOAD_FOR_INPADDR_ADDRESS:
4991 /* Similar, except that we check only for this and subsequent inputs
4992 and the address of only subsequent inputs and we do not need
4993 to check for RELOAD_OTHER objects since they are known not to
4996 for (i = opnum; i < reload_n_operands; i++)
4997 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5000 for (i = opnum + 1; i < reload_n_operands; i++)
5001 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5002 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5005 for (i = 0; i < reload_n_operands; i++)
5006 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5007 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5008 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5011 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5014 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5015 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5016 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5018 case RELOAD_FOR_INPUT:
5019 /* Similar to input address, except we start at the next operand for
5020 both input and input address and we do not check for
5021 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5024 for (i = opnum + 1; i < reload_n_operands; i++)
5025 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5026 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5027 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5030 /* ... fall through ... */
5032 case RELOAD_FOR_OPERAND_ADDRESS:
5033 /* Check outputs and their addresses. */
5035 for (i = 0; i < reload_n_operands; i++)
5036 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5037 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5038 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5041 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5043 case RELOAD_FOR_OPADDR_ADDR:
5044 for (i = 0; i < reload_n_operands; i++)
5045 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5046 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5047 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5050 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5051 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5052 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5054 case RELOAD_FOR_INSN:
5055 /* These conflict with other outputs with RELOAD_OTHER. So
5056 we need only check for output addresses. */
5058 opnum = reload_n_operands;
5060 /* ... fall through ... */
5062 case RELOAD_FOR_OUTPUT:
5063 case RELOAD_FOR_OUTPUT_ADDRESS:
5064 case RELOAD_FOR_OUTADDR_ADDRESS:
5065 /* We already know these can't conflict with a later output. So the
5066 only thing to check are later output addresses.
5067 Note that multiple output operands are emitted in reverse order,
5068 so the conflicting ones are those with lower indices. */
5069 for (i = 0; i < opnum; i++)
5070 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5071 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5081 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5082 every register in the range [REGNO, REGNO + NREGS). */
5085 reload_regs_reach_end_p (unsigned int regno, int nregs,
5086 int opnum, enum reload_type type)
5090 for (i = 0; i < nregs; i++)
5091 if (!reload_reg_reaches_end_p (regno + i, opnum, type))
5097 /* Returns whether R1 and R2 are uniquely chained: the value of one
5098 is used by the other, and that value is not used by any other
5099 reload for this insn. This is used to partially undo the decision
5100 made in find_reloads when in the case of multiple
5101 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5102 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5103 reloads. This code tries to avoid the conflict created by that
5104 change. It might be cleaner to explicitly keep track of which
5105 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5106 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5107 this after the fact. */
5109 reloads_unique_chain_p (int r1, int r2)
5113 /* We only check input reloads. */
5114 if (! rld[r1].in || ! rld[r2].in)
5117 /* Avoid anything with output reloads. */
5118 if (rld[r1].out || rld[r2].out)
5121 /* "chained" means one reload is a component of the other reload,
5122 not the same as the other reload. */
5123 if (rld[r1].opnum != rld[r2].opnum
5124 || rtx_equal_p (rld[r1].in, rld[r2].in)
5125 || rld[r1].optional || rld[r2].optional
5126 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5127 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5130 for (i = 0; i < n_reloads; i ++)
5131 /* Look for input reloads that aren't our two */
5132 if (i != r1 && i != r2 && rld[i].in)
5134 /* If our reload is mentioned at all, it isn't a simple chain. */
5135 if (reg_mentioned_p (rld[r1].in, rld[i].in))
5142 /* The recursive function change all occurrences of WHAT in *WHERE
5145 substitute (rtx *where, const_rtx what, rtx repl)
5154 if (*where == what || rtx_equal_p (*where, what))
5160 code = GET_CODE (*where);
5161 fmt = GET_RTX_FORMAT (code);
5162 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5168 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5169 substitute (&XVECEXP (*where, i, j), what, repl);
5171 else if (fmt[i] == 'e')
5172 substitute (&XEXP (*where, i), what, repl);
5176 /* The function returns TRUE if chain of reload R1 and R2 (in any
5177 order) can be evaluated without usage of intermediate register for
5178 the reload containing another reload. It is important to see
5179 gen_reload to understand what the function is trying to do. As an
5180 example, let us have reload chain
5183 r1: <something> + const
5185 and reload R2 got reload reg HR. The function returns true if
5186 there is a correct insn HR = HR + <something>. Otherwise,
5187 gen_reload will use intermediate register (and this is the reload
5188 reg for R1) to reload <something>.
5190 We need this function to find a conflict for chain reloads. In our
5191 example, if HR = HR + <something> is incorrect insn, then we cannot
5192 use HR as a reload register for R2. If we do use it then we get a
5201 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5205 rtx out, in, tem, insn;
5206 rtx last = get_last_insn ();
5208 /* Make r2 a component of r1. */
5209 if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5215 gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5216 regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5217 gcc_assert (regno >= 0);
5218 out = gen_rtx_REG (rld[r1].mode, regno);
5219 in = copy_rtx (rld[r1].in);
5220 substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5222 /* If IN is a paradoxical SUBREG, remove it and try to put the
5223 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5224 if (GET_CODE (in) == SUBREG
5225 && (GET_MODE_SIZE (GET_MODE (in))
5226 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
5227 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
5228 in = SUBREG_REG (in), out = tem;
5230 if (GET_CODE (in) == PLUS
5231 && (REG_P (XEXP (in, 0))
5232 || GET_CODE (XEXP (in, 0)) == SUBREG
5233 || MEM_P (XEXP (in, 0)))
5234 && (REG_P (XEXP (in, 1))
5235 || GET_CODE (XEXP (in, 1)) == SUBREG
5236 || CONSTANT_P (XEXP (in, 1))
5237 || MEM_P (XEXP (in, 1))))
5239 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
5240 code = recog_memoized (insn);
5245 extract_insn (insn);
5246 /* We want constrain operands to treat this insn strictly in
5247 its validity determination, i.e., the way it would after
5248 reload has completed. */
5249 result = constrain_operands (1);
5252 delete_insns_since (last);
5256 /* It looks like other cases in gen_reload are not possible for
5257 chain reloads or do need an intermediate hard registers. */
5261 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5264 This function uses the same algorithm as reload_reg_free_p above. */
5267 reloads_conflict (int r1, int r2)
5269 enum reload_type r1_type = rld[r1].when_needed;
5270 enum reload_type r2_type = rld[r2].when_needed;
5271 int r1_opnum = rld[r1].opnum;
5272 int r2_opnum = rld[r2].opnum;
5274 /* RELOAD_OTHER conflicts with everything. */
5275 if (r2_type == RELOAD_OTHER)
5278 /* Otherwise, check conflicts differently for each type. */
5282 case RELOAD_FOR_INPUT:
5283 return (r2_type == RELOAD_FOR_INSN
5284 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5285 || r2_type == RELOAD_FOR_OPADDR_ADDR
5286 || r2_type == RELOAD_FOR_INPUT
5287 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5288 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5289 && r2_opnum > r1_opnum));
5291 case RELOAD_FOR_INPUT_ADDRESS:
5292 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5293 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5295 case RELOAD_FOR_INPADDR_ADDRESS:
5296 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5297 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5299 case RELOAD_FOR_OUTPUT_ADDRESS:
5300 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5301 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5303 case RELOAD_FOR_OUTADDR_ADDRESS:
5304 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5305 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5307 case RELOAD_FOR_OPERAND_ADDRESS:
5308 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5309 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5310 && (!reloads_unique_chain_p (r1, r2)
5311 || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5313 case RELOAD_FOR_OPADDR_ADDR:
5314 return (r2_type == RELOAD_FOR_INPUT
5315 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5317 case RELOAD_FOR_OUTPUT:
5318 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5319 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5320 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5321 && r2_opnum >= r1_opnum));
5323 case RELOAD_FOR_INSN:
5324 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5325 || r2_type == RELOAD_FOR_INSN
5326 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5328 case RELOAD_FOR_OTHER_ADDRESS:
5329 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5339 /* Indexed by reload number, 1 if incoming value
5340 inherited from previous insns. */
5341 static char reload_inherited[MAX_RELOADS];
5343 /* For an inherited reload, this is the insn the reload was inherited from,
5344 if we know it. Otherwise, this is 0. */
5345 static rtx reload_inheritance_insn[MAX_RELOADS];
5347 /* If nonzero, this is a place to get the value of the reload,
5348 rather than using reload_in. */
5349 static rtx reload_override_in[MAX_RELOADS];
5351 /* For each reload, the hard register number of the register used,
5352 or -1 if we did not need a register for this reload. */
5353 static int reload_spill_index[MAX_RELOADS];
5355 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5356 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5358 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5359 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5361 /* Subroutine of free_for_value_p, used to check a single register.
5362 START_REGNO is the starting regno of the full reload register
5363 (possibly comprising multiple hard registers) that we are considering. */
5366 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5367 enum reload_type type, rtx value, rtx out,
5368 int reloadnum, int ignore_address_reloads)
5371 /* Set if we see an input reload that must not share its reload register
5372 with any new earlyclobber, but might otherwise share the reload
5373 register with an output or input-output reload. */
5374 int check_earlyclobber = 0;
5378 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5381 if (out == const0_rtx)
5387 /* We use some pseudo 'time' value to check if the lifetimes of the
5388 new register use would overlap with the one of a previous reload
5389 that is not read-only or uses a different value.
5390 The 'time' used doesn't have to be linear in any shape or form, just
5392 Some reload types use different 'buckets' for each operand.
5393 So there are MAX_RECOG_OPERANDS different time values for each
5395 We compute TIME1 as the time when the register for the prospective
5396 new reload ceases to be live, and TIME2 for each existing
5397 reload as the time when that the reload register of that reload
5399 Where there is little to be gained by exact lifetime calculations,
5400 we just make conservative assumptions, i.e. a longer lifetime;
5401 this is done in the 'default:' cases. */
5404 case RELOAD_FOR_OTHER_ADDRESS:
5405 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5406 time1 = copy ? 0 : 1;
5409 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5411 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5412 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5413 respectively, to the time values for these, we get distinct time
5414 values. To get distinct time values for each operand, we have to
5415 multiply opnum by at least three. We round that up to four because
5416 multiply by four is often cheaper. */
5417 case RELOAD_FOR_INPADDR_ADDRESS:
5418 time1 = opnum * 4 + 2;
5420 case RELOAD_FOR_INPUT_ADDRESS:
5421 time1 = opnum * 4 + 3;
5423 case RELOAD_FOR_INPUT:
5424 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5425 executes (inclusive). */
5426 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5428 case RELOAD_FOR_OPADDR_ADDR:
5430 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5431 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5433 case RELOAD_FOR_OPERAND_ADDRESS:
5434 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5436 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5438 case RELOAD_FOR_OUTADDR_ADDRESS:
5439 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5441 case RELOAD_FOR_OUTPUT_ADDRESS:
5442 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5445 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5448 for (i = 0; i < n_reloads; i++)
5450 rtx reg = rld[i].reg_rtx;
5451 if (reg && REG_P (reg)
5452 && ((unsigned) regno - true_regnum (reg)
5453 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5456 rtx other_input = rld[i].in;
5458 /* If the other reload loads the same input value, that
5459 will not cause a conflict only if it's loading it into
5460 the same register. */
5461 if (true_regnum (reg) != start_regno)
5462 other_input = NULL_RTX;
5463 if (! other_input || ! rtx_equal_p (other_input, value)
5464 || rld[i].out || out)
5467 switch (rld[i].when_needed)
5469 case RELOAD_FOR_OTHER_ADDRESS:
5472 case RELOAD_FOR_INPADDR_ADDRESS:
5473 /* find_reloads makes sure that a
5474 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5475 by at most one - the first -
5476 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5477 address reload is inherited, the address address reload
5478 goes away, so we can ignore this conflict. */
5479 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5480 && ignore_address_reloads
5481 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5482 Then the address address is still needed to store
5483 back the new address. */
5484 && ! rld[reloadnum].out)
5486 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5487 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5489 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5490 && ignore_address_reloads
5491 /* Unless we are reloading an auto_inc expression. */
5492 && ! rld[reloadnum].out)
5494 time2 = rld[i].opnum * 4 + 2;
5496 case RELOAD_FOR_INPUT_ADDRESS:
5497 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5498 && ignore_address_reloads
5499 && ! rld[reloadnum].out)
5501 time2 = rld[i].opnum * 4 + 3;
5503 case RELOAD_FOR_INPUT:
5504 time2 = rld[i].opnum * 4 + 4;
5505 check_earlyclobber = 1;
5507 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5508 == MAX_RECOG_OPERAND * 4 */
5509 case RELOAD_FOR_OPADDR_ADDR:
5510 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5511 && ignore_address_reloads
5512 && ! rld[reloadnum].out)
5514 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5516 case RELOAD_FOR_OPERAND_ADDRESS:
5517 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5518 check_earlyclobber = 1;
5520 case RELOAD_FOR_INSN:
5521 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5523 case RELOAD_FOR_OUTPUT:
5524 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5525 instruction is executed. */
5526 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5528 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5529 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5531 case RELOAD_FOR_OUTADDR_ADDRESS:
5532 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5533 && ignore_address_reloads
5534 && ! rld[reloadnum].out)
5536 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5538 case RELOAD_FOR_OUTPUT_ADDRESS:
5539 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5542 /* If there is no conflict in the input part, handle this
5543 like an output reload. */
5544 if (! rld[i].in || rtx_equal_p (other_input, value))
5546 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5547 /* Earlyclobbered outputs must conflict with inputs. */
5548 if (earlyclobber_operand_p (rld[i].out))
5549 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5554 /* RELOAD_OTHER might be live beyond instruction execution,
5555 but this is not obvious when we set time2 = 1. So check
5556 here if there might be a problem with the new reload
5557 clobbering the register used by the RELOAD_OTHER. */
5565 && (! rld[i].in || rld[i].out
5566 || ! rtx_equal_p (other_input, value)))
5567 || (out && rld[reloadnum].out_reg
5568 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5574 /* Earlyclobbered outputs must conflict with inputs. */
5575 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5581 /* Return 1 if the value in reload reg REGNO, as used by a reload
5582 needed for the part of the insn specified by OPNUM and TYPE,
5583 may be used to load VALUE into it.
5585 MODE is the mode in which the register is used, this is needed to
5586 determine how many hard regs to test.
5588 Other read-only reloads with the same value do not conflict
5589 unless OUT is nonzero and these other reloads have to live while
5590 output reloads live.
5591 If OUT is CONST0_RTX, this is a special case: it means that the
5592 test should not be for using register REGNO as reload register, but
5593 for copying from register REGNO into the reload register.
5595 RELOADNUM is the number of the reload we want to load this value for;
5596 a reload does not conflict with itself.
5598 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5599 reloads that load an address for the very reload we are considering.
5601 The caller has to make sure that there is no conflict with the return
5605 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5606 enum reload_type type, rtx value, rtx out, int reloadnum,
5607 int ignore_address_reloads)
5609 int nregs = hard_regno_nregs[regno][mode];
5611 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5612 value, out, reloadnum,
5613 ignore_address_reloads))
5618 /* Return nonzero if the rtx X is invariant over the current function. */
5619 /* ??? Actually, the places where we use this expect exactly what is
5620 tested here, and not everything that is function invariant. In
5621 particular, the frame pointer and arg pointer are special cased;
5622 pic_offset_table_rtx is not, and we must not spill these things to
5626 function_invariant_p (const_rtx x)
5630 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5632 if (GET_CODE (x) == PLUS
5633 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5634 && CONSTANT_P (XEXP (x, 1)))
5639 /* Determine whether the reload reg X overlaps any rtx'es used for
5640 overriding inheritance. Return nonzero if so. */
5643 conflicts_with_override (rtx x)
5646 for (i = 0; i < n_reloads; i++)
5647 if (reload_override_in[i]
5648 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5653 /* Give an error message saying we failed to find a reload for INSN,
5654 and clear out reload R. */
5656 failed_reload (rtx insn, int r)
5658 if (asm_noperands (PATTERN (insn)) < 0)
5659 /* It's the compiler's fault. */
5660 fatal_insn ("could not find a spill register", insn);
5662 /* It's the user's fault; the operand's mode and constraint
5663 don't match. Disable this reload so we don't crash in final. */
5664 error_for_asm (insn,
5665 "%<asm%> operand constraint incompatible with operand size");
5669 rld[r].optional = 1;
5670 rld[r].secondary_p = 1;
5673 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5674 for reload R. If it's valid, get an rtx for it. Return nonzero if
5677 set_reload_reg (int i, int r)
5680 rtx reg = spill_reg_rtx[i];
5682 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5683 spill_reg_rtx[i] = reg
5684 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5686 regno = true_regnum (reg);
5688 /* Detect when the reload reg can't hold the reload mode.
5689 This used to be one `if', but Sequent compiler can't handle that. */
5690 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5692 enum machine_mode test_mode = VOIDmode;
5694 test_mode = GET_MODE (rld[r].in);
5695 /* If rld[r].in has VOIDmode, it means we will load it
5696 in whatever mode the reload reg has: to wit, rld[r].mode.
5697 We have already tested that for validity. */
5698 /* Aside from that, we need to test that the expressions
5699 to reload from or into have modes which are valid for this
5700 reload register. Otherwise the reload insns would be invalid. */
5701 if (! (rld[r].in != 0 && test_mode != VOIDmode
5702 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5703 if (! (rld[r].out != 0
5704 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5706 /* The reg is OK. */
5709 /* Mark as in use for this insn the reload regs we use
5711 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5712 rld[r].when_needed, rld[r].mode);
5714 rld[r].reg_rtx = reg;
5715 reload_spill_index[r] = spill_regs[i];
5722 /* Find a spill register to use as a reload register for reload R.
5723 LAST_RELOAD is nonzero if this is the last reload for the insn being
5726 Set rld[R].reg_rtx to the register allocated.
5728 We return 1 if successful, or 0 if we couldn't find a spill reg and
5729 we didn't change anything. */
5732 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5737 /* If we put this reload ahead, thinking it is a group,
5738 then insist on finding a group. Otherwise we can grab a
5739 reg that some other reload needs.
5740 (That can happen when we have a 68000 DATA_OR_FP_REG
5741 which is a group of data regs or one fp reg.)
5742 We need not be so restrictive if there are no more reloads
5745 ??? Really it would be nicer to have smarter handling
5746 for that kind of reg class, where a problem like this is normal.
5747 Perhaps those classes should be avoided for reloading
5748 by use of more alternatives. */
5750 int force_group = rld[r].nregs > 1 && ! last_reload;
5752 /* If we want a single register and haven't yet found one,
5753 take any reg in the right class and not in use.
5754 If we want a consecutive group, here is where we look for it.
5756 We use two passes so we can first look for reload regs to
5757 reuse, which are already in use for other reloads in this insn,
5758 and only then use additional registers.
5759 I think that maximizing reuse is needed to make sure we don't
5760 run out of reload regs. Suppose we have three reloads, and
5761 reloads A and B can share regs. These need two regs.
5762 Suppose A and B are given different regs.
5763 That leaves none for C. */
5764 for (pass = 0; pass < 2; pass++)
5766 /* I is the index in spill_regs.
5767 We advance it round-robin between insns to use all spill regs
5768 equally, so that inherited reloads have a chance
5769 of leapfrogging each other. */
5773 for (count = 0; count < n_spills; count++)
5775 int rclass = (int) rld[r].rclass;
5781 regnum = spill_regs[i];
5783 if ((reload_reg_free_p (regnum, rld[r].opnum,
5786 /* We check reload_reg_used to make sure we
5787 don't clobber the return register. */
5788 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5789 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5790 rld[r].when_needed, rld[r].in,
5792 && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
5793 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5794 /* Look first for regs to share, then for unshared. But
5795 don't share regs used for inherited reloads; they are
5796 the ones we want to preserve. */
5798 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5800 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5803 int nr = hard_regno_nregs[regnum][rld[r].mode];
5804 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5805 (on 68000) got us two FP regs. If NR is 1,
5806 we would reject both of them. */
5809 /* If we need only one reg, we have already won. */
5812 /* But reject a single reg if we demand a group. */
5817 /* Otherwise check that as many consecutive regs as we need
5818 are available here. */
5821 int regno = regnum + nr - 1;
5822 if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
5823 && spill_reg_order[regno] >= 0
5824 && reload_reg_free_p (regno, rld[r].opnum,
5825 rld[r].when_needed)))
5834 /* If we found something on pass 1, omit pass 2. */
5835 if (count < n_spills)
5839 /* We should have found a spill register by now. */
5840 if (count >= n_spills)
5843 /* I is the index in SPILL_REG_RTX of the reload register we are to
5844 allocate. Get an rtx for it and find its register number. */
5846 return set_reload_reg (i, r);
5849 /* Initialize all the tables needed to allocate reload registers.
5850 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5851 is the array we use to restore the reg_rtx field for every reload. */
5854 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5858 for (i = 0; i < n_reloads; i++)
5859 rld[i].reg_rtx = save_reload_reg_rtx[i];
5861 memset (reload_inherited, 0, MAX_RELOADS);
5862 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5863 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5865 CLEAR_HARD_REG_SET (reload_reg_used);
5866 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5867 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5868 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5869 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5870 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5872 CLEAR_HARD_REG_SET (reg_used_in_insn);
5875 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5876 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5877 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5878 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5879 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5880 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5883 for (i = 0; i < reload_n_operands; i++)
5885 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5886 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5887 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5888 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5889 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5890 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5893 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5895 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5897 for (i = 0; i < n_reloads; i++)
5898 /* If we have already decided to use a certain register,
5899 don't use it in another way. */
5901 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5902 rld[i].when_needed, rld[i].mode);
5905 /* Assign hard reg targets for the pseudo-registers we must reload
5906 into hard regs for this insn.
5907 Also output the instructions to copy them in and out of the hard regs.
5909 For machines with register classes, we are responsible for
5910 finding a reload reg in the proper class. */
5913 choose_reload_regs (struct insn_chain *chain)
5915 rtx insn = chain->insn;
5917 unsigned int max_group_size = 1;
5918 enum reg_class group_class = NO_REGS;
5919 int pass, win, inheritance;
5921 rtx save_reload_reg_rtx[MAX_RELOADS];
5923 /* In order to be certain of getting the registers we need,
5924 we must sort the reloads into order of increasing register class.
5925 Then our grabbing of reload registers will parallel the process
5926 that provided the reload registers.
5928 Also note whether any of the reloads wants a consecutive group of regs.
5929 If so, record the maximum size of the group desired and what
5930 register class contains all the groups needed by this insn. */
5932 for (j = 0; j < n_reloads; j++)
5934 reload_order[j] = j;
5935 if (rld[j].reg_rtx != NULL_RTX)
5937 gcc_assert (REG_P (rld[j].reg_rtx)
5938 && HARD_REGISTER_P (rld[j].reg_rtx));
5939 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
5942 reload_spill_index[j] = -1;
5944 if (rld[j].nregs > 1)
5946 max_group_size = MAX (rld[j].nregs, max_group_size);
5948 = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
5951 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5955 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5957 /* If -O, try first with inheritance, then turning it off.
5958 If not -O, don't do inheritance.
5959 Using inheritance when not optimizing leads to paradoxes
5960 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5961 because one side of the comparison might be inherited. */
5963 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5965 choose_reload_regs_init (chain, save_reload_reg_rtx);
5967 /* Process the reloads in order of preference just found.
5968 Beyond this point, subregs can be found in reload_reg_rtx.
5970 This used to look for an existing reloaded home for all of the
5971 reloads, and only then perform any new reloads. But that could lose
5972 if the reloads were done out of reg-class order because a later
5973 reload with a looser constraint might have an old home in a register
5974 needed by an earlier reload with a tighter constraint.
5976 To solve this, we make two passes over the reloads, in the order
5977 described above. In the first pass we try to inherit a reload
5978 from a previous insn. If there is a later reload that needs a
5979 class that is a proper subset of the class being processed, we must
5980 also allocate a spill register during the first pass.
5982 Then make a second pass over the reloads to allocate any reloads
5983 that haven't been given registers yet. */
5985 for (j = 0; j < n_reloads; j++)
5987 int r = reload_order[j];
5988 rtx search_equiv = NULL_RTX;
5990 /* Ignore reloads that got marked inoperative. */
5991 if (rld[r].out == 0 && rld[r].in == 0
5992 && ! rld[r].secondary_p)
5995 /* If find_reloads chose to use reload_in or reload_out as a reload
5996 register, we don't need to chose one. Otherwise, try even if it
5997 found one since we might save an insn if we find the value lying
5999 Try also when reload_in is a pseudo without a hard reg. */
6000 if (rld[r].in != 0 && rld[r].reg_rtx != 0
6001 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
6002 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
6003 && !MEM_P (rld[r].in)
6004 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
6007 #if 0 /* No longer needed for correct operation.
6008 It might give better code, or might not; worth an experiment? */
6009 /* If this is an optional reload, we can't inherit from earlier insns
6010 until we are sure that any non-optional reloads have been allocated.
6011 The following code takes advantage of the fact that optional reloads
6012 are at the end of reload_order. */
6013 if (rld[r].optional != 0)
6014 for (i = 0; i < j; i++)
6015 if ((rld[reload_order[i]].out != 0
6016 || rld[reload_order[i]].in != 0
6017 || rld[reload_order[i]].secondary_p)
6018 && ! rld[reload_order[i]].optional
6019 && rld[reload_order[i]].reg_rtx == 0)
6020 allocate_reload_reg (chain, reload_order[i], 0);
6023 /* First see if this pseudo is already available as reloaded
6024 for a previous insn. We cannot try to inherit for reloads
6025 that are smaller than the maximum number of registers needed
6026 for groups unless the register we would allocate cannot be used
6029 We could check here to see if this is a secondary reload for
6030 an object that is already in a register of the desired class.
6031 This would avoid the need for the secondary reload register.
6032 But this is complex because we can't easily determine what
6033 objects might want to be loaded via this reload. So let a
6034 register be allocated here. In `emit_reload_insns' we suppress
6035 one of the loads in the case described above. */
6041 enum machine_mode mode = VOIDmode;
6045 else if (REG_P (rld[r].in))
6047 regno = REGNO (rld[r].in);
6048 mode = GET_MODE (rld[r].in);
6050 else if (REG_P (rld[r].in_reg))
6052 regno = REGNO (rld[r].in_reg);
6053 mode = GET_MODE (rld[r].in_reg);
6055 else if (GET_CODE (rld[r].in_reg) == SUBREG
6056 && REG_P (SUBREG_REG (rld[r].in_reg)))
6058 regno = REGNO (SUBREG_REG (rld[r].in_reg));
6059 if (regno < FIRST_PSEUDO_REGISTER)
6060 regno = subreg_regno (rld[r].in_reg);
6062 byte = SUBREG_BYTE (rld[r].in_reg);
6063 mode = GET_MODE (rld[r].in_reg);
6066 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6067 && REG_P (XEXP (rld[r].in_reg, 0)))
6069 regno = REGNO (XEXP (rld[r].in_reg, 0));
6070 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6071 rld[r].out = rld[r].in;
6075 /* This won't work, since REGNO can be a pseudo reg number.
6076 Also, it takes much more hair to keep track of all the things
6077 that can invalidate an inherited reload of part of a pseudoreg. */
6078 else if (GET_CODE (rld[r].in) == SUBREG
6079 && REG_P (SUBREG_REG (rld[r].in)))
6080 regno = subreg_regno (rld[r].in);
6084 && reg_last_reload_reg[regno] != 0
6085 #ifdef CANNOT_CHANGE_MODE_CLASS
6086 /* Verify that the register it's in can be used in
6088 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
6089 GET_MODE (reg_last_reload_reg[regno]),
6094 enum reg_class rclass = rld[r].rclass, last_class;
6095 rtx last_reg = reg_last_reload_reg[regno];
6096 enum machine_mode need_mode;
6098 i = REGNO (last_reg);
6099 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6100 last_class = REGNO_REG_CLASS (i);
6106 = smallest_mode_for_size
6107 (GET_MODE_BITSIZE (mode) + byte * BITS_PER_UNIT,
6108 GET_MODE_CLASS (mode) == MODE_PARTIAL_INT
6109 ? MODE_INT : GET_MODE_CLASS (mode));
6111 if ((GET_MODE_SIZE (GET_MODE (last_reg))
6112 >= GET_MODE_SIZE (need_mode))
6113 && reg_reloaded_contents[i] == regno
6114 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6115 && HARD_REGNO_MODE_OK (i, rld[r].mode)
6116 && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6117 /* Even if we can't use this register as a reload
6118 register, we might use it for reload_override_in,
6119 if copying it to the desired class is cheap
6121 || ((REGISTER_MOVE_COST (mode, last_class, rclass)
6122 < MEMORY_MOVE_COST (mode, rclass, 1))
6123 && (secondary_reload_class (1, rclass, mode,
6126 #ifdef SECONDARY_MEMORY_NEEDED
6127 && ! SECONDARY_MEMORY_NEEDED (last_class, rclass,
6132 && (rld[r].nregs == max_group_size
6133 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6135 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6136 rld[r].when_needed, rld[r].in,
6139 /* If a group is needed, verify that all the subsequent
6140 registers still have their values intact. */
6141 int nr = hard_regno_nregs[i][rld[r].mode];
6144 for (k = 1; k < nr; k++)
6145 if (reg_reloaded_contents[i + k] != regno
6146 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6154 last_reg = (GET_MODE (last_reg) == mode
6155 ? last_reg : gen_rtx_REG (mode, i));
6158 for (k = 0; k < nr; k++)
6159 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6162 /* We found a register that contains the
6163 value we need. If this register is the
6164 same as an `earlyclobber' operand of the
6165 current insn, just mark it as a place to
6166 reload from since we can't use it as the
6167 reload register itself. */
6169 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6170 if (reg_overlap_mentioned_for_reload_p
6171 (reg_last_reload_reg[regno],
6172 reload_earlyclobbers[i1]))
6175 if (i1 != n_earlyclobbers
6176 || ! (free_for_value_p (i, rld[r].mode,
6178 rld[r].when_needed, rld[r].in,
6180 /* Don't use it if we'd clobber a pseudo reg. */
6181 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6183 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6184 /* Don't clobber the frame pointer. */
6185 || (i == HARD_FRAME_POINTER_REGNUM
6186 && frame_pointer_needed
6188 /* Don't really use the inherited spill reg
6189 if we need it wider than we've got it. */
6190 || (GET_MODE_SIZE (rld[r].mode)
6191 > GET_MODE_SIZE (mode))
6194 /* If find_reloads chose reload_out as reload
6195 register, stay with it - that leaves the
6196 inherited register for subsequent reloads. */
6197 || (rld[r].out && rld[r].reg_rtx
6198 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6200 if (! rld[r].optional)
6202 reload_override_in[r] = last_reg;
6203 reload_inheritance_insn[r]
6204 = reg_reloaded_insn[i];
6210 /* We can use this as a reload reg. */
6211 /* Mark the register as in use for this part of
6213 mark_reload_reg_in_use (i,
6217 rld[r].reg_rtx = last_reg;
6218 reload_inherited[r] = 1;
6219 reload_inheritance_insn[r]
6220 = reg_reloaded_insn[i];
6221 reload_spill_index[r] = i;
6222 for (k = 0; k < nr; k++)
6223 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6231 /* Here's another way to see if the value is already lying around. */
6234 && ! reload_inherited[r]
6236 && (CONSTANT_P (rld[r].in)
6237 || GET_CODE (rld[r].in) == PLUS
6238 || REG_P (rld[r].in)
6239 || MEM_P (rld[r].in))
6240 && (rld[r].nregs == max_group_size
6241 || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6242 search_equiv = rld[r].in;
6243 /* If this is an output reload from a simple move insn, look
6244 if an equivalence for the input is available. */
6245 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
6247 rtx set = single_set (insn);
6250 && rtx_equal_p (rld[r].out, SET_DEST (set))
6251 && CONSTANT_P (SET_SRC (set)))
6252 search_equiv = SET_SRC (set);
6258 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6259 -1, NULL, 0, rld[r].mode);
6265 regno = REGNO (equiv);
6268 /* This must be a SUBREG of a hard register.
6269 Make a new REG since this might be used in an
6270 address and not all machines support SUBREGs
6272 gcc_assert (GET_CODE (equiv) == SUBREG);
6273 regno = subreg_regno (equiv);
6274 equiv = gen_rtx_REG (rld[r].mode, regno);
6275 /* If we choose EQUIV as the reload register, but the
6276 loop below decides to cancel the inheritance, we'll
6277 end up reloading EQUIV in rld[r].mode, not the mode
6278 it had originally. That isn't safe when EQUIV isn't
6279 available as a spill register since its value might
6280 still be live at this point. */
6281 for (i = regno; i < regno + (int) rld[r].nregs; i++)
6282 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6287 /* If we found a spill reg, reject it unless it is free
6288 and of the desired class. */
6292 int bad_for_class = 0;
6293 int max_regno = regno + rld[r].nregs;
6295 for (i = regno; i < max_regno; i++)
6297 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6299 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6304 && ! free_for_value_p (regno, rld[r].mode,
6305 rld[r].opnum, rld[r].when_needed,
6306 rld[r].in, rld[r].out, r, 1))
6311 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6314 /* We found a register that contains the value we need.
6315 If this register is the same as an `earlyclobber' operand
6316 of the current insn, just mark it as a place to reload from
6317 since we can't use it as the reload register itself. */
6320 for (i = 0; i < n_earlyclobbers; i++)
6321 if (reg_overlap_mentioned_for_reload_p (equiv,
6322 reload_earlyclobbers[i]))
6324 if (! rld[r].optional)
6325 reload_override_in[r] = equiv;
6330 /* If the equiv register we have found is explicitly clobbered
6331 in the current insn, it depends on the reload type if we
6332 can use it, use it for reload_override_in, or not at all.
6333 In particular, we then can't use EQUIV for a
6334 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6338 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6339 switch (rld[r].when_needed)
6341 case RELOAD_FOR_OTHER_ADDRESS:
6342 case RELOAD_FOR_INPADDR_ADDRESS:
6343 case RELOAD_FOR_INPUT_ADDRESS:
6344 case RELOAD_FOR_OPADDR_ADDR:
6347 case RELOAD_FOR_INPUT:
6348 case RELOAD_FOR_OPERAND_ADDRESS:
6349 if (! rld[r].optional)
6350 reload_override_in[r] = equiv;
6356 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6357 switch (rld[r].when_needed)
6359 case RELOAD_FOR_OTHER_ADDRESS:
6360 case RELOAD_FOR_INPADDR_ADDRESS:
6361 case RELOAD_FOR_INPUT_ADDRESS:
6362 case RELOAD_FOR_OPADDR_ADDR:
6363 case RELOAD_FOR_OPERAND_ADDRESS:
6364 case RELOAD_FOR_INPUT:
6367 if (! rld[r].optional)
6368 reload_override_in[r] = equiv;
6376 /* If we found an equivalent reg, say no code need be generated
6377 to load it, and use it as our reload reg. */
6379 && (regno != HARD_FRAME_POINTER_REGNUM
6380 || !frame_pointer_needed))
6382 int nr = hard_regno_nregs[regno][rld[r].mode];
6384 rld[r].reg_rtx = equiv;
6385 reload_spill_index[r] = regno;
6386 reload_inherited[r] = 1;
6388 /* If reg_reloaded_valid is not set for this register,
6389 there might be a stale spill_reg_store lying around.
6390 We must clear it, since otherwise emit_reload_insns
6391 might delete the store. */
6392 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6393 spill_reg_store[regno] = NULL_RTX;
6394 /* If any of the hard registers in EQUIV are spill
6395 registers, mark them as in use for this insn. */
6396 for (k = 0; k < nr; k++)
6398 i = spill_reg_order[regno + k];
6401 mark_reload_reg_in_use (regno, rld[r].opnum,
6404 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6411 /* If we found a register to use already, or if this is an optional
6412 reload, we are done. */
6413 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6417 /* No longer needed for correct operation. Might or might
6418 not give better code on the average. Want to experiment? */
6420 /* See if there is a later reload that has a class different from our
6421 class that intersects our class or that requires less register
6422 than our reload. If so, we must allocate a register to this
6423 reload now, since that reload might inherit a previous reload
6424 and take the only available register in our class. Don't do this
6425 for optional reloads since they will force all previous reloads
6426 to be allocated. Also don't do this for reloads that have been
6429 for (i = j + 1; i < n_reloads; i++)
6431 int s = reload_order[i];
6433 if ((rld[s].in == 0 && rld[s].out == 0
6434 && ! rld[s].secondary_p)
6438 if ((rld[s].rclass != rld[r].rclass
6439 && reg_classes_intersect_p (rld[r].rclass,
6441 || rld[s].nregs < rld[r].nregs)
6448 allocate_reload_reg (chain, r, j == n_reloads - 1);
6452 /* Now allocate reload registers for anything non-optional that
6453 didn't get one yet. */
6454 for (j = 0; j < n_reloads; j++)
6456 int r = reload_order[j];
6458 /* Ignore reloads that got marked inoperative. */
6459 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6462 /* Skip reloads that already have a register allocated or are
6464 if (rld[r].reg_rtx != 0 || rld[r].optional)
6467 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6471 /* If that loop got all the way, we have won. */
6478 /* Loop around and try without any inheritance. */
6483 /* First undo everything done by the failed attempt
6484 to allocate with inheritance. */
6485 choose_reload_regs_init (chain, save_reload_reg_rtx);
6487 /* Some sanity tests to verify that the reloads found in the first
6488 pass are identical to the ones we have now. */
6489 gcc_assert (chain->n_reloads == n_reloads);
6491 for (i = 0; i < n_reloads; i++)
6493 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6495 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6496 for (j = 0; j < n_spills; j++)
6497 if (spill_regs[j] == chain->rld[i].regno)
6498 if (! set_reload_reg (j, i))
6499 failed_reload (chain->insn, i);
6503 /* If we thought we could inherit a reload, because it seemed that
6504 nothing else wanted the same reload register earlier in the insn,
6505 verify that assumption, now that all reloads have been assigned.
6506 Likewise for reloads where reload_override_in has been set. */
6508 /* If doing expensive optimizations, do one preliminary pass that doesn't
6509 cancel any inheritance, but removes reloads that have been needed only
6510 for reloads that we know can be inherited. */
6511 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6513 for (j = 0; j < n_reloads; j++)
6515 int r = reload_order[j];
6517 if (reload_inherited[r] && rld[r].reg_rtx)
6518 check_reg = rld[r].reg_rtx;
6519 else if (reload_override_in[r]
6520 && (REG_P (reload_override_in[r])
6521 || GET_CODE (reload_override_in[r]) == SUBREG))
6522 check_reg = reload_override_in[r];
6525 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6526 rld[r].opnum, rld[r].when_needed, rld[r].in,
6527 (reload_inherited[r]
6528 ? rld[r].out : const0_rtx),
6533 reload_inherited[r] = 0;
6534 reload_override_in[r] = 0;
6536 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6537 reload_override_in, then we do not need its related
6538 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6539 likewise for other reload types.
6540 We handle this by removing a reload when its only replacement
6541 is mentioned in reload_in of the reload we are going to inherit.
6542 A special case are auto_inc expressions; even if the input is
6543 inherited, we still need the address for the output. We can
6544 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6545 If we succeeded removing some reload and we are doing a preliminary
6546 pass just to remove such reloads, make another pass, since the
6547 removal of one reload might allow us to inherit another one. */
6549 && rld[r].out != rld[r].in
6550 && remove_address_replacements (rld[r].in) && pass)
6555 /* Now that reload_override_in is known valid,
6556 actually override reload_in. */
6557 for (j = 0; j < n_reloads; j++)
6558 if (reload_override_in[j])
6559 rld[j].in = reload_override_in[j];
6561 /* If this reload won't be done because it has been canceled or is
6562 optional and not inherited, clear reload_reg_rtx so other
6563 routines (such as subst_reloads) don't get confused. */
6564 for (j = 0; j < n_reloads; j++)
6565 if (rld[j].reg_rtx != 0
6566 && ((rld[j].optional && ! reload_inherited[j])
6567 || (rld[j].in == 0 && rld[j].out == 0
6568 && ! rld[j].secondary_p)))
6570 int regno = true_regnum (rld[j].reg_rtx);
6572 if (spill_reg_order[regno] >= 0)
6573 clear_reload_reg_in_use (regno, rld[j].opnum,
6574 rld[j].when_needed, rld[j].mode);
6576 reload_spill_index[j] = -1;
6579 /* Record which pseudos and which spill regs have output reloads. */
6580 for (j = 0; j < n_reloads; j++)
6582 int r = reload_order[j];
6584 i = reload_spill_index[r];
6586 /* I is nonneg if this reload uses a register.
6587 If rld[r].reg_rtx is 0, this is an optional reload
6588 that we opted to ignore. */
6589 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6590 && rld[r].reg_rtx != 0)
6592 int nregno = REGNO (rld[r].out_reg);
6595 if (nregno < FIRST_PSEUDO_REGISTER)
6596 nr = hard_regno_nregs[nregno][rld[r].mode];
6599 SET_REGNO_REG_SET (®_has_output_reload,
6604 nr = hard_regno_nregs[i][rld[r].mode];
6606 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6609 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6610 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6611 || rld[r].when_needed == RELOAD_FOR_INSN);
6616 /* Deallocate the reload register for reload R. This is called from
6617 remove_address_replacements. */
6620 deallocate_reload_reg (int r)
6624 if (! rld[r].reg_rtx)
6626 regno = true_regnum (rld[r].reg_rtx);
6628 if (spill_reg_order[regno] >= 0)
6629 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6631 reload_spill_index[r] = -1;
6634 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6635 reloads of the same item for fear that we might not have enough reload
6636 registers. However, normally they will get the same reload register
6637 and hence actually need not be loaded twice.
6639 Here we check for the most common case of this phenomenon: when we have
6640 a number of reloads for the same object, each of which were allocated
6641 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6642 reload, and is not modified in the insn itself. If we find such,
6643 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6644 This will not increase the number of spill registers needed and will
6645 prevent redundant code. */
6648 merge_assigned_reloads (rtx insn)
6652 /* Scan all the reloads looking for ones that only load values and
6653 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6654 assigned and not modified by INSN. */
6656 for (i = 0; i < n_reloads; i++)
6658 int conflicting_input = 0;
6659 int max_input_address_opnum = -1;
6660 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6662 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6663 || rld[i].out != 0 || rld[i].reg_rtx == 0
6664 || reg_set_p (rld[i].reg_rtx, insn))
6667 /* Look at all other reloads. Ensure that the only use of this
6668 reload_reg_rtx is in a reload that just loads the same value
6669 as we do. Note that any secondary reloads must be of the identical
6670 class since the values, modes, and result registers are the
6671 same, so we need not do anything with any secondary reloads. */
6673 for (j = 0; j < n_reloads; j++)
6675 if (i == j || rld[j].reg_rtx == 0
6676 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6680 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6681 && rld[j].opnum > max_input_address_opnum)
6682 max_input_address_opnum = rld[j].opnum;
6684 /* If the reload regs aren't exactly the same (e.g, different modes)
6685 or if the values are different, we can't merge this reload.
6686 But if it is an input reload, we might still merge
6687 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6689 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6690 || rld[j].out != 0 || rld[j].in == 0
6691 || ! rtx_equal_p (rld[i].in, rld[j].in))
6693 if (rld[j].when_needed != RELOAD_FOR_INPUT
6694 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6695 || rld[i].opnum > rld[j].opnum)
6696 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6698 conflicting_input = 1;
6699 if (min_conflicting_input_opnum > rld[j].opnum)
6700 min_conflicting_input_opnum = rld[j].opnum;
6704 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6705 we, in fact, found any matching reloads. */
6708 && max_input_address_opnum <= min_conflicting_input_opnum)
6710 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6712 for (j = 0; j < n_reloads; j++)
6713 if (i != j && rld[j].reg_rtx != 0
6714 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6715 && (! conflicting_input
6716 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6717 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6719 rld[i].when_needed = RELOAD_OTHER;
6721 reload_spill_index[j] = -1;
6722 transfer_replacements (i, j);
6725 /* If this is now RELOAD_OTHER, look for any reloads that
6726 load parts of this operand and set them to
6727 RELOAD_FOR_OTHER_ADDRESS if they were for inputs,
6728 RELOAD_OTHER for outputs. Note that this test is
6729 equivalent to looking for reloads for this operand
6732 We must take special care with RELOAD_FOR_OUTPUT_ADDRESS;
6733 it may share registers with a RELOAD_FOR_INPUT, so we can
6734 not change it to RELOAD_FOR_OTHER_ADDRESS. We should
6735 never need to, since we do not modify RELOAD_FOR_OUTPUT.
6737 It is possible that the RELOAD_FOR_OPERAND_ADDRESS
6738 instruction is assigned the same register as the earlier
6739 RELOAD_FOR_OTHER_ADDRESS instruction. Merging these two
6740 instructions will cause the RELOAD_FOR_OTHER_ADDRESS
6741 instruction to be deleted later on. */
6743 if (rld[i].when_needed == RELOAD_OTHER)
6744 for (j = 0; j < n_reloads; j++)
6746 && rld[j].when_needed != RELOAD_OTHER
6747 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6748 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6749 && rld[j].when_needed != RELOAD_FOR_OPERAND_ADDRESS
6750 && (! conflicting_input
6751 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6752 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6753 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6759 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6760 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6761 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6763 /* Check to see if we accidentally converted two
6764 reloads that use the same reload register with
6765 different inputs to the same type. If so, the
6766 resulting code won't work. */
6768 for (k = 0; k < j; k++)
6769 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6770 || rld[k].when_needed != rld[j].when_needed
6771 || !rtx_equal_p (rld[k].reg_rtx,
6773 || rtx_equal_p (rld[k].in,
6780 /* These arrays are filled by emit_reload_insns and its subroutines. */
6781 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6782 static rtx other_input_address_reload_insns = 0;
6783 static rtx other_input_reload_insns = 0;
6784 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6785 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6786 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6787 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6788 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6789 static rtx operand_reload_insns = 0;
6790 static rtx other_operand_reload_insns = 0;
6791 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6793 /* Values to be put in spill_reg_store are put here first. */
6794 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6795 static HARD_REG_SET reg_reloaded_died;
6797 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6798 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6799 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6800 adjusted register, and return true. Otherwise, return false. */
6802 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6803 enum reg_class new_class,
6804 enum machine_mode new_mode)
6809 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6811 unsigned regno = REGNO (reg);
6813 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6815 if (GET_MODE (reg) != new_mode)
6817 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6819 if (hard_regno_nregs[regno][new_mode]
6820 > hard_regno_nregs[regno][GET_MODE (reg)])
6822 reg = reload_adjust_reg_for_mode (reg, new_mode);
6830 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6831 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6832 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6833 adjusted register, and return true. Otherwise, return false. */
6835 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6836 enum insn_code icode)
6839 enum reg_class new_class = scratch_reload_class (icode);
6840 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6842 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6843 new_class, new_mode);
6846 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6847 has the number J. OLD contains the value to be used as input. */
6850 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6853 rtx insn = chain->insn;
6855 rtx oldequiv_reg = 0;
6858 enum machine_mode mode;
6861 /* delete_output_reload is only invoked properly if old contains
6862 the original pseudo register. Since this is replaced with a
6863 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6864 find the pseudo in RELOAD_IN_REG. */
6865 if (reload_override_in[j]
6866 && REG_P (rl->in_reg))
6873 else if (REG_P (oldequiv))
6874 oldequiv_reg = oldequiv;
6875 else if (GET_CODE (oldequiv) == SUBREG)
6876 oldequiv_reg = SUBREG_REG (oldequiv);
6878 reloadreg = reload_reg_rtx_for_input[j];
6879 mode = GET_MODE (reloadreg);
6881 /* If we are reloading from a register that was recently stored in
6882 with an output-reload, see if we can prove there was
6883 actually no need to store the old value in it. */
6885 if (optimize && REG_P (oldequiv)
6886 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6887 && spill_reg_store[REGNO (oldequiv)]
6889 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6890 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6892 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6894 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
6897 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6898 oldequiv = SUBREG_REG (oldequiv);
6899 if (GET_MODE (oldequiv) != VOIDmode
6900 && mode != GET_MODE (oldequiv))
6901 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6903 /* Switch to the right place to emit the reload insns. */
6904 switch (rl->when_needed)
6907 where = &other_input_reload_insns;
6909 case RELOAD_FOR_INPUT:
6910 where = &input_reload_insns[rl->opnum];
6912 case RELOAD_FOR_INPUT_ADDRESS:
6913 where = &input_address_reload_insns[rl->opnum];
6915 case RELOAD_FOR_INPADDR_ADDRESS:
6916 where = &inpaddr_address_reload_insns[rl->opnum];
6918 case RELOAD_FOR_OUTPUT_ADDRESS:
6919 where = &output_address_reload_insns[rl->opnum];
6921 case RELOAD_FOR_OUTADDR_ADDRESS:
6922 where = &outaddr_address_reload_insns[rl->opnum];
6924 case RELOAD_FOR_OPERAND_ADDRESS:
6925 where = &operand_reload_insns;
6927 case RELOAD_FOR_OPADDR_ADDR:
6928 where = &other_operand_reload_insns;
6930 case RELOAD_FOR_OTHER_ADDRESS:
6931 where = &other_input_address_reload_insns;
6937 push_to_sequence (*where);
6939 /* Auto-increment addresses must be reloaded in a special way. */
6940 if (rl->out && ! rl->out_reg)
6942 /* We are not going to bother supporting the case where a
6943 incremented register can't be copied directly from
6944 OLDEQUIV since this seems highly unlikely. */
6945 gcc_assert (rl->secondary_in_reload < 0);
6947 if (reload_inherited[j])
6948 oldequiv = reloadreg;
6950 old = XEXP (rl->in_reg, 0);
6952 if (optimize && REG_P (oldequiv)
6953 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6954 && spill_reg_store[REGNO (oldequiv)]
6956 && (dead_or_set_p (insn,
6957 spill_reg_stored_to[REGNO (oldequiv)])
6958 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6960 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6962 /* Prevent normal processing of this reload. */
6964 /* Output a special code sequence for this case. */
6965 new_spill_reg_store[REGNO (reloadreg)]
6966 = inc_for_reload (reloadreg, oldequiv, rl->out,
6970 /* If we are reloading a pseudo-register that was set by the previous
6971 insn, see if we can get rid of that pseudo-register entirely
6972 by redirecting the previous insn into our reload register. */
6974 else if (optimize && REG_P (old)
6975 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6976 && dead_or_set_p (insn, old)
6977 /* This is unsafe if some other reload
6978 uses the same reg first. */
6979 && ! conflicts_with_override (reloadreg)
6980 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6981 rl->when_needed, old, rl->out, j, 0))
6983 rtx temp = PREV_INSN (insn);
6984 while (temp && (NOTE_P (temp) || DEBUG_INSN_P (temp)))
6985 temp = PREV_INSN (temp);
6987 && NONJUMP_INSN_P (temp)
6988 && GET_CODE (PATTERN (temp)) == SET
6989 && SET_DEST (PATTERN (temp)) == old
6990 /* Make sure we can access insn_operand_constraint. */
6991 && asm_noperands (PATTERN (temp)) < 0
6992 /* This is unsafe if operand occurs more than once in current
6993 insn. Perhaps some occurrences aren't reloaded. */
6994 && count_occurrences (PATTERN (insn), old, 0) == 1)
6996 rtx old = SET_DEST (PATTERN (temp));
6997 /* Store into the reload register instead of the pseudo. */
6998 SET_DEST (PATTERN (temp)) = reloadreg;
7000 /* Verify that resulting insn is valid. */
7001 extract_insn (temp);
7002 if (constrain_operands (1))
7004 /* If the previous insn is an output reload, the source is
7005 a reload register, and its spill_reg_store entry will
7006 contain the previous destination. This is now
7008 if (REG_P (SET_SRC (PATTERN (temp)))
7009 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
7011 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7012 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7015 /* If these are the only uses of the pseudo reg,
7016 pretend for GDB it lives in the reload reg we used. */
7017 if (REG_N_DEATHS (REGNO (old)) == 1
7018 && REG_N_SETS (REGNO (old)) == 1)
7020 reg_renumber[REGNO (old)] = REGNO (reloadreg);
7021 if (ira_conflicts_p)
7022 /* Inform IRA about the change. */
7023 ira_mark_allocation_change (REGNO (old));
7024 alter_reg (REGNO (old), -1, false);
7028 /* Adjust any debug insns between temp and insn. */
7029 while ((temp = NEXT_INSN (temp)) != insn)
7030 if (DEBUG_INSN_P (temp))
7031 replace_rtx (PATTERN (temp), old, reloadreg);
7033 gcc_assert (NOTE_P (temp));
7037 SET_DEST (PATTERN (temp)) = old;
7042 /* We can't do that, so output an insn to load RELOADREG. */
7044 /* If we have a secondary reload, pick up the secondary register
7045 and icode, if any. If OLDEQUIV and OLD are different or
7046 if this is an in-out reload, recompute whether or not we
7047 still need a secondary register and what the icode should
7048 be. If we still need a secondary register and the class or
7049 icode is different, go back to reloading from OLD if using
7050 OLDEQUIV means that we got the wrong type of register. We
7051 cannot have different class or icode due to an in-out reload
7052 because we don't make such reloads when both the input and
7053 output need secondary reload registers. */
7055 if (! special && rl->secondary_in_reload >= 0)
7057 rtx second_reload_reg = 0;
7058 rtx third_reload_reg = 0;
7059 int secondary_reload = rl->secondary_in_reload;
7060 rtx real_oldequiv = oldequiv;
7063 enum insn_code icode;
7064 enum insn_code tertiary_icode = CODE_FOR_nothing;
7066 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7067 and similarly for OLD.
7068 See comments in get_secondary_reload in reload.c. */
7069 /* If it is a pseudo that cannot be replaced with its
7070 equivalent MEM, we must fall back to reload_in, which
7071 will have all the necessary substitutions registered.
7072 Likewise for a pseudo that can't be replaced with its
7073 equivalent constant.
7075 Take extra care for subregs of such pseudos. Note that
7076 we cannot use reg_equiv_mem in this case because it is
7077 not in the right mode. */
7080 if (GET_CODE (tmp) == SUBREG)
7081 tmp = SUBREG_REG (tmp);
7083 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7084 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
7085 || reg_equiv_constant[REGNO (tmp)] != 0))
7087 if (! reg_equiv_mem[REGNO (tmp)]
7088 || num_not_at_initial_offset
7089 || GET_CODE (oldequiv) == SUBREG)
7090 real_oldequiv = rl->in;
7092 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
7096 if (GET_CODE (tmp) == SUBREG)
7097 tmp = SUBREG_REG (tmp);
7099 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7100 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
7101 || reg_equiv_constant[REGNO (tmp)] != 0))
7103 if (! reg_equiv_mem[REGNO (tmp)]
7104 || num_not_at_initial_offset
7105 || GET_CODE (old) == SUBREG)
7108 real_old = reg_equiv_mem[REGNO (tmp)];
7111 second_reload_reg = rld[secondary_reload].reg_rtx;
7112 if (rld[secondary_reload].secondary_in_reload >= 0)
7114 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7116 third_reload_reg = rld[tertiary_reload].reg_rtx;
7117 tertiary_icode = rld[secondary_reload].secondary_in_icode;
7118 /* We'd have to add more code for quartary reloads. */
7119 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7121 icode = rl->secondary_in_icode;
7123 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7124 || (rl->in != 0 && rl->out != 0))
7126 secondary_reload_info sri, sri2;
7127 enum reg_class new_class, new_t_class;
7129 sri.icode = CODE_FOR_nothing;
7130 sri.prev_sri = NULL;
7131 new_class = targetm.secondary_reload (1, real_oldequiv, rl->rclass,
7134 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7135 second_reload_reg = 0;
7136 else if (new_class == NO_REGS)
7138 if (reload_adjust_reg_for_icode (&second_reload_reg,
7140 (enum insn_code) sri.icode))
7142 icode = (enum insn_code) sri.icode;
7143 third_reload_reg = 0;
7148 real_oldequiv = real_old;
7151 else if (sri.icode != CODE_FOR_nothing)
7152 /* We currently lack a way to express this in reloads. */
7156 sri2.icode = CODE_FOR_nothing;
7157 sri2.prev_sri = &sri;
7158 new_t_class = targetm.secondary_reload (1, real_oldequiv,
7159 new_class, mode, &sri);
7160 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7162 if (reload_adjust_reg_for_temp (&second_reload_reg,
7166 third_reload_reg = 0;
7167 tertiary_icode = (enum insn_code) sri2.icode;
7172 real_oldequiv = real_old;
7175 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7177 rtx intermediate = second_reload_reg;
7179 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7181 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7185 second_reload_reg = intermediate;
7186 tertiary_icode = (enum insn_code) sri2.icode;
7191 real_oldequiv = real_old;
7194 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7196 rtx intermediate = second_reload_reg;
7198 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7200 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7203 second_reload_reg = intermediate;
7204 tertiary_icode = (enum insn_code) sri2.icode;
7209 real_oldequiv = real_old;
7214 /* This could be handled more intelligently too. */
7216 real_oldequiv = real_old;
7221 /* If we still need a secondary reload register, check
7222 to see if it is being used as a scratch or intermediate
7223 register and generate code appropriately. If we need
7224 a scratch register, use REAL_OLDEQUIV since the form of
7225 the insn may depend on the actual address if it is
7228 if (second_reload_reg)
7230 if (icode != CODE_FOR_nothing)
7232 /* We'd have to add extra code to handle this case. */
7233 gcc_assert (!third_reload_reg);
7235 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7236 second_reload_reg));
7241 /* See if we need a scratch register to load the
7242 intermediate register (a tertiary reload). */
7243 if (tertiary_icode != CODE_FOR_nothing)
7245 emit_insn ((GEN_FCN (tertiary_icode)
7246 (second_reload_reg, real_oldequiv,
7247 third_reload_reg)));
7249 else if (third_reload_reg)
7251 gen_reload (third_reload_reg, real_oldequiv,
7254 gen_reload (second_reload_reg, third_reload_reg,
7259 gen_reload (second_reload_reg, real_oldequiv,
7263 oldequiv = second_reload_reg;
7268 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7270 rtx real_oldequiv = oldequiv;
7272 if ((REG_P (oldequiv)
7273 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7274 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
7275 || reg_equiv_constant[REGNO (oldequiv)] != 0))
7276 || (GET_CODE (oldequiv) == SUBREG
7277 && REG_P (SUBREG_REG (oldequiv))
7278 && (REGNO (SUBREG_REG (oldequiv))
7279 >= FIRST_PSEUDO_REGISTER)
7280 && ((reg_equiv_memory_loc
7281 [REGNO (SUBREG_REG (oldequiv))] != 0)
7282 || (reg_equiv_constant
7283 [REGNO (SUBREG_REG (oldequiv))] != 0)))
7284 || (CONSTANT_P (oldequiv)
7285 && (PREFERRED_RELOAD_CLASS (oldequiv,
7286 REGNO_REG_CLASS (REGNO (reloadreg)))
7288 real_oldequiv = rl->in;
7289 gen_reload (reloadreg, real_oldequiv, rl->opnum,
7293 if (flag_non_call_exceptions)
7294 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7296 /* End this sequence. */
7297 *where = get_insns ();
7300 /* Update reload_override_in so that delete_address_reloads_1
7301 can see the actual register usage. */
7303 reload_override_in[j] = oldequiv;
7306 /* Generate insns to for the output reload RL, which is for the insn described
7307 by CHAIN and has the number J. */
7309 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7313 rtx insn = chain->insn;
7316 enum machine_mode mode;
7320 if (rl->when_needed == RELOAD_OTHER)
7323 push_to_sequence (output_reload_insns[rl->opnum]);
7325 rl_reg_rtx = reload_reg_rtx_for_output[j];
7326 mode = GET_MODE (rl_reg_rtx);
7328 reloadreg = rl_reg_rtx;
7330 /* If we need two reload regs, set RELOADREG to the intermediate
7331 one, since it will be stored into OLD. We might need a secondary
7332 register only for an input reload, so check again here. */
7334 if (rl->secondary_out_reload >= 0)
7337 int secondary_reload = rl->secondary_out_reload;
7338 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7340 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7341 && reg_equiv_mem[REGNO (old)] != 0)
7342 real_old = reg_equiv_mem[REGNO (old)];
7344 if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7346 rtx second_reloadreg = reloadreg;
7347 reloadreg = rld[secondary_reload].reg_rtx;
7349 /* See if RELOADREG is to be used as a scratch register
7350 or as an intermediate register. */
7351 if (rl->secondary_out_icode != CODE_FOR_nothing)
7353 /* We'd have to add extra code to handle this case. */
7354 gcc_assert (tertiary_reload < 0);
7356 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7357 (real_old, second_reloadreg, reloadreg)));
7362 /* See if we need both a scratch and intermediate reload
7365 enum insn_code tertiary_icode
7366 = rld[secondary_reload].secondary_out_icode;
7368 /* We'd have to add more code for quartary reloads. */
7369 gcc_assert (tertiary_reload < 0
7370 || rld[tertiary_reload].secondary_out_reload < 0);
7372 if (GET_MODE (reloadreg) != mode)
7373 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7375 if (tertiary_icode != CODE_FOR_nothing)
7377 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7380 /* Copy primary reload reg to secondary reload reg.
7381 (Note that these have been swapped above, then
7382 secondary reload reg to OLD using our insn.) */
7384 /* If REAL_OLD is a paradoxical SUBREG, remove it
7385 and try to put the opposite SUBREG on
7387 if (GET_CODE (real_old) == SUBREG
7388 && (GET_MODE_SIZE (GET_MODE (real_old))
7389 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7390 && 0 != (tem = gen_lowpart_common
7391 (GET_MODE (SUBREG_REG (real_old)),
7393 real_old = SUBREG_REG (real_old), reloadreg = tem;
7395 gen_reload (reloadreg, second_reloadreg,
7396 rl->opnum, rl->when_needed);
7397 emit_insn ((GEN_FCN (tertiary_icode)
7398 (real_old, reloadreg, third_reloadreg)));
7404 /* Copy between the reload regs here and then to
7407 gen_reload (reloadreg, second_reloadreg,
7408 rl->opnum, rl->when_needed);
7409 if (tertiary_reload >= 0)
7411 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7413 gen_reload (third_reloadreg, reloadreg,
7414 rl->opnum, rl->when_needed);
7415 reloadreg = third_reloadreg;
7422 /* Output the last reload insn. */
7427 /* Don't output the last reload if OLD is not the dest of
7428 INSN and is in the src and is clobbered by INSN. */
7429 if (! flag_expensive_optimizations
7431 || !(set = single_set (insn))
7432 || rtx_equal_p (old, SET_DEST (set))
7433 || !reg_mentioned_p (old, SET_SRC (set))
7434 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7435 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7436 gen_reload (old, reloadreg, rl->opnum,
7440 /* Look at all insns we emitted, just to be safe. */
7441 for (p = get_insns (); p; p = NEXT_INSN (p))
7444 rtx pat = PATTERN (p);
7446 /* If this output reload doesn't come from a spill reg,
7447 clear any memory of reloaded copies of the pseudo reg.
7448 If this output reload comes from a spill reg,
7449 reg_has_output_reload will make this do nothing. */
7450 note_stores (pat, forget_old_reloads_1, NULL);
7452 if (reg_mentioned_p (rl_reg_rtx, pat))
7454 rtx set = single_set (insn);
7455 if (reload_spill_index[j] < 0
7457 && SET_SRC (set) == rl_reg_rtx)
7459 int src = REGNO (SET_SRC (set));
7461 reload_spill_index[j] = src;
7462 SET_HARD_REG_BIT (reg_is_output_reload, src);
7463 if (find_regno_note (insn, REG_DEAD, src))
7464 SET_HARD_REG_BIT (reg_reloaded_died, src);
7466 if (HARD_REGISTER_P (rl_reg_rtx))
7468 int s = rl->secondary_out_reload;
7469 set = single_set (p);
7470 /* If this reload copies only to the secondary reload
7471 register, the secondary reload does the actual
7473 if (s >= 0 && set == NULL_RTX)
7474 /* We can't tell what function the secondary reload
7475 has and where the actual store to the pseudo is
7476 made; leave new_spill_reg_store alone. */
7479 && SET_SRC (set) == rl_reg_rtx
7480 && SET_DEST (set) == rld[s].reg_rtx)
7482 /* Usually the next instruction will be the
7483 secondary reload insn; if we can confirm
7484 that it is, setting new_spill_reg_store to
7485 that insn will allow an extra optimization. */
7486 rtx s_reg = rld[s].reg_rtx;
7487 rtx next = NEXT_INSN (p);
7488 rld[s].out = rl->out;
7489 rld[s].out_reg = rl->out_reg;
7490 set = single_set (next);
7491 if (set && SET_SRC (set) == s_reg
7492 && ! new_spill_reg_store[REGNO (s_reg)])
7494 SET_HARD_REG_BIT (reg_is_output_reload,
7496 new_spill_reg_store[REGNO (s_reg)] = next;
7500 new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7505 if (rl->when_needed == RELOAD_OTHER)
7507 emit_insn (other_output_reload_insns[rl->opnum]);
7508 other_output_reload_insns[rl->opnum] = get_insns ();
7511 output_reload_insns[rl->opnum] = get_insns ();
7513 if (flag_non_call_exceptions)
7514 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7519 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7520 and has the number J. */
7522 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7524 rtx insn = chain->insn;
7525 rtx old = (rl->in && MEM_P (rl->in)
7526 ? rl->in_reg : rl->in);
7527 rtx reg_rtx = rl->reg_rtx;
7531 enum machine_mode mode;
7533 /* Determine the mode to reload in.
7534 This is very tricky because we have three to choose from.
7535 There is the mode the insn operand wants (rl->inmode).
7536 There is the mode of the reload register RELOADREG.
7537 There is the intrinsic mode of the operand, which we could find
7538 by stripping some SUBREGs.
7539 It turns out that RELOADREG's mode is irrelevant:
7540 we can change that arbitrarily.
7542 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7543 then the reload reg may not support QImode moves, so use SImode.
7544 If foo is in memory due to spilling a pseudo reg, this is safe,
7545 because the QImode value is in the least significant part of a
7546 slot big enough for a SImode. If foo is some other sort of
7547 memory reference, then it is impossible to reload this case,
7548 so previous passes had better make sure this never happens.
7550 Then consider a one-word union which has SImode and one of its
7551 members is a float, being fetched as (SUBREG:SF union:SI).
7552 We must fetch that as SFmode because we could be loading into
7553 a float-only register. In this case OLD's mode is correct.
7555 Consider an immediate integer: it has VOIDmode. Here we need
7556 to get a mode from something else.
7558 In some cases, there is a fourth mode, the operand's
7559 containing mode. If the insn specifies a containing mode for
7560 this operand, it overrides all others.
7562 I am not sure whether the algorithm here is always right,
7563 but it does the right things in those cases. */
7565 mode = GET_MODE (old);
7566 if (mode == VOIDmode)
7569 /* We cannot use gen_lowpart_common since it can do the wrong thing
7570 when REG_RTX has a multi-word mode. Note that REG_RTX must
7571 always be a REG here. */
7572 if (GET_MODE (reg_rtx) != mode)
7573 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7575 reload_reg_rtx_for_input[j] = reg_rtx;
7578 /* AUTO_INC reloads need to be handled even if inherited. We got an
7579 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7580 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7581 && ! rtx_equal_p (reg_rtx, old)
7583 emit_input_reload_insns (chain, rld + j, old, j);
7585 /* When inheriting a wider reload, we have a MEM in rl->in,
7586 e.g. inheriting a SImode output reload for
7587 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7588 if (optimize && reload_inherited[j] && rl->in
7590 && MEM_P (rl->in_reg)
7591 && reload_spill_index[j] >= 0
7592 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7593 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7595 /* If we are reloading a register that was recently stored in with an
7596 output-reload, see if we can prove there was
7597 actually no need to store the old value in it. */
7600 && (reload_inherited[j] || reload_override_in[j])
7603 && spill_reg_store[REGNO (reg_rtx)] != 0
7605 /* There doesn't seem to be any reason to restrict this to pseudos
7606 and doing so loses in the case where we are copying from a
7607 register of the wrong class. */
7608 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7610 /* The insn might have already some references to stackslots
7611 replaced by MEMs, while reload_out_reg still names the
7613 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7614 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7615 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7618 /* Do output reloading for reload RL, which is for the insn described by
7619 CHAIN and has the number J.
7620 ??? At some point we need to support handling output reloads of
7621 JUMP_INSNs or insns that set cc0. */
7623 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7626 rtx insn = chain->insn;
7627 /* If this is an output reload that stores something that is
7628 not loaded in this same reload, see if we can eliminate a previous
7630 rtx pseudo = rl->out_reg;
7631 rtx reg_rtx = rl->reg_rtx;
7633 if (rl->out && reg_rtx)
7635 enum machine_mode mode;
7637 /* Determine the mode to reload in.
7638 See comments above (for input reloading). */
7639 mode = GET_MODE (rl->out);
7640 if (mode == VOIDmode)
7642 /* VOIDmode should never happen for an output. */
7643 if (asm_noperands (PATTERN (insn)) < 0)
7644 /* It's the compiler's fault. */
7645 fatal_insn ("VOIDmode on an output", insn);
7646 error_for_asm (insn, "output operand is constant in %<asm%>");
7647 /* Prevent crash--use something we know is valid. */
7649 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7651 if (GET_MODE (reg_rtx) != mode)
7652 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7654 reload_reg_rtx_for_output[j] = reg_rtx;
7659 && ! rtx_equal_p (rl->in_reg, pseudo)
7660 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7661 && reg_last_reload_reg[REGNO (pseudo)])
7663 int pseudo_no = REGNO (pseudo);
7664 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7666 /* We don't need to test full validity of last_regno for
7667 inherit here; we only want to know if the store actually
7668 matches the pseudo. */
7669 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7670 && reg_reloaded_contents[last_regno] == pseudo_no
7671 && spill_reg_store[last_regno]
7672 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7673 delete_output_reload (insn, j, last_regno, reg_rtx);
7679 || rtx_equal_p (old, reg_rtx))
7682 /* An output operand that dies right away does need a reload,
7683 but need not be copied from it. Show the new location in the
7685 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7686 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7688 XEXP (note, 0) = reg_rtx;
7691 /* Likewise for a SUBREG of an operand that dies. */
7692 else if (GET_CODE (old) == SUBREG
7693 && REG_P (SUBREG_REG (old))
7694 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7697 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
7700 else if (GET_CODE (old) == SCRATCH)
7701 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7702 but we don't want to make an output reload. */
7705 /* If is a JUMP_INSN, we can't support output reloads yet. */
7706 gcc_assert (NONJUMP_INSN_P (insn));
7708 emit_output_reload_insns (chain, rld + j, j);
7711 /* A reload copies values of MODE from register SRC to register DEST.
7712 Return true if it can be treated for inheritance purposes like a
7713 group of reloads, each one reloading a single hard register. The
7714 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7715 occupy the same number of hard registers. */
7718 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
7719 int src ATTRIBUTE_UNUSED,
7720 enum machine_mode mode ATTRIBUTE_UNUSED)
7722 #ifdef CANNOT_CHANGE_MODE_CLASS
7723 return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
7724 && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
7730 /* Output insns to reload values in and out of the chosen reload regs. */
7733 emit_reload_insns (struct insn_chain *chain)
7735 rtx insn = chain->insn;
7739 CLEAR_HARD_REG_SET (reg_reloaded_died);
7741 for (j = 0; j < reload_n_operands; j++)
7742 input_reload_insns[j] = input_address_reload_insns[j]
7743 = inpaddr_address_reload_insns[j]
7744 = output_reload_insns[j] = output_address_reload_insns[j]
7745 = outaddr_address_reload_insns[j]
7746 = other_output_reload_insns[j] = 0;
7747 other_input_address_reload_insns = 0;
7748 other_input_reload_insns = 0;
7749 operand_reload_insns = 0;
7750 other_operand_reload_insns = 0;
7752 /* Dump reloads into the dump file. */
7755 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7756 debug_reload_to_stream (dump_file);
7759 /* Now output the instructions to copy the data into and out of the
7760 reload registers. Do these in the order that the reloads were reported,
7761 since reloads of base and index registers precede reloads of operands
7762 and the operands may need the base and index registers reloaded. */
7764 for (j = 0; j < n_reloads; j++)
7766 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
7770 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
7771 new_spill_reg_store[i] = 0;
7774 do_input_reload (chain, rld + j, j);
7775 do_output_reload (chain, rld + j, j);
7778 /* Now write all the insns we made for reloads in the order expected by
7779 the allocation functions. Prior to the insn being reloaded, we write
7780 the following reloads:
7782 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7784 RELOAD_OTHER reloads.
7786 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7787 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7788 RELOAD_FOR_INPUT reload for the operand.
7790 RELOAD_FOR_OPADDR_ADDRS reloads.
7792 RELOAD_FOR_OPERAND_ADDRESS reloads.
7794 After the insn being reloaded, we write the following:
7796 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7797 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7798 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7799 reloads for the operand. The RELOAD_OTHER output reloads are
7800 output in descending order by reload number. */
7802 emit_insn_before (other_input_address_reload_insns, insn);
7803 emit_insn_before (other_input_reload_insns, insn);
7805 for (j = 0; j < reload_n_operands; j++)
7807 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7808 emit_insn_before (input_address_reload_insns[j], insn);
7809 emit_insn_before (input_reload_insns[j], insn);
7812 emit_insn_before (other_operand_reload_insns, insn);
7813 emit_insn_before (operand_reload_insns, insn);
7815 for (j = 0; j < reload_n_operands; j++)
7817 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7818 x = emit_insn_after (output_address_reload_insns[j], x);
7819 x = emit_insn_after (output_reload_insns[j], x);
7820 emit_insn_after (other_output_reload_insns[j], x);
7823 /* For all the spill regs newly reloaded in this instruction,
7824 record what they were reloaded from, so subsequent instructions
7825 can inherit the reloads.
7827 Update spill_reg_store for the reloads of this insn.
7828 Copy the elements that were updated in the loop above. */
7830 for (j = 0; j < n_reloads; j++)
7832 int r = reload_order[j];
7833 int i = reload_spill_index[r];
7835 /* If this is a non-inherited input reload from a pseudo, we must
7836 clear any memory of a previous store to the same pseudo. Only do
7837 something if there will not be an output reload for the pseudo
7839 if (rld[r].in_reg != 0
7840 && ! (reload_inherited[r] || reload_override_in[r]))
7842 rtx reg = rld[r].in_reg;
7844 if (GET_CODE (reg) == SUBREG)
7845 reg = SUBREG_REG (reg);
7848 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7849 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
7851 int nregno = REGNO (reg);
7853 if (reg_last_reload_reg[nregno])
7855 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7857 if (reg_reloaded_contents[last_regno] == nregno)
7858 spill_reg_store[last_regno] = 0;
7863 /* I is nonneg if this reload used a register.
7864 If rld[r].reg_rtx is 0, this is an optional reload
7865 that we opted to ignore. */
7867 if (i >= 0 && rld[r].reg_rtx != 0)
7869 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7872 /* For a multi register reload, we need to check if all or part
7873 of the value lives to the end. */
7874 for (k = 0; k < nr; k++)
7875 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7876 rld[r].when_needed))
7877 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7879 /* Maybe the spill reg contains a copy of reload_out. */
7881 && (REG_P (rld[r].out)
7885 || REG_P (rld[r].out_reg)))
7888 enum machine_mode mode;
7891 reg = reload_reg_rtx_for_output[r];
7892 mode = GET_MODE (reg);
7893 regno = REGNO (reg);
7894 nregs = hard_regno_nregs[regno][mode];
7895 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
7896 rld[r].when_needed))
7898 rtx out = (REG_P (rld[r].out)
7902 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7903 int out_regno = REGNO (out);
7904 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
7905 : hard_regno_nregs[out_regno][mode]);
7908 spill_reg_store[regno] = new_spill_reg_store[regno];
7909 spill_reg_stored_to[regno] = out;
7910 reg_last_reload_reg[out_regno] = reg;
7912 piecemeal = (HARD_REGISTER_NUM_P (out_regno)
7913 && nregs == out_nregs
7914 && inherit_piecemeal_p (out_regno, regno, mode));
7916 /* If OUT_REGNO is a hard register, it may occupy more than
7917 one register. If it does, say what is in the
7918 rest of the registers assuming that both registers
7919 agree on how many words the object takes. If not,
7920 invalidate the subsequent registers. */
7922 if (HARD_REGISTER_NUM_P (out_regno))
7923 for (k = 1; k < out_nregs; k++)
7924 reg_last_reload_reg[out_regno + k]
7925 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
7927 /* Now do the inverse operation. */
7928 for (k = 0; k < nregs; k++)
7930 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
7931 reg_reloaded_contents[regno + k]
7932 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
7935 reg_reloaded_insn[regno + k] = insn;
7936 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
7937 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
7938 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7941 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7946 /* Maybe the spill reg contains a copy of reload_in. Only do
7947 something if there will not be an output reload for
7948 the register being reloaded. */
7949 else if (rld[r].out_reg == 0
7951 && ((REG_P (rld[r].in)
7952 && !HARD_REGISTER_P (rld[r].in)
7953 && !REGNO_REG_SET_P (®_has_output_reload,
7955 || (REG_P (rld[r].in_reg)
7956 && !REGNO_REG_SET_P (®_has_output_reload,
7957 REGNO (rld[r].in_reg))))
7958 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
7961 enum machine_mode mode;
7964 reg = reload_reg_rtx_for_input[r];
7965 mode = GET_MODE (reg);
7966 regno = REGNO (reg);
7967 nregs = hard_regno_nregs[regno][mode];
7968 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
7969 rld[r].when_needed))
7976 if (REG_P (rld[r].in)
7977 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7979 else if (REG_P (rld[r].in_reg))
7982 in = XEXP (rld[r].in_reg, 0);
7983 in_regno = REGNO (in);
7985 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
7986 : hard_regno_nregs[in_regno][mode]);
7988 reg_last_reload_reg[in_regno] = reg;
7990 piecemeal = (HARD_REGISTER_NUM_P (in_regno)
7991 && nregs == in_nregs
7992 && inherit_piecemeal_p (regno, in_regno, mode));
7994 if (HARD_REGISTER_NUM_P (in_regno))
7995 for (k = 1; k < in_nregs; k++)
7996 reg_last_reload_reg[in_regno + k]
7997 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
7999 /* Unless we inherited this reload, show we haven't
8000 recently done a store.
8001 Previous stores of inherited auto_inc expressions
8002 also have to be discarded. */
8003 if (! reload_inherited[r]
8004 || (rld[r].out && ! rld[r].out_reg))
8005 spill_reg_store[regno] = 0;
8007 for (k = 0; k < nregs; k++)
8009 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8010 reg_reloaded_contents[regno + k]
8011 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
8014 reg_reloaded_insn[regno + k] = insn;
8015 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8016 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8017 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8020 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8027 /* The following if-statement was #if 0'd in 1.34 (or before...).
8028 It's reenabled in 1.35 because supposedly nothing else
8029 deals with this problem. */
8031 /* If a register gets output-reloaded from a non-spill register,
8032 that invalidates any previous reloaded copy of it.
8033 But forget_old_reloads_1 won't get to see it, because
8034 it thinks only about the original insn. So invalidate it here.
8035 Also do the same thing for RELOAD_OTHER constraints where the
8036 output is discarded. */
8038 && ((rld[r].out != 0
8039 && (REG_P (rld[r].out)
8040 || (MEM_P (rld[r].out)
8041 && REG_P (rld[r].out_reg))))
8042 || (rld[r].out == 0 && rld[r].out_reg
8043 && REG_P (rld[r].out_reg))))
8045 rtx out = ((rld[r].out && REG_P (rld[r].out))
8046 ? rld[r].out : rld[r].out_reg);
8047 int out_regno = REGNO (out);
8048 enum machine_mode mode = GET_MODE (out);
8050 /* REG_RTX is now set or clobbered by the main instruction.
8051 As the comment above explains, forget_old_reloads_1 only
8052 sees the original instruction, and there is no guarantee
8053 that the original instruction also clobbered REG_RTX.
8054 For example, if find_reloads sees that the input side of
8055 a matched operand pair dies in this instruction, it may
8056 use the input register as the reload register.
8058 Calling forget_old_reloads_1 is a waste of effort if
8059 REG_RTX is also the output register.
8061 If we know that REG_RTX holds the value of a pseudo
8062 register, the code after the call will record that fact. */
8063 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8064 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8066 if (!HARD_REGISTER_NUM_P (out_regno))
8068 rtx src_reg, store_insn = NULL_RTX;
8070 reg_last_reload_reg[out_regno] = 0;
8072 /* If we can find a hard register that is stored, record
8073 the storing insn so that we may delete this insn with
8074 delete_output_reload. */
8075 src_reg = reload_reg_rtx_for_output[r];
8077 /* If this is an optional reload, try to find the source reg
8078 from an input reload. */
8081 rtx set = single_set (insn);
8082 if (set && SET_DEST (set) == rld[r].out)
8086 src_reg = SET_SRC (set);
8088 for (k = 0; k < n_reloads; k++)
8090 if (rld[k].in == src_reg)
8092 src_reg = reload_reg_rtx_for_input[k];
8099 store_insn = new_spill_reg_store[REGNO (src_reg)];
8100 if (src_reg && REG_P (src_reg)
8101 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8103 int src_regno, src_nregs, k;
8106 gcc_assert (GET_MODE (src_reg) == mode);
8107 src_regno = REGNO (src_reg);
8108 src_nregs = hard_regno_nregs[src_regno][mode];
8109 /* The place where to find a death note varies with
8110 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8111 necessarily checked exactly in the code that moves
8112 notes, so just check both locations. */
8113 note = find_regno_note (insn, REG_DEAD, src_regno);
8114 if (! note && store_insn)
8115 note = find_regno_note (store_insn, REG_DEAD, src_regno);
8116 for (k = 0; k < src_nregs; k++)
8118 spill_reg_store[src_regno + k] = store_insn;
8119 spill_reg_stored_to[src_regno + k] = out;
8120 reg_reloaded_contents[src_regno + k] = out_regno;
8121 reg_reloaded_insn[src_regno + k] = store_insn;
8122 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8123 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8124 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
8126 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8129 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8131 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8133 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8135 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8137 reg_last_reload_reg[out_regno] = src_reg;
8138 /* We have to set reg_has_output_reload here, or else
8139 forget_old_reloads_1 will clear reg_last_reload_reg
8141 SET_REGNO_REG_SET (®_has_output_reload,
8147 int k, out_nregs = hard_regno_nregs[out_regno][mode];
8149 for (k = 0; k < out_nregs; k++)
8150 reg_last_reload_reg[out_regno + k] = 0;
8154 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
8157 /* Go through the motions to emit INSN and test if it is strictly valid.
8158 Return the emitted insn if valid, else return NULL. */
8161 emit_insn_if_valid_for_reload (rtx insn)
8163 rtx last = get_last_insn ();
8166 insn = emit_insn (insn);
8167 code = recog_memoized (insn);
8171 extract_insn (insn);
8172 /* We want constrain operands to treat this insn strictly in its
8173 validity determination, i.e., the way it would after reload has
8175 if (constrain_operands (1))
8179 delete_insns_since (last);
8183 /* Emit code to perform a reload from IN (which may be a reload register) to
8184 OUT (which may also be a reload register). IN or OUT is from operand
8185 OPNUM with reload type TYPE.
8187 Returns first insn emitted. */
8190 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8192 rtx last = get_last_insn ();
8195 /* If IN is a paradoxical SUBREG, remove it and try to put the
8196 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8197 if (GET_CODE (in) == SUBREG
8198 && (GET_MODE_SIZE (GET_MODE (in))
8199 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
8200 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
8201 in = SUBREG_REG (in), out = tem;
8202 else if (GET_CODE (out) == SUBREG
8203 && (GET_MODE_SIZE (GET_MODE (out))
8204 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
8205 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
8206 out = SUBREG_REG (out), in = tem;
8208 /* How to do this reload can get quite tricky. Normally, we are being
8209 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8210 register that didn't get a hard register. In that case we can just
8211 call emit_move_insn.
8213 We can also be asked to reload a PLUS that adds a register or a MEM to
8214 another register, constant or MEM. This can occur during frame pointer
8215 elimination and while reloading addresses. This case is handled by
8216 trying to emit a single insn to perform the add. If it is not valid,
8217 we use a two insn sequence.
8219 Or we can be asked to reload an unary operand that was a fragment of
8220 an addressing mode, into a register. If it isn't recognized as-is,
8221 we try making the unop operand and the reload-register the same:
8222 (set reg:X (unop:X expr:Y))
8223 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8225 Finally, we could be called to handle an 'o' constraint by putting
8226 an address into a register. In that case, we first try to do this
8227 with a named pattern of "reload_load_address". If no such pattern
8228 exists, we just emit a SET insn and hope for the best (it will normally
8229 be valid on machines that use 'o').
8231 This entire process is made complex because reload will never
8232 process the insns we generate here and so we must ensure that
8233 they will fit their constraints and also by the fact that parts of
8234 IN might be being reloaded separately and replaced with spill registers.
8235 Because of this, we are, in some sense, just guessing the right approach
8236 here. The one listed above seems to work.
8238 ??? At some point, this whole thing needs to be rethought. */
8240 if (GET_CODE (in) == PLUS
8241 && (REG_P (XEXP (in, 0))
8242 || GET_CODE (XEXP (in, 0)) == SUBREG
8243 || MEM_P (XEXP (in, 0)))
8244 && (REG_P (XEXP (in, 1))
8245 || GET_CODE (XEXP (in, 1)) == SUBREG
8246 || CONSTANT_P (XEXP (in, 1))
8247 || MEM_P (XEXP (in, 1))))
8249 /* We need to compute the sum of a register or a MEM and another
8250 register, constant, or MEM, and put it into the reload
8251 register. The best possible way of doing this is if the machine
8252 has a three-operand ADD insn that accepts the required operands.
8254 The simplest approach is to try to generate such an insn and see if it
8255 is recognized and matches its constraints. If so, it can be used.
8257 It might be better not to actually emit the insn unless it is valid,
8258 but we need to pass the insn as an operand to `recog' and
8259 `extract_insn' and it is simpler to emit and then delete the insn if
8260 not valid than to dummy things up. */
8262 rtx op0, op1, tem, insn;
8265 op0 = find_replacement (&XEXP (in, 0));
8266 op1 = find_replacement (&XEXP (in, 1));
8268 /* Since constraint checking is strict, commutativity won't be
8269 checked, so we need to do that here to avoid spurious failure
8270 if the add instruction is two-address and the second operand
8271 of the add is the same as the reload reg, which is frequently
8272 the case. If the insn would be A = B + A, rearrange it so
8273 it will be A = A + B as constrain_operands expects. */
8275 if (REG_P (XEXP (in, 1))
8276 && REGNO (out) == REGNO (XEXP (in, 1)))
8277 tem = op0, op0 = op1, op1 = tem;
8279 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8280 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8282 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8286 /* If that failed, we must use a conservative two-insn sequence.
8288 Use a move to copy one operand into the reload register. Prefer
8289 to reload a constant, MEM or pseudo since the move patterns can
8290 handle an arbitrary operand. If OP1 is not a constant, MEM or
8291 pseudo and OP1 is not a valid operand for an add instruction, then
8294 After reloading one of the operands into the reload register, add
8295 the reload register to the output register.
8297 If there is another way to do this for a specific machine, a
8298 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8301 code = (int) optab_handler (add_optab, GET_MODE (out))->insn_code;
8303 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8305 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8306 || (code != CODE_FOR_nothing
8307 && ! ((*insn_data[code].operand[2].predicate)
8308 (op1, insn_data[code].operand[2].mode))))
8309 tem = op0, op0 = op1, op1 = tem;
8311 gen_reload (out, op0, opnum, type);
8313 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8314 This fixes a problem on the 32K where the stack pointer cannot
8315 be used as an operand of an add insn. */
8317 if (rtx_equal_p (op0, op1))
8320 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8323 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8324 set_unique_reg_note (insn, REG_EQUIV, in);
8328 /* If that failed, copy the address register to the reload register.
8329 Then add the constant to the reload register. */
8331 gcc_assert (!reg_overlap_mentioned_p (out, op0));
8332 gen_reload (out, op1, opnum, type);
8333 insn = emit_insn (gen_add2_insn (out, op0));
8334 set_unique_reg_note (insn, REG_EQUIV, in);
8337 #ifdef SECONDARY_MEMORY_NEEDED
8338 /* If we need a memory location to do the move, do it that way. */
8339 else if ((REG_P (in)
8340 || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))))
8341 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
8343 || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out))))
8344 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
8345 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
8346 REGNO_REG_CLASS (reg_or_subregno (out)),
8349 /* Get the memory to use and rewrite both registers to its mode. */
8350 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8352 if (GET_MODE (loc) != GET_MODE (out))
8353 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
8355 if (GET_MODE (loc) != GET_MODE (in))
8356 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
8358 gen_reload (loc, in, opnum, type);
8359 gen_reload (out, loc, opnum, type);
8362 else if (REG_P (out) && UNARY_P (in))
8369 op1 = find_replacement (&XEXP (in, 0));
8370 if (op1 != XEXP (in, 0))
8371 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8373 /* First, try a plain SET. */
8374 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8378 /* If that failed, move the inner operand to the reload
8379 register, and try the same unop with the inner expression
8380 replaced with the reload register. */
8382 if (GET_MODE (op1) != GET_MODE (out))
8383 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8387 gen_reload (out_moded, op1, opnum, type);
8390 = gen_rtx_SET (VOIDmode, out,
8391 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8393 insn = emit_insn_if_valid_for_reload (insn);
8396 set_unique_reg_note (insn, REG_EQUIV, in);
8400 fatal_insn ("Failure trying to reload:", set);
8402 /* If IN is a simple operand, use gen_move_insn. */
8403 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8405 tem = emit_insn (gen_move_insn (out, in));
8406 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8407 mark_jump_label (in, tem, 0);
8410 #ifdef HAVE_reload_load_address
8411 else if (HAVE_reload_load_address)
8412 emit_insn (gen_reload_load_address (out, in));
8415 /* Otherwise, just write (set OUT IN) and hope for the best. */
8417 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8419 /* Return the first insn emitted.
8420 We can not just return get_last_insn, because there may have
8421 been multiple instructions emitted. Also note that gen_move_insn may
8422 emit more than one insn itself, so we can not assume that there is one
8423 insn emitted per emit_insn_before call. */
8425 return last ? NEXT_INSN (last) : get_insns ();
8428 /* Delete a previously made output-reload whose result we now believe
8429 is not needed. First we double-check.
8431 INSN is the insn now being processed.
8432 LAST_RELOAD_REG is the hard register number for which we want to delete
8433 the last output reload.
8434 J is the reload-number that originally used REG. The caller has made
8435 certain that reload J doesn't use REG any longer for input.
8436 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8439 delete_output_reload (rtx insn, int j, int last_reload_reg, rtx new_reload_reg)
8441 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8442 rtx reg = spill_reg_stored_to[last_reload_reg];
8445 int n_inherited = 0;
8449 /* It is possible that this reload has been only used to set another reload
8450 we eliminated earlier and thus deleted this instruction too. */
8451 if (INSN_DELETED_P (output_reload_insn))
8454 /* Get the raw pseudo-register referred to. */
8456 while (GET_CODE (reg) == SUBREG)
8457 reg = SUBREG_REG (reg);
8458 substed = reg_equiv_memory_loc[REGNO (reg)];
8460 /* This is unsafe if the operand occurs more often in the current
8461 insn than it is inherited. */
8462 for (k = n_reloads - 1; k >= 0; k--)
8464 rtx reg2 = rld[k].in;
8467 if (MEM_P (reg2) || reload_override_in[k])
8468 reg2 = rld[k].in_reg;
8470 if (rld[k].out && ! rld[k].out_reg)
8471 reg2 = XEXP (rld[k].in_reg, 0);
8473 while (GET_CODE (reg2) == SUBREG)
8474 reg2 = SUBREG_REG (reg2);
8475 if (rtx_equal_p (reg2, reg))
8477 if (reload_inherited[k] || reload_override_in[k] || k == j)
8483 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8484 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8485 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8488 n_occurrences += count_occurrences (PATTERN (insn),
8489 eliminate_regs (substed, VOIDmode,
8491 for (i1 = reg_equiv_alt_mem_list[REGNO (reg)]; i1; i1 = XEXP (i1, 1))
8493 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8494 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8496 if (n_occurrences > n_inherited)
8499 /* If the pseudo-reg we are reloading is no longer referenced
8500 anywhere between the store into it and here,
8501 and we're within the same basic block, then the value can only
8502 pass through the reload reg and end up here.
8503 Otherwise, give up--return. */
8504 for (i1 = NEXT_INSN (output_reload_insn);
8505 i1 != insn; i1 = NEXT_INSN (i1))
8507 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8509 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8510 && reg_mentioned_p (reg, PATTERN (i1)))
8512 /* If this is USE in front of INSN, we only have to check that
8513 there are no more references than accounted for by inheritance. */
8514 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8516 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8517 i1 = NEXT_INSN (i1);
8519 if (n_occurrences <= n_inherited && i1 == insn)
8525 /* We will be deleting the insn. Remove the spill reg information. */
8526 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8528 spill_reg_store[last_reload_reg + k] = 0;
8529 spill_reg_stored_to[last_reload_reg + k] = 0;
8532 /* The caller has already checked that REG dies or is set in INSN.
8533 It has also checked that we are optimizing, and thus some
8534 inaccuracies in the debugging information are acceptable.
8535 So we could just delete output_reload_insn. But in some cases
8536 we can improve the debugging information without sacrificing
8537 optimization - maybe even improving the code: See if the pseudo
8538 reg has been completely replaced with reload regs. If so, delete
8539 the store insn and forget we had a stack slot for the pseudo. */
8540 if (rld[j].out != rld[j].in
8541 && REG_N_DEATHS (REGNO (reg)) == 1
8542 && REG_N_SETS (REGNO (reg)) == 1
8543 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8544 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8548 /* We know that it was used only between here and the beginning of
8549 the current basic block. (We also know that the last use before
8550 INSN was the output reload we are thinking of deleting, but never
8551 mind that.) Search that range; see if any ref remains. */
8552 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8554 rtx set = single_set (i2);
8556 /* Uses which just store in the pseudo don't count,
8557 since if they are the only uses, they are dead. */
8558 if (set != 0 && SET_DEST (set) == reg)
8563 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8564 && reg_mentioned_p (reg, PATTERN (i2)))
8566 /* Some other ref remains; just delete the output reload we
8568 delete_address_reloads (output_reload_insn, insn);
8569 delete_insn (output_reload_insn);
8574 /* Delete the now-dead stores into this pseudo. Note that this
8575 loop also takes care of deleting output_reload_insn. */
8576 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8578 rtx set = single_set (i2);
8580 if (set != 0 && SET_DEST (set) == reg)
8582 delete_address_reloads (i2, insn);
8590 /* For the debugging info, say the pseudo lives in this reload reg. */
8591 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8592 if (ira_conflicts_p)
8593 /* Inform IRA about the change. */
8594 ira_mark_allocation_change (REGNO (reg));
8595 alter_reg (REGNO (reg), -1, false);
8599 delete_address_reloads (output_reload_insn, insn);
8600 delete_insn (output_reload_insn);
8604 /* We are going to delete DEAD_INSN. Recursively delete loads of
8605 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8606 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8608 delete_address_reloads (rtx dead_insn, rtx current_insn)
8610 rtx set = single_set (dead_insn);
8611 rtx set2, dst, prev, next;
8614 rtx dst = SET_DEST (set);
8616 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8618 /* If we deleted the store from a reloaded post_{in,de}c expression,
8619 we can delete the matching adds. */
8620 prev = PREV_INSN (dead_insn);
8621 next = NEXT_INSN (dead_insn);
8622 if (! prev || ! next)
8624 set = single_set (next);
8625 set2 = single_set (prev);
8627 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8628 || !CONST_INT_P (XEXP (SET_SRC (set), 1))
8629 || !CONST_INT_P (XEXP (SET_SRC (set2), 1)))
8631 dst = SET_DEST (set);
8632 if (! rtx_equal_p (dst, SET_DEST (set2))
8633 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8634 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8635 || (INTVAL (XEXP (SET_SRC (set), 1))
8636 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8638 delete_related_insns (prev);
8639 delete_related_insns (next);
8642 /* Subfunction of delete_address_reloads: process registers found in X. */
8644 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8646 rtx prev, set, dst, i2;
8648 enum rtx_code code = GET_CODE (x);
8652 const char *fmt = GET_RTX_FORMAT (code);
8653 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8656 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8657 else if (fmt[i] == 'E')
8659 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8660 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8667 if (spill_reg_order[REGNO (x)] < 0)
8670 /* Scan backwards for the insn that sets x. This might be a way back due
8672 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8674 code = GET_CODE (prev);
8675 if (code == CODE_LABEL || code == JUMP_INSN)
8679 if (reg_set_p (x, PATTERN (prev)))
8681 if (reg_referenced_p (x, PATTERN (prev)))
8684 if (! prev || INSN_UID (prev) < reload_first_uid)
8686 /* Check that PREV only sets the reload register. */
8687 set = single_set (prev);
8690 dst = SET_DEST (set);
8692 || ! rtx_equal_p (dst, x))
8694 if (! reg_set_p (dst, PATTERN (dead_insn)))
8696 /* Check if DST was used in a later insn -
8697 it might have been inherited. */
8698 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8704 if (reg_referenced_p (dst, PATTERN (i2)))
8706 /* If there is a reference to the register in the current insn,
8707 it might be loaded in a non-inherited reload. If no other
8708 reload uses it, that means the register is set before
8710 if (i2 == current_insn)
8712 for (j = n_reloads - 1; j >= 0; j--)
8713 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8714 || reload_override_in[j] == dst)
8716 for (j = n_reloads - 1; j >= 0; j--)
8717 if (rld[j].in && rld[j].reg_rtx == dst)
8726 /* If DST is still live at CURRENT_INSN, check if it is used for
8727 any reload. Note that even if CURRENT_INSN sets DST, we still
8728 have to check the reloads. */
8729 if (i2 == current_insn)
8731 for (j = n_reloads - 1; j >= 0; j--)
8732 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8733 || reload_override_in[j] == dst)
8735 /* ??? We can't finish the loop here, because dst might be
8736 allocated to a pseudo in this block if no reload in this
8737 block needs any of the classes containing DST - see
8738 spill_hard_reg. There is no easy way to tell this, so we
8739 have to scan till the end of the basic block. */
8741 if (reg_set_p (dst, PATTERN (i2)))
8745 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8746 reg_reloaded_contents[REGNO (dst)] = -1;
8750 /* Output reload-insns to reload VALUE into RELOADREG.
8751 VALUE is an autoincrement or autodecrement RTX whose operand
8752 is a register or memory location;
8753 so reloading involves incrementing that location.
8754 IN is either identical to VALUE, or some cheaper place to reload from.
8756 INC_AMOUNT is the number to increment or decrement by (always positive).
8757 This cannot be deduced from VALUE.
8759 Return the instruction that stores into RELOADREG. */
8762 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8764 /* REG or MEM to be copied and incremented. */
8765 rtx incloc = find_replacement (&XEXP (value, 0));
8766 /* Nonzero if increment after copying. */
8767 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8768 || GET_CODE (value) == POST_MODIFY);
8774 rtx real_in = in == value ? incloc : in;
8776 /* No hard register is equivalent to this register after
8777 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8778 we could inc/dec that register as well (maybe even using it for
8779 the source), but I'm not sure it's worth worrying about. */
8781 reg_last_reload_reg[REGNO (incloc)] = 0;
8783 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8785 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8786 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
8790 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8791 inc_amount = -inc_amount;
8793 inc = GEN_INT (inc_amount);
8796 /* If this is post-increment, first copy the location to the reload reg. */
8797 if (post && real_in != reloadreg)
8798 emit_insn (gen_move_insn (reloadreg, real_in));
8802 /* See if we can directly increment INCLOC. Use a method similar to
8803 that in gen_reload. */
8805 last = get_last_insn ();
8806 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8807 gen_rtx_PLUS (GET_MODE (incloc),
8810 code = recog_memoized (add_insn);
8813 extract_insn (add_insn);
8814 if (constrain_operands (1))
8816 /* If this is a pre-increment and we have incremented the value
8817 where it lives, copy the incremented value to RELOADREG to
8818 be used as an address. */
8821 emit_insn (gen_move_insn (reloadreg, incloc));
8826 delete_insns_since (last);
8829 /* If couldn't do the increment directly, must increment in RELOADREG.
8830 The way we do this depends on whether this is pre- or post-increment.
8831 For pre-increment, copy INCLOC to the reload register, increment it
8832 there, then save back. */
8836 if (in != reloadreg)
8837 emit_insn (gen_move_insn (reloadreg, real_in));
8838 emit_insn (gen_add2_insn (reloadreg, inc));
8839 store = emit_insn (gen_move_insn (incloc, reloadreg));
8844 Because this might be a jump insn or a compare, and because RELOADREG
8845 may not be available after the insn in an input reload, we must do
8846 the incrementation before the insn being reloaded for.
8848 We have already copied IN to RELOADREG. Increment the copy in
8849 RELOADREG, save that back, then decrement RELOADREG so it has
8850 the original value. */
8852 emit_insn (gen_add2_insn (reloadreg, inc));
8853 store = emit_insn (gen_move_insn (incloc, reloadreg));
8854 if (CONST_INT_P (inc))
8855 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
8857 emit_insn (gen_sub2_insn (reloadreg, inc));
8865 add_auto_inc_notes (rtx insn, rtx x)
8867 enum rtx_code code = GET_CODE (x);
8871 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8873 add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
8877 /* Scan all the operand sub-expressions. */
8878 fmt = GET_RTX_FORMAT (code);
8879 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8882 add_auto_inc_notes (insn, XEXP (x, i));
8883 else if (fmt[i] == 'E')
8884 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8885 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8890 /* This is used by reload pass, that does emit some instructions after
8891 abnormal calls moving basic block end, but in fact it wants to emit
8892 them on the edge. Looks for abnormal call edges, find backward the
8893 proper call and fix the damage.
8895 Similar handle instructions throwing exceptions internally. */
8897 fixup_abnormal_edges (void)
8899 bool inserted = false;
8907 /* Look for cases we are interested in - calls or instructions causing
8909 FOR_EACH_EDGE (e, ei, bb->succs)
8911 if (e->flags & EDGE_ABNORMAL_CALL)
8913 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8914 == (EDGE_ABNORMAL | EDGE_EH))
8917 if (e && !CALL_P (BB_END (bb))
8918 && !can_throw_internal (BB_END (bb)))
8922 /* Get past the new insns generated. Allow notes, as the insns
8923 may be already deleted. */
8925 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8926 && !can_throw_internal (insn)
8927 && insn != BB_HEAD (bb))
8928 insn = PREV_INSN (insn);
8930 if (CALL_P (insn) || can_throw_internal (insn))
8934 stop = NEXT_INSN (BB_END (bb));
8936 insn = NEXT_INSN (insn);
8938 FOR_EACH_EDGE (e, ei, bb->succs)
8939 if (e->flags & EDGE_FALLTHRU)
8942 while (insn && insn != stop)
8944 next = NEXT_INSN (insn);
8949 /* Sometimes there's still the return value USE.
8950 If it's placed after a trapping call (i.e. that
8951 call is the last insn anyway), we have no fallthru
8952 edge. Simply delete this use and don't try to insert
8953 on the non-existent edge. */
8954 if (GET_CODE (PATTERN (insn)) != USE)
8956 /* We're not deleting it, we're moving it. */
8957 INSN_DELETED_P (insn) = 0;
8958 PREV_INSN (insn) = NULL_RTX;
8959 NEXT_INSN (insn) = NULL_RTX;
8961 insert_insn_on_edge (insn, e);
8965 else if (!BARRIER_P (insn))
8966 set_block_for_insn (insn, NULL);
8971 /* It may be that we don't find any such trapping insn. In this
8972 case we discovered quite late that the insn that had been
8973 marked as can_throw_internal in fact couldn't trap at all.
8974 So we should in fact delete the EH edges out of the block. */
8976 purge_dead_edges (bb);
8980 /* We've possibly turned single trapping insn into multiple ones. */
8981 if (flag_non_call_exceptions)
8984 blocks = sbitmap_alloc (last_basic_block);
8985 sbitmap_ones (blocks);
8986 find_many_sub_basic_blocks (blocks);
8987 sbitmap_free (blocks);
8991 commit_edge_insertions ();
8993 #ifdef ENABLE_CHECKING
8994 /* Verify that we didn't turn one trapping insn into many, and that
8995 we found and corrected all of the problems wrt fixups on the
8997 verify_flow_info ();
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