1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx *reg_equiv_memory_loc;
105 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
106 collector can keep track of what is inside. */
107 varray_type reg_equiv_memory_loc_varray;
109 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
110 This is used when the address is not valid as a memory address
111 (because its displacement is too big for the machine.) */
112 rtx *reg_equiv_address;
114 /* Element N is the memory slot to which pseudo reg N is equivalent,
115 or zero if pseudo reg N is not equivalent to a memory slot. */
118 /* Widest width in which each pseudo reg is referred to (via subreg). */
119 static unsigned int *reg_max_ref_width;
121 /* Element N is the list of insns that initialized reg N from its equivalent
122 constant or memory slot. */
124 int reg_equiv_init_size;
126 /* Vector to remember old contents of reg_renumber before spilling. */
127 static short *reg_old_renumber;
129 /* During reload_as_needed, element N contains the last pseudo regno reloaded
130 into hard register N. If that pseudo reg occupied more than one register,
131 reg_reloaded_contents points to that pseudo for each spill register in
132 use; all of these must remain set for an inheritance to occur. */
133 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
135 /* During reload_as_needed, element N contains the insn for which
136 hard register N was last used. Its contents are significant only
137 when reg_reloaded_valid is set for this register. */
138 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
140 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
141 static HARD_REG_SET reg_reloaded_valid;
142 /* Indicate if the register was dead at the end of the reload.
143 This is only valid if reg_reloaded_contents is set and valid. */
144 static HARD_REG_SET reg_reloaded_dead;
146 /* Indicate whether the register's current value is one that is not
147 safe to retain across a call, even for registers that are normally
149 static HARD_REG_SET reg_reloaded_call_part_clobbered;
151 /* Number of spill-regs so far; number of valid elements of spill_regs. */
154 /* In parallel with spill_regs, contains REG rtx's for those regs.
155 Holds the last rtx used for any given reg, or 0 if it has never
156 been used for spilling yet. This rtx is reused, provided it has
158 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
160 /* In parallel with spill_regs, contains nonzero for a spill reg
161 that was stored after the last time it was used.
162 The precise value is the insn generated to do the store. */
163 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
165 /* This is the register that was stored with spill_reg_store. This is a
166 copy of reload_out / reload_out_reg when the value was stored; if
167 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
168 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
170 /* This table is the inverse mapping of spill_regs:
171 indexed by hard reg number,
172 it contains the position of that reg in spill_regs,
173 or -1 for something that is not in spill_regs.
175 ?!? This is no longer accurate. */
176 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
178 /* This reg set indicates registers that can't be used as spill registers for
179 the currently processed insn. These are the hard registers which are live
180 during the insn, but not allocated to pseudos, as well as fixed
182 static HARD_REG_SET bad_spill_regs;
184 /* These are the hard registers that can't be used as spill register for any
185 insn. This includes registers used for user variables and registers that
186 we can't eliminate. A register that appears in this set also can't be used
187 to retry register allocation. */
188 static HARD_REG_SET bad_spill_regs_global;
190 /* Describes order of use of registers for reloading
191 of spilled pseudo-registers. `n_spills' is the number of
192 elements that are actually valid; new ones are added at the end.
194 Both spill_regs and spill_reg_order are used on two occasions:
195 once during find_reload_regs, where they keep track of the spill registers
196 for a single insn, but also during reload_as_needed where they show all
197 the registers ever used by reload. For the latter case, the information
198 is calculated during finish_spills. */
199 static short spill_regs[FIRST_PSEUDO_REGISTER];
201 /* This vector of reg sets indicates, for each pseudo, which hard registers
202 may not be used for retrying global allocation because the register was
203 formerly spilled from one of them. If we allowed reallocating a pseudo to
204 a register that it was already allocated to, reload might not
206 static HARD_REG_SET *pseudo_previous_regs;
208 /* This vector of reg sets indicates, for each pseudo, which hard
209 registers may not be used for retrying global allocation because they
210 are used as spill registers during one of the insns in which the
212 static HARD_REG_SET *pseudo_forbidden_regs;
214 /* All hard regs that have been used as spill registers for any insn are
215 marked in this set. */
216 static HARD_REG_SET used_spill_regs;
218 /* Index of last register assigned as a spill register. We allocate in
219 a round-robin fashion. */
220 static int last_spill_reg;
222 /* Nonzero if indirect addressing is supported on the machine; this means
223 that spilling (REG n) does not require reloading it into a register in
224 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
225 value indicates the level of indirect addressing supported, e.g., two
226 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
228 static char spill_indirect_levels;
230 /* Nonzero if indirect addressing is supported when the innermost MEM is
231 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
232 which these are valid is the same as spill_indirect_levels, above. */
233 char indirect_symref_ok;
235 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
236 char double_reg_address_ok;
238 /* Record the stack slot for each spilled hard register. */
239 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
241 /* Width allocated so far for that stack slot. */
242 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
244 /* Record which pseudos needed to be spilled. */
245 static regset_head spilled_pseudos;
247 /* Used for communication between order_regs_for_reload and count_pseudo.
248 Used to avoid counting one pseudo twice. */
249 static regset_head pseudos_counted;
251 /* First uid used by insns created by reload in this function.
252 Used in find_equiv_reg. */
253 int reload_first_uid;
255 /* Flag set by local-alloc or global-alloc if anything is live in
256 a call-clobbered reg across calls. */
257 int caller_save_needed;
259 /* Set to 1 while reload_as_needed is operating.
260 Required by some machines to handle any generated moves differently. */
261 int reload_in_progress = 0;
263 /* These arrays record the insn_code of insns that may be needed to
264 perform input and output reloads of special objects. They provide a
265 place to pass a scratch register. */
266 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
267 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
269 /* This obstack is used for allocation of rtl during register elimination.
270 The allocated storage can be freed once find_reloads has processed the
272 static struct obstack reload_obstack;
274 /* Points to the beginning of the reload_obstack. All insn_chain structures
275 are allocated first. */
276 static char *reload_startobj;
278 /* The point after all insn_chain structures. Used to quickly deallocate
279 memory allocated in copy_reloads during calculate_needs_all_insns. */
280 static char *reload_firstobj;
282 /* This points before all local rtl generated by register elimination.
283 Used to quickly free all memory after processing one insn. */
284 static char *reload_insn_firstobj;
286 /* List of insn_chain instructions, one for every insn that reload needs to
288 struct insn_chain *reload_insn_chain;
290 /* List of all insns needing reloads. */
291 static struct insn_chain *insns_need_reload;
293 /* This structure is used to record information about register eliminations.
294 Each array entry describes one possible way of eliminating a register
295 in favor of another. If there is more than one way of eliminating a
296 particular register, the most preferred should be specified first. */
300 int from; /* Register number to be eliminated. */
301 int to; /* Register number used as replacement. */
302 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
303 int can_eliminate; /* Nonzero if this elimination can be done. */
304 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
305 insns made by reload. */
306 HOST_WIDE_INT offset; /* Current offset between the two regs. */
307 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
308 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
309 rtx from_rtx; /* REG rtx for the register to be eliminated.
310 We cannot simply compare the number since
311 we might then spuriously replace a hard
312 register corresponding to a pseudo
313 assigned to the reg to be eliminated. */
314 rtx to_rtx; /* REG rtx for the replacement. */
317 static struct elim_table *reg_eliminate = 0;
319 /* This is an intermediate structure to initialize the table. It has
320 exactly the members provided by ELIMINABLE_REGS. */
321 static const struct elim_table_1
325 } reg_eliminate_1[] =
327 /* If a set of eliminable registers was specified, define the table from it.
328 Otherwise, default to the normal case of the frame pointer being
329 replaced by the stack pointer. */
331 #ifdef ELIMINABLE_REGS
334 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
337 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
339 /* Record the number of pending eliminations that have an offset not equal
340 to their initial offset. If nonzero, we use a new copy of each
341 replacement result in any insns encountered. */
342 int num_not_at_initial_offset;
344 /* Count the number of registers that we may be able to eliminate. */
345 static int num_eliminable;
346 /* And the number of registers that are equivalent to a constant that
347 can be eliminated to frame_pointer / arg_pointer + constant. */
348 static int num_eliminable_invariants;
350 /* For each label, we record the offset of each elimination. If we reach
351 a label by more than one path and an offset differs, we cannot do the
352 elimination. This information is indexed by the difference of the
353 number of the label and the first label number. We can't offset the
354 pointer itself as this can cause problems on machines with segmented
355 memory. The first table is an array of flags that records whether we
356 have yet encountered a label and the second table is an array of arrays,
357 one entry in the latter array for each elimination. */
359 static int first_label_num;
360 static char *offsets_known_at;
361 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
363 /* Number of labels in the current function. */
365 static int num_labels;
367 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
368 static void maybe_fix_stack_asms (void);
369 static void copy_reloads (struct insn_chain *);
370 static void calculate_needs_all_insns (int);
371 static int find_reg (struct insn_chain *, int);
372 static void find_reload_regs (struct insn_chain *);
373 static void select_reload_regs (void);
374 static void delete_caller_save_insns (void);
376 static void spill_failure (rtx, enum reg_class);
377 static void count_spilled_pseudo (int, int, int);
378 static void delete_dead_insn (rtx);
379 static void alter_reg (int, int);
380 static void set_label_offsets (rtx, rtx, int);
381 static void check_eliminable_occurrences (rtx);
382 static void elimination_effects (rtx, enum machine_mode);
383 static int eliminate_regs_in_insn (rtx, int);
384 static void update_eliminable_offsets (void);
385 static void mark_not_eliminable (rtx, rtx, void *);
386 static void set_initial_elim_offsets (void);
387 static bool verify_initial_elim_offsets (void);
388 static void set_initial_label_offsets (void);
389 static void set_offsets_for_label (rtx);
390 static void init_elim_table (void);
391 static void update_eliminables (HARD_REG_SET *);
392 static void spill_hard_reg (unsigned int, int);
393 static int finish_spills (int);
394 static void scan_paradoxical_subregs (rtx);
395 static void count_pseudo (int);
396 static void order_regs_for_reload (struct insn_chain *);
397 static void reload_as_needed (int);
398 static void forget_old_reloads_1 (rtx, rtx, void *);
399 static int reload_reg_class_lower (const void *, const void *);
400 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
402 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
404 static int reload_reg_free_p (unsigned int, int, enum reload_type);
405 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
407 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
409 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
410 static int allocate_reload_reg (struct insn_chain *, int, int);
411 static int conflicts_with_override (rtx);
412 static void failed_reload (rtx, int);
413 static int set_reload_reg (int, int);
414 static void choose_reload_regs_init (struct insn_chain *, rtx *);
415 static void choose_reload_regs (struct insn_chain *);
416 static void merge_assigned_reloads (rtx);
417 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
419 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
421 static void do_input_reload (struct insn_chain *, struct reload *, int);
422 static void do_output_reload (struct insn_chain *, struct reload *, int);
423 static bool inherit_piecemeal_p (int, int);
424 static void emit_reload_insns (struct insn_chain *);
425 static void delete_output_reload (rtx, int, int);
426 static void delete_address_reloads (rtx, rtx);
427 static void delete_address_reloads_1 (rtx, rtx, rtx);
428 static rtx inc_for_reload (rtx, rtx, rtx, int);
430 static void add_auto_inc_notes (rtx, rtx);
432 static void copy_eh_notes (rtx, rtx);
433 static int reloads_conflict (int, int);
434 static rtx gen_reload (rtx, rtx, int, enum reload_type);
436 /* Initialize the reload pass once per compilation. */
443 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
444 Set spill_indirect_levels to the number of levels such addressing is
445 permitted, zero if it is not permitted at all. */
448 = gen_rtx_MEM (Pmode,
451 LAST_VIRTUAL_REGISTER + 1),
453 spill_indirect_levels = 0;
455 while (memory_address_p (QImode, tem))
457 spill_indirect_levels++;
458 tem = gen_rtx_MEM (Pmode, tem);
461 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
463 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
464 indirect_symref_ok = memory_address_p (QImode, tem);
466 /* See if reg+reg is a valid (and offsettable) address. */
468 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
470 tem = gen_rtx_PLUS (Pmode,
471 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
472 gen_rtx_REG (Pmode, i));
474 /* This way, we make sure that reg+reg is an offsettable address. */
475 tem = plus_constant (tem, 4);
477 if (memory_address_p (QImode, tem))
479 double_reg_address_ok = 1;
484 /* Initialize obstack for our rtl allocation. */
485 gcc_obstack_init (&reload_obstack);
486 reload_startobj = obstack_alloc (&reload_obstack, 0);
488 INIT_REG_SET (&spilled_pseudos);
489 INIT_REG_SET (&pseudos_counted);
490 VARRAY_RTX_INIT (reg_equiv_memory_loc_varray, 0, "reg_equiv_memory_loc");
493 /* List of insn chains that are currently unused. */
494 static struct insn_chain *unused_insn_chains = 0;
496 /* Allocate an empty insn_chain structure. */
498 new_insn_chain (void)
500 struct insn_chain *c;
502 if (unused_insn_chains == 0)
504 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
505 INIT_REG_SET (&c->live_throughout);
506 INIT_REG_SET (&c->dead_or_set);
510 c = unused_insn_chains;
511 unused_insn_chains = c->next;
513 c->is_caller_save_insn = 0;
514 c->need_operand_change = 0;
520 /* Small utility function to set all regs in hard reg set TO which are
521 allocated to pseudos in regset FROM. */
524 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
527 reg_set_iterator rsi;
529 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
531 int r = reg_renumber[regno];
536 /* reload_combine uses the information from
537 BASIC_BLOCK->global_live_at_start, which might still
538 contain registers that have not actually been allocated
539 since they have an equivalence. */
540 gcc_assert (reload_completed);
544 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)];
546 SET_HARD_REG_BIT (*to, r + nregs);
551 /* Replace all pseudos found in LOC with their corresponding
555 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
568 unsigned int regno = REGNO (x);
570 if (regno < FIRST_PSEUDO_REGISTER)
573 x = eliminate_regs (x, mem_mode, usage);
577 replace_pseudos_in (loc, mem_mode, usage);
581 if (reg_equiv_constant[regno])
582 *loc = reg_equiv_constant[regno];
583 else if (reg_equiv_mem[regno])
584 *loc = reg_equiv_mem[regno];
585 else if (reg_equiv_address[regno])
586 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
589 gcc_assert (!REG_P (regno_reg_rtx[regno])
590 || REGNO (regno_reg_rtx[regno]) != regno);
591 *loc = regno_reg_rtx[regno];
596 else if (code == MEM)
598 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
602 /* Process each of our operands recursively. */
603 fmt = GET_RTX_FORMAT (code);
604 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
606 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
607 else if (*fmt == 'E')
608 for (j = 0; j < XVECLEN (x, i); j++)
609 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
613 /* Global variables used by reload and its subroutines. */
615 /* Set during calculate_needs if an insn needs register elimination. */
616 static int something_needs_elimination;
617 /* Set during calculate_needs if an insn needs an operand changed. */
618 static int something_needs_operands_changed;
620 /* Nonzero means we couldn't get enough spill regs. */
623 /* Main entry point for the reload pass.
625 FIRST is the first insn of the function being compiled.
627 GLOBAL nonzero means we were called from global_alloc
628 and should attempt to reallocate any pseudoregs that we
629 displace from hard regs we will use for reloads.
630 If GLOBAL is zero, we do not have enough information to do that,
631 so any pseudo reg that is spilled must go to the stack.
633 Return value is nonzero if reload failed
634 and we must not do any more for this function. */
637 reload (rtx first, int global)
641 struct elim_table *ep;
644 /* Make sure even insns with volatile mem refs are recognizable. */
649 reload_firstobj = obstack_alloc (&reload_obstack, 0);
651 /* Make sure that the last insn in the chain
652 is not something that needs reloading. */
653 emit_note (NOTE_INSN_DELETED);
655 /* Enable find_equiv_reg to distinguish insns made by reload. */
656 reload_first_uid = get_max_uid ();
658 #ifdef SECONDARY_MEMORY_NEEDED
659 /* Initialize the secondary memory table. */
660 clear_secondary_mem ();
663 /* We don't have a stack slot for any spill reg yet. */
664 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
665 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
667 /* Initialize the save area information for caller-save, in case some
671 /* Compute which hard registers are now in use
672 as homes for pseudo registers.
673 This is done here rather than (eg) in global_alloc
674 because this point is reached even if not optimizing. */
675 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
678 /* A function that receives a nonlocal goto must save all call-saved
680 if (current_function_has_nonlocal_label)
681 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
682 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
683 regs_ever_live[i] = 1;
685 /* Find all the pseudo registers that didn't get hard regs
686 but do have known equivalent constants or memory slots.
687 These include parameters (known equivalent to parameter slots)
688 and cse'd or loop-moved constant memory addresses.
690 Record constant equivalents in reg_equiv_constant
691 so they will be substituted by find_reloads.
692 Record memory equivalents in reg_mem_equiv so they can
693 be substituted eventually by altering the REG-rtx's. */
695 reg_equiv_constant = xcalloc (max_regno, sizeof (rtx));
696 reg_equiv_mem = xcalloc (max_regno, sizeof (rtx));
697 reg_equiv_address = xcalloc (max_regno, sizeof (rtx));
698 reg_max_ref_width = xcalloc (max_regno, sizeof (int));
699 reg_old_renumber = xcalloc (max_regno, sizeof (short));
700 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
701 pseudo_forbidden_regs = xmalloc (max_regno * sizeof (HARD_REG_SET));
702 pseudo_previous_regs = xcalloc (max_regno, sizeof (HARD_REG_SET));
704 CLEAR_HARD_REG_SET (bad_spill_regs_global);
706 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
707 to. Also find all paradoxical subregs and find largest such for
710 num_eliminable_invariants = 0;
711 for (insn = first; insn; insn = NEXT_INSN (insn))
713 rtx set = single_set (insn);
715 /* We may introduce USEs that we want to remove at the end, so
716 we'll mark them with QImode. Make sure there are no
717 previously-marked insns left by say regmove. */
718 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
719 && GET_MODE (insn) != VOIDmode)
720 PUT_MODE (insn, VOIDmode);
723 scan_paradoxical_subregs (PATTERN (insn));
725 if (set != 0 && REG_P (SET_DEST (set)))
727 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
733 i = REGNO (SET_DEST (set));
736 if (i <= LAST_VIRTUAL_REGISTER)
739 if (! function_invariant_p (x)
741 /* A function invariant is often CONSTANT_P but may
742 include a register. We promise to only pass
743 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
745 && LEGITIMATE_PIC_OPERAND_P (x)))
747 /* It can happen that a REG_EQUIV note contains a MEM
748 that is not a legitimate memory operand. As later
749 stages of reload assume that all addresses found
750 in the reg_equiv_* arrays were originally legitimate,
751 we ignore such REG_EQUIV notes. */
752 if (memory_operand (x, VOIDmode))
754 /* Always unshare the equivalence, so we can
755 substitute into this insn without touching the
757 reg_equiv_memory_loc[i] = copy_rtx (x);
759 else if (function_invariant_p (x))
761 if (GET_CODE (x) == PLUS)
763 /* This is PLUS of frame pointer and a constant,
764 and might be shared. Unshare it. */
765 reg_equiv_constant[i] = copy_rtx (x);
766 num_eliminable_invariants++;
768 else if (x == frame_pointer_rtx
769 || x == arg_pointer_rtx)
771 reg_equiv_constant[i] = x;
772 num_eliminable_invariants++;
774 else if (LEGITIMATE_CONSTANT_P (x))
775 reg_equiv_constant[i] = x;
778 reg_equiv_memory_loc[i]
779 = force_const_mem (GET_MODE (SET_DEST (set)), x);
780 if (! reg_equiv_memory_loc[i])
781 reg_equiv_init[i] = NULL_RTX;
786 reg_equiv_init[i] = NULL_RTX;
791 reg_equiv_init[i] = NULL_RTX;
796 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
797 if (reg_equiv_init[i])
799 fprintf (dump_file, "init_insns for %u: ", i);
800 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
801 fprintf (dump_file, "\n");
806 first_label_num = get_first_label_num ();
807 num_labels = max_label_num () - first_label_num;
809 /* Allocate the tables used to store offset information at labels. */
810 /* We used to use alloca here, but the size of what it would try to
811 allocate would occasionally cause it to exceed the stack limit and
812 cause a core dump. */
813 offsets_known_at = xmalloc (num_labels);
814 offsets_at = xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
816 /* Alter each pseudo-reg rtx to contain its hard reg number.
817 Assign stack slots to the pseudos that lack hard regs or equivalents.
818 Do not touch virtual registers. */
820 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
823 /* If we have some registers we think can be eliminated, scan all insns to
824 see if there is an insn that sets one of these registers to something
825 other than itself plus a constant. If so, the register cannot be
826 eliminated. Doing this scan here eliminates an extra pass through the
827 main reload loop in the most common case where register elimination
829 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
831 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
833 maybe_fix_stack_asms ();
835 insns_need_reload = 0;
836 something_needs_elimination = 0;
838 /* Initialize to -1, which means take the first spill register. */
841 /* Spill any hard regs that we know we can't eliminate. */
842 CLEAR_HARD_REG_SET (used_spill_regs);
843 /* There can be multiple ways to eliminate a register;
844 they should be listed adjacently.
845 Elimination for any register fails only if all possible ways fail. */
846 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
849 int can_eliminate = 0;
852 can_eliminate |= ep->can_eliminate;
855 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
857 spill_hard_reg (from, 1);
860 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
861 if (frame_pointer_needed)
862 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
864 finish_spills (global);
866 /* From now on, we may need to generate moves differently. We may also
867 allow modifications of insns which cause them to not be recognized.
868 Any such modifications will be cleaned up during reload itself. */
869 reload_in_progress = 1;
871 /* This loop scans the entire function each go-round
872 and repeats until one repetition spills no additional hard regs. */
875 int something_changed;
878 HOST_WIDE_INT starting_frame_size;
880 /* Round size of stack frame to stack_alignment_needed. This must be done
881 here because the stack size may be a part of the offset computation
882 for register elimination, and there might have been new stack slots
883 created in the last iteration of this loop. */
884 if (cfun->stack_alignment_needed)
885 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
887 starting_frame_size = get_frame_size ();
889 set_initial_elim_offsets ();
890 set_initial_label_offsets ();
892 /* For each pseudo register that has an equivalent location defined,
893 try to eliminate any eliminable registers (such as the frame pointer)
894 assuming initial offsets for the replacement register, which
897 If the resulting location is directly addressable, substitute
898 the MEM we just got directly for the old REG.
900 If it is not addressable but is a constant or the sum of a hard reg
901 and constant, it is probably not addressable because the constant is
902 out of range, in that case record the address; we will generate
903 hairy code to compute the address in a register each time it is
904 needed. Similarly if it is a hard register, but one that is not
905 valid as an address register.
907 If the location is not addressable, but does not have one of the
908 above forms, assign a stack slot. We have to do this to avoid the
909 potential of producing lots of reloads if, e.g., a location involves
910 a pseudo that didn't get a hard register and has an equivalent memory
911 location that also involves a pseudo that didn't get a hard register.
913 Perhaps at some point we will improve reload_when_needed handling
914 so this problem goes away. But that's very hairy. */
916 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
917 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
919 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
921 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
923 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
924 else if (CONSTANT_P (XEXP (x, 0))
925 || (REG_P (XEXP (x, 0))
926 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
927 || (GET_CODE (XEXP (x, 0)) == PLUS
928 && REG_P (XEXP (XEXP (x, 0), 0))
929 && (REGNO (XEXP (XEXP (x, 0), 0))
930 < FIRST_PSEUDO_REGISTER)
931 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
932 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
935 /* Make a new stack slot. Then indicate that something
936 changed so we go back and recompute offsets for
937 eliminable registers because the allocation of memory
938 below might change some offset. reg_equiv_{mem,address}
939 will be set up for this pseudo on the next pass around
941 reg_equiv_memory_loc[i] = 0;
942 reg_equiv_init[i] = 0;
947 if (caller_save_needed)
950 /* If we allocated another stack slot, redo elimination bookkeeping. */
951 if (starting_frame_size != get_frame_size ())
954 if (caller_save_needed)
956 save_call_clobbered_regs ();
957 /* That might have allocated new insn_chain structures. */
958 reload_firstobj = obstack_alloc (&reload_obstack, 0);
961 calculate_needs_all_insns (global);
963 CLEAR_REG_SET (&spilled_pseudos);
966 something_changed = 0;
968 /* If we allocated any new memory locations, make another pass
969 since it might have changed elimination offsets. */
970 if (starting_frame_size != get_frame_size ())
971 something_changed = 1;
973 /* Even if the frame size remained the same, we might still have
974 changed elimination offsets, e.g. if find_reloads called
975 force_const_mem requiring the back end to allocate a constant
976 pool base register that needs to be saved on the stack. */
977 else if (!verify_initial_elim_offsets ())
978 something_changed = 1;
981 HARD_REG_SET to_spill;
982 CLEAR_HARD_REG_SET (to_spill);
983 update_eliminables (&to_spill);
984 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
985 if (TEST_HARD_REG_BIT (to_spill, i))
987 spill_hard_reg (i, 1);
990 /* Regardless of the state of spills, if we previously had
991 a register that we thought we could eliminate, but now can
992 not eliminate, we must run another pass.
994 Consider pseudos which have an entry in reg_equiv_* which
995 reference an eliminable register. We must make another pass
996 to update reg_equiv_* so that we do not substitute in the
997 old value from when we thought the elimination could be
999 something_changed = 1;
1003 select_reload_regs ();
1007 if (insns_need_reload != 0 || did_spill)
1008 something_changed |= finish_spills (global);
1010 if (! something_changed)
1013 if (caller_save_needed)
1014 delete_caller_save_insns ();
1016 obstack_free (&reload_obstack, reload_firstobj);
1019 /* If global-alloc was run, notify it of any register eliminations we have
1022 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1023 if (ep->can_eliminate)
1024 mark_elimination (ep->from, ep->to);
1026 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1027 If that insn didn't set the register (i.e., it copied the register to
1028 memory), just delete that insn instead of the equivalencing insn plus
1029 anything now dead. If we call delete_dead_insn on that insn, we may
1030 delete the insn that actually sets the register if the register dies
1031 there and that is incorrect. */
1033 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1035 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1038 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1040 rtx equiv_insn = XEXP (list, 0);
1042 /* If we already deleted the insn or if it may trap, we can't
1043 delete it. The latter case shouldn't happen, but can
1044 if an insn has a variable address, gets a REG_EH_REGION
1045 note added to it, and then gets converted into a load
1046 from a constant address. */
1047 if (NOTE_P (equiv_insn)
1048 || can_throw_internal (equiv_insn))
1050 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1051 delete_dead_insn (equiv_insn);
1053 SET_INSN_DELETED (equiv_insn);
1058 /* Use the reload registers where necessary
1059 by generating move instructions to move the must-be-register
1060 values into or out of the reload registers. */
1062 if (insns_need_reload != 0 || something_needs_elimination
1063 || something_needs_operands_changed)
1065 HOST_WIDE_INT old_frame_size = get_frame_size ();
1067 reload_as_needed (global);
1069 gcc_assert (old_frame_size == get_frame_size ());
1071 gcc_assert (verify_initial_elim_offsets ());
1074 /* If we were able to eliminate the frame pointer, show that it is no
1075 longer live at the start of any basic block. If it ls live by
1076 virtue of being in a pseudo, that pseudo will be marked live
1077 and hence the frame pointer will be known to be live via that
1080 if (! frame_pointer_needed)
1082 CLEAR_REGNO_REG_SET (bb->il.rtl->global_live_at_start,
1083 HARD_FRAME_POINTER_REGNUM);
1085 /* Come here (with failure set nonzero) if we can't get enough spill
1089 CLEAR_REG_SET (&spilled_pseudos);
1090 reload_in_progress = 0;
1092 /* Now eliminate all pseudo regs by modifying them into
1093 their equivalent memory references.
1094 The REG-rtx's for the pseudos are modified in place,
1095 so all insns that used to refer to them now refer to memory.
1097 For a reg that has a reg_equiv_address, all those insns
1098 were changed by reloading so that no insns refer to it any longer;
1099 but the DECL_RTL of a variable decl may refer to it,
1100 and if so this causes the debugging info to mention the variable. */
1102 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1106 if (reg_equiv_mem[i])
1107 addr = XEXP (reg_equiv_mem[i], 0);
1109 if (reg_equiv_address[i])
1110 addr = reg_equiv_address[i];
1114 if (reg_renumber[i] < 0)
1116 rtx reg = regno_reg_rtx[i];
1118 REG_USERVAR_P (reg) = 0;
1119 PUT_CODE (reg, MEM);
1120 XEXP (reg, 0) = addr;
1121 if (reg_equiv_memory_loc[i])
1122 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1125 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1126 MEM_ATTRS (reg) = 0;
1129 else if (reg_equiv_mem[i])
1130 XEXP (reg_equiv_mem[i], 0) = addr;
1134 /* We must set reload_completed now since the cleanup_subreg_operands call
1135 below will re-recognize each insn and reload may have generated insns
1136 which are only valid during and after reload. */
1137 reload_completed = 1;
1139 /* Make a pass over all the insns and delete all USEs which we inserted
1140 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1141 notes. Delete all CLOBBER insns, except those that refer to the return
1142 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1143 from misarranging variable-array code, and simplify (subreg (reg))
1144 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1145 are no longer useful or accurate. Strip and regenerate REG_INC notes
1146 that may have been moved around. */
1148 for (insn = first; insn; insn = NEXT_INSN (insn))
1154 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1155 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1157 if ((GET_CODE (PATTERN (insn)) == USE
1158 /* We mark with QImode USEs introduced by reload itself. */
1159 && (GET_MODE (insn) == QImode
1160 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1161 || (GET_CODE (PATTERN (insn)) == CLOBBER
1162 && (!MEM_P (XEXP (PATTERN (insn), 0))
1163 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1164 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1165 && XEXP (XEXP (PATTERN (insn), 0), 0)
1166 != stack_pointer_rtx))
1167 && (!REG_P (XEXP (PATTERN (insn), 0))
1168 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1174 /* Some CLOBBERs may survive until here and still reference unassigned
1175 pseudos with const equivalent, which may in turn cause ICE in later
1176 passes if the reference remains in place. */
1177 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1178 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1179 VOIDmode, PATTERN (insn));
1181 /* Discard obvious no-ops, even without -O. This optimization
1182 is fast and doesn't interfere with debugging. */
1183 if (NONJUMP_INSN_P (insn)
1184 && GET_CODE (PATTERN (insn)) == SET
1185 && REG_P (SET_SRC (PATTERN (insn)))
1186 && REG_P (SET_DEST (PATTERN (insn)))
1187 && (REGNO (SET_SRC (PATTERN (insn)))
1188 == REGNO (SET_DEST (PATTERN (insn)))))
1194 pnote = ®_NOTES (insn);
1197 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1198 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1199 || REG_NOTE_KIND (*pnote) == REG_INC
1200 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1201 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1202 *pnote = XEXP (*pnote, 1);
1204 pnote = &XEXP (*pnote, 1);
1208 add_auto_inc_notes (insn, PATTERN (insn));
1211 /* And simplify (subreg (reg)) if it appears as an operand. */
1212 cleanup_subreg_operands (insn);
1215 /* If we are doing stack checking, give a warning if this function's
1216 frame size is larger than we expect. */
1217 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1219 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1220 static int verbose_warned = 0;
1222 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1223 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1224 size += UNITS_PER_WORD;
1226 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1228 warning (0, "frame size too large for reliable stack checking");
1229 if (! verbose_warned)
1231 warning (0, "try reducing the number of local variables");
1237 /* Indicate that we no longer have known memory locations or constants. */
1238 if (reg_equiv_constant)
1239 free (reg_equiv_constant);
1240 reg_equiv_constant = 0;
1241 VARRAY_GROW (reg_equiv_memory_loc_varray, 0);
1242 reg_equiv_memory_loc = 0;
1244 if (offsets_known_at)
1245 free (offsets_known_at);
1249 free (reg_equiv_mem);
1251 free (reg_equiv_address);
1252 free (reg_max_ref_width);
1253 free (reg_old_renumber);
1254 free (pseudo_previous_regs);
1255 free (pseudo_forbidden_regs);
1257 CLEAR_HARD_REG_SET (used_spill_regs);
1258 for (i = 0; i < n_spills; i++)
1259 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1261 /* Free all the insn_chain structures at once. */
1262 obstack_free (&reload_obstack, reload_startobj);
1263 unused_insn_chains = 0;
1264 fixup_abnormal_edges ();
1266 /* Replacing pseudos with their memory equivalents might have
1267 created shared rtx. Subsequent passes would get confused
1268 by this, so unshare everything here. */
1269 unshare_all_rtl_again (first);
1271 #ifdef STACK_BOUNDARY
1272 /* init_emit has set the alignment of the hard frame pointer
1273 to STACK_BOUNDARY. It is very likely no longer valid if
1274 the hard frame pointer was used for register allocation. */
1275 if (!frame_pointer_needed)
1276 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1282 /* Yet another special case. Unfortunately, reg-stack forces people to
1283 write incorrect clobbers in asm statements. These clobbers must not
1284 cause the register to appear in bad_spill_regs, otherwise we'll call
1285 fatal_insn later. We clear the corresponding regnos in the live
1286 register sets to avoid this.
1287 The whole thing is rather sick, I'm afraid. */
1290 maybe_fix_stack_asms (void)
1293 const char *constraints[MAX_RECOG_OPERANDS];
1294 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1295 struct insn_chain *chain;
1297 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1300 HARD_REG_SET clobbered, allowed;
1303 if (! INSN_P (chain->insn)
1304 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1306 pat = PATTERN (chain->insn);
1307 if (GET_CODE (pat) != PARALLEL)
1310 CLEAR_HARD_REG_SET (clobbered);
1311 CLEAR_HARD_REG_SET (allowed);
1313 /* First, make a mask of all stack regs that are clobbered. */
1314 for (i = 0; i < XVECLEN (pat, 0); i++)
1316 rtx t = XVECEXP (pat, 0, i);
1317 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1318 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1321 /* Get the operand values and constraints out of the insn. */
1322 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1323 constraints, operand_mode);
1325 /* For every operand, see what registers are allowed. */
1326 for (i = 0; i < noperands; i++)
1328 const char *p = constraints[i];
1329 /* For every alternative, we compute the class of registers allowed
1330 for reloading in CLS, and merge its contents into the reg set
1332 int cls = (int) NO_REGS;
1338 if (c == '\0' || c == ',' || c == '#')
1340 /* End of one alternative - mark the regs in the current
1341 class, and reset the class. */
1342 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1348 } while (c != '\0' && c != ',');
1356 case '=': case '+': case '*': case '%': case '?': case '!':
1357 case '0': case '1': case '2': case '3': case '4': case 'm':
1358 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1359 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1360 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1365 cls = (int) reg_class_subunion[cls]
1366 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1371 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1375 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1376 cls = (int) reg_class_subunion[cls]
1377 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1379 cls = (int) reg_class_subunion[cls]
1380 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1382 p += CONSTRAINT_LEN (c, p);
1385 /* Those of the registers which are clobbered, but allowed by the
1386 constraints, must be usable as reload registers. So clear them
1387 out of the life information. */
1388 AND_HARD_REG_SET (allowed, clobbered);
1389 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1390 if (TEST_HARD_REG_BIT (allowed, i))
1392 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1393 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1400 /* Copy the global variables n_reloads and rld into the corresponding elts
1403 copy_reloads (struct insn_chain *chain)
1405 chain->n_reloads = n_reloads;
1406 chain->rld = obstack_alloc (&reload_obstack,
1407 n_reloads * sizeof (struct reload));
1408 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1409 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1412 /* Walk the chain of insns, and determine for each whether it needs reloads
1413 and/or eliminations. Build the corresponding insns_need_reload list, and
1414 set something_needs_elimination as appropriate. */
1416 calculate_needs_all_insns (int global)
1418 struct insn_chain **pprev_reload = &insns_need_reload;
1419 struct insn_chain *chain, *next = 0;
1421 something_needs_elimination = 0;
1423 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1424 for (chain = reload_insn_chain; chain != 0; chain = next)
1426 rtx insn = chain->insn;
1430 /* Clear out the shortcuts. */
1431 chain->n_reloads = 0;
1432 chain->need_elim = 0;
1433 chain->need_reload = 0;
1434 chain->need_operand_change = 0;
1436 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1437 include REG_LABEL), we need to see what effects this has on the
1438 known offsets at labels. */
1440 if (LABEL_P (insn) || JUMP_P (insn)
1441 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1442 set_label_offsets (insn, insn, 0);
1446 rtx old_body = PATTERN (insn);
1447 int old_code = INSN_CODE (insn);
1448 rtx old_notes = REG_NOTES (insn);
1449 int did_elimination = 0;
1450 int operands_changed = 0;
1451 rtx set = single_set (insn);
1453 /* Skip insns that only set an equivalence. */
1454 if (set && REG_P (SET_DEST (set))
1455 && reg_renumber[REGNO (SET_DEST (set))] < 0
1456 && reg_equiv_constant[REGNO (SET_DEST (set))])
1459 /* If needed, eliminate any eliminable registers. */
1460 if (num_eliminable || num_eliminable_invariants)
1461 did_elimination = eliminate_regs_in_insn (insn, 0);
1463 /* Analyze the instruction. */
1464 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1465 global, spill_reg_order);
1467 /* If a no-op set needs more than one reload, this is likely
1468 to be something that needs input address reloads. We
1469 can't get rid of this cleanly later, and it is of no use
1470 anyway, so discard it now.
1471 We only do this when expensive_optimizations is enabled,
1472 since this complements reload inheritance / output
1473 reload deletion, and it can make debugging harder. */
1474 if (flag_expensive_optimizations && n_reloads > 1)
1476 rtx set = single_set (insn);
1478 && SET_SRC (set) == SET_DEST (set)
1479 && REG_P (SET_SRC (set))
1480 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1483 /* Delete it from the reload chain. */
1485 chain->prev->next = next;
1487 reload_insn_chain = next;
1489 next->prev = chain->prev;
1490 chain->next = unused_insn_chains;
1491 unused_insn_chains = chain;
1496 update_eliminable_offsets ();
1498 /* Remember for later shortcuts which insns had any reloads or
1499 register eliminations. */
1500 chain->need_elim = did_elimination;
1501 chain->need_reload = n_reloads > 0;
1502 chain->need_operand_change = operands_changed;
1504 /* Discard any register replacements done. */
1505 if (did_elimination)
1507 obstack_free (&reload_obstack, reload_insn_firstobj);
1508 PATTERN (insn) = old_body;
1509 INSN_CODE (insn) = old_code;
1510 REG_NOTES (insn) = old_notes;
1511 something_needs_elimination = 1;
1514 something_needs_operands_changed |= operands_changed;
1518 copy_reloads (chain);
1519 *pprev_reload = chain;
1520 pprev_reload = &chain->next_need_reload;
1527 /* Comparison function for qsort to decide which of two reloads
1528 should be handled first. *P1 and *P2 are the reload numbers. */
1531 reload_reg_class_lower (const void *r1p, const void *r2p)
1533 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1536 /* Consider required reloads before optional ones. */
1537 t = rld[r1].optional - rld[r2].optional;
1541 /* Count all solitary classes before non-solitary ones. */
1542 t = ((reg_class_size[(int) rld[r2].class] == 1)
1543 - (reg_class_size[(int) rld[r1].class] == 1));
1547 /* Aside from solitaires, consider all multi-reg groups first. */
1548 t = rld[r2].nregs - rld[r1].nregs;
1552 /* Consider reloads in order of increasing reg-class number. */
1553 t = (int) rld[r1].class - (int) rld[r2].class;
1557 /* If reloads are equally urgent, sort by reload number,
1558 so that the results of qsort leave nothing to chance. */
1562 /* The cost of spilling each hard reg. */
1563 static int spill_cost[FIRST_PSEUDO_REGISTER];
1565 /* When spilling multiple hard registers, we use SPILL_COST for the first
1566 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1567 only the first hard reg for a multi-reg pseudo. */
1568 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1570 /* Update the spill cost arrays, considering that pseudo REG is live. */
1573 count_pseudo (int reg)
1575 int freq = REG_FREQ (reg);
1576 int r = reg_renumber[reg];
1579 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1580 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1583 SET_REGNO_REG_SET (&pseudos_counted, reg);
1585 gcc_assert (r >= 0);
1587 spill_add_cost[r] += freq;
1589 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1591 spill_cost[r + nregs] += freq;
1594 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1595 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1598 order_regs_for_reload (struct insn_chain *chain)
1601 HARD_REG_SET used_by_pseudos;
1602 HARD_REG_SET used_by_pseudos2;
1603 reg_set_iterator rsi;
1605 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1607 memset (spill_cost, 0, sizeof spill_cost);
1608 memset (spill_add_cost, 0, sizeof spill_add_cost);
1610 /* Count number of uses of each hard reg by pseudo regs allocated to it
1611 and then order them by decreasing use. First exclude hard registers
1612 that are live in or across this insn. */
1614 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1615 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1616 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1617 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1619 /* Now find out which pseudos are allocated to it, and update
1621 CLEAR_REG_SET (&pseudos_counted);
1623 EXECUTE_IF_SET_IN_REG_SET
1624 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1628 EXECUTE_IF_SET_IN_REG_SET
1629 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1633 CLEAR_REG_SET (&pseudos_counted);
1636 /* Vector of reload-numbers showing the order in which the reloads should
1638 static short reload_order[MAX_RELOADS];
1640 /* This is used to keep track of the spill regs used in one insn. */
1641 static HARD_REG_SET used_spill_regs_local;
1643 /* We decided to spill hard register SPILLED, which has a size of
1644 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1645 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1646 update SPILL_COST/SPILL_ADD_COST. */
1649 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1651 int r = reg_renumber[reg];
1652 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1654 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1655 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1658 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1660 spill_add_cost[r] -= REG_FREQ (reg);
1662 spill_cost[r + nregs] -= REG_FREQ (reg);
1665 /* Find reload register to use for reload number ORDER. */
1668 find_reg (struct insn_chain *chain, int order)
1670 int rnum = reload_order[order];
1671 struct reload *rl = rld + rnum;
1672 int best_cost = INT_MAX;
1676 HARD_REG_SET not_usable;
1677 HARD_REG_SET used_by_other_reload;
1678 reg_set_iterator rsi;
1680 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1681 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1682 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1684 CLEAR_HARD_REG_SET (used_by_other_reload);
1685 for (k = 0; k < order; k++)
1687 int other = reload_order[k];
1689 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1690 for (j = 0; j < rld[other].nregs; j++)
1691 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1694 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1696 unsigned int regno = i;
1698 if (! TEST_HARD_REG_BIT (not_usable, regno)
1699 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1700 && HARD_REGNO_MODE_OK (regno, rl->mode))
1702 int this_cost = spill_cost[regno];
1704 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1706 for (j = 1; j < this_nregs; j++)
1708 this_cost += spill_add_cost[regno + j];
1709 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1710 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1715 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1717 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1719 if (this_cost < best_cost
1720 /* Among registers with equal cost, prefer caller-saved ones, or
1721 use REG_ALLOC_ORDER if it is defined. */
1722 || (this_cost == best_cost
1723 #ifdef REG_ALLOC_ORDER
1724 && (inv_reg_alloc_order[regno]
1725 < inv_reg_alloc_order[best_reg])
1727 && call_used_regs[regno]
1728 && ! call_used_regs[best_reg]
1733 best_cost = this_cost;
1741 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1743 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1744 rl->regno = best_reg;
1746 EXECUTE_IF_SET_IN_REG_SET
1747 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1749 count_spilled_pseudo (best_reg, rl->nregs, j);
1752 EXECUTE_IF_SET_IN_REG_SET
1753 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1755 count_spilled_pseudo (best_reg, rl->nregs, j);
1758 for (i = 0; i < rl->nregs; i++)
1760 gcc_assert (spill_cost[best_reg + i] == 0);
1761 gcc_assert (spill_add_cost[best_reg + i] == 0);
1762 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1767 /* Find more reload regs to satisfy the remaining need of an insn, which
1769 Do it by ascending class number, since otherwise a reg
1770 might be spilled for a big class and might fail to count
1771 for a smaller class even though it belongs to that class. */
1774 find_reload_regs (struct insn_chain *chain)
1778 /* In order to be certain of getting the registers we need,
1779 we must sort the reloads into order of increasing register class.
1780 Then our grabbing of reload registers will parallel the process
1781 that provided the reload registers. */
1782 for (i = 0; i < chain->n_reloads; i++)
1784 /* Show whether this reload already has a hard reg. */
1785 if (chain->rld[i].reg_rtx)
1787 int regno = REGNO (chain->rld[i].reg_rtx);
1788 chain->rld[i].regno = regno;
1790 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1793 chain->rld[i].regno = -1;
1794 reload_order[i] = i;
1797 n_reloads = chain->n_reloads;
1798 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1800 CLEAR_HARD_REG_SET (used_spill_regs_local);
1803 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1805 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1807 /* Compute the order of preference for hard registers to spill. */
1809 order_regs_for_reload (chain);
1811 for (i = 0; i < n_reloads; i++)
1813 int r = reload_order[i];
1815 /* Ignore reloads that got marked inoperative. */
1816 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1817 && ! rld[r].optional
1818 && rld[r].regno == -1)
1819 if (! find_reg (chain, i))
1821 spill_failure (chain->insn, rld[r].class);
1827 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1828 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1830 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1834 select_reload_regs (void)
1836 struct insn_chain *chain;
1838 /* Try to satisfy the needs for each insn. */
1839 for (chain = insns_need_reload; chain != 0;
1840 chain = chain->next_need_reload)
1841 find_reload_regs (chain);
1844 /* Delete all insns that were inserted by emit_caller_save_insns during
1847 delete_caller_save_insns (void)
1849 struct insn_chain *c = reload_insn_chain;
1853 while (c != 0 && c->is_caller_save_insn)
1855 struct insn_chain *next = c->next;
1858 if (c == reload_insn_chain)
1859 reload_insn_chain = next;
1863 next->prev = c->prev;
1865 c->prev->next = next;
1866 c->next = unused_insn_chains;
1867 unused_insn_chains = c;
1875 /* Handle the failure to find a register to spill.
1876 INSN should be one of the insns which needed this particular spill reg. */
1879 spill_failure (rtx insn, enum reg_class class)
1881 if (asm_noperands (PATTERN (insn)) >= 0)
1882 error_for_asm (insn, "can't find a register in class %qs while "
1883 "reloading %<asm%>",
1884 reg_class_names[class]);
1887 error ("unable to find a register to spill in class %qs",
1888 reg_class_names[class]);
1889 fatal_insn ("this is the insn:", insn);
1893 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1894 data that is dead in INSN. */
1897 delete_dead_insn (rtx insn)
1899 rtx prev = prev_real_insn (insn);
1902 /* If the previous insn sets a register that dies in our insn, delete it
1904 if (prev && GET_CODE (PATTERN (prev)) == SET
1905 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
1906 && reg_mentioned_p (prev_dest, PATTERN (insn))
1907 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1908 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1909 delete_dead_insn (prev);
1911 SET_INSN_DELETED (insn);
1914 /* Modify the home of pseudo-reg I.
1915 The new home is present in reg_renumber[I].
1917 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1918 or it may be -1, meaning there is none or it is not relevant.
1919 This is used so that all pseudos spilled from a given hard reg
1920 can share one stack slot. */
1923 alter_reg (int i, int from_reg)
1925 /* When outputting an inline function, this can happen
1926 for a reg that isn't actually used. */
1927 if (regno_reg_rtx[i] == 0)
1930 /* If the reg got changed to a MEM at rtl-generation time,
1932 if (!REG_P (regno_reg_rtx[i]))
1935 /* Modify the reg-rtx to contain the new hard reg
1936 number or else to contain its pseudo reg number. */
1937 REGNO (regno_reg_rtx[i])
1938 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1940 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1941 allocate a stack slot for it. */
1943 if (reg_renumber[i] < 0
1944 && REG_N_REFS (i) > 0
1945 && reg_equiv_constant[i] == 0
1946 && reg_equiv_memory_loc[i] == 0)
1949 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1950 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1953 /* Each pseudo reg has an inherent size which comes from its own mode,
1954 and a total size which provides room for paradoxical subregs
1955 which refer to the pseudo reg in wider modes.
1957 We can use a slot already allocated if it provides both
1958 enough inherent space and enough total space.
1959 Otherwise, we allocate a new slot, making sure that it has no less
1960 inherent space, and no less total space, then the previous slot. */
1963 /* No known place to spill from => no slot to reuse. */
1964 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1965 inherent_size == total_size ? 0 : -1);
1966 if (BYTES_BIG_ENDIAN)
1967 /* Cancel the big-endian correction done in assign_stack_local.
1968 Get the address of the beginning of the slot.
1969 This is so we can do a big-endian correction unconditionally
1971 adjust = inherent_size - total_size;
1973 /* Nothing can alias this slot except this pseudo. */
1974 set_mem_alias_set (x, new_alias_set ());
1977 /* Reuse a stack slot if possible. */
1978 else if (spill_stack_slot[from_reg] != 0
1979 && spill_stack_slot_width[from_reg] >= total_size
1980 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1982 x = spill_stack_slot[from_reg];
1984 /* Allocate a bigger slot. */
1987 /* Compute maximum size needed, both for inherent size
1988 and for total size. */
1989 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1992 if (spill_stack_slot[from_reg])
1994 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1996 mode = GET_MODE (spill_stack_slot[from_reg]);
1997 if (spill_stack_slot_width[from_reg] > total_size)
1998 total_size = spill_stack_slot_width[from_reg];
2001 /* Make a slot with that size. */
2002 x = assign_stack_local (mode, total_size,
2003 inherent_size == total_size ? 0 : -1);
2006 /* All pseudos mapped to this slot can alias each other. */
2007 if (spill_stack_slot[from_reg])
2008 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2010 set_mem_alias_set (x, new_alias_set ());
2012 if (BYTES_BIG_ENDIAN)
2014 /* Cancel the big-endian correction done in assign_stack_local.
2015 Get the address of the beginning of the slot.
2016 This is so we can do a big-endian correction unconditionally
2018 adjust = GET_MODE_SIZE (mode) - total_size;
2021 = adjust_address_nv (x, mode_for_size (total_size
2027 spill_stack_slot[from_reg] = stack_slot;
2028 spill_stack_slot_width[from_reg] = total_size;
2031 /* On a big endian machine, the "address" of the slot
2032 is the address of the low part that fits its inherent mode. */
2033 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2034 adjust += (total_size - inherent_size);
2036 /* If we have any adjustment to make, or if the stack slot is the
2037 wrong mode, make a new stack slot. */
2038 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2040 /* If we have a decl for the original register, set it for the
2041 memory. If this is a shared MEM, make a copy. */
2042 if (REG_EXPR (regno_reg_rtx[i])
2043 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2045 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2047 /* We can do this only for the DECLs home pseudo, not for
2048 any copies of it, since otherwise when the stack slot
2049 is reused, nonoverlapping_memrefs_p might think they
2051 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2053 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2056 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2060 /* Save the stack slot for later. */
2061 reg_equiv_memory_loc[i] = x;
2065 /* Mark the slots in regs_ever_live for the hard regs
2066 used by pseudo-reg number REGNO. */
2069 mark_home_live (int regno)
2073 i = reg_renumber[regno];
2076 lim = i + hard_regno_nregs[i][PSEUDO_REGNO_MODE (regno)];
2078 regs_ever_live[i++] = 1;
2081 /* This function handles the tracking of elimination offsets around branches.
2083 X is a piece of RTL being scanned.
2085 INSN is the insn that it came from, if any.
2087 INITIAL_P is nonzero if we are to set the offset to be the initial
2088 offset and zero if we are setting the offset of the label to be the
2092 set_label_offsets (rtx x, rtx insn, int initial_p)
2094 enum rtx_code code = GET_CODE (x);
2097 struct elim_table *p;
2102 if (LABEL_REF_NONLOCAL_P (x))
2107 /* ... fall through ... */
2110 /* If we know nothing about this label, set the desired offsets. Note
2111 that this sets the offset at a label to be the offset before a label
2112 if we don't know anything about the label. This is not correct for
2113 the label after a BARRIER, but is the best guess we can make. If
2114 we guessed wrong, we will suppress an elimination that might have
2115 been possible had we been able to guess correctly. */
2117 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2119 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2120 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2121 = (initial_p ? reg_eliminate[i].initial_offset
2122 : reg_eliminate[i].offset);
2123 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2126 /* Otherwise, if this is the definition of a label and it is
2127 preceded by a BARRIER, set our offsets to the known offset of
2131 && (tem = prev_nonnote_insn (insn)) != 0
2133 set_offsets_for_label (insn);
2135 /* If neither of the above cases is true, compare each offset
2136 with those previously recorded and suppress any eliminations
2137 where the offsets disagree. */
2139 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2140 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2141 != (initial_p ? reg_eliminate[i].initial_offset
2142 : reg_eliminate[i].offset))
2143 reg_eliminate[i].can_eliminate = 0;
2148 set_label_offsets (PATTERN (insn), insn, initial_p);
2150 /* ... fall through ... */
2154 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2155 and hence must have all eliminations at their initial offsets. */
2156 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2157 if (REG_NOTE_KIND (tem) == REG_LABEL)
2158 set_label_offsets (XEXP (tem, 0), insn, 1);
2164 /* Each of the labels in the parallel or address vector must be
2165 at their initial offsets. We want the first field for PARALLEL
2166 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2168 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2169 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2174 /* We only care about setting PC. If the source is not RETURN,
2175 IF_THEN_ELSE, or a label, disable any eliminations not at
2176 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2177 isn't one of those possibilities. For branches to a label,
2178 call ourselves recursively.
2180 Note that this can disable elimination unnecessarily when we have
2181 a non-local goto since it will look like a non-constant jump to
2182 someplace in the current function. This isn't a significant
2183 problem since such jumps will normally be when all elimination
2184 pairs are back to their initial offsets. */
2186 if (SET_DEST (x) != pc_rtx)
2189 switch (GET_CODE (SET_SRC (x)))
2196 set_label_offsets (SET_SRC (x), insn, initial_p);
2200 tem = XEXP (SET_SRC (x), 1);
2201 if (GET_CODE (tem) == LABEL_REF)
2202 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2203 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2206 tem = XEXP (SET_SRC (x), 2);
2207 if (GET_CODE (tem) == LABEL_REF)
2208 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2209 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2217 /* If we reach here, all eliminations must be at their initial
2218 offset because we are doing a jump to a variable address. */
2219 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2220 if (p->offset != p->initial_offset)
2221 p->can_eliminate = 0;
2229 /* Scan X and replace any eliminable registers (such as fp) with a
2230 replacement (such as sp), plus an offset.
2232 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2233 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2234 MEM, we are allowed to replace a sum of a register and the constant zero
2235 with the register, which we cannot do outside a MEM. In addition, we need
2236 to record the fact that a register is referenced outside a MEM.
2238 If INSN is an insn, it is the insn containing X. If we replace a REG
2239 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2240 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2241 the REG is being modified.
2243 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2244 That's used when we eliminate in expressions stored in notes.
2245 This means, do not set ref_outside_mem even if the reference
2248 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2249 replacements done assuming all offsets are at their initial values. If
2250 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2251 encounter, return the actual location so that find_reloads will do
2252 the proper thing. */
2255 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2257 enum rtx_code code = GET_CODE (x);
2258 struct elim_table *ep;
2265 if (! current_function_decl)
2287 /* First handle the case where we encounter a bare register that
2288 is eliminable. Replace it with a PLUS. */
2289 if (regno < FIRST_PSEUDO_REGISTER)
2291 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2293 if (ep->from_rtx == x && ep->can_eliminate)
2294 return plus_constant (ep->to_rtx, ep->previous_offset);
2297 else if (reg_renumber && reg_renumber[regno] < 0
2298 && reg_equiv_constant && reg_equiv_constant[regno]
2299 && ! CONSTANT_P (reg_equiv_constant[regno]))
2300 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2304 /* You might think handling MINUS in a manner similar to PLUS is a
2305 good idea. It is not. It has been tried multiple times and every
2306 time the change has had to have been reverted.
2308 Other parts of reload know a PLUS is special (gen_reload for example)
2309 and require special code to handle code a reloaded PLUS operand.
2311 Also consider backends where the flags register is clobbered by a
2312 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2313 lea instruction comes to mind). If we try to reload a MINUS, we
2314 may kill the flags register that was holding a useful value.
2316 So, please before trying to handle MINUS, consider reload as a
2317 whole instead of this little section as well as the backend issues. */
2319 /* If this is the sum of an eliminable register and a constant, rework
2321 if (REG_P (XEXP (x, 0))
2322 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2323 && CONSTANT_P (XEXP (x, 1)))
2325 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2327 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2329 /* The only time we want to replace a PLUS with a REG (this
2330 occurs when the constant operand of the PLUS is the negative
2331 of the offset) is when we are inside a MEM. We won't want
2332 to do so at other times because that would change the
2333 structure of the insn in a way that reload can't handle.
2334 We special-case the commonest situation in
2335 eliminate_regs_in_insn, so just replace a PLUS with a
2336 PLUS here, unless inside a MEM. */
2337 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2338 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2341 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2342 plus_constant (XEXP (x, 1),
2343 ep->previous_offset));
2346 /* If the register is not eliminable, we are done since the other
2347 operand is a constant. */
2351 /* If this is part of an address, we want to bring any constant to the
2352 outermost PLUS. We will do this by doing register replacement in
2353 our operands and seeing if a constant shows up in one of them.
2355 Note that there is no risk of modifying the structure of the insn,
2356 since we only get called for its operands, thus we are either
2357 modifying the address inside a MEM, or something like an address
2358 operand of a load-address insn. */
2361 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2362 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2364 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2366 /* If one side is a PLUS and the other side is a pseudo that
2367 didn't get a hard register but has a reg_equiv_constant,
2368 we must replace the constant here since it may no longer
2369 be in the position of any operand. */
2370 if (GET_CODE (new0) == PLUS && REG_P (new1)
2371 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2372 && reg_renumber[REGNO (new1)] < 0
2373 && reg_equiv_constant != 0
2374 && reg_equiv_constant[REGNO (new1)] != 0)
2375 new1 = reg_equiv_constant[REGNO (new1)];
2376 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2377 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2378 && reg_renumber[REGNO (new0)] < 0
2379 && reg_equiv_constant[REGNO (new0)] != 0)
2380 new0 = reg_equiv_constant[REGNO (new0)];
2382 new = form_sum (new0, new1);
2384 /* As above, if we are not inside a MEM we do not want to
2385 turn a PLUS into something else. We might try to do so here
2386 for an addition of 0 if we aren't optimizing. */
2387 if (! mem_mode && GET_CODE (new) != PLUS)
2388 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2396 /* If this is the product of an eliminable register and a
2397 constant, apply the distribute law and move the constant out
2398 so that we have (plus (mult ..) ..). This is needed in order
2399 to keep load-address insns valid. This case is pathological.
2400 We ignore the possibility of overflow here. */
2401 if (REG_P (XEXP (x, 0))
2402 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2403 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2404 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2406 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2409 /* Refs inside notes don't count for this purpose. */
2410 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2411 || GET_CODE (insn) == INSN_LIST)))
2412 ep->ref_outside_mem = 1;
2415 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2416 ep->previous_offset * INTVAL (XEXP (x, 1)));
2419 /* ... fall through ... */
2423 /* See comments before PLUS about handling MINUS. */
2425 case DIV: case UDIV:
2426 case MOD: case UMOD:
2427 case AND: case IOR: case XOR:
2428 case ROTATERT: case ROTATE:
2429 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2431 case GE: case GT: case GEU: case GTU:
2432 case LE: case LT: case LEU: case LTU:
2434 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2436 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2438 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2439 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2444 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2447 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2448 if (new != XEXP (x, 0))
2450 /* If this is a REG_DEAD note, it is not valid anymore.
2451 Using the eliminated version could result in creating a
2452 REG_DEAD note for the stack or frame pointer. */
2453 if (GET_MODE (x) == REG_DEAD)
2455 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2458 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2462 /* ... fall through ... */
2465 /* Now do eliminations in the rest of the chain. If this was
2466 an EXPR_LIST, this might result in allocating more memory than is
2467 strictly needed, but it simplifies the code. */
2470 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2471 if (new != XEXP (x, 1))
2473 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2481 case STRICT_LOW_PART:
2483 case SIGN_EXTEND: case ZERO_EXTEND:
2484 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2485 case FLOAT: case FIX:
2486 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2494 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2495 if (new != XEXP (x, 0))
2496 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2500 /* Similar to above processing, but preserve SUBREG_BYTE.
2501 Convert (subreg (mem)) to (mem) if not paradoxical.
2502 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2503 pseudo didn't get a hard reg, we must replace this with the
2504 eliminated version of the memory location because push_reload
2505 may do the replacement in certain circumstances. */
2506 if (REG_P (SUBREG_REG (x))
2507 && (GET_MODE_SIZE (GET_MODE (x))
2508 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2509 && reg_equiv_memory_loc != 0
2510 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2512 new = SUBREG_REG (x);
2515 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2517 if (new != SUBREG_REG (x))
2519 int x_size = GET_MODE_SIZE (GET_MODE (x));
2520 int new_size = GET_MODE_SIZE (GET_MODE (new));
2523 && ((x_size < new_size
2524 #ifdef WORD_REGISTER_OPERATIONS
2525 /* On these machines, combine can create rtl of the form
2526 (set (subreg:m1 (reg:m2 R) 0) ...)
2527 where m1 < m2, and expects something interesting to
2528 happen to the entire word. Moreover, it will use the
2529 (reg:m2 R) later, expecting all bits to be preserved.
2530 So if the number of words is the same, preserve the
2531 subreg so that push_reload can see it. */
2532 && ! ((x_size - 1) / UNITS_PER_WORD
2533 == (new_size -1 ) / UNITS_PER_WORD)
2536 || x_size == new_size)
2538 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2540 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2546 /* Our only special processing is to pass the mode of the MEM to our
2547 recursive call and copy the flags. While we are here, handle this
2548 case more efficiently. */
2550 replace_equiv_address_nv (x,
2551 eliminate_regs (XEXP (x, 0),
2552 GET_MODE (x), insn));
2555 /* Handle insn_list USE that a call to a pure function may generate. */
2556 new = eliminate_regs (XEXP (x, 0), 0, insn);
2557 if (new != XEXP (x, 0))
2558 return gen_rtx_USE (GET_MODE (x), new);
2570 /* Process each of our operands recursively. If any have changed, make a
2572 fmt = GET_RTX_FORMAT (code);
2573 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2577 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2578 if (new != XEXP (x, i) && ! copied)
2580 rtx new_x = rtx_alloc (code);
2581 memcpy (new_x, x, RTX_SIZE (code));
2587 else if (*fmt == 'E')
2590 for (j = 0; j < XVECLEN (x, i); j++)
2592 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2593 if (new != XVECEXP (x, i, j) && ! copied_vec)
2595 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2599 rtx new_x = rtx_alloc (code);
2600 memcpy (new_x, x, RTX_SIZE (code));
2604 XVEC (x, i) = new_v;
2607 XVECEXP (x, i, j) = new;
2615 /* Scan rtx X for modifications of elimination target registers. Update
2616 the table of eliminables to reflect the changed state. MEM_MODE is
2617 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2620 elimination_effects (rtx x, enum machine_mode mem_mode)
2622 enum rtx_code code = GET_CODE (x);
2623 struct elim_table *ep;
2647 /* First handle the case where we encounter a bare register that
2648 is eliminable. Replace it with a PLUS. */
2649 if (regno < FIRST_PSEUDO_REGISTER)
2651 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2653 if (ep->from_rtx == x && ep->can_eliminate)
2656 ep->ref_outside_mem = 1;
2661 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2662 && reg_equiv_constant[regno]
2663 && ! function_invariant_p (reg_equiv_constant[regno]))
2664 elimination_effects (reg_equiv_constant[regno], mem_mode);
2673 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2674 if (ep->to_rtx == XEXP (x, 0))
2676 int size = GET_MODE_SIZE (mem_mode);
2678 /* If more bytes than MEM_MODE are pushed, account for them. */
2679 #ifdef PUSH_ROUNDING
2680 if (ep->to_rtx == stack_pointer_rtx)
2681 size = PUSH_ROUNDING (size);
2683 if (code == PRE_DEC || code == POST_DEC)
2685 else if (code == PRE_INC || code == POST_INC)
2687 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2688 && GET_CODE (XEXP (x, 1)) == PLUS
2689 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2690 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2691 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2694 /* These two aren't unary operators. */
2695 if (code == POST_MODIFY || code == PRE_MODIFY)
2698 /* Fall through to generic unary operation case. */
2699 case STRICT_LOW_PART:
2701 case SIGN_EXTEND: case ZERO_EXTEND:
2702 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2703 case FLOAT: case FIX:
2704 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2712 elimination_effects (XEXP (x, 0), mem_mode);
2716 if (REG_P (SUBREG_REG (x))
2717 && (GET_MODE_SIZE (GET_MODE (x))
2718 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2719 && reg_equiv_memory_loc != 0
2720 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2723 elimination_effects (SUBREG_REG (x), mem_mode);
2727 /* If using a register that is the source of an eliminate we still
2728 think can be performed, note it cannot be performed since we don't
2729 know how this register is used. */
2730 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2731 if (ep->from_rtx == XEXP (x, 0))
2732 ep->can_eliminate = 0;
2734 elimination_effects (XEXP (x, 0), mem_mode);
2738 /* If clobbering a register that is the replacement register for an
2739 elimination we still think can be performed, note that it cannot
2740 be performed. Otherwise, we need not be concerned about it. */
2741 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2742 if (ep->to_rtx == XEXP (x, 0))
2743 ep->can_eliminate = 0;
2745 elimination_effects (XEXP (x, 0), mem_mode);
2749 /* Check for setting a register that we know about. */
2750 if (REG_P (SET_DEST (x)))
2752 /* See if this is setting the replacement register for an
2755 If DEST is the hard frame pointer, we do nothing because we
2756 assume that all assignments to the frame pointer are for
2757 non-local gotos and are being done at a time when they are valid
2758 and do not disturb anything else. Some machines want to
2759 eliminate a fake argument pointer (or even a fake frame pointer)
2760 with either the real frame or the stack pointer. Assignments to
2761 the hard frame pointer must not prevent this elimination. */
2763 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2765 if (ep->to_rtx == SET_DEST (x)
2766 && SET_DEST (x) != hard_frame_pointer_rtx)
2768 /* If it is being incremented, adjust the offset. Otherwise,
2769 this elimination can't be done. */
2770 rtx src = SET_SRC (x);
2772 if (GET_CODE (src) == PLUS
2773 && XEXP (src, 0) == SET_DEST (x)
2774 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2775 ep->offset -= INTVAL (XEXP (src, 1));
2777 ep->can_eliminate = 0;
2781 elimination_effects (SET_DEST (x), 0);
2782 elimination_effects (SET_SRC (x), 0);
2786 /* Our only special processing is to pass the mode of the MEM to our
2788 elimination_effects (XEXP (x, 0), GET_MODE (x));
2795 fmt = GET_RTX_FORMAT (code);
2796 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2799 elimination_effects (XEXP (x, i), mem_mode);
2800 else if (*fmt == 'E')
2801 for (j = 0; j < XVECLEN (x, i); j++)
2802 elimination_effects (XVECEXP (x, i, j), mem_mode);
2806 /* Descend through rtx X and verify that no references to eliminable registers
2807 remain. If any do remain, mark the involved register as not
2811 check_eliminable_occurrences (rtx x)
2820 code = GET_CODE (x);
2822 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2824 struct elim_table *ep;
2826 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2827 if (ep->from_rtx == x)
2828 ep->can_eliminate = 0;
2832 fmt = GET_RTX_FORMAT (code);
2833 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2836 check_eliminable_occurrences (XEXP (x, i));
2837 else if (*fmt == 'E')
2840 for (j = 0; j < XVECLEN (x, i); j++)
2841 check_eliminable_occurrences (XVECEXP (x, i, j));
2846 /* Scan INSN and eliminate all eliminable registers in it.
2848 If REPLACE is nonzero, do the replacement destructively. Also
2849 delete the insn as dead it if it is setting an eliminable register.
2851 If REPLACE is zero, do all our allocations in reload_obstack.
2853 If no eliminations were done and this insn doesn't require any elimination
2854 processing (these are not identical conditions: it might be updating sp,
2855 but not referencing fp; this needs to be seen during reload_as_needed so
2856 that the offset between fp and sp can be taken into consideration), zero
2857 is returned. Otherwise, 1 is returned. */
2860 eliminate_regs_in_insn (rtx insn, int replace)
2862 int icode = recog_memoized (insn);
2863 rtx old_body = PATTERN (insn);
2864 int insn_is_asm = asm_noperands (old_body) >= 0;
2865 rtx old_set = single_set (insn);
2869 rtx substed_operand[MAX_RECOG_OPERANDS];
2870 rtx orig_operand[MAX_RECOG_OPERANDS];
2871 struct elim_table *ep;
2874 if (! insn_is_asm && icode < 0)
2876 gcc_assert (GET_CODE (PATTERN (insn)) == USE
2877 || GET_CODE (PATTERN (insn)) == CLOBBER
2878 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2879 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2880 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
2884 if (old_set != 0 && REG_P (SET_DEST (old_set))
2885 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2887 /* Check for setting an eliminable register. */
2888 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2889 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2891 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2892 /* If this is setting the frame pointer register to the
2893 hardware frame pointer register and this is an elimination
2894 that will be done (tested above), this insn is really
2895 adjusting the frame pointer downward to compensate for
2896 the adjustment done before a nonlocal goto. */
2897 if (ep->from == FRAME_POINTER_REGNUM
2898 && ep->to == HARD_FRAME_POINTER_REGNUM)
2900 rtx base = SET_SRC (old_set);
2901 rtx base_insn = insn;
2902 HOST_WIDE_INT offset = 0;
2904 while (base != ep->to_rtx)
2906 rtx prev_insn, prev_set;
2908 if (GET_CODE (base) == PLUS
2909 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2911 offset += INTVAL (XEXP (base, 1));
2912 base = XEXP (base, 0);
2914 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2915 && (prev_set = single_set (prev_insn)) != 0
2916 && rtx_equal_p (SET_DEST (prev_set), base))
2918 base = SET_SRC (prev_set);
2919 base_insn = prev_insn;
2925 if (base == ep->to_rtx)
2928 = plus_constant (ep->to_rtx, offset - ep->offset);
2930 new_body = old_body;
2933 new_body = copy_insn (old_body);
2934 if (REG_NOTES (insn))
2935 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2937 PATTERN (insn) = new_body;
2938 old_set = single_set (insn);
2940 /* First see if this insn remains valid when we
2941 make the change. If not, keep the INSN_CODE
2942 the same and let reload fit it up. */
2943 validate_change (insn, &SET_SRC (old_set), src, 1);
2944 validate_change (insn, &SET_DEST (old_set),
2946 if (! apply_change_group ())
2948 SET_SRC (old_set) = src;
2949 SET_DEST (old_set) = ep->to_rtx;
2958 /* In this case this insn isn't serving a useful purpose. We
2959 will delete it in reload_as_needed once we know that this
2960 elimination is, in fact, being done.
2962 If REPLACE isn't set, we can't delete this insn, but needn't
2963 process it since it won't be used unless something changes. */
2966 delete_dead_insn (insn);
2974 /* We allow one special case which happens to work on all machines we
2975 currently support: a single set with the source or a REG_EQUAL
2976 note being a PLUS of an eliminable register and a constant. */
2978 if (old_set && REG_P (SET_DEST (old_set)))
2980 /* First see if the source is of the form (plus (reg) CST). */
2981 if (GET_CODE (SET_SRC (old_set)) == PLUS
2982 && REG_P (XEXP (SET_SRC (old_set), 0))
2983 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
2984 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
2985 plus_src = SET_SRC (old_set);
2986 else if (REG_P (SET_SRC (old_set)))
2988 /* Otherwise, see if we have a REG_EQUAL note of the form
2989 (plus (reg) CST). */
2991 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
2993 if (REG_NOTE_KIND (links) == REG_EQUAL
2994 && GET_CODE (XEXP (links, 0)) == PLUS
2995 && REG_P (XEXP (XEXP (links, 0), 0))
2996 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT
2997 && REGNO (XEXP (XEXP (links, 0), 0)) < FIRST_PSEUDO_REGISTER)
2999 plus_src = XEXP (links, 0);
3007 rtx reg = XEXP (plus_src, 0);
3008 HOST_WIDE_INT offset = INTVAL (XEXP (plus_src, 1));
3010 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3011 if (ep->from_rtx == reg && ep->can_eliminate)
3013 offset += ep->offset;
3018 /* We assume here that if we need a PARALLEL with
3019 CLOBBERs for this assignment, we can do with the
3020 MATCH_SCRATCHes that add_clobbers allocates.
3021 There's not much we can do if that doesn't work. */
3022 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3026 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3029 rtvec vec = rtvec_alloc (num_clobbers + 1);
3031 vec->elem[0] = PATTERN (insn);
3032 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3033 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3035 gcc_assert (INSN_CODE (insn) >= 0);
3037 /* If we have a nonzero offset, and the source is already
3038 a simple REG, the following transformation would
3039 increase the cost of the insn by replacing a simple REG
3040 with (plus (reg sp) CST). So try only when plus_src
3041 comes from old_set proper, not REG_NOTES. */
3042 else if (SET_SRC (old_set) == plus_src)
3044 new_body = old_body;
3047 new_body = copy_insn (old_body);
3048 if (REG_NOTES (insn))
3049 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3051 PATTERN (insn) = new_body;
3052 old_set = single_set (insn);
3054 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3055 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3061 /* This can't have an effect on elimination offsets, so skip right
3067 /* Determine the effects of this insn on elimination offsets. */
3068 elimination_effects (old_body, 0);
3070 /* Eliminate all eliminable registers occurring in operands that
3071 can be handled by reload. */
3072 extract_insn (insn);
3073 for (i = 0; i < recog_data.n_operands; i++)
3075 orig_operand[i] = recog_data.operand[i];
3076 substed_operand[i] = recog_data.operand[i];
3078 /* For an asm statement, every operand is eliminable. */
3079 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3081 /* Check for setting a register that we know about. */
3082 if (recog_data.operand_type[i] != OP_IN
3083 && REG_P (orig_operand[i]))
3085 /* If we are assigning to a register that can be eliminated, it
3086 must be as part of a PARALLEL, since the code above handles
3087 single SETs. We must indicate that we can no longer
3088 eliminate this reg. */
3089 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3091 if (ep->from_rtx == orig_operand[i])
3092 ep->can_eliminate = 0;
3095 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3096 replace ? insn : NULL_RTX);
3097 if (substed_operand[i] != orig_operand[i])
3099 /* Terminate the search in check_eliminable_occurrences at
3101 *recog_data.operand_loc[i] = 0;
3103 /* If an output operand changed from a REG to a MEM and INSN is an
3104 insn, write a CLOBBER insn. */
3105 if (recog_data.operand_type[i] != OP_IN
3106 && REG_P (orig_operand[i])
3107 && MEM_P (substed_operand[i])
3109 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3114 for (i = 0; i < recog_data.n_dups; i++)
3115 *recog_data.dup_loc[i]
3116 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3118 /* If any eliminable remain, they aren't eliminable anymore. */
3119 check_eliminable_occurrences (old_body);
3121 /* Substitute the operands; the new values are in the substed_operand
3123 for (i = 0; i < recog_data.n_operands; i++)
3124 *recog_data.operand_loc[i] = substed_operand[i];
3125 for (i = 0; i < recog_data.n_dups; i++)
3126 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3128 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3129 re-recognize the insn. We do this in case we had a simple addition
3130 but now can do this as a load-address. This saves an insn in this
3132 If re-recognition fails, the old insn code number will still be used,
3133 and some register operands may have changed into PLUS expressions.
3134 These will be handled by find_reloads by loading them into a register
3139 /* If we aren't replacing things permanently and we changed something,
3140 make another copy to ensure that all the RTL is new. Otherwise
3141 things can go wrong if find_reload swaps commutative operands
3142 and one is inside RTL that has been copied while the other is not. */
3143 new_body = old_body;
3146 new_body = copy_insn (old_body);
3147 if (REG_NOTES (insn))
3148 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3150 PATTERN (insn) = new_body;
3152 /* If we had a move insn but now we don't, rerecognize it. This will
3153 cause spurious re-recognition if the old move had a PARALLEL since
3154 the new one still will, but we can't call single_set without
3155 having put NEW_BODY into the insn and the re-recognition won't
3156 hurt in this rare case. */
3157 /* ??? Why this huge if statement - why don't we just rerecognize the
3161 && ((REG_P (SET_SRC (old_set))
3162 && (GET_CODE (new_body) != SET
3163 || !REG_P (SET_SRC (new_body))))
3164 /* If this was a load from or store to memory, compare
3165 the MEM in recog_data.operand to the one in the insn.
3166 If they are not equal, then rerecognize the insn. */
3168 && ((MEM_P (SET_SRC (old_set))
3169 && SET_SRC (old_set) != recog_data.operand[1])
3170 || (MEM_P (SET_DEST (old_set))
3171 && SET_DEST (old_set) != recog_data.operand[0])))
3172 /* If this was an add insn before, rerecognize. */
3173 || GET_CODE (SET_SRC (old_set)) == PLUS))
3175 int new_icode = recog (PATTERN (insn), insn, 0);
3177 INSN_CODE (insn) = icode;
3181 /* Restore the old body. If there were any changes to it, we made a copy
3182 of it while the changes were still in place, so we'll correctly return
3183 a modified insn below. */
3186 /* Restore the old body. */
3187 for (i = 0; i < recog_data.n_operands; i++)
3188 *recog_data.operand_loc[i] = orig_operand[i];
3189 for (i = 0; i < recog_data.n_dups; i++)
3190 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3193 /* Update all elimination pairs to reflect the status after the current
3194 insn. The changes we make were determined by the earlier call to
3195 elimination_effects.
3197 We also detect cases where register elimination cannot be done,
3198 namely, if a register would be both changed and referenced outside a MEM
3199 in the resulting insn since such an insn is often undefined and, even if
3200 not, we cannot know what meaning will be given to it. Note that it is
3201 valid to have a register used in an address in an insn that changes it
3202 (presumably with a pre- or post-increment or decrement).
3204 If anything changes, return nonzero. */
3206 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3208 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3209 ep->can_eliminate = 0;
3211 ep->ref_outside_mem = 0;
3213 if (ep->previous_offset != ep->offset)
3218 /* If we changed something, perform elimination in REG_NOTES. This is
3219 needed even when REPLACE is zero because a REG_DEAD note might refer
3220 to a register that we eliminate and could cause a different number
3221 of spill registers to be needed in the final reload pass than in
3223 if (val && REG_NOTES (insn) != 0)
3224 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3229 /* Loop through all elimination pairs.
3230 Recalculate the number not at initial offset.
3232 Compute the maximum offset (minimum offset if the stack does not
3233 grow downward) for each elimination pair. */
3236 update_eliminable_offsets (void)
3238 struct elim_table *ep;
3240 num_not_at_initial_offset = 0;
3241 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3243 ep->previous_offset = ep->offset;
3244 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3245 num_not_at_initial_offset++;
3249 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3250 replacement we currently believe is valid, mark it as not eliminable if X
3251 modifies DEST in any way other than by adding a constant integer to it.
3253 If DEST is the frame pointer, we do nothing because we assume that
3254 all assignments to the hard frame pointer are nonlocal gotos and are being
3255 done at a time when they are valid and do not disturb anything else.
3256 Some machines want to eliminate a fake argument pointer with either the
3257 frame or stack pointer. Assignments to the hard frame pointer must not
3258 prevent this elimination.
3260 Called via note_stores from reload before starting its passes to scan
3261 the insns of the function. */
3264 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3268 /* A SUBREG of a hard register here is just changing its mode. We should
3269 not see a SUBREG of an eliminable hard register, but check just in
3271 if (GET_CODE (dest) == SUBREG)
3272 dest = SUBREG_REG (dest);
3274 if (dest == hard_frame_pointer_rtx)
3277 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3278 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3279 && (GET_CODE (x) != SET
3280 || GET_CODE (SET_SRC (x)) != PLUS
3281 || XEXP (SET_SRC (x), 0) != dest
3282 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3284 reg_eliminate[i].can_eliminate_previous
3285 = reg_eliminate[i].can_eliminate = 0;
3290 /* Verify that the initial elimination offsets did not change since the
3291 last call to set_initial_elim_offsets. This is used to catch cases
3292 where something illegal happened during reload_as_needed that could
3293 cause incorrect code to be generated if we did not check for it. */
3296 verify_initial_elim_offsets (void)
3300 if (!num_eliminable)
3303 #ifdef ELIMINABLE_REGS
3305 struct elim_table *ep;
3307 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3309 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3310 if (t != ep->initial_offset)
3315 INITIAL_FRAME_POINTER_OFFSET (t);
3316 if (t != reg_eliminate[0].initial_offset)
3323 /* Reset all offsets on eliminable registers to their initial values. */
3326 set_initial_elim_offsets (void)
3328 struct elim_table *ep = reg_eliminate;
3330 #ifdef ELIMINABLE_REGS
3331 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3333 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3334 ep->previous_offset = ep->offset = ep->initial_offset;
3337 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3338 ep->previous_offset = ep->offset = ep->initial_offset;
3341 num_not_at_initial_offset = 0;
3344 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3347 set_initial_eh_label_offset (rtx label)
3349 set_label_offsets (label, NULL_RTX, 1);
3352 /* Initialize the known label offsets.
3353 Set a known offset for each forced label to be at the initial offset
3354 of each elimination. We do this because we assume that all
3355 computed jumps occur from a location where each elimination is
3356 at its initial offset.
3357 For all other labels, show that we don't know the offsets. */
3360 set_initial_label_offsets (void)
3363 memset (offsets_known_at, 0, num_labels);
3365 for (x = forced_labels; x; x = XEXP (x, 1))
3367 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3369 for_each_eh_label (set_initial_eh_label_offset);
3372 /* Set all elimination offsets to the known values for the code label given
3376 set_offsets_for_label (rtx insn)
3379 int label_nr = CODE_LABEL_NUMBER (insn);
3380 struct elim_table *ep;
3382 num_not_at_initial_offset = 0;
3383 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3385 ep->offset = ep->previous_offset
3386 = offsets_at[label_nr - first_label_num][i];
3387 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3388 num_not_at_initial_offset++;
3392 /* See if anything that happened changes which eliminations are valid.
3393 For example, on the SPARC, whether or not the frame pointer can
3394 be eliminated can depend on what registers have been used. We need
3395 not check some conditions again (such as flag_omit_frame_pointer)
3396 since they can't have changed. */
3399 update_eliminables (HARD_REG_SET *pset)
3401 int previous_frame_pointer_needed = frame_pointer_needed;
3402 struct elim_table *ep;
3404 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3405 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3406 #ifdef ELIMINABLE_REGS
3407 || ! CAN_ELIMINATE (ep->from, ep->to)
3410 ep->can_eliminate = 0;
3412 /* Look for the case where we have discovered that we can't replace
3413 register A with register B and that means that we will now be
3414 trying to replace register A with register C. This means we can
3415 no longer replace register C with register B and we need to disable
3416 such an elimination, if it exists. This occurs often with A == ap,
3417 B == sp, and C == fp. */
3419 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3421 struct elim_table *op;
3424 if (! ep->can_eliminate && ep->can_eliminate_previous)
3426 /* Find the current elimination for ep->from, if there is a
3428 for (op = reg_eliminate;
3429 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3430 if (op->from == ep->from && op->can_eliminate)
3436 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3438 for (op = reg_eliminate;
3439 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3440 if (op->from == new_to && op->to == ep->to)
3441 op->can_eliminate = 0;
3445 /* See if any registers that we thought we could eliminate the previous
3446 time are no longer eliminable. If so, something has changed and we
3447 must spill the register. Also, recompute the number of eliminable
3448 registers and see if the frame pointer is needed; it is if there is
3449 no elimination of the frame pointer that we can perform. */
3451 frame_pointer_needed = 1;
3452 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3454 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3455 && ep->to != HARD_FRAME_POINTER_REGNUM)
3456 frame_pointer_needed = 0;
3458 if (! ep->can_eliminate && ep->can_eliminate_previous)
3460 ep->can_eliminate_previous = 0;
3461 SET_HARD_REG_BIT (*pset, ep->from);
3466 /* If we didn't need a frame pointer last time, but we do now, spill
3467 the hard frame pointer. */
3468 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3469 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3472 /* Initialize the table of registers to eliminate. */
3475 init_elim_table (void)
3477 struct elim_table *ep;
3478 #ifdef ELIMINABLE_REGS
3479 const struct elim_table_1 *ep1;
3483 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3485 /* Does this function require a frame pointer? */
3487 frame_pointer_needed = (! flag_omit_frame_pointer
3488 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3489 and restore sp for alloca. So we can't eliminate
3490 the frame pointer in that case. At some point,
3491 we should improve this by emitting the
3492 sp-adjusting insns for this case. */
3493 || (current_function_calls_alloca
3494 && EXIT_IGNORE_STACK)
3495 || current_function_accesses_prior_frames
3496 || FRAME_POINTER_REQUIRED);
3500 #ifdef ELIMINABLE_REGS
3501 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3502 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3504 ep->from = ep1->from;
3506 ep->can_eliminate = ep->can_eliminate_previous
3507 = (CAN_ELIMINATE (ep->from, ep->to)
3508 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3511 reg_eliminate[0].from = reg_eliminate_1[0].from;
3512 reg_eliminate[0].to = reg_eliminate_1[0].to;
3513 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3514 = ! frame_pointer_needed;
3517 /* Count the number of eliminable registers and build the FROM and TO
3518 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3519 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3520 We depend on this. */
3521 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3523 num_eliminable += ep->can_eliminate;
3524 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3525 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3529 /* Kick all pseudos out of hard register REGNO.
3531 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3532 because we found we can't eliminate some register. In the case, no pseudos
3533 are allowed to be in the register, even if they are only in a block that
3534 doesn't require spill registers, unlike the case when we are spilling this
3535 hard reg to produce another spill register.
3537 Return nonzero if any pseudos needed to be kicked out. */
3540 spill_hard_reg (unsigned int regno, int cant_eliminate)
3546 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3547 regs_ever_live[regno] = 1;
3550 /* Spill every pseudo reg that was allocated to this reg
3551 or to something that overlaps this reg. */
3553 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3554 if (reg_renumber[i] >= 0
3555 && (unsigned int) reg_renumber[i] <= regno
3556 && ((unsigned int) reg_renumber[i]
3557 + hard_regno_nregs[(unsigned int) reg_renumber[i]]
3558 [PSEUDO_REGNO_MODE (i)]
3560 SET_REGNO_REG_SET (&spilled_pseudos, i);
3563 /* After find_reload_regs has been run for all insn that need reloads,
3564 and/or spill_hard_regs was called, this function is used to actually
3565 spill pseudo registers and try to reallocate them. It also sets up the
3566 spill_regs array for use by choose_reload_regs. */
3569 finish_spills (int global)
3571 struct insn_chain *chain;
3572 int something_changed = 0;
3574 reg_set_iterator rsi;
3576 /* Build the spill_regs array for the function. */
3577 /* If there are some registers still to eliminate and one of the spill regs
3578 wasn't ever used before, additional stack space may have to be
3579 allocated to store this register. Thus, we may have changed the offset
3580 between the stack and frame pointers, so mark that something has changed.
3582 One might think that we need only set VAL to 1 if this is a call-used
3583 register. However, the set of registers that must be saved by the
3584 prologue is not identical to the call-used set. For example, the
3585 register used by the call insn for the return PC is a call-used register,
3586 but must be saved by the prologue. */
3589 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3590 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3592 spill_reg_order[i] = n_spills;
3593 spill_regs[n_spills++] = i;
3594 if (num_eliminable && ! regs_ever_live[i])
3595 something_changed = 1;
3596 regs_ever_live[i] = 1;
3599 spill_reg_order[i] = -1;
3601 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3603 /* Record the current hard register the pseudo is allocated to in
3604 pseudo_previous_regs so we avoid reallocating it to the same
3605 hard reg in a later pass. */
3606 gcc_assert (reg_renumber[i] >= 0);
3608 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3609 /* Mark it as no longer having a hard register home. */
3610 reg_renumber[i] = -1;
3611 /* We will need to scan everything again. */
3612 something_changed = 1;
3615 /* Retry global register allocation if possible. */
3618 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3619 /* For every insn that needs reloads, set the registers used as spill
3620 regs in pseudo_forbidden_regs for every pseudo live across the
3622 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3624 EXECUTE_IF_SET_IN_REG_SET
3625 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3627 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3628 chain->used_spill_regs);
3630 EXECUTE_IF_SET_IN_REG_SET
3631 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3633 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3634 chain->used_spill_regs);
3638 /* Retry allocating the spilled pseudos. For each reg, merge the
3639 various reg sets that indicate which hard regs can't be used,
3640 and call retry_global_alloc.
3641 We change spill_pseudos here to only contain pseudos that did not
3642 get a new hard register. */
3643 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3644 if (reg_old_renumber[i] != reg_renumber[i])
3646 HARD_REG_SET forbidden;
3647 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3648 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3649 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3650 retry_global_alloc (i, forbidden);
3651 if (reg_renumber[i] >= 0)
3652 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3656 /* Fix up the register information in the insn chain.
3657 This involves deleting those of the spilled pseudos which did not get
3658 a new hard register home from the live_{before,after} sets. */
3659 for (chain = reload_insn_chain; chain; chain = chain->next)
3661 HARD_REG_SET used_by_pseudos;
3662 HARD_REG_SET used_by_pseudos2;
3664 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3665 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3667 /* Mark any unallocated hard regs as available for spills. That
3668 makes inheritance work somewhat better. */
3669 if (chain->need_reload)
3671 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3672 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3673 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3675 /* Save the old value for the sanity test below. */
3676 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3678 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3679 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3680 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3681 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3683 /* Make sure we only enlarge the set. */
3684 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3690 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3691 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3693 int regno = reg_renumber[i];
3694 if (reg_old_renumber[i] == regno)
3697 alter_reg (i, reg_old_renumber[i]);
3698 reg_old_renumber[i] = regno;
3702 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3704 fprintf (dump_file, " Register %d now in %d.\n\n",
3705 i, reg_renumber[i]);
3709 return something_changed;
3712 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3715 scan_paradoxical_subregs (rtx x)
3719 enum rtx_code code = GET_CODE (x);
3729 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3737 if (REG_P (SUBREG_REG (x))
3738 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3739 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3740 = GET_MODE_SIZE (GET_MODE (x));
3747 fmt = GET_RTX_FORMAT (code);
3748 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3751 scan_paradoxical_subregs (XEXP (x, i));
3752 else if (fmt[i] == 'E')
3755 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3756 scan_paradoxical_subregs (XVECEXP (x, i, j));
3761 /* Reload pseudo-registers into hard regs around each insn as needed.
3762 Additional register load insns are output before the insn that needs it
3763 and perhaps store insns after insns that modify the reloaded pseudo reg.
3765 reg_last_reload_reg and reg_reloaded_contents keep track of
3766 which registers are already available in reload registers.
3767 We update these for the reloads that we perform,
3768 as the insns are scanned. */
3771 reload_as_needed (int live_known)
3773 struct insn_chain *chain;
3774 #if defined (AUTO_INC_DEC)
3779 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3780 memset (spill_reg_store, 0, sizeof spill_reg_store);
3781 reg_last_reload_reg = xcalloc (max_regno, sizeof (rtx));
3782 reg_has_output_reload = xmalloc (max_regno);
3783 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3784 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
3786 set_initial_elim_offsets ();
3788 for (chain = reload_insn_chain; chain; chain = chain->next)
3791 rtx insn = chain->insn;
3792 rtx old_next = NEXT_INSN (insn);
3794 /* If we pass a label, copy the offsets from the label information
3795 into the current offsets of each elimination. */
3797 set_offsets_for_label (insn);
3799 else if (INSN_P (insn))
3801 rtx oldpat = copy_rtx (PATTERN (insn));
3803 /* If this is a USE and CLOBBER of a MEM, ensure that any
3804 references to eliminable registers have been removed. */
3806 if ((GET_CODE (PATTERN (insn)) == USE
3807 || GET_CODE (PATTERN (insn)) == CLOBBER)
3808 && MEM_P (XEXP (PATTERN (insn), 0)))
3809 XEXP (XEXP (PATTERN (insn), 0), 0)
3810 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3811 GET_MODE (XEXP (PATTERN (insn), 0)),
3814 /* If we need to do register elimination processing, do so.
3815 This might delete the insn, in which case we are done. */
3816 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3818 eliminate_regs_in_insn (insn, 1);
3821 update_eliminable_offsets ();
3826 /* If need_elim is nonzero but need_reload is zero, one might think
3827 that we could simply set n_reloads to 0. However, find_reloads
3828 could have done some manipulation of the insn (such as swapping
3829 commutative operands), and these manipulations are lost during
3830 the first pass for every insn that needs register elimination.
3831 So the actions of find_reloads must be redone here. */
3833 if (! chain->need_elim && ! chain->need_reload
3834 && ! chain->need_operand_change)
3836 /* First find the pseudo regs that must be reloaded for this insn.
3837 This info is returned in the tables reload_... (see reload.h).
3838 Also modify the body of INSN by substituting RELOAD
3839 rtx's for those pseudo regs. */
3842 memset (reg_has_output_reload, 0, max_regno);
3843 CLEAR_HARD_REG_SET (reg_is_output_reload);
3845 find_reloads (insn, 1, spill_indirect_levels, live_known,
3851 rtx next = NEXT_INSN (insn);
3854 prev = PREV_INSN (insn);
3856 /* Now compute which reload regs to reload them into. Perhaps
3857 reusing reload regs from previous insns, or else output
3858 load insns to reload them. Maybe output store insns too.
3859 Record the choices of reload reg in reload_reg_rtx. */
3860 choose_reload_regs (chain);
3862 /* Merge any reloads that we didn't combine for fear of
3863 increasing the number of spill registers needed but now
3864 discover can be safely merged. */
3865 if (SMALL_REGISTER_CLASSES)
3866 merge_assigned_reloads (insn);
3868 /* Generate the insns to reload operands into or out of
3869 their reload regs. */
3870 emit_reload_insns (chain);
3872 /* Substitute the chosen reload regs from reload_reg_rtx
3873 into the insn's body (or perhaps into the bodies of other
3874 load and store insn that we just made for reloading
3875 and that we moved the structure into). */
3876 subst_reloads (insn);
3878 /* If this was an ASM, make sure that all the reload insns
3879 we have generated are valid. If not, give an error
3882 if (asm_noperands (PATTERN (insn)) >= 0)
3883 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3884 if (p != insn && INSN_P (p)
3885 && GET_CODE (PATTERN (p)) != USE
3886 && (recog_memoized (p) < 0
3887 || (extract_insn (p), ! constrain_operands (1))))
3889 error_for_asm (insn,
3890 "%<asm%> operand requires "
3891 "impossible reload");
3896 if (num_eliminable && chain->need_elim)
3897 update_eliminable_offsets ();
3899 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3900 is no longer validly lying around to save a future reload.
3901 Note that this does not detect pseudos that were reloaded
3902 for this insn in order to be stored in
3903 (obeying register constraints). That is correct; such reload
3904 registers ARE still valid. */
3905 note_stores (oldpat, forget_old_reloads_1, NULL);
3907 /* There may have been CLOBBER insns placed after INSN. So scan
3908 between INSN and NEXT and use them to forget old reloads. */
3909 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3910 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
3911 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3914 /* Likewise for regs altered by auto-increment in this insn.
3915 REG_INC notes have been changed by reloading:
3916 find_reloads_address_1 records substitutions for them,
3917 which have been performed by subst_reloads above. */
3918 for (i = n_reloads - 1; i >= 0; i--)
3920 rtx in_reg = rld[i].in_reg;
3923 enum rtx_code code = GET_CODE (in_reg);
3924 /* PRE_INC / PRE_DEC will have the reload register ending up
3925 with the same value as the stack slot, but that doesn't
3926 hold true for POST_INC / POST_DEC. Either we have to
3927 convert the memory access to a true POST_INC / POST_DEC,
3928 or we can't use the reload register for inheritance. */
3929 if ((code == POST_INC || code == POST_DEC)
3930 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3931 REGNO (rld[i].reg_rtx))
3932 /* Make sure it is the inc/dec pseudo, and not
3933 some other (e.g. output operand) pseudo. */
3934 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3935 == REGNO (XEXP (in_reg, 0))))
3938 rtx reload_reg = rld[i].reg_rtx;
3939 enum machine_mode mode = GET_MODE (reload_reg);
3943 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3945 /* We really want to ignore REG_INC notes here, so
3946 use PATTERN (p) as argument to reg_set_p . */
3947 if (reg_set_p (reload_reg, PATTERN (p)))
3949 n = count_occurrences (PATTERN (p), reload_reg, 0);
3954 n = validate_replace_rtx (reload_reg,
3955 gen_rtx_fmt_e (code,
3960 /* We must also verify that the constraints
3961 are met after the replacement. */
3964 n = constrain_operands (1);
3968 /* If the constraints were not met, then
3969 undo the replacement. */
3972 validate_replace_rtx (gen_rtx_fmt_e (code,
3985 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3987 /* Mark this as having an output reload so that the
3988 REG_INC processing code below won't invalidate
3989 the reload for inheritance. */
3990 SET_HARD_REG_BIT (reg_is_output_reload,
3991 REGNO (reload_reg));
3992 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3995 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
3998 else if ((code == PRE_INC || code == PRE_DEC)
3999 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4000 REGNO (rld[i].reg_rtx))
4001 /* Make sure it is the inc/dec pseudo, and not
4002 some other (e.g. output operand) pseudo. */
4003 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4004 == REGNO (XEXP (in_reg, 0))))
4006 SET_HARD_REG_BIT (reg_is_output_reload,
4007 REGNO (rld[i].reg_rtx));
4008 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4012 /* If a pseudo that got a hard register is auto-incremented,
4013 we must purge records of copying it into pseudos without
4015 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4016 if (REG_NOTE_KIND (x) == REG_INC)
4018 /* See if this pseudo reg was reloaded in this insn.
4019 If so, its last-reload info is still valid
4020 because it is based on this insn's reload. */
4021 for (i = 0; i < n_reloads; i++)
4022 if (rld[i].out == XEXP (x, 0))
4026 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4030 /* A reload reg's contents are unknown after a label. */
4032 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4034 /* Don't assume a reload reg is still good after a call insn
4035 if it is a call-used reg, or if it contains a value that will
4036 be partially clobbered by the call. */
4037 else if (CALL_P (insn))
4039 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4040 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4045 free (reg_last_reload_reg);
4046 free (reg_has_output_reload);
4049 /* Discard all record of any value reloaded from X,
4050 or reloaded in X from someplace else;
4051 unless X is an output reload reg of the current insn.
4053 X may be a hard reg (the reload reg)
4054 or it may be a pseudo reg that was reloaded from. */
4057 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4058 void *data ATTRIBUTE_UNUSED)
4063 /* note_stores does give us subregs of hard regs,
4064 subreg_regno_offset requires a hard reg. */
4065 while (GET_CODE (x) == SUBREG)
4067 /* We ignore the subreg offset when calculating the regno,
4068 because we are using the entire underlying hard register
4078 if (regno >= FIRST_PSEUDO_REGISTER)
4084 nr = hard_regno_nregs[regno][GET_MODE (x)];
4085 /* Storing into a spilled-reg invalidates its contents.
4086 This can happen if a block-local pseudo is allocated to that reg
4087 and it wasn't spilled because this block's total need is 0.
4088 Then some insn might have an optional reload and use this reg. */
4089 for (i = 0; i < nr; i++)
4090 /* But don't do this if the reg actually serves as an output
4091 reload reg in the current instruction. */
4093 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4095 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4096 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4097 spill_reg_store[regno + i] = 0;
4101 /* Since value of X has changed,
4102 forget any value previously copied from it. */
4105 /* But don't forget a copy if this is the output reload
4106 that establishes the copy's validity. */
4107 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4108 reg_last_reload_reg[regno + nr] = 0;
4111 /* The following HARD_REG_SETs indicate when each hard register is
4112 used for a reload of various parts of the current insn. */
4114 /* If reg is unavailable for all reloads. */
4115 static HARD_REG_SET reload_reg_unavailable;
4116 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4117 static HARD_REG_SET reload_reg_used;
4118 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4119 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4120 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4121 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4122 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4123 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4124 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4125 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4126 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4127 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4128 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4129 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4130 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4131 static HARD_REG_SET reload_reg_used_in_op_addr;
4132 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4133 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4134 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4135 static HARD_REG_SET reload_reg_used_in_insn;
4136 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4137 static HARD_REG_SET reload_reg_used_in_other_addr;
4139 /* If reg is in use as a reload reg for any sort of reload. */
4140 static HARD_REG_SET reload_reg_used_at_all;
4142 /* If reg is use as an inherited reload. We just mark the first register
4144 static HARD_REG_SET reload_reg_used_for_inherit;
4146 /* Records which hard regs are used in any way, either as explicit use or
4147 by being allocated to a pseudo during any point of the current insn. */
4148 static HARD_REG_SET reg_used_in_insn;
4150 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4151 TYPE. MODE is used to indicate how many consecutive regs are
4155 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4156 enum machine_mode mode)
4158 unsigned int nregs = hard_regno_nregs[regno][mode];
4161 for (i = regno; i < nregs + regno; i++)
4166 SET_HARD_REG_BIT (reload_reg_used, i);
4169 case RELOAD_FOR_INPUT_ADDRESS:
4170 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4173 case RELOAD_FOR_INPADDR_ADDRESS:
4174 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4177 case RELOAD_FOR_OUTPUT_ADDRESS:
4178 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4181 case RELOAD_FOR_OUTADDR_ADDRESS:
4182 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4185 case RELOAD_FOR_OPERAND_ADDRESS:
4186 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4189 case RELOAD_FOR_OPADDR_ADDR:
4190 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4193 case RELOAD_FOR_OTHER_ADDRESS:
4194 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4197 case RELOAD_FOR_INPUT:
4198 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4201 case RELOAD_FOR_OUTPUT:
4202 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4205 case RELOAD_FOR_INSN:
4206 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4210 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4214 /* Similarly, but show REGNO is no longer in use for a reload. */
4217 clear_reload_reg_in_use (unsigned int regno, int opnum,
4218 enum reload_type type, enum machine_mode mode)
4220 unsigned int nregs = hard_regno_nregs[regno][mode];
4221 unsigned int start_regno, end_regno, r;
4223 /* A complication is that for some reload types, inheritance might
4224 allow multiple reloads of the same types to share a reload register.
4225 We set check_opnum if we have to check only reloads with the same
4226 operand number, and check_any if we have to check all reloads. */
4227 int check_opnum = 0;
4229 HARD_REG_SET *used_in_set;
4234 used_in_set = &reload_reg_used;
4237 case RELOAD_FOR_INPUT_ADDRESS:
4238 used_in_set = &reload_reg_used_in_input_addr[opnum];
4241 case RELOAD_FOR_INPADDR_ADDRESS:
4243 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4246 case RELOAD_FOR_OUTPUT_ADDRESS:
4247 used_in_set = &reload_reg_used_in_output_addr[opnum];
4250 case RELOAD_FOR_OUTADDR_ADDRESS:
4252 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4255 case RELOAD_FOR_OPERAND_ADDRESS:
4256 used_in_set = &reload_reg_used_in_op_addr;
4259 case RELOAD_FOR_OPADDR_ADDR:
4261 used_in_set = &reload_reg_used_in_op_addr_reload;
4264 case RELOAD_FOR_OTHER_ADDRESS:
4265 used_in_set = &reload_reg_used_in_other_addr;
4269 case RELOAD_FOR_INPUT:
4270 used_in_set = &reload_reg_used_in_input[opnum];
4273 case RELOAD_FOR_OUTPUT:
4274 used_in_set = &reload_reg_used_in_output[opnum];
4277 case RELOAD_FOR_INSN:
4278 used_in_set = &reload_reg_used_in_insn;
4283 /* We resolve conflicts with remaining reloads of the same type by
4284 excluding the intervals of reload registers by them from the
4285 interval of freed reload registers. Since we only keep track of
4286 one set of interval bounds, we might have to exclude somewhat
4287 more than what would be necessary if we used a HARD_REG_SET here.
4288 But this should only happen very infrequently, so there should
4289 be no reason to worry about it. */
4291 start_regno = regno;
4292 end_regno = regno + nregs;
4293 if (check_opnum || check_any)
4295 for (i = n_reloads - 1; i >= 0; i--)
4297 if (rld[i].when_needed == type
4298 && (check_any || rld[i].opnum == opnum)
4301 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4302 unsigned int conflict_end
4304 + hard_regno_nregs[conflict_start][rld[i].mode]);
4306 /* If there is an overlap with the first to-be-freed register,
4307 adjust the interval start. */
4308 if (conflict_start <= start_regno && conflict_end > start_regno)
4309 start_regno = conflict_end;
4310 /* Otherwise, if there is a conflict with one of the other
4311 to-be-freed registers, adjust the interval end. */
4312 if (conflict_start > start_regno && conflict_start < end_regno)
4313 end_regno = conflict_start;
4318 for (r = start_regno; r < end_regno; r++)
4319 CLEAR_HARD_REG_BIT (*used_in_set, r);
4322 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4323 specified by OPNUM and TYPE. */
4326 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4330 /* In use for a RELOAD_OTHER means it's not available for anything. */
4331 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4332 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4338 /* In use for anything means we can't use it for RELOAD_OTHER. */
4339 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4340 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4341 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4342 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4345 for (i = 0; i < reload_n_operands; i++)
4346 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4347 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4348 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4349 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4350 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4351 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4356 case RELOAD_FOR_INPUT:
4357 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4358 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4361 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4364 /* If it is used for some other input, can't use it. */
4365 for (i = 0; i < reload_n_operands; i++)
4366 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4369 /* If it is used in a later operand's address, can't use it. */
4370 for (i = opnum + 1; i < reload_n_operands; i++)
4371 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4372 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4377 case RELOAD_FOR_INPUT_ADDRESS:
4378 /* Can't use a register if it is used for an input address for this
4379 operand or used as an input in an earlier one. */
4380 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4381 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4384 for (i = 0; i < opnum; i++)
4385 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4390 case RELOAD_FOR_INPADDR_ADDRESS:
4391 /* Can't use a register if it is used for an input address
4392 for this operand or used as an input in an earlier
4394 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4397 for (i = 0; i < opnum; i++)
4398 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4403 case RELOAD_FOR_OUTPUT_ADDRESS:
4404 /* Can't use a register if it is used for an output address for this
4405 operand or used as an output in this or a later operand. Note
4406 that multiple output operands are emitted in reverse order, so
4407 the conflicting ones are those with lower indices. */
4408 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4411 for (i = 0; i <= opnum; i++)
4412 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4417 case RELOAD_FOR_OUTADDR_ADDRESS:
4418 /* Can't use a register if it is used for an output address
4419 for this operand or used as an output in this or a
4420 later operand. Note that multiple output operands are
4421 emitted in reverse order, so the conflicting ones are
4422 those with lower indices. */
4423 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4426 for (i = 0; i <= opnum; i++)
4427 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4432 case RELOAD_FOR_OPERAND_ADDRESS:
4433 for (i = 0; i < reload_n_operands; i++)
4434 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4437 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4438 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4440 case RELOAD_FOR_OPADDR_ADDR:
4441 for (i = 0; i < reload_n_operands; i++)
4442 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4445 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4447 case RELOAD_FOR_OUTPUT:
4448 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4449 outputs, or an operand address for this or an earlier output.
4450 Note that multiple output operands are emitted in reverse order,
4451 so the conflicting ones are those with higher indices. */
4452 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4455 for (i = 0; i < reload_n_operands; i++)
4456 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4459 for (i = opnum; i < reload_n_operands; i++)
4460 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4461 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4466 case RELOAD_FOR_INSN:
4467 for (i = 0; i < reload_n_operands; i++)
4468 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4469 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4472 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4473 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4475 case RELOAD_FOR_OTHER_ADDRESS:
4476 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4483 /* Return 1 if the value in reload reg REGNO, as used by a reload
4484 needed for the part of the insn specified by OPNUM and TYPE,
4485 is still available in REGNO at the end of the insn.
4487 We can assume that the reload reg was already tested for availability
4488 at the time it is needed, and we should not check this again,
4489 in case the reg has already been marked in use. */
4492 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4499 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4500 its value must reach the end. */
4503 /* If this use is for part of the insn,
4504 its value reaches if no subsequent part uses the same register.
4505 Just like the above function, don't try to do this with lots
4508 case RELOAD_FOR_OTHER_ADDRESS:
4509 /* Here we check for everything else, since these don't conflict
4510 with anything else and everything comes later. */
4512 for (i = 0; i < reload_n_operands; i++)
4513 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4514 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4515 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4516 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4517 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4518 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4521 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4522 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4523 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4524 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4526 case RELOAD_FOR_INPUT_ADDRESS:
4527 case RELOAD_FOR_INPADDR_ADDRESS:
4528 /* Similar, except that we check only for this and subsequent inputs
4529 and the address of only subsequent inputs and we do not need
4530 to check for RELOAD_OTHER objects since they are known not to
4533 for (i = opnum; i < reload_n_operands; i++)
4534 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4537 for (i = opnum + 1; i < reload_n_operands; i++)
4538 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4539 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4542 for (i = 0; i < reload_n_operands; i++)
4543 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4544 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4545 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4548 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4551 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4552 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4553 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4555 case RELOAD_FOR_INPUT:
4556 /* Similar to input address, except we start at the next operand for
4557 both input and input address and we do not check for
4558 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4561 for (i = opnum + 1; i < reload_n_operands; i++)
4562 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4563 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4564 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4567 /* ... fall through ... */
4569 case RELOAD_FOR_OPERAND_ADDRESS:
4570 /* Check outputs and their addresses. */
4572 for (i = 0; i < reload_n_operands; i++)
4573 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4574 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4575 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4578 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4580 case RELOAD_FOR_OPADDR_ADDR:
4581 for (i = 0; i < reload_n_operands; i++)
4582 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4583 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4584 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4587 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4588 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4589 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4591 case RELOAD_FOR_INSN:
4592 /* These conflict with other outputs with RELOAD_OTHER. So
4593 we need only check for output addresses. */
4595 opnum = reload_n_operands;
4597 /* ... fall through ... */
4599 case RELOAD_FOR_OUTPUT:
4600 case RELOAD_FOR_OUTPUT_ADDRESS:
4601 case RELOAD_FOR_OUTADDR_ADDRESS:
4602 /* We already know these can't conflict with a later output. So the
4603 only thing to check are later output addresses.
4604 Note that multiple output operands are emitted in reverse order,
4605 so the conflicting ones are those with lower indices. */
4606 for (i = 0; i < opnum; i++)
4607 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4608 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4618 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4621 This function uses the same algorithm as reload_reg_free_p above. */
4624 reloads_conflict (int r1, int r2)
4626 enum reload_type r1_type = rld[r1].when_needed;
4627 enum reload_type r2_type = rld[r2].when_needed;
4628 int r1_opnum = rld[r1].opnum;
4629 int r2_opnum = rld[r2].opnum;
4631 /* RELOAD_OTHER conflicts with everything. */
4632 if (r2_type == RELOAD_OTHER)
4635 /* Otherwise, check conflicts differently for each type. */
4639 case RELOAD_FOR_INPUT:
4640 return (r2_type == RELOAD_FOR_INSN
4641 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4642 || r2_type == RELOAD_FOR_OPADDR_ADDR
4643 || r2_type == RELOAD_FOR_INPUT
4644 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4645 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4646 && r2_opnum > r1_opnum));
4648 case RELOAD_FOR_INPUT_ADDRESS:
4649 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4650 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4652 case RELOAD_FOR_INPADDR_ADDRESS:
4653 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4654 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4656 case RELOAD_FOR_OUTPUT_ADDRESS:
4657 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4658 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4660 case RELOAD_FOR_OUTADDR_ADDRESS:
4661 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4662 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4664 case RELOAD_FOR_OPERAND_ADDRESS:
4665 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4666 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4668 case RELOAD_FOR_OPADDR_ADDR:
4669 return (r2_type == RELOAD_FOR_INPUT
4670 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4672 case RELOAD_FOR_OUTPUT:
4673 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4674 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4675 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4676 && r2_opnum >= r1_opnum));
4678 case RELOAD_FOR_INSN:
4679 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4680 || r2_type == RELOAD_FOR_INSN
4681 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4683 case RELOAD_FOR_OTHER_ADDRESS:
4684 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4694 /* Indexed by reload number, 1 if incoming value
4695 inherited from previous insns. */
4696 static char reload_inherited[MAX_RELOADS];
4698 /* For an inherited reload, this is the insn the reload was inherited from,
4699 if we know it. Otherwise, this is 0. */
4700 static rtx reload_inheritance_insn[MAX_RELOADS];
4702 /* If nonzero, this is a place to get the value of the reload,
4703 rather than using reload_in. */
4704 static rtx reload_override_in[MAX_RELOADS];
4706 /* For each reload, the hard register number of the register used,
4707 or -1 if we did not need a register for this reload. */
4708 static int reload_spill_index[MAX_RELOADS];
4710 /* Subroutine of free_for_value_p, used to check a single register.
4711 START_REGNO is the starting regno of the full reload register
4712 (possibly comprising multiple hard registers) that we are considering. */
4715 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4716 enum reload_type type, rtx value, rtx out,
4717 int reloadnum, int ignore_address_reloads)
4720 /* Set if we see an input reload that must not share its reload register
4721 with any new earlyclobber, but might otherwise share the reload
4722 register with an output or input-output reload. */
4723 int check_earlyclobber = 0;
4727 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4730 if (out == const0_rtx)
4736 /* We use some pseudo 'time' value to check if the lifetimes of the
4737 new register use would overlap with the one of a previous reload
4738 that is not read-only or uses a different value.
4739 The 'time' used doesn't have to be linear in any shape or form, just
4741 Some reload types use different 'buckets' for each operand.
4742 So there are MAX_RECOG_OPERANDS different time values for each
4744 We compute TIME1 as the time when the register for the prospective
4745 new reload ceases to be live, and TIME2 for each existing
4746 reload as the time when that the reload register of that reload
4748 Where there is little to be gained by exact lifetime calculations,
4749 we just make conservative assumptions, i.e. a longer lifetime;
4750 this is done in the 'default:' cases. */
4753 case RELOAD_FOR_OTHER_ADDRESS:
4754 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4755 time1 = copy ? 0 : 1;
4758 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4760 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4761 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4762 respectively, to the time values for these, we get distinct time
4763 values. To get distinct time values for each operand, we have to
4764 multiply opnum by at least three. We round that up to four because
4765 multiply by four is often cheaper. */
4766 case RELOAD_FOR_INPADDR_ADDRESS:
4767 time1 = opnum * 4 + 2;
4769 case RELOAD_FOR_INPUT_ADDRESS:
4770 time1 = opnum * 4 + 3;
4772 case RELOAD_FOR_INPUT:
4773 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4774 executes (inclusive). */
4775 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4777 case RELOAD_FOR_OPADDR_ADDR:
4779 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4780 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4782 case RELOAD_FOR_OPERAND_ADDRESS:
4783 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4785 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4787 case RELOAD_FOR_OUTADDR_ADDRESS:
4788 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4790 case RELOAD_FOR_OUTPUT_ADDRESS:
4791 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4794 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4797 for (i = 0; i < n_reloads; i++)
4799 rtx reg = rld[i].reg_rtx;
4800 if (reg && REG_P (reg)
4801 && ((unsigned) regno - true_regnum (reg)
4802 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
4805 rtx other_input = rld[i].in;
4807 /* If the other reload loads the same input value, that
4808 will not cause a conflict only if it's loading it into
4809 the same register. */
4810 if (true_regnum (reg) != start_regno)
4811 other_input = NULL_RTX;
4812 if (! other_input || ! rtx_equal_p (other_input, value)
4813 || rld[i].out || out)
4816 switch (rld[i].when_needed)
4818 case RELOAD_FOR_OTHER_ADDRESS:
4821 case RELOAD_FOR_INPADDR_ADDRESS:
4822 /* find_reloads makes sure that a
4823 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4824 by at most one - the first -
4825 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4826 address reload is inherited, the address address reload
4827 goes away, so we can ignore this conflict. */
4828 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4829 && ignore_address_reloads
4830 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4831 Then the address address is still needed to store
4832 back the new address. */
4833 && ! rld[reloadnum].out)
4835 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4836 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4838 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4839 && ignore_address_reloads
4840 /* Unless we are reloading an auto_inc expression. */
4841 && ! rld[reloadnum].out)
4843 time2 = rld[i].opnum * 4 + 2;
4845 case RELOAD_FOR_INPUT_ADDRESS:
4846 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4847 && ignore_address_reloads
4848 && ! rld[reloadnum].out)
4850 time2 = rld[i].opnum * 4 + 3;
4852 case RELOAD_FOR_INPUT:
4853 time2 = rld[i].opnum * 4 + 4;
4854 check_earlyclobber = 1;
4856 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4857 == MAX_RECOG_OPERAND * 4 */
4858 case RELOAD_FOR_OPADDR_ADDR:
4859 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4860 && ignore_address_reloads
4861 && ! rld[reloadnum].out)
4863 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4865 case RELOAD_FOR_OPERAND_ADDRESS:
4866 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4867 check_earlyclobber = 1;
4869 case RELOAD_FOR_INSN:
4870 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4872 case RELOAD_FOR_OUTPUT:
4873 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4874 instruction is executed. */
4875 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4877 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4878 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4880 case RELOAD_FOR_OUTADDR_ADDRESS:
4881 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4882 && ignore_address_reloads
4883 && ! rld[reloadnum].out)
4885 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4887 case RELOAD_FOR_OUTPUT_ADDRESS:
4888 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4891 /* If there is no conflict in the input part, handle this
4892 like an output reload. */
4893 if (! rld[i].in || rtx_equal_p (other_input, value))
4895 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4896 /* Earlyclobbered outputs must conflict with inputs. */
4897 if (earlyclobber_operand_p (rld[i].out))
4898 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4903 /* RELOAD_OTHER might be live beyond instruction execution,
4904 but this is not obvious when we set time2 = 1. So check
4905 here if there might be a problem with the new reload
4906 clobbering the register used by the RELOAD_OTHER. */
4914 && (! rld[i].in || rld[i].out
4915 || ! rtx_equal_p (other_input, value)))
4916 || (out && rld[reloadnum].out_reg
4917 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4923 /* Earlyclobbered outputs must conflict with inputs. */
4924 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4930 /* Return 1 if the value in reload reg REGNO, as used by a reload
4931 needed for the part of the insn specified by OPNUM and TYPE,
4932 may be used to load VALUE into it.
4934 MODE is the mode in which the register is used, this is needed to
4935 determine how many hard regs to test.
4937 Other read-only reloads with the same value do not conflict
4938 unless OUT is nonzero and these other reloads have to live while
4939 output reloads live.
4940 If OUT is CONST0_RTX, this is a special case: it means that the
4941 test should not be for using register REGNO as reload register, but
4942 for copying from register REGNO into the reload register.
4944 RELOADNUM is the number of the reload we want to load this value for;
4945 a reload does not conflict with itself.
4947 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4948 reloads that load an address for the very reload we are considering.
4950 The caller has to make sure that there is no conflict with the return
4954 free_for_value_p (int regno, enum machine_mode mode, int opnum,
4955 enum reload_type type, rtx value, rtx out, int reloadnum,
4956 int ignore_address_reloads)
4958 int nregs = hard_regno_nregs[regno][mode];
4960 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
4961 value, out, reloadnum,
4962 ignore_address_reloads))
4967 /* Return nonzero if the rtx X is invariant over the current function. */
4968 /* ??? Actually, the places where we use this expect exactly what is
4969 tested here, and not everything that is function invariant. In
4970 particular, the frame pointer and arg pointer are special cased;
4971 pic_offset_table_rtx is not, and we must not spill these things to
4975 function_invariant_p (rtx x)
4979 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4981 if (GET_CODE (x) == PLUS
4982 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
4983 && CONSTANT_P (XEXP (x, 1)))
4988 /* Determine whether the reload reg X overlaps any rtx'es used for
4989 overriding inheritance. Return nonzero if so. */
4992 conflicts_with_override (rtx x)
4995 for (i = 0; i < n_reloads; i++)
4996 if (reload_override_in[i]
4997 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5002 /* Give an error message saying we failed to find a reload for INSN,
5003 and clear out reload R. */
5005 failed_reload (rtx insn, int r)
5007 if (asm_noperands (PATTERN (insn)) < 0)
5008 /* It's the compiler's fault. */
5009 fatal_insn ("could not find a spill register", insn);
5011 /* It's the user's fault; the operand's mode and constraint
5012 don't match. Disable this reload so we don't crash in final. */
5013 error_for_asm (insn,
5014 "%<asm%> operand constraint incompatible with operand size");
5018 rld[r].optional = 1;
5019 rld[r].secondary_p = 1;
5022 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5023 for reload R. If it's valid, get an rtx for it. Return nonzero if
5026 set_reload_reg (int i, int r)
5029 rtx reg = spill_reg_rtx[i];
5031 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5032 spill_reg_rtx[i] = reg
5033 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5035 regno = true_regnum (reg);
5037 /* Detect when the reload reg can't hold the reload mode.
5038 This used to be one `if', but Sequent compiler can't handle that. */
5039 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5041 enum machine_mode test_mode = VOIDmode;
5043 test_mode = GET_MODE (rld[r].in);
5044 /* If rld[r].in has VOIDmode, it means we will load it
5045 in whatever mode the reload reg has: to wit, rld[r].mode.
5046 We have already tested that for validity. */
5047 /* Aside from that, we need to test that the expressions
5048 to reload from or into have modes which are valid for this
5049 reload register. Otherwise the reload insns would be invalid. */
5050 if (! (rld[r].in != 0 && test_mode != VOIDmode
5051 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5052 if (! (rld[r].out != 0
5053 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5055 /* The reg is OK. */
5058 /* Mark as in use for this insn the reload regs we use
5060 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5061 rld[r].when_needed, rld[r].mode);
5063 rld[r].reg_rtx = reg;
5064 reload_spill_index[r] = spill_regs[i];
5071 /* Find a spill register to use as a reload register for reload R.
5072 LAST_RELOAD is nonzero if this is the last reload for the insn being
5075 Set rld[R].reg_rtx to the register allocated.
5077 We return 1 if successful, or 0 if we couldn't find a spill reg and
5078 we didn't change anything. */
5081 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5086 /* If we put this reload ahead, thinking it is a group,
5087 then insist on finding a group. Otherwise we can grab a
5088 reg that some other reload needs.
5089 (That can happen when we have a 68000 DATA_OR_FP_REG
5090 which is a group of data regs or one fp reg.)
5091 We need not be so restrictive if there are no more reloads
5094 ??? Really it would be nicer to have smarter handling
5095 for that kind of reg class, where a problem like this is normal.
5096 Perhaps those classes should be avoided for reloading
5097 by use of more alternatives. */
5099 int force_group = rld[r].nregs > 1 && ! last_reload;
5101 /* If we want a single register and haven't yet found one,
5102 take any reg in the right class and not in use.
5103 If we want a consecutive group, here is where we look for it.
5105 We use two passes so we can first look for reload regs to
5106 reuse, which are already in use for other reloads in this insn,
5107 and only then use additional registers.
5108 I think that maximizing reuse is needed to make sure we don't
5109 run out of reload regs. Suppose we have three reloads, and
5110 reloads A and B can share regs. These need two regs.
5111 Suppose A and B are given different regs.
5112 That leaves none for C. */
5113 for (pass = 0; pass < 2; pass++)
5115 /* I is the index in spill_regs.
5116 We advance it round-robin between insns to use all spill regs
5117 equally, so that inherited reloads have a chance
5118 of leapfrogging each other. */
5122 for (count = 0; count < n_spills; count++)
5124 int class = (int) rld[r].class;
5130 regnum = spill_regs[i];
5132 if ((reload_reg_free_p (regnum, rld[r].opnum,
5135 /* We check reload_reg_used to make sure we
5136 don't clobber the return register. */
5137 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5138 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5139 rld[r].when_needed, rld[r].in,
5141 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5142 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5143 /* Look first for regs to share, then for unshared. But
5144 don't share regs used for inherited reloads; they are
5145 the ones we want to preserve. */
5147 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5149 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5152 int nr = hard_regno_nregs[regnum][rld[r].mode];
5153 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5154 (on 68000) got us two FP regs. If NR is 1,
5155 we would reject both of them. */
5158 /* If we need only one reg, we have already won. */
5161 /* But reject a single reg if we demand a group. */
5166 /* Otherwise check that as many consecutive regs as we need
5167 are available here. */
5170 int regno = regnum + nr - 1;
5171 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5172 && spill_reg_order[regno] >= 0
5173 && reload_reg_free_p (regno, rld[r].opnum,
5174 rld[r].when_needed)))
5183 /* If we found something on pass 1, omit pass 2. */
5184 if (count < n_spills)
5188 /* We should have found a spill register by now. */
5189 if (count >= n_spills)
5192 /* I is the index in SPILL_REG_RTX of the reload register we are to
5193 allocate. Get an rtx for it and find its register number. */
5195 return set_reload_reg (i, r);
5198 /* Initialize all the tables needed to allocate reload registers.
5199 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5200 is the array we use to restore the reg_rtx field for every reload. */
5203 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5207 for (i = 0; i < n_reloads; i++)
5208 rld[i].reg_rtx = save_reload_reg_rtx[i];
5210 memset (reload_inherited, 0, MAX_RELOADS);
5211 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5212 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5214 CLEAR_HARD_REG_SET (reload_reg_used);
5215 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5216 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5217 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5218 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5219 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5221 CLEAR_HARD_REG_SET (reg_used_in_insn);
5224 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5225 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5226 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5227 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5228 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5229 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5232 for (i = 0; i < reload_n_operands; i++)
5234 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5235 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5236 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5237 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5238 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5239 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5242 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5244 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5246 for (i = 0; i < n_reloads; i++)
5247 /* If we have already decided to use a certain register,
5248 don't use it in another way. */
5250 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5251 rld[i].when_needed, rld[i].mode);
5254 /* Assign hard reg targets for the pseudo-registers we must reload
5255 into hard regs for this insn.
5256 Also output the instructions to copy them in and out of the hard regs.
5258 For machines with register classes, we are responsible for
5259 finding a reload reg in the proper class. */
5262 choose_reload_regs (struct insn_chain *chain)
5264 rtx insn = chain->insn;
5266 unsigned int max_group_size = 1;
5267 enum reg_class group_class = NO_REGS;
5268 int pass, win, inheritance;
5270 rtx save_reload_reg_rtx[MAX_RELOADS];
5272 /* In order to be certain of getting the registers we need,
5273 we must sort the reloads into order of increasing register class.
5274 Then our grabbing of reload registers will parallel the process
5275 that provided the reload registers.
5277 Also note whether any of the reloads wants a consecutive group of regs.
5278 If so, record the maximum size of the group desired and what
5279 register class contains all the groups needed by this insn. */
5281 for (j = 0; j < n_reloads; j++)
5283 reload_order[j] = j;
5284 reload_spill_index[j] = -1;
5286 if (rld[j].nregs > 1)
5288 max_group_size = MAX (rld[j].nregs, max_group_size);
5290 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5293 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5297 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5299 /* If -O, try first with inheritance, then turning it off.
5300 If not -O, don't do inheritance.
5301 Using inheritance when not optimizing leads to paradoxes
5302 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5303 because one side of the comparison might be inherited. */
5305 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5307 choose_reload_regs_init (chain, save_reload_reg_rtx);
5309 /* Process the reloads in order of preference just found.
5310 Beyond this point, subregs can be found in reload_reg_rtx.
5312 This used to look for an existing reloaded home for all of the
5313 reloads, and only then perform any new reloads. But that could lose
5314 if the reloads were done out of reg-class order because a later
5315 reload with a looser constraint might have an old home in a register
5316 needed by an earlier reload with a tighter constraint.
5318 To solve this, we make two passes over the reloads, in the order
5319 described above. In the first pass we try to inherit a reload
5320 from a previous insn. If there is a later reload that needs a
5321 class that is a proper subset of the class being processed, we must
5322 also allocate a spill register during the first pass.
5324 Then make a second pass over the reloads to allocate any reloads
5325 that haven't been given registers yet. */
5327 for (j = 0; j < n_reloads; j++)
5329 int r = reload_order[j];
5330 rtx search_equiv = NULL_RTX;
5332 /* Ignore reloads that got marked inoperative. */
5333 if (rld[r].out == 0 && rld[r].in == 0
5334 && ! rld[r].secondary_p)
5337 /* If find_reloads chose to use reload_in or reload_out as a reload
5338 register, we don't need to chose one. Otherwise, try even if it
5339 found one since we might save an insn if we find the value lying
5341 Try also when reload_in is a pseudo without a hard reg. */
5342 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5343 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5344 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5345 && !MEM_P (rld[r].in)
5346 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5349 #if 0 /* No longer needed for correct operation.
5350 It might give better code, or might not; worth an experiment? */
5351 /* If this is an optional reload, we can't inherit from earlier insns
5352 until we are sure that any non-optional reloads have been allocated.
5353 The following code takes advantage of the fact that optional reloads
5354 are at the end of reload_order. */
5355 if (rld[r].optional != 0)
5356 for (i = 0; i < j; i++)
5357 if ((rld[reload_order[i]].out != 0
5358 || rld[reload_order[i]].in != 0
5359 || rld[reload_order[i]].secondary_p)
5360 && ! rld[reload_order[i]].optional
5361 && rld[reload_order[i]].reg_rtx == 0)
5362 allocate_reload_reg (chain, reload_order[i], 0);
5365 /* First see if this pseudo is already available as reloaded
5366 for a previous insn. We cannot try to inherit for reloads
5367 that are smaller than the maximum number of registers needed
5368 for groups unless the register we would allocate cannot be used
5371 We could check here to see if this is a secondary reload for
5372 an object that is already in a register of the desired class.
5373 This would avoid the need for the secondary reload register.
5374 But this is complex because we can't easily determine what
5375 objects might want to be loaded via this reload. So let a
5376 register be allocated here. In `emit_reload_insns' we suppress
5377 one of the loads in the case described above. */
5383 enum machine_mode mode = VOIDmode;
5387 else if (REG_P (rld[r].in))
5389 regno = REGNO (rld[r].in);
5390 mode = GET_MODE (rld[r].in);
5392 else if (REG_P (rld[r].in_reg))
5394 regno = REGNO (rld[r].in_reg);
5395 mode = GET_MODE (rld[r].in_reg);
5397 else if (GET_CODE (rld[r].in_reg) == SUBREG
5398 && REG_P (SUBREG_REG (rld[r].in_reg)))
5400 byte = SUBREG_BYTE (rld[r].in_reg);
5401 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5402 if (regno < FIRST_PSEUDO_REGISTER)
5403 regno = subreg_regno (rld[r].in_reg);
5404 mode = GET_MODE (rld[r].in_reg);
5407 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5408 || GET_CODE (rld[r].in_reg) == PRE_DEC
5409 || GET_CODE (rld[r].in_reg) == POST_INC
5410 || GET_CODE (rld[r].in_reg) == POST_DEC)
5411 && REG_P (XEXP (rld[r].in_reg, 0)))
5413 regno = REGNO (XEXP (rld[r].in_reg, 0));
5414 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5415 rld[r].out = rld[r].in;
5419 /* This won't work, since REGNO can be a pseudo reg number.
5420 Also, it takes much more hair to keep track of all the things
5421 that can invalidate an inherited reload of part of a pseudoreg. */
5422 else if (GET_CODE (rld[r].in) == SUBREG
5423 && REG_P (SUBREG_REG (rld[r].in)))
5424 regno = subreg_regno (rld[r].in);
5427 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5429 enum reg_class class = rld[r].class, last_class;
5430 rtx last_reg = reg_last_reload_reg[regno];
5431 enum machine_mode need_mode;
5433 i = REGNO (last_reg);
5434 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5435 last_class = REGNO_REG_CLASS (i);
5441 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
5442 + byte * BITS_PER_UNIT,
5443 GET_MODE_CLASS (mode));
5445 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5446 >= GET_MODE_SIZE (need_mode))
5447 #ifdef CANNOT_CHANGE_MODE_CLASS
5448 /* Verify that the register in "i" can be obtained
5450 && !REG_CANNOT_CHANGE_MODE_P (REGNO (last_reg),
5451 GET_MODE (last_reg),
5454 && reg_reloaded_contents[i] == regno
5455 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5456 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5457 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5458 /* Even if we can't use this register as a reload
5459 register, we might use it for reload_override_in,
5460 if copying it to the desired class is cheap
5462 || ((REGISTER_MOVE_COST (mode, last_class, class)
5463 < MEMORY_MOVE_COST (mode, class, 1))
5464 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5465 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5469 #ifdef SECONDARY_MEMORY_NEEDED
5470 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5475 && (rld[r].nregs == max_group_size
5476 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5478 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5479 rld[r].when_needed, rld[r].in,
5482 /* If a group is needed, verify that all the subsequent
5483 registers still have their values intact. */
5484 int nr = hard_regno_nregs[i][rld[r].mode];
5487 for (k = 1; k < nr; k++)
5488 if (reg_reloaded_contents[i + k] != regno
5489 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5497 last_reg = (GET_MODE (last_reg) == mode
5498 ? last_reg : gen_rtx_REG (mode, i));
5501 for (k = 0; k < nr; k++)
5502 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5505 /* We found a register that contains the
5506 value we need. If this register is the
5507 same as an `earlyclobber' operand of the
5508 current insn, just mark it as a place to
5509 reload from since we can't use it as the
5510 reload register itself. */
5512 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5513 if (reg_overlap_mentioned_for_reload_p
5514 (reg_last_reload_reg[regno],
5515 reload_earlyclobbers[i1]))
5518 if (i1 != n_earlyclobbers
5519 || ! (free_for_value_p (i, rld[r].mode,
5521 rld[r].when_needed, rld[r].in,
5523 /* Don't use it if we'd clobber a pseudo reg. */
5524 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5526 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5527 /* Don't clobber the frame pointer. */
5528 || (i == HARD_FRAME_POINTER_REGNUM
5529 && frame_pointer_needed
5531 /* Don't really use the inherited spill reg
5532 if we need it wider than we've got it. */
5533 || (GET_MODE_SIZE (rld[r].mode)
5534 > GET_MODE_SIZE (mode))
5537 /* If find_reloads chose reload_out as reload
5538 register, stay with it - that leaves the
5539 inherited register for subsequent reloads. */
5540 || (rld[r].out && rld[r].reg_rtx
5541 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5543 if (! rld[r].optional)
5545 reload_override_in[r] = last_reg;
5546 reload_inheritance_insn[r]
5547 = reg_reloaded_insn[i];
5553 /* We can use this as a reload reg. */
5554 /* Mark the register as in use for this part of
5556 mark_reload_reg_in_use (i,
5560 rld[r].reg_rtx = last_reg;
5561 reload_inherited[r] = 1;
5562 reload_inheritance_insn[r]
5563 = reg_reloaded_insn[i];
5564 reload_spill_index[r] = i;
5565 for (k = 0; k < nr; k++)
5566 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5574 /* Here's another way to see if the value is already lying around. */
5577 && ! reload_inherited[r]
5579 && (CONSTANT_P (rld[r].in)
5580 || GET_CODE (rld[r].in) == PLUS
5581 || REG_P (rld[r].in)
5582 || MEM_P (rld[r].in))
5583 && (rld[r].nregs == max_group_size
5584 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5585 search_equiv = rld[r].in;
5586 /* If this is an output reload from a simple move insn, look
5587 if an equivalence for the input is available. */
5588 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5590 rtx set = single_set (insn);
5593 && rtx_equal_p (rld[r].out, SET_DEST (set))
5594 && CONSTANT_P (SET_SRC (set)))
5595 search_equiv = SET_SRC (set);
5601 = find_equiv_reg (search_equiv, insn, rld[r].class,
5602 -1, NULL, 0, rld[r].mode);
5608 regno = REGNO (equiv);
5611 /* This must be a SUBREG of a hard register.
5612 Make a new REG since this might be used in an
5613 address and not all machines support SUBREGs
5615 gcc_assert (GET_CODE (equiv) == SUBREG);
5616 regno = subreg_regno (equiv);
5617 equiv = gen_rtx_REG (rld[r].mode, regno);
5618 /* If we choose EQUIV as the reload register, but the
5619 loop below decides to cancel the inheritance, we'll
5620 end up reloading EQUIV in rld[r].mode, not the mode
5621 it had originally. That isn't safe when EQUIV isn't
5622 available as a spill register since its value might
5623 still be live at this point. */
5624 for (i = regno; i < regno + (int) rld[r].nregs; i++)
5625 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
5630 /* If we found a spill reg, reject it unless it is free
5631 and of the desired class. */
5635 int bad_for_class = 0;
5636 int max_regno = regno + rld[r].nregs;
5638 for (i = regno; i < max_regno; i++)
5640 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5642 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5647 && ! free_for_value_p (regno, rld[r].mode,
5648 rld[r].opnum, rld[r].when_needed,
5649 rld[r].in, rld[r].out, r, 1))
5654 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5657 /* We found a register that contains the value we need.
5658 If this register is the same as an `earlyclobber' operand
5659 of the current insn, just mark it as a place to reload from
5660 since we can't use it as the reload register itself. */
5663 for (i = 0; i < n_earlyclobbers; i++)
5664 if (reg_overlap_mentioned_for_reload_p (equiv,
5665 reload_earlyclobbers[i]))
5667 if (! rld[r].optional)
5668 reload_override_in[r] = equiv;
5673 /* If the equiv register we have found is explicitly clobbered
5674 in the current insn, it depends on the reload type if we
5675 can use it, use it for reload_override_in, or not at all.
5676 In particular, we then can't use EQUIV for a
5677 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5681 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5682 switch (rld[r].when_needed)
5684 case RELOAD_FOR_OTHER_ADDRESS:
5685 case RELOAD_FOR_INPADDR_ADDRESS:
5686 case RELOAD_FOR_INPUT_ADDRESS:
5687 case RELOAD_FOR_OPADDR_ADDR:
5690 case RELOAD_FOR_INPUT:
5691 case RELOAD_FOR_OPERAND_ADDRESS:
5692 if (! rld[r].optional)
5693 reload_override_in[r] = equiv;
5699 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5700 switch (rld[r].when_needed)
5702 case RELOAD_FOR_OTHER_ADDRESS:
5703 case RELOAD_FOR_INPADDR_ADDRESS:
5704 case RELOAD_FOR_INPUT_ADDRESS:
5705 case RELOAD_FOR_OPADDR_ADDR:
5706 case RELOAD_FOR_OPERAND_ADDRESS:
5707 case RELOAD_FOR_INPUT:
5710 if (! rld[r].optional)
5711 reload_override_in[r] = equiv;
5719 /* If we found an equivalent reg, say no code need be generated
5720 to load it, and use it as our reload reg. */
5722 && (regno != HARD_FRAME_POINTER_REGNUM
5723 || !frame_pointer_needed))
5725 int nr = hard_regno_nregs[regno][rld[r].mode];
5727 rld[r].reg_rtx = equiv;
5728 reload_inherited[r] = 1;
5730 /* If reg_reloaded_valid is not set for this register,
5731 there might be a stale spill_reg_store lying around.
5732 We must clear it, since otherwise emit_reload_insns
5733 might delete the store. */
5734 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5735 spill_reg_store[regno] = NULL_RTX;
5736 /* If any of the hard registers in EQUIV are spill
5737 registers, mark them as in use for this insn. */
5738 for (k = 0; k < nr; k++)
5740 i = spill_reg_order[regno + k];
5743 mark_reload_reg_in_use (regno, rld[r].opnum,
5746 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5753 /* If we found a register to use already, or if this is an optional
5754 reload, we are done. */
5755 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5759 /* No longer needed for correct operation. Might or might
5760 not give better code on the average. Want to experiment? */
5762 /* See if there is a later reload that has a class different from our
5763 class that intersects our class or that requires less register
5764 than our reload. If so, we must allocate a register to this
5765 reload now, since that reload might inherit a previous reload
5766 and take the only available register in our class. Don't do this
5767 for optional reloads since they will force all previous reloads
5768 to be allocated. Also don't do this for reloads that have been
5771 for (i = j + 1; i < n_reloads; i++)
5773 int s = reload_order[i];
5775 if ((rld[s].in == 0 && rld[s].out == 0
5776 && ! rld[s].secondary_p)
5780 if ((rld[s].class != rld[r].class
5781 && reg_classes_intersect_p (rld[r].class,
5783 || rld[s].nregs < rld[r].nregs)
5790 allocate_reload_reg (chain, r, j == n_reloads - 1);
5794 /* Now allocate reload registers for anything non-optional that
5795 didn't get one yet. */
5796 for (j = 0; j < n_reloads; j++)
5798 int r = reload_order[j];
5800 /* Ignore reloads that got marked inoperative. */
5801 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5804 /* Skip reloads that already have a register allocated or are
5806 if (rld[r].reg_rtx != 0 || rld[r].optional)
5809 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5813 /* If that loop got all the way, we have won. */
5820 /* Loop around and try without any inheritance. */
5825 /* First undo everything done by the failed attempt
5826 to allocate with inheritance. */
5827 choose_reload_regs_init (chain, save_reload_reg_rtx);
5829 /* Some sanity tests to verify that the reloads found in the first
5830 pass are identical to the ones we have now. */
5831 gcc_assert (chain->n_reloads == n_reloads);
5833 for (i = 0; i < n_reloads; i++)
5835 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5837 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
5838 for (j = 0; j < n_spills; j++)
5839 if (spill_regs[j] == chain->rld[i].regno)
5840 if (! set_reload_reg (j, i))
5841 failed_reload (chain->insn, i);
5845 /* If we thought we could inherit a reload, because it seemed that
5846 nothing else wanted the same reload register earlier in the insn,
5847 verify that assumption, now that all reloads have been assigned.
5848 Likewise for reloads where reload_override_in has been set. */
5850 /* If doing expensive optimizations, do one preliminary pass that doesn't
5851 cancel any inheritance, but removes reloads that have been needed only
5852 for reloads that we know can be inherited. */
5853 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5855 for (j = 0; j < n_reloads; j++)
5857 int r = reload_order[j];
5859 if (reload_inherited[r] && rld[r].reg_rtx)
5860 check_reg = rld[r].reg_rtx;
5861 else if (reload_override_in[r]
5862 && (REG_P (reload_override_in[r])
5863 || GET_CODE (reload_override_in[r]) == SUBREG))
5864 check_reg = reload_override_in[r];
5867 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5868 rld[r].opnum, rld[r].when_needed, rld[r].in,
5869 (reload_inherited[r]
5870 ? rld[r].out : const0_rtx),
5875 reload_inherited[r] = 0;
5876 reload_override_in[r] = 0;
5878 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5879 reload_override_in, then we do not need its related
5880 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5881 likewise for other reload types.
5882 We handle this by removing a reload when its only replacement
5883 is mentioned in reload_in of the reload we are going to inherit.
5884 A special case are auto_inc expressions; even if the input is
5885 inherited, we still need the address for the output. We can
5886 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5887 If we succeeded removing some reload and we are doing a preliminary
5888 pass just to remove such reloads, make another pass, since the
5889 removal of one reload might allow us to inherit another one. */
5891 && rld[r].out != rld[r].in
5892 && remove_address_replacements (rld[r].in) && pass)
5897 /* Now that reload_override_in is known valid,
5898 actually override reload_in. */
5899 for (j = 0; j < n_reloads; j++)
5900 if (reload_override_in[j])
5901 rld[j].in = reload_override_in[j];
5903 /* If this reload won't be done because it has been canceled or is
5904 optional and not inherited, clear reload_reg_rtx so other
5905 routines (such as subst_reloads) don't get confused. */
5906 for (j = 0; j < n_reloads; j++)
5907 if (rld[j].reg_rtx != 0
5908 && ((rld[j].optional && ! reload_inherited[j])
5909 || (rld[j].in == 0 && rld[j].out == 0
5910 && ! rld[j].secondary_p)))
5912 int regno = true_regnum (rld[j].reg_rtx);
5914 if (spill_reg_order[regno] >= 0)
5915 clear_reload_reg_in_use (regno, rld[j].opnum,
5916 rld[j].when_needed, rld[j].mode);
5918 reload_spill_index[j] = -1;
5921 /* Record which pseudos and which spill regs have output reloads. */
5922 for (j = 0; j < n_reloads; j++)
5924 int r = reload_order[j];
5926 i = reload_spill_index[r];
5928 /* I is nonneg if this reload uses a register.
5929 If rld[r].reg_rtx is 0, this is an optional reload
5930 that we opted to ignore. */
5931 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
5932 && rld[r].reg_rtx != 0)
5934 int nregno = REGNO (rld[r].out_reg);
5937 if (nregno < FIRST_PSEUDO_REGISTER)
5938 nr = hard_regno_nregs[nregno][rld[r].mode];
5941 reg_has_output_reload[nregno + nr] = 1;
5945 nr = hard_regno_nregs[i][rld[r].mode];
5947 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5950 gcc_assert (rld[r].when_needed == RELOAD_OTHER
5951 || rld[r].when_needed == RELOAD_FOR_OUTPUT
5952 || rld[r].when_needed == RELOAD_FOR_INSN);
5957 /* Deallocate the reload register for reload R. This is called from
5958 remove_address_replacements. */
5961 deallocate_reload_reg (int r)
5965 if (! rld[r].reg_rtx)
5967 regno = true_regnum (rld[r].reg_rtx);
5969 if (spill_reg_order[regno] >= 0)
5970 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5972 reload_spill_index[r] = -1;
5975 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
5976 reloads of the same item for fear that we might not have enough reload
5977 registers. However, normally they will get the same reload register
5978 and hence actually need not be loaded twice.
5980 Here we check for the most common case of this phenomenon: when we have
5981 a number of reloads for the same object, each of which were allocated
5982 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5983 reload, and is not modified in the insn itself. If we find such,
5984 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5985 This will not increase the number of spill registers needed and will
5986 prevent redundant code. */
5989 merge_assigned_reloads (rtx insn)
5993 /* Scan all the reloads looking for ones that only load values and
5994 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5995 assigned and not modified by INSN. */
5997 for (i = 0; i < n_reloads; i++)
5999 int conflicting_input = 0;
6000 int max_input_address_opnum = -1;
6001 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6003 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6004 || rld[i].out != 0 || rld[i].reg_rtx == 0
6005 || reg_set_p (rld[i].reg_rtx, insn))
6008 /* Look at all other reloads. Ensure that the only use of this
6009 reload_reg_rtx is in a reload that just loads the same value
6010 as we do. Note that any secondary reloads must be of the identical
6011 class since the values, modes, and result registers are the
6012 same, so we need not do anything with any secondary reloads. */
6014 for (j = 0; j < n_reloads; j++)
6016 if (i == j || rld[j].reg_rtx == 0
6017 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6021 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6022 && rld[j].opnum > max_input_address_opnum)
6023 max_input_address_opnum = rld[j].opnum;
6025 /* If the reload regs aren't exactly the same (e.g, different modes)
6026 or if the values are different, we can't merge this reload.
6027 But if it is an input reload, we might still merge
6028 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6030 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6031 || rld[j].out != 0 || rld[j].in == 0
6032 || ! rtx_equal_p (rld[i].in, rld[j].in))
6034 if (rld[j].when_needed != RELOAD_FOR_INPUT
6035 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6036 || rld[i].opnum > rld[j].opnum)
6037 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6039 conflicting_input = 1;
6040 if (min_conflicting_input_opnum > rld[j].opnum)
6041 min_conflicting_input_opnum = rld[j].opnum;
6045 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6046 we, in fact, found any matching reloads. */
6049 && max_input_address_opnum <= min_conflicting_input_opnum)
6051 for (j = 0; j < n_reloads; j++)
6052 if (i != j && rld[j].reg_rtx != 0
6053 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6054 && (! conflicting_input
6055 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6056 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6058 rld[i].when_needed = RELOAD_OTHER;
6060 reload_spill_index[j] = -1;
6061 transfer_replacements (i, j);
6064 /* If this is now RELOAD_OTHER, look for any reloads that load
6065 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6066 if they were for inputs, RELOAD_OTHER for outputs. Note that
6067 this test is equivalent to looking for reloads for this operand
6069 /* We must take special care when there are two or more reloads to
6070 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6071 same value or a part of it; we must not change its type if there
6072 is a conflicting input. */
6074 if (rld[i].when_needed == RELOAD_OTHER)
6075 for (j = 0; j < n_reloads; j++)
6077 && rld[j].when_needed != RELOAD_OTHER
6078 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6079 && (! conflicting_input
6080 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6081 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6082 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6088 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6089 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6090 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6092 /* Check to see if we accidentally converted two
6093 reloads that use the same reload register with
6094 different inputs to the same type. If so, the
6095 resulting code won't work. */
6097 for (k = 0; k < j; k++)
6098 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6099 || rld[k].when_needed != rld[j].when_needed
6100 || !rtx_equal_p (rld[k].reg_rtx,
6102 || rtx_equal_p (rld[k].in,
6109 /* These arrays are filled by emit_reload_insns and its subroutines. */
6110 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6111 static rtx other_input_address_reload_insns = 0;
6112 static rtx other_input_reload_insns = 0;
6113 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6114 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6115 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6116 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6117 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6118 static rtx operand_reload_insns = 0;
6119 static rtx other_operand_reload_insns = 0;
6120 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6122 /* Values to be put in spill_reg_store are put here first. */
6123 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6124 static HARD_REG_SET reg_reloaded_died;
6126 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6127 has the number J. OLD contains the value to be used as input. */
6130 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6133 rtx insn = chain->insn;
6134 rtx reloadreg = rl->reg_rtx;
6135 rtx oldequiv_reg = 0;
6138 enum machine_mode mode;
6141 /* Determine the mode to reload in.
6142 This is very tricky because we have three to choose from.
6143 There is the mode the insn operand wants (rl->inmode).
6144 There is the mode of the reload register RELOADREG.
6145 There is the intrinsic mode of the operand, which we could find
6146 by stripping some SUBREGs.
6147 It turns out that RELOADREG's mode is irrelevant:
6148 we can change that arbitrarily.
6150 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6151 then the reload reg may not support QImode moves, so use SImode.
6152 If foo is in memory due to spilling a pseudo reg, this is safe,
6153 because the QImode value is in the least significant part of a
6154 slot big enough for a SImode. If foo is some other sort of
6155 memory reference, then it is impossible to reload this case,
6156 so previous passes had better make sure this never happens.
6158 Then consider a one-word union which has SImode and one of its
6159 members is a float, being fetched as (SUBREG:SF union:SI).
6160 We must fetch that as SFmode because we could be loading into
6161 a float-only register. In this case OLD's mode is correct.
6163 Consider an immediate integer: it has VOIDmode. Here we need
6164 to get a mode from something else.
6166 In some cases, there is a fourth mode, the operand's
6167 containing mode. If the insn specifies a containing mode for
6168 this operand, it overrides all others.
6170 I am not sure whether the algorithm here is always right,
6171 but it does the right things in those cases. */
6173 mode = GET_MODE (old);
6174 if (mode == VOIDmode)
6177 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6178 /* If we need a secondary register for this operation, see if
6179 the value is already in a register in that class. Don't
6180 do this if the secondary register will be used as a scratch
6183 if (rl->secondary_in_reload >= 0
6184 && rl->secondary_in_icode == CODE_FOR_nothing
6187 = find_equiv_reg (old, insn,
6188 rld[rl->secondary_in_reload].class,
6192 /* If reloading from memory, see if there is a register
6193 that already holds the same value. If so, reload from there.
6194 We can pass 0 as the reload_reg_p argument because
6195 any other reload has either already been emitted,
6196 in which case find_equiv_reg will see the reload-insn,
6197 or has yet to be emitted, in which case it doesn't matter
6198 because we will use this equiv reg right away. */
6200 if (oldequiv == 0 && optimize
6203 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6204 && reg_renumber[REGNO (old)] < 0)))
6205 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6209 unsigned int regno = true_regnum (oldequiv);
6211 /* Don't use OLDEQUIV if any other reload changes it at an
6212 earlier stage of this insn or at this stage. */
6213 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6214 rl->in, const0_rtx, j, 0))
6217 /* If it is no cheaper to copy from OLDEQUIV into the
6218 reload register than it would be to move from memory,
6219 don't use it. Likewise, if we need a secondary register
6223 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6224 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6226 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6227 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6228 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6232 #ifdef SECONDARY_MEMORY_NEEDED
6233 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6241 /* delete_output_reload is only invoked properly if old contains
6242 the original pseudo register. Since this is replaced with a
6243 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6244 find the pseudo in RELOAD_IN_REG. */
6246 && reload_override_in[j]
6247 && REG_P (rl->in_reg))
6254 else if (REG_P (oldequiv))
6255 oldequiv_reg = oldequiv;
6256 else if (GET_CODE (oldequiv) == SUBREG)
6257 oldequiv_reg = SUBREG_REG (oldequiv);
6259 /* If we are reloading from a register that was recently stored in
6260 with an output-reload, see if we can prove there was
6261 actually no need to store the old value in it. */
6263 if (optimize && REG_P (oldequiv)
6264 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6265 && spill_reg_store[REGNO (oldequiv)]
6267 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6268 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6270 delete_output_reload (insn, j, REGNO (oldequiv));
6272 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6273 then load RELOADREG from OLDEQUIV. Note that we cannot use
6274 gen_lowpart_common since it can do the wrong thing when
6275 RELOADREG has a multi-word mode. Note that RELOADREG
6276 must always be a REG here. */
6278 if (GET_MODE (reloadreg) != mode)
6279 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6280 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6281 oldequiv = SUBREG_REG (oldequiv);
6282 if (GET_MODE (oldequiv) != VOIDmode
6283 && mode != GET_MODE (oldequiv))
6284 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6286 /* Switch to the right place to emit the reload insns. */
6287 switch (rl->when_needed)
6290 where = &other_input_reload_insns;
6292 case RELOAD_FOR_INPUT:
6293 where = &input_reload_insns[rl->opnum];
6295 case RELOAD_FOR_INPUT_ADDRESS:
6296 where = &input_address_reload_insns[rl->opnum];
6298 case RELOAD_FOR_INPADDR_ADDRESS:
6299 where = &inpaddr_address_reload_insns[rl->opnum];
6301 case RELOAD_FOR_OUTPUT_ADDRESS:
6302 where = &output_address_reload_insns[rl->opnum];
6304 case RELOAD_FOR_OUTADDR_ADDRESS:
6305 where = &outaddr_address_reload_insns[rl->opnum];
6307 case RELOAD_FOR_OPERAND_ADDRESS:
6308 where = &operand_reload_insns;
6310 case RELOAD_FOR_OPADDR_ADDR:
6311 where = &other_operand_reload_insns;
6313 case RELOAD_FOR_OTHER_ADDRESS:
6314 where = &other_input_address_reload_insns;
6320 push_to_sequence (*where);
6322 /* Auto-increment addresses must be reloaded in a special way. */
6323 if (rl->out && ! rl->out_reg)
6325 /* We are not going to bother supporting the case where a
6326 incremented register can't be copied directly from
6327 OLDEQUIV since this seems highly unlikely. */
6328 gcc_assert (rl->secondary_in_reload < 0);
6330 if (reload_inherited[j])
6331 oldequiv = reloadreg;
6333 old = XEXP (rl->in_reg, 0);
6335 if (optimize && REG_P (oldequiv)
6336 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6337 && spill_reg_store[REGNO (oldequiv)]
6339 && (dead_or_set_p (insn,
6340 spill_reg_stored_to[REGNO (oldequiv)])
6341 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6343 delete_output_reload (insn, j, REGNO (oldequiv));
6345 /* Prevent normal processing of this reload. */
6347 /* Output a special code sequence for this case. */
6348 new_spill_reg_store[REGNO (reloadreg)]
6349 = inc_for_reload (reloadreg, oldequiv, rl->out,
6353 /* If we are reloading a pseudo-register that was set by the previous
6354 insn, see if we can get rid of that pseudo-register entirely
6355 by redirecting the previous insn into our reload register. */
6357 else if (optimize && REG_P (old)
6358 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6359 && dead_or_set_p (insn, old)
6360 /* This is unsafe if some other reload
6361 uses the same reg first. */
6362 && ! conflicts_with_override (reloadreg)
6363 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6364 rl->when_needed, old, rl->out, j, 0))
6366 rtx temp = PREV_INSN (insn);
6367 while (temp && NOTE_P (temp))
6368 temp = PREV_INSN (temp);
6370 && NONJUMP_INSN_P (temp)
6371 && GET_CODE (PATTERN (temp)) == SET
6372 && SET_DEST (PATTERN (temp)) == old
6373 /* Make sure we can access insn_operand_constraint. */
6374 && asm_noperands (PATTERN (temp)) < 0
6375 /* This is unsafe if operand occurs more than once in current
6376 insn. Perhaps some occurrences aren't reloaded. */
6377 && count_occurrences (PATTERN (insn), old, 0) == 1)
6379 rtx old = SET_DEST (PATTERN (temp));
6380 /* Store into the reload register instead of the pseudo. */
6381 SET_DEST (PATTERN (temp)) = reloadreg;
6383 /* Verify that resulting insn is valid. */
6384 extract_insn (temp);
6385 if (constrain_operands (1))
6387 /* If the previous insn is an output reload, the source is
6388 a reload register, and its spill_reg_store entry will
6389 contain the previous destination. This is now
6391 if (REG_P (SET_SRC (PATTERN (temp)))
6392 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6394 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6395 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6398 /* If these are the only uses of the pseudo reg,
6399 pretend for GDB it lives in the reload reg we used. */
6400 if (REG_N_DEATHS (REGNO (old)) == 1
6401 && REG_N_SETS (REGNO (old)) == 1)
6403 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6404 alter_reg (REGNO (old), -1);
6410 SET_DEST (PATTERN (temp)) = old;
6415 /* We can't do that, so output an insn to load RELOADREG. */
6417 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6418 /* If we have a secondary reload, pick up the secondary register
6419 and icode, if any. If OLDEQUIV and OLD are different or
6420 if this is an in-out reload, recompute whether or not we
6421 still need a secondary register and what the icode should
6422 be. If we still need a secondary register and the class or
6423 icode is different, go back to reloading from OLD if using
6424 OLDEQUIV means that we got the wrong type of register. We
6425 cannot have different class or icode due to an in-out reload
6426 because we don't make such reloads when both the input and
6427 output need secondary reload registers. */
6429 if (! special && rl->secondary_in_reload >= 0)
6431 rtx second_reload_reg = 0;
6432 int secondary_reload = rl->secondary_in_reload;
6433 rtx real_oldequiv = oldequiv;
6436 enum insn_code icode;
6438 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6439 and similarly for OLD.
6440 See comments in get_secondary_reload in reload.c. */
6441 /* If it is a pseudo that cannot be replaced with its
6442 equivalent MEM, we must fall back to reload_in, which
6443 will have all the necessary substitutions registered.
6444 Likewise for a pseudo that can't be replaced with its
6445 equivalent constant.
6447 Take extra care for subregs of such pseudos. Note that
6448 we cannot use reg_equiv_mem in this case because it is
6449 not in the right mode. */
6452 if (GET_CODE (tmp) == SUBREG)
6453 tmp = SUBREG_REG (tmp);
6455 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6456 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6457 || reg_equiv_constant[REGNO (tmp)] != 0))
6459 if (! reg_equiv_mem[REGNO (tmp)]
6460 || num_not_at_initial_offset
6461 || GET_CODE (oldequiv) == SUBREG)
6462 real_oldequiv = rl->in;
6464 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6468 if (GET_CODE (tmp) == SUBREG)
6469 tmp = SUBREG_REG (tmp);
6471 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6472 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6473 || reg_equiv_constant[REGNO (tmp)] != 0))
6475 if (! reg_equiv_mem[REGNO (tmp)]
6476 || num_not_at_initial_offset
6477 || GET_CODE (old) == SUBREG)
6480 real_old = reg_equiv_mem[REGNO (tmp)];
6483 second_reload_reg = rld[secondary_reload].reg_rtx;
6484 icode = rl->secondary_in_icode;
6486 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6487 || (rl->in != 0 && rl->out != 0))
6489 enum reg_class new_class
6490 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6491 mode, real_oldequiv);
6493 if (new_class == NO_REGS)
6494 second_reload_reg = 0;
6497 enum insn_code new_icode;
6498 enum machine_mode new_mode;
6500 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6501 REGNO (second_reload_reg)))
6502 oldequiv = old, real_oldequiv = real_old;
6505 new_icode = reload_in_optab[(int) mode];
6506 if (new_icode != CODE_FOR_nothing
6507 && ((insn_data[(int) new_icode].operand[0].predicate
6508 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6510 || (insn_data[(int) new_icode].operand[1].predicate
6511 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6512 (real_oldequiv, mode)))))
6513 new_icode = CODE_FOR_nothing;
6515 if (new_icode == CODE_FOR_nothing)
6518 new_mode = insn_data[(int) new_icode].operand[2].mode;
6520 if (GET_MODE (second_reload_reg) != new_mode)
6522 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6524 oldequiv = old, real_oldequiv = real_old;
6527 = reload_adjust_reg_for_mode (second_reload_reg,
6534 /* If we still need a secondary reload register, check
6535 to see if it is being used as a scratch or intermediate
6536 register and generate code appropriately. If we need
6537 a scratch register, use REAL_OLDEQUIV since the form of
6538 the insn may depend on the actual address if it is
6541 if (second_reload_reg)
6543 if (icode != CODE_FOR_nothing)
6545 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6546 second_reload_reg));
6551 /* See if we need a scratch register to load the
6552 intermediate register (a tertiary reload). */
6553 enum insn_code tertiary_icode
6554 = rld[secondary_reload].secondary_in_icode;
6556 if (tertiary_icode != CODE_FOR_nothing)
6558 rtx third_reload_reg
6559 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6561 emit_insn ((GEN_FCN (tertiary_icode)
6562 (second_reload_reg, real_oldequiv,
6563 third_reload_reg)));
6566 gen_reload (second_reload_reg, real_oldequiv,
6570 oldequiv = second_reload_reg;
6576 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6578 rtx real_oldequiv = oldequiv;
6580 if ((REG_P (oldequiv)
6581 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6582 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6583 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6584 || (GET_CODE (oldequiv) == SUBREG
6585 && REG_P (SUBREG_REG (oldequiv))
6586 && (REGNO (SUBREG_REG (oldequiv))
6587 >= FIRST_PSEUDO_REGISTER)
6588 && ((reg_equiv_memory_loc
6589 [REGNO (SUBREG_REG (oldequiv))] != 0)
6590 || (reg_equiv_constant
6591 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6592 || (CONSTANT_P (oldequiv)
6593 && (PREFERRED_RELOAD_CLASS (oldequiv,
6594 REGNO_REG_CLASS (REGNO (reloadreg)))
6596 real_oldequiv = rl->in;
6597 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6601 if (flag_non_call_exceptions)
6602 copy_eh_notes (insn, get_insns ());
6604 /* End this sequence. */
6605 *where = get_insns ();
6608 /* Update reload_override_in so that delete_address_reloads_1
6609 can see the actual register usage. */
6611 reload_override_in[j] = oldequiv;
6614 /* Generate insns to for the output reload RL, which is for the insn described
6615 by CHAIN and has the number J. */
6617 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6620 rtx reloadreg = rl->reg_rtx;
6621 rtx insn = chain->insn;
6624 enum machine_mode mode = GET_MODE (old);
6627 if (rl->when_needed == RELOAD_OTHER)
6630 push_to_sequence (output_reload_insns[rl->opnum]);
6632 /* Determine the mode to reload in.
6633 See comments above (for input reloading). */
6635 if (mode == VOIDmode)
6637 /* VOIDmode should never happen for an output. */
6638 if (asm_noperands (PATTERN (insn)) < 0)
6639 /* It's the compiler's fault. */
6640 fatal_insn ("VOIDmode on an output", insn);
6641 error_for_asm (insn, "output operand is constant in %<asm%>");
6642 /* Prevent crash--use something we know is valid. */
6644 old = gen_rtx_REG (mode, REGNO (reloadreg));
6647 if (GET_MODE (reloadreg) != mode)
6648 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6650 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6652 /* If we need two reload regs, set RELOADREG to the intermediate
6653 one, since it will be stored into OLD. We might need a secondary
6654 register only for an input reload, so check again here. */
6656 if (rl->secondary_out_reload >= 0)
6660 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
6661 && reg_equiv_mem[REGNO (old)] != 0)
6662 real_old = reg_equiv_mem[REGNO (old)];
6664 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6668 rtx second_reloadreg = reloadreg;
6669 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6671 /* See if RELOADREG is to be used as a scratch register
6672 or as an intermediate register. */
6673 if (rl->secondary_out_icode != CODE_FOR_nothing)
6675 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6676 (real_old, second_reloadreg, reloadreg)));
6681 /* See if we need both a scratch and intermediate reload
6684 int secondary_reload = rl->secondary_out_reload;
6685 enum insn_code tertiary_icode
6686 = rld[secondary_reload].secondary_out_icode;
6688 if (GET_MODE (reloadreg) != mode)
6689 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6691 if (tertiary_icode != CODE_FOR_nothing)
6694 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6697 /* Copy primary reload reg to secondary reload reg.
6698 (Note that these have been swapped above, then
6699 secondary reload reg to OLD using our insn.) */
6701 /* If REAL_OLD is a paradoxical SUBREG, remove it
6702 and try to put the opposite SUBREG on
6704 if (GET_CODE (real_old) == SUBREG
6705 && (GET_MODE_SIZE (GET_MODE (real_old))
6706 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6707 && 0 != (tem = gen_lowpart_common
6708 (GET_MODE (SUBREG_REG (real_old)),
6710 real_old = SUBREG_REG (real_old), reloadreg = tem;
6712 gen_reload (reloadreg, second_reloadreg,
6713 rl->opnum, rl->when_needed);
6714 emit_insn ((GEN_FCN (tertiary_icode)
6715 (real_old, reloadreg, third_reloadreg)));
6720 /* Copy between the reload regs here and then to
6723 gen_reload (reloadreg, second_reloadreg,
6724 rl->opnum, rl->when_needed);
6730 /* Output the last reload insn. */
6735 /* Don't output the last reload if OLD is not the dest of
6736 INSN and is in the src and is clobbered by INSN. */
6737 if (! flag_expensive_optimizations
6739 || !(set = single_set (insn))
6740 || rtx_equal_p (old, SET_DEST (set))
6741 || !reg_mentioned_p (old, SET_SRC (set))
6742 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
6743 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
6744 gen_reload (old, reloadreg, rl->opnum,
6748 /* Look at all insns we emitted, just to be safe. */
6749 for (p = get_insns (); p; p = NEXT_INSN (p))
6752 rtx pat = PATTERN (p);
6754 /* If this output reload doesn't come from a spill reg,
6755 clear any memory of reloaded copies of the pseudo reg.
6756 If this output reload comes from a spill reg,
6757 reg_has_output_reload will make this do nothing. */
6758 note_stores (pat, forget_old_reloads_1, NULL);
6760 if (reg_mentioned_p (rl->reg_rtx, pat))
6762 rtx set = single_set (insn);
6763 if (reload_spill_index[j] < 0
6765 && SET_SRC (set) == rl->reg_rtx)
6767 int src = REGNO (SET_SRC (set));
6769 reload_spill_index[j] = src;
6770 SET_HARD_REG_BIT (reg_is_output_reload, src);
6771 if (find_regno_note (insn, REG_DEAD, src))
6772 SET_HARD_REG_BIT (reg_reloaded_died, src);
6774 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6776 int s = rl->secondary_out_reload;
6777 set = single_set (p);
6778 /* If this reload copies only to the secondary reload
6779 register, the secondary reload does the actual
6781 if (s >= 0 && set == NULL_RTX)
6782 /* We can't tell what function the secondary reload
6783 has and where the actual store to the pseudo is
6784 made; leave new_spill_reg_store alone. */
6787 && SET_SRC (set) == rl->reg_rtx
6788 && SET_DEST (set) == rld[s].reg_rtx)
6790 /* Usually the next instruction will be the
6791 secondary reload insn; if we can confirm
6792 that it is, setting new_spill_reg_store to
6793 that insn will allow an extra optimization. */
6794 rtx s_reg = rld[s].reg_rtx;
6795 rtx next = NEXT_INSN (p);
6796 rld[s].out = rl->out;
6797 rld[s].out_reg = rl->out_reg;
6798 set = single_set (next);
6799 if (set && SET_SRC (set) == s_reg
6800 && ! new_spill_reg_store[REGNO (s_reg)])
6802 SET_HARD_REG_BIT (reg_is_output_reload,
6804 new_spill_reg_store[REGNO (s_reg)] = next;
6808 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6813 if (rl->when_needed == RELOAD_OTHER)
6815 emit_insn (other_output_reload_insns[rl->opnum]);
6816 other_output_reload_insns[rl->opnum] = get_insns ();
6819 output_reload_insns[rl->opnum] = get_insns ();
6821 if (flag_non_call_exceptions)
6822 copy_eh_notes (insn, get_insns ());
6827 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6828 and has the number J. */
6830 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
6832 rtx insn = chain->insn;
6833 rtx old = (rl->in && MEM_P (rl->in)
6834 ? rl->in_reg : rl->in);
6837 /* AUTO_INC reloads need to be handled even if inherited. We got an
6838 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6839 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6840 && ! rtx_equal_p (rl->reg_rtx, old)
6841 && rl->reg_rtx != 0)
6842 emit_input_reload_insns (chain, rld + j, old, j);
6844 /* When inheriting a wider reload, we have a MEM in rl->in,
6845 e.g. inheriting a SImode output reload for
6846 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6847 if (optimize && reload_inherited[j] && rl->in
6849 && MEM_P (rl->in_reg)
6850 && reload_spill_index[j] >= 0
6851 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6852 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6854 /* If we are reloading a register that was recently stored in with an
6855 output-reload, see if we can prove there was
6856 actually no need to store the old value in it. */
6859 /* Only attempt this for input reloads; for RELOAD_OTHER we miss
6860 that there may be multiple uses of the previous output reload.
6861 Restricting to RELOAD_FOR_INPUT is mostly paranoia. */
6862 && rl->when_needed == RELOAD_FOR_INPUT
6863 && (reload_inherited[j] || reload_override_in[j])
6865 && REG_P (rl->reg_rtx)
6866 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6868 /* There doesn't seem to be any reason to restrict this to pseudos
6869 and doing so loses in the case where we are copying from a
6870 register of the wrong class. */
6871 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6872 >= FIRST_PSEUDO_REGISTER)
6874 /* The insn might have already some references to stackslots
6875 replaced by MEMs, while reload_out_reg still names the
6877 && (dead_or_set_p (insn,
6878 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6879 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6881 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6884 /* Do output reloading for reload RL, which is for the insn described by
6885 CHAIN and has the number J.
6886 ??? At some point we need to support handling output reloads of
6887 JUMP_INSNs or insns that set cc0. */
6889 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
6892 rtx insn = chain->insn;
6893 /* If this is an output reload that stores something that is
6894 not loaded in this same reload, see if we can eliminate a previous
6896 rtx pseudo = rl->out_reg;
6901 && ! rtx_equal_p (rl->in_reg, pseudo)
6902 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6903 && reg_last_reload_reg[REGNO (pseudo)])
6905 int pseudo_no = REGNO (pseudo);
6906 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6908 /* We don't need to test full validity of last_regno for
6909 inherit here; we only want to know if the store actually
6910 matches the pseudo. */
6911 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6912 && reg_reloaded_contents[last_regno] == pseudo_no
6913 && spill_reg_store[last_regno]
6914 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6915 delete_output_reload (insn, j, last_regno);
6920 || rl->reg_rtx == old
6921 || rl->reg_rtx == 0)
6924 /* An output operand that dies right away does need a reload,
6925 but need not be copied from it. Show the new location in the
6927 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
6928 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6930 XEXP (note, 0) = rl->reg_rtx;
6933 /* Likewise for a SUBREG of an operand that dies. */
6934 else if (GET_CODE (old) == SUBREG
6935 && REG_P (SUBREG_REG (old))
6936 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6939 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6943 else if (GET_CODE (old) == SCRATCH)
6944 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6945 but we don't want to make an output reload. */
6948 /* If is a JUMP_INSN, we can't support output reloads yet. */
6949 gcc_assert (!JUMP_P (insn));
6951 emit_output_reload_insns (chain, rld + j, j);
6954 /* Reload number R reloads from or to a group of hard registers starting at
6955 register REGNO. Return true if it can be treated for inheritance purposes
6956 like a group of reloads, each one reloading a single hard register.
6957 The caller has already checked that the spill register and REGNO use
6958 the same number of registers to store the reload value. */
6961 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
6963 #ifdef CANNOT_CHANGE_MODE_CLASS
6964 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
6965 GET_MODE (rld[r].reg_rtx),
6966 reg_raw_mode[reload_spill_index[r]])
6967 && !REG_CANNOT_CHANGE_MODE_P (regno,
6968 GET_MODE (rld[r].reg_rtx),
6969 reg_raw_mode[regno]));
6975 /* Output insns to reload values in and out of the chosen reload regs. */
6978 emit_reload_insns (struct insn_chain *chain)
6980 rtx insn = chain->insn;
6984 CLEAR_HARD_REG_SET (reg_reloaded_died);
6986 for (j = 0; j < reload_n_operands; j++)
6987 input_reload_insns[j] = input_address_reload_insns[j]
6988 = inpaddr_address_reload_insns[j]
6989 = output_reload_insns[j] = output_address_reload_insns[j]
6990 = outaddr_address_reload_insns[j]
6991 = other_output_reload_insns[j] = 0;
6992 other_input_address_reload_insns = 0;
6993 other_input_reload_insns = 0;
6994 operand_reload_insns = 0;
6995 other_operand_reload_insns = 0;
6997 /* Dump reloads into the dump file. */
7000 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7001 debug_reload_to_stream (dump_file);
7004 /* Now output the instructions to copy the data into and out of the
7005 reload registers. Do these in the order that the reloads were reported,
7006 since reloads of base and index registers precede reloads of operands
7007 and the operands may need the base and index registers reloaded. */
7009 for (j = 0; j < n_reloads; j++)
7012 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7013 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7015 do_input_reload (chain, rld + j, j);
7016 do_output_reload (chain, rld + j, j);
7019 /* Now write all the insns we made for reloads in the order expected by
7020 the allocation functions. Prior to the insn being reloaded, we write
7021 the following reloads:
7023 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7025 RELOAD_OTHER reloads.
7027 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7028 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7029 RELOAD_FOR_INPUT reload for the operand.
7031 RELOAD_FOR_OPADDR_ADDRS reloads.
7033 RELOAD_FOR_OPERAND_ADDRESS reloads.
7035 After the insn being reloaded, we write the following:
7037 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7038 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7039 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7040 reloads for the operand. The RELOAD_OTHER output reloads are
7041 output in descending order by reload number. */
7043 emit_insn_before (other_input_address_reload_insns, insn);
7044 emit_insn_before (other_input_reload_insns, insn);
7046 for (j = 0; j < reload_n_operands; j++)
7048 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7049 emit_insn_before (input_address_reload_insns[j], insn);
7050 emit_insn_before (input_reload_insns[j], insn);
7053 emit_insn_before (other_operand_reload_insns, insn);
7054 emit_insn_before (operand_reload_insns, insn);
7056 for (j = 0; j < reload_n_operands; j++)
7058 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7059 x = emit_insn_after (output_address_reload_insns[j], x);
7060 x = emit_insn_after (output_reload_insns[j], x);
7061 emit_insn_after (other_output_reload_insns[j], x);
7064 /* For all the spill regs newly reloaded in this instruction,
7065 record what they were reloaded from, so subsequent instructions
7066 can inherit the reloads.
7068 Update spill_reg_store for the reloads of this insn.
7069 Copy the elements that were updated in the loop above. */
7071 for (j = 0; j < n_reloads; j++)
7073 int r = reload_order[j];
7074 int i = reload_spill_index[r];
7076 /* If this is a non-inherited input reload from a pseudo, we must
7077 clear any memory of a previous store to the same pseudo. Only do
7078 something if there will not be an output reload for the pseudo
7080 if (rld[r].in_reg != 0
7081 && ! (reload_inherited[r] || reload_override_in[r]))
7083 rtx reg = rld[r].in_reg;
7085 if (GET_CODE (reg) == SUBREG)
7086 reg = SUBREG_REG (reg);
7089 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7090 && ! reg_has_output_reload[REGNO (reg)])
7092 int nregno = REGNO (reg);
7094 if (reg_last_reload_reg[nregno])
7096 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7098 if (reg_reloaded_contents[last_regno] == nregno)
7099 spill_reg_store[last_regno] = 0;
7104 /* I is nonneg if this reload used a register.
7105 If rld[r].reg_rtx is 0, this is an optional reload
7106 that we opted to ignore. */
7108 if (i >= 0 && rld[r].reg_rtx != 0)
7110 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7112 int part_reaches_end = 0;
7113 int all_reaches_end = 1;
7115 /* For a multi register reload, we need to check if all or part
7116 of the value lives to the end. */
7117 for (k = 0; k < nr; k++)
7119 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7120 rld[r].when_needed))
7121 part_reaches_end = 1;
7123 all_reaches_end = 0;
7126 /* Ignore reloads that don't reach the end of the insn in
7128 if (all_reaches_end)
7130 /* First, clear out memory of what used to be in this spill reg.
7131 If consecutive registers are used, clear them all. */
7133 for (k = 0; k < nr; k++)
7135 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7136 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7139 /* Maybe the spill reg contains a copy of reload_out. */
7141 && (REG_P (rld[r].out)
7145 || REG_P (rld[r].out_reg)))
7147 rtx out = (REG_P (rld[r].out)
7151 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7152 int nregno = REGNO (out);
7153 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7154 : hard_regno_nregs[nregno]
7155 [GET_MODE (rld[r].reg_rtx)]);
7158 spill_reg_store[i] = new_spill_reg_store[i];
7159 spill_reg_stored_to[i] = out;
7160 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7162 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7164 && inherit_piecemeal_p (r, nregno));
7166 /* If NREGNO is a hard register, it may occupy more than
7167 one register. If it does, say what is in the
7168 rest of the registers assuming that both registers
7169 agree on how many words the object takes. If not,
7170 invalidate the subsequent registers. */
7172 if (nregno < FIRST_PSEUDO_REGISTER)
7173 for (k = 1; k < nnr; k++)
7174 reg_last_reload_reg[nregno + k]
7176 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7179 /* Now do the inverse operation. */
7180 for (k = 0; k < nr; k++)
7182 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7183 reg_reloaded_contents[i + k]
7184 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7187 reg_reloaded_insn[i + k] = insn;
7188 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7189 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7190 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7194 /* Maybe the spill reg contains a copy of reload_in. Only do
7195 something if there will not be an output reload for
7196 the register being reloaded. */
7197 else if (rld[r].out_reg == 0
7199 && ((REG_P (rld[r].in)
7200 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7201 && ! reg_has_output_reload[REGNO (rld[r].in)])
7202 || (REG_P (rld[r].in_reg)
7203 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7204 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7211 if (REG_P (rld[r].in)
7212 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7214 else if (REG_P (rld[r].in_reg))
7217 in = XEXP (rld[r].in_reg, 0);
7218 nregno = REGNO (in);
7220 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7221 : hard_regno_nregs[nregno]
7222 [GET_MODE (rld[r].reg_rtx)]);
7224 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7226 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7228 && inherit_piecemeal_p (r, nregno));
7230 if (nregno < FIRST_PSEUDO_REGISTER)
7231 for (k = 1; k < nnr; k++)
7232 reg_last_reload_reg[nregno + k]
7234 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7237 /* Unless we inherited this reload, show we haven't
7238 recently done a store.
7239 Previous stores of inherited auto_inc expressions
7240 also have to be discarded. */
7241 if (! reload_inherited[r]
7242 || (rld[r].out && ! rld[r].out_reg))
7243 spill_reg_store[i] = 0;
7245 for (k = 0; k < nr; k++)
7247 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7248 reg_reloaded_contents[i + k]
7249 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7252 reg_reloaded_insn[i + k] = insn;
7253 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7254 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7255 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7260 /* However, if part of the reload reaches the end, then we must
7261 invalidate the old info for the part that survives to the end. */
7262 else if (part_reaches_end)
7264 for (k = 0; k < nr; k++)
7265 if (reload_reg_reaches_end_p (i + k,
7267 rld[r].when_needed))
7268 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7272 /* The following if-statement was #if 0'd in 1.34 (or before...).
7273 It's reenabled in 1.35 because supposedly nothing else
7274 deals with this problem. */
7276 /* If a register gets output-reloaded from a non-spill register,
7277 that invalidates any previous reloaded copy of it.
7278 But forget_old_reloads_1 won't get to see it, because
7279 it thinks only about the original insn. So invalidate it here. */
7280 if (i < 0 && rld[r].out != 0
7281 && (REG_P (rld[r].out)
7282 || (MEM_P (rld[r].out)
7283 && REG_P (rld[r].out_reg))))
7285 rtx out = (REG_P (rld[r].out)
7286 ? rld[r].out : rld[r].out_reg);
7287 int nregno = REGNO (out);
7288 if (nregno >= FIRST_PSEUDO_REGISTER)
7290 rtx src_reg, store_insn = NULL_RTX;
7292 reg_last_reload_reg[nregno] = 0;
7294 /* If we can find a hard register that is stored, record
7295 the storing insn so that we may delete this insn with
7296 delete_output_reload. */
7297 src_reg = rld[r].reg_rtx;
7299 /* If this is an optional reload, try to find the source reg
7300 from an input reload. */
7303 rtx set = single_set (insn);
7304 if (set && SET_DEST (set) == rld[r].out)
7308 src_reg = SET_SRC (set);
7310 for (k = 0; k < n_reloads; k++)
7312 if (rld[k].in == src_reg)
7314 src_reg = rld[k].reg_rtx;
7321 store_insn = new_spill_reg_store[REGNO (src_reg)];
7322 if (src_reg && REG_P (src_reg)
7323 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7325 int src_regno = REGNO (src_reg);
7326 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7327 /* The place where to find a death note varies with
7328 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7329 necessarily checked exactly in the code that moves
7330 notes, so just check both locations. */
7331 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7332 if (! note && store_insn)
7333 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7336 spill_reg_store[src_regno + nr] = store_insn;
7337 spill_reg_stored_to[src_regno + nr] = out;
7338 reg_reloaded_contents[src_regno + nr] = nregno;
7339 reg_reloaded_insn[src_regno + nr] = store_insn;
7340 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7341 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7342 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7343 GET_MODE (src_reg)))
7344 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7346 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7348 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7350 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7352 reg_last_reload_reg[nregno] = src_reg;
7353 /* We have to set reg_has_output_reload here, or else
7354 forget_old_reloads_1 will clear reg_last_reload_reg
7356 reg_has_output_reload[nregno] = 1;
7361 int num_regs = hard_regno_nregs[nregno][GET_MODE (rld[r].out)];
7363 while (num_regs-- > 0)
7364 reg_last_reload_reg[nregno + num_regs] = 0;
7368 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7371 /* Emit code to perform a reload from IN (which may be a reload register) to
7372 OUT (which may also be a reload register). IN or OUT is from operand
7373 OPNUM with reload type TYPE.
7375 Returns first insn emitted. */
7378 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7380 rtx last = get_last_insn ();
7383 /* If IN is a paradoxical SUBREG, remove it and try to put the
7384 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7385 if (GET_CODE (in) == SUBREG
7386 && (GET_MODE_SIZE (GET_MODE (in))
7387 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7388 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7389 in = SUBREG_REG (in), out = tem;
7390 else if (GET_CODE (out) == SUBREG
7391 && (GET_MODE_SIZE (GET_MODE (out))
7392 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7393 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7394 out = SUBREG_REG (out), in = tem;
7396 /* How to do this reload can get quite tricky. Normally, we are being
7397 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7398 register that didn't get a hard register. In that case we can just
7399 call emit_move_insn.
7401 We can also be asked to reload a PLUS that adds a register or a MEM to
7402 another register, constant or MEM. This can occur during frame pointer
7403 elimination and while reloading addresses. This case is handled by
7404 trying to emit a single insn to perform the add. If it is not valid,
7405 we use a two insn sequence.
7407 Finally, we could be called to handle an 'o' constraint by putting
7408 an address into a register. In that case, we first try to do this
7409 with a named pattern of "reload_load_address". If no such pattern
7410 exists, we just emit a SET insn and hope for the best (it will normally
7411 be valid on machines that use 'o').
7413 This entire process is made complex because reload will never
7414 process the insns we generate here and so we must ensure that
7415 they will fit their constraints and also by the fact that parts of
7416 IN might be being reloaded separately and replaced with spill registers.
7417 Because of this, we are, in some sense, just guessing the right approach
7418 here. The one listed above seems to work.
7420 ??? At some point, this whole thing needs to be rethought. */
7422 if (GET_CODE (in) == PLUS
7423 && (REG_P (XEXP (in, 0))
7424 || GET_CODE (XEXP (in, 0)) == SUBREG
7425 || MEM_P (XEXP (in, 0)))
7426 && (REG_P (XEXP (in, 1))
7427 || GET_CODE (XEXP (in, 1)) == SUBREG
7428 || CONSTANT_P (XEXP (in, 1))
7429 || MEM_P (XEXP (in, 1))))
7431 /* We need to compute the sum of a register or a MEM and another
7432 register, constant, or MEM, and put it into the reload
7433 register. The best possible way of doing this is if the machine
7434 has a three-operand ADD insn that accepts the required operands.
7436 The simplest approach is to try to generate such an insn and see if it
7437 is recognized and matches its constraints. If so, it can be used.
7439 It might be better not to actually emit the insn unless it is valid,
7440 but we need to pass the insn as an operand to `recog' and
7441 `extract_insn' and it is simpler to emit and then delete the insn if
7442 not valid than to dummy things up. */
7444 rtx op0, op1, tem, insn;
7447 op0 = find_replacement (&XEXP (in, 0));
7448 op1 = find_replacement (&XEXP (in, 1));
7450 /* Since constraint checking is strict, commutativity won't be
7451 checked, so we need to do that here to avoid spurious failure
7452 if the add instruction is two-address and the second operand
7453 of the add is the same as the reload reg, which is frequently
7454 the case. If the insn would be A = B + A, rearrange it so
7455 it will be A = A + B as constrain_operands expects. */
7457 if (REG_P (XEXP (in, 1))
7458 && REGNO (out) == REGNO (XEXP (in, 1)))
7459 tem = op0, op0 = op1, op1 = tem;
7461 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7462 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7464 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7465 code = recog_memoized (insn);
7469 extract_insn (insn);
7470 /* We want constrain operands to treat this insn strictly in
7471 its validity determination, i.e., the way it would after reload
7473 if (constrain_operands (1))
7477 delete_insns_since (last);
7479 /* If that failed, we must use a conservative two-insn sequence.
7481 Use a move to copy one operand into the reload register. Prefer
7482 to reload a constant, MEM or pseudo since the move patterns can
7483 handle an arbitrary operand. If OP1 is not a constant, MEM or
7484 pseudo and OP1 is not a valid operand for an add instruction, then
7487 After reloading one of the operands into the reload register, add
7488 the reload register to the output register.
7490 If there is another way to do this for a specific machine, a
7491 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7494 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7496 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7498 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7499 || (code != CODE_FOR_nothing
7500 && ! ((*insn_data[code].operand[2].predicate)
7501 (op1, insn_data[code].operand[2].mode))))
7502 tem = op0, op0 = op1, op1 = tem;
7504 gen_reload (out, op0, opnum, type);
7506 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7507 This fixes a problem on the 32K where the stack pointer cannot
7508 be used as an operand of an add insn. */
7510 if (rtx_equal_p (op0, op1))
7513 insn = emit_insn (gen_add2_insn (out, op1));
7515 /* If that failed, copy the address register to the reload register.
7516 Then add the constant to the reload register. */
7518 code = recog_memoized (insn);
7522 extract_insn (insn);
7523 /* We want constrain operands to treat this insn strictly in
7524 its validity determination, i.e., the way it would after reload
7526 if (constrain_operands (1))
7528 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7530 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7535 delete_insns_since (last);
7537 gen_reload (out, op1, opnum, type);
7538 insn = emit_insn (gen_add2_insn (out, op0));
7539 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7542 #ifdef SECONDARY_MEMORY_NEEDED
7543 /* If we need a memory location to do the move, do it that way. */
7544 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7545 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7546 && (REG_P (out) || GET_CODE (out) == SUBREG)
7547 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7548 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7549 REGNO_REG_CLASS (reg_or_subregno (out)),
7552 /* Get the memory to use and rewrite both registers to its mode. */
7553 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7555 if (GET_MODE (loc) != GET_MODE (out))
7556 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7558 if (GET_MODE (loc) != GET_MODE (in))
7559 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7561 gen_reload (loc, in, opnum, type);
7562 gen_reload (out, loc, opnum, type);
7566 /* If IN is a simple operand, use gen_move_insn. */
7567 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
7568 emit_insn (gen_move_insn (out, in));
7570 #ifdef HAVE_reload_load_address
7571 else if (HAVE_reload_load_address)
7572 emit_insn (gen_reload_load_address (out, in));
7575 /* Otherwise, just write (set OUT IN) and hope for the best. */
7577 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7579 /* Return the first insn emitted.
7580 We can not just return get_last_insn, because there may have
7581 been multiple instructions emitted. Also note that gen_move_insn may
7582 emit more than one insn itself, so we can not assume that there is one
7583 insn emitted per emit_insn_before call. */
7585 return last ? NEXT_INSN (last) : get_insns ();
7588 /* Delete a previously made output-reload whose result we now believe
7589 is not needed. First we double-check.
7591 INSN is the insn now being processed.
7592 LAST_RELOAD_REG is the hard register number for which we want to delete
7593 the last output reload.
7594 J is the reload-number that originally used REG. The caller has made
7595 certain that reload J doesn't use REG any longer for input. */
7598 delete_output_reload (rtx insn, int j, int last_reload_reg)
7600 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7601 rtx reg = spill_reg_stored_to[last_reload_reg];
7604 int n_inherited = 0;
7608 /* It is possible that this reload has been only used to set another reload
7609 we eliminated earlier and thus deleted this instruction too. */
7610 if (INSN_DELETED_P (output_reload_insn))
7613 /* Get the raw pseudo-register referred to. */
7615 while (GET_CODE (reg) == SUBREG)
7616 reg = SUBREG_REG (reg);
7617 substed = reg_equiv_memory_loc[REGNO (reg)];
7619 /* This is unsafe if the operand occurs more often in the current
7620 insn than it is inherited. */
7621 for (k = n_reloads - 1; k >= 0; k--)
7623 rtx reg2 = rld[k].in;
7626 if (MEM_P (reg2) || reload_override_in[k])
7627 reg2 = rld[k].in_reg;
7629 if (rld[k].out && ! rld[k].out_reg)
7630 reg2 = XEXP (rld[k].in_reg, 0);
7632 while (GET_CODE (reg2) == SUBREG)
7633 reg2 = SUBREG_REG (reg2);
7634 if (rtx_equal_p (reg2, reg))
7636 if (reload_inherited[k] || reload_override_in[k] || k == j)
7639 reg2 = rld[k].out_reg;
7642 while (GET_CODE (reg2) == SUBREG)
7643 reg2 = XEXP (reg2, 0);
7644 if (rtx_equal_p (reg2, reg))
7651 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7653 n_occurrences += count_occurrences (PATTERN (insn),
7654 eliminate_regs (substed, 0,
7656 if (n_occurrences > n_inherited)
7659 /* If the pseudo-reg we are reloading is no longer referenced
7660 anywhere between the store into it and here,
7661 and we're within the same basic block, then the value can only
7662 pass through the reload reg and end up here.
7663 Otherwise, give up--return. */
7664 for (i1 = NEXT_INSN (output_reload_insn);
7665 i1 != insn; i1 = NEXT_INSN (i1))
7667 if (NOTE_INSN_BASIC_BLOCK_P (i1))
7669 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
7670 && reg_mentioned_p (reg, PATTERN (i1)))
7672 /* If this is USE in front of INSN, we only have to check that
7673 there are no more references than accounted for by inheritance. */
7674 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
7676 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7677 i1 = NEXT_INSN (i1);
7679 if (n_occurrences <= n_inherited && i1 == insn)
7685 /* We will be deleting the insn. Remove the spill reg information. */
7686 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
7688 spill_reg_store[last_reload_reg + k] = 0;
7689 spill_reg_stored_to[last_reload_reg + k] = 0;
7692 /* The caller has already checked that REG dies or is set in INSN.
7693 It has also checked that we are optimizing, and thus some
7694 inaccuracies in the debugging information are acceptable.
7695 So we could just delete output_reload_insn. But in some cases
7696 we can improve the debugging information without sacrificing
7697 optimization - maybe even improving the code: See if the pseudo
7698 reg has been completely replaced with reload regs. If so, delete
7699 the store insn and forget we had a stack slot for the pseudo. */
7700 if (rld[j].out != rld[j].in
7701 && REG_N_DEATHS (REGNO (reg)) == 1
7702 && REG_N_SETS (REGNO (reg)) == 1
7703 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7704 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7708 /* We know that it was used only between here and the beginning of
7709 the current basic block. (We also know that the last use before
7710 INSN was the output reload we are thinking of deleting, but never
7711 mind that.) Search that range; see if any ref remains. */
7712 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7714 rtx set = single_set (i2);
7716 /* Uses which just store in the pseudo don't count,
7717 since if they are the only uses, they are dead. */
7718 if (set != 0 && SET_DEST (set) == reg)
7723 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
7724 && reg_mentioned_p (reg, PATTERN (i2)))
7726 /* Some other ref remains; just delete the output reload we
7728 delete_address_reloads (output_reload_insn, insn);
7729 delete_insn (output_reload_insn);
7734 /* Delete the now-dead stores into this pseudo. Note that this
7735 loop also takes care of deleting output_reload_insn. */
7736 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7738 rtx set = single_set (i2);
7740 if (set != 0 && SET_DEST (set) == reg)
7742 delete_address_reloads (i2, insn);
7750 /* For the debugging info, say the pseudo lives in this reload reg. */
7751 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7752 alter_reg (REGNO (reg), -1);
7756 delete_address_reloads (output_reload_insn, insn);
7757 delete_insn (output_reload_insn);
7761 /* We are going to delete DEAD_INSN. Recursively delete loads of
7762 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7763 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7765 delete_address_reloads (rtx dead_insn, rtx current_insn)
7767 rtx set = single_set (dead_insn);
7768 rtx set2, dst, prev, next;
7771 rtx dst = SET_DEST (set);
7773 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7775 /* If we deleted the store from a reloaded post_{in,de}c expression,
7776 we can delete the matching adds. */
7777 prev = PREV_INSN (dead_insn);
7778 next = NEXT_INSN (dead_insn);
7779 if (! prev || ! next)
7781 set = single_set (next);
7782 set2 = single_set (prev);
7784 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7785 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7786 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7788 dst = SET_DEST (set);
7789 if (! rtx_equal_p (dst, SET_DEST (set2))
7790 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7791 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7792 || (INTVAL (XEXP (SET_SRC (set), 1))
7793 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7795 delete_related_insns (prev);
7796 delete_related_insns (next);
7799 /* Subfunction of delete_address_reloads: process registers found in X. */
7801 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
7803 rtx prev, set, dst, i2;
7805 enum rtx_code code = GET_CODE (x);
7809 const char *fmt = GET_RTX_FORMAT (code);
7810 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7813 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7814 else if (fmt[i] == 'E')
7816 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7817 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7824 if (spill_reg_order[REGNO (x)] < 0)
7827 /* Scan backwards for the insn that sets x. This might be a way back due
7829 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7831 code = GET_CODE (prev);
7832 if (code == CODE_LABEL || code == JUMP_INSN)
7836 if (reg_set_p (x, PATTERN (prev)))
7838 if (reg_referenced_p (x, PATTERN (prev)))
7841 if (! prev || INSN_UID (prev) < reload_first_uid)
7843 /* Check that PREV only sets the reload register. */
7844 set = single_set (prev);
7847 dst = SET_DEST (set);
7849 || ! rtx_equal_p (dst, x))
7851 if (! reg_set_p (dst, PATTERN (dead_insn)))
7853 /* Check if DST was used in a later insn -
7854 it might have been inherited. */
7855 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7861 if (reg_referenced_p (dst, PATTERN (i2)))
7863 /* If there is a reference to the register in the current insn,
7864 it might be loaded in a non-inherited reload. If no other
7865 reload uses it, that means the register is set before
7867 if (i2 == current_insn)
7869 for (j = n_reloads - 1; j >= 0; j--)
7870 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7871 || reload_override_in[j] == dst)
7873 for (j = n_reloads - 1; j >= 0; j--)
7874 if (rld[j].in && rld[j].reg_rtx == dst)
7883 /* If DST is still live at CURRENT_INSN, check if it is used for
7884 any reload. Note that even if CURRENT_INSN sets DST, we still
7885 have to check the reloads. */
7886 if (i2 == current_insn)
7888 for (j = n_reloads - 1; j >= 0; j--)
7889 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7890 || reload_override_in[j] == dst)
7892 /* ??? We can't finish the loop here, because dst might be
7893 allocated to a pseudo in this block if no reload in this
7894 block needs any of the classes containing DST - see
7895 spill_hard_reg. There is no easy way to tell this, so we
7896 have to scan till the end of the basic block. */
7898 if (reg_set_p (dst, PATTERN (i2)))
7902 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7903 reg_reloaded_contents[REGNO (dst)] = -1;
7907 /* Output reload-insns to reload VALUE into RELOADREG.
7908 VALUE is an autoincrement or autodecrement RTX whose operand
7909 is a register or memory location;
7910 so reloading involves incrementing that location.
7911 IN is either identical to VALUE, or some cheaper place to reload from.
7913 INC_AMOUNT is the number to increment or decrement by (always positive).
7914 This cannot be deduced from VALUE.
7916 Return the instruction that stores into RELOADREG. */
7919 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
7921 /* REG or MEM to be copied and incremented. */
7922 rtx incloc = XEXP (value, 0);
7923 /* Nonzero if increment after copying. */
7924 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7930 rtx real_in = in == value ? XEXP (in, 0) : in;
7932 /* No hard register is equivalent to this register after
7933 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7934 we could inc/dec that register as well (maybe even using it for
7935 the source), but I'm not sure it's worth worrying about. */
7937 reg_last_reload_reg[REGNO (incloc)] = 0;
7939 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7940 inc_amount = -inc_amount;
7942 inc = GEN_INT (inc_amount);
7944 /* If this is post-increment, first copy the location to the reload reg. */
7945 if (post && real_in != reloadreg)
7946 emit_insn (gen_move_insn (reloadreg, real_in));
7950 /* See if we can directly increment INCLOC. Use a method similar to
7951 that in gen_reload. */
7953 last = get_last_insn ();
7954 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7955 gen_rtx_PLUS (GET_MODE (incloc),
7958 code = recog_memoized (add_insn);
7961 extract_insn (add_insn);
7962 if (constrain_operands (1))
7964 /* If this is a pre-increment and we have incremented the value
7965 where it lives, copy the incremented value to RELOADREG to
7966 be used as an address. */
7969 emit_insn (gen_move_insn (reloadreg, incloc));
7974 delete_insns_since (last);
7977 /* If couldn't do the increment directly, must increment in RELOADREG.
7978 The way we do this depends on whether this is pre- or post-increment.
7979 For pre-increment, copy INCLOC to the reload register, increment it
7980 there, then save back. */
7984 if (in != reloadreg)
7985 emit_insn (gen_move_insn (reloadreg, real_in));
7986 emit_insn (gen_add2_insn (reloadreg, inc));
7987 store = emit_insn (gen_move_insn (incloc, reloadreg));
7992 Because this might be a jump insn or a compare, and because RELOADREG
7993 may not be available after the insn in an input reload, we must do
7994 the incrementation before the insn being reloaded for.
7996 We have already copied IN to RELOADREG. Increment the copy in
7997 RELOADREG, save that back, then decrement RELOADREG so it has
7998 the original value. */
8000 emit_insn (gen_add2_insn (reloadreg, inc));
8001 store = emit_insn (gen_move_insn (incloc, reloadreg));
8002 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8010 add_auto_inc_notes (rtx insn, rtx x)
8012 enum rtx_code code = GET_CODE (x);
8016 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8019 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8023 /* Scan all the operand sub-expressions. */
8024 fmt = GET_RTX_FORMAT (code);
8025 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8028 add_auto_inc_notes (insn, XEXP (x, i));
8029 else if (fmt[i] == 'E')
8030 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8031 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8036 /* Copy EH notes from an insn to its reloads. */
8038 copy_eh_notes (rtx insn, rtx x)
8040 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8043 for (; x != 0; x = NEXT_INSN (x))
8045 if (may_trap_p (PATTERN (x)))
8047 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8053 /* This is used by reload pass, that does emit some instructions after
8054 abnormal calls moving basic block end, but in fact it wants to emit
8055 them on the edge. Looks for abnormal call edges, find backward the
8056 proper call and fix the damage.
8058 Similar handle instructions throwing exceptions internally. */
8060 fixup_abnormal_edges (void)
8062 bool inserted = false;
8070 /* Look for cases we are interested in - calls or instructions causing
8072 FOR_EACH_EDGE (e, ei, bb->succs)
8074 if (e->flags & EDGE_ABNORMAL_CALL)
8076 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8077 == (EDGE_ABNORMAL | EDGE_EH))
8080 if (e && !CALL_P (BB_END (bb))
8081 && !can_throw_internal (BB_END (bb)))
8083 rtx insn = BB_END (bb), stop = NEXT_INSN (BB_END (bb));
8085 FOR_EACH_EDGE (e, ei, bb->succs)
8086 if (e->flags & EDGE_FALLTHRU)
8088 /* Get past the new insns generated. Allow notes, as the insns may
8089 be already deleted. */
8090 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8091 && !can_throw_internal (insn)
8092 && insn != BB_HEAD (bb))
8093 insn = PREV_INSN (insn);
8094 gcc_assert (CALL_P (insn) || can_throw_internal (insn));
8097 insn = NEXT_INSN (insn);
8098 while (insn && insn != stop)
8100 next = NEXT_INSN (insn);
8105 /* Sometimes there's still the return value USE.
8106 If it's placed after a trapping call (i.e. that
8107 call is the last insn anyway), we have no fallthru
8108 edge. Simply delete this use and don't try to insert
8109 on the non-existent edge. */
8110 if (GET_CODE (PATTERN (insn)) != USE)
8112 /* We're not deleting it, we're moving it. */
8113 INSN_DELETED_P (insn) = 0;
8114 PREV_INSN (insn) = NULL_RTX;
8115 NEXT_INSN (insn) = NULL_RTX;
8117 insert_insn_on_edge (insn, e);
8124 /* We've possibly turned single trapping insn into multiple ones. */
8125 if (flag_non_call_exceptions)
8128 blocks = sbitmap_alloc (last_basic_block);
8129 sbitmap_ones (blocks);
8130 find_many_sub_basic_blocks (blocks);
8133 commit_edge_insertions ();
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