1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation,
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
33 #include "insn-config.h"
39 #include "basic-block.h"
49 /* This file contains the reload pass of the compiler, which is
50 run after register allocation has been done. It checks that
51 each insn is valid (operands required to be in registers really
52 are in registers of the proper class) and fixes up invalid ones
53 by copying values temporarily into registers for the insns
56 The results of register allocation are described by the vector
57 reg_renumber; the insns still contain pseudo regs, but reg_renumber
58 can be used to find which hard reg, if any, a pseudo reg is in.
60 The technique we always use is to free up a few hard regs that are
61 called ``reload regs'', and for each place where a pseudo reg
62 must be in a hard reg, copy it temporarily into one of the reload regs.
64 Reload regs are allocated locally for every instruction that needs
65 reloads. When there are pseudos which are allocated to a register that
66 has been chosen as a reload reg, such pseudos must be ``spilled''.
67 This means that they go to other hard regs, or to stack slots if no other
68 available hard regs can be found. Spilling can invalidate more
69 insns, requiring additional need for reloads, so we must keep checking
70 until the process stabilizes.
72 For machines with different classes of registers, we must keep track
73 of the register class needed for each reload, and make sure that
74 we allocate enough reload registers of each class.
76 The file reload.c contains the code that checks one insn for
77 validity and reports the reloads that it needs. This file
78 is in charge of scanning the entire rtl code, accumulating the
79 reload needs, spilling, assigning reload registers to use for
80 fixing up each insn, and generating the new insns to copy values
81 into the reload registers. */
83 /* During reload_as_needed, element N contains a REG rtx for the hard reg
84 into which reg N has been reloaded (perhaps for a previous insn). */
85 static rtx *reg_last_reload_reg;
87 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
88 for an output reload that stores into reg N. */
89 static char *reg_has_output_reload;
91 /* Indicates which hard regs are reload-registers for an output reload
92 in the current insn. */
93 static HARD_REG_SET reg_is_output_reload;
95 /* Element N is the constant value to which pseudo reg N is equivalent,
96 or zero if pseudo reg N is not equivalent to a constant.
97 find_reloads looks at this in order to replace pseudo reg N
98 with the constant it stands for. */
99 rtx *reg_equiv_constant;
101 /* Element N is an invariant value to which pseudo reg N is equivalent.
102 eliminate_regs_in_insn uses this to replace pseudos in particular
104 rtx *reg_equiv_invariant;
106 /* Element N is a memory location to which pseudo reg N is equivalent,
107 prior to any register elimination (such as frame pointer to stack
108 pointer). Depending on whether or not it is a valid address, this value
109 is transferred to either reg_equiv_address or reg_equiv_mem. */
110 rtx *reg_equiv_memory_loc;
112 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
113 collector can keep track of what is inside. */
114 varray_type reg_equiv_memory_loc_varray;
116 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
117 This is used when the address is not valid as a memory address
118 (because its displacement is too big for the machine.) */
119 rtx *reg_equiv_address;
121 /* Element N is the memory slot to which pseudo reg N is equivalent,
122 or zero if pseudo reg N is not equivalent to a memory slot. */
125 /* Widest width in which each pseudo reg is referred to (via subreg). */
126 static unsigned int *reg_max_ref_width;
128 /* Element N is the list of insns that initialized reg N from its equivalent
129 constant or memory slot. */
131 int reg_equiv_init_size;
133 /* Vector to remember old contents of reg_renumber before spilling. */
134 static short *reg_old_renumber;
136 /* During reload_as_needed, element N contains the last pseudo regno reloaded
137 into hard register N. If that pseudo reg occupied more than one register,
138 reg_reloaded_contents points to that pseudo for each spill register in
139 use; all of these must remain set for an inheritance to occur. */
140 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
142 /* During reload_as_needed, element N contains the insn for which
143 hard register N was last used. Its contents are significant only
144 when reg_reloaded_valid is set for this register. */
145 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
147 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
148 static HARD_REG_SET reg_reloaded_valid;
149 /* Indicate if the register was dead at the end of the reload.
150 This is only valid if reg_reloaded_contents is set and valid. */
151 static HARD_REG_SET reg_reloaded_dead;
153 /* Indicate whether the register's current value is one that is not
154 safe to retain across a call, even for registers that are normally
156 static HARD_REG_SET reg_reloaded_call_part_clobbered;
158 /* Number of spill-regs so far; number of valid elements of spill_regs. */
161 /* In parallel with spill_regs, contains REG rtx's for those regs.
162 Holds the last rtx used for any given reg, or 0 if it has never
163 been used for spilling yet. This rtx is reused, provided it has
165 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
167 /* In parallel with spill_regs, contains nonzero for a spill reg
168 that was stored after the last time it was used.
169 The precise value is the insn generated to do the store. */
170 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
172 /* This is the register that was stored with spill_reg_store. This is a
173 copy of reload_out / reload_out_reg when the value was stored; if
174 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
175 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
177 /* This table is the inverse mapping of spill_regs:
178 indexed by hard reg number,
179 it contains the position of that reg in spill_regs,
180 or -1 for something that is not in spill_regs.
182 ?!? This is no longer accurate. */
183 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
185 /* This reg set indicates registers that can't be used as spill registers for
186 the currently processed insn. These are the hard registers which are live
187 during the insn, but not allocated to pseudos, as well as fixed
189 static HARD_REG_SET bad_spill_regs;
191 /* These are the hard registers that can't be used as spill register for any
192 insn. This includes registers used for user variables and registers that
193 we can't eliminate. A register that appears in this set also can't be used
194 to retry register allocation. */
195 static HARD_REG_SET bad_spill_regs_global;
197 /* Describes order of use of registers for reloading
198 of spilled pseudo-registers. `n_spills' is the number of
199 elements that are actually valid; new ones are added at the end.
201 Both spill_regs and spill_reg_order are used on two occasions:
202 once during find_reload_regs, where they keep track of the spill registers
203 for a single insn, but also during reload_as_needed where they show all
204 the registers ever used by reload. For the latter case, the information
205 is calculated during finish_spills. */
206 static short spill_regs[FIRST_PSEUDO_REGISTER];
208 /* This vector of reg sets indicates, for each pseudo, which hard registers
209 may not be used for retrying global allocation because the register was
210 formerly spilled from one of them. If we allowed reallocating a pseudo to
211 a register that it was already allocated to, reload might not
213 static HARD_REG_SET *pseudo_previous_regs;
215 /* This vector of reg sets indicates, for each pseudo, which hard
216 registers may not be used for retrying global allocation because they
217 are used as spill registers during one of the insns in which the
219 static HARD_REG_SET *pseudo_forbidden_regs;
221 /* All hard regs that have been used as spill registers for any insn are
222 marked in this set. */
223 static HARD_REG_SET used_spill_regs;
225 /* Index of last register assigned as a spill register. We allocate in
226 a round-robin fashion. */
227 static int last_spill_reg;
229 /* Nonzero if indirect addressing is supported on the machine; this means
230 that spilling (REG n) does not require reloading it into a register in
231 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
232 value indicates the level of indirect addressing supported, e.g., two
233 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
235 static char spill_indirect_levels;
237 /* Nonzero if indirect addressing is supported when the innermost MEM is
238 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
239 which these are valid is the same as spill_indirect_levels, above. */
240 char indirect_symref_ok;
242 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
243 char double_reg_address_ok;
245 /* Record the stack slot for each spilled hard register. */
246 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
248 /* Width allocated so far for that stack slot. */
249 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
251 /* Record which pseudos needed to be spilled. */
252 static regset_head spilled_pseudos;
254 /* Used for communication between order_regs_for_reload and count_pseudo.
255 Used to avoid counting one pseudo twice. */
256 static regset_head pseudos_counted;
258 /* First uid used by insns created by reload in this function.
259 Used in find_equiv_reg. */
260 int reload_first_uid;
262 /* Flag set by local-alloc or global-alloc if anything is live in
263 a call-clobbered reg across calls. */
264 int caller_save_needed;
266 /* Set to 1 while reload_as_needed is operating.
267 Required by some machines to handle any generated moves differently. */
268 int reload_in_progress = 0;
270 /* These arrays record the insn_code of insns that may be needed to
271 perform input and output reloads of special objects. They provide a
272 place to pass a scratch register. */
273 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
274 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
276 /* This obstack is used for allocation of rtl during register elimination.
277 The allocated storage can be freed once find_reloads has processed the
279 static struct obstack reload_obstack;
281 /* Points to the beginning of the reload_obstack. All insn_chain structures
282 are allocated first. */
283 static char *reload_startobj;
285 /* The point after all insn_chain structures. Used to quickly deallocate
286 memory allocated in copy_reloads during calculate_needs_all_insns. */
287 static char *reload_firstobj;
289 /* This points before all local rtl generated by register elimination.
290 Used to quickly free all memory after processing one insn. */
291 static char *reload_insn_firstobj;
293 /* List of insn_chain instructions, one for every insn that reload needs to
295 struct insn_chain *reload_insn_chain;
297 /* List of all insns needing reloads. */
298 static struct insn_chain *insns_need_reload;
300 /* This structure is used to record information about register eliminations.
301 Each array entry describes one possible way of eliminating a register
302 in favor of another. If there is more than one way of eliminating a
303 particular register, the most preferred should be specified first. */
307 int from; /* Register number to be eliminated. */
308 int to; /* Register number used as replacement. */
309 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
310 int can_eliminate; /* Nonzero if this elimination can be done. */
311 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
312 insns made by reload. */
313 HOST_WIDE_INT offset; /* Current offset between the two regs. */
314 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
315 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
316 rtx from_rtx; /* REG rtx for the register to be eliminated.
317 We cannot simply compare the number since
318 we might then spuriously replace a hard
319 register corresponding to a pseudo
320 assigned to the reg to be eliminated. */
321 rtx to_rtx; /* REG rtx for the replacement. */
324 static struct elim_table *reg_eliminate = 0;
326 /* This is an intermediate structure to initialize the table. It has
327 exactly the members provided by ELIMINABLE_REGS. */
328 static const struct elim_table_1
332 } reg_eliminate_1[] =
334 /* If a set of eliminable registers was specified, define the table from it.
335 Otherwise, default to the normal case of the frame pointer being
336 replaced by the stack pointer. */
338 #ifdef ELIMINABLE_REGS
341 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
344 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
346 /* Record the number of pending eliminations that have an offset not equal
347 to their initial offset. If nonzero, we use a new copy of each
348 replacement result in any insns encountered. */
349 int num_not_at_initial_offset;
351 /* Count the number of registers that we may be able to eliminate. */
352 static int num_eliminable;
353 /* And the number of registers that are equivalent to a constant that
354 can be eliminated to frame_pointer / arg_pointer + constant. */
355 static int num_eliminable_invariants;
357 /* For each label, we record the offset of each elimination. If we reach
358 a label by more than one path and an offset differs, we cannot do the
359 elimination. This information is indexed by the difference of the
360 number of the label and the first label number. We can't offset the
361 pointer itself as this can cause problems on machines with segmented
362 memory. The first table is an array of flags that records whether we
363 have yet encountered a label and the second table is an array of arrays,
364 one entry in the latter array for each elimination. */
366 static int first_label_num;
367 static char *offsets_known_at;
368 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
370 /* Number of labels in the current function. */
372 static int num_labels;
374 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
375 static void maybe_fix_stack_asms (void);
376 static void copy_reloads (struct insn_chain *);
377 static void calculate_needs_all_insns (int);
378 static int find_reg (struct insn_chain *, int);
379 static void find_reload_regs (struct insn_chain *);
380 static void select_reload_regs (void);
381 static void delete_caller_save_insns (void);
383 static void spill_failure (rtx, enum reg_class);
384 static void count_spilled_pseudo (int, int, int);
385 static void delete_dead_insn (rtx);
386 static void alter_reg (int, int);
387 static void set_label_offsets (rtx, rtx, int);
388 static void check_eliminable_occurrences (rtx);
389 static void elimination_effects (rtx, enum machine_mode);
390 static int eliminate_regs_in_insn (rtx, int);
391 static void update_eliminable_offsets (void);
392 static void mark_not_eliminable (rtx, rtx, void *);
393 static void set_initial_elim_offsets (void);
394 static bool verify_initial_elim_offsets (void);
395 static void set_initial_label_offsets (void);
396 static void set_offsets_for_label (rtx);
397 static void init_elim_table (void);
398 static void update_eliminables (HARD_REG_SET *);
399 static void spill_hard_reg (unsigned int, int);
400 static int finish_spills (int);
401 static void scan_paradoxical_subregs (rtx);
402 static void count_pseudo (int);
403 static void order_regs_for_reload (struct insn_chain *);
404 static void reload_as_needed (int);
405 static void forget_old_reloads_1 (rtx, rtx, void *);
406 static int reload_reg_class_lower (const void *, const void *);
407 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
409 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
411 static int reload_reg_free_p (unsigned int, int, enum reload_type);
412 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
414 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
416 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
417 static int allocate_reload_reg (struct insn_chain *, int, int);
418 static int conflicts_with_override (rtx);
419 static void failed_reload (rtx, int);
420 static int set_reload_reg (int, int);
421 static void choose_reload_regs_init (struct insn_chain *, rtx *);
422 static void choose_reload_regs (struct insn_chain *);
423 static void merge_assigned_reloads (rtx);
424 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
426 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
428 static void do_input_reload (struct insn_chain *, struct reload *, int);
429 static void do_output_reload (struct insn_chain *, struct reload *, int);
430 static bool inherit_piecemeal_p (int, int);
431 static void emit_reload_insns (struct insn_chain *);
432 static void delete_output_reload (rtx, int, int);
433 static void delete_address_reloads (rtx, rtx);
434 static void delete_address_reloads_1 (rtx, rtx, rtx);
435 static rtx inc_for_reload (rtx, rtx, rtx, int);
437 static void add_auto_inc_notes (rtx, rtx);
439 static void copy_eh_notes (rtx, rtx);
440 static int reloads_conflict (int, int);
441 static rtx gen_reload (rtx, rtx, int, enum reload_type);
442 static rtx emit_insn_if_valid_for_reload (rtx);
444 /* Initialize the reload pass once per compilation. */
451 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
452 Set spill_indirect_levels to the number of levels such addressing is
453 permitted, zero if it is not permitted at all. */
456 = gen_rtx_MEM (Pmode,
459 LAST_VIRTUAL_REGISTER + 1),
461 spill_indirect_levels = 0;
463 while (memory_address_p (QImode, tem))
465 spill_indirect_levels++;
466 tem = gen_rtx_MEM (Pmode, tem);
469 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
471 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
472 indirect_symref_ok = memory_address_p (QImode, tem);
474 /* See if reg+reg is a valid (and offsettable) address. */
476 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
478 tem = gen_rtx_PLUS (Pmode,
479 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
480 gen_rtx_REG (Pmode, i));
482 /* This way, we make sure that reg+reg is an offsettable address. */
483 tem = plus_constant (tem, 4);
485 if (memory_address_p (QImode, tem))
487 double_reg_address_ok = 1;
492 /* Initialize obstack for our rtl allocation. */
493 gcc_obstack_init (&reload_obstack);
494 reload_startobj = obstack_alloc (&reload_obstack, 0);
496 INIT_REG_SET (&spilled_pseudos);
497 INIT_REG_SET (&pseudos_counted);
498 VARRAY_RTX_INIT (reg_equiv_memory_loc_varray, 0, "reg_equiv_memory_loc");
501 /* List of insn chains that are currently unused. */
502 static struct insn_chain *unused_insn_chains = 0;
504 /* Allocate an empty insn_chain structure. */
506 new_insn_chain (void)
508 struct insn_chain *c;
510 if (unused_insn_chains == 0)
512 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
513 INIT_REG_SET (&c->live_throughout);
514 INIT_REG_SET (&c->dead_or_set);
518 c = unused_insn_chains;
519 unused_insn_chains = c->next;
521 c->is_caller_save_insn = 0;
522 c->need_operand_change = 0;
528 /* Small utility function to set all regs in hard reg set TO which are
529 allocated to pseudos in regset FROM. */
532 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
535 reg_set_iterator rsi;
537 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
539 int r = reg_renumber[regno];
544 /* reload_combine uses the information from
545 BASIC_BLOCK->global_live_at_start, which might still
546 contain registers that have not actually been allocated
547 since they have an equivalence. */
548 gcc_assert (reload_completed);
552 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)];
554 SET_HARD_REG_BIT (*to, r + nregs);
559 /* Replace all pseudos found in LOC with their corresponding
563 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
576 unsigned int regno = REGNO (x);
578 if (regno < FIRST_PSEUDO_REGISTER)
581 x = eliminate_regs (x, mem_mode, usage);
585 replace_pseudos_in (loc, mem_mode, usage);
589 if (reg_equiv_constant[regno])
590 *loc = reg_equiv_constant[regno];
591 else if (reg_equiv_mem[regno])
592 *loc = reg_equiv_mem[regno];
593 else if (reg_equiv_address[regno])
594 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
597 gcc_assert (!REG_P (regno_reg_rtx[regno])
598 || REGNO (regno_reg_rtx[regno]) != regno);
599 *loc = regno_reg_rtx[regno];
604 else if (code == MEM)
606 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
610 /* Process each of our operands recursively. */
611 fmt = GET_RTX_FORMAT (code);
612 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
614 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
615 else if (*fmt == 'E')
616 for (j = 0; j < XVECLEN (x, i); j++)
617 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
621 /* Global variables used by reload and its subroutines. */
623 /* Set during calculate_needs if an insn needs register elimination. */
624 static int something_needs_elimination;
625 /* Set during calculate_needs if an insn needs an operand changed. */
626 static int something_needs_operands_changed;
628 /* Nonzero means we couldn't get enough spill regs. */
631 /* Main entry point for the reload pass.
633 FIRST is the first insn of the function being compiled.
635 GLOBAL nonzero means we were called from global_alloc
636 and should attempt to reallocate any pseudoregs that we
637 displace from hard regs we will use for reloads.
638 If GLOBAL is zero, we do not have enough information to do that,
639 so any pseudo reg that is spilled must go to the stack.
641 Return value is nonzero if reload failed
642 and we must not do any more for this function. */
645 reload (rtx first, int global)
649 struct elim_table *ep;
652 /* Make sure even insns with volatile mem refs are recognizable. */
657 reload_firstobj = obstack_alloc (&reload_obstack, 0);
659 /* Make sure that the last insn in the chain
660 is not something that needs reloading. */
661 emit_note (NOTE_INSN_DELETED);
663 /* Enable find_equiv_reg to distinguish insns made by reload. */
664 reload_first_uid = get_max_uid ();
666 #ifdef SECONDARY_MEMORY_NEEDED
667 /* Initialize the secondary memory table. */
668 clear_secondary_mem ();
671 /* We don't have a stack slot for any spill reg yet. */
672 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
673 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
675 /* Initialize the save area information for caller-save, in case some
679 /* Compute which hard registers are now in use
680 as homes for pseudo registers.
681 This is done here rather than (eg) in global_alloc
682 because this point is reached even if not optimizing. */
683 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
686 /* A function that receives a nonlocal goto must save all call-saved
688 if (current_function_has_nonlocal_label)
689 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
690 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
691 regs_ever_live[i] = 1;
693 /* Find all the pseudo registers that didn't get hard regs
694 but do have known equivalent constants or memory slots.
695 These include parameters (known equivalent to parameter slots)
696 and cse'd or loop-moved constant memory addresses.
698 Record constant equivalents in reg_equiv_constant
699 so they will be substituted by find_reloads.
700 Record memory equivalents in reg_mem_equiv so they can
701 be substituted eventually by altering the REG-rtx's. */
703 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
704 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
705 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
706 reg_equiv_address = XCNEWVEC (rtx, max_regno);
707 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
708 reg_old_renumber = XCNEWVEC (short, max_regno);
709 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
710 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
711 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
713 CLEAR_HARD_REG_SET (bad_spill_regs_global);
715 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
716 to. Also find all paradoxical subregs and find largest such for
719 num_eliminable_invariants = 0;
720 for (insn = first; insn; insn = NEXT_INSN (insn))
722 rtx set = single_set (insn);
724 /* We may introduce USEs that we want to remove at the end, so
725 we'll mark them with QImode. Make sure there are no
726 previously-marked insns left by say regmove. */
727 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
728 && GET_MODE (insn) != VOIDmode)
729 PUT_MODE (insn, VOIDmode);
732 scan_paradoxical_subregs (PATTERN (insn));
734 if (set != 0 && REG_P (SET_DEST (set)))
736 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
742 i = REGNO (SET_DEST (set));
745 if (i <= LAST_VIRTUAL_REGISTER)
748 if (! function_invariant_p (x)
750 /* A function invariant is often CONSTANT_P but may
751 include a register. We promise to only pass
752 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
754 && LEGITIMATE_PIC_OPERAND_P (x)))
756 /* It can happen that a REG_EQUIV note contains a MEM
757 that is not a legitimate memory operand. As later
758 stages of reload assume that all addresses found
759 in the reg_equiv_* arrays were originally legitimate,
760 we ignore such REG_EQUIV notes. */
761 if (memory_operand (x, VOIDmode))
763 /* Always unshare the equivalence, so we can
764 substitute into this insn without touching the
766 reg_equiv_memory_loc[i] = copy_rtx (x);
768 else if (function_invariant_p (x))
770 if (GET_CODE (x) == PLUS)
772 /* This is PLUS of frame pointer and a constant,
773 and might be shared. Unshare it. */
774 reg_equiv_invariant[i] = copy_rtx (x);
775 num_eliminable_invariants++;
777 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
779 reg_equiv_invariant[i] = x;
780 num_eliminable_invariants++;
782 else if (LEGITIMATE_CONSTANT_P (x))
783 reg_equiv_constant[i] = x;
786 reg_equiv_memory_loc[i]
787 = force_const_mem (GET_MODE (SET_DEST (set)), x);
788 if (! reg_equiv_memory_loc[i])
789 reg_equiv_init[i] = NULL_RTX;
794 reg_equiv_init[i] = NULL_RTX;
799 reg_equiv_init[i] = NULL_RTX;
804 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
805 if (reg_equiv_init[i])
807 fprintf (dump_file, "init_insns for %u: ", i);
808 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
809 fprintf (dump_file, "\n");
814 first_label_num = get_first_label_num ();
815 num_labels = max_label_num () - first_label_num;
817 /* Allocate the tables used to store offset information at labels. */
818 /* We used to use alloca here, but the size of what it would try to
819 allocate would occasionally cause it to exceed the stack limit and
820 cause a core dump. */
821 offsets_known_at = XNEWVEC (char, num_labels);
822 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
824 /* Alter each pseudo-reg rtx to contain its hard reg number.
825 Assign stack slots to the pseudos that lack hard regs or equivalents.
826 Do not touch virtual registers. */
828 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
831 /* If we have some registers we think can be eliminated, scan all insns to
832 see if there is an insn that sets one of these registers to something
833 other than itself plus a constant. If so, the register cannot be
834 eliminated. Doing this scan here eliminates an extra pass through the
835 main reload loop in the most common case where register elimination
837 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
839 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
841 maybe_fix_stack_asms ();
843 insns_need_reload = 0;
844 something_needs_elimination = 0;
846 /* Initialize to -1, which means take the first spill register. */
849 /* Spill any hard regs that we know we can't eliminate. */
850 CLEAR_HARD_REG_SET (used_spill_regs);
851 /* There can be multiple ways to eliminate a register;
852 they should be listed adjacently.
853 Elimination for any register fails only if all possible ways fail. */
854 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
857 int can_eliminate = 0;
860 can_eliminate |= ep->can_eliminate;
863 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
865 spill_hard_reg (from, 1);
868 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
869 if (frame_pointer_needed)
870 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
872 finish_spills (global);
874 /* From now on, we may need to generate moves differently. We may also
875 allow modifications of insns which cause them to not be recognized.
876 Any such modifications will be cleaned up during reload itself. */
877 reload_in_progress = 1;
879 /* This loop scans the entire function each go-round
880 and repeats until one repetition spills no additional hard regs. */
883 int something_changed;
886 HOST_WIDE_INT starting_frame_size;
888 /* Round size of stack frame to stack_alignment_needed. This must be done
889 here because the stack size may be a part of the offset computation
890 for register elimination, and there might have been new stack slots
891 created in the last iteration of this loop. */
892 if (cfun->stack_alignment_needed)
893 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
895 starting_frame_size = get_frame_size ();
897 set_initial_elim_offsets ();
898 set_initial_label_offsets ();
900 /* For each pseudo register that has an equivalent location defined,
901 try to eliminate any eliminable registers (such as the frame pointer)
902 assuming initial offsets for the replacement register, which
905 If the resulting location is directly addressable, substitute
906 the MEM we just got directly for the old REG.
908 If it is not addressable but is a constant or the sum of a hard reg
909 and constant, it is probably not addressable because the constant is
910 out of range, in that case record the address; we will generate
911 hairy code to compute the address in a register each time it is
912 needed. Similarly if it is a hard register, but one that is not
913 valid as an address register.
915 If the location is not addressable, but does not have one of the
916 above forms, assign a stack slot. We have to do this to avoid the
917 potential of producing lots of reloads if, e.g., a location involves
918 a pseudo that didn't get a hard register and has an equivalent memory
919 location that also involves a pseudo that didn't get a hard register.
921 Perhaps at some point we will improve reload_when_needed handling
922 so this problem goes away. But that's very hairy. */
924 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
925 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
927 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
929 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
931 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
932 else if (CONSTANT_P (XEXP (x, 0))
933 || (REG_P (XEXP (x, 0))
934 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
935 || (GET_CODE (XEXP (x, 0)) == PLUS
936 && REG_P (XEXP (XEXP (x, 0), 0))
937 && (REGNO (XEXP (XEXP (x, 0), 0))
938 < FIRST_PSEUDO_REGISTER)
939 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
940 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
943 /* Make a new stack slot. Then indicate that something
944 changed so we go back and recompute offsets for
945 eliminable registers because the allocation of memory
946 below might change some offset. reg_equiv_{mem,address}
947 will be set up for this pseudo on the next pass around
949 reg_equiv_memory_loc[i] = 0;
950 reg_equiv_init[i] = 0;
955 if (caller_save_needed)
958 /* If we allocated another stack slot, redo elimination bookkeeping. */
959 if (starting_frame_size != get_frame_size ())
962 if (caller_save_needed)
964 save_call_clobbered_regs ();
965 /* That might have allocated new insn_chain structures. */
966 reload_firstobj = obstack_alloc (&reload_obstack, 0);
969 calculate_needs_all_insns (global);
971 CLEAR_REG_SET (&spilled_pseudos);
974 something_changed = 0;
976 /* If we allocated any new memory locations, make another pass
977 since it might have changed elimination offsets. */
978 if (starting_frame_size != get_frame_size ())
979 something_changed = 1;
981 /* Even if the frame size remained the same, we might still have
982 changed elimination offsets, e.g. if find_reloads called
983 force_const_mem requiring the back end to allocate a constant
984 pool base register that needs to be saved on the stack. */
985 else if (!verify_initial_elim_offsets ())
986 something_changed = 1;
989 HARD_REG_SET to_spill;
990 CLEAR_HARD_REG_SET (to_spill);
991 update_eliminables (&to_spill);
992 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
993 if (TEST_HARD_REG_BIT (to_spill, i))
995 spill_hard_reg (i, 1);
998 /* Regardless of the state of spills, if we previously had
999 a register that we thought we could eliminate, but now can
1000 not eliminate, we must run another pass.
1002 Consider pseudos which have an entry in reg_equiv_* which
1003 reference an eliminable register. We must make another pass
1004 to update reg_equiv_* so that we do not substitute in the
1005 old value from when we thought the elimination could be
1007 something_changed = 1;
1011 select_reload_regs ();
1015 if (insns_need_reload != 0 || did_spill)
1016 something_changed |= finish_spills (global);
1018 if (! something_changed)
1021 if (caller_save_needed)
1022 delete_caller_save_insns ();
1024 obstack_free (&reload_obstack, reload_firstobj);
1027 /* If global-alloc was run, notify it of any register eliminations we have
1030 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1031 if (ep->can_eliminate)
1032 mark_elimination (ep->from, ep->to);
1034 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1035 If that insn didn't set the register (i.e., it copied the register to
1036 memory), just delete that insn instead of the equivalencing insn plus
1037 anything now dead. If we call delete_dead_insn on that insn, we may
1038 delete the insn that actually sets the register if the register dies
1039 there and that is incorrect. */
1041 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1043 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1046 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1048 rtx equiv_insn = XEXP (list, 0);
1050 /* If we already deleted the insn or if it may trap, we can't
1051 delete it. The latter case shouldn't happen, but can
1052 if an insn has a variable address, gets a REG_EH_REGION
1053 note added to it, and then gets converted into a load
1054 from a constant address. */
1055 if (NOTE_P (equiv_insn)
1056 || can_throw_internal (equiv_insn))
1058 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1059 delete_dead_insn (equiv_insn);
1061 SET_INSN_DELETED (equiv_insn);
1066 /* Use the reload registers where necessary
1067 by generating move instructions to move the must-be-register
1068 values into or out of the reload registers. */
1070 if (insns_need_reload != 0 || something_needs_elimination
1071 || something_needs_operands_changed)
1073 HOST_WIDE_INT old_frame_size = get_frame_size ();
1075 reload_as_needed (global);
1077 gcc_assert (old_frame_size == get_frame_size ());
1079 gcc_assert (verify_initial_elim_offsets ());
1082 /* If we were able to eliminate the frame pointer, show that it is no
1083 longer live at the start of any basic block. If it ls live by
1084 virtue of being in a pseudo, that pseudo will be marked live
1085 and hence the frame pointer will be known to be live via that
1088 if (! frame_pointer_needed)
1090 CLEAR_REGNO_REG_SET (bb->il.rtl->global_live_at_start,
1091 HARD_FRAME_POINTER_REGNUM);
1093 /* Come here (with failure set nonzero) if we can't get enough spill
1097 CLEAR_REG_SET (&spilled_pseudos);
1098 reload_in_progress = 0;
1100 /* Now eliminate all pseudo regs by modifying them into
1101 their equivalent memory references.
1102 The REG-rtx's for the pseudos are modified in place,
1103 so all insns that used to refer to them now refer to memory.
1105 For a reg that has a reg_equiv_address, all those insns
1106 were changed by reloading so that no insns refer to it any longer;
1107 but the DECL_RTL of a variable decl may refer to it,
1108 and if so this causes the debugging info to mention the variable. */
1110 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1114 if (reg_equiv_mem[i])
1115 addr = XEXP (reg_equiv_mem[i], 0);
1117 if (reg_equiv_address[i])
1118 addr = reg_equiv_address[i];
1122 if (reg_renumber[i] < 0)
1124 rtx reg = regno_reg_rtx[i];
1126 REG_USERVAR_P (reg) = 0;
1127 PUT_CODE (reg, MEM);
1128 XEXP (reg, 0) = addr;
1129 if (reg_equiv_memory_loc[i])
1130 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1133 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1134 MEM_ATTRS (reg) = 0;
1136 MEM_NOTRAP_P (reg) = 1;
1138 else if (reg_equiv_mem[i])
1139 XEXP (reg_equiv_mem[i], 0) = addr;
1143 /* We must set reload_completed now since the cleanup_subreg_operands call
1144 below will re-recognize each insn and reload may have generated insns
1145 which are only valid during and after reload. */
1146 reload_completed = 1;
1148 /* Make a pass over all the insns and delete all USEs which we inserted
1149 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1150 notes. Delete all CLOBBER insns, except those that refer to the return
1151 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1152 from misarranging variable-array code, and simplify (subreg (reg))
1153 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1154 are no longer useful or accurate. Strip and regenerate REG_INC notes
1155 that may have been moved around. */
1157 for (insn = first; insn; insn = NEXT_INSN (insn))
1163 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1164 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1166 if ((GET_CODE (PATTERN (insn)) == USE
1167 /* We mark with QImode USEs introduced by reload itself. */
1168 && (GET_MODE (insn) == QImode
1169 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1170 || (GET_CODE (PATTERN (insn)) == CLOBBER
1171 && (!MEM_P (XEXP (PATTERN (insn), 0))
1172 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1173 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1174 && XEXP (XEXP (PATTERN (insn), 0), 0)
1175 != stack_pointer_rtx))
1176 && (!REG_P (XEXP (PATTERN (insn), 0))
1177 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1183 /* Some CLOBBERs may survive until here and still reference unassigned
1184 pseudos with const equivalent, which may in turn cause ICE in later
1185 passes if the reference remains in place. */
1186 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1187 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1188 VOIDmode, PATTERN (insn));
1190 /* Discard obvious no-ops, even without -O. This optimization
1191 is fast and doesn't interfere with debugging. */
1192 if (NONJUMP_INSN_P (insn)
1193 && GET_CODE (PATTERN (insn)) == SET
1194 && REG_P (SET_SRC (PATTERN (insn)))
1195 && REG_P (SET_DEST (PATTERN (insn)))
1196 && (REGNO (SET_SRC (PATTERN (insn)))
1197 == REGNO (SET_DEST (PATTERN (insn)))))
1203 pnote = ®_NOTES (insn);
1206 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1207 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1208 || REG_NOTE_KIND (*pnote) == REG_INC
1209 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1210 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1211 *pnote = XEXP (*pnote, 1);
1213 pnote = &XEXP (*pnote, 1);
1217 add_auto_inc_notes (insn, PATTERN (insn));
1220 /* And simplify (subreg (reg)) if it appears as an operand. */
1221 cleanup_subreg_operands (insn);
1224 /* If we are doing stack checking, give a warning if this function's
1225 frame size is larger than we expect. */
1226 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1228 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1229 static int verbose_warned = 0;
1231 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1232 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1233 size += UNITS_PER_WORD;
1235 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1237 warning (0, "frame size too large for reliable stack checking");
1238 if (! verbose_warned)
1240 warning (0, "try reducing the number of local variables");
1246 /* Indicate that we no longer have known memory locations or constants. */
1247 if (reg_equiv_constant)
1248 free (reg_equiv_constant);
1249 if (reg_equiv_invariant)
1250 free (reg_equiv_invariant);
1251 reg_equiv_constant = 0;
1252 reg_equiv_invariant = 0;
1253 VARRAY_GROW (reg_equiv_memory_loc_varray, 0);
1254 reg_equiv_memory_loc = 0;
1256 if (offsets_known_at)
1257 free (offsets_known_at);
1261 free (reg_equiv_mem);
1263 free (reg_equiv_address);
1264 free (reg_max_ref_width);
1265 free (reg_old_renumber);
1266 free (pseudo_previous_regs);
1267 free (pseudo_forbidden_regs);
1269 CLEAR_HARD_REG_SET (used_spill_regs);
1270 for (i = 0; i < n_spills; i++)
1271 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1273 /* Free all the insn_chain structures at once. */
1274 obstack_free (&reload_obstack, reload_startobj);
1275 unused_insn_chains = 0;
1276 fixup_abnormal_edges ();
1278 /* Replacing pseudos with their memory equivalents might have
1279 created shared rtx. Subsequent passes would get confused
1280 by this, so unshare everything here. */
1281 unshare_all_rtl_again (first);
1283 #ifdef STACK_BOUNDARY
1284 /* init_emit has set the alignment of the hard frame pointer
1285 to STACK_BOUNDARY. It is very likely no longer valid if
1286 the hard frame pointer was used for register allocation. */
1287 if (!frame_pointer_needed)
1288 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1294 /* Yet another special case. Unfortunately, reg-stack forces people to
1295 write incorrect clobbers in asm statements. These clobbers must not
1296 cause the register to appear in bad_spill_regs, otherwise we'll call
1297 fatal_insn later. We clear the corresponding regnos in the live
1298 register sets to avoid this.
1299 The whole thing is rather sick, I'm afraid. */
1302 maybe_fix_stack_asms (void)
1305 const char *constraints[MAX_RECOG_OPERANDS];
1306 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1307 struct insn_chain *chain;
1309 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1312 HARD_REG_SET clobbered, allowed;
1315 if (! INSN_P (chain->insn)
1316 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1318 pat = PATTERN (chain->insn);
1319 if (GET_CODE (pat) != PARALLEL)
1322 CLEAR_HARD_REG_SET (clobbered);
1323 CLEAR_HARD_REG_SET (allowed);
1325 /* First, make a mask of all stack regs that are clobbered. */
1326 for (i = 0; i < XVECLEN (pat, 0); i++)
1328 rtx t = XVECEXP (pat, 0, i);
1329 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1330 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1333 /* Get the operand values and constraints out of the insn. */
1334 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1335 constraints, operand_mode);
1337 /* For every operand, see what registers are allowed. */
1338 for (i = 0; i < noperands; i++)
1340 const char *p = constraints[i];
1341 /* For every alternative, we compute the class of registers allowed
1342 for reloading in CLS, and merge its contents into the reg set
1344 int cls = (int) NO_REGS;
1350 if (c == '\0' || c == ',' || c == '#')
1352 /* End of one alternative - mark the regs in the current
1353 class, and reset the class. */
1354 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1360 } while (c != '\0' && c != ',');
1368 case '=': case '+': case '*': case '%': case '?': case '!':
1369 case '0': case '1': case '2': case '3': case '4': case 'm':
1370 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1371 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1372 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1377 cls = (int) reg_class_subunion[cls]
1378 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1383 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1387 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1388 cls = (int) reg_class_subunion[cls]
1389 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1391 cls = (int) reg_class_subunion[cls]
1392 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1394 p += CONSTRAINT_LEN (c, p);
1397 /* Those of the registers which are clobbered, but allowed by the
1398 constraints, must be usable as reload registers. So clear them
1399 out of the life information. */
1400 AND_HARD_REG_SET (allowed, clobbered);
1401 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1402 if (TEST_HARD_REG_BIT (allowed, i))
1404 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1405 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1412 /* Copy the global variables n_reloads and rld into the corresponding elts
1415 copy_reloads (struct insn_chain *chain)
1417 chain->n_reloads = n_reloads;
1418 chain->rld = obstack_alloc (&reload_obstack,
1419 n_reloads * sizeof (struct reload));
1420 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1421 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1424 /* Walk the chain of insns, and determine for each whether it needs reloads
1425 and/or eliminations. Build the corresponding insns_need_reload list, and
1426 set something_needs_elimination as appropriate. */
1428 calculate_needs_all_insns (int global)
1430 struct insn_chain **pprev_reload = &insns_need_reload;
1431 struct insn_chain *chain, *next = 0;
1433 something_needs_elimination = 0;
1435 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1436 for (chain = reload_insn_chain; chain != 0; chain = next)
1438 rtx insn = chain->insn;
1442 /* Clear out the shortcuts. */
1443 chain->n_reloads = 0;
1444 chain->need_elim = 0;
1445 chain->need_reload = 0;
1446 chain->need_operand_change = 0;
1448 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1449 include REG_LABEL), we need to see what effects this has on the
1450 known offsets at labels. */
1452 if (LABEL_P (insn) || JUMP_P (insn)
1453 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1454 set_label_offsets (insn, insn, 0);
1458 rtx old_body = PATTERN (insn);
1459 int old_code = INSN_CODE (insn);
1460 rtx old_notes = REG_NOTES (insn);
1461 int did_elimination = 0;
1462 int operands_changed = 0;
1463 rtx set = single_set (insn);
1465 /* Skip insns that only set an equivalence. */
1466 if (set && REG_P (SET_DEST (set))
1467 && reg_renumber[REGNO (SET_DEST (set))] < 0
1468 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1469 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1470 && reg_equiv_init[REGNO (SET_DEST (set))])
1473 /* If needed, eliminate any eliminable registers. */
1474 if (num_eliminable || num_eliminable_invariants)
1475 did_elimination = eliminate_regs_in_insn (insn, 0);
1477 /* Analyze the instruction. */
1478 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1479 global, spill_reg_order);
1481 /* If a no-op set needs more than one reload, this is likely
1482 to be something that needs input address reloads. We
1483 can't get rid of this cleanly later, and it is of no use
1484 anyway, so discard it now.
1485 We only do this when expensive_optimizations is enabled,
1486 since this complements reload inheritance / output
1487 reload deletion, and it can make debugging harder. */
1488 if (flag_expensive_optimizations && n_reloads > 1)
1490 rtx set = single_set (insn);
1492 && SET_SRC (set) == SET_DEST (set)
1493 && REG_P (SET_SRC (set))
1494 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1497 /* Delete it from the reload chain. */
1499 chain->prev->next = next;
1501 reload_insn_chain = next;
1503 next->prev = chain->prev;
1504 chain->next = unused_insn_chains;
1505 unused_insn_chains = chain;
1510 update_eliminable_offsets ();
1512 /* Remember for later shortcuts which insns had any reloads or
1513 register eliminations. */
1514 chain->need_elim = did_elimination;
1515 chain->need_reload = n_reloads > 0;
1516 chain->need_operand_change = operands_changed;
1518 /* Discard any register replacements done. */
1519 if (did_elimination)
1521 obstack_free (&reload_obstack, reload_insn_firstobj);
1522 PATTERN (insn) = old_body;
1523 INSN_CODE (insn) = old_code;
1524 REG_NOTES (insn) = old_notes;
1525 something_needs_elimination = 1;
1528 something_needs_operands_changed |= operands_changed;
1532 copy_reloads (chain);
1533 *pprev_reload = chain;
1534 pprev_reload = &chain->next_need_reload;
1541 /* Comparison function for qsort to decide which of two reloads
1542 should be handled first. *P1 and *P2 are the reload numbers. */
1545 reload_reg_class_lower (const void *r1p, const void *r2p)
1547 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1550 /* Consider required reloads before optional ones. */
1551 t = rld[r1].optional - rld[r2].optional;
1555 /* Count all solitary classes before non-solitary ones. */
1556 t = ((reg_class_size[(int) rld[r2].class] == 1)
1557 - (reg_class_size[(int) rld[r1].class] == 1));
1561 /* Aside from solitaires, consider all multi-reg groups first. */
1562 t = rld[r2].nregs - rld[r1].nregs;
1566 /* Consider reloads in order of increasing reg-class number. */
1567 t = (int) rld[r1].class - (int) rld[r2].class;
1571 /* If reloads are equally urgent, sort by reload number,
1572 so that the results of qsort leave nothing to chance. */
1576 /* The cost of spilling each hard reg. */
1577 static int spill_cost[FIRST_PSEUDO_REGISTER];
1579 /* When spilling multiple hard registers, we use SPILL_COST for the first
1580 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1581 only the first hard reg for a multi-reg pseudo. */
1582 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1584 /* Update the spill cost arrays, considering that pseudo REG is live. */
1587 count_pseudo (int reg)
1589 int freq = REG_FREQ (reg);
1590 int r = reg_renumber[reg];
1593 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1594 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1597 SET_REGNO_REG_SET (&pseudos_counted, reg);
1599 gcc_assert (r >= 0);
1601 spill_add_cost[r] += freq;
1603 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1605 spill_cost[r + nregs] += freq;
1608 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1609 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1612 order_regs_for_reload (struct insn_chain *chain)
1615 HARD_REG_SET used_by_pseudos;
1616 HARD_REG_SET used_by_pseudos2;
1617 reg_set_iterator rsi;
1619 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1621 memset (spill_cost, 0, sizeof spill_cost);
1622 memset (spill_add_cost, 0, sizeof spill_add_cost);
1624 /* Count number of uses of each hard reg by pseudo regs allocated to it
1625 and then order them by decreasing use. First exclude hard registers
1626 that are live in or across this insn. */
1628 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1629 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1630 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1631 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1633 /* Now find out which pseudos are allocated to it, and update
1635 CLEAR_REG_SET (&pseudos_counted);
1637 EXECUTE_IF_SET_IN_REG_SET
1638 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1642 EXECUTE_IF_SET_IN_REG_SET
1643 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1647 CLEAR_REG_SET (&pseudos_counted);
1650 /* Vector of reload-numbers showing the order in which the reloads should
1652 static short reload_order[MAX_RELOADS];
1654 /* This is used to keep track of the spill regs used in one insn. */
1655 static HARD_REG_SET used_spill_regs_local;
1657 /* We decided to spill hard register SPILLED, which has a size of
1658 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1659 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1660 update SPILL_COST/SPILL_ADD_COST. */
1663 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1665 int r = reg_renumber[reg];
1666 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1668 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1669 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1672 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1674 spill_add_cost[r] -= REG_FREQ (reg);
1676 spill_cost[r + nregs] -= REG_FREQ (reg);
1679 /* Find reload register to use for reload number ORDER. */
1682 find_reg (struct insn_chain *chain, int order)
1684 int rnum = reload_order[order];
1685 struct reload *rl = rld + rnum;
1686 int best_cost = INT_MAX;
1690 HARD_REG_SET not_usable;
1691 HARD_REG_SET used_by_other_reload;
1692 reg_set_iterator rsi;
1694 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1695 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1696 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1698 CLEAR_HARD_REG_SET (used_by_other_reload);
1699 for (k = 0; k < order; k++)
1701 int other = reload_order[k];
1703 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1704 for (j = 0; j < rld[other].nregs; j++)
1705 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1708 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1710 unsigned int regno = i;
1712 if (! TEST_HARD_REG_BIT (not_usable, regno)
1713 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1714 && HARD_REGNO_MODE_OK (regno, rl->mode))
1716 int this_cost = spill_cost[regno];
1718 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1720 for (j = 1; j < this_nregs; j++)
1722 this_cost += spill_add_cost[regno + j];
1723 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1724 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1729 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1731 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1733 if (this_cost < best_cost
1734 /* Among registers with equal cost, prefer caller-saved ones, or
1735 use REG_ALLOC_ORDER if it is defined. */
1736 || (this_cost == best_cost
1737 #ifdef REG_ALLOC_ORDER
1738 && (inv_reg_alloc_order[regno]
1739 < inv_reg_alloc_order[best_reg])
1741 && call_used_regs[regno]
1742 && ! call_used_regs[best_reg]
1747 best_cost = this_cost;
1755 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1757 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1758 rl->regno = best_reg;
1760 EXECUTE_IF_SET_IN_REG_SET
1761 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1763 count_spilled_pseudo (best_reg, rl->nregs, j);
1766 EXECUTE_IF_SET_IN_REG_SET
1767 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1769 count_spilled_pseudo (best_reg, rl->nregs, j);
1772 for (i = 0; i < rl->nregs; i++)
1774 gcc_assert (spill_cost[best_reg + i] == 0);
1775 gcc_assert (spill_add_cost[best_reg + i] == 0);
1776 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1781 /* Find more reload regs to satisfy the remaining need of an insn, which
1783 Do it by ascending class number, since otherwise a reg
1784 might be spilled for a big class and might fail to count
1785 for a smaller class even though it belongs to that class. */
1788 find_reload_regs (struct insn_chain *chain)
1792 /* In order to be certain of getting the registers we need,
1793 we must sort the reloads into order of increasing register class.
1794 Then our grabbing of reload registers will parallel the process
1795 that provided the reload registers. */
1796 for (i = 0; i < chain->n_reloads; i++)
1798 /* Show whether this reload already has a hard reg. */
1799 if (chain->rld[i].reg_rtx)
1801 int regno = REGNO (chain->rld[i].reg_rtx);
1802 chain->rld[i].regno = regno;
1804 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1807 chain->rld[i].regno = -1;
1808 reload_order[i] = i;
1811 n_reloads = chain->n_reloads;
1812 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1814 CLEAR_HARD_REG_SET (used_spill_regs_local);
1817 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1819 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1821 /* Compute the order of preference for hard registers to spill. */
1823 order_regs_for_reload (chain);
1825 for (i = 0; i < n_reloads; i++)
1827 int r = reload_order[i];
1829 /* Ignore reloads that got marked inoperative. */
1830 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1831 && ! rld[r].optional
1832 && rld[r].regno == -1)
1833 if (! find_reg (chain, i))
1836 fprintf(dump_file, "reload failure for reload %d\n", r);
1837 spill_failure (chain->insn, rld[r].class);
1843 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1844 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1846 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1850 select_reload_regs (void)
1852 struct insn_chain *chain;
1854 /* Try to satisfy the needs for each insn. */
1855 for (chain = insns_need_reload; chain != 0;
1856 chain = chain->next_need_reload)
1857 find_reload_regs (chain);
1860 /* Delete all insns that were inserted by emit_caller_save_insns during
1863 delete_caller_save_insns (void)
1865 struct insn_chain *c = reload_insn_chain;
1869 while (c != 0 && c->is_caller_save_insn)
1871 struct insn_chain *next = c->next;
1874 if (c == reload_insn_chain)
1875 reload_insn_chain = next;
1879 next->prev = c->prev;
1881 c->prev->next = next;
1882 c->next = unused_insn_chains;
1883 unused_insn_chains = c;
1891 /* Handle the failure to find a register to spill.
1892 INSN should be one of the insns which needed this particular spill reg. */
1895 spill_failure (rtx insn, enum reg_class class)
1897 if (asm_noperands (PATTERN (insn)) >= 0)
1898 error_for_asm (insn, "can't find a register in class %qs while "
1899 "reloading %<asm%>",
1900 reg_class_names[class]);
1903 error ("unable to find a register to spill in class %qs",
1904 reg_class_names[class]);
1908 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
1909 debug_reload_to_stream (dump_file);
1911 fatal_insn ("this is the insn:", insn);
1915 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1916 data that is dead in INSN. */
1919 delete_dead_insn (rtx insn)
1921 rtx prev = prev_real_insn (insn);
1924 /* If the previous insn sets a register that dies in our insn, delete it
1926 if (prev && GET_CODE (PATTERN (prev)) == SET
1927 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
1928 && reg_mentioned_p (prev_dest, PATTERN (insn))
1929 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1930 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1931 delete_dead_insn (prev);
1933 SET_INSN_DELETED (insn);
1936 /* Modify the home of pseudo-reg I.
1937 The new home is present in reg_renumber[I].
1939 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1940 or it may be -1, meaning there is none or it is not relevant.
1941 This is used so that all pseudos spilled from a given hard reg
1942 can share one stack slot. */
1945 alter_reg (int i, int from_reg)
1947 /* When outputting an inline function, this can happen
1948 for a reg that isn't actually used. */
1949 if (regno_reg_rtx[i] == 0)
1952 /* If the reg got changed to a MEM at rtl-generation time,
1954 if (!REG_P (regno_reg_rtx[i]))
1957 /* Modify the reg-rtx to contain the new hard reg
1958 number or else to contain its pseudo reg number. */
1959 REGNO (regno_reg_rtx[i])
1960 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1962 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1963 allocate a stack slot for it. */
1965 if (reg_renumber[i] < 0
1966 && REG_N_REFS (i) > 0
1967 && reg_equiv_constant[i] == 0
1968 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
1969 && reg_equiv_memory_loc[i] == 0)
1972 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1973 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1976 /* Each pseudo reg has an inherent size which comes from its own mode,
1977 and a total size which provides room for paradoxical subregs
1978 which refer to the pseudo reg in wider modes.
1980 We can use a slot already allocated if it provides both
1981 enough inherent space and enough total space.
1982 Otherwise, we allocate a new slot, making sure that it has no less
1983 inherent space, and no less total space, then the previous slot. */
1986 /* No known place to spill from => no slot to reuse. */
1987 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1988 inherent_size == total_size ? 0 : -1);
1989 if (BYTES_BIG_ENDIAN)
1990 /* Cancel the big-endian correction done in assign_stack_local.
1991 Get the address of the beginning of the slot.
1992 This is so we can do a big-endian correction unconditionally
1994 adjust = inherent_size - total_size;
1996 /* Nothing can alias this slot except this pseudo. */
1997 set_mem_alias_set (x, new_alias_set ());
2000 /* Reuse a stack slot if possible. */
2001 else if (spill_stack_slot[from_reg] != 0
2002 && spill_stack_slot_width[from_reg] >= total_size
2003 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2005 x = spill_stack_slot[from_reg];
2007 /* Allocate a bigger slot. */
2010 /* Compute maximum size needed, both for inherent size
2011 and for total size. */
2012 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2015 if (spill_stack_slot[from_reg])
2017 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2019 mode = GET_MODE (spill_stack_slot[from_reg]);
2020 if (spill_stack_slot_width[from_reg] > total_size)
2021 total_size = spill_stack_slot_width[from_reg];
2024 /* Make a slot with that size. */
2025 x = assign_stack_local (mode, total_size,
2026 inherent_size == total_size ? 0 : -1);
2029 /* All pseudos mapped to this slot can alias each other. */
2030 if (spill_stack_slot[from_reg])
2031 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2033 set_mem_alias_set (x, new_alias_set ());
2035 if (BYTES_BIG_ENDIAN)
2037 /* Cancel the big-endian correction done in assign_stack_local.
2038 Get the address of the beginning of the slot.
2039 This is so we can do a big-endian correction unconditionally
2041 adjust = GET_MODE_SIZE (mode) - total_size;
2044 = adjust_address_nv (x, mode_for_size (total_size
2050 spill_stack_slot[from_reg] = stack_slot;
2051 spill_stack_slot_width[from_reg] = total_size;
2054 /* On a big endian machine, the "address" of the slot
2055 is the address of the low part that fits its inherent mode. */
2056 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2057 adjust += (total_size - inherent_size);
2059 /* If we have any adjustment to make, or if the stack slot is the
2060 wrong mode, make a new stack slot. */
2061 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2063 /* If we have a decl for the original register, set it for the
2064 memory. If this is a shared MEM, make a copy. */
2065 if (REG_EXPR (regno_reg_rtx[i])
2066 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2068 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2070 /* We can do this only for the DECLs home pseudo, not for
2071 any copies of it, since otherwise when the stack slot
2072 is reused, nonoverlapping_memrefs_p might think they
2074 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2076 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2079 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2083 /* Save the stack slot for later. */
2084 reg_equiv_memory_loc[i] = x;
2088 /* Mark the slots in regs_ever_live for the hard regs
2089 used by pseudo-reg number REGNO. */
2092 mark_home_live (int regno)
2096 i = reg_renumber[regno];
2099 lim = i + hard_regno_nregs[i][PSEUDO_REGNO_MODE (regno)];
2101 regs_ever_live[i++] = 1;
2104 /* This function handles the tracking of elimination offsets around branches.
2106 X is a piece of RTL being scanned.
2108 INSN is the insn that it came from, if any.
2110 INITIAL_P is nonzero if we are to set the offset to be the initial
2111 offset and zero if we are setting the offset of the label to be the
2115 set_label_offsets (rtx x, rtx insn, int initial_p)
2117 enum rtx_code code = GET_CODE (x);
2120 struct elim_table *p;
2125 if (LABEL_REF_NONLOCAL_P (x))
2130 /* ... fall through ... */
2133 /* If we know nothing about this label, set the desired offsets. Note
2134 that this sets the offset at a label to be the offset before a label
2135 if we don't know anything about the label. This is not correct for
2136 the label after a BARRIER, but is the best guess we can make. If
2137 we guessed wrong, we will suppress an elimination that might have
2138 been possible had we been able to guess correctly. */
2140 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2142 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2143 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2144 = (initial_p ? reg_eliminate[i].initial_offset
2145 : reg_eliminate[i].offset);
2146 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2149 /* Otherwise, if this is the definition of a label and it is
2150 preceded by a BARRIER, set our offsets to the known offset of
2154 && (tem = prev_nonnote_insn (insn)) != 0
2156 set_offsets_for_label (insn);
2158 /* If neither of the above cases is true, compare each offset
2159 with those previously recorded and suppress any eliminations
2160 where the offsets disagree. */
2162 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2163 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2164 != (initial_p ? reg_eliminate[i].initial_offset
2165 : reg_eliminate[i].offset))
2166 reg_eliminate[i].can_eliminate = 0;
2171 set_label_offsets (PATTERN (insn), insn, initial_p);
2173 /* ... fall through ... */
2177 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2178 and hence must have all eliminations at their initial offsets. */
2179 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2180 if (REG_NOTE_KIND (tem) == REG_LABEL)
2181 set_label_offsets (XEXP (tem, 0), insn, 1);
2187 /* Each of the labels in the parallel or address vector must be
2188 at their initial offsets. We want the first field for PARALLEL
2189 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2191 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2192 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2197 /* We only care about setting PC. If the source is not RETURN,
2198 IF_THEN_ELSE, or a label, disable any eliminations not at
2199 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2200 isn't one of those possibilities. For branches to a label,
2201 call ourselves recursively.
2203 Note that this can disable elimination unnecessarily when we have
2204 a non-local goto since it will look like a non-constant jump to
2205 someplace in the current function. This isn't a significant
2206 problem since such jumps will normally be when all elimination
2207 pairs are back to their initial offsets. */
2209 if (SET_DEST (x) != pc_rtx)
2212 switch (GET_CODE (SET_SRC (x)))
2219 set_label_offsets (SET_SRC (x), insn, initial_p);
2223 tem = XEXP (SET_SRC (x), 1);
2224 if (GET_CODE (tem) == LABEL_REF)
2225 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2226 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2229 tem = XEXP (SET_SRC (x), 2);
2230 if (GET_CODE (tem) == LABEL_REF)
2231 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2232 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2240 /* If we reach here, all eliminations must be at their initial
2241 offset because we are doing a jump to a variable address. */
2242 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2243 if (p->offset != p->initial_offset)
2244 p->can_eliminate = 0;
2252 /* Scan X and replace any eliminable registers (such as fp) with a
2253 replacement (such as sp), plus an offset.
2255 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2256 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2257 MEM, we are allowed to replace a sum of a register and the constant zero
2258 with the register, which we cannot do outside a MEM. In addition, we need
2259 to record the fact that a register is referenced outside a MEM.
2261 If INSN is an insn, it is the insn containing X. If we replace a REG
2262 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2263 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2264 the REG is being modified.
2266 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2267 That's used when we eliminate in expressions stored in notes.
2268 This means, do not set ref_outside_mem even if the reference
2271 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2272 replacements done assuming all offsets are at their initial values. If
2273 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2274 encounter, return the actual location so that find_reloads will do
2275 the proper thing. */
2278 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2279 bool may_use_invariant)
2281 enum rtx_code code = GET_CODE (x);
2282 struct elim_table *ep;
2289 if (! current_function_decl)
2311 /* First handle the case where we encounter a bare register that
2312 is eliminable. Replace it with a PLUS. */
2313 if (regno < FIRST_PSEUDO_REGISTER)
2315 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2317 if (ep->from_rtx == x && ep->can_eliminate)
2318 return plus_constant (ep->to_rtx, ep->previous_offset);
2321 else if (reg_renumber && reg_renumber[regno] < 0
2322 && reg_equiv_invariant && reg_equiv_invariant[regno])
2324 if (may_use_invariant)
2325 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2326 mem_mode, insn, true);
2327 /* There exists at least one use of REGNO that cannot be
2328 eliminated. Prevent the defining insn from being deleted. */
2329 reg_equiv_init[regno] = NULL_RTX;
2330 alter_reg (regno, -1);
2334 /* You might think handling MINUS in a manner similar to PLUS is a
2335 good idea. It is not. It has been tried multiple times and every
2336 time the change has had to have been reverted.
2338 Other parts of reload know a PLUS is special (gen_reload for example)
2339 and require special code to handle code a reloaded PLUS operand.
2341 Also consider backends where the flags register is clobbered by a
2342 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2343 lea instruction comes to mind). If we try to reload a MINUS, we
2344 may kill the flags register that was holding a useful value.
2346 So, please before trying to handle MINUS, consider reload as a
2347 whole instead of this little section as well as the backend issues. */
2349 /* If this is the sum of an eliminable register and a constant, rework
2351 if (REG_P (XEXP (x, 0))
2352 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2353 && CONSTANT_P (XEXP (x, 1)))
2355 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2357 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2359 /* The only time we want to replace a PLUS with a REG (this
2360 occurs when the constant operand of the PLUS is the negative
2361 of the offset) is when we are inside a MEM. We won't want
2362 to do so at other times because that would change the
2363 structure of the insn in a way that reload can't handle.
2364 We special-case the commonest situation in
2365 eliminate_regs_in_insn, so just replace a PLUS with a
2366 PLUS here, unless inside a MEM. */
2367 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2368 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2371 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2372 plus_constant (XEXP (x, 1),
2373 ep->previous_offset));
2376 /* If the register is not eliminable, we are done since the other
2377 operand is a constant. */
2381 /* If this is part of an address, we want to bring any constant to the
2382 outermost PLUS. We will do this by doing register replacement in
2383 our operands and seeing if a constant shows up in one of them.
2385 Note that there is no risk of modifying the structure of the insn,
2386 since we only get called for its operands, thus we are either
2387 modifying the address inside a MEM, or something like an address
2388 operand of a load-address insn. */
2391 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2392 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2394 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2396 /* If one side is a PLUS and the other side is a pseudo that
2397 didn't get a hard register but has a reg_equiv_constant,
2398 we must replace the constant here since it may no longer
2399 be in the position of any operand. */
2400 if (GET_CODE (new0) == PLUS && REG_P (new1)
2401 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2402 && reg_renumber[REGNO (new1)] < 0
2403 && reg_equiv_constant != 0
2404 && reg_equiv_constant[REGNO (new1)] != 0)
2405 new1 = reg_equiv_constant[REGNO (new1)];
2406 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2407 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2408 && reg_renumber[REGNO (new0)] < 0
2409 && reg_equiv_constant[REGNO (new0)] != 0)
2410 new0 = reg_equiv_constant[REGNO (new0)];
2412 new = form_sum (new0, new1);
2414 /* As above, if we are not inside a MEM we do not want to
2415 turn a PLUS into something else. We might try to do so here
2416 for an addition of 0 if we aren't optimizing. */
2417 if (! mem_mode && GET_CODE (new) != PLUS)
2418 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2426 /* If this is the product of an eliminable register and a
2427 constant, apply the distribute law and move the constant out
2428 so that we have (plus (mult ..) ..). This is needed in order
2429 to keep load-address insns valid. This case is pathological.
2430 We ignore the possibility of overflow here. */
2431 if (REG_P (XEXP (x, 0))
2432 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2433 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2434 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2436 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2439 /* Refs inside notes don't count for this purpose. */
2440 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2441 || GET_CODE (insn) == INSN_LIST)))
2442 ep->ref_outside_mem = 1;
2445 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2446 ep->previous_offset * INTVAL (XEXP (x, 1)));
2449 /* ... fall through ... */
2453 /* See comments before PLUS about handling MINUS. */
2455 case DIV: case UDIV:
2456 case MOD: case UMOD:
2457 case AND: case IOR: case XOR:
2458 case ROTATERT: case ROTATE:
2459 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2461 case GE: case GT: case GEU: case GTU:
2462 case LE: case LT: case LEU: case LTU:
2464 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2465 rtx new1 = XEXP (x, 1)
2466 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2468 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2469 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2474 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2477 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2478 if (new != XEXP (x, 0))
2480 /* If this is a REG_DEAD note, it is not valid anymore.
2481 Using the eliminated version could result in creating a
2482 REG_DEAD note for the stack or frame pointer. */
2483 if (GET_MODE (x) == REG_DEAD)
2485 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2488 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2492 /* ... fall through ... */
2495 /* Now do eliminations in the rest of the chain. If this was
2496 an EXPR_LIST, this might result in allocating more memory than is
2497 strictly needed, but it simplifies the code. */
2500 new = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2501 if (new != XEXP (x, 1))
2503 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2511 case STRICT_LOW_PART:
2513 case SIGN_EXTEND: case ZERO_EXTEND:
2514 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2515 case FLOAT: case FIX:
2516 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2524 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2525 if (new != XEXP (x, 0))
2526 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2530 /* Similar to above processing, but preserve SUBREG_BYTE.
2531 Convert (subreg (mem)) to (mem) if not paradoxical.
2532 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2533 pseudo didn't get a hard reg, we must replace this with the
2534 eliminated version of the memory location because push_reload
2535 may do the replacement in certain circumstances. */
2536 if (REG_P (SUBREG_REG (x))
2537 && (GET_MODE_SIZE (GET_MODE (x))
2538 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2539 && reg_equiv_memory_loc != 0
2540 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2542 new = SUBREG_REG (x);
2545 new = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2547 if (new != SUBREG_REG (x))
2549 int x_size = GET_MODE_SIZE (GET_MODE (x));
2550 int new_size = GET_MODE_SIZE (GET_MODE (new));
2553 && ((x_size < new_size
2554 #ifdef WORD_REGISTER_OPERATIONS
2555 /* On these machines, combine can create rtl of the form
2556 (set (subreg:m1 (reg:m2 R) 0) ...)
2557 where m1 < m2, and expects something interesting to
2558 happen to the entire word. Moreover, it will use the
2559 (reg:m2 R) later, expecting all bits to be preserved.
2560 So if the number of words is the same, preserve the
2561 subreg so that push_reload can see it. */
2562 && ! ((x_size - 1) / UNITS_PER_WORD
2563 == (new_size -1 ) / UNITS_PER_WORD)
2566 || x_size == new_size)
2568 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2570 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2576 /* Our only special processing is to pass the mode of the MEM to our
2577 recursive call and copy the flags. While we are here, handle this
2578 case more efficiently. */
2580 replace_equiv_address_nv (x,
2581 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2585 /* Handle insn_list USE that a call to a pure function may generate. */
2586 new = eliminate_regs_1 (XEXP (x, 0), 0, insn, false);
2587 if (new != XEXP (x, 0))
2588 return gen_rtx_USE (GET_MODE (x), new);
2600 /* Process each of our operands recursively. If any have changed, make a
2602 fmt = GET_RTX_FORMAT (code);
2603 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2607 new = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2608 if (new != XEXP (x, i) && ! copied)
2610 x = shallow_copy_rtx (x);
2615 else if (*fmt == 'E')
2618 for (j = 0; j < XVECLEN (x, i); j++)
2620 new = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2621 if (new != XVECEXP (x, i, j) && ! copied_vec)
2623 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2627 x = shallow_copy_rtx (x);
2630 XVEC (x, i) = new_v;
2633 XVECEXP (x, i, j) = new;
2642 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2644 return eliminate_regs_1 (x, mem_mode, insn, false);
2647 /* Scan rtx X for modifications of elimination target registers. Update
2648 the table of eliminables to reflect the changed state. MEM_MODE is
2649 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2652 elimination_effects (rtx x, enum machine_mode mem_mode)
2654 enum rtx_code code = GET_CODE (x);
2655 struct elim_table *ep;
2679 /* First handle the case where we encounter a bare register that
2680 is eliminable. Replace it with a PLUS. */
2681 if (regno < FIRST_PSEUDO_REGISTER)
2683 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2685 if (ep->from_rtx == x && ep->can_eliminate)
2688 ep->ref_outside_mem = 1;
2693 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2694 && reg_equiv_constant[regno]
2695 && ! function_invariant_p (reg_equiv_constant[regno]))
2696 elimination_effects (reg_equiv_constant[regno], mem_mode);
2705 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2706 if (ep->to_rtx == XEXP (x, 0))
2708 int size = GET_MODE_SIZE (mem_mode);
2710 /* If more bytes than MEM_MODE are pushed, account for them. */
2711 #ifdef PUSH_ROUNDING
2712 if (ep->to_rtx == stack_pointer_rtx)
2713 size = PUSH_ROUNDING (size);
2715 if (code == PRE_DEC || code == POST_DEC)
2717 else if (code == PRE_INC || code == POST_INC)
2719 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2720 && GET_CODE (XEXP (x, 1)) == PLUS
2721 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2722 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2723 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2726 /* These two aren't unary operators. */
2727 if (code == POST_MODIFY || code == PRE_MODIFY)
2730 /* Fall through to generic unary operation case. */
2731 case STRICT_LOW_PART:
2733 case SIGN_EXTEND: case ZERO_EXTEND:
2734 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2735 case FLOAT: case FIX:
2736 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2744 elimination_effects (XEXP (x, 0), mem_mode);
2748 if (REG_P (SUBREG_REG (x))
2749 && (GET_MODE_SIZE (GET_MODE (x))
2750 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2751 && reg_equiv_memory_loc != 0
2752 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2755 elimination_effects (SUBREG_REG (x), mem_mode);
2759 /* If using a register that is the source of an eliminate we still
2760 think can be performed, note it cannot be performed since we don't
2761 know how this register is used. */
2762 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2763 if (ep->from_rtx == XEXP (x, 0))
2764 ep->can_eliminate = 0;
2766 elimination_effects (XEXP (x, 0), mem_mode);
2770 /* If clobbering a register that is the replacement register for an
2771 elimination we still think can be performed, note that it cannot
2772 be performed. Otherwise, we need not be concerned about it. */
2773 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2774 if (ep->to_rtx == XEXP (x, 0))
2775 ep->can_eliminate = 0;
2777 elimination_effects (XEXP (x, 0), mem_mode);
2781 /* Check for setting a register that we know about. */
2782 if (REG_P (SET_DEST (x)))
2784 /* See if this is setting the replacement register for an
2787 If DEST is the hard frame pointer, we do nothing because we
2788 assume that all assignments to the frame pointer are for
2789 non-local gotos and are being done at a time when they are valid
2790 and do not disturb anything else. Some machines want to
2791 eliminate a fake argument pointer (or even a fake frame pointer)
2792 with either the real frame or the stack pointer. Assignments to
2793 the hard frame pointer must not prevent this elimination. */
2795 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2797 if (ep->to_rtx == SET_DEST (x)
2798 && SET_DEST (x) != hard_frame_pointer_rtx)
2800 /* If it is being incremented, adjust the offset. Otherwise,
2801 this elimination can't be done. */
2802 rtx src = SET_SRC (x);
2804 if (GET_CODE (src) == PLUS
2805 && XEXP (src, 0) == SET_DEST (x)
2806 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2807 ep->offset -= INTVAL (XEXP (src, 1));
2809 ep->can_eliminate = 0;
2813 elimination_effects (SET_DEST (x), 0);
2814 elimination_effects (SET_SRC (x), 0);
2818 /* Our only special processing is to pass the mode of the MEM to our
2820 elimination_effects (XEXP (x, 0), GET_MODE (x));
2827 fmt = GET_RTX_FORMAT (code);
2828 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2831 elimination_effects (XEXP (x, i), mem_mode);
2832 else if (*fmt == 'E')
2833 for (j = 0; j < XVECLEN (x, i); j++)
2834 elimination_effects (XVECEXP (x, i, j), mem_mode);
2838 /* Descend through rtx X and verify that no references to eliminable registers
2839 remain. If any do remain, mark the involved register as not
2843 check_eliminable_occurrences (rtx x)
2852 code = GET_CODE (x);
2854 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2856 struct elim_table *ep;
2858 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2859 if (ep->from_rtx == x)
2860 ep->can_eliminate = 0;
2864 fmt = GET_RTX_FORMAT (code);
2865 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2868 check_eliminable_occurrences (XEXP (x, i));
2869 else if (*fmt == 'E')
2872 for (j = 0; j < XVECLEN (x, i); j++)
2873 check_eliminable_occurrences (XVECEXP (x, i, j));
2878 /* Scan INSN and eliminate all eliminable registers in it.
2880 If REPLACE is nonzero, do the replacement destructively. Also
2881 delete the insn as dead it if it is setting an eliminable register.
2883 If REPLACE is zero, do all our allocations in reload_obstack.
2885 If no eliminations were done and this insn doesn't require any elimination
2886 processing (these are not identical conditions: it might be updating sp,
2887 but not referencing fp; this needs to be seen during reload_as_needed so
2888 that the offset between fp and sp can be taken into consideration), zero
2889 is returned. Otherwise, 1 is returned. */
2892 eliminate_regs_in_insn (rtx insn, int replace)
2894 int icode = recog_memoized (insn);
2895 rtx old_body = PATTERN (insn);
2896 int insn_is_asm = asm_noperands (old_body) >= 0;
2897 rtx old_set = single_set (insn);
2901 rtx substed_operand[MAX_RECOG_OPERANDS];
2902 rtx orig_operand[MAX_RECOG_OPERANDS];
2903 struct elim_table *ep;
2904 rtx plus_src, plus_cst_src;
2906 if (! insn_is_asm && icode < 0)
2908 gcc_assert (GET_CODE (PATTERN (insn)) == USE
2909 || GET_CODE (PATTERN (insn)) == CLOBBER
2910 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2911 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2912 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
2916 if (old_set != 0 && REG_P (SET_DEST (old_set))
2917 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2919 /* Check for setting an eliminable register. */
2920 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2921 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2923 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2924 /* If this is setting the frame pointer register to the
2925 hardware frame pointer register and this is an elimination
2926 that will be done (tested above), this insn is really
2927 adjusting the frame pointer downward to compensate for
2928 the adjustment done before a nonlocal goto. */
2929 if (ep->from == FRAME_POINTER_REGNUM
2930 && ep->to == HARD_FRAME_POINTER_REGNUM)
2932 rtx base = SET_SRC (old_set);
2933 rtx base_insn = insn;
2934 HOST_WIDE_INT offset = 0;
2936 while (base != ep->to_rtx)
2938 rtx prev_insn, prev_set;
2940 if (GET_CODE (base) == PLUS
2941 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2943 offset += INTVAL (XEXP (base, 1));
2944 base = XEXP (base, 0);
2946 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2947 && (prev_set = single_set (prev_insn)) != 0
2948 && rtx_equal_p (SET_DEST (prev_set), base))
2950 base = SET_SRC (prev_set);
2951 base_insn = prev_insn;
2957 if (base == ep->to_rtx)
2960 = plus_constant (ep->to_rtx, offset - ep->offset);
2962 new_body = old_body;
2965 new_body = copy_insn (old_body);
2966 if (REG_NOTES (insn))
2967 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2969 PATTERN (insn) = new_body;
2970 old_set = single_set (insn);
2972 /* First see if this insn remains valid when we
2973 make the change. If not, keep the INSN_CODE
2974 the same and let reload fit it up. */
2975 validate_change (insn, &SET_SRC (old_set), src, 1);
2976 validate_change (insn, &SET_DEST (old_set),
2978 if (! apply_change_group ())
2980 SET_SRC (old_set) = src;
2981 SET_DEST (old_set) = ep->to_rtx;
2990 /* In this case this insn isn't serving a useful purpose. We
2991 will delete it in reload_as_needed once we know that this
2992 elimination is, in fact, being done.
2994 If REPLACE isn't set, we can't delete this insn, but needn't
2995 process it since it won't be used unless something changes. */
2998 delete_dead_insn (insn);
3006 /* We allow one special case which happens to work on all machines we
3007 currently support: a single set with the source or a REG_EQUAL
3008 note being a PLUS of an eliminable register and a constant. */
3009 plus_src = plus_cst_src = 0;
3010 if (old_set && REG_P (SET_DEST (old_set)))
3012 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3013 plus_src = SET_SRC (old_set);
3014 /* First see if the source is of the form (plus (...) CST). */
3016 && GET_CODE (XEXP (plus_src, 1)) == CONST_INT)
3017 plus_cst_src = plus_src;
3018 else if (REG_P (SET_SRC (old_set))
3021 /* Otherwise, see if we have a REG_EQUAL note of the form
3022 (plus (...) CST). */
3024 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3026 if (REG_NOTE_KIND (links) == REG_EQUAL
3027 && GET_CODE (XEXP (links, 0)) == PLUS
3028 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT)
3030 plus_cst_src = XEXP (links, 0);
3036 /* Check that the first operand of the PLUS is a hard reg or
3037 the lowpart subreg of one. */
3040 rtx reg = XEXP (plus_cst_src, 0);
3041 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3042 reg = SUBREG_REG (reg);
3044 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3050 rtx reg = XEXP (plus_cst_src, 0);
3051 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3053 if (GET_CODE (reg) == SUBREG)
3054 reg = SUBREG_REG (reg);
3056 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3057 if (ep->from_rtx == reg && ep->can_eliminate)
3059 rtx to_rtx = ep->to_rtx;
3060 offset += ep->offset;
3062 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3063 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3068 /* We assume here that if we need a PARALLEL with
3069 CLOBBERs for this assignment, we can do with the
3070 MATCH_SCRATCHes that add_clobbers allocates.
3071 There's not much we can do if that doesn't work. */
3072 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3076 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3079 rtvec vec = rtvec_alloc (num_clobbers + 1);
3081 vec->elem[0] = PATTERN (insn);
3082 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3083 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3085 gcc_assert (INSN_CODE (insn) >= 0);
3087 /* If we have a nonzero offset, and the source is already
3088 a simple REG, the following transformation would
3089 increase the cost of the insn by replacing a simple REG
3090 with (plus (reg sp) CST). So try only when we already
3091 had a PLUS before. */
3094 new_body = old_body;
3097 new_body = copy_insn (old_body);
3098 if (REG_NOTES (insn))
3099 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3101 PATTERN (insn) = new_body;
3102 old_set = single_set (insn);
3104 XEXP (SET_SRC (old_set), 0) = to_rtx;
3105 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3111 /* This can't have an effect on elimination offsets, so skip right
3117 /* Determine the effects of this insn on elimination offsets. */
3118 elimination_effects (old_body, 0);
3120 /* Eliminate all eliminable registers occurring in operands that
3121 can be handled by reload. */
3122 extract_insn (insn);
3123 for (i = 0; i < recog_data.n_operands; i++)
3125 orig_operand[i] = recog_data.operand[i];
3126 substed_operand[i] = recog_data.operand[i];
3128 /* For an asm statement, every operand is eliminable. */
3129 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3131 bool is_set_src, in_plus;
3133 /* Check for setting a register that we know about. */
3134 if (recog_data.operand_type[i] != OP_IN
3135 && REG_P (orig_operand[i]))
3137 /* If we are assigning to a register that can be eliminated, it
3138 must be as part of a PARALLEL, since the code above handles
3139 single SETs. We must indicate that we can no longer
3140 eliminate this reg. */
3141 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3143 if (ep->from_rtx == orig_operand[i])
3144 ep->can_eliminate = 0;
3147 /* Companion to the above plus substitution, we can allow
3148 invariants as the source of a plain move. */
3150 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3154 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3155 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3159 = eliminate_regs_1 (recog_data.operand[i], 0,
3160 replace ? insn : NULL_RTX,
3161 is_set_src || in_plus);
3162 if (substed_operand[i] != orig_operand[i])
3164 /* Terminate the search in check_eliminable_occurrences at
3166 *recog_data.operand_loc[i] = 0;
3168 /* If an output operand changed from a REG to a MEM and INSN is an
3169 insn, write a CLOBBER insn. */
3170 if (recog_data.operand_type[i] != OP_IN
3171 && REG_P (orig_operand[i])
3172 && MEM_P (substed_operand[i])
3174 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3179 for (i = 0; i < recog_data.n_dups; i++)
3180 *recog_data.dup_loc[i]
3181 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3183 /* If any eliminable remain, they aren't eliminable anymore. */
3184 check_eliminable_occurrences (old_body);
3186 /* Substitute the operands; the new values are in the substed_operand
3188 for (i = 0; i < recog_data.n_operands; i++)
3189 *recog_data.operand_loc[i] = substed_operand[i];
3190 for (i = 0; i < recog_data.n_dups; i++)
3191 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3193 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3194 re-recognize the insn. We do this in case we had a simple addition
3195 but now can do this as a load-address. This saves an insn in this
3197 If re-recognition fails, the old insn code number will still be used,
3198 and some register operands may have changed into PLUS expressions.
3199 These will be handled by find_reloads by loading them into a register
3204 /* If we aren't replacing things permanently and we changed something,
3205 make another copy to ensure that all the RTL is new. Otherwise
3206 things can go wrong if find_reload swaps commutative operands
3207 and one is inside RTL that has been copied while the other is not. */
3208 new_body = old_body;
3211 new_body = copy_insn (old_body);
3212 if (REG_NOTES (insn))
3213 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3215 PATTERN (insn) = new_body;
3217 /* If we had a move insn but now we don't, rerecognize it. This will
3218 cause spurious re-recognition if the old move had a PARALLEL since
3219 the new one still will, but we can't call single_set without
3220 having put NEW_BODY into the insn and the re-recognition won't
3221 hurt in this rare case. */
3222 /* ??? Why this huge if statement - why don't we just rerecognize the
3226 && ((REG_P (SET_SRC (old_set))
3227 && (GET_CODE (new_body) != SET
3228 || !REG_P (SET_SRC (new_body))))
3229 /* If this was a load from or store to memory, compare
3230 the MEM in recog_data.operand to the one in the insn.
3231 If they are not equal, then rerecognize the insn. */
3233 && ((MEM_P (SET_SRC (old_set))
3234 && SET_SRC (old_set) != recog_data.operand[1])
3235 || (MEM_P (SET_DEST (old_set))
3236 && SET_DEST (old_set) != recog_data.operand[0])))
3237 /* If this was an add insn before, rerecognize. */
3238 || GET_CODE (SET_SRC (old_set)) == PLUS))
3240 int new_icode = recog (PATTERN (insn), insn, 0);
3242 INSN_CODE (insn) = new_icode;
3246 /* Restore the old body. If there were any changes to it, we made a copy
3247 of it while the changes were still in place, so we'll correctly return
3248 a modified insn below. */
3251 /* Restore the old body. */
3252 for (i = 0; i < recog_data.n_operands; i++)
3253 *recog_data.operand_loc[i] = orig_operand[i];
3254 for (i = 0; i < recog_data.n_dups; i++)
3255 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3258 /* Update all elimination pairs to reflect the status after the current
3259 insn. The changes we make were determined by the earlier call to
3260 elimination_effects.
3262 We also detect cases where register elimination cannot be done,
3263 namely, if a register would be both changed and referenced outside a MEM
3264 in the resulting insn since such an insn is often undefined and, even if
3265 not, we cannot know what meaning will be given to it. Note that it is
3266 valid to have a register used in an address in an insn that changes it
3267 (presumably with a pre- or post-increment or decrement).
3269 If anything changes, return nonzero. */
3271 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3273 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3274 ep->can_eliminate = 0;
3276 ep->ref_outside_mem = 0;
3278 if (ep->previous_offset != ep->offset)
3283 /* If we changed something, perform elimination in REG_NOTES. This is
3284 needed even when REPLACE is zero because a REG_DEAD note might refer
3285 to a register that we eliminate and could cause a different number
3286 of spill registers to be needed in the final reload pass than in
3288 if (val && REG_NOTES (insn) != 0)
3290 = eliminate_regs_1 (REG_NOTES (insn), 0, REG_NOTES (insn), true);
3295 /* Loop through all elimination pairs.
3296 Recalculate the number not at initial offset.
3298 Compute the maximum offset (minimum offset if the stack does not
3299 grow downward) for each elimination pair. */
3302 update_eliminable_offsets (void)
3304 struct elim_table *ep;
3306 num_not_at_initial_offset = 0;
3307 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3309 ep->previous_offset = ep->offset;
3310 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3311 num_not_at_initial_offset++;
3315 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3316 replacement we currently believe is valid, mark it as not eliminable if X
3317 modifies DEST in any way other than by adding a constant integer to it.
3319 If DEST is the frame pointer, we do nothing because we assume that
3320 all assignments to the hard frame pointer are nonlocal gotos and are being
3321 done at a time when they are valid and do not disturb anything else.
3322 Some machines want to eliminate a fake argument pointer with either the
3323 frame or stack pointer. Assignments to the hard frame pointer must not
3324 prevent this elimination.
3326 Called via note_stores from reload before starting its passes to scan
3327 the insns of the function. */
3330 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3334 /* A SUBREG of a hard register here is just changing its mode. We should
3335 not see a SUBREG of an eliminable hard register, but check just in
3337 if (GET_CODE (dest) == SUBREG)
3338 dest = SUBREG_REG (dest);
3340 if (dest == hard_frame_pointer_rtx)
3343 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3344 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3345 && (GET_CODE (x) != SET
3346 || GET_CODE (SET_SRC (x)) != PLUS
3347 || XEXP (SET_SRC (x), 0) != dest
3348 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3350 reg_eliminate[i].can_eliminate_previous
3351 = reg_eliminate[i].can_eliminate = 0;
3356 /* Verify that the initial elimination offsets did not change since the
3357 last call to set_initial_elim_offsets. This is used to catch cases
3358 where something illegal happened during reload_as_needed that could
3359 cause incorrect code to be generated if we did not check for it. */
3362 verify_initial_elim_offsets (void)
3366 if (!num_eliminable)
3369 #ifdef ELIMINABLE_REGS
3371 struct elim_table *ep;
3373 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3375 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3376 if (t != ep->initial_offset)
3381 INITIAL_FRAME_POINTER_OFFSET (t);
3382 if (t != reg_eliminate[0].initial_offset)
3389 /* Reset all offsets on eliminable registers to their initial values. */
3392 set_initial_elim_offsets (void)
3394 struct elim_table *ep = reg_eliminate;
3396 #ifdef ELIMINABLE_REGS
3397 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3399 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3400 ep->previous_offset = ep->offset = ep->initial_offset;
3403 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3404 ep->previous_offset = ep->offset = ep->initial_offset;
3407 num_not_at_initial_offset = 0;
3410 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3413 set_initial_eh_label_offset (rtx label)
3415 set_label_offsets (label, NULL_RTX, 1);
3418 /* Initialize the known label offsets.
3419 Set a known offset for each forced label to be at the initial offset
3420 of each elimination. We do this because we assume that all
3421 computed jumps occur from a location where each elimination is
3422 at its initial offset.
3423 For all other labels, show that we don't know the offsets. */
3426 set_initial_label_offsets (void)
3429 memset (offsets_known_at, 0, num_labels);
3431 for (x = forced_labels; x; x = XEXP (x, 1))
3433 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3435 for_each_eh_label (set_initial_eh_label_offset);
3438 /* Set all elimination offsets to the known values for the code label given
3442 set_offsets_for_label (rtx insn)
3445 int label_nr = CODE_LABEL_NUMBER (insn);
3446 struct elim_table *ep;
3448 num_not_at_initial_offset = 0;
3449 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3451 ep->offset = ep->previous_offset
3452 = offsets_at[label_nr - first_label_num][i];
3453 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3454 num_not_at_initial_offset++;
3458 /* See if anything that happened changes which eliminations are valid.
3459 For example, on the SPARC, whether or not the frame pointer can
3460 be eliminated can depend on what registers have been used. We need
3461 not check some conditions again (such as flag_omit_frame_pointer)
3462 since they can't have changed. */
3465 update_eliminables (HARD_REG_SET *pset)
3467 int previous_frame_pointer_needed = frame_pointer_needed;
3468 struct elim_table *ep;
3470 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3471 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3472 #ifdef ELIMINABLE_REGS
3473 || ! CAN_ELIMINATE (ep->from, ep->to)
3476 ep->can_eliminate = 0;
3478 /* Look for the case where we have discovered that we can't replace
3479 register A with register B and that means that we will now be
3480 trying to replace register A with register C. This means we can
3481 no longer replace register C with register B and we need to disable
3482 such an elimination, if it exists. This occurs often with A == ap,
3483 B == sp, and C == fp. */
3485 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3487 struct elim_table *op;
3490 if (! ep->can_eliminate && ep->can_eliminate_previous)
3492 /* Find the current elimination for ep->from, if there is a
3494 for (op = reg_eliminate;
3495 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3496 if (op->from == ep->from && op->can_eliminate)
3502 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3504 for (op = reg_eliminate;
3505 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3506 if (op->from == new_to && op->to == ep->to)
3507 op->can_eliminate = 0;
3511 /* See if any registers that we thought we could eliminate the previous
3512 time are no longer eliminable. If so, something has changed and we
3513 must spill the register. Also, recompute the number of eliminable
3514 registers and see if the frame pointer is needed; it is if there is
3515 no elimination of the frame pointer that we can perform. */
3517 frame_pointer_needed = 1;
3518 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3520 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3521 && ep->to != HARD_FRAME_POINTER_REGNUM)
3522 frame_pointer_needed = 0;
3524 if (! ep->can_eliminate && ep->can_eliminate_previous)
3526 ep->can_eliminate_previous = 0;
3527 SET_HARD_REG_BIT (*pset, ep->from);
3532 /* If we didn't need a frame pointer last time, but we do now, spill
3533 the hard frame pointer. */
3534 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3535 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3538 /* Initialize the table of registers to eliminate. */
3541 init_elim_table (void)
3543 struct elim_table *ep;
3544 #ifdef ELIMINABLE_REGS
3545 const struct elim_table_1 *ep1;
3549 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3551 /* Does this function require a frame pointer? */
3553 frame_pointer_needed = (! flag_omit_frame_pointer
3554 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3555 and restore sp for alloca. So we can't eliminate
3556 the frame pointer in that case. At some point,
3557 we should improve this by emitting the
3558 sp-adjusting insns for this case. */
3559 || (current_function_calls_alloca
3560 && EXIT_IGNORE_STACK)
3561 || current_function_accesses_prior_frames
3562 || FRAME_POINTER_REQUIRED);
3566 #ifdef ELIMINABLE_REGS
3567 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3568 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3570 ep->from = ep1->from;
3572 ep->can_eliminate = ep->can_eliminate_previous
3573 = (CAN_ELIMINATE (ep->from, ep->to)
3574 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3577 reg_eliminate[0].from = reg_eliminate_1[0].from;
3578 reg_eliminate[0].to = reg_eliminate_1[0].to;
3579 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3580 = ! frame_pointer_needed;
3583 /* Count the number of eliminable registers and build the FROM and TO
3584 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3585 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3586 We depend on this. */
3587 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3589 num_eliminable += ep->can_eliminate;
3590 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3591 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3595 /* Kick all pseudos out of hard register REGNO.
3597 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3598 because we found we can't eliminate some register. In the case, no pseudos
3599 are allowed to be in the register, even if they are only in a block that
3600 doesn't require spill registers, unlike the case when we are spilling this
3601 hard reg to produce another spill register.
3603 Return nonzero if any pseudos needed to be kicked out. */
3606 spill_hard_reg (unsigned int regno, int cant_eliminate)
3612 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3613 regs_ever_live[regno] = 1;
3616 /* Spill every pseudo reg that was allocated to this reg
3617 or to something that overlaps this reg. */
3619 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3620 if (reg_renumber[i] >= 0
3621 && (unsigned int) reg_renumber[i] <= regno
3622 && ((unsigned int) reg_renumber[i]
3623 + hard_regno_nregs[(unsigned int) reg_renumber[i]]
3624 [PSEUDO_REGNO_MODE (i)]
3626 SET_REGNO_REG_SET (&spilled_pseudos, i);
3629 /* After find_reload_regs has been run for all insn that need reloads,
3630 and/or spill_hard_regs was called, this function is used to actually
3631 spill pseudo registers and try to reallocate them. It also sets up the
3632 spill_regs array for use by choose_reload_regs. */
3635 finish_spills (int global)
3637 struct insn_chain *chain;
3638 int something_changed = 0;
3640 reg_set_iterator rsi;
3642 /* Build the spill_regs array for the function. */
3643 /* If there are some registers still to eliminate and one of the spill regs
3644 wasn't ever used before, additional stack space may have to be
3645 allocated to store this register. Thus, we may have changed the offset
3646 between the stack and frame pointers, so mark that something has changed.
3648 One might think that we need only set VAL to 1 if this is a call-used
3649 register. However, the set of registers that must be saved by the
3650 prologue is not identical to the call-used set. For example, the
3651 register used by the call insn for the return PC is a call-used register,
3652 but must be saved by the prologue. */
3655 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3656 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3658 spill_reg_order[i] = n_spills;
3659 spill_regs[n_spills++] = i;
3660 if (num_eliminable && ! regs_ever_live[i])
3661 something_changed = 1;
3662 regs_ever_live[i] = 1;
3665 spill_reg_order[i] = -1;
3667 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3669 /* Record the current hard register the pseudo is allocated to in
3670 pseudo_previous_regs so we avoid reallocating it to the same
3671 hard reg in a later pass. */
3672 gcc_assert (reg_renumber[i] >= 0);
3674 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3675 /* Mark it as no longer having a hard register home. */
3676 reg_renumber[i] = -1;
3677 /* We will need to scan everything again. */
3678 something_changed = 1;
3681 /* Retry global register allocation if possible. */
3684 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3685 /* For every insn that needs reloads, set the registers used as spill
3686 regs in pseudo_forbidden_regs for every pseudo live across the
3688 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3690 EXECUTE_IF_SET_IN_REG_SET
3691 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3693 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3694 chain->used_spill_regs);
3696 EXECUTE_IF_SET_IN_REG_SET
3697 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3699 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3700 chain->used_spill_regs);
3704 /* Retry allocating the spilled pseudos. For each reg, merge the
3705 various reg sets that indicate which hard regs can't be used,
3706 and call retry_global_alloc.
3707 We change spill_pseudos here to only contain pseudos that did not
3708 get a new hard register. */
3709 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3710 if (reg_old_renumber[i] != reg_renumber[i])
3712 HARD_REG_SET forbidden;
3713 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3714 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3715 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3716 retry_global_alloc (i, forbidden);
3717 if (reg_renumber[i] >= 0)
3718 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3722 /* Fix up the register information in the insn chain.
3723 This involves deleting those of the spilled pseudos which did not get
3724 a new hard register home from the live_{before,after} sets. */
3725 for (chain = reload_insn_chain; chain; chain = chain->next)
3727 HARD_REG_SET used_by_pseudos;
3728 HARD_REG_SET used_by_pseudos2;
3730 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3731 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3733 /* Mark any unallocated hard regs as available for spills. That
3734 makes inheritance work somewhat better. */
3735 if (chain->need_reload)
3737 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3738 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3739 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3741 /* Save the old value for the sanity test below. */
3742 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3744 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3745 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3746 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3747 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3749 /* Make sure we only enlarge the set. */
3750 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3756 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3757 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3759 int regno = reg_renumber[i];
3760 if (reg_old_renumber[i] == regno)
3763 alter_reg (i, reg_old_renumber[i]);
3764 reg_old_renumber[i] = regno;
3768 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3770 fprintf (dump_file, " Register %d now in %d.\n\n",
3771 i, reg_renumber[i]);
3775 return something_changed;
3778 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3781 scan_paradoxical_subregs (rtx x)
3785 enum rtx_code code = GET_CODE (x);
3795 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3803 if (REG_P (SUBREG_REG (x))
3804 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3805 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3806 = GET_MODE_SIZE (GET_MODE (x));
3813 fmt = GET_RTX_FORMAT (code);
3814 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3817 scan_paradoxical_subregs (XEXP (x, i));
3818 else if (fmt[i] == 'E')
3821 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3822 scan_paradoxical_subregs (XVECEXP (x, i, j));
3827 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
3828 examine all of the reload insns between PREV and NEXT exclusive, and
3829 annotate all that may trap. */
3832 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
3834 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
3835 unsigned int trap_count;
3841 if (may_trap_p (PATTERN (insn)))
3845 remove_note (insn, note);
3849 for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i))
3850 if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i)))
3854 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (note, 0), REG_NOTES (i));
3858 /* Reload pseudo-registers into hard regs around each insn as needed.
3859 Additional register load insns are output before the insn that needs it
3860 and perhaps store insns after insns that modify the reloaded pseudo reg.
3862 reg_last_reload_reg and reg_reloaded_contents keep track of
3863 which registers are already available in reload registers.
3864 We update these for the reloads that we perform,
3865 as the insns are scanned. */
3868 reload_as_needed (int live_known)
3870 struct insn_chain *chain;
3871 #if defined (AUTO_INC_DEC)
3876 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3877 memset (spill_reg_store, 0, sizeof spill_reg_store);
3878 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
3879 reg_has_output_reload = XNEWVEC (char, max_regno);
3880 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3881 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
3883 set_initial_elim_offsets ();
3885 for (chain = reload_insn_chain; chain; chain = chain->next)
3888 rtx insn = chain->insn;
3889 rtx old_next = NEXT_INSN (insn);
3891 /* If we pass a label, copy the offsets from the label information
3892 into the current offsets of each elimination. */
3894 set_offsets_for_label (insn);
3896 else if (INSN_P (insn))
3898 rtx oldpat = copy_rtx (PATTERN (insn));
3900 /* If this is a USE and CLOBBER of a MEM, ensure that any
3901 references to eliminable registers have been removed. */
3903 if ((GET_CODE (PATTERN (insn)) == USE
3904 || GET_CODE (PATTERN (insn)) == CLOBBER)
3905 && MEM_P (XEXP (PATTERN (insn), 0)))
3906 XEXP (XEXP (PATTERN (insn), 0), 0)
3907 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3908 GET_MODE (XEXP (PATTERN (insn), 0)),
3911 /* If we need to do register elimination processing, do so.
3912 This might delete the insn, in which case we are done. */
3913 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3915 eliminate_regs_in_insn (insn, 1);
3918 update_eliminable_offsets ();
3923 /* If need_elim is nonzero but need_reload is zero, one might think
3924 that we could simply set n_reloads to 0. However, find_reloads
3925 could have done some manipulation of the insn (such as swapping
3926 commutative operands), and these manipulations are lost during
3927 the first pass for every insn that needs register elimination.
3928 So the actions of find_reloads must be redone here. */
3930 if (! chain->need_elim && ! chain->need_reload
3931 && ! chain->need_operand_change)
3933 /* First find the pseudo regs that must be reloaded for this insn.
3934 This info is returned in the tables reload_... (see reload.h).
3935 Also modify the body of INSN by substituting RELOAD
3936 rtx's for those pseudo regs. */
3939 memset (reg_has_output_reload, 0, max_regno);
3940 CLEAR_HARD_REG_SET (reg_is_output_reload);
3942 find_reloads (insn, 1, spill_indirect_levels, live_known,
3948 rtx next = NEXT_INSN (insn);
3951 prev = PREV_INSN (insn);
3953 /* Now compute which reload regs to reload them into. Perhaps
3954 reusing reload regs from previous insns, or else output
3955 load insns to reload them. Maybe output store insns too.
3956 Record the choices of reload reg in reload_reg_rtx. */
3957 choose_reload_regs (chain);
3959 /* Merge any reloads that we didn't combine for fear of
3960 increasing the number of spill registers needed but now
3961 discover can be safely merged. */
3962 if (SMALL_REGISTER_CLASSES)
3963 merge_assigned_reloads (insn);
3965 /* Generate the insns to reload operands into or out of
3966 their reload regs. */
3967 emit_reload_insns (chain);
3969 /* Substitute the chosen reload regs from reload_reg_rtx
3970 into the insn's body (or perhaps into the bodies of other
3971 load and store insn that we just made for reloading
3972 and that we moved the structure into). */
3973 subst_reloads (insn);
3975 /* Adjust the exception region notes for loads and stores. */
3976 if (flag_non_call_exceptions && !CALL_P (insn))
3977 fixup_eh_region_note (insn, prev, next);
3979 /* If this was an ASM, make sure that all the reload insns
3980 we have generated are valid. If not, give an error
3982 if (asm_noperands (PATTERN (insn)) >= 0)
3983 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3984 if (p != insn && INSN_P (p)
3985 && GET_CODE (PATTERN (p)) != USE
3986 && (recog_memoized (p) < 0
3987 || (extract_insn (p), ! constrain_operands (1))))
3989 error_for_asm (insn,
3990 "%<asm%> operand requires "
3991 "impossible reload");
3996 if (num_eliminable && chain->need_elim)
3997 update_eliminable_offsets ();
3999 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4000 is no longer validly lying around to save a future reload.
4001 Note that this does not detect pseudos that were reloaded
4002 for this insn in order to be stored in
4003 (obeying register constraints). That is correct; such reload
4004 registers ARE still valid. */
4005 note_stores (oldpat, forget_old_reloads_1, NULL);
4007 /* There may have been CLOBBER insns placed after INSN. So scan
4008 between INSN and NEXT and use them to forget old reloads. */
4009 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4010 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4011 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4014 /* Likewise for regs altered by auto-increment in this insn.
4015 REG_INC notes have been changed by reloading:
4016 find_reloads_address_1 records substitutions for them,
4017 which have been performed by subst_reloads above. */
4018 for (i = n_reloads - 1; i >= 0; i--)
4020 rtx in_reg = rld[i].in_reg;
4023 enum rtx_code code = GET_CODE (in_reg);
4024 /* PRE_INC / PRE_DEC will have the reload register ending up
4025 with the same value as the stack slot, but that doesn't
4026 hold true for POST_INC / POST_DEC. Either we have to
4027 convert the memory access to a true POST_INC / POST_DEC,
4028 or we can't use the reload register for inheritance. */
4029 if ((code == POST_INC || code == POST_DEC)
4030 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4031 REGNO (rld[i].reg_rtx))
4032 /* Make sure it is the inc/dec pseudo, and not
4033 some other (e.g. output operand) pseudo. */
4034 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4035 == REGNO (XEXP (in_reg, 0))))
4038 rtx reload_reg = rld[i].reg_rtx;
4039 enum machine_mode mode = GET_MODE (reload_reg);
4043 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4045 /* We really want to ignore REG_INC notes here, so
4046 use PATTERN (p) as argument to reg_set_p . */
4047 if (reg_set_p (reload_reg, PATTERN (p)))
4049 n = count_occurrences (PATTERN (p), reload_reg, 0);
4054 n = validate_replace_rtx (reload_reg,
4055 gen_rtx_fmt_e (code,
4060 /* We must also verify that the constraints
4061 are met after the replacement. */
4064 n = constrain_operands (1);
4068 /* If the constraints were not met, then
4069 undo the replacement. */
4072 validate_replace_rtx (gen_rtx_fmt_e (code,
4085 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4087 /* Mark this as having an output reload so that the
4088 REG_INC processing code below won't invalidate
4089 the reload for inheritance. */
4090 SET_HARD_REG_BIT (reg_is_output_reload,
4091 REGNO (reload_reg));
4092 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4095 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4098 else if ((code == PRE_INC || code == PRE_DEC)
4099 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4100 REGNO (rld[i].reg_rtx))
4101 /* Make sure it is the inc/dec pseudo, and not
4102 some other (e.g. output operand) pseudo. */
4103 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4104 == REGNO (XEXP (in_reg, 0))))
4106 SET_HARD_REG_BIT (reg_is_output_reload,
4107 REGNO (rld[i].reg_rtx));
4108 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4112 /* If a pseudo that got a hard register is auto-incremented,
4113 we must purge records of copying it into pseudos without
4115 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4116 if (REG_NOTE_KIND (x) == REG_INC)
4118 /* See if this pseudo reg was reloaded in this insn.
4119 If so, its last-reload info is still valid
4120 because it is based on this insn's reload. */
4121 for (i = 0; i < n_reloads; i++)
4122 if (rld[i].out == XEXP (x, 0))
4126 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4130 /* A reload reg's contents are unknown after a label. */
4132 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4134 /* Don't assume a reload reg is still good after a call insn
4135 if it is a call-used reg, or if it contains a value that will
4136 be partially clobbered by the call. */
4137 else if (CALL_P (insn))
4139 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4140 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4145 free (reg_last_reload_reg);
4146 free (reg_has_output_reload);
4149 /* Discard all record of any value reloaded from X,
4150 or reloaded in X from someplace else;
4151 unless X is an output reload reg of the current insn.
4153 X may be a hard reg (the reload reg)
4154 or it may be a pseudo reg that was reloaded from. */
4157 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4158 void *data ATTRIBUTE_UNUSED)
4163 /* note_stores does give us subregs of hard regs,
4164 subreg_regno_offset requires a hard reg. */
4165 while (GET_CODE (x) == SUBREG)
4167 /* We ignore the subreg offset when calculating the regno,
4168 because we are using the entire underlying hard register
4178 if (regno >= FIRST_PSEUDO_REGISTER)
4184 nr = hard_regno_nregs[regno][GET_MODE (x)];
4185 /* Storing into a spilled-reg invalidates its contents.
4186 This can happen if a block-local pseudo is allocated to that reg
4187 and it wasn't spilled because this block's total need is 0.
4188 Then some insn might have an optional reload and use this reg. */
4189 for (i = 0; i < nr; i++)
4190 /* But don't do this if the reg actually serves as an output
4191 reload reg in the current instruction. */
4193 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4195 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4196 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4197 spill_reg_store[regno + i] = 0;
4201 /* Since value of X has changed,
4202 forget any value previously copied from it. */
4205 /* But don't forget a copy if this is the output reload
4206 that establishes the copy's validity. */
4207 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4208 reg_last_reload_reg[regno + nr] = 0;
4211 /* The following HARD_REG_SETs indicate when each hard register is
4212 used for a reload of various parts of the current insn. */
4214 /* If reg is unavailable for all reloads. */
4215 static HARD_REG_SET reload_reg_unavailable;
4216 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4217 static HARD_REG_SET reload_reg_used;
4218 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4219 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4220 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4221 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4222 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4223 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4224 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4225 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4226 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4227 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4228 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4229 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4230 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4231 static HARD_REG_SET reload_reg_used_in_op_addr;
4232 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4233 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4234 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4235 static HARD_REG_SET reload_reg_used_in_insn;
4236 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4237 static HARD_REG_SET reload_reg_used_in_other_addr;
4239 /* If reg is in use as a reload reg for any sort of reload. */
4240 static HARD_REG_SET reload_reg_used_at_all;
4242 /* If reg is use as an inherited reload. We just mark the first register
4244 static HARD_REG_SET reload_reg_used_for_inherit;
4246 /* Records which hard regs are used in any way, either as explicit use or
4247 by being allocated to a pseudo during any point of the current insn. */
4248 static HARD_REG_SET reg_used_in_insn;
4250 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4251 TYPE. MODE is used to indicate how many consecutive regs are
4255 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4256 enum machine_mode mode)
4258 unsigned int nregs = hard_regno_nregs[regno][mode];
4261 for (i = regno; i < nregs + regno; i++)
4266 SET_HARD_REG_BIT (reload_reg_used, i);
4269 case RELOAD_FOR_INPUT_ADDRESS:
4270 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4273 case RELOAD_FOR_INPADDR_ADDRESS:
4274 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4277 case RELOAD_FOR_OUTPUT_ADDRESS:
4278 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4281 case RELOAD_FOR_OUTADDR_ADDRESS:
4282 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4285 case RELOAD_FOR_OPERAND_ADDRESS:
4286 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4289 case RELOAD_FOR_OPADDR_ADDR:
4290 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4293 case RELOAD_FOR_OTHER_ADDRESS:
4294 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4297 case RELOAD_FOR_INPUT:
4298 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4301 case RELOAD_FOR_OUTPUT:
4302 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4305 case RELOAD_FOR_INSN:
4306 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4310 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4314 /* Similarly, but show REGNO is no longer in use for a reload. */
4317 clear_reload_reg_in_use (unsigned int regno, int opnum,
4318 enum reload_type type, enum machine_mode mode)
4320 unsigned int nregs = hard_regno_nregs[regno][mode];
4321 unsigned int start_regno, end_regno, r;
4323 /* A complication is that for some reload types, inheritance might
4324 allow multiple reloads of the same types to share a reload register.
4325 We set check_opnum if we have to check only reloads with the same
4326 operand number, and check_any if we have to check all reloads. */
4327 int check_opnum = 0;
4329 HARD_REG_SET *used_in_set;
4334 used_in_set = &reload_reg_used;
4337 case RELOAD_FOR_INPUT_ADDRESS:
4338 used_in_set = &reload_reg_used_in_input_addr[opnum];
4341 case RELOAD_FOR_INPADDR_ADDRESS:
4343 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4346 case RELOAD_FOR_OUTPUT_ADDRESS:
4347 used_in_set = &reload_reg_used_in_output_addr[opnum];
4350 case RELOAD_FOR_OUTADDR_ADDRESS:
4352 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4355 case RELOAD_FOR_OPERAND_ADDRESS:
4356 used_in_set = &reload_reg_used_in_op_addr;
4359 case RELOAD_FOR_OPADDR_ADDR:
4361 used_in_set = &reload_reg_used_in_op_addr_reload;
4364 case RELOAD_FOR_OTHER_ADDRESS:
4365 used_in_set = &reload_reg_used_in_other_addr;
4369 case RELOAD_FOR_INPUT:
4370 used_in_set = &reload_reg_used_in_input[opnum];
4373 case RELOAD_FOR_OUTPUT:
4374 used_in_set = &reload_reg_used_in_output[opnum];
4377 case RELOAD_FOR_INSN:
4378 used_in_set = &reload_reg_used_in_insn;
4383 /* We resolve conflicts with remaining reloads of the same type by
4384 excluding the intervals of reload registers by them from the
4385 interval of freed reload registers. Since we only keep track of
4386 one set of interval bounds, we might have to exclude somewhat
4387 more than what would be necessary if we used a HARD_REG_SET here.
4388 But this should only happen very infrequently, so there should
4389 be no reason to worry about it. */
4391 start_regno = regno;
4392 end_regno = regno + nregs;
4393 if (check_opnum || check_any)
4395 for (i = n_reloads - 1; i >= 0; i--)
4397 if (rld[i].when_needed == type
4398 && (check_any || rld[i].opnum == opnum)
4401 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4402 unsigned int conflict_end
4404 + hard_regno_nregs[conflict_start][rld[i].mode]);
4406 /* If there is an overlap with the first to-be-freed register,
4407 adjust the interval start. */
4408 if (conflict_start <= start_regno && conflict_end > start_regno)
4409 start_regno = conflict_end;
4410 /* Otherwise, if there is a conflict with one of the other
4411 to-be-freed registers, adjust the interval end. */
4412 if (conflict_start > start_regno && conflict_start < end_regno)
4413 end_regno = conflict_start;
4418 for (r = start_regno; r < end_regno; r++)
4419 CLEAR_HARD_REG_BIT (*used_in_set, r);
4422 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4423 specified by OPNUM and TYPE. */
4426 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4430 /* In use for a RELOAD_OTHER means it's not available for anything. */
4431 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4432 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4438 /* In use for anything means we can't use it for RELOAD_OTHER. */
4439 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4440 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4441 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4442 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4445 for (i = 0; i < reload_n_operands; i++)
4446 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4447 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4448 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4449 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4450 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4451 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4456 case RELOAD_FOR_INPUT:
4457 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4458 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4461 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4464 /* If it is used for some other input, can't use it. */
4465 for (i = 0; i < reload_n_operands; i++)
4466 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4469 /* If it is used in a later operand's address, can't use it. */
4470 for (i = opnum + 1; i < reload_n_operands; i++)
4471 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4472 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4477 case RELOAD_FOR_INPUT_ADDRESS:
4478 /* Can't use a register if it is used for an input address for this
4479 operand or used as an input in an earlier one. */
4480 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4481 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4484 for (i = 0; i < opnum; i++)
4485 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4490 case RELOAD_FOR_INPADDR_ADDRESS:
4491 /* Can't use a register if it is used for an input address
4492 for this operand or used as an input in an earlier
4494 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4497 for (i = 0; i < opnum; i++)
4498 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4503 case RELOAD_FOR_OUTPUT_ADDRESS:
4504 /* Can't use a register if it is used for an output address for this
4505 operand or used as an output in this or a later operand. Note
4506 that multiple output operands are emitted in reverse order, so
4507 the conflicting ones are those with lower indices. */
4508 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4511 for (i = 0; i <= opnum; i++)
4512 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4517 case RELOAD_FOR_OUTADDR_ADDRESS:
4518 /* Can't use a register if it is used for an output address
4519 for this operand or used as an output in this or a
4520 later operand. Note that multiple output operands are
4521 emitted in reverse order, so the conflicting ones are
4522 those with lower indices. */
4523 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4526 for (i = 0; i <= opnum; i++)
4527 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4532 case RELOAD_FOR_OPERAND_ADDRESS:
4533 for (i = 0; i < reload_n_operands; i++)
4534 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4537 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4538 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4540 case RELOAD_FOR_OPADDR_ADDR:
4541 for (i = 0; i < reload_n_operands; i++)
4542 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4545 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4547 case RELOAD_FOR_OUTPUT:
4548 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4549 outputs, or an operand address for this or an earlier output.
4550 Note that multiple output operands are emitted in reverse order,
4551 so the conflicting ones are those with higher indices. */
4552 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4555 for (i = 0; i < reload_n_operands; i++)
4556 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4559 for (i = opnum; i < reload_n_operands; i++)
4560 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4561 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4566 case RELOAD_FOR_INSN:
4567 for (i = 0; i < reload_n_operands; i++)
4568 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4569 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4572 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4573 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4575 case RELOAD_FOR_OTHER_ADDRESS:
4576 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4583 /* Return 1 if the value in reload reg REGNO, as used by a reload
4584 needed for the part of the insn specified by OPNUM and TYPE,
4585 is still available in REGNO at the end of the insn.
4587 We can assume that the reload reg was already tested for availability
4588 at the time it is needed, and we should not check this again,
4589 in case the reg has already been marked in use. */
4592 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4599 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4600 its value must reach the end. */
4603 /* If this use is for part of the insn,
4604 its value reaches if no subsequent part uses the same register.
4605 Just like the above function, don't try to do this with lots
4608 case RELOAD_FOR_OTHER_ADDRESS:
4609 /* Here we check for everything else, since these don't conflict
4610 with anything else and everything comes later. */
4612 for (i = 0; i < reload_n_operands; i++)
4613 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4614 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4615 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4616 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4617 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4618 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4621 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4622 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4623 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4624 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4626 case RELOAD_FOR_INPUT_ADDRESS:
4627 case RELOAD_FOR_INPADDR_ADDRESS:
4628 /* Similar, except that we check only for this and subsequent inputs
4629 and the address of only subsequent inputs and we do not need
4630 to check for RELOAD_OTHER objects since they are known not to
4633 for (i = opnum; i < reload_n_operands; i++)
4634 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4637 for (i = opnum + 1; i < reload_n_operands; i++)
4638 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4639 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4642 for (i = 0; i < reload_n_operands; i++)
4643 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4644 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4645 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4648 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4651 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4652 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4653 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4655 case RELOAD_FOR_INPUT:
4656 /* Similar to input address, except we start at the next operand for
4657 both input and input address and we do not check for
4658 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4661 for (i = opnum + 1; i < reload_n_operands; i++)
4662 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4663 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4664 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4667 /* ... fall through ... */
4669 case RELOAD_FOR_OPERAND_ADDRESS:
4670 /* Check outputs and their addresses. */
4672 for (i = 0; i < reload_n_operands; i++)
4673 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4674 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4675 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4678 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4680 case RELOAD_FOR_OPADDR_ADDR:
4681 for (i = 0; i < reload_n_operands; i++)
4682 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4683 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4684 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4687 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4688 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4689 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4691 case RELOAD_FOR_INSN:
4692 /* These conflict with other outputs with RELOAD_OTHER. So
4693 we need only check for output addresses. */
4695 opnum = reload_n_operands;
4697 /* ... fall through ... */
4699 case RELOAD_FOR_OUTPUT:
4700 case RELOAD_FOR_OUTPUT_ADDRESS:
4701 case RELOAD_FOR_OUTADDR_ADDRESS:
4702 /* We already know these can't conflict with a later output. So the
4703 only thing to check are later output addresses.
4704 Note that multiple output operands are emitted in reverse order,
4705 so the conflicting ones are those with lower indices. */
4706 for (i = 0; i < opnum; i++)
4707 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4708 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4718 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4721 This function uses the same algorithm as reload_reg_free_p above. */
4724 reloads_conflict (int r1, int r2)
4726 enum reload_type r1_type = rld[r1].when_needed;
4727 enum reload_type r2_type = rld[r2].when_needed;
4728 int r1_opnum = rld[r1].opnum;
4729 int r2_opnum = rld[r2].opnum;
4731 /* RELOAD_OTHER conflicts with everything. */
4732 if (r2_type == RELOAD_OTHER)
4735 /* Otherwise, check conflicts differently for each type. */
4739 case RELOAD_FOR_INPUT:
4740 return (r2_type == RELOAD_FOR_INSN
4741 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4742 || r2_type == RELOAD_FOR_OPADDR_ADDR
4743 || r2_type == RELOAD_FOR_INPUT
4744 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4745 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4746 && r2_opnum > r1_opnum));
4748 case RELOAD_FOR_INPUT_ADDRESS:
4749 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4750 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4752 case RELOAD_FOR_INPADDR_ADDRESS:
4753 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4754 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4756 case RELOAD_FOR_OUTPUT_ADDRESS:
4757 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4758 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4760 case RELOAD_FOR_OUTADDR_ADDRESS:
4761 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4762 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4764 case RELOAD_FOR_OPERAND_ADDRESS:
4765 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4766 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4768 case RELOAD_FOR_OPADDR_ADDR:
4769 return (r2_type == RELOAD_FOR_INPUT
4770 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4772 case RELOAD_FOR_OUTPUT:
4773 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4774 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4775 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4776 && r2_opnum >= r1_opnum));
4778 case RELOAD_FOR_INSN:
4779 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4780 || r2_type == RELOAD_FOR_INSN
4781 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4783 case RELOAD_FOR_OTHER_ADDRESS:
4784 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4794 /* Indexed by reload number, 1 if incoming value
4795 inherited from previous insns. */
4796 static char reload_inherited[MAX_RELOADS];
4798 /* For an inherited reload, this is the insn the reload was inherited from,
4799 if we know it. Otherwise, this is 0. */
4800 static rtx reload_inheritance_insn[MAX_RELOADS];
4802 /* If nonzero, this is a place to get the value of the reload,
4803 rather than using reload_in. */
4804 static rtx reload_override_in[MAX_RELOADS];
4806 /* For each reload, the hard register number of the register used,
4807 or -1 if we did not need a register for this reload. */
4808 static int reload_spill_index[MAX_RELOADS];
4810 /* Subroutine of free_for_value_p, used to check a single register.
4811 START_REGNO is the starting regno of the full reload register
4812 (possibly comprising multiple hard registers) that we are considering. */
4815 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4816 enum reload_type type, rtx value, rtx out,
4817 int reloadnum, int ignore_address_reloads)
4820 /* Set if we see an input reload that must not share its reload register
4821 with any new earlyclobber, but might otherwise share the reload
4822 register with an output or input-output reload. */
4823 int check_earlyclobber = 0;
4827 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4830 if (out == const0_rtx)
4836 /* We use some pseudo 'time' value to check if the lifetimes of the
4837 new register use would overlap with the one of a previous reload
4838 that is not read-only or uses a different value.
4839 The 'time' used doesn't have to be linear in any shape or form, just
4841 Some reload types use different 'buckets' for each operand.
4842 So there are MAX_RECOG_OPERANDS different time values for each
4844 We compute TIME1 as the time when the register for the prospective
4845 new reload ceases to be live, and TIME2 for each existing
4846 reload as the time when that the reload register of that reload
4848 Where there is little to be gained by exact lifetime calculations,
4849 we just make conservative assumptions, i.e. a longer lifetime;
4850 this is done in the 'default:' cases. */
4853 case RELOAD_FOR_OTHER_ADDRESS:
4854 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4855 time1 = copy ? 0 : 1;
4858 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4860 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4861 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4862 respectively, to the time values for these, we get distinct time
4863 values. To get distinct time values for each operand, we have to
4864 multiply opnum by at least three. We round that up to four because
4865 multiply by four is often cheaper. */
4866 case RELOAD_FOR_INPADDR_ADDRESS:
4867 time1 = opnum * 4 + 2;
4869 case RELOAD_FOR_INPUT_ADDRESS:
4870 time1 = opnum * 4 + 3;
4872 case RELOAD_FOR_INPUT:
4873 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4874 executes (inclusive). */
4875 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4877 case RELOAD_FOR_OPADDR_ADDR:
4879 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4880 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4882 case RELOAD_FOR_OPERAND_ADDRESS:
4883 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4885 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4887 case RELOAD_FOR_OUTADDR_ADDRESS:
4888 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4890 case RELOAD_FOR_OUTPUT_ADDRESS:
4891 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4894 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4897 for (i = 0; i < n_reloads; i++)
4899 rtx reg = rld[i].reg_rtx;
4900 if (reg && REG_P (reg)
4901 && ((unsigned) regno - true_regnum (reg)
4902 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
4905 rtx other_input = rld[i].in;
4907 /* If the other reload loads the same input value, that
4908 will not cause a conflict only if it's loading it into
4909 the same register. */
4910 if (true_regnum (reg) != start_regno)
4911 other_input = NULL_RTX;
4912 if (! other_input || ! rtx_equal_p (other_input, value)
4913 || rld[i].out || out)
4916 switch (rld[i].when_needed)
4918 case RELOAD_FOR_OTHER_ADDRESS:
4921 case RELOAD_FOR_INPADDR_ADDRESS:
4922 /* find_reloads makes sure that a
4923 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4924 by at most one - the first -
4925 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4926 address reload is inherited, the address address reload
4927 goes away, so we can ignore this conflict. */
4928 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4929 && ignore_address_reloads
4930 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4931 Then the address address is still needed to store
4932 back the new address. */
4933 && ! rld[reloadnum].out)
4935 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4936 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4938 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4939 && ignore_address_reloads
4940 /* Unless we are reloading an auto_inc expression. */
4941 && ! rld[reloadnum].out)
4943 time2 = rld[i].opnum * 4 + 2;
4945 case RELOAD_FOR_INPUT_ADDRESS:
4946 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4947 && ignore_address_reloads
4948 && ! rld[reloadnum].out)
4950 time2 = rld[i].opnum * 4 + 3;
4952 case RELOAD_FOR_INPUT:
4953 time2 = rld[i].opnum * 4 + 4;
4954 check_earlyclobber = 1;
4956 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4957 == MAX_RECOG_OPERAND * 4 */
4958 case RELOAD_FOR_OPADDR_ADDR:
4959 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4960 && ignore_address_reloads
4961 && ! rld[reloadnum].out)
4963 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4965 case RELOAD_FOR_OPERAND_ADDRESS:
4966 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4967 check_earlyclobber = 1;
4969 case RELOAD_FOR_INSN:
4970 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4972 case RELOAD_FOR_OUTPUT:
4973 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4974 instruction is executed. */
4975 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4977 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4978 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4980 case RELOAD_FOR_OUTADDR_ADDRESS:
4981 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4982 && ignore_address_reloads
4983 && ! rld[reloadnum].out)
4985 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4987 case RELOAD_FOR_OUTPUT_ADDRESS:
4988 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4991 /* If there is no conflict in the input part, handle this
4992 like an output reload. */
4993 if (! rld[i].in || rtx_equal_p (other_input, value))
4995 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4996 /* Earlyclobbered outputs must conflict with inputs. */
4997 if (earlyclobber_operand_p (rld[i].out))
4998 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5003 /* RELOAD_OTHER might be live beyond instruction execution,
5004 but this is not obvious when we set time2 = 1. So check
5005 here if there might be a problem with the new reload
5006 clobbering the register used by the RELOAD_OTHER. */
5014 && (! rld[i].in || rld[i].out
5015 || ! rtx_equal_p (other_input, value)))
5016 || (out && rld[reloadnum].out_reg
5017 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5023 /* Earlyclobbered outputs must conflict with inputs. */
5024 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5030 /* Return 1 if the value in reload reg REGNO, as used by a reload
5031 needed for the part of the insn specified by OPNUM and TYPE,
5032 may be used to load VALUE into it.
5034 MODE is the mode in which the register is used, this is needed to
5035 determine how many hard regs to test.
5037 Other read-only reloads with the same value do not conflict
5038 unless OUT is nonzero and these other reloads have to live while
5039 output reloads live.
5040 If OUT is CONST0_RTX, this is a special case: it means that the
5041 test should not be for using register REGNO as reload register, but
5042 for copying from register REGNO into the reload register.
5044 RELOADNUM is the number of the reload we want to load this value for;
5045 a reload does not conflict with itself.
5047 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5048 reloads that load an address for the very reload we are considering.
5050 The caller has to make sure that there is no conflict with the return
5054 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5055 enum reload_type type, rtx value, rtx out, int reloadnum,
5056 int ignore_address_reloads)
5058 int nregs = hard_regno_nregs[regno][mode];
5060 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5061 value, out, reloadnum,
5062 ignore_address_reloads))
5067 /* Return nonzero if the rtx X is invariant over the current function. */
5068 /* ??? Actually, the places where we use this expect exactly what is
5069 tested here, and not everything that is function invariant. In
5070 particular, the frame pointer and arg pointer are special cased;
5071 pic_offset_table_rtx is not, and we must not spill these things to
5075 function_invariant_p (rtx x)
5079 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5081 if (GET_CODE (x) == PLUS
5082 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5083 && CONSTANT_P (XEXP (x, 1)))
5088 /* Determine whether the reload reg X overlaps any rtx'es used for
5089 overriding inheritance. Return nonzero if so. */
5092 conflicts_with_override (rtx x)
5095 for (i = 0; i < n_reloads; i++)
5096 if (reload_override_in[i]
5097 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5102 /* Give an error message saying we failed to find a reload for INSN,
5103 and clear out reload R. */
5105 failed_reload (rtx insn, int r)
5107 if (asm_noperands (PATTERN (insn)) < 0)
5108 /* It's the compiler's fault. */
5109 fatal_insn ("could not find a spill register", insn);
5111 /* It's the user's fault; the operand's mode and constraint
5112 don't match. Disable this reload so we don't crash in final. */
5113 error_for_asm (insn,
5114 "%<asm%> operand constraint incompatible with operand size");
5118 rld[r].optional = 1;
5119 rld[r].secondary_p = 1;
5122 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5123 for reload R. If it's valid, get an rtx for it. Return nonzero if
5126 set_reload_reg (int i, int r)
5129 rtx reg = spill_reg_rtx[i];
5131 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5132 spill_reg_rtx[i] = reg
5133 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5135 regno = true_regnum (reg);
5137 /* Detect when the reload reg can't hold the reload mode.
5138 This used to be one `if', but Sequent compiler can't handle that. */
5139 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5141 enum machine_mode test_mode = VOIDmode;
5143 test_mode = GET_MODE (rld[r].in);
5144 /* If rld[r].in has VOIDmode, it means we will load it
5145 in whatever mode the reload reg has: to wit, rld[r].mode.
5146 We have already tested that for validity. */
5147 /* Aside from that, we need to test that the expressions
5148 to reload from or into have modes which are valid for this
5149 reload register. Otherwise the reload insns would be invalid. */
5150 if (! (rld[r].in != 0 && test_mode != VOIDmode
5151 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5152 if (! (rld[r].out != 0
5153 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5155 /* The reg is OK. */
5158 /* Mark as in use for this insn the reload regs we use
5160 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5161 rld[r].when_needed, rld[r].mode);
5163 rld[r].reg_rtx = reg;
5164 reload_spill_index[r] = spill_regs[i];
5171 /* Find a spill register to use as a reload register for reload R.
5172 LAST_RELOAD is nonzero if this is the last reload for the insn being
5175 Set rld[R].reg_rtx to the register allocated.
5177 We return 1 if successful, or 0 if we couldn't find a spill reg and
5178 we didn't change anything. */
5181 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5186 /* If we put this reload ahead, thinking it is a group,
5187 then insist on finding a group. Otherwise we can grab a
5188 reg that some other reload needs.
5189 (That can happen when we have a 68000 DATA_OR_FP_REG
5190 which is a group of data regs or one fp reg.)
5191 We need not be so restrictive if there are no more reloads
5194 ??? Really it would be nicer to have smarter handling
5195 for that kind of reg class, where a problem like this is normal.
5196 Perhaps those classes should be avoided for reloading
5197 by use of more alternatives. */
5199 int force_group = rld[r].nregs > 1 && ! last_reload;
5201 /* If we want a single register and haven't yet found one,
5202 take any reg in the right class and not in use.
5203 If we want a consecutive group, here is where we look for it.
5205 We use two passes so we can first look for reload regs to
5206 reuse, which are already in use for other reloads in this insn,
5207 and only then use additional registers.
5208 I think that maximizing reuse is needed to make sure we don't
5209 run out of reload regs. Suppose we have three reloads, and
5210 reloads A and B can share regs. These need two regs.
5211 Suppose A and B are given different regs.
5212 That leaves none for C. */
5213 for (pass = 0; pass < 2; pass++)
5215 /* I is the index in spill_regs.
5216 We advance it round-robin between insns to use all spill regs
5217 equally, so that inherited reloads have a chance
5218 of leapfrogging each other. */
5222 for (count = 0; count < n_spills; count++)
5224 int class = (int) rld[r].class;
5230 regnum = spill_regs[i];
5232 if ((reload_reg_free_p (regnum, rld[r].opnum,
5235 /* We check reload_reg_used to make sure we
5236 don't clobber the return register. */
5237 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5238 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5239 rld[r].when_needed, rld[r].in,
5241 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5242 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5243 /* Look first for regs to share, then for unshared. But
5244 don't share regs used for inherited reloads; they are
5245 the ones we want to preserve. */
5247 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5249 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5252 int nr = hard_regno_nregs[regnum][rld[r].mode];
5253 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5254 (on 68000) got us two FP regs. If NR is 1,
5255 we would reject both of them. */
5258 /* If we need only one reg, we have already won. */
5261 /* But reject a single reg if we demand a group. */
5266 /* Otherwise check that as many consecutive regs as we need
5267 are available here. */
5270 int regno = regnum + nr - 1;
5271 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5272 && spill_reg_order[regno] >= 0
5273 && reload_reg_free_p (regno, rld[r].opnum,
5274 rld[r].when_needed)))
5283 /* If we found something on pass 1, omit pass 2. */
5284 if (count < n_spills)
5288 /* We should have found a spill register by now. */
5289 if (count >= n_spills)
5292 /* I is the index in SPILL_REG_RTX of the reload register we are to
5293 allocate. Get an rtx for it and find its register number. */
5295 return set_reload_reg (i, r);
5298 /* Initialize all the tables needed to allocate reload registers.
5299 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5300 is the array we use to restore the reg_rtx field for every reload. */
5303 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5307 for (i = 0; i < n_reloads; i++)
5308 rld[i].reg_rtx = save_reload_reg_rtx[i];
5310 memset (reload_inherited, 0, MAX_RELOADS);
5311 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5312 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5314 CLEAR_HARD_REG_SET (reload_reg_used);
5315 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5316 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5317 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5318 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5319 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5321 CLEAR_HARD_REG_SET (reg_used_in_insn);
5324 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5325 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5326 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5327 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5328 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5329 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5332 for (i = 0; i < reload_n_operands; i++)
5334 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5335 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5336 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5337 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5338 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5339 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5342 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5344 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5346 for (i = 0; i < n_reloads; i++)
5347 /* If we have already decided to use a certain register,
5348 don't use it in another way. */
5350 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5351 rld[i].when_needed, rld[i].mode);
5354 /* Assign hard reg targets for the pseudo-registers we must reload
5355 into hard regs for this insn.
5356 Also output the instructions to copy them in and out of the hard regs.
5358 For machines with register classes, we are responsible for
5359 finding a reload reg in the proper class. */
5362 choose_reload_regs (struct insn_chain *chain)
5364 rtx insn = chain->insn;
5366 unsigned int max_group_size = 1;
5367 enum reg_class group_class = NO_REGS;
5368 int pass, win, inheritance;
5370 rtx save_reload_reg_rtx[MAX_RELOADS];
5372 /* In order to be certain of getting the registers we need,
5373 we must sort the reloads into order of increasing register class.
5374 Then our grabbing of reload registers will parallel the process
5375 that provided the reload registers.
5377 Also note whether any of the reloads wants a consecutive group of regs.
5378 If so, record the maximum size of the group desired and what
5379 register class contains all the groups needed by this insn. */
5381 for (j = 0; j < n_reloads; j++)
5383 reload_order[j] = j;
5384 reload_spill_index[j] = -1;
5386 if (rld[j].nregs > 1)
5388 max_group_size = MAX (rld[j].nregs, max_group_size);
5390 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5393 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5397 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5399 /* If -O, try first with inheritance, then turning it off.
5400 If not -O, don't do inheritance.
5401 Using inheritance when not optimizing leads to paradoxes
5402 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5403 because one side of the comparison might be inherited. */
5405 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5407 choose_reload_regs_init (chain, save_reload_reg_rtx);
5409 /* Process the reloads in order of preference just found.
5410 Beyond this point, subregs can be found in reload_reg_rtx.
5412 This used to look for an existing reloaded home for all of the
5413 reloads, and only then perform any new reloads. But that could lose
5414 if the reloads were done out of reg-class order because a later
5415 reload with a looser constraint might have an old home in a register
5416 needed by an earlier reload with a tighter constraint.
5418 To solve this, we make two passes over the reloads, in the order
5419 described above. In the first pass we try to inherit a reload
5420 from a previous insn. If there is a later reload that needs a
5421 class that is a proper subset of the class being processed, we must
5422 also allocate a spill register during the first pass.
5424 Then make a second pass over the reloads to allocate any reloads
5425 that haven't been given registers yet. */
5427 for (j = 0; j < n_reloads; j++)
5429 int r = reload_order[j];
5430 rtx search_equiv = NULL_RTX;
5432 /* Ignore reloads that got marked inoperative. */
5433 if (rld[r].out == 0 && rld[r].in == 0
5434 && ! rld[r].secondary_p)
5437 /* If find_reloads chose to use reload_in or reload_out as a reload
5438 register, we don't need to chose one. Otherwise, try even if it
5439 found one since we might save an insn if we find the value lying
5441 Try also when reload_in is a pseudo without a hard reg. */
5442 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5443 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5444 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5445 && !MEM_P (rld[r].in)
5446 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5449 #if 0 /* No longer needed for correct operation.
5450 It might give better code, or might not; worth an experiment? */
5451 /* If this is an optional reload, we can't inherit from earlier insns
5452 until we are sure that any non-optional reloads have been allocated.
5453 The following code takes advantage of the fact that optional reloads
5454 are at the end of reload_order. */
5455 if (rld[r].optional != 0)
5456 for (i = 0; i < j; i++)
5457 if ((rld[reload_order[i]].out != 0
5458 || rld[reload_order[i]].in != 0
5459 || rld[reload_order[i]].secondary_p)
5460 && ! rld[reload_order[i]].optional
5461 && rld[reload_order[i]].reg_rtx == 0)
5462 allocate_reload_reg (chain, reload_order[i], 0);
5465 /* First see if this pseudo is already available as reloaded
5466 for a previous insn. We cannot try to inherit for reloads
5467 that are smaller than the maximum number of registers needed
5468 for groups unless the register we would allocate cannot be used
5471 We could check here to see if this is a secondary reload for
5472 an object that is already in a register of the desired class.
5473 This would avoid the need for the secondary reload register.
5474 But this is complex because we can't easily determine what
5475 objects might want to be loaded via this reload. So let a
5476 register be allocated here. In `emit_reload_insns' we suppress
5477 one of the loads in the case described above. */
5483 enum machine_mode mode = VOIDmode;
5487 else if (REG_P (rld[r].in))
5489 regno = REGNO (rld[r].in);
5490 mode = GET_MODE (rld[r].in);
5492 else if (REG_P (rld[r].in_reg))
5494 regno = REGNO (rld[r].in_reg);
5495 mode = GET_MODE (rld[r].in_reg);
5497 else if (GET_CODE (rld[r].in_reg) == SUBREG
5498 && REG_P (SUBREG_REG (rld[r].in_reg)))
5500 byte = SUBREG_BYTE (rld[r].in_reg);
5501 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5502 if (regno < FIRST_PSEUDO_REGISTER)
5503 regno = subreg_regno (rld[r].in_reg);
5504 mode = GET_MODE (rld[r].in_reg);
5507 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5508 || GET_CODE (rld[r].in_reg) == PRE_DEC
5509 || GET_CODE (rld[r].in_reg) == POST_INC
5510 || GET_CODE (rld[r].in_reg) == POST_DEC)
5511 && REG_P (XEXP (rld[r].in_reg, 0)))
5513 regno = REGNO (XEXP (rld[r].in_reg, 0));
5514 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5515 rld[r].out = rld[r].in;
5519 /* This won't work, since REGNO can be a pseudo reg number.
5520 Also, it takes much more hair to keep track of all the things
5521 that can invalidate an inherited reload of part of a pseudoreg. */
5522 else if (GET_CODE (rld[r].in) == SUBREG
5523 && REG_P (SUBREG_REG (rld[r].in)))
5524 regno = subreg_regno (rld[r].in);
5527 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5529 enum reg_class class = rld[r].class, last_class;
5530 rtx last_reg = reg_last_reload_reg[regno];
5531 enum machine_mode need_mode;
5533 i = REGNO (last_reg);
5534 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5535 last_class = REGNO_REG_CLASS (i);
5541 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
5542 + byte * BITS_PER_UNIT,
5543 GET_MODE_CLASS (mode));
5545 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5546 >= GET_MODE_SIZE (need_mode))
5547 #ifdef CANNOT_CHANGE_MODE_CLASS
5548 /* Verify that the register in "i" can be obtained
5550 && !REG_CANNOT_CHANGE_MODE_P (REGNO (last_reg),
5551 GET_MODE (last_reg),
5554 && reg_reloaded_contents[i] == regno
5555 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5556 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5557 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5558 /* Even if we can't use this register as a reload
5559 register, we might use it for reload_override_in,
5560 if copying it to the desired class is cheap
5562 || ((REGISTER_MOVE_COST (mode, last_class, class)
5563 < MEMORY_MOVE_COST (mode, class, 1))
5564 && (secondary_reload_class (1, class, mode,
5567 #ifdef SECONDARY_MEMORY_NEEDED
5568 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5573 && (rld[r].nregs == max_group_size
5574 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5576 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5577 rld[r].when_needed, rld[r].in,
5580 /* If a group is needed, verify that all the subsequent
5581 registers still have their values intact. */
5582 int nr = hard_regno_nregs[i][rld[r].mode];
5585 for (k = 1; k < nr; k++)
5586 if (reg_reloaded_contents[i + k] != regno
5587 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5595 last_reg = (GET_MODE (last_reg) == mode
5596 ? last_reg : gen_rtx_REG (mode, i));
5599 for (k = 0; k < nr; k++)
5600 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5603 /* We found a register that contains the
5604 value we need. If this register is the
5605 same as an `earlyclobber' operand of the
5606 current insn, just mark it as a place to
5607 reload from since we can't use it as the
5608 reload register itself. */
5610 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5611 if (reg_overlap_mentioned_for_reload_p
5612 (reg_last_reload_reg[regno],
5613 reload_earlyclobbers[i1]))
5616 if (i1 != n_earlyclobbers
5617 || ! (free_for_value_p (i, rld[r].mode,
5619 rld[r].when_needed, rld[r].in,
5621 /* Don't use it if we'd clobber a pseudo reg. */
5622 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5624 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5625 /* Don't clobber the frame pointer. */
5626 || (i == HARD_FRAME_POINTER_REGNUM
5627 && frame_pointer_needed
5629 /* Don't really use the inherited spill reg
5630 if we need it wider than we've got it. */
5631 || (GET_MODE_SIZE (rld[r].mode)
5632 > GET_MODE_SIZE (mode))
5635 /* If find_reloads chose reload_out as reload
5636 register, stay with it - that leaves the
5637 inherited register for subsequent reloads. */
5638 || (rld[r].out && rld[r].reg_rtx
5639 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5641 if (! rld[r].optional)
5643 reload_override_in[r] = last_reg;
5644 reload_inheritance_insn[r]
5645 = reg_reloaded_insn[i];
5651 /* We can use this as a reload reg. */
5652 /* Mark the register as in use for this part of
5654 mark_reload_reg_in_use (i,
5658 rld[r].reg_rtx = last_reg;
5659 reload_inherited[r] = 1;
5660 reload_inheritance_insn[r]
5661 = reg_reloaded_insn[i];
5662 reload_spill_index[r] = i;
5663 for (k = 0; k < nr; k++)
5664 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5672 /* Here's another way to see if the value is already lying around. */
5675 && ! reload_inherited[r]
5677 && (CONSTANT_P (rld[r].in)
5678 || GET_CODE (rld[r].in) == PLUS
5679 || REG_P (rld[r].in)
5680 || MEM_P (rld[r].in))
5681 && (rld[r].nregs == max_group_size
5682 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5683 search_equiv = rld[r].in;
5684 /* If this is an output reload from a simple move insn, look
5685 if an equivalence for the input is available. */
5686 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5688 rtx set = single_set (insn);
5691 && rtx_equal_p (rld[r].out, SET_DEST (set))
5692 && CONSTANT_P (SET_SRC (set)))
5693 search_equiv = SET_SRC (set);
5699 = find_equiv_reg (search_equiv, insn, rld[r].class,
5700 -1, NULL, 0, rld[r].mode);
5706 regno = REGNO (equiv);
5709 /* This must be a SUBREG of a hard register.
5710 Make a new REG since this might be used in an
5711 address and not all machines support SUBREGs
5713 gcc_assert (GET_CODE (equiv) == SUBREG);
5714 regno = subreg_regno (equiv);
5715 equiv = gen_rtx_REG (rld[r].mode, regno);
5716 /* If we choose EQUIV as the reload register, but the
5717 loop below decides to cancel the inheritance, we'll
5718 end up reloading EQUIV in rld[r].mode, not the mode
5719 it had originally. That isn't safe when EQUIV isn't
5720 available as a spill register since its value might
5721 still be live at this point. */
5722 for (i = regno; i < regno + (int) rld[r].nregs; i++)
5723 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
5728 /* If we found a spill reg, reject it unless it is free
5729 and of the desired class. */
5733 int bad_for_class = 0;
5734 int max_regno = regno + rld[r].nregs;
5736 for (i = regno; i < max_regno; i++)
5738 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5740 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5745 && ! free_for_value_p (regno, rld[r].mode,
5746 rld[r].opnum, rld[r].when_needed,
5747 rld[r].in, rld[r].out, r, 1))
5752 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5755 /* We found a register that contains the value we need.
5756 If this register is the same as an `earlyclobber' operand
5757 of the current insn, just mark it as a place to reload from
5758 since we can't use it as the reload register itself. */
5761 for (i = 0; i < n_earlyclobbers; i++)
5762 if (reg_overlap_mentioned_for_reload_p (equiv,
5763 reload_earlyclobbers[i]))
5765 if (! rld[r].optional)
5766 reload_override_in[r] = equiv;
5771 /* If the equiv register we have found is explicitly clobbered
5772 in the current insn, it depends on the reload type if we
5773 can use it, use it for reload_override_in, or not at all.
5774 In particular, we then can't use EQUIV for a
5775 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5779 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
5780 switch (rld[r].when_needed)
5782 case RELOAD_FOR_OTHER_ADDRESS:
5783 case RELOAD_FOR_INPADDR_ADDRESS:
5784 case RELOAD_FOR_INPUT_ADDRESS:
5785 case RELOAD_FOR_OPADDR_ADDR:
5788 case RELOAD_FOR_INPUT:
5789 case RELOAD_FOR_OPERAND_ADDRESS:
5790 if (! rld[r].optional)
5791 reload_override_in[r] = equiv;
5797 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5798 switch (rld[r].when_needed)
5800 case RELOAD_FOR_OTHER_ADDRESS:
5801 case RELOAD_FOR_INPADDR_ADDRESS:
5802 case RELOAD_FOR_INPUT_ADDRESS:
5803 case RELOAD_FOR_OPADDR_ADDR:
5804 case RELOAD_FOR_OPERAND_ADDRESS:
5805 case RELOAD_FOR_INPUT:
5808 if (! rld[r].optional)
5809 reload_override_in[r] = equiv;
5817 /* If we found an equivalent reg, say no code need be generated
5818 to load it, and use it as our reload reg. */
5820 && (regno != HARD_FRAME_POINTER_REGNUM
5821 || !frame_pointer_needed))
5823 int nr = hard_regno_nregs[regno][rld[r].mode];
5825 rld[r].reg_rtx = equiv;
5826 reload_inherited[r] = 1;
5828 /* If reg_reloaded_valid is not set for this register,
5829 there might be a stale spill_reg_store lying around.
5830 We must clear it, since otherwise emit_reload_insns
5831 might delete the store. */
5832 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5833 spill_reg_store[regno] = NULL_RTX;
5834 /* If any of the hard registers in EQUIV are spill
5835 registers, mark them as in use for this insn. */
5836 for (k = 0; k < nr; k++)
5838 i = spill_reg_order[regno + k];
5841 mark_reload_reg_in_use (regno, rld[r].opnum,
5844 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5851 /* If we found a register to use already, or if this is an optional
5852 reload, we are done. */
5853 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5857 /* No longer needed for correct operation. Might or might
5858 not give better code on the average. Want to experiment? */
5860 /* See if there is a later reload that has a class different from our
5861 class that intersects our class or that requires less register
5862 than our reload. If so, we must allocate a register to this
5863 reload now, since that reload might inherit a previous reload
5864 and take the only available register in our class. Don't do this
5865 for optional reloads since they will force all previous reloads
5866 to be allocated. Also don't do this for reloads that have been
5869 for (i = j + 1; i < n_reloads; i++)
5871 int s = reload_order[i];
5873 if ((rld[s].in == 0 && rld[s].out == 0
5874 && ! rld[s].secondary_p)
5878 if ((rld[s].class != rld[r].class
5879 && reg_classes_intersect_p (rld[r].class,
5881 || rld[s].nregs < rld[r].nregs)
5888 allocate_reload_reg (chain, r, j == n_reloads - 1);
5892 /* Now allocate reload registers for anything non-optional that
5893 didn't get one yet. */
5894 for (j = 0; j < n_reloads; j++)
5896 int r = reload_order[j];
5898 /* Ignore reloads that got marked inoperative. */
5899 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5902 /* Skip reloads that already have a register allocated or are
5904 if (rld[r].reg_rtx != 0 || rld[r].optional)
5907 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5911 /* If that loop got all the way, we have won. */
5918 /* Loop around and try without any inheritance. */
5923 /* First undo everything done by the failed attempt
5924 to allocate with inheritance. */
5925 choose_reload_regs_init (chain, save_reload_reg_rtx);
5927 /* Some sanity tests to verify that the reloads found in the first
5928 pass are identical to the ones we have now. */
5929 gcc_assert (chain->n_reloads == n_reloads);
5931 for (i = 0; i < n_reloads; i++)
5933 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5935 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
5936 for (j = 0; j < n_spills; j++)
5937 if (spill_regs[j] == chain->rld[i].regno)
5938 if (! set_reload_reg (j, i))
5939 failed_reload (chain->insn, i);
5943 /* If we thought we could inherit a reload, because it seemed that
5944 nothing else wanted the same reload register earlier in the insn,
5945 verify that assumption, now that all reloads have been assigned.
5946 Likewise for reloads where reload_override_in has been set. */
5948 /* If doing expensive optimizations, do one preliminary pass that doesn't
5949 cancel any inheritance, but removes reloads that have been needed only
5950 for reloads that we know can be inherited. */
5951 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5953 for (j = 0; j < n_reloads; j++)
5955 int r = reload_order[j];
5957 if (reload_inherited[r] && rld[r].reg_rtx)
5958 check_reg = rld[r].reg_rtx;
5959 else if (reload_override_in[r]
5960 && (REG_P (reload_override_in[r])
5961 || GET_CODE (reload_override_in[r]) == SUBREG))
5962 check_reg = reload_override_in[r];
5965 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5966 rld[r].opnum, rld[r].when_needed, rld[r].in,
5967 (reload_inherited[r]
5968 ? rld[r].out : const0_rtx),
5973 reload_inherited[r] = 0;
5974 reload_override_in[r] = 0;
5976 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5977 reload_override_in, then we do not need its related
5978 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5979 likewise for other reload types.
5980 We handle this by removing a reload when its only replacement
5981 is mentioned in reload_in of the reload we are going to inherit.
5982 A special case are auto_inc expressions; even if the input is
5983 inherited, we still need the address for the output. We can
5984 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5985 If we succeeded removing some reload and we are doing a preliminary
5986 pass just to remove such reloads, make another pass, since the
5987 removal of one reload might allow us to inherit another one. */
5989 && rld[r].out != rld[r].in
5990 && remove_address_replacements (rld[r].in) && pass)
5995 /* Now that reload_override_in is known valid,
5996 actually override reload_in. */
5997 for (j = 0; j < n_reloads; j++)
5998 if (reload_override_in[j])
5999 rld[j].in = reload_override_in[j];
6001 /* If this reload won't be done because it has been canceled or is
6002 optional and not inherited, clear reload_reg_rtx so other
6003 routines (such as subst_reloads) don't get confused. */
6004 for (j = 0; j < n_reloads; j++)
6005 if (rld[j].reg_rtx != 0
6006 && ((rld[j].optional && ! reload_inherited[j])
6007 || (rld[j].in == 0 && rld[j].out == 0
6008 && ! rld[j].secondary_p)))
6010 int regno = true_regnum (rld[j].reg_rtx);
6012 if (spill_reg_order[regno] >= 0)
6013 clear_reload_reg_in_use (regno, rld[j].opnum,
6014 rld[j].when_needed, rld[j].mode);
6016 reload_spill_index[j] = -1;
6019 /* Record which pseudos and which spill regs have output reloads. */
6020 for (j = 0; j < n_reloads; j++)
6022 int r = reload_order[j];
6024 i = reload_spill_index[r];
6026 /* I is nonneg if this reload uses a register.
6027 If rld[r].reg_rtx is 0, this is an optional reload
6028 that we opted to ignore. */
6029 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6030 && rld[r].reg_rtx != 0)
6032 int nregno = REGNO (rld[r].out_reg);
6035 if (nregno < FIRST_PSEUDO_REGISTER)
6036 nr = hard_regno_nregs[nregno][rld[r].mode];
6039 reg_has_output_reload[nregno + nr] = 1;
6043 nr = hard_regno_nregs[i][rld[r].mode];
6045 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6048 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6049 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6050 || rld[r].when_needed == RELOAD_FOR_INSN);
6055 /* Deallocate the reload register for reload R. This is called from
6056 remove_address_replacements. */
6059 deallocate_reload_reg (int r)
6063 if (! rld[r].reg_rtx)
6065 regno = true_regnum (rld[r].reg_rtx);
6067 if (spill_reg_order[regno] >= 0)
6068 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6070 reload_spill_index[r] = -1;
6073 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6074 reloads of the same item for fear that we might not have enough reload
6075 registers. However, normally they will get the same reload register
6076 and hence actually need not be loaded twice.
6078 Here we check for the most common case of this phenomenon: when we have
6079 a number of reloads for the same object, each of which were allocated
6080 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6081 reload, and is not modified in the insn itself. If we find such,
6082 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6083 This will not increase the number of spill registers needed and will
6084 prevent redundant code. */
6087 merge_assigned_reloads (rtx insn)
6091 /* Scan all the reloads looking for ones that only load values and
6092 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6093 assigned and not modified by INSN. */
6095 for (i = 0; i < n_reloads; i++)
6097 int conflicting_input = 0;
6098 int max_input_address_opnum = -1;
6099 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6101 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6102 || rld[i].out != 0 || rld[i].reg_rtx == 0
6103 || reg_set_p (rld[i].reg_rtx, insn))
6106 /* Look at all other reloads. Ensure that the only use of this
6107 reload_reg_rtx is in a reload that just loads the same value
6108 as we do. Note that any secondary reloads must be of the identical
6109 class since the values, modes, and result registers are the
6110 same, so we need not do anything with any secondary reloads. */
6112 for (j = 0; j < n_reloads; j++)
6114 if (i == j || rld[j].reg_rtx == 0
6115 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6119 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6120 && rld[j].opnum > max_input_address_opnum)
6121 max_input_address_opnum = rld[j].opnum;
6123 /* If the reload regs aren't exactly the same (e.g, different modes)
6124 or if the values are different, we can't merge this reload.
6125 But if it is an input reload, we might still merge
6126 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6128 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6129 || rld[j].out != 0 || rld[j].in == 0
6130 || ! rtx_equal_p (rld[i].in, rld[j].in))
6132 if (rld[j].when_needed != RELOAD_FOR_INPUT
6133 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6134 || rld[i].opnum > rld[j].opnum)
6135 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6137 conflicting_input = 1;
6138 if (min_conflicting_input_opnum > rld[j].opnum)
6139 min_conflicting_input_opnum = rld[j].opnum;
6143 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6144 we, in fact, found any matching reloads. */
6147 && max_input_address_opnum <= min_conflicting_input_opnum)
6149 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6151 for (j = 0; j < n_reloads; j++)
6152 if (i != j && rld[j].reg_rtx != 0
6153 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6154 && (! conflicting_input
6155 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6156 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6158 rld[i].when_needed = RELOAD_OTHER;
6160 reload_spill_index[j] = -1;
6161 transfer_replacements (i, j);
6164 /* If this is now RELOAD_OTHER, look for any reloads that load
6165 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6166 if they were for inputs, RELOAD_OTHER for outputs. Note that
6167 this test is equivalent to looking for reloads for this operand
6169 /* We must take special care with RELOAD_FOR_OUTPUT_ADDRESS; it may
6170 share registers with a RELOAD_FOR_INPUT, so we can not change it
6171 to RELOAD_FOR_OTHER_ADDRESS. We should never need to, since we
6172 do not modify RELOAD_FOR_OUTPUT. */
6174 if (rld[i].when_needed == RELOAD_OTHER)
6175 for (j = 0; j < n_reloads; j++)
6177 && rld[j].when_needed != RELOAD_OTHER
6178 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6179 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6180 && (! conflicting_input
6181 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6182 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6183 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6189 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6190 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6191 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6193 /* Check to see if we accidentally converted two
6194 reloads that use the same reload register with
6195 different inputs to the same type. If so, the
6196 resulting code won't work. */
6198 for (k = 0; k < j; k++)
6199 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6200 || rld[k].when_needed != rld[j].when_needed
6201 || !rtx_equal_p (rld[k].reg_rtx,
6203 || rtx_equal_p (rld[k].in,
6210 /* These arrays are filled by emit_reload_insns and its subroutines. */
6211 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6212 static rtx other_input_address_reload_insns = 0;
6213 static rtx other_input_reload_insns = 0;
6214 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6215 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6216 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6217 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6218 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6219 static rtx operand_reload_insns = 0;
6220 static rtx other_operand_reload_insns = 0;
6221 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6223 /* Values to be put in spill_reg_store are put here first. */
6224 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6225 static HARD_REG_SET reg_reloaded_died;
6227 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6228 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6229 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6230 adjusted register, and return true. Otherwise, return false. */
6232 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6233 enum reg_class new_class,
6234 enum machine_mode new_mode)
6239 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6241 unsigned regno = REGNO (reg);
6243 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6245 if (GET_MODE (reg) != new_mode)
6247 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6249 if (hard_regno_nregs[regno][new_mode]
6250 > hard_regno_nregs[regno][GET_MODE (reg)])
6252 reg = reload_adjust_reg_for_mode (reg, new_mode);
6260 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6261 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6262 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6263 adjusted register, and return true. Otherwise, return false. */
6265 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6266 enum insn_code icode)
6269 enum reg_class new_class = scratch_reload_class (icode);
6270 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6272 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6273 new_class, new_mode);
6276 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6277 has the number J. OLD contains the value to be used as input. */
6280 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6283 rtx insn = chain->insn;
6284 rtx reloadreg = rl->reg_rtx;
6285 rtx oldequiv_reg = 0;
6288 enum machine_mode mode;
6291 /* Determine the mode to reload in.
6292 This is very tricky because we have three to choose from.
6293 There is the mode the insn operand wants (rl->inmode).
6294 There is the mode of the reload register RELOADREG.
6295 There is the intrinsic mode of the operand, which we could find
6296 by stripping some SUBREGs.
6297 It turns out that RELOADREG's mode is irrelevant:
6298 we can change that arbitrarily.
6300 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6301 then the reload reg may not support QImode moves, so use SImode.
6302 If foo is in memory due to spilling a pseudo reg, this is safe,
6303 because the QImode value is in the least significant part of a
6304 slot big enough for a SImode. If foo is some other sort of
6305 memory reference, then it is impossible to reload this case,
6306 so previous passes had better make sure this never happens.
6308 Then consider a one-word union which has SImode and one of its
6309 members is a float, being fetched as (SUBREG:SF union:SI).
6310 We must fetch that as SFmode because we could be loading into
6311 a float-only register. In this case OLD's mode is correct.
6313 Consider an immediate integer: it has VOIDmode. Here we need
6314 to get a mode from something else.
6316 In some cases, there is a fourth mode, the operand's
6317 containing mode. If the insn specifies a containing mode for
6318 this operand, it overrides all others.
6320 I am not sure whether the algorithm here is always right,
6321 but it does the right things in those cases. */
6323 mode = GET_MODE (old);
6324 if (mode == VOIDmode)
6327 /* delete_output_reload is only invoked properly if old contains
6328 the original pseudo register. Since this is replaced with a
6329 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6330 find the pseudo in RELOAD_IN_REG. */
6331 if (reload_override_in[j]
6332 && REG_P (rl->in_reg))
6339 else if (REG_P (oldequiv))
6340 oldequiv_reg = oldequiv;
6341 else if (GET_CODE (oldequiv) == SUBREG)
6342 oldequiv_reg = SUBREG_REG (oldequiv);
6344 /* If we are reloading from a register that was recently stored in
6345 with an output-reload, see if we can prove there was
6346 actually no need to store the old value in it. */
6348 if (optimize && REG_P (oldequiv)
6349 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6350 && spill_reg_store[REGNO (oldequiv)]
6352 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6353 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6355 delete_output_reload (insn, j, REGNO (oldequiv));
6357 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6358 then load RELOADREG from OLDEQUIV. Note that we cannot use
6359 gen_lowpart_common since it can do the wrong thing when
6360 RELOADREG has a multi-word mode. Note that RELOADREG
6361 must always be a REG here. */
6363 if (GET_MODE (reloadreg) != mode)
6364 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6365 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6366 oldequiv = SUBREG_REG (oldequiv);
6367 if (GET_MODE (oldequiv) != VOIDmode
6368 && mode != GET_MODE (oldequiv))
6369 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6371 /* Switch to the right place to emit the reload insns. */
6372 switch (rl->when_needed)
6375 where = &other_input_reload_insns;
6377 case RELOAD_FOR_INPUT:
6378 where = &input_reload_insns[rl->opnum];
6380 case RELOAD_FOR_INPUT_ADDRESS:
6381 where = &input_address_reload_insns[rl->opnum];
6383 case RELOAD_FOR_INPADDR_ADDRESS:
6384 where = &inpaddr_address_reload_insns[rl->opnum];
6386 case RELOAD_FOR_OUTPUT_ADDRESS:
6387 where = &output_address_reload_insns[rl->opnum];
6389 case RELOAD_FOR_OUTADDR_ADDRESS:
6390 where = &outaddr_address_reload_insns[rl->opnum];
6392 case RELOAD_FOR_OPERAND_ADDRESS:
6393 where = &operand_reload_insns;
6395 case RELOAD_FOR_OPADDR_ADDR:
6396 where = &other_operand_reload_insns;
6398 case RELOAD_FOR_OTHER_ADDRESS:
6399 where = &other_input_address_reload_insns;
6405 push_to_sequence (*where);
6407 /* Auto-increment addresses must be reloaded in a special way. */
6408 if (rl->out && ! rl->out_reg)
6410 /* We are not going to bother supporting the case where a
6411 incremented register can't be copied directly from
6412 OLDEQUIV since this seems highly unlikely. */
6413 gcc_assert (rl->secondary_in_reload < 0);
6415 if (reload_inherited[j])
6416 oldequiv = reloadreg;
6418 old = XEXP (rl->in_reg, 0);
6420 if (optimize && REG_P (oldequiv)
6421 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6422 && spill_reg_store[REGNO (oldequiv)]
6424 && (dead_or_set_p (insn,
6425 spill_reg_stored_to[REGNO (oldequiv)])
6426 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6428 delete_output_reload (insn, j, REGNO (oldequiv));
6430 /* Prevent normal processing of this reload. */
6432 /* Output a special code sequence for this case. */
6433 new_spill_reg_store[REGNO (reloadreg)]
6434 = inc_for_reload (reloadreg, oldequiv, rl->out,
6438 /* If we are reloading a pseudo-register that was set by the previous
6439 insn, see if we can get rid of that pseudo-register entirely
6440 by redirecting the previous insn into our reload register. */
6442 else if (optimize && REG_P (old)
6443 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6444 && dead_or_set_p (insn, old)
6445 /* This is unsafe if some other reload
6446 uses the same reg first. */
6447 && ! conflicts_with_override (reloadreg)
6448 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6449 rl->when_needed, old, rl->out, j, 0))
6451 rtx temp = PREV_INSN (insn);
6452 while (temp && NOTE_P (temp))
6453 temp = PREV_INSN (temp);
6455 && NONJUMP_INSN_P (temp)
6456 && GET_CODE (PATTERN (temp)) == SET
6457 && SET_DEST (PATTERN (temp)) == old
6458 /* Make sure we can access insn_operand_constraint. */
6459 && asm_noperands (PATTERN (temp)) < 0
6460 /* This is unsafe if operand occurs more than once in current
6461 insn. Perhaps some occurrences aren't reloaded. */
6462 && count_occurrences (PATTERN (insn), old, 0) == 1)
6464 rtx old = SET_DEST (PATTERN (temp));
6465 /* Store into the reload register instead of the pseudo. */
6466 SET_DEST (PATTERN (temp)) = reloadreg;
6468 /* Verify that resulting insn is valid. */
6469 extract_insn (temp);
6470 if (constrain_operands (1))
6472 /* If the previous insn is an output reload, the source is
6473 a reload register, and its spill_reg_store entry will
6474 contain the previous destination. This is now
6476 if (REG_P (SET_SRC (PATTERN (temp)))
6477 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6479 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6480 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6483 /* If these are the only uses of the pseudo reg,
6484 pretend for GDB it lives in the reload reg we used. */
6485 if (REG_N_DEATHS (REGNO (old)) == 1
6486 && REG_N_SETS (REGNO (old)) == 1)
6488 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6489 alter_reg (REGNO (old), -1);
6495 SET_DEST (PATTERN (temp)) = old;
6500 /* We can't do that, so output an insn to load RELOADREG. */
6502 /* If we have a secondary reload, pick up the secondary register
6503 and icode, if any. If OLDEQUIV and OLD are different or
6504 if this is an in-out reload, recompute whether or not we
6505 still need a secondary register and what the icode should
6506 be. If we still need a secondary register and the class or
6507 icode is different, go back to reloading from OLD if using
6508 OLDEQUIV means that we got the wrong type of register. We
6509 cannot have different class or icode due to an in-out reload
6510 because we don't make such reloads when both the input and
6511 output need secondary reload registers. */
6513 if (! special && rl->secondary_in_reload >= 0)
6515 rtx second_reload_reg = 0;
6516 rtx third_reload_reg = 0;
6517 int secondary_reload = rl->secondary_in_reload;
6518 rtx real_oldequiv = oldequiv;
6521 enum insn_code icode;
6522 enum insn_code tertiary_icode = CODE_FOR_nothing;
6524 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6525 and similarly for OLD.
6526 See comments in get_secondary_reload in reload.c. */
6527 /* If it is a pseudo that cannot be replaced with its
6528 equivalent MEM, we must fall back to reload_in, which
6529 will have all the necessary substitutions registered.
6530 Likewise for a pseudo that can't be replaced with its
6531 equivalent constant.
6533 Take extra care for subregs of such pseudos. Note that
6534 we cannot use reg_equiv_mem in this case because it is
6535 not in the right mode. */
6538 if (GET_CODE (tmp) == SUBREG)
6539 tmp = SUBREG_REG (tmp);
6541 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6542 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6543 || reg_equiv_constant[REGNO (tmp)] != 0))
6545 if (! reg_equiv_mem[REGNO (tmp)]
6546 || num_not_at_initial_offset
6547 || GET_CODE (oldequiv) == SUBREG)
6548 real_oldequiv = rl->in;
6550 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6554 if (GET_CODE (tmp) == SUBREG)
6555 tmp = SUBREG_REG (tmp);
6557 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6558 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6559 || reg_equiv_constant[REGNO (tmp)] != 0))
6561 if (! reg_equiv_mem[REGNO (tmp)]
6562 || num_not_at_initial_offset
6563 || GET_CODE (old) == SUBREG)
6566 real_old = reg_equiv_mem[REGNO (tmp)];
6569 second_reload_reg = rld[secondary_reload].reg_rtx;
6570 if (rld[secondary_reload].secondary_in_reload >= 0)
6572 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
6574 third_reload_reg = rld[tertiary_reload].reg_rtx;
6575 tertiary_icode = rld[secondary_reload].secondary_in_icode;
6576 /* We'd have to add more code for quartary reloads. */
6577 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
6579 icode = rl->secondary_in_icode;
6581 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6582 || (rl->in != 0 && rl->out != 0))
6584 secondary_reload_info sri, sri2;
6585 enum reg_class new_class, new_t_class;
6587 sri.icode = CODE_FOR_nothing;
6588 sri.prev_sri = NULL;
6589 new_class = targetm.secondary_reload (1, real_oldequiv, rl->class,
6592 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
6593 second_reload_reg = 0;
6594 else if (new_class == NO_REGS)
6596 if (reload_adjust_reg_for_icode (&second_reload_reg,
6597 third_reload_reg, sri.icode))
6598 icode = sri.icode, third_reload_reg = 0;
6600 oldequiv = old, real_oldequiv = real_old;
6602 else if (sri.icode != CODE_FOR_nothing)
6603 /* We currently lack a way to express this in reloads. */
6607 sri2.icode = CODE_FOR_nothing;
6608 sri2.prev_sri = &sri;
6609 new_t_class = targetm.secondary_reload (1, real_oldequiv,
6610 new_class, mode, &sri);
6611 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
6613 if (reload_adjust_reg_for_temp (&second_reload_reg,
6616 third_reload_reg = 0, tertiary_icode = sri2.icode;
6618 oldequiv = old, real_oldequiv = real_old;
6620 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
6622 rtx intermediate = second_reload_reg;
6624 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6626 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
6629 second_reload_reg = intermediate;
6630 tertiary_icode = sri2.icode;
6633 oldequiv = old, real_oldequiv = real_old;
6635 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
6637 rtx intermediate = second_reload_reg;
6639 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6641 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
6644 second_reload_reg = intermediate;
6645 tertiary_icode = sri2.icode;
6648 oldequiv = old, real_oldequiv = real_old;
6651 /* This could be handled more intelligently too. */
6652 oldequiv = old, real_oldequiv = real_old;
6656 /* If we still need a secondary reload register, check
6657 to see if it is being used as a scratch or intermediate
6658 register and generate code appropriately. If we need
6659 a scratch register, use REAL_OLDEQUIV since the form of
6660 the insn may depend on the actual address if it is
6663 if (second_reload_reg)
6665 if (icode != CODE_FOR_nothing)
6667 /* We'd have to add extra code to handle this case. */
6668 gcc_assert (!third_reload_reg);
6670 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6671 second_reload_reg));
6676 /* See if we need a scratch register to load the
6677 intermediate register (a tertiary reload). */
6678 if (tertiary_icode != CODE_FOR_nothing)
6680 emit_insn ((GEN_FCN (tertiary_icode)
6681 (second_reload_reg, real_oldequiv,
6682 third_reload_reg)));
6684 else if (third_reload_reg)
6686 gen_reload (third_reload_reg, real_oldequiv,
6689 gen_reload (second_reload_reg, third_reload_reg,
6694 gen_reload (second_reload_reg, real_oldequiv,
6698 oldequiv = second_reload_reg;
6703 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6705 rtx real_oldequiv = oldequiv;
6707 if ((REG_P (oldequiv)
6708 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6709 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6710 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6711 || (GET_CODE (oldequiv) == SUBREG
6712 && REG_P (SUBREG_REG (oldequiv))
6713 && (REGNO (SUBREG_REG (oldequiv))
6714 >= FIRST_PSEUDO_REGISTER)
6715 && ((reg_equiv_memory_loc
6716 [REGNO (SUBREG_REG (oldequiv))] != 0)
6717 || (reg_equiv_constant
6718 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6719 || (CONSTANT_P (oldequiv)
6720 && (PREFERRED_RELOAD_CLASS (oldequiv,
6721 REGNO_REG_CLASS (REGNO (reloadreg)))
6723 real_oldequiv = rl->in;
6724 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6728 if (flag_non_call_exceptions)
6729 copy_eh_notes (insn, get_insns ());
6731 /* End this sequence. */
6732 *where = get_insns ();
6735 /* Update reload_override_in so that delete_address_reloads_1
6736 can see the actual register usage. */
6738 reload_override_in[j] = oldequiv;
6741 /* Generate insns to for the output reload RL, which is for the insn described
6742 by CHAIN and has the number J. */
6744 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6747 rtx reloadreg = rl->reg_rtx;
6748 rtx insn = chain->insn;
6751 enum machine_mode mode = GET_MODE (old);
6754 if (rl->when_needed == RELOAD_OTHER)
6757 push_to_sequence (output_reload_insns[rl->opnum]);
6759 /* Determine the mode to reload in.
6760 See comments above (for input reloading). */
6762 if (mode == VOIDmode)
6764 /* VOIDmode should never happen for an output. */
6765 if (asm_noperands (PATTERN (insn)) < 0)
6766 /* It's the compiler's fault. */
6767 fatal_insn ("VOIDmode on an output", insn);
6768 error_for_asm (insn, "output operand is constant in %<asm%>");
6769 /* Prevent crash--use something we know is valid. */
6771 old = gen_rtx_REG (mode, REGNO (reloadreg));
6774 if (GET_MODE (reloadreg) != mode)
6775 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6777 /* If we need two reload regs, set RELOADREG to the intermediate
6778 one, since it will be stored into OLD. We might need a secondary
6779 register only for an input reload, so check again here. */
6781 if (rl->secondary_out_reload >= 0)
6784 int secondary_reload = rl->secondary_out_reload;
6785 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
6787 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
6788 && reg_equiv_mem[REGNO (old)] != 0)
6789 real_old = reg_equiv_mem[REGNO (old)];
6791 if (secondary_reload_class (0, rl->class, mode, real_old) != NO_REGS)
6793 rtx second_reloadreg = reloadreg;
6794 reloadreg = rld[secondary_reload].reg_rtx;
6796 /* See if RELOADREG is to be used as a scratch register
6797 or as an intermediate register. */
6798 if (rl->secondary_out_icode != CODE_FOR_nothing)
6800 /* We'd have to add extra code to handle this case. */
6801 gcc_assert (tertiary_reload < 0);
6803 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6804 (real_old, second_reloadreg, reloadreg)));
6809 /* See if we need both a scratch and intermediate reload
6812 enum insn_code tertiary_icode
6813 = rld[secondary_reload].secondary_out_icode;
6815 /* We'd have to add more code for quartary reloads. */
6816 gcc_assert (tertiary_reload < 0
6817 || rld[tertiary_reload].secondary_out_reload < 0);
6819 if (GET_MODE (reloadreg) != mode)
6820 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6822 if (tertiary_icode != CODE_FOR_nothing)
6824 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
6827 /* Copy primary reload reg to secondary reload reg.
6828 (Note that these have been swapped above, then
6829 secondary reload reg to OLD using our insn.) */
6831 /* If REAL_OLD is a paradoxical SUBREG, remove it
6832 and try to put the opposite SUBREG on
6834 if (GET_CODE (real_old) == SUBREG
6835 && (GET_MODE_SIZE (GET_MODE (real_old))
6836 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6837 && 0 != (tem = gen_lowpart_common
6838 (GET_MODE (SUBREG_REG (real_old)),
6840 real_old = SUBREG_REG (real_old), reloadreg = tem;
6842 gen_reload (reloadreg, second_reloadreg,
6843 rl->opnum, rl->when_needed);
6844 emit_insn ((GEN_FCN (tertiary_icode)
6845 (real_old, reloadreg, third_reloadreg)));
6851 /* Copy between the reload regs here and then to
6854 gen_reload (reloadreg, second_reloadreg,
6855 rl->opnum, rl->when_needed);
6856 if (tertiary_reload >= 0)
6858 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
6860 gen_reload (third_reloadreg, reloadreg,
6861 rl->opnum, rl->when_needed);
6862 reloadreg = third_reloadreg;
6869 /* Output the last reload insn. */
6874 /* Don't output the last reload if OLD is not the dest of
6875 INSN and is in the src and is clobbered by INSN. */
6876 if (! flag_expensive_optimizations
6878 || !(set = single_set (insn))
6879 || rtx_equal_p (old, SET_DEST (set))
6880 || !reg_mentioned_p (old, SET_SRC (set))
6881 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
6882 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
6883 gen_reload (old, reloadreg, rl->opnum,
6887 /* Look at all insns we emitted, just to be safe. */
6888 for (p = get_insns (); p; p = NEXT_INSN (p))
6891 rtx pat = PATTERN (p);
6893 /* If this output reload doesn't come from a spill reg,
6894 clear any memory of reloaded copies of the pseudo reg.
6895 If this output reload comes from a spill reg,
6896 reg_has_output_reload will make this do nothing. */
6897 note_stores (pat, forget_old_reloads_1, NULL);
6899 if (reg_mentioned_p (rl->reg_rtx, pat))
6901 rtx set = single_set (insn);
6902 if (reload_spill_index[j] < 0
6904 && SET_SRC (set) == rl->reg_rtx)
6906 int src = REGNO (SET_SRC (set));
6908 reload_spill_index[j] = src;
6909 SET_HARD_REG_BIT (reg_is_output_reload, src);
6910 if (find_regno_note (insn, REG_DEAD, src))
6911 SET_HARD_REG_BIT (reg_reloaded_died, src);
6913 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6915 int s = rl->secondary_out_reload;
6916 set = single_set (p);
6917 /* If this reload copies only to the secondary reload
6918 register, the secondary reload does the actual
6920 if (s >= 0 && set == NULL_RTX)
6921 /* We can't tell what function the secondary reload
6922 has and where the actual store to the pseudo is
6923 made; leave new_spill_reg_store alone. */
6926 && SET_SRC (set) == rl->reg_rtx
6927 && SET_DEST (set) == rld[s].reg_rtx)
6929 /* Usually the next instruction will be the
6930 secondary reload insn; if we can confirm
6931 that it is, setting new_spill_reg_store to
6932 that insn will allow an extra optimization. */
6933 rtx s_reg = rld[s].reg_rtx;
6934 rtx next = NEXT_INSN (p);
6935 rld[s].out = rl->out;
6936 rld[s].out_reg = rl->out_reg;
6937 set = single_set (next);
6938 if (set && SET_SRC (set) == s_reg
6939 && ! new_spill_reg_store[REGNO (s_reg)])
6941 SET_HARD_REG_BIT (reg_is_output_reload,
6943 new_spill_reg_store[REGNO (s_reg)] = next;
6947 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6952 if (rl->when_needed == RELOAD_OTHER)
6954 emit_insn (other_output_reload_insns[rl->opnum]);
6955 other_output_reload_insns[rl->opnum] = get_insns ();
6958 output_reload_insns[rl->opnum] = get_insns ();
6960 if (flag_non_call_exceptions)
6961 copy_eh_notes (insn, get_insns ());
6966 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6967 and has the number J. */
6969 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
6971 rtx insn = chain->insn;
6972 rtx old = (rl->in && MEM_P (rl->in)
6973 ? rl->in_reg : rl->in);
6976 /* AUTO_INC reloads need to be handled even if inherited. We got an
6977 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6978 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6979 && ! rtx_equal_p (rl->reg_rtx, old)
6980 && rl->reg_rtx != 0)
6981 emit_input_reload_insns (chain, rld + j, old, j);
6983 /* When inheriting a wider reload, we have a MEM in rl->in,
6984 e.g. inheriting a SImode output reload for
6985 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6986 if (optimize && reload_inherited[j] && rl->in
6988 && MEM_P (rl->in_reg)
6989 && reload_spill_index[j] >= 0
6990 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6991 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6993 /* If we are reloading a register that was recently stored in with an
6994 output-reload, see if we can prove there was
6995 actually no need to store the old value in it. */
6998 /* Only attempt this for input reloads; for RELOAD_OTHER we miss
6999 that there may be multiple uses of the previous output reload.
7000 Restricting to RELOAD_FOR_INPUT is mostly paranoia. */
7001 && rl->when_needed == RELOAD_FOR_INPUT
7002 && (reload_inherited[j] || reload_override_in[j])
7004 && REG_P (rl->reg_rtx)
7005 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
7007 /* There doesn't seem to be any reason to restrict this to pseudos
7008 and doing so loses in the case where we are copying from a
7009 register of the wrong class. */
7010 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
7011 >= FIRST_PSEUDO_REGISTER)
7013 /* The insn might have already some references to stackslots
7014 replaced by MEMs, while reload_out_reg still names the
7016 && (dead_or_set_p (insn,
7017 spill_reg_stored_to[REGNO (rl->reg_rtx)])
7018 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
7020 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
7023 /* Do output reloading for reload RL, which is for the insn described by
7024 CHAIN and has the number J.
7025 ??? At some point we need to support handling output reloads of
7026 JUMP_INSNs or insns that set cc0. */
7028 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7031 rtx insn = chain->insn;
7032 /* If this is an output reload that stores something that is
7033 not loaded in this same reload, see if we can eliminate a previous
7035 rtx pseudo = rl->out_reg;
7040 && ! rtx_equal_p (rl->in_reg, pseudo)
7041 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7042 && reg_last_reload_reg[REGNO (pseudo)])
7044 int pseudo_no = REGNO (pseudo);
7045 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7047 /* We don't need to test full validity of last_regno for
7048 inherit here; we only want to know if the store actually
7049 matches the pseudo. */
7050 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7051 && reg_reloaded_contents[last_regno] == pseudo_no
7052 && spill_reg_store[last_regno]
7053 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7054 delete_output_reload (insn, j, last_regno);
7059 || rl->reg_rtx == old
7060 || rl->reg_rtx == 0)
7063 /* An output operand that dies right away does need a reload,
7064 but need not be copied from it. Show the new location in the
7066 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7067 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7069 XEXP (note, 0) = rl->reg_rtx;
7072 /* Likewise for a SUBREG of an operand that dies. */
7073 else if (GET_CODE (old) == SUBREG
7074 && REG_P (SUBREG_REG (old))
7075 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7078 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
7082 else if (GET_CODE (old) == SCRATCH)
7083 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7084 but we don't want to make an output reload. */
7087 /* If is a JUMP_INSN, we can't support output reloads yet. */
7088 gcc_assert (NONJUMP_INSN_P (insn));
7090 emit_output_reload_insns (chain, rld + j, j);
7093 /* Reload number R reloads from or to a group of hard registers starting at
7094 register REGNO. Return true if it can be treated for inheritance purposes
7095 like a group of reloads, each one reloading a single hard register.
7096 The caller has already checked that the spill register and REGNO use
7097 the same number of registers to store the reload value. */
7100 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
7102 #ifdef CANNOT_CHANGE_MODE_CLASS
7103 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
7104 GET_MODE (rld[r].reg_rtx),
7105 reg_raw_mode[reload_spill_index[r]])
7106 && !REG_CANNOT_CHANGE_MODE_P (regno,
7107 GET_MODE (rld[r].reg_rtx),
7108 reg_raw_mode[regno]));
7114 /* Output insns to reload values in and out of the chosen reload regs. */
7117 emit_reload_insns (struct insn_chain *chain)
7119 rtx insn = chain->insn;
7123 CLEAR_HARD_REG_SET (reg_reloaded_died);
7125 for (j = 0; j < reload_n_operands; j++)
7126 input_reload_insns[j] = input_address_reload_insns[j]
7127 = inpaddr_address_reload_insns[j]
7128 = output_reload_insns[j] = output_address_reload_insns[j]
7129 = outaddr_address_reload_insns[j]
7130 = other_output_reload_insns[j] = 0;
7131 other_input_address_reload_insns = 0;
7132 other_input_reload_insns = 0;
7133 operand_reload_insns = 0;
7134 other_operand_reload_insns = 0;
7136 /* Dump reloads into the dump file. */
7139 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7140 debug_reload_to_stream (dump_file);
7143 /* Now output the instructions to copy the data into and out of the
7144 reload registers. Do these in the order that the reloads were reported,
7145 since reloads of base and index registers precede reloads of operands
7146 and the operands may need the base and index registers reloaded. */
7148 for (j = 0; j < n_reloads; j++)
7151 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7152 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7154 do_input_reload (chain, rld + j, j);
7155 do_output_reload (chain, rld + j, j);
7158 /* Now write all the insns we made for reloads in the order expected by
7159 the allocation functions. Prior to the insn being reloaded, we write
7160 the following reloads:
7162 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7164 RELOAD_OTHER reloads.
7166 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7167 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7168 RELOAD_FOR_INPUT reload for the operand.
7170 RELOAD_FOR_OPADDR_ADDRS reloads.
7172 RELOAD_FOR_OPERAND_ADDRESS reloads.
7174 After the insn being reloaded, we write the following:
7176 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7177 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7178 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7179 reloads for the operand. The RELOAD_OTHER output reloads are
7180 output in descending order by reload number. */
7182 emit_insn_before (other_input_address_reload_insns, insn);
7183 emit_insn_before (other_input_reload_insns, insn);
7185 for (j = 0; j < reload_n_operands; j++)
7187 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7188 emit_insn_before (input_address_reload_insns[j], insn);
7189 emit_insn_before (input_reload_insns[j], insn);
7192 emit_insn_before (other_operand_reload_insns, insn);
7193 emit_insn_before (operand_reload_insns, insn);
7195 for (j = 0; j < reload_n_operands; j++)
7197 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7198 x = emit_insn_after (output_address_reload_insns[j], x);
7199 x = emit_insn_after (output_reload_insns[j], x);
7200 emit_insn_after (other_output_reload_insns[j], x);
7203 /* For all the spill regs newly reloaded in this instruction,
7204 record what they were reloaded from, so subsequent instructions
7205 can inherit the reloads.
7207 Update spill_reg_store for the reloads of this insn.
7208 Copy the elements that were updated in the loop above. */
7210 for (j = 0; j < n_reloads; j++)
7212 int r = reload_order[j];
7213 int i = reload_spill_index[r];
7215 /* If this is a non-inherited input reload from a pseudo, we must
7216 clear any memory of a previous store to the same pseudo. Only do
7217 something if there will not be an output reload for the pseudo
7219 if (rld[r].in_reg != 0
7220 && ! (reload_inherited[r] || reload_override_in[r]))
7222 rtx reg = rld[r].in_reg;
7224 if (GET_CODE (reg) == SUBREG)
7225 reg = SUBREG_REG (reg);
7228 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7229 && ! reg_has_output_reload[REGNO (reg)])
7231 int nregno = REGNO (reg);
7233 if (reg_last_reload_reg[nregno])
7235 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7237 if (reg_reloaded_contents[last_regno] == nregno)
7238 spill_reg_store[last_regno] = 0;
7243 /* I is nonneg if this reload used a register.
7244 If rld[r].reg_rtx is 0, this is an optional reload
7245 that we opted to ignore. */
7247 if (i >= 0 && rld[r].reg_rtx != 0)
7249 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7251 int part_reaches_end = 0;
7252 int all_reaches_end = 1;
7254 /* For a multi register reload, we need to check if all or part
7255 of the value lives to the end. */
7256 for (k = 0; k < nr; k++)
7258 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7259 rld[r].when_needed))
7260 part_reaches_end = 1;
7262 all_reaches_end = 0;
7265 /* Ignore reloads that don't reach the end of the insn in
7267 if (all_reaches_end)
7269 /* First, clear out memory of what used to be in this spill reg.
7270 If consecutive registers are used, clear them all. */
7272 for (k = 0; k < nr; k++)
7274 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7275 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7278 /* Maybe the spill reg contains a copy of reload_out. */
7280 && (REG_P (rld[r].out)
7284 || REG_P (rld[r].out_reg)))
7286 rtx out = (REG_P (rld[r].out)
7290 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7291 int nregno = REGNO (out);
7292 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7293 : hard_regno_nregs[nregno]
7294 [GET_MODE (rld[r].reg_rtx)]);
7297 spill_reg_store[i] = new_spill_reg_store[i];
7298 spill_reg_stored_to[i] = out;
7299 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7301 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7303 && inherit_piecemeal_p (r, nregno));
7305 /* If NREGNO is a hard register, it may occupy more than
7306 one register. If it does, say what is in the
7307 rest of the registers assuming that both registers
7308 agree on how many words the object takes. If not,
7309 invalidate the subsequent registers. */
7311 if (nregno < FIRST_PSEUDO_REGISTER)
7312 for (k = 1; k < nnr; k++)
7313 reg_last_reload_reg[nregno + k]
7315 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7318 /* Now do the inverse operation. */
7319 for (k = 0; k < nr; k++)
7321 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7322 reg_reloaded_contents[i + k]
7323 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7326 reg_reloaded_insn[i + k] = insn;
7327 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7328 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7329 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7333 /* Maybe the spill reg contains a copy of reload_in. Only do
7334 something if there will not be an output reload for
7335 the register being reloaded. */
7336 else if (rld[r].out_reg == 0
7338 && ((REG_P (rld[r].in)
7339 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7340 && ! reg_has_output_reload[REGNO (rld[r].in)])
7341 || (REG_P (rld[r].in_reg)
7342 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7343 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7350 if (REG_P (rld[r].in)
7351 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7353 else if (REG_P (rld[r].in_reg))
7356 in = XEXP (rld[r].in_reg, 0);
7357 nregno = REGNO (in);
7359 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7360 : hard_regno_nregs[nregno]
7361 [GET_MODE (rld[r].reg_rtx)]);
7363 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7365 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7367 && inherit_piecemeal_p (r, nregno));
7369 if (nregno < FIRST_PSEUDO_REGISTER)
7370 for (k = 1; k < nnr; k++)
7371 reg_last_reload_reg[nregno + k]
7373 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7376 /* Unless we inherited this reload, show we haven't
7377 recently done a store.
7378 Previous stores of inherited auto_inc expressions
7379 also have to be discarded. */
7380 if (! reload_inherited[r]
7381 || (rld[r].out && ! rld[r].out_reg))
7382 spill_reg_store[i] = 0;
7384 for (k = 0; k < nr; k++)
7386 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7387 reg_reloaded_contents[i + k]
7388 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7391 reg_reloaded_insn[i + k] = insn;
7392 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7393 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7394 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7399 /* However, if part of the reload reaches the end, then we must
7400 invalidate the old info for the part that survives to the end. */
7401 else if (part_reaches_end)
7403 for (k = 0; k < nr; k++)
7404 if (reload_reg_reaches_end_p (i + k,
7406 rld[r].when_needed))
7407 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7411 /* The following if-statement was #if 0'd in 1.34 (or before...).
7412 It's reenabled in 1.35 because supposedly nothing else
7413 deals with this problem. */
7415 /* If a register gets output-reloaded from a non-spill register,
7416 that invalidates any previous reloaded copy of it.
7417 But forget_old_reloads_1 won't get to see it, because
7418 it thinks only about the original insn. So invalidate it here.
7419 Also do the same thing for RELOAD_OTHER constraints where the
7420 output is discarded. */
7422 && ((rld[r].out != 0
7423 && (REG_P (rld[r].out)
7424 || (MEM_P (rld[r].out)
7425 && REG_P (rld[r].out_reg))))
7426 || (rld[r].out == 0 && rld[r].out_reg
7427 && REG_P (rld[r].out_reg))))
7429 rtx out = ((rld[r].out && REG_P (rld[r].out))
7430 ? rld[r].out : rld[r].out_reg);
7431 int nregno = REGNO (out);
7432 if (nregno >= FIRST_PSEUDO_REGISTER)
7434 rtx src_reg, store_insn = NULL_RTX;
7436 reg_last_reload_reg[nregno] = 0;
7438 /* If we can find a hard register that is stored, record
7439 the storing insn so that we may delete this insn with
7440 delete_output_reload. */
7441 src_reg = rld[r].reg_rtx;
7443 /* If this is an optional reload, try to find the source reg
7444 from an input reload. */
7447 rtx set = single_set (insn);
7448 if (set && SET_DEST (set) == rld[r].out)
7452 src_reg = SET_SRC (set);
7454 for (k = 0; k < n_reloads; k++)
7456 if (rld[k].in == src_reg)
7458 src_reg = rld[k].reg_rtx;
7465 store_insn = new_spill_reg_store[REGNO (src_reg)];
7466 if (src_reg && REG_P (src_reg)
7467 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7469 int src_regno = REGNO (src_reg);
7470 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7471 /* The place where to find a death note varies with
7472 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7473 necessarily checked exactly in the code that moves
7474 notes, so just check both locations. */
7475 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7476 if (! note && store_insn)
7477 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7480 spill_reg_store[src_regno + nr] = store_insn;
7481 spill_reg_stored_to[src_regno + nr] = out;
7482 reg_reloaded_contents[src_regno + nr] = nregno;
7483 reg_reloaded_insn[src_regno + nr] = store_insn;
7484 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7485 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7486 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7487 GET_MODE (src_reg)))
7488 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7490 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7492 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7494 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7496 reg_last_reload_reg[nregno] = src_reg;
7497 /* We have to set reg_has_output_reload here, or else
7498 forget_old_reloads_1 will clear reg_last_reload_reg
7500 reg_has_output_reload[nregno] = 1;
7505 int num_regs = hard_regno_nregs[nregno][GET_MODE (out)];
7507 while (num_regs-- > 0)
7508 reg_last_reload_reg[nregno + num_regs] = 0;
7512 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7515 /* Go through the motions to emit INSN and test if it is strictly valid.
7516 Return the emitted insn if valid, else return NULL. */
7519 emit_insn_if_valid_for_reload (rtx insn)
7521 rtx last = get_last_insn ();
7524 insn = emit_insn (insn);
7525 code = recog_memoized (insn);
7529 extract_insn (insn);
7530 /* We want constrain operands to treat this insn strictly in its
7531 validity determination, i.e., the way it would after reload has
7533 if (constrain_operands (1))
7537 delete_insns_since (last);
7541 /* Emit code to perform a reload from IN (which may be a reload register) to
7542 OUT (which may also be a reload register). IN or OUT is from operand
7543 OPNUM with reload type TYPE.
7545 Returns first insn emitted. */
7548 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7550 rtx last = get_last_insn ();
7553 /* If IN is a paradoxical SUBREG, remove it and try to put the
7554 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7555 if (GET_CODE (in) == SUBREG
7556 && (GET_MODE_SIZE (GET_MODE (in))
7557 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7558 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7559 in = SUBREG_REG (in), out = tem;
7560 else if (GET_CODE (out) == SUBREG
7561 && (GET_MODE_SIZE (GET_MODE (out))
7562 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7563 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7564 out = SUBREG_REG (out), in = tem;
7566 /* How to do this reload can get quite tricky. Normally, we are being
7567 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7568 register that didn't get a hard register. In that case we can just
7569 call emit_move_insn.
7571 We can also be asked to reload a PLUS that adds a register or a MEM to
7572 another register, constant or MEM. This can occur during frame pointer
7573 elimination and while reloading addresses. This case is handled by
7574 trying to emit a single insn to perform the add. If it is not valid,
7575 we use a two insn sequence.
7577 Or we can be asked to reload an unary operand that was a fragment of
7578 an addressing mode, into a register. If it isn't recognized as-is,
7579 we try making the unop operand and the reload-register the same:
7580 (set reg:X (unop:X expr:Y))
7581 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
7583 Finally, we could be called to handle an 'o' constraint by putting
7584 an address into a register. In that case, we first try to do this
7585 with a named pattern of "reload_load_address". If no such pattern
7586 exists, we just emit a SET insn and hope for the best (it will normally
7587 be valid on machines that use 'o').
7589 This entire process is made complex because reload will never
7590 process the insns we generate here and so we must ensure that
7591 they will fit their constraints and also by the fact that parts of
7592 IN might be being reloaded separately and replaced with spill registers.
7593 Because of this, we are, in some sense, just guessing the right approach
7594 here. The one listed above seems to work.
7596 ??? At some point, this whole thing needs to be rethought. */
7598 if (GET_CODE (in) == PLUS
7599 && (REG_P (XEXP (in, 0))
7600 || GET_CODE (XEXP (in, 0)) == SUBREG
7601 || MEM_P (XEXP (in, 0)))
7602 && (REG_P (XEXP (in, 1))
7603 || GET_CODE (XEXP (in, 1)) == SUBREG
7604 || CONSTANT_P (XEXP (in, 1))
7605 || MEM_P (XEXP (in, 1))))
7607 /* We need to compute the sum of a register or a MEM and another
7608 register, constant, or MEM, and put it into the reload
7609 register. The best possible way of doing this is if the machine
7610 has a three-operand ADD insn that accepts the required operands.
7612 The simplest approach is to try to generate such an insn and see if it
7613 is recognized and matches its constraints. If so, it can be used.
7615 It might be better not to actually emit the insn unless it is valid,
7616 but we need to pass the insn as an operand to `recog' and
7617 `extract_insn' and it is simpler to emit and then delete the insn if
7618 not valid than to dummy things up. */
7620 rtx op0, op1, tem, insn;
7623 op0 = find_replacement (&XEXP (in, 0));
7624 op1 = find_replacement (&XEXP (in, 1));
7626 /* Since constraint checking is strict, commutativity won't be
7627 checked, so we need to do that here to avoid spurious failure
7628 if the add instruction is two-address and the second operand
7629 of the add is the same as the reload reg, which is frequently
7630 the case. If the insn would be A = B + A, rearrange it so
7631 it will be A = A + B as constrain_operands expects. */
7633 if (REG_P (XEXP (in, 1))
7634 && REGNO (out) == REGNO (XEXP (in, 1)))
7635 tem = op0, op0 = op1, op1 = tem;
7637 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7638 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7640 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7644 /* If that failed, we must use a conservative two-insn sequence.
7646 Use a move to copy one operand into the reload register. Prefer
7647 to reload a constant, MEM or pseudo since the move patterns can
7648 handle an arbitrary operand. If OP1 is not a constant, MEM or
7649 pseudo and OP1 is not a valid operand for an add instruction, then
7652 After reloading one of the operands into the reload register, add
7653 the reload register to the output register.
7655 If there is another way to do this for a specific machine, a
7656 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7659 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7661 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7663 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7664 || (code != CODE_FOR_nothing
7665 && ! ((*insn_data[code].operand[2].predicate)
7666 (op1, insn_data[code].operand[2].mode))))
7667 tem = op0, op0 = op1, op1 = tem;
7669 gen_reload (out, op0, opnum, type);
7671 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7672 This fixes a problem on the 32K where the stack pointer cannot
7673 be used as an operand of an add insn. */
7675 if (rtx_equal_p (op0, op1))
7678 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
7681 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7683 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7687 /* If that failed, copy the address register to the reload register.
7688 Then add the constant to the reload register. */
7690 gen_reload (out, op1, opnum, type);
7691 insn = emit_insn (gen_add2_insn (out, op0));
7692 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7695 #ifdef SECONDARY_MEMORY_NEEDED
7696 /* If we need a memory location to do the move, do it that way. */
7697 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7698 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7699 && (REG_P (out) || GET_CODE (out) == SUBREG)
7700 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7701 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7702 REGNO_REG_CLASS (reg_or_subregno (out)),
7705 /* Get the memory to use and rewrite both registers to its mode. */
7706 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7708 if (GET_MODE (loc) != GET_MODE (out))
7709 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7711 if (GET_MODE (loc) != GET_MODE (in))
7712 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7714 gen_reload (loc, in, opnum, type);
7715 gen_reload (out, loc, opnum, type);
7718 else if (REG_P (out) && UNARY_P (in))
7725 op1 = find_replacement (&XEXP (in, 0));
7726 if (op1 != XEXP (in, 0))
7727 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
7729 /* First, try a plain SET. */
7730 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7734 /* If that failed, move the inner operand to the reload
7735 register, and try the same unop with the inner expression
7736 replaced with the reload register. */
7738 if (GET_MODE (op1) != GET_MODE (out))
7739 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
7743 gen_reload (out_moded, op1, opnum, type);
7746 = gen_rtx_SET (VOIDmode, out,
7747 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
7749 insn = emit_insn_if_valid_for_reload (insn);
7753 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7757 fatal_insn ("Failure trying to reload:", set);
7759 /* If IN is a simple operand, use gen_move_insn. */
7760 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
7761 emit_insn (gen_move_insn (out, in));
7763 #ifdef HAVE_reload_load_address
7764 else if (HAVE_reload_load_address)
7765 emit_insn (gen_reload_load_address (out, in));
7768 /* Otherwise, just write (set OUT IN) and hope for the best. */
7770 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7772 /* Return the first insn emitted.
7773 We can not just return get_last_insn, because there may have
7774 been multiple instructions emitted. Also note that gen_move_insn may
7775 emit more than one insn itself, so we can not assume that there is one
7776 insn emitted per emit_insn_before call. */
7778 return last ? NEXT_INSN (last) : get_insns ();
7781 /* Delete a previously made output-reload whose result we now believe
7782 is not needed. First we double-check.
7784 INSN is the insn now being processed.
7785 LAST_RELOAD_REG is the hard register number for which we want to delete
7786 the last output reload.
7787 J is the reload-number that originally used REG. The caller has made
7788 certain that reload J doesn't use REG any longer for input. */
7791 delete_output_reload (rtx insn, int j, int last_reload_reg)
7793 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7794 rtx reg = spill_reg_stored_to[last_reload_reg];
7797 int n_inherited = 0;
7801 /* It is possible that this reload has been only used to set another reload
7802 we eliminated earlier and thus deleted this instruction too. */
7803 if (INSN_DELETED_P (output_reload_insn))
7806 /* Get the raw pseudo-register referred to. */
7808 while (GET_CODE (reg) == SUBREG)
7809 reg = SUBREG_REG (reg);
7810 substed = reg_equiv_memory_loc[REGNO (reg)];
7812 /* This is unsafe if the operand occurs more often in the current
7813 insn than it is inherited. */
7814 for (k = n_reloads - 1; k >= 0; k--)
7816 rtx reg2 = rld[k].in;
7819 if (MEM_P (reg2) || reload_override_in[k])
7820 reg2 = rld[k].in_reg;
7822 if (rld[k].out && ! rld[k].out_reg)
7823 reg2 = XEXP (rld[k].in_reg, 0);
7825 while (GET_CODE (reg2) == SUBREG)
7826 reg2 = SUBREG_REG (reg2);
7827 if (rtx_equal_p (reg2, reg))
7829 if (reload_inherited[k] || reload_override_in[k] || k == j)
7832 reg2 = rld[k].out_reg;
7835 while (GET_CODE (reg2) == SUBREG)
7836 reg2 = XEXP (reg2, 0);
7837 if (rtx_equal_p (reg2, reg))
7844 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7846 n_occurrences += count_occurrences (PATTERN (insn),
7847 eliminate_regs (substed, 0,
7849 if (n_occurrences > n_inherited)
7852 /* If the pseudo-reg we are reloading is no longer referenced
7853 anywhere between the store into it and here,
7854 and we're within the same basic block, then the value can only
7855 pass through the reload reg and end up here.
7856 Otherwise, give up--return. */
7857 for (i1 = NEXT_INSN (output_reload_insn);
7858 i1 != insn; i1 = NEXT_INSN (i1))
7860 if (NOTE_INSN_BASIC_BLOCK_P (i1))
7862 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
7863 && reg_mentioned_p (reg, PATTERN (i1)))
7865 /* If this is USE in front of INSN, we only have to check that
7866 there are no more references than accounted for by inheritance. */
7867 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
7869 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7870 i1 = NEXT_INSN (i1);
7872 if (n_occurrences <= n_inherited && i1 == insn)
7878 /* We will be deleting the insn. Remove the spill reg information. */
7879 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
7881 spill_reg_store[last_reload_reg + k] = 0;
7882 spill_reg_stored_to[last_reload_reg + k] = 0;
7885 /* The caller has already checked that REG dies or is set in INSN.
7886 It has also checked that we are optimizing, and thus some
7887 inaccuracies in the debugging information are acceptable.
7888 So we could just delete output_reload_insn. But in some cases
7889 we can improve the debugging information without sacrificing
7890 optimization - maybe even improving the code: See if the pseudo
7891 reg has been completely replaced with reload regs. If so, delete
7892 the store insn and forget we had a stack slot for the pseudo. */
7893 if (rld[j].out != rld[j].in
7894 && REG_N_DEATHS (REGNO (reg)) == 1
7895 && REG_N_SETS (REGNO (reg)) == 1
7896 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7897 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7901 /* We know that it was used only between here and the beginning of
7902 the current basic block. (We also know that the last use before
7903 INSN was the output reload we are thinking of deleting, but never
7904 mind that.) Search that range; see if any ref remains. */
7905 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7907 rtx set = single_set (i2);
7909 /* Uses which just store in the pseudo don't count,
7910 since if they are the only uses, they are dead. */
7911 if (set != 0 && SET_DEST (set) == reg)
7916 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
7917 && reg_mentioned_p (reg, PATTERN (i2)))
7919 /* Some other ref remains; just delete the output reload we
7921 delete_address_reloads (output_reload_insn, insn);
7922 delete_insn (output_reload_insn);
7927 /* Delete the now-dead stores into this pseudo. Note that this
7928 loop also takes care of deleting output_reload_insn. */
7929 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7931 rtx set = single_set (i2);
7933 if (set != 0 && SET_DEST (set) == reg)
7935 delete_address_reloads (i2, insn);
7943 /* For the debugging info, say the pseudo lives in this reload reg. */
7944 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7945 alter_reg (REGNO (reg), -1);
7949 delete_address_reloads (output_reload_insn, insn);
7950 delete_insn (output_reload_insn);
7954 /* We are going to delete DEAD_INSN. Recursively delete loads of
7955 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7956 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7958 delete_address_reloads (rtx dead_insn, rtx current_insn)
7960 rtx set = single_set (dead_insn);
7961 rtx set2, dst, prev, next;
7964 rtx dst = SET_DEST (set);
7966 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7968 /* If we deleted the store from a reloaded post_{in,de}c expression,
7969 we can delete the matching adds. */
7970 prev = PREV_INSN (dead_insn);
7971 next = NEXT_INSN (dead_insn);
7972 if (! prev || ! next)
7974 set = single_set (next);
7975 set2 = single_set (prev);
7977 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7978 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7979 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7981 dst = SET_DEST (set);
7982 if (! rtx_equal_p (dst, SET_DEST (set2))
7983 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7984 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7985 || (INTVAL (XEXP (SET_SRC (set), 1))
7986 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7988 delete_related_insns (prev);
7989 delete_related_insns (next);
7992 /* Subfunction of delete_address_reloads: process registers found in X. */
7994 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
7996 rtx prev, set, dst, i2;
7998 enum rtx_code code = GET_CODE (x);
8002 const char *fmt = GET_RTX_FORMAT (code);
8003 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8006 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8007 else if (fmt[i] == 'E')
8009 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8010 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8017 if (spill_reg_order[REGNO (x)] < 0)
8020 /* Scan backwards for the insn that sets x. This might be a way back due
8022 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8024 code = GET_CODE (prev);
8025 if (code == CODE_LABEL || code == JUMP_INSN)
8029 if (reg_set_p (x, PATTERN (prev)))
8031 if (reg_referenced_p (x, PATTERN (prev)))
8034 if (! prev || INSN_UID (prev) < reload_first_uid)
8036 /* Check that PREV only sets the reload register. */
8037 set = single_set (prev);
8040 dst = SET_DEST (set);
8042 || ! rtx_equal_p (dst, x))
8044 if (! reg_set_p (dst, PATTERN (dead_insn)))
8046 /* Check if DST was used in a later insn -
8047 it might have been inherited. */
8048 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8054 if (reg_referenced_p (dst, PATTERN (i2)))
8056 /* If there is a reference to the register in the current insn,
8057 it might be loaded in a non-inherited reload. If no other
8058 reload uses it, that means the register is set before
8060 if (i2 == current_insn)
8062 for (j = n_reloads - 1; j >= 0; j--)
8063 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8064 || reload_override_in[j] == dst)
8066 for (j = n_reloads - 1; j >= 0; j--)
8067 if (rld[j].in && rld[j].reg_rtx == dst)
8076 /* If DST is still live at CURRENT_INSN, check if it is used for
8077 any reload. Note that even if CURRENT_INSN sets DST, we still
8078 have to check the reloads. */
8079 if (i2 == current_insn)
8081 for (j = n_reloads - 1; j >= 0; j--)
8082 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8083 || reload_override_in[j] == dst)
8085 /* ??? We can't finish the loop here, because dst might be
8086 allocated to a pseudo in this block if no reload in this
8087 block needs any of the classes containing DST - see
8088 spill_hard_reg. There is no easy way to tell this, so we
8089 have to scan till the end of the basic block. */
8091 if (reg_set_p (dst, PATTERN (i2)))
8095 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8096 reg_reloaded_contents[REGNO (dst)] = -1;
8100 /* Output reload-insns to reload VALUE into RELOADREG.
8101 VALUE is an autoincrement or autodecrement RTX whose operand
8102 is a register or memory location;
8103 so reloading involves incrementing that location.
8104 IN is either identical to VALUE, or some cheaper place to reload from.
8106 INC_AMOUNT is the number to increment or decrement by (always positive).
8107 This cannot be deduced from VALUE.
8109 Return the instruction that stores into RELOADREG. */
8112 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8114 /* REG or MEM to be copied and incremented. */
8115 rtx incloc = XEXP (value, 0);
8116 /* Nonzero if increment after copying. */
8117 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
8123 rtx real_in = in == value ? XEXP (in, 0) : in;
8125 /* No hard register is equivalent to this register after
8126 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8127 we could inc/dec that register as well (maybe even using it for
8128 the source), but I'm not sure it's worth worrying about. */
8130 reg_last_reload_reg[REGNO (incloc)] = 0;
8132 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8133 inc_amount = -inc_amount;
8135 inc = GEN_INT (inc_amount);
8137 /* If this is post-increment, first copy the location to the reload reg. */
8138 if (post && real_in != reloadreg)
8139 emit_insn (gen_move_insn (reloadreg, real_in));
8143 /* See if we can directly increment INCLOC. Use a method similar to
8144 that in gen_reload. */
8146 last = get_last_insn ();
8147 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8148 gen_rtx_PLUS (GET_MODE (incloc),
8151 code = recog_memoized (add_insn);
8154 extract_insn (add_insn);
8155 if (constrain_operands (1))
8157 /* If this is a pre-increment and we have incremented the value
8158 where it lives, copy the incremented value to RELOADREG to
8159 be used as an address. */
8162 emit_insn (gen_move_insn (reloadreg, incloc));
8167 delete_insns_since (last);
8170 /* If couldn't do the increment directly, must increment in RELOADREG.
8171 The way we do this depends on whether this is pre- or post-increment.
8172 For pre-increment, copy INCLOC to the reload register, increment it
8173 there, then save back. */
8177 if (in != reloadreg)
8178 emit_insn (gen_move_insn (reloadreg, real_in));
8179 emit_insn (gen_add2_insn (reloadreg, inc));
8180 store = emit_insn (gen_move_insn (incloc, reloadreg));
8185 Because this might be a jump insn or a compare, and because RELOADREG
8186 may not be available after the insn in an input reload, we must do
8187 the incrementation before the insn being reloaded for.
8189 We have already copied IN to RELOADREG. Increment the copy in
8190 RELOADREG, save that back, then decrement RELOADREG so it has
8191 the original value. */
8193 emit_insn (gen_add2_insn (reloadreg, inc));
8194 store = emit_insn (gen_move_insn (incloc, reloadreg));
8195 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8203 add_auto_inc_notes (rtx insn, rtx x)
8205 enum rtx_code code = GET_CODE (x);
8209 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8212 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8216 /* Scan all the operand sub-expressions. */
8217 fmt = GET_RTX_FORMAT (code);
8218 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8221 add_auto_inc_notes (insn, XEXP (x, i));
8222 else if (fmt[i] == 'E')
8223 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8224 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8229 /* Copy EH notes from an insn to its reloads. */
8231 copy_eh_notes (rtx insn, rtx x)
8233 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8236 for (; x != 0; x = NEXT_INSN (x))
8238 if (may_trap_p (PATTERN (x)))
8240 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8246 /* This is used by reload pass, that does emit some instructions after
8247 abnormal calls moving basic block end, but in fact it wants to emit
8248 them on the edge. Looks for abnormal call edges, find backward the
8249 proper call and fix the damage.
8251 Similar handle instructions throwing exceptions internally. */
8253 fixup_abnormal_edges (void)
8255 bool inserted = false;
8263 /* Look for cases we are interested in - calls or instructions causing
8265 FOR_EACH_EDGE (e, ei, bb->succs)
8267 if (e->flags & EDGE_ABNORMAL_CALL)
8269 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8270 == (EDGE_ABNORMAL | EDGE_EH))
8273 if (e && !CALL_P (BB_END (bb))
8274 && !can_throw_internal (BB_END (bb)))
8278 /* Get past the new insns generated. Allow notes, as the insns
8279 may be already deleted. */
8281 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8282 && !can_throw_internal (insn)
8283 && insn != BB_HEAD (bb))
8284 insn = PREV_INSN (insn);
8286 if (CALL_P (insn) || can_throw_internal (insn))
8290 stop = NEXT_INSN (BB_END (bb));
8292 insn = NEXT_INSN (insn);
8294 FOR_EACH_EDGE (e, ei, bb->succs)
8295 if (e->flags & EDGE_FALLTHRU)
8298 while (insn && insn != stop)
8300 next = NEXT_INSN (insn);
8305 /* Sometimes there's still the return value USE.
8306 If it's placed after a trapping call (i.e. that
8307 call is the last insn anyway), we have no fallthru
8308 edge. Simply delete this use and don't try to insert
8309 on the non-existent edge. */
8310 if (GET_CODE (PATTERN (insn)) != USE)
8312 /* We're not deleting it, we're moving it. */
8313 INSN_DELETED_P (insn) = 0;
8314 PREV_INSN (insn) = NULL_RTX;
8315 NEXT_INSN (insn) = NULL_RTX;
8317 insert_insn_on_edge (insn, e);
8325 /* It may be that we don't find any such trapping insn. In this
8326 case we discovered quite late that the insn that had been
8327 marked as can_throw_internal in fact couldn't trap at all.
8328 So we should in fact delete the EH edges out of the block. */
8330 purge_dead_edges (bb);
8334 /* We've possibly turned single trapping insn into multiple ones. */
8335 if (flag_non_call_exceptions)
8338 blocks = sbitmap_alloc (last_basic_block);
8339 sbitmap_ones (blocks);
8340 find_many_sub_basic_blocks (blocks);
8344 commit_edge_insertions ();
8346 #ifdef ENABLE_CHECKING
8347 /* Verify that we didn't turn one trapping insn into many, and that
8348 we found and corrected all of the problems wrt fixups on the
8350 verify_flow_info ();
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