1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
35 #include "basic-block.h"
44 #if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY
45 #define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY
48 /* This file contains the reload pass of the compiler, which is
49 run after register allocation has been done. It checks that
50 each insn is valid (operands required to be in registers really
51 are in registers of the proper class) and fixes up invalid ones
52 by copying values temporarily into registers for the insns
55 The results of register allocation are described by the vector
56 reg_renumber; the insns still contain pseudo regs, but reg_renumber
57 can be used to find which hard reg, if any, a pseudo reg is in.
59 The technique we always use is to free up a few hard regs that are
60 called ``reload regs'', and for each place where a pseudo reg
61 must be in a hard reg, copy it temporarily into one of the reload regs.
63 Reload regs are allocated locally for every instruction that needs
64 reloads. When there are pseudos which are allocated to a register that
65 has been chosen as a reload reg, such pseudos must be ``spilled''.
66 This means that they go to other hard regs, or to stack slots if no other
67 available hard regs can be found. Spilling can invalidate more
68 insns, requiring additional need for reloads, so we must keep checking
69 until the process stabilizes.
71 For machines with different classes of registers, we must keep track
72 of the register class needed for each reload, and make sure that
73 we allocate enough reload registers of each class.
75 The file reload.c contains the code that checks one insn for
76 validity and reports the reloads that it needs. This file
77 is in charge of scanning the entire rtl code, accumulating the
78 reload needs, spilling, assigning reload registers to use for
79 fixing up each insn, and generating the new insns to copy values
80 into the reload registers. */
82 #ifndef REGISTER_MOVE_COST
83 #define REGISTER_MOVE_COST(m, x, y) 2
87 #define LOCAL_REGNO(REGNO) 0
90 /* During reload_as_needed, element N contains a REG rtx for the hard reg
91 into which reg N has been reloaded (perhaps for a previous insn). */
92 static rtx *reg_last_reload_reg;
94 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
95 for an output reload that stores into reg N. */
96 static char *reg_has_output_reload;
98 /* Indicates which hard regs are reload-registers for an output reload
99 in the current insn. */
100 static HARD_REG_SET reg_is_output_reload;
102 /* Element N is the constant value to which pseudo reg N is equivalent,
103 or zero if pseudo reg N is not equivalent to a constant.
104 find_reloads looks at this in order to replace pseudo reg N
105 with the constant it stands for. */
106 rtx *reg_equiv_constant;
108 /* Element N is a memory location to which pseudo reg N is equivalent,
109 prior to any register elimination (such as frame pointer to stack
110 pointer). Depending on whether or not it is a valid address, this value
111 is transferred to either reg_equiv_address or reg_equiv_mem. */
112 rtx *reg_equiv_memory_loc;
114 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
115 This is used when the address is not valid as a memory address
116 (because its displacement is too big for the machine.) */
117 rtx *reg_equiv_address;
119 /* Element N is the memory slot to which pseudo reg N is equivalent,
120 or zero if pseudo reg N is not equivalent to a memory slot. */
123 /* Widest width in which each pseudo reg is referred to (via subreg). */
124 static unsigned int *reg_max_ref_width;
126 /* Element N is the list of insns that initialized reg N from its equivalent
127 constant or memory slot. */
128 static rtx *reg_equiv_init;
130 /* Vector to remember old contents of reg_renumber before spilling. */
131 static short *reg_old_renumber;
133 /* During reload_as_needed, element N contains the last pseudo regno reloaded
134 into hard register N. If that pseudo reg occupied more than one register,
135 reg_reloaded_contents points to that pseudo for each spill register in
136 use; all of these must remain set for an inheritance to occur. */
137 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
139 /* During reload_as_needed, element N contains the insn for which
140 hard register N was last used. Its contents are significant only
141 when reg_reloaded_valid is set for this register. */
142 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
144 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
145 static HARD_REG_SET reg_reloaded_valid;
146 /* Indicate if the register was dead at the end of the reload.
147 This is only valid if reg_reloaded_contents is set and valid. */
148 static HARD_REG_SET reg_reloaded_dead;
150 /* Number of spill-regs so far; number of valid elements of spill_regs. */
153 /* In parallel with spill_regs, contains REG rtx's for those regs.
154 Holds the last rtx used for any given reg, or 0 if it has never
155 been used for spilling yet. This rtx is reused, provided it has
157 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
159 /* In parallel with spill_regs, contains nonzero for a spill reg
160 that was stored after the last time it was used.
161 The precise value is the insn generated to do the store. */
162 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
164 /* This is the register that was stored with spill_reg_store. This is a
165 copy of reload_out / reload_out_reg when the value was stored; if
166 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
167 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
169 /* This table is the inverse mapping of spill_regs:
170 indexed by hard reg number,
171 it contains the position of that reg in spill_regs,
172 or -1 for something that is not in spill_regs.
174 ?!? This is no longer accurate. */
175 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
177 /* This reg set indicates registers that can't be used as spill registers for
178 the currently processed insn. These are the hard registers which are live
179 during the insn, but not allocated to pseudos, as well as fixed
181 static HARD_REG_SET bad_spill_regs;
183 /* These are the hard registers that can't be used as spill register for any
184 insn. This includes registers used for user variables and registers that
185 we can't eliminate. A register that appears in this set also can't be used
186 to retry register allocation. */
187 static HARD_REG_SET bad_spill_regs_global;
189 /* Describes order of use of registers for reloading
190 of spilled pseudo-registers. `n_spills' is the number of
191 elements that are actually valid; new ones are added at the end.
193 Both spill_regs and spill_reg_order are used on two occasions:
194 once during find_reload_regs, where they keep track of the spill registers
195 for a single insn, but also during reload_as_needed where they show all
196 the registers ever used by reload. For the latter case, the information
197 is calculated during finish_spills. */
198 static short spill_regs[FIRST_PSEUDO_REGISTER];
200 /* This vector of reg sets indicates, for each pseudo, which hard registers
201 may not be used for retrying global allocation because the register was
202 formerly spilled from one of them. If we allowed reallocating a pseudo to
203 a register that it was already allocated to, reload might not
205 static HARD_REG_SET *pseudo_previous_regs;
207 /* This vector of reg sets indicates, for each pseudo, which hard
208 registers may not be used for retrying global allocation because they
209 are used as spill registers during one of the insns in which the
211 static HARD_REG_SET *pseudo_forbidden_regs;
213 /* All hard regs that have been used as spill registers for any insn are
214 marked in this set. */
215 static HARD_REG_SET used_spill_regs;
217 /* Index of last register assigned as a spill register. We allocate in
218 a round-robin fashion. */
219 static int last_spill_reg;
221 /* Nonzero if indirect addressing is supported on the machine; this means
222 that spilling (REG n) does not require reloading it into a register in
223 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
224 value indicates the level of indirect addressing supported, e.g., two
225 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
227 static char spill_indirect_levels;
229 /* Nonzero if indirect addressing is supported when the innermost MEM is
230 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
231 which these are valid is the same as spill_indirect_levels, above. */
232 char indirect_symref_ok;
234 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
235 char double_reg_address_ok;
237 /* Record the stack slot for each spilled hard register. */
238 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
240 /* Width allocated so far for that stack slot. */
241 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
243 /* Record which pseudos needed to be spilled. */
244 static regset_head spilled_pseudos;
246 /* Used for communication between order_regs_for_reload and count_pseudo.
247 Used to avoid counting one pseudo twice. */
248 static regset_head pseudos_counted;
250 /* First uid used by insns created by reload in this function.
251 Used in find_equiv_reg. */
252 int reload_first_uid;
254 /* Flag set by local-alloc or global-alloc if anything is live in
255 a call-clobbered reg across calls. */
256 int caller_save_needed;
258 /* Set to 1 while reload_as_needed is operating.
259 Required by some machines to handle any generated moves differently. */
260 int reload_in_progress = 0;
262 /* These arrays record the insn_code of insns that may be needed to
263 perform input and output reloads of special objects. They provide a
264 place to pass a scratch register. */
265 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
266 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
268 /* This obstack is used for allocation of rtl during register elimination.
269 The allocated storage can be freed once find_reloads has processed the
271 struct obstack reload_obstack;
273 /* Points to the beginning of the reload_obstack. All insn_chain structures
274 are allocated first. */
275 char *reload_startobj;
277 /* The point after all insn_chain structures. Used to quickly deallocate
278 memory allocated in copy_reloads during calculate_needs_all_insns. */
279 char *reload_firstobj;
281 /* This points before all local rtl generated by register elimination.
282 Used to quickly free all memory after processing one insn. */
283 static char *reload_insn_firstobj;
285 #define obstack_chunk_alloc xmalloc
286 #define obstack_chunk_free free
288 /* List of insn_chain instructions, one for every insn that reload needs to
290 struct insn_chain *reload_insn_chain;
293 extern tree current_function_decl;
295 extern union tree_node *current_function_decl;
298 /* List of all insns needing reloads. */
299 static struct insn_chain *insns_need_reload;
301 /* This structure is used to record information about register eliminations.
302 Each array entry describes one possible way of eliminating a register
303 in favor of another. If there is more than one way of eliminating a
304 particular register, the most preferred should be specified first. */
308 int from; /* Register number to be eliminated. */
309 int to; /* Register number used as replacement. */
310 int initial_offset; /* Initial difference between values. */
311 int can_eliminate; /* Non-zero if this elimination can be done. */
312 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
313 insns made by reload. */
314 int offset; /* Current offset between the two regs. */
315 int previous_offset; /* Offset at end of previous insn. */
316 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
317 rtx from_rtx; /* REG rtx for the register to be eliminated.
318 We cannot simply compare the number since
319 we might then spuriously replace a hard
320 register corresponding to a pseudo
321 assigned to the reg to be eliminated. */
322 rtx to_rtx; /* REG rtx for the replacement. */
325 static struct elim_table *reg_eliminate = 0;
327 /* This is an intermediate structure to initialize the table. It has
328 exactly the members provided by ELIMINABLE_REGS. */
329 static struct elim_table_1
333 } reg_eliminate_1[] =
335 /* If a set of eliminable registers was specified, define the table from it.
336 Otherwise, default to the normal case of the frame pointer being
337 replaced by the stack pointer. */
339 #ifdef ELIMINABLE_REGS
342 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
345 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
347 /* Record the number of pending eliminations that have an offset not equal
348 to their initial offset. If non-zero, we use a new copy of each
349 replacement result in any insns encountered. */
350 int num_not_at_initial_offset;
352 /* Count the number of registers that we may be able to eliminate. */
353 static int num_eliminable;
354 /* And the number of registers that are equivalent to a constant that
355 can be eliminated to frame_pointer / arg_pointer + constant. */
356 static int num_eliminable_invariants;
358 /* For each label, we record the offset of each elimination. If we reach
359 a label by more than one path and an offset differs, we cannot do the
360 elimination. This information is indexed by the number of the label.
361 The first table is an array of flags that records whether we have yet
362 encountered a label and the second table is an array of arrays, one
363 entry in the latter array for each elimination. */
365 static char *offsets_known_at;
366 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
368 /* Number of labels in the current function. */
370 static int num_labels;
372 static void replace_pseudos_in_call_usage PARAMS((rtx *,
375 static void maybe_fix_stack_asms PARAMS ((void));
376 static void copy_reloads PARAMS ((struct insn_chain *));
377 static void calculate_needs_all_insns PARAMS ((int));
378 static int find_reg PARAMS ((struct insn_chain *, int));
379 static void find_reload_regs PARAMS ((struct insn_chain *));
380 static void select_reload_regs PARAMS ((void));
381 static void delete_caller_save_insns PARAMS ((void));
383 static void spill_failure PARAMS ((rtx, enum reg_class));
384 static void count_spilled_pseudo PARAMS ((int, int, int));
385 static void delete_dead_insn PARAMS ((rtx));
386 static void alter_reg PARAMS ((int, int));
387 static void set_label_offsets PARAMS ((rtx, rtx, int));
388 static void check_eliminable_occurrences PARAMS ((rtx));
389 static void elimination_effects PARAMS ((rtx, enum machine_mode));
390 static int eliminate_regs_in_insn PARAMS ((rtx, int));
391 static void update_eliminable_offsets PARAMS ((void));
392 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
393 static void set_initial_elim_offsets PARAMS ((void));
394 static void verify_initial_elim_offsets PARAMS ((void));
395 static void set_initial_label_offsets PARAMS ((void));
396 static void set_offsets_for_label PARAMS ((rtx));
397 static void init_elim_table PARAMS ((void));
398 static void update_eliminables PARAMS ((HARD_REG_SET *));
399 static void spill_hard_reg PARAMS ((unsigned int, int));
400 static int finish_spills PARAMS ((int));
401 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
402 static void scan_paradoxical_subregs PARAMS ((rtx));
403 static void count_pseudo PARAMS ((int));
404 static void order_regs_for_reload PARAMS ((struct insn_chain *));
405 static void reload_as_needed PARAMS ((int));
406 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
407 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
408 static void mark_reload_reg_in_use PARAMS ((unsigned int, int,
411 static void clear_reload_reg_in_use PARAMS ((unsigned int, int,
414 static int reload_reg_free_p PARAMS ((unsigned int, int,
416 static int reload_reg_free_for_value_p PARAMS ((int, int, int,
418 rtx, rtx, int, int));
419 static int free_for_value_p PARAMS ((int, enum machine_mode, int,
420 enum reload_type, rtx, rtx,
422 static int reload_reg_reaches_end_p PARAMS ((unsigned int, int,
424 static int allocate_reload_reg PARAMS ((struct insn_chain *, int,
426 static int conflicts_with_override PARAMS ((rtx));
427 static void failed_reload PARAMS ((rtx, int));
428 static int set_reload_reg PARAMS ((int, int));
429 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
430 static void choose_reload_regs PARAMS ((struct insn_chain *));
431 static void merge_assigned_reloads PARAMS ((rtx));
432 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
433 struct reload *, rtx, int));
434 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
435 struct reload *, int));
436 static void do_input_reload PARAMS ((struct insn_chain *,
437 struct reload *, int));
438 static void do_output_reload PARAMS ((struct insn_chain *,
439 struct reload *, int));
440 static void emit_reload_insns PARAMS ((struct insn_chain *));
441 static void delete_output_reload PARAMS ((rtx, int, int));
442 static void delete_address_reloads PARAMS ((rtx, rtx));
443 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
444 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
445 static int constraint_accepts_reg_p PARAMS ((const char *, rtx));
446 static void reload_cse_regs_1 PARAMS ((rtx));
447 static int reload_cse_noop_set_p PARAMS ((rtx));
448 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
449 static int reload_cse_simplify_operands PARAMS ((rtx));
450 static void reload_combine PARAMS ((void));
451 static void reload_combine_note_use PARAMS ((rtx *, rtx));
452 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
453 static void reload_cse_move2add PARAMS ((rtx));
454 static void move2add_note_store PARAMS ((rtx, rtx, void *));
456 static void add_auto_inc_notes PARAMS ((rtx, rtx));
458 static void copy_eh_notes PARAMS ((rtx, rtx));
459 static HOST_WIDE_INT sext_for_mode PARAMS ((enum machine_mode,
461 static void failed_reload PARAMS ((rtx, int));
462 static int set_reload_reg PARAMS ((int, int));
463 static void reload_cse_delete_noop_set PARAMS ((rtx, rtx));
464 static void reload_cse_simplify PARAMS ((rtx));
465 static void fixup_abnormal_edges PARAMS ((void));
466 extern void dump_needs PARAMS ((struct insn_chain *));
468 /* Initialize the reload pass once per compilation. */
475 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
476 Set spill_indirect_levels to the number of levels such addressing is
477 permitted, zero if it is not permitted at all. */
480 = gen_rtx_MEM (Pmode,
483 LAST_VIRTUAL_REGISTER + 1),
485 spill_indirect_levels = 0;
487 while (memory_address_p (QImode, tem))
489 spill_indirect_levels++;
490 tem = gen_rtx_MEM (Pmode, tem);
493 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
495 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
496 indirect_symref_ok = memory_address_p (QImode, tem);
498 /* See if reg+reg is a valid (and offsettable) address. */
500 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
502 tem = gen_rtx_PLUS (Pmode,
503 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
504 gen_rtx_REG (Pmode, i));
506 /* This way, we make sure that reg+reg is an offsettable address. */
507 tem = plus_constant (tem, 4);
509 if (memory_address_p (QImode, tem))
511 double_reg_address_ok = 1;
516 /* Initialize obstack for our rtl allocation. */
517 gcc_obstack_init (&reload_obstack);
518 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
520 INIT_REG_SET (&spilled_pseudos);
521 INIT_REG_SET (&pseudos_counted);
524 /* List of insn chains that are currently unused. */
525 static struct insn_chain *unused_insn_chains = 0;
527 /* Allocate an empty insn_chain structure. */
531 struct insn_chain *c;
533 if (unused_insn_chains == 0)
535 c = (struct insn_chain *)
536 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
537 INIT_REG_SET (&c->live_throughout);
538 INIT_REG_SET (&c->dead_or_set);
542 c = unused_insn_chains;
543 unused_insn_chains = c->next;
545 c->is_caller_save_insn = 0;
546 c->need_operand_change = 0;
552 /* Small utility function to set all regs in hard reg set TO which are
553 allocated to pseudos in regset FROM. */
556 compute_use_by_pseudos (to, from)
562 EXECUTE_IF_SET_IN_REG_SET
563 (from, FIRST_PSEUDO_REGISTER, regno,
565 int r = reg_renumber[regno];
570 /* reload_combine uses the information from
571 BASIC_BLOCK->global_live_at_start, which might still
572 contain registers that have not actually been allocated
573 since they have an equivalence. */
574 if (! reload_completed)
579 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
581 SET_HARD_REG_BIT (*to, r + nregs);
586 /* Replace all pseudos found in LOC with their corresponding
590 replace_pseudos_in_call_usage (loc, mem_mode, usage)
592 enum machine_mode mem_mode;
606 unsigned int regno = REGNO (x);
608 if (regno < FIRST_PSEUDO_REGISTER)
611 x = eliminate_regs (x, mem_mode, usage);
615 replace_pseudos_in_call_usage (loc, mem_mode, usage);
619 if (reg_equiv_constant[regno])
620 *loc = reg_equiv_constant[regno];
621 else if (reg_equiv_mem[regno])
622 *loc = reg_equiv_mem[regno];
623 else if (reg_equiv_address[regno])
624 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
625 else if (GET_CODE (regno_reg_rtx[regno]) != REG
626 || REGNO (regno_reg_rtx[regno]) != regno)
627 *loc = regno_reg_rtx[regno];
633 else if (code == MEM)
635 replace_pseudos_in_call_usage (& XEXP (x, 0), GET_MODE (x), usage);
639 /* Process each of our operands recursively. */
640 fmt = GET_RTX_FORMAT (code);
641 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
643 replace_pseudos_in_call_usage (&XEXP (x, i), mem_mode, usage);
644 else if (*fmt == 'E')
645 for (j = 0; j < XVECLEN (x, i); j++)
646 replace_pseudos_in_call_usage (& XVECEXP (x, i, j), mem_mode, usage);
650 /* Global variables used by reload and its subroutines. */
652 /* Set during calculate_needs if an insn needs register elimination. */
653 static int something_needs_elimination;
654 /* Set during calculate_needs if an insn needs an operand changed. */
655 int something_needs_operands_changed;
657 /* Nonzero means we couldn't get enough spill regs. */
660 /* Main entry point for the reload pass.
662 FIRST is the first insn of the function being compiled.
664 GLOBAL nonzero means we were called from global_alloc
665 and should attempt to reallocate any pseudoregs that we
666 displace from hard regs we will use for reloads.
667 If GLOBAL is zero, we do not have enough information to do that,
668 so any pseudo reg that is spilled must go to the stack.
670 Return value is nonzero if reload failed
671 and we must not do any more for this function. */
674 reload (first, global)
680 register struct elim_table *ep;
682 /* The two pointers used to track the true location of the memory used
683 for label offsets. */
684 char *real_known_ptr = NULL;
685 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
687 /* Make sure even insns with volatile mem refs are recognizable. */
692 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
694 /* Make sure that the last insn in the chain
695 is not something that needs reloading. */
696 emit_note (NULL, NOTE_INSN_DELETED);
698 /* Enable find_equiv_reg to distinguish insns made by reload. */
699 reload_first_uid = get_max_uid ();
701 #ifdef SECONDARY_MEMORY_NEEDED
702 /* Initialize the secondary memory table. */
703 clear_secondary_mem ();
706 /* We don't have a stack slot for any spill reg yet. */
707 memset ((char *) spill_stack_slot, 0, sizeof spill_stack_slot);
708 memset ((char *) spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
710 /* Initialize the save area information for caller-save, in case some
714 /* Compute which hard registers are now in use
715 as homes for pseudo registers.
716 This is done here rather than (eg) in global_alloc
717 because this point is reached even if not optimizing. */
718 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
721 /* A function that receives a nonlocal goto must save all call-saved
723 if (current_function_has_nonlocal_label)
724 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
725 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
726 regs_ever_live[i] = 1;
728 /* Find all the pseudo registers that didn't get hard regs
729 but do have known equivalent constants or memory slots.
730 These include parameters (known equivalent to parameter slots)
731 and cse'd or loop-moved constant memory addresses.
733 Record constant equivalents in reg_equiv_constant
734 so they will be substituted by find_reloads.
735 Record memory equivalents in reg_mem_equiv so they can
736 be substituted eventually by altering the REG-rtx's. */
738 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
739 reg_equiv_memory_loc = (rtx *) xcalloc (max_regno, sizeof (rtx));
740 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
741 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
742 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
743 reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int));
744 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
745 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
746 pseudo_forbidden_regs
747 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
749 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
751 CLEAR_HARD_REG_SET (bad_spill_regs_global);
753 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
754 Also find all paradoxical subregs and find largest such for each pseudo.
755 On machines with small register classes, record hard registers that
756 are used for user variables. These can never be used for spills.
757 Also look for a "constant" REG_SETJMP. This means that all
758 caller-saved registers must be marked live. */
760 num_eliminable_invariants = 0;
761 for (insn = first; insn; insn = NEXT_INSN (insn))
763 rtx set = single_set (insn);
765 if (GET_CODE (insn) == CALL && find_reg_note (insn, REG_SETJMP, NULL))
766 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
767 if (! call_used_regs[i])
768 regs_ever_live[i] = 1;
770 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
772 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
774 #ifdef LEGITIMATE_PIC_OPERAND_P
775 && (! function_invariant_p (XEXP (note, 0))
777 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
781 rtx x = XEXP (note, 0);
782 i = REGNO (SET_DEST (set));
783 if (i > LAST_VIRTUAL_REGISTER)
785 if (GET_CODE (x) == MEM)
787 /* If the operand is a PLUS, the MEM may be shared,
788 so make sure we have an unshared copy here. */
789 if (GET_CODE (XEXP (x, 0)) == PLUS)
792 reg_equiv_memory_loc[i] = x;
794 else if (function_invariant_p (x))
796 if (GET_CODE (x) == PLUS)
798 /* This is PLUS of frame pointer and a constant,
799 and might be shared. Unshare it. */
800 reg_equiv_constant[i] = copy_rtx (x);
801 num_eliminable_invariants++;
803 else if (x == frame_pointer_rtx
804 || x == arg_pointer_rtx)
806 reg_equiv_constant[i] = x;
807 num_eliminable_invariants++;
809 else if (LEGITIMATE_CONSTANT_P (x))
810 reg_equiv_constant[i] = x;
812 reg_equiv_memory_loc[i]
813 = force_const_mem (GET_MODE (SET_DEST (set)), x);
818 /* If this register is being made equivalent to a MEM
819 and the MEM is not SET_SRC, the equivalencing insn
820 is one with the MEM as a SET_DEST and it occurs later.
821 So don't mark this insn now. */
822 if (GET_CODE (x) != MEM
823 || rtx_equal_p (SET_SRC (set), x))
825 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
830 /* If this insn is setting a MEM from a register equivalent to it,
831 this is the equivalencing insn. */
832 else if (set && GET_CODE (SET_DEST (set)) == MEM
833 && GET_CODE (SET_SRC (set)) == REG
834 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
835 && rtx_equal_p (SET_DEST (set),
836 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
837 reg_equiv_init[REGNO (SET_SRC (set))]
838 = gen_rtx_INSN_LIST (VOIDmode, insn,
839 reg_equiv_init[REGNO (SET_SRC (set))]);
842 scan_paradoxical_subregs (PATTERN (insn));
847 num_labels = max_label_num () - get_first_label_num ();
849 /* Allocate the tables used to store offset information at labels. */
850 /* We used to use alloca here, but the size of what it would try to
851 allocate would occasionally cause it to exceed the stack limit and
852 cause a core dump. */
853 real_known_ptr = xmalloc (num_labels);
855 = (int (*)[NUM_ELIMINABLE_REGS])
856 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
858 offsets_known_at = real_known_ptr - get_first_label_num ();
860 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
862 /* Alter each pseudo-reg rtx to contain its hard reg number.
863 Assign stack slots to the pseudos that lack hard regs or equivalents.
864 Do not touch virtual registers. */
866 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
869 /* If we have some registers we think can be eliminated, scan all insns to
870 see if there is an insn that sets one of these registers to something
871 other than itself plus a constant. If so, the register cannot be
872 eliminated. Doing this scan here eliminates an extra pass through the
873 main reload loop in the most common case where register elimination
875 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
876 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
877 || GET_CODE (insn) == CALL_INSN)
878 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
880 maybe_fix_stack_asms ();
882 insns_need_reload = 0;
883 something_needs_elimination = 0;
885 /* Initialize to -1, which means take the first spill register. */
888 /* Spill any hard regs that we know we can't eliminate. */
889 CLEAR_HARD_REG_SET (used_spill_regs);
890 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
891 if (! ep->can_eliminate)
892 spill_hard_reg (ep->from, 1);
894 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
895 if (frame_pointer_needed)
896 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
898 finish_spills (global);
900 /* From now on, we may need to generate moves differently. We may also
901 allow modifications of insns which cause them to not be recognized.
902 Any such modifications will be cleaned up during reload itself. */
903 reload_in_progress = 1;
905 /* This loop scans the entire function each go-round
906 and repeats until one repetition spills no additional hard regs. */
909 int something_changed;
912 HOST_WIDE_INT starting_frame_size;
914 /* Round size of stack frame to stack_alignment_needed. This must be done
915 here because the stack size may be a part of the offset computation
916 for register elimination, and there might have been new stack slots
917 created in the last iteration of this loop. */
918 if (cfun->stack_alignment_needed)
919 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
921 starting_frame_size = get_frame_size ();
923 set_initial_elim_offsets ();
924 set_initial_label_offsets ();
926 /* For each pseudo register that has an equivalent location defined,
927 try to eliminate any eliminable registers (such as the frame pointer)
928 assuming initial offsets for the replacement register, which
931 If the resulting location is directly addressable, substitute
932 the MEM we just got directly for the old REG.
934 If it is not addressable but is a constant or the sum of a hard reg
935 and constant, it is probably not addressable because the constant is
936 out of range, in that case record the address; we will generate
937 hairy code to compute the address in a register each time it is
938 needed. Similarly if it is a hard register, but one that is not
939 valid as an address register.
941 If the location is not addressable, but does not have one of the
942 above forms, assign a stack slot. We have to do this to avoid the
943 potential of producing lots of reloads if, e.g., a location involves
944 a pseudo that didn't get a hard register and has an equivalent memory
945 location that also involves a pseudo that didn't get a hard register.
947 Perhaps at some point we will improve reload_when_needed handling
948 so this problem goes away. But that's very hairy. */
950 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
951 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
953 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
955 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
957 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
958 else if (CONSTANT_P (XEXP (x, 0))
959 || (GET_CODE (XEXP (x, 0)) == REG
960 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
961 || (GET_CODE (XEXP (x, 0)) == PLUS
962 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
963 && (REGNO (XEXP (XEXP (x, 0), 0))
964 < FIRST_PSEUDO_REGISTER)
965 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
966 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
969 /* Make a new stack slot. Then indicate that something
970 changed so we go back and recompute offsets for
971 eliminable registers because the allocation of memory
972 below might change some offset. reg_equiv_{mem,address}
973 will be set up for this pseudo on the next pass around
975 reg_equiv_memory_loc[i] = 0;
976 reg_equiv_init[i] = 0;
981 if (caller_save_needed)
984 /* If we allocated another stack slot, redo elimination bookkeeping. */
985 if (starting_frame_size != get_frame_size ())
988 if (caller_save_needed)
990 save_call_clobbered_regs ();
991 /* That might have allocated new insn_chain structures. */
992 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
995 calculate_needs_all_insns (global);
997 CLEAR_REG_SET (&spilled_pseudos);
1000 something_changed = 0;
1002 /* If we allocated any new memory locations, make another pass
1003 since it might have changed elimination offsets. */
1004 if (starting_frame_size != get_frame_size ())
1005 something_changed = 1;
1008 HARD_REG_SET to_spill;
1009 CLEAR_HARD_REG_SET (to_spill);
1010 update_eliminables (&to_spill);
1011 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1012 if (TEST_HARD_REG_BIT (to_spill, i))
1014 spill_hard_reg (i, 1);
1017 /* Regardless of the state of spills, if we previously had
1018 a register that we thought we could eliminate, but no can
1019 not eliminate, we must run another pass.
1021 Consider pseudos which have an entry in reg_equiv_* which
1022 reference an eliminable register. We must make another pass
1023 to update reg_equiv_* so that we do not substitute in the
1024 old value from when we thought the elimination could be
1026 something_changed = 1;
1030 select_reload_regs ();
1034 if (insns_need_reload != 0 || did_spill)
1035 something_changed |= finish_spills (global);
1037 if (! something_changed)
1040 if (caller_save_needed)
1041 delete_caller_save_insns ();
1043 obstack_free (&reload_obstack, reload_firstobj);
1046 /* If global-alloc was run, notify it of any register eliminations we have
1049 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1050 if (ep->can_eliminate)
1051 mark_elimination (ep->from, ep->to);
1053 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1054 If that insn didn't set the register (i.e., it copied the register to
1055 memory), just delete that insn instead of the equivalencing insn plus
1056 anything now dead. If we call delete_dead_insn on that insn, we may
1057 delete the insn that actually sets the register if the register dies
1058 there and that is incorrect. */
1060 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1062 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1065 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1067 rtx equiv_insn = XEXP (list, 0);
1068 if (GET_CODE (equiv_insn) == NOTE)
1070 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1071 delete_dead_insn (equiv_insn);
1074 PUT_CODE (equiv_insn, NOTE);
1075 NOTE_SOURCE_FILE (equiv_insn) = 0;
1076 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1082 /* Use the reload registers where necessary
1083 by generating move instructions to move the must-be-register
1084 values into or out of the reload registers. */
1086 if (insns_need_reload != 0 || something_needs_elimination
1087 || something_needs_operands_changed)
1089 HOST_WIDE_INT old_frame_size = get_frame_size ();
1091 reload_as_needed (global);
1093 if (old_frame_size != get_frame_size ())
1097 verify_initial_elim_offsets ();
1100 /* If we were able to eliminate the frame pointer, show that it is no
1101 longer live at the start of any basic block. If it ls live by
1102 virtue of being in a pseudo, that pseudo will be marked live
1103 and hence the frame pointer will be known to be live via that
1106 if (! frame_pointer_needed)
1107 for (i = 0; i < n_basic_blocks; i++)
1108 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
1109 HARD_FRAME_POINTER_REGNUM);
1111 /* Come here (with failure set nonzero) if we can't get enough spill regs
1112 and we decide not to abort about it. */
1115 CLEAR_REG_SET (&spilled_pseudos);
1116 reload_in_progress = 0;
1118 /* Now eliminate all pseudo regs by modifying them into
1119 their equivalent memory references.
1120 The REG-rtx's for the pseudos are modified in place,
1121 so all insns that used to refer to them now refer to memory.
1123 For a reg that has a reg_equiv_address, all those insns
1124 were changed by reloading so that no insns refer to it any longer;
1125 but the DECL_RTL of a variable decl may refer to it,
1126 and if so this causes the debugging info to mention the variable. */
1128 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1133 int is_readonly = 0;
1135 if (reg_equiv_memory_loc[i])
1137 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1138 is_scalar = MEM_SCALAR_P (reg_equiv_memory_loc[i]);
1139 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1142 if (reg_equiv_mem[i])
1143 addr = XEXP (reg_equiv_mem[i], 0);
1145 if (reg_equiv_address[i])
1146 addr = reg_equiv_address[i];
1150 if (reg_renumber[i] < 0)
1152 rtx reg = regno_reg_rtx[i];
1153 PUT_CODE (reg, MEM);
1154 XEXP (reg, 0) = addr;
1155 REG_USERVAR_P (reg) = 0;
1156 RTX_UNCHANGING_P (reg) = is_readonly;
1157 MEM_IN_STRUCT_P (reg) = in_struct;
1158 MEM_SCALAR_P (reg) = is_scalar;
1159 /* We have no alias information about this newly created
1161 set_mem_alias_set (reg, 0);
1163 else if (reg_equiv_mem[i])
1164 XEXP (reg_equiv_mem[i], 0) = addr;
1168 /* We must set reload_completed now since the cleanup_subreg_operands call
1169 below will re-recognize each insn and reload may have generated insns
1170 which are only valid during and after reload. */
1171 reload_completed = 1;
1173 /* Make a pass over all the insns and delete all USEs which we inserted
1174 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1175 notes. Delete all CLOBBER insns that don't refer to the return value
1176 and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1177 REG_LIBCALL notes since they are no longer useful or accurate. Strip
1178 and regenerate REG_INC notes that may have been moved around. */
1180 for (insn = first; insn; insn = NEXT_INSN (insn))
1185 if (GET_CODE (insn) == CALL_INSN)
1186 replace_pseudos_in_call_usage (& CALL_INSN_FUNCTION_USAGE (insn),
1188 CALL_INSN_FUNCTION_USAGE (insn));
1190 if ((GET_CODE (PATTERN (insn)) == USE
1191 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1192 || (GET_CODE (PATTERN (insn)) == CLOBBER
1193 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1194 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1196 PUT_CODE (insn, NOTE);
1197 NOTE_SOURCE_FILE (insn) = 0;
1198 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1202 pnote = ®_NOTES (insn);
1205 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1206 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1207 || REG_NOTE_KIND (*pnote) == REG_INC
1208 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1209 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1210 *pnote = XEXP (*pnote, 1);
1212 pnote = &XEXP (*pnote, 1);
1216 add_auto_inc_notes (insn, PATTERN (insn));
1219 /* And simplify (subreg (reg)) if it appears as an operand. */
1220 cleanup_subreg_operands (insn);
1223 /* If we are doing stack checking, give a warning if this function's
1224 frame size is larger than we expect. */
1225 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1227 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1228 static int verbose_warned = 0;
1230 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1231 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1232 size += UNITS_PER_WORD;
1234 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1236 warning ("frame size too large for reliable stack checking");
1237 if (! verbose_warned)
1239 warning ("try reducing the number of local variables");
1245 /* Indicate that we no longer have known memory locations or constants. */
1246 if (reg_equiv_constant)
1247 free (reg_equiv_constant);
1248 reg_equiv_constant = 0;
1249 if (reg_equiv_memory_loc)
1250 free (reg_equiv_memory_loc);
1251 reg_equiv_memory_loc = 0;
1254 free (real_known_ptr);
1258 free (reg_equiv_mem);
1259 free (reg_equiv_init);
1260 free (reg_equiv_address);
1261 free (reg_max_ref_width);
1262 free (reg_old_renumber);
1263 free (pseudo_previous_regs);
1264 free (pseudo_forbidden_regs);
1266 CLEAR_HARD_REG_SET (used_spill_regs);
1267 for (i = 0; i < n_spills; i++)
1268 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1270 /* Free all the insn_chain structures at once. */
1271 obstack_free (&reload_obstack, reload_startobj);
1272 unused_insn_chains = 0;
1273 fixup_abnormal_edges ();
1278 /* Yet another special case. Unfortunately, reg-stack forces people to
1279 write incorrect clobbers in asm statements. These clobbers must not
1280 cause the register to appear in bad_spill_regs, otherwise we'll call
1281 fatal_insn later. We clear the corresponding regnos in the live
1282 register sets to avoid this.
1283 The whole thing is rather sick, I'm afraid. */
1286 maybe_fix_stack_asms ()
1289 const char *constraints[MAX_RECOG_OPERANDS];
1290 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1291 struct insn_chain *chain;
1293 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1296 HARD_REG_SET clobbered, allowed;
1299 if (! INSN_P (chain->insn)
1300 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1302 pat = PATTERN (chain->insn);
1303 if (GET_CODE (pat) != PARALLEL)
1306 CLEAR_HARD_REG_SET (clobbered);
1307 CLEAR_HARD_REG_SET (allowed);
1309 /* First, make a mask of all stack regs that are clobbered. */
1310 for (i = 0; i < XVECLEN (pat, 0); i++)
1312 rtx t = XVECEXP (pat, 0, i);
1313 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1314 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1317 /* Get the operand values and constraints out of the insn. */
1318 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1319 constraints, operand_mode);
1321 /* For every operand, see what registers are allowed. */
1322 for (i = 0; i < noperands; i++)
1324 const char *p = constraints[i];
1325 /* For every alternative, we compute the class of registers allowed
1326 for reloading in CLS, and merge its contents into the reg set
1328 int cls = (int) NO_REGS;
1334 if (c == '\0' || c == ',' || c == '#')
1336 /* End of one alternative - mark the regs in the current
1337 class, and reset the class. */
1338 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1343 } while (c != '\0' && c != ',');
1351 case '=': case '+': case '*': case '%': case '?': case '!':
1352 case '0': case '1': case '2': case '3': case '4': case 'm':
1353 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1354 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1355 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1360 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1365 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1369 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1374 /* Those of the registers which are clobbered, but allowed by the
1375 constraints, must be usable as reload registers. So clear them
1376 out of the life information. */
1377 AND_HARD_REG_SET (allowed, clobbered);
1378 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1379 if (TEST_HARD_REG_BIT (allowed, i))
1381 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1382 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1389 /* Copy the global variables n_reloads and rld into the corresponding elts
1392 copy_reloads (chain)
1393 struct insn_chain *chain;
1395 chain->n_reloads = n_reloads;
1397 = (struct reload *) obstack_alloc (&reload_obstack,
1398 n_reloads * sizeof (struct reload));
1399 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1400 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1403 /* Walk the chain of insns, and determine for each whether it needs reloads
1404 and/or eliminations. Build the corresponding insns_need_reload list, and
1405 set something_needs_elimination as appropriate. */
1407 calculate_needs_all_insns (global)
1410 struct insn_chain **pprev_reload = &insns_need_reload;
1411 struct insn_chain *chain, *next = 0;
1413 something_needs_elimination = 0;
1415 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1416 for (chain = reload_insn_chain; chain != 0; chain = next)
1418 rtx insn = chain->insn;
1422 /* Clear out the shortcuts. */
1423 chain->n_reloads = 0;
1424 chain->need_elim = 0;
1425 chain->need_reload = 0;
1426 chain->need_operand_change = 0;
1428 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1429 include REG_LABEL), we need to see what effects this has on the
1430 known offsets at labels. */
1432 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1433 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1434 set_label_offsets (insn, insn, 0);
1438 rtx old_body = PATTERN (insn);
1439 int old_code = INSN_CODE (insn);
1440 rtx old_notes = REG_NOTES (insn);
1441 int did_elimination = 0;
1442 int operands_changed = 0;
1443 rtx set = single_set (insn);
1445 /* Skip insns that only set an equivalence. */
1446 if (set && GET_CODE (SET_DEST (set)) == REG
1447 && reg_renumber[REGNO (SET_DEST (set))] < 0
1448 && reg_equiv_constant[REGNO (SET_DEST (set))])
1451 /* If needed, eliminate any eliminable registers. */
1452 if (num_eliminable || num_eliminable_invariants)
1453 did_elimination = eliminate_regs_in_insn (insn, 0);
1455 /* Analyze the instruction. */
1456 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1457 global, spill_reg_order);
1459 /* If a no-op set needs more than one reload, this is likely
1460 to be something that needs input address reloads. We
1461 can't get rid of this cleanly later, and it is of no use
1462 anyway, so discard it now.
1463 We only do this when expensive_optimizations is enabled,
1464 since this complements reload inheritance / output
1465 reload deletion, and it can make debugging harder. */
1466 if (flag_expensive_optimizations && n_reloads > 1)
1468 rtx set = single_set (insn);
1470 && SET_SRC (set) == SET_DEST (set)
1471 && GET_CODE (SET_SRC (set)) == REG
1472 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1474 PUT_CODE (insn, NOTE);
1475 NOTE_SOURCE_FILE (insn) = 0;
1476 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1477 /* Delete it from the reload chain */
1479 chain->prev->next = next;
1481 reload_insn_chain = next;
1483 next->prev = chain->prev;
1484 chain->next = unused_insn_chains;
1485 unused_insn_chains = chain;
1490 update_eliminable_offsets ();
1492 /* Remember for later shortcuts which insns had any reloads or
1493 register eliminations. */
1494 chain->need_elim = did_elimination;
1495 chain->need_reload = n_reloads > 0;
1496 chain->need_operand_change = operands_changed;
1498 /* Discard any register replacements done. */
1499 if (did_elimination)
1501 obstack_free (&reload_obstack, reload_insn_firstobj);
1502 PATTERN (insn) = old_body;
1503 INSN_CODE (insn) = old_code;
1504 REG_NOTES (insn) = old_notes;
1505 something_needs_elimination = 1;
1508 something_needs_operands_changed |= operands_changed;
1512 copy_reloads (chain);
1513 *pprev_reload = chain;
1514 pprev_reload = &chain->next_need_reload;
1521 /* Comparison function for qsort to decide which of two reloads
1522 should be handled first. *P1 and *P2 are the reload numbers. */
1525 reload_reg_class_lower (r1p, r2p)
1529 register int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1532 /* Consider required reloads before optional ones. */
1533 t = rld[r1].optional - rld[r2].optional;
1537 /* Count all solitary classes before non-solitary ones. */
1538 t = ((reg_class_size[(int) rld[r2].class] == 1)
1539 - (reg_class_size[(int) rld[r1].class] == 1));
1543 /* Aside from solitaires, consider all multi-reg groups first. */
1544 t = rld[r2].nregs - rld[r1].nregs;
1548 /* Consider reloads in order of increasing reg-class number. */
1549 t = (int) rld[r1].class - (int) rld[r2].class;
1553 /* If reloads are equally urgent, sort by reload number,
1554 so that the results of qsort leave nothing to chance. */
1558 /* The cost of spilling each hard reg. */
1559 static int spill_cost[FIRST_PSEUDO_REGISTER];
1561 /* When spilling multiple hard registers, we use SPILL_COST for the first
1562 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1563 only the first hard reg for a multi-reg pseudo. */
1564 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1566 /* Update the spill cost arrays, considering that pseudo REG is live. */
1572 int freq = REG_FREQ (reg);
1573 int r = reg_renumber[reg];
1576 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1577 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1580 SET_REGNO_REG_SET (&pseudos_counted, reg);
1585 spill_add_cost[r] += freq;
1587 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1589 spill_cost[r + nregs] += freq;
1592 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1593 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1596 order_regs_for_reload (chain)
1597 struct insn_chain *chain;
1600 HARD_REG_SET used_by_pseudos;
1601 HARD_REG_SET used_by_pseudos2;
1603 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1605 memset (spill_cost, 0, sizeof spill_cost);
1606 memset (spill_add_cost, 0, sizeof spill_add_cost);
1608 /* Count number of uses of each hard reg by pseudo regs allocated to it
1609 and then order them by decreasing use. First exclude hard registers
1610 that are live in or across this insn. */
1612 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1613 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1614 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1615 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1617 /* Now find out which pseudos are allocated to it, and update
1619 CLEAR_REG_SET (&pseudos_counted);
1621 EXECUTE_IF_SET_IN_REG_SET
1622 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1626 EXECUTE_IF_SET_IN_REG_SET
1627 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1631 CLEAR_REG_SET (&pseudos_counted);
1634 /* Vector of reload-numbers showing the order in which the reloads should
1636 static short reload_order[MAX_RELOADS];
1638 /* This is used to keep track of the spill regs used in one insn. */
1639 static HARD_REG_SET used_spill_regs_local;
1641 /* We decided to spill hard register SPILLED, which has a size of
1642 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1643 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1644 update SPILL_COST/SPILL_ADD_COST. */
1647 count_spilled_pseudo (spilled, spilled_nregs, reg)
1648 int spilled, spilled_nregs, reg;
1650 int r = reg_renumber[reg];
1651 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1653 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1654 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1657 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1659 spill_add_cost[r] -= REG_FREQ (reg);
1661 spill_cost[r + nregs] -= REG_FREQ (reg);
1664 /* Find reload register to use for reload number ORDER. */
1667 find_reg (chain, order)
1668 struct insn_chain *chain;
1671 int rnum = reload_order[order];
1672 struct reload *rl = rld + rnum;
1673 int best_cost = INT_MAX;
1677 HARD_REG_SET not_usable;
1678 HARD_REG_SET used_by_other_reload;
1680 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1681 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1682 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1684 CLEAR_HARD_REG_SET (used_by_other_reload);
1685 for (k = 0; k < order; k++)
1687 int other = reload_order[k];
1689 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1690 for (j = 0; j < rld[other].nregs; j++)
1691 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1694 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1696 unsigned int regno = i;
1698 if (! TEST_HARD_REG_BIT (not_usable, regno)
1699 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1700 && HARD_REGNO_MODE_OK (regno, rl->mode))
1702 int this_cost = spill_cost[regno];
1704 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1706 for (j = 1; j < this_nregs; j++)
1708 this_cost += spill_add_cost[regno + j];
1709 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1710 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1715 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1717 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1719 if (this_cost < best_cost
1720 /* Among registers with equal cost, prefer caller-saved ones, or
1721 use REG_ALLOC_ORDER if it is defined. */
1722 || (this_cost == best_cost
1723 #ifdef REG_ALLOC_ORDER
1724 && (inv_reg_alloc_order[regno]
1725 < inv_reg_alloc_order[best_reg])
1727 && call_used_regs[regno]
1728 && ! call_used_regs[best_reg]
1733 best_cost = this_cost;
1741 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1743 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1744 rl->regno = best_reg;
1746 EXECUTE_IF_SET_IN_REG_SET
1747 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1749 count_spilled_pseudo (best_reg, rl->nregs, j);
1752 EXECUTE_IF_SET_IN_REG_SET
1753 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1755 count_spilled_pseudo (best_reg, rl->nregs, j);
1758 for (i = 0; i < rl->nregs; i++)
1760 if (spill_cost[best_reg + i] != 0
1761 || spill_add_cost[best_reg + i] != 0)
1763 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1768 /* Find more reload regs to satisfy the remaining need of an insn, which
1770 Do it by ascending class number, since otherwise a reg
1771 might be spilled for a big class and might fail to count
1772 for a smaller class even though it belongs to that class. */
1775 find_reload_regs (chain)
1776 struct insn_chain *chain;
1780 /* In order to be certain of getting the registers we need,
1781 we must sort the reloads into order of increasing register class.
1782 Then our grabbing of reload registers will parallel the process
1783 that provided the reload registers. */
1784 for (i = 0; i < chain->n_reloads; i++)
1786 /* Show whether this reload already has a hard reg. */
1787 if (chain->rld[i].reg_rtx)
1789 int regno = REGNO (chain->rld[i].reg_rtx);
1790 chain->rld[i].regno = regno;
1792 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1795 chain->rld[i].regno = -1;
1796 reload_order[i] = i;
1799 n_reloads = chain->n_reloads;
1800 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1802 CLEAR_HARD_REG_SET (used_spill_regs_local);
1805 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1807 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1809 /* Compute the order of preference for hard registers to spill. */
1811 order_regs_for_reload (chain);
1813 for (i = 0; i < n_reloads; i++)
1815 int r = reload_order[i];
1817 /* Ignore reloads that got marked inoperative. */
1818 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1819 && ! rld[r].optional
1820 && rld[r].regno == -1)
1821 if (! find_reg (chain, i))
1823 spill_failure (chain->insn, rld[r].class);
1829 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1830 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1832 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1836 select_reload_regs ()
1838 struct insn_chain *chain;
1840 /* Try to satisfy the needs for each insn. */
1841 for (chain = insns_need_reload; chain != 0;
1842 chain = chain->next_need_reload)
1843 find_reload_regs (chain);
1846 /* Delete all insns that were inserted by emit_caller_save_insns during
1849 delete_caller_save_insns ()
1851 struct insn_chain *c = reload_insn_chain;
1855 while (c != 0 && c->is_caller_save_insn)
1857 struct insn_chain *next = c->next;
1860 if (insn == BLOCK_HEAD (c->block))
1861 BLOCK_HEAD (c->block) = NEXT_INSN (insn);
1862 if (insn == BLOCK_END (c->block))
1863 BLOCK_END (c->block) = PREV_INSN (insn);
1864 if (c == reload_insn_chain)
1865 reload_insn_chain = next;
1867 if (NEXT_INSN (insn) != 0)
1868 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
1869 if (PREV_INSN (insn) != 0)
1870 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
1873 next->prev = c->prev;
1875 c->prev->next = next;
1876 c->next = unused_insn_chains;
1877 unused_insn_chains = c;
1885 /* Handle the failure to find a register to spill.
1886 INSN should be one of the insns which needed this particular spill reg. */
1889 spill_failure (insn, class)
1891 enum reg_class class;
1893 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1894 if (asm_noperands (PATTERN (insn)) >= 0)
1895 error_for_asm (insn, "Can't find a register in class `%s' while reloading `asm'.",
1896 reg_class_names[class]);
1899 error ("Unable to find a register to spill in class `%s'.",
1900 reg_class_names[class]);
1901 fatal_insn ("This is the insn:", insn);
1905 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1906 data that is dead in INSN. */
1909 delete_dead_insn (insn)
1912 rtx prev = prev_real_insn (insn);
1915 /* If the previous insn sets a register that dies in our insn, delete it
1917 if (prev && GET_CODE (PATTERN (prev)) == SET
1918 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1919 && reg_mentioned_p (prev_dest, PATTERN (insn))
1920 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1921 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1922 delete_dead_insn (prev);
1924 PUT_CODE (insn, NOTE);
1925 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1926 NOTE_SOURCE_FILE (insn) = 0;
1929 /* Modify the home of pseudo-reg I.
1930 The new home is present in reg_renumber[I].
1932 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1933 or it may be -1, meaning there is none or it is not relevant.
1934 This is used so that all pseudos spilled from a given hard reg
1935 can share one stack slot. */
1938 alter_reg (i, from_reg)
1942 /* When outputting an inline function, this can happen
1943 for a reg that isn't actually used. */
1944 if (regno_reg_rtx[i] == 0)
1947 /* If the reg got changed to a MEM at rtl-generation time,
1949 if (GET_CODE (regno_reg_rtx[i]) != REG)
1952 /* Modify the reg-rtx to contain the new hard reg
1953 number or else to contain its pseudo reg number. */
1954 REGNO (regno_reg_rtx[i])
1955 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1957 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1958 allocate a stack slot for it. */
1960 if (reg_renumber[i] < 0
1961 && REG_N_REFS (i) > 0
1962 && reg_equiv_constant[i] == 0
1963 && reg_equiv_memory_loc[i] == 0)
1966 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1967 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1970 /* Each pseudo reg has an inherent size which comes from its own mode,
1971 and a total size which provides room for paradoxical subregs
1972 which refer to the pseudo reg in wider modes.
1974 We can use a slot already allocated if it provides both
1975 enough inherent space and enough total space.
1976 Otherwise, we allocate a new slot, making sure that it has no less
1977 inherent space, and no less total space, then the previous slot. */
1980 /* No known place to spill from => no slot to reuse. */
1981 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1982 inherent_size == total_size ? 0 : -1);
1983 if (BYTES_BIG_ENDIAN)
1984 /* Cancel the big-endian correction done in assign_stack_local.
1985 Get the address of the beginning of the slot.
1986 This is so we can do a big-endian correction unconditionally
1988 adjust = inherent_size - total_size;
1990 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1992 /* Nothing can alias this slot except this pseudo. */
1993 set_mem_alias_set (x, new_alias_set ());
1996 /* Reuse a stack slot if possible. */
1997 else if (spill_stack_slot[from_reg] != 0
1998 && spill_stack_slot_width[from_reg] >= total_size
1999 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2001 x = spill_stack_slot[from_reg];
2003 /* Allocate a bigger slot. */
2006 /* Compute maximum size needed, both for inherent size
2007 and for total size. */
2008 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2011 if (spill_stack_slot[from_reg])
2013 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2015 mode = GET_MODE (spill_stack_slot[from_reg]);
2016 if (spill_stack_slot_width[from_reg] > total_size)
2017 total_size = spill_stack_slot_width[from_reg];
2020 /* Make a slot with that size. */
2021 x = assign_stack_local (mode, total_size,
2022 inherent_size == total_size ? 0 : -1);
2025 /* All pseudos mapped to this slot can alias each other. */
2026 if (spill_stack_slot[from_reg])
2027 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2029 set_mem_alias_set (x, new_alias_set ());
2031 if (BYTES_BIG_ENDIAN)
2033 /* Cancel the big-endian correction done in assign_stack_local.
2034 Get the address of the beginning of the slot.
2035 This is so we can do a big-endian correction unconditionally
2037 adjust = GET_MODE_SIZE (mode) - total_size;
2039 stack_slot = gen_rtx_MEM (mode_for_size (total_size
2042 plus_constant (XEXP (x, 0), adjust));
2045 spill_stack_slot[from_reg] = stack_slot;
2046 spill_stack_slot_width[from_reg] = total_size;
2049 /* On a big endian machine, the "address" of the slot
2050 is the address of the low part that fits its inherent mode. */
2051 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2052 adjust += (total_size - inherent_size);
2054 /* If we have any adjustment to make, or if the stack slot is the
2055 wrong mode, make a new stack slot. */
2056 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2057 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2059 /* Save the stack slot for later. */
2060 reg_equiv_memory_loc[i] = x;
2064 /* Mark the slots in regs_ever_live for the hard regs
2065 used by pseudo-reg number REGNO. */
2068 mark_home_live (regno)
2071 register int i, lim;
2073 i = reg_renumber[regno];
2076 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2078 regs_ever_live[i++] = 1;
2081 /* This function handles the tracking of elimination offsets around branches.
2083 X is a piece of RTL being scanned.
2085 INSN is the insn that it came from, if any.
2087 INITIAL_P is non-zero if we are to set the offset to be the initial
2088 offset and zero if we are setting the offset of the label to be the
2092 set_label_offsets (x, insn, initial_p)
2097 enum rtx_code code = GET_CODE (x);
2100 struct elim_table *p;
2105 if (LABEL_REF_NONLOCAL_P (x))
2110 /* ... fall through ... */
2113 /* If we know nothing about this label, set the desired offsets. Note
2114 that this sets the offset at a label to be the offset before a label
2115 if we don't know anything about the label. This is not correct for
2116 the label after a BARRIER, but is the best guess we can make. If
2117 we guessed wrong, we will suppress an elimination that might have
2118 been possible had we been able to guess correctly. */
2120 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2122 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2123 offsets_at[CODE_LABEL_NUMBER (x)][i]
2124 = (initial_p ? reg_eliminate[i].initial_offset
2125 : reg_eliminate[i].offset);
2126 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2129 /* Otherwise, if this is the definition of a label and it is
2130 preceded by a BARRIER, set our offsets to the known offset of
2134 && (tem = prev_nonnote_insn (insn)) != 0
2135 && GET_CODE (tem) == BARRIER)
2136 set_offsets_for_label (insn);
2138 /* If neither of the above cases is true, compare each offset
2139 with those previously recorded and suppress any eliminations
2140 where the offsets disagree. */
2142 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2143 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2144 != (initial_p ? reg_eliminate[i].initial_offset
2145 : reg_eliminate[i].offset))
2146 reg_eliminate[i].can_eliminate = 0;
2151 set_label_offsets (PATTERN (insn), insn, initial_p);
2153 /* ... fall through ... */
2157 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2158 and hence must have all eliminations at their initial offsets. */
2159 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2160 if (REG_NOTE_KIND (tem) == REG_LABEL)
2161 set_label_offsets (XEXP (tem, 0), insn, 1);
2167 /* Each of the labels in the parallel or address vector must be
2168 at their initial offsets. We want the first field for PARALLEL
2169 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2171 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2172 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2177 /* We only care about setting PC. If the source is not RETURN,
2178 IF_THEN_ELSE, or a label, disable any eliminations not at
2179 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2180 isn't one of those possibilities. For branches to a label,
2181 call ourselves recursively.
2183 Note that this can disable elimination unnecessarily when we have
2184 a non-local goto since it will look like a non-constant jump to
2185 someplace in the current function. This isn't a significant
2186 problem since such jumps will normally be when all elimination
2187 pairs are back to their initial offsets. */
2189 if (SET_DEST (x) != pc_rtx)
2192 switch (GET_CODE (SET_SRC (x)))
2199 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2203 tem = XEXP (SET_SRC (x), 1);
2204 if (GET_CODE (tem) == LABEL_REF)
2205 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2206 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2209 tem = XEXP (SET_SRC (x), 2);
2210 if (GET_CODE (tem) == LABEL_REF)
2211 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2212 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2220 /* If we reach here, all eliminations must be at their initial
2221 offset because we are doing a jump to a variable address. */
2222 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2223 if (p->offset != p->initial_offset)
2224 p->can_eliminate = 0;
2232 /* Scan X and replace any eliminable registers (such as fp) with a
2233 replacement (such as sp), plus an offset.
2235 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2236 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2237 MEM, we are allowed to replace a sum of a register and the constant zero
2238 with the register, which we cannot do outside a MEM. In addition, we need
2239 to record the fact that a register is referenced outside a MEM.
2241 If INSN is an insn, it is the insn containing X. If we replace a REG
2242 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2243 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2244 the REG is being modified.
2246 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2247 That's used when we eliminate in expressions stored in notes.
2248 This means, do not set ref_outside_mem even if the reference
2251 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2252 replacements done assuming all offsets are at their initial values. If
2253 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2254 encounter, return the actual location so that find_reloads will do
2255 the proper thing. */
2258 eliminate_regs (x, mem_mode, insn)
2260 enum machine_mode mem_mode;
2263 enum rtx_code code = GET_CODE (x);
2264 struct elim_table *ep;
2271 if (! current_function_decl)
2290 /* This is only for the benefit of the debugging backends, which call
2291 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2292 removed after CSE. */
2293 new = eliminate_regs (XEXP (x, 0), 0, insn);
2294 if (GET_CODE (new) == MEM)
2295 return XEXP (new, 0);
2301 /* First handle the case where we encounter a bare register that
2302 is eliminable. Replace it with a PLUS. */
2303 if (regno < FIRST_PSEUDO_REGISTER)
2305 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2307 if (ep->from_rtx == x && ep->can_eliminate)
2308 return plus_constant (ep->to_rtx, ep->previous_offset);
2311 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2312 && reg_equiv_constant[regno]
2313 && ! CONSTANT_P (reg_equiv_constant[regno]))
2314 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2318 /* You might think handling MINUS in a manner similar to PLUS is a
2319 good idea. It is not. It has been tried multiple times and every
2320 time the change has had to have been reverted.
2322 Other parts of reload know a PLUS is special (gen_reload for example)
2323 and require special code to handle code a reloaded PLUS operand.
2325 Also consider backends where the flags register is clobbered by a
2326 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2327 lea instruction comes to mind). If we try to reload a MINUS, we
2328 may kill the flags register that was holding a useful value.
2330 So, please before trying to handle MINUS, consider reload as a
2331 whole instead of this little section as well as the backend issues. */
2333 /* If this is the sum of an eliminable register and a constant, rework
2335 if (GET_CODE (XEXP (x, 0)) == REG
2336 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2337 && CONSTANT_P (XEXP (x, 1)))
2339 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2341 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2343 /* The only time we want to replace a PLUS with a REG (this
2344 occurs when the constant operand of the PLUS is the negative
2345 of the offset) is when we are inside a MEM. We won't want
2346 to do so at other times because that would change the
2347 structure of the insn in a way that reload can't handle.
2348 We special-case the commonest situation in
2349 eliminate_regs_in_insn, so just replace a PLUS with a
2350 PLUS here, unless inside a MEM. */
2351 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2352 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2355 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2356 plus_constant (XEXP (x, 1),
2357 ep->previous_offset));
2360 /* If the register is not eliminable, we are done since the other
2361 operand is a constant. */
2365 /* If this is part of an address, we want to bring any constant to the
2366 outermost PLUS. We will do this by doing register replacement in
2367 our operands and seeing if a constant shows up in one of them.
2369 Note that there is no risk of modifying the structure of the insn,
2370 since we only get called for its operands, thus we are either
2371 modifying the address inside a MEM, or something like an address
2372 operand of a load-address insn. */
2375 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2376 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2378 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2380 /* If one side is a PLUS and the other side is a pseudo that
2381 didn't get a hard register but has a reg_equiv_constant,
2382 we must replace the constant here since it may no longer
2383 be in the position of any operand. */
2384 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2385 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2386 && reg_renumber[REGNO (new1)] < 0
2387 && reg_equiv_constant != 0
2388 && reg_equiv_constant[REGNO (new1)] != 0)
2389 new1 = reg_equiv_constant[REGNO (new1)];
2390 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2391 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2392 && reg_renumber[REGNO (new0)] < 0
2393 && reg_equiv_constant[REGNO (new0)] != 0)
2394 new0 = reg_equiv_constant[REGNO (new0)];
2396 new = form_sum (new0, new1);
2398 /* As above, if we are not inside a MEM we do not want to
2399 turn a PLUS into something else. We might try to do so here
2400 for an addition of 0 if we aren't optimizing. */
2401 if (! mem_mode && GET_CODE (new) != PLUS)
2402 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2410 /* If this is the product of an eliminable register and a
2411 constant, apply the distribute law and move the constant out
2412 so that we have (plus (mult ..) ..). This is needed in order
2413 to keep load-address insns valid. This case is pathological.
2414 We ignore the possibility of overflow here. */
2415 if (GET_CODE (XEXP (x, 0)) == REG
2416 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2417 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2418 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2420 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2423 /* Refs inside notes don't count for this purpose. */
2424 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2425 || GET_CODE (insn) == INSN_LIST)))
2426 ep->ref_outside_mem = 1;
2429 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2430 ep->previous_offset * INTVAL (XEXP (x, 1)));
2433 /* ... fall through ... */
2437 /* See comments before PLUS about handling MINUS. */
2439 case DIV: case UDIV:
2440 case MOD: case UMOD:
2441 case AND: case IOR: case XOR:
2442 case ROTATERT: case ROTATE:
2443 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2445 case GE: case GT: case GEU: case GTU:
2446 case LE: case LT: case LEU: case LTU:
2448 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2450 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2452 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2453 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2458 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2461 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2462 if (new != XEXP (x, 0))
2464 /* If this is a REG_DEAD note, it is not valid anymore.
2465 Using the eliminated version could result in creating a
2466 REG_DEAD note for the stack or frame pointer. */
2467 if (GET_MODE (x) == REG_DEAD)
2469 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2472 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2476 /* ... fall through ... */
2479 /* Now do eliminations in the rest of the chain. If this was
2480 an EXPR_LIST, this might result in allocating more memory than is
2481 strictly needed, but it simplifies the code. */
2484 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2485 if (new != XEXP (x, 1))
2486 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2494 case STRICT_LOW_PART:
2496 case SIGN_EXTEND: case ZERO_EXTEND:
2497 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2498 case FLOAT: case FIX:
2499 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2503 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2504 if (new != XEXP (x, 0))
2505 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2509 /* Similar to above processing, but preserve SUBREG_BYTE.
2510 Convert (subreg (mem)) to (mem) if not paradoxical.
2511 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2512 pseudo didn't get a hard reg, we must replace this with the
2513 eliminated version of the memory location because push_reloads
2514 may do the replacement in certain circumstances. */
2515 if (GET_CODE (SUBREG_REG (x)) == REG
2516 && (GET_MODE_SIZE (GET_MODE (x))
2517 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2518 && reg_equiv_memory_loc != 0
2519 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2521 new = SUBREG_REG (x);
2524 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2526 if (new != SUBREG_REG (x))
2528 int x_size = GET_MODE_SIZE (GET_MODE (x));
2529 int new_size = GET_MODE_SIZE (GET_MODE (new));
2531 if (GET_CODE (new) == MEM
2532 && ((x_size < new_size
2533 #ifdef WORD_REGISTER_OPERATIONS
2534 /* On these machines, combine can create rtl of the form
2535 (set (subreg:m1 (reg:m2 R) 0) ...)
2536 where m1 < m2, and expects something interesting to
2537 happen to the entire word. Moreover, it will use the
2538 (reg:m2 R) later, expecting all bits to be preserved.
2539 So if the number of words is the same, preserve the
2540 subreg so that push_reloads can see it. */
2541 && ! ((x_size - 1) / UNITS_PER_WORD
2542 == (new_size -1 ) / UNITS_PER_WORD)
2545 || x_size == new_size)
2548 int offset = SUBREG_BYTE (x);
2549 enum machine_mode mode = GET_MODE (x);
2551 PUT_MODE (new, mode);
2552 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2556 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2562 /* This is only for the benefit of the debugging backends, which call
2563 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2564 removed after CSE. */
2565 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2566 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2568 /* Our only special processing is to pass the mode of the MEM to our
2569 recursive call and copy the flags. While we are here, handle this
2570 case more efficiently. */
2572 replace_equiv_address_nv (x,
2573 eliminate_regs (XEXP (x, 0),
2574 GET_MODE (x), insn));
2577 /* Handle insn_list USE that a call to a pure function may generate. */
2578 new = eliminate_regs (XEXP (x, 0), 0, insn);
2579 if (new != XEXP (x, 0))
2580 return gen_rtx_USE (GET_MODE (x), new);
2592 /* Process each of our operands recursively. If any have changed, make a
2594 fmt = GET_RTX_FORMAT (code);
2595 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2599 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2600 if (new != XEXP (x, i) && ! copied)
2602 rtx new_x = rtx_alloc (code);
2604 (sizeof (*new_x) - sizeof (new_x->fld)
2605 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2611 else if (*fmt == 'E')
2614 for (j = 0; j < XVECLEN (x, i); j++)
2616 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2617 if (new != XVECEXP (x, i, j) && ! copied_vec)
2619 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2623 rtx new_x = rtx_alloc (code);
2625 (sizeof (*new_x) - sizeof (new_x->fld)
2626 + (sizeof (new_x->fld[0])
2627 * GET_RTX_LENGTH (code))));
2631 XVEC (x, i) = new_v;
2634 XVECEXP (x, i, j) = new;
2642 /* Scan rtx X for modifications of elimination target registers. Update
2643 the table of eliminables to reflect the changed state. MEM_MODE is
2644 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2647 elimination_effects (x, mem_mode)
2649 enum machine_mode mem_mode;
2652 enum rtx_code code = GET_CODE (x);
2653 struct elim_table *ep;
2679 /* First handle the case where we encounter a bare register that
2680 is eliminable. Replace it with a PLUS. */
2681 if (regno < FIRST_PSEUDO_REGISTER)
2683 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2685 if (ep->from_rtx == x && ep->can_eliminate)
2688 ep->ref_outside_mem = 1;
2693 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2694 && reg_equiv_constant[regno]
2695 && ! CONSTANT_P (reg_equiv_constant[regno]))
2696 elimination_effects (reg_equiv_constant[regno], mem_mode);
2705 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2706 if (ep->to_rtx == XEXP (x, 0))
2708 int size = GET_MODE_SIZE (mem_mode);
2710 /* If more bytes than MEM_MODE are pushed, account for them. */
2711 #ifdef PUSH_ROUNDING
2712 if (ep->to_rtx == stack_pointer_rtx)
2713 size = PUSH_ROUNDING (size);
2715 if (code == PRE_DEC || code == POST_DEC)
2717 else if (code == PRE_INC || code == POST_INC)
2719 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2720 && GET_CODE (XEXP (x, 1)) == PLUS
2721 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2722 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2723 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2726 /* These two aren't unary operators. */
2727 if (code == POST_MODIFY || code == PRE_MODIFY)
2730 /* Fall through to generic unary operation case. */
2731 case STRICT_LOW_PART:
2733 case SIGN_EXTEND: case ZERO_EXTEND:
2734 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2735 case FLOAT: case FIX:
2736 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2740 elimination_effects (XEXP (x, 0), mem_mode);
2744 if (GET_CODE (SUBREG_REG (x)) == REG
2745 && (GET_MODE_SIZE (GET_MODE (x))
2746 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2747 && reg_equiv_memory_loc != 0
2748 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2751 elimination_effects (SUBREG_REG (x), mem_mode);
2755 /* If using a register that is the source of an eliminate we still
2756 think can be performed, note it cannot be performed since we don't
2757 know how this register is used. */
2758 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2759 if (ep->from_rtx == XEXP (x, 0))
2760 ep->can_eliminate = 0;
2762 elimination_effects (XEXP (x, 0), mem_mode);
2766 /* If clobbering a register that is the replacement register for an
2767 elimination we still think can be performed, note that it cannot
2768 be performed. Otherwise, we need not be concerned about it. */
2769 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2770 if (ep->to_rtx == XEXP (x, 0))
2771 ep->can_eliminate = 0;
2773 elimination_effects (XEXP (x, 0), mem_mode);
2777 /* Check for setting a register that we know about. */
2778 if (GET_CODE (SET_DEST (x)) == REG)
2780 /* See if this is setting the replacement register for an
2783 If DEST is the hard frame pointer, we do nothing because we
2784 assume that all assignments to the frame pointer are for
2785 non-local gotos and are being done at a time when they are valid
2786 and do not disturb anything else. Some machines want to
2787 eliminate a fake argument pointer (or even a fake frame pointer)
2788 with either the real frame or the stack pointer. Assignments to
2789 the hard frame pointer must not prevent this elimination. */
2791 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2793 if (ep->to_rtx == SET_DEST (x)
2794 && SET_DEST (x) != hard_frame_pointer_rtx)
2796 /* If it is being incremented, adjust the offset. Otherwise,
2797 this elimination can't be done. */
2798 rtx src = SET_SRC (x);
2800 if (GET_CODE (src) == PLUS
2801 && XEXP (src, 0) == SET_DEST (x)
2802 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2803 ep->offset -= INTVAL (XEXP (src, 1));
2805 ep->can_eliminate = 0;
2809 elimination_effects (SET_DEST (x), 0);
2810 elimination_effects (SET_SRC (x), 0);
2814 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2817 /* Our only special processing is to pass the mode of the MEM to our
2819 elimination_effects (XEXP (x, 0), GET_MODE (x));
2826 fmt = GET_RTX_FORMAT (code);
2827 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2830 elimination_effects (XEXP (x, i), mem_mode);
2831 else if (*fmt == 'E')
2832 for (j = 0; j < XVECLEN (x, i); j++)
2833 elimination_effects (XVECEXP (x, i, j), mem_mode);
2837 /* Descend through rtx X and verify that no references to eliminable registers
2838 remain. If any do remain, mark the involved register as not
2842 check_eliminable_occurrences (x)
2852 code = GET_CODE (x);
2854 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2856 struct elim_table *ep;
2858 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2859 if (ep->from_rtx == x && ep->can_eliminate)
2860 ep->can_eliminate = 0;
2864 fmt = GET_RTX_FORMAT (code);
2865 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2868 check_eliminable_occurrences (XEXP (x, i));
2869 else if (*fmt == 'E')
2872 for (j = 0; j < XVECLEN (x, i); j++)
2873 check_eliminable_occurrences (XVECEXP (x, i, j));
2878 /* Scan INSN and eliminate all eliminable registers in it.
2880 If REPLACE is nonzero, do the replacement destructively. Also
2881 delete the insn as dead it if it is setting an eliminable register.
2883 If REPLACE is zero, do all our allocations in reload_obstack.
2885 If no eliminations were done and this insn doesn't require any elimination
2886 processing (these are not identical conditions: it might be updating sp,
2887 but not referencing fp; this needs to be seen during reload_as_needed so
2888 that the offset between fp and sp can be taken into consideration), zero
2889 is returned. Otherwise, 1 is returned. */
2892 eliminate_regs_in_insn (insn, replace)
2896 int icode = recog_memoized (insn);
2897 rtx old_body = PATTERN (insn);
2898 int insn_is_asm = asm_noperands (old_body) >= 0;
2899 rtx old_set = single_set (insn);
2903 rtx substed_operand[MAX_RECOG_OPERANDS];
2904 rtx orig_operand[MAX_RECOG_OPERANDS];
2905 struct elim_table *ep;
2907 if (! insn_is_asm && icode < 0)
2909 if (GET_CODE (PATTERN (insn)) == USE
2910 || GET_CODE (PATTERN (insn)) == CLOBBER
2911 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2912 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2913 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2918 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2919 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2921 /* Check for setting an eliminable register. */
2922 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2923 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2925 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2926 /* If this is setting the frame pointer register to the
2927 hardware frame pointer register and this is an elimination
2928 that will be done (tested above), this insn is really
2929 adjusting the frame pointer downward to compensate for
2930 the adjustment done before a nonlocal goto. */
2931 if (ep->from == FRAME_POINTER_REGNUM
2932 && ep->to == HARD_FRAME_POINTER_REGNUM)
2934 rtx src = SET_SRC (old_set);
2935 int offset = 0, ok = 0;
2936 rtx prev_insn, prev_set;
2938 if (src == ep->to_rtx)
2940 else if (GET_CODE (src) == PLUS
2941 && GET_CODE (XEXP (src, 0)) == CONST_INT
2942 && XEXP (src, 1) == ep->to_rtx)
2943 offset = INTVAL (XEXP (src, 0)), ok = 1;
2944 else if (GET_CODE (src) == PLUS
2945 && GET_CODE (XEXP (src, 1)) == CONST_INT
2946 && XEXP (src, 0) == ep->to_rtx)
2947 offset = INTVAL (XEXP (src, 1)), ok = 1;
2948 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
2949 && (prev_set = single_set (prev_insn)) != 0
2950 && rtx_equal_p (SET_DEST (prev_set), src))
2952 src = SET_SRC (prev_set);
2953 if (src == ep->to_rtx)
2955 else if (GET_CODE (src) == PLUS
2956 && GET_CODE (XEXP (src, 0)) == CONST_INT
2957 && XEXP (src, 1) == ep->to_rtx)
2958 offset = INTVAL (XEXP (src, 0)), ok = 1;
2959 else if (GET_CODE (src) == PLUS
2960 && GET_CODE (XEXP (src, 1)) == CONST_INT
2961 && XEXP (src, 0) == ep->to_rtx)
2962 offset = INTVAL (XEXP (src, 1)), ok = 1;
2968 = plus_constant (ep->to_rtx, offset - ep->offset);
2970 new_body = old_body;
2973 new_body = copy_insn (old_body);
2974 if (REG_NOTES (insn))
2975 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2977 PATTERN (insn) = new_body;
2978 old_set = single_set (insn);
2980 /* First see if this insn remains valid when we
2981 make the change. If not, keep the INSN_CODE
2982 the same and let reload fit it up. */
2983 validate_change (insn, &SET_SRC (old_set), src, 1);
2984 validate_change (insn, &SET_DEST (old_set),
2986 if (! apply_change_group ())
2988 SET_SRC (old_set) = src;
2989 SET_DEST (old_set) = ep->to_rtx;
2998 /* In this case this insn isn't serving a useful purpose. We
2999 will delete it in reload_as_needed once we know that this
3000 elimination is, in fact, being done.
3002 If REPLACE isn't set, we can't delete this insn, but needn't
3003 process it since it won't be used unless something changes. */
3006 delete_dead_insn (insn);
3014 /* We allow one special case which happens to work on all machines we
3015 currently support: a single set with the source being a PLUS of an
3016 eliminable register and a constant. */
3018 && GET_CODE (SET_DEST (old_set)) == REG
3019 && GET_CODE (SET_SRC (old_set)) == PLUS
3020 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3021 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
3022 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
3024 rtx reg = XEXP (SET_SRC (old_set), 0);
3025 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
3027 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3028 if (ep->from_rtx == reg && ep->can_eliminate)
3030 offset += ep->offset;
3035 /* We assume here that if we need a PARALLEL with
3036 CLOBBERs for this assignment, we can do with the
3037 MATCH_SCRATCHes that add_clobbers allocates.
3038 There's not much we can do if that doesn't work. */
3039 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3043 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3046 rtvec vec = rtvec_alloc (num_clobbers + 1);
3048 vec->elem[0] = PATTERN (insn);
3049 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3050 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3052 if (INSN_CODE (insn) < 0)
3057 new_body = old_body;
3060 new_body = copy_insn (old_body);
3061 if (REG_NOTES (insn))
3062 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3064 PATTERN (insn) = new_body;
3065 old_set = single_set (insn);
3067 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3068 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3071 /* This can't have an effect on elimination offsets, so skip right
3077 /* Determine the effects of this insn on elimination offsets. */
3078 elimination_effects (old_body, 0);
3080 /* Eliminate all eliminable registers occurring in operands that
3081 can be handled by reload. */
3082 extract_insn (insn);
3084 for (i = 0; i < recog_data.n_operands; i++)
3086 orig_operand[i] = recog_data.operand[i];
3087 substed_operand[i] = recog_data.operand[i];
3089 /* For an asm statement, every operand is eliminable. */
3090 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3092 /* Check for setting a register that we know about. */
3093 if (recog_data.operand_type[i] != OP_IN
3094 && GET_CODE (orig_operand[i]) == REG)
3096 /* If we are assigning to a register that can be eliminated, it
3097 must be as part of a PARALLEL, since the code above handles
3098 single SETs. We must indicate that we can no longer
3099 eliminate this reg. */
3100 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3102 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3103 ep->can_eliminate = 0;
3106 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3107 replace ? insn : NULL_RTX);
3108 if (substed_operand[i] != orig_operand[i])
3109 val = any_changes = 1;
3110 /* Terminate the search in check_eliminable_occurrences at
3112 *recog_data.operand_loc[i] = 0;
3114 /* If an output operand changed from a REG to a MEM and INSN is an
3115 insn, write a CLOBBER insn. */
3116 if (recog_data.operand_type[i] != OP_IN
3117 && GET_CODE (orig_operand[i]) == REG
3118 && GET_CODE (substed_operand[i]) == MEM
3120 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3125 for (i = 0; i < recog_data.n_dups; i++)
3126 *recog_data.dup_loc[i]
3127 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3129 /* If any eliminable remain, they aren't eliminable anymore. */
3130 check_eliminable_occurrences (old_body);
3132 /* Substitute the operands; the new values are in the substed_operand
3134 for (i = 0; i < recog_data.n_operands; i++)
3135 *recog_data.operand_loc[i] = substed_operand[i];
3136 for (i = 0; i < recog_data.n_dups; i++)
3137 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3139 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3140 re-recognize the insn. We do this in case we had a simple addition
3141 but now can do this as a load-address. This saves an insn in this
3143 If re-recognition fails, the old insn code number will still be used,
3144 and some register operands may have changed into PLUS expressions.
3145 These will be handled by find_reloads by loading them into a register
3150 /* If we aren't replacing things permanently and we changed something,
3151 make another copy to ensure that all the RTL is new. Otherwise
3152 things can go wrong if find_reload swaps commutative operands
3153 and one is inside RTL that has been copied while the other is not. */
3154 new_body = old_body;
3157 new_body = copy_insn (old_body);
3158 if (REG_NOTES (insn))
3159 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3161 PATTERN (insn) = new_body;
3163 /* If we had a move insn but now we don't, rerecognize it. This will
3164 cause spurious re-recognition if the old move had a PARALLEL since
3165 the new one still will, but we can't call single_set without
3166 having put NEW_BODY into the insn and the re-recognition won't
3167 hurt in this rare case. */
3168 /* ??? Why this huge if statement - why don't we just rerecognize the
3172 && ((GET_CODE (SET_SRC (old_set)) == REG
3173 && (GET_CODE (new_body) != SET
3174 || GET_CODE (SET_SRC (new_body)) != REG))
3175 /* If this was a load from or store to memory, compare
3176 the MEM in recog_data.operand to the one in the insn.
3177 If they are not equal, then rerecognize the insn. */
3179 && ((GET_CODE (SET_SRC (old_set)) == MEM
3180 && SET_SRC (old_set) != recog_data.operand[1])
3181 || (GET_CODE (SET_DEST (old_set)) == MEM
3182 && SET_DEST (old_set) != recog_data.operand[0])))
3183 /* If this was an add insn before, rerecognize. */
3184 || GET_CODE (SET_SRC (old_set)) == PLUS))
3186 int new_icode = recog (PATTERN (insn), insn, 0);
3188 INSN_CODE (insn) = icode;
3192 /* Restore the old body. If there were any changes to it, we made a copy
3193 of it while the changes were still in place, so we'll correctly return
3194 a modified insn below. */
3197 /* Restore the old body. */
3198 for (i = 0; i < recog_data.n_operands; i++)
3199 *recog_data.operand_loc[i] = orig_operand[i];
3200 for (i = 0; i < recog_data.n_dups; i++)
3201 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3204 /* Update all elimination pairs to reflect the status after the current
3205 insn. The changes we make were determined by the earlier call to
3206 elimination_effects.
3208 We also detect a cases where register elimination cannot be done,
3209 namely, if a register would be both changed and referenced outside a MEM
3210 in the resulting insn since such an insn is often undefined and, even if
3211 not, we cannot know what meaning will be given to it. Note that it is
3212 valid to have a register used in an address in an insn that changes it
3213 (presumably with a pre- or post-increment or decrement).
3215 If anything changes, return nonzero. */
3217 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3219 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3220 ep->can_eliminate = 0;
3222 ep->ref_outside_mem = 0;
3224 if (ep->previous_offset != ep->offset)
3229 /* If we changed something, perform elimination in REG_NOTES. This is
3230 needed even when REPLACE is zero because a REG_DEAD note might refer
3231 to a register that we eliminate and could cause a different number
3232 of spill registers to be needed in the final reload pass than in
3234 if (val && REG_NOTES (insn) != 0)
3235 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3240 /* Loop through all elimination pairs.
3241 Recalculate the number not at initial offset.
3243 Compute the maximum offset (minimum offset if the stack does not
3244 grow downward) for each elimination pair. */
3247 update_eliminable_offsets ()
3249 struct elim_table *ep;
3251 num_not_at_initial_offset = 0;
3252 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3254 ep->previous_offset = ep->offset;
3255 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3256 num_not_at_initial_offset++;
3260 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3261 replacement we currently believe is valid, mark it as not eliminable if X
3262 modifies DEST in any way other than by adding a constant integer to it.
3264 If DEST is the frame pointer, we do nothing because we assume that
3265 all assignments to the hard frame pointer are nonlocal gotos and are being
3266 done at a time when they are valid and do not disturb anything else.
3267 Some machines want to eliminate a fake argument pointer with either the
3268 frame or stack pointer. Assignments to the hard frame pointer must not
3269 prevent this elimination.
3271 Called via note_stores from reload before starting its passes to scan
3272 the insns of the function. */
3275 mark_not_eliminable (dest, x, data)
3278 void *data ATTRIBUTE_UNUSED;
3280 register unsigned int i;
3282 /* A SUBREG of a hard register here is just changing its mode. We should
3283 not see a SUBREG of an eliminable hard register, but check just in
3285 if (GET_CODE (dest) == SUBREG)
3286 dest = SUBREG_REG (dest);
3288 if (dest == hard_frame_pointer_rtx)
3291 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3292 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3293 && (GET_CODE (x) != SET
3294 || GET_CODE (SET_SRC (x)) != PLUS
3295 || XEXP (SET_SRC (x), 0) != dest
3296 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3298 reg_eliminate[i].can_eliminate_previous
3299 = reg_eliminate[i].can_eliminate = 0;
3304 /* Verify that the initial elimination offsets did not change since the
3305 last call to set_initial_elim_offsets. This is used to catch cases
3306 where something illegal happened during reload_as_needed that could
3307 cause incorrect code to be generated if we did not check for it. */
3310 verify_initial_elim_offsets ()
3314 #ifdef ELIMINABLE_REGS
3315 struct elim_table *ep;
3317 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3319 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3320 if (t != ep->initial_offset)
3324 INITIAL_FRAME_POINTER_OFFSET (t);
3325 if (t != reg_eliminate[0].initial_offset)
3330 /* Reset all offsets on eliminable registers to their initial values. */
3333 set_initial_elim_offsets ()
3335 struct elim_table *ep = reg_eliminate;
3337 #ifdef ELIMINABLE_REGS
3338 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3340 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3341 ep->previous_offset = ep->offset = ep->initial_offset;
3344 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3345 ep->previous_offset = ep->offset = ep->initial_offset;
3348 num_not_at_initial_offset = 0;
3351 /* Initialize the known label offsets.
3352 Set a known offset for each forced label to be at the initial offset
3353 of each elimination. We do this because we assume that all
3354 computed jumps occur from a location where each elimination is
3355 at its initial offset.
3356 For all other labels, show that we don't know the offsets. */
3359 set_initial_label_offsets ()
3362 memset ((char *) &offsets_known_at[get_first_label_num ()], 0, num_labels);
3364 for (x = forced_labels; x; x = XEXP (x, 1))
3366 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3369 /* Set all elimination offsets to the known values for the code label given
3373 set_offsets_for_label (insn)
3377 int label_nr = CODE_LABEL_NUMBER (insn);
3378 struct elim_table *ep;
3380 num_not_at_initial_offset = 0;
3381 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3383 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3384 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3385 num_not_at_initial_offset++;
3389 /* See if anything that happened changes which eliminations are valid.
3390 For example, on the Sparc, whether or not the frame pointer can
3391 be eliminated can depend on what registers have been used. We need
3392 not check some conditions again (such as flag_omit_frame_pointer)
3393 since they can't have changed. */
3396 update_eliminables (pset)
3399 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3400 int previous_frame_pointer_needed = frame_pointer_needed;
3402 struct elim_table *ep;
3404 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3405 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3406 #ifdef ELIMINABLE_REGS
3407 || ! CAN_ELIMINATE (ep->from, ep->to)
3410 ep->can_eliminate = 0;
3412 /* Look for the case where we have discovered that we can't replace
3413 register A with register B and that means that we will now be
3414 trying to replace register A with register C. This means we can
3415 no longer replace register C with register B and we need to disable
3416 such an elimination, if it exists. This occurs often with A == ap,
3417 B == sp, and C == fp. */
3419 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3421 struct elim_table *op;
3422 register int new_to = -1;
3424 if (! ep->can_eliminate && ep->can_eliminate_previous)
3426 /* Find the current elimination for ep->from, if there is a
3428 for (op = reg_eliminate;
3429 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3430 if (op->from == ep->from && op->can_eliminate)
3436 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3438 for (op = reg_eliminate;
3439 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3440 if (op->from == new_to && op->to == ep->to)
3441 op->can_eliminate = 0;
3445 /* See if any registers that we thought we could eliminate the previous
3446 time are no longer eliminable. If so, something has changed and we
3447 must spill the register. Also, recompute the number of eliminable
3448 registers and see if the frame pointer is needed; it is if there is
3449 no elimination of the frame pointer that we can perform. */
3451 frame_pointer_needed = 1;
3452 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3454 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3455 && ep->to != HARD_FRAME_POINTER_REGNUM)
3456 frame_pointer_needed = 0;
3458 if (! ep->can_eliminate && ep->can_eliminate_previous)
3460 ep->can_eliminate_previous = 0;
3461 SET_HARD_REG_BIT (*pset, ep->from);
3466 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3467 /* If we didn't need a frame pointer last time, but we do now, spill
3468 the hard frame pointer. */
3469 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3470 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3474 /* Initialize the table of registers to eliminate. */
3479 struct elim_table *ep;
3480 #ifdef ELIMINABLE_REGS
3481 struct elim_table_1 *ep1;
3485 reg_eliminate = (struct elim_table *)
3486 xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3488 /* Does this function require a frame pointer? */
3490 frame_pointer_needed = (! flag_omit_frame_pointer
3491 #ifdef EXIT_IGNORE_STACK
3492 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3493 and restore sp for alloca. So we can't eliminate
3494 the frame pointer in that case. At some point,
3495 we should improve this by emitting the
3496 sp-adjusting insns for this case. */
3497 || (current_function_calls_alloca
3498 && EXIT_IGNORE_STACK)
3500 || FRAME_POINTER_REQUIRED);
3504 #ifdef ELIMINABLE_REGS
3505 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3506 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3508 ep->from = ep1->from;
3510 ep->can_eliminate = ep->can_eliminate_previous
3511 = (CAN_ELIMINATE (ep->from, ep->to)
3512 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3515 reg_eliminate[0].from = reg_eliminate_1[0].from;
3516 reg_eliminate[0].to = reg_eliminate_1[0].to;
3517 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3518 = ! frame_pointer_needed;
3521 /* Count the number of eliminable registers and build the FROM and TO
3522 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3523 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3524 We depend on this. */
3525 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3527 num_eliminable += ep->can_eliminate;
3528 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3529 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3533 /* Kick all pseudos out of hard register REGNO.
3535 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3536 because we found we can't eliminate some register. In the case, no pseudos
3537 are allowed to be in the register, even if they are only in a block that
3538 doesn't require spill registers, unlike the case when we are spilling this
3539 hard reg to produce another spill register.
3541 Return nonzero if any pseudos needed to be kicked out. */
3544 spill_hard_reg (regno, cant_eliminate)
3552 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3553 regs_ever_live[regno] = 1;
3556 /* Spill every pseudo reg that was allocated to this reg
3557 or to something that overlaps this reg. */
3559 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3560 if (reg_renumber[i] >= 0
3561 && (unsigned int) reg_renumber[i] <= regno
3562 && ((unsigned int) reg_renumber[i]
3563 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3564 PSEUDO_REGNO_MODE (i))
3566 SET_REGNO_REG_SET (&spilled_pseudos, i);
3569 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3570 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3573 ior_hard_reg_set (set1, set2)
3574 HARD_REG_SET *set1, *set2;
3576 IOR_HARD_REG_SET (*set1, *set2);
3579 /* After find_reload_regs has been run for all insn that need reloads,
3580 and/or spill_hard_regs was called, this function is used to actually
3581 spill pseudo registers and try to reallocate them. It also sets up the
3582 spill_regs array for use by choose_reload_regs. */
3585 finish_spills (global)
3588 struct insn_chain *chain;
3589 int something_changed = 0;
3592 /* Build the spill_regs array for the function. */
3593 /* If there are some registers still to eliminate and one of the spill regs
3594 wasn't ever used before, additional stack space may have to be
3595 allocated to store this register. Thus, we may have changed the offset
3596 between the stack and frame pointers, so mark that something has changed.
3598 One might think that we need only set VAL to 1 if this is a call-used
3599 register. However, the set of registers that must be saved by the
3600 prologue is not identical to the call-used set. For example, the
3601 register used by the call insn for the return PC is a call-used register,
3602 but must be saved by the prologue. */
3605 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3606 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3608 spill_reg_order[i] = n_spills;
3609 spill_regs[n_spills++] = i;
3610 if (num_eliminable && ! regs_ever_live[i])
3611 something_changed = 1;
3612 regs_ever_live[i] = 1;
3615 spill_reg_order[i] = -1;
3617 EXECUTE_IF_SET_IN_REG_SET
3618 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3620 /* Record the current hard register the pseudo is allocated to in
3621 pseudo_previous_regs so we avoid reallocating it to the same
3622 hard reg in a later pass. */
3623 if (reg_renumber[i] < 0)
3626 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3627 /* Mark it as no longer having a hard register home. */
3628 reg_renumber[i] = -1;
3629 /* We will need to scan everything again. */
3630 something_changed = 1;
3633 /* Retry global register allocation if possible. */
3636 memset ((char *) pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3637 /* For every insn that needs reloads, set the registers used as spill
3638 regs in pseudo_forbidden_regs for every pseudo live across the
3640 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3642 EXECUTE_IF_SET_IN_REG_SET
3643 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3645 ior_hard_reg_set (pseudo_forbidden_regs + i,
3646 &chain->used_spill_regs);
3648 EXECUTE_IF_SET_IN_REG_SET
3649 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3651 ior_hard_reg_set (pseudo_forbidden_regs + i,
3652 &chain->used_spill_regs);
3656 /* Retry allocating the spilled pseudos. For each reg, merge the
3657 various reg sets that indicate which hard regs can't be used,
3658 and call retry_global_alloc.
3659 We change spill_pseudos here to only contain pseudos that did not
3660 get a new hard register. */
3661 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3662 if (reg_old_renumber[i] != reg_renumber[i])
3664 HARD_REG_SET forbidden;
3665 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3666 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3667 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3668 retry_global_alloc (i, forbidden);
3669 if (reg_renumber[i] >= 0)
3670 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3674 /* Fix up the register information in the insn chain.
3675 This involves deleting those of the spilled pseudos which did not get
3676 a new hard register home from the live_{before,after} sets. */
3677 for (chain = reload_insn_chain; chain; chain = chain->next)
3679 HARD_REG_SET used_by_pseudos;
3680 HARD_REG_SET used_by_pseudos2;
3682 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3683 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3685 /* Mark any unallocated hard regs as available for spills. That
3686 makes inheritance work somewhat better. */
3687 if (chain->need_reload)
3689 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3690 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3691 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3693 /* Save the old value for the sanity test below. */
3694 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3696 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3697 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3698 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3699 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3701 /* Make sure we only enlarge the set. */
3702 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3708 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3709 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3711 int regno = reg_renumber[i];
3712 if (reg_old_renumber[i] == regno)
3715 alter_reg (i, reg_old_renumber[i]);
3716 reg_old_renumber[i] = regno;
3720 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3722 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3723 i, reg_renumber[i]);
3727 return something_changed;
3730 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3731 Also mark any hard registers used to store user variables as
3732 forbidden from being used for spill registers. */
3735 scan_paradoxical_subregs (x)
3739 register const char *fmt;
3740 register enum rtx_code code = GET_CODE (x);
3746 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3747 && REG_USERVAR_P (x))
3748 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3764 if (GET_CODE (SUBREG_REG (x)) == REG
3765 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3766 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3767 = GET_MODE_SIZE (GET_MODE (x));
3774 fmt = GET_RTX_FORMAT (code);
3775 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3778 scan_paradoxical_subregs (XEXP (x, i));
3779 else if (fmt[i] == 'E')
3782 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3783 scan_paradoxical_subregs (XVECEXP (x, i, j));
3788 /* Reload pseudo-registers into hard regs around each insn as needed.
3789 Additional register load insns are output before the insn that needs it
3790 and perhaps store insns after insns that modify the reloaded pseudo reg.
3792 reg_last_reload_reg and reg_reloaded_contents keep track of
3793 which registers are already available in reload registers.
3794 We update these for the reloads that we perform,
3795 as the insns are scanned. */
3798 reload_as_needed (live_known)
3801 struct insn_chain *chain;
3802 #if defined (AUTO_INC_DEC)
3807 memset ((char *) spill_reg_rtx, 0, sizeof spill_reg_rtx);
3808 memset ((char *) spill_reg_store, 0, sizeof spill_reg_store);
3809 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3810 reg_has_output_reload = (char *) xmalloc (max_regno);
3811 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3813 set_initial_elim_offsets ();
3815 for (chain = reload_insn_chain; chain; chain = chain->next)
3818 rtx insn = chain->insn;
3819 rtx old_next = NEXT_INSN (insn);
3821 /* If we pass a label, copy the offsets from the label information
3822 into the current offsets of each elimination. */
3823 if (GET_CODE (insn) == CODE_LABEL)
3824 set_offsets_for_label (insn);
3826 else if (INSN_P (insn))
3828 rtx oldpat = PATTERN (insn);
3830 /* If this is a USE and CLOBBER of a MEM, ensure that any
3831 references to eliminable registers have been removed. */
3833 if ((GET_CODE (PATTERN (insn)) == USE
3834 || GET_CODE (PATTERN (insn)) == CLOBBER)
3835 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3836 XEXP (XEXP (PATTERN (insn), 0), 0)
3837 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3838 GET_MODE (XEXP (PATTERN (insn), 0)),
3841 /* If we need to do register elimination processing, do so.
3842 This might delete the insn, in which case we are done. */
3843 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3845 eliminate_regs_in_insn (insn, 1);
3846 if (GET_CODE (insn) == NOTE)
3848 update_eliminable_offsets ();
3853 /* If need_elim is nonzero but need_reload is zero, one might think
3854 that we could simply set n_reloads to 0. However, find_reloads
3855 could have done some manipulation of the insn (such as swapping
3856 commutative operands), and these manipulations are lost during
3857 the first pass for every insn that needs register elimination.
3858 So the actions of find_reloads must be redone here. */
3860 if (! chain->need_elim && ! chain->need_reload
3861 && ! chain->need_operand_change)
3863 /* First find the pseudo regs that must be reloaded for this insn.
3864 This info is returned in the tables reload_... (see reload.h).
3865 Also modify the body of INSN by substituting RELOAD
3866 rtx's for those pseudo regs. */
3869 memset (reg_has_output_reload, 0, max_regno);
3870 CLEAR_HARD_REG_SET (reg_is_output_reload);
3872 find_reloads (insn, 1, spill_indirect_levels, live_known,
3878 rtx next = NEXT_INSN (insn);
3881 prev = PREV_INSN (insn);
3883 /* Now compute which reload regs to reload them into. Perhaps
3884 reusing reload regs from previous insns, or else output
3885 load insns to reload them. Maybe output store insns too.
3886 Record the choices of reload reg in reload_reg_rtx. */
3887 choose_reload_regs (chain);
3889 /* Merge any reloads that we didn't combine for fear of
3890 increasing the number of spill registers needed but now
3891 discover can be safely merged. */
3892 if (SMALL_REGISTER_CLASSES)
3893 merge_assigned_reloads (insn);
3895 /* Generate the insns to reload operands into or out of
3896 their reload regs. */
3897 emit_reload_insns (chain);
3899 /* Substitute the chosen reload regs from reload_reg_rtx
3900 into the insn's body (or perhaps into the bodies of other
3901 load and store insn that we just made for reloading
3902 and that we moved the structure into). */
3903 subst_reloads (insn);
3905 /* If this was an ASM, make sure that all the reload insns
3906 we have generated are valid. If not, give an error
3909 if (asm_noperands (PATTERN (insn)) >= 0)
3910 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3911 if (p != insn && INSN_P (p)
3912 && (recog_memoized (p) < 0
3913 || (extract_insn (p), ! constrain_operands (1))))
3915 error_for_asm (insn,
3916 "`asm' operand requires impossible reload");
3918 NOTE_SOURCE_FILE (p) = 0;
3919 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
3923 if (num_eliminable && chain->need_elim)
3924 update_eliminable_offsets ();
3926 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3927 is no longer validly lying around to save a future reload.
3928 Note that this does not detect pseudos that were reloaded
3929 for this insn in order to be stored in
3930 (obeying register constraints). That is correct; such reload
3931 registers ARE still valid. */
3932 note_stores (oldpat, forget_old_reloads_1, NULL);
3934 /* There may have been CLOBBER insns placed after INSN. So scan
3935 between INSN and NEXT and use them to forget old reloads. */
3936 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3937 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3938 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3941 /* Likewise for regs altered by auto-increment in this insn.
3942 REG_INC notes have been changed by reloading:
3943 find_reloads_address_1 records substitutions for them,
3944 which have been performed by subst_reloads above. */
3945 for (i = n_reloads - 1; i >= 0; i--)
3947 rtx in_reg = rld[i].in_reg;
3950 enum rtx_code code = GET_CODE (in_reg);
3951 /* PRE_INC / PRE_DEC will have the reload register ending up
3952 with the same value as the stack slot, but that doesn't
3953 hold true for POST_INC / POST_DEC. Either we have to
3954 convert the memory access to a true POST_INC / POST_DEC,
3955 or we can't use the reload register for inheritance. */
3956 if ((code == POST_INC || code == POST_DEC)
3957 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3958 REGNO (rld[i].reg_rtx))
3959 /* Make sure it is the inc/dec pseudo, and not
3960 some other (e.g. output operand) pseudo. */
3961 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3962 == REGNO (XEXP (in_reg, 0))))
3965 rtx reload_reg = rld[i].reg_rtx;
3966 enum machine_mode mode = GET_MODE (reload_reg);
3970 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3972 /* We really want to ignore REG_INC notes here, so
3973 use PATTERN (p) as argument to reg_set_p . */
3974 if (reg_set_p (reload_reg, PATTERN (p)))
3976 n = count_occurrences (PATTERN (p), reload_reg, 0);
3981 n = validate_replace_rtx (reload_reg,
3982 gen_rtx (code, mode,
3986 /* We must also verify that the constraints
3987 are met after the replacement. */
3990 n = constrain_operands (1);
3994 /* If the constraints were not met, then
3995 undo the replacement. */
3998 validate_replace_rtx (gen_rtx (code, mode,
4010 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4012 /* Mark this as having an output reload so that the
4013 REG_INC processing code below won't invalidate
4014 the reload for inheritance. */
4015 SET_HARD_REG_BIT (reg_is_output_reload,
4016 REGNO (reload_reg));
4017 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4020 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4023 else if ((code == PRE_INC || code == PRE_DEC)
4024 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4025 REGNO (rld[i].reg_rtx))
4026 /* Make sure it is the inc/dec pseudo, and not
4027 some other (e.g. output operand) pseudo. */
4028 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4029 == REGNO (XEXP (in_reg, 0))))
4031 SET_HARD_REG_BIT (reg_is_output_reload,
4032 REGNO (rld[i].reg_rtx));
4033 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4037 /* If a pseudo that got a hard register is auto-incremented,
4038 we must purge records of copying it into pseudos without
4040 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4041 if (REG_NOTE_KIND (x) == REG_INC)
4043 /* See if this pseudo reg was reloaded in this insn.
4044 If so, its last-reload info is still valid
4045 because it is based on this insn's reload. */
4046 for (i = 0; i < n_reloads; i++)
4047 if (rld[i].out == XEXP (x, 0))
4051 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4055 /* A reload reg's contents are unknown after a label. */
4056 if (GET_CODE (insn) == CODE_LABEL)
4057 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4059 /* Don't assume a reload reg is still good after a call insn
4060 if it is a call-used reg. */
4061 else if (GET_CODE (insn) == CALL_INSN)
4062 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
4066 free (reg_last_reload_reg);
4067 free (reg_has_output_reload);
4070 /* Discard all record of any value reloaded from X,
4071 or reloaded in X from someplace else;
4072 unless X is an output reload reg of the current insn.
4074 X may be a hard reg (the reload reg)
4075 or it may be a pseudo reg that was reloaded from. */
4078 forget_old_reloads_1 (x, ignored, data)
4080 rtx ignored ATTRIBUTE_UNUSED;
4081 void *data ATTRIBUTE_UNUSED;
4087 /* note_stores does give us subregs of hard regs,
4088 subreg_regno_offset will abort if it is not a hard reg. */
4089 while (GET_CODE (x) == SUBREG)
4091 offset += subreg_regno_offset (REGNO (SUBREG_REG (x)),
4092 GET_MODE (SUBREG_REG (x)),
4098 if (GET_CODE (x) != REG)
4101 regno = REGNO (x) + offset;
4103 if (regno >= FIRST_PSEUDO_REGISTER)
4109 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4110 /* Storing into a spilled-reg invalidates its contents.
4111 This can happen if a block-local pseudo is allocated to that reg
4112 and it wasn't spilled because this block's total need is 0.
4113 Then some insn might have an optional reload and use this reg. */
4114 for (i = 0; i < nr; i++)
4115 /* But don't do this if the reg actually serves as an output
4116 reload reg in the current instruction. */
4118 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4120 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4121 spill_reg_store[regno + i] = 0;
4125 /* Since value of X has changed,
4126 forget any value previously copied from it. */
4129 /* But don't forget a copy if this is the output reload
4130 that establishes the copy's validity. */
4131 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4132 reg_last_reload_reg[regno + nr] = 0;
4135 /* The following HARD_REG_SETs indicate when each hard register is
4136 used for a reload of various parts of the current insn. */
4138 /* If reg is unavailable for all reloads. */
4139 static HARD_REG_SET reload_reg_unavailable;
4140 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4141 static HARD_REG_SET reload_reg_used;
4142 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4143 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4144 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4145 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4146 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4147 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4148 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4149 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4150 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4151 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4152 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4153 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4154 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4155 static HARD_REG_SET reload_reg_used_in_op_addr;
4156 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4157 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4158 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4159 static HARD_REG_SET reload_reg_used_in_insn;
4160 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4161 static HARD_REG_SET reload_reg_used_in_other_addr;
4163 /* If reg is in use as a reload reg for any sort of reload. */
4164 static HARD_REG_SET reload_reg_used_at_all;
4166 /* If reg is use as an inherited reload. We just mark the first register
4168 static HARD_REG_SET reload_reg_used_for_inherit;
4170 /* Records which hard regs are used in any way, either as explicit use or
4171 by being allocated to a pseudo during any point of the current insn. */
4172 static HARD_REG_SET reg_used_in_insn;
4174 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4175 TYPE. MODE is used to indicate how many consecutive regs are
4179 mark_reload_reg_in_use (regno, opnum, type, mode)
4182 enum reload_type type;
4183 enum machine_mode mode;
4185 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4188 for (i = regno; i < nregs + regno; i++)
4193 SET_HARD_REG_BIT (reload_reg_used, i);
4196 case RELOAD_FOR_INPUT_ADDRESS:
4197 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4200 case RELOAD_FOR_INPADDR_ADDRESS:
4201 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4204 case RELOAD_FOR_OUTPUT_ADDRESS:
4205 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4208 case RELOAD_FOR_OUTADDR_ADDRESS:
4209 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4212 case RELOAD_FOR_OPERAND_ADDRESS:
4213 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4216 case RELOAD_FOR_OPADDR_ADDR:
4217 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4220 case RELOAD_FOR_OTHER_ADDRESS:
4221 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4224 case RELOAD_FOR_INPUT:
4225 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4228 case RELOAD_FOR_OUTPUT:
4229 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4232 case RELOAD_FOR_INSN:
4233 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4237 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4241 /* Similarly, but show REGNO is no longer in use for a reload. */
4244 clear_reload_reg_in_use (regno, opnum, type, mode)
4247 enum reload_type type;
4248 enum machine_mode mode;
4250 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4251 unsigned int start_regno, end_regno, r;
4253 /* A complication is that for some reload types, inheritance might
4254 allow multiple reloads of the same types to share a reload register.
4255 We set check_opnum if we have to check only reloads with the same
4256 operand number, and check_any if we have to check all reloads. */
4257 int check_opnum = 0;
4259 HARD_REG_SET *used_in_set;
4264 used_in_set = &reload_reg_used;
4267 case RELOAD_FOR_INPUT_ADDRESS:
4268 used_in_set = &reload_reg_used_in_input_addr[opnum];
4271 case RELOAD_FOR_INPADDR_ADDRESS:
4273 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4276 case RELOAD_FOR_OUTPUT_ADDRESS:
4277 used_in_set = &reload_reg_used_in_output_addr[opnum];
4280 case RELOAD_FOR_OUTADDR_ADDRESS:
4282 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4285 case RELOAD_FOR_OPERAND_ADDRESS:
4286 used_in_set = &reload_reg_used_in_op_addr;
4289 case RELOAD_FOR_OPADDR_ADDR:
4291 used_in_set = &reload_reg_used_in_op_addr_reload;
4294 case RELOAD_FOR_OTHER_ADDRESS:
4295 used_in_set = &reload_reg_used_in_other_addr;
4299 case RELOAD_FOR_INPUT:
4300 used_in_set = &reload_reg_used_in_input[opnum];
4303 case RELOAD_FOR_OUTPUT:
4304 used_in_set = &reload_reg_used_in_output[opnum];
4307 case RELOAD_FOR_INSN:
4308 used_in_set = &reload_reg_used_in_insn;
4313 /* We resolve conflicts with remaining reloads of the same type by
4314 excluding the intervals of of reload registers by them from the
4315 interval of freed reload registers. Since we only keep track of
4316 one set of interval bounds, we might have to exclude somewhat
4317 more then what would be necessary if we used a HARD_REG_SET here.
4318 But this should only happen very infrequently, so there should
4319 be no reason to worry about it. */
4321 start_regno = regno;
4322 end_regno = regno + nregs;
4323 if (check_opnum || check_any)
4325 for (i = n_reloads - 1; i >= 0; i--)
4327 if (rld[i].when_needed == type
4328 && (check_any || rld[i].opnum == opnum)
4331 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4332 unsigned int conflict_end
4334 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4336 /* If there is an overlap with the first to-be-freed register,
4337 adjust the interval start. */
4338 if (conflict_start <= start_regno && conflict_end > start_regno)
4339 start_regno = conflict_end;
4340 /* Otherwise, if there is a conflict with one of the other
4341 to-be-freed registers, adjust the interval end. */
4342 if (conflict_start > start_regno && conflict_start < end_regno)
4343 end_regno = conflict_start;
4348 for (r = start_regno; r < end_regno; r++)
4349 CLEAR_HARD_REG_BIT (*used_in_set, r);
4352 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4353 specified by OPNUM and TYPE. */
4356 reload_reg_free_p (regno, opnum, type)
4359 enum reload_type type;
4363 /* In use for a RELOAD_OTHER means it's not available for anything. */
4364 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4365 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4371 /* In use for anything means we can't use it for RELOAD_OTHER. */
4372 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4373 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4374 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4377 for (i = 0; i < reload_n_operands; i++)
4378 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4379 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4380 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4381 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4382 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4383 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4388 case RELOAD_FOR_INPUT:
4389 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4390 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4393 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4396 /* If it is used for some other input, can't use it. */
4397 for (i = 0; i < reload_n_operands; i++)
4398 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4401 /* If it is used in a later operand's address, can't use it. */
4402 for (i = opnum + 1; i < reload_n_operands; i++)
4403 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4404 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4409 case RELOAD_FOR_INPUT_ADDRESS:
4410 /* Can't use a register if it is used for an input address for this
4411 operand or used as an input in an earlier one. */
4412 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4413 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4416 for (i = 0; i < opnum; i++)
4417 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4422 case RELOAD_FOR_INPADDR_ADDRESS:
4423 /* Can't use a register if it is used for an input address
4424 for this operand or used as an input in an earlier
4426 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4429 for (i = 0; i < opnum; i++)
4430 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4435 case RELOAD_FOR_OUTPUT_ADDRESS:
4436 /* Can't use a register if it is used for an output address for this
4437 operand or used as an output in this or a later operand. */
4438 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4441 for (i = opnum; i < reload_n_operands; i++)
4442 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4447 case RELOAD_FOR_OUTADDR_ADDRESS:
4448 /* Can't use a register if it is used for an output address
4449 for this operand or used as an output in this or a
4451 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4454 for (i = opnum; i < reload_n_operands; i++)
4455 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4460 case RELOAD_FOR_OPERAND_ADDRESS:
4461 for (i = 0; i < reload_n_operands; i++)
4462 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4465 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4466 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4468 case RELOAD_FOR_OPADDR_ADDR:
4469 for (i = 0; i < reload_n_operands; i++)
4470 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4473 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4475 case RELOAD_FOR_OUTPUT:
4476 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4477 outputs, or an operand address for this or an earlier output. */
4478 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4481 for (i = 0; i < reload_n_operands; i++)
4482 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4485 for (i = 0; i <= opnum; i++)
4486 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4487 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4492 case RELOAD_FOR_INSN:
4493 for (i = 0; i < reload_n_operands; i++)
4494 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4495 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4498 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4499 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4501 case RELOAD_FOR_OTHER_ADDRESS:
4502 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4507 /* Return 1 if the value in reload reg REGNO, as used by a reload
4508 needed for the part of the insn specified by OPNUM and TYPE,
4509 is still available in REGNO at the end of the insn.
4511 We can assume that the reload reg was already tested for availability
4512 at the time it is needed, and we should not check this again,
4513 in case the reg has already been marked in use. */
4516 reload_reg_reaches_end_p (regno, opnum, type)
4519 enum reload_type type;
4526 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4527 its value must reach the end. */
4530 /* If this use is for part of the insn,
4531 its value reaches if no subsequent part uses the same register.
4532 Just like the above function, don't try to do this with lots
4535 case RELOAD_FOR_OTHER_ADDRESS:
4536 /* Here we check for everything else, since these don't conflict
4537 with anything else and everything comes later. */
4539 for (i = 0; i < reload_n_operands; i++)
4540 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4541 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4542 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4543 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4544 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4545 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4548 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4549 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4550 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4552 case RELOAD_FOR_INPUT_ADDRESS:
4553 case RELOAD_FOR_INPADDR_ADDRESS:
4554 /* Similar, except that we check only for this and subsequent inputs
4555 and the address of only subsequent inputs and we do not need
4556 to check for RELOAD_OTHER objects since they are known not to
4559 for (i = opnum; i < reload_n_operands; i++)
4560 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4563 for (i = opnum + 1; i < reload_n_operands; i++)
4564 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4565 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4568 for (i = 0; i < reload_n_operands; i++)
4569 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4570 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4571 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4574 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4577 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4578 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4579 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4581 case RELOAD_FOR_INPUT:
4582 /* Similar to input address, except we start at the next operand for
4583 both input and input address and we do not check for
4584 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4587 for (i = opnum + 1; i < reload_n_operands; i++)
4588 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4589 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4590 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4593 /* ... fall through ... */
4595 case RELOAD_FOR_OPERAND_ADDRESS:
4596 /* Check outputs and their addresses. */
4598 for (i = 0; i < reload_n_operands; i++)
4599 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4600 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4601 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4604 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4606 case RELOAD_FOR_OPADDR_ADDR:
4607 for (i = 0; i < reload_n_operands; i++)
4608 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4609 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4610 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4613 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4614 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4615 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4617 case RELOAD_FOR_INSN:
4618 /* These conflict with other outputs with RELOAD_OTHER. So
4619 we need only check for output addresses. */
4623 /* ... fall through ... */
4625 case RELOAD_FOR_OUTPUT:
4626 case RELOAD_FOR_OUTPUT_ADDRESS:
4627 case RELOAD_FOR_OUTADDR_ADDRESS:
4628 /* We already know these can't conflict with a later output. So the
4629 only thing to check are later output addresses. */
4630 for (i = opnum + 1; i < reload_n_operands; i++)
4631 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4632 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4641 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4644 This function uses the same algorithm as reload_reg_free_p above. */
4647 reloads_conflict (r1, r2)
4650 enum reload_type r1_type = rld[r1].when_needed;
4651 enum reload_type r2_type = rld[r2].when_needed;
4652 int r1_opnum = rld[r1].opnum;
4653 int r2_opnum = rld[r2].opnum;
4655 /* RELOAD_OTHER conflicts with everything. */
4656 if (r2_type == RELOAD_OTHER)
4659 /* Otherwise, check conflicts differently for each type. */
4663 case RELOAD_FOR_INPUT:
4664 return (r2_type == RELOAD_FOR_INSN
4665 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4666 || r2_type == RELOAD_FOR_OPADDR_ADDR
4667 || r2_type == RELOAD_FOR_INPUT
4668 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4669 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4670 && r2_opnum > r1_opnum));
4672 case RELOAD_FOR_INPUT_ADDRESS:
4673 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4674 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4676 case RELOAD_FOR_INPADDR_ADDRESS:
4677 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4678 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4680 case RELOAD_FOR_OUTPUT_ADDRESS:
4681 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4682 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4684 case RELOAD_FOR_OUTADDR_ADDRESS:
4685 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4686 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4688 case RELOAD_FOR_OPERAND_ADDRESS:
4689 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4690 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4692 case RELOAD_FOR_OPADDR_ADDR:
4693 return (r2_type == RELOAD_FOR_INPUT
4694 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4696 case RELOAD_FOR_OUTPUT:
4697 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4698 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4699 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4700 && r2_opnum <= r1_opnum));
4702 case RELOAD_FOR_INSN:
4703 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4704 || r2_type == RELOAD_FOR_INSN
4705 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4707 case RELOAD_FOR_OTHER_ADDRESS:
4708 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4718 /* Indexed by reload number, 1 if incoming value
4719 inherited from previous insns. */
4720 char reload_inherited[MAX_RELOADS];
4722 /* For an inherited reload, this is the insn the reload was inherited from,
4723 if we know it. Otherwise, this is 0. */
4724 rtx reload_inheritance_insn[MAX_RELOADS];
4726 /* If non-zero, this is a place to get the value of the reload,
4727 rather than using reload_in. */
4728 rtx reload_override_in[MAX_RELOADS];
4730 /* For each reload, the hard register number of the register used,
4731 or -1 if we did not need a register for this reload. */
4732 int reload_spill_index[MAX_RELOADS];
4734 /* Subroutine of free_for_value_p, used to check a single register.
4735 START_REGNO is the starting regno of the full reload register
4736 (possibly comprising multiple hard registers) that we are considering. */
4739 reload_reg_free_for_value_p (start_regno, regno, opnum, type, value, out,
4740 reloadnum, ignore_address_reloads)
4741 int start_regno, regno;
4743 enum reload_type type;
4746 int ignore_address_reloads;
4749 /* Set if we see an input reload that must not share its reload register
4750 with any new earlyclobber, but might otherwise share the reload
4751 register with an output or input-output reload. */
4752 int check_earlyclobber = 0;
4756 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4759 if (out == const0_rtx)
4765 /* We use some pseudo 'time' value to check if the lifetimes of the
4766 new register use would overlap with the one of a previous reload
4767 that is not read-only or uses a different value.
4768 The 'time' used doesn't have to be linear in any shape or form, just
4770 Some reload types use different 'buckets' for each operand.
4771 So there are MAX_RECOG_OPERANDS different time values for each
4773 We compute TIME1 as the time when the register for the prospective
4774 new reload ceases to be live, and TIME2 for each existing
4775 reload as the time when that the reload register of that reload
4777 Where there is little to be gained by exact lifetime calculations,
4778 we just make conservative assumptions, i.e. a longer lifetime;
4779 this is done in the 'default:' cases. */
4782 case RELOAD_FOR_OTHER_ADDRESS:
4783 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4784 time1 = copy ? 0 : 1;
4787 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4789 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4790 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4791 respectively, to the time values for these, we get distinct time
4792 values. To get distinct time values for each operand, we have to
4793 multiply opnum by at least three. We round that up to four because
4794 multiply by four is often cheaper. */
4795 case RELOAD_FOR_INPADDR_ADDRESS:
4796 time1 = opnum * 4 + 2;
4798 case RELOAD_FOR_INPUT_ADDRESS:
4799 time1 = opnum * 4 + 3;
4801 case RELOAD_FOR_INPUT:
4802 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4803 executes (inclusive). */
4804 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4806 case RELOAD_FOR_OPADDR_ADDR:
4808 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4809 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4811 case RELOAD_FOR_OPERAND_ADDRESS:
4812 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4814 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4816 case RELOAD_FOR_OUTADDR_ADDRESS:
4817 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4819 case RELOAD_FOR_OUTPUT_ADDRESS:
4820 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4823 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4826 for (i = 0; i < n_reloads; i++)
4828 rtx reg = rld[i].reg_rtx;
4829 if (reg && GET_CODE (reg) == REG
4830 && ((unsigned) regno - true_regnum (reg)
4831 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
4834 rtx other_input = rld[i].in;
4836 /* If the other reload loads the same input value, that
4837 will not cause a conflict only if it's loading it into
4838 the same register. */
4839 if (true_regnum (reg) != start_regno)
4840 other_input = NULL_RTX;
4841 if (! other_input || ! rtx_equal_p (other_input, value)
4842 || rld[i].out || out)
4845 switch (rld[i].when_needed)
4847 case RELOAD_FOR_OTHER_ADDRESS:
4850 case RELOAD_FOR_INPADDR_ADDRESS:
4851 /* find_reloads makes sure that a
4852 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4853 by at most one - the first -
4854 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4855 address reload is inherited, the address address reload
4856 goes away, so we can ignore this conflict. */
4857 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4858 && ignore_address_reloads
4859 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4860 Then the address address is still needed to store
4861 back the new address. */
4862 && ! rld[reloadnum].out)
4864 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4865 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4867 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4868 && ignore_address_reloads
4869 /* Unless we are reloading an auto_inc expression. */
4870 && ! rld[reloadnum].out)
4872 time2 = rld[i].opnum * 4 + 2;
4874 case RELOAD_FOR_INPUT_ADDRESS:
4875 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4876 && ignore_address_reloads
4877 && ! rld[reloadnum].out)
4879 time2 = rld[i].opnum * 4 + 3;
4881 case RELOAD_FOR_INPUT:
4882 time2 = rld[i].opnum * 4 + 4;
4883 check_earlyclobber = 1;
4885 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4886 == MAX_RECOG_OPERAND * 4 */
4887 case RELOAD_FOR_OPADDR_ADDR:
4888 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4889 && ignore_address_reloads
4890 && ! rld[reloadnum].out)
4892 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4894 case RELOAD_FOR_OPERAND_ADDRESS:
4895 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4896 check_earlyclobber = 1;
4898 case RELOAD_FOR_INSN:
4899 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4901 case RELOAD_FOR_OUTPUT:
4902 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4903 instruction is executed. */
4904 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4906 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4907 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4909 case RELOAD_FOR_OUTADDR_ADDRESS:
4910 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4911 && ignore_address_reloads
4912 && ! rld[reloadnum].out)
4914 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4916 case RELOAD_FOR_OUTPUT_ADDRESS:
4917 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4920 /* If there is no conflict in the input part, handle this
4921 like an output reload. */
4922 if (! rld[i].in || rtx_equal_p (other_input, value))
4924 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4925 /* Earlyclobbered outputs must conflict with inputs. */
4926 if (earlyclobber_operand_p (rld[i].out))
4927 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4932 /* RELOAD_OTHER might be live beyond instruction execution,
4933 but this is not obvious when we set time2 = 1. So check
4934 here if there might be a problem with the new reload
4935 clobbering the register used by the RELOAD_OTHER. */
4943 && (! rld[i].in || rld[i].out
4944 || ! rtx_equal_p (other_input, value)))
4945 || (out && rld[reloadnum].out_reg
4946 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4952 /* Earlyclobbered outputs must conflict with inputs. */
4953 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4959 /* Return 1 if the value in reload reg REGNO, as used by a reload
4960 needed for the part of the insn specified by OPNUM and TYPE,
4961 may be used to load VALUE into it.
4963 MODE is the mode in which the register is used, this is needed to
4964 determine how many hard regs to test.
4966 Other read-only reloads with the same value do not conflict
4967 unless OUT is non-zero and these other reloads have to live while
4968 output reloads live.
4969 If OUT is CONST0_RTX, this is a special case: it means that the
4970 test should not be for using register REGNO as reload register, but
4971 for copying from register REGNO into the reload register.
4973 RELOADNUM is the number of the reload we want to load this value for;
4974 a reload does not conflict with itself.
4976 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4977 reloads that load an address for the very reload we are considering.
4979 The caller has to make sure that there is no conflict with the return
4983 free_for_value_p (regno, mode, opnum, type, value, out, reloadnum,
4984 ignore_address_reloads)
4986 enum machine_mode mode;
4988 enum reload_type type;
4991 int ignore_address_reloads;
4993 int nregs = HARD_REGNO_NREGS (regno, mode);
4995 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
4996 value, out, reloadnum,
4997 ignore_address_reloads))
5002 /* Determine whether the reload reg X overlaps any rtx'es used for
5003 overriding inheritance. Return nonzero if so. */
5006 conflicts_with_override (x)
5010 for (i = 0; i < n_reloads; i++)
5011 if (reload_override_in[i]
5012 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5017 /* Give an error message saying we failed to find a reload for INSN,
5018 and clear out reload R. */
5020 failed_reload (insn, r)
5024 if (asm_noperands (PATTERN (insn)) < 0)
5025 /* It's the compiler's fault. */
5026 fatal_insn ("Could not find a spill register", insn);
5028 /* It's the user's fault; the operand's mode and constraint
5029 don't match. Disable this reload so we don't crash in final. */
5030 error_for_asm (insn,
5031 "`asm' operand constraint incompatible with operand size");
5035 rld[r].optional = 1;
5036 rld[r].secondary_p = 1;
5039 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5040 for reload R. If it's valid, get an rtx for it. Return nonzero if
5043 set_reload_reg (i, r)
5047 rtx reg = spill_reg_rtx[i];
5049 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5050 spill_reg_rtx[i] = reg
5051 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5053 regno = true_regnum (reg);
5055 /* Detect when the reload reg can't hold the reload mode.
5056 This used to be one `if', but Sequent compiler can't handle that. */
5057 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5059 enum machine_mode test_mode = VOIDmode;
5061 test_mode = GET_MODE (rld[r].in);
5062 /* If rld[r].in has VOIDmode, it means we will load it
5063 in whatever mode the reload reg has: to wit, rld[r].mode.
5064 We have already tested that for validity. */
5065 /* Aside from that, we need to test that the expressions
5066 to reload from or into have modes which are valid for this
5067 reload register. Otherwise the reload insns would be invalid. */
5068 if (! (rld[r].in != 0 && test_mode != VOIDmode
5069 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5070 if (! (rld[r].out != 0
5071 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5073 /* The reg is OK. */
5076 /* Mark as in use for this insn the reload regs we use
5078 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5079 rld[r].when_needed, rld[r].mode);
5081 rld[r].reg_rtx = reg;
5082 reload_spill_index[r] = spill_regs[i];
5089 /* Find a spill register to use as a reload register for reload R.
5090 LAST_RELOAD is non-zero if this is the last reload for the insn being
5093 Set rld[R].reg_rtx to the register allocated.
5095 We return 1 if successful, or 0 if we couldn't find a spill reg and
5096 we didn't change anything. */
5099 allocate_reload_reg (chain, r, last_reload)
5100 struct insn_chain *chain ATTRIBUTE_UNUSED;
5106 /* If we put this reload ahead, thinking it is a group,
5107 then insist on finding a group. Otherwise we can grab a
5108 reg that some other reload needs.
5109 (That can happen when we have a 68000 DATA_OR_FP_REG
5110 which is a group of data regs or one fp reg.)
5111 We need not be so restrictive if there are no more reloads
5114 ??? Really it would be nicer to have smarter handling
5115 for that kind of reg class, where a problem like this is normal.
5116 Perhaps those classes should be avoided for reloading
5117 by use of more alternatives. */
5119 int force_group = rld[r].nregs > 1 && ! last_reload;
5121 /* If we want a single register and haven't yet found one,
5122 take any reg in the right class and not in use.
5123 If we want a consecutive group, here is where we look for it.
5125 We use two passes so we can first look for reload regs to
5126 reuse, which are already in use for other reloads in this insn,
5127 and only then use additional registers.
5128 I think that maximizing reuse is needed to make sure we don't
5129 run out of reload regs. Suppose we have three reloads, and
5130 reloads A and B can share regs. These need two regs.
5131 Suppose A and B are given different regs.
5132 That leaves none for C. */
5133 for (pass = 0; pass < 2; pass++)
5135 /* I is the index in spill_regs.
5136 We advance it round-robin between insns to use all spill regs
5137 equally, so that inherited reloads have a chance
5138 of leapfrogging each other. */
5142 for (count = 0; count < n_spills; count++)
5144 int class = (int) rld[r].class;
5150 regnum = spill_regs[i];
5152 if ((reload_reg_free_p (regnum, rld[r].opnum,
5155 /* We check reload_reg_used to make sure we
5156 don't clobber the return register. */
5157 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5158 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5159 rld[r].when_needed, rld[r].in,
5161 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5162 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5163 /* Look first for regs to share, then for unshared. But
5164 don't share regs used for inherited reloads; they are
5165 the ones we want to preserve. */
5167 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5169 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5172 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5173 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5174 (on 68000) got us two FP regs. If NR is 1,
5175 we would reject both of them. */
5178 /* If we need only one reg, we have already won. */
5181 /* But reject a single reg if we demand a group. */
5186 /* Otherwise check that as many consecutive regs as we need
5187 are available here. */
5190 int regno = regnum + nr - 1;
5191 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5192 && spill_reg_order[regno] >= 0
5193 && reload_reg_free_p (regno, rld[r].opnum,
5194 rld[r].when_needed)))
5203 /* If we found something on pass 1, omit pass 2. */
5204 if (count < n_spills)
5208 /* We should have found a spill register by now. */
5209 if (count >= n_spills)
5212 /* I is the index in SPILL_REG_RTX of the reload register we are to
5213 allocate. Get an rtx for it and find its register number. */
5215 return set_reload_reg (i, r);
5218 /* Initialize all the tables needed to allocate reload registers.
5219 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5220 is the array we use to restore the reg_rtx field for every reload. */
5223 choose_reload_regs_init (chain, save_reload_reg_rtx)
5224 struct insn_chain *chain;
5225 rtx *save_reload_reg_rtx;
5229 for (i = 0; i < n_reloads; i++)
5230 rld[i].reg_rtx = save_reload_reg_rtx[i];
5232 memset (reload_inherited, 0, MAX_RELOADS);
5233 memset ((char *) reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5234 memset ((char *) reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5236 CLEAR_HARD_REG_SET (reload_reg_used);
5237 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5238 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5239 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5240 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5241 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5243 CLEAR_HARD_REG_SET (reg_used_in_insn);
5246 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5247 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5248 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5249 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5250 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5251 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5254 for (i = 0; i < reload_n_operands; i++)
5256 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5257 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5258 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5259 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5260 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5261 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5264 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5266 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5268 for (i = 0; i < n_reloads; i++)
5269 /* If we have already decided to use a certain register,
5270 don't use it in another way. */
5272 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5273 rld[i].when_needed, rld[i].mode);
5276 /* Assign hard reg targets for the pseudo-registers we must reload
5277 into hard regs for this insn.
5278 Also output the instructions to copy them in and out of the hard regs.
5280 For machines with register classes, we are responsible for
5281 finding a reload reg in the proper class. */
5284 choose_reload_regs (chain)
5285 struct insn_chain *chain;
5287 rtx insn = chain->insn;
5289 unsigned int max_group_size = 1;
5290 enum reg_class group_class = NO_REGS;
5291 int pass, win, inheritance;
5293 rtx save_reload_reg_rtx[MAX_RELOADS];
5295 /* In order to be certain of getting the registers we need,
5296 we must sort the reloads into order of increasing register class.
5297 Then our grabbing of reload registers will parallel the process
5298 that provided the reload registers.
5300 Also note whether any of the reloads wants a consecutive group of regs.
5301 If so, record the maximum size of the group desired and what
5302 register class contains all the groups needed by this insn. */
5304 for (j = 0; j < n_reloads; j++)
5306 reload_order[j] = j;
5307 reload_spill_index[j] = -1;
5309 if (rld[j].nregs > 1)
5311 max_group_size = MAX (rld[j].nregs, max_group_size);
5313 = reg_class_superunion[(int) rld[j].class][(int)group_class];
5316 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5320 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5322 /* If -O, try first with inheritance, then turning it off.
5323 If not -O, don't do inheritance.
5324 Using inheritance when not optimizing leads to paradoxes
5325 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5326 because one side of the comparison might be inherited. */
5328 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5330 choose_reload_regs_init (chain, save_reload_reg_rtx);
5332 /* Process the reloads in order of preference just found.
5333 Beyond this point, subregs can be found in reload_reg_rtx.
5335 This used to look for an existing reloaded home for all of the
5336 reloads, and only then perform any new reloads. But that could lose
5337 if the reloads were done out of reg-class order because a later
5338 reload with a looser constraint might have an old home in a register
5339 needed by an earlier reload with a tighter constraint.
5341 To solve this, we make two passes over the reloads, in the order
5342 described above. In the first pass we try to inherit a reload
5343 from a previous insn. If there is a later reload that needs a
5344 class that is a proper subset of the class being processed, we must
5345 also allocate a spill register during the first pass.
5347 Then make a second pass over the reloads to allocate any reloads
5348 that haven't been given registers yet. */
5350 for (j = 0; j < n_reloads; j++)
5352 register int r = reload_order[j];
5353 rtx search_equiv = NULL_RTX;
5355 /* Ignore reloads that got marked inoperative. */
5356 if (rld[r].out == 0 && rld[r].in == 0
5357 && ! rld[r].secondary_p)
5360 /* If find_reloads chose to use reload_in or reload_out as a reload
5361 register, we don't need to chose one. Otherwise, try even if it
5362 found one since we might save an insn if we find the value lying
5364 Try also when reload_in is a pseudo without a hard reg. */
5365 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5366 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5367 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5368 && GET_CODE (rld[r].in) != MEM
5369 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5372 #if 0 /* No longer needed for correct operation.
5373 It might give better code, or might not; worth an experiment? */
5374 /* If this is an optional reload, we can't inherit from earlier insns
5375 until we are sure that any non-optional reloads have been allocated.
5376 The following code takes advantage of the fact that optional reloads
5377 are at the end of reload_order. */
5378 if (rld[r].optional != 0)
5379 for (i = 0; i < j; i++)
5380 if ((rld[reload_order[i]].out != 0
5381 || rld[reload_order[i]].in != 0
5382 || rld[reload_order[i]].secondary_p)
5383 && ! rld[reload_order[i]].optional
5384 && rld[reload_order[i]].reg_rtx == 0)
5385 allocate_reload_reg (chain, reload_order[i], 0);
5388 /* First see if this pseudo is already available as reloaded
5389 for a previous insn. We cannot try to inherit for reloads
5390 that are smaller than the maximum number of registers needed
5391 for groups unless the register we would allocate cannot be used
5394 We could check here to see if this is a secondary reload for
5395 an object that is already in a register of the desired class.
5396 This would avoid the need for the secondary reload register.
5397 But this is complex because we can't easily determine what
5398 objects might want to be loaded via this reload. So let a
5399 register be allocated here. In `emit_reload_insns' we suppress
5400 one of the loads in the case described above. */
5405 register int regno = -1;
5406 enum machine_mode mode = VOIDmode;
5410 else if (GET_CODE (rld[r].in) == REG)
5412 regno = REGNO (rld[r].in);
5413 mode = GET_MODE (rld[r].in);
5415 else if (GET_CODE (rld[r].in_reg) == REG)
5417 regno = REGNO (rld[r].in_reg);
5418 mode = GET_MODE (rld[r].in_reg);
5420 else if (GET_CODE (rld[r].in_reg) == SUBREG
5421 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5423 byte = SUBREG_BYTE (rld[r].in_reg);
5424 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5425 if (regno < FIRST_PSEUDO_REGISTER)
5426 regno = subreg_regno (rld[r].in_reg);
5427 mode = GET_MODE (rld[r].in_reg);
5430 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5431 || GET_CODE (rld[r].in_reg) == PRE_DEC
5432 || GET_CODE (rld[r].in_reg) == POST_INC
5433 || GET_CODE (rld[r].in_reg) == POST_DEC)
5434 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5436 regno = REGNO (XEXP (rld[r].in_reg, 0));
5437 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5438 rld[r].out = rld[r].in;
5442 /* This won't work, since REGNO can be a pseudo reg number.
5443 Also, it takes much more hair to keep track of all the things
5444 that can invalidate an inherited reload of part of a pseudoreg. */
5445 else if (GET_CODE (rld[r].in) == SUBREG
5446 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5447 regno = subreg_regno (rld[r].in);
5450 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5452 enum reg_class class = rld[r].class, last_class;
5453 rtx last_reg = reg_last_reload_reg[regno];
5454 enum machine_mode need_mode;
5456 i = REGNO (last_reg);
5457 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5458 last_class = REGNO_REG_CLASS (i);
5464 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5465 GET_MODE_CLASS (mode));
5468 #ifdef CLASS_CANNOT_CHANGE_MODE
5470 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], i)
5471 ? ! CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (last_reg),
5473 : (GET_MODE_SIZE (GET_MODE (last_reg))
5474 >= GET_MODE_SIZE (need_mode)))
5476 (GET_MODE_SIZE (GET_MODE (last_reg))
5477 >= GET_MODE_SIZE (need_mode))
5479 && reg_reloaded_contents[i] == regno
5480 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5481 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5482 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5483 /* Even if we can't use this register as a reload
5484 register, we might use it for reload_override_in,
5485 if copying it to the desired class is cheap
5487 || ((REGISTER_MOVE_COST (mode, last_class, class)
5488 < MEMORY_MOVE_COST (mode, class, 1))
5489 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5490 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5494 #ifdef SECONDARY_MEMORY_NEEDED
5495 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5500 && (rld[r].nregs == max_group_size
5501 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5503 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5504 rld[r].when_needed, rld[r].in,
5507 /* If a group is needed, verify that all the subsequent
5508 registers still have their values intact. */
5509 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5512 for (k = 1; k < nr; k++)
5513 if (reg_reloaded_contents[i + k] != regno
5514 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5522 last_reg = (GET_MODE (last_reg) == mode
5523 ? last_reg : gen_rtx_REG (mode, i));
5526 for (k = 0; k < nr; k++)
5527 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5530 /* We found a register that contains the
5531 value we need. If this register is the
5532 same as an `earlyclobber' operand of the
5533 current insn, just mark it as a place to
5534 reload from since we can't use it as the
5535 reload register itself. */
5537 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5538 if (reg_overlap_mentioned_for_reload_p
5539 (reg_last_reload_reg[regno],
5540 reload_earlyclobbers[i1]))
5543 if (i1 != n_earlyclobbers
5544 || ! (free_for_value_p (i, rld[r].mode,
5546 rld[r].when_needed, rld[r].in,
5548 /* Don't use it if we'd clobber a pseudo reg. */
5549 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5551 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5552 /* Don't clobber the frame pointer. */
5553 || (i == HARD_FRAME_POINTER_REGNUM
5555 /* Don't really use the inherited spill reg
5556 if we need it wider than we've got it. */
5557 || (GET_MODE_SIZE (rld[r].mode)
5558 > GET_MODE_SIZE (mode))
5561 /* If find_reloads chose reload_out as reload
5562 register, stay with it - that leaves the
5563 inherited register for subsequent reloads. */
5564 || (rld[r].out && rld[r].reg_rtx
5565 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5567 if (! rld[r].optional)
5569 reload_override_in[r] = last_reg;
5570 reload_inheritance_insn[r]
5571 = reg_reloaded_insn[i];
5577 /* We can use this as a reload reg. */
5578 /* Mark the register as in use for this part of
5580 mark_reload_reg_in_use (i,
5584 rld[r].reg_rtx = last_reg;
5585 reload_inherited[r] = 1;
5586 reload_inheritance_insn[r]
5587 = reg_reloaded_insn[i];
5588 reload_spill_index[r] = i;
5589 for (k = 0; k < nr; k++)
5590 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5598 /* Here's another way to see if the value is already lying around. */
5601 && ! reload_inherited[r]
5603 && (CONSTANT_P (rld[r].in)
5604 || GET_CODE (rld[r].in) == PLUS
5605 || GET_CODE (rld[r].in) == REG
5606 || GET_CODE (rld[r].in) == MEM)
5607 && (rld[r].nregs == max_group_size
5608 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5609 search_equiv = rld[r].in;
5610 /* If this is an output reload from a simple move insn, look
5611 if an equivalence for the input is available. */
5612 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5614 rtx set = single_set (insn);
5617 && rtx_equal_p (rld[r].out, SET_DEST (set))
5618 && CONSTANT_P (SET_SRC (set)))
5619 search_equiv = SET_SRC (set);
5625 = find_equiv_reg (search_equiv, insn, rld[r].class,
5626 -1, NULL, 0, rld[r].mode);
5631 if (GET_CODE (equiv) == REG)
5632 regno = REGNO (equiv);
5633 else if (GET_CODE (equiv) == SUBREG)
5635 /* This must be a SUBREG of a hard register.
5636 Make a new REG since this might be used in an
5637 address and not all machines support SUBREGs
5639 regno = subreg_regno (equiv);
5640 equiv = gen_rtx_REG (rld[r].mode, regno);
5646 /* If we found a spill reg, reject it unless it is free
5647 and of the desired class. */
5649 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5650 && ! free_for_value_p (regno, rld[r].mode,
5651 rld[r].opnum, rld[r].when_needed,
5652 rld[r].in, rld[r].out, r, 1))
5653 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5657 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5660 /* We found a register that contains the value we need.
5661 If this register is the same as an `earlyclobber' operand
5662 of the current insn, just mark it as a place to reload from
5663 since we can't use it as the reload register itself. */
5666 for (i = 0; i < n_earlyclobbers; i++)
5667 if (reg_overlap_mentioned_for_reload_p (equiv,
5668 reload_earlyclobbers[i]))
5670 if (! rld[r].optional)
5671 reload_override_in[r] = equiv;
5676 /* If the equiv register we have found is explicitly clobbered
5677 in the current insn, it depends on the reload type if we
5678 can use it, use it for reload_override_in, or not at all.
5679 In particular, we then can't use EQUIV for a
5680 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5684 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5685 switch (rld[r].when_needed)
5687 case RELOAD_FOR_OTHER_ADDRESS:
5688 case RELOAD_FOR_INPADDR_ADDRESS:
5689 case RELOAD_FOR_INPUT_ADDRESS:
5690 case RELOAD_FOR_OPADDR_ADDR:
5693 case RELOAD_FOR_INPUT:
5694 case RELOAD_FOR_OPERAND_ADDRESS:
5695 if (! rld[r].optional)
5696 reload_override_in[r] = equiv;
5702 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5703 switch (rld[r].when_needed)
5705 case RELOAD_FOR_OTHER_ADDRESS:
5706 case RELOAD_FOR_INPADDR_ADDRESS:
5707 case RELOAD_FOR_INPUT_ADDRESS:
5708 case RELOAD_FOR_OPADDR_ADDR:
5709 case RELOAD_FOR_OPERAND_ADDRESS:
5710 case RELOAD_FOR_INPUT:
5713 if (! rld[r].optional)
5714 reload_override_in[r] = equiv;
5722 /* If we found an equivalent reg, say no code need be generated
5723 to load it, and use it as our reload reg. */
5724 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5726 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5728 rld[r].reg_rtx = equiv;
5729 reload_inherited[r] = 1;
5731 /* If reg_reloaded_valid is not set for this register,
5732 there might be a stale spill_reg_store lying around.
5733 We must clear it, since otherwise emit_reload_insns
5734 might delete the store. */
5735 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5736 spill_reg_store[regno] = NULL_RTX;
5737 /* If any of the hard registers in EQUIV are spill
5738 registers, mark them as in use for this insn. */
5739 for (k = 0; k < nr; k++)
5741 i = spill_reg_order[regno + k];
5744 mark_reload_reg_in_use (regno, rld[r].opnum,
5747 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5754 /* If we found a register to use already, or if this is an optional
5755 reload, we are done. */
5756 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5760 /* No longer needed for correct operation. Might or might
5761 not give better code on the average. Want to experiment? */
5763 /* See if there is a later reload that has a class different from our
5764 class that intersects our class or that requires less register
5765 than our reload. If so, we must allocate a register to this
5766 reload now, since that reload might inherit a previous reload
5767 and take the only available register in our class. Don't do this
5768 for optional reloads since they will force all previous reloads
5769 to be allocated. Also don't do this for reloads that have been
5772 for (i = j + 1; i < n_reloads; i++)
5774 int s = reload_order[i];
5776 if ((rld[s].in == 0 && rld[s].out == 0
5777 && ! rld[s].secondary_p)
5781 if ((rld[s].class != rld[r].class
5782 && reg_classes_intersect_p (rld[r].class,
5784 || rld[s].nregs < rld[r].nregs)
5791 allocate_reload_reg (chain, r, j == n_reloads - 1);
5795 /* Now allocate reload registers for anything non-optional that
5796 didn't get one yet. */
5797 for (j = 0; j < n_reloads; j++)
5799 register int r = reload_order[j];
5801 /* Ignore reloads that got marked inoperative. */
5802 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5805 /* Skip reloads that already have a register allocated or are
5807 if (rld[r].reg_rtx != 0 || rld[r].optional)
5810 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5814 /* If that loop got all the way, we have won. */
5821 /* Loop around and try without any inheritance. */
5826 /* First undo everything done by the failed attempt
5827 to allocate with inheritance. */
5828 choose_reload_regs_init (chain, save_reload_reg_rtx);
5830 /* Some sanity tests to verify that the reloads found in the first
5831 pass are identical to the ones we have now. */
5832 if (chain->n_reloads != n_reloads)
5835 for (i = 0; i < n_reloads; i++)
5837 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5839 if (chain->rld[i].when_needed != rld[i].when_needed)
5841 for (j = 0; j < n_spills; j++)
5842 if (spill_regs[j] == chain->rld[i].regno)
5843 if (! set_reload_reg (j, i))
5844 failed_reload (chain->insn, i);
5848 /* If we thought we could inherit a reload, because it seemed that
5849 nothing else wanted the same reload register earlier in the insn,
5850 verify that assumption, now that all reloads have been assigned.
5851 Likewise for reloads where reload_override_in has been set. */
5853 /* If doing expensive optimizations, do one preliminary pass that doesn't
5854 cancel any inheritance, but removes reloads that have been needed only
5855 for reloads that we know can be inherited. */
5856 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5858 for (j = 0; j < n_reloads; j++)
5860 register int r = reload_order[j];
5862 if (reload_inherited[r] && rld[r].reg_rtx)
5863 check_reg = rld[r].reg_rtx;
5864 else if (reload_override_in[r]
5865 && (GET_CODE (reload_override_in[r]) == REG
5866 || GET_CODE (reload_override_in[r]) == SUBREG))
5867 check_reg = reload_override_in[r];
5870 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5871 rld[r].opnum, rld[r].when_needed, rld[r].in,
5872 (reload_inherited[r]
5873 ? rld[r].out : const0_rtx),
5878 reload_inherited[r] = 0;
5879 reload_override_in[r] = 0;
5881 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5882 reload_override_in, then we do not need its related
5883 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5884 likewise for other reload types.
5885 We handle this by removing a reload when its only replacement
5886 is mentioned in reload_in of the reload we are going to inherit.
5887 A special case are auto_inc expressions; even if the input is
5888 inherited, we still need the address for the output. We can
5889 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5890 If we suceeded removing some reload and we are doing a preliminary
5891 pass just to remove such reloads, make another pass, since the
5892 removal of one reload might allow us to inherit another one. */
5894 && rld[r].out != rld[r].in
5895 && remove_address_replacements (rld[r].in) && pass)
5900 /* Now that reload_override_in is known valid,
5901 actually override reload_in. */
5902 for (j = 0; j < n_reloads; j++)
5903 if (reload_override_in[j])
5904 rld[j].in = reload_override_in[j];
5906 /* If this reload won't be done because it has been cancelled or is
5907 optional and not inherited, clear reload_reg_rtx so other
5908 routines (such as subst_reloads) don't get confused. */
5909 for (j = 0; j < n_reloads; j++)
5910 if (rld[j].reg_rtx != 0
5911 && ((rld[j].optional && ! reload_inherited[j])
5912 || (rld[j].in == 0 && rld[j].out == 0
5913 && ! rld[j].secondary_p)))
5915 int regno = true_regnum (rld[j].reg_rtx);
5917 if (spill_reg_order[regno] >= 0)
5918 clear_reload_reg_in_use (regno, rld[j].opnum,
5919 rld[j].when_needed, rld[j].mode);
5921 reload_spill_index[j] = -1;
5924 /* Record which pseudos and which spill regs have output reloads. */
5925 for (j = 0; j < n_reloads; j++)
5927 register int r = reload_order[j];
5929 i = reload_spill_index[r];
5931 /* I is nonneg if this reload uses a register.
5932 If rld[r].reg_rtx is 0, this is an optional reload
5933 that we opted to ignore. */
5934 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5935 && rld[r].reg_rtx != 0)
5937 register int nregno = REGNO (rld[r].out_reg);
5940 if (nregno < FIRST_PSEUDO_REGISTER)
5941 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5944 reg_has_output_reload[nregno + nr] = 1;
5948 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5950 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5953 if (rld[r].when_needed != RELOAD_OTHER
5954 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5955 && rld[r].when_needed != RELOAD_FOR_INSN)
5961 /* Deallocate the reload register for reload R. This is called from
5962 remove_address_replacements. */
5965 deallocate_reload_reg (r)
5970 if (! rld[r].reg_rtx)
5972 regno = true_regnum (rld[r].reg_rtx);
5974 if (spill_reg_order[regno] >= 0)
5975 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5977 reload_spill_index[r] = -1;
5980 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
5981 reloads of the same item for fear that we might not have enough reload
5982 registers. However, normally they will get the same reload register
5983 and hence actually need not be loaded twice.
5985 Here we check for the most common case of this phenomenon: when we have
5986 a number of reloads for the same object, each of which were allocated
5987 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5988 reload, and is not modified in the insn itself. If we find such,
5989 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5990 This will not increase the number of spill registers needed and will
5991 prevent redundant code. */
5994 merge_assigned_reloads (insn)
5999 /* Scan all the reloads looking for ones that only load values and
6000 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6001 assigned and not modified by INSN. */
6003 for (i = 0; i < n_reloads; i++)
6005 int conflicting_input = 0;
6006 int max_input_address_opnum = -1;
6007 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6009 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6010 || rld[i].out != 0 || rld[i].reg_rtx == 0
6011 || reg_set_p (rld[i].reg_rtx, insn))
6014 /* Look at all other reloads. Ensure that the only use of this
6015 reload_reg_rtx is in a reload that just loads the same value
6016 as we do. Note that any secondary reloads must be of the identical
6017 class since the values, modes, and result registers are the
6018 same, so we need not do anything with any secondary reloads. */
6020 for (j = 0; j < n_reloads; j++)
6022 if (i == j || rld[j].reg_rtx == 0
6023 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6027 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6028 && rld[j].opnum > max_input_address_opnum)
6029 max_input_address_opnum = rld[j].opnum;
6031 /* If the reload regs aren't exactly the same (e.g, different modes)
6032 or if the values are different, we can't merge this reload.
6033 But if it is an input reload, we might still merge
6034 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6036 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6037 || rld[j].out != 0 || rld[j].in == 0
6038 || ! rtx_equal_p (rld[i].in, rld[j].in))
6040 if (rld[j].when_needed != RELOAD_FOR_INPUT
6041 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6042 || rld[i].opnum > rld[j].opnum)
6043 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6045 conflicting_input = 1;
6046 if (min_conflicting_input_opnum > rld[j].opnum)
6047 min_conflicting_input_opnum = rld[j].opnum;
6051 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6052 we, in fact, found any matching reloads. */
6055 && max_input_address_opnum <= min_conflicting_input_opnum)
6057 for (j = 0; j < n_reloads; j++)
6058 if (i != j && rld[j].reg_rtx != 0
6059 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6060 && (! conflicting_input
6061 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6062 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6064 rld[i].when_needed = RELOAD_OTHER;
6066 reload_spill_index[j] = -1;
6067 transfer_replacements (i, j);
6070 /* If this is now RELOAD_OTHER, look for any reloads that load
6071 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6072 if they were for inputs, RELOAD_OTHER for outputs. Note that
6073 this test is equivalent to looking for reloads for this operand
6076 if (rld[i].when_needed == RELOAD_OTHER)
6077 for (j = 0; j < n_reloads; j++)
6079 && rld[j].when_needed != RELOAD_OTHER
6080 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6083 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6084 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6085 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6090 /* These arrays are filled by emit_reload_insns and its subroutines. */
6091 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6092 static rtx other_input_address_reload_insns = 0;
6093 static rtx other_input_reload_insns = 0;
6094 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6095 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6096 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6097 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6098 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6099 static rtx operand_reload_insns = 0;
6100 static rtx other_operand_reload_insns = 0;
6101 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6103 /* Values to be put in spill_reg_store are put here first. */
6104 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6105 static HARD_REG_SET reg_reloaded_died;
6107 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6108 has the number J. OLD contains the value to be used as input. */
6111 emit_input_reload_insns (chain, rl, old, j)
6112 struct insn_chain *chain;
6117 rtx insn = chain->insn;
6118 register rtx reloadreg = rl->reg_rtx;
6119 rtx oldequiv_reg = 0;
6122 enum machine_mode mode;
6125 /* Determine the mode to reload in.
6126 This is very tricky because we have three to choose from.
6127 There is the mode the insn operand wants (rl->inmode).
6128 There is the mode of the reload register RELOADREG.
6129 There is the intrinsic mode of the operand, which we could find
6130 by stripping some SUBREGs.
6131 It turns out that RELOADREG's mode is irrelevant:
6132 we can change that arbitrarily.
6134 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6135 then the reload reg may not support QImode moves, so use SImode.
6136 If foo is in memory due to spilling a pseudo reg, this is safe,
6137 because the QImode value is in the least significant part of a
6138 slot big enough for a SImode. If foo is some other sort of
6139 memory reference, then it is impossible to reload this case,
6140 so previous passes had better make sure this never happens.
6142 Then consider a one-word union which has SImode and one of its
6143 members is a float, being fetched as (SUBREG:SF union:SI).
6144 We must fetch that as SFmode because we could be loading into
6145 a float-only register. In this case OLD's mode is correct.
6147 Consider an immediate integer: it has VOIDmode. Here we need
6148 to get a mode from something else.
6150 In some cases, there is a fourth mode, the operand's
6151 containing mode. If the insn specifies a containing mode for
6152 this operand, it overrides all others.
6154 I am not sure whether the algorithm here is always right,
6155 but it does the right things in those cases. */
6157 mode = GET_MODE (old);
6158 if (mode == VOIDmode)
6161 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6162 /* If we need a secondary register for this operation, see if
6163 the value is already in a register in that class. Don't
6164 do this if the secondary register will be used as a scratch
6167 if (rl->secondary_in_reload >= 0
6168 && rl->secondary_in_icode == CODE_FOR_nothing
6171 = find_equiv_reg (old, insn,
6172 rld[rl->secondary_in_reload].class,
6176 /* If reloading from memory, see if there is a register
6177 that already holds the same value. If so, reload from there.
6178 We can pass 0 as the reload_reg_p argument because
6179 any other reload has either already been emitted,
6180 in which case find_equiv_reg will see the reload-insn,
6181 or has yet to be emitted, in which case it doesn't matter
6182 because we will use this equiv reg right away. */
6184 if (oldequiv == 0 && optimize
6185 && (GET_CODE (old) == MEM
6186 || (GET_CODE (old) == REG
6187 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6188 && reg_renumber[REGNO (old)] < 0)))
6189 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6193 unsigned int regno = true_regnum (oldequiv);
6195 /* Don't use OLDEQUIV if any other reload changes it at an
6196 earlier stage of this insn or at this stage. */
6197 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6198 rl->in, const0_rtx, j, 0))
6201 /* If it is no cheaper to copy from OLDEQUIV into the
6202 reload register than it would be to move from memory,
6203 don't use it. Likewise, if we need a secondary register
6207 && ((REGNO_REG_CLASS (regno) != rl->class
6208 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6210 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6211 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6212 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6216 #ifdef SECONDARY_MEMORY_NEEDED
6217 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6225 /* delete_output_reload is only invoked properly if old contains
6226 the original pseudo register. Since this is replaced with a
6227 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6228 find the pseudo in RELOAD_IN_REG. */
6230 && reload_override_in[j]
6231 && GET_CODE (rl->in_reg) == REG)
6238 else if (GET_CODE (oldequiv) == REG)
6239 oldequiv_reg = oldequiv;
6240 else if (GET_CODE (oldequiv) == SUBREG)
6241 oldequiv_reg = SUBREG_REG (oldequiv);
6243 /* If we are reloading from a register that was recently stored in
6244 with an output-reload, see if we can prove there was
6245 actually no need to store the old value in it. */
6247 if (optimize && GET_CODE (oldequiv) == REG
6248 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6249 && spill_reg_store[REGNO (oldequiv)]
6250 && GET_CODE (old) == REG
6251 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6252 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6254 delete_output_reload (insn, j, REGNO (oldequiv));
6256 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6257 then load RELOADREG from OLDEQUIV. Note that we cannot use
6258 gen_lowpart_common since it can do the wrong thing when
6259 RELOADREG has a multi-word mode. Note that RELOADREG
6260 must always be a REG here. */
6262 if (GET_MODE (reloadreg) != mode)
6263 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6264 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6265 oldequiv = SUBREG_REG (oldequiv);
6266 if (GET_MODE (oldequiv) != VOIDmode
6267 && mode != GET_MODE (oldequiv))
6268 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6270 /* Switch to the right place to emit the reload insns. */
6271 switch (rl->when_needed)
6274 where = &other_input_reload_insns;
6276 case RELOAD_FOR_INPUT:
6277 where = &input_reload_insns[rl->opnum];
6279 case RELOAD_FOR_INPUT_ADDRESS:
6280 where = &input_address_reload_insns[rl->opnum];
6282 case RELOAD_FOR_INPADDR_ADDRESS:
6283 where = &inpaddr_address_reload_insns[rl->opnum];
6285 case RELOAD_FOR_OUTPUT_ADDRESS:
6286 where = &output_address_reload_insns[rl->opnum];
6288 case RELOAD_FOR_OUTADDR_ADDRESS:
6289 where = &outaddr_address_reload_insns[rl->opnum];
6291 case RELOAD_FOR_OPERAND_ADDRESS:
6292 where = &operand_reload_insns;
6294 case RELOAD_FOR_OPADDR_ADDR:
6295 where = &other_operand_reload_insns;
6297 case RELOAD_FOR_OTHER_ADDRESS:
6298 where = &other_input_address_reload_insns;
6304 push_to_sequence (*where);
6306 /* Auto-increment addresses must be reloaded in a special way. */
6307 if (rl->out && ! rl->out_reg)
6309 /* We are not going to bother supporting the case where a
6310 incremented register can't be copied directly from
6311 OLDEQUIV since this seems highly unlikely. */
6312 if (rl->secondary_in_reload >= 0)
6315 if (reload_inherited[j])
6316 oldequiv = reloadreg;
6318 old = XEXP (rl->in_reg, 0);
6320 if (optimize && GET_CODE (oldequiv) == REG
6321 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6322 && spill_reg_store[REGNO (oldequiv)]
6323 && GET_CODE (old) == REG
6324 && (dead_or_set_p (insn,
6325 spill_reg_stored_to[REGNO (oldequiv)])
6326 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6328 delete_output_reload (insn, j, REGNO (oldequiv));
6330 /* Prevent normal processing of this reload. */
6332 /* Output a special code sequence for this case. */
6333 new_spill_reg_store[REGNO (reloadreg)]
6334 = inc_for_reload (reloadreg, oldequiv, rl->out,
6338 /* If we are reloading a pseudo-register that was set by the previous
6339 insn, see if we can get rid of that pseudo-register entirely
6340 by redirecting the previous insn into our reload register. */
6342 else if (optimize && GET_CODE (old) == REG
6343 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6344 && dead_or_set_p (insn, old)
6345 /* This is unsafe if some other reload
6346 uses the same reg first. */
6347 && ! conflicts_with_override (reloadreg)
6348 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6349 rl->when_needed, old, rl->out, j, 0))
6351 rtx temp = PREV_INSN (insn);
6352 while (temp && GET_CODE (temp) == NOTE)
6353 temp = PREV_INSN (temp);
6355 && GET_CODE (temp) == INSN
6356 && GET_CODE (PATTERN (temp)) == SET
6357 && SET_DEST (PATTERN (temp)) == old
6358 /* Make sure we can access insn_operand_constraint. */
6359 && asm_noperands (PATTERN (temp)) < 0
6360 /* This is unsafe if prev insn rejects our reload reg. */
6361 && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint,
6363 /* This is unsafe if operand occurs more than once in current
6364 insn. Perhaps some occurrences aren't reloaded. */
6365 && count_occurrences (PATTERN (insn), old, 0) == 1
6366 /* Don't risk splitting a matching pair of operands. */
6367 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6369 /* Store into the reload register instead of the pseudo. */
6370 SET_DEST (PATTERN (temp)) = reloadreg;
6372 /* If the previous insn is an output reload, the source is
6373 a reload register, and its spill_reg_store entry will
6374 contain the previous destination. This is now
6376 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6377 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6379 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6380 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6383 /* If these are the only uses of the pseudo reg,
6384 pretend for GDB it lives in the reload reg we used. */
6385 if (REG_N_DEATHS (REGNO (old)) == 1
6386 && REG_N_SETS (REGNO (old)) == 1)
6388 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6389 alter_reg (REGNO (old), -1);
6395 /* We can't do that, so output an insn to load RELOADREG. */
6397 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6398 /* If we have a secondary reload, pick up the secondary register
6399 and icode, if any. If OLDEQUIV and OLD are different or
6400 if this is an in-out reload, recompute whether or not we
6401 still need a secondary register and what the icode should
6402 be. If we still need a secondary register and the class or
6403 icode is different, go back to reloading from OLD if using
6404 OLDEQUIV means that we got the wrong type of register. We
6405 cannot have different class or icode due to an in-out reload
6406 because we don't make such reloads when both the input and
6407 output need secondary reload registers. */
6409 if (! special && rl->secondary_in_reload >= 0)
6411 rtx second_reload_reg = 0;
6412 int secondary_reload = rl->secondary_in_reload;
6413 rtx real_oldequiv = oldequiv;
6416 enum insn_code icode;
6418 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6419 and similarly for OLD.
6420 See comments in get_secondary_reload in reload.c. */
6421 /* If it is a pseudo that cannot be replaced with its
6422 equivalent MEM, we must fall back to reload_in, which
6423 will have all the necessary substitutions registered.
6424 Likewise for a pseudo that can't be replaced with its
6425 equivalent constant.
6427 Take extra care for subregs of such pseudos. Note that
6428 we cannot use reg_equiv_mem in this case because it is
6429 not in the right mode. */
6432 if (GET_CODE (tmp) == SUBREG)
6433 tmp = SUBREG_REG (tmp);
6434 if (GET_CODE (tmp) == REG
6435 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6436 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6437 || reg_equiv_constant[REGNO (tmp)] != 0))
6439 if (! reg_equiv_mem[REGNO (tmp)]
6440 || num_not_at_initial_offset
6441 || GET_CODE (oldequiv) == SUBREG)
6442 real_oldequiv = rl->in;
6444 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6448 if (GET_CODE (tmp) == SUBREG)
6449 tmp = SUBREG_REG (tmp);
6450 if (GET_CODE (tmp) == REG
6451 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6452 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6453 || reg_equiv_constant[REGNO (tmp)] != 0))
6455 if (! reg_equiv_mem[REGNO (tmp)]
6456 || num_not_at_initial_offset
6457 || GET_CODE (old) == SUBREG)
6460 real_old = reg_equiv_mem[REGNO (tmp)];
6463 second_reload_reg = rld[secondary_reload].reg_rtx;
6464 icode = rl->secondary_in_icode;
6466 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6467 || (rl->in != 0 && rl->out != 0))
6469 enum reg_class new_class
6470 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6471 mode, real_oldequiv);
6473 if (new_class == NO_REGS)
6474 second_reload_reg = 0;
6477 enum insn_code new_icode;
6478 enum machine_mode new_mode;
6480 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6481 REGNO (second_reload_reg)))
6482 oldequiv = old, real_oldequiv = real_old;
6485 new_icode = reload_in_optab[(int) mode];
6486 if (new_icode != CODE_FOR_nothing
6487 && ((insn_data[(int) new_icode].operand[0].predicate
6488 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6490 || (insn_data[(int) new_icode].operand[1].predicate
6491 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6492 (real_oldequiv, mode)))))
6493 new_icode = CODE_FOR_nothing;
6495 if (new_icode == CODE_FOR_nothing)
6498 new_mode = insn_data[(int) new_icode].operand[2].mode;
6500 if (GET_MODE (second_reload_reg) != new_mode)
6502 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6504 oldequiv = old, real_oldequiv = real_old;
6507 = gen_rtx_REG (new_mode,
6508 REGNO (second_reload_reg));
6514 /* If we still need a secondary reload register, check
6515 to see if it is being used as a scratch or intermediate
6516 register and generate code appropriately. If we need
6517 a scratch register, use REAL_OLDEQUIV since the form of
6518 the insn may depend on the actual address if it is
6521 if (second_reload_reg)
6523 if (icode != CODE_FOR_nothing)
6525 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6526 second_reload_reg));
6531 /* See if we need a scratch register to load the
6532 intermediate register (a tertiary reload). */
6533 enum insn_code tertiary_icode
6534 = rld[secondary_reload].secondary_in_icode;
6536 if (tertiary_icode != CODE_FOR_nothing)
6538 rtx third_reload_reg
6539 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6541 emit_insn ((GEN_FCN (tertiary_icode)
6542 (second_reload_reg, real_oldequiv,
6543 third_reload_reg)));
6546 gen_reload (second_reload_reg, real_oldequiv,
6550 oldequiv = second_reload_reg;
6556 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6558 rtx real_oldequiv = oldequiv;
6560 if ((GET_CODE (oldequiv) == REG
6561 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6562 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6563 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6564 || (GET_CODE (oldequiv) == SUBREG
6565 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6566 && (REGNO (SUBREG_REG (oldequiv))
6567 >= FIRST_PSEUDO_REGISTER)
6568 && ((reg_equiv_memory_loc
6569 [REGNO (SUBREG_REG (oldequiv))] != 0)
6570 || (reg_equiv_constant
6571 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6572 || (CONSTANT_P (oldequiv)
6573 && PREFERRED_RELOAD_CLASS (oldequiv,
6574 REGNO_REG_CLASS (REGNO (reloadreg))) == NO_REGS))
6575 real_oldequiv = rl->in;
6576 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6580 if (flag_non_call_exceptions)
6581 copy_eh_notes (insn, get_insns ());
6583 /* End this sequence. */
6584 *where = get_insns ();
6587 /* Update reload_override_in so that delete_address_reloads_1
6588 can see the actual register usage. */
6590 reload_override_in[j] = oldequiv;
6593 /* Generate insns to for the output reload RL, which is for the insn described
6594 by CHAIN and has the number J. */
6596 emit_output_reload_insns (chain, rl, j)
6597 struct insn_chain *chain;
6601 rtx reloadreg = rl->reg_rtx;
6602 rtx insn = chain->insn;
6605 enum machine_mode mode = GET_MODE (old);
6608 if (rl->when_needed == RELOAD_OTHER)
6611 push_to_sequence (output_reload_insns[rl->opnum]);
6613 /* Determine the mode to reload in.
6614 See comments above (for input reloading). */
6616 if (mode == VOIDmode)
6618 /* VOIDmode should never happen for an output. */
6619 if (asm_noperands (PATTERN (insn)) < 0)
6620 /* It's the compiler's fault. */
6621 fatal_insn ("VOIDmode on an output", insn);
6622 error_for_asm (insn, "output operand is constant in `asm'");
6623 /* Prevent crash--use something we know is valid. */
6625 old = gen_rtx_REG (mode, REGNO (reloadreg));
6628 if (GET_MODE (reloadreg) != mode)
6629 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6631 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6633 /* If we need two reload regs, set RELOADREG to the intermediate
6634 one, since it will be stored into OLD. We might need a secondary
6635 register only for an input reload, so check again here. */
6637 if (rl->secondary_out_reload >= 0)
6641 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6642 && reg_equiv_mem[REGNO (old)] != 0)
6643 real_old = reg_equiv_mem[REGNO (old)];
6645 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6649 rtx second_reloadreg = reloadreg;
6650 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6652 /* See if RELOADREG is to be used as a scratch register
6653 or as an intermediate register. */
6654 if (rl->secondary_out_icode != CODE_FOR_nothing)
6656 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6657 (real_old, second_reloadreg, reloadreg)));
6662 /* See if we need both a scratch and intermediate reload
6665 int secondary_reload = rl->secondary_out_reload;
6666 enum insn_code tertiary_icode
6667 = rld[secondary_reload].secondary_out_icode;
6669 if (GET_MODE (reloadreg) != mode)
6670 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6672 if (tertiary_icode != CODE_FOR_nothing)
6675 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6678 /* Copy primary reload reg to secondary reload reg.
6679 (Note that these have been swapped above, then
6680 secondary reload reg to OLD using our insn.) */
6682 /* If REAL_OLD is a paradoxical SUBREG, remove it
6683 and try to put the opposite SUBREG on
6685 if (GET_CODE (real_old) == SUBREG
6686 && (GET_MODE_SIZE (GET_MODE (real_old))
6687 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6688 && 0 != (tem = gen_lowpart_common
6689 (GET_MODE (SUBREG_REG (real_old)),
6691 real_old = SUBREG_REG (real_old), reloadreg = tem;
6693 gen_reload (reloadreg, second_reloadreg,
6694 rl->opnum, rl->when_needed);
6695 emit_insn ((GEN_FCN (tertiary_icode)
6696 (real_old, reloadreg, third_reloadreg)));
6701 /* Copy between the reload regs here and then to
6704 gen_reload (reloadreg, second_reloadreg,
6705 rl->opnum, rl->when_needed);
6711 /* Output the last reload insn. */
6716 /* Don't output the last reload if OLD is not the dest of
6717 INSN and is in the src and is clobbered by INSN. */
6718 if (! flag_expensive_optimizations
6719 || GET_CODE (old) != REG
6720 || !(set = single_set (insn))
6721 || rtx_equal_p (old, SET_DEST (set))
6722 || !reg_mentioned_p (old, SET_SRC (set))
6723 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6724 gen_reload (old, reloadreg, rl->opnum,
6728 /* Look at all insns we emitted, just to be safe. */
6729 for (p = get_insns (); p; p = NEXT_INSN (p))
6732 rtx pat = PATTERN (p);
6734 /* If this output reload doesn't come from a spill reg,
6735 clear any memory of reloaded copies of the pseudo reg.
6736 If this output reload comes from a spill reg,
6737 reg_has_output_reload will make this do nothing. */
6738 note_stores (pat, forget_old_reloads_1, NULL);
6740 if (reg_mentioned_p (rl->reg_rtx, pat))
6742 rtx set = single_set (insn);
6743 if (reload_spill_index[j] < 0
6745 && SET_SRC (set) == rl->reg_rtx)
6747 int src = REGNO (SET_SRC (set));
6749 reload_spill_index[j] = src;
6750 SET_HARD_REG_BIT (reg_is_output_reload, src);
6751 if (find_regno_note (insn, REG_DEAD, src))
6752 SET_HARD_REG_BIT (reg_reloaded_died, src);
6754 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6756 int s = rl->secondary_out_reload;
6757 set = single_set (p);
6758 /* If this reload copies only to the secondary reload
6759 register, the secondary reload does the actual
6761 if (s >= 0 && set == NULL_RTX)
6762 /* We can't tell what function the secondary reload
6763 has and where the actual store to the pseudo is
6764 made; leave new_spill_reg_store alone. */
6767 && SET_SRC (set) == rl->reg_rtx
6768 && SET_DEST (set) == rld[s].reg_rtx)
6770 /* Usually the next instruction will be the
6771 secondary reload insn; if we can confirm
6772 that it is, setting new_spill_reg_store to
6773 that insn will allow an extra optimization. */
6774 rtx s_reg = rld[s].reg_rtx;
6775 rtx next = NEXT_INSN (p);
6776 rld[s].out = rl->out;
6777 rld[s].out_reg = rl->out_reg;
6778 set = single_set (next);
6779 if (set && SET_SRC (set) == s_reg
6780 && ! new_spill_reg_store[REGNO (s_reg)])
6782 SET_HARD_REG_BIT (reg_is_output_reload,
6784 new_spill_reg_store[REGNO (s_reg)] = next;
6788 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6793 if (rl->when_needed == RELOAD_OTHER)
6795 emit_insns (other_output_reload_insns[rl->opnum]);
6796 other_output_reload_insns[rl->opnum] = get_insns ();
6799 output_reload_insns[rl->opnum] = get_insns ();
6801 if (flag_non_call_exceptions)
6802 copy_eh_notes (insn, get_insns ());
6807 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6808 and has the number J. */
6810 do_input_reload (chain, rl, j)
6811 struct insn_chain *chain;
6815 int expect_occurrences = 1;
6816 rtx insn = chain->insn;
6817 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6818 ? rl->in_reg : rl->in);
6821 /* AUTO_INC reloads need to be handled even if inherited. We got an
6822 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6823 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6824 && ! rtx_equal_p (rl->reg_rtx, old)
6825 && rl->reg_rtx != 0)
6826 emit_input_reload_insns (chain, rld + j, old, j);
6828 /* When inheriting a wider reload, we have a MEM in rl->in,
6829 e.g. inheriting a SImode output reload for
6830 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6831 if (optimize && reload_inherited[j] && rl->in
6832 && GET_CODE (rl->in) == MEM
6833 && GET_CODE (rl->in_reg) == MEM
6834 && reload_spill_index[j] >= 0
6835 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6838 = count_occurrences (PATTERN (insn), rl->in, 0) == 1 ? 0 : -1;
6839 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6842 /* If we are reloading a register that was recently stored in with an
6843 output-reload, see if we can prove there was
6844 actually no need to store the old value in it. */
6847 && (reload_inherited[j] || reload_override_in[j])
6849 && GET_CODE (rl->reg_rtx) == REG
6850 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6852 /* There doesn't seem to be any reason to restrict this to pseudos
6853 and doing so loses in the case where we are copying from a
6854 register of the wrong class. */
6855 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6856 >= FIRST_PSEUDO_REGISTER)
6858 /* The insn might have already some references to stackslots
6859 replaced by MEMs, while reload_out_reg still names the
6861 && (dead_or_set_p (insn,
6862 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6863 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6865 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6868 /* Do output reloading for reload RL, which is for the insn described by
6869 CHAIN and has the number J.
6870 ??? At some point we need to support handling output reloads of
6871 JUMP_INSNs or insns that set cc0. */
6873 do_output_reload (chain, rl, j)
6874 struct insn_chain *chain;
6879 rtx insn = chain->insn;
6880 /* If this is an output reload that stores something that is
6881 not loaded in this same reload, see if we can eliminate a previous
6883 rtx pseudo = rl->out_reg;
6886 && GET_CODE (pseudo) == REG
6887 && ! rtx_equal_p (rl->in_reg, pseudo)
6888 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6889 && reg_last_reload_reg[REGNO (pseudo)])
6891 int pseudo_no = REGNO (pseudo);
6892 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6894 /* We don't need to test full validity of last_regno for
6895 inherit here; we only want to know if the store actually
6896 matches the pseudo. */
6897 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6898 && reg_reloaded_contents[last_regno] == pseudo_no
6899 && spill_reg_store[last_regno]
6900 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6901 delete_output_reload (insn, j, last_regno);
6906 || rl->reg_rtx == old
6907 || rl->reg_rtx == 0)
6910 /* An output operand that dies right away does need a reload,
6911 but need not be copied from it. Show the new location in the
6913 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6914 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6916 XEXP (note, 0) = rl->reg_rtx;
6919 /* Likewise for a SUBREG of an operand that dies. */
6920 else if (GET_CODE (old) == SUBREG
6921 && GET_CODE (SUBREG_REG (old)) == REG
6922 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6925 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6929 else if (GET_CODE (old) == SCRATCH)
6930 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6931 but we don't want to make an output reload. */
6934 /* If is a JUMP_INSN, we can't support output reloads yet. */
6935 if (GET_CODE (insn) == JUMP_INSN)
6938 emit_output_reload_insns (chain, rld + j, j);
6941 /* Output insns to reload values in and out of the chosen reload regs. */
6944 emit_reload_insns (chain)
6945 struct insn_chain *chain;
6947 rtx insn = chain->insn;
6950 rtx following_insn = NEXT_INSN (insn);
6951 rtx before_insn = PREV_INSN (insn);
6953 CLEAR_HARD_REG_SET (reg_reloaded_died);
6955 for (j = 0; j < reload_n_operands; j++)
6956 input_reload_insns[j] = input_address_reload_insns[j]
6957 = inpaddr_address_reload_insns[j]
6958 = output_reload_insns[j] = output_address_reload_insns[j]
6959 = outaddr_address_reload_insns[j]
6960 = other_output_reload_insns[j] = 0;
6961 other_input_address_reload_insns = 0;
6962 other_input_reload_insns = 0;
6963 operand_reload_insns = 0;
6964 other_operand_reload_insns = 0;
6966 /* Dump reloads into the dump file. */
6969 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6970 debug_reload_to_stream (rtl_dump_file);
6973 /* Now output the instructions to copy the data into and out of the
6974 reload registers. Do these in the order that the reloads were reported,
6975 since reloads of base and index registers precede reloads of operands
6976 and the operands may need the base and index registers reloaded. */
6978 for (j = 0; j < n_reloads; j++)
6981 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6982 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6984 do_input_reload (chain, rld + j, j);
6985 do_output_reload (chain, rld + j, j);
6988 /* Now write all the insns we made for reloads in the order expected by
6989 the allocation functions. Prior to the insn being reloaded, we write
6990 the following reloads:
6992 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6994 RELOAD_OTHER reloads.
6996 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6997 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6998 RELOAD_FOR_INPUT reload for the operand.
7000 RELOAD_FOR_OPADDR_ADDRS reloads.
7002 RELOAD_FOR_OPERAND_ADDRESS reloads.
7004 After the insn being reloaded, we write the following:
7006 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7007 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7008 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7009 reloads for the operand. The RELOAD_OTHER output reloads are
7010 output in descending order by reload number. */
7012 emit_insns_before (other_input_address_reload_insns, insn);
7013 emit_insns_before (other_input_reload_insns, insn);
7015 for (j = 0; j < reload_n_operands; j++)
7017 emit_insns_before (inpaddr_address_reload_insns[j], insn);
7018 emit_insns_before (input_address_reload_insns[j], insn);
7019 emit_insns_before (input_reload_insns[j], insn);
7022 emit_insns_before (other_operand_reload_insns, insn);
7023 emit_insns_before (operand_reload_insns, insn);
7025 for (j = 0; j < reload_n_operands; j++)
7027 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
7028 emit_insns_before (output_address_reload_insns[j], following_insn);
7029 emit_insns_before (output_reload_insns[j], following_insn);
7030 emit_insns_before (other_output_reload_insns[j], following_insn);
7033 /* Keep basic block info up to date. */
7036 if (BLOCK_HEAD (chain->block) == insn)
7037 BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn);
7038 if (BLOCK_END (chain->block) == insn)
7039 BLOCK_END (chain->block) = PREV_INSN (following_insn);
7042 /* For all the spill regs newly reloaded in this instruction,
7043 record what they were reloaded from, so subsequent instructions
7044 can inherit the reloads.
7046 Update spill_reg_store for the reloads of this insn.
7047 Copy the elements that were updated in the loop above. */
7049 for (j = 0; j < n_reloads; j++)
7051 register int r = reload_order[j];
7052 register int i = reload_spill_index[r];
7054 /* If this is a non-inherited input reload from a pseudo, we must
7055 clear any memory of a previous store to the same pseudo. Only do
7056 something if there will not be an output reload for the pseudo
7058 if (rld[r].in_reg != 0
7059 && ! (reload_inherited[r] || reload_override_in[r]))
7061 rtx reg = rld[r].in_reg;
7063 if (GET_CODE (reg) == SUBREG)
7064 reg = SUBREG_REG (reg);
7066 if (GET_CODE (reg) == REG
7067 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7068 && ! reg_has_output_reload[REGNO (reg)])
7070 int nregno = REGNO (reg);
7072 if (reg_last_reload_reg[nregno])
7074 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7076 if (reg_reloaded_contents[last_regno] == nregno)
7077 spill_reg_store[last_regno] = 0;
7082 /* I is nonneg if this reload used a register.
7083 If rld[r].reg_rtx is 0, this is an optional reload
7084 that we opted to ignore. */
7086 if (i >= 0 && rld[r].reg_rtx != 0)
7088 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
7090 int part_reaches_end = 0;
7091 int all_reaches_end = 1;
7093 /* For a multi register reload, we need to check if all or part
7094 of the value lives to the end. */
7095 for (k = 0; k < nr; k++)
7097 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7098 rld[r].when_needed))
7099 part_reaches_end = 1;
7101 all_reaches_end = 0;
7104 /* Ignore reloads that don't reach the end of the insn in
7106 if (all_reaches_end)
7108 /* First, clear out memory of what used to be in this spill reg.
7109 If consecutive registers are used, clear them all. */
7111 for (k = 0; k < nr; k++)
7112 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7114 /* Maybe the spill reg contains a copy of reload_out. */
7116 && (GET_CODE (rld[r].out) == REG
7120 || GET_CODE (rld[r].out_reg) == REG))
7122 rtx out = (GET_CODE (rld[r].out) == REG
7126 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7127 register int nregno = REGNO (out);
7128 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7129 : HARD_REGNO_NREGS (nregno,
7130 GET_MODE (rld[r].reg_rtx)));
7132 spill_reg_store[i] = new_spill_reg_store[i];
7133 spill_reg_stored_to[i] = out;
7134 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7136 /* If NREGNO is a hard register, it may occupy more than
7137 one register. If it does, say what is in the
7138 rest of the registers assuming that both registers
7139 agree on how many words the object takes. If not,
7140 invalidate the subsequent registers. */
7142 if (nregno < FIRST_PSEUDO_REGISTER)
7143 for (k = 1; k < nnr; k++)
7144 reg_last_reload_reg[nregno + k]
7146 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7147 REGNO (rld[r].reg_rtx) + k)
7150 /* Now do the inverse operation. */
7151 for (k = 0; k < nr; k++)
7153 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7154 reg_reloaded_contents[i + k]
7155 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7158 reg_reloaded_insn[i + k] = insn;
7159 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7163 /* Maybe the spill reg contains a copy of reload_in. Only do
7164 something if there will not be an output reload for
7165 the register being reloaded. */
7166 else if (rld[r].out_reg == 0
7168 && ((GET_CODE (rld[r].in) == REG
7169 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7170 && ! reg_has_output_reload[REGNO (rld[r].in)])
7171 || (GET_CODE (rld[r].in_reg) == REG
7172 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7173 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7175 register int nregno;
7178 if (GET_CODE (rld[r].in) == REG
7179 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7180 nregno = REGNO (rld[r].in);
7181 else if (GET_CODE (rld[r].in_reg) == REG)
7182 nregno = REGNO (rld[r].in_reg);
7184 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7186 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7187 : HARD_REGNO_NREGS (nregno,
7188 GET_MODE (rld[r].reg_rtx)));
7190 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7192 if (nregno < FIRST_PSEUDO_REGISTER)
7193 for (k = 1; k < nnr; k++)
7194 reg_last_reload_reg[nregno + k]
7196 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7197 REGNO (rld[r].reg_rtx) + k)
7200 /* Unless we inherited this reload, show we haven't
7201 recently done a store.
7202 Previous stores of inherited auto_inc expressions
7203 also have to be discarded. */
7204 if (! reload_inherited[r]
7205 || (rld[r].out && ! rld[r].out_reg))
7206 spill_reg_store[i] = 0;
7208 for (k = 0; k < nr; k++)
7210 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7211 reg_reloaded_contents[i + k]
7212 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7215 reg_reloaded_insn[i + k] = insn;
7216 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7221 /* However, if part of the reload reaches the end, then we must
7222 invalidate the old info for the part that survives to the end. */
7223 else if (part_reaches_end)
7225 for (k = 0; k < nr; k++)
7226 if (reload_reg_reaches_end_p (i + k,
7228 rld[r].when_needed))
7229 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7233 /* The following if-statement was #if 0'd in 1.34 (or before...).
7234 It's reenabled in 1.35 because supposedly nothing else
7235 deals with this problem. */
7237 /* If a register gets output-reloaded from a non-spill register,
7238 that invalidates any previous reloaded copy of it.
7239 But forget_old_reloads_1 won't get to see it, because
7240 it thinks only about the original insn. So invalidate it here. */
7241 if (i < 0 && rld[r].out != 0
7242 && (GET_CODE (rld[r].out) == REG
7243 || (GET_CODE (rld[r].out) == MEM
7244 && GET_CODE (rld[r].out_reg) == REG)))
7246 rtx out = (GET_CODE (rld[r].out) == REG
7247 ? rld[r].out : rld[r].out_reg);
7248 register int nregno = REGNO (out);
7249 if (nregno >= FIRST_PSEUDO_REGISTER)
7251 rtx src_reg, store_insn = NULL_RTX;
7253 reg_last_reload_reg[nregno] = 0;
7255 /* If we can find a hard register that is stored, record
7256 the storing insn so that we may delete this insn with
7257 delete_output_reload. */
7258 src_reg = rld[r].reg_rtx;
7260 /* If this is an optional reload, try to find the source reg
7261 from an input reload. */
7264 rtx set = single_set (insn);
7265 if (set && SET_DEST (set) == rld[r].out)
7269 src_reg = SET_SRC (set);
7271 for (k = 0; k < n_reloads; k++)
7273 if (rld[k].in == src_reg)
7275 src_reg = rld[k].reg_rtx;
7282 store_insn = new_spill_reg_store[REGNO (src_reg)];
7283 if (src_reg && GET_CODE (src_reg) == REG
7284 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7286 int src_regno = REGNO (src_reg);
7287 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7288 /* The place where to find a death note varies with
7289 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7290 necessarily checked exactly in the code that moves
7291 notes, so just check both locations. */
7292 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7294 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7297 spill_reg_store[src_regno + nr] = store_insn;
7298 spill_reg_stored_to[src_regno + nr] = out;
7299 reg_reloaded_contents[src_regno + nr] = nregno;
7300 reg_reloaded_insn[src_regno + nr] = store_insn;
7301 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7302 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7303 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7305 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7307 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7309 reg_last_reload_reg[nregno] = src_reg;
7314 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7316 while (num_regs-- > 0)
7317 reg_last_reload_reg[nregno + num_regs] = 0;
7321 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7324 /* Emit code to perform a reload from IN (which may be a reload register) to
7325 OUT (which may also be a reload register). IN or OUT is from operand
7326 OPNUM with reload type TYPE.
7328 Returns first insn emitted. */
7331 gen_reload (out, in, opnum, type)
7335 enum reload_type type;
7337 rtx last = get_last_insn ();
7340 /* If IN is a paradoxical SUBREG, remove it and try to put the
7341 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7342 if (GET_CODE (in) == SUBREG
7343 && (GET_MODE_SIZE (GET_MODE (in))
7344 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7345 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7346 in = SUBREG_REG (in), out = tem;
7347 else if (GET_CODE (out) == SUBREG
7348 && (GET_MODE_SIZE (GET_MODE (out))
7349 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7350 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7351 out = SUBREG_REG (out), in = tem;
7353 /* How to do this reload can get quite tricky. Normally, we are being
7354 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7355 register that didn't get a hard register. In that case we can just
7356 call emit_move_insn.
7358 We can also be asked to reload a PLUS that adds a register or a MEM to
7359 another register, constant or MEM. This can occur during frame pointer
7360 elimination and while reloading addresses. This case is handled by
7361 trying to emit a single insn to perform the add. If it is not valid,
7362 we use a two insn sequence.
7364 Finally, we could be called to handle an 'o' constraint by putting
7365 an address into a register. In that case, we first try to do this
7366 with a named pattern of "reload_load_address". If no such pattern
7367 exists, we just emit a SET insn and hope for the best (it will normally
7368 be valid on machines that use 'o').
7370 This entire process is made complex because reload will never
7371 process the insns we generate here and so we must ensure that
7372 they will fit their constraints and also by the fact that parts of
7373 IN might be being reloaded separately and replaced with spill registers.
7374 Because of this, we are, in some sense, just guessing the right approach
7375 here. The one listed above seems to work.
7377 ??? At some point, this whole thing needs to be rethought. */
7379 if (GET_CODE (in) == PLUS
7380 && (GET_CODE (XEXP (in, 0)) == REG
7381 || GET_CODE (XEXP (in, 0)) == SUBREG
7382 || GET_CODE (XEXP (in, 0)) == MEM)
7383 && (GET_CODE (XEXP (in, 1)) == REG
7384 || GET_CODE (XEXP (in, 1)) == SUBREG
7385 || CONSTANT_P (XEXP (in, 1))
7386 || GET_CODE (XEXP (in, 1)) == MEM))
7388 /* We need to compute the sum of a register or a MEM and another
7389 register, constant, or MEM, and put it into the reload
7390 register. The best possible way of doing this is if the machine
7391 has a three-operand ADD insn that accepts the required operands.
7393 The simplest approach is to try to generate such an insn and see if it
7394 is recognized and matches its constraints. If so, it can be used.
7396 It might be better not to actually emit the insn unless it is valid,
7397 but we need to pass the insn as an operand to `recog' and
7398 `extract_insn' and it is simpler to emit and then delete the insn if
7399 not valid than to dummy things up. */
7401 rtx op0, op1, tem, insn;
7404 op0 = find_replacement (&XEXP (in, 0));
7405 op1 = find_replacement (&XEXP (in, 1));
7407 /* Since constraint checking is strict, commutativity won't be
7408 checked, so we need to do that here to avoid spurious failure
7409 if the add instruction is two-address and the second operand
7410 of the add is the same as the reload reg, which is frequently
7411 the case. If the insn would be A = B + A, rearrange it so
7412 it will be A = A + B as constrain_operands expects. */
7414 if (GET_CODE (XEXP (in, 1)) == REG
7415 && REGNO (out) == REGNO (XEXP (in, 1)))
7416 tem = op0, op0 = op1, op1 = tem;
7418 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7419 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7421 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7422 code = recog_memoized (insn);
7426 extract_insn (insn);
7427 /* We want constrain operands to treat this insn strictly in
7428 its validity determination, i.e., the way it would after reload
7430 if (constrain_operands (1))
7434 delete_insns_since (last);
7436 /* If that failed, we must use a conservative two-insn sequence.
7438 Use a move to copy one operand into the reload register. Prefer
7439 to reload a constant, MEM or pseudo since the move patterns can
7440 handle an arbitrary operand. If OP1 is not a constant, MEM or
7441 pseudo and OP1 is not a valid operand for an add instruction, then
7444 After reloading one of the operands into the reload register, add
7445 the reload register to the output register.
7447 If there is another way to do this for a specific machine, a
7448 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7451 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7453 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7454 || (GET_CODE (op1) == REG
7455 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7456 || (code != CODE_FOR_nothing
7457 && ! ((*insn_data[code].operand[2].predicate)
7458 (op1, insn_data[code].operand[2].mode))))
7459 tem = op0, op0 = op1, op1 = tem;
7461 gen_reload (out, op0, opnum, type);
7463 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7464 This fixes a problem on the 32K where the stack pointer cannot
7465 be used as an operand of an add insn. */
7467 if (rtx_equal_p (op0, op1))
7470 insn = emit_insn (gen_add2_insn (out, op1));
7472 /* If that failed, copy the address register to the reload register.
7473 Then add the constant to the reload register. */
7475 code = recog_memoized (insn);
7479 extract_insn (insn);
7480 /* We want constrain operands to treat this insn strictly in
7481 its validity determination, i.e., the way it would after reload
7483 if (constrain_operands (1))
7485 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7487 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7492 delete_insns_since (last);
7494 gen_reload (out, op1, opnum, type);
7495 insn = emit_insn (gen_add2_insn (out, op0));
7496 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7499 #ifdef SECONDARY_MEMORY_NEEDED
7500 /* If we need a memory location to do the move, do it that way. */
7501 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7502 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7503 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7504 REGNO_REG_CLASS (REGNO (out)),
7507 /* Get the memory to use and rewrite both registers to its mode. */
7508 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7510 if (GET_MODE (loc) != GET_MODE (out))
7511 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7513 if (GET_MODE (loc) != GET_MODE (in))
7514 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7516 gen_reload (loc, in, opnum, type);
7517 gen_reload (out, loc, opnum, type);
7521 /* If IN is a simple operand, use gen_move_insn. */
7522 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7523 emit_insn (gen_move_insn (out, in));
7525 #ifdef HAVE_reload_load_address
7526 else if (HAVE_reload_load_address)
7527 emit_insn (gen_reload_load_address (out, in));
7530 /* Otherwise, just write (set OUT IN) and hope for the best. */
7532 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7534 /* Return the first insn emitted.
7535 We can not just return get_last_insn, because there may have
7536 been multiple instructions emitted. Also note that gen_move_insn may
7537 emit more than one insn itself, so we can not assume that there is one
7538 insn emitted per emit_insn_before call. */
7540 return last ? NEXT_INSN (last) : get_insns ();
7543 /* Delete a previously made output-reload
7544 whose result we now believe is not needed.
7545 First we double-check.
7547 INSN is the insn now being processed.
7548 LAST_RELOAD_REG is the hard register number for which we want to delete
7549 the last output reload.
7550 J is the reload-number that originally used REG. The caller has made
7551 certain that reload J doesn't use REG any longer for input. */
7554 delete_output_reload (insn, j, last_reload_reg)
7557 int last_reload_reg;
7559 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7560 rtx reg = spill_reg_stored_to[last_reload_reg];
7563 int n_inherited = 0;
7567 /* Get the raw pseudo-register referred to. */
7569 while (GET_CODE (reg) == SUBREG)
7570 reg = SUBREG_REG (reg);
7571 substed = reg_equiv_memory_loc[REGNO (reg)];
7573 /* This is unsafe if the operand occurs more often in the current
7574 insn than it is inherited. */
7575 for (k = n_reloads - 1; k >= 0; k--)
7577 rtx reg2 = rld[k].in;
7580 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7581 reg2 = rld[k].in_reg;
7583 if (rld[k].out && ! rld[k].out_reg)
7584 reg2 = XEXP (rld[k].in_reg, 0);
7586 while (GET_CODE (reg2) == SUBREG)
7587 reg2 = SUBREG_REG (reg2);
7588 if (rtx_equal_p (reg2, reg))
7590 if (reload_inherited[k] || reload_override_in[k] || k == j)
7593 reg2 = rld[k].out_reg;
7596 while (GET_CODE (reg2) == SUBREG)
7597 reg2 = XEXP (reg2, 0);
7598 if (rtx_equal_p (reg2, reg))
7605 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7607 n_occurrences += count_occurrences (PATTERN (insn),
7608 eliminate_regs (substed, 0,
7610 if (n_occurrences > n_inherited)
7613 /* If the pseudo-reg we are reloading is no longer referenced
7614 anywhere between the store into it and here,
7615 and no jumps or labels intervene, then the value can get
7616 here through the reload reg alone.
7617 Otherwise, give up--return. */
7618 for (i1 = NEXT_INSN (output_reload_insn);
7619 i1 != insn; i1 = NEXT_INSN (i1))
7621 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7623 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7624 && reg_mentioned_p (reg, PATTERN (i1)))
7626 /* If this is USE in front of INSN, we only have to check that
7627 there are no more references than accounted for by inheritance. */
7628 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7630 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7631 i1 = NEXT_INSN (i1);
7633 if (n_occurrences <= n_inherited && i1 == insn)
7639 /* The caller has already checked that REG dies or is set in INSN.
7640 It has also checked that we are optimizing, and thus some inaccurancies
7641 in the debugging information are acceptable.
7642 So we could just delete output_reload_insn.
7643 But in some cases we can improve the debugging information without
7644 sacrificing optimization - maybe even improving the code:
7645 See if the pseudo reg has been completely replaced
7646 with reload regs. If so, delete the store insn
7647 and forget we had a stack slot for the pseudo. */
7648 if (rld[j].out != rld[j].in
7649 && REG_N_DEATHS (REGNO (reg)) == 1
7650 && REG_N_SETS (REGNO (reg)) == 1
7651 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7652 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7656 /* We know that it was used only between here
7657 and the beginning of the current basic block.
7658 (We also know that the last use before INSN was
7659 the output reload we are thinking of deleting, but never mind that.)
7660 Search that range; see if any ref remains. */
7661 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7663 rtx set = single_set (i2);
7665 /* Uses which just store in the pseudo don't count,
7666 since if they are the only uses, they are dead. */
7667 if (set != 0 && SET_DEST (set) == reg)
7669 if (GET_CODE (i2) == CODE_LABEL
7670 || GET_CODE (i2) == JUMP_INSN)
7672 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7673 && reg_mentioned_p (reg, PATTERN (i2)))
7675 /* Some other ref remains; just delete the output reload we
7677 delete_address_reloads (output_reload_insn, insn);
7678 PUT_CODE (output_reload_insn, NOTE);
7679 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7680 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7685 /* Delete the now-dead stores into this pseudo. */
7686 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7688 rtx set = single_set (i2);
7690 if (set != 0 && SET_DEST (set) == reg)
7692 delete_address_reloads (i2, insn);
7693 /* This might be a basic block head,
7694 thus don't use delete_insn. */
7695 PUT_CODE (i2, NOTE);
7696 NOTE_SOURCE_FILE (i2) = 0;
7697 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7699 if (GET_CODE (i2) == CODE_LABEL
7700 || GET_CODE (i2) == JUMP_INSN)
7704 /* For the debugging info,
7705 say the pseudo lives in this reload reg. */
7706 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7707 alter_reg (REGNO (reg), -1);
7709 delete_address_reloads (output_reload_insn, insn);
7710 PUT_CODE (output_reload_insn, NOTE);
7711 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7712 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7716 /* We are going to delete DEAD_INSN. Recursively delete loads of
7717 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7718 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7720 delete_address_reloads (dead_insn, current_insn)
7721 rtx dead_insn, current_insn;
7723 rtx set = single_set (dead_insn);
7724 rtx set2, dst, prev, next;
7727 rtx dst = SET_DEST (set);
7728 if (GET_CODE (dst) == MEM)
7729 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7731 /* If we deleted the store from a reloaded post_{in,de}c expression,
7732 we can delete the matching adds. */
7733 prev = PREV_INSN (dead_insn);
7734 next = NEXT_INSN (dead_insn);
7735 if (! prev || ! next)
7737 set = single_set (next);
7738 set2 = single_set (prev);
7740 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7741 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7742 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7744 dst = SET_DEST (set);
7745 if (! rtx_equal_p (dst, SET_DEST (set2))
7746 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7747 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7748 || (INTVAL (XEXP (SET_SRC (set), 1))
7749 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7755 /* Subfunction of delete_address_reloads: process registers found in X. */
7757 delete_address_reloads_1 (dead_insn, x, current_insn)
7758 rtx dead_insn, x, current_insn;
7760 rtx prev, set, dst, i2;
7762 enum rtx_code code = GET_CODE (x);
7766 const char *fmt = GET_RTX_FORMAT (code);
7767 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7770 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7771 else if (fmt[i] == 'E')
7773 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7774 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7781 if (spill_reg_order[REGNO (x)] < 0)
7784 /* Scan backwards for the insn that sets x. This might be a way back due
7786 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7788 code = GET_CODE (prev);
7789 if (code == CODE_LABEL || code == JUMP_INSN)
7791 if (GET_RTX_CLASS (code) != 'i')
7793 if (reg_set_p (x, PATTERN (prev)))
7795 if (reg_referenced_p (x, PATTERN (prev)))
7798 if (! prev || INSN_UID (prev) < reload_first_uid)
7800 /* Check that PREV only sets the reload register. */
7801 set = single_set (prev);
7804 dst = SET_DEST (set);
7805 if (GET_CODE (dst) != REG
7806 || ! rtx_equal_p (dst, x))
7808 if (! reg_set_p (dst, PATTERN (dead_insn)))
7810 /* Check if DST was used in a later insn -
7811 it might have been inherited. */
7812 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7814 if (GET_CODE (i2) == CODE_LABEL)
7818 if (reg_referenced_p (dst, PATTERN (i2)))
7820 /* If there is a reference to the register in the current insn,
7821 it might be loaded in a non-inherited reload. If no other
7822 reload uses it, that means the register is set before
7824 if (i2 == current_insn)
7826 for (j = n_reloads - 1; j >= 0; j--)
7827 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7828 || reload_override_in[j] == dst)
7830 for (j = n_reloads - 1; j >= 0; j--)
7831 if (rld[j].in && rld[j].reg_rtx == dst)
7838 if (GET_CODE (i2) == JUMP_INSN)
7840 /* If DST is still live at CURRENT_INSN, check if it is used for
7841 any reload. Note that even if CURRENT_INSN sets DST, we still
7842 have to check the reloads. */
7843 if (i2 == current_insn)
7845 for (j = n_reloads - 1; j >= 0; j--)
7846 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7847 || reload_override_in[j] == dst)
7849 /* ??? We can't finish the loop here, because dst might be
7850 allocated to a pseudo in this block if no reload in this
7851 block needs any of the clsses containing DST - see
7852 spill_hard_reg. There is no easy way to tell this, so we
7853 have to scan till the end of the basic block. */
7855 if (reg_set_p (dst, PATTERN (i2)))
7859 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7860 reg_reloaded_contents[REGNO (dst)] = -1;
7861 /* Can't use delete_insn here because PREV might be a basic block head. */
7862 PUT_CODE (prev, NOTE);
7863 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
7864 NOTE_SOURCE_FILE (prev) = 0;
7867 /* Output reload-insns to reload VALUE into RELOADREG.
7868 VALUE is an autoincrement or autodecrement RTX whose operand
7869 is a register or memory location;
7870 so reloading involves incrementing that location.
7871 IN is either identical to VALUE, or some cheaper place to reload from.
7873 INC_AMOUNT is the number to increment or decrement by (always positive).
7874 This cannot be deduced from VALUE.
7876 Return the instruction that stores into RELOADREG. */
7879 inc_for_reload (reloadreg, in, value, inc_amount)
7884 /* REG or MEM to be copied and incremented. */
7885 rtx incloc = XEXP (value, 0);
7886 /* Nonzero if increment after copying. */
7887 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7893 rtx real_in = in == value ? XEXP (in, 0) : in;
7895 /* No hard register is equivalent to this register after
7896 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7897 we could inc/dec that register as well (maybe even using it for
7898 the source), but I'm not sure it's worth worrying about. */
7899 if (GET_CODE (incloc) == REG)
7900 reg_last_reload_reg[REGNO (incloc)] = 0;
7902 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7903 inc_amount = -inc_amount;
7905 inc = GEN_INT (inc_amount);
7907 /* If this is post-increment, first copy the location to the reload reg. */
7908 if (post && real_in != reloadreg)
7909 emit_insn (gen_move_insn (reloadreg, real_in));
7913 /* See if we can directly increment INCLOC. Use a method similar to
7914 that in gen_reload. */
7916 last = get_last_insn ();
7917 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7918 gen_rtx_PLUS (GET_MODE (incloc),
7921 code = recog_memoized (add_insn);
7924 extract_insn (add_insn);
7925 if (constrain_operands (1))
7927 /* If this is a pre-increment and we have incremented the value
7928 where it lives, copy the incremented value to RELOADREG to
7929 be used as an address. */
7932 emit_insn (gen_move_insn (reloadreg, incloc));
7937 delete_insns_since (last);
7940 /* If couldn't do the increment directly, must increment in RELOADREG.
7941 The way we do this depends on whether this is pre- or post-increment.
7942 For pre-increment, copy INCLOC to the reload register, increment it
7943 there, then save back. */
7947 if (in != reloadreg)
7948 emit_insn (gen_move_insn (reloadreg, real_in));
7949 emit_insn (gen_add2_insn (reloadreg, inc));
7950 store = emit_insn (gen_move_insn (incloc, reloadreg));
7955 Because this might be a jump insn or a compare, and because RELOADREG
7956 may not be available after the insn in an input reload, we must do
7957 the incrementation before the insn being reloaded for.
7959 We have already copied IN to RELOADREG. Increment the copy in
7960 RELOADREG, save that back, then decrement RELOADREG so it has
7961 the original value. */
7963 emit_insn (gen_add2_insn (reloadreg, inc));
7964 store = emit_insn (gen_move_insn (incloc, reloadreg));
7965 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7971 /* Return 1 if we are certain that the constraint-string STRING allows
7972 the hard register REG. Return 0 if we can't be sure of this. */
7975 constraint_accepts_reg_p (string, reg)
7980 int regno = true_regnum (reg);
7983 /* Initialize for first alternative. */
7985 /* Check that each alternative contains `g' or `r'. */
7987 switch (c = *string++)
7990 /* If an alternative lacks `g' or `r', we lose. */
7993 /* If an alternative lacks `g' or `r', we lose. */
7996 /* Initialize for next alternative. */
8001 /* Any general reg wins for this alternative. */
8002 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
8006 /* Any reg in specified class wins for this alternative. */
8008 enum reg_class class = REG_CLASS_FROM_LETTER (c);
8010 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
8016 /* INSN is a no-op; delete it.
8017 If this sets the return value of the function, we must keep a USE around,
8018 in case this is in a different basic block than the final USE. Otherwise,
8019 we could loose important register lifeness information on
8020 SMALL_REGISTER_CLASSES machines, where return registers might be used as
8021 spills: subsequent passes assume that spill registers are dead at the end
8023 VALUE must be the return value in such a case, NULL otherwise. */
8025 reload_cse_delete_noop_set (insn, value)
8030 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
8031 INSN_CODE (insn) = -1;
8032 REG_NOTES (insn) = NULL_RTX;
8036 PUT_CODE (insn, NOTE);
8037 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8038 NOTE_SOURCE_FILE (insn) = 0;
8042 /* See whether a single set SET is a noop. */
8044 reload_cse_noop_set_p (set)
8047 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
8050 /* Try to simplify INSN. */
8052 reload_cse_simplify (insn)
8055 rtx body = PATTERN (insn);
8057 if (GET_CODE (body) == SET)
8061 /* Simplify even if we may think it is a no-op.
8062 We may think a memory load of a value smaller than WORD_SIZE
8063 is redundant because we haven't taken into account possible
8064 implicit extension. reload_cse_simplify_set() will bring
8065 this out, so it's safer to simplify before we delete. */
8066 count += reload_cse_simplify_set (body, insn);
8068 if (!count && reload_cse_noop_set_p (body))
8070 rtx value = SET_DEST (body);
8071 if (! REG_FUNCTION_VALUE_P (SET_DEST (body)))
8073 reload_cse_delete_noop_set (insn, value);
8078 apply_change_group ();
8080 reload_cse_simplify_operands (insn);
8082 else if (GET_CODE (body) == PARALLEL)
8086 rtx value = NULL_RTX;
8088 /* If every action in a PARALLEL is a noop, we can delete
8089 the entire PARALLEL. */
8090 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8092 rtx part = XVECEXP (body, 0, i);
8093 if (GET_CODE (part) == SET)
8095 if (! reload_cse_noop_set_p (part))
8097 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
8101 value = SET_DEST (part);
8104 else if (GET_CODE (part) != CLOBBER)
8110 reload_cse_delete_noop_set (insn, value);
8111 /* We're done with this insn. */
8115 /* It's not a no-op, but we can try to simplify it. */
8116 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8117 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8118 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8121 apply_change_group ();
8123 reload_cse_simplify_operands (insn);
8127 /* Do a very simple CSE pass over the hard registers.
8129 This function detects no-op moves where we happened to assign two
8130 different pseudo-registers to the same hard register, and then
8131 copied one to the other. Reload will generate a useless
8132 instruction copying a register to itself.
8134 This function also detects cases where we load a value from memory
8135 into two different registers, and (if memory is more expensive than
8136 registers) changes it to simply copy the first register into the
8139 Another optimization is performed that scans the operands of each
8140 instruction to see whether the value is already available in a
8141 hard register. It then replaces the operand with the hard register
8142 if possible, much like an optional reload would. */
8145 reload_cse_regs_1 (first)
8151 init_alias_analysis ();
8153 for (insn = first; insn; insn = NEXT_INSN (insn))
8156 reload_cse_simplify (insn);
8158 cselib_process_insn (insn);
8162 end_alias_analysis ();
8166 /* Call cse / combine like post-reload optimization phases.
8167 FIRST is the first instruction. */
8169 reload_cse_regs (first)
8172 reload_cse_regs_1 (first);
8174 reload_cse_move2add (first);
8175 if (flag_expensive_optimizations)
8176 reload_cse_regs_1 (first);
8179 /* Try to simplify a single SET instruction. SET is the set pattern.
8180 INSN is the instruction it came from.
8181 This function only handles one case: if we set a register to a value
8182 which is not a register, we try to find that value in some other register
8183 and change the set into a register copy. */
8186 reload_cse_simplify_set (set, insn)
8193 enum reg_class dclass;
8196 struct elt_loc_list *l;
8197 #ifdef LOAD_EXTEND_OP
8198 enum rtx_code extend_op = NIL;
8201 dreg = true_regnum (SET_DEST (set));
8205 src = SET_SRC (set);
8206 if (side_effects_p (src) || true_regnum (src) >= 0)
8209 dclass = REGNO_REG_CLASS (dreg);
8211 #ifdef LOAD_EXTEND_OP
8212 /* When replacing a memory with a register, we need to honor assumptions
8213 that combine made wrt the contents of sign bits. We'll do this by
8214 generating an extend instruction instead of a reg->reg copy. Thus
8215 the destination must be a register that we can widen. */
8216 if (GET_CODE (src) == MEM
8217 && GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD
8218 && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != NIL
8219 && GET_CODE (SET_DEST (set)) != REG)
8223 /* If memory loads are cheaper than register copies, don't change them. */
8224 if (GET_CODE (src) == MEM)
8225 old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
8226 else if (CONSTANT_P (src))
8227 old_cost = rtx_cost (src, SET);
8228 else if (GET_CODE (src) == REG)
8229 old_cost = REGISTER_MOVE_COST (GET_MODE (src),
8230 REGNO_REG_CLASS (REGNO (src)), dclass);
8233 old_cost = rtx_cost (src, SET);
8235 val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0);
8238 for (l = val->locs; l; l = l->next)
8240 rtx this_rtx = l->loc;
8243 if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0))
8245 #ifdef LOAD_EXTEND_OP
8246 if (extend_op != NIL)
8248 HOST_WIDE_INT this_val;
8250 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
8251 constants, such as SYMBOL_REF, cannot be extended. */
8252 if (GET_CODE (this_rtx) != CONST_INT)
8255 this_val = INTVAL (this_rtx);
8259 this_val &= GET_MODE_MASK (GET_MODE (src));
8262 /* ??? In theory we're already extended. */
8263 if (this_val == trunc_int_for_mode (this_val, GET_MODE (src)))
8268 this_rtx = GEN_INT (this_val);
8271 this_cost = rtx_cost (this_rtx, SET);
8273 else if (GET_CODE (this_rtx) == REG)
8275 #ifdef LOAD_EXTEND_OP
8276 if (extend_op != NIL)
8278 this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx);
8279 this_cost = rtx_cost (this_rtx, SET);
8283 this_cost = REGISTER_MOVE_COST (GET_MODE (this_rtx),
8284 REGNO_REG_CLASS (REGNO (this_rtx)),
8290 /* If equal costs, prefer registers over anything else. That
8291 tends to lead to smaller instructions on some machines. */
8292 if (this_cost < old_cost
8293 || (this_cost == old_cost
8294 && GET_CODE (this_rtx) == REG
8295 && GET_CODE (SET_SRC (set)) != REG))
8297 #ifdef LOAD_EXTEND_OP
8298 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD
8299 && extend_op != NIL)
8301 rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set)));
8302 ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set));
8303 validate_change (insn, &SET_DEST (set), wide_dest, 1);
8307 validate_change (insn, &SET_SRC (set), copy_rtx (this_rtx), 1);
8308 old_cost = this_cost, did_change = 1;
8315 /* Try to replace operands in INSN with equivalent values that are already
8316 in registers. This can be viewed as optional reloading.
8318 For each non-register operand in the insn, see if any hard regs are
8319 known to be equivalent to that operand. Record the alternatives which
8320 can accept these hard registers. Among all alternatives, select the
8321 ones which are better or equal to the one currently matching, where
8322 "better" is in terms of '?' and '!' constraints. Among the remaining
8323 alternatives, select the one which replaces most operands with
8327 reload_cse_simplify_operands (insn)
8332 /* For each operand, all registers that are equivalent to it. */
8333 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
8335 const char *constraints[MAX_RECOG_OPERANDS];
8337 /* Vector recording how bad an alternative is. */
8338 int *alternative_reject;
8339 /* Vector recording how many registers can be introduced by choosing
8340 this alternative. */
8341 int *alternative_nregs;
8342 /* Array of vectors recording, for each operand and each alternative,
8343 which hard register to substitute, or -1 if the operand should be
8345 int *op_alt_regno[MAX_RECOG_OPERANDS];
8346 /* Array of alternatives, sorted in order of decreasing desirability. */
8347 int *alternative_order;
8348 rtx reg = gen_rtx_REG (VOIDmode, -1);
8350 extract_insn (insn);
8352 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8355 /* Figure out which alternative currently matches. */
8356 if (! constrain_operands (1))
8357 fatal_insn_not_found (insn);
8359 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8360 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8361 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8362 memset ((char *)alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
8363 memset ((char *)alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
8365 /* For each operand, find out which regs are equivalent. */
8366 for (i = 0; i < recog_data.n_operands; i++)
8369 struct elt_loc_list *l;
8371 CLEAR_HARD_REG_SET (equiv_regs[i]);
8373 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8374 right, so avoid the problem here. Likewise if we have a constant
8375 and the insn pattern doesn't tell us the mode we need. */
8376 if (GET_CODE (recog_data.operand[i]) == CODE_LABEL
8377 || (CONSTANT_P (recog_data.operand[i])
8378 && recog_data.operand_mode[i] == VOIDmode))
8381 v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0);
8385 for (l = v->locs; l; l = l->next)
8386 if (GET_CODE (l->loc) == REG)
8387 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
8390 for (i = 0; i < recog_data.n_operands; i++)
8392 enum machine_mode mode;
8396 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8397 for (j = 0; j < recog_data.n_alternatives; j++)
8398 op_alt_regno[i][j] = -1;
8400 p = constraints[i] = recog_data.constraints[i];
8401 mode = recog_data.operand_mode[i];
8403 /* Add the reject values for each alternative given by the constraints
8404 for this operand. */
8412 alternative_reject[j] += 3;
8414 alternative_reject[j] += 300;
8417 /* We won't change operands which are already registers. We
8418 also don't want to modify output operands. */
8419 regno = true_regnum (recog_data.operand[i]);
8421 || constraints[i][0] == '='
8422 || constraints[i][0] == '+')
8425 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8427 int class = (int) NO_REGS;
8429 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
8432 REGNO (reg) = regno;
8433 PUT_MODE (reg, mode);
8435 /* We found a register equal to this operand. Now look for all
8436 alternatives that can accept this register and have not been
8437 assigned a register they can use yet. */
8446 case '=': case '+': case '?':
8447 case '#': case '&': case '!':
8449 case '0': case '1': case '2': case '3': case '4':
8450 case '5': case '6': case '7': case '8': case '9':
8451 case 'm': case '<': case '>': case 'V': case 'o':
8452 case 'E': case 'F': case 'G': case 'H':
8453 case 's': case 'i': case 'n':
8454 case 'I': case 'J': case 'K': case 'L':
8455 case 'M': case 'N': case 'O': case 'P':
8457 /* These don't say anything we care about. */
8461 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8466 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
8469 case ',': case '\0':
8470 /* See if REGNO fits this alternative, and set it up as the
8471 replacement register if we don't have one for this
8472 alternative yet and the operand being replaced is not
8473 a cheap CONST_INT. */
8474 if (op_alt_regno[i][j] == -1
8475 && reg_fits_class_p (reg, class, 0, mode)
8476 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8477 || (rtx_cost (recog_data.operand[i], SET)
8478 > rtx_cost (reg, SET))))
8480 alternative_nregs[j]++;
8481 op_alt_regno[i][j] = regno;
8493 /* Record all alternatives which are better or equal to the currently
8494 matching one in the alternative_order array. */
8495 for (i = j = 0; i < recog_data.n_alternatives; i++)
8496 if (alternative_reject[i] <= alternative_reject[which_alternative])
8497 alternative_order[j++] = i;
8498 recog_data.n_alternatives = j;
8500 /* Sort it. Given a small number of alternatives, a dumb algorithm
8501 won't hurt too much. */
8502 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8505 int best_reject = alternative_reject[alternative_order[i]];
8506 int best_nregs = alternative_nregs[alternative_order[i]];
8509 for (j = i + 1; j < recog_data.n_alternatives; j++)
8511 int this_reject = alternative_reject[alternative_order[j]];
8512 int this_nregs = alternative_nregs[alternative_order[j]];
8514 if (this_reject < best_reject
8515 || (this_reject == best_reject && this_nregs < best_nregs))
8518 best_reject = this_reject;
8519 best_nregs = this_nregs;
8523 tmp = alternative_order[best];
8524 alternative_order[best] = alternative_order[i];
8525 alternative_order[i] = tmp;
8528 /* Substitute the operands as determined by op_alt_regno for the best
8530 j = alternative_order[0];
8532 for (i = 0; i < recog_data.n_operands; i++)
8534 enum machine_mode mode = recog_data.operand_mode[i];
8535 if (op_alt_regno[i][j] == -1)
8538 validate_change (insn, recog_data.operand_loc[i],
8539 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8542 for (i = recog_data.n_dups - 1; i >= 0; i--)
8544 int op = recog_data.dup_num[i];
8545 enum machine_mode mode = recog_data.operand_mode[op];
8547 if (op_alt_regno[op][j] == -1)
8550 validate_change (insn, recog_data.dup_loc[i],
8551 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8554 return apply_change_group ();
8557 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8559 This code might also be useful when reload gave up on reg+reg addresssing
8560 because of clashes between the return register and INDEX_REG_CLASS. */
8562 /* The maximum number of uses of a register we can keep track of to
8563 replace them with reg+reg addressing. */
8564 #define RELOAD_COMBINE_MAX_USES 6
8566 /* INSN is the insn where a register has ben used, and USEP points to the
8567 location of the register within the rtl. */
8568 struct reg_use { rtx insn, *usep; };
8570 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8571 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8572 indicates where it becomes live again.
8573 Otherwise, USE_INDEX is the index of the last encountered use of the
8574 register (which is first among these we have seen since we scan backwards),
8575 OFFSET contains the constant offset that is added to the register in
8576 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8577 last, of these uses.
8578 STORE_RUID is always meaningful if we only want to use a value in a
8579 register in a different place: it denotes the next insn in the insn
8580 stream (i.e. the last ecountered) that sets or clobbers the register. */
8583 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8588 } reg_state[FIRST_PSEUDO_REGISTER];
8590 /* Reverse linear uid. This is increased in reload_combine while scanning
8591 the instructions from last to first. It is used to set last_label_ruid
8592 and the store_ruid / use_ruid fields in reg_state. */
8593 static int reload_combine_ruid;
8595 #define LABEL_LIVE(LABEL) \
8596 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8602 int first_index_reg = -1;
8603 int last_index_reg = 0;
8606 int last_label_ruid;
8607 int min_labelno, n_labels;
8608 HARD_REG_SET ever_live_at_start, *label_live;
8610 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
8611 reload has already used it where appropriate, so there is no use in
8612 trying to generate it now. */
8613 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8616 /* To avoid wasting too much time later searching for an index register,
8617 determine the minimum and maximum index register numbers. */
8618 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8619 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
8621 if (first_index_reg == -1)
8622 first_index_reg = r;
8627 /* If no index register is available, we can quit now. */
8628 if (first_index_reg == -1)
8631 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8632 information is a bit fuzzy immediately after reload, but it's
8633 still good enough to determine which registers are live at a jump
8635 min_labelno = get_first_label_num ();
8636 n_labels = max_label_num () - min_labelno;
8637 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8638 CLEAR_HARD_REG_SET (ever_live_at_start);
8640 for (i = n_basic_blocks - 1; i >= 0; i--)
8642 insn = BLOCK_HEAD (i);
8643 if (GET_CODE (insn) == CODE_LABEL)
8647 REG_SET_TO_HARD_REG_SET (live,
8648 BASIC_BLOCK (i)->global_live_at_start);
8649 compute_use_by_pseudos (&live,
8650 BASIC_BLOCK (i)->global_live_at_start);
8651 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8652 IOR_HARD_REG_SET (ever_live_at_start, live);
8656 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8657 last_label_ruid = reload_combine_ruid = 0;
8658 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8660 reg_state[r].store_ruid = reload_combine_ruid;
8662 reg_state[r].use_index = -1;
8664 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8667 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8671 /* We cannot do our optimization across labels. Invalidating all the use
8672 information we have would be costly, so we just note where the label
8673 is and then later disable any optimization that would cross it. */
8674 if (GET_CODE (insn) == CODE_LABEL)
8675 last_label_ruid = reload_combine_ruid;
8676 else if (GET_CODE (insn) == BARRIER)
8677 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8678 if (! fixed_regs[r])
8679 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8681 if (! INSN_P (insn))
8684 reload_combine_ruid++;
8686 /* Look for (set (REGX) (CONST_INT))
8687 (set (REGX) (PLUS (REGX) (REGY)))
8689 ... (MEM (REGX)) ...
8691 (set (REGZ) (CONST_INT))
8693 ... (MEM (PLUS (REGZ) (REGY)))... .
8695 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8696 and that we know all uses of REGX before it dies. */
8697 set = single_set (insn);
8699 && GET_CODE (SET_DEST (set)) == REG
8700 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
8701 GET_MODE (SET_DEST (set)))
8703 && GET_CODE (SET_SRC (set)) == PLUS
8704 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
8705 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
8706 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
8708 rtx reg = SET_DEST (set);
8709 rtx plus = SET_SRC (set);
8710 rtx base = XEXP (plus, 1);
8711 rtx prev = prev_nonnote_insn (insn);
8712 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
8713 unsigned int regno = REGNO (reg);
8714 rtx const_reg = NULL_RTX;
8715 rtx reg_sum = NULL_RTX;
8717 /* Now, we need an index register.
8718 We'll set index_reg to this index register, const_reg to the
8719 register that is to be loaded with the constant
8720 (denoted as REGZ in the substitution illustration above),
8721 and reg_sum to the register-register that we want to use to
8722 substitute uses of REG (typically in MEMs) with.
8723 First check REG and BASE for being index registers;
8724 we can use them even if they are not dead. */
8725 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
8726 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8734 /* Otherwise, look for a free index register. Since we have
8735 checked above that neiter REG nor BASE are index registers,
8736 if we find anything at all, it will be different from these
8738 for (i = first_index_reg; i <= last_index_reg; i++)
8740 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8742 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
8743 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
8744 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
8746 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
8748 const_reg = index_reg;
8749 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
8755 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8756 (REGY), i.e. BASE, is not clobbered before the last use we'll
8759 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
8760 && rtx_equal_p (SET_DEST (prev_set), reg)
8761 && reg_state[regno].use_index >= 0
8762 && (reg_state[REGNO (base)].store_ruid
8763 <= reg_state[regno].use_ruid)
8768 /* Change destination register and, if necessary, the
8769 constant value in PREV, the constant loading instruction. */
8770 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
8771 if (reg_state[regno].offset != const0_rtx)
8772 validate_change (prev,
8773 &SET_SRC (prev_set),
8774 GEN_INT (INTVAL (SET_SRC (prev_set))
8775 + INTVAL (reg_state[regno].offset)),
8778 /* Now for every use of REG that we have recorded, replace REG
8780 for (i = reg_state[regno].use_index;
8781 i < RELOAD_COMBINE_MAX_USES; i++)
8782 validate_change (reg_state[regno].reg_use[i].insn,
8783 reg_state[regno].reg_use[i].usep,
8786 if (apply_change_group ())
8790 /* Delete the reg-reg addition. */
8791 PUT_CODE (insn, NOTE);
8792 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8793 NOTE_SOURCE_FILE (insn) = 0;
8795 if (reg_state[regno].offset != const0_rtx)
8796 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8798 for (np = ®_NOTES (prev); *np;)
8800 if (REG_NOTE_KIND (*np) == REG_EQUAL
8801 || REG_NOTE_KIND (*np) == REG_EQUIV)
8802 *np = XEXP (*np, 1);
8804 np = &XEXP (*np, 1);
8807 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8808 reg_state[REGNO (const_reg)].store_ruid
8809 = reload_combine_ruid;
8815 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
8817 if (GET_CODE (insn) == CALL_INSN)
8821 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8822 if (call_used_regs[r])
8824 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8825 reg_state[r].store_ruid = reload_combine_ruid;
8828 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
8829 link = XEXP (link, 1))
8831 rtx usage_rtx = XEXP (XEXP (link, 0), 0);
8832 if (GET_CODE (usage_rtx) == REG)
8835 unsigned int start_reg = REGNO (usage_rtx);
8836 unsigned int num_regs =
8837 HARD_REGNO_NREGS (start_reg, GET_MODE (usage_rtx));
8838 unsigned int end_reg = start_reg + num_regs - 1;
8839 for (i = start_reg; i <= end_reg; i++)
8840 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
8842 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8843 reg_state[i].store_ruid = reload_combine_ruid;
8846 reg_state[i].use_index = -1;
8851 else if (GET_CODE (insn) == JUMP_INSN
8852 && GET_CODE (PATTERN (insn)) != RETURN)
8854 /* Non-spill registers might be used at the call destination in
8855 some unknown fashion, so we have to mark the unknown use. */
8858 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
8859 && JUMP_LABEL (insn))
8860 live = &LABEL_LIVE (JUMP_LABEL (insn));
8862 live = &ever_live_at_start;
8864 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8865 if (TEST_HARD_REG_BIT (*live, i))
8866 reg_state[i].use_index = -1;
8869 reload_combine_note_use (&PATTERN (insn), insn);
8870 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8872 if (REG_NOTE_KIND (note) == REG_INC
8873 && GET_CODE (XEXP (note, 0)) == REG)
8875 int regno = REGNO (XEXP (note, 0));
8877 reg_state[regno].store_ruid = reload_combine_ruid;
8878 reg_state[regno].use_index = -1;
8886 /* Check if DST is a register or a subreg of a register; if it is,
8887 update reg_state[regno].store_ruid and reg_state[regno].use_index
8888 accordingly. Called via note_stores from reload_combine. */
8891 reload_combine_note_store (dst, set, data)
8893 void *data ATTRIBUTE_UNUSED;
8897 enum machine_mode mode = GET_MODE (dst);
8899 if (GET_CODE (dst) == SUBREG)
8901 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
8902 GET_MODE (SUBREG_REG (dst)),
8905 dst = SUBREG_REG (dst);
8907 if (GET_CODE (dst) != REG)
8909 regno += REGNO (dst);
8911 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8912 careful with registers / register parts that are not full words.
8914 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8915 if (GET_CODE (set) != SET
8916 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
8917 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
8918 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
8920 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8922 reg_state[i].use_index = -1;
8923 reg_state[i].store_ruid = reload_combine_ruid;
8928 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8930 reg_state[i].store_ruid = reload_combine_ruid;
8931 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8936 /* XP points to a piece of rtl that has to be checked for any uses of
8938 *XP is the pattern of INSN, or a part of it.
8939 Called from reload_combine, and recursively by itself. */
8941 reload_combine_note_use (xp, insn)
8945 enum rtx_code code = x->code;
8948 rtx offset = const0_rtx; /* For the REG case below. */
8953 if (GET_CODE (SET_DEST (x)) == REG)
8955 reload_combine_note_use (&SET_SRC (x), insn);
8961 /* If this is the USE of a return value, we can't change it. */
8962 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
8964 /* Mark the return register as used in an unknown fashion. */
8965 rtx reg = XEXP (x, 0);
8966 int regno = REGNO (reg);
8967 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
8969 while (--nregs >= 0)
8970 reg_state[regno + nregs].use_index = -1;
8976 if (GET_CODE (SET_DEST (x)) == REG)
8981 /* We are interested in (plus (reg) (const_int)) . */
8982 if (GET_CODE (XEXP (x, 0)) != REG
8983 || GET_CODE (XEXP (x, 1)) != CONST_INT)
8985 offset = XEXP (x, 1);
8990 int regno = REGNO (x);
8994 /* Some spurious USEs of pseudo registers might remain.
8995 Just ignore them. */
8996 if (regno >= FIRST_PSEUDO_REGISTER)
8999 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x));
9001 /* We can't substitute into multi-hard-reg uses. */
9004 while (--nregs >= 0)
9005 reg_state[regno + nregs].use_index = -1;
9009 /* If this register is already used in some unknown fashion, we
9011 If we decrement the index from zero to -1, we can't store more
9012 uses, so this register becomes used in an unknown fashion. */
9013 use_index = --reg_state[regno].use_index;
9017 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
9019 /* We have found another use for a register that is already
9020 used later. Check if the offsets match; if not, mark the
9021 register as used in an unknown fashion. */
9022 if (! rtx_equal_p (offset, reg_state[regno].offset))
9024 reg_state[regno].use_index = -1;
9030 /* This is the first use of this register we have seen since we
9031 marked it as dead. */
9032 reg_state[regno].offset = offset;
9033 reg_state[regno].use_ruid = reload_combine_ruid;
9035 reg_state[regno].reg_use[use_index].insn = insn;
9036 reg_state[regno].reg_use[use_index].usep = xp;
9044 /* Recursively process the components of X. */
9045 fmt = GET_RTX_FORMAT (code);
9046 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9049 reload_combine_note_use (&XEXP (x, i), insn);
9050 else if (fmt[i] == 'E')
9052 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9053 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9058 /* See if we can reduce the cost of a constant by replacing a move
9059 with an add. We track situations in which a register is set to a
9060 constant or to a register plus a constant. */
9061 /* We cannot do our optimization across labels. Invalidating all the
9062 information about register contents we have would be costly, so we
9063 use move2add_last_label_luid to note where the label is and then
9064 later disable any optimization that would cross it.
9065 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9066 reg_set_luid[n] is greater than last_label_luid[n] . */
9067 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9069 /* If reg_base_reg[n] is negative, register n has been set to
9070 reg_offset[n] in mode reg_mode[n] .
9071 If reg_base_reg[n] is non-negative, register n has been set to the
9072 sum of reg_offset[n] and the value of register reg_base_reg[n]
9073 before reg_set_luid[n], calculated in mode reg_mode[n] . */
9074 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
9075 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9076 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9078 /* move2add_luid is linearily increased while scanning the instructions
9079 from first to last. It is used to set reg_set_luid in
9080 reload_cse_move2add and move2add_note_store. */
9081 static int move2add_luid;
9083 /* move2add_last_label_luid is set whenever a label is found. Labels
9084 invalidate all previously collected reg_offset data. */
9085 static int move2add_last_label_luid;
9087 /* Generate a CONST_INT and force it in the range of MODE. */
9089 static HOST_WIDE_INT
9090 sext_for_mode (mode, value)
9091 enum machine_mode mode;
9092 HOST_WIDE_INT value;
9094 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
9095 int width = GET_MODE_BITSIZE (mode);
9097 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
9099 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
9100 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
9101 cval |= (HOST_WIDE_INT) -1 << width;
9106 /* ??? We don't know how zero / sign extension is handled, hence we
9107 can't go from a narrower to a wider mode. */
9108 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
9109 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
9110 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
9111 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \
9112 GET_MODE_BITSIZE (INMODE))))
9115 reload_cse_move2add (first)
9121 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9122 reg_set_luid[i] = 0;
9124 move2add_last_label_luid = 0;
9126 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
9130 if (GET_CODE (insn) == CODE_LABEL)
9132 move2add_last_label_luid = move2add_luid;
9133 /* We're going to increment move2add_luid twice after a
9134 label, so that we can use move2add_last_label_luid + 1 as
9135 the luid for constants. */
9139 if (! INSN_P (insn))
9141 pat = PATTERN (insn);
9142 /* For simplicity, we only perform this optimization on
9143 straightforward SETs. */
9144 if (GET_CODE (pat) == SET
9145 && GET_CODE (SET_DEST (pat)) == REG)
9147 rtx reg = SET_DEST (pat);
9148 int regno = REGNO (reg);
9149 rtx src = SET_SRC (pat);
9151 /* Check if we have valid information on the contents of this
9152 register in the mode of REG. */
9153 if (reg_set_luid[regno] > move2add_last_label_luid
9154 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno]))
9156 /* Try to transform (set (REGX) (CONST_INT A))
9158 (set (REGX) (CONST_INT B))
9160 (set (REGX) (CONST_INT A))
9162 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9164 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
9167 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9169 - reg_offset[regno]));
9170 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9171 use (set (reg) (reg)) instead.
9172 We don't delete this insn, nor do we convert it into a
9173 note, to avoid losing register notes or the return
9174 value flag. jump2 already knowns how to get rid of
9176 if (new_src == const0_rtx)
9177 success = validate_change (insn, &SET_SRC (pat), reg, 0);
9178 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
9179 && have_add2_insn (reg, new_src))
9180 success = validate_change (insn, &PATTERN (insn),
9181 gen_add2_insn (reg, new_src), 0);
9182 reg_set_luid[regno] = move2add_luid;
9183 reg_mode[regno] = GET_MODE (reg);
9184 reg_offset[regno] = INTVAL (src);
9188 /* Try to transform (set (REGX) (REGY))
9189 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9192 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9195 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9197 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9198 else if (GET_CODE (src) == REG
9199 && reg_set_luid[regno] == reg_set_luid[REGNO (src)]
9200 && reg_base_reg[regno] == reg_base_reg[REGNO (src)]
9201 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg),
9202 reg_mode[REGNO (src)]))
9204 rtx next = next_nonnote_insn (insn);
9207 set = single_set (next);
9209 && SET_DEST (set) == reg
9210 && GET_CODE (SET_SRC (set)) == PLUS
9211 && XEXP (SET_SRC (set), 0) == reg
9212 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9214 rtx src3 = XEXP (SET_SRC (set), 1);
9215 HOST_WIDE_INT added_offset = INTVAL (src3);
9216 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)];
9217 HOST_WIDE_INT regno_offset = reg_offset[regno];
9218 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9224 if (new_src == const0_rtx)
9225 /* See above why we create (set (reg) (reg)) here. */
9227 = validate_change (next, &SET_SRC (set), reg, 0);
9228 else if ((rtx_cost (new_src, PLUS)
9229 < COSTS_N_INSNS (1) + rtx_cost (src3, SET))
9230 && have_add2_insn (reg, new_src))
9232 = validate_change (next, &PATTERN (next),
9233 gen_add2_insn (reg, new_src), 0);
9236 /* INSN might be the first insn in a basic block
9237 if the preceding insn is a conditional jump
9238 or a possible-throwing call. */
9239 PUT_CODE (insn, NOTE);
9240 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9241 NOTE_SOURCE_FILE (insn) = 0;
9244 reg_mode[regno] = GET_MODE (reg);
9245 reg_offset[regno] = sext_for_mode (GET_MODE (reg),
9254 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9256 if (REG_NOTE_KIND (note) == REG_INC
9257 && GET_CODE (XEXP (note, 0)) == REG)
9259 /* Reset the information about this register. */
9260 int regno = REGNO (XEXP (note, 0));
9261 if (regno < FIRST_PSEUDO_REGISTER)
9262 reg_set_luid[regno] = 0;
9265 note_stores (PATTERN (insn), move2add_note_store, NULL);
9266 /* If this is a CALL_INSN, all call used registers are stored with
9268 if (GET_CODE (insn) == CALL_INSN)
9270 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9272 if (call_used_regs[i])
9273 /* Reset the information about this register. */
9274 reg_set_luid[i] = 0;
9280 /* SET is a SET or CLOBBER that sets DST.
9281 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9282 Called from reload_cse_move2add via note_stores. */
9285 move2add_note_store (dst, set, data)
9287 void *data ATTRIBUTE_UNUSED;
9289 unsigned int regno = 0;
9291 enum machine_mode mode = GET_MODE (dst);
9293 if (GET_CODE (dst) == SUBREG)
9295 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
9296 GET_MODE (SUBREG_REG (dst)),
9299 dst = SUBREG_REG (dst);
9302 /* Some targets do argument pushes without adding REG_INC notes. */
9304 if (GET_CODE (dst) == MEM)
9306 dst = XEXP (dst, 0);
9307 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_DEC
9308 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC)
9309 reg_set_luid[REGNO (XEXP (dst, 0))] = 0;
9312 if (GET_CODE (dst) != REG)
9315 regno += REGNO (dst);
9317 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9318 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9319 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9320 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9322 rtx src = SET_SRC (set);
9324 HOST_WIDE_INT offset;
9326 /* This may be different from mode, if SET_DEST (set) is a
9328 enum machine_mode dst_mode = GET_MODE (dst);
9330 switch (GET_CODE (src))
9333 if (GET_CODE (XEXP (src, 0)) == REG)
9335 base_reg = XEXP (src, 0);
9337 if (GET_CODE (XEXP (src, 1)) == CONST_INT)
9338 offset = INTVAL (XEXP (src, 1));
9339 else if (GET_CODE (XEXP (src, 1)) == REG
9340 && (reg_set_luid[REGNO (XEXP (src, 1))]
9341 > move2add_last_label_luid)
9342 && (MODES_OK_FOR_MOVE2ADD
9343 (dst_mode, reg_mode[REGNO (XEXP (src, 1))])))
9345 if (reg_base_reg[REGNO (XEXP (src, 1))] < 0)
9346 offset = reg_offset[REGNO (XEXP (src, 1))];
9347 /* Maybe the first register is known to be a
9349 else if (reg_set_luid[REGNO (base_reg)]
9350 > move2add_last_label_luid
9351 && (MODES_OK_FOR_MOVE2ADD
9352 (dst_mode, reg_mode[REGNO (XEXP (src, 1))]))
9353 && reg_base_reg[REGNO (base_reg)] < 0)
9355 offset = reg_offset[REGNO (base_reg)];
9356 base_reg = XEXP (src, 1);
9375 /* Start tracking the register as a constant. */
9376 reg_base_reg[regno] = -1;
9377 reg_offset[regno] = INTVAL (SET_SRC (set));
9378 /* We assign the same luid to all registers set to constants. */
9379 reg_set_luid[regno] = move2add_last_label_luid + 1;
9380 reg_mode[regno] = mode;
9385 /* Invalidate the contents of the register. */
9386 reg_set_luid[regno] = 0;
9390 base_regno = REGNO (base_reg);
9391 /* If information about the base register is not valid, set it
9392 up as a new base register, pretending its value is known
9393 starting from the current insn. */
9394 if (reg_set_luid[base_regno] <= move2add_last_label_luid)
9396 reg_base_reg[base_regno] = base_regno;
9397 reg_offset[base_regno] = 0;
9398 reg_set_luid[base_regno] = move2add_luid;
9399 reg_mode[base_regno] = mode;
9401 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode,
9402 reg_mode[base_regno]))
9405 reg_mode[regno] = mode;
9407 /* Copy base information from our base register. */
9408 reg_set_luid[regno] = reg_set_luid[base_regno];
9409 reg_base_reg[regno] = reg_base_reg[base_regno];
9411 /* Compute the sum of the offsets or constants. */
9412 reg_offset[regno] = sext_for_mode (dst_mode,
9414 + reg_offset[base_regno]);
9418 unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode);
9420 for (i = regno; i < endregno; i++)
9421 /* Reset the information about this register. */
9422 reg_set_luid[i] = 0;
9428 add_auto_inc_notes (insn, x)
9432 enum rtx_code code = GET_CODE (x);
9436 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9439 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9443 /* Scan all the operand sub-expressions. */
9444 fmt = GET_RTX_FORMAT (code);
9445 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9448 add_auto_inc_notes (insn, XEXP (x, i));
9449 else if (fmt[i] == 'E')
9450 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9451 add_auto_inc_notes (insn, XVECEXP (x, i, j));
9456 /* Copy EH notes from an insn to its reloads. */
9458 copy_eh_notes (insn, x)
9462 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
9465 for (; x != 0; x = NEXT_INSN (x))
9467 if (may_trap_p (PATTERN (x)))
9469 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
9475 /* This is used by reload pass, that does emit some instructions after
9476 abnormal calls moving basic block end, but in fact it wants to emit
9477 them on the edge. Looks for abnormal call edges, find backward the
9478 proper call and fix the damage.
9480 Similar handle instructions throwing exceptions internally. */
9482 fixup_abnormal_edges ()
9485 bool inserted = false;
9487 for (i = 0; i < n_basic_blocks; i++)
9489 basic_block bb = BASIC_BLOCK (i);
9492 /* Look for cases we are interested in - an calls or instructions causing
9494 for (e = bb->succ; e; e = e->succ_next)
9496 if (e->flags & EDGE_ABNORMAL_CALL)
9498 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
9499 == (EDGE_ABNORMAL | EDGE_EH))
9502 if (e && GET_CODE (bb->end) != CALL_INSN && !can_throw_internal (bb->end))
9506 for (e = bb->succ; e; e = e->succ_next)
9507 if (e->flags & EDGE_FALLTHRU)
9509 /* Get past the new insns generated. Allow notes, as the insns may
9510 be already deleted. */
9511 while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE)
9512 && !can_throw_internal (insn)
9513 && insn != bb->head)
9514 insn = PREV_INSN (insn);
9515 if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn))
9519 insn = NEXT_INSN (insn);
9520 while (insn && GET_CODE (insn) == INSN)
9522 next = NEXT_INSN (insn);
9523 insert_insn_on_edge (PATTERN (insn), e);
9524 flow_delete_insn (insn);
9530 commit_edge_insertions ();
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