1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "addresses.h"
39 #include "basic-block.h"
52 /* This file contains the reload pass of the compiler, which is
53 run after register allocation has been done. It checks that
54 each insn is valid (operands required to be in registers really
55 are in registers of the proper class) and fixes up invalid ones
56 by copying values temporarily into registers for the insns
59 The results of register allocation are described by the vector
60 reg_renumber; the insns still contain pseudo regs, but reg_renumber
61 can be used to find which hard reg, if any, a pseudo reg is in.
63 The technique we always use is to free up a few hard regs that are
64 called ``reload regs'', and for each place where a pseudo reg
65 must be in a hard reg, copy it temporarily into one of the reload regs.
67 Reload regs are allocated locally for every instruction that needs
68 reloads. When there are pseudos which are allocated to a register that
69 has been chosen as a reload reg, such pseudos must be ``spilled''.
70 This means that they go to other hard regs, or to stack slots if no other
71 available hard regs can be found. Spilling can invalidate more
72 insns, requiring additional need for reloads, so we must keep checking
73 until the process stabilizes.
75 For machines with different classes of registers, we must keep track
76 of the register class needed for each reload, and make sure that
77 we allocate enough reload registers of each class.
79 The file reload.c contains the code that checks one insn for
80 validity and reports the reloads that it needs. This file
81 is in charge of scanning the entire rtl code, accumulating the
82 reload needs, spilling, assigning reload registers to use for
83 fixing up each insn, and generating the new insns to copy values
84 into the reload registers. */
86 /* During reload_as_needed, element N contains a REG rtx for the hard reg
87 into which reg N has been reloaded (perhaps for a previous insn). */
88 static rtx *reg_last_reload_reg;
90 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
91 for an output reload that stores into reg N. */
92 static regset_head reg_has_output_reload;
94 /* Indicates which hard regs are reload-registers for an output reload
95 in the current insn. */
96 static HARD_REG_SET reg_is_output_reload;
98 /* Element N is the constant value to which pseudo reg N is equivalent,
99 or zero if pseudo reg N is not equivalent to a constant.
100 find_reloads looks at this in order to replace pseudo reg N
101 with the constant it stands for. */
102 rtx *reg_equiv_constant;
104 /* Element N is an invariant value to which pseudo reg N is equivalent.
105 eliminate_regs_in_insn uses this to replace pseudos in particular
107 rtx *reg_equiv_invariant;
109 /* Element N is a memory location to which pseudo reg N is equivalent,
110 prior to any register elimination (such as frame pointer to stack
111 pointer). Depending on whether or not it is a valid address, this value
112 is transferred to either reg_equiv_address or reg_equiv_mem. */
113 rtx *reg_equiv_memory_loc;
115 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
116 collector can keep track of what is inside. */
117 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
119 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
120 This is used when the address is not valid as a memory address
121 (because its displacement is too big for the machine.) */
122 rtx *reg_equiv_address;
124 /* Element N is the memory slot to which pseudo reg N is equivalent,
125 or zero if pseudo reg N is not equivalent to a memory slot. */
128 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
129 alternate representations of the location of pseudo reg N. */
130 rtx *reg_equiv_alt_mem_list;
132 /* Widest width in which each pseudo reg is referred to (via subreg). */
133 static unsigned int *reg_max_ref_width;
135 /* Element N is the list of insns that initialized reg N from its equivalent
136 constant or memory slot. */
138 int reg_equiv_init_size;
140 /* Vector to remember old contents of reg_renumber before spilling. */
141 static short *reg_old_renumber;
143 /* During reload_as_needed, element N contains the last pseudo regno reloaded
144 into hard register N. If that pseudo reg occupied more than one register,
145 reg_reloaded_contents points to that pseudo for each spill register in
146 use; all of these must remain set for an inheritance to occur. */
147 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
149 /* During reload_as_needed, element N contains the insn for which
150 hard register N was last used. Its contents are significant only
151 when reg_reloaded_valid is set for this register. */
152 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
154 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
155 static HARD_REG_SET reg_reloaded_valid;
156 /* Indicate if the register was dead at the end of the reload.
157 This is only valid if reg_reloaded_contents is set and valid. */
158 static HARD_REG_SET reg_reloaded_dead;
160 /* Indicate whether the register's current value is one that is not
161 safe to retain across a call, even for registers that are normally
162 call-saved. This is only meaningful for members of reg_reloaded_valid. */
163 static HARD_REG_SET reg_reloaded_call_part_clobbered;
165 /* Number of spill-regs so far; number of valid elements of spill_regs. */
168 /* In parallel with spill_regs, contains REG rtx's for those regs.
169 Holds the last rtx used for any given reg, or 0 if it has never
170 been used for spilling yet. This rtx is reused, provided it has
172 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
174 /* In parallel with spill_regs, contains nonzero for a spill reg
175 that was stored after the last time it was used.
176 The precise value is the insn generated to do the store. */
177 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
179 /* This is the register that was stored with spill_reg_store. This is a
180 copy of reload_out / reload_out_reg when the value was stored; if
181 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
182 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
184 /* This table is the inverse mapping of spill_regs:
185 indexed by hard reg number,
186 it contains the position of that reg in spill_regs,
187 or -1 for something that is not in spill_regs.
189 ?!? This is no longer accurate. */
190 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
192 /* This reg set indicates registers that can't be used as spill registers for
193 the currently processed insn. These are the hard registers which are live
194 during the insn, but not allocated to pseudos, as well as fixed
196 static HARD_REG_SET bad_spill_regs;
198 /* These are the hard registers that can't be used as spill register for any
199 insn. This includes registers used for user variables and registers that
200 we can't eliminate. A register that appears in this set also can't be used
201 to retry register allocation. */
202 static HARD_REG_SET bad_spill_regs_global;
204 /* Describes order of use of registers for reloading
205 of spilled pseudo-registers. `n_spills' is the number of
206 elements that are actually valid; new ones are added at the end.
208 Both spill_regs and spill_reg_order are used on two occasions:
209 once during find_reload_regs, where they keep track of the spill registers
210 for a single insn, but also during reload_as_needed where they show all
211 the registers ever used by reload. For the latter case, the information
212 is calculated during finish_spills. */
213 static short spill_regs[FIRST_PSEUDO_REGISTER];
215 /* This vector of reg sets indicates, for each pseudo, which hard registers
216 may not be used for retrying global allocation because the register was
217 formerly spilled from one of them. If we allowed reallocating a pseudo to
218 a register that it was already allocated to, reload might not
220 static HARD_REG_SET *pseudo_previous_regs;
222 /* This vector of reg sets indicates, for each pseudo, which hard
223 registers may not be used for retrying global allocation because they
224 are used as spill registers during one of the insns in which the
226 static HARD_REG_SET *pseudo_forbidden_regs;
228 /* All hard regs that have been used as spill registers for any insn are
229 marked in this set. */
230 static HARD_REG_SET used_spill_regs;
232 /* Index of last register assigned as a spill register. We allocate in
233 a round-robin fashion. */
234 static int last_spill_reg;
236 /* Nonzero if indirect addressing is supported on the machine; this means
237 that spilling (REG n) does not require reloading it into a register in
238 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
239 value indicates the level of indirect addressing supported, e.g., two
240 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
242 static char spill_indirect_levels;
244 /* Nonzero if indirect addressing is supported when the innermost MEM is
245 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
246 which these are valid is the same as spill_indirect_levels, above. */
247 char indirect_symref_ok;
249 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
250 char double_reg_address_ok;
252 /* Record the stack slot for each spilled hard register. */
253 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
255 /* Width allocated so far for that stack slot. */
256 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
258 /* Record which pseudos needed to be spilled. */
259 static regset_head spilled_pseudos;
261 /* Record which pseudos changed their allocation in finish_spills. */
262 static regset_head changed_allocation_pseudos;
264 /* Used for communication between order_regs_for_reload and count_pseudo.
265 Used to avoid counting one pseudo twice. */
266 static regset_head pseudos_counted;
268 /* First uid used by insns created by reload in this function.
269 Used in find_equiv_reg. */
270 int reload_first_uid;
272 /* Flag set by local-alloc or global-alloc if anything is live in
273 a call-clobbered reg across calls. */
274 int caller_save_needed;
276 /* Set to 1 while reload_as_needed is operating.
277 Required by some machines to handle any generated moves differently. */
278 int reload_in_progress = 0;
280 /* These arrays record the insn_code of insns that may be needed to
281 perform input and output reloads of special objects. They provide a
282 place to pass a scratch register. */
283 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
284 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
286 /* This obstack is used for allocation of rtl during register elimination.
287 The allocated storage can be freed once find_reloads has processed the
289 static struct obstack reload_obstack;
291 /* Points to the beginning of the reload_obstack. All insn_chain structures
292 are allocated first. */
293 static char *reload_startobj;
295 /* The point after all insn_chain structures. Used to quickly deallocate
296 memory allocated in copy_reloads during calculate_needs_all_insns. */
297 static char *reload_firstobj;
299 /* This points before all local rtl generated by register elimination.
300 Used to quickly free all memory after processing one insn. */
301 static char *reload_insn_firstobj;
303 /* List of insn_chain instructions, one for every insn that reload needs to
305 struct insn_chain *reload_insn_chain;
307 /* List of all insns needing reloads. */
308 static struct insn_chain *insns_need_reload;
310 /* This structure is used to record information about register eliminations.
311 Each array entry describes one possible way of eliminating a register
312 in favor of another. If there is more than one way of eliminating a
313 particular register, the most preferred should be specified first. */
317 int from; /* Register number to be eliminated. */
318 int to; /* Register number used as replacement. */
319 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
320 int can_eliminate; /* Nonzero if this elimination can be done. */
321 int can_eliminate_previous; /* Value returned by TARGET_CAN_ELIMINATE
322 target hook in previous scan over insns
324 HOST_WIDE_INT offset; /* Current offset between the two regs. */
325 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
326 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
327 rtx from_rtx; /* REG rtx for the register to be eliminated.
328 We cannot simply compare the number since
329 we might then spuriously replace a hard
330 register corresponding to a pseudo
331 assigned to the reg to be eliminated. */
332 rtx to_rtx; /* REG rtx for the replacement. */
335 static struct elim_table *reg_eliminate = 0;
337 /* This is an intermediate structure to initialize the table. It has
338 exactly the members provided by ELIMINABLE_REGS. */
339 static const struct elim_table_1
343 } reg_eliminate_1[] =
345 /* If a set of eliminable registers was specified, define the table from it.
346 Otherwise, default to the normal case of the frame pointer being
347 replaced by the stack pointer. */
349 #ifdef ELIMINABLE_REGS
352 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
355 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
357 /* Record the number of pending eliminations that have an offset not equal
358 to their initial offset. If nonzero, we use a new copy of each
359 replacement result in any insns encountered. */
360 int num_not_at_initial_offset;
362 /* Count the number of registers that we may be able to eliminate. */
363 static int num_eliminable;
364 /* And the number of registers that are equivalent to a constant that
365 can be eliminated to frame_pointer / arg_pointer + constant. */
366 static int num_eliminable_invariants;
368 /* For each label, we record the offset of each elimination. If we reach
369 a label by more than one path and an offset differs, we cannot do the
370 elimination. This information is indexed by the difference of the
371 number of the label and the first label number. We can't offset the
372 pointer itself as this can cause problems on machines with segmented
373 memory. The first table is an array of flags that records whether we
374 have yet encountered a label and the second table is an array of arrays,
375 one entry in the latter array for each elimination. */
377 static int first_label_num;
378 static char *offsets_known_at;
379 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
381 /* Stack of addresses where an rtx has been changed. We can undo the
382 changes by popping items off the stack and restoring the original
383 value at each location.
385 We use this simplistic undo capability rather than copy_rtx as copy_rtx
386 will not make a deep copy of a normally sharable rtx, such as
387 (const (plus (symbol_ref) (const_int))). If such an expression appears
388 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
389 rtx expression would be changed. See PR 42431. */
393 DEF_VEC_ALLOC_P(rtx_p,heap);
394 static VEC(rtx_p,heap) *substitute_stack;
396 /* Number of labels in the current function. */
398 static int num_labels;
400 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
401 static void maybe_fix_stack_asms (void);
402 static void copy_reloads (struct insn_chain *);
403 static void calculate_needs_all_insns (int);
404 static int find_reg (struct insn_chain *, int);
405 static void find_reload_regs (struct insn_chain *);
406 static void select_reload_regs (void);
407 static void delete_caller_save_insns (void);
409 static void spill_failure (rtx, enum reg_class);
410 static void count_spilled_pseudo (int, int, int);
411 static void delete_dead_insn (rtx);
412 static void alter_reg (int, int, bool);
413 static void set_label_offsets (rtx, rtx, int);
414 static void check_eliminable_occurrences (rtx);
415 static void elimination_effects (rtx, enum machine_mode);
416 static int eliminate_regs_in_insn (rtx, int);
417 static void update_eliminable_offsets (void);
418 static void mark_not_eliminable (rtx, const_rtx, void *);
419 static void set_initial_elim_offsets (void);
420 static bool verify_initial_elim_offsets (void);
421 static void set_initial_label_offsets (void);
422 static void set_offsets_for_label (rtx);
423 static void init_elim_table (void);
424 static void update_eliminables (HARD_REG_SET *);
425 static void spill_hard_reg (unsigned int, int);
426 static int finish_spills (int);
427 static void scan_paradoxical_subregs (rtx);
428 static void count_pseudo (int);
429 static void order_regs_for_reload (struct insn_chain *);
430 static void reload_as_needed (int);
431 static void forget_old_reloads_1 (rtx, const_rtx, void *);
432 static void forget_marked_reloads (regset);
433 static int reload_reg_class_lower (const void *, const void *);
434 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
436 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
438 static int reload_reg_free_p (unsigned int, int, enum reload_type);
439 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
441 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
443 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
444 static int allocate_reload_reg (struct insn_chain *, int, int);
445 static int conflicts_with_override (rtx);
446 static void failed_reload (rtx, int);
447 static int set_reload_reg (int, int);
448 static void choose_reload_regs_init (struct insn_chain *, rtx *);
449 static void choose_reload_regs (struct insn_chain *);
450 static void merge_assigned_reloads (rtx);
451 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
453 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
455 static void do_input_reload (struct insn_chain *, struct reload *, int);
456 static void do_output_reload (struct insn_chain *, struct reload *, int);
457 static void emit_reload_insns (struct insn_chain *);
458 static void delete_output_reload (rtx, int, int, rtx);
459 static void delete_address_reloads (rtx, rtx);
460 static void delete_address_reloads_1 (rtx, rtx, rtx);
461 static rtx inc_for_reload (rtx, rtx, rtx, int);
463 static void add_auto_inc_notes (rtx, rtx);
465 static void substitute (rtx *, const_rtx, rtx);
466 static bool gen_reload_chain_without_interm_reg_p (int, int);
467 static int reloads_conflict (int, int);
468 static rtx gen_reload (rtx, rtx, int, enum reload_type);
469 static rtx emit_insn_if_valid_for_reload (rtx);
471 /* Initialize the reload pass. This is called at the beginning of compilation
472 and may be called again if the target is reinitialized. */
479 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
480 Set spill_indirect_levels to the number of levels such addressing is
481 permitted, zero if it is not permitted at all. */
484 = gen_rtx_MEM (Pmode,
487 LAST_VIRTUAL_REGISTER + 1),
489 spill_indirect_levels = 0;
491 while (memory_address_p (QImode, tem))
493 spill_indirect_levels++;
494 tem = gen_rtx_MEM (Pmode, tem);
497 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
499 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
500 indirect_symref_ok = memory_address_p (QImode, tem);
502 /* See if reg+reg is a valid (and offsettable) address. */
504 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
506 tem = gen_rtx_PLUS (Pmode,
507 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
508 gen_rtx_REG (Pmode, i));
510 /* This way, we make sure that reg+reg is an offsettable address. */
511 tem = plus_constant (tem, 4);
513 if (memory_address_p (QImode, tem))
515 double_reg_address_ok = 1;
520 /* Initialize obstack for our rtl allocation. */
521 gcc_obstack_init (&reload_obstack);
522 reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
524 INIT_REG_SET (&spilled_pseudos);
525 INIT_REG_SET (&changed_allocation_pseudos);
526 INIT_REG_SET (&pseudos_counted);
529 /* List of insn chains that are currently unused. */
530 static struct insn_chain *unused_insn_chains = 0;
532 /* Allocate an empty insn_chain structure. */
534 new_insn_chain (void)
536 struct insn_chain *c;
538 if (unused_insn_chains == 0)
540 c = XOBNEW (&reload_obstack, struct insn_chain);
541 INIT_REG_SET (&c->live_throughout);
542 INIT_REG_SET (&c->dead_or_set);
546 c = unused_insn_chains;
547 unused_insn_chains = c->next;
549 c->is_caller_save_insn = 0;
550 c->need_operand_change = 0;
556 /* Small utility function to set all regs in hard reg set TO which are
557 allocated to pseudos in regset FROM. */
560 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
563 reg_set_iterator rsi;
565 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
567 int r = reg_renumber[regno];
571 /* reload_combine uses the information from DF_LIVE_IN,
572 which might still contain registers that have not
573 actually been allocated since they have an
575 gcc_assert (ira_conflicts_p || reload_completed);
578 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
582 /* Replace all pseudos found in LOC with their corresponding
586 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
599 unsigned int regno = REGNO (x);
601 if (regno < FIRST_PSEUDO_REGISTER)
604 x = eliminate_regs (x, mem_mode, usage);
608 replace_pseudos_in (loc, mem_mode, usage);
612 if (reg_equiv_constant[regno])
613 *loc = reg_equiv_constant[regno];
614 else if (reg_equiv_mem[regno])
615 *loc = reg_equiv_mem[regno];
616 else if (reg_equiv_address[regno])
617 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
620 gcc_assert (!REG_P (regno_reg_rtx[regno])
621 || REGNO (regno_reg_rtx[regno]) != regno);
622 *loc = regno_reg_rtx[regno];
627 else if (code == MEM)
629 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
633 /* Process each of our operands recursively. */
634 fmt = GET_RTX_FORMAT (code);
635 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
637 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
638 else if (*fmt == 'E')
639 for (j = 0; j < XVECLEN (x, i); j++)
640 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
643 /* Determine if the current function has an exception receiver block
644 that reaches the exit block via non-exceptional edges */
647 has_nonexceptional_receiver (void)
651 basic_block *tos, *worklist, bb;
653 /* If we're not optimizing, then just err on the safe side. */
657 /* First determine which blocks can reach exit via normal paths. */
658 tos = worklist = XNEWVEC (basic_block, n_basic_blocks + 1);
661 bb->flags &= ~BB_REACHABLE;
663 /* Place the exit block on our worklist. */
664 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
665 *tos++ = EXIT_BLOCK_PTR;
667 /* Iterate: find everything reachable from what we've already seen. */
668 while (tos != worklist)
672 FOR_EACH_EDGE (e, ei, bb->preds)
673 if (!(e->flags & EDGE_ABNORMAL))
675 basic_block src = e->src;
677 if (!(src->flags & BB_REACHABLE))
679 src->flags |= BB_REACHABLE;
686 /* Now see if there's a reachable block with an exceptional incoming
689 if (bb->flags & BB_REACHABLE)
690 FOR_EACH_EDGE (e, ei, bb->preds)
691 if (e->flags & EDGE_ABNORMAL)
694 /* No exceptional block reached exit unexceptionally. */
699 /* Global variables used by reload and its subroutines. */
701 /* Set during calculate_needs if an insn needs register elimination. */
702 static int something_needs_elimination;
703 /* Set during calculate_needs if an insn needs an operand changed. */
704 static int something_needs_operands_changed;
706 /* Nonzero means we couldn't get enough spill regs. */
709 /* Temporary array of pseudo-register number. */
710 static int *temp_pseudo_reg_arr;
712 /* Main entry point for the reload pass.
714 FIRST is the first insn of the function being compiled.
716 GLOBAL nonzero means we were called from global_alloc
717 and should attempt to reallocate any pseudoregs that we
718 displace from hard regs we will use for reloads.
719 If GLOBAL is zero, we do not have enough information to do that,
720 so any pseudo reg that is spilled must go to the stack.
722 Return value is nonzero if reload failed
723 and we must not do any more for this function. */
726 reload (rtx first, int global)
730 struct elim_table *ep;
733 /* Make sure even insns with volatile mem refs are recognizable. */
738 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
740 /* Make sure that the last insn in the chain
741 is not something that needs reloading. */
742 emit_note (NOTE_INSN_DELETED);
744 /* Enable find_equiv_reg to distinguish insns made by reload. */
745 reload_first_uid = get_max_uid ();
747 #ifdef SECONDARY_MEMORY_NEEDED
748 /* Initialize the secondary memory table. */
749 clear_secondary_mem ();
752 /* We don't have a stack slot for any spill reg yet. */
753 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
754 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
756 /* Initialize the save area information for caller-save, in case some
760 /* Compute which hard registers are now in use
761 as homes for pseudo registers.
762 This is done here rather than (eg) in global_alloc
763 because this point is reached even if not optimizing. */
764 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
767 /* A function that has a nonlocal label that can reach the exit
768 block via non-exceptional paths must save all call-saved
770 if (cfun->has_nonlocal_label
771 && has_nonexceptional_receiver ())
772 crtl->saves_all_registers = 1;
774 if (crtl->saves_all_registers)
775 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
776 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
777 df_set_regs_ever_live (i, true);
779 /* Find all the pseudo registers that didn't get hard regs
780 but do have known equivalent constants or memory slots.
781 These include parameters (known equivalent to parameter slots)
782 and cse'd or loop-moved constant memory addresses.
784 Record constant equivalents in reg_equiv_constant
785 so they will be substituted by find_reloads.
786 Record memory equivalents in reg_mem_equiv so they can
787 be substituted eventually by altering the REG-rtx's. */
789 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
790 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
791 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
792 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
793 reg_equiv_address = XCNEWVEC (rtx, max_regno);
794 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
795 reg_old_renumber = XCNEWVEC (short, max_regno);
796 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
797 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
798 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
800 CLEAR_HARD_REG_SET (bad_spill_regs_global);
802 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
803 to. Also find all paradoxical subregs and find largest such for
806 num_eliminable_invariants = 0;
807 for (insn = first; insn; insn = NEXT_INSN (insn))
809 rtx set = single_set (insn);
811 /* We may introduce USEs that we want to remove at the end, so
812 we'll mark them with QImode. Make sure there are no
813 previously-marked insns left by say regmove. */
814 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
815 && GET_MODE (insn) != VOIDmode)
816 PUT_MODE (insn, VOIDmode);
818 if (NONDEBUG_INSN_P (insn))
819 scan_paradoxical_subregs (PATTERN (insn));
821 if (set != 0 && REG_P (SET_DEST (set)))
823 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
829 i = REGNO (SET_DEST (set));
832 if (i <= LAST_VIRTUAL_REGISTER)
835 if (! function_invariant_p (x)
837 /* A function invariant is often CONSTANT_P but may
838 include a register. We promise to only pass
839 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
841 && LEGITIMATE_PIC_OPERAND_P (x)))
843 /* It can happen that a REG_EQUIV note contains a MEM
844 that is not a legitimate memory operand. As later
845 stages of reload assume that all addresses found
846 in the reg_equiv_* arrays were originally legitimate,
847 we ignore such REG_EQUIV notes. */
848 if (memory_operand (x, VOIDmode))
850 /* Always unshare the equivalence, so we can
851 substitute into this insn without touching the
853 reg_equiv_memory_loc[i] = copy_rtx (x);
855 else if (function_invariant_p (x))
857 if (GET_CODE (x) == PLUS)
859 /* This is PLUS of frame pointer and a constant,
860 and might be shared. Unshare it. */
861 reg_equiv_invariant[i] = copy_rtx (x);
862 num_eliminable_invariants++;
864 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
866 reg_equiv_invariant[i] = x;
867 num_eliminable_invariants++;
869 else if (LEGITIMATE_CONSTANT_P (x))
870 reg_equiv_constant[i] = x;
873 reg_equiv_memory_loc[i]
874 = force_const_mem (GET_MODE (SET_DEST (set)), x);
875 if (! reg_equiv_memory_loc[i])
876 reg_equiv_init[i] = NULL_RTX;
881 reg_equiv_init[i] = NULL_RTX;
886 reg_equiv_init[i] = NULL_RTX;
891 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
892 if (reg_equiv_init[i])
894 fprintf (dump_file, "init_insns for %u: ", i);
895 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
896 fprintf (dump_file, "\n");
901 first_label_num = get_first_label_num ();
902 num_labels = max_label_num () - first_label_num;
904 /* Allocate the tables used to store offset information at labels. */
905 /* We used to use alloca here, but the size of what it would try to
906 allocate would occasionally cause it to exceed the stack limit and
907 cause a core dump. */
908 offsets_known_at = XNEWVEC (char, num_labels);
909 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
911 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
912 stack slots to the pseudos that lack hard regs or equivalents.
913 Do not touch virtual registers. */
915 temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
916 for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
917 temp_pseudo_reg_arr[n++] = i;
920 /* Ask IRA to order pseudo-registers for better stack slot
922 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width);
924 for (i = 0; i < n; i++)
925 alter_reg (temp_pseudo_reg_arr[i], -1, false);
927 /* If we have some registers we think can be eliminated, scan all insns to
928 see if there is an insn that sets one of these registers to something
929 other than itself plus a constant. If so, the register cannot be
930 eliminated. Doing this scan here eliminates an extra pass through the
931 main reload loop in the most common case where register elimination
933 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
935 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
937 maybe_fix_stack_asms ();
939 insns_need_reload = 0;
940 something_needs_elimination = 0;
942 /* Initialize to -1, which means take the first spill register. */
945 /* Spill any hard regs that we know we can't eliminate. */
946 CLEAR_HARD_REG_SET (used_spill_regs);
947 /* There can be multiple ways to eliminate a register;
948 they should be listed adjacently.
949 Elimination for any register fails only if all possible ways fail. */
950 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
953 int can_eliminate = 0;
956 can_eliminate |= ep->can_eliminate;
959 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
961 spill_hard_reg (from, 1);
964 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
965 if (frame_pointer_needed)
966 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
968 finish_spills (global);
970 /* From now on, we may need to generate moves differently. We may also
971 allow modifications of insns which cause them to not be recognized.
972 Any such modifications will be cleaned up during reload itself. */
973 reload_in_progress = 1;
975 /* This loop scans the entire function each go-round
976 and repeats until one repetition spills no additional hard regs. */
979 int something_changed;
981 HOST_WIDE_INT starting_frame_size;
983 starting_frame_size = get_frame_size ();
985 set_initial_elim_offsets ();
986 set_initial_label_offsets ();
988 /* For each pseudo register that has an equivalent location defined,
989 try to eliminate any eliminable registers (such as the frame pointer)
990 assuming initial offsets for the replacement register, which
993 If the resulting location is directly addressable, substitute
994 the MEM we just got directly for the old REG.
996 If it is not addressable but is a constant or the sum of a hard reg
997 and constant, it is probably not addressable because the constant is
998 out of range, in that case record the address; we will generate
999 hairy code to compute the address in a register each time it is
1000 needed. Similarly if it is a hard register, but one that is not
1001 valid as an address register.
1003 If the location is not addressable, but does not have one of the
1004 above forms, assign a stack slot. We have to do this to avoid the
1005 potential of producing lots of reloads if, e.g., a location involves
1006 a pseudo that didn't get a hard register and has an equivalent memory
1007 location that also involves a pseudo that didn't get a hard register.
1009 Perhaps at some point we will improve reload_when_needed handling
1010 so this problem goes away. But that's very hairy. */
1012 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1013 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
1015 rtx x = eliminate_regs (reg_equiv_memory_loc[i], VOIDmode,
1018 if (strict_memory_address_addr_space_p
1019 (GET_MODE (regno_reg_rtx[i]), XEXP (x, 0),
1020 MEM_ADDR_SPACE (x)))
1021 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
1022 else if (CONSTANT_P (XEXP (x, 0))
1023 || (REG_P (XEXP (x, 0))
1024 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
1025 || (GET_CODE (XEXP (x, 0)) == PLUS
1026 && REG_P (XEXP (XEXP (x, 0), 0))
1027 && (REGNO (XEXP (XEXP (x, 0), 0))
1028 < FIRST_PSEUDO_REGISTER)
1029 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
1030 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
1033 /* Make a new stack slot. Then indicate that something
1034 changed so we go back and recompute offsets for
1035 eliminable registers because the allocation of memory
1036 below might change some offset. reg_equiv_{mem,address}
1037 will be set up for this pseudo on the next pass around
1039 reg_equiv_memory_loc[i] = 0;
1040 reg_equiv_init[i] = 0;
1041 alter_reg (i, -1, true);
1045 if (caller_save_needed)
1046 setup_save_areas ();
1048 /* If we allocated another stack slot, redo elimination bookkeeping. */
1049 if (starting_frame_size != get_frame_size ())
1051 if (starting_frame_size && crtl->stack_alignment_needed)
1053 /* If we have a stack frame, we must align it now. The
1054 stack size may be a part of the offset computation for
1055 register elimination. So if this changes the stack size,
1056 then repeat the elimination bookkeeping. We don't
1057 realign when there is no stack, as that will cause a
1058 stack frame when none is needed should
1059 STARTING_FRAME_OFFSET not be already aligned to
1061 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
1062 if (starting_frame_size != get_frame_size ())
1066 if (caller_save_needed)
1068 save_call_clobbered_regs ();
1069 /* That might have allocated new insn_chain structures. */
1070 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1073 calculate_needs_all_insns (global);
1075 if (! ira_conflicts_p)
1076 /* Don't do it for IRA. We need this info because we don't
1077 change live_throughout and dead_or_set for chains when IRA
1079 CLEAR_REG_SET (&spilled_pseudos);
1083 something_changed = 0;
1085 /* If we allocated any new memory locations, make another pass
1086 since it might have changed elimination offsets. */
1087 if (starting_frame_size != get_frame_size ())
1088 something_changed = 1;
1090 /* Even if the frame size remained the same, we might still have
1091 changed elimination offsets, e.g. if find_reloads called
1092 force_const_mem requiring the back end to allocate a constant
1093 pool base register that needs to be saved on the stack. */
1094 else if (!verify_initial_elim_offsets ())
1095 something_changed = 1;
1098 HARD_REG_SET to_spill;
1099 CLEAR_HARD_REG_SET (to_spill);
1100 update_eliminables (&to_spill);
1101 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
1103 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1104 if (TEST_HARD_REG_BIT (to_spill, i))
1106 spill_hard_reg (i, 1);
1109 /* Regardless of the state of spills, if we previously had
1110 a register that we thought we could eliminate, but now can
1111 not eliminate, we must run another pass.
1113 Consider pseudos which have an entry in reg_equiv_* which
1114 reference an eliminable register. We must make another pass
1115 to update reg_equiv_* so that we do not substitute in the
1116 old value from when we thought the elimination could be
1118 something_changed = 1;
1122 select_reload_regs ();
1126 if (insns_need_reload != 0 || did_spill)
1127 something_changed |= finish_spills (global);
1129 if (! something_changed)
1132 if (caller_save_needed)
1133 delete_caller_save_insns ();
1135 obstack_free (&reload_obstack, reload_firstobj);
1138 /* If global-alloc was run, notify it of any register eliminations we have
1141 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1142 if (ep->can_eliminate)
1143 mark_elimination (ep->from, ep->to);
1145 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1146 If that insn didn't set the register (i.e., it copied the register to
1147 memory), just delete that insn instead of the equivalencing insn plus
1148 anything now dead. If we call delete_dead_insn on that insn, we may
1149 delete the insn that actually sets the register if the register dies
1150 there and that is incorrect. */
1152 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1154 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1157 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1159 rtx equiv_insn = XEXP (list, 0);
1161 /* If we already deleted the insn or if it may trap, we can't
1162 delete it. The latter case shouldn't happen, but can
1163 if an insn has a variable address, gets a REG_EH_REGION
1164 note added to it, and then gets converted into a load
1165 from a constant address. */
1166 if (NOTE_P (equiv_insn)
1167 || can_throw_internal (equiv_insn))
1169 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1170 delete_dead_insn (equiv_insn);
1172 SET_INSN_DELETED (equiv_insn);
1177 /* Use the reload registers where necessary
1178 by generating move instructions to move the must-be-register
1179 values into or out of the reload registers. */
1181 if (insns_need_reload != 0 || something_needs_elimination
1182 || something_needs_operands_changed)
1184 HOST_WIDE_INT old_frame_size = get_frame_size ();
1186 reload_as_needed (global);
1188 gcc_assert (old_frame_size == get_frame_size ());
1190 gcc_assert (verify_initial_elim_offsets ());
1193 /* If we were able to eliminate the frame pointer, show that it is no
1194 longer live at the start of any basic block. If it ls live by
1195 virtue of being in a pseudo, that pseudo will be marked live
1196 and hence the frame pointer will be known to be live via that
1199 if (! frame_pointer_needed)
1201 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1203 /* Come here (with failure set nonzero) if we can't get enough spill
1207 CLEAR_REG_SET (&changed_allocation_pseudos);
1208 CLEAR_REG_SET (&spilled_pseudos);
1209 reload_in_progress = 0;
1211 /* Now eliminate all pseudo regs by modifying them into
1212 their equivalent memory references.
1213 The REG-rtx's for the pseudos are modified in place,
1214 so all insns that used to refer to them now refer to memory.
1216 For a reg that has a reg_equiv_address, all those insns
1217 were changed by reloading so that no insns refer to it any longer;
1218 but the DECL_RTL of a variable decl may refer to it,
1219 and if so this causes the debugging info to mention the variable. */
1221 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1225 if (reg_equiv_mem[i])
1226 addr = XEXP (reg_equiv_mem[i], 0);
1228 if (reg_equiv_address[i])
1229 addr = reg_equiv_address[i];
1233 if (reg_renumber[i] < 0)
1235 rtx reg = regno_reg_rtx[i];
1237 REG_USERVAR_P (reg) = 0;
1238 PUT_CODE (reg, MEM);
1239 XEXP (reg, 0) = addr;
1240 if (reg_equiv_memory_loc[i])
1241 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1244 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1245 MEM_ATTRS (reg) = 0;
1247 MEM_NOTRAP_P (reg) = 1;
1249 else if (reg_equiv_mem[i])
1250 XEXP (reg_equiv_mem[i], 0) = addr;
1253 /* We don't want complex addressing modes in debug insns
1254 if simpler ones will do, so delegitimize equivalences
1256 if (MAY_HAVE_DEBUG_INSNS && reg_renumber[i] < 0)
1258 rtx reg = regno_reg_rtx[i];
1262 if (reg_equiv_constant[i])
1263 equiv = reg_equiv_constant[i];
1264 else if (reg_equiv_invariant[i])
1265 equiv = reg_equiv_invariant[i];
1266 else if (reg && MEM_P (reg))
1267 equiv = targetm.delegitimize_address (reg);
1268 else if (reg && REG_P (reg) && (int)REGNO (reg) != i)
1274 for (use = DF_REG_USE_CHAIN (i); use; use = next)
1276 insn = DF_REF_INSN (use);
1278 /* Make sure the next ref is for a different instruction,
1279 so that we're not affected by the rescan. */
1280 next = DF_REF_NEXT_REG (use);
1281 while (next && DF_REF_INSN (next) == insn)
1282 next = DF_REF_NEXT_REG (next);
1284 if (DEBUG_INSN_P (insn))
1288 INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
1289 df_insn_rescan_debug_internal (insn);
1292 INSN_VAR_LOCATION_LOC (insn)
1293 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn),
1300 /* We must set reload_completed now since the cleanup_subreg_operands call
1301 below will re-recognize each insn and reload may have generated insns
1302 which are only valid during and after reload. */
1303 reload_completed = 1;
1305 /* Make a pass over all the insns and delete all USEs which we inserted
1306 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1307 notes. Delete all CLOBBER insns, except those that refer to the return
1308 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1309 from misarranging variable-array code, and simplify (subreg (reg))
1310 operands. Strip and regenerate REG_INC notes that may have been moved
1313 for (insn = first; insn; insn = NEXT_INSN (insn))
1319 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1320 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1322 if ((GET_CODE (PATTERN (insn)) == USE
1323 /* We mark with QImode USEs introduced by reload itself. */
1324 && (GET_MODE (insn) == QImode
1325 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1326 || (GET_CODE (PATTERN (insn)) == CLOBBER
1327 && (!MEM_P (XEXP (PATTERN (insn), 0))
1328 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1329 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1330 && XEXP (XEXP (PATTERN (insn), 0), 0)
1331 != stack_pointer_rtx))
1332 && (!REG_P (XEXP (PATTERN (insn), 0))
1333 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1339 /* Some CLOBBERs may survive until here and still reference unassigned
1340 pseudos with const equivalent, which may in turn cause ICE in later
1341 passes if the reference remains in place. */
1342 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1343 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1344 VOIDmode, PATTERN (insn));
1346 /* Discard obvious no-ops, even without -O. This optimization
1347 is fast and doesn't interfere with debugging. */
1348 if (NONJUMP_INSN_P (insn)
1349 && GET_CODE (PATTERN (insn)) == SET
1350 && REG_P (SET_SRC (PATTERN (insn)))
1351 && REG_P (SET_DEST (PATTERN (insn)))
1352 && (REGNO (SET_SRC (PATTERN (insn)))
1353 == REGNO (SET_DEST (PATTERN (insn)))))
1359 pnote = ®_NOTES (insn);
1362 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1363 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1364 || REG_NOTE_KIND (*pnote) == REG_INC)
1365 *pnote = XEXP (*pnote, 1);
1367 pnote = &XEXP (*pnote, 1);
1371 add_auto_inc_notes (insn, PATTERN (insn));
1374 /* Simplify (subreg (reg)) if it appears as an operand. */
1375 cleanup_subreg_operands (insn);
1377 /* Clean up invalid ASMs so that they don't confuse later passes.
1379 if (asm_noperands (PATTERN (insn)) >= 0)
1381 extract_insn (insn);
1382 if (!constrain_operands (1))
1384 error_for_asm (insn,
1385 "%<asm%> operand has impossible constraints");
1392 /* If we are doing generic stack checking, give a warning if this
1393 function's frame size is larger than we expect. */
1394 if (flag_stack_check == GENERIC_STACK_CHECK)
1396 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1397 static int verbose_warned = 0;
1399 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1400 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1401 size += UNITS_PER_WORD;
1403 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1405 warning (0, "frame size too large for reliable stack checking");
1406 if (! verbose_warned)
1408 warning (0, "try reducing the number of local variables");
1414 /* Indicate that we no longer have known memory locations or constants. */
1415 if (reg_equiv_constant)
1416 free (reg_equiv_constant);
1417 if (reg_equiv_invariant)
1418 free (reg_equiv_invariant);
1419 reg_equiv_constant = 0;
1420 reg_equiv_invariant = 0;
1421 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
1422 reg_equiv_memory_loc = 0;
1424 free (temp_pseudo_reg_arr);
1426 if (offsets_known_at)
1427 free (offsets_known_at);
1431 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1432 if (reg_equiv_alt_mem_list[i])
1433 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
1434 free (reg_equiv_alt_mem_list);
1436 free (reg_equiv_mem);
1438 free (reg_equiv_address);
1439 free (reg_max_ref_width);
1440 free (reg_old_renumber);
1441 free (pseudo_previous_regs);
1442 free (pseudo_forbidden_regs);
1444 CLEAR_HARD_REG_SET (used_spill_regs);
1445 for (i = 0; i < n_spills; i++)
1446 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1448 /* Free all the insn_chain structures at once. */
1449 obstack_free (&reload_obstack, reload_startobj);
1450 unused_insn_chains = 0;
1451 fixup_abnormal_edges ();
1453 /* Replacing pseudos with their memory equivalents might have
1454 created shared rtx. Subsequent passes would get confused
1455 by this, so unshare everything here. */
1456 unshare_all_rtl_again (first);
1458 #ifdef STACK_BOUNDARY
1459 /* init_emit has set the alignment of the hard frame pointer
1460 to STACK_BOUNDARY. It is very likely no longer valid if
1461 the hard frame pointer was used for register allocation. */
1462 if (!frame_pointer_needed)
1463 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1466 VEC_free (rtx_p, heap, substitute_stack);
1471 /* Yet another special case. Unfortunately, reg-stack forces people to
1472 write incorrect clobbers in asm statements. These clobbers must not
1473 cause the register to appear in bad_spill_regs, otherwise we'll call
1474 fatal_insn later. We clear the corresponding regnos in the live
1475 register sets to avoid this.
1476 The whole thing is rather sick, I'm afraid. */
1479 maybe_fix_stack_asms (void)
1482 const char *constraints[MAX_RECOG_OPERANDS];
1483 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1484 struct insn_chain *chain;
1486 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1489 HARD_REG_SET clobbered, allowed;
1492 if (! INSN_P (chain->insn)
1493 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1495 pat = PATTERN (chain->insn);
1496 if (GET_CODE (pat) != PARALLEL)
1499 CLEAR_HARD_REG_SET (clobbered);
1500 CLEAR_HARD_REG_SET (allowed);
1502 /* First, make a mask of all stack regs that are clobbered. */
1503 for (i = 0; i < XVECLEN (pat, 0); i++)
1505 rtx t = XVECEXP (pat, 0, i);
1506 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1507 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1510 /* Get the operand values and constraints out of the insn. */
1511 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1512 constraints, operand_mode, NULL);
1514 /* For every operand, see what registers are allowed. */
1515 for (i = 0; i < noperands; i++)
1517 const char *p = constraints[i];
1518 /* For every alternative, we compute the class of registers allowed
1519 for reloading in CLS, and merge its contents into the reg set
1521 int cls = (int) NO_REGS;
1527 if (c == '\0' || c == ',' || c == '#')
1529 /* End of one alternative - mark the regs in the current
1530 class, and reset the class. */
1531 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1537 } while (c != '\0' && c != ',');
1545 case '=': case '+': case '*': case '%': case '?': case '!':
1546 case '0': case '1': case '2': case '3': case '4': case '<':
1547 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1548 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1549 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1550 case TARGET_MEM_CONSTRAINT:
1554 cls = (int) reg_class_subunion[cls]
1555 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1560 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1564 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1565 cls = (int) reg_class_subunion[cls]
1566 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1568 cls = (int) reg_class_subunion[cls]
1569 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1571 p += CONSTRAINT_LEN (c, p);
1574 /* Those of the registers which are clobbered, but allowed by the
1575 constraints, must be usable as reload registers. So clear them
1576 out of the life information. */
1577 AND_HARD_REG_SET (allowed, clobbered);
1578 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1579 if (TEST_HARD_REG_BIT (allowed, i))
1581 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1582 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1589 /* Copy the global variables n_reloads and rld into the corresponding elts
1592 copy_reloads (struct insn_chain *chain)
1594 chain->n_reloads = n_reloads;
1595 chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1596 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1597 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1600 /* Walk the chain of insns, and determine for each whether it needs reloads
1601 and/or eliminations. Build the corresponding insns_need_reload list, and
1602 set something_needs_elimination as appropriate. */
1604 calculate_needs_all_insns (int global)
1606 struct insn_chain **pprev_reload = &insns_need_reload;
1607 struct insn_chain *chain, *next = 0;
1609 something_needs_elimination = 0;
1611 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1612 for (chain = reload_insn_chain; chain != 0; chain = next)
1614 rtx insn = chain->insn;
1618 /* Clear out the shortcuts. */
1619 chain->n_reloads = 0;
1620 chain->need_elim = 0;
1621 chain->need_reload = 0;
1622 chain->need_operand_change = 0;
1624 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1625 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1626 what effects this has on the known offsets at labels. */
1628 if (LABEL_P (insn) || JUMP_P (insn)
1629 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1630 set_label_offsets (insn, insn, 0);
1634 rtx old_body = PATTERN (insn);
1635 int old_code = INSN_CODE (insn);
1636 rtx old_notes = REG_NOTES (insn);
1637 int did_elimination = 0;
1638 int operands_changed = 0;
1639 rtx set = single_set (insn);
1641 /* Skip insns that only set an equivalence. */
1642 if (set && REG_P (SET_DEST (set))
1643 && reg_renumber[REGNO (SET_DEST (set))] < 0
1644 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1645 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1646 && reg_equiv_init[REGNO (SET_DEST (set))])
1649 /* If needed, eliminate any eliminable registers. */
1650 if (num_eliminable || num_eliminable_invariants)
1651 did_elimination = eliminate_regs_in_insn (insn, 0);
1653 /* Analyze the instruction. */
1654 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1655 global, spill_reg_order);
1657 /* If a no-op set needs more than one reload, this is likely
1658 to be something that needs input address reloads. We
1659 can't get rid of this cleanly later, and it is of no use
1660 anyway, so discard it now.
1661 We only do this when expensive_optimizations is enabled,
1662 since this complements reload inheritance / output
1663 reload deletion, and it can make debugging harder. */
1664 if (flag_expensive_optimizations && n_reloads > 1)
1666 rtx set = single_set (insn);
1669 ((SET_SRC (set) == SET_DEST (set)
1670 && REG_P (SET_SRC (set))
1671 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1672 || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1673 && reg_renumber[REGNO (SET_SRC (set))] < 0
1674 && reg_renumber[REGNO (SET_DEST (set))] < 0
1675 && reg_equiv_memory_loc[REGNO (SET_SRC (set))] != NULL
1676 && reg_equiv_memory_loc[REGNO (SET_DEST (set))] != NULL
1677 && rtx_equal_p (reg_equiv_memory_loc
1678 [REGNO (SET_SRC (set))],
1679 reg_equiv_memory_loc
1680 [REGNO (SET_DEST (set))]))))
1682 if (ira_conflicts_p)
1683 /* Inform IRA about the insn deletion. */
1684 ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1685 REGNO (SET_SRC (set)));
1687 /* Delete it from the reload chain. */
1689 chain->prev->next = next;
1691 reload_insn_chain = next;
1693 next->prev = chain->prev;
1694 chain->next = unused_insn_chains;
1695 unused_insn_chains = chain;
1700 update_eliminable_offsets ();
1702 /* Remember for later shortcuts which insns had any reloads or
1703 register eliminations. */
1704 chain->need_elim = did_elimination;
1705 chain->need_reload = n_reloads > 0;
1706 chain->need_operand_change = operands_changed;
1708 /* Discard any register replacements done. */
1709 if (did_elimination)
1711 obstack_free (&reload_obstack, reload_insn_firstobj);
1712 PATTERN (insn) = old_body;
1713 INSN_CODE (insn) = old_code;
1714 REG_NOTES (insn) = old_notes;
1715 something_needs_elimination = 1;
1718 something_needs_operands_changed |= operands_changed;
1722 copy_reloads (chain);
1723 *pprev_reload = chain;
1724 pprev_reload = &chain->next_need_reload;
1731 /* Comparison function for qsort to decide which of two reloads
1732 should be handled first. *P1 and *P2 are the reload numbers. */
1735 reload_reg_class_lower (const void *r1p, const void *r2p)
1737 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1740 /* Consider required reloads before optional ones. */
1741 t = rld[r1].optional - rld[r2].optional;
1745 /* Count all solitary classes before non-solitary ones. */
1746 t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1747 - (reg_class_size[(int) rld[r1].rclass] == 1));
1751 /* Aside from solitaires, consider all multi-reg groups first. */
1752 t = rld[r2].nregs - rld[r1].nregs;
1756 /* Consider reloads in order of increasing reg-class number. */
1757 t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1761 /* If reloads are equally urgent, sort by reload number,
1762 so that the results of qsort leave nothing to chance. */
1766 /* The cost of spilling each hard reg. */
1767 static int spill_cost[FIRST_PSEUDO_REGISTER];
1769 /* When spilling multiple hard registers, we use SPILL_COST for the first
1770 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1771 only the first hard reg for a multi-reg pseudo. */
1772 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1774 /* Map of hard regno to pseudo regno currently occupying the hard
1776 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1778 /* Update the spill cost arrays, considering that pseudo REG is live. */
1781 count_pseudo (int reg)
1783 int freq = REG_FREQ (reg);
1784 int r = reg_renumber[reg];
1787 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1788 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1789 /* Ignore spilled pseudo-registers which can be here only if IRA
1791 || (ira_conflicts_p && r < 0))
1794 SET_REGNO_REG_SET (&pseudos_counted, reg);
1796 gcc_assert (r >= 0);
1798 spill_add_cost[r] += freq;
1799 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1802 hard_regno_to_pseudo_regno[r + nregs] = reg;
1803 spill_cost[r + nregs] += freq;
1807 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1808 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1811 order_regs_for_reload (struct insn_chain *chain)
1814 HARD_REG_SET used_by_pseudos;
1815 HARD_REG_SET used_by_pseudos2;
1816 reg_set_iterator rsi;
1818 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1820 memset (spill_cost, 0, sizeof spill_cost);
1821 memset (spill_add_cost, 0, sizeof spill_add_cost);
1822 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1823 hard_regno_to_pseudo_regno[i] = -1;
1825 /* Count number of uses of each hard reg by pseudo regs allocated to it
1826 and then order them by decreasing use. First exclude hard registers
1827 that are live in or across this insn. */
1829 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1830 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1831 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1832 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1834 /* Now find out which pseudos are allocated to it, and update
1836 CLEAR_REG_SET (&pseudos_counted);
1838 EXECUTE_IF_SET_IN_REG_SET
1839 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1843 EXECUTE_IF_SET_IN_REG_SET
1844 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1848 CLEAR_REG_SET (&pseudos_counted);
1851 /* Vector of reload-numbers showing the order in which the reloads should
1853 static short reload_order[MAX_RELOADS];
1855 /* This is used to keep track of the spill regs used in one insn. */
1856 static HARD_REG_SET used_spill_regs_local;
1858 /* We decided to spill hard register SPILLED, which has a size of
1859 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1860 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1861 update SPILL_COST/SPILL_ADD_COST. */
1864 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1866 int freq = REG_FREQ (reg);
1867 int r = reg_renumber[reg];
1868 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1870 /* Ignore spilled pseudo-registers which can be here only if IRA is
1872 if ((ira_conflicts_p && r < 0)
1873 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1874 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1877 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1879 spill_add_cost[r] -= freq;
1882 hard_regno_to_pseudo_regno[r + nregs] = -1;
1883 spill_cost[r + nregs] -= freq;
1887 /* Find reload register to use for reload number ORDER. */
1890 find_reg (struct insn_chain *chain, int order)
1892 int rnum = reload_order[order];
1893 struct reload *rl = rld + rnum;
1894 int best_cost = INT_MAX;
1896 unsigned int i, j, n;
1898 HARD_REG_SET not_usable;
1899 HARD_REG_SET used_by_other_reload;
1900 reg_set_iterator rsi;
1901 static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1902 static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1904 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1905 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1906 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
1908 CLEAR_HARD_REG_SET (used_by_other_reload);
1909 for (k = 0; k < order; k++)
1911 int other = reload_order[k];
1913 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1914 for (j = 0; j < rld[other].nregs; j++)
1915 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1918 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1920 #ifdef REG_ALLOC_ORDER
1921 unsigned int regno = reg_alloc_order[i];
1923 unsigned int regno = i;
1926 if (! TEST_HARD_REG_BIT (not_usable, regno)
1927 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1928 && HARD_REGNO_MODE_OK (regno, rl->mode))
1930 int this_cost = spill_cost[regno];
1932 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1934 for (j = 1; j < this_nregs; j++)
1936 this_cost += spill_add_cost[regno + j];
1937 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1938 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1944 if (ira_conflicts_p)
1946 /* Ask IRA to find a better pseudo-register for
1948 for (n = j = 0; j < this_nregs; j++)
1950 int r = hard_regno_to_pseudo_regno[regno + j];
1954 if (n == 0 || regno_pseudo_regs[n - 1] != r)
1955 regno_pseudo_regs[n++] = r;
1957 regno_pseudo_regs[n++] = -1;
1959 || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1960 best_regno_pseudo_regs,
1967 best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1968 if (regno_pseudo_regs[j] < 0)
1975 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1977 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1979 if (this_cost < best_cost
1980 /* Among registers with equal cost, prefer caller-saved ones, or
1981 use REG_ALLOC_ORDER if it is defined. */
1982 || (this_cost == best_cost
1983 #ifdef REG_ALLOC_ORDER
1984 && (inv_reg_alloc_order[regno]
1985 < inv_reg_alloc_order[best_reg])
1987 && call_used_regs[regno]
1988 && ! call_used_regs[best_reg]
1993 best_cost = this_cost;
2001 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
2003 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
2004 rl->regno = best_reg;
2006 EXECUTE_IF_SET_IN_REG_SET
2007 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
2009 count_spilled_pseudo (best_reg, rl->nregs, j);
2012 EXECUTE_IF_SET_IN_REG_SET
2013 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
2015 count_spilled_pseudo (best_reg, rl->nregs, j);
2018 for (i = 0; i < rl->nregs; i++)
2020 gcc_assert (spill_cost[best_reg + i] == 0);
2021 gcc_assert (spill_add_cost[best_reg + i] == 0);
2022 gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
2023 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
2028 /* Find more reload regs to satisfy the remaining need of an insn, which
2030 Do it by ascending class number, since otherwise a reg
2031 might be spilled for a big class and might fail to count
2032 for a smaller class even though it belongs to that class. */
2035 find_reload_regs (struct insn_chain *chain)
2039 /* In order to be certain of getting the registers we need,
2040 we must sort the reloads into order of increasing register class.
2041 Then our grabbing of reload registers will parallel the process
2042 that provided the reload registers. */
2043 for (i = 0; i < chain->n_reloads; i++)
2045 /* Show whether this reload already has a hard reg. */
2046 if (chain->rld[i].reg_rtx)
2048 int regno = REGNO (chain->rld[i].reg_rtx);
2049 chain->rld[i].regno = regno;
2051 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
2054 chain->rld[i].regno = -1;
2055 reload_order[i] = i;
2058 n_reloads = chain->n_reloads;
2059 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
2061 CLEAR_HARD_REG_SET (used_spill_regs_local);
2064 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
2066 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
2068 /* Compute the order of preference for hard registers to spill. */
2070 order_regs_for_reload (chain);
2072 for (i = 0; i < n_reloads; i++)
2074 int r = reload_order[i];
2076 /* Ignore reloads that got marked inoperative. */
2077 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
2078 && ! rld[r].optional
2079 && rld[r].regno == -1)
2080 if (! find_reg (chain, i))
2083 fprintf (dump_file, "reload failure for reload %d\n", r);
2084 spill_failure (chain->insn, rld[r].rclass);
2090 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
2091 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
2093 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2097 select_reload_regs (void)
2099 struct insn_chain *chain;
2101 /* Try to satisfy the needs for each insn. */
2102 for (chain = insns_need_reload; chain != 0;
2103 chain = chain->next_need_reload)
2104 find_reload_regs (chain);
2107 /* Delete all insns that were inserted by emit_caller_save_insns during
2110 delete_caller_save_insns (void)
2112 struct insn_chain *c = reload_insn_chain;
2116 while (c != 0 && c->is_caller_save_insn)
2118 struct insn_chain *next = c->next;
2121 if (c == reload_insn_chain)
2122 reload_insn_chain = next;
2126 next->prev = c->prev;
2128 c->prev->next = next;
2129 c->next = unused_insn_chains;
2130 unused_insn_chains = c;
2138 /* Handle the failure to find a register to spill.
2139 INSN should be one of the insns which needed this particular spill reg. */
2142 spill_failure (rtx insn, enum reg_class rclass)
2144 if (asm_noperands (PATTERN (insn)) >= 0)
2145 error_for_asm (insn, "can't find a register in class %qs while "
2146 "reloading %<asm%>",
2147 reg_class_names[rclass]);
2150 error ("unable to find a register to spill in class %qs",
2151 reg_class_names[rclass]);
2155 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2156 debug_reload_to_stream (dump_file);
2158 fatal_insn ("this is the insn:", insn);
2162 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2163 data that is dead in INSN. */
2166 delete_dead_insn (rtx insn)
2168 rtx prev = prev_real_insn (insn);
2171 /* If the previous insn sets a register that dies in our insn, delete it
2173 if (prev && GET_CODE (PATTERN (prev)) == SET
2174 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2175 && reg_mentioned_p (prev_dest, PATTERN (insn))
2176 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2177 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2178 delete_dead_insn (prev);
2180 SET_INSN_DELETED (insn);
2183 /* Modify the home of pseudo-reg I.
2184 The new home is present in reg_renumber[I].
2186 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2187 or it may be -1, meaning there is none or it is not relevant.
2188 This is used so that all pseudos spilled from a given hard reg
2189 can share one stack slot. */
2192 alter_reg (int i, int from_reg, bool dont_share_p)
2194 /* When outputting an inline function, this can happen
2195 for a reg that isn't actually used. */
2196 if (regno_reg_rtx[i] == 0)
2199 /* If the reg got changed to a MEM at rtl-generation time,
2201 if (!REG_P (regno_reg_rtx[i]))
2204 /* Modify the reg-rtx to contain the new hard reg
2205 number or else to contain its pseudo reg number. */
2206 SET_REGNO (regno_reg_rtx[i],
2207 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2209 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2210 allocate a stack slot for it. */
2212 if (reg_renumber[i] < 0
2213 && REG_N_REFS (i) > 0
2214 && reg_equiv_constant[i] == 0
2215 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
2216 && reg_equiv_memory_loc[i] == 0)
2219 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2220 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2221 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2222 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2223 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2226 if (ira_conflicts_p)
2228 /* Mark the spill for IRA. */
2229 SET_REGNO_REG_SET (&spilled_pseudos, i);
2231 x = ira_reuse_stack_slot (i, inherent_size, total_size);
2237 /* Each pseudo reg has an inherent size which comes from its own mode,
2238 and a total size which provides room for paradoxical subregs
2239 which refer to the pseudo reg in wider modes.
2241 We can use a slot already allocated if it provides both
2242 enough inherent space and enough total space.
2243 Otherwise, we allocate a new slot, making sure that it has no less
2244 inherent space, and no less total space, then the previous slot. */
2245 else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
2249 /* No known place to spill from => no slot to reuse. */
2250 x = assign_stack_local (mode, total_size,
2251 min_align > inherent_align
2252 || total_size > inherent_size ? -1 : 0);
2256 /* Cancel the big-endian correction done in assign_stack_local.
2257 Get the address of the beginning of the slot. This is so we
2258 can do a big-endian correction unconditionally below. */
2259 if (BYTES_BIG_ENDIAN)
2261 adjust = inherent_size - total_size;
2264 = adjust_address_nv (x, mode_for_size (total_size
2270 if (! dont_share_p && ira_conflicts_p)
2271 /* Inform IRA about allocation a new stack slot. */
2272 ira_mark_new_stack_slot (stack_slot, i, total_size);
2275 /* Reuse a stack slot if possible. */
2276 else if (spill_stack_slot[from_reg] != 0
2277 && spill_stack_slot_width[from_reg] >= total_size
2278 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2280 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2281 x = spill_stack_slot[from_reg];
2283 /* Allocate a bigger slot. */
2286 /* Compute maximum size needed, both for inherent size
2287 and for total size. */
2290 if (spill_stack_slot[from_reg])
2292 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2294 mode = GET_MODE (spill_stack_slot[from_reg]);
2295 if (spill_stack_slot_width[from_reg] > total_size)
2296 total_size = spill_stack_slot_width[from_reg];
2297 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2298 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2301 /* Make a slot with that size. */
2302 x = assign_stack_local (mode, total_size,
2303 min_align > inherent_align
2304 || total_size > inherent_size ? -1 : 0);
2307 /* Cancel the big-endian correction done in assign_stack_local.
2308 Get the address of the beginning of the slot. This is so we
2309 can do a big-endian correction unconditionally below. */
2310 if (BYTES_BIG_ENDIAN)
2312 adjust = GET_MODE_SIZE (mode) - total_size;
2315 = adjust_address_nv (x, mode_for_size (total_size
2321 spill_stack_slot[from_reg] = stack_slot;
2322 spill_stack_slot_width[from_reg] = total_size;
2325 /* On a big endian machine, the "address" of the slot
2326 is the address of the low part that fits its inherent mode. */
2327 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2328 adjust += (total_size - inherent_size);
2330 /* If we have any adjustment to make, or if the stack slot is the
2331 wrong mode, make a new stack slot. */
2332 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2334 /* Set all of the memory attributes as appropriate for a spill. */
2335 set_mem_attrs_for_spill (x);
2337 /* Save the stack slot for later. */
2338 reg_equiv_memory_loc[i] = x;
2342 /* Mark the slots in regs_ever_live for the hard regs used by
2343 pseudo-reg number REGNO, accessed in MODE. */
2346 mark_home_live_1 (int regno, enum machine_mode mode)
2350 i = reg_renumber[regno];
2353 lim = end_hard_regno (mode, i);
2355 df_set_regs_ever_live(i++, true);
2358 /* Mark the slots in regs_ever_live for the hard regs
2359 used by pseudo-reg number REGNO. */
2362 mark_home_live (int regno)
2364 if (reg_renumber[regno] >= 0)
2365 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2368 /* This function handles the tracking of elimination offsets around branches.
2370 X is a piece of RTL being scanned.
2372 INSN is the insn that it came from, if any.
2374 INITIAL_P is nonzero if we are to set the offset to be the initial
2375 offset and zero if we are setting the offset of the label to be the
2379 set_label_offsets (rtx x, rtx insn, int initial_p)
2381 enum rtx_code code = GET_CODE (x);
2384 struct elim_table *p;
2389 if (LABEL_REF_NONLOCAL_P (x))
2394 /* ... fall through ... */
2397 /* If we know nothing about this label, set the desired offsets. Note
2398 that this sets the offset at a label to be the offset before a label
2399 if we don't know anything about the label. This is not correct for
2400 the label after a BARRIER, but is the best guess we can make. If
2401 we guessed wrong, we will suppress an elimination that might have
2402 been possible had we been able to guess correctly. */
2404 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2406 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2407 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2408 = (initial_p ? reg_eliminate[i].initial_offset
2409 : reg_eliminate[i].offset);
2410 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2413 /* Otherwise, if this is the definition of a label and it is
2414 preceded by a BARRIER, set our offsets to the known offset of
2418 && (tem = prev_nonnote_insn (insn)) != 0
2420 set_offsets_for_label (insn);
2422 /* If neither of the above cases is true, compare each offset
2423 with those previously recorded and suppress any eliminations
2424 where the offsets disagree. */
2426 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2427 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2428 != (initial_p ? reg_eliminate[i].initial_offset
2429 : reg_eliminate[i].offset))
2430 reg_eliminate[i].can_eliminate = 0;
2435 set_label_offsets (PATTERN (insn), insn, initial_p);
2437 /* ... fall through ... */
2441 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2442 to indirectly and hence must have all eliminations at their
2444 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2445 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2446 set_label_offsets (XEXP (tem, 0), insn, 1);
2452 /* Each of the labels in the parallel or address vector must be
2453 at their initial offsets. We want the first field for PARALLEL
2454 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2456 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2457 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2462 /* We only care about setting PC. If the source is not RETURN,
2463 IF_THEN_ELSE, or a label, disable any eliminations not at
2464 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2465 isn't one of those possibilities. For branches to a label,
2466 call ourselves recursively.
2468 Note that this can disable elimination unnecessarily when we have
2469 a non-local goto since it will look like a non-constant jump to
2470 someplace in the current function. This isn't a significant
2471 problem since such jumps will normally be when all elimination
2472 pairs are back to their initial offsets. */
2474 if (SET_DEST (x) != pc_rtx)
2477 switch (GET_CODE (SET_SRC (x)))
2484 set_label_offsets (SET_SRC (x), insn, initial_p);
2488 tem = XEXP (SET_SRC (x), 1);
2489 if (GET_CODE (tem) == LABEL_REF)
2490 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2491 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2494 tem = XEXP (SET_SRC (x), 2);
2495 if (GET_CODE (tem) == LABEL_REF)
2496 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2497 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2505 /* If we reach here, all eliminations must be at their initial
2506 offset because we are doing a jump to a variable address. */
2507 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2508 if (p->offset != p->initial_offset)
2509 p->can_eliminate = 0;
2517 /* Scan X and replace any eliminable registers (such as fp) with a
2518 replacement (such as sp), plus an offset.
2520 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2521 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2522 MEM, we are allowed to replace a sum of a register and the constant zero
2523 with the register, which we cannot do outside a MEM. In addition, we need
2524 to record the fact that a register is referenced outside a MEM.
2526 If INSN is an insn, it is the insn containing X. If we replace a REG
2527 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2528 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2529 the REG is being modified.
2531 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2532 That's used when we eliminate in expressions stored in notes.
2533 This means, do not set ref_outside_mem even if the reference
2536 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2537 replacements done assuming all offsets are at their initial values. If
2538 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2539 encounter, return the actual location so that find_reloads will do
2540 the proper thing. */
2543 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2544 bool may_use_invariant)
2546 enum rtx_code code = GET_CODE (x);
2547 struct elim_table *ep;
2554 if (! current_function_decl)
2577 /* First handle the case where we encounter a bare register that
2578 is eliminable. Replace it with a PLUS. */
2579 if (regno < FIRST_PSEUDO_REGISTER)
2581 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2583 if (ep->from_rtx == x && ep->can_eliminate)
2584 return plus_constant (ep->to_rtx, ep->previous_offset);
2587 else if (reg_renumber && reg_renumber[regno] < 0
2588 && reg_equiv_invariant && reg_equiv_invariant[regno])
2590 if (may_use_invariant || (insn && DEBUG_INSN_P (insn)))
2591 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2592 mem_mode, insn, true);
2593 /* There exists at least one use of REGNO that cannot be
2594 eliminated. Prevent the defining insn from being deleted. */
2595 reg_equiv_init[regno] = NULL_RTX;
2596 alter_reg (regno, -1, true);
2600 /* You might think handling MINUS in a manner similar to PLUS is a
2601 good idea. It is not. It has been tried multiple times and every
2602 time the change has had to have been reverted.
2604 Other parts of reload know a PLUS is special (gen_reload for example)
2605 and require special code to handle code a reloaded PLUS operand.
2607 Also consider backends where the flags register is clobbered by a
2608 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2609 lea instruction comes to mind). If we try to reload a MINUS, we
2610 may kill the flags register that was holding a useful value.
2612 So, please before trying to handle MINUS, consider reload as a
2613 whole instead of this little section as well as the backend issues. */
2615 /* If this is the sum of an eliminable register and a constant, rework
2617 if (REG_P (XEXP (x, 0))
2618 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2619 && CONSTANT_P (XEXP (x, 1)))
2621 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2623 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2625 /* The only time we want to replace a PLUS with a REG (this
2626 occurs when the constant operand of the PLUS is the negative
2627 of the offset) is when we are inside a MEM. We won't want
2628 to do so at other times because that would change the
2629 structure of the insn in a way that reload can't handle.
2630 We special-case the commonest situation in
2631 eliminate_regs_in_insn, so just replace a PLUS with a
2632 PLUS here, unless inside a MEM. */
2633 if (mem_mode != 0 && CONST_INT_P (XEXP (x, 1))
2634 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2637 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2638 plus_constant (XEXP (x, 1),
2639 ep->previous_offset));
2642 /* If the register is not eliminable, we are done since the other
2643 operand is a constant. */
2647 /* If this is part of an address, we want to bring any constant to the
2648 outermost PLUS. We will do this by doing register replacement in
2649 our operands and seeing if a constant shows up in one of them.
2651 Note that there is no risk of modifying the structure of the insn,
2652 since we only get called for its operands, thus we are either
2653 modifying the address inside a MEM, or something like an address
2654 operand of a load-address insn. */
2657 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2658 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2660 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2662 /* If one side is a PLUS and the other side is a pseudo that
2663 didn't get a hard register but has a reg_equiv_constant,
2664 we must replace the constant here since it may no longer
2665 be in the position of any operand. */
2666 if (GET_CODE (new0) == PLUS && REG_P (new1)
2667 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2668 && reg_renumber[REGNO (new1)] < 0
2669 && reg_equiv_constant != 0
2670 && reg_equiv_constant[REGNO (new1)] != 0)
2671 new1 = reg_equiv_constant[REGNO (new1)];
2672 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2673 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2674 && reg_renumber[REGNO (new0)] < 0
2675 && reg_equiv_constant[REGNO (new0)] != 0)
2676 new0 = reg_equiv_constant[REGNO (new0)];
2678 new_rtx = form_sum (GET_MODE (x), new0, new1);
2680 /* As above, if we are not inside a MEM we do not want to
2681 turn a PLUS into something else. We might try to do so here
2682 for an addition of 0 if we aren't optimizing. */
2683 if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2684 return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2692 /* If this is the product of an eliminable register and a
2693 constant, apply the distribute law and move the constant out
2694 so that we have (plus (mult ..) ..). This is needed in order
2695 to keep load-address insns valid. This case is pathological.
2696 We ignore the possibility of overflow here. */
2697 if (REG_P (XEXP (x, 0))
2698 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2699 && CONST_INT_P (XEXP (x, 1)))
2700 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2702 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2705 /* Refs inside notes or in DEBUG_INSNs don't count for
2707 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2708 || GET_CODE (insn) == INSN_LIST
2709 || DEBUG_INSN_P (insn))))
2710 ep->ref_outside_mem = 1;
2713 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2714 ep->previous_offset * INTVAL (XEXP (x, 1)));
2717 /* ... fall through ... */
2721 /* See comments before PLUS about handling MINUS. */
2723 case DIV: case UDIV:
2724 case MOD: case UMOD:
2725 case AND: case IOR: case XOR:
2726 case ROTATERT: case ROTATE:
2727 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2729 case GE: case GT: case GEU: case GTU:
2730 case LE: case LT: case LEU: case LTU:
2732 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2733 rtx new1 = XEXP (x, 1)
2734 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2736 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2737 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2742 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2745 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2746 if (new_rtx != XEXP (x, 0))
2748 /* If this is a REG_DEAD note, it is not valid anymore.
2749 Using the eliminated version could result in creating a
2750 REG_DEAD note for the stack or frame pointer. */
2751 if (REG_NOTE_KIND (x) == REG_DEAD)
2753 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2756 x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2760 /* ... fall through ... */
2763 /* Now do eliminations in the rest of the chain. If this was
2764 an EXPR_LIST, this might result in allocating more memory than is
2765 strictly needed, but it simplifies the code. */
2768 new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2769 if (new_rtx != XEXP (x, 1))
2771 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2779 /* We do not support elimination of a register that is modified.
2780 elimination_effects has already make sure that this does not
2786 /* We do not support elimination of a register that is modified.
2787 elimination_effects has already make sure that this does not
2788 happen. The only remaining case we need to consider here is
2789 that the increment value may be an eliminable register. */
2790 if (GET_CODE (XEXP (x, 1)) == PLUS
2791 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2793 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2796 if (new_rtx != XEXP (XEXP (x, 1), 1))
2797 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2798 gen_rtx_PLUS (GET_MODE (x),
2799 XEXP (x, 0), new_rtx));
2803 case STRICT_LOW_PART:
2805 case SIGN_EXTEND: case ZERO_EXTEND:
2806 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2807 case FLOAT: case FIX:
2808 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2817 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2818 if (new_rtx != XEXP (x, 0))
2819 return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2823 /* Similar to above processing, but preserve SUBREG_BYTE.
2824 Convert (subreg (mem)) to (mem) if not paradoxical.
2825 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2826 pseudo didn't get a hard reg, we must replace this with the
2827 eliminated version of the memory location because push_reload
2828 may do the replacement in certain circumstances. */
2829 if (REG_P (SUBREG_REG (x))
2830 && (GET_MODE_SIZE (GET_MODE (x))
2831 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2832 && reg_equiv_memory_loc != 0
2833 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2835 new_rtx = SUBREG_REG (x);
2838 new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2840 if (new_rtx != SUBREG_REG (x))
2842 int x_size = GET_MODE_SIZE (GET_MODE (x));
2843 int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2846 && ((x_size < new_size
2847 #ifdef WORD_REGISTER_OPERATIONS
2848 /* On these machines, combine can create rtl of the form
2849 (set (subreg:m1 (reg:m2 R) 0) ...)
2850 where m1 < m2, and expects something interesting to
2851 happen to the entire word. Moreover, it will use the
2852 (reg:m2 R) later, expecting all bits to be preserved.
2853 So if the number of words is the same, preserve the
2854 subreg so that push_reload can see it. */
2855 && ! ((x_size - 1) / UNITS_PER_WORD
2856 == (new_size -1 ) / UNITS_PER_WORD)
2859 || x_size == new_size)
2861 return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2863 return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2869 /* Our only special processing is to pass the mode of the MEM to our
2870 recursive call and copy the flags. While we are here, handle this
2871 case more efficiently. */
2873 replace_equiv_address_nv (x,
2874 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2878 /* Handle insn_list USE that a call to a pure function may generate. */
2879 new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false);
2880 if (new_rtx != XEXP (x, 0))
2881 return gen_rtx_USE (GET_MODE (x), new_rtx);
2885 gcc_assert (insn && DEBUG_INSN_P (insn));
2896 /* Process each of our operands recursively. If any have changed, make a
2898 fmt = GET_RTX_FORMAT (code);
2899 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2903 new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2904 if (new_rtx != XEXP (x, i) && ! copied)
2906 x = shallow_copy_rtx (x);
2909 XEXP (x, i) = new_rtx;
2911 else if (*fmt == 'E')
2914 for (j = 0; j < XVECLEN (x, i); j++)
2916 new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2917 if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2919 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2923 x = shallow_copy_rtx (x);
2926 XVEC (x, i) = new_v;
2929 XVECEXP (x, i, j) = new_rtx;
2938 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2940 return eliminate_regs_1 (x, mem_mode, insn, false);
2943 /* Scan rtx X for modifications of elimination target registers. Update
2944 the table of eliminables to reflect the changed state. MEM_MODE is
2945 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2948 elimination_effects (rtx x, enum machine_mode mem_mode)
2950 enum rtx_code code = GET_CODE (x);
2951 struct elim_table *ep;
2976 /* First handle the case where we encounter a bare register that
2977 is eliminable. Replace it with a PLUS. */
2978 if (regno < FIRST_PSEUDO_REGISTER)
2980 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2982 if (ep->from_rtx == x && ep->can_eliminate)
2985 ep->ref_outside_mem = 1;
2990 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2991 && reg_equiv_constant[regno]
2992 && ! function_invariant_p (reg_equiv_constant[regno]))
2993 elimination_effects (reg_equiv_constant[regno], mem_mode);
3002 /* If we modify the source of an elimination rule, disable it. */
3003 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3004 if (ep->from_rtx == XEXP (x, 0))
3005 ep->can_eliminate = 0;
3007 /* If we modify the target of an elimination rule by adding a constant,
3008 update its offset. If we modify the target in any other way, we'll
3009 have to disable the rule as well. */
3010 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3011 if (ep->to_rtx == XEXP (x, 0))
3013 int size = GET_MODE_SIZE (mem_mode);
3015 /* If more bytes than MEM_MODE are pushed, account for them. */
3016 #ifdef PUSH_ROUNDING
3017 if (ep->to_rtx == stack_pointer_rtx)
3018 size = PUSH_ROUNDING (size);
3020 if (code == PRE_DEC || code == POST_DEC)
3022 else if (code == PRE_INC || code == POST_INC)
3024 else if (code == PRE_MODIFY || code == POST_MODIFY)
3026 if (GET_CODE (XEXP (x, 1)) == PLUS
3027 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
3028 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
3029 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
3031 ep->can_eliminate = 0;
3035 /* These two aren't unary operators. */
3036 if (code == POST_MODIFY || code == PRE_MODIFY)
3039 /* Fall through to generic unary operation case. */
3040 case STRICT_LOW_PART:
3042 case SIGN_EXTEND: case ZERO_EXTEND:
3043 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3044 case FLOAT: case FIX:
3045 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3054 elimination_effects (XEXP (x, 0), mem_mode);
3058 if (REG_P (SUBREG_REG (x))
3059 && (GET_MODE_SIZE (GET_MODE (x))
3060 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3061 && reg_equiv_memory_loc != 0
3062 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
3065 elimination_effects (SUBREG_REG (x), mem_mode);
3069 /* If using a register that is the source of an eliminate we still
3070 think can be performed, note it cannot be performed since we don't
3071 know how this register is used. */
3072 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3073 if (ep->from_rtx == XEXP (x, 0))
3074 ep->can_eliminate = 0;
3076 elimination_effects (XEXP (x, 0), mem_mode);
3080 /* If clobbering a register that is the replacement register for an
3081 elimination we still think can be performed, note that it cannot
3082 be performed. Otherwise, we need not be concerned about it. */
3083 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3084 if (ep->to_rtx == XEXP (x, 0))
3085 ep->can_eliminate = 0;
3087 elimination_effects (XEXP (x, 0), mem_mode);
3091 /* Check for setting a register that we know about. */
3092 if (REG_P (SET_DEST (x)))
3094 /* See if this is setting the replacement register for an
3097 If DEST is the hard frame pointer, we do nothing because we
3098 assume that all assignments to the frame pointer are for
3099 non-local gotos and are being done at a time when they are valid
3100 and do not disturb anything else. Some machines want to
3101 eliminate a fake argument pointer (or even a fake frame pointer)
3102 with either the real frame or the stack pointer. Assignments to
3103 the hard frame pointer must not prevent this elimination. */
3105 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3107 if (ep->to_rtx == SET_DEST (x)
3108 && SET_DEST (x) != hard_frame_pointer_rtx)
3110 /* If it is being incremented, adjust the offset. Otherwise,
3111 this elimination can't be done. */
3112 rtx src = SET_SRC (x);
3114 if (GET_CODE (src) == PLUS
3115 && XEXP (src, 0) == SET_DEST (x)
3116 && CONST_INT_P (XEXP (src, 1)))
3117 ep->offset -= INTVAL (XEXP (src, 1));
3119 ep->can_eliminate = 0;
3123 elimination_effects (SET_DEST (x), VOIDmode);
3124 elimination_effects (SET_SRC (x), VOIDmode);
3128 /* Our only special processing is to pass the mode of the MEM to our
3130 elimination_effects (XEXP (x, 0), GET_MODE (x));
3137 fmt = GET_RTX_FORMAT (code);
3138 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3141 elimination_effects (XEXP (x, i), mem_mode);
3142 else if (*fmt == 'E')
3143 for (j = 0; j < XVECLEN (x, i); j++)
3144 elimination_effects (XVECEXP (x, i, j), mem_mode);
3148 /* Descend through rtx X and verify that no references to eliminable registers
3149 remain. If any do remain, mark the involved register as not
3153 check_eliminable_occurrences (rtx x)
3162 code = GET_CODE (x);
3164 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3166 struct elim_table *ep;
3168 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3169 if (ep->from_rtx == x)
3170 ep->can_eliminate = 0;
3174 fmt = GET_RTX_FORMAT (code);
3175 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3178 check_eliminable_occurrences (XEXP (x, i));
3179 else if (*fmt == 'E')
3182 for (j = 0; j < XVECLEN (x, i); j++)
3183 check_eliminable_occurrences (XVECEXP (x, i, j));
3188 /* Scan INSN and eliminate all eliminable registers in it.
3190 If REPLACE is nonzero, do the replacement destructively. Also
3191 delete the insn as dead it if it is setting an eliminable register.
3193 If REPLACE is zero, do all our allocations in reload_obstack.
3195 If no eliminations were done and this insn doesn't require any elimination
3196 processing (these are not identical conditions: it might be updating sp,
3197 but not referencing fp; this needs to be seen during reload_as_needed so
3198 that the offset between fp and sp can be taken into consideration), zero
3199 is returned. Otherwise, 1 is returned. */
3202 eliminate_regs_in_insn (rtx insn, int replace)
3204 int icode = recog_memoized (insn);
3205 rtx old_body = PATTERN (insn);
3206 int insn_is_asm = asm_noperands (old_body) >= 0;
3207 rtx old_set = single_set (insn);
3211 rtx substed_operand[MAX_RECOG_OPERANDS];
3212 rtx orig_operand[MAX_RECOG_OPERANDS];
3213 struct elim_table *ep;
3214 rtx plus_src, plus_cst_src;
3216 if (! insn_is_asm && icode < 0)
3218 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3219 || GET_CODE (PATTERN (insn)) == CLOBBER
3220 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3221 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3222 || GET_CODE (PATTERN (insn)) == ASM_INPUT
3223 || DEBUG_INSN_P (insn));
3224 if (DEBUG_INSN_P (insn))
3225 INSN_VAR_LOCATION_LOC (insn)
3226 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn), VOIDmode, insn);
3230 if (old_set != 0 && REG_P (SET_DEST (old_set))
3231 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3233 /* Check for setting an eliminable register. */
3234 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3235 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3237 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3238 /* If this is setting the frame pointer register to the
3239 hardware frame pointer register and this is an elimination
3240 that will be done (tested above), this insn is really
3241 adjusting the frame pointer downward to compensate for
3242 the adjustment done before a nonlocal goto. */
3243 if (ep->from == FRAME_POINTER_REGNUM
3244 && ep->to == HARD_FRAME_POINTER_REGNUM)
3246 rtx base = SET_SRC (old_set);
3247 rtx base_insn = insn;
3248 HOST_WIDE_INT offset = 0;
3250 while (base != ep->to_rtx)
3252 rtx prev_insn, prev_set;
3254 if (GET_CODE (base) == PLUS
3255 && CONST_INT_P (XEXP (base, 1)))
3257 offset += INTVAL (XEXP (base, 1));
3258 base = XEXP (base, 0);
3260 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3261 && (prev_set = single_set (prev_insn)) != 0
3262 && rtx_equal_p (SET_DEST (prev_set), base))
3264 base = SET_SRC (prev_set);
3265 base_insn = prev_insn;
3271 if (base == ep->to_rtx)
3274 = plus_constant (ep->to_rtx, offset - ep->offset);
3276 new_body = old_body;
3279 new_body = copy_insn (old_body);
3280 if (REG_NOTES (insn))
3281 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3283 PATTERN (insn) = new_body;
3284 old_set = single_set (insn);
3286 /* First see if this insn remains valid when we
3287 make the change. If not, keep the INSN_CODE
3288 the same and let reload fit it up. */
3289 validate_change (insn, &SET_SRC (old_set), src, 1);
3290 validate_change (insn, &SET_DEST (old_set),
3292 if (! apply_change_group ())
3294 SET_SRC (old_set) = src;
3295 SET_DEST (old_set) = ep->to_rtx;
3304 /* In this case this insn isn't serving a useful purpose. We
3305 will delete it in reload_as_needed once we know that this
3306 elimination is, in fact, being done.
3308 If REPLACE isn't set, we can't delete this insn, but needn't
3309 process it since it won't be used unless something changes. */
3312 delete_dead_insn (insn);
3320 /* We allow one special case which happens to work on all machines we
3321 currently support: a single set with the source or a REG_EQUAL
3322 note being a PLUS of an eliminable register and a constant. */
3323 plus_src = plus_cst_src = 0;
3324 if (old_set && REG_P (SET_DEST (old_set)))
3326 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3327 plus_src = SET_SRC (old_set);
3328 /* First see if the source is of the form (plus (...) CST). */
3330 && CONST_INT_P (XEXP (plus_src, 1)))
3331 plus_cst_src = plus_src;
3332 else if (REG_P (SET_SRC (old_set))
3335 /* Otherwise, see if we have a REG_EQUAL note of the form
3336 (plus (...) CST). */
3338 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3340 if ((REG_NOTE_KIND (links) == REG_EQUAL
3341 || REG_NOTE_KIND (links) == REG_EQUIV)
3342 && GET_CODE (XEXP (links, 0)) == PLUS
3343 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3345 plus_cst_src = XEXP (links, 0);
3351 /* Check that the first operand of the PLUS is a hard reg or
3352 the lowpart subreg of one. */
3355 rtx reg = XEXP (plus_cst_src, 0);
3356 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3357 reg = SUBREG_REG (reg);
3359 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3365 rtx reg = XEXP (plus_cst_src, 0);
3366 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3368 if (GET_CODE (reg) == SUBREG)
3369 reg = SUBREG_REG (reg);
3371 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3372 if (ep->from_rtx == reg && ep->can_eliminate)
3374 rtx to_rtx = ep->to_rtx;
3375 offset += ep->offset;
3376 offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
3378 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3379 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3381 /* If we have a nonzero offset, and the source is already
3382 a simple REG, the following transformation would
3383 increase the cost of the insn by replacing a simple REG
3384 with (plus (reg sp) CST). So try only when we already
3385 had a PLUS before. */
3386 if (offset == 0 || plus_src)
3388 rtx new_src = plus_constant (to_rtx, offset);
3390 new_body = old_body;
3393 new_body = copy_insn (old_body);
3394 if (REG_NOTES (insn))
3395 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3397 PATTERN (insn) = new_body;
3398 old_set = single_set (insn);
3400 /* First see if this insn remains valid when we make the
3401 change. If not, try to replace the whole pattern with
3402 a simple set (this may help if the original insn was a
3403 PARALLEL that was only recognized as single_set due to
3404 REG_UNUSED notes). If this isn't valid either, keep
3405 the INSN_CODE the same and let reload fix it up. */
3406 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3408 rtx new_pat = gen_rtx_SET (VOIDmode,
3409 SET_DEST (old_set), new_src);
3411 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3412 SET_SRC (old_set) = new_src;
3419 /* This can't have an effect on elimination offsets, so skip right
3425 /* Determine the effects of this insn on elimination offsets. */
3426 elimination_effects (old_body, VOIDmode);
3428 /* Eliminate all eliminable registers occurring in operands that
3429 can be handled by reload. */
3430 extract_insn (insn);
3431 for (i = 0; i < recog_data.n_operands; i++)
3433 orig_operand[i] = recog_data.operand[i];
3434 substed_operand[i] = recog_data.operand[i];
3436 /* For an asm statement, every operand is eliminable. */
3437 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3439 bool is_set_src, in_plus;
3441 /* Check for setting a register that we know about. */
3442 if (recog_data.operand_type[i] != OP_IN
3443 && REG_P (orig_operand[i]))
3445 /* If we are assigning to a register that can be eliminated, it
3446 must be as part of a PARALLEL, since the code above handles
3447 single SETs. We must indicate that we can no longer
3448 eliminate this reg. */
3449 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3451 if (ep->from_rtx == orig_operand[i])
3452 ep->can_eliminate = 0;
3455 /* Companion to the above plus substitution, we can allow
3456 invariants as the source of a plain move. */
3458 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3462 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3463 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3467 = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3468 replace ? insn : NULL_RTX,
3469 is_set_src || in_plus);
3470 if (substed_operand[i] != orig_operand[i])
3472 /* Terminate the search in check_eliminable_occurrences at
3474 *recog_data.operand_loc[i] = 0;
3476 /* If an output operand changed from a REG to a MEM and INSN is an
3477 insn, write a CLOBBER insn. */
3478 if (recog_data.operand_type[i] != OP_IN
3479 && REG_P (orig_operand[i])
3480 && MEM_P (substed_operand[i])
3482 emit_insn_after (gen_clobber (orig_operand[i]), insn);
3486 for (i = 0; i < recog_data.n_dups; i++)
3487 *recog_data.dup_loc[i]
3488 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3490 /* If any eliminable remain, they aren't eliminable anymore. */
3491 check_eliminable_occurrences (old_body);
3493 /* Substitute the operands; the new values are in the substed_operand
3495 for (i = 0; i < recog_data.n_operands; i++)
3496 *recog_data.operand_loc[i] = substed_operand[i];
3497 for (i = 0; i < recog_data.n_dups; i++)
3498 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3500 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3501 re-recognize the insn. We do this in case we had a simple addition
3502 but now can do this as a load-address. This saves an insn in this
3504 If re-recognition fails, the old insn code number will still be used,
3505 and some register operands may have changed into PLUS expressions.
3506 These will be handled by find_reloads by loading them into a register
3511 /* If we aren't replacing things permanently and we changed something,
3512 make another copy to ensure that all the RTL is new. Otherwise
3513 things can go wrong if find_reload swaps commutative operands
3514 and one is inside RTL that has been copied while the other is not. */
3515 new_body = old_body;
3518 new_body = copy_insn (old_body);
3519 if (REG_NOTES (insn))
3520 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3522 PATTERN (insn) = new_body;
3524 /* If we had a move insn but now we don't, rerecognize it. This will
3525 cause spurious re-recognition if the old move had a PARALLEL since
3526 the new one still will, but we can't call single_set without
3527 having put NEW_BODY into the insn and the re-recognition won't
3528 hurt in this rare case. */
3529 /* ??? Why this huge if statement - why don't we just rerecognize the
3533 && ((REG_P (SET_SRC (old_set))
3534 && (GET_CODE (new_body) != SET
3535 || !REG_P (SET_SRC (new_body))))
3536 /* If this was a load from or store to memory, compare
3537 the MEM in recog_data.operand to the one in the insn.
3538 If they are not equal, then rerecognize the insn. */
3540 && ((MEM_P (SET_SRC (old_set))
3541 && SET_SRC (old_set) != recog_data.operand[1])
3542 || (MEM_P (SET_DEST (old_set))
3543 && SET_DEST (old_set) != recog_data.operand[0])))
3544 /* If this was an add insn before, rerecognize. */
3545 || GET_CODE (SET_SRC (old_set)) == PLUS))
3547 int new_icode = recog (PATTERN (insn), insn, 0);
3549 INSN_CODE (insn) = new_icode;
3553 /* Restore the old body. If there were any changes to it, we made a copy
3554 of it while the changes were still in place, so we'll correctly return
3555 a modified insn below. */
3558 /* Restore the old body. */
3559 for (i = 0; i < recog_data.n_operands; i++)
3560 /* Restoring a top-level match_parallel would clobber the new_body
3561 we installed in the insn. */
3562 if (recog_data.operand_loc[i] != &PATTERN (insn))
3563 *recog_data.operand_loc[i] = orig_operand[i];
3564 for (i = 0; i < recog_data.n_dups; i++)
3565 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3568 /* Update all elimination pairs to reflect the status after the current
3569 insn. The changes we make were determined by the earlier call to
3570 elimination_effects.
3572 We also detect cases where register elimination cannot be done,
3573 namely, if a register would be both changed and referenced outside a MEM
3574 in the resulting insn since such an insn is often undefined and, even if
3575 not, we cannot know what meaning will be given to it. Note that it is
3576 valid to have a register used in an address in an insn that changes it
3577 (presumably with a pre- or post-increment or decrement).
3579 If anything changes, return nonzero. */
3581 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3583 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3584 ep->can_eliminate = 0;
3586 ep->ref_outside_mem = 0;
3588 if (ep->previous_offset != ep->offset)
3593 /* If we changed something, perform elimination in REG_NOTES. This is
3594 needed even when REPLACE is zero because a REG_DEAD note might refer
3595 to a register that we eliminate and could cause a different number
3596 of spill registers to be needed in the final reload pass than in
3598 if (val && REG_NOTES (insn) != 0)
3600 = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true);
3605 /* Loop through all elimination pairs.
3606 Recalculate the number not at initial offset.
3608 Compute the maximum offset (minimum offset if the stack does not
3609 grow downward) for each elimination pair. */
3612 update_eliminable_offsets (void)
3614 struct elim_table *ep;
3616 num_not_at_initial_offset = 0;
3617 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3619 ep->previous_offset = ep->offset;
3620 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3621 num_not_at_initial_offset++;
3625 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3626 replacement we currently believe is valid, mark it as not eliminable if X
3627 modifies DEST in any way other than by adding a constant integer to it.
3629 If DEST is the frame pointer, we do nothing because we assume that
3630 all assignments to the hard frame pointer are nonlocal gotos and are being
3631 done at a time when they are valid and do not disturb anything else.
3632 Some machines want to eliminate a fake argument pointer with either the
3633 frame or stack pointer. Assignments to the hard frame pointer must not
3634 prevent this elimination.
3636 Called via note_stores from reload before starting its passes to scan
3637 the insns of the function. */
3640 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3644 /* A SUBREG of a hard register here is just changing its mode. We should
3645 not see a SUBREG of an eliminable hard register, but check just in
3647 if (GET_CODE (dest) == SUBREG)
3648 dest = SUBREG_REG (dest);
3650 if (dest == hard_frame_pointer_rtx)
3653 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3654 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3655 && (GET_CODE (x) != SET
3656 || GET_CODE (SET_SRC (x)) != PLUS
3657 || XEXP (SET_SRC (x), 0) != dest
3658 || !CONST_INT_P (XEXP (SET_SRC (x), 1))))
3660 reg_eliminate[i].can_eliminate_previous
3661 = reg_eliminate[i].can_eliminate = 0;
3666 /* Verify that the initial elimination offsets did not change since the
3667 last call to set_initial_elim_offsets. This is used to catch cases
3668 where something illegal happened during reload_as_needed that could
3669 cause incorrect code to be generated if we did not check for it. */
3672 verify_initial_elim_offsets (void)
3676 if (!num_eliminable)
3679 #ifdef ELIMINABLE_REGS
3681 struct elim_table *ep;
3683 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3685 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3686 if (t != ep->initial_offset)
3691 INITIAL_FRAME_POINTER_OFFSET (t);
3692 if (t != reg_eliminate[0].initial_offset)
3699 /* Reset all offsets on eliminable registers to their initial values. */
3702 set_initial_elim_offsets (void)
3704 struct elim_table *ep = reg_eliminate;
3706 #ifdef ELIMINABLE_REGS
3707 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3709 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3710 ep->previous_offset = ep->offset = ep->initial_offset;
3713 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3714 ep->previous_offset = ep->offset = ep->initial_offset;
3717 num_not_at_initial_offset = 0;
3720 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3723 set_initial_eh_label_offset (rtx label)
3725 set_label_offsets (label, NULL_RTX, 1);
3728 /* Initialize the known label offsets.
3729 Set a known offset for each forced label to be at the initial offset
3730 of each elimination. We do this because we assume that all
3731 computed jumps occur from a location where each elimination is
3732 at its initial offset.
3733 For all other labels, show that we don't know the offsets. */
3736 set_initial_label_offsets (void)
3739 memset (offsets_known_at, 0, num_labels);
3741 for (x = forced_labels; x; x = XEXP (x, 1))
3743 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3745 for_each_eh_label (set_initial_eh_label_offset);
3748 /* Set all elimination offsets to the known values for the code label given
3752 set_offsets_for_label (rtx insn)
3755 int label_nr = CODE_LABEL_NUMBER (insn);
3756 struct elim_table *ep;
3758 num_not_at_initial_offset = 0;
3759 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3761 ep->offset = ep->previous_offset
3762 = offsets_at[label_nr - first_label_num][i];
3763 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3764 num_not_at_initial_offset++;
3768 /* See if anything that happened changes which eliminations are valid.
3769 For example, on the SPARC, whether or not the frame pointer can
3770 be eliminated can depend on what registers have been used. We need
3771 not check some conditions again (such as flag_omit_frame_pointer)
3772 since they can't have changed. */
3775 update_eliminables (HARD_REG_SET *pset)
3777 int previous_frame_pointer_needed = frame_pointer_needed;
3778 struct elim_table *ep;
3780 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3781 if ((ep->from == HARD_FRAME_POINTER_REGNUM
3782 && targetm.frame_pointer_required ())
3783 #ifdef ELIMINABLE_REGS
3784 || ! targetm.can_eliminate (ep->from, ep->to)
3787 ep->can_eliminate = 0;
3789 /* Look for the case where we have discovered that we can't replace
3790 register A with register B and that means that we will now be
3791 trying to replace register A with register C. This means we can
3792 no longer replace register C with register B and we need to disable
3793 such an elimination, if it exists. This occurs often with A == ap,
3794 B == sp, and C == fp. */
3796 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3798 struct elim_table *op;
3801 if (! ep->can_eliminate && ep->can_eliminate_previous)
3803 /* Find the current elimination for ep->from, if there is a
3805 for (op = reg_eliminate;
3806 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3807 if (op->from == ep->from && op->can_eliminate)
3813 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3815 for (op = reg_eliminate;
3816 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3817 if (op->from == new_to && op->to == ep->to)
3818 op->can_eliminate = 0;
3822 /* See if any registers that we thought we could eliminate the previous
3823 time are no longer eliminable. If so, something has changed and we
3824 must spill the register. Also, recompute the number of eliminable
3825 registers and see if the frame pointer is needed; it is if there is
3826 no elimination of the frame pointer that we can perform. */
3828 frame_pointer_needed = 1;
3829 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3831 if (ep->can_eliminate
3832 && ep->from == FRAME_POINTER_REGNUM
3833 && ep->to != HARD_FRAME_POINTER_REGNUM
3834 && (! SUPPORTS_STACK_ALIGNMENT
3835 || ! crtl->stack_realign_needed))
3836 frame_pointer_needed = 0;
3838 if (! ep->can_eliminate && ep->can_eliminate_previous)
3840 ep->can_eliminate_previous = 0;
3841 SET_HARD_REG_BIT (*pset, ep->from);
3846 /* If we didn't need a frame pointer last time, but we do now, spill
3847 the hard frame pointer. */
3848 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3849 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3852 /* Return true if X is used as the target register of an elimination. */
3855 elimination_target_reg_p (rtx x)
3857 struct elim_table *ep;
3859 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3860 if (ep->to_rtx == x && ep->can_eliminate)
3866 /* Initialize the table of registers to eliminate.
3867 Pre-condition: global flag frame_pointer_needed has been set before
3868 calling this function. */
3871 init_elim_table (void)
3873 struct elim_table *ep;
3874 #ifdef ELIMINABLE_REGS
3875 const struct elim_table_1 *ep1;
3879 reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
3883 #ifdef ELIMINABLE_REGS
3884 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3885 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3887 ep->from = ep1->from;
3889 ep->can_eliminate = ep->can_eliminate_previous
3890 = (targetm.can_eliminate (ep->from, ep->to)
3891 && ! (ep->to == STACK_POINTER_REGNUM
3892 && frame_pointer_needed
3893 && (! SUPPORTS_STACK_ALIGNMENT
3894 || ! stack_realign_fp)));
3897 reg_eliminate[0].from = reg_eliminate_1[0].from;
3898 reg_eliminate[0].to = reg_eliminate_1[0].to;
3899 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3900 = ! frame_pointer_needed;
3903 /* Count the number of eliminable registers and build the FROM and TO
3904 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3905 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3906 We depend on this. */
3907 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3909 num_eliminable += ep->can_eliminate;
3910 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3911 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3915 /* Kick all pseudos out of hard register REGNO.
3917 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3918 because we found we can't eliminate some register. In the case, no pseudos
3919 are allowed to be in the register, even if they are only in a block that
3920 doesn't require spill registers, unlike the case when we are spilling this
3921 hard reg to produce another spill register.
3923 Return nonzero if any pseudos needed to be kicked out. */
3926 spill_hard_reg (unsigned int regno, int cant_eliminate)
3932 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3933 df_set_regs_ever_live (regno, true);
3936 /* Spill every pseudo reg that was allocated to this reg
3937 or to something that overlaps this reg. */
3939 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3940 if (reg_renumber[i] >= 0
3941 && (unsigned int) reg_renumber[i] <= regno
3942 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
3943 SET_REGNO_REG_SET (&spilled_pseudos, i);
3946 /* After find_reload_regs has been run for all insn that need reloads,
3947 and/or spill_hard_regs was called, this function is used to actually
3948 spill pseudo registers and try to reallocate them. It also sets up the
3949 spill_regs array for use by choose_reload_regs. */
3952 finish_spills (int global)
3954 struct insn_chain *chain;
3955 int something_changed = 0;
3957 reg_set_iterator rsi;
3959 /* Build the spill_regs array for the function. */
3960 /* If there are some registers still to eliminate and one of the spill regs
3961 wasn't ever used before, additional stack space may have to be
3962 allocated to store this register. Thus, we may have changed the offset
3963 between the stack and frame pointers, so mark that something has changed.
3965 One might think that we need only set VAL to 1 if this is a call-used
3966 register. However, the set of registers that must be saved by the
3967 prologue is not identical to the call-used set. For example, the
3968 register used by the call insn for the return PC is a call-used register,
3969 but must be saved by the prologue. */
3972 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3973 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3975 spill_reg_order[i] = n_spills;
3976 spill_regs[n_spills++] = i;
3977 if (num_eliminable && ! df_regs_ever_live_p (i))
3978 something_changed = 1;
3979 df_set_regs_ever_live (i, true);
3982 spill_reg_order[i] = -1;
3984 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3985 if (! ira_conflicts_p || reg_renumber[i] >= 0)
3987 /* Record the current hard register the pseudo is allocated to
3988 in pseudo_previous_regs so we avoid reallocating it to the
3989 same hard reg in a later pass. */
3990 gcc_assert (reg_renumber[i] >= 0);
3992 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3993 /* Mark it as no longer having a hard register home. */
3994 reg_renumber[i] = -1;
3995 if (ira_conflicts_p)
3996 /* Inform IRA about the change. */
3997 ira_mark_allocation_change (i);
3998 /* We will need to scan everything again. */
3999 something_changed = 1;
4002 /* Retry global register allocation if possible. */
4003 if (global && ira_conflicts_p)
4007 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
4008 /* For every insn that needs reloads, set the registers used as spill
4009 regs in pseudo_forbidden_regs for every pseudo live across the
4011 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
4013 EXECUTE_IF_SET_IN_REG_SET
4014 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
4016 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4017 chain->used_spill_regs);
4019 EXECUTE_IF_SET_IN_REG_SET
4020 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
4022 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4023 chain->used_spill_regs);
4027 /* Retry allocating the pseudos spilled in IRA and the
4028 reload. For each reg, merge the various reg sets that
4029 indicate which hard regs can't be used, and call
4030 ira_reassign_pseudos. */
4031 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
4032 if (reg_old_renumber[i] != reg_renumber[i])
4034 if (reg_renumber[i] < 0)
4035 temp_pseudo_reg_arr[n++] = i;
4037 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4039 if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
4040 bad_spill_regs_global,
4041 pseudo_forbidden_regs, pseudo_previous_regs,
4043 something_changed = 1;
4045 /* Fix up the register information in the insn chain.
4046 This involves deleting those of the spilled pseudos which did not get
4047 a new hard register home from the live_{before,after} sets. */
4048 for (chain = reload_insn_chain; chain; chain = chain->next)
4050 HARD_REG_SET used_by_pseudos;
4051 HARD_REG_SET used_by_pseudos2;
4053 if (! ira_conflicts_p)
4055 /* Don't do it for IRA because IRA and the reload still can
4056 assign hard registers to the spilled pseudos on next
4057 reload iterations. */
4058 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
4059 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
4061 /* Mark any unallocated hard regs as available for spills. That
4062 makes inheritance work somewhat better. */
4063 if (chain->need_reload)
4065 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
4066 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
4067 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
4069 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
4070 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
4071 /* Value of chain->used_spill_regs from previous iteration
4072 may be not included in the value calculated here because
4073 of possible removing caller-saves insns (see function
4074 delete_caller_save_insns. */
4075 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
4076 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4080 CLEAR_REG_SET (&changed_allocation_pseudos);
4081 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4082 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4084 int regno = reg_renumber[i];
4085 if (reg_old_renumber[i] == regno)
4088 SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4090 alter_reg (i, reg_old_renumber[i], false);
4091 reg_old_renumber[i] = regno;
4095 fprintf (dump_file, " Register %d now on stack.\n\n", i);
4097 fprintf (dump_file, " Register %d now in %d.\n\n",
4098 i, reg_renumber[i]);
4102 return something_changed;
4105 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4108 scan_paradoxical_subregs (rtx x)
4112 enum rtx_code code = GET_CODE (x);
4123 case CONST_VECTOR: /* shouldn't happen, but just in case. */
4131 if (REG_P (SUBREG_REG (x))
4132 && (GET_MODE_SIZE (GET_MODE (x))
4133 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
4135 reg_max_ref_width[REGNO (SUBREG_REG (x))]
4136 = GET_MODE_SIZE (GET_MODE (x));
4137 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
4145 fmt = GET_RTX_FORMAT (code);
4146 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4149 scan_paradoxical_subregs (XEXP (x, i));
4150 else if (fmt[i] == 'E')
4153 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4154 scan_paradoxical_subregs (XVECEXP (x, i, j));
4159 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4160 examine all of the reload insns between PREV and NEXT exclusive, and
4161 annotate all that may trap. */
4164 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
4166 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4169 if (!insn_could_throw_p (insn))
4170 remove_note (insn, note);
4171 copy_reg_eh_region_note_forward (note, NEXT_INSN (prev), next);
4174 /* Reload pseudo-registers into hard regs around each insn as needed.
4175 Additional register load insns are output before the insn that needs it
4176 and perhaps store insns after insns that modify the reloaded pseudo reg.
4178 reg_last_reload_reg and reg_reloaded_contents keep track of
4179 which registers are already available in reload registers.
4180 We update these for the reloads that we perform,
4181 as the insns are scanned. */
4184 reload_as_needed (int live_known)
4186 struct insn_chain *chain;
4187 #if defined (AUTO_INC_DEC)
4192 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4193 memset (spill_reg_store, 0, sizeof spill_reg_store);
4194 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4195 INIT_REG_SET (®_has_output_reload);
4196 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4197 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4199 set_initial_elim_offsets ();
4201 for (chain = reload_insn_chain; chain; chain = chain->next)
4204 rtx insn = chain->insn;
4205 rtx old_next = NEXT_INSN (insn);
4207 rtx old_prev = PREV_INSN (insn);
4210 /* If we pass a label, copy the offsets from the label information
4211 into the current offsets of each elimination. */
4213 set_offsets_for_label (insn);
4215 else if (INSN_P (insn))
4217 regset_head regs_to_forget;
4218 INIT_REG_SET (®s_to_forget);
4219 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4221 /* If this is a USE and CLOBBER of a MEM, ensure that any
4222 references to eliminable registers have been removed. */
4224 if ((GET_CODE (PATTERN (insn)) == USE
4225 || GET_CODE (PATTERN (insn)) == CLOBBER)
4226 && MEM_P (XEXP (PATTERN (insn), 0)))
4227 XEXP (XEXP (PATTERN (insn), 0), 0)
4228 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4229 GET_MODE (XEXP (PATTERN (insn), 0)),
4232 /* If we need to do register elimination processing, do so.
4233 This might delete the insn, in which case we are done. */
4234 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4236 eliminate_regs_in_insn (insn, 1);
4239 update_eliminable_offsets ();
4240 CLEAR_REG_SET (®s_to_forget);
4245 /* If need_elim is nonzero but need_reload is zero, one might think
4246 that we could simply set n_reloads to 0. However, find_reloads
4247 could have done some manipulation of the insn (such as swapping
4248 commutative operands), and these manipulations are lost during
4249 the first pass for every insn that needs register elimination.
4250 So the actions of find_reloads must be redone here. */
4252 if (! chain->need_elim && ! chain->need_reload
4253 && ! chain->need_operand_change)
4255 /* First find the pseudo regs that must be reloaded for this insn.
4256 This info is returned in the tables reload_... (see reload.h).
4257 Also modify the body of INSN by substituting RELOAD
4258 rtx's for those pseudo regs. */
4261 CLEAR_REG_SET (®_has_output_reload);
4262 CLEAR_HARD_REG_SET (reg_is_output_reload);
4264 find_reloads (insn, 1, spill_indirect_levels, live_known,
4270 rtx next = NEXT_INSN (insn);
4273 prev = PREV_INSN (insn);
4275 /* Now compute which reload regs to reload them into. Perhaps
4276 reusing reload regs from previous insns, or else output
4277 load insns to reload them. Maybe output store insns too.
4278 Record the choices of reload reg in reload_reg_rtx. */
4279 choose_reload_regs (chain);
4281 /* Merge any reloads that we didn't combine for fear of
4282 increasing the number of spill registers needed but now
4283 discover can be safely merged. */
4284 if (targetm.small_register_classes_for_mode_p (VOIDmode))
4285 merge_assigned_reloads (insn);
4287 /* Generate the insns to reload operands into or out of
4288 their reload regs. */
4289 emit_reload_insns (chain);
4291 /* Substitute the chosen reload regs from reload_reg_rtx
4292 into the insn's body (or perhaps into the bodies of other
4293 load and store insn that we just made for reloading
4294 and that we moved the structure into). */
4295 subst_reloads (insn);
4297 /* Adjust the exception region notes for loads and stores. */
4298 if (flag_non_call_exceptions && !CALL_P (insn))
4299 fixup_eh_region_note (insn, prev, next);
4301 /* If this was an ASM, make sure that all the reload insns
4302 we have generated are valid. If not, give an error
4304 if (asm_noperands (PATTERN (insn)) >= 0)
4305 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4306 if (p != insn && INSN_P (p)
4307 && GET_CODE (PATTERN (p)) != USE
4308 && (recog_memoized (p) < 0
4309 || (extract_insn (p), ! constrain_operands (1))))
4311 error_for_asm (insn,
4312 "%<asm%> operand requires "
4313 "impossible reload");
4318 if (num_eliminable && chain->need_elim)
4319 update_eliminable_offsets ();
4321 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4322 is no longer validly lying around to save a future reload.
4323 Note that this does not detect pseudos that were reloaded
4324 for this insn in order to be stored in
4325 (obeying register constraints). That is correct; such reload
4326 registers ARE still valid. */
4327 forget_marked_reloads (®s_to_forget);
4328 CLEAR_REG_SET (®s_to_forget);
4330 /* There may have been CLOBBER insns placed after INSN. So scan
4331 between INSN and NEXT and use them to forget old reloads. */
4332 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4333 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4334 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4337 /* Likewise for regs altered by auto-increment in this insn.
4338 REG_INC notes have been changed by reloading:
4339 find_reloads_address_1 records substitutions for them,
4340 which have been performed by subst_reloads above. */
4341 for (i = n_reloads - 1; i >= 0; i--)
4343 rtx in_reg = rld[i].in_reg;
4346 enum rtx_code code = GET_CODE (in_reg);
4347 /* PRE_INC / PRE_DEC will have the reload register ending up
4348 with the same value as the stack slot, but that doesn't
4349 hold true for POST_INC / POST_DEC. Either we have to
4350 convert the memory access to a true POST_INC / POST_DEC,
4351 or we can't use the reload register for inheritance. */
4352 if ((code == POST_INC || code == POST_DEC)
4353 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4354 REGNO (rld[i].reg_rtx))
4355 /* Make sure it is the inc/dec pseudo, and not
4356 some other (e.g. output operand) pseudo. */
4357 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4358 == REGNO (XEXP (in_reg, 0))))
4361 rtx reload_reg = rld[i].reg_rtx;
4362 enum machine_mode mode = GET_MODE (reload_reg);
4366 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4368 /* We really want to ignore REG_INC notes here, so
4369 use PATTERN (p) as argument to reg_set_p . */
4370 if (reg_set_p (reload_reg, PATTERN (p)))
4372 n = count_occurrences (PATTERN (p), reload_reg, 0);
4378 = gen_rtx_fmt_e (code, mode, reload_reg);
4380 validate_replace_rtx_group (reload_reg,
4382 n = verify_changes (0);
4384 /* We must also verify that the constraints
4385 are met after the replacement. Make sure
4386 extract_insn is only called for an insn
4387 where the replacements were found to be
4392 n = constrain_operands (1);
4395 /* If the constraints were not met, then
4396 undo the replacement, else confirm it. */
4400 confirm_change_group ();
4406 add_reg_note (p, REG_INC, reload_reg);
4407 /* Mark this as having an output reload so that the
4408 REG_INC processing code below won't invalidate
4409 the reload for inheritance. */
4410 SET_HARD_REG_BIT (reg_is_output_reload,
4411 REGNO (reload_reg));
4412 SET_REGNO_REG_SET (®_has_output_reload,
4413 REGNO (XEXP (in_reg, 0)));
4416 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4419 else if ((code == PRE_INC || code == PRE_DEC)
4420 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4421 REGNO (rld[i].reg_rtx))
4422 /* Make sure it is the inc/dec pseudo, and not
4423 some other (e.g. output operand) pseudo. */
4424 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4425 == REGNO (XEXP (in_reg, 0))))
4427 SET_HARD_REG_BIT (reg_is_output_reload,
4428 REGNO (rld[i].reg_rtx));
4429 SET_REGNO_REG_SET (®_has_output_reload,
4430 REGNO (XEXP (in_reg, 0)));
4432 else if (code == PRE_INC || code == PRE_DEC
4433 || code == POST_INC || code == POST_DEC)
4435 int in_regno = REGNO (XEXP (in_reg, 0));
4437 if (reg_last_reload_reg[in_regno] != NULL_RTX)
4440 bool forget_p = true;
4442 in_hard_regno = REGNO (reg_last_reload_reg[in_regno]);
4443 if (TEST_HARD_REG_BIT (reg_reloaded_valid,
4446 for (x = old_prev ? NEXT_INSN (old_prev) : insn;
4449 if (x == reg_reloaded_insn[in_hard_regno])
4455 /* If for some reasons, we didn't set up
4456 reg_last_reload_reg in this insn,
4457 invalidate inheritance from previous
4458 insns for the incremented/decremented
4459 register. Such registers will be not in
4460 reg_has_output_reload. Invalidate it
4461 also if the corresponding element in
4462 reg_reloaded_insn is also
4465 forget_old_reloads_1 (XEXP (in_reg, 0),
4471 /* If a pseudo that got a hard register is auto-incremented,
4472 we must purge records of copying it into pseudos without
4474 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4475 if (REG_NOTE_KIND (x) == REG_INC)
4477 /* See if this pseudo reg was reloaded in this insn.
4478 If so, its last-reload info is still valid
4479 because it is based on this insn's reload. */
4480 for (i = 0; i < n_reloads; i++)
4481 if (rld[i].out == XEXP (x, 0))
4485 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4489 /* A reload reg's contents are unknown after a label. */
4491 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4493 /* Don't assume a reload reg is still good after a call insn
4494 if it is a call-used reg, or if it contains a value that will
4495 be partially clobbered by the call. */
4496 else if (CALL_P (insn))
4498 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4499 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4504 free (reg_last_reload_reg);
4505 CLEAR_REG_SET (®_has_output_reload);
4508 /* Discard all record of any value reloaded from X,
4509 or reloaded in X from someplace else;
4510 unless X is an output reload reg of the current insn.
4512 X may be a hard reg (the reload reg)
4513 or it may be a pseudo reg that was reloaded from.
4515 When DATA is non-NULL just mark the registers in regset
4516 to be forgotten later. */
4519 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4524 regset regs = (regset) data;
4526 /* note_stores does give us subregs of hard regs,
4527 subreg_regno_offset requires a hard reg. */
4528 while (GET_CODE (x) == SUBREG)
4530 /* We ignore the subreg offset when calculating the regno,
4531 because we are using the entire underlying hard register
4541 if (regno >= FIRST_PSEUDO_REGISTER)
4547 nr = hard_regno_nregs[regno][GET_MODE (x)];
4548 /* Storing into a spilled-reg invalidates its contents.
4549 This can happen if a block-local pseudo is allocated to that reg
4550 and it wasn't spilled because this block's total need is 0.
4551 Then some insn might have an optional reload and use this reg. */
4553 for (i = 0; i < nr; i++)
4554 /* But don't do this if the reg actually serves as an output
4555 reload reg in the current instruction. */
4557 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4559 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4560 spill_reg_store[regno + i] = 0;
4566 SET_REGNO_REG_SET (regs, regno + nr);
4569 /* Since value of X has changed,
4570 forget any value previously copied from it. */
4573 /* But don't forget a copy if this is the output reload
4574 that establishes the copy's validity. */
4576 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4577 reg_last_reload_reg[regno + nr] = 0;
4581 /* Forget the reloads marked in regset by previous function. */
4583 forget_marked_reloads (regset regs)
4586 reg_set_iterator rsi;
4587 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4589 if (reg < FIRST_PSEUDO_REGISTER
4590 /* But don't do this if the reg actually serves as an output
4591 reload reg in the current instruction. */
4593 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4595 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4596 spill_reg_store[reg] = 0;
4599 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4600 reg_last_reload_reg[reg] = 0;
4604 /* The following HARD_REG_SETs indicate when each hard register is
4605 used for a reload of various parts of the current insn. */
4607 /* If reg is unavailable for all reloads. */
4608 static HARD_REG_SET reload_reg_unavailable;
4609 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4610 static HARD_REG_SET reload_reg_used;
4611 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4612 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4613 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4614 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4615 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4616 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4617 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4618 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4619 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4620 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4621 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4622 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4623 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4624 static HARD_REG_SET reload_reg_used_in_op_addr;
4625 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4626 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4627 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4628 static HARD_REG_SET reload_reg_used_in_insn;
4629 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4630 static HARD_REG_SET reload_reg_used_in_other_addr;
4632 /* If reg is in use as a reload reg for any sort of reload. */
4633 static HARD_REG_SET reload_reg_used_at_all;
4635 /* If reg is use as an inherited reload. We just mark the first register
4637 static HARD_REG_SET reload_reg_used_for_inherit;
4639 /* Records which hard regs are used in any way, either as explicit use or
4640 by being allocated to a pseudo during any point of the current insn. */
4641 static HARD_REG_SET reg_used_in_insn;
4643 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4644 TYPE. MODE is used to indicate how many consecutive regs are
4648 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4649 enum machine_mode mode)
4651 unsigned int nregs = hard_regno_nregs[regno][mode];
4654 for (i = regno; i < nregs + regno; i++)
4659 SET_HARD_REG_BIT (reload_reg_used, i);
4662 case RELOAD_FOR_INPUT_ADDRESS:
4663 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4666 case RELOAD_FOR_INPADDR_ADDRESS:
4667 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4670 case RELOAD_FOR_OUTPUT_ADDRESS:
4671 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4674 case RELOAD_FOR_OUTADDR_ADDRESS:
4675 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4678 case RELOAD_FOR_OPERAND_ADDRESS:
4679 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4682 case RELOAD_FOR_OPADDR_ADDR:
4683 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4686 case RELOAD_FOR_OTHER_ADDRESS:
4687 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4690 case RELOAD_FOR_INPUT:
4691 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4694 case RELOAD_FOR_OUTPUT:
4695 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4698 case RELOAD_FOR_INSN:
4699 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4703 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4707 /* Similarly, but show REGNO is no longer in use for a reload. */
4710 clear_reload_reg_in_use (unsigned int regno, int opnum,
4711 enum reload_type type, enum machine_mode mode)
4713 unsigned int nregs = hard_regno_nregs[regno][mode];
4714 unsigned int start_regno, end_regno, r;
4716 /* A complication is that for some reload types, inheritance might
4717 allow multiple reloads of the same types to share a reload register.
4718 We set check_opnum if we have to check only reloads with the same
4719 operand number, and check_any if we have to check all reloads. */
4720 int check_opnum = 0;
4722 HARD_REG_SET *used_in_set;
4727 used_in_set = &reload_reg_used;
4730 case RELOAD_FOR_INPUT_ADDRESS:
4731 used_in_set = &reload_reg_used_in_input_addr[opnum];
4734 case RELOAD_FOR_INPADDR_ADDRESS:
4736 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4739 case RELOAD_FOR_OUTPUT_ADDRESS:
4740 used_in_set = &reload_reg_used_in_output_addr[opnum];
4743 case RELOAD_FOR_OUTADDR_ADDRESS:
4745 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4748 case RELOAD_FOR_OPERAND_ADDRESS:
4749 used_in_set = &reload_reg_used_in_op_addr;
4752 case RELOAD_FOR_OPADDR_ADDR:
4754 used_in_set = &reload_reg_used_in_op_addr_reload;
4757 case RELOAD_FOR_OTHER_ADDRESS:
4758 used_in_set = &reload_reg_used_in_other_addr;
4762 case RELOAD_FOR_INPUT:
4763 used_in_set = &reload_reg_used_in_input[opnum];
4766 case RELOAD_FOR_OUTPUT:
4767 used_in_set = &reload_reg_used_in_output[opnum];
4770 case RELOAD_FOR_INSN:
4771 used_in_set = &reload_reg_used_in_insn;
4776 /* We resolve conflicts with remaining reloads of the same type by
4777 excluding the intervals of reload registers by them from the
4778 interval of freed reload registers. Since we only keep track of
4779 one set of interval bounds, we might have to exclude somewhat
4780 more than what would be necessary if we used a HARD_REG_SET here.
4781 But this should only happen very infrequently, so there should
4782 be no reason to worry about it. */
4784 start_regno = regno;
4785 end_regno = regno + nregs;
4786 if (check_opnum || check_any)
4788 for (i = n_reloads - 1; i >= 0; i--)
4790 if (rld[i].when_needed == type
4791 && (check_any || rld[i].opnum == opnum)
4794 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4795 unsigned int conflict_end
4796 = end_hard_regno (rld[i].mode, conflict_start);
4798 /* If there is an overlap with the first to-be-freed register,
4799 adjust the interval start. */
4800 if (conflict_start <= start_regno && conflict_end > start_regno)
4801 start_regno = conflict_end;
4802 /* Otherwise, if there is a conflict with one of the other
4803 to-be-freed registers, adjust the interval end. */
4804 if (conflict_start > start_regno && conflict_start < end_regno)
4805 end_regno = conflict_start;
4810 for (r = start_regno; r < end_regno; r++)
4811 CLEAR_HARD_REG_BIT (*used_in_set, r);
4814 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4815 specified by OPNUM and TYPE. */
4818 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4822 /* In use for a RELOAD_OTHER means it's not available for anything. */
4823 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4824 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4830 /* In use for anything means we can't use it for RELOAD_OTHER. */
4831 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4832 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4833 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4834 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4837 for (i = 0; i < reload_n_operands; i++)
4838 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4839 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4840 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4841 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4842 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4843 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4848 case RELOAD_FOR_INPUT:
4849 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4850 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4853 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4856 /* If it is used for some other input, can't use it. */
4857 for (i = 0; i < reload_n_operands; i++)
4858 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4861 /* If it is used in a later operand's address, can't use it. */
4862 for (i = opnum + 1; i < reload_n_operands; i++)
4863 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4864 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4869 case RELOAD_FOR_INPUT_ADDRESS:
4870 /* Can't use a register if it is used for an input address for this
4871 operand or used as an input in an earlier one. */
4872 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4873 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4876 for (i = 0; i < opnum; i++)
4877 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4882 case RELOAD_FOR_INPADDR_ADDRESS:
4883 /* Can't use a register if it is used for an input address
4884 for this operand or used as an input in an earlier
4886 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4889 for (i = 0; i < opnum; i++)
4890 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4895 case RELOAD_FOR_OUTPUT_ADDRESS:
4896 /* Can't use a register if it is used for an output address for this
4897 operand or used as an output in this or a later operand. Note
4898 that multiple output operands are emitted in reverse order, so
4899 the conflicting ones are those with lower indices. */
4900 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4903 for (i = 0; i <= opnum; i++)
4904 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4909 case RELOAD_FOR_OUTADDR_ADDRESS:
4910 /* Can't use a register if it is used for an output address
4911 for this operand or used as an output in this or a
4912 later operand. Note that multiple output operands are
4913 emitted in reverse order, so the conflicting ones are
4914 those with lower indices. */
4915 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4918 for (i = 0; i <= opnum; i++)
4919 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4924 case RELOAD_FOR_OPERAND_ADDRESS:
4925 for (i = 0; i < reload_n_operands; i++)
4926 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4929 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4930 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4932 case RELOAD_FOR_OPADDR_ADDR:
4933 for (i = 0; i < reload_n_operands; i++)
4934 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4937 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4939 case RELOAD_FOR_OUTPUT:
4940 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4941 outputs, or an operand address for this or an earlier output.
4942 Note that multiple output operands are emitted in reverse order,
4943 so the conflicting ones are those with higher indices. */
4944 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4947 for (i = 0; i < reload_n_operands; i++)
4948 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4951 for (i = opnum; i < reload_n_operands; i++)
4952 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4953 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4958 case RELOAD_FOR_INSN:
4959 for (i = 0; i < reload_n_operands; i++)
4960 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4961 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4964 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4965 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4967 case RELOAD_FOR_OTHER_ADDRESS:
4968 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4975 /* Return 1 if the value in reload reg REGNO, as used by a reload
4976 needed for the part of the insn specified by OPNUM and TYPE,
4977 is still available in REGNO at the end of the insn.
4979 We can assume that the reload reg was already tested for availability
4980 at the time it is needed, and we should not check this again,
4981 in case the reg has already been marked in use. */
4984 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4991 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4992 its value must reach the end. */
4995 /* If this use is for part of the insn,
4996 its value reaches if no subsequent part uses the same register.
4997 Just like the above function, don't try to do this with lots
5000 case RELOAD_FOR_OTHER_ADDRESS:
5001 /* Here we check for everything else, since these don't conflict
5002 with anything else and everything comes later. */
5004 for (i = 0; i < reload_n_operands; i++)
5005 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5006 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5007 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
5008 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5009 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5010 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5013 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5014 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5015 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5016 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
5018 case RELOAD_FOR_INPUT_ADDRESS:
5019 case RELOAD_FOR_INPADDR_ADDRESS:
5020 /* Similar, except that we check only for this and subsequent inputs
5021 and the address of only subsequent inputs and we do not need
5022 to check for RELOAD_OTHER objects since they are known not to
5025 for (i = opnum; i < reload_n_operands; i++)
5026 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5029 for (i = opnum + 1; i < reload_n_operands; i++)
5030 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5031 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5034 for (i = 0; i < reload_n_operands; i++)
5035 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5036 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5037 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5040 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5043 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5044 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5045 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5047 case RELOAD_FOR_INPUT:
5048 /* Similar to input address, except we start at the next operand for
5049 both input and input address and we do not check for
5050 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5053 for (i = opnum + 1; i < reload_n_operands; i++)
5054 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5055 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5056 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5059 /* ... fall through ... */
5061 case RELOAD_FOR_OPERAND_ADDRESS:
5062 /* Check outputs and their addresses. */
5064 for (i = 0; i < reload_n_operands; i++)
5065 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5066 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5067 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5070 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5072 case RELOAD_FOR_OPADDR_ADDR:
5073 for (i = 0; i < reload_n_operands; i++)
5074 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5075 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5076 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5079 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5080 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5081 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5083 case RELOAD_FOR_INSN:
5084 /* These conflict with other outputs with RELOAD_OTHER. So
5085 we need only check for output addresses. */
5087 opnum = reload_n_operands;
5089 /* ... fall through ... */
5091 case RELOAD_FOR_OUTPUT:
5092 case RELOAD_FOR_OUTPUT_ADDRESS:
5093 case RELOAD_FOR_OUTADDR_ADDRESS:
5094 /* We already know these can't conflict with a later output. So the
5095 only thing to check are later output addresses.
5096 Note that multiple output operands are emitted in reverse order,
5097 so the conflicting ones are those with lower indices. */
5098 for (i = 0; i < opnum; i++)
5099 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5100 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5110 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5111 every register in the range [REGNO, REGNO + NREGS). */
5114 reload_regs_reach_end_p (unsigned int regno, int nregs,
5115 int opnum, enum reload_type type)
5119 for (i = 0; i < nregs; i++)
5120 if (!reload_reg_reaches_end_p (regno + i, opnum, type))
5126 /* Returns whether R1 and R2 are uniquely chained: the value of one
5127 is used by the other, and that value is not used by any other
5128 reload for this insn. This is used to partially undo the decision
5129 made in find_reloads when in the case of multiple
5130 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5131 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5132 reloads. This code tries to avoid the conflict created by that
5133 change. It might be cleaner to explicitly keep track of which
5134 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5135 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5136 this after the fact. */
5138 reloads_unique_chain_p (int r1, int r2)
5142 /* We only check input reloads. */
5143 if (! rld[r1].in || ! rld[r2].in)
5146 /* Avoid anything with output reloads. */
5147 if (rld[r1].out || rld[r2].out)
5150 /* "chained" means one reload is a component of the other reload,
5151 not the same as the other reload. */
5152 if (rld[r1].opnum != rld[r2].opnum
5153 || rtx_equal_p (rld[r1].in, rld[r2].in)
5154 || rld[r1].optional || rld[r2].optional
5155 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5156 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5159 for (i = 0; i < n_reloads; i ++)
5160 /* Look for input reloads that aren't our two */
5161 if (i != r1 && i != r2 && rld[i].in)
5163 /* If our reload is mentioned at all, it isn't a simple chain. */
5164 if (reg_mentioned_p (rld[r1].in, rld[i].in))
5170 /* The recursive function change all occurrences of WHAT in *WHERE
5173 substitute (rtx *where, const_rtx what, rtx repl)
5182 if (*where == what || rtx_equal_p (*where, what))
5184 /* Record the location of the changed rtx. */
5185 VEC_safe_push (rtx_p, heap, substitute_stack, where);
5190 code = GET_CODE (*where);
5191 fmt = GET_RTX_FORMAT (code);
5192 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5198 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5199 substitute (&XVECEXP (*where, i, j), what, repl);
5201 else if (fmt[i] == 'e')
5202 substitute (&XEXP (*where, i), what, repl);
5206 /* The function returns TRUE if chain of reload R1 and R2 (in any
5207 order) can be evaluated without usage of intermediate register for
5208 the reload containing another reload. It is important to see
5209 gen_reload to understand what the function is trying to do. As an
5210 example, let us have reload chain
5213 r1: <something> + const
5215 and reload R2 got reload reg HR. The function returns true if
5216 there is a correct insn HR = HR + <something>. Otherwise,
5217 gen_reload will use intermediate register (and this is the reload
5218 reg for R1) to reload <something>.
5220 We need this function to find a conflict for chain reloads. In our
5221 example, if HR = HR + <something> is incorrect insn, then we cannot
5222 use HR as a reload register for R2. If we do use it then we get a
5231 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5233 /* Assume other cases in gen_reload are not possible for
5234 chain reloads or do need an intermediate hard registers. */
5237 rtx out, in, tem, insn;
5238 rtx last = get_last_insn ();
5240 /* Make r2 a component of r1. */
5241 if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5247 gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5248 regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5249 gcc_assert (regno >= 0);
5250 out = gen_rtx_REG (rld[r1].mode, regno);
5252 substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5254 /* If IN is a paradoxical SUBREG, remove it and try to put the
5255 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5256 if (GET_CODE (in) == SUBREG
5257 && (GET_MODE_SIZE (GET_MODE (in))
5258 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
5259 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
5260 in = SUBREG_REG (in), out = tem;
5262 if (GET_CODE (in) == PLUS
5263 && (REG_P (XEXP (in, 0))
5264 || GET_CODE (XEXP (in, 0)) == SUBREG
5265 || MEM_P (XEXP (in, 0)))
5266 && (REG_P (XEXP (in, 1))
5267 || GET_CODE (XEXP (in, 1)) == SUBREG
5268 || CONSTANT_P (XEXP (in, 1))
5269 || MEM_P (XEXP (in, 1))))
5271 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
5272 code = recog_memoized (insn);
5277 extract_insn (insn);
5278 /* We want constrain operands to treat this insn strictly in
5279 its validity determination, i.e., the way it would after
5280 reload has completed. */
5281 result = constrain_operands (1);
5284 delete_insns_since (last);
5287 /* Restore the original value at each changed address within R1. */
5288 while (!VEC_empty (rtx_p, substitute_stack))
5290 rtx *where = VEC_pop (rtx_p, substitute_stack);
5291 *where = rld[r2].in;
5297 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5300 This function uses the same algorithm as reload_reg_free_p above. */
5303 reloads_conflict (int r1, int r2)
5305 enum reload_type r1_type = rld[r1].when_needed;
5306 enum reload_type r2_type = rld[r2].when_needed;
5307 int r1_opnum = rld[r1].opnum;
5308 int r2_opnum = rld[r2].opnum;
5310 /* RELOAD_OTHER conflicts with everything. */
5311 if (r2_type == RELOAD_OTHER)
5314 /* Otherwise, check conflicts differently for each type. */
5318 case RELOAD_FOR_INPUT:
5319 return (r2_type == RELOAD_FOR_INSN
5320 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5321 || r2_type == RELOAD_FOR_OPADDR_ADDR
5322 || r2_type == RELOAD_FOR_INPUT
5323 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5324 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5325 && r2_opnum > r1_opnum));
5327 case RELOAD_FOR_INPUT_ADDRESS:
5328 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5329 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5331 case RELOAD_FOR_INPADDR_ADDRESS:
5332 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5333 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5335 case RELOAD_FOR_OUTPUT_ADDRESS:
5336 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5337 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5339 case RELOAD_FOR_OUTADDR_ADDRESS:
5340 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5341 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5343 case RELOAD_FOR_OPERAND_ADDRESS:
5344 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5345 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5346 && (!reloads_unique_chain_p (r1, r2)
5347 || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5349 case RELOAD_FOR_OPADDR_ADDR:
5350 return (r2_type == RELOAD_FOR_INPUT
5351 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5353 case RELOAD_FOR_OUTPUT:
5354 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5355 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5356 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5357 && r2_opnum >= r1_opnum));
5359 case RELOAD_FOR_INSN:
5360 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5361 || r2_type == RELOAD_FOR_INSN
5362 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5364 case RELOAD_FOR_OTHER_ADDRESS:
5365 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5375 /* Indexed by reload number, 1 if incoming value
5376 inherited from previous insns. */
5377 static char reload_inherited[MAX_RELOADS];
5379 /* For an inherited reload, this is the insn the reload was inherited from,
5380 if we know it. Otherwise, this is 0. */
5381 static rtx reload_inheritance_insn[MAX_RELOADS];
5383 /* If nonzero, this is a place to get the value of the reload,
5384 rather than using reload_in. */
5385 static rtx reload_override_in[MAX_RELOADS];
5387 /* For each reload, the hard register number of the register used,
5388 or -1 if we did not need a register for this reload. */
5389 static int reload_spill_index[MAX_RELOADS];
5391 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5392 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5394 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5395 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5397 /* Subroutine of free_for_value_p, used to check a single register.
5398 START_REGNO is the starting regno of the full reload register
5399 (possibly comprising multiple hard registers) that we are considering. */
5402 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5403 enum reload_type type, rtx value, rtx out,
5404 int reloadnum, int ignore_address_reloads)
5407 /* Set if we see an input reload that must not share its reload register
5408 with any new earlyclobber, but might otherwise share the reload
5409 register with an output or input-output reload. */
5410 int check_earlyclobber = 0;
5414 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5417 if (out == const0_rtx)
5423 /* We use some pseudo 'time' value to check if the lifetimes of the
5424 new register use would overlap with the one of a previous reload
5425 that is not read-only or uses a different value.
5426 The 'time' used doesn't have to be linear in any shape or form, just
5428 Some reload types use different 'buckets' for each operand.
5429 So there are MAX_RECOG_OPERANDS different time values for each
5431 We compute TIME1 as the time when the register for the prospective
5432 new reload ceases to be live, and TIME2 for each existing
5433 reload as the time when that the reload register of that reload
5435 Where there is little to be gained by exact lifetime calculations,
5436 we just make conservative assumptions, i.e. a longer lifetime;
5437 this is done in the 'default:' cases. */
5440 case RELOAD_FOR_OTHER_ADDRESS:
5441 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5442 time1 = copy ? 0 : 1;
5445 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5447 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5448 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5449 respectively, to the time values for these, we get distinct time
5450 values. To get distinct time values for each operand, we have to
5451 multiply opnum by at least three. We round that up to four because
5452 multiply by four is often cheaper. */
5453 case RELOAD_FOR_INPADDR_ADDRESS:
5454 time1 = opnum * 4 + 2;
5456 case RELOAD_FOR_INPUT_ADDRESS:
5457 time1 = opnum * 4 + 3;
5459 case RELOAD_FOR_INPUT:
5460 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5461 executes (inclusive). */
5462 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5464 case RELOAD_FOR_OPADDR_ADDR:
5466 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5467 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5469 case RELOAD_FOR_OPERAND_ADDRESS:
5470 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5472 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5474 case RELOAD_FOR_OUTADDR_ADDRESS:
5475 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5477 case RELOAD_FOR_OUTPUT_ADDRESS:
5478 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5481 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5484 for (i = 0; i < n_reloads; i++)
5486 rtx reg = rld[i].reg_rtx;
5487 if (reg && REG_P (reg)
5488 && ((unsigned) regno - true_regnum (reg)
5489 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5492 rtx other_input = rld[i].in;
5494 /* If the other reload loads the same input value, that
5495 will not cause a conflict only if it's loading it into
5496 the same register. */
5497 if (true_regnum (reg) != start_regno)
5498 other_input = NULL_RTX;
5499 if (! other_input || ! rtx_equal_p (other_input, value)
5500 || rld[i].out || out)
5503 switch (rld[i].when_needed)
5505 case RELOAD_FOR_OTHER_ADDRESS:
5508 case RELOAD_FOR_INPADDR_ADDRESS:
5509 /* find_reloads makes sure that a
5510 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5511 by at most one - the first -
5512 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5513 address reload is inherited, the address address reload
5514 goes away, so we can ignore this conflict. */
5515 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5516 && ignore_address_reloads
5517 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5518 Then the address address is still needed to store
5519 back the new address. */
5520 && ! rld[reloadnum].out)
5522 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5523 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5525 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5526 && ignore_address_reloads
5527 /* Unless we are reloading an auto_inc expression. */
5528 && ! rld[reloadnum].out)
5530 time2 = rld[i].opnum * 4 + 2;
5532 case RELOAD_FOR_INPUT_ADDRESS:
5533 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5534 && ignore_address_reloads
5535 && ! rld[reloadnum].out)
5537 time2 = rld[i].opnum * 4 + 3;
5539 case RELOAD_FOR_INPUT:
5540 time2 = rld[i].opnum * 4 + 4;
5541 check_earlyclobber = 1;
5543 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5544 == MAX_RECOG_OPERAND * 4 */
5545 case RELOAD_FOR_OPADDR_ADDR:
5546 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5547 && ignore_address_reloads
5548 && ! rld[reloadnum].out)
5550 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5552 case RELOAD_FOR_OPERAND_ADDRESS:
5553 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5554 check_earlyclobber = 1;
5556 case RELOAD_FOR_INSN:
5557 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5559 case RELOAD_FOR_OUTPUT:
5560 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5561 instruction is executed. */
5562 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5564 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5565 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5567 case RELOAD_FOR_OUTADDR_ADDRESS:
5568 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5569 && ignore_address_reloads
5570 && ! rld[reloadnum].out)
5572 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5574 case RELOAD_FOR_OUTPUT_ADDRESS:
5575 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5578 /* If there is no conflict in the input part, handle this
5579 like an output reload. */
5580 if (! rld[i].in || rtx_equal_p (other_input, value))
5582 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5583 /* Earlyclobbered outputs must conflict with inputs. */
5584 if (earlyclobber_operand_p (rld[i].out))
5585 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5590 /* RELOAD_OTHER might be live beyond instruction execution,
5591 but this is not obvious when we set time2 = 1. So check
5592 here if there might be a problem with the new reload
5593 clobbering the register used by the RELOAD_OTHER. */
5601 && (! rld[i].in || rld[i].out
5602 || ! rtx_equal_p (other_input, value)))
5603 || (out && rld[reloadnum].out_reg
5604 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5610 /* Earlyclobbered outputs must conflict with inputs. */
5611 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5617 /* Return 1 if the value in reload reg REGNO, as used by a reload
5618 needed for the part of the insn specified by OPNUM and TYPE,
5619 may be used to load VALUE into it.
5621 MODE is the mode in which the register is used, this is needed to
5622 determine how many hard regs to test.
5624 Other read-only reloads with the same value do not conflict
5625 unless OUT is nonzero and these other reloads have to live while
5626 output reloads live.
5627 If OUT is CONST0_RTX, this is a special case: it means that the
5628 test should not be for using register REGNO as reload register, but
5629 for copying from register REGNO into the reload register.
5631 RELOADNUM is the number of the reload we want to load this value for;
5632 a reload does not conflict with itself.
5634 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5635 reloads that load an address for the very reload we are considering.
5637 The caller has to make sure that there is no conflict with the return
5641 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5642 enum reload_type type, rtx value, rtx out, int reloadnum,
5643 int ignore_address_reloads)
5645 int nregs = hard_regno_nregs[regno][mode];
5647 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5648 value, out, reloadnum,
5649 ignore_address_reloads))
5654 /* Return nonzero if the rtx X is invariant over the current function. */
5655 /* ??? Actually, the places where we use this expect exactly what is
5656 tested here, and not everything that is function invariant. In
5657 particular, the frame pointer and arg pointer are special cased;
5658 pic_offset_table_rtx is not, and we must not spill these things to
5662 function_invariant_p (const_rtx x)
5666 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5668 if (GET_CODE (x) == PLUS
5669 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5670 && CONSTANT_P (XEXP (x, 1)))
5675 /* Determine whether the reload reg X overlaps any rtx'es used for
5676 overriding inheritance. Return nonzero if so. */
5679 conflicts_with_override (rtx x)
5682 for (i = 0; i < n_reloads; i++)
5683 if (reload_override_in[i]
5684 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5689 /* Give an error message saying we failed to find a reload for INSN,
5690 and clear out reload R. */
5692 failed_reload (rtx insn, int r)
5694 if (asm_noperands (PATTERN (insn)) < 0)
5695 /* It's the compiler's fault. */
5696 fatal_insn ("could not find a spill register", insn);
5698 /* It's the user's fault; the operand's mode and constraint
5699 don't match. Disable this reload so we don't crash in final. */
5700 error_for_asm (insn,
5701 "%<asm%> operand constraint incompatible with operand size");
5705 rld[r].optional = 1;
5706 rld[r].secondary_p = 1;
5709 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5710 for reload R. If it's valid, get an rtx for it. Return nonzero if
5713 set_reload_reg (int i, int r)
5716 rtx reg = spill_reg_rtx[i];
5718 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5719 spill_reg_rtx[i] = reg
5720 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5722 regno = true_regnum (reg);
5724 /* Detect when the reload reg can't hold the reload mode.
5725 This used to be one `if', but Sequent compiler can't handle that. */
5726 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5728 enum machine_mode test_mode = VOIDmode;
5730 test_mode = GET_MODE (rld[r].in);
5731 /* If rld[r].in has VOIDmode, it means we will load it
5732 in whatever mode the reload reg has: to wit, rld[r].mode.
5733 We have already tested that for validity. */
5734 /* Aside from that, we need to test that the expressions
5735 to reload from or into have modes which are valid for this
5736 reload register. Otherwise the reload insns would be invalid. */
5737 if (! (rld[r].in != 0 && test_mode != VOIDmode
5738 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5739 if (! (rld[r].out != 0
5740 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5742 /* The reg is OK. */
5745 /* Mark as in use for this insn the reload regs we use
5747 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5748 rld[r].when_needed, rld[r].mode);
5750 rld[r].reg_rtx = reg;
5751 reload_spill_index[r] = spill_regs[i];
5758 /* Find a spill register to use as a reload register for reload R.
5759 LAST_RELOAD is nonzero if this is the last reload for the insn being
5762 Set rld[R].reg_rtx to the register allocated.
5764 We return 1 if successful, or 0 if we couldn't find a spill reg and
5765 we didn't change anything. */
5768 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5773 /* If we put this reload ahead, thinking it is a group,
5774 then insist on finding a group. Otherwise we can grab a
5775 reg that some other reload needs.
5776 (That can happen when we have a 68000 DATA_OR_FP_REG
5777 which is a group of data regs or one fp reg.)
5778 We need not be so restrictive if there are no more reloads
5781 ??? Really it would be nicer to have smarter handling
5782 for that kind of reg class, where a problem like this is normal.
5783 Perhaps those classes should be avoided for reloading
5784 by use of more alternatives. */
5786 int force_group = rld[r].nregs > 1 && ! last_reload;
5788 /* If we want a single register and haven't yet found one,
5789 take any reg in the right class and not in use.
5790 If we want a consecutive group, here is where we look for it.
5792 We use two passes so we can first look for reload regs to
5793 reuse, which are already in use for other reloads in this insn,
5794 and only then use additional registers.
5795 I think that maximizing reuse is needed to make sure we don't
5796 run out of reload regs. Suppose we have three reloads, and
5797 reloads A and B can share regs. These need two regs.
5798 Suppose A and B are given different regs.
5799 That leaves none for C. */
5800 for (pass = 0; pass < 2; pass++)
5802 /* I is the index in spill_regs.
5803 We advance it round-robin between insns to use all spill regs
5804 equally, so that inherited reloads have a chance
5805 of leapfrogging each other. */
5809 for (count = 0; count < n_spills; count++)
5811 int rclass = (int) rld[r].rclass;
5817 regnum = spill_regs[i];
5819 if ((reload_reg_free_p (regnum, rld[r].opnum,
5822 /* We check reload_reg_used to make sure we
5823 don't clobber the return register. */
5824 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5825 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5826 rld[r].when_needed, rld[r].in,
5828 && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
5829 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5830 /* Look first for regs to share, then for unshared. But
5831 don't share regs used for inherited reloads; they are
5832 the ones we want to preserve. */
5834 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5836 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5839 int nr = hard_regno_nregs[regnum][rld[r].mode];
5840 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5841 (on 68000) got us two FP regs. If NR is 1,
5842 we would reject both of them. */
5845 /* If we need only one reg, we have already won. */
5848 /* But reject a single reg if we demand a group. */
5853 /* Otherwise check that as many consecutive regs as we need
5854 are available here. */
5857 int regno = regnum + nr - 1;
5858 if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
5859 && spill_reg_order[regno] >= 0
5860 && reload_reg_free_p (regno, rld[r].opnum,
5861 rld[r].when_needed)))
5870 /* If we found something on pass 1, omit pass 2. */
5871 if (count < n_spills)
5875 /* We should have found a spill register by now. */
5876 if (count >= n_spills)
5879 /* I is the index in SPILL_REG_RTX of the reload register we are to
5880 allocate. Get an rtx for it and find its register number. */
5882 return set_reload_reg (i, r);
5885 /* Initialize all the tables needed to allocate reload registers.
5886 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5887 is the array we use to restore the reg_rtx field for every reload. */
5890 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5894 for (i = 0; i < n_reloads; i++)
5895 rld[i].reg_rtx = save_reload_reg_rtx[i];
5897 memset (reload_inherited, 0, MAX_RELOADS);
5898 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5899 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5901 CLEAR_HARD_REG_SET (reload_reg_used);
5902 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5903 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5904 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5905 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5906 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5908 CLEAR_HARD_REG_SET (reg_used_in_insn);
5911 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5912 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5913 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5914 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5915 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5916 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5919 for (i = 0; i < reload_n_operands; i++)
5921 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5922 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5923 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5924 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5925 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5926 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5929 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5931 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5933 for (i = 0; i < n_reloads; i++)
5934 /* If we have already decided to use a certain register,
5935 don't use it in another way. */
5937 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5938 rld[i].when_needed, rld[i].mode);
5941 /* Assign hard reg targets for the pseudo-registers we must reload
5942 into hard regs for this insn.
5943 Also output the instructions to copy them in and out of the hard regs.
5945 For machines with register classes, we are responsible for
5946 finding a reload reg in the proper class. */
5949 choose_reload_regs (struct insn_chain *chain)
5951 rtx insn = chain->insn;
5953 unsigned int max_group_size = 1;
5954 enum reg_class group_class = NO_REGS;
5955 int pass, win, inheritance;
5957 rtx save_reload_reg_rtx[MAX_RELOADS];
5959 /* In order to be certain of getting the registers we need,
5960 we must sort the reloads into order of increasing register class.
5961 Then our grabbing of reload registers will parallel the process
5962 that provided the reload registers.
5964 Also note whether any of the reloads wants a consecutive group of regs.
5965 If so, record the maximum size of the group desired and what
5966 register class contains all the groups needed by this insn. */
5968 for (j = 0; j < n_reloads; j++)
5970 reload_order[j] = j;
5971 if (rld[j].reg_rtx != NULL_RTX)
5973 gcc_assert (REG_P (rld[j].reg_rtx)
5974 && HARD_REGISTER_P (rld[j].reg_rtx));
5975 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
5978 reload_spill_index[j] = -1;
5980 if (rld[j].nregs > 1)
5982 max_group_size = MAX (rld[j].nregs, max_group_size);
5984 = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
5987 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5991 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5993 /* If -O, try first with inheritance, then turning it off.
5994 If not -O, don't do inheritance.
5995 Using inheritance when not optimizing leads to paradoxes
5996 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5997 because one side of the comparison might be inherited. */
5999 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
6001 choose_reload_regs_init (chain, save_reload_reg_rtx);
6003 /* Process the reloads in order of preference just found.
6004 Beyond this point, subregs can be found in reload_reg_rtx.
6006 This used to look for an existing reloaded home for all of the
6007 reloads, and only then perform any new reloads. But that could lose
6008 if the reloads were done out of reg-class order because a later
6009 reload with a looser constraint might have an old home in a register
6010 needed by an earlier reload with a tighter constraint.
6012 To solve this, we make two passes over the reloads, in the order
6013 described above. In the first pass we try to inherit a reload
6014 from a previous insn. If there is a later reload that needs a
6015 class that is a proper subset of the class being processed, we must
6016 also allocate a spill register during the first pass.
6018 Then make a second pass over the reloads to allocate any reloads
6019 that haven't been given registers yet. */
6021 for (j = 0; j < n_reloads; j++)
6023 int r = reload_order[j];
6024 rtx search_equiv = NULL_RTX;
6026 /* Ignore reloads that got marked inoperative. */
6027 if (rld[r].out == 0 && rld[r].in == 0
6028 && ! rld[r].secondary_p)
6031 /* If find_reloads chose to use reload_in or reload_out as a reload
6032 register, we don't need to chose one. Otherwise, try even if it
6033 found one since we might save an insn if we find the value lying
6035 Try also when reload_in is a pseudo without a hard reg. */
6036 if (rld[r].in != 0 && rld[r].reg_rtx != 0
6037 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
6038 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
6039 && !MEM_P (rld[r].in)
6040 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
6043 #if 0 /* No longer needed for correct operation.
6044 It might give better code, or might not; worth an experiment? */
6045 /* If this is an optional reload, we can't inherit from earlier insns
6046 until we are sure that any non-optional reloads have been allocated.
6047 The following code takes advantage of the fact that optional reloads
6048 are at the end of reload_order. */
6049 if (rld[r].optional != 0)
6050 for (i = 0; i < j; i++)
6051 if ((rld[reload_order[i]].out != 0
6052 || rld[reload_order[i]].in != 0
6053 || rld[reload_order[i]].secondary_p)
6054 && ! rld[reload_order[i]].optional
6055 && rld[reload_order[i]].reg_rtx == 0)
6056 allocate_reload_reg (chain, reload_order[i], 0);
6059 /* First see if this pseudo is already available as reloaded
6060 for a previous insn. We cannot try to inherit for reloads
6061 that are smaller than the maximum number of registers needed
6062 for groups unless the register we would allocate cannot be used
6065 We could check here to see if this is a secondary reload for
6066 an object that is already in a register of the desired class.
6067 This would avoid the need for the secondary reload register.
6068 But this is complex because we can't easily determine what
6069 objects might want to be loaded via this reload. So let a
6070 register be allocated here. In `emit_reload_insns' we suppress
6071 one of the loads in the case described above. */
6077 enum machine_mode mode = VOIDmode;
6081 else if (REG_P (rld[r].in))
6083 regno = REGNO (rld[r].in);
6084 mode = GET_MODE (rld[r].in);
6086 else if (REG_P (rld[r].in_reg))
6088 regno = REGNO (rld[r].in_reg);
6089 mode = GET_MODE (rld[r].in_reg);
6091 else if (GET_CODE (rld[r].in_reg) == SUBREG
6092 && REG_P (SUBREG_REG (rld[r].in_reg)))
6094 regno = REGNO (SUBREG_REG (rld[r].in_reg));
6095 if (regno < FIRST_PSEUDO_REGISTER)
6096 regno = subreg_regno (rld[r].in_reg);
6098 byte = SUBREG_BYTE (rld[r].in_reg);
6099 mode = GET_MODE (rld[r].in_reg);
6102 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6103 && REG_P (XEXP (rld[r].in_reg, 0)))
6105 regno = REGNO (XEXP (rld[r].in_reg, 0));
6106 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6107 rld[r].out = rld[r].in;
6111 /* This won't work, since REGNO can be a pseudo reg number.
6112 Also, it takes much more hair to keep track of all the things
6113 that can invalidate an inherited reload of part of a pseudoreg. */
6114 else if (GET_CODE (rld[r].in) == SUBREG
6115 && REG_P (SUBREG_REG (rld[r].in)))
6116 regno = subreg_regno (rld[r].in);
6120 && reg_last_reload_reg[regno] != 0
6121 #ifdef CANNOT_CHANGE_MODE_CLASS
6122 /* Verify that the register it's in can be used in
6124 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
6125 GET_MODE (reg_last_reload_reg[regno]),
6130 enum reg_class rclass = rld[r].rclass, last_class;
6131 rtx last_reg = reg_last_reload_reg[regno];
6132 enum machine_mode need_mode;
6134 i = REGNO (last_reg);
6135 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6136 last_class = REGNO_REG_CLASS (i);
6142 = smallest_mode_for_size
6143 (GET_MODE_BITSIZE (mode) + byte * BITS_PER_UNIT,
6144 GET_MODE_CLASS (mode) == MODE_PARTIAL_INT
6145 ? MODE_INT : GET_MODE_CLASS (mode));
6147 if ((GET_MODE_SIZE (GET_MODE (last_reg))
6148 >= GET_MODE_SIZE (need_mode))
6149 && reg_reloaded_contents[i] == regno
6150 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6151 && HARD_REGNO_MODE_OK (i, rld[r].mode)
6152 && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6153 /* Even if we can't use this register as a reload
6154 register, we might use it for reload_override_in,
6155 if copying it to the desired class is cheap
6157 || ((REGISTER_MOVE_COST (mode, last_class, rclass)
6158 < MEMORY_MOVE_COST (mode, rclass, 1))
6159 && (secondary_reload_class (1, rclass, mode,
6162 #ifdef SECONDARY_MEMORY_NEEDED
6163 && ! SECONDARY_MEMORY_NEEDED (last_class, rclass,
6168 && (rld[r].nregs == max_group_size
6169 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6171 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6172 rld[r].when_needed, rld[r].in,
6175 /* If a group is needed, verify that all the subsequent
6176 registers still have their values intact. */
6177 int nr = hard_regno_nregs[i][rld[r].mode];
6180 for (k = 1; k < nr; k++)
6181 if (reg_reloaded_contents[i + k] != regno
6182 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6190 last_reg = (GET_MODE (last_reg) == mode
6191 ? last_reg : gen_rtx_REG (mode, i));
6194 for (k = 0; k < nr; k++)
6195 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6198 /* We found a register that contains the
6199 value we need. If this register is the
6200 same as an `earlyclobber' operand of the
6201 current insn, just mark it as a place to
6202 reload from since we can't use it as the
6203 reload register itself. */
6205 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6206 if (reg_overlap_mentioned_for_reload_p
6207 (reg_last_reload_reg[regno],
6208 reload_earlyclobbers[i1]))
6211 if (i1 != n_earlyclobbers
6212 || ! (free_for_value_p (i, rld[r].mode,
6214 rld[r].when_needed, rld[r].in,
6216 /* Don't use it if we'd clobber a pseudo reg. */
6217 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6219 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6220 /* Don't clobber the frame pointer. */
6221 || (i == HARD_FRAME_POINTER_REGNUM
6222 && frame_pointer_needed
6224 /* Don't really use the inherited spill reg
6225 if we need it wider than we've got it. */
6226 || (GET_MODE_SIZE (rld[r].mode)
6227 > GET_MODE_SIZE (mode))
6230 /* If find_reloads chose reload_out as reload
6231 register, stay with it - that leaves the
6232 inherited register for subsequent reloads. */
6233 || (rld[r].out && rld[r].reg_rtx
6234 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6236 if (! rld[r].optional)
6238 reload_override_in[r] = last_reg;
6239 reload_inheritance_insn[r]
6240 = reg_reloaded_insn[i];
6246 /* We can use this as a reload reg. */
6247 /* Mark the register as in use for this part of
6249 mark_reload_reg_in_use (i,
6253 rld[r].reg_rtx = last_reg;
6254 reload_inherited[r] = 1;
6255 reload_inheritance_insn[r]
6256 = reg_reloaded_insn[i];
6257 reload_spill_index[r] = i;
6258 for (k = 0; k < nr; k++)
6259 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6267 /* Here's another way to see if the value is already lying around. */
6270 && ! reload_inherited[r]
6272 && (CONSTANT_P (rld[r].in)
6273 || GET_CODE (rld[r].in) == PLUS
6274 || REG_P (rld[r].in)
6275 || MEM_P (rld[r].in))
6276 && (rld[r].nregs == max_group_size
6277 || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6278 search_equiv = rld[r].in;
6279 /* If this is an output reload from a simple move insn, look
6280 if an equivalence for the input is available. */
6281 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
6283 rtx set = single_set (insn);
6286 && rtx_equal_p (rld[r].out, SET_DEST (set))
6287 && CONSTANT_P (SET_SRC (set)))
6288 search_equiv = SET_SRC (set);
6294 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6295 -1, NULL, 0, rld[r].mode);
6301 regno = REGNO (equiv);
6304 /* This must be a SUBREG of a hard register.
6305 Make a new REG since this might be used in an
6306 address and not all machines support SUBREGs
6308 gcc_assert (GET_CODE (equiv) == SUBREG);
6309 regno = subreg_regno (equiv);
6310 equiv = gen_rtx_REG (rld[r].mode, regno);
6311 /* If we choose EQUIV as the reload register, but the
6312 loop below decides to cancel the inheritance, we'll
6313 end up reloading EQUIV in rld[r].mode, not the mode
6314 it had originally. That isn't safe when EQUIV isn't
6315 available as a spill register since its value might
6316 still be live at this point. */
6317 for (i = regno; i < regno + (int) rld[r].nregs; i++)
6318 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6323 /* If we found a spill reg, reject it unless it is free
6324 and of the desired class. */
6328 int bad_for_class = 0;
6329 int max_regno = regno + rld[r].nregs;
6331 for (i = regno; i < max_regno; i++)
6333 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6335 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6340 && ! free_for_value_p (regno, rld[r].mode,
6341 rld[r].opnum, rld[r].when_needed,
6342 rld[r].in, rld[r].out, r, 1))
6347 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6350 /* We found a register that contains the value we need.
6351 If this register is the same as an `earlyclobber' operand
6352 of the current insn, just mark it as a place to reload from
6353 since we can't use it as the reload register itself. */
6356 for (i = 0; i < n_earlyclobbers; i++)
6357 if (reg_overlap_mentioned_for_reload_p (equiv,
6358 reload_earlyclobbers[i]))
6360 if (! rld[r].optional)
6361 reload_override_in[r] = equiv;
6366 /* If the equiv register we have found is explicitly clobbered
6367 in the current insn, it depends on the reload type if we
6368 can use it, use it for reload_override_in, or not at all.
6369 In particular, we then can't use EQUIV for a
6370 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6374 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6375 switch (rld[r].when_needed)
6377 case RELOAD_FOR_OTHER_ADDRESS:
6378 case RELOAD_FOR_INPADDR_ADDRESS:
6379 case RELOAD_FOR_INPUT_ADDRESS:
6380 case RELOAD_FOR_OPADDR_ADDR:
6383 case RELOAD_FOR_INPUT:
6384 case RELOAD_FOR_OPERAND_ADDRESS:
6385 if (! rld[r].optional)
6386 reload_override_in[r] = equiv;
6392 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6393 switch (rld[r].when_needed)
6395 case RELOAD_FOR_OTHER_ADDRESS:
6396 case RELOAD_FOR_INPADDR_ADDRESS:
6397 case RELOAD_FOR_INPUT_ADDRESS:
6398 case RELOAD_FOR_OPADDR_ADDR:
6399 case RELOAD_FOR_OPERAND_ADDRESS:
6400 case RELOAD_FOR_INPUT:
6403 if (! rld[r].optional)
6404 reload_override_in[r] = equiv;
6412 /* If we found an equivalent reg, say no code need be generated
6413 to load it, and use it as our reload reg. */
6415 && (regno != HARD_FRAME_POINTER_REGNUM
6416 || !frame_pointer_needed))
6418 int nr = hard_regno_nregs[regno][rld[r].mode];
6420 rld[r].reg_rtx = equiv;
6421 reload_spill_index[r] = regno;
6422 reload_inherited[r] = 1;
6424 /* If reg_reloaded_valid is not set for this register,
6425 there might be a stale spill_reg_store lying around.
6426 We must clear it, since otherwise emit_reload_insns
6427 might delete the store. */
6428 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6429 spill_reg_store[regno] = NULL_RTX;
6430 /* If any of the hard registers in EQUIV are spill
6431 registers, mark them as in use for this insn. */
6432 for (k = 0; k < nr; k++)
6434 i = spill_reg_order[regno + k];
6437 mark_reload_reg_in_use (regno, rld[r].opnum,
6440 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6447 /* If we found a register to use already, or if this is an optional
6448 reload, we are done. */
6449 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6453 /* No longer needed for correct operation. Might or might
6454 not give better code on the average. Want to experiment? */
6456 /* See if there is a later reload that has a class different from our
6457 class that intersects our class or that requires less register
6458 than our reload. If so, we must allocate a register to this
6459 reload now, since that reload might inherit a previous reload
6460 and take the only available register in our class. Don't do this
6461 for optional reloads since they will force all previous reloads
6462 to be allocated. Also don't do this for reloads that have been
6465 for (i = j + 1; i < n_reloads; i++)
6467 int s = reload_order[i];
6469 if ((rld[s].in == 0 && rld[s].out == 0
6470 && ! rld[s].secondary_p)
6474 if ((rld[s].rclass != rld[r].rclass
6475 && reg_classes_intersect_p (rld[r].rclass,
6477 || rld[s].nregs < rld[r].nregs)
6484 allocate_reload_reg (chain, r, j == n_reloads - 1);
6488 /* Now allocate reload registers for anything non-optional that
6489 didn't get one yet. */
6490 for (j = 0; j < n_reloads; j++)
6492 int r = reload_order[j];
6494 /* Ignore reloads that got marked inoperative. */
6495 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6498 /* Skip reloads that already have a register allocated or are
6500 if (rld[r].reg_rtx != 0 || rld[r].optional)
6503 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6507 /* If that loop got all the way, we have won. */
6514 /* Loop around and try without any inheritance. */
6519 /* First undo everything done by the failed attempt
6520 to allocate with inheritance. */
6521 choose_reload_regs_init (chain, save_reload_reg_rtx);
6523 /* Some sanity tests to verify that the reloads found in the first
6524 pass are identical to the ones we have now. */
6525 gcc_assert (chain->n_reloads == n_reloads);
6527 for (i = 0; i < n_reloads; i++)
6529 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6531 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6532 for (j = 0; j < n_spills; j++)
6533 if (spill_regs[j] == chain->rld[i].regno)
6534 if (! set_reload_reg (j, i))
6535 failed_reload (chain->insn, i);
6539 /* If we thought we could inherit a reload, because it seemed that
6540 nothing else wanted the same reload register earlier in the insn,
6541 verify that assumption, now that all reloads have been assigned.
6542 Likewise for reloads where reload_override_in has been set. */
6544 /* If doing expensive optimizations, do one preliminary pass that doesn't
6545 cancel any inheritance, but removes reloads that have been needed only
6546 for reloads that we know can be inherited. */
6547 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6549 for (j = 0; j < n_reloads; j++)
6551 int r = reload_order[j];
6553 if (reload_inherited[r] && rld[r].reg_rtx)
6554 check_reg = rld[r].reg_rtx;
6555 else if (reload_override_in[r]
6556 && (REG_P (reload_override_in[r])
6557 || GET_CODE (reload_override_in[r]) == SUBREG))
6558 check_reg = reload_override_in[r];
6561 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6562 rld[r].opnum, rld[r].when_needed, rld[r].in,
6563 (reload_inherited[r]
6564 ? rld[r].out : const0_rtx),
6569 reload_inherited[r] = 0;
6570 reload_override_in[r] = 0;
6572 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6573 reload_override_in, then we do not need its related
6574 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6575 likewise for other reload types.
6576 We handle this by removing a reload when its only replacement
6577 is mentioned in reload_in of the reload we are going to inherit.
6578 A special case are auto_inc expressions; even if the input is
6579 inherited, we still need the address for the output. We can
6580 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6581 If we succeeded removing some reload and we are doing a preliminary
6582 pass just to remove such reloads, make another pass, since the
6583 removal of one reload might allow us to inherit another one. */
6585 && rld[r].out != rld[r].in
6586 && remove_address_replacements (rld[r].in) && pass)
6591 /* Now that reload_override_in is known valid,
6592 actually override reload_in. */
6593 for (j = 0; j < n_reloads; j++)
6594 if (reload_override_in[j])
6595 rld[j].in = reload_override_in[j];
6597 /* If this reload won't be done because it has been canceled or is
6598 optional and not inherited, clear reload_reg_rtx so other
6599 routines (such as subst_reloads) don't get confused. */
6600 for (j = 0; j < n_reloads; j++)
6601 if (rld[j].reg_rtx != 0
6602 && ((rld[j].optional && ! reload_inherited[j])
6603 || (rld[j].in == 0 && rld[j].out == 0
6604 && ! rld[j].secondary_p)))
6606 int regno = true_regnum (rld[j].reg_rtx);
6608 if (spill_reg_order[regno] >= 0)
6609 clear_reload_reg_in_use (regno, rld[j].opnum,
6610 rld[j].when_needed, rld[j].mode);
6612 reload_spill_index[j] = -1;
6615 /* Record which pseudos and which spill regs have output reloads. */
6616 for (j = 0; j < n_reloads; j++)
6618 int r = reload_order[j];
6620 i = reload_spill_index[r];
6622 /* I is nonneg if this reload uses a register.
6623 If rld[r].reg_rtx is 0, this is an optional reload
6624 that we opted to ignore. */
6625 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6626 && rld[r].reg_rtx != 0)
6628 int nregno = REGNO (rld[r].out_reg);
6631 if (nregno < FIRST_PSEUDO_REGISTER)
6632 nr = hard_regno_nregs[nregno][rld[r].mode];
6635 SET_REGNO_REG_SET (®_has_output_reload,
6640 nr = hard_regno_nregs[i][rld[r].mode];
6642 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6645 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6646 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6647 || rld[r].when_needed == RELOAD_FOR_INSN);
6652 /* Deallocate the reload register for reload R. This is called from
6653 remove_address_replacements. */
6656 deallocate_reload_reg (int r)
6660 if (! rld[r].reg_rtx)
6662 regno = true_regnum (rld[r].reg_rtx);
6664 if (spill_reg_order[regno] >= 0)
6665 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6667 reload_spill_index[r] = -1;
6670 /* If the small_register_classes_for_mode_p target hook returns true for
6671 some machine modes, we may not have merged two reloads of the same item
6672 for fear that we might not have enough reload registers. However,
6673 normally they will get the same reload register and hence actually need
6674 not be loaded twice.
6676 Here we check for the most common case of this phenomenon: when we have
6677 a number of reloads for the same object, each of which were allocated
6678 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6679 reload, and is not modified in the insn itself. If we find such,
6680 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6681 This will not increase the number of spill registers needed and will
6682 prevent redundant code. */
6685 merge_assigned_reloads (rtx insn)
6689 /* Scan all the reloads looking for ones that only load values and
6690 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6691 assigned and not modified by INSN. */
6693 for (i = 0; i < n_reloads; i++)
6695 int conflicting_input = 0;
6696 int max_input_address_opnum = -1;
6697 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6699 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6700 || rld[i].out != 0 || rld[i].reg_rtx == 0
6701 || reg_set_p (rld[i].reg_rtx, insn))
6704 /* Look at all other reloads. Ensure that the only use of this
6705 reload_reg_rtx is in a reload that just loads the same value
6706 as we do. Note that any secondary reloads must be of the identical
6707 class since the values, modes, and result registers are the
6708 same, so we need not do anything with any secondary reloads. */
6710 for (j = 0; j < n_reloads; j++)
6712 if (i == j || rld[j].reg_rtx == 0
6713 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6717 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6718 && rld[j].opnum > max_input_address_opnum)
6719 max_input_address_opnum = rld[j].opnum;
6721 /* If the reload regs aren't exactly the same (e.g, different modes)
6722 or if the values are different, we can't merge this reload.
6723 But if it is an input reload, we might still merge
6724 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6726 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6727 || rld[j].out != 0 || rld[j].in == 0
6728 || ! rtx_equal_p (rld[i].in, rld[j].in))
6730 if (rld[j].when_needed != RELOAD_FOR_INPUT
6731 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6732 || rld[i].opnum > rld[j].opnum)
6733 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6735 conflicting_input = 1;
6736 if (min_conflicting_input_opnum > rld[j].opnum)
6737 min_conflicting_input_opnum = rld[j].opnum;
6741 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6742 we, in fact, found any matching reloads. */
6745 && max_input_address_opnum <= min_conflicting_input_opnum)
6747 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6749 for (j = 0; j < n_reloads; j++)
6750 if (i != j && rld[j].reg_rtx != 0
6751 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6752 && (! conflicting_input
6753 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6754 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6756 rld[i].when_needed = RELOAD_OTHER;
6758 reload_spill_index[j] = -1;
6759 transfer_replacements (i, j);
6762 /* If this is now RELOAD_OTHER, look for any reloads that
6763 load parts of this operand and set them to
6764 RELOAD_FOR_OTHER_ADDRESS if they were for inputs,
6765 RELOAD_OTHER for outputs. Note that this test is
6766 equivalent to looking for reloads for this operand
6769 We must take special care with RELOAD_FOR_OUTPUT_ADDRESS;
6770 it may share registers with a RELOAD_FOR_INPUT, so we can
6771 not change it to RELOAD_FOR_OTHER_ADDRESS. We should
6772 never need to, since we do not modify RELOAD_FOR_OUTPUT.
6774 It is possible that the RELOAD_FOR_OPERAND_ADDRESS
6775 instruction is assigned the same register as the earlier
6776 RELOAD_FOR_OTHER_ADDRESS instruction. Merging these two
6777 instructions will cause the RELOAD_FOR_OTHER_ADDRESS
6778 instruction to be deleted later on. */
6780 if (rld[i].when_needed == RELOAD_OTHER)
6781 for (j = 0; j < n_reloads; j++)
6783 && rld[j].when_needed != RELOAD_OTHER
6784 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6785 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6786 && rld[j].when_needed != RELOAD_FOR_OPERAND_ADDRESS
6787 && (! conflicting_input
6788 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6789 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6790 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6796 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6797 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6798 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6800 /* Check to see if we accidentally converted two
6801 reloads that use the same reload register with
6802 different inputs to the same type. If so, the
6803 resulting code won't work. */
6805 for (k = 0; k < j; k++)
6806 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6807 || rld[k].when_needed != rld[j].when_needed
6808 || !rtx_equal_p (rld[k].reg_rtx,
6810 || rtx_equal_p (rld[k].in,
6817 /* These arrays are filled by emit_reload_insns and its subroutines. */
6818 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6819 static rtx other_input_address_reload_insns = 0;
6820 static rtx other_input_reload_insns = 0;
6821 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6822 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6823 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6824 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6825 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6826 static rtx operand_reload_insns = 0;
6827 static rtx other_operand_reload_insns = 0;
6828 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6830 /* Values to be put in spill_reg_store are put here first. */
6831 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6832 static HARD_REG_SET reg_reloaded_died;
6834 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6835 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6836 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6837 adjusted register, and return true. Otherwise, return false. */
6839 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6840 enum reg_class new_class,
6841 enum machine_mode new_mode)
6846 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6848 unsigned regno = REGNO (reg);
6850 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6852 if (GET_MODE (reg) != new_mode)
6854 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6856 if (hard_regno_nregs[regno][new_mode]
6857 > hard_regno_nregs[regno][GET_MODE (reg)])
6859 reg = reload_adjust_reg_for_mode (reg, new_mode);
6867 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6868 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6869 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6870 adjusted register, and return true. Otherwise, return false. */
6872 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6873 enum insn_code icode)
6876 enum reg_class new_class = scratch_reload_class (icode);
6877 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6879 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6880 new_class, new_mode);
6883 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6884 has the number J. OLD contains the value to be used as input. */
6887 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6890 rtx insn = chain->insn;
6892 rtx oldequiv_reg = 0;
6895 enum machine_mode mode;
6898 /* delete_output_reload is only invoked properly if old contains
6899 the original pseudo register. Since this is replaced with a
6900 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6901 find the pseudo in RELOAD_IN_REG. */
6902 if (reload_override_in[j]
6903 && REG_P (rl->in_reg))
6910 else if (REG_P (oldequiv))
6911 oldequiv_reg = oldequiv;
6912 else if (GET_CODE (oldequiv) == SUBREG)
6913 oldequiv_reg = SUBREG_REG (oldequiv);
6915 reloadreg = reload_reg_rtx_for_input[j];
6916 mode = GET_MODE (reloadreg);
6918 /* If we are reloading from a register that was recently stored in
6919 with an output-reload, see if we can prove there was
6920 actually no need to store the old value in it. */
6922 if (optimize && REG_P (oldequiv)
6923 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6924 && spill_reg_store[REGNO (oldequiv)]
6926 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6927 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6929 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6931 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
6934 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6935 oldequiv = SUBREG_REG (oldequiv);
6936 if (GET_MODE (oldequiv) != VOIDmode
6937 && mode != GET_MODE (oldequiv))
6938 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6940 /* Switch to the right place to emit the reload insns. */
6941 switch (rl->when_needed)
6944 where = &other_input_reload_insns;
6946 case RELOAD_FOR_INPUT:
6947 where = &input_reload_insns[rl->opnum];
6949 case RELOAD_FOR_INPUT_ADDRESS:
6950 where = &input_address_reload_insns[rl->opnum];
6952 case RELOAD_FOR_INPADDR_ADDRESS:
6953 where = &inpaddr_address_reload_insns[rl->opnum];
6955 case RELOAD_FOR_OUTPUT_ADDRESS:
6956 where = &output_address_reload_insns[rl->opnum];
6958 case RELOAD_FOR_OUTADDR_ADDRESS:
6959 where = &outaddr_address_reload_insns[rl->opnum];
6961 case RELOAD_FOR_OPERAND_ADDRESS:
6962 where = &operand_reload_insns;
6964 case RELOAD_FOR_OPADDR_ADDR:
6965 where = &other_operand_reload_insns;
6967 case RELOAD_FOR_OTHER_ADDRESS:
6968 where = &other_input_address_reload_insns;
6974 push_to_sequence (*where);
6976 /* Auto-increment addresses must be reloaded in a special way. */
6977 if (rl->out && ! rl->out_reg)
6979 /* We are not going to bother supporting the case where a
6980 incremented register can't be copied directly from
6981 OLDEQUIV since this seems highly unlikely. */
6982 gcc_assert (rl->secondary_in_reload < 0);
6984 if (reload_inherited[j])
6985 oldequiv = reloadreg;
6987 old = XEXP (rl->in_reg, 0);
6989 if (optimize && REG_P (oldequiv)
6990 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6991 && spill_reg_store[REGNO (oldequiv)]
6993 && (dead_or_set_p (insn,
6994 spill_reg_stored_to[REGNO (oldequiv)])
6995 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6997 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6999 /* Prevent normal processing of this reload. */
7001 /* Output a special code sequence for this case. */
7002 new_spill_reg_store[REGNO (reloadreg)]
7003 = inc_for_reload (reloadreg, oldequiv, rl->out,
7007 /* If we are reloading a pseudo-register that was set by the previous
7008 insn, see if we can get rid of that pseudo-register entirely
7009 by redirecting the previous insn into our reload register. */
7011 else if (optimize && REG_P (old)
7012 && REGNO (old) >= FIRST_PSEUDO_REGISTER
7013 && dead_or_set_p (insn, old)
7014 /* This is unsafe if some other reload
7015 uses the same reg first. */
7016 && ! conflicts_with_override (reloadreg)
7017 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
7018 rl->when_needed, old, rl->out, j, 0))
7020 rtx temp = PREV_INSN (insn);
7021 while (temp && (NOTE_P (temp) || DEBUG_INSN_P (temp)))
7022 temp = PREV_INSN (temp);
7024 && NONJUMP_INSN_P (temp)
7025 && GET_CODE (PATTERN (temp)) == SET
7026 && SET_DEST (PATTERN (temp)) == old
7027 /* Make sure we can access insn_operand_constraint. */
7028 && asm_noperands (PATTERN (temp)) < 0
7029 /* This is unsafe if operand occurs more than once in current
7030 insn. Perhaps some occurrences aren't reloaded. */
7031 && count_occurrences (PATTERN (insn), old, 0) == 1)
7033 rtx old = SET_DEST (PATTERN (temp));
7034 /* Store into the reload register instead of the pseudo. */
7035 SET_DEST (PATTERN (temp)) = reloadreg;
7037 /* Verify that resulting insn is valid. */
7038 extract_insn (temp);
7039 if (constrain_operands (1))
7041 /* If the previous insn is an output reload, the source is
7042 a reload register, and its spill_reg_store entry will
7043 contain the previous destination. This is now
7045 if (REG_P (SET_SRC (PATTERN (temp)))
7046 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
7048 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7049 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7052 /* If these are the only uses of the pseudo reg,
7053 pretend for GDB it lives in the reload reg we used. */
7054 if (REG_N_DEATHS (REGNO (old)) == 1
7055 && REG_N_SETS (REGNO (old)) == 1)
7057 reg_renumber[REGNO (old)] = REGNO (reloadreg);
7058 if (ira_conflicts_p)
7059 /* Inform IRA about the change. */
7060 ira_mark_allocation_change (REGNO (old));
7061 alter_reg (REGNO (old), -1, false);
7065 /* Adjust any debug insns between temp and insn. */
7066 while ((temp = NEXT_INSN (temp)) != insn)
7067 if (DEBUG_INSN_P (temp))
7068 replace_rtx (PATTERN (temp), old, reloadreg);
7070 gcc_assert (NOTE_P (temp));
7074 SET_DEST (PATTERN (temp)) = old;
7079 /* We can't do that, so output an insn to load RELOADREG. */
7081 /* If we have a secondary reload, pick up the secondary register
7082 and icode, if any. If OLDEQUIV and OLD are different or
7083 if this is an in-out reload, recompute whether or not we
7084 still need a secondary register and what the icode should
7085 be. If we still need a secondary register and the class or
7086 icode is different, go back to reloading from OLD if using
7087 OLDEQUIV means that we got the wrong type of register. We
7088 cannot have different class or icode due to an in-out reload
7089 because we don't make such reloads when both the input and
7090 output need secondary reload registers. */
7092 if (! special && rl->secondary_in_reload >= 0)
7094 rtx second_reload_reg = 0;
7095 rtx third_reload_reg = 0;
7096 int secondary_reload = rl->secondary_in_reload;
7097 rtx real_oldequiv = oldequiv;
7100 enum insn_code icode;
7101 enum insn_code tertiary_icode = CODE_FOR_nothing;
7103 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7104 and similarly for OLD.
7105 See comments in get_secondary_reload in reload.c. */
7106 /* If it is a pseudo that cannot be replaced with its
7107 equivalent MEM, we must fall back to reload_in, which
7108 will have all the necessary substitutions registered.
7109 Likewise for a pseudo that can't be replaced with its
7110 equivalent constant.
7112 Take extra care for subregs of such pseudos. Note that
7113 we cannot use reg_equiv_mem in this case because it is
7114 not in the right mode. */
7117 if (GET_CODE (tmp) == SUBREG)
7118 tmp = SUBREG_REG (tmp);
7120 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7121 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
7122 || reg_equiv_constant[REGNO (tmp)] != 0))
7124 if (! reg_equiv_mem[REGNO (tmp)]
7125 || num_not_at_initial_offset
7126 || GET_CODE (oldequiv) == SUBREG)
7127 real_oldequiv = rl->in;
7129 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
7133 if (GET_CODE (tmp) == SUBREG)
7134 tmp = SUBREG_REG (tmp);
7136 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7137 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
7138 || reg_equiv_constant[REGNO (tmp)] != 0))
7140 if (! reg_equiv_mem[REGNO (tmp)]
7141 || num_not_at_initial_offset
7142 || GET_CODE (old) == SUBREG)
7145 real_old = reg_equiv_mem[REGNO (tmp)];
7148 second_reload_reg = rld[secondary_reload].reg_rtx;
7149 if (rld[secondary_reload].secondary_in_reload >= 0)
7151 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7153 third_reload_reg = rld[tertiary_reload].reg_rtx;
7154 tertiary_icode = rld[secondary_reload].secondary_in_icode;
7155 /* We'd have to add more code for quartary reloads. */
7156 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7158 icode = rl->secondary_in_icode;
7160 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7161 || (rl->in != 0 && rl->out != 0))
7163 secondary_reload_info sri, sri2;
7164 enum reg_class new_class, new_t_class;
7166 sri.icode = CODE_FOR_nothing;
7167 sri.prev_sri = NULL;
7168 new_class = targetm.secondary_reload (1, real_oldequiv, rl->rclass,
7171 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7172 second_reload_reg = 0;
7173 else if (new_class == NO_REGS)
7175 if (reload_adjust_reg_for_icode (&second_reload_reg,
7177 (enum insn_code) sri.icode))
7179 icode = (enum insn_code) sri.icode;
7180 third_reload_reg = 0;
7185 real_oldequiv = real_old;
7188 else if (sri.icode != CODE_FOR_nothing)
7189 /* We currently lack a way to express this in reloads. */
7193 sri2.icode = CODE_FOR_nothing;
7194 sri2.prev_sri = &sri;
7195 new_t_class = targetm.secondary_reload (1, real_oldequiv,
7196 new_class, mode, &sri);
7197 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7199 if (reload_adjust_reg_for_temp (&second_reload_reg,
7203 third_reload_reg = 0;
7204 tertiary_icode = (enum insn_code) sri2.icode;
7209 real_oldequiv = real_old;
7212 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7214 rtx intermediate = second_reload_reg;
7216 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7218 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7222 second_reload_reg = intermediate;
7223 tertiary_icode = (enum insn_code) sri2.icode;
7228 real_oldequiv = real_old;
7231 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7233 rtx intermediate = second_reload_reg;
7235 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7237 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7240 second_reload_reg = intermediate;
7241 tertiary_icode = (enum insn_code) sri2.icode;
7246 real_oldequiv = real_old;
7251 /* This could be handled more intelligently too. */
7253 real_oldequiv = real_old;
7258 /* If we still need a secondary reload register, check
7259 to see if it is being used as a scratch or intermediate
7260 register and generate code appropriately. If we need
7261 a scratch register, use REAL_OLDEQUIV since the form of
7262 the insn may depend on the actual address if it is
7265 if (second_reload_reg)
7267 if (icode != CODE_FOR_nothing)
7269 /* We'd have to add extra code to handle this case. */
7270 gcc_assert (!third_reload_reg);
7272 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7273 second_reload_reg));
7278 /* See if we need a scratch register to load the
7279 intermediate register (a tertiary reload). */
7280 if (tertiary_icode != CODE_FOR_nothing)
7282 emit_insn ((GEN_FCN (tertiary_icode)
7283 (second_reload_reg, real_oldequiv,
7284 third_reload_reg)));
7286 else if (third_reload_reg)
7288 gen_reload (third_reload_reg, real_oldequiv,
7291 gen_reload (second_reload_reg, third_reload_reg,
7296 gen_reload (second_reload_reg, real_oldequiv,
7300 oldequiv = second_reload_reg;
7305 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7307 rtx real_oldequiv = oldequiv;
7309 if ((REG_P (oldequiv)
7310 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7311 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
7312 || reg_equiv_constant[REGNO (oldequiv)] != 0))
7313 || (GET_CODE (oldequiv) == SUBREG
7314 && REG_P (SUBREG_REG (oldequiv))
7315 && (REGNO (SUBREG_REG (oldequiv))
7316 >= FIRST_PSEUDO_REGISTER)
7317 && ((reg_equiv_memory_loc
7318 [REGNO (SUBREG_REG (oldequiv))] != 0)
7319 || (reg_equiv_constant
7320 [REGNO (SUBREG_REG (oldequiv))] != 0)))
7321 || (CONSTANT_P (oldequiv)
7322 && (PREFERRED_RELOAD_CLASS (oldequiv,
7323 REGNO_REG_CLASS (REGNO (reloadreg)))
7325 real_oldequiv = rl->in;
7326 gen_reload (reloadreg, real_oldequiv, rl->opnum,
7330 if (flag_non_call_exceptions)
7331 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7333 /* End this sequence. */
7334 *where = get_insns ();
7337 /* Update reload_override_in so that delete_address_reloads_1
7338 can see the actual register usage. */
7340 reload_override_in[j] = oldequiv;
7343 /* Generate insns to for the output reload RL, which is for the insn described
7344 by CHAIN and has the number J. */
7346 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7350 rtx insn = chain->insn;
7353 enum machine_mode mode;
7357 if (rl->when_needed == RELOAD_OTHER)
7360 push_to_sequence (output_reload_insns[rl->opnum]);
7362 rl_reg_rtx = reload_reg_rtx_for_output[j];
7363 mode = GET_MODE (rl_reg_rtx);
7365 reloadreg = rl_reg_rtx;
7367 /* If we need two reload regs, set RELOADREG to the intermediate
7368 one, since it will be stored into OLD. We might need a secondary
7369 register only for an input reload, so check again here. */
7371 if (rl->secondary_out_reload >= 0)
7374 int secondary_reload = rl->secondary_out_reload;
7375 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7377 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7378 && reg_equiv_mem[REGNO (old)] != 0)
7379 real_old = reg_equiv_mem[REGNO (old)];
7381 if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7383 rtx second_reloadreg = reloadreg;
7384 reloadreg = rld[secondary_reload].reg_rtx;
7386 /* See if RELOADREG is to be used as a scratch register
7387 or as an intermediate register. */
7388 if (rl->secondary_out_icode != CODE_FOR_nothing)
7390 /* We'd have to add extra code to handle this case. */
7391 gcc_assert (tertiary_reload < 0);
7393 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7394 (real_old, second_reloadreg, reloadreg)));
7399 /* See if we need both a scratch and intermediate reload
7402 enum insn_code tertiary_icode
7403 = rld[secondary_reload].secondary_out_icode;
7405 /* We'd have to add more code for quartary reloads. */
7406 gcc_assert (tertiary_reload < 0
7407 || rld[tertiary_reload].secondary_out_reload < 0);
7409 if (GET_MODE (reloadreg) != mode)
7410 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7412 if (tertiary_icode != CODE_FOR_nothing)
7414 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7417 /* Copy primary reload reg to secondary reload reg.
7418 (Note that these have been swapped above, then
7419 secondary reload reg to OLD using our insn.) */
7421 /* If REAL_OLD is a paradoxical SUBREG, remove it
7422 and try to put the opposite SUBREG on
7424 if (GET_CODE (real_old) == SUBREG
7425 && (GET_MODE_SIZE (GET_MODE (real_old))
7426 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7427 && 0 != (tem = gen_lowpart_common
7428 (GET_MODE (SUBREG_REG (real_old)),
7430 real_old = SUBREG_REG (real_old), reloadreg = tem;
7432 gen_reload (reloadreg, second_reloadreg,
7433 rl->opnum, rl->when_needed);
7434 emit_insn ((GEN_FCN (tertiary_icode)
7435 (real_old, reloadreg, third_reloadreg)));
7441 /* Copy between the reload regs here and then to
7444 gen_reload (reloadreg, second_reloadreg,
7445 rl->opnum, rl->when_needed);
7446 if (tertiary_reload >= 0)
7448 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7450 gen_reload (third_reloadreg, reloadreg,
7451 rl->opnum, rl->when_needed);
7452 reloadreg = third_reloadreg;
7459 /* Output the last reload insn. */
7464 /* Don't output the last reload if OLD is not the dest of
7465 INSN and is in the src and is clobbered by INSN. */
7466 if (! flag_expensive_optimizations
7468 || !(set = single_set (insn))
7469 || rtx_equal_p (old, SET_DEST (set))
7470 || !reg_mentioned_p (old, SET_SRC (set))
7471 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7472 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7473 gen_reload (old, reloadreg, rl->opnum,
7477 /* Look at all insns we emitted, just to be safe. */
7478 for (p = get_insns (); p; p = NEXT_INSN (p))
7481 rtx pat = PATTERN (p);
7483 /* If this output reload doesn't come from a spill reg,
7484 clear any memory of reloaded copies of the pseudo reg.
7485 If this output reload comes from a spill reg,
7486 reg_has_output_reload will make this do nothing. */
7487 note_stores (pat, forget_old_reloads_1, NULL);
7489 if (reg_mentioned_p (rl_reg_rtx, pat))
7491 rtx set = single_set (insn);
7492 if (reload_spill_index[j] < 0
7494 && SET_SRC (set) == rl_reg_rtx)
7496 int src = REGNO (SET_SRC (set));
7498 reload_spill_index[j] = src;
7499 SET_HARD_REG_BIT (reg_is_output_reload, src);
7500 if (find_regno_note (insn, REG_DEAD, src))
7501 SET_HARD_REG_BIT (reg_reloaded_died, src);
7503 if (HARD_REGISTER_P (rl_reg_rtx))
7505 int s = rl->secondary_out_reload;
7506 set = single_set (p);
7507 /* If this reload copies only to the secondary reload
7508 register, the secondary reload does the actual
7510 if (s >= 0 && set == NULL_RTX)
7511 /* We can't tell what function the secondary reload
7512 has and where the actual store to the pseudo is
7513 made; leave new_spill_reg_store alone. */
7516 && SET_SRC (set) == rl_reg_rtx
7517 && SET_DEST (set) == rld[s].reg_rtx)
7519 /* Usually the next instruction will be the
7520 secondary reload insn; if we can confirm
7521 that it is, setting new_spill_reg_store to
7522 that insn will allow an extra optimization. */
7523 rtx s_reg = rld[s].reg_rtx;
7524 rtx next = NEXT_INSN (p);
7525 rld[s].out = rl->out;
7526 rld[s].out_reg = rl->out_reg;
7527 set = single_set (next);
7528 if (set && SET_SRC (set) == s_reg
7529 && ! new_spill_reg_store[REGNO (s_reg)])
7531 SET_HARD_REG_BIT (reg_is_output_reload,
7533 new_spill_reg_store[REGNO (s_reg)] = next;
7537 new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7542 if (rl->when_needed == RELOAD_OTHER)
7544 emit_insn (other_output_reload_insns[rl->opnum]);
7545 other_output_reload_insns[rl->opnum] = get_insns ();
7548 output_reload_insns[rl->opnum] = get_insns ();
7550 if (flag_non_call_exceptions)
7551 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7556 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7557 and has the number J. */
7559 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7561 rtx insn = chain->insn;
7562 rtx old = (rl->in && MEM_P (rl->in)
7563 ? rl->in_reg : rl->in);
7564 rtx reg_rtx = rl->reg_rtx;
7568 enum machine_mode mode;
7570 /* Determine the mode to reload in.
7571 This is very tricky because we have three to choose from.
7572 There is the mode the insn operand wants (rl->inmode).
7573 There is the mode of the reload register RELOADREG.
7574 There is the intrinsic mode of the operand, which we could find
7575 by stripping some SUBREGs.
7576 It turns out that RELOADREG's mode is irrelevant:
7577 we can change that arbitrarily.
7579 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7580 then the reload reg may not support QImode moves, so use SImode.
7581 If foo is in memory due to spilling a pseudo reg, this is safe,
7582 because the QImode value is in the least significant part of a
7583 slot big enough for a SImode. If foo is some other sort of
7584 memory reference, then it is impossible to reload this case,
7585 so previous passes had better make sure this never happens.
7587 Then consider a one-word union which has SImode and one of its
7588 members is a float, being fetched as (SUBREG:SF union:SI).
7589 We must fetch that as SFmode because we could be loading into
7590 a float-only register. In this case OLD's mode is correct.
7592 Consider an immediate integer: it has VOIDmode. Here we need
7593 to get a mode from something else.
7595 In some cases, there is a fourth mode, the operand's
7596 containing mode. If the insn specifies a containing mode for
7597 this operand, it overrides all others.
7599 I am not sure whether the algorithm here is always right,
7600 but it does the right things in those cases. */
7602 mode = GET_MODE (old);
7603 if (mode == VOIDmode)
7606 /* We cannot use gen_lowpart_common since it can do the wrong thing
7607 when REG_RTX has a multi-word mode. Note that REG_RTX must
7608 always be a REG here. */
7609 if (GET_MODE (reg_rtx) != mode)
7610 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7612 reload_reg_rtx_for_input[j] = reg_rtx;
7615 /* AUTO_INC reloads need to be handled even if inherited. We got an
7616 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7617 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7618 && ! rtx_equal_p (reg_rtx, old)
7620 emit_input_reload_insns (chain, rld + j, old, j);
7622 /* When inheriting a wider reload, we have a MEM in rl->in,
7623 e.g. inheriting a SImode output reload for
7624 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7625 if (optimize && reload_inherited[j] && rl->in
7627 && MEM_P (rl->in_reg)
7628 && reload_spill_index[j] >= 0
7629 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7630 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7632 /* If we are reloading a register that was recently stored in with an
7633 output-reload, see if we can prove there was
7634 actually no need to store the old value in it. */
7637 && (reload_inherited[j] || reload_override_in[j])
7640 && spill_reg_store[REGNO (reg_rtx)] != 0
7642 /* There doesn't seem to be any reason to restrict this to pseudos
7643 and doing so loses in the case where we are copying from a
7644 register of the wrong class. */
7645 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7647 /* The insn might have already some references to stackslots
7648 replaced by MEMs, while reload_out_reg still names the
7650 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7651 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7652 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7655 /* Do output reloading for reload RL, which is for the insn described by
7656 CHAIN and has the number J.
7657 ??? At some point we need to support handling output reloads of
7658 JUMP_INSNs or insns that set cc0. */
7660 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7663 rtx insn = chain->insn;
7664 /* If this is an output reload that stores something that is
7665 not loaded in this same reload, see if we can eliminate a previous
7667 rtx pseudo = rl->out_reg;
7668 rtx reg_rtx = rl->reg_rtx;
7670 if (rl->out && reg_rtx)
7672 enum machine_mode mode;
7674 /* Determine the mode to reload in.
7675 See comments above (for input reloading). */
7676 mode = GET_MODE (rl->out);
7677 if (mode == VOIDmode)
7679 /* VOIDmode should never happen for an output. */
7680 if (asm_noperands (PATTERN (insn)) < 0)
7681 /* It's the compiler's fault. */
7682 fatal_insn ("VOIDmode on an output", insn);
7683 error_for_asm (insn, "output operand is constant in %<asm%>");
7684 /* Prevent crash--use something we know is valid. */
7686 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7688 if (GET_MODE (reg_rtx) != mode)
7689 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7691 reload_reg_rtx_for_output[j] = reg_rtx;
7696 && ! rtx_equal_p (rl->in_reg, pseudo)
7697 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7698 && reg_last_reload_reg[REGNO (pseudo)])
7700 int pseudo_no = REGNO (pseudo);
7701 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7703 /* We don't need to test full validity of last_regno for
7704 inherit here; we only want to know if the store actually
7705 matches the pseudo. */
7706 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7707 && reg_reloaded_contents[last_regno] == pseudo_no
7708 && spill_reg_store[last_regno]
7709 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7710 delete_output_reload (insn, j, last_regno, reg_rtx);
7716 || rtx_equal_p (old, reg_rtx))
7719 /* An output operand that dies right away does need a reload,
7720 but need not be copied from it. Show the new location in the
7722 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7723 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7725 XEXP (note, 0) = reg_rtx;
7728 /* Likewise for a SUBREG of an operand that dies. */
7729 else if (GET_CODE (old) == SUBREG
7730 && REG_P (SUBREG_REG (old))
7731 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7734 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
7737 else if (GET_CODE (old) == SCRATCH)
7738 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7739 but we don't want to make an output reload. */
7742 /* If is a JUMP_INSN, we can't support output reloads yet. */
7743 gcc_assert (NONJUMP_INSN_P (insn));
7745 emit_output_reload_insns (chain, rld + j, j);
7748 /* A reload copies values of MODE from register SRC to register DEST.
7749 Return true if it can be treated for inheritance purposes like a
7750 group of reloads, each one reloading a single hard register. The
7751 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7752 occupy the same number of hard registers. */
7755 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
7756 int src ATTRIBUTE_UNUSED,
7757 enum machine_mode mode ATTRIBUTE_UNUSED)
7759 #ifdef CANNOT_CHANGE_MODE_CLASS
7760 return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
7761 && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
7767 /* Output insns to reload values in and out of the chosen reload regs. */
7770 emit_reload_insns (struct insn_chain *chain)
7772 rtx insn = chain->insn;
7776 CLEAR_HARD_REG_SET (reg_reloaded_died);
7778 for (j = 0; j < reload_n_operands; j++)
7779 input_reload_insns[j] = input_address_reload_insns[j]
7780 = inpaddr_address_reload_insns[j]
7781 = output_reload_insns[j] = output_address_reload_insns[j]
7782 = outaddr_address_reload_insns[j]
7783 = other_output_reload_insns[j] = 0;
7784 other_input_address_reload_insns = 0;
7785 other_input_reload_insns = 0;
7786 operand_reload_insns = 0;
7787 other_operand_reload_insns = 0;
7789 /* Dump reloads into the dump file. */
7792 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7793 debug_reload_to_stream (dump_file);
7796 /* Now output the instructions to copy the data into and out of the
7797 reload registers. Do these in the order that the reloads were reported,
7798 since reloads of base and index registers precede reloads of operands
7799 and the operands may need the base and index registers reloaded. */
7801 for (j = 0; j < n_reloads; j++)
7803 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
7807 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
7808 new_spill_reg_store[i] = 0;
7811 do_input_reload (chain, rld + j, j);
7812 do_output_reload (chain, rld + j, j);
7815 /* Now write all the insns we made for reloads in the order expected by
7816 the allocation functions. Prior to the insn being reloaded, we write
7817 the following reloads:
7819 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7821 RELOAD_OTHER reloads.
7823 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7824 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7825 RELOAD_FOR_INPUT reload for the operand.
7827 RELOAD_FOR_OPADDR_ADDRS reloads.
7829 RELOAD_FOR_OPERAND_ADDRESS reloads.
7831 After the insn being reloaded, we write the following:
7833 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7834 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7835 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7836 reloads for the operand. The RELOAD_OTHER output reloads are
7837 output in descending order by reload number. */
7839 emit_insn_before (other_input_address_reload_insns, insn);
7840 emit_insn_before (other_input_reload_insns, insn);
7842 for (j = 0; j < reload_n_operands; j++)
7844 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7845 emit_insn_before (input_address_reload_insns[j], insn);
7846 emit_insn_before (input_reload_insns[j], insn);
7849 emit_insn_before (other_operand_reload_insns, insn);
7850 emit_insn_before (operand_reload_insns, insn);
7852 for (j = 0; j < reload_n_operands; j++)
7854 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7855 x = emit_insn_after (output_address_reload_insns[j], x);
7856 x = emit_insn_after (output_reload_insns[j], x);
7857 emit_insn_after (other_output_reload_insns[j], x);
7860 /* For all the spill regs newly reloaded in this instruction,
7861 record what they were reloaded from, so subsequent instructions
7862 can inherit the reloads.
7864 Update spill_reg_store for the reloads of this insn.
7865 Copy the elements that were updated in the loop above. */
7867 for (j = 0; j < n_reloads; j++)
7869 int r = reload_order[j];
7870 int i = reload_spill_index[r];
7872 /* If this is a non-inherited input reload from a pseudo, we must
7873 clear any memory of a previous store to the same pseudo. Only do
7874 something if there will not be an output reload for the pseudo
7876 if (rld[r].in_reg != 0
7877 && ! (reload_inherited[r] || reload_override_in[r]))
7879 rtx reg = rld[r].in_reg;
7881 if (GET_CODE (reg) == SUBREG)
7882 reg = SUBREG_REG (reg);
7885 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7886 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
7888 int nregno = REGNO (reg);
7890 if (reg_last_reload_reg[nregno])
7892 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7894 if (reg_reloaded_contents[last_regno] == nregno)
7895 spill_reg_store[last_regno] = 0;
7900 /* I is nonneg if this reload used a register.
7901 If rld[r].reg_rtx is 0, this is an optional reload
7902 that we opted to ignore. */
7904 if (i >= 0 && rld[r].reg_rtx != 0)
7906 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7909 /* For a multi register reload, we need to check if all or part
7910 of the value lives to the end. */
7911 for (k = 0; k < nr; k++)
7912 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7913 rld[r].when_needed))
7914 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7916 /* Maybe the spill reg contains a copy of reload_out. */
7918 && (REG_P (rld[r].out)
7922 || REG_P (rld[r].out_reg)))
7925 enum machine_mode mode;
7928 reg = reload_reg_rtx_for_output[r];
7929 mode = GET_MODE (reg);
7930 regno = REGNO (reg);
7931 nregs = hard_regno_nregs[regno][mode];
7932 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
7933 rld[r].when_needed))
7935 rtx out = (REG_P (rld[r].out)
7939 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7940 int out_regno = REGNO (out);
7941 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
7942 : hard_regno_nregs[out_regno][mode]);
7945 spill_reg_store[regno] = new_spill_reg_store[regno];
7946 spill_reg_stored_to[regno] = out;
7947 reg_last_reload_reg[out_regno] = reg;
7949 piecemeal = (HARD_REGISTER_NUM_P (out_regno)
7950 && nregs == out_nregs
7951 && inherit_piecemeal_p (out_regno, regno, mode));
7953 /* If OUT_REGNO is a hard register, it may occupy more than
7954 one register. If it does, say what is in the
7955 rest of the registers assuming that both registers
7956 agree on how many words the object takes. If not,
7957 invalidate the subsequent registers. */
7959 if (HARD_REGISTER_NUM_P (out_regno))
7960 for (k = 1; k < out_nregs; k++)
7961 reg_last_reload_reg[out_regno + k]
7962 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
7964 /* Now do the inverse operation. */
7965 for (k = 0; k < nregs; k++)
7967 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
7968 reg_reloaded_contents[regno + k]
7969 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
7972 reg_reloaded_insn[regno + k] = insn;
7973 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
7974 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
7975 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7978 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7983 /* Maybe the spill reg contains a copy of reload_in. Only do
7984 something if there will not be an output reload for
7985 the register being reloaded. */
7986 else if (rld[r].out_reg == 0
7988 && ((REG_P (rld[r].in)
7989 && !HARD_REGISTER_P (rld[r].in)
7990 && !REGNO_REG_SET_P (®_has_output_reload,
7992 || (REG_P (rld[r].in_reg)
7993 && !REGNO_REG_SET_P (®_has_output_reload,
7994 REGNO (rld[r].in_reg))))
7995 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
7998 enum machine_mode mode;
8001 reg = reload_reg_rtx_for_input[r];
8002 mode = GET_MODE (reg);
8003 regno = REGNO (reg);
8004 nregs = hard_regno_nregs[regno][mode];
8005 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
8006 rld[r].when_needed))
8013 if (REG_P (rld[r].in)
8014 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
8016 else if (REG_P (rld[r].in_reg))
8019 in = XEXP (rld[r].in_reg, 0);
8020 in_regno = REGNO (in);
8022 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
8023 : hard_regno_nregs[in_regno][mode]);
8025 reg_last_reload_reg[in_regno] = reg;
8027 piecemeal = (HARD_REGISTER_NUM_P (in_regno)
8028 && nregs == in_nregs
8029 && inherit_piecemeal_p (regno, in_regno, mode));
8031 if (HARD_REGISTER_NUM_P (in_regno))
8032 for (k = 1; k < in_nregs; k++)
8033 reg_last_reload_reg[in_regno + k]
8034 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8036 /* Unless we inherited this reload, show we haven't
8037 recently done a store.
8038 Previous stores of inherited auto_inc expressions
8039 also have to be discarded. */
8040 if (! reload_inherited[r]
8041 || (rld[r].out && ! rld[r].out_reg))
8042 spill_reg_store[regno] = 0;
8044 for (k = 0; k < nregs; k++)
8046 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8047 reg_reloaded_contents[regno + k]
8048 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
8051 reg_reloaded_insn[regno + k] = insn;
8052 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8053 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8054 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8057 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8064 /* The following if-statement was #if 0'd in 1.34 (or before...).
8065 It's reenabled in 1.35 because supposedly nothing else
8066 deals with this problem. */
8068 /* If a register gets output-reloaded from a non-spill register,
8069 that invalidates any previous reloaded copy of it.
8070 But forget_old_reloads_1 won't get to see it, because
8071 it thinks only about the original insn. So invalidate it here.
8072 Also do the same thing for RELOAD_OTHER constraints where the
8073 output is discarded. */
8075 && ((rld[r].out != 0
8076 && (REG_P (rld[r].out)
8077 || (MEM_P (rld[r].out)
8078 && REG_P (rld[r].out_reg))))
8079 || (rld[r].out == 0 && rld[r].out_reg
8080 && REG_P (rld[r].out_reg))))
8082 rtx out = ((rld[r].out && REG_P (rld[r].out))
8083 ? rld[r].out : rld[r].out_reg);
8084 int out_regno = REGNO (out);
8085 enum machine_mode mode = GET_MODE (out);
8087 /* REG_RTX is now set or clobbered by the main instruction.
8088 As the comment above explains, forget_old_reloads_1 only
8089 sees the original instruction, and there is no guarantee
8090 that the original instruction also clobbered REG_RTX.
8091 For example, if find_reloads sees that the input side of
8092 a matched operand pair dies in this instruction, it may
8093 use the input register as the reload register.
8095 Calling forget_old_reloads_1 is a waste of effort if
8096 REG_RTX is also the output register.
8098 If we know that REG_RTX holds the value of a pseudo
8099 register, the code after the call will record that fact. */
8100 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8101 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8103 if (!HARD_REGISTER_NUM_P (out_regno))
8105 rtx src_reg, store_insn = NULL_RTX;
8107 reg_last_reload_reg[out_regno] = 0;
8109 /* If we can find a hard register that is stored, record
8110 the storing insn so that we may delete this insn with
8111 delete_output_reload. */
8112 src_reg = reload_reg_rtx_for_output[r];
8114 /* If this is an optional reload, try to find the source reg
8115 from an input reload. */
8118 rtx set = single_set (insn);
8119 if (set && SET_DEST (set) == rld[r].out)
8123 src_reg = SET_SRC (set);
8125 for (k = 0; k < n_reloads; k++)
8127 if (rld[k].in == src_reg)
8129 src_reg = reload_reg_rtx_for_input[k];
8136 store_insn = new_spill_reg_store[REGNO (src_reg)];
8137 if (src_reg && REG_P (src_reg)
8138 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8140 int src_regno, src_nregs, k;
8143 gcc_assert (GET_MODE (src_reg) == mode);
8144 src_regno = REGNO (src_reg);
8145 src_nregs = hard_regno_nregs[src_regno][mode];
8146 /* The place where to find a death note varies with
8147 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8148 necessarily checked exactly in the code that moves
8149 notes, so just check both locations. */
8150 note = find_regno_note (insn, REG_DEAD, src_regno);
8151 if (! note && store_insn)
8152 note = find_regno_note (store_insn, REG_DEAD, src_regno);
8153 for (k = 0; k < src_nregs; k++)
8155 spill_reg_store[src_regno + k] = store_insn;
8156 spill_reg_stored_to[src_regno + k] = out;
8157 reg_reloaded_contents[src_regno + k] = out_regno;
8158 reg_reloaded_insn[src_regno + k] = store_insn;
8159 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8160 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8161 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
8163 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8166 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8168 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8170 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8172 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8174 reg_last_reload_reg[out_regno] = src_reg;
8175 /* We have to set reg_has_output_reload here, or else
8176 forget_old_reloads_1 will clear reg_last_reload_reg
8178 SET_REGNO_REG_SET (®_has_output_reload,
8184 int k, out_nregs = hard_regno_nregs[out_regno][mode];
8186 for (k = 0; k < out_nregs; k++)
8187 reg_last_reload_reg[out_regno + k] = 0;
8191 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
8194 /* Go through the motions to emit INSN and test if it is strictly valid.
8195 Return the emitted insn if valid, else return NULL. */
8198 emit_insn_if_valid_for_reload (rtx insn)
8200 rtx last = get_last_insn ();
8203 insn = emit_insn (insn);
8204 code = recog_memoized (insn);
8208 extract_insn (insn);
8209 /* We want constrain operands to treat this insn strictly in its
8210 validity determination, i.e., the way it would after reload has
8212 if (constrain_operands (1))
8216 delete_insns_since (last);
8220 /* Emit code to perform a reload from IN (which may be a reload register) to
8221 OUT (which may also be a reload register). IN or OUT is from operand
8222 OPNUM with reload type TYPE.
8224 Returns first insn emitted. */
8227 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8229 rtx last = get_last_insn ();
8232 /* If IN is a paradoxical SUBREG, remove it and try to put the
8233 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8234 if (GET_CODE (in) == SUBREG
8235 && (GET_MODE_SIZE (GET_MODE (in))
8236 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
8237 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
8238 in = SUBREG_REG (in), out = tem;
8239 else if (GET_CODE (out) == SUBREG
8240 && (GET_MODE_SIZE (GET_MODE (out))
8241 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
8242 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
8243 out = SUBREG_REG (out), in = tem;
8245 /* How to do this reload can get quite tricky. Normally, we are being
8246 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8247 register that didn't get a hard register. In that case we can just
8248 call emit_move_insn.
8250 We can also be asked to reload a PLUS that adds a register or a MEM to
8251 another register, constant or MEM. This can occur during frame pointer
8252 elimination and while reloading addresses. This case is handled by
8253 trying to emit a single insn to perform the add. If it is not valid,
8254 we use a two insn sequence.
8256 Or we can be asked to reload an unary operand that was a fragment of
8257 an addressing mode, into a register. If it isn't recognized as-is,
8258 we try making the unop operand and the reload-register the same:
8259 (set reg:X (unop:X expr:Y))
8260 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8262 Finally, we could be called to handle an 'o' constraint by putting
8263 an address into a register. In that case, we first try to do this
8264 with a named pattern of "reload_load_address". If no such pattern
8265 exists, we just emit a SET insn and hope for the best (it will normally
8266 be valid on machines that use 'o').
8268 This entire process is made complex because reload will never
8269 process the insns we generate here and so we must ensure that
8270 they will fit their constraints and also by the fact that parts of
8271 IN might be being reloaded separately and replaced with spill registers.
8272 Because of this, we are, in some sense, just guessing the right approach
8273 here. The one listed above seems to work.
8275 ??? At some point, this whole thing needs to be rethought. */
8277 if (GET_CODE (in) == PLUS
8278 && (REG_P (XEXP (in, 0))
8279 || GET_CODE (XEXP (in, 0)) == SUBREG
8280 || MEM_P (XEXP (in, 0)))
8281 && (REG_P (XEXP (in, 1))
8282 || GET_CODE (XEXP (in, 1)) == SUBREG
8283 || CONSTANT_P (XEXP (in, 1))
8284 || MEM_P (XEXP (in, 1))))
8286 /* We need to compute the sum of a register or a MEM and another
8287 register, constant, or MEM, and put it into the reload
8288 register. The best possible way of doing this is if the machine
8289 has a three-operand ADD insn that accepts the required operands.
8291 The simplest approach is to try to generate such an insn and see if it
8292 is recognized and matches its constraints. If so, it can be used.
8294 It might be better not to actually emit the insn unless it is valid,
8295 but we need to pass the insn as an operand to `recog' and
8296 `extract_insn' and it is simpler to emit and then delete the insn if
8297 not valid than to dummy things up. */
8299 rtx op0, op1, tem, insn;
8302 op0 = find_replacement (&XEXP (in, 0));
8303 op1 = find_replacement (&XEXP (in, 1));
8305 /* Since constraint checking is strict, commutativity won't be
8306 checked, so we need to do that here to avoid spurious failure
8307 if the add instruction is two-address and the second operand
8308 of the add is the same as the reload reg, which is frequently
8309 the case. If the insn would be A = B + A, rearrange it so
8310 it will be A = A + B as constrain_operands expects. */
8312 if (REG_P (XEXP (in, 1))
8313 && REGNO (out) == REGNO (XEXP (in, 1)))
8314 tem = op0, op0 = op1, op1 = tem;
8316 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8317 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8319 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8323 /* If that failed, we must use a conservative two-insn sequence.
8325 Use a move to copy one operand into the reload register. Prefer
8326 to reload a constant, MEM or pseudo since the move patterns can
8327 handle an arbitrary operand. If OP1 is not a constant, MEM or
8328 pseudo and OP1 is not a valid operand for an add instruction, then
8331 After reloading one of the operands into the reload register, add
8332 the reload register to the output register.
8334 If there is another way to do this for a specific machine, a
8335 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8338 code = (int) optab_handler (add_optab, GET_MODE (out))->insn_code;
8340 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8342 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8343 || (code != CODE_FOR_nothing
8344 && ! ((*insn_data[code].operand[2].predicate)
8345 (op1, insn_data[code].operand[2].mode))))
8346 tem = op0, op0 = op1, op1 = tem;
8348 gen_reload (out, op0, opnum, type);
8350 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8351 This fixes a problem on the 32K where the stack pointer cannot
8352 be used as an operand of an add insn. */
8354 if (rtx_equal_p (op0, op1))
8357 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8360 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8361 set_unique_reg_note (insn, REG_EQUIV, in);
8365 /* If that failed, copy the address register to the reload register.
8366 Then add the constant to the reload register. */
8368 gcc_assert (!reg_overlap_mentioned_p (out, op0));
8369 gen_reload (out, op1, opnum, type);
8370 insn = emit_insn (gen_add2_insn (out, op0));
8371 set_unique_reg_note (insn, REG_EQUIV, in);
8374 #ifdef SECONDARY_MEMORY_NEEDED
8375 /* If we need a memory location to do the move, do it that way. */
8376 else if ((REG_P (in)
8377 || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))))
8378 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
8380 || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out))))
8381 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
8382 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
8383 REGNO_REG_CLASS (reg_or_subregno (out)),
8386 /* Get the memory to use and rewrite both registers to its mode. */
8387 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8389 if (GET_MODE (loc) != GET_MODE (out))
8390 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
8392 if (GET_MODE (loc) != GET_MODE (in))
8393 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
8395 gen_reload (loc, in, opnum, type);
8396 gen_reload (out, loc, opnum, type);
8399 else if (REG_P (out) && UNARY_P (in))
8406 op1 = find_replacement (&XEXP (in, 0));
8407 if (op1 != XEXP (in, 0))
8408 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8410 /* First, try a plain SET. */
8411 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8415 /* If that failed, move the inner operand to the reload
8416 register, and try the same unop with the inner expression
8417 replaced with the reload register. */
8419 if (GET_MODE (op1) != GET_MODE (out))
8420 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8424 gen_reload (out_moded, op1, opnum, type);
8427 = gen_rtx_SET (VOIDmode, out,
8428 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8430 insn = emit_insn_if_valid_for_reload (insn);
8433 set_unique_reg_note (insn, REG_EQUIV, in);
8437 fatal_insn ("Failure trying to reload:", set);
8439 /* If IN is a simple operand, use gen_move_insn. */
8440 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8442 tem = emit_insn (gen_move_insn (out, in));
8443 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8444 mark_jump_label (in, tem, 0);
8447 #ifdef HAVE_reload_load_address
8448 else if (HAVE_reload_load_address)
8449 emit_insn (gen_reload_load_address (out, in));
8452 /* Otherwise, just write (set OUT IN) and hope for the best. */
8454 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8456 /* Return the first insn emitted.
8457 We can not just return get_last_insn, because there may have
8458 been multiple instructions emitted. Also note that gen_move_insn may
8459 emit more than one insn itself, so we can not assume that there is one
8460 insn emitted per emit_insn_before call. */
8462 return last ? NEXT_INSN (last) : get_insns ();
8465 /* Delete a previously made output-reload whose result we now believe
8466 is not needed. First we double-check.
8468 INSN is the insn now being processed.
8469 LAST_RELOAD_REG is the hard register number for which we want to delete
8470 the last output reload.
8471 J is the reload-number that originally used REG. The caller has made
8472 certain that reload J doesn't use REG any longer for input.
8473 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8476 delete_output_reload (rtx insn, int j, int last_reload_reg, rtx new_reload_reg)
8478 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8479 rtx reg = spill_reg_stored_to[last_reload_reg];
8482 int n_inherited = 0;
8486 /* It is possible that this reload has been only used to set another reload
8487 we eliminated earlier and thus deleted this instruction too. */
8488 if (INSN_DELETED_P (output_reload_insn))
8491 /* Get the raw pseudo-register referred to. */
8493 while (GET_CODE (reg) == SUBREG)
8494 reg = SUBREG_REG (reg);
8495 substed = reg_equiv_memory_loc[REGNO (reg)];
8497 /* This is unsafe if the operand occurs more often in the current
8498 insn than it is inherited. */
8499 for (k = n_reloads - 1; k >= 0; k--)
8501 rtx reg2 = rld[k].in;
8504 if (MEM_P (reg2) || reload_override_in[k])
8505 reg2 = rld[k].in_reg;
8507 if (rld[k].out && ! rld[k].out_reg)
8508 reg2 = XEXP (rld[k].in_reg, 0);
8510 while (GET_CODE (reg2) == SUBREG)
8511 reg2 = SUBREG_REG (reg2);
8512 if (rtx_equal_p (reg2, reg))
8514 if (reload_inherited[k] || reload_override_in[k] || k == j)
8520 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8521 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8522 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8525 n_occurrences += count_occurrences (PATTERN (insn),
8526 eliminate_regs (substed, VOIDmode,
8528 for (i1 = reg_equiv_alt_mem_list[REGNO (reg)]; i1; i1 = XEXP (i1, 1))
8530 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8531 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8533 if (n_occurrences > n_inherited)
8536 /* If the pseudo-reg we are reloading is no longer referenced
8537 anywhere between the store into it and here,
8538 and we're within the same basic block, then the value can only
8539 pass through the reload reg and end up here.
8540 Otherwise, give up--return. */
8541 for (i1 = NEXT_INSN (output_reload_insn);
8542 i1 != insn; i1 = NEXT_INSN (i1))
8544 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8546 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8547 && reg_mentioned_p (reg, PATTERN (i1)))
8549 /* If this is USE in front of INSN, we only have to check that
8550 there are no more references than accounted for by inheritance. */
8551 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8553 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8554 i1 = NEXT_INSN (i1);
8556 if (n_occurrences <= n_inherited && i1 == insn)
8562 /* We will be deleting the insn. Remove the spill reg information. */
8563 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8565 spill_reg_store[last_reload_reg + k] = 0;
8566 spill_reg_stored_to[last_reload_reg + k] = 0;
8569 /* The caller has already checked that REG dies or is set in INSN.
8570 It has also checked that we are optimizing, and thus some
8571 inaccuracies in the debugging information are acceptable.
8572 So we could just delete output_reload_insn. But in some cases
8573 we can improve the debugging information without sacrificing
8574 optimization - maybe even improving the code: See if the pseudo
8575 reg has been completely replaced with reload regs. If so, delete
8576 the store insn and forget we had a stack slot for the pseudo. */
8577 if (rld[j].out != rld[j].in
8578 && REG_N_DEATHS (REGNO (reg)) == 1
8579 && REG_N_SETS (REGNO (reg)) == 1
8580 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8581 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8585 /* We know that it was used only between here and the beginning of
8586 the current basic block. (We also know that the last use before
8587 INSN was the output reload we are thinking of deleting, but never
8588 mind that.) Search that range; see if any ref remains. */
8589 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8591 rtx set = single_set (i2);
8593 /* Uses which just store in the pseudo don't count,
8594 since if they are the only uses, they are dead. */
8595 if (set != 0 && SET_DEST (set) == reg)
8600 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8601 && reg_mentioned_p (reg, PATTERN (i2)))
8603 /* Some other ref remains; just delete the output reload we
8605 delete_address_reloads (output_reload_insn, insn);
8606 delete_insn (output_reload_insn);
8611 /* Delete the now-dead stores into this pseudo. Note that this
8612 loop also takes care of deleting output_reload_insn. */
8613 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8615 rtx set = single_set (i2);
8617 if (set != 0 && SET_DEST (set) == reg)
8619 delete_address_reloads (i2, insn);
8627 /* For the debugging info, say the pseudo lives in this reload reg. */
8628 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8629 if (ira_conflicts_p)
8630 /* Inform IRA about the change. */
8631 ira_mark_allocation_change (REGNO (reg));
8632 alter_reg (REGNO (reg), -1, false);
8636 delete_address_reloads (output_reload_insn, insn);
8637 delete_insn (output_reload_insn);
8641 /* We are going to delete DEAD_INSN. Recursively delete loads of
8642 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8643 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8645 delete_address_reloads (rtx dead_insn, rtx current_insn)
8647 rtx set = single_set (dead_insn);
8648 rtx set2, dst, prev, next;
8651 rtx dst = SET_DEST (set);
8653 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8655 /* If we deleted the store from a reloaded post_{in,de}c expression,
8656 we can delete the matching adds. */
8657 prev = PREV_INSN (dead_insn);
8658 next = NEXT_INSN (dead_insn);
8659 if (! prev || ! next)
8661 set = single_set (next);
8662 set2 = single_set (prev);
8664 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8665 || !CONST_INT_P (XEXP (SET_SRC (set), 1))
8666 || !CONST_INT_P (XEXP (SET_SRC (set2), 1)))
8668 dst = SET_DEST (set);
8669 if (! rtx_equal_p (dst, SET_DEST (set2))
8670 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8671 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8672 || (INTVAL (XEXP (SET_SRC (set), 1))
8673 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8675 delete_related_insns (prev);
8676 delete_related_insns (next);
8679 /* Subfunction of delete_address_reloads: process registers found in X. */
8681 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8683 rtx prev, set, dst, i2;
8685 enum rtx_code code = GET_CODE (x);
8689 const char *fmt = GET_RTX_FORMAT (code);
8690 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8693 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8694 else if (fmt[i] == 'E')
8696 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8697 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8704 if (spill_reg_order[REGNO (x)] < 0)
8707 /* Scan backwards for the insn that sets x. This might be a way back due
8709 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8711 code = GET_CODE (prev);
8712 if (code == CODE_LABEL || code == JUMP_INSN)
8716 if (reg_set_p (x, PATTERN (prev)))
8718 if (reg_referenced_p (x, PATTERN (prev)))
8721 if (! prev || INSN_UID (prev) < reload_first_uid)
8723 /* Check that PREV only sets the reload register. */
8724 set = single_set (prev);
8727 dst = SET_DEST (set);
8729 || ! rtx_equal_p (dst, x))
8731 if (! reg_set_p (dst, PATTERN (dead_insn)))
8733 /* Check if DST was used in a later insn -
8734 it might have been inherited. */
8735 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8741 if (reg_referenced_p (dst, PATTERN (i2)))
8743 /* If there is a reference to the register in the current insn,
8744 it might be loaded in a non-inherited reload. If no other
8745 reload uses it, that means the register is set before
8747 if (i2 == current_insn)
8749 for (j = n_reloads - 1; j >= 0; j--)
8750 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8751 || reload_override_in[j] == dst)
8753 for (j = n_reloads - 1; j >= 0; j--)
8754 if (rld[j].in && rld[j].reg_rtx == dst)
8763 /* If DST is still live at CURRENT_INSN, check if it is used for
8764 any reload. Note that even if CURRENT_INSN sets DST, we still
8765 have to check the reloads. */
8766 if (i2 == current_insn)
8768 for (j = n_reloads - 1; j >= 0; j--)
8769 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8770 || reload_override_in[j] == dst)
8772 /* ??? We can't finish the loop here, because dst might be
8773 allocated to a pseudo in this block if no reload in this
8774 block needs any of the classes containing DST - see
8775 spill_hard_reg. There is no easy way to tell this, so we
8776 have to scan till the end of the basic block. */
8778 if (reg_set_p (dst, PATTERN (i2)))
8782 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8783 reg_reloaded_contents[REGNO (dst)] = -1;
8787 /* Output reload-insns to reload VALUE into RELOADREG.
8788 VALUE is an autoincrement or autodecrement RTX whose operand
8789 is a register or memory location;
8790 so reloading involves incrementing that location.
8791 IN is either identical to VALUE, or some cheaper place to reload from.
8793 INC_AMOUNT is the number to increment or decrement by (always positive).
8794 This cannot be deduced from VALUE.
8796 Return the instruction that stores into RELOADREG. */
8799 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8801 /* REG or MEM to be copied and incremented. */
8802 rtx incloc = find_replacement (&XEXP (value, 0));
8803 /* Nonzero if increment after copying. */
8804 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8805 || GET_CODE (value) == POST_MODIFY);
8811 rtx real_in = in == value ? incloc : in;
8813 /* No hard register is equivalent to this register after
8814 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8815 we could inc/dec that register as well (maybe even using it for
8816 the source), but I'm not sure it's worth worrying about. */
8818 reg_last_reload_reg[REGNO (incloc)] = 0;
8820 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8822 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8823 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
8827 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8828 inc_amount = -inc_amount;
8830 inc = GEN_INT (inc_amount);
8833 /* If this is post-increment, first copy the location to the reload reg. */
8834 if (post && real_in != reloadreg)
8835 emit_insn (gen_move_insn (reloadreg, real_in));
8839 /* See if we can directly increment INCLOC. Use a method similar to
8840 that in gen_reload. */
8842 last = get_last_insn ();
8843 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8844 gen_rtx_PLUS (GET_MODE (incloc),
8847 code = recog_memoized (add_insn);
8850 extract_insn (add_insn);
8851 if (constrain_operands (1))
8853 /* If this is a pre-increment and we have incremented the value
8854 where it lives, copy the incremented value to RELOADREG to
8855 be used as an address. */
8858 emit_insn (gen_move_insn (reloadreg, incloc));
8863 delete_insns_since (last);
8866 /* If couldn't do the increment directly, must increment in RELOADREG.
8867 The way we do this depends on whether this is pre- or post-increment.
8868 For pre-increment, copy INCLOC to the reload register, increment it
8869 there, then save back. */
8873 if (in != reloadreg)
8874 emit_insn (gen_move_insn (reloadreg, real_in));
8875 emit_insn (gen_add2_insn (reloadreg, inc));
8876 store = emit_insn (gen_move_insn (incloc, reloadreg));
8881 Because this might be a jump insn or a compare, and because RELOADREG
8882 may not be available after the insn in an input reload, we must do
8883 the incrementation before the insn being reloaded for.
8885 We have already copied IN to RELOADREG. Increment the copy in
8886 RELOADREG, save that back, then decrement RELOADREG so it has
8887 the original value. */
8889 emit_insn (gen_add2_insn (reloadreg, inc));
8890 store = emit_insn (gen_move_insn (incloc, reloadreg));
8891 if (CONST_INT_P (inc))
8892 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
8894 emit_insn (gen_sub2_insn (reloadreg, inc));
8902 add_auto_inc_notes (rtx insn, rtx x)
8904 enum rtx_code code = GET_CODE (x);
8908 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8910 add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
8914 /* Scan all the operand sub-expressions. */
8915 fmt = GET_RTX_FORMAT (code);
8916 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8919 add_auto_inc_notes (insn, XEXP (x, i));
8920 else if (fmt[i] == 'E')
8921 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8922 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8927 /* This is used by reload pass, that does emit some instructions after
8928 abnormal calls moving basic block end, but in fact it wants to emit
8929 them on the edge. Looks for abnormal call edges, find backward the
8930 proper call and fix the damage.
8932 Similar handle instructions throwing exceptions internally. */
8934 fixup_abnormal_edges (void)
8936 bool inserted = false;
8944 /* Look for cases we are interested in - calls or instructions causing
8946 FOR_EACH_EDGE (e, ei, bb->succs)
8948 if (e->flags & EDGE_ABNORMAL_CALL)
8950 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8951 == (EDGE_ABNORMAL | EDGE_EH))
8954 if (e && !CALL_P (BB_END (bb))
8955 && !can_throw_internal (BB_END (bb)))
8959 /* Get past the new insns generated. Allow notes, as the insns
8960 may be already deleted. */
8962 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8963 && !can_throw_internal (insn)
8964 && insn != BB_HEAD (bb))
8965 insn = PREV_INSN (insn);
8967 if (CALL_P (insn) || can_throw_internal (insn))
8971 stop = NEXT_INSN (BB_END (bb));
8973 insn = NEXT_INSN (insn);
8975 FOR_EACH_EDGE (e, ei, bb->succs)
8976 if (e->flags & EDGE_FALLTHRU)
8979 while (insn && insn != stop)
8981 next = NEXT_INSN (insn);
8986 /* Sometimes there's still the return value USE.
8987 If it's placed after a trapping call (i.e. that
8988 call is the last insn anyway), we have no fallthru
8989 edge. Simply delete this use and don't try to insert
8990 on the non-existent edge. */
8991 if (GET_CODE (PATTERN (insn)) != USE)
8993 /* We're not deleting it, we're moving it. */
8994 INSN_DELETED_P (insn) = 0;
8995 PREV_INSN (insn) = NULL_RTX;
8996 NEXT_INSN (insn) = NULL_RTX;
8998 insert_insn_on_edge (insn, e);
9002 else if (!BARRIER_P (insn))
9003 set_block_for_insn (insn, NULL);
9008 /* It may be that we don't find any such trapping insn. In this
9009 case we discovered quite late that the insn that had been
9010 marked as can_throw_internal in fact couldn't trap at all.
9011 So we should in fact delete the EH edges out of the block. */
9013 purge_dead_edges (bb);
9017 /* We've possibly turned single trapping insn into multiple ones. */
9018 if (flag_non_call_exceptions)
9021 blocks = sbitmap_alloc (last_basic_block);
9022 sbitmap_ones (blocks);
9023 find_many_sub_basic_blocks (blocks);
9024 sbitmap_free (blocks);
9028 commit_edge_insertions ();
9030 #ifdef ENABLE_CHECKING
9031 /* Verify that we didn't turn one trapping insn into many, and that
9032 we found and corrected all of the problems wrt fixups on the
9034 verify_flow_info ();
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