1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 88, 89, 92-6, 1997 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "insn-config.h"
27 #include "insn-flags.h"
28 #include "insn-codes.h"
32 #include "hard-reg-set.h"
35 #include "basic-block.h"
39 /* This file contains the reload pass of the compiler, which is
40 run after register allocation has been done. It checks that
41 each insn is valid (operands required to be in registers really
42 are in registers of the proper class) and fixes up invalid ones
43 by copying values temporarily into registers for the insns
46 The results of register allocation are described by the vector
47 reg_renumber; the insns still contain pseudo regs, but reg_renumber
48 can be used to find which hard reg, if any, a pseudo reg is in.
50 The technique we always use is to free up a few hard regs that are
51 called ``reload regs'', and for each place where a pseudo reg
52 must be in a hard reg, copy it temporarily into one of the reload regs.
54 All the pseudos that were formerly allocated to the hard regs that
55 are now in use as reload regs must be ``spilled''. This means
56 that they go to other hard regs, or to stack slots if no other
57 available hard regs can be found. Spilling can invalidate more
58 insns, requiring additional need for reloads, so we must keep checking
59 until the process stabilizes.
61 For machines with different classes of registers, we must keep track
62 of the register class needed for each reload, and make sure that
63 we allocate enough reload registers of each class.
65 The file reload.c contains the code that checks one insn for
66 validity and reports the reloads that it needs. This file
67 is in charge of scanning the entire rtl code, accumulating the
68 reload needs, spilling, assigning reload registers to use for
69 fixing up each insn, and generating the new insns to copy values
70 into the reload registers. */
73 #ifndef REGISTER_MOVE_COST
74 #define REGISTER_MOVE_COST(x, y) 2
77 #ifndef MEMORY_MOVE_COST
78 #define MEMORY_MOVE_COST(x) 4
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx *reg_equiv_memory_loc;
105 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
106 This is used when the address is not valid as a memory address
107 (because its displacement is too big for the machine.) */
108 rtx *reg_equiv_address;
110 /* Element N is the memory slot to which pseudo reg N is equivalent,
111 or zero if pseudo reg N is not equivalent to a memory slot. */
114 /* Widest width in which each pseudo reg is referred to (via subreg). */
115 static int *reg_max_ref_width;
117 /* Element N is the insn that initialized reg N from its equivalent
118 constant or memory slot. */
119 static rtx *reg_equiv_init;
121 /* During reload_as_needed, element N contains the last pseudo regno
122 reloaded into the Nth reload register. This vector is in parallel
123 with spill_regs. If that pseudo reg occupied more than one register,
124 reg_reloaded_contents points to that pseudo for each spill register in
125 use; all of these must remain set for an inheritance to occur. */
126 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
128 /* During reload_as_needed, element N contains the insn for which
129 the Nth reload register was last used. This vector is in parallel
130 with spill_regs, and its contents are significant only when
131 reg_reloaded_contents is significant. */
132 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
134 /* Number of spill-regs so far; number of valid elements of spill_regs. */
137 /* In parallel with spill_regs, contains REG rtx's for those regs.
138 Holds the last rtx used for any given reg, or 0 if it has never
139 been used for spilling yet. This rtx is reused, provided it has
141 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
143 /* In parallel with spill_regs, contains nonzero for a spill reg
144 that was stored after the last time it was used.
145 The precise value is the insn generated to do the store. */
146 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
148 /* This table is the inverse mapping of spill_regs:
149 indexed by hard reg number,
150 it contains the position of that reg in spill_regs,
151 or -1 for something that is not in spill_regs. */
152 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
154 /* This reg set indicates registers that may not be used for retrying global
155 allocation. The registers that may not be used include all spill registers
156 and the frame pointer (if we are using one). */
157 HARD_REG_SET forbidden_regs;
159 /* This reg set indicates registers that are not good for spill registers.
160 They will not be used to complete groups of spill registers. This includes
161 all fixed registers, registers that may be eliminated, and, if
162 SMALL_REGISTER_CLASSES is not defined, registers explicitly used in the rtl.
164 (spill_reg_order prevents these registers from being used to start a
166 static HARD_REG_SET bad_spill_regs;
168 /* Describes order of use of registers for reloading
169 of spilled pseudo-registers. `spills' is the number of
170 elements that are actually valid; new ones are added at the end. */
171 static short spill_regs[FIRST_PSEUDO_REGISTER];
173 /* This reg set indicates those registers that have been used a spill
174 registers. This information is used in reorg.c, to help figure out
175 what registers are live at any point. It is assumed that all spill_regs
176 are dead at every CODE_LABEL. */
178 HARD_REG_SET used_spill_regs;
180 /* Index of last register assigned as a spill register. We allocate in
181 a round-robin fashion. */
183 static int last_spill_reg;
185 /* Describes order of preference for putting regs into spill_regs.
186 Contains the numbers of all the hard regs, in order most preferred first.
187 This order is different for each function.
188 It is set up by order_regs_for_reload.
189 Empty elements at the end contain -1. */
190 static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
192 /* 1 for a hard register that appears explicitly in the rtl
193 (for example, function value registers, special registers
194 used by insns, structure value pointer registers). */
195 static char regs_explicitly_used[FIRST_PSEUDO_REGISTER];
197 /* Indicates if a register was counted against the need for
198 groups. 0 means it can count against max_nongroup instead. */
199 static HARD_REG_SET counted_for_groups;
201 /* Indicates if a register was counted against the need for
202 non-groups. 0 means it can become part of a new group.
203 During choose_reload_regs, 1 here means don't use this reg
204 as part of a group, even if it seems to be otherwise ok. */
205 static HARD_REG_SET counted_for_nongroups;
207 /* Indexed by pseudo reg number N,
208 says may not delete stores into the real (memory) home of pseudo N.
209 This is set if we already substituted a memory equivalent in some uses,
210 which happens when we have to eliminate the fp from it. */
211 static char *cannot_omit_stores;
213 /* Nonzero if indirect addressing is supported on the machine; this means
214 that spilling (REG n) does not require reloading it into a register in
215 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
216 value indicates the level of indirect addressing supported, e.g., two
217 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
220 static char spill_indirect_levels;
222 /* Nonzero if indirect addressing is supported when the innermost MEM is
223 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
224 which these are valid is the same as spill_indirect_levels, above. */
226 char indirect_symref_ok;
228 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
230 char double_reg_address_ok;
232 /* Record the stack slot for each spilled hard register. */
234 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
236 /* Width allocated so far for that stack slot. */
238 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
240 /* Indexed by register class and basic block number, nonzero if there is
241 any need for a spill register of that class in that basic block.
242 The pointer is 0 if we did stupid allocation and don't know
243 the structure of basic blocks. */
245 char *basic_block_needs[N_REG_CLASSES];
247 /* First uid used by insns created by reload in this function.
248 Used in find_equiv_reg. */
249 int reload_first_uid;
251 /* Flag set by local-alloc or global-alloc if anything is live in
252 a call-clobbered reg across calls. */
254 int caller_save_needed;
256 /* The register class to use for a base register when reloading an
257 address. This is normally BASE_REG_CLASS, but it may be different
258 when using SMALL_REGISTER_CLASSES and passing parameters in
260 enum reg_class reload_address_base_reg_class;
262 /* The register class to use for an index register when reloading an
263 address. This is normally INDEX_REG_CLASS, but it may be different
264 when using SMALL_REGISTER_CLASSES and passing parameters in
266 enum reg_class reload_address_index_reg_class;
268 /* Set to 1 while reload_as_needed is operating.
269 Required by some machines to handle any generated moves differently. */
271 int reload_in_progress = 0;
273 /* These arrays record the insn_code of insns that may be needed to
274 perform input and output reloads of special objects. They provide a
275 place to pass a scratch register. */
277 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
278 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
280 /* This obstack is used for allocation of rtl during register elimination.
281 The allocated storage can be freed once find_reloads has processed the
284 struct obstack reload_obstack;
285 char *reload_firstobj;
287 #define obstack_chunk_alloc xmalloc
288 #define obstack_chunk_free free
290 /* List of labels that must never be deleted. */
291 extern rtx forced_labels;
293 /* Allocation number table from global register allocation. */
294 extern int *reg_allocno;
296 /* This structure is used to record information about register eliminations.
297 Each array entry describes one possible way of eliminating a register
298 in favor of another. If there is more than one way of eliminating a
299 particular register, the most preferred should be specified first. */
301 static struct elim_table
303 int from; /* Register number to be eliminated. */
304 int to; /* Register number used as replacement. */
305 int initial_offset; /* Initial difference between values. */
306 int can_eliminate; /* Non-zero if this elimination can be done. */
307 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
308 insns made by reload. */
309 int offset; /* Current offset between the two regs. */
310 int max_offset; /* Maximum offset between the two regs. */
311 int previous_offset; /* Offset at end of previous insn. */
312 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
313 rtx from_rtx; /* REG rtx for the register to be eliminated.
314 We cannot simply compare the number since
315 we might then spuriously replace a hard
316 register corresponding to a pseudo
317 assigned to the reg to be eliminated. */
318 rtx to_rtx; /* REG rtx for the replacement. */
321 /* If a set of eliminable registers was specified, define the table from it.
322 Otherwise, default to the normal case of the frame pointer being
323 replaced by the stack pointer. */
325 #ifdef ELIMINABLE_REGS
328 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
331 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate / sizeof reg_eliminate[0])
333 /* Record the number of pending eliminations that have an offset not equal
334 to their initial offset. If non-zero, we use a new copy of each
335 replacement result in any insns encountered. */
336 static int num_not_at_initial_offset;
338 /* Count the number of registers that we may be able to eliminate. */
339 static int num_eliminable;
341 /* For each label, we record the offset of each elimination. If we reach
342 a label by more than one path and an offset differs, we cannot do the
343 elimination. This information is indexed by the number of the label.
344 The first table is an array of flags that records whether we have yet
345 encountered a label and the second table is an array of arrays, one
346 entry in the latter array for each elimination. */
348 static char *offsets_known_at;
349 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
351 /* Number of labels in the current function. */
353 static int num_labels;
355 struct hard_reg_n_uses { int regno; int uses; };
357 static int possible_group_p PROTO((int, int *));
358 static void count_possible_groups PROTO((int *, enum machine_mode *,
360 static int modes_equiv_for_class_p PROTO((enum machine_mode,
363 static void spill_failure PROTO((rtx));
364 static int new_spill_reg PROTO((int, int, int *, int *, int,
366 static void delete_dead_insn PROTO((rtx));
367 static void alter_reg PROTO((int, int));
368 static void mark_scratch_live PROTO((rtx));
369 static void set_label_offsets PROTO((rtx, rtx, int));
370 static int eliminate_regs_in_insn PROTO((rtx, int));
371 static void mark_not_eliminable PROTO((rtx, rtx));
372 static int spill_hard_reg PROTO((int, int, FILE *, int));
373 static void scan_paradoxical_subregs PROTO((rtx));
374 static int hard_reg_use_compare PROTO((const GENERIC_PTR, const GENERIC_PTR));
375 static void order_regs_for_reload PROTO((int));
376 static int compare_spill_regs PROTO((const GENERIC_PTR, const GENERIC_PTR));
377 static void reload_as_needed PROTO((rtx, int));
378 static void forget_old_reloads_1 PROTO((rtx, rtx));
379 static int reload_reg_class_lower PROTO((const GENERIC_PTR, const GENERIC_PTR));
380 static void mark_reload_reg_in_use PROTO((int, int, enum reload_type,
382 static void clear_reload_reg_in_use PROTO((int, int, enum reload_type,
384 static int reload_reg_free_p PROTO((int, int, enum reload_type));
385 static int reload_reg_free_before_p PROTO((int, int, enum reload_type));
386 static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type));
387 static int reloads_conflict PROTO((int, int));
388 static int allocate_reload_reg PROTO((int, rtx, int, int));
389 static void choose_reload_regs PROTO((rtx, rtx));
390 static void merge_assigned_reloads PROTO((rtx));
391 static void emit_reload_insns PROTO((rtx));
392 static void delete_output_reload PROTO((rtx, int, rtx));
393 static void inc_for_reload PROTO((rtx, rtx, int));
394 static int constraint_accepts_reg_p PROTO((char *, rtx));
395 static int count_occurrences PROTO((rtx, rtx));
396 static void reload_cse_invalidate_regno PROTO((int, enum machine_mode, int));
397 static int reload_cse_mem_conflict_p PROTO((rtx, rtx, enum machine_mode,
399 static void reload_cse_invalidate_mem PROTO((rtx));
400 static void reload_cse_invalidate_rtx PROTO((rtx, rtx));
401 static void reload_cse_regs PROTO((rtx));
402 static int reload_cse_regno_equal_p PROTO((int, rtx, enum machine_mode));
403 static int reload_cse_noop_set_p PROTO((rtx, rtx));
404 static void reload_cse_simplify_set PROTO((rtx, rtx));
405 static void reload_cse_check_clobber PROTO((rtx, rtx));
406 static void reload_cse_record_set PROTO((rtx, rtx));
408 /* Initialize the reload pass once per compilation. */
415 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
416 Set spill_indirect_levels to the number of levels such addressing is
417 permitted, zero if it is not permitted at all. */
420 = gen_rtx (MEM, Pmode,
421 gen_rtx (PLUS, Pmode,
422 gen_rtx (REG, Pmode, LAST_VIRTUAL_REGISTER + 1),
424 spill_indirect_levels = 0;
426 while (memory_address_p (QImode, tem))
428 spill_indirect_levels++;
429 tem = gen_rtx (MEM, Pmode, tem);
432 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
434 tem = gen_rtx (MEM, Pmode, gen_rtx (SYMBOL_REF, Pmode, "foo"));
435 indirect_symref_ok = memory_address_p (QImode, tem);
437 /* See if reg+reg is a valid (and offsettable) address. */
439 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
441 tem = gen_rtx (PLUS, Pmode,
442 gen_rtx (REG, Pmode, HARD_FRAME_POINTER_REGNUM),
443 gen_rtx (REG, Pmode, i));
444 /* This way, we make sure that reg+reg is an offsettable address. */
445 tem = plus_constant (tem, 4);
447 if (memory_address_p (QImode, tem))
449 double_reg_address_ok = 1;
454 /* Initialize obstack for our rtl allocation. */
455 gcc_obstack_init (&reload_obstack);
456 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
458 /* Decide which register class should be used when reloading
459 addresses. If we are using SMALL_REGISTER_CLASSES, and any
460 parameters are passed in registers, then we do not want to use
461 those registers when reloading an address. Otherwise, if a
462 function argument needs a reload, we may wind up clobbering
463 another argument to the function which was already computed. If
464 we find a subset class which simply avoids those registers, we
465 use it instead. ??? It would be better to only use the
466 restricted class when we actually are loading function arguments,
467 but that is hard to determine. */
468 reload_address_base_reg_class = BASE_REG_CLASS;
469 reload_address_index_reg_class = INDEX_REG_CLASS;
470 #ifdef SMALL_REGISTER_CLASSES
471 if (SMALL_REGISTER_CLASSES)
474 HARD_REG_SET base, index;
477 COPY_HARD_REG_SET (base, reg_class_contents[BASE_REG_CLASS]);
478 COPY_HARD_REG_SET (index, reg_class_contents[INDEX_REG_CLASS]);
479 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
481 if (FUNCTION_ARG_REGNO_P (regno))
483 CLEAR_HARD_REG_BIT (base, regno);
484 CLEAR_HARD_REG_BIT (index, regno);
488 GO_IF_HARD_REG_EQUAL (base, reg_class_contents[BASE_REG_CLASS],
490 for (p = reg_class_subclasses[BASE_REG_CLASS];
491 *p != LIM_REG_CLASSES;
494 GO_IF_HARD_REG_EQUAL (base, reg_class_contents[*p], usebase);
497 reload_address_base_reg_class = *p;
502 GO_IF_HARD_REG_EQUAL (index, reg_class_contents[INDEX_REG_CLASS],
504 for (p = reg_class_subclasses[INDEX_REG_CLASS];
505 *p != LIM_REG_CLASSES;
508 GO_IF_HARD_REG_EQUAL (index, reg_class_contents[*p], useindex);
511 reload_address_index_reg_class = *p;
516 #endif /* SMALL_REGISTER_CLASSES */
519 /* Main entry point for the reload pass.
521 FIRST is the first insn of the function being compiled.
523 GLOBAL nonzero means we were called from global_alloc
524 and should attempt to reallocate any pseudoregs that we
525 displace from hard regs we will use for reloads.
526 If GLOBAL is zero, we do not have enough information to do that,
527 so any pseudo reg that is spilled must go to the stack.
529 DUMPFILE is the global-reg debugging dump file stream, or 0.
530 If it is nonzero, messages are written to it to describe
531 which registers are seized as reload regs, which pseudo regs
532 are spilled from them, and where the pseudo regs are reallocated to.
534 Return value is nonzero if reload failed
535 and we must not do any more for this function. */
538 reload (first, global, dumpfile)
544 register int i, j, k;
546 register struct elim_table *ep;
548 int something_changed;
549 int something_needs_reloads;
550 int something_needs_elimination;
551 int new_basic_block_needs;
552 enum reg_class caller_save_spill_class = NO_REGS;
553 int caller_save_group_size = 1;
555 /* Nonzero means we couldn't get enough spill regs. */
558 /* The basic block number currently being processed for INSN. */
561 /* Make sure even insns with volatile mem refs are recognizable. */
564 /* Enable find_equiv_reg to distinguish insns made by reload. */
565 reload_first_uid = get_max_uid ();
567 for (i = 0; i < N_REG_CLASSES; i++)
568 basic_block_needs[i] = 0;
570 #ifdef SECONDARY_MEMORY_NEEDED
571 /* Initialize the secondary memory table. */
572 clear_secondary_mem ();
575 /* Remember which hard regs appear explicitly
576 before we merge into `regs_ever_live' the ones in which
577 pseudo regs have been allocated. */
578 bcopy (regs_ever_live, regs_explicitly_used, sizeof regs_ever_live);
580 /* We don't have a stack slot for any spill reg yet. */
581 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
582 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
584 /* Initialize the save area information for caller-save, in case some
588 /* Compute which hard registers are now in use
589 as homes for pseudo registers.
590 This is done here rather than (eg) in global_alloc
591 because this point is reached even if not optimizing. */
592 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
595 /* A function that receives a nonlocal goto must save all call-saved
597 if (current_function_has_nonlocal_label)
598 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
600 if (! call_used_regs[i] && ! fixed_regs[i])
601 regs_ever_live[i] = 1;
604 for (i = 0; i < scratch_list_length; i++)
606 mark_scratch_live (scratch_list[i]);
608 /* Make sure that the last insn in the chain
609 is not something that needs reloading. */
610 emit_note (NULL_PTR, NOTE_INSN_DELETED);
612 /* Find all the pseudo registers that didn't get hard regs
613 but do have known equivalent constants or memory slots.
614 These include parameters (known equivalent to parameter slots)
615 and cse'd or loop-moved constant memory addresses.
617 Record constant equivalents in reg_equiv_constant
618 so they will be substituted by find_reloads.
619 Record memory equivalents in reg_mem_equiv so they can
620 be substituted eventually by altering the REG-rtx's. */
622 reg_equiv_constant = (rtx *) alloca (max_regno * sizeof (rtx));
623 bzero ((char *) reg_equiv_constant, max_regno * sizeof (rtx));
624 reg_equiv_memory_loc = (rtx *) alloca (max_regno * sizeof (rtx));
625 bzero ((char *) reg_equiv_memory_loc, max_regno * sizeof (rtx));
626 reg_equiv_mem = (rtx *) alloca (max_regno * sizeof (rtx));
627 bzero ((char *) reg_equiv_mem, max_regno * sizeof (rtx));
628 reg_equiv_init = (rtx *) alloca (max_regno * sizeof (rtx));
629 bzero ((char *) reg_equiv_init, max_regno * sizeof (rtx));
630 reg_equiv_address = (rtx *) alloca (max_regno * sizeof (rtx));
631 bzero ((char *) reg_equiv_address, max_regno * sizeof (rtx));
632 reg_max_ref_width = (int *) alloca (max_regno * sizeof (int));
633 bzero ((char *) reg_max_ref_width, max_regno * sizeof (int));
634 cannot_omit_stores = (char *) alloca (max_regno);
635 bzero (cannot_omit_stores, max_regno);
637 #ifdef SMALL_REGISTER_CLASSES
638 if (SMALL_REGISTER_CLASSES)
639 CLEAR_HARD_REG_SET (forbidden_regs);
642 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
643 Also find all paradoxical subregs and find largest such for each pseudo.
644 On machines with small register classes, record hard registers that
645 are used for user variables. These can never be used for spills.
646 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
647 caller-saved registers must be marked live. */
649 for (insn = first; insn; insn = NEXT_INSN (insn))
651 rtx set = single_set (insn);
653 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
654 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
655 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
656 if (! call_used_regs[i])
657 regs_ever_live[i] = 1;
659 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
661 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
663 #ifdef LEGITIMATE_PIC_OPERAND_P
664 && (! CONSTANT_P (XEXP (note, 0)) || ! flag_pic
665 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
669 rtx x = XEXP (note, 0);
670 i = REGNO (SET_DEST (set));
671 if (i > LAST_VIRTUAL_REGISTER)
673 if (GET_CODE (x) == MEM)
674 reg_equiv_memory_loc[i] = x;
675 else if (CONSTANT_P (x))
677 if (LEGITIMATE_CONSTANT_P (x))
678 reg_equiv_constant[i] = x;
680 reg_equiv_memory_loc[i]
681 = force_const_mem (GET_MODE (SET_DEST (set)), x);
686 /* If this register is being made equivalent to a MEM
687 and the MEM is not SET_SRC, the equivalencing insn
688 is one with the MEM as a SET_DEST and it occurs later.
689 So don't mark this insn now. */
690 if (GET_CODE (x) != MEM
691 || rtx_equal_p (SET_SRC (set), x))
692 reg_equiv_init[i] = insn;
697 /* If this insn is setting a MEM from a register equivalent to it,
698 this is the equivalencing insn. */
699 else if (set && GET_CODE (SET_DEST (set)) == MEM
700 && GET_CODE (SET_SRC (set)) == REG
701 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
702 && rtx_equal_p (SET_DEST (set),
703 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
704 reg_equiv_init[REGNO (SET_SRC (set))] = insn;
706 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
707 scan_paradoxical_subregs (PATTERN (insn));
710 /* Does this function require a frame pointer? */
712 frame_pointer_needed = (! flag_omit_frame_pointer
713 #ifdef EXIT_IGNORE_STACK
714 /* ?? If EXIT_IGNORE_STACK is set, we will not save
715 and restore sp for alloca. So we can't eliminate
716 the frame pointer in that case. At some point,
717 we should improve this by emitting the
718 sp-adjusting insns for this case. */
719 || (current_function_calls_alloca
720 && EXIT_IGNORE_STACK)
722 || FRAME_POINTER_REQUIRED);
726 /* Initialize the table of registers to eliminate. The way we do this
727 depends on how the eliminable registers were defined. */
728 #ifdef ELIMINABLE_REGS
729 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
731 ep->can_eliminate = ep->can_eliminate_previous
732 = (CAN_ELIMINATE (ep->from, ep->to)
733 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
736 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
737 = ! frame_pointer_needed;
740 /* Count the number of eliminable registers and build the FROM and TO
741 REG rtx's. Note that code in gen_rtx will cause, e.g.,
742 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
743 We depend on this. */
744 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
746 num_eliminable += ep->can_eliminate;
747 ep->from_rtx = gen_rtx (REG, Pmode, ep->from);
748 ep->to_rtx = gen_rtx (REG, Pmode, ep->to);
751 num_labels = max_label_num () - get_first_label_num ();
753 /* Allocate the tables used to store offset information at labels. */
754 offsets_known_at = (char *) alloca (num_labels);
756 = (int (*)[NUM_ELIMINABLE_REGS])
757 alloca (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
759 offsets_known_at -= get_first_label_num ();
760 offsets_at -= get_first_label_num ();
762 /* Alter each pseudo-reg rtx to contain its hard reg number.
763 Assign stack slots to the pseudos that lack hard regs or equivalents.
764 Do not touch virtual registers. */
766 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
769 /* If we have some registers we think can be eliminated, scan all insns to
770 see if there is an insn that sets one of these registers to something
771 other than itself plus a constant. If so, the register cannot be
772 eliminated. Doing this scan here eliminates an extra pass through the
773 main reload loop in the most common case where register elimination
775 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
776 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
777 || GET_CODE (insn) == CALL_INSN)
778 note_stores (PATTERN (insn), mark_not_eliminable);
780 #ifndef REGISTER_CONSTRAINTS
781 /* If all the pseudo regs have hard regs,
782 except for those that are never referenced,
783 we know that no reloads are needed. */
784 /* But that is not true if there are register constraints, since
785 in that case some pseudos might be in the wrong kind of hard reg. */
787 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
788 if (reg_renumber[i] == -1 && reg_n_refs[i] != 0)
791 if (i == max_regno && num_eliminable == 0 && ! caller_save_needed)
795 /* Compute the order of preference for hard registers to spill.
796 Store them by decreasing preference in potential_reload_regs. */
798 order_regs_for_reload (global);
800 /* So far, no hard regs have been spilled. */
802 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
803 spill_reg_order[i] = -1;
805 /* Initialize to -1, which means take the first spill register. */
808 /* On most machines, we can't use any register explicitly used in the
809 rtl as a spill register. But on some, we have to. Those will have
810 taken care to keep the life of hard regs as short as possible. */
812 #ifdef SMALL_REGISTER_CLASSES
813 if (! SMALL_REGISTER_CLASSES)
815 COPY_HARD_REG_SET (forbidden_regs, bad_spill_regs);
817 /* Spill any hard regs that we know we can't eliminate. */
818 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
819 if (! ep->can_eliminate)
820 spill_hard_reg (ep->from, global, dumpfile, 1);
822 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
823 if (frame_pointer_needed)
824 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, global, dumpfile, 1);
828 for (i = 0; i < N_REG_CLASSES; i++)
830 basic_block_needs[i] = (char *) alloca (n_basic_blocks);
831 bzero (basic_block_needs[i], n_basic_blocks);
834 /* From now on, we need to emit any moves without making new pseudos. */
835 reload_in_progress = 1;
837 /* This loop scans the entire function each go-round
838 and repeats until one repetition spills no additional hard regs. */
840 /* This flag is set when a pseudo reg is spilled,
841 to require another pass. Note that getting an additional reload
842 reg does not necessarily imply any pseudo reg was spilled;
843 sometimes we find a reload reg that no pseudo reg was allocated in. */
844 something_changed = 1;
845 /* This flag is set if there are any insns that require reloading. */
846 something_needs_reloads = 0;
847 /* This flag is set if there are any insns that require register
849 something_needs_elimination = 0;
850 while (something_changed)
854 /* For each class, number of reload regs needed in that class.
855 This is the maximum over all insns of the needs in that class
856 of the individual insn. */
857 int max_needs[N_REG_CLASSES];
858 /* For each class, size of group of consecutive regs
859 that is needed for the reloads of this class. */
860 int group_size[N_REG_CLASSES];
861 /* For each class, max number of consecutive groups needed.
862 (Each group contains group_size[CLASS] consecutive registers.) */
863 int max_groups[N_REG_CLASSES];
864 /* For each class, max number needed of regs that don't belong
865 to any of the groups. */
866 int max_nongroups[N_REG_CLASSES];
867 /* For each class, the machine mode which requires consecutive
868 groups of regs of that class.
869 If two different modes ever require groups of one class,
870 they must be the same size and equally restrictive for that class,
871 otherwise we can't handle the complexity. */
872 enum machine_mode group_mode[N_REG_CLASSES];
873 /* Record the insn where each maximum need is first found. */
874 rtx max_needs_insn[N_REG_CLASSES];
875 rtx max_groups_insn[N_REG_CLASSES];
876 rtx max_nongroups_insn[N_REG_CLASSES];
878 HOST_WIDE_INT starting_frame_size;
879 int previous_frame_pointer_needed = frame_pointer_needed;
880 static char *reg_class_names[] = REG_CLASS_NAMES;
882 something_changed = 0;
883 bzero ((char *) max_needs, sizeof max_needs);
884 bzero ((char *) max_groups, sizeof max_groups);
885 bzero ((char *) max_nongroups, sizeof max_nongroups);
886 bzero ((char *) max_needs_insn, sizeof max_needs_insn);
887 bzero ((char *) max_groups_insn, sizeof max_groups_insn);
888 bzero ((char *) max_nongroups_insn, sizeof max_nongroups_insn);
889 bzero ((char *) group_size, sizeof group_size);
890 for (i = 0; i < N_REG_CLASSES; i++)
891 group_mode[i] = VOIDmode;
893 /* Keep track of which basic blocks are needing the reloads. */
896 /* Remember whether any element of basic_block_needs
897 changes from 0 to 1 in this pass. */
898 new_basic_block_needs = 0;
900 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done
901 here because the stack size may be a part of the offset computation
902 for register elimination, and there might have been new stack slots
903 created in the last iteration of this loop. */
904 assign_stack_local (BLKmode, 0, 0);
906 starting_frame_size = get_frame_size ();
908 /* Reset all offsets on eliminable registers to their initial values. */
909 #ifdef ELIMINABLE_REGS
910 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
912 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
913 ep->previous_offset = ep->offset
914 = ep->max_offset = ep->initial_offset;
917 #ifdef INITIAL_FRAME_POINTER_OFFSET
918 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
920 if (!FRAME_POINTER_REQUIRED)
922 reg_eliminate[0].initial_offset = 0;
924 reg_eliminate[0].previous_offset = reg_eliminate[0].max_offset
925 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
928 num_not_at_initial_offset = 0;
930 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
932 /* Set a known offset for each forced label to be at the initial offset
933 of each elimination. We do this because we assume that all
934 computed jumps occur from a location where each elimination is
935 at its initial offset. */
937 for (x = forced_labels; x; x = XEXP (x, 1))
939 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
941 /* For each pseudo register that has an equivalent location defined,
942 try to eliminate any eliminable registers (such as the frame pointer)
943 assuming initial offsets for the replacement register, which
946 If the resulting location is directly addressable, substitute
947 the MEM we just got directly for the old REG.
949 If it is not addressable but is a constant or the sum of a hard reg
950 and constant, it is probably not addressable because the constant is
951 out of range, in that case record the address; we will generate
952 hairy code to compute the address in a register each time it is
953 needed. Similarly if it is a hard register, but one that is not
954 valid as an address register.
956 If the location is not addressable, but does not have one of the
957 above forms, assign a stack slot. We have to do this to avoid the
958 potential of producing lots of reloads if, e.g., a location involves
959 a pseudo that didn't get a hard register and has an equivalent memory
960 location that also involves a pseudo that didn't get a hard register.
962 Perhaps at some point we will improve reload_when_needed handling
963 so this problem goes away. But that's very hairy. */
965 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
966 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
968 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX, 0);
970 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
972 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
973 else if (CONSTANT_P (XEXP (x, 0))
974 || (GET_CODE (XEXP (x, 0)) == REG
975 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
976 || (GET_CODE (XEXP (x, 0)) == PLUS
977 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
978 && (REGNO (XEXP (XEXP (x, 0), 0))
979 < FIRST_PSEUDO_REGISTER)
980 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
981 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
984 /* Make a new stack slot. Then indicate that something
985 changed so we go back and recompute offsets for
986 eliminable registers because the allocation of memory
987 below might change some offset. reg_equiv_{mem,address}
988 will be set up for this pseudo on the next pass around
990 reg_equiv_memory_loc[i] = 0;
991 reg_equiv_init[i] = 0;
993 something_changed = 1;
997 /* If we allocated another pseudo to the stack, redo elimination
999 if (something_changed)
1002 /* If caller-saves needs a group, initialize the group to include
1003 the size and mode required for caller-saves. */
1005 if (caller_save_group_size > 1)
1007 group_mode[(int) caller_save_spill_class] = Pmode;
1008 group_size[(int) caller_save_spill_class] = caller_save_group_size;
1011 /* Compute the most additional registers needed by any instruction.
1012 Collect information separately for each class of regs. */
1014 for (insn = first; insn; insn = NEXT_INSN (insn))
1016 if (global && this_block + 1 < n_basic_blocks
1017 && insn == basic_block_head[this_block+1])
1020 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which
1021 might include REG_LABEL), we need to see what effects this
1022 has on the known offsets at labels. */
1024 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1025 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1026 && REG_NOTES (insn) != 0))
1027 set_label_offsets (insn, insn, 0);
1029 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1031 /* Nonzero means don't use a reload reg that overlaps
1032 the place where a function value can be returned. */
1033 rtx avoid_return_reg = 0;
1035 rtx old_body = PATTERN (insn);
1036 int old_code = INSN_CODE (insn);
1037 rtx old_notes = REG_NOTES (insn);
1038 int did_elimination = 0;
1040 /* To compute the number of reload registers of each class
1041 needed for an insn, we must simulate what choose_reload_regs
1042 can do. We do this by splitting an insn into an "input" and
1043 an "output" part. RELOAD_OTHER reloads are used in both.
1044 The input part uses those reloads, RELOAD_FOR_INPUT reloads,
1045 which must be live over the entire input section of reloads,
1046 and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
1047 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the
1050 The registers needed for output are RELOAD_OTHER and
1051 RELOAD_FOR_OUTPUT, which are live for the entire output
1052 portion, and the maximum of all the RELOAD_FOR_OUTPUT_ADDRESS
1053 reloads for each operand.
1055 The total number of registers needed is the maximum of the
1056 inputs and outputs. */
1060 /* [0] is normal, [1] is nongroup. */
1061 int regs[2][N_REG_CLASSES];
1062 int groups[N_REG_CLASSES];
1065 /* Each `struct needs' corresponds to one RELOAD_... type. */
1069 struct needs output;
1071 struct needs other_addr;
1072 struct needs op_addr;
1073 struct needs op_addr_reload;
1074 struct needs in_addr[MAX_RECOG_OPERANDS];
1075 struct needs in_addr_addr[MAX_RECOG_OPERANDS];
1076 struct needs out_addr[MAX_RECOG_OPERANDS];
1077 struct needs out_addr_addr[MAX_RECOG_OPERANDS];
1080 /* If needed, eliminate any eliminable registers. */
1082 did_elimination = eliminate_regs_in_insn (insn, 0);
1084 #ifdef SMALL_REGISTER_CLASSES
1085 /* Set avoid_return_reg if this is an insn
1086 that might use the value of a function call. */
1087 if (SMALL_REGISTER_CLASSES && GET_CODE (insn) == CALL_INSN)
1089 if (GET_CODE (PATTERN (insn)) == SET)
1090 after_call = SET_DEST (PATTERN (insn));
1091 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1092 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1093 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
1097 else if (SMALL_REGISTER_CLASSES
1099 && !(GET_CODE (PATTERN (insn)) == SET
1100 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
1102 if (reg_referenced_p (after_call, PATTERN (insn)))
1103 avoid_return_reg = after_call;
1106 #endif /* SMALL_REGISTER_CLASSES */
1108 /* Analyze the instruction. */
1109 find_reloads (insn, 0, spill_indirect_levels, global,
1112 /* Remember for later shortcuts which insns had any reloads or
1113 register eliminations.
1115 One might think that it would be worthwhile to mark insns
1116 that need register replacements but not reloads, but this is
1117 not safe because find_reloads may do some manipulation of
1118 the insn (such as swapping commutative operands), which would
1119 be lost when we restore the old pattern after register
1120 replacement. So the actions of find_reloads must be redone in
1121 subsequent passes or in reload_as_needed.
1123 However, it is safe to mark insns that need reloads
1124 but not register replacement. */
1126 PUT_MODE (insn, (did_elimination ? QImode
1127 : n_reloads ? HImode
1128 : GET_MODE (insn) == DImode ? DImode
1131 /* Discard any register replacements done. */
1132 if (did_elimination)
1134 obstack_free (&reload_obstack, reload_firstobj);
1135 PATTERN (insn) = old_body;
1136 INSN_CODE (insn) = old_code;
1137 REG_NOTES (insn) = old_notes;
1138 something_needs_elimination = 1;
1141 /* If this insn has no reloads, we need not do anything except
1142 in the case of a CALL_INSN when we have caller-saves and
1143 caller-save needs reloads. */
1146 && ! (GET_CODE (insn) == CALL_INSN
1147 && caller_save_spill_class != NO_REGS))
1150 something_needs_reloads = 1;
1151 bzero ((char *) &insn_needs, sizeof insn_needs);
1153 /* Count each reload once in every class
1154 containing the reload's own class. */
1156 for (i = 0; i < n_reloads; i++)
1158 register enum reg_class *p;
1159 enum reg_class class = reload_reg_class[i];
1161 enum machine_mode mode;
1163 struct needs *this_needs;
1165 /* Don't count the dummy reloads, for which one of the
1166 regs mentioned in the insn can be used for reloading.
1167 Don't count optional reloads.
1168 Don't count reloads that got combined with others. */
1169 if (reload_reg_rtx[i] != 0
1170 || reload_optional[i] != 0
1171 || (reload_out[i] == 0 && reload_in[i] == 0
1172 && ! reload_secondary_p[i]))
1175 /* Show that a reload register of this class is needed
1176 in this basic block. We do not use insn_needs and
1177 insn_groups because they are overly conservative for
1179 if (global && ! basic_block_needs[(int) class][this_block])
1181 basic_block_needs[(int) class][this_block] = 1;
1182 new_basic_block_needs = 1;
1186 mode = reload_inmode[i];
1187 if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode))
1188 mode = reload_outmode[i];
1189 size = CLASS_MAX_NREGS (class, mode);
1191 /* If this class doesn't want a group, determine if we have
1192 a nongroup need or a regular need. We have a nongroup
1193 need if this reload conflicts with a group reload whose
1194 class intersects with this reload's class. */
1198 for (j = 0; j < n_reloads; j++)
1199 if ((CLASS_MAX_NREGS (reload_reg_class[j],
1200 (GET_MODE_SIZE (reload_outmode[j])
1201 > GET_MODE_SIZE (reload_inmode[j]))
1205 && (!reload_optional[j])
1206 && (reload_in[j] != 0 || reload_out[j] != 0
1207 || reload_secondary_p[j])
1208 && reloads_conflict (i, j)
1209 && reg_classes_intersect_p (class,
1210 reload_reg_class[j]))
1216 /* Decide which time-of-use to count this reload for. */
1217 switch (reload_when_needed[i])
1220 this_needs = &insn_needs.other;
1222 case RELOAD_FOR_INPUT:
1223 this_needs = &insn_needs.input;
1225 case RELOAD_FOR_OUTPUT:
1226 this_needs = &insn_needs.output;
1228 case RELOAD_FOR_INSN:
1229 this_needs = &insn_needs.insn;
1231 case RELOAD_FOR_OTHER_ADDRESS:
1232 this_needs = &insn_needs.other_addr;
1234 case RELOAD_FOR_INPUT_ADDRESS:
1235 this_needs = &insn_needs.in_addr[reload_opnum[i]];
1237 case RELOAD_FOR_INPADDR_ADDRESS:
1238 this_needs = &insn_needs.in_addr_addr[reload_opnum[i]];
1240 case RELOAD_FOR_OUTPUT_ADDRESS:
1241 this_needs = &insn_needs.out_addr[reload_opnum[i]];
1243 case RELOAD_FOR_OUTADDR_ADDRESS:
1244 this_needs = &insn_needs.out_addr_addr[reload_opnum[i]];
1246 case RELOAD_FOR_OPERAND_ADDRESS:
1247 this_needs = &insn_needs.op_addr;
1249 case RELOAD_FOR_OPADDR_ADDR:
1250 this_needs = &insn_needs.op_addr_reload;
1256 enum machine_mode other_mode, allocate_mode;
1258 /* Count number of groups needed separately from
1259 number of individual regs needed. */
1260 this_needs->groups[(int) class]++;
1261 p = reg_class_superclasses[(int) class];
1262 while (*p != LIM_REG_CLASSES)
1263 this_needs->groups[(int) *p++]++;
1265 /* Record size and mode of a group of this class. */
1266 /* If more than one size group is needed,
1267 make all groups the largest needed size. */
1268 if (group_size[(int) class] < size)
1270 other_mode = group_mode[(int) class];
1271 allocate_mode = mode;
1273 group_size[(int) class] = size;
1274 group_mode[(int) class] = mode;
1279 allocate_mode = group_mode[(int) class];
1282 /* Crash if two dissimilar machine modes both need
1283 groups of consecutive regs of the same class. */
1285 if (other_mode != VOIDmode && other_mode != allocate_mode
1286 && ! modes_equiv_for_class_p (allocate_mode,
1288 fatal_insn ("Two dissimilar machine modes both need groups of consecutive regs of the same class",
1293 this_needs->regs[nongroup_need][(int) class] += 1;
1294 p = reg_class_superclasses[(int) class];
1295 while (*p != LIM_REG_CLASSES)
1296 this_needs->regs[nongroup_need][(int) *p++] += 1;
1302 /* All reloads have been counted for this insn;
1303 now merge the various times of use.
1304 This sets insn_needs, etc., to the maximum total number
1305 of registers needed at any point in this insn. */
1307 for (i = 0; i < N_REG_CLASSES; i++)
1309 int in_max, out_max;
1311 /* Compute normal and nongroup needs. */
1312 for (j = 0; j <= 1; j++)
1314 for (in_max = 0, out_max = 0, k = 0;
1315 k < reload_n_operands; k++)
1318 = MAX (in_max, insn_needs.in_addr[k].regs[j][i]);
1321 insn_needs.in_addr_addr[k].regs[j][i]);
1323 = MAX (out_max, insn_needs.out_addr[k].regs[j][i]);
1326 insn_needs.out_addr_addr[k].regs[j][i]);
1329 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1330 and operand addresses but not things used to reload
1331 them. Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads
1332 don't conflict with things needed to reload inputs or
1335 in_max = MAX (MAX (insn_needs.op_addr.regs[j][i],
1336 insn_needs.op_addr_reload.regs[j][i]),
1339 out_max = MAX (out_max, insn_needs.insn.regs[j][i]);
1341 insn_needs.input.regs[j][i]
1342 = MAX (insn_needs.input.regs[j][i]
1343 + insn_needs.op_addr.regs[j][i]
1344 + insn_needs.insn.regs[j][i],
1345 in_max + insn_needs.input.regs[j][i]);
1347 insn_needs.output.regs[j][i] += out_max;
1348 insn_needs.other.regs[j][i]
1349 += MAX (MAX (insn_needs.input.regs[j][i],
1350 insn_needs.output.regs[j][i]),
1351 insn_needs.other_addr.regs[j][i]);
1355 /* Now compute group needs. */
1356 for (in_max = 0, out_max = 0, j = 0;
1357 j < reload_n_operands; j++)
1359 in_max = MAX (in_max, insn_needs.in_addr[j].groups[i]);
1360 in_max = MAX (in_max,
1361 insn_needs.in_addr_addr[j].groups[i]);
1363 = MAX (out_max, insn_needs.out_addr[j].groups[i]);
1365 = MAX (out_max, insn_needs.out_addr_addr[j].groups[i]);
1368 in_max = MAX (MAX (insn_needs.op_addr.groups[i],
1369 insn_needs.op_addr_reload.groups[i]),
1371 out_max = MAX (out_max, insn_needs.insn.groups[i]);
1373 insn_needs.input.groups[i]
1374 = MAX (insn_needs.input.groups[i]
1375 + insn_needs.op_addr.groups[i]
1376 + insn_needs.insn.groups[i],
1377 in_max + insn_needs.input.groups[i]);
1379 insn_needs.output.groups[i] += out_max;
1380 insn_needs.other.groups[i]
1381 += MAX (MAX (insn_needs.input.groups[i],
1382 insn_needs.output.groups[i]),
1383 insn_needs.other_addr.groups[i]);
1386 /* If this is a CALL_INSN and caller-saves will need
1387 a spill register, act as if the spill register is
1388 needed for this insn. However, the spill register
1389 can be used by any reload of this insn, so we only
1390 need do something if no need for that class has
1393 The assumption that every CALL_INSN will trigger a
1394 caller-save is highly conservative, however, the number
1395 of cases where caller-saves will need a spill register but
1396 a block containing a CALL_INSN won't need a spill register
1397 of that class should be quite rare.
1399 If a group is needed, the size and mode of the group will
1400 have been set up at the beginning of this loop. */
1402 if (GET_CODE (insn) == CALL_INSN
1403 && caller_save_spill_class != NO_REGS)
1405 /* See if this register would conflict with any reload
1406 that needs a group. */
1407 int nongroup_need = 0;
1408 int *caller_save_needs;
1410 for (j = 0; j < n_reloads; j++)
1411 if ((CLASS_MAX_NREGS (reload_reg_class[j],
1412 (GET_MODE_SIZE (reload_outmode[j])
1413 > GET_MODE_SIZE (reload_inmode[j]))
1417 && reg_classes_intersect_p (caller_save_spill_class,
1418 reload_reg_class[j]))
1425 = (caller_save_group_size > 1
1426 ? insn_needs.other.groups
1427 : insn_needs.other.regs[nongroup_need]);
1429 if (caller_save_needs[(int) caller_save_spill_class] == 0)
1431 register enum reg_class *p
1432 = reg_class_superclasses[(int) caller_save_spill_class];
1434 caller_save_needs[(int) caller_save_spill_class]++;
1436 while (*p != LIM_REG_CLASSES)
1437 caller_save_needs[(int) *p++] += 1;
1440 /* Show that this basic block will need a register of
1444 && ! (basic_block_needs[(int) caller_save_spill_class]
1447 basic_block_needs[(int) caller_save_spill_class]
1449 new_basic_block_needs = 1;
1453 #ifdef SMALL_REGISTER_CLASSES
1454 /* If this insn stores the value of a function call,
1455 and that value is in a register that has been spilled,
1456 and if the insn needs a reload in a class
1457 that might use that register as the reload register,
1458 then add add an extra need in that class.
1459 This makes sure we have a register available that does
1460 not overlap the return value. */
1462 if (SMALL_REGISTER_CLASSES && avoid_return_reg)
1464 int regno = REGNO (avoid_return_reg);
1466 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
1468 int basic_needs[N_REG_CLASSES], basic_groups[N_REG_CLASSES];
1470 /* First compute the "basic needs", which counts a
1471 need only in the smallest class in which it
1474 bcopy ((char *) insn_needs.other.regs[0],
1475 (char *) basic_needs, sizeof basic_needs);
1476 bcopy ((char *) insn_needs.other.groups,
1477 (char *) basic_groups, sizeof basic_groups);
1479 for (i = 0; i < N_REG_CLASSES; i++)
1483 if (basic_needs[i] >= 0)
1484 for (p = reg_class_superclasses[i];
1485 *p != LIM_REG_CLASSES; p++)
1486 basic_needs[(int) *p] -= basic_needs[i];
1488 if (basic_groups[i] >= 0)
1489 for (p = reg_class_superclasses[i];
1490 *p != LIM_REG_CLASSES; p++)
1491 basic_groups[(int) *p] -= basic_groups[i];
1494 /* Now count extra regs if there might be a conflict with
1495 the return value register. */
1497 for (r = regno; r < regno + nregs; r++)
1498 if (spill_reg_order[r] >= 0)
1499 for (i = 0; i < N_REG_CLASSES; i++)
1500 if (TEST_HARD_REG_BIT (reg_class_contents[i], r))
1502 if (basic_needs[i] > 0)
1506 insn_needs.other.regs[0][i]++;
1507 p = reg_class_superclasses[i];
1508 while (*p != LIM_REG_CLASSES)
1509 insn_needs.other.regs[0][(int) *p++]++;
1511 if (basic_groups[i] > 0)
1515 insn_needs.other.groups[i]++;
1516 p = reg_class_superclasses[i];
1517 while (*p != LIM_REG_CLASSES)
1518 insn_needs.other.groups[(int) *p++]++;
1522 #endif /* SMALL_REGISTER_CLASSES */
1524 /* For each class, collect maximum need of any insn. */
1526 for (i = 0; i < N_REG_CLASSES; i++)
1528 if (max_needs[i] < insn_needs.other.regs[0][i])
1530 max_needs[i] = insn_needs.other.regs[0][i];
1531 max_needs_insn[i] = insn;
1533 if (max_groups[i] < insn_needs.other.groups[i])
1535 max_groups[i] = insn_needs.other.groups[i];
1536 max_groups_insn[i] = insn;
1538 if (max_nongroups[i] < insn_needs.other.regs[1][i])
1540 max_nongroups[i] = insn_needs.other.regs[1][i];
1541 max_nongroups_insn[i] = insn;
1545 /* Note that there is a continue statement above. */
1548 /* If we allocated any new memory locations, make another pass
1549 since it might have changed elimination offsets. */
1550 if (starting_frame_size != get_frame_size ())
1551 something_changed = 1;
1554 for (i = 0; i < N_REG_CLASSES; i++)
1556 if (max_needs[i] > 0)
1558 ";; Need %d reg%s of class %s (for insn %d).\n",
1559 max_needs[i], max_needs[i] == 1 ? "" : "s",
1560 reg_class_names[i], INSN_UID (max_needs_insn[i]));
1561 if (max_nongroups[i] > 0)
1563 ";; Need %d nongroup reg%s of class %s (for insn %d).\n",
1564 max_nongroups[i], max_nongroups[i] == 1 ? "" : "s",
1565 reg_class_names[i], INSN_UID (max_nongroups_insn[i]));
1566 if (max_groups[i] > 0)
1568 ";; Need %d group%s (%smode) of class %s (for insn %d).\n",
1569 max_groups[i], max_groups[i] == 1 ? "" : "s",
1570 mode_name[(int) group_mode[i]],
1571 reg_class_names[i], INSN_UID (max_groups_insn[i]));
1574 /* If we have caller-saves, set up the save areas and see if caller-save
1575 will need a spill register. */
1577 if (caller_save_needed)
1579 /* Set the offsets for setup_save_areas. */
1580 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
1582 ep->previous_offset = ep->max_offset;
1584 if ( ! setup_save_areas (&something_changed)
1585 && caller_save_spill_class == NO_REGS)
1587 /* The class we will need depends on whether the machine
1588 supports the sum of two registers for an address; see
1589 find_address_reloads for details. */
1591 caller_save_spill_class
1592 = double_reg_address_ok ? INDEX_REG_CLASS : BASE_REG_CLASS;
1593 caller_save_group_size
1594 = CLASS_MAX_NREGS (caller_save_spill_class, Pmode);
1595 something_changed = 1;
1599 /* See if anything that happened changes which eliminations are valid.
1600 For example, on the Sparc, whether or not the frame pointer can
1601 be eliminated can depend on what registers have been used. We need
1602 not check some conditions again (such as flag_omit_frame_pointer)
1603 since they can't have changed. */
1605 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1606 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
1607 #ifdef ELIMINABLE_REGS
1608 || ! CAN_ELIMINATE (ep->from, ep->to)
1611 ep->can_eliminate = 0;
1613 /* Look for the case where we have discovered that we can't replace
1614 register A with register B and that means that we will now be
1615 trying to replace register A with register C. This means we can
1616 no longer replace register C with register B and we need to disable
1617 such an elimination, if it exists. This occurs often with A == ap,
1618 B == sp, and C == fp. */
1620 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1622 struct elim_table *op;
1623 register int new_to = -1;
1625 if (! ep->can_eliminate && ep->can_eliminate_previous)
1627 /* Find the current elimination for ep->from, if there is a
1629 for (op = reg_eliminate;
1630 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1631 if (op->from == ep->from && op->can_eliminate)
1637 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
1639 for (op = reg_eliminate;
1640 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1641 if (op->from == new_to && op->to == ep->to)
1642 op->can_eliminate = 0;
1646 /* See if any registers that we thought we could eliminate the previous
1647 time are no longer eliminable. If so, something has changed and we
1648 must spill the register. Also, recompute the number of eliminable
1649 registers and see if the frame pointer is needed; it is if there is
1650 no elimination of the frame pointer that we can perform. */
1652 frame_pointer_needed = 1;
1653 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1655 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
1656 && ep->to != HARD_FRAME_POINTER_REGNUM)
1657 frame_pointer_needed = 0;
1659 if (! ep->can_eliminate && ep->can_eliminate_previous)
1661 ep->can_eliminate_previous = 0;
1662 spill_hard_reg (ep->from, global, dumpfile, 1);
1663 something_changed = 1;
1668 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1669 /* If we didn't need a frame pointer last time, but we do now, spill
1670 the hard frame pointer. */
1671 if (frame_pointer_needed && ! previous_frame_pointer_needed)
1673 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, global, dumpfile, 1);
1674 something_changed = 1;
1678 /* If all needs are met, we win. */
1680 for (i = 0; i < N_REG_CLASSES; i++)
1681 if (max_needs[i] > 0 || max_groups[i] > 0 || max_nongroups[i] > 0)
1683 if (i == N_REG_CLASSES && !new_basic_block_needs && ! something_changed)
1686 /* Not all needs are met; must spill some hard regs. */
1688 /* Put all registers spilled so far back in potential_reload_regs, but
1689 put them at the front, since we've already spilled most of the
1690 pseudos in them (we might have left some pseudos unspilled if they
1691 were in a block that didn't need any spill registers of a conflicting
1692 class. We used to try to mark off the need for those registers,
1693 but doing so properly is very complex and reallocating them is the
1694 simpler approach. First, "pack" potential_reload_regs by pushing
1695 any nonnegative entries towards the end. That will leave room
1696 for the registers we already spilled.
1698 Also, undo the marking of the spill registers from the last time
1699 around in FORBIDDEN_REGS since we will be probably be allocating
1702 ??? It is theoretically possible that we might end up not using one
1703 of our previously-spilled registers in this allocation, even though
1704 they are at the head of the list. It's not clear what to do about
1705 this, but it was no better before, when we marked off the needs met
1706 by the previously-spilled registers. With the current code, globals
1707 can be allocated into these registers, but locals cannot. */
1711 for (i = j = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
1712 if (potential_reload_regs[i] != -1)
1713 potential_reload_regs[j--] = potential_reload_regs[i];
1715 for (i = 0; i < n_spills; i++)
1717 potential_reload_regs[i] = spill_regs[i];
1718 spill_reg_order[spill_regs[i]] = -1;
1719 CLEAR_HARD_REG_BIT (forbidden_regs, spill_regs[i]);
1725 /* Now find more reload regs to satisfy the remaining need
1726 Do it by ascending class number, since otherwise a reg
1727 might be spilled for a big class and might fail to count
1728 for a smaller class even though it belongs to that class.
1730 Count spilled regs in `spills', and add entries to
1731 `spill_regs' and `spill_reg_order'.
1733 ??? Note there is a problem here.
1734 When there is a need for a group in a high-numbered class,
1735 and also need for non-group regs that come from a lower class,
1736 the non-group regs are chosen first. If there aren't many regs,
1737 they might leave no room for a group.
1739 This was happening on the 386. To fix it, we added the code
1740 that calls possible_group_p, so that the lower class won't
1741 break up the last possible group.
1743 Really fixing the problem would require changes above
1744 in counting the regs already spilled, and in choose_reload_regs.
1745 It might be hard to avoid introducing bugs there. */
1747 CLEAR_HARD_REG_SET (counted_for_groups);
1748 CLEAR_HARD_REG_SET (counted_for_nongroups);
1750 for (class = 0; class < N_REG_CLASSES; class++)
1752 /* First get the groups of registers.
1753 If we got single registers first, we might fragment
1755 while (max_groups[class] > 0)
1757 /* If any single spilled regs happen to form groups,
1758 count them now. Maybe we don't really need
1759 to spill another group. */
1760 count_possible_groups (group_size, group_mode, max_groups,
1763 if (max_groups[class] <= 0)
1766 /* Groups of size 2 (the only groups used on most machines)
1767 are treated specially. */
1768 if (group_size[class] == 2)
1770 /* First, look for a register that will complete a group. */
1771 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1775 j = potential_reload_regs[i];
1776 if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1778 ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1779 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1780 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1781 && HARD_REGNO_MODE_OK (other, group_mode[class])
1782 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1784 /* We don't want one part of another group.
1785 We could get "two groups" that overlap! */
1786 && ! TEST_HARD_REG_BIT (counted_for_groups, other))
1788 (j < FIRST_PSEUDO_REGISTER - 1
1789 && (other = j + 1, spill_reg_order[other] >= 0)
1790 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1791 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1792 && HARD_REGNO_MODE_OK (j, group_mode[class])
1793 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1795 && ! TEST_HARD_REG_BIT (counted_for_groups,
1798 register enum reg_class *p;
1800 /* We have found one that will complete a group,
1801 so count off one group as provided. */
1802 max_groups[class]--;
1803 p = reg_class_superclasses[class];
1804 while (*p != LIM_REG_CLASSES)
1806 if (group_size [(int) *p] <= group_size [class])
1807 max_groups[(int) *p]--;
1811 /* Indicate both these regs are part of a group. */
1812 SET_HARD_REG_BIT (counted_for_groups, j);
1813 SET_HARD_REG_BIT (counted_for_groups, other);
1817 /* We can't complete a group, so start one. */
1818 #ifdef SMALL_REGISTER_CLASSES
1819 /* Look for a pair neither of which is explicitly used. */
1820 if (SMALL_REGISTER_CLASSES && i == FIRST_PSEUDO_REGISTER)
1821 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1824 j = potential_reload_regs[i];
1825 /* Verify that J+1 is a potential reload reg. */
1826 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1827 if (potential_reload_regs[k] == j + 1)
1829 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1830 && k < FIRST_PSEUDO_REGISTER
1831 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1832 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1833 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1834 && HARD_REGNO_MODE_OK (j, group_mode[class])
1835 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1837 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1)
1838 /* Reject J at this stage
1839 if J+1 was explicitly used. */
1840 && ! regs_explicitly_used[j + 1])
1844 /* Now try any group at all
1845 whose registers are not in bad_spill_regs. */
1846 if (i == FIRST_PSEUDO_REGISTER)
1847 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1850 j = potential_reload_regs[i];
1851 /* Verify that J+1 is a potential reload reg. */
1852 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1853 if (potential_reload_regs[k] == j + 1)
1855 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1856 && k < FIRST_PSEUDO_REGISTER
1857 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1858 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1859 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1860 && HARD_REGNO_MODE_OK (j, group_mode[class])
1861 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1863 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1))
1867 /* I should be the index in potential_reload_regs
1868 of the new reload reg we have found. */
1870 if (i >= FIRST_PSEUDO_REGISTER)
1872 /* There are no groups left to spill. */
1873 spill_failure (max_groups_insn[class]);
1879 |= new_spill_reg (i, class, max_needs, NULL_PTR,
1884 /* For groups of more than 2 registers,
1885 look for a sufficient sequence of unspilled registers,
1886 and spill them all at once. */
1887 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1891 j = potential_reload_regs[i];
1893 && j + group_size[class] <= FIRST_PSEUDO_REGISTER
1894 && HARD_REGNO_MODE_OK (j, group_mode[class]))
1896 /* Check each reg in the sequence. */
1897 for (k = 0; k < group_size[class]; k++)
1898 if (! (spill_reg_order[j + k] < 0
1899 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1900 && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1902 /* We got a full sequence, so spill them all. */
1903 if (k == group_size[class])
1905 register enum reg_class *p;
1906 for (k = 0; k < group_size[class]; k++)
1909 SET_HARD_REG_BIT (counted_for_groups, j + k);
1910 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1911 if (potential_reload_regs[idx] == j + k)
1914 |= new_spill_reg (idx, class,
1915 max_needs, NULL_PTR,
1919 /* We have found one that will complete a group,
1920 so count off one group as provided. */
1921 max_groups[class]--;
1922 p = reg_class_superclasses[class];
1923 while (*p != LIM_REG_CLASSES)
1925 if (group_size [(int) *p]
1926 <= group_size [class])
1927 max_groups[(int) *p]--;
1934 /* We couldn't find any registers for this reload.
1935 Avoid going into an infinite loop. */
1936 if (i >= FIRST_PSEUDO_REGISTER)
1938 /* There are no groups left. */
1939 spill_failure (max_groups_insn[class]);
1946 /* Now similarly satisfy all need for single registers. */
1948 while (max_needs[class] > 0 || max_nongroups[class] > 0)
1950 /* If we spilled enough regs, but they weren't counted
1951 against the non-group need, see if we can count them now.
1952 If so, we can avoid some actual spilling. */
1953 if (max_needs[class] <= 0 && max_nongroups[class] > 0)
1954 for (i = 0; i < n_spills; i++)
1955 if (TEST_HARD_REG_BIT (reg_class_contents[class],
1957 && !TEST_HARD_REG_BIT (counted_for_groups,
1959 && !TEST_HARD_REG_BIT (counted_for_nongroups,
1961 && max_nongroups[class] > 0)
1963 register enum reg_class *p;
1965 SET_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]);
1966 max_nongroups[class]--;
1967 p = reg_class_superclasses[class];
1968 while (*p != LIM_REG_CLASSES)
1969 max_nongroups[(int) *p++]--;
1971 if (max_needs[class] <= 0 && max_nongroups[class] <= 0)
1974 /* Consider the potential reload regs that aren't
1975 yet in use as reload regs, in order of preference.
1976 Find the most preferred one that's in this class. */
1978 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1979 if (potential_reload_regs[i] >= 0
1980 && TEST_HARD_REG_BIT (reg_class_contents[class],
1981 potential_reload_regs[i])
1982 /* If this reg will not be available for groups,
1983 pick one that does not foreclose possible groups.
1984 This is a kludge, and not very general,
1985 but it should be sufficient to make the 386 work,
1986 and the problem should not occur on machines with
1988 && (max_nongroups[class] == 0
1989 || possible_group_p (potential_reload_regs[i], max_groups)))
1992 /* If we couldn't get a register, try to get one even if we
1993 might foreclose possible groups. This may cause problems
1994 later, but that's better than aborting now, since it is
1995 possible that we will, in fact, be able to form the needed
1996 group even with this allocation. */
1998 if (i >= FIRST_PSEUDO_REGISTER
1999 && (asm_noperands (max_needs[class] > 0
2000 ? max_needs_insn[class]
2001 : max_nongroups_insn[class])
2003 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2004 if (potential_reload_regs[i] >= 0
2005 && TEST_HARD_REG_BIT (reg_class_contents[class],
2006 potential_reload_regs[i]))
2009 /* I should be the index in potential_reload_regs
2010 of the new reload reg we have found. */
2012 if (i >= FIRST_PSEUDO_REGISTER)
2014 /* There are no possible registers left to spill. */
2015 spill_failure (max_needs[class] > 0 ? max_needs_insn[class]
2016 : max_nongroups_insn[class]);
2022 |= new_spill_reg (i, class, max_needs, max_nongroups,
2028 /* If global-alloc was run, notify it of any register eliminations we have
2031 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2032 if (ep->can_eliminate)
2033 mark_elimination (ep->from, ep->to);
2035 /* Insert code to save and restore call-clobbered hard regs
2036 around calls. Tell if what mode to use so that we will process
2037 those insns in reload_as_needed if we have to. */
2039 if (caller_save_needed)
2040 save_call_clobbered_regs (num_eliminable ? QImode
2041 : caller_save_spill_class != NO_REGS ? HImode
2044 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
2045 If that insn didn't set the register (i.e., it copied the register to
2046 memory), just delete that insn instead of the equivalencing insn plus
2047 anything now dead. If we call delete_dead_insn on that insn, we may
2048 delete the insn that actually sets the register if the register die
2049 there and that is incorrect. */
2051 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2052 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0
2053 && GET_CODE (reg_equiv_init[i]) != NOTE)
2055 if (reg_set_p (regno_reg_rtx[i], PATTERN (reg_equiv_init[i])))
2056 delete_dead_insn (reg_equiv_init[i]);
2059 PUT_CODE (reg_equiv_init[i], NOTE);
2060 NOTE_SOURCE_FILE (reg_equiv_init[i]) = 0;
2061 NOTE_LINE_NUMBER (reg_equiv_init[i]) = NOTE_INSN_DELETED;
2065 /* Use the reload registers where necessary
2066 by generating move instructions to move the must-be-register
2067 values into or out of the reload registers. */
2069 if (something_needs_reloads || something_needs_elimination
2070 || (caller_save_needed && num_eliminable)
2071 || caller_save_spill_class != NO_REGS)
2072 reload_as_needed (first, global);
2074 /* If we were able to eliminate the frame pointer, show that it is no
2075 longer live at the start of any basic block. If it ls live by
2076 virtue of being in a pseudo, that pseudo will be marked live
2077 and hence the frame pointer will be known to be live via that
2080 if (! frame_pointer_needed)
2081 for (i = 0; i < n_basic_blocks; i++)
2082 basic_block_live_at_start[i][HARD_FRAME_POINTER_REGNUM / REGSET_ELT_BITS]
2083 &= ~ ((REGSET_ELT_TYPE) 1 << (HARD_FRAME_POINTER_REGNUM
2084 % REGSET_ELT_BITS));
2086 /* Come here (with failure set nonzero) if we can't get enough spill regs
2087 and we decide not to abort about it. */
2090 reload_in_progress = 0;
2092 /* Now eliminate all pseudo regs by modifying them into
2093 their equivalent memory references.
2094 The REG-rtx's for the pseudos are modified in place,
2095 so all insns that used to refer to them now refer to memory.
2097 For a reg that has a reg_equiv_address, all those insns
2098 were changed by reloading so that no insns refer to it any longer;
2099 but the DECL_RTL of a variable decl may refer to it,
2100 and if so this causes the debugging info to mention the variable. */
2102 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2106 if (reg_equiv_mem[i])
2108 addr = XEXP (reg_equiv_mem[i], 0);
2109 in_struct = MEM_IN_STRUCT_P (reg_equiv_mem[i]);
2111 if (reg_equiv_address[i])
2112 addr = reg_equiv_address[i];
2115 if (reg_renumber[i] < 0)
2117 rtx reg = regno_reg_rtx[i];
2118 XEXP (reg, 0) = addr;
2119 REG_USERVAR_P (reg) = 0;
2120 MEM_IN_STRUCT_P (reg) = in_struct;
2121 PUT_CODE (reg, MEM);
2123 else if (reg_equiv_mem[i])
2124 XEXP (reg_equiv_mem[i], 0) = addr;
2128 /* Do a very simple CSE pass over just the hard registers. */
2130 reload_cse_regs (first);
2132 #ifdef PRESERVE_DEATH_INFO_REGNO_P
2133 /* Make a pass over all the insns and remove death notes for things that
2134 are no longer registers or no longer die in the insn (e.g., an input
2135 and output pseudo being tied). */
2137 for (insn = first; insn; insn = NEXT_INSN (insn))
2138 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
2142 for (note = REG_NOTES (insn); note; note = next)
2144 next = XEXP (note, 1);
2145 if (REG_NOTE_KIND (note) == REG_DEAD
2146 && (GET_CODE (XEXP (note, 0)) != REG
2147 || reg_set_p (XEXP (note, 0), PATTERN (insn))))
2148 remove_note (insn, note);
2153 /* Indicate that we no longer have known memory locations or constants. */
2154 reg_equiv_constant = 0;
2155 reg_equiv_memory_loc = 0;
2158 free (scratch_list);
2161 free (scratch_block);
2164 CLEAR_HARD_REG_SET (used_spill_regs);
2165 for (i = 0; i < n_spills; i++)
2166 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
2171 /* Nonzero if, after spilling reg REGNO for non-groups,
2172 it will still be possible to find a group if we still need one. */
2175 possible_group_p (regno, max_groups)
2180 int class = (int) NO_REGS;
2182 for (i = 0; i < (int) N_REG_CLASSES; i++)
2183 if (max_groups[i] > 0)
2189 if (class == (int) NO_REGS)
2192 /* Consider each pair of consecutive registers. */
2193 for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
2195 /* Ignore pairs that include reg REGNO. */
2196 if (i == regno || i + 1 == regno)
2199 /* Ignore pairs that are outside the class that needs the group.
2200 ??? Here we fail to handle the case where two different classes
2201 independently need groups. But this never happens with our
2202 current machine descriptions. */
2203 if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
2204 && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
2207 /* A pair of consecutive regs we can still spill does the trick. */
2208 if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
2209 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2210 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
2213 /* A pair of one already spilled and one we can spill does it
2214 provided the one already spilled is not otherwise reserved. */
2215 if (spill_reg_order[i] < 0
2216 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2217 && spill_reg_order[i + 1] >= 0
2218 && ! TEST_HARD_REG_BIT (counted_for_groups, i + 1)
2219 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i + 1))
2221 if (spill_reg_order[i + 1] < 0
2222 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
2223 && spill_reg_order[i] >= 0
2224 && ! TEST_HARD_REG_BIT (counted_for_groups, i)
2225 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i))
2232 /* Count any groups of CLASS that can be formed from the registers recently
2236 count_possible_groups (group_size, group_mode, max_groups, class)
2238 enum machine_mode *group_mode;
2245 /* Now find all consecutive groups of spilled registers
2246 and mark each group off against the need for such groups.
2247 But don't count them against ordinary need, yet. */
2249 if (group_size[class] == 0)
2252 CLEAR_HARD_REG_SET (new);
2254 /* Make a mask of all the regs that are spill regs in class I. */
2255 for (i = 0; i < n_spills; i++)
2256 if (TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i])
2257 && ! TEST_HARD_REG_BIT (counted_for_groups, spill_regs[i])
2258 && ! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
2259 SET_HARD_REG_BIT (new, spill_regs[i]);
2261 /* Find each consecutive group of them. */
2262 for (i = 0; i < FIRST_PSEUDO_REGISTER && max_groups[class] > 0; i++)
2263 if (TEST_HARD_REG_BIT (new, i)
2264 && i + group_size[class] <= FIRST_PSEUDO_REGISTER
2265 && HARD_REGNO_MODE_OK (i, group_mode[class]))
2267 for (j = 1; j < group_size[class]; j++)
2268 if (! TEST_HARD_REG_BIT (new, i + j))
2271 if (j == group_size[class])
2273 /* We found a group. Mark it off against this class's need for
2274 groups, and against each superclass too. */
2275 register enum reg_class *p;
2277 max_groups[class]--;
2278 p = reg_class_superclasses[class];
2279 while (*p != LIM_REG_CLASSES)
2281 if (group_size [(int) *p] <= group_size [class])
2282 max_groups[(int) *p]--;
2286 /* Don't count these registers again. */
2287 for (j = 0; j < group_size[class]; j++)
2288 SET_HARD_REG_BIT (counted_for_groups, i + j);
2291 /* Skip to the last reg in this group. When i is incremented above,
2292 it will then point to the first reg of the next possible group. */
2297 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2298 another mode that needs to be reloaded for the same register class CLASS.
2299 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2300 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2302 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2303 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2304 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2305 causes unnecessary failures on machines requiring alignment of register
2306 groups when the two modes are different sizes, because the larger mode has
2307 more strict alignment rules than the smaller mode. */
2310 modes_equiv_for_class_p (allocate_mode, other_mode, class)
2311 enum machine_mode allocate_mode, other_mode;
2312 enum reg_class class;
2315 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2317 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
2318 && HARD_REGNO_MODE_OK (regno, allocate_mode)
2319 && ! HARD_REGNO_MODE_OK (regno, other_mode))
2325 /* Handle the failure to find a register to spill.
2326 INSN should be one of the insns which needed this particular spill reg. */
2329 spill_failure (insn)
2332 if (asm_noperands (PATTERN (insn)) >= 0)
2333 error_for_asm (insn, "`asm' needs too many reloads");
2335 fatal_insn ("Unable to find a register to spill.", insn);
2338 /* Add a new register to the tables of available spill-registers
2339 (as well as spilling all pseudos allocated to the register).
2340 I is the index of this register in potential_reload_regs.
2341 CLASS is the regclass whose need is being satisfied.
2342 MAX_NEEDS and MAX_NONGROUPS are the vectors of needs,
2343 so that this register can count off against them.
2344 MAX_NONGROUPS is 0 if this register is part of a group.
2345 GLOBAL and DUMPFILE are the same as the args that `reload' got. */
2348 new_spill_reg (i, class, max_needs, max_nongroups, global, dumpfile)
2356 register enum reg_class *p;
2358 int regno = potential_reload_regs[i];
2360 if (i >= FIRST_PSEUDO_REGISTER)
2361 abort (); /* Caller failed to find any register. */
2363 if (fixed_regs[regno] || TEST_HARD_REG_BIT (forbidden_regs, regno))
2364 fatal ("fixed or forbidden register was spilled.\n\
2365 This may be due to a compiler bug or to impossible asm\n\
2366 statements or clauses.");
2368 /* Make reg REGNO an additional reload reg. */
2370 potential_reload_regs[i] = -1;
2371 spill_regs[n_spills] = regno;
2372 spill_reg_order[regno] = n_spills;
2374 fprintf (dumpfile, "Spilling reg %d.\n", spill_regs[n_spills]);
2376 /* Clear off the needs we just satisfied. */
2379 p = reg_class_superclasses[class];
2380 while (*p != LIM_REG_CLASSES)
2381 max_needs[(int) *p++]--;
2383 if (max_nongroups && max_nongroups[class] > 0)
2385 SET_HARD_REG_BIT (counted_for_nongroups, regno);
2386 max_nongroups[class]--;
2387 p = reg_class_superclasses[class];
2388 while (*p != LIM_REG_CLASSES)
2389 max_nongroups[(int) *p++]--;
2392 /* Spill every pseudo reg that was allocated to this reg
2393 or to something that overlaps this reg. */
2395 val = spill_hard_reg (spill_regs[n_spills], global, dumpfile, 0);
2397 /* If there are some registers still to eliminate and this register
2398 wasn't ever used before, additional stack space may have to be
2399 allocated to store this register. Thus, we may have changed the offset
2400 between the stack and frame pointers, so mark that something has changed.
2401 (If new pseudos were spilled, thus requiring more space, VAL would have
2402 been set non-zero by the call to spill_hard_reg above since additional
2403 reloads may be needed in that case.
2405 One might think that we need only set VAL to 1 if this is a call-used
2406 register. However, the set of registers that must be saved by the
2407 prologue is not identical to the call-used set. For example, the
2408 register used by the call insn for the return PC is a call-used register,
2409 but must be saved by the prologue. */
2410 if (num_eliminable && ! regs_ever_live[spill_regs[n_spills]])
2413 regs_ever_live[spill_regs[n_spills]] = 1;
2419 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2420 data that is dead in INSN. */
2423 delete_dead_insn (insn)
2426 rtx prev = prev_real_insn (insn);
2429 /* If the previous insn sets a register that dies in our insn, delete it
2431 if (prev && GET_CODE (PATTERN (prev)) == SET
2432 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
2433 && reg_mentioned_p (prev_dest, PATTERN (insn))
2434 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)))
2435 delete_dead_insn (prev);
2437 PUT_CODE (insn, NOTE);
2438 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2439 NOTE_SOURCE_FILE (insn) = 0;
2442 /* Modify the home of pseudo-reg I.
2443 The new home is present in reg_renumber[I].
2445 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2446 or it may be -1, meaning there is none or it is not relevant.
2447 This is used so that all pseudos spilled from a given hard reg
2448 can share one stack slot. */
2451 alter_reg (i, from_reg)
2455 /* When outputting an inline function, this can happen
2456 for a reg that isn't actually used. */
2457 if (regno_reg_rtx[i] == 0)
2460 /* If the reg got changed to a MEM at rtl-generation time,
2462 if (GET_CODE (regno_reg_rtx[i]) != REG)
2465 /* Modify the reg-rtx to contain the new hard reg
2466 number or else to contain its pseudo reg number. */
2467 REGNO (regno_reg_rtx[i])
2468 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2470 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2471 allocate a stack slot for it. */
2473 if (reg_renumber[i] < 0
2474 && reg_n_refs[i] > 0
2475 && reg_equiv_constant[i] == 0
2476 && reg_equiv_memory_loc[i] == 0)
2479 int inherent_size = PSEUDO_REGNO_BYTES (i);
2480 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2483 /* Each pseudo reg has an inherent size which comes from its own mode,
2484 and a total size which provides room for paradoxical subregs
2485 which refer to the pseudo reg in wider modes.
2487 We can use a slot already allocated if it provides both
2488 enough inherent space and enough total space.
2489 Otherwise, we allocate a new slot, making sure that it has no less
2490 inherent space, and no less total space, then the previous slot. */
2493 /* No known place to spill from => no slot to reuse. */
2494 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
2495 inherent_size == total_size ? 0 : -1);
2496 if (BYTES_BIG_ENDIAN)
2497 /* Cancel the big-endian correction done in assign_stack_local.
2498 Get the address of the beginning of the slot.
2499 This is so we can do a big-endian correction unconditionally
2501 adjust = inherent_size - total_size;
2503 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2505 /* Reuse a stack slot if possible. */
2506 else if (spill_stack_slot[from_reg] != 0
2507 && spill_stack_slot_width[from_reg] >= total_size
2508 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2510 x = spill_stack_slot[from_reg];
2511 /* Allocate a bigger slot. */
2514 /* Compute maximum size needed, both for inherent size
2515 and for total size. */
2516 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2518 if (spill_stack_slot[from_reg])
2520 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2522 mode = GET_MODE (spill_stack_slot[from_reg]);
2523 if (spill_stack_slot_width[from_reg] > total_size)
2524 total_size = spill_stack_slot_width[from_reg];
2526 /* Make a slot with that size. */
2527 x = assign_stack_local (mode, total_size,
2528 inherent_size == total_size ? 0 : -1);
2530 if (BYTES_BIG_ENDIAN)
2532 /* Cancel the big-endian correction done in assign_stack_local.
2533 Get the address of the beginning of the slot.
2534 This is so we can do a big-endian correction unconditionally
2536 adjust = GET_MODE_SIZE (mode) - total_size;
2538 stack_slot = gen_rtx (MEM, mode_for_size (total_size
2541 plus_constant (XEXP (x, 0), adjust));
2543 spill_stack_slot[from_reg] = stack_slot;
2544 spill_stack_slot_width[from_reg] = total_size;
2547 /* On a big endian machine, the "address" of the slot
2548 is the address of the low part that fits its inherent mode. */
2549 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2550 adjust += (total_size - inherent_size);
2552 /* If we have any adjustment to make, or if the stack slot is the
2553 wrong mode, make a new stack slot. */
2554 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2556 x = gen_rtx (MEM, GET_MODE (regno_reg_rtx[i]),
2557 plus_constant (XEXP (x, 0), adjust));
2558 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2561 /* Save the stack slot for later. */
2562 reg_equiv_memory_loc[i] = x;
2566 /* Mark the slots in regs_ever_live for the hard regs
2567 used by pseudo-reg number REGNO. */
2570 mark_home_live (regno)
2573 register int i, lim;
2574 i = reg_renumber[regno];
2577 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2579 regs_ever_live[i++] = 1;
2582 /* Mark the registers used in SCRATCH as being live. */
2585 mark_scratch_live (scratch)
2589 int regno = REGNO (scratch);
2590 int lim = regno + HARD_REGNO_NREGS (regno, GET_MODE (scratch));
2592 for (i = regno; i < lim; i++)
2593 regs_ever_live[i] = 1;
2596 /* This function handles the tracking of elimination offsets around branches.
2598 X is a piece of RTL being scanned.
2600 INSN is the insn that it came from, if any.
2602 INITIAL_P is non-zero if we are to set the offset to be the initial
2603 offset and zero if we are setting the offset of the label to be the
2607 set_label_offsets (x, insn, initial_p)
2612 enum rtx_code code = GET_CODE (x);
2615 struct elim_table *p;
2620 if (LABEL_REF_NONLOCAL_P (x))
2625 /* ... fall through ... */
2628 /* If we know nothing about this label, set the desired offsets. Note
2629 that this sets the offset at a label to be the offset before a label
2630 if we don't know anything about the label. This is not correct for
2631 the label after a BARRIER, but is the best guess we can make. If
2632 we guessed wrong, we will suppress an elimination that might have
2633 been possible had we been able to guess correctly. */
2635 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2637 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2638 offsets_at[CODE_LABEL_NUMBER (x)][i]
2639 = (initial_p ? reg_eliminate[i].initial_offset
2640 : reg_eliminate[i].offset);
2641 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2644 /* Otherwise, if this is the definition of a label and it is
2645 preceded by a BARRIER, set our offsets to the known offset of
2649 && (tem = prev_nonnote_insn (insn)) != 0
2650 && GET_CODE (tem) == BARRIER)
2652 num_not_at_initial_offset = 0;
2653 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2655 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
2656 = offsets_at[CODE_LABEL_NUMBER (x)][i];
2657 if (reg_eliminate[i].can_eliminate
2658 && (reg_eliminate[i].offset
2659 != reg_eliminate[i].initial_offset))
2660 num_not_at_initial_offset++;
2665 /* If neither of the above cases is true, compare each offset
2666 with those previously recorded and suppress any eliminations
2667 where the offsets disagree. */
2669 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2670 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2671 != (initial_p ? reg_eliminate[i].initial_offset
2672 : reg_eliminate[i].offset))
2673 reg_eliminate[i].can_eliminate = 0;
2678 set_label_offsets (PATTERN (insn), insn, initial_p);
2680 /* ... fall through ... */
2684 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2685 and hence must have all eliminations at their initial offsets. */
2686 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2687 if (REG_NOTE_KIND (tem) == REG_LABEL)
2688 set_label_offsets (XEXP (tem, 0), insn, 1);
2693 /* Each of the labels in the address vector must be at their initial
2694 offsets. We want the first first for ADDR_VEC and the second
2695 field for ADDR_DIFF_VEC. */
2697 for (i = 0; i < XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2698 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2703 /* We only care about setting PC. If the source is not RETURN,
2704 IF_THEN_ELSE, or a label, disable any eliminations not at
2705 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2706 isn't one of those possibilities. For branches to a label,
2707 call ourselves recursively.
2709 Note that this can disable elimination unnecessarily when we have
2710 a non-local goto since it will look like a non-constant jump to
2711 someplace in the current function. This isn't a significant
2712 problem since such jumps will normally be when all elimination
2713 pairs are back to their initial offsets. */
2715 if (SET_DEST (x) != pc_rtx)
2718 switch (GET_CODE (SET_SRC (x)))
2725 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2729 tem = XEXP (SET_SRC (x), 1);
2730 if (GET_CODE (tem) == LABEL_REF)
2731 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2732 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2735 tem = XEXP (SET_SRC (x), 2);
2736 if (GET_CODE (tem) == LABEL_REF)
2737 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2738 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2743 /* If we reach here, all eliminations must be at their initial
2744 offset because we are doing a jump to a variable address. */
2745 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2746 if (p->offset != p->initial_offset)
2747 p->can_eliminate = 0;
2751 /* Used for communication between the next two function to properly share
2752 the vector for an ASM_OPERANDS. */
2754 static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec;
2756 /* Scan X and replace any eliminable registers (such as fp) with a
2757 replacement (such as sp), plus an offset.
2759 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2760 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2761 MEM, we are allowed to replace a sum of a register and the constant zero
2762 with the register, which we cannot do outside a MEM. In addition, we need
2763 to record the fact that a register is referenced outside a MEM.
2765 If INSN is an insn, it is the insn containing X. If we replace a REG
2766 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2767 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2768 that the REG is being modified.
2770 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2771 That's used when we eliminate in expressions stored in notes.
2772 This means, do not set ref_outside_mem even if the reference
2775 If we see a modification to a register we know about, take the
2776 appropriate action (see case SET, below).
2778 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2779 replacements done assuming all offsets are at their initial values. If
2780 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2781 encounter, return the actual location so that find_reloads will do
2782 the proper thing. */
2785 eliminate_regs (x, mem_mode, insn, storing)
2787 enum machine_mode mem_mode;
2791 enum rtx_code code = GET_CODE (x);
2792 struct elim_table *ep;
2817 /* First handle the case where we encounter a bare register that
2818 is eliminable. Replace it with a PLUS. */
2819 if (regno < FIRST_PSEUDO_REGISTER)
2821 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2823 if (ep->from_rtx == x && ep->can_eliminate)
2826 /* Refs inside notes don't count for this purpose. */
2827 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2828 || GET_CODE (insn) == INSN_LIST)))
2829 ep->ref_outside_mem = 1;
2830 return plus_constant (ep->to_rtx, ep->previous_offset);
2834 else if (reg_equiv_memory_loc && reg_equiv_memory_loc[regno]
2835 && (reg_equiv_address[regno] || num_not_at_initial_offset))
2837 /* In this case, find_reloads would attempt to either use an
2838 incorrect address (if something is not at its initial offset)
2839 or substitute an replaced address into an insn (which loses
2840 if the offset is changed by some later action). So we simply
2841 return the replaced stack slot (assuming it is changed by
2842 elimination) and ignore the fact that this is actually a
2843 reference to the pseudo. Ensure we make a copy of the
2844 address in case it is shared. */
2845 new = eliminate_regs (reg_equiv_memory_loc[regno],
2847 if (new != reg_equiv_memory_loc[regno])
2849 cannot_omit_stores[regno] = 1;
2850 return copy_rtx (new);
2856 /* If this is the sum of an eliminable register and a constant, rework
2858 if (GET_CODE (XEXP (x, 0)) == REG
2859 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2860 && CONSTANT_P (XEXP (x, 1)))
2862 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2864 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2867 /* Refs inside notes don't count for this purpose. */
2868 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2869 || GET_CODE (insn) == INSN_LIST)))
2870 ep->ref_outside_mem = 1;
2872 /* The only time we want to replace a PLUS with a REG (this
2873 occurs when the constant operand of the PLUS is the negative
2874 of the offset) is when we are inside a MEM. We won't want
2875 to do so at other times because that would change the
2876 structure of the insn in a way that reload can't handle.
2877 We special-case the commonest situation in
2878 eliminate_regs_in_insn, so just replace a PLUS with a
2879 PLUS here, unless inside a MEM. */
2880 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2881 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2884 return gen_rtx (PLUS, Pmode, ep->to_rtx,
2885 plus_constant (XEXP (x, 1),
2886 ep->previous_offset));
2889 /* If the register is not eliminable, we are done since the other
2890 operand is a constant. */
2894 /* If this is part of an address, we want to bring any constant to the
2895 outermost PLUS. We will do this by doing register replacement in
2896 our operands and seeing if a constant shows up in one of them.
2898 We assume here this is part of an address (or a "load address" insn)
2899 since an eliminable register is not likely to appear in any other
2902 If we have (plus (eliminable) (reg)), we want to produce
2903 (plus (plus (replacement) (reg) (const))). If this was part of a
2904 normal add insn, (plus (replacement) (reg)) will be pushed as a
2905 reload. This is the desired action. */
2908 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn, 0);
2909 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn, 0);
2911 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2913 /* If one side is a PLUS and the other side is a pseudo that
2914 didn't get a hard register but has a reg_equiv_constant,
2915 we must replace the constant here since it may no longer
2916 be in the position of any operand. */
2917 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2918 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2919 && reg_renumber[REGNO (new1)] < 0
2920 && reg_equiv_constant != 0
2921 && reg_equiv_constant[REGNO (new1)] != 0)
2922 new1 = reg_equiv_constant[REGNO (new1)];
2923 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2924 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2925 && reg_renumber[REGNO (new0)] < 0
2926 && reg_equiv_constant[REGNO (new0)] != 0)
2927 new0 = reg_equiv_constant[REGNO (new0)];
2929 new = form_sum (new0, new1);
2931 /* As above, if we are not inside a MEM we do not want to
2932 turn a PLUS into something else. We might try to do so here
2933 for an addition of 0 if we aren't optimizing. */
2934 if (! mem_mode && GET_CODE (new) != PLUS)
2935 return gen_rtx (PLUS, GET_MODE (x), new, const0_rtx);
2943 /* If this is the product of an eliminable register and a
2944 constant, apply the distribute law and move the constant out
2945 so that we have (plus (mult ..) ..). This is needed in order
2946 to keep load-address insns valid. This case is pathological.
2947 We ignore the possibility of overflow here. */
2948 if (GET_CODE (XEXP (x, 0)) == REG
2949 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2950 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2951 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2953 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2956 /* Refs inside notes don't count for this purpose. */
2957 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2958 || GET_CODE (insn) == INSN_LIST)))
2959 ep->ref_outside_mem = 1;
2962 plus_constant (gen_rtx (MULT, Pmode, ep->to_rtx, XEXP (x, 1)),
2963 ep->previous_offset * INTVAL (XEXP (x, 1)));
2966 /* ... fall through ... */
2971 case DIV: case UDIV:
2972 case MOD: case UMOD:
2973 case AND: case IOR: case XOR:
2974 case ROTATERT: case ROTATE:
2975 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2977 case GE: case GT: case GEU: case GTU:
2978 case LE: case LT: case LEU: case LTU:
2980 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn, 0);
2982 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn, 0) : 0;
2984 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2985 return gen_rtx (code, GET_MODE (x), new0, new1);
2990 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2993 new = eliminate_regs (XEXP (x, 0), mem_mode, insn, 0);
2994 if (new != XEXP (x, 0))
2995 x = gen_rtx (EXPR_LIST, REG_NOTE_KIND (x), new, XEXP (x, 1));
2998 /* ... fall through ... */
3001 /* Now do eliminations in the rest of the chain. If this was
3002 an EXPR_LIST, this might result in allocating more memory than is
3003 strictly needed, but it simplifies the code. */
3006 new = eliminate_regs (XEXP (x, 1), mem_mode, insn, 0);
3007 if (new != XEXP (x, 1))
3008 return gen_rtx (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
3016 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3017 if (ep->to_rtx == XEXP (x, 0))
3019 int size = GET_MODE_SIZE (mem_mode);
3021 /* If more bytes than MEM_MODE are pushed, account for them. */
3022 #ifdef PUSH_ROUNDING
3023 if (ep->to_rtx == stack_pointer_rtx)
3024 size = PUSH_ROUNDING (size);
3026 if (code == PRE_DEC || code == POST_DEC)
3032 /* Fall through to generic unary operation case. */
3033 case STRICT_LOW_PART:
3035 case SIGN_EXTEND: case ZERO_EXTEND:
3036 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3037 case FLOAT: case FIX:
3038 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3042 new = eliminate_regs (XEXP (x, 0), mem_mode, insn, 0);
3043 if (new != XEXP (x, 0))
3044 return gen_rtx (code, GET_MODE (x), new);
3048 /* Similar to above processing, but preserve SUBREG_WORD.
3049 Convert (subreg (mem)) to (mem) if not paradoxical.
3050 Also, if we have a non-paradoxical (subreg (pseudo)) and the
3051 pseudo didn't get a hard reg, we must replace this with the
3052 eliminated version of the memory location because push_reloads
3053 may do the replacement in certain circumstances. */
3054 if (GET_CODE (SUBREG_REG (x)) == REG
3055 && (GET_MODE_SIZE (GET_MODE (x))
3056 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3057 && reg_equiv_memory_loc != 0
3058 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
3060 new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))],
3063 /* If we didn't change anything, we must retain the pseudo. */
3064 if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))])
3065 new = SUBREG_REG (x);
3068 /* Otherwise, ensure NEW isn't shared in case we have to reload
3070 new = copy_rtx (new);
3072 /* In this case, we must show that the pseudo is used in this
3073 insn so that delete_output_reload will do the right thing. */
3074 if (insn != 0 && GET_CODE (insn) != EXPR_LIST
3075 && GET_CODE (insn) != INSN_LIST)
3076 emit_insn_before (gen_rtx (USE, VOIDmode, SUBREG_REG (x)),
3081 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn, 0);
3083 if (new != XEXP (x, 0))
3085 int x_size = GET_MODE_SIZE (GET_MODE (x));
3086 int new_size = GET_MODE_SIZE (GET_MODE (new));
3088 /* When asked to spill a partial word subreg, we need to go
3089 ahead and spill the whole thing against the possibility
3090 that we reload the whole reg and find garbage at the top. */
3092 && GET_CODE (new) == MEM
3093 && x_size < new_size
3094 && ((x_size + UNITS_PER_WORD-1) / UNITS_PER_WORD
3095 == (new_size + UNITS_PER_WORD-1) / UNITS_PER_WORD))
3097 else if (GET_CODE (new) == MEM
3098 && x_size <= new_size
3099 #ifdef LOAD_EXTEND_OP
3100 /* On these machines we will be reloading what is
3101 inside the SUBREG if it originally was a pseudo and
3102 the inner and outer modes are both a word or
3103 smaller. So leave the SUBREG then. */
3104 && ! (GET_CODE (SUBREG_REG (x)) == REG
3105 && x_size <= UNITS_PER_WORD
3106 && new_size <= UNITS_PER_WORD
3107 && x_size > new_size
3108 && INTEGRAL_MODE_P (GET_MODE (new))
3109 && LOAD_EXTEND_OP (GET_MODE (new)) != NIL)
3113 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
3114 enum machine_mode mode = GET_MODE (x);
3116 if (BYTES_BIG_ENDIAN)
3117 offset += (MIN (UNITS_PER_WORD,
3118 GET_MODE_SIZE (GET_MODE (new)))
3119 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
3121 PUT_MODE (new, mode);
3122 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
3126 return gen_rtx (SUBREG, GET_MODE (x), new, SUBREG_WORD (x));
3132 /* If using a register that is the source of an eliminate we still
3133 think can be performed, note it cannot be performed since we don't
3134 know how this register is used. */
3135 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3136 if (ep->from_rtx == XEXP (x, 0))
3137 ep->can_eliminate = 0;
3139 new = eliminate_regs (XEXP (x, 0), mem_mode, insn, 0);
3140 if (new != XEXP (x, 0))
3141 return gen_rtx (code, GET_MODE (x), new);
3145 /* If clobbering a register that is the replacement register for an
3146 elimination we still think can be performed, note that it cannot
3147 be performed. Otherwise, we need not be concerned about it. */
3148 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3149 if (ep->to_rtx == XEXP (x, 0))
3150 ep->can_eliminate = 0;
3152 new = eliminate_regs (XEXP (x, 0), mem_mode, insn, 0);
3153 if (new != XEXP (x, 0))
3154 return gen_rtx (code, GET_MODE (x), new);
3160 /* Properly handle sharing input and constraint vectors. */
3161 if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec)
3163 /* When we come to a new vector not seen before,
3164 scan all its elements; keep the old vector if none
3165 of them changes; otherwise, make a copy. */
3166 old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x);
3167 temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx));
3168 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3169 temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i),
3172 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3173 if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i))
3176 if (i == ASM_OPERANDS_INPUT_LENGTH (x))
3177 new_asm_operands_vec = old_asm_operands_vec;
3179 new_asm_operands_vec
3180 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec);
3183 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
3184 if (new_asm_operands_vec == old_asm_operands_vec)
3187 new = gen_rtx (ASM_OPERANDS, VOIDmode, ASM_OPERANDS_TEMPLATE (x),
3188 ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
3189 ASM_OPERANDS_OUTPUT_IDX (x), new_asm_operands_vec,
3190 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x),
3191 ASM_OPERANDS_SOURCE_FILE (x),
3192 ASM_OPERANDS_SOURCE_LINE (x));
3193 new->volatil = x->volatil;
3198 /* Check for setting a register that we know about. */
3199 if (GET_CODE (SET_DEST (x)) == REG)
3201 /* See if this is setting the replacement register for an
3204 If DEST is the hard frame pointer, we do nothing because we
3205 assume that all assignments to the frame pointer are for
3206 non-local gotos and are being done at a time when they are valid
3207 and do not disturb anything else. Some machines want to
3208 eliminate a fake argument pointer (or even a fake frame pointer)
3209 with either the real frame or the stack pointer. Assignments to
3210 the hard frame pointer must not prevent this elimination. */
3212 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3214 if (ep->to_rtx == SET_DEST (x)
3215 && SET_DEST (x) != hard_frame_pointer_rtx)
3217 /* If it is being incremented, adjust the offset. Otherwise,
3218 this elimination can't be done. */
3219 rtx src = SET_SRC (x);
3221 if (GET_CODE (src) == PLUS
3222 && XEXP (src, 0) == SET_DEST (x)
3223 && GET_CODE (XEXP (src, 1)) == CONST_INT)
3224 ep->offset -= INTVAL (XEXP (src, 1));
3226 ep->can_eliminate = 0;
3229 /* Now check to see we are assigning to a register that can be
3230 eliminated. If so, it must be as part of a PARALLEL, since we
3231 will not have been called if this is a single SET. So indicate
3232 that we can no longer eliminate this reg. */
3233 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3235 if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate)
3236 ep->can_eliminate = 0;
3239 /* Now avoid the loop below in this common case. */
3241 rtx new0 = eliminate_regs (SET_DEST (x), 0, insn, 1);
3242 rtx new1 = eliminate_regs (SET_SRC (x), 0, insn, 0);
3244 /* If SET_DEST changed from a REG to a MEM and INSN is an insn,
3245 write a CLOBBER insn. */
3246 if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM
3247 && insn != 0 && GET_CODE (insn) != EXPR_LIST
3248 && GET_CODE (insn) != INSN_LIST)
3249 emit_insn_after (gen_rtx (CLOBBER, VOIDmode, SET_DEST (x)), insn);
3251 if (new0 != SET_DEST (x) || new1 != SET_SRC (x))
3252 return gen_rtx (SET, VOIDmode, new0, new1);
3258 /* Our only special processing is to pass the mode of the MEM to our
3259 recursive call and copy the flags. While we are here, handle this
3260 case more efficiently. */
3261 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn, 0);
3262 if (new != XEXP (x, 0))
3264 new = gen_rtx (MEM, GET_MODE (x), new);
3265 new->volatil = x->volatil;
3266 new->unchanging = x->unchanging;
3267 new->in_struct = x->in_struct;
3274 /* Process each of our operands recursively. If any have changed, make a
3276 fmt = GET_RTX_FORMAT (code);
3277 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3281 new = eliminate_regs (XEXP (x, i), mem_mode, insn, 0);
3282 if (new != XEXP (x, i) && ! copied)
3284 rtx new_x = rtx_alloc (code);
3285 bcopy ((char *) x, (char *) new_x,
3286 (sizeof (*new_x) - sizeof (new_x->fld)
3287 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
3293 else if (*fmt == 'E')
3296 for (j = 0; j < XVECLEN (x, i); j++)
3298 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn, 0);
3299 if (new != XVECEXP (x, i, j) && ! copied_vec)
3301 rtvec new_v = gen_rtvec_vv (XVECLEN (x, i),
3305 rtx new_x = rtx_alloc (code);
3306 bcopy ((char *) x, (char *) new_x,
3307 (sizeof (*new_x) - sizeof (new_x->fld)
3308 + (sizeof (new_x->fld[0])
3309 * GET_RTX_LENGTH (code))));
3313 XVEC (x, i) = new_v;
3316 XVECEXP (x, i, j) = new;
3324 /* Scan INSN and eliminate all eliminable registers in it.
3326 If REPLACE is nonzero, do the replacement destructively. Also
3327 delete the insn as dead it if it is setting an eliminable register.
3329 If REPLACE is zero, do all our allocations in reload_obstack.
3331 If no eliminations were done and this insn doesn't require any elimination
3332 processing (these are not identical conditions: it might be updating sp,
3333 but not referencing fp; this needs to be seen during reload_as_needed so
3334 that the offset between fp and sp can be taken into consideration), zero
3335 is returned. Otherwise, 1 is returned. */
3338 eliminate_regs_in_insn (insn, replace)
3342 rtx old_body = PATTERN (insn);
3343 rtx old_set = single_set (insn);
3346 struct elim_table *ep;
3349 push_obstacks (&reload_obstack, &reload_obstack);
3351 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
3352 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3354 /* Check for setting an eliminable register. */
3355 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3356 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3358 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3359 /* If this is setting the frame pointer register to the
3360 hardware frame pointer register and this is an elimination
3361 that will be done (tested above), this insn is really
3362 adjusting the frame pointer downward to compensate for
3363 the adjustment done before a nonlocal goto. */
3364 if (ep->from == FRAME_POINTER_REGNUM
3365 && ep->to == HARD_FRAME_POINTER_REGNUM)
3367 rtx src = SET_SRC (old_set);
3369 rtx prev_insn, prev_set;
3371 if (src == ep->to_rtx)
3373 else if (GET_CODE (src) == PLUS
3374 && GET_CODE (XEXP (src, 0)) == CONST_INT)
3375 offset = INTVAL (XEXP (src, 0)), ok = 1;
3376 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
3377 && (prev_set = single_set (prev_insn)) != 0
3378 && rtx_equal_p (SET_DEST (prev_set), src))
3380 src = SET_SRC (prev_set);
3381 if (src == ep->to_rtx)
3383 else if (GET_CODE (src) == PLUS
3384 && GET_CODE (XEXP (src, 0)) == CONST_INT
3385 && XEXP (src, 1) == ep->to_rtx)
3386 offset = INTVAL (XEXP (src, 0)), ok = 1;
3387 else if (GET_CODE (src) == PLUS
3388 && GET_CODE (XEXP (src, 1)) == CONST_INT
3389 && XEXP (src, 0) == ep->to_rtx)
3390 offset = INTVAL (XEXP (src, 1)), ok = 1;
3398 = plus_constant (ep->to_rtx, offset - ep->offset);
3400 /* First see if this insn remains valid when we
3401 make the change. If not, keep the INSN_CODE
3402 the same and let reload fit it up. */
3403 validate_change (insn, &SET_SRC (old_set), src, 1);
3404 validate_change (insn, &SET_DEST (old_set),
3406 if (! apply_change_group ())
3408 SET_SRC (old_set) = src;
3409 SET_DEST (old_set) = ep->to_rtx;
3419 /* In this case this insn isn't serving a useful purpose. We
3420 will delete it in reload_as_needed once we know that this
3421 elimination is, in fact, being done.
3423 If REPLACE isn't set, we can't delete this insn, but needn't
3424 process it since it won't be used unless something changes. */
3426 delete_dead_insn (insn);
3431 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3432 in the insn is the negative of the offset in FROM. Substitute
3433 (set (reg) (reg to)) for the insn and change its code.
3435 We have to do this here, rather than in eliminate_regs, do that we can
3436 change the insn code. */
3438 if (GET_CODE (SET_SRC (old_set)) == PLUS
3439 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3440 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT)
3441 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3443 if (ep->from_rtx == XEXP (SET_SRC (old_set), 0)
3444 && ep->can_eliminate)
3446 /* We must stop at the first elimination that will be used.
3447 If this one would replace the PLUS with a REG, do it
3448 now. Otherwise, quit the loop and let eliminate_regs
3449 do its normal replacement. */
3450 if (ep->offset == - INTVAL (XEXP (SET_SRC (old_set), 1)))
3452 /* We assume here that we don't need a PARALLEL of
3453 any CLOBBERs for this assignment. There's not
3454 much we can do if we do need it. */
3455 PATTERN (insn) = gen_rtx (SET, VOIDmode,
3456 SET_DEST (old_set), ep->to_rtx);
3457 INSN_CODE (insn) = -1;
3466 old_asm_operands_vec = 0;
3468 /* Replace the body of this insn with a substituted form. If we changed
3469 something, return non-zero.
3471 If we are replacing a body that was a (set X (plus Y Z)), try to
3472 re-recognize the insn. We do this in case we had a simple addition
3473 but now can do this as a load-address. This saves an insn in this
3476 new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX, 0);
3477 if (new_body != old_body)
3479 /* If we aren't replacing things permanently and we changed something,
3480 make another copy to ensure that all the RTL is new. Otherwise
3481 things can go wrong if find_reload swaps commutative operands
3482 and one is inside RTL that has been copied while the other is not. */
3484 /* Don't copy an asm_operands because (1) there's no need and (2)
3485 copy_rtx can't do it properly when there are multiple outputs. */
3486 if (! replace && asm_noperands (old_body) < 0)
3487 new_body = copy_rtx (new_body);
3489 /* If we had a move insn but now we don't, rerecognize it. This will
3490 cause spurious re-recognition if the old move had a PARALLEL since
3491 the new one still will, but we can't call single_set without
3492 having put NEW_BODY into the insn and the re-recognition won't
3493 hurt in this rare case. */
3495 && ((GET_CODE (SET_SRC (old_set)) == REG
3496 && (GET_CODE (new_body) != SET
3497 || GET_CODE (SET_SRC (new_body)) != REG))
3498 /* If this was a load from or store to memory, compare
3499 the MEM in recog_operand to the one in the insn. If they
3500 are not equal, then rerecognize the insn. */
3502 && ((GET_CODE (SET_SRC (old_set)) == MEM
3503 && SET_SRC (old_set) != recog_operand[1])
3504 || (GET_CODE (SET_DEST (old_set)) == MEM
3505 && SET_DEST (old_set) != recog_operand[0])))
3506 /* If this was an add insn before, rerecognize. */
3507 || GET_CODE (SET_SRC (old_set)) == PLUS))
3509 if (! validate_change (insn, &PATTERN (insn), new_body, 0))
3510 /* If recognition fails, store the new body anyway.
3511 It's normal to have recognition failures here
3512 due to bizarre memory addresses; reloading will fix them. */
3513 PATTERN (insn) = new_body;
3516 PATTERN (insn) = new_body;
3521 /* Loop through all elimination pairs. See if any have changed and
3522 recalculate the number not at initial offset.
3524 Compute the maximum offset (minimum offset if the stack does not
3525 grow downward) for each elimination pair.
3527 We also detect a cases where register elimination cannot be done,
3528 namely, if a register would be both changed and referenced outside a MEM
3529 in the resulting insn since such an insn is often undefined and, even if
3530 not, we cannot know what meaning will be given to it. Note that it is
3531 valid to have a register used in an address in an insn that changes it
3532 (presumably with a pre- or post-increment or decrement).
3534 If anything changes, return nonzero. */
3536 num_not_at_initial_offset = 0;
3537 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3539 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3540 ep->can_eliminate = 0;
3542 ep->ref_outside_mem = 0;
3544 if (ep->previous_offset != ep->offset)
3547 ep->previous_offset = ep->offset;
3548 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3549 num_not_at_initial_offset++;
3551 #ifdef STACK_GROWS_DOWNWARD
3552 ep->max_offset = MAX (ep->max_offset, ep->offset);
3554 ep->max_offset = MIN (ep->max_offset, ep->offset);
3559 /* If we changed something, perform elimination in REG_NOTES. This is
3560 needed even when REPLACE is zero because a REG_DEAD note might refer
3561 to a register that we eliminate and could cause a different number
3562 of spill registers to be needed in the final reload pass than in
3564 if (val && REG_NOTES (insn) != 0)
3565 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn), 0);
3573 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3574 replacement we currently believe is valid, mark it as not eliminable if X
3575 modifies DEST in any way other than by adding a constant integer to it.
3577 If DEST is the frame pointer, we do nothing because we assume that
3578 all assignments to the hard frame pointer are nonlocal gotos and are being
3579 done at a time when they are valid and do not disturb anything else.
3580 Some machines want to eliminate a fake argument pointer with either the
3581 frame or stack pointer. Assignments to the hard frame pointer must not
3582 prevent this elimination.
3584 Called via note_stores from reload before starting its passes to scan
3585 the insns of the function. */
3588 mark_not_eliminable (dest, x)
3594 /* A SUBREG of a hard register here is just changing its mode. We should
3595 not see a SUBREG of an eliminable hard register, but check just in
3597 if (GET_CODE (dest) == SUBREG)
3598 dest = SUBREG_REG (dest);
3600 if (dest == hard_frame_pointer_rtx)
3603 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3604 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3605 && (GET_CODE (x) != SET
3606 || GET_CODE (SET_SRC (x)) != PLUS
3607 || XEXP (SET_SRC (x), 0) != dest
3608 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3610 reg_eliminate[i].can_eliminate_previous
3611 = reg_eliminate[i].can_eliminate = 0;
3616 /* Kick all pseudos out of hard register REGNO.
3617 If GLOBAL is nonzero, try to find someplace else to put them.
3618 If DUMPFILE is nonzero, log actions taken on that file.
3620 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3621 because we found we can't eliminate some register. In the case, no pseudos
3622 are allowed to be in the register, even if they are only in a block that
3623 doesn't require spill registers, unlike the case when we are spilling this
3624 hard reg to produce another spill register.
3626 Return nonzero if any pseudos needed to be kicked out. */
3629 spill_hard_reg (regno, global, dumpfile, cant_eliminate)
3635 enum reg_class class = REGNO_REG_CLASS (regno);
3636 int something_changed = 0;
3639 SET_HARD_REG_BIT (forbidden_regs, regno);
3642 regs_ever_live[regno] = 1;
3644 /* Spill every pseudo reg that was allocated to this reg
3645 or to something that overlaps this reg. */
3647 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3648 if (reg_renumber[i] >= 0
3649 && reg_renumber[i] <= regno
3651 + HARD_REGNO_NREGS (reg_renumber[i],
3652 PSEUDO_REGNO_MODE (i))
3655 /* If this register belongs solely to a basic block which needed no
3656 spilling of any class that this register is contained in,
3657 leave it be, unless we are spilling this register because
3658 it was a hard register that can't be eliminated. */
3660 if (! cant_eliminate
3661 && basic_block_needs[0]
3662 && reg_basic_block[i] >= 0
3663 && basic_block_needs[(int) class][reg_basic_block[i]] == 0)
3667 for (p = reg_class_superclasses[(int) class];
3668 *p != LIM_REG_CLASSES; p++)
3669 if (basic_block_needs[(int) *p][reg_basic_block[i]] > 0)
3672 if (*p == LIM_REG_CLASSES)
3676 /* Mark it as no longer having a hard register home. */
3677 reg_renumber[i] = -1;
3678 /* We will need to scan everything again. */
3679 something_changed = 1;
3681 retry_global_alloc (i, forbidden_regs);
3683 alter_reg (i, regno);
3686 if (reg_renumber[i] == -1)
3687 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3689 fprintf (dumpfile, " Register %d now in %d.\n\n",
3690 i, reg_renumber[i]);
3693 for (i = 0; i < scratch_list_length; i++)
3695 if (scratch_list[i] && REGNO (scratch_list[i]) == regno)
3697 if (! cant_eliminate && basic_block_needs[0]
3698 && ! basic_block_needs[(int) class][scratch_block[i]])
3702 for (p = reg_class_superclasses[(int) class];
3703 *p != LIM_REG_CLASSES; p++)
3704 if (basic_block_needs[(int) *p][scratch_block[i]] > 0)
3707 if (*p == LIM_REG_CLASSES)
3710 PUT_CODE (scratch_list[i], SCRATCH);
3711 scratch_list[i] = 0;
3712 something_changed = 1;
3717 return something_changed;
3720 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3721 Also mark any hard registers used to store user variables as
3722 forbidden from being used for spill registers. */
3725 scan_paradoxical_subregs (x)
3730 register enum rtx_code code = GET_CODE (x);
3735 #ifdef SMALL_REGISTER_CLASSES
3736 if (SMALL_REGISTER_CLASSES
3737 && REGNO (x) < FIRST_PSEUDO_REGISTER
3738 && REG_USERVAR_P (x))
3739 SET_HARD_REG_BIT (forbidden_regs, REGNO (x));
3755 if (GET_CODE (SUBREG_REG (x)) == REG
3756 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3757 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3758 = GET_MODE_SIZE (GET_MODE (x));
3762 fmt = GET_RTX_FORMAT (code);
3763 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3766 scan_paradoxical_subregs (XEXP (x, i));
3767 else if (fmt[i] == 'E')
3770 for (j = XVECLEN (x, i) - 1; j >=0; j--)
3771 scan_paradoxical_subregs (XVECEXP (x, i, j));
3777 hard_reg_use_compare (p1p, p2p)
3778 const GENERIC_PTR p1p;
3779 const GENERIC_PTR p2p;
3781 struct hard_reg_n_uses *p1 = (struct hard_reg_n_uses *)p1p,
3782 *p2 = (struct hard_reg_n_uses *)p2p;
3783 int tem = p1->uses - p2->uses;
3784 if (tem != 0) return tem;
3785 /* If regs are equally good, sort by regno,
3786 so that the results of qsort leave nothing to chance. */
3787 return p1->regno - p2->regno;
3790 /* Choose the order to consider regs for use as reload registers
3791 based on how much trouble would be caused by spilling one.
3792 Store them in order of decreasing preference in potential_reload_regs. */
3795 order_regs_for_reload (global)
3802 struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
3804 CLEAR_HARD_REG_SET (bad_spill_regs);
3806 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3807 potential_reload_regs[i] = -1;
3809 /* Count number of uses of each hard reg by pseudo regs allocated to it
3810 and then order them by decreasing use. */
3812 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3814 hard_reg_n_uses[i].uses = 0;
3815 hard_reg_n_uses[i].regno = i;
3818 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3820 int regno = reg_renumber[i];
3823 int lim = regno + HARD_REGNO_NREGS (regno, PSEUDO_REGNO_MODE (i));
3826 /* If allocated by local-alloc, show more uses since
3827 we're not going to be able to reallocate it, but
3828 we might if allocated by global alloc. */
3829 if (global && reg_allocno[i] < 0)
3830 hard_reg_n_uses[regno].uses += (reg_n_refs[i] + 1) / 2;
3832 hard_reg_n_uses[regno++].uses += reg_n_refs[i];
3835 large += reg_n_refs[i];
3838 /* Now fixed registers (which cannot safely be used for reloading)
3839 get a very high use count so they will be considered least desirable.
3840 Registers used explicitly in the rtl code are almost as bad. */
3842 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3846 hard_reg_n_uses[i].uses += 2 * large + 2;
3847 SET_HARD_REG_BIT (bad_spill_regs, i);
3849 else if (regs_explicitly_used[i])
3851 hard_reg_n_uses[i].uses += large + 1;
3852 /* ??? We are doing this here because of the potential that
3853 bad code may be generated if a register explicitly used in
3854 an insn was used as a spill register for that insn. But
3855 not using these are spill registers may lose on some machine.
3856 We'll have to see how this works out. */
3857 #ifdef SMALL_REGISTER_CLASSES
3858 if (! SMALL_REGISTER_CLASSES)
3860 SET_HARD_REG_BIT (bad_spill_regs, i);
3863 hard_reg_n_uses[HARD_FRAME_POINTER_REGNUM].uses += 2 * large + 2;
3864 SET_HARD_REG_BIT (bad_spill_regs, HARD_FRAME_POINTER_REGNUM);
3866 #ifdef ELIMINABLE_REGS
3867 /* If registers other than the frame pointer are eliminable, mark them as
3869 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3871 hard_reg_n_uses[reg_eliminate[i].from].uses += 2 * large + 2;
3872 SET_HARD_REG_BIT (bad_spill_regs, reg_eliminate[i].from);
3876 /* Prefer registers not so far used, for use in temporary loading.
3877 Among them, if REG_ALLOC_ORDER is defined, use that order.
3878 Otherwise, prefer registers not preserved by calls. */
3880 #ifdef REG_ALLOC_ORDER
3881 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3883 int regno = reg_alloc_order[i];
3885 if (hard_reg_n_uses[regno].uses == 0)
3886 potential_reload_regs[o++] = regno;
3889 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3891 if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i])
3892 potential_reload_regs[o++] = i;
3894 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3896 if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i])
3897 potential_reload_regs[o++] = i;
3901 qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
3902 sizeof hard_reg_n_uses[0], hard_reg_use_compare);
3904 /* Now add the regs that are already used,
3905 preferring those used less often. The fixed and otherwise forbidden
3906 registers will be at the end of this list. */
3908 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3909 if (hard_reg_n_uses[i].uses != 0)
3910 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
3913 /* Used in reload_as_needed to sort the spilled regs. */
3916 compare_spill_regs (r1p, r2p)
3917 const GENERIC_PTR r1p;
3918 const GENERIC_PTR r2p;
3920 short r1 = *(short *)r1p, r2 = *(short *)r2p;
3924 /* Reload pseudo-registers into hard regs around each insn as needed.
3925 Additional register load insns are output before the insn that needs it
3926 and perhaps store insns after insns that modify the reloaded pseudo reg.
3928 reg_last_reload_reg and reg_reloaded_contents keep track of
3929 which registers are already available in reload registers.
3930 We update these for the reloads that we perform,
3931 as the insns are scanned. */
3934 reload_as_needed (first, live_known)
3944 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
3945 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
3946 reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
3947 bzero ((char *) reg_last_reload_reg, max_regno * sizeof (rtx));
3948 reg_has_output_reload = (char *) alloca (max_regno);
3949 for (i = 0; i < n_spills; i++)
3951 reg_reloaded_contents[i] = -1;
3952 reg_reloaded_insn[i] = 0;
3955 /* Reset all offsets on eliminable registers to their initial values. */
3956 #ifdef ELIMINABLE_REGS
3957 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3959 INITIAL_ELIMINATION_OFFSET (reg_eliminate[i].from, reg_eliminate[i].to,
3960 reg_eliminate[i].initial_offset);
3961 reg_eliminate[i].previous_offset
3962 = reg_eliminate[i].offset = reg_eliminate[i].initial_offset;
3965 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
3966 reg_eliminate[0].previous_offset
3967 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
3970 num_not_at_initial_offset = 0;
3972 /* Order the spilled regs, so that allocate_reload_regs can guarantee to
3973 pack registers with group needs. */
3976 qsort (spill_regs, n_spills, sizeof (short), compare_spill_regs);
3977 for (i = 0; i < n_spills; i++)
3978 spill_reg_order[spill_regs[i]] = i;
3981 for (insn = first; insn;)
3983 register rtx next = NEXT_INSN (insn);
3985 /* Notice when we move to a new basic block. */
3986 if (live_known && this_block + 1 < n_basic_blocks
3987 && insn == basic_block_head[this_block+1])
3990 /* If we pass a label, copy the offsets from the label information
3991 into the current offsets of each elimination. */
3992 if (GET_CODE (insn) == CODE_LABEL)
3994 num_not_at_initial_offset = 0;
3995 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3997 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
3998 = offsets_at[CODE_LABEL_NUMBER (insn)][i];
3999 if (reg_eliminate[i].can_eliminate
4000 && (reg_eliminate[i].offset
4001 != reg_eliminate[i].initial_offset))
4002 num_not_at_initial_offset++;
4006 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
4008 rtx avoid_return_reg = 0;
4009 rtx oldpat = PATTERN (insn);
4011 #ifdef SMALL_REGISTER_CLASSES
4012 /* Set avoid_return_reg if this is an insn
4013 that might use the value of a function call. */
4014 if (SMALL_REGISTER_CLASSES && GET_CODE (insn) == CALL_INSN)
4016 if (GET_CODE (PATTERN (insn)) == SET)
4017 after_call = SET_DEST (PATTERN (insn));
4018 else if (GET_CODE (PATTERN (insn)) == PARALLEL
4019 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
4020 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
4024 else if (SMALL_REGISTER_CLASSES
4026 && !(GET_CODE (PATTERN (insn)) == SET
4027 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
4029 if (reg_referenced_p (after_call, PATTERN (insn)))
4030 avoid_return_reg = after_call;
4033 #endif /* SMALL_REGISTER_CLASSES */
4035 /* If this is a USE and CLOBBER of a MEM, ensure that any
4036 references to eliminable registers have been removed. */
4038 if ((GET_CODE (PATTERN (insn)) == USE
4039 || GET_CODE (PATTERN (insn)) == CLOBBER)
4040 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
4041 XEXP (XEXP (PATTERN (insn), 0), 0)
4042 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4043 GET_MODE (XEXP (PATTERN (insn), 0)),
4046 /* If we need to do register elimination processing, do so.
4047 This might delete the insn, in which case we are done. */
4048 if (num_eliminable && GET_MODE (insn) == QImode)
4050 eliminate_regs_in_insn (insn, 1);
4051 if (GET_CODE (insn) == NOTE)
4058 if (GET_MODE (insn) == VOIDmode)
4060 /* First find the pseudo regs that must be reloaded for this insn.
4061 This info is returned in the tables reload_... (see reload.h).
4062 Also modify the body of INSN by substituting RELOAD
4063 rtx's for those pseudo regs. */
4066 bzero (reg_has_output_reload, max_regno);
4067 CLEAR_HARD_REG_SET (reg_is_output_reload);
4069 find_reloads (insn, 1, spill_indirect_levels, live_known,
4075 rtx prev = PREV_INSN (insn), next = NEXT_INSN (insn);
4079 /* If this block has not had spilling done for a
4080 particular clas and we have any non-optionals that need a
4081 spill reg in that class, abort. */
4083 for (class = 0; class < N_REG_CLASSES; class++)
4084 if (basic_block_needs[class] != 0
4085 && basic_block_needs[class][this_block] == 0)
4086 for (i = 0; i < n_reloads; i++)
4087 if (class == (int) reload_reg_class[i]
4088 && reload_reg_rtx[i] == 0
4089 && ! reload_optional[i]
4090 && (reload_in[i] != 0 || reload_out[i] != 0
4091 || reload_secondary_p[i] != 0))
4092 fatal_insn ("Non-optional registers need a spill register", insn);
4094 /* Now compute which reload regs to reload them into. Perhaps
4095 reusing reload regs from previous insns, or else output
4096 load insns to reload them. Maybe output store insns too.
4097 Record the choices of reload reg in reload_reg_rtx. */
4098 choose_reload_regs (insn, avoid_return_reg);
4100 #ifdef SMALL_REGISTER_CLASSES
4101 /* Merge any reloads that we didn't combine for fear of
4102 increasing the number of spill registers needed but now
4103 discover can be safely merged. */
4104 if (SMALL_REGISTER_CLASSES)
4105 merge_assigned_reloads (insn);
4108 /* Generate the insns to reload operands into or out of
4109 their reload regs. */
4110 emit_reload_insns (insn);
4112 /* Substitute the chosen reload regs from reload_reg_rtx
4113 into the insn's body (or perhaps into the bodies of other
4114 load and store insn that we just made for reloading
4115 and that we moved the structure into). */
4118 /* If this was an ASM, make sure that all the reload insns
4119 we have generated are valid. If not, give an error
4122 if (asm_noperands (PATTERN (insn)) >= 0)
4123 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4124 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
4125 && (recog_memoized (p) < 0
4126 || (insn_extract (p),
4127 ! constrain_operands (INSN_CODE (p), 1))))
4129 error_for_asm (insn,
4130 "`asm' operand requires impossible reload");
4132 NOTE_SOURCE_FILE (p) = 0;
4133 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
4136 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4137 is no longer validly lying around to save a future reload.
4138 Note that this does not detect pseudos that were reloaded
4139 for this insn in order to be stored in
4140 (obeying register constraints). That is correct; such reload
4141 registers ARE still valid. */
4142 note_stores (oldpat, forget_old_reloads_1);
4144 /* There may have been CLOBBER insns placed after INSN. So scan
4145 between INSN and NEXT and use them to forget old reloads. */
4146 for (x = NEXT_INSN (insn); x != next; x = NEXT_INSN (x))
4147 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
4148 note_stores (PATTERN (x), forget_old_reloads_1);
4151 /* Likewise for regs altered by auto-increment in this insn.
4152 But note that the reg-notes are not changed by reloading:
4153 they still contain the pseudo-regs, not the spill regs. */
4154 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4155 if (REG_NOTE_KIND (x) == REG_INC)
4157 /* See if this pseudo reg was reloaded in this insn.
4158 If so, its last-reload info is still valid
4159 because it is based on this insn's reload. */
4160 for (i = 0; i < n_reloads; i++)
4161 if (reload_out[i] == XEXP (x, 0))
4165 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX);
4169 /* A reload reg's contents are unknown after a label. */
4170 if (GET_CODE (insn) == CODE_LABEL)
4171 for (i = 0; i < n_spills; i++)
4173 reg_reloaded_contents[i] = -1;
4174 reg_reloaded_insn[i] = 0;
4177 /* Don't assume a reload reg is still good after a call insn
4178 if it is a call-used reg. */
4179 else if (GET_CODE (insn) == CALL_INSN)
4180 for (i = 0; i < n_spills; i++)
4181 if (call_used_regs[spill_regs[i]])
4183 reg_reloaded_contents[i] = -1;
4184 reg_reloaded_insn[i] = 0;
4187 /* In case registers overlap, allow certain insns to invalidate
4188 particular hard registers. */
4190 #ifdef INSN_CLOBBERS_REGNO_P
4191 for (i = 0 ; i < n_spills ; i++)
4192 if (INSN_CLOBBERS_REGNO_P (insn, spill_regs[i]))
4194 reg_reloaded_contents[i] = -1;
4195 reg_reloaded_insn[i] = 0;
4207 /* Discard all record of any value reloaded from X,
4208 or reloaded in X from someplace else;
4209 unless X is an output reload reg of the current insn.
4211 X may be a hard reg (the reload reg)
4212 or it may be a pseudo reg that was reloaded from. */
4215 forget_old_reloads_1 (x, ignored)
4223 /* note_stores does give us subregs of hard regs. */
4224 while (GET_CODE (x) == SUBREG)
4226 offset += SUBREG_WORD (x);
4230 if (GET_CODE (x) != REG)
4233 regno = REGNO (x) + offset;
4235 if (regno >= FIRST_PSEUDO_REGISTER)
4240 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4241 /* Storing into a spilled-reg invalidates its contents.
4242 This can happen if a block-local pseudo is allocated to that reg
4243 and it wasn't spilled because this block's total need is 0.
4244 Then some insn might have an optional reload and use this reg. */
4245 for (i = 0; i < nr; i++)
4246 if (spill_reg_order[regno + i] >= 0
4247 /* But don't do this if the reg actually serves as an output
4248 reload reg in the current instruction. */
4250 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i)))
4252 reg_reloaded_contents[spill_reg_order[regno + i]] = -1;
4253 reg_reloaded_insn[spill_reg_order[regno + i]] = 0;
4257 /* Since value of X has changed,
4258 forget any value previously copied from it. */
4261 /* But don't forget a copy if this is the output reload
4262 that establishes the copy's validity. */
4263 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4264 reg_last_reload_reg[regno + nr] = 0;
4267 /* For each reload, the mode of the reload register. */
4268 static enum machine_mode reload_mode[MAX_RELOADS];
4270 /* For each reload, the largest number of registers it will require. */
4271 static int reload_nregs[MAX_RELOADS];
4273 /* Comparison function for qsort to decide which of two reloads
4274 should be handled first. *P1 and *P2 are the reload numbers. */
4277 reload_reg_class_lower (r1p, r2p)
4278 const GENERIC_PTR r1p;
4279 const GENERIC_PTR r2p;
4281 register int r1 = *(short *)r1p, r2 = *(short *)r2p;
4284 /* Consider required reloads before optional ones. */
4285 t = reload_optional[r1] - reload_optional[r2];
4289 /* Count all solitary classes before non-solitary ones. */
4290 t = ((reg_class_size[(int) reload_reg_class[r2]] == 1)
4291 - (reg_class_size[(int) reload_reg_class[r1]] == 1));
4295 /* Aside from solitaires, consider all multi-reg groups first. */
4296 t = reload_nregs[r2] - reload_nregs[r1];
4300 /* Consider reloads in order of increasing reg-class number. */
4301 t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2];
4305 /* If reloads are equally urgent, sort by reload number,
4306 so that the results of qsort leave nothing to chance. */
4310 /* The following HARD_REG_SETs indicate when each hard register is
4311 used for a reload of various parts of the current insn. */
4313 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4314 static HARD_REG_SET reload_reg_used;
4315 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4316 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4317 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4318 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4319 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4320 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4321 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4322 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4323 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4324 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4325 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4326 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4327 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4328 static HARD_REG_SET reload_reg_used_in_op_addr;
4329 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4330 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4331 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4332 static HARD_REG_SET reload_reg_used_in_insn;
4333 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4334 static HARD_REG_SET reload_reg_used_in_other_addr;
4336 /* If reg is in use as a reload reg for any sort of reload. */
4337 static HARD_REG_SET reload_reg_used_at_all;
4339 /* If reg is use as an inherited reload. We just mark the first register
4341 static HARD_REG_SET reload_reg_used_for_inherit;
4343 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4344 TYPE. MODE is used to indicate how many consecutive regs are
4348 mark_reload_reg_in_use (regno, opnum, type, mode)
4351 enum reload_type type;
4352 enum machine_mode mode;
4354 int nregs = HARD_REGNO_NREGS (regno, mode);
4357 for (i = regno; i < nregs + regno; i++)
4362 SET_HARD_REG_BIT (reload_reg_used, i);
4365 case RELOAD_FOR_INPUT_ADDRESS:
4366 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4369 case RELOAD_FOR_INPADDR_ADDRESS:
4370 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4373 case RELOAD_FOR_OUTPUT_ADDRESS:
4374 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4377 case RELOAD_FOR_OUTADDR_ADDRESS:
4378 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4381 case RELOAD_FOR_OPERAND_ADDRESS:
4382 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4385 case RELOAD_FOR_OPADDR_ADDR:
4386 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4389 case RELOAD_FOR_OTHER_ADDRESS:
4390 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4393 case RELOAD_FOR_INPUT:
4394 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4397 case RELOAD_FOR_OUTPUT:
4398 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4401 case RELOAD_FOR_INSN:
4402 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4406 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4410 /* Similarly, but show REGNO is no longer in use for a reload. */
4413 clear_reload_reg_in_use (regno, opnum, type, mode)
4416 enum reload_type type;
4417 enum machine_mode mode;
4419 int nregs = HARD_REGNO_NREGS (regno, mode);
4422 for (i = regno; i < nregs + regno; i++)
4427 CLEAR_HARD_REG_BIT (reload_reg_used, i);
4430 case RELOAD_FOR_INPUT_ADDRESS:
4431 CLEAR_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4434 case RELOAD_FOR_INPADDR_ADDRESS:
4435 CLEAR_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4438 case RELOAD_FOR_OUTPUT_ADDRESS:
4439 CLEAR_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4442 case RELOAD_FOR_OUTADDR_ADDRESS:
4443 CLEAR_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4446 case RELOAD_FOR_OPERAND_ADDRESS:
4447 CLEAR_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4450 case RELOAD_FOR_OPADDR_ADDR:
4451 CLEAR_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4454 case RELOAD_FOR_OTHER_ADDRESS:
4455 CLEAR_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4458 case RELOAD_FOR_INPUT:
4459 CLEAR_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4462 case RELOAD_FOR_OUTPUT:
4463 CLEAR_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4466 case RELOAD_FOR_INSN:
4467 CLEAR_HARD_REG_BIT (reload_reg_used_in_insn, i);
4473 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4474 specified by OPNUM and TYPE. */
4477 reload_reg_free_p (regno, opnum, type)
4480 enum reload_type type;
4484 /* In use for a RELOAD_OTHER means it's not available for anything. */
4485 if (TEST_HARD_REG_BIT (reload_reg_used, regno))
4491 /* In use for anything means we can't use it for RELOAD_OTHER. */
4492 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4493 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4494 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4497 for (i = 0; i < reload_n_operands; i++)
4498 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4499 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4500 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4501 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4502 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4503 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4508 case RELOAD_FOR_INPUT:
4509 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4510 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4513 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4516 /* If it is used for some other input, can't use it. */
4517 for (i = 0; i < reload_n_operands; i++)
4518 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4521 /* If it is used in a later operand's address, can't use it. */
4522 for (i = opnum + 1; i < reload_n_operands; i++)
4523 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4524 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4529 case RELOAD_FOR_INPUT_ADDRESS:
4530 /* Can't use a register if it is used for an input address for this
4531 operand or used as an input in an earlier one. */
4532 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4533 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4536 for (i = 0; i < opnum; i++)
4537 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4542 case RELOAD_FOR_INPADDR_ADDRESS:
4543 /* Can't use a register if it is used for an input address
4544 address for this operand or used as an input in an earlier
4546 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4549 for (i = 0; i < opnum; i++)
4550 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4555 case RELOAD_FOR_OUTPUT_ADDRESS:
4556 /* Can't use a register if it is used for an output address for this
4557 operand or used as an output in this or a later operand. */
4558 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4561 for (i = opnum; i < reload_n_operands; i++)
4562 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4567 case RELOAD_FOR_OUTADDR_ADDRESS:
4568 /* Can't use a register if it is used for an output address
4569 address for this operand or used as an output in this or a
4571 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4574 for (i = opnum; i < reload_n_operands; i++)
4575 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4580 case RELOAD_FOR_OPERAND_ADDRESS:
4581 for (i = 0; i < reload_n_operands; i++)
4582 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4585 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4586 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4588 case RELOAD_FOR_OPADDR_ADDR:
4589 for (i = 0; i < reload_n_operands; i++)
4590 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4593 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4595 case RELOAD_FOR_OUTPUT:
4596 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4597 outputs, or an operand address for this or an earlier output. */
4598 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4601 for (i = 0; i < reload_n_operands; i++)
4602 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4605 for (i = 0; i <= opnum; i++)
4606 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4607 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4612 case RELOAD_FOR_INSN:
4613 for (i = 0; i < reload_n_operands; i++)
4614 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4615 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4618 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4619 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4621 case RELOAD_FOR_OTHER_ADDRESS:
4622 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4627 /* Return 1 if the value in reload reg REGNO, as used by a reload
4628 needed for the part of the insn specified by OPNUM and TYPE,
4629 is not in use for a reload in any prior part of the insn.
4631 We can assume that the reload reg was already tested for availability
4632 at the time it is needed, and we should not check this again,
4633 in case the reg has already been marked in use. */
4636 reload_reg_free_before_p (regno, opnum, type)
4639 enum reload_type type;
4645 case RELOAD_FOR_OTHER_ADDRESS:
4646 /* These always come first. */
4650 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4652 /* If this use is for part of the insn,
4653 check the reg is not in use for any prior part. It is tempting
4654 to try to do this by falling through from objecs that occur
4655 later in the insn to ones that occur earlier, but that will not
4656 correctly take into account the fact that here we MUST ignore
4657 things that would prevent the register from being allocated in
4658 the first place, since we know that it was allocated. */
4660 case RELOAD_FOR_OUTPUT_ADDRESS:
4661 case RELOAD_FOR_OUTADDR_ADDRESS:
4662 /* Earlier reloads are for earlier outputs or their addresses,
4663 any RELOAD_FOR_INSN reloads, any inputs or their addresses, or any
4664 RELOAD_FOR_OTHER_ADDRESS reloads (we know it can't conflict with
4666 for (i = 0; i < opnum; i++)
4667 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4668 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4669 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4672 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4675 for (i = 0; i < reload_n_operands; i++)
4676 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4677 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4678 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4681 return (! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4682 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4683 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4685 case RELOAD_FOR_OUTPUT:
4686 /* This can't be used in the output address for this operand and
4687 anything that can't be used for it, except that we've already
4688 tested for RELOAD_FOR_INSN objects. */
4690 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno)
4691 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4694 for (i = 0; i < opnum; i++)
4695 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4696 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4697 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4700 for (i = 0; i < reload_n_operands; i++)
4701 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4702 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4703 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4704 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4707 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4709 case RELOAD_FOR_OPERAND_ADDRESS:
4710 /* Earlier reloads include RELOAD_FOR_OPADDR_ADDR reloads. */
4711 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4714 /* ... fall through ... */
4716 case RELOAD_FOR_OPADDR_ADDR:
4717 case RELOAD_FOR_INSN:
4718 /* These can't conflict with inputs, or each other, so all we have to
4719 test is input addresses and the addresses of OTHER items. */
4721 for (i = 0; i < reload_n_operands; i++)
4722 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4723 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4726 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4728 case RELOAD_FOR_INPUT:
4729 /* The only things earlier are the address for this and
4730 earlier inputs, other inputs (which we know we don't conflict
4731 with), and addresses of RELOAD_OTHER objects. */
4733 for (i = 0; i <= opnum; i++)
4734 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4735 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4738 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4740 case RELOAD_FOR_INPUT_ADDRESS:
4741 case RELOAD_FOR_INPADDR_ADDRESS:
4742 /* Similarly, all we have to check is for use in earlier inputs'
4744 for (i = 0; i < opnum; i++)
4745 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4746 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4749 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4754 /* Return 1 if the value in reload reg REGNO, as used by a reload
4755 needed for the part of the insn specified by OPNUM and TYPE,
4756 is still available in REGNO at the end of the insn.
4758 We can assume that the reload reg was already tested for availability
4759 at the time it is needed, and we should not check this again,
4760 in case the reg has already been marked in use. */
4763 reload_reg_reaches_end_p (regno, opnum, type)
4766 enum reload_type type;
4773 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4774 its value must reach the end. */
4777 /* If this use is for part of the insn,
4778 its value reaches if no subsequent part uses the same register.
4779 Just like the above function, don't try to do this with lots
4782 case RELOAD_FOR_OTHER_ADDRESS:
4783 /* Here we check for everything else, since these don't conflict
4784 with anything else and everything comes later. */
4786 for (i = 0; i < reload_n_operands; i++)
4787 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4788 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4789 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4790 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4791 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4792 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4795 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4796 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4797 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4799 case RELOAD_FOR_INPUT_ADDRESS:
4800 case RELOAD_FOR_INPADDR_ADDRESS:
4801 /* Similar, except that we check only for this and subsequent inputs
4802 and the address of only subsequent inputs and we do not need
4803 to check for RELOAD_OTHER objects since they are known not to
4806 for (i = opnum; i < reload_n_operands; i++)
4807 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4810 for (i = opnum + 1; i < reload_n_operands; i++)
4811 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4812 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4815 for (i = 0; i < reload_n_operands; i++)
4816 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4817 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4818 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4821 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4824 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4825 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4827 case RELOAD_FOR_INPUT:
4828 /* Similar to input address, except we start at the next operand for
4829 both input and input address and we do not check for
4830 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4833 for (i = opnum + 1; i < reload_n_operands; i++)
4834 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4835 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4836 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4839 /* ... fall through ... */
4841 case RELOAD_FOR_OPERAND_ADDRESS:
4842 /* Check outputs and their addresses. */
4844 for (i = 0; i < reload_n_operands; i++)
4845 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4846 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4847 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4852 case RELOAD_FOR_OPADDR_ADDR:
4853 for (i = 0; i < reload_n_operands; i++)
4854 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4855 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4856 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4859 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4860 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4862 case RELOAD_FOR_INSN:
4863 /* These conflict with other outputs with RELOAD_OTHER. So
4864 we need only check for output addresses. */
4868 /* ... fall through ... */
4870 case RELOAD_FOR_OUTPUT:
4871 case RELOAD_FOR_OUTPUT_ADDRESS:
4872 case RELOAD_FOR_OUTADDR_ADDRESS:
4873 /* We already know these can't conflict with a later output. So the
4874 only thing to check are later output addresses. */
4875 for (i = opnum + 1; i < reload_n_operands; i++)
4876 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4877 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4886 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4889 This function uses the same algorithm as reload_reg_free_p above. */
4892 reloads_conflict (r1, r2)
4895 enum reload_type r1_type = reload_when_needed[r1];
4896 enum reload_type r2_type = reload_when_needed[r2];
4897 int r1_opnum = reload_opnum[r1];
4898 int r2_opnum = reload_opnum[r2];
4900 /* RELOAD_OTHER conflicts with everything. */
4901 if (r2_type == RELOAD_OTHER)
4904 /* Otherwise, check conflicts differently for each type. */
4908 case RELOAD_FOR_INPUT:
4909 return (r2_type == RELOAD_FOR_INSN
4910 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4911 || r2_type == RELOAD_FOR_OPADDR_ADDR
4912 || r2_type == RELOAD_FOR_INPUT
4913 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4914 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4915 && r2_opnum > r1_opnum));
4917 case RELOAD_FOR_INPUT_ADDRESS:
4918 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4919 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4921 case RELOAD_FOR_INPADDR_ADDRESS:
4922 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4923 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4925 case RELOAD_FOR_OUTPUT_ADDRESS:
4926 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4927 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4929 case RELOAD_FOR_OUTADDR_ADDRESS:
4930 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4931 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4933 case RELOAD_FOR_OPERAND_ADDRESS:
4934 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4935 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4937 case RELOAD_FOR_OPADDR_ADDR:
4938 return (r2_type == RELOAD_FOR_INPUT
4939 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4941 case RELOAD_FOR_OUTPUT:
4942 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4943 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4944 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4945 && r2_opnum >= r1_opnum));
4947 case RELOAD_FOR_INSN:
4948 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4949 || r2_type == RELOAD_FOR_INSN
4950 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4952 case RELOAD_FOR_OTHER_ADDRESS:
4953 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4963 /* Vector of reload-numbers showing the order in which the reloads should
4965 short reload_order[MAX_RELOADS];
4967 /* Indexed by reload number, 1 if incoming value
4968 inherited from previous insns. */
4969 char reload_inherited[MAX_RELOADS];
4971 /* For an inherited reload, this is the insn the reload was inherited from,
4972 if we know it. Otherwise, this is 0. */
4973 rtx reload_inheritance_insn[MAX_RELOADS];
4975 /* If non-zero, this is a place to get the value of the reload,
4976 rather than using reload_in. */
4977 rtx reload_override_in[MAX_RELOADS];
4979 /* For each reload, the index in spill_regs of the spill register used,
4980 or -1 if we did not need one of the spill registers for this reload. */
4981 int reload_spill_index[MAX_RELOADS];
4983 /* Find a spill register to use as a reload register for reload R.
4984 LAST_RELOAD is non-zero if this is the last reload for the insn being
4987 Set reload_reg_rtx[R] to the register allocated.
4989 If NOERROR is nonzero, we return 1 if successful,
4990 or 0 if we couldn't find a spill reg and we didn't change anything. */
4993 allocate_reload_reg (r, insn, last_reload, noerror)
5005 /* If we put this reload ahead, thinking it is a group,
5006 then insist on finding a group. Otherwise we can grab a
5007 reg that some other reload needs.
5008 (That can happen when we have a 68000 DATA_OR_FP_REG
5009 which is a group of data regs or one fp reg.)
5010 We need not be so restrictive if there are no more reloads
5013 ??? Really it would be nicer to have smarter handling
5014 for that kind of reg class, where a problem like this is normal.
5015 Perhaps those classes should be avoided for reloading
5016 by use of more alternatives. */
5018 int force_group = reload_nregs[r] > 1 && ! last_reload;
5020 /* If we want a single register and haven't yet found one,
5021 take any reg in the right class and not in use.
5022 If we want a consecutive group, here is where we look for it.
5024 We use two passes so we can first look for reload regs to
5025 reuse, which are already in use for other reloads in this insn,
5026 and only then use additional registers.
5027 I think that maximizing reuse is needed to make sure we don't
5028 run out of reload regs. Suppose we have three reloads, and
5029 reloads A and B can share regs. These need two regs.
5030 Suppose A and B are given different regs.
5031 That leaves none for C. */
5032 for (pass = 0; pass < 2; pass++)
5034 /* I is the index in spill_regs.
5035 We advance it round-robin between insns to use all spill regs
5036 equally, so that inherited reloads have a chance
5037 of leapfrogging each other. Don't do this, however, when we have
5038 group needs and failure would be fatal; if we only have a relatively
5039 small number of spill registers, and more than one of them has
5040 group needs, then by starting in the middle, we may end up
5041 allocating the first one in such a way that we are not left with
5042 sufficient groups to handle the rest. */
5044 if (noerror || ! force_group)
5049 for (count = 0; count < n_spills; count++)
5051 int class = (int) reload_reg_class[r];
5053 i = (i + 1) % n_spills;
5055 if (reload_reg_free_p (spill_regs[i], reload_opnum[r],
5056 reload_when_needed[r])
5057 && TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i])
5058 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
5059 /* Look first for regs to share, then for unshared. But
5060 don't share regs used for inherited reloads; they are
5061 the ones we want to preserve. */
5063 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5065 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5068 int nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
5069 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5070 (on 68000) got us two FP regs. If NR is 1,
5071 we would reject both of them. */
5073 nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]);
5074 /* If we need only one reg, we have already won. */
5077 /* But reject a single reg if we demand a group. */
5082 /* Otherwise check that as many consecutive regs as we need
5084 Also, don't use for a group registers that are
5085 needed for nongroups. */
5086 if (! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
5089 regno = spill_regs[i] + nr - 1;
5090 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5091 && spill_reg_order[regno] >= 0
5092 && reload_reg_free_p (regno, reload_opnum[r],
5093 reload_when_needed[r])
5094 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
5104 /* If we found something on pass 1, omit pass 2. */
5105 if (count < n_spills)
5109 /* We should have found a spill register by now. */
5110 if (count == n_spills)
5117 /* I is the index in SPILL_REG_RTX of the reload register we are to
5118 allocate. Get an rtx for it and find its register number. */
5120 new = spill_reg_rtx[i];
5122 if (new == 0 || GET_MODE (new) != reload_mode[r])
5123 spill_reg_rtx[i] = new
5124 = gen_rtx (REG, reload_mode[r], spill_regs[i]);
5126 regno = true_regnum (new);
5128 /* Detect when the reload reg can't hold the reload mode.
5129 This used to be one `if', but Sequent compiler can't handle that. */
5130 if (HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5132 enum machine_mode test_mode = VOIDmode;
5134 test_mode = GET_MODE (reload_in[r]);
5135 /* If reload_in[r] has VOIDmode, it means we will load it
5136 in whatever mode the reload reg has: to wit, reload_mode[r].
5137 We have already tested that for validity. */
5138 /* Aside from that, we need to test that the expressions
5139 to reload from or into have modes which are valid for this
5140 reload register. Otherwise the reload insns would be invalid. */
5141 if (! (reload_in[r] != 0 && test_mode != VOIDmode
5142 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5143 if (! (reload_out[r] != 0
5144 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r]))))
5146 /* The reg is OK. */
5149 /* Mark as in use for this insn the reload regs we use
5151 mark_reload_reg_in_use (spill_regs[i], reload_opnum[r],
5152 reload_when_needed[r], reload_mode[r]);
5154 reload_reg_rtx[r] = new;
5155 reload_spill_index[r] = i;
5160 /* The reg is not OK. */
5165 if (asm_noperands (PATTERN (insn)) < 0)
5166 /* It's the compiler's fault. */
5167 fatal_insn ("Could not find a spill register", insn);
5169 /* It's the user's fault; the operand's mode and constraint
5170 don't match. Disable this reload so we don't crash in final. */
5171 error_for_asm (insn,
5172 "`asm' operand constraint incompatible with operand size");
5175 reload_reg_rtx[r] = 0;
5176 reload_optional[r] = 1;
5177 reload_secondary_p[r] = 1;
5182 /* Assign hard reg targets for the pseudo-registers we must reload
5183 into hard regs for this insn.
5184 Also output the instructions to copy them in and out of the hard regs.
5186 For machines with register classes, we are responsible for
5187 finding a reload reg in the proper class. */
5190 choose_reload_regs (insn, avoid_return_reg)
5192 rtx avoid_return_reg;
5195 int max_group_size = 1;
5196 enum reg_class group_class = NO_REGS;
5199 rtx save_reload_reg_rtx[MAX_RELOADS];
5200 char save_reload_inherited[MAX_RELOADS];
5201 rtx save_reload_inheritance_insn[MAX_RELOADS];
5202 rtx save_reload_override_in[MAX_RELOADS];
5203 int save_reload_spill_index[MAX_RELOADS];
5204 HARD_REG_SET save_reload_reg_used;
5205 HARD_REG_SET save_reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
5206 HARD_REG_SET save_reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
5207 HARD_REG_SET save_reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
5208 HARD_REG_SET save_reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
5209 HARD_REG_SET save_reload_reg_used_in_input[MAX_RECOG_OPERANDS];
5210 HARD_REG_SET save_reload_reg_used_in_output[MAX_RECOG_OPERANDS];
5211 HARD_REG_SET save_reload_reg_used_in_op_addr;
5212 HARD_REG_SET save_reload_reg_used_in_op_addr_reload;
5213 HARD_REG_SET save_reload_reg_used_in_insn;
5214 HARD_REG_SET save_reload_reg_used_in_other_addr;
5215 HARD_REG_SET save_reload_reg_used_at_all;
5217 bzero (reload_inherited, MAX_RELOADS);
5218 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
5219 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
5221 CLEAR_HARD_REG_SET (reload_reg_used);
5222 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5223 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5224 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5225 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5226 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5228 for (i = 0; i < reload_n_operands; i++)
5230 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5231 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5232 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5233 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5234 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5235 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5238 #ifdef SMALL_REGISTER_CLASSES
5239 /* Don't bother with avoiding the return reg
5240 if we have no mandatory reload that could use it. */
5241 if (SMALL_REGISTER_CLASSES && avoid_return_reg)
5244 int regno = REGNO (avoid_return_reg);
5246 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
5249 for (r = regno; r < regno + nregs; r++)
5250 if (spill_reg_order[r] >= 0)
5251 for (j = 0; j < n_reloads; j++)
5252 if (!reload_optional[j] && reload_reg_rtx[j] == 0
5253 && (reload_in[j] != 0 || reload_out[j] != 0
5254 || reload_secondary_p[j])
5256 TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[j]], r))
5259 avoid_return_reg = 0;
5261 #endif /* SMALL_REGISTER_CLASSES */
5263 #if 0 /* Not needed, now that we can always retry without inheritance. */
5264 /* See if we have more mandatory reloads than spill regs.
5265 If so, then we cannot risk optimizations that could prevent
5266 reloads from sharing one spill register.
5268 Since we will try finding a better register than reload_reg_rtx
5269 unless it is equal to reload_in or reload_out, count such reloads. */
5273 #ifdef SMALL_REGISTER_CLASSES
5274 if (SMALL_REGISTER_CLASSES)
5275 tem = (avoid_return_reg != 0);
5277 for (j = 0; j < n_reloads; j++)
5278 if (! reload_optional[j]
5279 && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j])
5280 && (reload_reg_rtx[j] == 0
5281 || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j])
5282 && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j]))))
5289 #ifdef SMALL_REGISTER_CLASSES
5290 /* Don't use the subroutine call return reg for a reload
5291 if we are supposed to avoid it. */
5292 if (SMALL_REGISTER_CLASSES && avoid_return_reg)
5294 int regno = REGNO (avoid_return_reg);
5296 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
5299 for (r = regno; r < regno + nregs; r++)
5300 if (spill_reg_order[r] >= 0)
5301 SET_HARD_REG_BIT (reload_reg_used, r);
5303 #endif /* SMALL_REGISTER_CLASSES */
5305 /* In order to be certain of getting the registers we need,
5306 we must sort the reloads into order of increasing register class.
5307 Then our grabbing of reload registers will parallel the process
5308 that provided the reload registers.
5310 Also note whether any of the reloads wants a consecutive group of regs.
5311 If so, record the maximum size of the group desired and what
5312 register class contains all the groups needed by this insn. */
5314 for (j = 0; j < n_reloads; j++)
5316 reload_order[j] = j;
5317 reload_spill_index[j] = -1;
5320 = (reload_inmode[j] == VOIDmode
5321 || (GET_MODE_SIZE (reload_outmode[j])
5322 > GET_MODE_SIZE (reload_inmode[j])))
5323 ? reload_outmode[j] : reload_inmode[j];
5325 reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]);
5327 if (reload_nregs[j] > 1)
5329 max_group_size = MAX (reload_nregs[j], max_group_size);
5330 group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class];
5333 /* If we have already decided to use a certain register,
5334 don't use it in another way. */
5335 if (reload_reg_rtx[j])
5336 mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]), reload_opnum[j],
5337 reload_when_needed[j], reload_mode[j]);
5341 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5343 bcopy ((char *) reload_reg_rtx, (char *) save_reload_reg_rtx,
5344 sizeof reload_reg_rtx);
5345 bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited);
5346 bcopy ((char *) reload_inheritance_insn,
5347 (char *) save_reload_inheritance_insn,
5348 sizeof reload_inheritance_insn);
5349 bcopy ((char *) reload_override_in, (char *) save_reload_override_in,
5350 sizeof reload_override_in);
5351 bcopy ((char *) reload_spill_index, (char *) save_reload_spill_index,
5352 sizeof reload_spill_index);
5353 COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used);
5354 COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all);
5355 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr,
5356 reload_reg_used_in_op_addr);
5358 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr_reload,
5359 reload_reg_used_in_op_addr_reload);
5361 COPY_HARD_REG_SET (save_reload_reg_used_in_insn,
5362 reload_reg_used_in_insn);
5363 COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr,
5364 reload_reg_used_in_other_addr);
5366 for (i = 0; i < reload_n_operands; i++)
5368 COPY_HARD_REG_SET (save_reload_reg_used_in_output[i],
5369 reload_reg_used_in_output[i]);
5370 COPY_HARD_REG_SET (save_reload_reg_used_in_input[i],
5371 reload_reg_used_in_input[i]);
5372 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr[i],
5373 reload_reg_used_in_input_addr[i]);
5374 COPY_HARD_REG_SET (save_reload_reg_used_in_inpaddr_addr[i],
5375 reload_reg_used_in_inpaddr_addr[i]);
5376 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr[i],
5377 reload_reg_used_in_output_addr[i]);
5378 COPY_HARD_REG_SET (save_reload_reg_used_in_outaddr_addr[i],
5379 reload_reg_used_in_outaddr_addr[i]);
5382 /* If -O, try first with inheritance, then turning it off.
5383 If not -O, don't do inheritance.
5384 Using inheritance when not optimizing leads to paradoxes
5385 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5386 because one side of the comparison might be inherited. */
5388 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5390 /* Process the reloads in order of preference just found.
5391 Beyond this point, subregs can be found in reload_reg_rtx.
5393 This used to look for an existing reloaded home for all
5394 of the reloads, and only then perform any new reloads.
5395 But that could lose if the reloads were done out of reg-class order
5396 because a later reload with a looser constraint might have an old
5397 home in a register needed by an earlier reload with a tighter constraint.
5399 To solve this, we make two passes over the reloads, in the order
5400 described above. In the first pass we try to inherit a reload
5401 from a previous insn. If there is a later reload that needs a
5402 class that is a proper subset of the class being processed, we must
5403 also allocate a spill register during the first pass.
5405 Then make a second pass over the reloads to allocate any reloads
5406 that haven't been given registers yet. */
5408 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5410 for (j = 0; j < n_reloads; j++)
5412 register int r = reload_order[j];
5414 /* Ignore reloads that got marked inoperative. */
5415 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
5418 /* If find_reloads chose a to use reload_in or reload_out as a reload
5419 register, we don't need to chose one. Otherwise, try even if it found
5420 one since we might save an insn if we find the value lying around. */
5421 if (reload_in[r] != 0 && reload_reg_rtx[r] != 0
5422 && (rtx_equal_p (reload_in[r], reload_reg_rtx[r])
5423 || rtx_equal_p (reload_out[r], reload_reg_rtx[r])))
5426 #if 0 /* No longer needed for correct operation.
5427 It might give better code, or might not; worth an experiment? */
5428 /* If this is an optional reload, we can't inherit from earlier insns
5429 until we are sure that any non-optional reloads have been allocated.
5430 The following code takes advantage of the fact that optional reloads
5431 are at the end of reload_order. */
5432 if (reload_optional[r] != 0)
5433 for (i = 0; i < j; i++)
5434 if ((reload_out[reload_order[i]] != 0
5435 || reload_in[reload_order[i]] != 0
5436 || reload_secondary_p[reload_order[i]])
5437 && ! reload_optional[reload_order[i]]
5438 && reload_reg_rtx[reload_order[i]] == 0)
5439 allocate_reload_reg (reload_order[i], insn, 0, inheritance);
5442 /* First see if this pseudo is already available as reloaded
5443 for a previous insn. We cannot try to inherit for reloads
5444 that are smaller than the maximum number of registers needed
5445 for groups unless the register we would allocate cannot be used
5448 We could check here to see if this is a secondary reload for
5449 an object that is already in a register of the desired class.
5450 This would avoid the need for the secondary reload register.
5451 But this is complex because we can't easily determine what
5452 objects might want to be loaded via this reload. So let a register
5453 be allocated here. In `emit_reload_insns' we suppress one of the
5454 loads in the case described above. */
5458 register int regno = -1;
5459 enum machine_mode mode;
5461 if (reload_in[r] == 0)
5463 else if (GET_CODE (reload_in[r]) == REG)
5465 regno = REGNO (reload_in[r]);
5466 mode = GET_MODE (reload_in[r]);
5468 else if (GET_CODE (reload_in_reg[r]) == REG)
5470 regno = REGNO (reload_in_reg[r]);
5471 mode = GET_MODE (reload_in_reg[r]);
5474 /* This won't work, since REGNO can be a pseudo reg number.
5475 Also, it takes much more hair to keep track of all the things
5476 that can invalidate an inherited reload of part of a pseudoreg. */
5477 else if (GET_CODE (reload_in[r]) == SUBREG
5478 && GET_CODE (SUBREG_REG (reload_in[r])) == REG)
5479 regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]);
5482 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5484 i = spill_reg_order[REGNO (reg_last_reload_reg[regno])];
5486 if (reg_reloaded_contents[i] == regno
5487 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno]))
5488 >= GET_MODE_SIZE (mode))
5489 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
5490 && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5492 && (reload_nregs[r] == max_group_size
5493 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5495 && reload_reg_free_p (spill_regs[i], reload_opnum[r],
5496 reload_when_needed[r])
5497 && reload_reg_free_before_p (spill_regs[i],
5499 reload_when_needed[r]))
5501 /* If a group is needed, verify that all the subsequent
5502 registers still have their values intact. */
5504 = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
5507 for (k = 1; k < nr; k++)
5508 if (reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
5516 /* We found a register that contains the
5517 value we need. If this register is the
5518 same as an `earlyclobber' operand of the
5519 current insn, just mark it as a place to
5520 reload from since we can't use it as the
5521 reload register itself. */
5523 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5524 if (reg_overlap_mentioned_for_reload_p
5525 (reg_last_reload_reg[regno],
5526 reload_earlyclobbers[i1]))
5529 if (i1 != n_earlyclobbers
5530 /* Don't really use the inherited spill reg
5531 if we need it wider than we've got it. */
5532 || (GET_MODE_SIZE (reload_mode[r])
5533 > GET_MODE_SIZE (mode)))
5534 reload_override_in[r] = reg_last_reload_reg[regno];
5538 /* We can use this as a reload reg. */
5539 /* Mark the register as in use for this part of
5541 mark_reload_reg_in_use (spill_regs[i],
5543 reload_when_needed[r],
5545 reload_reg_rtx[r] = reg_last_reload_reg[regno];
5546 reload_inherited[r] = 1;
5547 reload_inheritance_insn[r]
5548 = reg_reloaded_insn[i];
5549 reload_spill_index[r] = i;
5550 for (k = 0; k < nr; k++)
5551 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5559 /* Here's another way to see if the value is already lying around. */
5561 && reload_in[r] != 0
5562 && ! reload_inherited[r]
5563 && reload_out[r] == 0
5564 && (CONSTANT_P (reload_in[r])
5565 || GET_CODE (reload_in[r]) == PLUS
5566 || GET_CODE (reload_in[r]) == REG
5567 || GET_CODE (reload_in[r]) == MEM)
5568 && (reload_nregs[r] == max_group_size
5569 || ! reg_classes_intersect_p (reload_reg_class[r], group_class)))
5572 = find_equiv_reg (reload_in[r], insn, reload_reg_class[r],
5573 -1, NULL_PTR, 0, reload_mode[r]);
5578 if (GET_CODE (equiv) == REG)
5579 regno = REGNO (equiv);
5580 else if (GET_CODE (equiv) == SUBREG)
5582 /* This must be a SUBREG of a hard register.
5583 Make a new REG since this might be used in an
5584 address and not all machines support SUBREGs
5586 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
5587 equiv = gen_rtx (REG, reload_mode[r], regno);
5593 /* If we found a spill reg, reject it unless it is free
5594 and of the desired class. */
5596 && ((spill_reg_order[regno] >= 0
5597 && ! reload_reg_free_before_p (regno, reload_opnum[r],
5598 reload_when_needed[r]))
5599 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5603 if (equiv != 0 && TEST_HARD_REG_BIT (reload_reg_used_at_all, regno))
5606 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5609 /* We found a register that contains the value we need.
5610 If this register is the same as an `earlyclobber' operand
5611 of the current insn, just mark it as a place to reload from
5612 since we can't use it as the reload register itself. */
5615 for (i = 0; i < n_earlyclobbers; i++)
5616 if (reg_overlap_mentioned_for_reload_p (equiv,
5617 reload_earlyclobbers[i]))
5619 reload_override_in[r] = equiv;
5624 /* JRV: If the equiv register we have found is
5625 explicitly clobbered in the current insn, mark but
5626 don't use, as above. */
5628 if (equiv != 0 && regno_clobbered_p (regno, insn))
5630 reload_override_in[r] = equiv;
5634 /* If we found an equivalent reg, say no code need be generated
5635 to load it, and use it as our reload reg. */
5636 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5638 int nr = HARD_REGNO_NREGS (regno, reload_mode[r]);
5640 reload_reg_rtx[r] = equiv;
5641 reload_inherited[r] = 1;
5643 /* If any of the hard registers in EQUIV are spill
5644 registers, mark them as in use for this insn. */
5645 for (k = 0; k < nr; k++)
5647 i = spill_reg_order[regno + k];
5650 mark_reload_reg_in_use (regno, reload_opnum[r],
5651 reload_when_needed[r],
5653 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5660 /* If we found a register to use already, or if this is an optional
5661 reload, we are done. */
5662 if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0)
5665 #if 0 /* No longer needed for correct operation. Might or might not
5666 give better code on the average. Want to experiment? */
5668 /* See if there is a later reload that has a class different from our
5669 class that intersects our class or that requires less register
5670 than our reload. If so, we must allocate a register to this
5671 reload now, since that reload might inherit a previous reload
5672 and take the only available register in our class. Don't do this
5673 for optional reloads since they will force all previous reloads
5674 to be allocated. Also don't do this for reloads that have been
5677 for (i = j + 1; i < n_reloads; i++)
5679 int s = reload_order[i];
5681 if ((reload_in[s] == 0 && reload_out[s] == 0
5682 && ! reload_secondary_p[s])
5683 || reload_optional[s])
5686 if ((reload_reg_class[s] != reload_reg_class[r]
5687 && reg_classes_intersect_p (reload_reg_class[r],
5688 reload_reg_class[s]))
5689 || reload_nregs[s] < reload_nregs[r])
5696 allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance);
5700 /* Now allocate reload registers for anything non-optional that
5701 didn't get one yet. */
5702 for (j = 0; j < n_reloads; j++)
5704 register int r = reload_order[j];
5706 /* Ignore reloads that got marked inoperative. */
5707 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
5710 /* Skip reloads that already have a register allocated or are
5712 if (reload_reg_rtx[r] != 0 || reload_optional[r])
5715 if (! allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance))
5719 /* If that loop got all the way, we have won. */
5724 /* Loop around and try without any inheritance. */
5725 /* First undo everything done by the failed attempt
5726 to allocate with inheritance. */
5727 bcopy ((char *) save_reload_reg_rtx, (char *) reload_reg_rtx,
5728 sizeof reload_reg_rtx);
5729 bcopy ((char *) save_reload_inherited, (char *) reload_inherited,
5730 sizeof reload_inherited);
5731 bcopy ((char *) save_reload_inheritance_insn,
5732 (char *) reload_inheritance_insn,
5733 sizeof reload_inheritance_insn);
5734 bcopy ((char *) save_reload_override_in, (char *) reload_override_in,
5735 sizeof reload_override_in);
5736 bcopy ((char *) save_reload_spill_index, (char *) reload_spill_index,
5737 sizeof reload_spill_index);
5738 COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used);
5739 COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all);
5740 COPY_HARD_REG_SET (reload_reg_used_in_op_addr,
5741 save_reload_reg_used_in_op_addr);
5742 COPY_HARD_REG_SET (reload_reg_used_in_op_addr_reload,
5743 save_reload_reg_used_in_op_addr_reload);
5744 COPY_HARD_REG_SET (reload_reg_used_in_insn,
5745 save_reload_reg_used_in_insn);
5746 COPY_HARD_REG_SET (reload_reg_used_in_other_addr,
5747 save_reload_reg_used_in_other_addr);
5749 for (i = 0; i < reload_n_operands; i++)
5751 COPY_HARD_REG_SET (reload_reg_used_in_input[i],
5752 save_reload_reg_used_in_input[i]);
5753 COPY_HARD_REG_SET (reload_reg_used_in_output[i],
5754 save_reload_reg_used_in_output[i]);
5755 COPY_HARD_REG_SET (reload_reg_used_in_input_addr[i],
5756 save_reload_reg_used_in_input_addr[i]);
5757 COPY_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i],
5758 save_reload_reg_used_in_inpaddr_addr[i]);
5759 COPY_HARD_REG_SET (reload_reg_used_in_output_addr[i],
5760 save_reload_reg_used_in_output_addr[i]);
5761 COPY_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i],
5762 save_reload_reg_used_in_outaddr_addr[i]);
5766 /* If we thought we could inherit a reload, because it seemed that
5767 nothing else wanted the same reload register earlier in the insn,
5768 verify that assumption, now that all reloads have been assigned. */
5770 for (j = 0; j < n_reloads; j++)
5772 register int r = reload_order[j];
5774 if (reload_inherited[r] && reload_reg_rtx[r] != 0
5775 && ! reload_reg_free_before_p (true_regnum (reload_reg_rtx[r]),
5777 reload_when_needed[r]))
5778 reload_inherited[r] = 0;
5780 /* If we found a better place to reload from,
5781 validate it in the same fashion, if it is a reload reg. */
5782 if (reload_override_in[r]
5783 && (GET_CODE (reload_override_in[r]) == REG
5784 || GET_CODE (reload_override_in[r]) == SUBREG))
5786 int regno = true_regnum (reload_override_in[r]);
5787 if (spill_reg_order[regno] >= 0
5788 && ! reload_reg_free_before_p (regno, reload_opnum[r],
5789 reload_when_needed[r]))
5790 reload_override_in[r] = 0;
5794 /* Now that reload_override_in is known valid,
5795 actually override reload_in. */
5796 for (j = 0; j < n_reloads; j++)
5797 if (reload_override_in[j])
5798 reload_in[j] = reload_override_in[j];
5800 /* If this reload won't be done because it has been cancelled or is
5801 optional and not inherited, clear reload_reg_rtx so other
5802 routines (such as subst_reloads) don't get confused. */
5803 for (j = 0; j < n_reloads; j++)
5804 if (reload_reg_rtx[j] != 0
5805 && ((reload_optional[j] && ! reload_inherited[j])
5806 || (reload_in[j] == 0 && reload_out[j] == 0
5807 && ! reload_secondary_p[j])))
5809 int regno = true_regnum (reload_reg_rtx[j]);
5811 if (spill_reg_order[regno] >= 0)
5812 clear_reload_reg_in_use (regno, reload_opnum[j],
5813 reload_when_needed[j], reload_mode[j]);
5814 reload_reg_rtx[j] = 0;
5817 /* Record which pseudos and which spill regs have output reloads. */
5818 for (j = 0; j < n_reloads; j++)
5820 register int r = reload_order[j];
5822 i = reload_spill_index[r];
5824 /* I is nonneg if this reload used one of the spill regs.
5825 If reload_reg_rtx[r] is 0, this is an optional reload
5826 that we opted to ignore. */
5827 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG
5828 && reload_reg_rtx[r] != 0)
5830 register int nregno = REGNO (reload_out[r]);
5833 if (nregno < FIRST_PSEUDO_REGISTER)
5834 nr = HARD_REGNO_NREGS (nregno, reload_mode[r]);
5837 reg_has_output_reload[nregno + nr] = 1;
5841 nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
5843 SET_HARD_REG_BIT (reg_is_output_reload, spill_regs[i] + nr);
5846 if (reload_when_needed[r] != RELOAD_OTHER
5847 && reload_when_needed[r] != RELOAD_FOR_OUTPUT
5848 && reload_when_needed[r] != RELOAD_FOR_INSN)
5854 /* If SMALL_REGISTER_CLASSES are defined, we may not have merged two
5855 reloads of the same item for fear that we might not have enough reload
5856 registers. However, normally they will get the same reload register
5857 and hence actually need not be loaded twice.
5859 Here we check for the most common case of this phenomenon: when we have
5860 a number of reloads for the same object, each of which were allocated
5861 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5862 reload, and is not modified in the insn itself. If we find such,
5863 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5864 This will not increase the number of spill registers needed and will
5865 prevent redundant code. */
5867 #ifdef SMALL_REGISTER_CLASSES
5870 merge_assigned_reloads (insn)
5875 /* Scan all the reloads looking for ones that only load values and
5876 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5877 assigned and not modified by INSN. */
5879 for (i = 0; i < n_reloads; i++)
5881 if (reload_in[i] == 0 || reload_when_needed[i] == RELOAD_OTHER
5882 || reload_out[i] != 0 || reload_reg_rtx[i] == 0
5883 || reg_set_p (reload_reg_rtx[i], insn))
5886 /* Look at all other reloads. Ensure that the only use of this
5887 reload_reg_rtx is in a reload that just loads the same value
5888 as we do. Note that any secondary reloads must be of the identical
5889 class since the values, modes, and result registers are the
5890 same, so we need not do anything with any secondary reloads. */
5892 for (j = 0; j < n_reloads; j++)
5894 if (i == j || reload_reg_rtx[j] == 0
5895 || ! reg_overlap_mentioned_p (reload_reg_rtx[j],
5899 /* If the reload regs aren't exactly the same (e.g, different modes)
5900 or if the values are different, we can't merge anything with this
5903 if (! rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
5904 || reload_out[j] != 0 || reload_in[j] == 0
5905 || ! rtx_equal_p (reload_in[i], reload_in[j]))
5909 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5910 we, in fact, found any matching reloads. */
5914 for (j = 0; j < n_reloads; j++)
5915 if (i != j && reload_reg_rtx[j] != 0
5916 && rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j]))
5918 reload_when_needed[i] = RELOAD_OTHER;
5920 transfer_replacements (i, j);
5923 /* If this is now RELOAD_OTHER, look for any reloads that load
5924 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
5925 if they were for inputs, RELOAD_OTHER for outputs. Note that
5926 this test is equivalent to looking for reloads for this operand
5929 if (reload_when_needed[i] == RELOAD_OTHER)
5930 for (j = 0; j < n_reloads; j++)
5931 if (reload_in[j] != 0
5932 && reload_when_needed[i] != RELOAD_OTHER
5933 && reg_overlap_mentioned_for_reload_p (reload_in[j],
5935 reload_when_needed[j]
5936 = ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS
5937 || reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS)
5938 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
5942 #endif /* SMALL_RELOAD_CLASSES */
5944 /* Output insns to reload values in and out of the chosen reload regs. */
5947 emit_reload_insns (insn)
5951 rtx input_reload_insns[MAX_RECOG_OPERANDS];
5952 rtx other_input_address_reload_insns = 0;
5953 rtx other_input_reload_insns = 0;
5954 rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
5955 rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
5956 rtx output_reload_insns[MAX_RECOG_OPERANDS];
5957 rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
5958 rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
5959 rtx operand_reload_insns = 0;
5960 rtx other_operand_reload_insns = 0;
5961 rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
5962 rtx following_insn = NEXT_INSN (insn);
5963 rtx before_insn = insn;
5965 /* Values to be put in spill_reg_store are put here first. */
5966 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
5968 for (j = 0; j < reload_n_operands; j++)
5969 input_reload_insns[j] = input_address_reload_insns[j]
5970 = inpaddr_address_reload_insns[j]
5971 = output_reload_insns[j] = output_address_reload_insns[j]
5972 = outaddr_address_reload_insns[j]
5973 = other_output_reload_insns[j] = 0;
5975 /* Now output the instructions to copy the data into and out of the
5976 reload registers. Do these in the order that the reloads were reported,
5977 since reloads of base and index registers precede reloads of operands
5978 and the operands may need the base and index registers reloaded. */
5980 for (j = 0; j < n_reloads; j++)
5983 rtx oldequiv_reg = 0;
5984 rtx this_reload_insn = 0;
5986 if (reload_spill_index[j] >= 0)
5987 new_spill_reg_store[reload_spill_index[j]] = 0;
5990 if (old != 0 && ! reload_inherited[j]
5991 && ! rtx_equal_p (reload_reg_rtx[j], old)
5992 && reload_reg_rtx[j] != 0)
5994 register rtx reloadreg = reload_reg_rtx[j];
5996 enum machine_mode mode;
5999 /* Determine the mode to reload in.
6000 This is very tricky because we have three to choose from.
6001 There is the mode the insn operand wants (reload_inmode[J]).
6002 There is the mode of the reload register RELOADREG.
6003 There is the intrinsic mode of the operand, which we could find
6004 by stripping some SUBREGs.
6005 It turns out that RELOADREG's mode is irrelevant:
6006 we can change that arbitrarily.
6008 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6009 then the reload reg may not support QImode moves, so use SImode.
6010 If foo is in memory due to spilling a pseudo reg, this is safe,
6011 because the QImode value is in the least significant part of a
6012 slot big enough for a SImode. If foo is some other sort of
6013 memory reference, then it is impossible to reload this case,
6014 so previous passes had better make sure this never happens.
6016 Then consider a one-word union which has SImode and one of its
6017 members is a float, being fetched as (SUBREG:SF union:SI).
6018 We must fetch that as SFmode because we could be loading into
6019 a float-only register. In this case OLD's mode is correct.
6021 Consider an immediate integer: it has VOIDmode. Here we need
6022 to get a mode from something else.
6024 In some cases, there is a fourth mode, the operand's
6025 containing mode. If the insn specifies a containing mode for
6026 this operand, it overrides all others.
6028 I am not sure whether the algorithm here is always right,
6029 but it does the right things in those cases. */
6031 mode = GET_MODE (old);
6032 if (mode == VOIDmode)
6033 mode = reload_inmode[j];
6035 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6036 /* If we need a secondary register for this operation, see if
6037 the value is already in a register in that class. Don't
6038 do this if the secondary register will be used as a scratch
6041 if (reload_secondary_in_reload[j] >= 0
6042 && reload_secondary_in_icode[j] == CODE_FOR_nothing
6045 = find_equiv_reg (old, insn,
6046 reload_reg_class[reload_secondary_in_reload[j]],
6047 -1, NULL_PTR, 0, mode);
6050 /* If reloading from memory, see if there is a register
6051 that already holds the same value. If so, reload from there.
6052 We can pass 0 as the reload_reg_p argument because
6053 any other reload has either already been emitted,
6054 in which case find_equiv_reg will see the reload-insn,
6055 or has yet to be emitted, in which case it doesn't matter
6056 because we will use this equiv reg right away. */
6058 if (oldequiv == 0 && optimize
6059 && (GET_CODE (old) == MEM
6060 || (GET_CODE (old) == REG
6061 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6062 && reg_renumber[REGNO (old)] < 0)))
6063 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
6064 -1, NULL_PTR, 0, mode);
6068 int regno = true_regnum (oldequiv);
6070 /* If OLDEQUIV is a spill register, don't use it for this
6071 if any other reload needs it at an earlier stage of this insn
6072 or at this stage. */
6073 if (spill_reg_order[regno] >= 0
6074 && (! reload_reg_free_p (regno, reload_opnum[j],
6075 reload_when_needed[j])
6076 || ! reload_reg_free_before_p (regno, reload_opnum[j],
6077 reload_when_needed[j])))
6080 /* If OLDEQUIV is not a spill register,
6081 don't use it if any other reload wants it. */
6082 if (spill_reg_order[regno] < 0)
6085 for (k = 0; k < n_reloads; k++)
6086 if (reload_reg_rtx[k] != 0 && k != j
6087 && reg_overlap_mentioned_for_reload_p (reload_reg_rtx[k],
6095 /* If it is no cheaper to copy from OLDEQUIV into the
6096 reload register than it would be to move from memory,
6097 don't use it. Likewise, if we need a secondary register
6101 && ((REGNO_REG_CLASS (regno) != reload_reg_class[j]
6102 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
6103 reload_reg_class[j])
6104 >= MEMORY_MOVE_COST (mode)))
6105 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6106 || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6110 #ifdef SECONDARY_MEMORY_NEEDED
6111 || SECONDARY_MEMORY_NEEDED (reload_reg_class[j],
6112 REGNO_REG_CLASS (regno),
6121 else if (GET_CODE (oldequiv) == REG)
6122 oldequiv_reg = oldequiv;
6123 else if (GET_CODE (oldequiv) == SUBREG)
6124 oldequiv_reg = SUBREG_REG (oldequiv);
6126 /* If we are reloading from a register that was recently stored in
6127 with an output-reload, see if we can prove there was
6128 actually no need to store the old value in it. */
6130 if (optimize && GET_CODE (oldequiv) == REG
6131 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6132 && spill_reg_order[REGNO (oldequiv)] >= 0
6133 && spill_reg_store[spill_reg_order[REGNO (oldequiv)]] != 0
6134 && find_reg_note (insn, REG_DEAD, reload_in[j])
6135 /* This is unsafe if operand occurs more than once in current
6136 insn. Perhaps some occurrences weren't reloaded. */
6137 && count_occurrences (PATTERN (insn), reload_in[j]) == 1)
6138 delete_output_reload
6139 (insn, j, spill_reg_store[spill_reg_order[REGNO (oldequiv)]]);
6141 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6142 then load RELOADREG from OLDEQUIV. Note that we cannot use
6143 gen_lowpart_common since it can do the wrong thing when
6144 RELOADREG has a multi-word mode. Note that RELOADREG
6145 must always be a REG here. */
6147 if (GET_MODE (reloadreg) != mode)
6148 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
6149 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6150 oldequiv = SUBREG_REG (oldequiv);
6151 if (GET_MODE (oldequiv) != VOIDmode
6152 && mode != GET_MODE (oldequiv))
6153 oldequiv = gen_rtx (SUBREG, mode, oldequiv, 0);
6155 /* Switch to the right place to emit the reload insns. */
6156 switch (reload_when_needed[j])
6159 where = &other_input_reload_insns;
6161 case RELOAD_FOR_INPUT:
6162 where = &input_reload_insns[reload_opnum[j]];
6164 case RELOAD_FOR_INPUT_ADDRESS:
6165 where = &input_address_reload_insns[reload_opnum[j]];
6167 case RELOAD_FOR_INPADDR_ADDRESS:
6168 where = &inpaddr_address_reload_insns[reload_opnum[j]];
6170 case RELOAD_FOR_OUTPUT_ADDRESS:
6171 where = &output_address_reload_insns[reload_opnum[j]];
6173 case RELOAD_FOR_OUTADDR_ADDRESS:
6174 where = &outaddr_address_reload_insns[reload_opnum[j]];
6176 case RELOAD_FOR_OPERAND_ADDRESS:
6177 where = &operand_reload_insns;
6179 case RELOAD_FOR_OPADDR_ADDR:
6180 where = &other_operand_reload_insns;
6182 case RELOAD_FOR_OTHER_ADDRESS:
6183 where = &other_input_address_reload_insns;
6189 push_to_sequence (*where);
6192 /* Auto-increment addresses must be reloaded in a special way. */
6193 if (GET_CODE (oldequiv) == POST_INC
6194 || GET_CODE (oldequiv) == POST_DEC
6195 || GET_CODE (oldequiv) == PRE_INC
6196 || GET_CODE (oldequiv) == PRE_DEC)
6198 /* We are not going to bother supporting the case where a
6199 incremented register can't be copied directly from
6200 OLDEQUIV since this seems highly unlikely. */
6201 if (reload_secondary_in_reload[j] >= 0)
6203 /* Prevent normal processing of this reload. */
6205 /* Output a special code sequence for this case. */
6206 inc_for_reload (reloadreg, oldequiv, reload_inc[j]);
6209 /* If we are reloading a pseudo-register that was set by the previous
6210 insn, see if we can get rid of that pseudo-register entirely
6211 by redirecting the previous insn into our reload register. */
6213 else if (optimize && GET_CODE (old) == REG
6214 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6215 && dead_or_set_p (insn, old)
6216 /* This is unsafe if some other reload
6217 uses the same reg first. */
6218 && reload_reg_free_before_p (REGNO (reloadreg),
6220 reload_when_needed[j]))
6222 rtx temp = PREV_INSN (insn);
6223 while (temp && GET_CODE (temp) == NOTE)
6224 temp = PREV_INSN (temp);
6226 && GET_CODE (temp) == INSN
6227 && GET_CODE (PATTERN (temp)) == SET
6228 && SET_DEST (PATTERN (temp)) == old
6229 /* Make sure we can access insn_operand_constraint. */
6230 && asm_noperands (PATTERN (temp)) < 0
6231 /* This is unsafe if prev insn rejects our reload reg. */
6232 && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0],
6234 /* This is unsafe if operand occurs more than once in current
6235 insn. Perhaps some occurrences aren't reloaded. */
6236 && count_occurrences (PATTERN (insn), old) == 1
6237 /* Don't risk splitting a matching pair of operands. */
6238 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6240 /* Store into the reload register instead of the pseudo. */
6241 SET_DEST (PATTERN (temp)) = reloadreg;
6242 /* If these are the only uses of the pseudo reg,
6243 pretend for GDB it lives in the reload reg we used. */
6244 if (reg_n_deaths[REGNO (old)] == 1
6245 && reg_n_sets[REGNO (old)] == 1)
6247 reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]);
6248 alter_reg (REGNO (old), -1);
6254 /* We can't do that, so output an insn to load RELOADREG. */
6258 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6259 rtx second_reload_reg = 0;
6260 enum insn_code icode;
6262 /* If we have a secondary reload, pick up the secondary register
6263 and icode, if any. If OLDEQUIV and OLD are different or
6264 if this is an in-out reload, recompute whether or not we
6265 still need a secondary register and what the icode should
6266 be. If we still need a secondary register and the class or
6267 icode is different, go back to reloading from OLD if using
6268 OLDEQUIV means that we got the wrong type of register. We
6269 cannot have different class or icode due to an in-out reload
6270 because we don't make such reloads when both the input and
6271 output need secondary reload registers. */
6273 if (reload_secondary_in_reload[j] >= 0)
6275 int secondary_reload = reload_secondary_in_reload[j];
6276 rtx real_oldequiv = oldequiv;
6279 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6280 and similarly for OLD.
6281 See comments in get_secondary_reload in reload.c. */
6282 if (GET_CODE (oldequiv) == REG
6283 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6284 && reg_equiv_mem[REGNO (oldequiv)] != 0)
6285 real_oldequiv = reg_equiv_mem[REGNO (oldequiv)];
6287 if (GET_CODE (old) == REG
6288 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6289 && reg_equiv_mem[REGNO (old)] != 0)
6290 real_old = reg_equiv_mem[REGNO (old)];
6292 second_reload_reg = reload_reg_rtx[secondary_reload];
6293 icode = reload_secondary_in_icode[j];
6295 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6296 || (reload_in[j] != 0 && reload_out[j] != 0))
6298 enum reg_class new_class
6299 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6300 mode, real_oldequiv);
6302 if (new_class == NO_REGS)
6303 second_reload_reg = 0;
6306 enum insn_code new_icode;
6307 enum machine_mode new_mode;
6309 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6310 REGNO (second_reload_reg)))
6311 oldequiv = old, real_oldequiv = real_old;
6314 new_icode = reload_in_optab[(int) mode];
6315 if (new_icode != CODE_FOR_nothing
6316 && ((insn_operand_predicate[(int) new_icode][0]
6317 && ! ((*insn_operand_predicate[(int) new_icode][0])
6319 || (insn_operand_predicate[(int) new_icode][1]
6320 && ! ((*insn_operand_predicate[(int) new_icode][1])
6321 (real_oldequiv, mode)))))
6322 new_icode = CODE_FOR_nothing;
6324 if (new_icode == CODE_FOR_nothing)
6327 new_mode = insn_operand_mode[(int) new_icode][2];
6329 if (GET_MODE (second_reload_reg) != new_mode)
6331 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6333 oldequiv = old, real_oldequiv = real_old;
6336 = gen_rtx (REG, new_mode,
6337 REGNO (second_reload_reg));
6343 /* If we still need a secondary reload register, check
6344 to see if it is being used as a scratch or intermediate
6345 register and generate code appropriately. If we need
6346 a scratch register, use REAL_OLDEQUIV since the form of
6347 the insn may depend on the actual address if it is
6350 if (second_reload_reg)
6352 if (icode != CODE_FOR_nothing)
6354 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6355 second_reload_reg));
6360 /* See if we need a scratch register to load the
6361 intermediate register (a tertiary reload). */
6362 enum insn_code tertiary_icode
6363 = reload_secondary_in_icode[secondary_reload];
6365 if (tertiary_icode != CODE_FOR_nothing)
6367 rtx third_reload_reg
6368 = reload_reg_rtx[reload_secondary_in_reload[secondary_reload]];
6370 emit_insn ((GEN_FCN (tertiary_icode)
6371 (second_reload_reg, real_oldequiv,
6372 third_reload_reg)));
6375 gen_reload (second_reload_reg, oldequiv,
6377 reload_when_needed[j]);
6379 oldequiv = second_reload_reg;
6385 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6386 gen_reload (reloadreg, oldequiv, reload_opnum[j],
6387 reload_when_needed[j]);
6389 #if defined(SECONDARY_INPUT_RELOAD_CLASS) && defined(PRESERVE_DEATH_INFO_REGNO_P)
6390 /* We may have to make a REG_DEAD note for the secondary reload
6391 register in the insns we just made. Find the last insn that
6392 mentioned the register. */
6393 if (! special && second_reload_reg
6394 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reload_reg)))
6398 for (prev = get_last_insn (); prev;
6399 prev = PREV_INSN (prev))
6400 if (GET_RTX_CLASS (GET_CODE (prev) == 'i')
6401 && reg_overlap_mentioned_for_reload_p (second_reload_reg,
6404 REG_NOTES (prev) = gen_rtx (EXPR_LIST, REG_DEAD,
6413 this_reload_insn = get_last_insn ();
6414 /* End this sequence. */
6415 *where = get_insns ();
6419 /* Add a note saying the input reload reg
6420 dies in this insn, if anyone cares. */
6421 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6423 && reload_reg_rtx[j] != old
6424 && reload_reg_rtx[j] != 0
6425 && reload_out[j] == 0
6426 && ! reload_inherited[j]
6427 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j])))
6429 register rtx reloadreg = reload_reg_rtx[j];
6432 /* We can't abort here because we need to support this for sched.c.
6433 It's not terrible to miss a REG_DEAD note, but we should try
6434 to figure out how to do this correctly. */
6435 /* The code below is incorrect for address-only reloads. */
6436 if (reload_when_needed[j] != RELOAD_OTHER
6437 && reload_when_needed[j] != RELOAD_FOR_INPUT)
6441 /* Add a death note to this insn, for an input reload. */
6443 if ((reload_when_needed[j] == RELOAD_OTHER
6444 || reload_when_needed[j] == RELOAD_FOR_INPUT)
6445 && ! dead_or_set_p (insn, reloadreg))
6447 = gen_rtx (EXPR_LIST, REG_DEAD,
6448 reloadreg, REG_NOTES (insn));
6451 /* When we inherit a reload, the last marked death of the reload reg
6452 may no longer really be a death. */
6453 if (reload_reg_rtx[j] != 0
6454 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j]))
6455 && reload_inherited[j])
6457 /* Handle inheriting an output reload.
6458 Remove the death note from the output reload insn. */
6459 if (reload_spill_index[j] >= 0
6460 && GET_CODE (reload_in[j]) == REG
6461 && spill_reg_store[reload_spill_index[j]] != 0
6462 && find_regno_note (spill_reg_store[reload_spill_index[j]],
6463 REG_DEAD, REGNO (reload_reg_rtx[j])))
6464 remove_death (REGNO (reload_reg_rtx[j]),
6465 spill_reg_store[reload_spill_index[j]]);
6466 /* Likewise for input reloads that were inherited. */
6467 else if (reload_spill_index[j] >= 0
6468 && GET_CODE (reload_in[j]) == REG
6469 && spill_reg_store[reload_spill_index[j]] == 0
6470 && reload_inheritance_insn[j] != 0
6471 && find_regno_note (reload_inheritance_insn[j], REG_DEAD,
6472 REGNO (reload_reg_rtx[j])))
6473 remove_death (REGNO (reload_reg_rtx[j]),
6474 reload_inheritance_insn[j]);
6479 /* We got this register from find_equiv_reg.
6480 Search back for its last death note and get rid of it.
6481 But don't search back too far.
6482 Don't go past a place where this reg is set,
6483 since a death note before that remains valid. */
6484 for (prev = PREV_INSN (insn);
6485 prev && GET_CODE (prev) != CODE_LABEL;
6486 prev = PREV_INSN (prev))
6487 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
6488 && dead_or_set_p (prev, reload_reg_rtx[j]))
6490 if (find_regno_note (prev, REG_DEAD,
6491 REGNO (reload_reg_rtx[j])))
6492 remove_death (REGNO (reload_reg_rtx[j]), prev);
6498 /* We might have used find_equiv_reg above to choose an alternate
6499 place from which to reload. If so, and it died, we need to remove
6500 that death and move it to one of the insns we just made. */
6502 if (oldequiv_reg != 0
6503 && PRESERVE_DEATH_INFO_REGNO_P (true_regnum (oldequiv_reg)))
6507 for (prev = PREV_INSN (insn); prev && GET_CODE (prev) != CODE_LABEL;
6508 prev = PREV_INSN (prev))
6509 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
6510 && dead_or_set_p (prev, oldequiv_reg))
6512 if (find_regno_note (prev, REG_DEAD, REGNO (oldequiv_reg)))
6514 for (prev1 = this_reload_insn;
6515 prev1; prev1 = PREV_INSN (prev1))
6516 if (GET_RTX_CLASS (GET_CODE (prev1) == 'i')
6517 && reg_overlap_mentioned_for_reload_p (oldequiv_reg,
6520 REG_NOTES (prev1) = gen_rtx (EXPR_LIST, REG_DEAD,
6525 remove_death (REGNO (oldequiv_reg), prev);
6532 /* If we are reloading a register that was recently stored in with an
6533 output-reload, see if we can prove there was
6534 actually no need to store the old value in it. */
6536 if (optimize && reload_inherited[j] && reload_spill_index[j] >= 0
6537 && reload_in[j] != 0
6538 && GET_CODE (reload_in[j]) == REG
6540 /* There doesn't seem to be any reason to restrict this to pseudos
6541 and doing so loses in the case where we are copying from a
6542 register of the wrong class. */
6543 && REGNO (reload_in[j]) >= FIRST_PSEUDO_REGISTER
6545 && spill_reg_store[reload_spill_index[j]] != 0
6546 /* This is unsafe if some other reload uses the same reg first. */
6547 && reload_reg_free_before_p (spill_regs[reload_spill_index[j]],
6548 reload_opnum[j], reload_when_needed[j])
6549 && dead_or_set_p (insn, reload_in[j])
6550 /* This is unsafe if operand occurs more than once in current
6551 insn. Perhaps some occurrences weren't reloaded. */
6552 && count_occurrences (PATTERN (insn), reload_in[j]) == 1)
6553 delete_output_reload (insn, j,
6554 spill_reg_store[reload_spill_index[j]]);
6556 /* Input-reloading is done. Now do output-reloading,
6557 storing the value from the reload-register after the main insn
6558 if reload_out[j] is nonzero.
6560 ??? At some point we need to support handling output reloads of
6561 JUMP_INSNs or insns that set cc0. */
6562 old = reload_out[j];
6564 && reload_reg_rtx[j] != old
6565 && reload_reg_rtx[j] != 0)
6567 register rtx reloadreg = reload_reg_rtx[j];
6568 register rtx second_reloadreg = 0;
6570 enum machine_mode mode;
6573 /* An output operand that dies right away does need a reload,
6574 but need not be copied from it. Show the new location in the
6576 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6577 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6579 XEXP (note, 0) = reload_reg_rtx[j];
6582 /* Likewise for a SUBREG of an operand that dies. */
6583 else if (GET_CODE (old) == SUBREG
6584 && GET_CODE (SUBREG_REG (old)) == REG
6585 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6588 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6592 else if (GET_CODE (old) == SCRATCH)
6593 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6594 but we don't want to make an output reload. */
6598 /* Strip off of OLD any size-increasing SUBREGs such as
6599 (SUBREG:SI foo:QI 0). */
6601 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
6602 && (GET_MODE_SIZE (GET_MODE (old))
6603 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
6604 old = SUBREG_REG (old);
6607 /* If is a JUMP_INSN, we can't support output reloads yet. */
6608 if (GET_CODE (insn) == JUMP_INSN)
6611 if (reload_when_needed[j] == RELOAD_OTHER)
6614 push_to_sequence (output_reload_insns[reload_opnum[j]]);
6616 /* Determine the mode to reload in.
6617 See comments above (for input reloading). */
6619 mode = GET_MODE (old);
6620 if (mode == VOIDmode)
6622 /* VOIDmode should never happen for an output. */
6623 if (asm_noperands (PATTERN (insn)) < 0)
6624 /* It's the compiler's fault. */
6625 fatal_insn ("VOIDmode on an output", insn);
6626 error_for_asm (insn, "output operand is constant in `asm'");
6627 /* Prevent crash--use something we know is valid. */
6629 old = gen_rtx (REG, mode, REGNO (reloadreg));
6632 if (GET_MODE (reloadreg) != mode)
6633 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
6635 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6637 /* If we need two reload regs, set RELOADREG to the intermediate
6638 one, since it will be stored into OLD. We might need a secondary
6639 register only for an input reload, so check again here. */
6641 if (reload_secondary_out_reload[j] >= 0)
6645 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6646 && reg_equiv_mem[REGNO (old)] != 0)
6647 real_old = reg_equiv_mem[REGNO (old)];
6649 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j],
6653 second_reloadreg = reloadreg;
6654 reloadreg = reload_reg_rtx[reload_secondary_out_reload[j]];
6656 /* See if RELOADREG is to be used as a scratch register
6657 or as an intermediate register. */
6658 if (reload_secondary_out_icode[j] != CODE_FOR_nothing)
6660 emit_insn ((GEN_FCN (reload_secondary_out_icode[j])
6661 (real_old, second_reloadreg, reloadreg)));
6666 /* See if we need both a scratch and intermediate reload
6669 int secondary_reload = reload_secondary_out_reload[j];
6670 enum insn_code tertiary_icode
6671 = reload_secondary_out_icode[secondary_reload];
6673 if (GET_MODE (reloadreg) != mode)
6674 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
6676 if (tertiary_icode != CODE_FOR_nothing)
6679 = reload_reg_rtx[reload_secondary_out_reload[secondary_reload]];
6682 /* Copy primary reload reg to secondary reload reg.
6683 (Note that these have been swapped above, then
6684 secondary reload reg to OLD using our insn. */
6686 /* If REAL_OLD is a paradoxical SUBREG, remove it
6687 and try to put the opposite SUBREG on
6689 if (GET_CODE (real_old) == SUBREG
6690 && (GET_MODE_SIZE (GET_MODE (real_old))
6691 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6692 && 0 != (tem = gen_lowpart_common
6693 (GET_MODE (SUBREG_REG (real_old)),
6695 real_old = SUBREG_REG (real_old), reloadreg = tem;
6697 gen_reload (reloadreg, second_reloadreg,
6698 reload_opnum[j], reload_when_needed[j]);
6699 emit_insn ((GEN_FCN (tertiary_icode)
6700 (real_old, reloadreg, third_reloadreg)));
6705 /* Copy between the reload regs here and then to
6708 gen_reload (reloadreg, second_reloadreg,
6709 reload_opnum[j], reload_when_needed[j]);
6715 /* Output the last reload insn. */
6717 gen_reload (old, reloadreg, reload_opnum[j],
6718 reload_when_needed[j]);
6720 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6721 /* If final will look at death notes for this reg,
6722 put one on the last output-reload insn to use it. Similarly
6723 for any secondary register. */
6724 if (PRESERVE_DEATH_INFO_REGNO_P (REGNO (reloadreg)))
6725 for (p = get_last_insn (); p; p = PREV_INSN (p))
6726 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
6727 && reg_overlap_mentioned_for_reload_p (reloadreg,
6729 REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
6730 reloadreg, REG_NOTES (p));
6732 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6733 if (! special && second_reloadreg
6734 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reloadreg)))
6735 for (p = get_last_insn (); p; p = PREV_INSN (p))
6736 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
6737 && reg_overlap_mentioned_for_reload_p (second_reloadreg,
6739 REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
6740 second_reloadreg, REG_NOTES (p));
6743 /* Look at all insns we emitted, just to be safe. */
6744 for (p = get_insns (); p; p = NEXT_INSN (p))
6745 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
6747 /* If this output reload doesn't come from a spill reg,
6748 clear any memory of reloaded copies of the pseudo reg.
6749 If this output reload comes from a spill reg,
6750 reg_has_output_reload will make this do nothing. */
6751 note_stores (PATTERN (p), forget_old_reloads_1);
6753 if (reg_mentioned_p (reload_reg_rtx[j], PATTERN (p))
6754 && reload_spill_index[j] >= 0)
6755 new_spill_reg_store[reload_spill_index[j]] = p;
6758 if (reload_when_needed[j] == RELOAD_OTHER)
6760 emit_insns (other_output_reload_insns[reload_opnum[j]]);
6761 other_output_reload_insns[reload_opnum[j]] = get_insns ();
6764 output_reload_insns[reload_opnum[j]] = get_insns ();
6770 /* Now write all the insns we made for reloads in the order expected by
6771 the allocation functions. Prior to the insn being reloaded, we write
6772 the following reloads:
6774 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6776 RELOAD_OTHER reloads.
6778 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6779 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6780 RELOAD_FOR_INPUT reload for the operand.
6782 RELOAD_FOR_OPADDR_ADDRS reloads.
6784 RELOAD_FOR_OPERAND_ADDRESS reloads.
6786 After the insn being reloaded, we write the following:
6788 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6789 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6790 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6791 reloads for the operand. The RELOAD_OTHER output reloads are
6792 output in descending order by reload number. */
6794 emit_insns_before (other_input_address_reload_insns, before_insn);
6795 emit_insns_before (other_input_reload_insns, before_insn);
6797 for (j = 0; j < reload_n_operands; j++)
6799 emit_insns_before (inpaddr_address_reload_insns[j], before_insn);
6800 emit_insns_before (input_address_reload_insns[j], before_insn);
6801 emit_insns_before (input_reload_insns[j], before_insn);
6804 emit_insns_before (other_operand_reload_insns, before_insn);
6805 emit_insns_before (operand_reload_insns, before_insn);
6807 for (j = 0; j < reload_n_operands; j++)
6809 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
6810 emit_insns_before (output_address_reload_insns[j], following_insn);
6811 emit_insns_before (output_reload_insns[j], following_insn);
6812 emit_insns_before (other_output_reload_insns[j], following_insn);
6815 /* Move death notes from INSN
6816 to output-operand-address and output reload insns. */
6817 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6820 /* Loop over those insns, last ones first. */
6821 for (insn1 = PREV_INSN (following_insn); insn1 != insn;
6822 insn1 = PREV_INSN (insn1))
6823 if (GET_CODE (insn1) == INSN && GET_CODE (PATTERN (insn1)) == SET)
6825 rtx source = SET_SRC (PATTERN (insn1));
6826 rtx dest = SET_DEST (PATTERN (insn1));
6828 /* The note we will examine next. */
6829 rtx reg_notes = REG_NOTES (insn);
6830 /* The place that pointed to this note. */
6831 rtx *prev_reg_note = ®_NOTES (insn);
6833 /* If the note is for something used in the source of this
6834 reload insn, or in the output address, move the note. */
6837 rtx next_reg_notes = XEXP (reg_notes, 1);
6838 if (REG_NOTE_KIND (reg_notes) == REG_DEAD
6839 && GET_CODE (XEXP (reg_notes, 0)) == REG
6840 && ((GET_CODE (dest) != REG
6841 && reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
6843 || reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
6846 *prev_reg_note = next_reg_notes;
6847 XEXP (reg_notes, 1) = REG_NOTES (insn1);
6848 REG_NOTES (insn1) = reg_notes;
6851 prev_reg_note = &XEXP (reg_notes, 1);
6853 reg_notes = next_reg_notes;
6859 /* For all the spill regs newly reloaded in this instruction,
6860 record what they were reloaded from, so subsequent instructions
6861 can inherit the reloads.
6863 Update spill_reg_store for the reloads of this insn.
6864 Copy the elements that were updated in the loop above. */
6866 for (j = 0; j < n_reloads; j++)
6868 register int r = reload_order[j];
6869 register int i = reload_spill_index[r];
6871 /* I is nonneg if this reload used one of the spill regs.
6872 If reload_reg_rtx[r] is 0, this is an optional reload
6873 that we opted to ignore. */
6875 if (i >= 0 && reload_reg_rtx[r] != 0)
6878 = HARD_REGNO_NREGS (spill_regs[i], GET_MODE (reload_reg_rtx[r]));
6880 int part_reaches_end = 0;
6881 int all_reaches_end = 1;
6883 /* For a multi register reload, we need to check if all or part
6884 of the value lives to the end. */
6885 for (k = 0; k < nr; k++)
6887 if (reload_reg_reaches_end_p (spill_regs[i] + k, reload_opnum[r],
6888 reload_when_needed[r]))
6889 part_reaches_end = 1;
6891 all_reaches_end = 0;
6894 /* Ignore reloads that don't reach the end of the insn in
6896 if (all_reaches_end)
6898 /* First, clear out memory of what used to be in this spill reg.
6899 If consecutive registers are used, clear them all. */
6901 for (k = 0; k < nr; k++)
6903 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] = -1;
6904 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = 0;
6907 /* Maybe the spill reg contains a copy of reload_out. */
6908 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
6910 register int nregno = REGNO (reload_out[r]);
6911 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6912 : HARD_REGNO_NREGS (nregno,
6913 GET_MODE (reload_reg_rtx[r])));
6915 spill_reg_store[i] = new_spill_reg_store[i];
6916 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
6918 /* If NREGNO is a hard register, it may occupy more than
6919 one register. If it does, say what is in the
6920 rest of the registers assuming that both registers
6921 agree on how many words the object takes. If not,
6922 invalidate the subsequent registers. */
6924 if (nregno < FIRST_PSEUDO_REGISTER)
6925 for (k = 1; k < nnr; k++)
6926 reg_last_reload_reg[nregno + k]
6929 reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
6930 REGNO (reload_reg_rtx[r]) + k)
6933 /* Now do the inverse operation. */
6934 for (k = 0; k < nr; k++)
6936 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
6937 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
6940 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = insn;
6944 /* Maybe the spill reg contains a copy of reload_in. Only do
6945 something if there will not be an output reload for
6946 the register being reloaded. */
6947 else if (reload_out[r] == 0
6948 && reload_in[r] != 0
6949 && ((GET_CODE (reload_in[r]) == REG
6950 && ! reg_has_output_reload[REGNO (reload_in[r])])
6951 || (GET_CODE (reload_in_reg[r]) == REG
6952 && ! reg_has_output_reload[REGNO (reload_in_reg[r])])))
6954 register int nregno;
6957 if (GET_CODE (reload_in[r]) == REG)
6958 nregno = REGNO (reload_in[r]);
6960 nregno = REGNO (reload_in_reg[r]);
6962 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6963 : HARD_REGNO_NREGS (nregno,
6964 GET_MODE (reload_reg_rtx[r])));
6966 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
6968 if (nregno < FIRST_PSEUDO_REGISTER)
6969 for (k = 1; k < nnr; k++)
6970 reg_last_reload_reg[nregno + k]
6973 reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
6974 REGNO (reload_reg_rtx[r]) + k)
6977 /* Unless we inherited this reload, show we haven't
6978 recently done a store. */
6979 if (! reload_inherited[r])
6980 spill_reg_store[i] = 0;
6982 for (k = 0; k < nr; k++)
6984 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
6985 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
6988 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]]
6994 /* However, if part of the reload reaches the end, then we must
6995 invalidate the old info for the part that survives to the end. */
6996 else if (part_reaches_end)
6998 for (k = 0; k < nr; k++)
6999 if (reload_reg_reaches_end_p (spill_regs[i] + k,
7001 reload_when_needed[r]))
7003 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] = -1;
7004 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = 0;
7009 /* The following if-statement was #if 0'd in 1.34 (or before...).
7010 It's reenabled in 1.35 because supposedly nothing else
7011 deals with this problem. */
7013 /* If a register gets output-reloaded from a non-spill register,
7014 that invalidates any previous reloaded copy of it.
7015 But forget_old_reloads_1 won't get to see it, because
7016 it thinks only about the original insn. So invalidate it here. */
7017 if (i < 0 && reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
7019 register int nregno = REGNO (reload_out[r]);
7020 if (nregno >= FIRST_PSEUDO_REGISTER)
7021 reg_last_reload_reg[nregno] = 0;
7024 int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (reload_out[r]));
7026 while (num_regs-- > 0)
7027 reg_last_reload_reg[nregno + num_regs] = 0;
7033 /* Emit code to perform a reload from IN (which may be a reload register) to
7034 OUT (which may also be a reload register). IN or OUT is from operand
7035 OPNUM with reload type TYPE.
7037 Returns first insn emitted. */
7040 gen_reload (out, in, opnum, type)
7044 enum reload_type type;
7046 rtx last = get_last_insn ();
7049 /* If IN is a paradoxical SUBREG, remove it and try to put the
7050 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7051 if (GET_CODE (in) == SUBREG
7052 && (GET_MODE_SIZE (GET_MODE (in))
7053 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7054 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7055 in = SUBREG_REG (in), out = tem;
7056 else if (GET_CODE (out) == SUBREG
7057 && (GET_MODE_SIZE (GET_MODE (out))
7058 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7059 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7060 out = SUBREG_REG (out), in = tem;
7062 /* How to do this reload can get quite tricky. Normally, we are being
7063 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7064 register that didn't get a hard register. In that case we can just
7065 call emit_move_insn.
7067 We can also be asked to reload a PLUS that adds a register or a MEM to
7068 another register, constant or MEM. This can occur during frame pointer
7069 elimination and while reloading addresses. This case is handled by
7070 trying to emit a single insn to perform the add. If it is not valid,
7071 we use a two insn sequence.
7073 Finally, we could be called to handle an 'o' constraint by putting
7074 an address into a register. In that case, we first try to do this
7075 with a named pattern of "reload_load_address". If no such pattern
7076 exists, we just emit a SET insn and hope for the best (it will normally
7077 be valid on machines that use 'o').
7079 This entire process is made complex because reload will never
7080 process the insns we generate here and so we must ensure that
7081 they will fit their constraints and also by the fact that parts of
7082 IN might be being reloaded separately and replaced with spill registers.
7083 Because of this, we are, in some sense, just guessing the right approach
7084 here. The one listed above seems to work.
7086 ??? At some point, this whole thing needs to be rethought. */
7088 if (GET_CODE (in) == PLUS
7089 && (GET_CODE (XEXP (in, 0)) == REG
7090 || GET_CODE (XEXP (in, 0)) == SUBREG
7091 || GET_CODE (XEXP (in, 0)) == MEM)
7092 && (GET_CODE (XEXP (in, 1)) == REG
7093 || GET_CODE (XEXP (in, 1)) == SUBREG
7094 || CONSTANT_P (XEXP (in, 1))
7095 || GET_CODE (XEXP (in, 1)) == MEM))
7097 /* We need to compute the sum of a register or a MEM and another
7098 register, constant, or MEM, and put it into the reload
7099 register. The best possible way of doing this is if the machine
7100 has a three-operand ADD insn that accepts the required operands.
7102 The simplest approach is to try to generate such an insn and see if it
7103 is recognized and matches its constraints. If so, it can be used.
7105 It might be better not to actually emit the insn unless it is valid,
7106 but we need to pass the insn as an operand to `recog' and
7107 `insn_extract' and it is simpler to emit and then delete the insn if
7108 not valid than to dummy things up. */
7110 rtx op0, op1, tem, insn;
7113 op0 = find_replacement (&XEXP (in, 0));
7114 op1 = find_replacement (&XEXP (in, 1));
7116 /* Since constraint checking is strict, commutativity won't be
7117 checked, so we need to do that here to avoid spurious failure
7118 if the add instruction is two-address and the second operand
7119 of the add is the same as the reload reg, which is frequently
7120 the case. If the insn would be A = B + A, rearrange it so
7121 it will be A = A + B as constrain_operands expects. */
7123 if (GET_CODE (XEXP (in, 1)) == REG
7124 && REGNO (out) == REGNO (XEXP (in, 1)))
7125 tem = op0, op0 = op1, op1 = tem;
7127 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7128 in = gen_rtx (PLUS, GET_MODE (in), op0, op1);
7130 insn = emit_insn (gen_rtx (SET, VOIDmode, out, in));
7131 code = recog_memoized (insn);
7135 insn_extract (insn);
7136 /* We want constrain operands to treat this insn strictly in
7137 its validity determination, i.e., the way it would after reload
7139 if (constrain_operands (code, 1))
7143 delete_insns_since (last);
7145 /* If that failed, we must use a conservative two-insn sequence.
7146 use move to copy constant, MEM, or pseudo register to the reload
7147 register since "move" will be able to handle an arbitrary operand,
7148 unlike add which can't, in general. Then add the registers.
7150 If there is another way to do this for a specific machine, a
7151 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7154 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7155 || (GET_CODE (op1) == REG
7156 && REGNO (op1) >= FIRST_PSEUDO_REGISTER))
7157 tem = op0, op0 = op1, op1 = tem;
7159 gen_reload (out, op0, opnum, type);
7161 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7162 This fixes a problem on the 32K where the stack pointer cannot
7163 be used as an operand of an add insn. */
7165 if (rtx_equal_p (op0, op1))
7168 insn = emit_insn (gen_add2_insn (out, op1));
7170 /* If that failed, copy the address register to the reload register.
7171 Then add the constant to the reload register. */
7173 code = recog_memoized (insn);
7177 insn_extract (insn);
7178 /* We want constrain operands to treat this insn strictly in
7179 its validity determination, i.e., the way it would after reload
7181 if (constrain_operands (code, 1))
7185 delete_insns_since (last);
7187 gen_reload (out, op1, opnum, type);
7188 emit_insn (gen_add2_insn (out, op0));
7191 #ifdef SECONDARY_MEMORY_NEEDED
7192 /* If we need a memory location to do the move, do it that way. */
7193 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7194 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7195 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7196 REGNO_REG_CLASS (REGNO (out)),
7199 /* Get the memory to use and rewrite both registers to its mode. */
7200 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7202 if (GET_MODE (loc) != GET_MODE (out))
7203 out = gen_rtx (REG, GET_MODE (loc), REGNO (out));
7205 if (GET_MODE (loc) != GET_MODE (in))
7206 in = gen_rtx (REG, GET_MODE (loc), REGNO (in));
7208 gen_reload (loc, in, opnum, type);
7209 gen_reload (out, loc, opnum, type);
7213 /* If IN is a simple operand, use gen_move_insn. */
7214 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7215 emit_insn (gen_move_insn (out, in));
7217 #ifdef HAVE_reload_load_address
7218 else if (HAVE_reload_load_address)
7219 emit_insn (gen_reload_load_address (out, in));
7222 /* Otherwise, just write (set OUT IN) and hope for the best. */
7224 emit_insn (gen_rtx (SET, VOIDmode, out, in));
7226 /* Return the first insn emitted.
7227 We can not just return get_last_insn, because there may have
7228 been multiple instructions emitted. Also note that gen_move_insn may
7229 emit more than one insn itself, so we can not assume that there is one
7230 insn emitted per emit_insn_before call. */
7232 return last ? NEXT_INSN (last) : get_insns ();
7235 /* Delete a previously made output-reload
7236 whose result we now believe is not needed.
7237 First we double-check.
7239 INSN is the insn now being processed.
7240 OUTPUT_RELOAD_INSN is the insn of the output reload.
7241 J is the reload-number for this insn. */
7244 delete_output_reload (insn, j, output_reload_insn)
7247 rtx output_reload_insn;
7251 /* Get the raw pseudo-register referred to. */
7253 rtx reg = reload_in[j];
7254 while (GET_CODE (reg) == SUBREG)
7255 reg = SUBREG_REG (reg);
7257 /* If the pseudo-reg we are reloading is no longer referenced
7258 anywhere between the store into it and here,
7259 and no jumps or labels intervene, then the value can get
7260 here through the reload reg alone.
7261 Otherwise, give up--return. */
7262 for (i1 = NEXT_INSN (output_reload_insn);
7263 i1 != insn; i1 = NEXT_INSN (i1))
7265 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7267 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7268 && reg_mentioned_p (reg, PATTERN (i1)))
7272 if (cannot_omit_stores[REGNO (reg)])
7275 /* If this insn will store in the pseudo again,
7276 the previous store can be removed. */
7277 if (reload_out[j] == reload_in[j])
7278 delete_insn (output_reload_insn);
7280 /* See if the pseudo reg has been completely replaced
7281 with reload regs. If so, delete the store insn
7282 and forget we had a stack slot for the pseudo. */
7283 else if (reg_n_deaths[REGNO (reg)] == 1
7284 && reg_basic_block[REGNO (reg)] >= 0
7285 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7289 /* We know that it was used only between here
7290 and the beginning of the current basic block.
7291 (We also know that the last use before INSN was
7292 the output reload we are thinking of deleting, but never mind that.)
7293 Search that range; see if any ref remains. */
7294 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7296 rtx set = single_set (i2);
7298 /* Uses which just store in the pseudo don't count,
7299 since if they are the only uses, they are dead. */
7300 if (set != 0 && SET_DEST (set) == reg)
7302 if (GET_CODE (i2) == CODE_LABEL
7303 || GET_CODE (i2) == JUMP_INSN)
7305 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7306 && reg_mentioned_p (reg, PATTERN (i2)))
7307 /* Some other ref remains;
7308 we can't do anything. */
7312 /* Delete the now-dead stores into this pseudo. */
7313 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7315 rtx set = single_set (i2);
7317 if (set != 0 && SET_DEST (set) == reg)
7319 /* This might be a basic block head,
7320 thus don't use delete_insn. */
7321 PUT_CODE (i2, NOTE);
7322 NOTE_SOURCE_FILE (i2) = 0;
7323 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7325 if (GET_CODE (i2) == CODE_LABEL
7326 || GET_CODE (i2) == JUMP_INSN)
7330 /* For the debugging info,
7331 say the pseudo lives in this reload reg. */
7332 reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]);
7333 alter_reg (REGNO (reg), -1);
7337 /* Output reload-insns to reload VALUE into RELOADREG.
7338 VALUE is an autoincrement or autodecrement RTX whose operand
7339 is a register or memory location;
7340 so reloading involves incrementing that location.
7342 INC_AMOUNT is the number to increment or decrement by (always positive).
7343 This cannot be deduced from VALUE. */
7346 inc_for_reload (reloadreg, value, inc_amount)
7351 /* REG or MEM to be copied and incremented. */
7352 rtx incloc = XEXP (value, 0);
7353 /* Nonzero if increment after copying. */
7354 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7360 /* No hard register is equivalent to this register after
7361 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7362 we could inc/dec that register as well (maybe even using it for
7363 the source), but I'm not sure it's worth worrying about. */
7364 if (GET_CODE (incloc) == REG)
7365 reg_last_reload_reg[REGNO (incloc)] = 0;
7367 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7368 inc_amount = - inc_amount;
7370 inc = GEN_INT (inc_amount);
7372 /* If this is post-increment, first copy the location to the reload reg. */
7374 emit_insn (gen_move_insn (reloadreg, incloc));
7376 /* See if we can directly increment INCLOC. Use a method similar to that
7379 last = get_last_insn ();
7380 add_insn = emit_insn (gen_rtx (SET, VOIDmode, incloc,
7381 gen_rtx (PLUS, GET_MODE (incloc),
7384 code = recog_memoized (add_insn);
7387 insn_extract (add_insn);
7388 if (constrain_operands (code, 1))
7390 /* If this is a pre-increment and we have incremented the value
7391 where it lives, copy the incremented value to RELOADREG to
7392 be used as an address. */
7395 emit_insn (gen_move_insn (reloadreg, incloc));
7401 delete_insns_since (last);
7403 /* If couldn't do the increment directly, must increment in RELOADREG.
7404 The way we do this depends on whether this is pre- or post-increment.
7405 For pre-increment, copy INCLOC to the reload register, increment it
7406 there, then save back. */
7410 emit_insn (gen_move_insn (reloadreg, incloc));
7411 emit_insn (gen_add2_insn (reloadreg, inc));
7412 emit_insn (gen_move_insn (incloc, reloadreg));
7417 Because this might be a jump insn or a compare, and because RELOADREG
7418 may not be available after the insn in an input reload, we must do
7419 the incrementation before the insn being reloaded for.
7421 We have already copied INCLOC to RELOADREG. Increment the copy in
7422 RELOADREG, save that back, then decrement RELOADREG so it has
7423 the original value. */
7425 emit_insn (gen_add2_insn (reloadreg, inc));
7426 emit_insn (gen_move_insn (incloc, reloadreg));
7427 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7433 /* Return 1 if we are certain that the constraint-string STRING allows
7434 the hard register REG. Return 0 if we can't be sure of this. */
7437 constraint_accepts_reg_p (string, reg)
7442 int regno = true_regnum (reg);
7445 /* Initialize for first alternative. */
7447 /* Check that each alternative contains `g' or `r'. */
7449 switch (c = *string++)
7452 /* If an alternative lacks `g' or `r', we lose. */
7455 /* If an alternative lacks `g' or `r', we lose. */
7458 /* Initialize for next alternative. */
7463 /* Any general reg wins for this alternative. */
7464 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7468 /* Any reg in specified class wins for this alternative. */
7470 enum reg_class class = REG_CLASS_FROM_LETTER (c);
7472 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
7478 /* Return the number of places FIND appears within X, but don't count
7479 an occurrence if some SET_DEST is FIND. */
7482 count_occurrences (x, find)
7483 register rtx x, find;
7486 register enum rtx_code code;
7487 register char *format_ptr;
7495 code = GET_CODE (x);
7510 if (SET_DEST (x) == find)
7511 return count_occurrences (SET_SRC (x), find);
7515 format_ptr = GET_RTX_FORMAT (code);
7518 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7520 switch (*format_ptr++)
7523 count += count_occurrences (XEXP (x, i), find);
7527 if (XVEC (x, i) != NULL)
7529 for (j = 0; j < XVECLEN (x, i); j++)
7530 count += count_occurrences (XVECEXP (x, i, j), find);
7538 /* This array holds values which are equivalent to a hard register
7539 during reload_cse_regs. Each array element is an EXPR_LIST of
7540 values. Each time a hard register is set, we set the corresponding
7541 array element to the value. Each time a hard register is copied
7542 into memory, we add the memory location to the corresponding array
7543 element. We don't store values or memory addresses with side
7544 effects in this array.
7546 If the value is a CONST_INT, then the mode of the containing
7547 EXPR_LIST is the mode in which that CONST_INT was referenced.
7549 We sometimes clobber a specific entry in a list. In that case, we
7550 just set XEXP (list-entry, 0) to 0. */
7552 static rtx *reg_values;
7554 /* This is a preallocated REG rtx which we use as a temporary in
7555 reload_cse_invalidate_regno, so that we don't need to allocate a
7556 new one each time through a loop in that function. */
7558 static rtx invalidate_regno_rtx;
7560 /* Invalidate any entries in reg_values which depend on REGNO,
7561 including those for REGNO itself. This is called if REGNO is
7562 changing. If CLOBBER is true, then always forget anything we
7563 currently know about REGNO. MODE is the mode of the assignment to
7564 REGNO, which is used to determine how many hard registers are being
7565 changed. If MODE is VOIDmode, then only REGNO is being changed;
7566 this is used when invalidating call clobbered registers across a
7570 reload_cse_invalidate_regno (regno, mode, clobber)
7572 enum machine_mode mode;
7578 /* Our callers don't always go through true_regnum; we may see a
7579 pseudo-register here from a CLOBBER or the like. We probably
7580 won't ever see a pseudo-register that has a real register number,
7581 for we check anyhow for safety. */
7582 if (regno >= FIRST_PSEUDO_REGISTER)
7583 regno = reg_renumber[regno];
7587 if (mode == VOIDmode)
7588 endregno = regno + 1;
7590 endregno = regno + HARD_REGNO_NREGS (regno, mode);
7593 for (i = regno; i < endregno; i++)
7596 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
7600 for (x = reg_values[i]; x; x = XEXP (x, 1))
7602 if (XEXP (x, 0) != 0
7603 && refers_to_regno_p (regno, endregno, XEXP (x, 0), NULL_RTX))
7605 /* If this is the only entry on the list, clear
7606 reg_values[i]. Otherwise, just clear this entry on
7608 if (XEXP (x, 1) == 0 && x == reg_values[i])
7618 /* We must look at earlier registers, in case REGNO is part of a
7619 multi word value but is not the first register. If an earlier
7620 register has a value in a mode which overlaps REGNO, then we must
7621 invalidate that earlier register. Note that we do not need to
7622 check REGNO or later registers (we must not check REGNO itself,
7623 because we would incorrectly conclude that there was a conflict). */
7625 for (i = 0; i < regno; i++)
7629 for (x = reg_values[i]; x; x = XEXP (x, 1))
7631 if (XEXP (x, 0) != 0)
7633 PUT_MODE (invalidate_regno_rtx, GET_MODE (XEXP (x, 0)));
7634 REGNO (invalidate_regno_rtx) = i;
7635 if (refers_to_regno_p (regno, endregno, invalidate_regno_rtx,
7638 reload_cse_invalidate_regno (i, VOIDmode, 1);
7646 /* The memory at address (plus MEM_BASE MEM_OFFSET), where MEM_OFFSET
7647 is a CONST_INT, is being changed. MEM_MODE is the mode of the
7648 memory reference. Return whether this change will invalidate VAL. */
7651 reload_cse_mem_conflict_p (mem_base, mem_offset, mem_mode, val)
7654 enum machine_mode mem_mode;
7661 code = GET_CODE (val);
7664 /* Get rid of a few simple cases quickly. */
7679 rtx val_base, val_offset;
7681 if (mem_mode == BLKmode || GET_MODE (val) == BLKmode)
7684 val_offset = const0_rtx;
7685 val_base = eliminate_constant_term (XEXP (val, 0), &val_offset);
7687 /* If MEM_BASE and VAL_BASE are the same, but the offsets do
7688 not overlap, then we do not have a conflict on this MEM.
7689 For complete safety, we still need to check that VAL_BASE
7690 itself does not contain an overlapping MEM.
7692 We can't simplify the check to just OFFSET + SIZE <=
7693 OTHER_OFFSET, because SIZE might cause OFFSET to wrap from
7694 positive to negative. If we used unsigned arithmetic, we
7695 would have the same problem wrapping around zero. */
7697 if (rtx_equal_p (mem_base, val_base)
7698 && ((INTVAL (mem_offset) < INTVAL (val_offset)
7699 && (INTVAL (mem_offset) + GET_MODE_SIZE (mem_mode)
7700 <= INTVAL (val_offset)))
7701 || (INTVAL (val_offset) < INTVAL (mem_offset)
7702 && (INTVAL (val_offset) + GET_MODE_SIZE (GET_MODE (val))
7703 <= INTVAL (mem_offset)))))
7704 return reload_cse_mem_conflict_p (mem_base, mem_offset, mem_mode,
7714 fmt = GET_RTX_FORMAT (code);
7716 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7720 if (reload_cse_mem_conflict_p (mem_base, mem_offset, mem_mode,
7724 else if (fmt[i] == 'E')
7728 for (j = 0; j < XVECLEN (val, i); j++)
7729 if (reload_cse_mem_conflict_p (mem_base, mem_offset, mem_mode,
7730 XVECEXP (val, i, j)))
7738 /* Invalidate any entries in reg_values which are changed because of a
7739 store to MEM_RTX. If this is called because of a non-const call
7740 instruction, MEM_RTX is (mem:BLK const0_rtx). */
7743 reload_cse_invalidate_mem (mem_rtx)
7747 rtx mem_base, mem_offset;
7748 enum machine_mode mem_mode;
7750 /* We detect certain cases where memory addresses can not conflict:
7751 if they use the same register, and the offsets do not overlap. */
7753 mem_offset = const0_rtx;
7754 mem_base = eliminate_constant_term (XEXP (mem_rtx, 0), &mem_offset);
7755 mem_mode = GET_MODE (mem_rtx);
7757 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
7761 for (x = reg_values[i]; x; x = XEXP (x, 1))
7763 if (XEXP (x, 0) != 0
7764 && reload_cse_mem_conflict_p (mem_base, mem_offset, mem_mode,
7767 /* If this is the only entry on the list, clear
7768 reg_values[i]. Otherwise, just clear this entry on
7770 if (XEXP (x, 1) == 0 && x == reg_values[i])
7781 /* Invalidate DEST, which is being assigned to or clobbered. The
7782 second parameter exists so that this function can be passed to
7783 note_stores; it is ignored. */
7786 reload_cse_invalidate_rtx (dest, ignore)
7790 while (GET_CODE (dest) == STRICT_LOW_PART
7791 || GET_CODE (dest) == SIGN_EXTRACT
7792 || GET_CODE (dest) == ZERO_EXTRACT
7793 || GET_CODE (dest) == SUBREG)
7794 dest = XEXP (dest, 0);
7796 if (GET_CODE (dest) == REG)
7797 reload_cse_invalidate_regno (REGNO (dest), GET_MODE (dest), 1);
7798 else if (GET_CODE (dest) == MEM)
7799 reload_cse_invalidate_mem (dest);
7802 /* Do a very simple CSE pass over the hard registers.
7804 This function detects no-op moves where we happened to assign two
7805 different pseudo-registers to the same hard register, and then
7806 copied one to the other. Reload will generate a useless
7807 instruction copying a register to itself.
7809 This function also detects cases where we load a value from memory
7810 into two different registers, and (if memory is more expensive than
7811 registers) changes it to simply copy the first register into the
7815 reload_cse_regs (first)
7823 reg_values = (rtx *) alloca (FIRST_PSEUDO_REGISTER * sizeof (rtx));
7824 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
7827 /* Create our EXPR_LIST structures on reload_obstack, so that we can
7828 free them when we are done. */
7829 push_obstacks (&reload_obstack, &reload_obstack);
7830 firstobj = (char *) obstack_alloc (&reload_obstack, 0);
7832 /* We pass this to reload_cse_invalidate_mem to invalidate all of
7833 memory for a non-const call instruction. */
7834 callmem = gen_rtx (MEM, BLKmode, const0_rtx);
7836 /* This is used in reload_cse_invalidate_regno to avoid consing a
7837 new REG in a loop in that function. */
7838 invalidate_regno_rtx = gen_rtx (REG, VOIDmode, 0);
7840 for (insn = first; insn; insn = NEXT_INSN (insn))
7844 if (GET_CODE (insn) == CODE_LABEL)
7846 /* Forget all the register values at a code label. We don't
7847 try to do anything clever around jumps. */
7848 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
7854 #ifdef NON_SAVING_SETJMP
7855 if (NON_SAVING_SETJMP && GET_CODE (insn) == NOTE
7856 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
7858 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
7865 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
7868 /* If this is a call instruction, forget anything stored in a
7869 call clobbered register, or, if this is not a const call, in
7871 if (GET_CODE (insn) == CALL_INSN)
7873 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
7874 if (call_used_regs[i])
7875 reload_cse_invalidate_regno (i, VOIDmode, 1);
7877 if (! CONST_CALL_P (insn))
7878 reload_cse_invalidate_mem (callmem);
7881 body = PATTERN (insn);
7882 if (GET_CODE (body) == SET)
7884 if (reload_cse_noop_set_p (body, insn))
7886 PUT_CODE (insn, NOTE);
7887 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
7888 NOTE_SOURCE_FILE (insn) = 0;
7890 /* We're done with this insn. */
7894 reload_cse_simplify_set (body, insn);
7895 reload_cse_record_set (body, body);
7897 else if (GET_CODE (body) == PARALLEL)
7901 /* If every action in a PARALLEL is a noop, we can delete
7902 the entire PARALLEL. */
7903 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
7904 if (GET_CODE (XVECEXP (body, 0, i)) != SET
7905 || ! reload_cse_noop_set_p (XVECEXP (body, 0, i), insn))
7909 PUT_CODE (insn, NOTE);
7910 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
7911 NOTE_SOURCE_FILE (insn) = 0;
7913 /* We're done with this insn. */
7917 /* Look through the PARALLEL and record the values being
7918 set, if possible. Also handle any CLOBBERs. */
7919 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
7921 rtx x = XVECEXP (body, 0, i);
7923 if (GET_CODE (x) == SET)
7924 reload_cse_record_set (x, body);
7926 note_stores (x, reload_cse_invalidate_rtx);
7930 note_stores (body, reload_cse_invalidate_rtx);
7933 /* Clobber any registers which appear in REG_INC notes. We
7934 could keep track of the changes to their values, but it is
7935 unlikely to help. */
7939 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
7940 if (REG_NOTE_KIND (x) == REG_INC)
7941 reload_cse_invalidate_rtx (XEXP (x, 0), NULL_RTX);
7945 /* Look for any CLOBBERs in CALL_INSN_FUNCTION_USAGE, but only
7946 after we have processed the insn. */
7947 if (GET_CODE (insn) == CALL_INSN)
7951 for (x = CALL_INSN_FUNCTION_USAGE (insn); x; x = XEXP (x, 1))
7952 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
7953 reload_cse_invalidate_rtx (XEXP (XEXP (x, 0), 0), NULL_RTX);
7957 /* Free all the temporary structures we created, and go back to the
7958 regular obstacks. */
7959 obstack_free (&reload_obstack, firstobj);
7963 /* Return whether the values known for REGNO are equal to VAL. MODE
7964 is the mode of the object that VAL is being copied to; this matters
7965 if VAL is a CONST_INT. */
7968 reload_cse_regno_equal_p (regno, val, mode)
7971 enum machine_mode mode;
7978 for (x = reg_values[regno]; x; x = XEXP (x, 1))
7979 if (XEXP (x, 0) != 0
7980 && rtx_equal_p (XEXP (x, 0), val)
7981 && (GET_CODE (val) != CONST_INT
7982 || mode == GET_MODE (x)
7983 || (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
7984 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
7985 GET_MODE_BITSIZE (GET_MODE (x))))))
7991 /* See whether a single set is a noop. SET is the set instruction we
7992 are should check, and INSN is the instruction from which it came. */
7995 reload_cse_noop_set_p (set, insn)
8000 enum machine_mode dest_mode;
8004 src = SET_SRC (set);
8005 dest = SET_DEST (set);
8006 dest_mode = GET_MODE (dest);
8008 if (side_effects_p (src))
8011 dreg = true_regnum (dest);
8012 sreg = true_regnum (src);
8014 /* Check for setting a register to itself. In this case, we don't
8015 have to worry about REG_DEAD notes. */
8016 if (dreg >= 0 && dreg == sreg)
8022 /* Check for setting a register to itself. */
8026 /* Check for setting a register to a value which we already know
8027 is in the register. */
8028 else if (reload_cse_regno_equal_p (dreg, src, dest_mode))
8031 /* Check for setting a register DREG to another register SREG
8032 where SREG is equal to a value which is already in DREG. */
8037 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
8039 if (XEXP (x, 0) != 0
8040 && reload_cse_regno_equal_p (dreg, XEXP (x, 0), dest_mode))
8048 else if (GET_CODE (dest) == MEM)
8050 /* Check for storing a register to memory when we know that the
8051 register is equivalent to the memory location. */
8053 && reload_cse_regno_equal_p (sreg, dest, dest_mode)
8054 && ! side_effects_p (dest))
8058 /* If we can delete this SET, then we need to look for an earlier
8059 REG_DEAD note on DREG, and remove it if it exists. */
8062 if (! find_regno_note (insn, REG_UNUSED, dreg))
8066 for (trial = prev_nonnote_insn (insn);
8068 && GET_CODE (trial) != CODE_LABEL
8069 && GET_CODE (trial) != BARRIER);
8070 trial = prev_nonnote_insn (trial))
8072 if (find_regno_note (trial, REG_DEAD, dreg))
8074 remove_death (dreg, trial);
8084 /* Try to simplify a single SET instruction. SET is the set pattern.
8085 INSN is the instruction it came from. */
8088 reload_cse_simplify_set (set, insn)
8094 enum machine_mode dest_mode;
8095 enum reg_class dclass;
8098 /* We only handle one case: if we set a register to a value which is
8099 not a register, we try to find that value in some other register
8100 and change the set into a register copy. */
8102 dreg = true_regnum (SET_DEST (set));
8106 src = SET_SRC (set);
8107 if (side_effects_p (src) || true_regnum (src) >= 0)
8110 /* If memory loads are cheaper than register copies, don't change
8112 if (GET_CODE (src) == MEM && MEMORY_MOVE_COST (GET_MODE (src)) < 2)
8115 dest_mode = GET_MODE (SET_DEST (set));
8116 dclass = REGNO_REG_CLASS (dreg);
8117 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8120 && REGISTER_MOVE_COST (REGNO_REG_CLASS (i), dclass) == 2
8121 && reload_cse_regno_equal_p (i, src, dest_mode))
8125 /* Pop back to the real obstacks while changing the insn. */
8128 validated = validate_change (insn, &SET_SRC (set),
8129 gen_rtx (REG, dest_mode, i), 0);
8131 /* Go back to the obstack we are using for temporary
8133 push_obstacks (&reload_obstack, &reload_obstack);
8137 /* We need to look for an earlier REG_DEAD note on I,
8138 and remove it if it exists. */
8139 if (! find_regno_note (insn, REG_UNUSED, i))
8143 for (trial = prev_nonnote_insn (insn);
8145 && GET_CODE (trial) != CODE_LABEL
8146 && GET_CODE (trial) != BARRIER);
8147 trial = prev_nonnote_insn (trial))
8149 if (find_regno_note (trial, REG_DEAD, i))
8151 remove_death (i, trial);
8163 /* These two variables are used to pass information from
8164 reload_cse_record_set to reload_cse_check_clobber. */
8166 static int reload_cse_check_clobbered;
8167 static rtx reload_cse_check_src;
8169 /* See if DEST overlaps with RELOAD_CSE_CHECK_SRC. If it does, set
8170 RELOAD_CSE_CHECK_CLOBBERED. This is called via note_stores. The
8171 second argument, which is passed by note_stores, is ignored. */
8174 reload_cse_check_clobber (dest, ignore)
8178 if (reg_overlap_mentioned_p (dest, reload_cse_check_src))
8179 reload_cse_check_clobbered = 1;
8182 /* Record the result of a SET instruction. SET is the set pattern.
8183 BODY is the pattern of the insn that it came from. */
8186 reload_cse_record_set (set, body)
8192 enum machine_mode dest_mode;
8194 dest = SET_DEST (set);
8195 src = SET_SRC (set);
8196 dreg = true_regnum (dest);
8197 sreg = true_regnum (src);
8198 dest_mode = GET_MODE (dest);
8200 /* We can only handle an assignment to a register, or a store of a
8201 register to a memory location. For other cases, we just clobber
8202 the destination. We also have to just clobber if there are side
8203 effects in SRC or DEST. */
8204 if ((dreg < 0 && GET_CODE (dest) != MEM)
8205 || side_effects_p (src)
8206 || side_effects_p (dest))
8208 reload_cse_invalidate_rtx (dest, NULL_RTX);
8213 /* We don't try to handle values involving CC, because it's a pain
8214 to keep track of when they have to be invalidated. */
8215 if (reg_mentioned_p (cc0_rtx, src)
8216 || reg_mentioned_p (cc0_rtx, dest))
8218 reload_cse_invalidate_rtx (dest, NULL_RTX);
8223 /* If BODY is a PARALLEL, then we need to see whether the source of
8224 SET is clobbered by some other instruction in the PARALLEL. */
8225 if (GET_CODE (body) == PARALLEL)
8229 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8233 x = XVECEXP (body, 0, i);
8237 reload_cse_check_clobbered = 0;
8238 reload_cse_check_src = src;
8239 note_stores (x, reload_cse_check_clobber);
8240 if (reload_cse_check_clobbered)
8242 reload_cse_invalidate_rtx (dest, NULL_RTX);
8252 /* This is an assignment to a register. Update the value we
8253 have stored for the register. */
8258 /* This is a copy from one register to another. Any values
8259 which were valid for SREG are now valid for DREG. If the
8260 mode changes, we use gen_lowpart_common to extract only
8261 the part of the value that is copied. */
8262 reg_values[dreg] = 0;
8263 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
8267 if (XEXP (x, 0) == 0)
8269 if (dest_mode == GET_MODE (XEXP (x, 0)))
8272 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
8274 reg_values[dreg] = gen_rtx (EXPR_LIST, dest_mode, tmp,
8279 reg_values[dreg] = gen_rtx (EXPR_LIST, dest_mode, src, NULL_RTX);
8281 /* We've changed DREG, so invalidate any values held by other
8282 registers that depend upon it. */
8283 reload_cse_invalidate_regno (dreg, dest_mode, 0);
8285 /* If this assignment changes more than one hard register,
8286 forget anything we know about the others. */
8287 for (i = 1; i < HARD_REGNO_NREGS (dreg, dest_mode); i++)
8288 reg_values[dreg + i] = 0;
8290 else if (GET_CODE (dest) == MEM)
8292 /* Invalidate conflicting memory locations. */
8293 reload_cse_invalidate_mem (dest);
8295 /* If we're storing a register to memory, add DEST to the list
8297 if (sreg >= 0 && ! side_effects_p (dest))
8298 reg_values[sreg] = gen_rtx (EXPR_LIST, dest_mode, dest,
8303 /* We should have bailed out earlier. */
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