1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx *reg_equiv_memory_loc;
105 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
106 collector can keep track of what is inside. */
107 varray_type reg_equiv_memory_loc_varray;
109 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
110 This is used when the address is not valid as a memory address
111 (because its displacement is too big for the machine.) */
112 rtx *reg_equiv_address;
114 /* Element N is the memory slot to which pseudo reg N is equivalent,
115 or zero if pseudo reg N is not equivalent to a memory slot. */
118 /* Widest width in which each pseudo reg is referred to (via subreg). */
119 static unsigned int *reg_max_ref_width;
121 /* Element N is the list of insns that initialized reg N from its equivalent
122 constant or memory slot. */
123 static rtx *reg_equiv_init;
125 /* Vector to remember old contents of reg_renumber before spilling. */
126 static short *reg_old_renumber;
128 /* During reload_as_needed, element N contains the last pseudo regno reloaded
129 into hard register N. If that pseudo reg occupied more than one register,
130 reg_reloaded_contents points to that pseudo for each spill register in
131 use; all of these must remain set for an inheritance to occur. */
132 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
134 /* During reload_as_needed, element N contains the insn for which
135 hard register N was last used. Its contents are significant only
136 when reg_reloaded_valid is set for this register. */
137 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
139 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
140 static HARD_REG_SET reg_reloaded_valid;
141 /* Indicate if the register was dead at the end of the reload.
142 This is only valid if reg_reloaded_contents is set and valid. */
143 static HARD_REG_SET reg_reloaded_dead;
145 /* Indicate whether the register's current value is one that is not
146 safe to retain across a call, even for registers that are normally
148 static HARD_REG_SET reg_reloaded_call_part_clobbered;
150 /* Number of spill-regs so far; number of valid elements of spill_regs. */
153 /* In parallel with spill_regs, contains REG rtx's for those regs.
154 Holds the last rtx used for any given reg, or 0 if it has never
155 been used for spilling yet. This rtx is reused, provided it has
157 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
159 /* In parallel with spill_regs, contains nonzero for a spill reg
160 that was stored after the last time it was used.
161 The precise value is the insn generated to do the store. */
162 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
164 /* This is the register that was stored with spill_reg_store. This is a
165 copy of reload_out / reload_out_reg when the value was stored; if
166 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
167 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
169 /* This table is the inverse mapping of spill_regs:
170 indexed by hard reg number,
171 it contains the position of that reg in spill_regs,
172 or -1 for something that is not in spill_regs.
174 ?!? This is no longer accurate. */
175 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
177 /* This reg set indicates registers that can't be used as spill registers for
178 the currently processed insn. These are the hard registers which are live
179 during the insn, but not allocated to pseudos, as well as fixed
181 static HARD_REG_SET bad_spill_regs;
183 /* These are the hard registers that can't be used as spill register for any
184 insn. This includes registers used for user variables and registers that
185 we can't eliminate. A register that appears in this set also can't be used
186 to retry register allocation. */
187 static HARD_REG_SET bad_spill_regs_global;
189 /* Describes order of use of registers for reloading
190 of spilled pseudo-registers. `n_spills' is the number of
191 elements that are actually valid; new ones are added at the end.
193 Both spill_regs and spill_reg_order are used on two occasions:
194 once during find_reload_regs, where they keep track of the spill registers
195 for a single insn, but also during reload_as_needed where they show all
196 the registers ever used by reload. For the latter case, the information
197 is calculated during finish_spills. */
198 static short spill_regs[FIRST_PSEUDO_REGISTER];
200 /* This vector of reg sets indicates, for each pseudo, which hard registers
201 may not be used for retrying global allocation because the register was
202 formerly spilled from one of them. If we allowed reallocating a pseudo to
203 a register that it was already allocated to, reload might not
205 static HARD_REG_SET *pseudo_previous_regs;
207 /* This vector of reg sets indicates, for each pseudo, which hard
208 registers may not be used for retrying global allocation because they
209 are used as spill registers during one of the insns in which the
211 static HARD_REG_SET *pseudo_forbidden_regs;
213 /* All hard regs that have been used as spill registers for any insn are
214 marked in this set. */
215 static HARD_REG_SET used_spill_regs;
217 /* Index of last register assigned as a spill register. We allocate in
218 a round-robin fashion. */
219 static int last_spill_reg;
221 /* Nonzero if indirect addressing is supported on the machine; this means
222 that spilling (REG n) does not require reloading it into a register in
223 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
224 value indicates the level of indirect addressing supported, e.g., two
225 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
227 static char spill_indirect_levels;
229 /* Nonzero if indirect addressing is supported when the innermost MEM is
230 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
231 which these are valid is the same as spill_indirect_levels, above. */
232 char indirect_symref_ok;
234 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
235 char double_reg_address_ok;
237 /* Record the stack slot for each spilled hard register. */
238 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
240 /* Width allocated so far for that stack slot. */
241 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
243 /* Record which pseudos needed to be spilled. */
244 static regset_head spilled_pseudos;
246 /* Used for communication between order_regs_for_reload and count_pseudo.
247 Used to avoid counting one pseudo twice. */
248 static regset_head pseudos_counted;
250 /* First uid used by insns created by reload in this function.
251 Used in find_equiv_reg. */
252 int reload_first_uid;
254 /* Flag set by local-alloc or global-alloc if anything is live in
255 a call-clobbered reg across calls. */
256 int caller_save_needed;
258 /* Set to 1 while reload_as_needed is operating.
259 Required by some machines to handle any generated moves differently. */
260 int reload_in_progress = 0;
262 /* These arrays record the insn_code of insns that may be needed to
263 perform input and output reloads of special objects. They provide a
264 place to pass a scratch register. */
265 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
266 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
268 /* This obstack is used for allocation of rtl during register elimination.
269 The allocated storage can be freed once find_reloads has processed the
271 static struct obstack reload_obstack;
273 /* Points to the beginning of the reload_obstack. All insn_chain structures
274 are allocated first. */
275 static char *reload_startobj;
277 /* The point after all insn_chain structures. Used to quickly deallocate
278 memory allocated in copy_reloads during calculate_needs_all_insns. */
279 static char *reload_firstobj;
281 /* This points before all local rtl generated by register elimination.
282 Used to quickly free all memory after processing one insn. */
283 static char *reload_insn_firstobj;
285 /* List of insn_chain instructions, one for every insn that reload needs to
287 struct insn_chain *reload_insn_chain;
289 /* List of all insns needing reloads. */
290 static struct insn_chain *insns_need_reload;
292 /* This structure is used to record information about register eliminations.
293 Each array entry describes one possible way of eliminating a register
294 in favor of another. If there is more than one way of eliminating a
295 particular register, the most preferred should be specified first. */
299 int from; /* Register number to be eliminated. */
300 int to; /* Register number used as replacement. */
301 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
302 int can_eliminate; /* Nonzero if this elimination can be done. */
303 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
304 insns made by reload. */
305 HOST_WIDE_INT offset; /* Current offset between the two regs. */
306 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
307 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
308 rtx from_rtx; /* REG rtx for the register to be eliminated.
309 We cannot simply compare the number since
310 we might then spuriously replace a hard
311 register corresponding to a pseudo
312 assigned to the reg to be eliminated. */
313 rtx to_rtx; /* REG rtx for the replacement. */
316 static struct elim_table *reg_eliminate = 0;
318 /* This is an intermediate structure to initialize the table. It has
319 exactly the members provided by ELIMINABLE_REGS. */
320 static const struct elim_table_1
324 } reg_eliminate_1[] =
326 /* If a set of eliminable registers was specified, define the table from it.
327 Otherwise, default to the normal case of the frame pointer being
328 replaced by the stack pointer. */
330 #ifdef ELIMINABLE_REGS
333 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
336 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
338 /* Record the number of pending eliminations that have an offset not equal
339 to their initial offset. If nonzero, we use a new copy of each
340 replacement result in any insns encountered. */
341 int num_not_at_initial_offset;
343 /* Count the number of registers that we may be able to eliminate. */
344 static int num_eliminable;
345 /* And the number of registers that are equivalent to a constant that
346 can be eliminated to frame_pointer / arg_pointer + constant. */
347 static int num_eliminable_invariants;
349 /* For each label, we record the offset of each elimination. If we reach
350 a label by more than one path and an offset differs, we cannot do the
351 elimination. This information is indexed by the difference of the
352 number of the label and the first label number. We can't offset the
353 pointer itself as this can cause problems on machines with segmented
354 memory. The first table is an array of flags that records whether we
355 have yet encountered a label and the second table is an array of arrays,
356 one entry in the latter array for each elimination. */
358 static int first_label_num;
359 static char *offsets_known_at;
360 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
362 /* Number of labels in the current function. */
364 static int num_labels;
366 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
367 static void maybe_fix_stack_asms (void);
368 static void copy_reloads (struct insn_chain *);
369 static void calculate_needs_all_insns (int);
370 static int find_reg (struct insn_chain *, int);
371 static void find_reload_regs (struct insn_chain *);
372 static void select_reload_regs (void);
373 static void delete_caller_save_insns (void);
375 static void spill_failure (rtx, enum reg_class);
376 static void count_spilled_pseudo (int, int, int);
377 static void delete_dead_insn (rtx);
378 static void alter_reg (int, int);
379 static void set_label_offsets (rtx, rtx, int);
380 static void check_eliminable_occurrences (rtx);
381 static void elimination_effects (rtx, enum machine_mode);
382 static int eliminate_regs_in_insn (rtx, int);
383 static void update_eliminable_offsets (void);
384 static void mark_not_eliminable (rtx, rtx, void *);
385 static void set_initial_elim_offsets (void);
386 static void verify_initial_elim_offsets (void);
387 static void set_initial_label_offsets (void);
388 static void set_offsets_for_label (rtx);
389 static void init_elim_table (void);
390 static void update_eliminables (HARD_REG_SET *);
391 static void spill_hard_reg (unsigned int, int);
392 static int finish_spills (int);
393 static void scan_paradoxical_subregs (rtx);
394 static void count_pseudo (int);
395 static void order_regs_for_reload (struct insn_chain *);
396 static void reload_as_needed (int);
397 static void forget_old_reloads_1 (rtx, rtx, void *);
398 static int reload_reg_class_lower (const void *, const void *);
399 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
401 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
403 static int reload_reg_free_p (unsigned int, int, enum reload_type);
404 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
406 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
408 static int function_invariant_p (rtx);
409 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
410 static int allocate_reload_reg (struct insn_chain *, int, int);
411 static int conflicts_with_override (rtx);
412 static void failed_reload (rtx, int);
413 static int set_reload_reg (int, int);
414 static void choose_reload_regs_init (struct insn_chain *, rtx *);
415 static void choose_reload_regs (struct insn_chain *);
416 static void merge_assigned_reloads (rtx);
417 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
419 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
421 static void do_input_reload (struct insn_chain *, struct reload *, int);
422 static void do_output_reload (struct insn_chain *, struct reload *, int);
423 static bool inherit_piecemeal_p (int, int);
424 static void emit_reload_insns (struct insn_chain *);
425 static void delete_output_reload (rtx, int, int);
426 static void delete_address_reloads (rtx, rtx);
427 static void delete_address_reloads_1 (rtx, rtx, rtx);
428 static rtx inc_for_reload (rtx, rtx, rtx, int);
430 static void add_auto_inc_notes (rtx, rtx);
432 static void copy_eh_notes (rtx, rtx);
433 static int reloads_conflict (int, int);
434 static rtx gen_reload (rtx, rtx, int, enum reload_type);
436 /* Initialize the reload pass once per compilation. */
443 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
444 Set spill_indirect_levels to the number of levels such addressing is
445 permitted, zero if it is not permitted at all. */
448 = gen_rtx_MEM (Pmode,
451 LAST_VIRTUAL_REGISTER + 1),
453 spill_indirect_levels = 0;
455 while (memory_address_p (QImode, tem))
457 spill_indirect_levels++;
458 tem = gen_rtx_MEM (Pmode, tem);
461 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
463 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
464 indirect_symref_ok = memory_address_p (QImode, tem);
466 /* See if reg+reg is a valid (and offsettable) address. */
468 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
470 tem = gen_rtx_PLUS (Pmode,
471 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
472 gen_rtx_REG (Pmode, i));
474 /* This way, we make sure that reg+reg is an offsettable address. */
475 tem = plus_constant (tem, 4);
477 if (memory_address_p (QImode, tem))
479 double_reg_address_ok = 1;
484 /* Initialize obstack for our rtl allocation. */
485 gcc_obstack_init (&reload_obstack);
486 reload_startobj = obstack_alloc (&reload_obstack, 0);
488 INIT_REG_SET (&spilled_pseudos);
489 INIT_REG_SET (&pseudos_counted);
490 VARRAY_RTX_INIT (reg_equiv_memory_loc_varray, 0, "reg_equiv_memory_loc");
493 /* List of insn chains that are currently unused. */
494 static struct insn_chain *unused_insn_chains = 0;
496 /* Allocate an empty insn_chain structure. */
498 new_insn_chain (void)
500 struct insn_chain *c;
502 if (unused_insn_chains == 0)
504 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
505 INIT_REG_SET (&c->live_throughout);
506 INIT_REG_SET (&c->dead_or_set);
510 c = unused_insn_chains;
511 unused_insn_chains = c->next;
513 c->is_caller_save_insn = 0;
514 c->need_operand_change = 0;
520 /* Small utility function to set all regs in hard reg set TO which are
521 allocated to pseudos in regset FROM. */
524 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
527 reg_set_iterator rsi;
529 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
531 int r = reg_renumber[regno];
536 /* reload_combine uses the information from
537 BASIC_BLOCK->global_live_at_start, which might still
538 contain registers that have not actually been allocated
539 since they have an equivalence. */
540 gcc_assert (reload_completed);
544 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)];
546 SET_HARD_REG_BIT (*to, r + nregs);
551 /* Replace all pseudos found in LOC with their corresponding
555 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
568 unsigned int regno = REGNO (x);
570 if (regno < FIRST_PSEUDO_REGISTER)
573 x = eliminate_regs (x, mem_mode, usage);
577 replace_pseudos_in (loc, mem_mode, usage);
581 if (reg_equiv_constant[regno])
582 *loc = reg_equiv_constant[regno];
583 else if (reg_equiv_mem[regno])
584 *loc = reg_equiv_mem[regno];
585 else if (reg_equiv_address[regno])
586 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
589 gcc_assert (!REG_P (regno_reg_rtx[regno])
590 || REGNO (regno_reg_rtx[regno]) != regno);
591 *loc = regno_reg_rtx[regno];
596 else if (code == MEM)
598 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
602 /* Process each of our operands recursively. */
603 fmt = GET_RTX_FORMAT (code);
604 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
606 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
607 else if (*fmt == 'E')
608 for (j = 0; j < XVECLEN (x, i); j++)
609 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
613 /* Global variables used by reload and its subroutines. */
615 /* Set during calculate_needs if an insn needs register elimination. */
616 static int something_needs_elimination;
617 /* Set during calculate_needs if an insn needs an operand changed. */
618 static int something_needs_operands_changed;
620 /* Nonzero means we couldn't get enough spill regs. */
623 /* Main entry point for the reload pass.
625 FIRST is the first insn of the function being compiled.
627 GLOBAL nonzero means we were called from global_alloc
628 and should attempt to reallocate any pseudoregs that we
629 displace from hard regs we will use for reloads.
630 If GLOBAL is zero, we do not have enough information to do that,
631 so any pseudo reg that is spilled must go to the stack.
633 Return value is nonzero if reload failed
634 and we must not do any more for this function. */
637 reload (rtx first, int global)
641 struct elim_table *ep;
644 /* Make sure even insns with volatile mem refs are recognizable. */
649 reload_firstobj = obstack_alloc (&reload_obstack, 0);
651 /* Make sure that the last insn in the chain
652 is not something that needs reloading. */
653 emit_note (NOTE_INSN_DELETED);
655 /* Enable find_equiv_reg to distinguish insns made by reload. */
656 reload_first_uid = get_max_uid ();
658 #ifdef SECONDARY_MEMORY_NEEDED
659 /* Initialize the secondary memory table. */
660 clear_secondary_mem ();
663 /* We don't have a stack slot for any spill reg yet. */
664 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
665 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
667 /* Initialize the save area information for caller-save, in case some
671 /* Compute which hard registers are now in use
672 as homes for pseudo registers.
673 This is done here rather than (eg) in global_alloc
674 because this point is reached even if not optimizing. */
675 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
678 /* A function that receives a nonlocal goto must save all call-saved
680 if (current_function_has_nonlocal_label)
681 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
682 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
683 regs_ever_live[i] = 1;
685 /* Find all the pseudo registers that didn't get hard regs
686 but do have known equivalent constants or memory slots.
687 These include parameters (known equivalent to parameter slots)
688 and cse'd or loop-moved constant memory addresses.
690 Record constant equivalents in reg_equiv_constant
691 so they will be substituted by find_reloads.
692 Record memory equivalents in reg_mem_equiv so they can
693 be substituted eventually by altering the REG-rtx's. */
695 reg_equiv_constant = xcalloc (max_regno, sizeof (rtx));
696 reg_equiv_mem = xcalloc (max_regno, sizeof (rtx));
697 reg_equiv_init = xcalloc (max_regno, sizeof (rtx));
698 reg_equiv_address = xcalloc (max_regno, sizeof (rtx));
699 reg_max_ref_width = xcalloc (max_regno, sizeof (int));
700 reg_old_renumber = xcalloc (max_regno, sizeof (short));
701 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
702 pseudo_forbidden_regs = xmalloc (max_regno * sizeof (HARD_REG_SET));
703 pseudo_previous_regs = xcalloc (max_regno, sizeof (HARD_REG_SET));
705 CLEAR_HARD_REG_SET (bad_spill_regs_global);
707 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
708 to. Also find all paradoxical subregs and find largest such for
711 num_eliminable_invariants = 0;
712 for (insn = first; insn; insn = NEXT_INSN (insn))
714 rtx set = single_set (insn);
716 /* We may introduce USEs that we want to remove at the end, so
717 we'll mark them with QImode. Make sure there are no
718 previously-marked insns left by say regmove. */
719 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
720 && GET_MODE (insn) != VOIDmode)
721 PUT_MODE (insn, VOIDmode);
723 if (set != 0 && REG_P (SET_DEST (set)))
725 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
727 && (! function_invariant_p (XEXP (note, 0))
729 /* A function invariant is often CONSTANT_P but may
730 include a register. We promise to only pass
731 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
732 || (CONSTANT_P (XEXP (note, 0))
733 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))))
735 rtx x = XEXP (note, 0);
736 i = REGNO (SET_DEST (set));
737 if (i > LAST_VIRTUAL_REGISTER)
739 /* It can happen that a REG_EQUIV note contains a MEM
740 that is not a legitimate memory operand. As later
741 stages of reload assume that all addresses found
742 in the reg_equiv_* arrays were originally legitimate,
743 we ignore such REG_EQUIV notes. */
744 if (memory_operand (x, VOIDmode))
746 /* Always unshare the equivalence, so we can
747 substitute into this insn without touching the
749 reg_equiv_memory_loc[i] = copy_rtx (x);
751 else if (function_invariant_p (x))
753 if (GET_CODE (x) == PLUS)
755 /* This is PLUS of frame pointer and a constant,
756 and might be shared. Unshare it. */
757 reg_equiv_constant[i] = copy_rtx (x);
758 num_eliminable_invariants++;
760 else if (x == frame_pointer_rtx
761 || x == arg_pointer_rtx)
763 reg_equiv_constant[i] = x;
764 num_eliminable_invariants++;
766 else if (LEGITIMATE_CONSTANT_P (x))
767 reg_equiv_constant[i] = x;
770 reg_equiv_memory_loc[i]
771 = force_const_mem (GET_MODE (SET_DEST (set)), x);
772 if (!reg_equiv_memory_loc[i])
779 /* If this register is being made equivalent to a MEM
780 and the MEM is not SET_SRC, the equivalencing insn
781 is one with the MEM as a SET_DEST and it occurs later.
782 So don't mark this insn now. */
784 || rtx_equal_p (SET_SRC (set), x))
786 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
791 /* If this insn is setting a MEM from a register equivalent to it,
792 this is the equivalencing insn. */
793 else if (set && MEM_P (SET_DEST (set))
794 && REG_P (SET_SRC (set))
795 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
796 && rtx_equal_p (SET_DEST (set),
797 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
798 reg_equiv_init[REGNO (SET_SRC (set))]
799 = gen_rtx_INSN_LIST (VOIDmode, insn,
800 reg_equiv_init[REGNO (SET_SRC (set))]);
803 scan_paradoxical_subregs (PATTERN (insn));
808 first_label_num = get_first_label_num ();
809 num_labels = max_label_num () - first_label_num;
811 /* Allocate the tables used to store offset information at labels. */
812 /* We used to use alloca here, but the size of what it would try to
813 allocate would occasionally cause it to exceed the stack limit and
814 cause a core dump. */
815 offsets_known_at = xmalloc (num_labels);
816 offsets_at = xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
818 /* Alter each pseudo-reg rtx to contain its hard reg number.
819 Assign stack slots to the pseudos that lack hard regs or equivalents.
820 Do not touch virtual registers. */
822 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
825 /* If we have some registers we think can be eliminated, scan all insns to
826 see if there is an insn that sets one of these registers to something
827 other than itself plus a constant. If so, the register cannot be
828 eliminated. Doing this scan here eliminates an extra pass through the
829 main reload loop in the most common case where register elimination
831 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
833 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
835 maybe_fix_stack_asms ();
837 insns_need_reload = 0;
838 something_needs_elimination = 0;
840 /* Initialize to -1, which means take the first spill register. */
843 /* Spill any hard regs that we know we can't eliminate. */
844 CLEAR_HARD_REG_SET (used_spill_regs);
845 /* There can be multiple ways to eliminate a register;
846 they should be listed adjacently.
847 Elimination for any register fails only if all possible ways fail. */
848 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
851 int can_eliminate = 0;
854 can_eliminate |= ep->can_eliminate;
857 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
859 spill_hard_reg (from, 1);
862 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
863 if (frame_pointer_needed)
864 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
866 finish_spills (global);
868 /* From now on, we may need to generate moves differently. We may also
869 allow modifications of insns which cause them to not be recognized.
870 Any such modifications will be cleaned up during reload itself. */
871 reload_in_progress = 1;
873 /* This loop scans the entire function each go-round
874 and repeats until one repetition spills no additional hard regs. */
877 int something_changed;
880 HOST_WIDE_INT starting_frame_size;
882 /* Round size of stack frame to stack_alignment_needed. This must be done
883 here because the stack size may be a part of the offset computation
884 for register elimination, and there might have been new stack slots
885 created in the last iteration of this loop. */
886 if (cfun->stack_alignment_needed)
887 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
889 starting_frame_size = get_frame_size ();
891 set_initial_elim_offsets ();
892 set_initial_label_offsets ();
894 /* For each pseudo register that has an equivalent location defined,
895 try to eliminate any eliminable registers (such as the frame pointer)
896 assuming initial offsets for the replacement register, which
899 If the resulting location is directly addressable, substitute
900 the MEM we just got directly for the old REG.
902 If it is not addressable but is a constant or the sum of a hard reg
903 and constant, it is probably not addressable because the constant is
904 out of range, in that case record the address; we will generate
905 hairy code to compute the address in a register each time it is
906 needed. Similarly if it is a hard register, but one that is not
907 valid as an address register.
909 If the location is not addressable, but does not have one of the
910 above forms, assign a stack slot. We have to do this to avoid the
911 potential of producing lots of reloads if, e.g., a location involves
912 a pseudo that didn't get a hard register and has an equivalent memory
913 location that also involves a pseudo that didn't get a hard register.
915 Perhaps at some point we will improve reload_when_needed handling
916 so this problem goes away. But that's very hairy. */
918 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
919 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
921 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
923 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
925 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
926 else if (CONSTANT_P (XEXP (x, 0))
927 || (REG_P (XEXP (x, 0))
928 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
929 || (GET_CODE (XEXP (x, 0)) == PLUS
930 && REG_P (XEXP (XEXP (x, 0), 0))
931 && (REGNO (XEXP (XEXP (x, 0), 0))
932 < FIRST_PSEUDO_REGISTER)
933 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
934 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
937 /* Make a new stack slot. Then indicate that something
938 changed so we go back and recompute offsets for
939 eliminable registers because the allocation of memory
940 below might change some offset. reg_equiv_{mem,address}
941 will be set up for this pseudo on the next pass around
943 reg_equiv_memory_loc[i] = 0;
944 reg_equiv_init[i] = 0;
949 if (caller_save_needed)
952 /* If we allocated another stack slot, redo elimination bookkeeping. */
953 if (starting_frame_size != get_frame_size ())
956 if (caller_save_needed)
958 save_call_clobbered_regs ();
959 /* That might have allocated new insn_chain structures. */
960 reload_firstobj = obstack_alloc (&reload_obstack, 0);
963 calculate_needs_all_insns (global);
965 CLEAR_REG_SET (&spilled_pseudos);
968 something_changed = 0;
970 /* If we allocated any new memory locations, make another pass
971 since it might have changed elimination offsets. */
972 if (starting_frame_size != get_frame_size ())
973 something_changed = 1;
976 HARD_REG_SET to_spill;
977 CLEAR_HARD_REG_SET (to_spill);
978 update_eliminables (&to_spill);
979 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
980 if (TEST_HARD_REG_BIT (to_spill, i))
982 spill_hard_reg (i, 1);
985 /* Regardless of the state of spills, if we previously had
986 a register that we thought we could eliminate, but now can
987 not eliminate, we must run another pass.
989 Consider pseudos which have an entry in reg_equiv_* which
990 reference an eliminable register. We must make another pass
991 to update reg_equiv_* so that we do not substitute in the
992 old value from when we thought the elimination could be
994 something_changed = 1;
998 select_reload_regs ();
1002 if (insns_need_reload != 0 || did_spill)
1003 something_changed |= finish_spills (global);
1005 if (! something_changed)
1008 if (caller_save_needed)
1009 delete_caller_save_insns ();
1011 obstack_free (&reload_obstack, reload_firstobj);
1014 /* If global-alloc was run, notify it of any register eliminations we have
1017 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1018 if (ep->can_eliminate)
1019 mark_elimination (ep->from, ep->to);
1021 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1022 If that insn didn't set the register (i.e., it copied the register to
1023 memory), just delete that insn instead of the equivalencing insn plus
1024 anything now dead. If we call delete_dead_insn on that insn, we may
1025 delete the insn that actually sets the register if the register dies
1026 there and that is incorrect. */
1028 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1030 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1033 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1035 rtx equiv_insn = XEXP (list, 0);
1037 /* If we already deleted the insn or if it may trap, we can't
1038 delete it. The latter case shouldn't happen, but can
1039 if an insn has a variable address, gets a REG_EH_REGION
1040 note added to it, and then gets converted into an load
1041 from a constant address. */
1042 if (NOTE_P (equiv_insn)
1043 || can_throw_internal (equiv_insn))
1045 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1046 delete_dead_insn (equiv_insn);
1048 SET_INSN_DELETED (equiv_insn);
1053 /* Use the reload registers where necessary
1054 by generating move instructions to move the must-be-register
1055 values into or out of the reload registers. */
1057 if (insns_need_reload != 0 || something_needs_elimination
1058 || something_needs_operands_changed)
1060 HOST_WIDE_INT old_frame_size = get_frame_size ();
1062 reload_as_needed (global);
1064 gcc_assert (old_frame_size == get_frame_size ());
1067 verify_initial_elim_offsets ();
1070 /* If we were able to eliminate the frame pointer, show that it is no
1071 longer live at the start of any basic block. If it ls live by
1072 virtue of being in a pseudo, that pseudo will be marked live
1073 and hence the frame pointer will be known to be live via that
1076 if (! frame_pointer_needed)
1078 CLEAR_REGNO_REG_SET (bb->global_live_at_start,
1079 HARD_FRAME_POINTER_REGNUM);
1081 /* Come here (with failure set nonzero) if we can't get enough spill regs
1082 and we decide not to abort about it. */
1085 CLEAR_REG_SET (&spilled_pseudos);
1086 reload_in_progress = 0;
1088 /* Now eliminate all pseudo regs by modifying them into
1089 their equivalent memory references.
1090 The REG-rtx's for the pseudos are modified in place,
1091 so all insns that used to refer to them now refer to memory.
1093 For a reg that has a reg_equiv_address, all those insns
1094 were changed by reloading so that no insns refer to it any longer;
1095 but the DECL_RTL of a variable decl may refer to it,
1096 and if so this causes the debugging info to mention the variable. */
1098 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1102 if (reg_equiv_mem[i])
1103 addr = XEXP (reg_equiv_mem[i], 0);
1105 if (reg_equiv_address[i])
1106 addr = reg_equiv_address[i];
1110 if (reg_renumber[i] < 0)
1112 rtx reg = regno_reg_rtx[i];
1114 REG_USERVAR_P (reg) = 0;
1115 PUT_CODE (reg, MEM);
1116 XEXP (reg, 0) = addr;
1117 if (reg_equiv_memory_loc[i])
1118 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1121 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1122 MEM_ATTRS (reg) = 0;
1125 else if (reg_equiv_mem[i])
1126 XEXP (reg_equiv_mem[i], 0) = addr;
1130 /* We must set reload_completed now since the cleanup_subreg_operands call
1131 below will re-recognize each insn and reload may have generated insns
1132 which are only valid during and after reload. */
1133 reload_completed = 1;
1135 /* Make a pass over all the insns and delete all USEs which we inserted
1136 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1137 notes. Delete all CLOBBER insns, except those that refer to the return
1138 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1139 from misarranging variable-array code, and simplify (subreg (reg))
1140 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1141 are no longer useful or accurate. Strip and regenerate REG_INC notes
1142 that may have been moved around. */
1144 for (insn = first; insn; insn = NEXT_INSN (insn))
1150 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1151 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1153 if ((GET_CODE (PATTERN (insn)) == USE
1154 /* We mark with QImode USEs introduced by reload itself. */
1155 && (GET_MODE (insn) == QImode
1156 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1157 || (GET_CODE (PATTERN (insn)) == CLOBBER
1158 && (!MEM_P (XEXP (PATTERN (insn), 0))
1159 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1160 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1161 && XEXP (XEXP (PATTERN (insn), 0), 0)
1162 != stack_pointer_rtx))
1163 && (!REG_P (XEXP (PATTERN (insn), 0))
1164 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1170 /* Some CLOBBERs may survive until here and still reference unassigned
1171 pseudos with const equivalent, which may in turn cause ICE in later
1172 passes if the reference remains in place. */
1173 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1174 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1175 VOIDmode, PATTERN (insn));
1177 /* Discard obvious no-ops, even without -O. This optimization
1178 is fast and doesn't interfere with debugging. */
1179 if (NONJUMP_INSN_P (insn)
1180 && GET_CODE (PATTERN (insn)) == SET
1181 && REG_P (SET_SRC (PATTERN (insn)))
1182 && REG_P (SET_DEST (PATTERN (insn)))
1183 && (REGNO (SET_SRC (PATTERN (insn)))
1184 == REGNO (SET_DEST (PATTERN (insn)))))
1190 pnote = ®_NOTES (insn);
1193 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1194 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1195 || REG_NOTE_KIND (*pnote) == REG_INC
1196 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1197 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1198 *pnote = XEXP (*pnote, 1);
1200 pnote = &XEXP (*pnote, 1);
1204 add_auto_inc_notes (insn, PATTERN (insn));
1207 /* And simplify (subreg (reg)) if it appears as an operand. */
1208 cleanup_subreg_operands (insn);
1211 /* If we are doing stack checking, give a warning if this function's
1212 frame size is larger than we expect. */
1213 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1215 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1216 static int verbose_warned = 0;
1218 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1219 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1220 size += UNITS_PER_WORD;
1222 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1224 warning ("frame size too large for reliable stack checking");
1225 if (! verbose_warned)
1227 warning ("try reducing the number of local variables");
1233 /* Indicate that we no longer have known memory locations or constants. */
1234 if (reg_equiv_constant)
1235 free (reg_equiv_constant);
1236 reg_equiv_constant = 0;
1237 VARRAY_GROW (reg_equiv_memory_loc_varray, 0);
1238 reg_equiv_memory_loc = 0;
1240 if (offsets_known_at)
1241 free (offsets_known_at);
1245 free (reg_equiv_mem);
1246 free (reg_equiv_init);
1247 free (reg_equiv_address);
1248 free (reg_max_ref_width);
1249 free (reg_old_renumber);
1250 free (pseudo_previous_regs);
1251 free (pseudo_forbidden_regs);
1253 CLEAR_HARD_REG_SET (used_spill_regs);
1254 for (i = 0; i < n_spills; i++)
1255 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1257 /* Free all the insn_chain structures at once. */
1258 obstack_free (&reload_obstack, reload_startobj);
1259 unused_insn_chains = 0;
1260 fixup_abnormal_edges ();
1262 /* Replacing pseudos with their memory equivalents might have
1263 created shared rtx. Subsequent passes would get confused
1264 by this, so unshare everything here. */
1265 unshare_all_rtl_again (first);
1267 #ifdef STACK_BOUNDARY
1268 /* init_emit has set the alignment of the hard frame pointer
1269 to STACK_BOUNDARY. It is very likely no longer valid if
1270 the hard frame pointer was used for register allocation. */
1271 if (!frame_pointer_needed)
1272 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1278 /* Yet another special case. Unfortunately, reg-stack forces people to
1279 write incorrect clobbers in asm statements. These clobbers must not
1280 cause the register to appear in bad_spill_regs, otherwise we'll call
1281 fatal_insn later. We clear the corresponding regnos in the live
1282 register sets to avoid this.
1283 The whole thing is rather sick, I'm afraid. */
1286 maybe_fix_stack_asms (void)
1289 const char *constraints[MAX_RECOG_OPERANDS];
1290 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1291 struct insn_chain *chain;
1293 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1296 HARD_REG_SET clobbered, allowed;
1299 if (! INSN_P (chain->insn)
1300 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1302 pat = PATTERN (chain->insn);
1303 if (GET_CODE (pat) != PARALLEL)
1306 CLEAR_HARD_REG_SET (clobbered);
1307 CLEAR_HARD_REG_SET (allowed);
1309 /* First, make a mask of all stack regs that are clobbered. */
1310 for (i = 0; i < XVECLEN (pat, 0); i++)
1312 rtx t = XVECEXP (pat, 0, i);
1313 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1314 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1317 /* Get the operand values and constraints out of the insn. */
1318 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1319 constraints, operand_mode);
1321 /* For every operand, see what registers are allowed. */
1322 for (i = 0; i < noperands; i++)
1324 const char *p = constraints[i];
1325 /* For every alternative, we compute the class of registers allowed
1326 for reloading in CLS, and merge its contents into the reg set
1328 int cls = (int) NO_REGS;
1334 if (c == '\0' || c == ',' || c == '#')
1336 /* End of one alternative - mark the regs in the current
1337 class, and reset the class. */
1338 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1344 } while (c != '\0' && c != ',');
1352 case '=': case '+': case '*': case '%': case '?': case '!':
1353 case '0': case '1': case '2': case '3': case '4': case 'm':
1354 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1355 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1356 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1361 cls = (int) reg_class_subunion[cls]
1362 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1367 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1371 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1372 cls = (int) reg_class_subunion[cls]
1373 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1375 cls = (int) reg_class_subunion[cls]
1376 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1378 p += CONSTRAINT_LEN (c, p);
1381 /* Those of the registers which are clobbered, but allowed by the
1382 constraints, must be usable as reload registers. So clear them
1383 out of the life information. */
1384 AND_HARD_REG_SET (allowed, clobbered);
1385 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1386 if (TEST_HARD_REG_BIT (allowed, i))
1388 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1389 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1396 /* Copy the global variables n_reloads and rld into the corresponding elts
1399 copy_reloads (struct insn_chain *chain)
1401 chain->n_reloads = n_reloads;
1402 chain->rld = obstack_alloc (&reload_obstack,
1403 n_reloads * sizeof (struct reload));
1404 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1405 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1408 /* Walk the chain of insns, and determine for each whether it needs reloads
1409 and/or eliminations. Build the corresponding insns_need_reload list, and
1410 set something_needs_elimination as appropriate. */
1412 calculate_needs_all_insns (int global)
1414 struct insn_chain **pprev_reload = &insns_need_reload;
1415 struct insn_chain *chain, *next = 0;
1417 something_needs_elimination = 0;
1419 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1420 for (chain = reload_insn_chain; chain != 0; chain = next)
1422 rtx insn = chain->insn;
1426 /* Clear out the shortcuts. */
1427 chain->n_reloads = 0;
1428 chain->need_elim = 0;
1429 chain->need_reload = 0;
1430 chain->need_operand_change = 0;
1432 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1433 include REG_LABEL), we need to see what effects this has on the
1434 known offsets at labels. */
1436 if (LABEL_P (insn) || JUMP_P (insn)
1437 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1438 set_label_offsets (insn, insn, 0);
1442 rtx old_body = PATTERN (insn);
1443 int old_code = INSN_CODE (insn);
1444 rtx old_notes = REG_NOTES (insn);
1445 int did_elimination = 0;
1446 int operands_changed = 0;
1447 rtx set = single_set (insn);
1449 /* Skip insns that only set an equivalence. */
1450 if (set && REG_P (SET_DEST (set))
1451 && reg_renumber[REGNO (SET_DEST (set))] < 0
1452 && reg_equiv_constant[REGNO (SET_DEST (set))])
1455 /* If needed, eliminate any eliminable registers. */
1456 if (num_eliminable || num_eliminable_invariants)
1457 did_elimination = eliminate_regs_in_insn (insn, 0);
1459 /* Analyze the instruction. */
1460 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1461 global, spill_reg_order);
1463 /* If a no-op set needs more than one reload, this is likely
1464 to be something that needs input address reloads. We
1465 can't get rid of this cleanly later, and it is of no use
1466 anyway, so discard it now.
1467 We only do this when expensive_optimizations is enabled,
1468 since this complements reload inheritance / output
1469 reload deletion, and it can make debugging harder. */
1470 if (flag_expensive_optimizations && n_reloads > 1)
1472 rtx set = single_set (insn);
1474 && SET_SRC (set) == SET_DEST (set)
1475 && REG_P (SET_SRC (set))
1476 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1479 /* Delete it from the reload chain. */
1481 chain->prev->next = next;
1483 reload_insn_chain = next;
1485 next->prev = chain->prev;
1486 chain->next = unused_insn_chains;
1487 unused_insn_chains = chain;
1492 update_eliminable_offsets ();
1494 /* Remember for later shortcuts which insns had any reloads or
1495 register eliminations. */
1496 chain->need_elim = did_elimination;
1497 chain->need_reload = n_reloads > 0;
1498 chain->need_operand_change = operands_changed;
1500 /* Discard any register replacements done. */
1501 if (did_elimination)
1503 obstack_free (&reload_obstack, reload_insn_firstobj);
1504 PATTERN (insn) = old_body;
1505 INSN_CODE (insn) = old_code;
1506 REG_NOTES (insn) = old_notes;
1507 something_needs_elimination = 1;
1510 something_needs_operands_changed |= operands_changed;
1514 copy_reloads (chain);
1515 *pprev_reload = chain;
1516 pprev_reload = &chain->next_need_reload;
1523 /* Comparison function for qsort to decide which of two reloads
1524 should be handled first. *P1 and *P2 are the reload numbers. */
1527 reload_reg_class_lower (const void *r1p, const void *r2p)
1529 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1532 /* Consider required reloads before optional ones. */
1533 t = rld[r1].optional - rld[r2].optional;
1537 /* Count all solitary classes before non-solitary ones. */
1538 t = ((reg_class_size[(int) rld[r2].class] == 1)
1539 - (reg_class_size[(int) rld[r1].class] == 1));
1543 /* Aside from solitaires, consider all multi-reg groups first. */
1544 t = rld[r2].nregs - rld[r1].nregs;
1548 /* Consider reloads in order of increasing reg-class number. */
1549 t = (int) rld[r1].class - (int) rld[r2].class;
1553 /* If reloads are equally urgent, sort by reload number,
1554 so that the results of qsort leave nothing to chance. */
1558 /* The cost of spilling each hard reg. */
1559 static int spill_cost[FIRST_PSEUDO_REGISTER];
1561 /* When spilling multiple hard registers, we use SPILL_COST for the first
1562 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1563 only the first hard reg for a multi-reg pseudo. */
1564 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1566 /* Update the spill cost arrays, considering that pseudo REG is live. */
1569 count_pseudo (int reg)
1571 int freq = REG_FREQ (reg);
1572 int r = reg_renumber[reg];
1575 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1576 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1579 SET_REGNO_REG_SET (&pseudos_counted, reg);
1581 gcc_assert (r >= 0);
1583 spill_add_cost[r] += freq;
1585 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1587 spill_cost[r + nregs] += freq;
1590 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1591 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1594 order_regs_for_reload (struct insn_chain *chain)
1597 HARD_REG_SET used_by_pseudos;
1598 HARD_REG_SET used_by_pseudos2;
1599 reg_set_iterator rsi;
1601 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1603 memset (spill_cost, 0, sizeof spill_cost);
1604 memset (spill_add_cost, 0, sizeof spill_add_cost);
1606 /* Count number of uses of each hard reg by pseudo regs allocated to it
1607 and then order them by decreasing use. First exclude hard registers
1608 that are live in or across this insn. */
1610 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1611 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1612 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1613 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1615 /* Now find out which pseudos are allocated to it, and update
1617 CLEAR_REG_SET (&pseudos_counted);
1619 EXECUTE_IF_SET_IN_REG_SET
1620 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1624 EXECUTE_IF_SET_IN_REG_SET
1625 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1629 CLEAR_REG_SET (&pseudos_counted);
1632 /* Vector of reload-numbers showing the order in which the reloads should
1634 static short reload_order[MAX_RELOADS];
1636 /* This is used to keep track of the spill regs used in one insn. */
1637 static HARD_REG_SET used_spill_regs_local;
1639 /* We decided to spill hard register SPILLED, which has a size of
1640 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1641 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1642 update SPILL_COST/SPILL_ADD_COST. */
1645 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1647 int r = reg_renumber[reg];
1648 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1650 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1651 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1654 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1656 spill_add_cost[r] -= REG_FREQ (reg);
1658 spill_cost[r + nregs] -= REG_FREQ (reg);
1661 /* Find reload register to use for reload number ORDER. */
1664 find_reg (struct insn_chain *chain, int order)
1666 int rnum = reload_order[order];
1667 struct reload *rl = rld + rnum;
1668 int best_cost = INT_MAX;
1672 HARD_REG_SET not_usable;
1673 HARD_REG_SET used_by_other_reload;
1674 reg_set_iterator rsi;
1676 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1677 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1678 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1680 CLEAR_HARD_REG_SET (used_by_other_reload);
1681 for (k = 0; k < order; k++)
1683 int other = reload_order[k];
1685 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1686 for (j = 0; j < rld[other].nregs; j++)
1687 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1690 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1692 unsigned int regno = i;
1694 if (! TEST_HARD_REG_BIT (not_usable, regno)
1695 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1696 && HARD_REGNO_MODE_OK (regno, rl->mode))
1698 int this_cost = spill_cost[regno];
1700 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1702 for (j = 1; j < this_nregs; j++)
1704 this_cost += spill_add_cost[regno + j];
1705 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1706 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1711 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1713 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1715 if (this_cost < best_cost
1716 /* Among registers with equal cost, prefer caller-saved ones, or
1717 use REG_ALLOC_ORDER if it is defined. */
1718 || (this_cost == best_cost
1719 #ifdef REG_ALLOC_ORDER
1720 && (inv_reg_alloc_order[regno]
1721 < inv_reg_alloc_order[best_reg])
1723 && call_used_regs[regno]
1724 && ! call_used_regs[best_reg]
1729 best_cost = this_cost;
1737 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1739 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1740 rl->regno = best_reg;
1742 EXECUTE_IF_SET_IN_REG_SET
1743 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1745 count_spilled_pseudo (best_reg, rl->nregs, j);
1748 EXECUTE_IF_SET_IN_REG_SET
1749 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1751 count_spilled_pseudo (best_reg, rl->nregs, j);
1754 for (i = 0; i < rl->nregs; i++)
1756 gcc_assert (spill_cost[best_reg + i] == 0);
1757 gcc_assert (spill_add_cost[best_reg + i] == 0);
1758 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1763 /* Find more reload regs to satisfy the remaining need of an insn, which
1765 Do it by ascending class number, since otherwise a reg
1766 might be spilled for a big class and might fail to count
1767 for a smaller class even though it belongs to that class. */
1770 find_reload_regs (struct insn_chain *chain)
1774 /* In order to be certain of getting the registers we need,
1775 we must sort the reloads into order of increasing register class.
1776 Then our grabbing of reload registers will parallel the process
1777 that provided the reload registers. */
1778 for (i = 0; i < chain->n_reloads; i++)
1780 /* Show whether this reload already has a hard reg. */
1781 if (chain->rld[i].reg_rtx)
1783 int regno = REGNO (chain->rld[i].reg_rtx);
1784 chain->rld[i].regno = regno;
1786 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1789 chain->rld[i].regno = -1;
1790 reload_order[i] = i;
1793 n_reloads = chain->n_reloads;
1794 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1796 CLEAR_HARD_REG_SET (used_spill_regs_local);
1799 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1801 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1803 /* Compute the order of preference for hard registers to spill. */
1805 order_regs_for_reload (chain);
1807 for (i = 0; i < n_reloads; i++)
1809 int r = reload_order[i];
1811 /* Ignore reloads that got marked inoperative. */
1812 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1813 && ! rld[r].optional
1814 && rld[r].regno == -1)
1815 if (! find_reg (chain, i))
1817 spill_failure (chain->insn, rld[r].class);
1823 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1824 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1826 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1830 select_reload_regs (void)
1832 struct insn_chain *chain;
1834 /* Try to satisfy the needs for each insn. */
1835 for (chain = insns_need_reload; chain != 0;
1836 chain = chain->next_need_reload)
1837 find_reload_regs (chain);
1840 /* Delete all insns that were inserted by emit_caller_save_insns during
1843 delete_caller_save_insns (void)
1845 struct insn_chain *c = reload_insn_chain;
1849 while (c != 0 && c->is_caller_save_insn)
1851 struct insn_chain *next = c->next;
1854 if (c == reload_insn_chain)
1855 reload_insn_chain = next;
1859 next->prev = c->prev;
1861 c->prev->next = next;
1862 c->next = unused_insn_chains;
1863 unused_insn_chains = c;
1871 /* Handle the failure to find a register to spill.
1872 INSN should be one of the insns which needed this particular spill reg. */
1875 spill_failure (rtx insn, enum reg_class class)
1877 if (asm_noperands (PATTERN (insn)) >= 0)
1878 error_for_asm (insn, "can't find a register in class %qs while "
1879 "reloading %<asm%>",
1880 reg_class_names[class]);
1883 error ("unable to find a register to spill in class %qs",
1884 reg_class_names[class]);
1885 fatal_insn ("this is the insn:", insn);
1889 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1890 data that is dead in INSN. */
1893 delete_dead_insn (rtx insn)
1895 rtx prev = prev_real_insn (insn);
1898 /* If the previous insn sets a register that dies in our insn, delete it
1900 if (prev && GET_CODE (PATTERN (prev)) == SET
1901 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
1902 && reg_mentioned_p (prev_dest, PATTERN (insn))
1903 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1904 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1905 delete_dead_insn (prev);
1907 SET_INSN_DELETED (insn);
1910 /* Modify the home of pseudo-reg I.
1911 The new home is present in reg_renumber[I].
1913 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1914 or it may be -1, meaning there is none or it is not relevant.
1915 This is used so that all pseudos spilled from a given hard reg
1916 can share one stack slot. */
1919 alter_reg (int i, int from_reg)
1921 /* When outputting an inline function, this can happen
1922 for a reg that isn't actually used. */
1923 if (regno_reg_rtx[i] == 0)
1926 /* If the reg got changed to a MEM at rtl-generation time,
1928 if (!REG_P (regno_reg_rtx[i]))
1931 /* Modify the reg-rtx to contain the new hard reg
1932 number or else to contain its pseudo reg number. */
1933 REGNO (regno_reg_rtx[i])
1934 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1936 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1937 allocate a stack slot for it. */
1939 if (reg_renumber[i] < 0
1940 && REG_N_REFS (i) > 0
1941 && reg_equiv_constant[i] == 0
1942 && reg_equiv_memory_loc[i] == 0)
1945 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1946 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1949 /* Each pseudo reg has an inherent size which comes from its own mode,
1950 and a total size which provides room for paradoxical subregs
1951 which refer to the pseudo reg in wider modes.
1953 We can use a slot already allocated if it provides both
1954 enough inherent space and enough total space.
1955 Otherwise, we allocate a new slot, making sure that it has no less
1956 inherent space, and no less total space, then the previous slot. */
1959 /* No known place to spill from => no slot to reuse. */
1960 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1961 inherent_size == total_size ? 0 : -1);
1962 if (BYTES_BIG_ENDIAN)
1963 /* Cancel the big-endian correction done in assign_stack_local.
1964 Get the address of the beginning of the slot.
1965 This is so we can do a big-endian correction unconditionally
1967 adjust = inherent_size - total_size;
1969 /* Nothing can alias this slot except this pseudo. */
1970 set_mem_alias_set (x, new_alias_set ());
1973 /* Reuse a stack slot if possible. */
1974 else if (spill_stack_slot[from_reg] != 0
1975 && spill_stack_slot_width[from_reg] >= total_size
1976 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1978 x = spill_stack_slot[from_reg];
1980 /* Allocate a bigger slot. */
1983 /* Compute maximum size needed, both for inherent size
1984 and for total size. */
1985 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1988 if (spill_stack_slot[from_reg])
1990 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1992 mode = GET_MODE (spill_stack_slot[from_reg]);
1993 if (spill_stack_slot_width[from_reg] > total_size)
1994 total_size = spill_stack_slot_width[from_reg];
1997 /* Make a slot with that size. */
1998 x = assign_stack_local (mode, total_size,
1999 inherent_size == total_size ? 0 : -1);
2002 /* All pseudos mapped to this slot can alias each other. */
2003 if (spill_stack_slot[from_reg])
2004 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2006 set_mem_alias_set (x, new_alias_set ());
2008 if (BYTES_BIG_ENDIAN)
2010 /* Cancel the big-endian correction done in assign_stack_local.
2011 Get the address of the beginning of the slot.
2012 This is so we can do a big-endian correction unconditionally
2014 adjust = GET_MODE_SIZE (mode) - total_size;
2017 = adjust_address_nv (x, mode_for_size (total_size
2023 spill_stack_slot[from_reg] = stack_slot;
2024 spill_stack_slot_width[from_reg] = total_size;
2027 /* On a big endian machine, the "address" of the slot
2028 is the address of the low part that fits its inherent mode. */
2029 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2030 adjust += (total_size - inherent_size);
2032 /* If we have any adjustment to make, or if the stack slot is the
2033 wrong mode, make a new stack slot. */
2034 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2036 /* If we have a decl for the original register, set it for the
2037 memory. If this is a shared MEM, make a copy. */
2038 if (REG_EXPR (regno_reg_rtx[i])
2039 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2041 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2043 /* We can do this only for the DECLs home pseudo, not for
2044 any copies of it, since otherwise when the stack slot
2045 is reused, nonoverlapping_memrefs_p might think they
2047 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2049 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2052 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2056 /* Save the stack slot for later. */
2057 reg_equiv_memory_loc[i] = x;
2061 /* Mark the slots in regs_ever_live for the hard regs
2062 used by pseudo-reg number REGNO. */
2065 mark_home_live (int regno)
2069 i = reg_renumber[regno];
2072 lim = i + hard_regno_nregs[i][PSEUDO_REGNO_MODE (regno)];
2074 regs_ever_live[i++] = 1;
2077 /* This function handles the tracking of elimination offsets around branches.
2079 X is a piece of RTL being scanned.
2081 INSN is the insn that it came from, if any.
2083 INITIAL_P is nonzero if we are to set the offset to be the initial
2084 offset and zero if we are setting the offset of the label to be the
2088 set_label_offsets (rtx x, rtx insn, int initial_p)
2090 enum rtx_code code = GET_CODE (x);
2093 struct elim_table *p;
2098 if (LABEL_REF_NONLOCAL_P (x))
2103 /* ... fall through ... */
2106 /* If we know nothing about this label, set the desired offsets. Note
2107 that this sets the offset at a label to be the offset before a label
2108 if we don't know anything about the label. This is not correct for
2109 the label after a BARRIER, but is the best guess we can make. If
2110 we guessed wrong, we will suppress an elimination that might have
2111 been possible had we been able to guess correctly. */
2113 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2115 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2116 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2117 = (initial_p ? reg_eliminate[i].initial_offset
2118 : reg_eliminate[i].offset);
2119 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2122 /* Otherwise, if this is the definition of a label and it is
2123 preceded by a BARRIER, set our offsets to the known offset of
2127 && (tem = prev_nonnote_insn (insn)) != 0
2129 set_offsets_for_label (insn);
2131 /* If neither of the above cases is true, compare each offset
2132 with those previously recorded and suppress any eliminations
2133 where the offsets disagree. */
2135 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2136 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2137 != (initial_p ? reg_eliminate[i].initial_offset
2138 : reg_eliminate[i].offset))
2139 reg_eliminate[i].can_eliminate = 0;
2144 set_label_offsets (PATTERN (insn), insn, initial_p);
2146 /* ... fall through ... */
2150 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2151 and hence must have all eliminations at their initial offsets. */
2152 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2153 if (REG_NOTE_KIND (tem) == REG_LABEL)
2154 set_label_offsets (XEXP (tem, 0), insn, 1);
2160 /* Each of the labels in the parallel or address vector must be
2161 at their initial offsets. We want the first field for PARALLEL
2162 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2164 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2165 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2170 /* We only care about setting PC. If the source is not RETURN,
2171 IF_THEN_ELSE, or a label, disable any eliminations not at
2172 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2173 isn't one of those possibilities. For branches to a label,
2174 call ourselves recursively.
2176 Note that this can disable elimination unnecessarily when we have
2177 a non-local goto since it will look like a non-constant jump to
2178 someplace in the current function. This isn't a significant
2179 problem since such jumps will normally be when all elimination
2180 pairs are back to their initial offsets. */
2182 if (SET_DEST (x) != pc_rtx)
2185 switch (GET_CODE (SET_SRC (x)))
2192 set_label_offsets (SET_SRC (x), insn, initial_p);
2196 tem = XEXP (SET_SRC (x), 1);
2197 if (GET_CODE (tem) == LABEL_REF)
2198 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2199 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2202 tem = XEXP (SET_SRC (x), 2);
2203 if (GET_CODE (tem) == LABEL_REF)
2204 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2205 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2213 /* If we reach here, all eliminations must be at their initial
2214 offset because we are doing a jump to a variable address. */
2215 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2216 if (p->offset != p->initial_offset)
2217 p->can_eliminate = 0;
2225 /* Scan X and replace any eliminable registers (such as fp) with a
2226 replacement (such as sp), plus an offset.
2228 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2229 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2230 MEM, we are allowed to replace a sum of a register and the constant zero
2231 with the register, which we cannot do outside a MEM. In addition, we need
2232 to record the fact that a register is referenced outside a MEM.
2234 If INSN is an insn, it is the insn containing X. If we replace a REG
2235 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2236 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2237 the REG is being modified.
2239 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2240 That's used when we eliminate in expressions stored in notes.
2241 This means, do not set ref_outside_mem even if the reference
2244 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2245 replacements done assuming all offsets are at their initial values. If
2246 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2247 encounter, return the actual location so that find_reloads will do
2248 the proper thing. */
2251 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2253 enum rtx_code code = GET_CODE (x);
2254 struct elim_table *ep;
2261 if (! current_function_decl)
2283 /* First handle the case where we encounter a bare register that
2284 is eliminable. Replace it with a PLUS. */
2285 if (regno < FIRST_PSEUDO_REGISTER)
2287 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2289 if (ep->from_rtx == x && ep->can_eliminate)
2290 return plus_constant (ep->to_rtx, ep->previous_offset);
2293 else if (reg_renumber && reg_renumber[regno] < 0
2294 && reg_equiv_constant && reg_equiv_constant[regno]
2295 && ! CONSTANT_P (reg_equiv_constant[regno]))
2296 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2300 /* You might think handling MINUS in a manner similar to PLUS is a
2301 good idea. It is not. It has been tried multiple times and every
2302 time the change has had to have been reverted.
2304 Other parts of reload know a PLUS is special (gen_reload for example)
2305 and require special code to handle code a reloaded PLUS operand.
2307 Also consider backends where the flags register is clobbered by a
2308 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2309 lea instruction comes to mind). If we try to reload a MINUS, we
2310 may kill the flags register that was holding a useful value.
2312 So, please before trying to handle MINUS, consider reload as a
2313 whole instead of this little section as well as the backend issues. */
2315 /* If this is the sum of an eliminable register and a constant, rework
2317 if (REG_P (XEXP (x, 0))
2318 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2319 && CONSTANT_P (XEXP (x, 1)))
2321 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2323 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2325 /* The only time we want to replace a PLUS with a REG (this
2326 occurs when the constant operand of the PLUS is the negative
2327 of the offset) is when we are inside a MEM. We won't want
2328 to do so at other times because that would change the
2329 structure of the insn in a way that reload can't handle.
2330 We special-case the commonest situation in
2331 eliminate_regs_in_insn, so just replace a PLUS with a
2332 PLUS here, unless inside a MEM. */
2333 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2334 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2337 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2338 plus_constant (XEXP (x, 1),
2339 ep->previous_offset));
2342 /* If the register is not eliminable, we are done since the other
2343 operand is a constant. */
2347 /* If this is part of an address, we want to bring any constant to the
2348 outermost PLUS. We will do this by doing register replacement in
2349 our operands and seeing if a constant shows up in one of them.
2351 Note that there is no risk of modifying the structure of the insn,
2352 since we only get called for its operands, thus we are either
2353 modifying the address inside a MEM, or something like an address
2354 operand of a load-address insn. */
2357 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2358 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2360 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2362 /* If one side is a PLUS and the other side is a pseudo that
2363 didn't get a hard register but has a reg_equiv_constant,
2364 we must replace the constant here since it may no longer
2365 be in the position of any operand. */
2366 if (GET_CODE (new0) == PLUS && REG_P (new1)
2367 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2368 && reg_renumber[REGNO (new1)] < 0
2369 && reg_equiv_constant != 0
2370 && reg_equiv_constant[REGNO (new1)] != 0)
2371 new1 = reg_equiv_constant[REGNO (new1)];
2372 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2373 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2374 && reg_renumber[REGNO (new0)] < 0
2375 && reg_equiv_constant[REGNO (new0)] != 0)
2376 new0 = reg_equiv_constant[REGNO (new0)];
2378 new = form_sum (new0, new1);
2380 /* As above, if we are not inside a MEM we do not want to
2381 turn a PLUS into something else. We might try to do so here
2382 for an addition of 0 if we aren't optimizing. */
2383 if (! mem_mode && GET_CODE (new) != PLUS)
2384 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2392 /* If this is the product of an eliminable register and a
2393 constant, apply the distribute law and move the constant out
2394 so that we have (plus (mult ..) ..). This is needed in order
2395 to keep load-address insns valid. This case is pathological.
2396 We ignore the possibility of overflow here. */
2397 if (REG_P (XEXP (x, 0))
2398 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2399 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2400 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2402 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2405 /* Refs inside notes don't count for this purpose. */
2406 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2407 || GET_CODE (insn) == INSN_LIST)))
2408 ep->ref_outside_mem = 1;
2411 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2412 ep->previous_offset * INTVAL (XEXP (x, 1)));
2415 /* ... fall through ... */
2419 /* See comments before PLUS about handling MINUS. */
2421 case DIV: case UDIV:
2422 case MOD: case UMOD:
2423 case AND: case IOR: case XOR:
2424 case ROTATERT: case ROTATE:
2425 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2427 case GE: case GT: case GEU: case GTU:
2428 case LE: case LT: case LEU: case LTU:
2430 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2432 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2434 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2435 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2440 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2443 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2444 if (new != XEXP (x, 0))
2446 /* If this is a REG_DEAD note, it is not valid anymore.
2447 Using the eliminated version could result in creating a
2448 REG_DEAD note for the stack or frame pointer. */
2449 if (GET_MODE (x) == REG_DEAD)
2451 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2454 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2458 /* ... fall through ... */
2461 /* Now do eliminations in the rest of the chain. If this was
2462 an EXPR_LIST, this might result in allocating more memory than is
2463 strictly needed, but it simplifies the code. */
2466 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2467 if (new != XEXP (x, 1))
2469 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2477 case STRICT_LOW_PART:
2479 case SIGN_EXTEND: case ZERO_EXTEND:
2480 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2481 case FLOAT: case FIX:
2482 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2490 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2491 if (new != XEXP (x, 0))
2492 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2496 /* Similar to above processing, but preserve SUBREG_BYTE.
2497 Convert (subreg (mem)) to (mem) if not paradoxical.
2498 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2499 pseudo didn't get a hard reg, we must replace this with the
2500 eliminated version of the memory location because push_reload
2501 may do the replacement in certain circumstances. */
2502 if (REG_P (SUBREG_REG (x))
2503 && (GET_MODE_SIZE (GET_MODE (x))
2504 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2505 && reg_equiv_memory_loc != 0
2506 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2508 new = SUBREG_REG (x);
2511 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2513 if (new != SUBREG_REG (x))
2515 int x_size = GET_MODE_SIZE (GET_MODE (x));
2516 int new_size = GET_MODE_SIZE (GET_MODE (new));
2519 && ((x_size < new_size
2520 #ifdef WORD_REGISTER_OPERATIONS
2521 /* On these machines, combine can create rtl of the form
2522 (set (subreg:m1 (reg:m2 R) 0) ...)
2523 where m1 < m2, and expects something interesting to
2524 happen to the entire word. Moreover, it will use the
2525 (reg:m2 R) later, expecting all bits to be preserved.
2526 So if the number of words is the same, preserve the
2527 subreg so that push_reload can see it. */
2528 && ! ((x_size - 1) / UNITS_PER_WORD
2529 == (new_size -1 ) / UNITS_PER_WORD)
2532 || x_size == new_size)
2534 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2536 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2542 /* Our only special processing is to pass the mode of the MEM to our
2543 recursive call and copy the flags. While we are here, handle this
2544 case more efficiently. */
2546 replace_equiv_address_nv (x,
2547 eliminate_regs (XEXP (x, 0),
2548 GET_MODE (x), insn));
2551 /* Handle insn_list USE that a call to a pure function may generate. */
2552 new = eliminate_regs (XEXP (x, 0), 0, insn);
2553 if (new != XEXP (x, 0))
2554 return gen_rtx_USE (GET_MODE (x), new);
2566 /* Process each of our operands recursively. If any have changed, make a
2568 fmt = GET_RTX_FORMAT (code);
2569 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2573 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2574 if (new != XEXP (x, i) && ! copied)
2576 rtx new_x = rtx_alloc (code);
2577 memcpy (new_x, x, RTX_SIZE (code));
2583 else if (*fmt == 'E')
2586 for (j = 0; j < XVECLEN (x, i); j++)
2588 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2589 if (new != XVECEXP (x, i, j) && ! copied_vec)
2591 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2595 rtx new_x = rtx_alloc (code);
2596 memcpy (new_x, x, RTX_SIZE (code));
2600 XVEC (x, i) = new_v;
2603 XVECEXP (x, i, j) = new;
2611 /* Scan rtx X for modifications of elimination target registers. Update
2612 the table of eliminables to reflect the changed state. MEM_MODE is
2613 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2616 elimination_effects (rtx x, enum machine_mode mem_mode)
2618 enum rtx_code code = GET_CODE (x);
2619 struct elim_table *ep;
2643 /* First handle the case where we encounter a bare register that
2644 is eliminable. Replace it with a PLUS. */
2645 if (regno < FIRST_PSEUDO_REGISTER)
2647 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2649 if (ep->from_rtx == x && ep->can_eliminate)
2652 ep->ref_outside_mem = 1;
2657 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2658 && reg_equiv_constant[regno]
2659 && ! function_invariant_p (reg_equiv_constant[regno]))
2660 elimination_effects (reg_equiv_constant[regno], mem_mode);
2669 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2670 if (ep->to_rtx == XEXP (x, 0))
2672 int size = GET_MODE_SIZE (mem_mode);
2674 /* If more bytes than MEM_MODE are pushed, account for them. */
2675 #ifdef PUSH_ROUNDING
2676 if (ep->to_rtx == stack_pointer_rtx)
2677 size = PUSH_ROUNDING (size);
2679 if (code == PRE_DEC || code == POST_DEC)
2681 else if (code == PRE_INC || code == POST_INC)
2683 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2684 && GET_CODE (XEXP (x, 1)) == PLUS
2685 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2686 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2687 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2690 /* These two aren't unary operators. */
2691 if (code == POST_MODIFY || code == PRE_MODIFY)
2694 /* Fall through to generic unary operation case. */
2695 case STRICT_LOW_PART:
2697 case SIGN_EXTEND: case ZERO_EXTEND:
2698 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2699 case FLOAT: case FIX:
2700 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2708 elimination_effects (XEXP (x, 0), mem_mode);
2712 if (REG_P (SUBREG_REG (x))
2713 && (GET_MODE_SIZE (GET_MODE (x))
2714 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2715 && reg_equiv_memory_loc != 0
2716 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2719 elimination_effects (SUBREG_REG (x), mem_mode);
2723 /* If using a register that is the source of an eliminate we still
2724 think can be performed, note it cannot be performed since we don't
2725 know how this register is used. */
2726 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2727 if (ep->from_rtx == XEXP (x, 0))
2728 ep->can_eliminate = 0;
2730 elimination_effects (XEXP (x, 0), mem_mode);
2734 /* If clobbering a register that is the replacement register for an
2735 elimination we still think can be performed, note that it cannot
2736 be performed. Otherwise, we need not be concerned about it. */
2737 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2738 if (ep->to_rtx == XEXP (x, 0))
2739 ep->can_eliminate = 0;
2741 elimination_effects (XEXP (x, 0), mem_mode);
2745 /* Check for setting a register that we know about. */
2746 if (REG_P (SET_DEST (x)))
2748 /* See if this is setting the replacement register for an
2751 If DEST is the hard frame pointer, we do nothing because we
2752 assume that all assignments to the frame pointer are for
2753 non-local gotos and are being done at a time when they are valid
2754 and do not disturb anything else. Some machines want to
2755 eliminate a fake argument pointer (or even a fake frame pointer)
2756 with either the real frame or the stack pointer. Assignments to
2757 the hard frame pointer must not prevent this elimination. */
2759 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2761 if (ep->to_rtx == SET_DEST (x)
2762 && SET_DEST (x) != hard_frame_pointer_rtx)
2764 /* If it is being incremented, adjust the offset. Otherwise,
2765 this elimination can't be done. */
2766 rtx src = SET_SRC (x);
2768 if (GET_CODE (src) == PLUS
2769 && XEXP (src, 0) == SET_DEST (x)
2770 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2771 ep->offset -= INTVAL (XEXP (src, 1));
2773 ep->can_eliminate = 0;
2777 elimination_effects (SET_DEST (x), 0);
2778 elimination_effects (SET_SRC (x), 0);
2782 /* Our only special processing is to pass the mode of the MEM to our
2784 elimination_effects (XEXP (x, 0), GET_MODE (x));
2791 fmt = GET_RTX_FORMAT (code);
2792 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2795 elimination_effects (XEXP (x, i), mem_mode);
2796 else if (*fmt == 'E')
2797 for (j = 0; j < XVECLEN (x, i); j++)
2798 elimination_effects (XVECEXP (x, i, j), mem_mode);
2802 /* Descend through rtx X and verify that no references to eliminable registers
2803 remain. If any do remain, mark the involved register as not
2807 check_eliminable_occurrences (rtx x)
2816 code = GET_CODE (x);
2818 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2820 struct elim_table *ep;
2822 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2823 if (ep->from_rtx == x)
2824 ep->can_eliminate = 0;
2828 fmt = GET_RTX_FORMAT (code);
2829 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2832 check_eliminable_occurrences (XEXP (x, i));
2833 else if (*fmt == 'E')
2836 for (j = 0; j < XVECLEN (x, i); j++)
2837 check_eliminable_occurrences (XVECEXP (x, i, j));
2842 /* Scan INSN and eliminate all eliminable registers in it.
2844 If REPLACE is nonzero, do the replacement destructively. Also
2845 delete the insn as dead it if it is setting an eliminable register.
2847 If REPLACE is zero, do all our allocations in reload_obstack.
2849 If no eliminations were done and this insn doesn't require any elimination
2850 processing (these are not identical conditions: it might be updating sp,
2851 but not referencing fp; this needs to be seen during reload_as_needed so
2852 that the offset between fp and sp can be taken into consideration), zero
2853 is returned. Otherwise, 1 is returned. */
2856 eliminate_regs_in_insn (rtx insn, int replace)
2858 int icode = recog_memoized (insn);
2859 rtx old_body = PATTERN (insn);
2860 int insn_is_asm = asm_noperands (old_body) >= 0;
2861 rtx old_set = single_set (insn);
2865 rtx substed_operand[MAX_RECOG_OPERANDS];
2866 rtx orig_operand[MAX_RECOG_OPERANDS];
2867 struct elim_table *ep;
2870 if (! insn_is_asm && icode < 0)
2872 gcc_assert (GET_CODE (PATTERN (insn)) == USE
2873 || GET_CODE (PATTERN (insn)) == CLOBBER
2874 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2875 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2876 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
2880 if (old_set != 0 && REG_P (SET_DEST (old_set))
2881 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2883 /* Check for setting an eliminable register. */
2884 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2885 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2887 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2888 /* If this is setting the frame pointer register to the
2889 hardware frame pointer register and this is an elimination
2890 that will be done (tested above), this insn is really
2891 adjusting the frame pointer downward to compensate for
2892 the adjustment done before a nonlocal goto. */
2893 if (ep->from == FRAME_POINTER_REGNUM
2894 && ep->to == HARD_FRAME_POINTER_REGNUM)
2896 rtx base = SET_SRC (old_set);
2897 rtx base_insn = insn;
2898 HOST_WIDE_INT offset = 0;
2900 while (base != ep->to_rtx)
2902 rtx prev_insn, prev_set;
2904 if (GET_CODE (base) == PLUS
2905 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2907 offset += INTVAL (XEXP (base, 1));
2908 base = XEXP (base, 0);
2910 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2911 && (prev_set = single_set (prev_insn)) != 0
2912 && rtx_equal_p (SET_DEST (prev_set), base))
2914 base = SET_SRC (prev_set);
2915 base_insn = prev_insn;
2921 if (base == ep->to_rtx)
2924 = plus_constant (ep->to_rtx, offset - ep->offset);
2926 new_body = old_body;
2929 new_body = copy_insn (old_body);
2930 if (REG_NOTES (insn))
2931 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2933 PATTERN (insn) = new_body;
2934 old_set = single_set (insn);
2936 /* First see if this insn remains valid when we
2937 make the change. If not, keep the INSN_CODE
2938 the same and let reload fit it up. */
2939 validate_change (insn, &SET_SRC (old_set), src, 1);
2940 validate_change (insn, &SET_DEST (old_set),
2942 if (! apply_change_group ())
2944 SET_SRC (old_set) = src;
2945 SET_DEST (old_set) = ep->to_rtx;
2954 /* In this case this insn isn't serving a useful purpose. We
2955 will delete it in reload_as_needed once we know that this
2956 elimination is, in fact, being done.
2958 If REPLACE isn't set, we can't delete this insn, but needn't
2959 process it since it won't be used unless something changes. */
2962 delete_dead_insn (insn);
2970 /* We allow one special case which happens to work on all machines we
2971 currently support: a single set with the source or a REG_EQUAL
2972 note being a PLUS of an eliminable register and a constant. */
2974 if (old_set && REG_P (SET_DEST (old_set)))
2976 /* First see if the source is of the form (plus (reg) CST). */
2977 if (GET_CODE (SET_SRC (old_set)) == PLUS
2978 && REG_P (XEXP (SET_SRC (old_set), 0))
2979 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
2980 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
2981 plus_src = SET_SRC (old_set);
2982 else if (REG_P (SET_SRC (old_set)))
2984 /* Otherwise, see if we have a REG_EQUAL note of the form
2985 (plus (reg) CST). */
2987 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
2989 if (REG_NOTE_KIND (links) == REG_EQUAL
2990 && GET_CODE (XEXP (links, 0)) == PLUS
2991 && REG_P (XEXP (XEXP (links, 0), 0))
2992 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT
2993 && REGNO (XEXP (XEXP (links, 0), 0)) < FIRST_PSEUDO_REGISTER)
2995 plus_src = XEXP (links, 0);
3003 rtx reg = XEXP (plus_src, 0);
3004 HOST_WIDE_INT offset = INTVAL (XEXP (plus_src, 1));
3006 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3007 if (ep->from_rtx == reg && ep->can_eliminate)
3009 offset += ep->offset;
3014 /* We assume here that if we need a PARALLEL with
3015 CLOBBERs for this assignment, we can do with the
3016 MATCH_SCRATCHes that add_clobbers allocates.
3017 There's not much we can do if that doesn't work. */
3018 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3022 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3025 rtvec vec = rtvec_alloc (num_clobbers + 1);
3027 vec->elem[0] = PATTERN (insn);
3028 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3029 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3031 gcc_assert (INSN_CODE (insn) >= 0);
3033 /* If we have a nonzero offset, and the source is already
3034 a simple REG, the following transformation would
3035 increase the cost of the insn by replacing a simple REG
3036 with (plus (reg sp) CST). So try only when plus_src
3037 comes from old_set proper, not REG_NOTES. */
3038 else if (SET_SRC (old_set) == plus_src)
3040 new_body = old_body;
3043 new_body = copy_insn (old_body);
3044 if (REG_NOTES (insn))
3045 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3047 PATTERN (insn) = new_body;
3048 old_set = single_set (insn);
3050 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3051 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3057 /* This can't have an effect on elimination offsets, so skip right
3063 /* Determine the effects of this insn on elimination offsets. */
3064 elimination_effects (old_body, 0);
3066 /* Eliminate all eliminable registers occurring in operands that
3067 can be handled by reload. */
3068 extract_insn (insn);
3069 for (i = 0; i < recog_data.n_operands; i++)
3071 orig_operand[i] = recog_data.operand[i];
3072 substed_operand[i] = recog_data.operand[i];
3074 /* For an asm statement, every operand is eliminable. */
3075 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3077 /* Check for setting a register that we know about. */
3078 if (recog_data.operand_type[i] != OP_IN
3079 && REG_P (orig_operand[i]))
3081 /* If we are assigning to a register that can be eliminated, it
3082 must be as part of a PARALLEL, since the code above handles
3083 single SETs. We must indicate that we can no longer
3084 eliminate this reg. */
3085 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3087 if (ep->from_rtx == orig_operand[i])
3088 ep->can_eliminate = 0;
3091 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3092 replace ? insn : NULL_RTX);
3093 if (substed_operand[i] != orig_operand[i])
3095 /* Terminate the search in check_eliminable_occurrences at
3097 *recog_data.operand_loc[i] = 0;
3099 /* If an output operand changed from a REG to a MEM and INSN is an
3100 insn, write a CLOBBER insn. */
3101 if (recog_data.operand_type[i] != OP_IN
3102 && REG_P (orig_operand[i])
3103 && MEM_P (substed_operand[i])
3105 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3110 for (i = 0; i < recog_data.n_dups; i++)
3111 *recog_data.dup_loc[i]
3112 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3114 /* If any eliminable remain, they aren't eliminable anymore. */
3115 check_eliminable_occurrences (old_body);
3117 /* Substitute the operands; the new values are in the substed_operand
3119 for (i = 0; i < recog_data.n_operands; i++)
3120 *recog_data.operand_loc[i] = substed_operand[i];
3121 for (i = 0; i < recog_data.n_dups; i++)
3122 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3124 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3125 re-recognize the insn. We do this in case we had a simple addition
3126 but now can do this as a load-address. This saves an insn in this
3128 If re-recognition fails, the old insn code number will still be used,
3129 and some register operands may have changed into PLUS expressions.
3130 These will be handled by find_reloads by loading them into a register
3135 /* If we aren't replacing things permanently and we changed something,
3136 make another copy to ensure that all the RTL is new. Otherwise
3137 things can go wrong if find_reload swaps commutative operands
3138 and one is inside RTL that has been copied while the other is not. */
3139 new_body = old_body;
3142 new_body = copy_insn (old_body);
3143 if (REG_NOTES (insn))
3144 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3146 PATTERN (insn) = new_body;
3148 /* If we had a move insn but now we don't, rerecognize it. This will
3149 cause spurious re-recognition if the old move had a PARALLEL since
3150 the new one still will, but we can't call single_set without
3151 having put NEW_BODY into the insn and the re-recognition won't
3152 hurt in this rare case. */
3153 /* ??? Why this huge if statement - why don't we just rerecognize the
3157 && ((REG_P (SET_SRC (old_set))
3158 && (GET_CODE (new_body) != SET
3159 || !REG_P (SET_SRC (new_body))))
3160 /* If this was a load from or store to memory, compare
3161 the MEM in recog_data.operand to the one in the insn.
3162 If they are not equal, then rerecognize the insn. */
3164 && ((MEM_P (SET_SRC (old_set))
3165 && SET_SRC (old_set) != recog_data.operand[1])
3166 || (MEM_P (SET_DEST (old_set))
3167 && SET_DEST (old_set) != recog_data.operand[0])))
3168 /* If this was an add insn before, rerecognize. */
3169 || GET_CODE (SET_SRC (old_set)) == PLUS))
3171 int new_icode = recog (PATTERN (insn), insn, 0);
3173 INSN_CODE (insn) = icode;
3177 /* Restore the old body. If there were any changes to it, we made a copy
3178 of it while the changes were still in place, so we'll correctly return
3179 a modified insn below. */
3182 /* Restore the old body. */
3183 for (i = 0; i < recog_data.n_operands; i++)
3184 *recog_data.operand_loc[i] = orig_operand[i];
3185 for (i = 0; i < recog_data.n_dups; i++)
3186 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3189 /* Update all elimination pairs to reflect the status after the current
3190 insn. The changes we make were determined by the earlier call to
3191 elimination_effects.
3193 We also detect cases where register elimination cannot be done,
3194 namely, if a register would be both changed and referenced outside a MEM
3195 in the resulting insn since such an insn is often undefined and, even if
3196 not, we cannot know what meaning will be given to it. Note that it is
3197 valid to have a register used in an address in an insn that changes it
3198 (presumably with a pre- or post-increment or decrement).
3200 If anything changes, return nonzero. */
3202 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3204 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3205 ep->can_eliminate = 0;
3207 ep->ref_outside_mem = 0;
3209 if (ep->previous_offset != ep->offset)
3214 /* If we changed something, perform elimination in REG_NOTES. This is
3215 needed even when REPLACE is zero because a REG_DEAD note might refer
3216 to a register that we eliminate and could cause a different number
3217 of spill registers to be needed in the final reload pass than in
3219 if (val && REG_NOTES (insn) != 0)
3220 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3225 /* Loop through all elimination pairs.
3226 Recalculate the number not at initial offset.
3228 Compute the maximum offset (minimum offset if the stack does not
3229 grow downward) for each elimination pair. */
3232 update_eliminable_offsets (void)
3234 struct elim_table *ep;
3236 num_not_at_initial_offset = 0;
3237 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3239 ep->previous_offset = ep->offset;
3240 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3241 num_not_at_initial_offset++;
3245 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3246 replacement we currently believe is valid, mark it as not eliminable if X
3247 modifies DEST in any way other than by adding a constant integer to it.
3249 If DEST is the frame pointer, we do nothing because we assume that
3250 all assignments to the hard frame pointer are nonlocal gotos and are being
3251 done at a time when they are valid and do not disturb anything else.
3252 Some machines want to eliminate a fake argument pointer with either the
3253 frame or stack pointer. Assignments to the hard frame pointer must not
3254 prevent this elimination.
3256 Called via note_stores from reload before starting its passes to scan
3257 the insns of the function. */
3260 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3264 /* A SUBREG of a hard register here is just changing its mode. We should
3265 not see a SUBREG of an eliminable hard register, but check just in
3267 if (GET_CODE (dest) == SUBREG)
3268 dest = SUBREG_REG (dest);
3270 if (dest == hard_frame_pointer_rtx)
3273 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3274 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3275 && (GET_CODE (x) != SET
3276 || GET_CODE (SET_SRC (x)) != PLUS
3277 || XEXP (SET_SRC (x), 0) != dest
3278 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3280 reg_eliminate[i].can_eliminate_previous
3281 = reg_eliminate[i].can_eliminate = 0;
3286 /* Verify that the initial elimination offsets did not change since the
3287 last call to set_initial_elim_offsets. This is used to catch cases
3288 where something illegal happened during reload_as_needed that could
3289 cause incorrect code to be generated if we did not check for it. */
3292 verify_initial_elim_offsets (void)
3296 #ifdef ELIMINABLE_REGS
3297 struct elim_table *ep;
3299 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3301 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3302 gcc_assert (t == ep->initial_offset);
3305 INITIAL_FRAME_POINTER_OFFSET (t);
3306 gcc_assert (t == reg_eliminate[0].initial_offset);
3310 /* Reset all offsets on eliminable registers to their initial values. */
3313 set_initial_elim_offsets (void)
3315 struct elim_table *ep = reg_eliminate;
3317 #ifdef ELIMINABLE_REGS
3318 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3320 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3321 ep->previous_offset = ep->offset = ep->initial_offset;
3324 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3325 ep->previous_offset = ep->offset = ep->initial_offset;
3328 num_not_at_initial_offset = 0;
3331 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3334 set_initial_eh_label_offset (rtx label)
3336 set_label_offsets (label, NULL_RTX, 1);
3339 /* Initialize the known label offsets.
3340 Set a known offset for each forced label to be at the initial offset
3341 of each elimination. We do this because we assume that all
3342 computed jumps occur from a location where each elimination is
3343 at its initial offset.
3344 For all other labels, show that we don't know the offsets. */
3347 set_initial_label_offsets (void)
3350 memset (offsets_known_at, 0, num_labels);
3352 for (x = forced_labels; x; x = XEXP (x, 1))
3354 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3356 for_each_eh_label (set_initial_eh_label_offset);
3359 /* Set all elimination offsets to the known values for the code label given
3363 set_offsets_for_label (rtx insn)
3366 int label_nr = CODE_LABEL_NUMBER (insn);
3367 struct elim_table *ep;
3369 num_not_at_initial_offset = 0;
3370 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3372 ep->offset = ep->previous_offset
3373 = offsets_at[label_nr - first_label_num][i];
3374 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3375 num_not_at_initial_offset++;
3379 /* See if anything that happened changes which eliminations are valid.
3380 For example, on the SPARC, whether or not the frame pointer can
3381 be eliminated can depend on what registers have been used. We need
3382 not check some conditions again (such as flag_omit_frame_pointer)
3383 since they can't have changed. */
3386 update_eliminables (HARD_REG_SET *pset)
3388 int previous_frame_pointer_needed = frame_pointer_needed;
3389 struct elim_table *ep;
3391 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3392 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3393 #ifdef ELIMINABLE_REGS
3394 || ! CAN_ELIMINATE (ep->from, ep->to)
3397 ep->can_eliminate = 0;
3399 /* Look for the case where we have discovered that we can't replace
3400 register A with register B and that means that we will now be
3401 trying to replace register A with register C. This means we can
3402 no longer replace register C with register B and we need to disable
3403 such an elimination, if it exists. This occurs often with A == ap,
3404 B == sp, and C == fp. */
3406 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3408 struct elim_table *op;
3411 if (! ep->can_eliminate && ep->can_eliminate_previous)
3413 /* Find the current elimination for ep->from, if there is a
3415 for (op = reg_eliminate;
3416 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3417 if (op->from == ep->from && op->can_eliminate)
3423 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3425 for (op = reg_eliminate;
3426 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3427 if (op->from == new_to && op->to == ep->to)
3428 op->can_eliminate = 0;
3432 /* See if any registers that we thought we could eliminate the previous
3433 time are no longer eliminable. If so, something has changed and we
3434 must spill the register. Also, recompute the number of eliminable
3435 registers and see if the frame pointer is needed; it is if there is
3436 no elimination of the frame pointer that we can perform. */
3438 frame_pointer_needed = 1;
3439 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3441 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3442 && ep->to != HARD_FRAME_POINTER_REGNUM)
3443 frame_pointer_needed = 0;
3445 if (! ep->can_eliminate && ep->can_eliminate_previous)
3447 ep->can_eliminate_previous = 0;
3448 SET_HARD_REG_BIT (*pset, ep->from);
3453 /* If we didn't need a frame pointer last time, but we do now, spill
3454 the hard frame pointer. */
3455 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3456 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3459 /* Initialize the table of registers to eliminate. */
3462 init_elim_table (void)
3464 struct elim_table *ep;
3465 #ifdef ELIMINABLE_REGS
3466 const struct elim_table_1 *ep1;
3470 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3472 /* Does this function require a frame pointer? */
3474 frame_pointer_needed = (! flag_omit_frame_pointer
3475 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3476 and restore sp for alloca. So we can't eliminate
3477 the frame pointer in that case. At some point,
3478 we should improve this by emitting the
3479 sp-adjusting insns for this case. */
3480 || (current_function_calls_alloca
3481 && EXIT_IGNORE_STACK)
3482 || FRAME_POINTER_REQUIRED);
3486 #ifdef ELIMINABLE_REGS
3487 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3488 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3490 ep->from = ep1->from;
3492 ep->can_eliminate = ep->can_eliminate_previous
3493 = (CAN_ELIMINATE (ep->from, ep->to)
3494 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3497 reg_eliminate[0].from = reg_eliminate_1[0].from;
3498 reg_eliminate[0].to = reg_eliminate_1[0].to;
3499 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3500 = ! frame_pointer_needed;
3503 /* Count the number of eliminable registers and build the FROM and TO
3504 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3505 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3506 We depend on this. */
3507 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3509 num_eliminable += ep->can_eliminate;
3510 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3511 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3515 /* Kick all pseudos out of hard register REGNO.
3517 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3518 because we found we can't eliminate some register. In the case, no pseudos
3519 are allowed to be in the register, even if they are only in a block that
3520 doesn't require spill registers, unlike the case when we are spilling this
3521 hard reg to produce another spill register.
3523 Return nonzero if any pseudos needed to be kicked out. */
3526 spill_hard_reg (unsigned int regno, int cant_eliminate)
3532 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3533 regs_ever_live[regno] = 1;
3536 /* Spill every pseudo reg that was allocated to this reg
3537 or to something that overlaps this reg. */
3539 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3540 if (reg_renumber[i] >= 0
3541 && (unsigned int) reg_renumber[i] <= regno
3542 && ((unsigned int) reg_renumber[i]
3543 + hard_regno_nregs[(unsigned int) reg_renumber[i]]
3544 [PSEUDO_REGNO_MODE (i)]
3546 SET_REGNO_REG_SET (&spilled_pseudos, i);
3549 /* After find_reload_regs has been run for all insn that need reloads,
3550 and/or spill_hard_regs was called, this function is used to actually
3551 spill pseudo registers and try to reallocate them. It also sets up the
3552 spill_regs array for use by choose_reload_regs. */
3555 finish_spills (int global)
3557 struct insn_chain *chain;
3558 int something_changed = 0;
3560 reg_set_iterator rsi;
3562 /* Build the spill_regs array for the function. */
3563 /* If there are some registers still to eliminate and one of the spill regs
3564 wasn't ever used before, additional stack space may have to be
3565 allocated to store this register. Thus, we may have changed the offset
3566 between the stack and frame pointers, so mark that something has changed.
3568 One might think that we need only set VAL to 1 if this is a call-used
3569 register. However, the set of registers that must be saved by the
3570 prologue is not identical to the call-used set. For example, the
3571 register used by the call insn for the return PC is a call-used register,
3572 but must be saved by the prologue. */
3575 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3576 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3578 spill_reg_order[i] = n_spills;
3579 spill_regs[n_spills++] = i;
3580 if (num_eliminable && ! regs_ever_live[i])
3581 something_changed = 1;
3582 regs_ever_live[i] = 1;
3585 spill_reg_order[i] = -1;
3587 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3589 /* Record the current hard register the pseudo is allocated to in
3590 pseudo_previous_regs so we avoid reallocating it to the same
3591 hard reg in a later pass. */
3592 gcc_assert (reg_renumber[i] >= 0);
3594 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3595 /* Mark it as no longer having a hard register home. */
3596 reg_renumber[i] = -1;
3597 /* We will need to scan everything again. */
3598 something_changed = 1;
3601 /* Retry global register allocation if possible. */
3604 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3605 /* For every insn that needs reloads, set the registers used as spill
3606 regs in pseudo_forbidden_regs for every pseudo live across the
3608 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3610 EXECUTE_IF_SET_IN_REG_SET
3611 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3613 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3614 chain->used_spill_regs);
3616 EXECUTE_IF_SET_IN_REG_SET
3617 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3619 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3620 chain->used_spill_regs);
3624 /* Retry allocating the spilled pseudos. For each reg, merge the
3625 various reg sets that indicate which hard regs can't be used,
3626 and call retry_global_alloc.
3627 We change spill_pseudos here to only contain pseudos that did not
3628 get a new hard register. */
3629 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3630 if (reg_old_renumber[i] != reg_renumber[i])
3632 HARD_REG_SET forbidden;
3633 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3634 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3635 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3636 retry_global_alloc (i, forbidden);
3637 if (reg_renumber[i] >= 0)
3638 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3642 /* Fix up the register information in the insn chain.
3643 This involves deleting those of the spilled pseudos which did not get
3644 a new hard register home from the live_{before,after} sets. */
3645 for (chain = reload_insn_chain; chain; chain = chain->next)
3647 HARD_REG_SET used_by_pseudos;
3648 HARD_REG_SET used_by_pseudos2;
3650 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3651 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3653 /* Mark any unallocated hard regs as available for spills. That
3654 makes inheritance work somewhat better. */
3655 if (chain->need_reload)
3657 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3658 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3659 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3661 /* Save the old value for the sanity test below. */
3662 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3664 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3665 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3666 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3667 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3669 /* Make sure we only enlarge the set. */
3670 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3676 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3677 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3679 int regno = reg_renumber[i];
3680 if (reg_old_renumber[i] == regno)
3683 alter_reg (i, reg_old_renumber[i]);
3684 reg_old_renumber[i] = regno;
3688 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3690 fprintf (dump_file, " Register %d now in %d.\n\n",
3691 i, reg_renumber[i]);
3695 return something_changed;
3698 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3701 scan_paradoxical_subregs (rtx x)
3705 enum rtx_code code = GET_CODE (x);
3715 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3723 if (REG_P (SUBREG_REG (x))
3724 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3725 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3726 = GET_MODE_SIZE (GET_MODE (x));
3733 fmt = GET_RTX_FORMAT (code);
3734 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3737 scan_paradoxical_subregs (XEXP (x, i));
3738 else if (fmt[i] == 'E')
3741 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3742 scan_paradoxical_subregs (XVECEXP (x, i, j));
3747 /* Reload pseudo-registers into hard regs around each insn as needed.
3748 Additional register load insns are output before the insn that needs it
3749 and perhaps store insns after insns that modify the reloaded pseudo reg.
3751 reg_last_reload_reg and reg_reloaded_contents keep track of
3752 which registers are already available in reload registers.
3753 We update these for the reloads that we perform,
3754 as the insns are scanned. */
3757 reload_as_needed (int live_known)
3759 struct insn_chain *chain;
3760 #if defined (AUTO_INC_DEC)
3765 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3766 memset (spill_reg_store, 0, sizeof spill_reg_store);
3767 reg_last_reload_reg = xcalloc (max_regno, sizeof (rtx));
3768 reg_has_output_reload = xmalloc (max_regno);
3769 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3770 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
3772 set_initial_elim_offsets ();
3774 for (chain = reload_insn_chain; chain; chain = chain->next)
3777 rtx insn = chain->insn;
3778 rtx old_next = NEXT_INSN (insn);
3780 /* If we pass a label, copy the offsets from the label information
3781 into the current offsets of each elimination. */
3783 set_offsets_for_label (insn);
3785 else if (INSN_P (insn))
3787 rtx oldpat = copy_rtx (PATTERN (insn));
3789 /* If this is a USE and CLOBBER of a MEM, ensure that any
3790 references to eliminable registers have been removed. */
3792 if ((GET_CODE (PATTERN (insn)) == USE
3793 || GET_CODE (PATTERN (insn)) == CLOBBER)
3794 && MEM_P (XEXP (PATTERN (insn), 0)))
3795 XEXP (XEXP (PATTERN (insn), 0), 0)
3796 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3797 GET_MODE (XEXP (PATTERN (insn), 0)),
3800 /* If we need to do register elimination processing, do so.
3801 This might delete the insn, in which case we are done. */
3802 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3804 eliminate_regs_in_insn (insn, 1);
3807 update_eliminable_offsets ();
3812 /* If need_elim is nonzero but need_reload is zero, one might think
3813 that we could simply set n_reloads to 0. However, find_reloads
3814 could have done some manipulation of the insn (such as swapping
3815 commutative operands), and these manipulations are lost during
3816 the first pass for every insn that needs register elimination.
3817 So the actions of find_reloads must be redone here. */
3819 if (! chain->need_elim && ! chain->need_reload
3820 && ! chain->need_operand_change)
3822 /* First find the pseudo regs that must be reloaded for this insn.
3823 This info is returned in the tables reload_... (see reload.h).
3824 Also modify the body of INSN by substituting RELOAD
3825 rtx's for those pseudo regs. */
3828 memset (reg_has_output_reload, 0, max_regno);
3829 CLEAR_HARD_REG_SET (reg_is_output_reload);
3831 find_reloads (insn, 1, spill_indirect_levels, live_known,
3837 rtx next = NEXT_INSN (insn);
3840 prev = PREV_INSN (insn);
3842 /* Now compute which reload regs to reload them into. Perhaps
3843 reusing reload regs from previous insns, or else output
3844 load insns to reload them. Maybe output store insns too.
3845 Record the choices of reload reg in reload_reg_rtx. */
3846 choose_reload_regs (chain);
3848 /* Merge any reloads that we didn't combine for fear of
3849 increasing the number of spill registers needed but now
3850 discover can be safely merged. */
3851 if (SMALL_REGISTER_CLASSES)
3852 merge_assigned_reloads (insn);
3854 /* Generate the insns to reload operands into or out of
3855 their reload regs. */
3856 emit_reload_insns (chain);
3858 /* Substitute the chosen reload regs from reload_reg_rtx
3859 into the insn's body (or perhaps into the bodies of other
3860 load and store insn that we just made for reloading
3861 and that we moved the structure into). */
3862 subst_reloads (insn);
3864 /* If this was an ASM, make sure that all the reload insns
3865 we have generated are valid. If not, give an error
3868 if (asm_noperands (PATTERN (insn)) >= 0)
3869 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3870 if (p != insn && INSN_P (p)
3871 && GET_CODE (PATTERN (p)) != USE
3872 && (recog_memoized (p) < 0
3873 || (extract_insn (p), ! constrain_operands (1))))
3875 error_for_asm (insn,
3876 "%<asm%> operand requires "
3877 "impossible reload");
3882 if (num_eliminable && chain->need_elim)
3883 update_eliminable_offsets ();
3885 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3886 is no longer validly lying around to save a future reload.
3887 Note that this does not detect pseudos that were reloaded
3888 for this insn in order to be stored in
3889 (obeying register constraints). That is correct; such reload
3890 registers ARE still valid. */
3891 note_stores (oldpat, forget_old_reloads_1, NULL);
3893 /* There may have been CLOBBER insns placed after INSN. So scan
3894 between INSN and NEXT and use them to forget old reloads. */
3895 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3896 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
3897 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3900 /* Likewise for regs altered by auto-increment in this insn.
3901 REG_INC notes have been changed by reloading:
3902 find_reloads_address_1 records substitutions for them,
3903 which have been performed by subst_reloads above. */
3904 for (i = n_reloads - 1; i >= 0; i--)
3906 rtx in_reg = rld[i].in_reg;
3909 enum rtx_code code = GET_CODE (in_reg);
3910 /* PRE_INC / PRE_DEC will have the reload register ending up
3911 with the same value as the stack slot, but that doesn't
3912 hold true for POST_INC / POST_DEC. Either we have to
3913 convert the memory access to a true POST_INC / POST_DEC,
3914 or we can't use the reload register for inheritance. */
3915 if ((code == POST_INC || code == POST_DEC)
3916 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3917 REGNO (rld[i].reg_rtx))
3918 /* Make sure it is the inc/dec pseudo, and not
3919 some other (e.g. output operand) pseudo. */
3920 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3921 == REGNO (XEXP (in_reg, 0))))
3924 rtx reload_reg = rld[i].reg_rtx;
3925 enum machine_mode mode = GET_MODE (reload_reg);
3929 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3931 /* We really want to ignore REG_INC notes here, so
3932 use PATTERN (p) as argument to reg_set_p . */
3933 if (reg_set_p (reload_reg, PATTERN (p)))
3935 n = count_occurrences (PATTERN (p), reload_reg, 0);
3940 n = validate_replace_rtx (reload_reg,
3941 gen_rtx_fmt_e (code,
3946 /* We must also verify that the constraints
3947 are met after the replacement. */
3950 n = constrain_operands (1);
3954 /* If the constraints were not met, then
3955 undo the replacement. */
3958 validate_replace_rtx (gen_rtx_fmt_e (code,
3971 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3973 /* Mark this as having an output reload so that the
3974 REG_INC processing code below won't invalidate
3975 the reload for inheritance. */
3976 SET_HARD_REG_BIT (reg_is_output_reload,
3977 REGNO (reload_reg));
3978 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3981 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
3984 else if ((code == PRE_INC || code == PRE_DEC)
3985 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3986 REGNO (rld[i].reg_rtx))
3987 /* Make sure it is the inc/dec pseudo, and not
3988 some other (e.g. output operand) pseudo. */
3989 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3990 == REGNO (XEXP (in_reg, 0))))
3992 SET_HARD_REG_BIT (reg_is_output_reload,
3993 REGNO (rld[i].reg_rtx));
3994 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3998 /* If a pseudo that got a hard register is auto-incremented,
3999 we must purge records of copying it into pseudos without
4001 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4002 if (REG_NOTE_KIND (x) == REG_INC)
4004 /* See if this pseudo reg was reloaded in this insn.
4005 If so, its last-reload info is still valid
4006 because it is based on this insn's reload. */
4007 for (i = 0; i < n_reloads; i++)
4008 if (rld[i].out == XEXP (x, 0))
4012 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4016 /* A reload reg's contents are unknown after a label. */
4018 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4020 /* Don't assume a reload reg is still good after a call insn
4021 if it is a call-used reg, or if it contains a value that will
4022 be partially clobbered by the call. */
4023 else if (CALL_P (insn))
4025 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4026 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4031 free (reg_last_reload_reg);
4032 free (reg_has_output_reload);
4035 /* Discard all record of any value reloaded from X,
4036 or reloaded in X from someplace else;
4037 unless X is an output reload reg of the current insn.
4039 X may be a hard reg (the reload reg)
4040 or it may be a pseudo reg that was reloaded from. */
4043 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4044 void *data ATTRIBUTE_UNUSED)
4049 /* note_stores does give us subregs of hard regs,
4050 subreg_regno_offset will abort if it is not a hard reg. */
4051 while (GET_CODE (x) == SUBREG)
4053 /* We ignore the subreg offset when calculating the regno,
4054 because we are using the entire underlying hard register
4064 if (regno >= FIRST_PSEUDO_REGISTER)
4070 nr = hard_regno_nregs[regno][GET_MODE (x)];
4071 /* Storing into a spilled-reg invalidates its contents.
4072 This can happen if a block-local pseudo is allocated to that reg
4073 and it wasn't spilled because this block's total need is 0.
4074 Then some insn might have an optional reload and use this reg. */
4075 for (i = 0; i < nr; i++)
4076 /* But don't do this if the reg actually serves as an output
4077 reload reg in the current instruction. */
4079 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4081 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4082 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4083 spill_reg_store[regno + i] = 0;
4087 /* Since value of X has changed,
4088 forget any value previously copied from it. */
4091 /* But don't forget a copy if this is the output reload
4092 that establishes the copy's validity. */
4093 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4094 reg_last_reload_reg[regno + nr] = 0;
4097 /* The following HARD_REG_SETs indicate when each hard register is
4098 used for a reload of various parts of the current insn. */
4100 /* If reg is unavailable for all reloads. */
4101 static HARD_REG_SET reload_reg_unavailable;
4102 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4103 static HARD_REG_SET reload_reg_used;
4104 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4105 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4106 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4107 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4108 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4109 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4110 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4111 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4112 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4113 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4114 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4115 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4116 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4117 static HARD_REG_SET reload_reg_used_in_op_addr;
4118 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4119 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4120 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4121 static HARD_REG_SET reload_reg_used_in_insn;
4122 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4123 static HARD_REG_SET reload_reg_used_in_other_addr;
4125 /* If reg is in use as a reload reg for any sort of reload. */
4126 static HARD_REG_SET reload_reg_used_at_all;
4128 /* If reg is use as an inherited reload. We just mark the first register
4130 static HARD_REG_SET reload_reg_used_for_inherit;
4132 /* Records which hard regs are used in any way, either as explicit use or
4133 by being allocated to a pseudo during any point of the current insn. */
4134 static HARD_REG_SET reg_used_in_insn;
4136 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4137 TYPE. MODE is used to indicate how many consecutive regs are
4141 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4142 enum machine_mode mode)
4144 unsigned int nregs = hard_regno_nregs[regno][mode];
4147 for (i = regno; i < nregs + regno; i++)
4152 SET_HARD_REG_BIT (reload_reg_used, i);
4155 case RELOAD_FOR_INPUT_ADDRESS:
4156 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4159 case RELOAD_FOR_INPADDR_ADDRESS:
4160 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4163 case RELOAD_FOR_OUTPUT_ADDRESS:
4164 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4167 case RELOAD_FOR_OUTADDR_ADDRESS:
4168 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4171 case RELOAD_FOR_OPERAND_ADDRESS:
4172 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4175 case RELOAD_FOR_OPADDR_ADDR:
4176 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4179 case RELOAD_FOR_OTHER_ADDRESS:
4180 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4183 case RELOAD_FOR_INPUT:
4184 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4187 case RELOAD_FOR_OUTPUT:
4188 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4191 case RELOAD_FOR_INSN:
4192 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4196 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4200 /* Similarly, but show REGNO is no longer in use for a reload. */
4203 clear_reload_reg_in_use (unsigned int regno, int opnum,
4204 enum reload_type type, enum machine_mode mode)
4206 unsigned int nregs = hard_regno_nregs[regno][mode];
4207 unsigned int start_regno, end_regno, r;
4209 /* A complication is that for some reload types, inheritance might
4210 allow multiple reloads of the same types to share a reload register.
4211 We set check_opnum if we have to check only reloads with the same
4212 operand number, and check_any if we have to check all reloads. */
4213 int check_opnum = 0;
4215 HARD_REG_SET *used_in_set;
4220 used_in_set = &reload_reg_used;
4223 case RELOAD_FOR_INPUT_ADDRESS:
4224 used_in_set = &reload_reg_used_in_input_addr[opnum];
4227 case RELOAD_FOR_INPADDR_ADDRESS:
4229 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4232 case RELOAD_FOR_OUTPUT_ADDRESS:
4233 used_in_set = &reload_reg_used_in_output_addr[opnum];
4236 case RELOAD_FOR_OUTADDR_ADDRESS:
4238 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4241 case RELOAD_FOR_OPERAND_ADDRESS:
4242 used_in_set = &reload_reg_used_in_op_addr;
4245 case RELOAD_FOR_OPADDR_ADDR:
4247 used_in_set = &reload_reg_used_in_op_addr_reload;
4250 case RELOAD_FOR_OTHER_ADDRESS:
4251 used_in_set = &reload_reg_used_in_other_addr;
4255 case RELOAD_FOR_INPUT:
4256 used_in_set = &reload_reg_used_in_input[opnum];
4259 case RELOAD_FOR_OUTPUT:
4260 used_in_set = &reload_reg_used_in_output[opnum];
4263 case RELOAD_FOR_INSN:
4264 used_in_set = &reload_reg_used_in_insn;
4269 /* We resolve conflicts with remaining reloads of the same type by
4270 excluding the intervals of reload registers by them from the
4271 interval of freed reload registers. Since we only keep track of
4272 one set of interval bounds, we might have to exclude somewhat
4273 more than what would be necessary if we used a HARD_REG_SET here.
4274 But this should only happen very infrequently, so there should
4275 be no reason to worry about it. */
4277 start_regno = regno;
4278 end_regno = regno + nregs;
4279 if (check_opnum || check_any)
4281 for (i = n_reloads - 1; i >= 0; i--)
4283 if (rld[i].when_needed == type
4284 && (check_any || rld[i].opnum == opnum)
4287 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4288 unsigned int conflict_end
4290 + hard_regno_nregs[conflict_start][rld[i].mode]);
4292 /* If there is an overlap with the first to-be-freed register,
4293 adjust the interval start. */
4294 if (conflict_start <= start_regno && conflict_end > start_regno)
4295 start_regno = conflict_end;
4296 /* Otherwise, if there is a conflict with one of the other
4297 to-be-freed registers, adjust the interval end. */
4298 if (conflict_start > start_regno && conflict_start < end_regno)
4299 end_regno = conflict_start;
4304 for (r = start_regno; r < end_regno; r++)
4305 CLEAR_HARD_REG_BIT (*used_in_set, r);
4308 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4309 specified by OPNUM and TYPE. */
4312 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4316 /* In use for a RELOAD_OTHER means it's not available for anything. */
4317 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4318 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4324 /* In use for anything means we can't use it for RELOAD_OTHER. */
4325 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4326 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4327 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4328 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4331 for (i = 0; i < reload_n_operands; i++)
4332 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4333 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4334 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4335 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4336 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4337 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4342 case RELOAD_FOR_INPUT:
4343 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4344 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4347 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4350 /* If it is used for some other input, can't use it. */
4351 for (i = 0; i < reload_n_operands; i++)
4352 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4355 /* If it is used in a later operand's address, can't use it. */
4356 for (i = opnum + 1; i < reload_n_operands; i++)
4357 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4358 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4363 case RELOAD_FOR_INPUT_ADDRESS:
4364 /* Can't use a register if it is used for an input address for this
4365 operand or used as an input in an earlier one. */
4366 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4367 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4370 for (i = 0; i < opnum; i++)
4371 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4376 case RELOAD_FOR_INPADDR_ADDRESS:
4377 /* Can't use a register if it is used for an input address
4378 for this operand or used as an input in an earlier
4380 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4383 for (i = 0; i < opnum; i++)
4384 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4389 case RELOAD_FOR_OUTPUT_ADDRESS:
4390 /* Can't use a register if it is used for an output address for this
4391 operand or used as an output in this or a later operand. Note
4392 that multiple output operands are emitted in reverse order, so
4393 the conflicting ones are those with lower indices. */
4394 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4397 for (i = 0; i <= opnum; i++)
4398 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4403 case RELOAD_FOR_OUTADDR_ADDRESS:
4404 /* Can't use a register if it is used for an output address
4405 for this operand or used as an output in this or a
4406 later operand. Note that multiple output operands are
4407 emitted in reverse order, so the conflicting ones are
4408 those with lower indices. */
4409 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4412 for (i = 0; i <= opnum; i++)
4413 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4418 case RELOAD_FOR_OPERAND_ADDRESS:
4419 for (i = 0; i < reload_n_operands; i++)
4420 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4423 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4424 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4426 case RELOAD_FOR_OPADDR_ADDR:
4427 for (i = 0; i < reload_n_operands; i++)
4428 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4431 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4433 case RELOAD_FOR_OUTPUT:
4434 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4435 outputs, or an operand address for this or an earlier output.
4436 Note that multiple output operands are emitted in reverse order,
4437 so the conflicting ones are those with higher indices. */
4438 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4441 for (i = 0; i < reload_n_operands; i++)
4442 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4445 for (i = opnum; i < reload_n_operands; i++)
4446 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4447 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4452 case RELOAD_FOR_INSN:
4453 for (i = 0; i < reload_n_operands; i++)
4454 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4455 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4458 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4459 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4461 case RELOAD_FOR_OTHER_ADDRESS:
4462 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4469 /* Return 1 if the value in reload reg REGNO, as used by a reload
4470 needed for the part of the insn specified by OPNUM and TYPE,
4471 is still available in REGNO at the end of the insn.
4473 We can assume that the reload reg was already tested for availability
4474 at the time it is needed, and we should not check this again,
4475 in case the reg has already been marked in use. */
4478 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4485 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4486 its value must reach the end. */
4489 /* If this use is for part of the insn,
4490 its value reaches if no subsequent part uses the same register.
4491 Just like the above function, don't try to do this with lots
4494 case RELOAD_FOR_OTHER_ADDRESS:
4495 /* Here we check for everything else, since these don't conflict
4496 with anything else and everything comes later. */
4498 for (i = 0; i < reload_n_operands; i++)
4499 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4500 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4501 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4502 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4503 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4504 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4507 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4508 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4509 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4510 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4512 case RELOAD_FOR_INPUT_ADDRESS:
4513 case RELOAD_FOR_INPADDR_ADDRESS:
4514 /* Similar, except that we check only for this and subsequent inputs
4515 and the address of only subsequent inputs and we do not need
4516 to check for RELOAD_OTHER objects since they are known not to
4519 for (i = opnum; i < reload_n_operands; i++)
4520 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4523 for (i = opnum + 1; i < reload_n_operands; i++)
4524 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4525 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4528 for (i = 0; i < reload_n_operands; i++)
4529 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4530 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4531 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4534 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4537 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4538 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4539 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4541 case RELOAD_FOR_INPUT:
4542 /* Similar to input address, except we start at the next operand for
4543 both input and input address and we do not check for
4544 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4547 for (i = opnum + 1; i < reload_n_operands; i++)
4548 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4549 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4550 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4553 /* ... fall through ... */
4555 case RELOAD_FOR_OPERAND_ADDRESS:
4556 /* Check outputs and their addresses. */
4558 for (i = 0; i < reload_n_operands; i++)
4559 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4560 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4561 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4564 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4566 case RELOAD_FOR_OPADDR_ADDR:
4567 for (i = 0; i < reload_n_operands; i++)
4568 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4569 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4570 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4573 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4574 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4575 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4577 case RELOAD_FOR_INSN:
4578 /* These conflict with other outputs with RELOAD_OTHER. So
4579 we need only check for output addresses. */
4581 opnum = reload_n_operands;
4583 /* ... fall through ... */
4585 case RELOAD_FOR_OUTPUT:
4586 case RELOAD_FOR_OUTPUT_ADDRESS:
4587 case RELOAD_FOR_OUTADDR_ADDRESS:
4588 /* We already know these can't conflict with a later output. So the
4589 only thing to check are later output addresses.
4590 Note that multiple output operands are emitted in reverse order,
4591 so the conflicting ones are those with lower indices. */
4592 for (i = 0; i < opnum; i++)
4593 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4594 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4604 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4607 This function uses the same algorithm as reload_reg_free_p above. */
4610 reloads_conflict (int r1, int r2)
4612 enum reload_type r1_type = rld[r1].when_needed;
4613 enum reload_type r2_type = rld[r2].when_needed;
4614 int r1_opnum = rld[r1].opnum;
4615 int r2_opnum = rld[r2].opnum;
4617 /* RELOAD_OTHER conflicts with everything. */
4618 if (r2_type == RELOAD_OTHER)
4621 /* Otherwise, check conflicts differently for each type. */
4625 case RELOAD_FOR_INPUT:
4626 return (r2_type == RELOAD_FOR_INSN
4627 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4628 || r2_type == RELOAD_FOR_OPADDR_ADDR
4629 || r2_type == RELOAD_FOR_INPUT
4630 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4631 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4632 && r2_opnum > r1_opnum));
4634 case RELOAD_FOR_INPUT_ADDRESS:
4635 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4636 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4638 case RELOAD_FOR_INPADDR_ADDRESS:
4639 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4640 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4642 case RELOAD_FOR_OUTPUT_ADDRESS:
4643 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4644 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4646 case RELOAD_FOR_OUTADDR_ADDRESS:
4647 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4648 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4650 case RELOAD_FOR_OPERAND_ADDRESS:
4651 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4652 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4654 case RELOAD_FOR_OPADDR_ADDR:
4655 return (r2_type == RELOAD_FOR_INPUT
4656 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4658 case RELOAD_FOR_OUTPUT:
4659 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4660 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4661 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4662 && r2_opnum >= r1_opnum));
4664 case RELOAD_FOR_INSN:
4665 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4666 || r2_type == RELOAD_FOR_INSN
4667 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4669 case RELOAD_FOR_OTHER_ADDRESS:
4670 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4680 /* Indexed by reload number, 1 if incoming value
4681 inherited from previous insns. */
4682 static char reload_inherited[MAX_RELOADS];
4684 /* For an inherited reload, this is the insn the reload was inherited from,
4685 if we know it. Otherwise, this is 0. */
4686 static rtx reload_inheritance_insn[MAX_RELOADS];
4688 /* If nonzero, this is a place to get the value of the reload,
4689 rather than using reload_in. */
4690 static rtx reload_override_in[MAX_RELOADS];
4692 /* For each reload, the hard register number of the register used,
4693 or -1 if we did not need a register for this reload. */
4694 static int reload_spill_index[MAX_RELOADS];
4696 /* Subroutine of free_for_value_p, used to check a single register.
4697 START_REGNO is the starting regno of the full reload register
4698 (possibly comprising multiple hard registers) that we are considering. */
4701 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4702 enum reload_type type, rtx value, rtx out,
4703 int reloadnum, int ignore_address_reloads)
4706 /* Set if we see an input reload that must not share its reload register
4707 with any new earlyclobber, but might otherwise share the reload
4708 register with an output or input-output reload. */
4709 int check_earlyclobber = 0;
4713 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4716 if (out == const0_rtx)
4722 /* We use some pseudo 'time' value to check if the lifetimes of the
4723 new register use would overlap with the one of a previous reload
4724 that is not read-only or uses a different value.
4725 The 'time' used doesn't have to be linear in any shape or form, just
4727 Some reload types use different 'buckets' for each operand.
4728 So there are MAX_RECOG_OPERANDS different time values for each
4730 We compute TIME1 as the time when the register for the prospective
4731 new reload ceases to be live, and TIME2 for each existing
4732 reload as the time when that the reload register of that reload
4734 Where there is little to be gained by exact lifetime calculations,
4735 we just make conservative assumptions, i.e. a longer lifetime;
4736 this is done in the 'default:' cases. */
4739 case RELOAD_FOR_OTHER_ADDRESS:
4740 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4741 time1 = copy ? 0 : 1;
4744 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4746 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4747 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4748 respectively, to the time values for these, we get distinct time
4749 values. To get distinct time values for each operand, we have to
4750 multiply opnum by at least three. We round that up to four because
4751 multiply by four is often cheaper. */
4752 case RELOAD_FOR_INPADDR_ADDRESS:
4753 time1 = opnum * 4 + 2;
4755 case RELOAD_FOR_INPUT_ADDRESS:
4756 time1 = opnum * 4 + 3;
4758 case RELOAD_FOR_INPUT:
4759 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4760 executes (inclusive). */
4761 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4763 case RELOAD_FOR_OPADDR_ADDR:
4765 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4766 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4768 case RELOAD_FOR_OPERAND_ADDRESS:
4769 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4771 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4773 case RELOAD_FOR_OUTADDR_ADDRESS:
4774 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4776 case RELOAD_FOR_OUTPUT_ADDRESS:
4777 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4780 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4783 for (i = 0; i < n_reloads; i++)
4785 rtx reg = rld[i].reg_rtx;
4786 if (reg && REG_P (reg)
4787 && ((unsigned) regno - true_regnum (reg)
4788 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
4791 rtx other_input = rld[i].in;
4793 /* If the other reload loads the same input value, that
4794 will not cause a conflict only if it's loading it into
4795 the same register. */
4796 if (true_regnum (reg) != start_regno)
4797 other_input = NULL_RTX;
4798 if (! other_input || ! rtx_equal_p (other_input, value)
4799 || rld[i].out || out)
4802 switch (rld[i].when_needed)
4804 case RELOAD_FOR_OTHER_ADDRESS:
4807 case RELOAD_FOR_INPADDR_ADDRESS:
4808 /* find_reloads makes sure that a
4809 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4810 by at most one - the first -
4811 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4812 address reload is inherited, the address address reload
4813 goes away, so we can ignore this conflict. */
4814 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4815 && ignore_address_reloads
4816 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4817 Then the address address is still needed to store
4818 back the new address. */
4819 && ! rld[reloadnum].out)
4821 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4822 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4824 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4825 && ignore_address_reloads
4826 /* Unless we are reloading an auto_inc expression. */
4827 && ! rld[reloadnum].out)
4829 time2 = rld[i].opnum * 4 + 2;
4831 case RELOAD_FOR_INPUT_ADDRESS:
4832 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4833 && ignore_address_reloads
4834 && ! rld[reloadnum].out)
4836 time2 = rld[i].opnum * 4 + 3;
4838 case RELOAD_FOR_INPUT:
4839 time2 = rld[i].opnum * 4 + 4;
4840 check_earlyclobber = 1;
4842 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4843 == MAX_RECOG_OPERAND * 4 */
4844 case RELOAD_FOR_OPADDR_ADDR:
4845 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4846 && ignore_address_reloads
4847 && ! rld[reloadnum].out)
4849 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4851 case RELOAD_FOR_OPERAND_ADDRESS:
4852 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4853 check_earlyclobber = 1;
4855 case RELOAD_FOR_INSN:
4856 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4858 case RELOAD_FOR_OUTPUT:
4859 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4860 instruction is executed. */
4861 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4863 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4864 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4866 case RELOAD_FOR_OUTADDR_ADDRESS:
4867 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4868 && ignore_address_reloads
4869 && ! rld[reloadnum].out)
4871 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4873 case RELOAD_FOR_OUTPUT_ADDRESS:
4874 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4877 /* If there is no conflict in the input part, handle this
4878 like an output reload. */
4879 if (! rld[i].in || rtx_equal_p (other_input, value))
4881 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4882 /* Earlyclobbered outputs must conflict with inputs. */
4883 if (earlyclobber_operand_p (rld[i].out))
4884 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4889 /* RELOAD_OTHER might be live beyond instruction execution,
4890 but this is not obvious when we set time2 = 1. So check
4891 here if there might be a problem with the new reload
4892 clobbering the register used by the RELOAD_OTHER. */
4900 && (! rld[i].in || rld[i].out
4901 || ! rtx_equal_p (other_input, value)))
4902 || (out && rld[reloadnum].out_reg
4903 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4909 /* Earlyclobbered outputs must conflict with inputs. */
4910 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4916 /* Return 1 if the value in reload reg REGNO, as used by a reload
4917 needed for the part of the insn specified by OPNUM and TYPE,
4918 may be used to load VALUE into it.
4920 MODE is the mode in which the register is used, this is needed to
4921 determine how many hard regs to test.
4923 Other read-only reloads with the same value do not conflict
4924 unless OUT is nonzero and these other reloads have to live while
4925 output reloads live.
4926 If OUT is CONST0_RTX, this is a special case: it means that the
4927 test should not be for using register REGNO as reload register, but
4928 for copying from register REGNO into the reload register.
4930 RELOADNUM is the number of the reload we want to load this value for;
4931 a reload does not conflict with itself.
4933 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4934 reloads that load an address for the very reload we are considering.
4936 The caller has to make sure that there is no conflict with the return
4940 free_for_value_p (int regno, enum machine_mode mode, int opnum,
4941 enum reload_type type, rtx value, rtx out, int reloadnum,
4942 int ignore_address_reloads)
4944 int nregs = hard_regno_nregs[regno][mode];
4946 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
4947 value, out, reloadnum,
4948 ignore_address_reloads))
4953 /* Return nonzero if the rtx X is invariant over the current function. */
4954 /* ??? Actually, the places where we use this expect exactly what
4955 * is tested here, and not everything that is function invariant. In
4956 * particular, the frame pointer and arg pointer are special cased;
4957 * pic_offset_table_rtx is not, and this will cause aborts when we
4958 * go to spill these things to memory. */
4961 function_invariant_p (rtx x)
4965 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4967 if (GET_CODE (x) == PLUS
4968 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
4969 && CONSTANT_P (XEXP (x, 1)))
4974 /* Determine whether the reload reg X overlaps any rtx'es used for
4975 overriding inheritance. Return nonzero if so. */
4978 conflicts_with_override (rtx x)
4981 for (i = 0; i < n_reloads; i++)
4982 if (reload_override_in[i]
4983 && reg_overlap_mentioned_p (x, reload_override_in[i]))
4988 /* Give an error message saying we failed to find a reload for INSN,
4989 and clear out reload R. */
4991 failed_reload (rtx insn, int r)
4993 if (asm_noperands (PATTERN (insn)) < 0)
4994 /* It's the compiler's fault. */
4995 fatal_insn ("could not find a spill register", insn);
4997 /* It's the user's fault; the operand's mode and constraint
4998 don't match. Disable this reload so we don't crash in final. */
4999 error_for_asm (insn,
5000 "%<asm%> operand constraint incompatible with operand size");
5004 rld[r].optional = 1;
5005 rld[r].secondary_p = 1;
5008 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5009 for reload R. If it's valid, get an rtx for it. Return nonzero if
5012 set_reload_reg (int i, int r)
5015 rtx reg = spill_reg_rtx[i];
5017 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5018 spill_reg_rtx[i] = reg
5019 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5021 regno = true_regnum (reg);
5023 /* Detect when the reload reg can't hold the reload mode.
5024 This used to be one `if', but Sequent compiler can't handle that. */
5025 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5027 enum machine_mode test_mode = VOIDmode;
5029 test_mode = GET_MODE (rld[r].in);
5030 /* If rld[r].in has VOIDmode, it means we will load it
5031 in whatever mode the reload reg has: to wit, rld[r].mode.
5032 We have already tested that for validity. */
5033 /* Aside from that, we need to test that the expressions
5034 to reload from or into have modes which are valid for this
5035 reload register. Otherwise the reload insns would be invalid. */
5036 if (! (rld[r].in != 0 && test_mode != VOIDmode
5037 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5038 if (! (rld[r].out != 0
5039 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5041 /* The reg is OK. */
5044 /* Mark as in use for this insn the reload regs we use
5046 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5047 rld[r].when_needed, rld[r].mode);
5049 rld[r].reg_rtx = reg;
5050 reload_spill_index[r] = spill_regs[i];
5057 /* Find a spill register to use as a reload register for reload R.
5058 LAST_RELOAD is nonzero if this is the last reload for the insn being
5061 Set rld[R].reg_rtx to the register allocated.
5063 We return 1 if successful, or 0 if we couldn't find a spill reg and
5064 we didn't change anything. */
5067 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5072 /* If we put this reload ahead, thinking it is a group,
5073 then insist on finding a group. Otherwise we can grab a
5074 reg that some other reload needs.
5075 (That can happen when we have a 68000 DATA_OR_FP_REG
5076 which is a group of data regs or one fp reg.)
5077 We need not be so restrictive if there are no more reloads
5080 ??? Really it would be nicer to have smarter handling
5081 for that kind of reg class, where a problem like this is normal.
5082 Perhaps those classes should be avoided for reloading
5083 by use of more alternatives. */
5085 int force_group = rld[r].nregs > 1 && ! last_reload;
5087 /* If we want a single register and haven't yet found one,
5088 take any reg in the right class and not in use.
5089 If we want a consecutive group, here is where we look for it.
5091 We use two passes so we can first look for reload regs to
5092 reuse, which are already in use for other reloads in this insn,
5093 and only then use additional registers.
5094 I think that maximizing reuse is needed to make sure we don't
5095 run out of reload regs. Suppose we have three reloads, and
5096 reloads A and B can share regs. These need two regs.
5097 Suppose A and B are given different regs.
5098 That leaves none for C. */
5099 for (pass = 0; pass < 2; pass++)
5101 /* I is the index in spill_regs.
5102 We advance it round-robin between insns to use all spill regs
5103 equally, so that inherited reloads have a chance
5104 of leapfrogging each other. */
5108 for (count = 0; count < n_spills; count++)
5110 int class = (int) rld[r].class;
5116 regnum = spill_regs[i];
5118 if ((reload_reg_free_p (regnum, rld[r].opnum,
5121 /* We check reload_reg_used to make sure we
5122 don't clobber the return register. */
5123 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5124 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5125 rld[r].when_needed, rld[r].in,
5127 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5128 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5129 /* Look first for regs to share, then for unshared. But
5130 don't share regs used for inherited reloads; they are
5131 the ones we want to preserve. */
5133 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5135 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5138 int nr = hard_regno_nregs[regnum][rld[r].mode];
5139 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5140 (on 68000) got us two FP regs. If NR is 1,
5141 we would reject both of them. */
5144 /* If we need only one reg, we have already won. */
5147 /* But reject a single reg if we demand a group. */
5152 /* Otherwise check that as many consecutive regs as we need
5153 are available here. */
5156 int regno = regnum + nr - 1;
5157 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5158 && spill_reg_order[regno] >= 0
5159 && reload_reg_free_p (regno, rld[r].opnum,
5160 rld[r].when_needed)))
5169 /* If we found something on pass 1, omit pass 2. */
5170 if (count < n_spills)
5174 /* We should have found a spill register by now. */
5175 if (count >= n_spills)
5178 /* I is the index in SPILL_REG_RTX of the reload register we are to
5179 allocate. Get an rtx for it and find its register number. */
5181 return set_reload_reg (i, r);
5184 /* Initialize all the tables needed to allocate reload registers.
5185 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5186 is the array we use to restore the reg_rtx field for every reload. */
5189 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5193 for (i = 0; i < n_reloads; i++)
5194 rld[i].reg_rtx = save_reload_reg_rtx[i];
5196 memset (reload_inherited, 0, MAX_RELOADS);
5197 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5198 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5200 CLEAR_HARD_REG_SET (reload_reg_used);
5201 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5202 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5203 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5204 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5205 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5207 CLEAR_HARD_REG_SET (reg_used_in_insn);
5210 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5211 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5212 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5213 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5214 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5215 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5218 for (i = 0; i < reload_n_operands; i++)
5220 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5221 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5222 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5223 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5224 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5225 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5228 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5230 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5232 for (i = 0; i < n_reloads; i++)
5233 /* If we have already decided to use a certain register,
5234 don't use it in another way. */
5236 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5237 rld[i].when_needed, rld[i].mode);
5240 /* Assign hard reg targets for the pseudo-registers we must reload
5241 into hard regs for this insn.
5242 Also output the instructions to copy them in and out of the hard regs.
5244 For machines with register classes, we are responsible for
5245 finding a reload reg in the proper class. */
5248 choose_reload_regs (struct insn_chain *chain)
5250 rtx insn = chain->insn;
5252 unsigned int max_group_size = 1;
5253 enum reg_class group_class = NO_REGS;
5254 int pass, win, inheritance;
5256 rtx save_reload_reg_rtx[MAX_RELOADS];
5258 /* In order to be certain of getting the registers we need,
5259 we must sort the reloads into order of increasing register class.
5260 Then our grabbing of reload registers will parallel the process
5261 that provided the reload registers.
5263 Also note whether any of the reloads wants a consecutive group of regs.
5264 If so, record the maximum size of the group desired and what
5265 register class contains all the groups needed by this insn. */
5267 for (j = 0; j < n_reloads; j++)
5269 reload_order[j] = j;
5270 reload_spill_index[j] = -1;
5272 if (rld[j].nregs > 1)
5274 max_group_size = MAX (rld[j].nregs, max_group_size);
5276 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5279 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5283 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5285 /* If -O, try first with inheritance, then turning it off.
5286 If not -O, don't do inheritance.
5287 Using inheritance when not optimizing leads to paradoxes
5288 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5289 because one side of the comparison might be inherited. */
5291 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5293 choose_reload_regs_init (chain, save_reload_reg_rtx);
5295 /* Process the reloads in order of preference just found.
5296 Beyond this point, subregs can be found in reload_reg_rtx.
5298 This used to look for an existing reloaded home for all of the
5299 reloads, and only then perform any new reloads. But that could lose
5300 if the reloads were done out of reg-class order because a later
5301 reload with a looser constraint might have an old home in a register
5302 needed by an earlier reload with a tighter constraint.
5304 To solve this, we make two passes over the reloads, in the order
5305 described above. In the first pass we try to inherit a reload
5306 from a previous insn. If there is a later reload that needs a
5307 class that is a proper subset of the class being processed, we must
5308 also allocate a spill register during the first pass.
5310 Then make a second pass over the reloads to allocate any reloads
5311 that haven't been given registers yet. */
5313 for (j = 0; j < n_reloads; j++)
5315 int r = reload_order[j];
5316 rtx search_equiv = NULL_RTX;
5318 /* Ignore reloads that got marked inoperative. */
5319 if (rld[r].out == 0 && rld[r].in == 0
5320 && ! rld[r].secondary_p)
5323 /* If find_reloads chose to use reload_in or reload_out as a reload
5324 register, we don't need to chose one. Otherwise, try even if it
5325 found one since we might save an insn if we find the value lying
5327 Try also when reload_in is a pseudo without a hard reg. */
5328 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5329 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5330 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5331 && !MEM_P (rld[r].in)
5332 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5335 #if 0 /* No longer needed for correct operation.
5336 It might give better code, or might not; worth an experiment? */
5337 /* If this is an optional reload, we can't inherit from earlier insns
5338 until we are sure that any non-optional reloads have been allocated.
5339 The following code takes advantage of the fact that optional reloads
5340 are at the end of reload_order. */
5341 if (rld[r].optional != 0)
5342 for (i = 0; i < j; i++)
5343 if ((rld[reload_order[i]].out != 0
5344 || rld[reload_order[i]].in != 0
5345 || rld[reload_order[i]].secondary_p)
5346 && ! rld[reload_order[i]].optional
5347 && rld[reload_order[i]].reg_rtx == 0)
5348 allocate_reload_reg (chain, reload_order[i], 0);
5351 /* First see if this pseudo is already available as reloaded
5352 for a previous insn. We cannot try to inherit for reloads
5353 that are smaller than the maximum number of registers needed
5354 for groups unless the register we would allocate cannot be used
5357 We could check here to see if this is a secondary reload for
5358 an object that is already in a register of the desired class.
5359 This would avoid the need for the secondary reload register.
5360 But this is complex because we can't easily determine what
5361 objects might want to be loaded via this reload. So let a
5362 register be allocated here. In `emit_reload_insns' we suppress
5363 one of the loads in the case described above. */
5369 enum machine_mode mode = VOIDmode;
5373 else if (REG_P (rld[r].in))
5375 regno = REGNO (rld[r].in);
5376 mode = GET_MODE (rld[r].in);
5378 else if (REG_P (rld[r].in_reg))
5380 regno = REGNO (rld[r].in_reg);
5381 mode = GET_MODE (rld[r].in_reg);
5383 else if (GET_CODE (rld[r].in_reg) == SUBREG
5384 && REG_P (SUBREG_REG (rld[r].in_reg)))
5386 byte = SUBREG_BYTE (rld[r].in_reg);
5387 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5388 if (regno < FIRST_PSEUDO_REGISTER)
5389 regno = subreg_regno (rld[r].in_reg);
5390 mode = GET_MODE (rld[r].in_reg);
5393 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5394 || GET_CODE (rld[r].in_reg) == PRE_DEC
5395 || GET_CODE (rld[r].in_reg) == POST_INC
5396 || GET_CODE (rld[r].in_reg) == POST_DEC)
5397 && REG_P (XEXP (rld[r].in_reg, 0)))
5399 regno = REGNO (XEXP (rld[r].in_reg, 0));
5400 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5401 rld[r].out = rld[r].in;
5405 /* This won't work, since REGNO can be a pseudo reg number.
5406 Also, it takes much more hair to keep track of all the things
5407 that can invalidate an inherited reload of part of a pseudoreg. */
5408 else if (GET_CODE (rld[r].in) == SUBREG
5409 && REG_P (SUBREG_REG (rld[r].in)))
5410 regno = subreg_regno (rld[r].in);
5413 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5415 enum reg_class class = rld[r].class, last_class;
5416 rtx last_reg = reg_last_reload_reg[regno];
5417 enum machine_mode need_mode;
5419 i = REGNO (last_reg);
5420 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5421 last_class = REGNO_REG_CLASS (i);
5427 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
5428 + byte * BITS_PER_UNIT,
5429 GET_MODE_CLASS (mode));
5431 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5432 >= GET_MODE_SIZE (need_mode))
5433 #ifdef CANNOT_CHANGE_MODE_CLASS
5434 /* Verify that the register in "i" can be obtained
5436 && !REG_CANNOT_CHANGE_MODE_P (REGNO (last_reg),
5437 GET_MODE (last_reg),
5440 && reg_reloaded_contents[i] == regno
5441 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5442 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5443 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5444 /* Even if we can't use this register as a reload
5445 register, we might use it for reload_override_in,
5446 if copying it to the desired class is cheap
5448 || ((REGISTER_MOVE_COST (mode, last_class, class)
5449 < MEMORY_MOVE_COST (mode, class, 1))
5450 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5451 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5455 #ifdef SECONDARY_MEMORY_NEEDED
5456 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5461 && (rld[r].nregs == max_group_size
5462 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5464 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5465 rld[r].when_needed, rld[r].in,
5468 /* If a group is needed, verify that all the subsequent
5469 registers still have their values intact. */
5470 int nr = hard_regno_nregs[i][rld[r].mode];
5473 for (k = 1; k < nr; k++)
5474 if (reg_reloaded_contents[i + k] != regno
5475 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5483 last_reg = (GET_MODE (last_reg) == mode
5484 ? last_reg : gen_rtx_REG (mode, i));
5487 for (k = 0; k < nr; k++)
5488 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5491 /* We found a register that contains the
5492 value we need. If this register is the
5493 same as an `earlyclobber' operand of the
5494 current insn, just mark it as a place to
5495 reload from since we can't use it as the
5496 reload register itself. */
5498 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5499 if (reg_overlap_mentioned_for_reload_p
5500 (reg_last_reload_reg[regno],
5501 reload_earlyclobbers[i1]))
5504 if (i1 != n_earlyclobbers
5505 || ! (free_for_value_p (i, rld[r].mode,
5507 rld[r].when_needed, rld[r].in,
5509 /* Don't use it if we'd clobber a pseudo reg. */
5510 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5512 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5513 /* Don't clobber the frame pointer. */
5514 || (i == HARD_FRAME_POINTER_REGNUM
5515 && frame_pointer_needed
5517 /* Don't really use the inherited spill reg
5518 if we need it wider than we've got it. */
5519 || (GET_MODE_SIZE (rld[r].mode)
5520 > GET_MODE_SIZE (mode))
5523 /* If find_reloads chose reload_out as reload
5524 register, stay with it - that leaves the
5525 inherited register for subsequent reloads. */
5526 || (rld[r].out && rld[r].reg_rtx
5527 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5529 if (! rld[r].optional)
5531 reload_override_in[r] = last_reg;
5532 reload_inheritance_insn[r]
5533 = reg_reloaded_insn[i];
5539 /* We can use this as a reload reg. */
5540 /* Mark the register as in use for this part of
5542 mark_reload_reg_in_use (i,
5546 rld[r].reg_rtx = last_reg;
5547 reload_inherited[r] = 1;
5548 reload_inheritance_insn[r]
5549 = reg_reloaded_insn[i];
5550 reload_spill_index[r] = i;
5551 for (k = 0; k < nr; k++)
5552 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5560 /* Here's another way to see if the value is already lying around. */
5563 && ! reload_inherited[r]
5565 && (CONSTANT_P (rld[r].in)
5566 || GET_CODE (rld[r].in) == PLUS
5567 || REG_P (rld[r].in)
5568 || MEM_P (rld[r].in))
5569 && (rld[r].nregs == max_group_size
5570 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5571 search_equiv = rld[r].in;
5572 /* If this is an output reload from a simple move insn, look
5573 if an equivalence for the input is available. */
5574 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5576 rtx set = single_set (insn);
5579 && rtx_equal_p (rld[r].out, SET_DEST (set))
5580 && CONSTANT_P (SET_SRC (set)))
5581 search_equiv = SET_SRC (set);
5587 = find_equiv_reg (search_equiv, insn, rld[r].class,
5588 -1, NULL, 0, rld[r].mode);
5594 regno = REGNO (equiv);
5597 /* This must be a SUBREG of a hard register.
5598 Make a new REG since this might be used in an
5599 address and not all machines support SUBREGs
5601 gcc_assert (GET_CODE (equiv) == SUBREG);
5602 regno = subreg_regno (equiv);
5603 equiv = gen_rtx_REG (rld[r].mode, regno);
5604 /* If we choose EQUIV as the reload register, but the
5605 loop below decides to cancel the inheritance, we'll
5606 end up reloading EQUIV in rld[r].mode, not the mode
5607 it had originally. That isn't safe when EQUIV isn't
5608 available as a spill register since its value might
5609 still be live at this point. */
5610 for (i = regno; i < regno + (int) rld[r].nregs; i++)
5611 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
5616 /* If we found a spill reg, reject it unless it is free
5617 and of the desired class. */
5621 int bad_for_class = 0;
5622 int max_regno = regno + rld[r].nregs;
5624 for (i = regno; i < max_regno; i++)
5626 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5628 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5633 && ! free_for_value_p (regno, rld[r].mode,
5634 rld[r].opnum, rld[r].when_needed,
5635 rld[r].in, rld[r].out, r, 1))
5640 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5643 /* We found a register that contains the value we need.
5644 If this register is the same as an `earlyclobber' operand
5645 of the current insn, just mark it as a place to reload from
5646 since we can't use it as the reload register itself. */
5649 for (i = 0; i < n_earlyclobbers; i++)
5650 if (reg_overlap_mentioned_for_reload_p (equiv,
5651 reload_earlyclobbers[i]))
5653 if (! rld[r].optional)
5654 reload_override_in[r] = equiv;
5659 /* If the equiv register we have found is explicitly clobbered
5660 in the current insn, it depends on the reload type if we
5661 can use it, use it for reload_override_in, or not at all.
5662 In particular, we then can't use EQUIV for a
5663 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5667 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5668 switch (rld[r].when_needed)
5670 case RELOAD_FOR_OTHER_ADDRESS:
5671 case RELOAD_FOR_INPADDR_ADDRESS:
5672 case RELOAD_FOR_INPUT_ADDRESS:
5673 case RELOAD_FOR_OPADDR_ADDR:
5676 case RELOAD_FOR_INPUT:
5677 case RELOAD_FOR_OPERAND_ADDRESS:
5678 if (! rld[r].optional)
5679 reload_override_in[r] = equiv;
5685 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5686 switch (rld[r].when_needed)
5688 case RELOAD_FOR_OTHER_ADDRESS:
5689 case RELOAD_FOR_INPADDR_ADDRESS:
5690 case RELOAD_FOR_INPUT_ADDRESS:
5691 case RELOAD_FOR_OPADDR_ADDR:
5692 case RELOAD_FOR_OPERAND_ADDRESS:
5693 case RELOAD_FOR_INPUT:
5696 if (! rld[r].optional)
5697 reload_override_in[r] = equiv;
5705 /* If we found an equivalent reg, say no code need be generated
5706 to load it, and use it as our reload reg. */
5708 && (regno != HARD_FRAME_POINTER_REGNUM
5709 || !frame_pointer_needed))
5711 int nr = hard_regno_nregs[regno][rld[r].mode];
5713 rld[r].reg_rtx = equiv;
5714 reload_inherited[r] = 1;
5716 /* If reg_reloaded_valid is not set for this register,
5717 there might be a stale spill_reg_store lying around.
5718 We must clear it, since otherwise emit_reload_insns
5719 might delete the store. */
5720 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5721 spill_reg_store[regno] = NULL_RTX;
5722 /* If any of the hard registers in EQUIV are spill
5723 registers, mark them as in use for this insn. */
5724 for (k = 0; k < nr; k++)
5726 i = spill_reg_order[regno + k];
5729 mark_reload_reg_in_use (regno, rld[r].opnum,
5732 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5739 /* If we found a register to use already, or if this is an optional
5740 reload, we are done. */
5741 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5745 /* No longer needed for correct operation. Might or might
5746 not give better code on the average. Want to experiment? */
5748 /* See if there is a later reload that has a class different from our
5749 class that intersects our class or that requires less register
5750 than our reload. If so, we must allocate a register to this
5751 reload now, since that reload might inherit a previous reload
5752 and take the only available register in our class. Don't do this
5753 for optional reloads since they will force all previous reloads
5754 to be allocated. Also don't do this for reloads that have been
5757 for (i = j + 1; i < n_reloads; i++)
5759 int s = reload_order[i];
5761 if ((rld[s].in == 0 && rld[s].out == 0
5762 && ! rld[s].secondary_p)
5766 if ((rld[s].class != rld[r].class
5767 && reg_classes_intersect_p (rld[r].class,
5769 || rld[s].nregs < rld[r].nregs)
5776 allocate_reload_reg (chain, r, j == n_reloads - 1);
5780 /* Now allocate reload registers for anything non-optional that
5781 didn't get one yet. */
5782 for (j = 0; j < n_reloads; j++)
5784 int r = reload_order[j];
5786 /* Ignore reloads that got marked inoperative. */
5787 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5790 /* Skip reloads that already have a register allocated or are
5792 if (rld[r].reg_rtx != 0 || rld[r].optional)
5795 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5799 /* If that loop got all the way, we have won. */
5806 /* Loop around and try without any inheritance. */
5811 /* First undo everything done by the failed attempt
5812 to allocate with inheritance. */
5813 choose_reload_regs_init (chain, save_reload_reg_rtx);
5815 /* Some sanity tests to verify that the reloads found in the first
5816 pass are identical to the ones we have now. */
5817 gcc_assert (chain->n_reloads == n_reloads);
5819 for (i = 0; i < n_reloads; i++)
5821 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5823 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
5824 for (j = 0; j < n_spills; j++)
5825 if (spill_regs[j] == chain->rld[i].regno)
5826 if (! set_reload_reg (j, i))
5827 failed_reload (chain->insn, i);
5831 /* If we thought we could inherit a reload, because it seemed that
5832 nothing else wanted the same reload register earlier in the insn,
5833 verify that assumption, now that all reloads have been assigned.
5834 Likewise for reloads where reload_override_in has been set. */
5836 /* If doing expensive optimizations, do one preliminary pass that doesn't
5837 cancel any inheritance, but removes reloads that have been needed only
5838 for reloads that we know can be inherited. */
5839 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5841 for (j = 0; j < n_reloads; j++)
5843 int r = reload_order[j];
5845 if (reload_inherited[r] && rld[r].reg_rtx)
5846 check_reg = rld[r].reg_rtx;
5847 else if (reload_override_in[r]
5848 && (REG_P (reload_override_in[r])
5849 || GET_CODE (reload_override_in[r]) == SUBREG))
5850 check_reg = reload_override_in[r];
5853 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5854 rld[r].opnum, rld[r].when_needed, rld[r].in,
5855 (reload_inherited[r]
5856 ? rld[r].out : const0_rtx),
5861 reload_inherited[r] = 0;
5862 reload_override_in[r] = 0;
5864 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5865 reload_override_in, then we do not need its related
5866 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5867 likewise for other reload types.
5868 We handle this by removing a reload when its only replacement
5869 is mentioned in reload_in of the reload we are going to inherit.
5870 A special case are auto_inc expressions; even if the input is
5871 inherited, we still need the address for the output. We can
5872 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5873 If we succeeded removing some reload and we are doing a preliminary
5874 pass just to remove such reloads, make another pass, since the
5875 removal of one reload might allow us to inherit another one. */
5877 && rld[r].out != rld[r].in
5878 && remove_address_replacements (rld[r].in) && pass)
5883 /* Now that reload_override_in is known valid,
5884 actually override reload_in. */
5885 for (j = 0; j < n_reloads; j++)
5886 if (reload_override_in[j])
5887 rld[j].in = reload_override_in[j];
5889 /* If this reload won't be done because it has been canceled or is
5890 optional and not inherited, clear reload_reg_rtx so other
5891 routines (such as subst_reloads) don't get confused. */
5892 for (j = 0; j < n_reloads; j++)
5893 if (rld[j].reg_rtx != 0
5894 && ((rld[j].optional && ! reload_inherited[j])
5895 || (rld[j].in == 0 && rld[j].out == 0
5896 && ! rld[j].secondary_p)))
5898 int regno = true_regnum (rld[j].reg_rtx);
5900 if (spill_reg_order[regno] >= 0)
5901 clear_reload_reg_in_use (regno, rld[j].opnum,
5902 rld[j].when_needed, rld[j].mode);
5904 reload_spill_index[j] = -1;
5907 /* Record which pseudos and which spill regs have output reloads. */
5908 for (j = 0; j < n_reloads; j++)
5910 int r = reload_order[j];
5912 i = reload_spill_index[r];
5914 /* I is nonneg if this reload uses a register.
5915 If rld[r].reg_rtx is 0, this is an optional reload
5916 that we opted to ignore. */
5917 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
5918 && rld[r].reg_rtx != 0)
5920 int nregno = REGNO (rld[r].out_reg);
5923 if (nregno < FIRST_PSEUDO_REGISTER)
5924 nr = hard_regno_nregs[nregno][rld[r].mode];
5927 reg_has_output_reload[nregno + nr] = 1;
5931 nr = hard_regno_nregs[i][rld[r].mode];
5933 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5936 gcc_assert (rld[r].when_needed == RELOAD_OTHER
5937 || rld[r].when_needed == RELOAD_FOR_OUTPUT
5938 || rld[r].when_needed == RELOAD_FOR_INSN);
5943 /* Deallocate the reload register for reload R. This is called from
5944 remove_address_replacements. */
5947 deallocate_reload_reg (int r)
5951 if (! rld[r].reg_rtx)
5953 regno = true_regnum (rld[r].reg_rtx);
5955 if (spill_reg_order[regno] >= 0)
5956 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5958 reload_spill_index[r] = -1;
5961 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
5962 reloads of the same item for fear that we might not have enough reload
5963 registers. However, normally they will get the same reload register
5964 and hence actually need not be loaded twice.
5966 Here we check for the most common case of this phenomenon: when we have
5967 a number of reloads for the same object, each of which were allocated
5968 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5969 reload, and is not modified in the insn itself. If we find such,
5970 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5971 This will not increase the number of spill registers needed and will
5972 prevent redundant code. */
5975 merge_assigned_reloads (rtx insn)
5979 /* Scan all the reloads looking for ones that only load values and
5980 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5981 assigned and not modified by INSN. */
5983 for (i = 0; i < n_reloads; i++)
5985 int conflicting_input = 0;
5986 int max_input_address_opnum = -1;
5987 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
5989 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
5990 || rld[i].out != 0 || rld[i].reg_rtx == 0
5991 || reg_set_p (rld[i].reg_rtx, insn))
5994 /* Look at all other reloads. Ensure that the only use of this
5995 reload_reg_rtx is in a reload that just loads the same value
5996 as we do. Note that any secondary reloads must be of the identical
5997 class since the values, modes, and result registers are the
5998 same, so we need not do anything with any secondary reloads. */
6000 for (j = 0; j < n_reloads; j++)
6002 if (i == j || rld[j].reg_rtx == 0
6003 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6007 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6008 && rld[j].opnum > max_input_address_opnum)
6009 max_input_address_opnum = rld[j].opnum;
6011 /* If the reload regs aren't exactly the same (e.g, different modes)
6012 or if the values are different, we can't merge this reload.
6013 But if it is an input reload, we might still merge
6014 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6016 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6017 || rld[j].out != 0 || rld[j].in == 0
6018 || ! rtx_equal_p (rld[i].in, rld[j].in))
6020 if (rld[j].when_needed != RELOAD_FOR_INPUT
6021 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6022 || rld[i].opnum > rld[j].opnum)
6023 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6025 conflicting_input = 1;
6026 if (min_conflicting_input_opnum > rld[j].opnum)
6027 min_conflicting_input_opnum = rld[j].opnum;
6031 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6032 we, in fact, found any matching reloads. */
6035 && max_input_address_opnum <= min_conflicting_input_opnum)
6037 for (j = 0; j < n_reloads; j++)
6038 if (i != j && rld[j].reg_rtx != 0
6039 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6040 && (! conflicting_input
6041 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6042 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6044 rld[i].when_needed = RELOAD_OTHER;
6046 reload_spill_index[j] = -1;
6047 transfer_replacements (i, j);
6050 /* If this is now RELOAD_OTHER, look for any reloads that load
6051 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6052 if they were for inputs, RELOAD_OTHER for outputs. Note that
6053 this test is equivalent to looking for reloads for this operand
6055 /* We must take special care when there are two or more reloads to
6056 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6057 same value or a part of it; we must not change its type if there
6058 is a conflicting input. */
6060 if (rld[i].when_needed == RELOAD_OTHER)
6061 for (j = 0; j < n_reloads; j++)
6063 && rld[j].when_needed != RELOAD_OTHER
6064 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6065 && (! conflicting_input
6066 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6067 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6068 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6074 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6075 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6076 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6078 /* Check to see if we accidentally converted two reloads
6079 that use the same reload register with different inputs
6080 to the same type. If so, the resulting code won't work,
6083 for (k = 0; k < j; k++)
6084 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6085 || rld[k].when_needed != rld[j].when_needed
6086 || !rtx_equal_p (rld[k].reg_rtx,
6088 || rtx_equal_p (rld[k].in,
6095 /* These arrays are filled by emit_reload_insns and its subroutines. */
6096 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6097 static rtx other_input_address_reload_insns = 0;
6098 static rtx other_input_reload_insns = 0;
6099 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6100 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6101 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6102 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6103 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6104 static rtx operand_reload_insns = 0;
6105 static rtx other_operand_reload_insns = 0;
6106 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6108 /* Values to be put in spill_reg_store are put here first. */
6109 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6110 static HARD_REG_SET reg_reloaded_died;
6112 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6113 has the number J. OLD contains the value to be used as input. */
6116 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6119 rtx insn = chain->insn;
6120 rtx reloadreg = rl->reg_rtx;
6121 rtx oldequiv_reg = 0;
6124 enum machine_mode mode;
6127 /* Determine the mode to reload in.
6128 This is very tricky because we have three to choose from.
6129 There is the mode the insn operand wants (rl->inmode).
6130 There is the mode of the reload register RELOADREG.
6131 There is the intrinsic mode of the operand, which we could find
6132 by stripping some SUBREGs.
6133 It turns out that RELOADREG's mode is irrelevant:
6134 we can change that arbitrarily.
6136 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6137 then the reload reg may not support QImode moves, so use SImode.
6138 If foo is in memory due to spilling a pseudo reg, this is safe,
6139 because the QImode value is in the least significant part of a
6140 slot big enough for a SImode. If foo is some other sort of
6141 memory reference, then it is impossible to reload this case,
6142 so previous passes had better make sure this never happens.
6144 Then consider a one-word union which has SImode and one of its
6145 members is a float, being fetched as (SUBREG:SF union:SI).
6146 We must fetch that as SFmode because we could be loading into
6147 a float-only register. In this case OLD's mode is correct.
6149 Consider an immediate integer: it has VOIDmode. Here we need
6150 to get a mode from something else.
6152 In some cases, there is a fourth mode, the operand's
6153 containing mode. If the insn specifies a containing mode for
6154 this operand, it overrides all others.
6156 I am not sure whether the algorithm here is always right,
6157 but it does the right things in those cases. */
6159 mode = GET_MODE (old);
6160 if (mode == VOIDmode)
6163 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6164 /* If we need a secondary register for this operation, see if
6165 the value is already in a register in that class. Don't
6166 do this if the secondary register will be used as a scratch
6169 if (rl->secondary_in_reload >= 0
6170 && rl->secondary_in_icode == CODE_FOR_nothing
6173 = find_equiv_reg (old, insn,
6174 rld[rl->secondary_in_reload].class,
6178 /* If reloading from memory, see if there is a register
6179 that already holds the same value. If so, reload from there.
6180 We can pass 0 as the reload_reg_p argument because
6181 any other reload has either already been emitted,
6182 in which case find_equiv_reg will see the reload-insn,
6183 or has yet to be emitted, in which case it doesn't matter
6184 because we will use this equiv reg right away. */
6186 if (oldequiv == 0 && optimize
6189 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6190 && reg_renumber[REGNO (old)] < 0)))
6191 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6195 unsigned int regno = true_regnum (oldequiv);
6197 /* Don't use OLDEQUIV if any other reload changes it at an
6198 earlier stage of this insn or at this stage. */
6199 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6200 rl->in, const0_rtx, j, 0))
6203 /* If it is no cheaper to copy from OLDEQUIV into the
6204 reload register than it would be to move from memory,
6205 don't use it. Likewise, if we need a secondary register
6209 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6210 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6212 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6213 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6214 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6218 #ifdef SECONDARY_MEMORY_NEEDED
6219 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6227 /* delete_output_reload is only invoked properly if old contains
6228 the original pseudo register. Since this is replaced with a
6229 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6230 find the pseudo in RELOAD_IN_REG. */
6232 && reload_override_in[j]
6233 && REG_P (rl->in_reg))
6240 else if (REG_P (oldequiv))
6241 oldequiv_reg = oldequiv;
6242 else if (GET_CODE (oldequiv) == SUBREG)
6243 oldequiv_reg = SUBREG_REG (oldequiv);
6245 /* If we are reloading from a register that was recently stored in
6246 with an output-reload, see if we can prove there was
6247 actually no need to store the old value in it. */
6249 if (optimize && REG_P (oldequiv)
6250 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6251 && spill_reg_store[REGNO (oldequiv)]
6253 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6254 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6256 delete_output_reload (insn, j, REGNO (oldequiv));
6258 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6259 then load RELOADREG from OLDEQUIV. Note that we cannot use
6260 gen_lowpart_common since it can do the wrong thing when
6261 RELOADREG has a multi-word mode. Note that RELOADREG
6262 must always be a REG here. */
6264 if (GET_MODE (reloadreg) != mode)
6265 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6266 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6267 oldequiv = SUBREG_REG (oldequiv);
6268 if (GET_MODE (oldequiv) != VOIDmode
6269 && mode != GET_MODE (oldequiv))
6270 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6272 /* Switch to the right place to emit the reload insns. */
6273 switch (rl->when_needed)
6276 where = &other_input_reload_insns;
6278 case RELOAD_FOR_INPUT:
6279 where = &input_reload_insns[rl->opnum];
6281 case RELOAD_FOR_INPUT_ADDRESS:
6282 where = &input_address_reload_insns[rl->opnum];
6284 case RELOAD_FOR_INPADDR_ADDRESS:
6285 where = &inpaddr_address_reload_insns[rl->opnum];
6287 case RELOAD_FOR_OUTPUT_ADDRESS:
6288 where = &output_address_reload_insns[rl->opnum];
6290 case RELOAD_FOR_OUTADDR_ADDRESS:
6291 where = &outaddr_address_reload_insns[rl->opnum];
6293 case RELOAD_FOR_OPERAND_ADDRESS:
6294 where = &operand_reload_insns;
6296 case RELOAD_FOR_OPADDR_ADDR:
6297 where = &other_operand_reload_insns;
6299 case RELOAD_FOR_OTHER_ADDRESS:
6300 where = &other_input_address_reload_insns;
6306 push_to_sequence (*where);
6308 /* Auto-increment addresses must be reloaded in a special way. */
6309 if (rl->out && ! rl->out_reg)
6311 /* We are not going to bother supporting the case where a
6312 incremented register can't be copied directly from
6313 OLDEQUIV since this seems highly unlikely. */
6314 gcc_assert (rl->secondary_in_reload < 0);
6316 if (reload_inherited[j])
6317 oldequiv = reloadreg;
6319 old = XEXP (rl->in_reg, 0);
6321 if (optimize && REG_P (oldequiv)
6322 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6323 && spill_reg_store[REGNO (oldequiv)]
6325 && (dead_or_set_p (insn,
6326 spill_reg_stored_to[REGNO (oldequiv)])
6327 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6329 delete_output_reload (insn, j, REGNO (oldequiv));
6331 /* Prevent normal processing of this reload. */
6333 /* Output a special code sequence for this case. */
6334 new_spill_reg_store[REGNO (reloadreg)]
6335 = inc_for_reload (reloadreg, oldequiv, rl->out,
6339 /* If we are reloading a pseudo-register that was set by the previous
6340 insn, see if we can get rid of that pseudo-register entirely
6341 by redirecting the previous insn into our reload register. */
6343 else if (optimize && REG_P (old)
6344 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6345 && dead_or_set_p (insn, old)
6346 /* This is unsafe if some other reload
6347 uses the same reg first. */
6348 && ! conflicts_with_override (reloadreg)
6349 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6350 rl->when_needed, old, rl->out, j, 0))
6352 rtx temp = PREV_INSN (insn);
6353 while (temp && NOTE_P (temp))
6354 temp = PREV_INSN (temp);
6356 && NONJUMP_INSN_P (temp)
6357 && GET_CODE (PATTERN (temp)) == SET
6358 && SET_DEST (PATTERN (temp)) == old
6359 /* Make sure we can access insn_operand_constraint. */
6360 && asm_noperands (PATTERN (temp)) < 0
6361 /* This is unsafe if operand occurs more than once in current
6362 insn. Perhaps some occurrences aren't reloaded. */
6363 && count_occurrences (PATTERN (insn), old, 0) == 1)
6365 rtx old = SET_DEST (PATTERN (temp));
6366 /* Store into the reload register instead of the pseudo. */
6367 SET_DEST (PATTERN (temp)) = reloadreg;
6369 /* Verify that resulting insn is valid. */
6370 extract_insn (temp);
6371 if (constrain_operands (1))
6373 /* If the previous insn is an output reload, the source is
6374 a reload register, and its spill_reg_store entry will
6375 contain the previous destination. This is now
6377 if (REG_P (SET_SRC (PATTERN (temp)))
6378 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6380 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6381 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6384 /* If these are the only uses of the pseudo reg,
6385 pretend for GDB it lives in the reload reg we used. */
6386 if (REG_N_DEATHS (REGNO (old)) == 1
6387 && REG_N_SETS (REGNO (old)) == 1)
6389 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6390 alter_reg (REGNO (old), -1);
6396 SET_DEST (PATTERN (temp)) = old;
6401 /* We can't do that, so output an insn to load RELOADREG. */
6403 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6404 /* If we have a secondary reload, pick up the secondary register
6405 and icode, if any. If OLDEQUIV and OLD are different or
6406 if this is an in-out reload, recompute whether or not we
6407 still need a secondary register and what the icode should
6408 be. If we still need a secondary register and the class or
6409 icode is different, go back to reloading from OLD if using
6410 OLDEQUIV means that we got the wrong type of register. We
6411 cannot have different class or icode due to an in-out reload
6412 because we don't make such reloads when both the input and
6413 output need secondary reload registers. */
6415 if (! special && rl->secondary_in_reload >= 0)
6417 rtx second_reload_reg = 0;
6418 int secondary_reload = rl->secondary_in_reload;
6419 rtx real_oldequiv = oldequiv;
6422 enum insn_code icode;
6424 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6425 and similarly for OLD.
6426 See comments in get_secondary_reload in reload.c. */
6427 /* If it is a pseudo that cannot be replaced with its
6428 equivalent MEM, we must fall back to reload_in, which
6429 will have all the necessary substitutions registered.
6430 Likewise for a pseudo that can't be replaced with its
6431 equivalent constant.
6433 Take extra care for subregs of such pseudos. Note that
6434 we cannot use reg_equiv_mem in this case because it is
6435 not in the right mode. */
6438 if (GET_CODE (tmp) == SUBREG)
6439 tmp = SUBREG_REG (tmp);
6441 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6442 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6443 || reg_equiv_constant[REGNO (tmp)] != 0))
6445 if (! reg_equiv_mem[REGNO (tmp)]
6446 || num_not_at_initial_offset
6447 || GET_CODE (oldequiv) == SUBREG)
6448 real_oldequiv = rl->in;
6450 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6454 if (GET_CODE (tmp) == SUBREG)
6455 tmp = SUBREG_REG (tmp);
6457 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6458 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6459 || reg_equiv_constant[REGNO (tmp)] != 0))
6461 if (! reg_equiv_mem[REGNO (tmp)]
6462 || num_not_at_initial_offset
6463 || GET_CODE (old) == SUBREG)
6466 real_old = reg_equiv_mem[REGNO (tmp)];
6469 second_reload_reg = rld[secondary_reload].reg_rtx;
6470 icode = rl->secondary_in_icode;
6472 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6473 || (rl->in != 0 && rl->out != 0))
6475 enum reg_class new_class
6476 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6477 mode, real_oldequiv);
6479 if (new_class == NO_REGS)
6480 second_reload_reg = 0;
6483 enum insn_code new_icode;
6484 enum machine_mode new_mode;
6486 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6487 REGNO (second_reload_reg)))
6488 oldequiv = old, real_oldequiv = real_old;
6491 new_icode = reload_in_optab[(int) mode];
6492 if (new_icode != CODE_FOR_nothing
6493 && ((insn_data[(int) new_icode].operand[0].predicate
6494 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6496 || (insn_data[(int) new_icode].operand[1].predicate
6497 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6498 (real_oldequiv, mode)))))
6499 new_icode = CODE_FOR_nothing;
6501 if (new_icode == CODE_FOR_nothing)
6504 new_mode = insn_data[(int) new_icode].operand[2].mode;
6506 if (GET_MODE (second_reload_reg) != new_mode)
6508 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6510 oldequiv = old, real_oldequiv = real_old;
6513 = reload_adjust_reg_for_mode (second_reload_reg,
6520 /* If we still need a secondary reload register, check
6521 to see if it is being used as a scratch or intermediate
6522 register and generate code appropriately. If we need
6523 a scratch register, use REAL_OLDEQUIV since the form of
6524 the insn may depend on the actual address if it is
6527 if (second_reload_reg)
6529 if (icode != CODE_FOR_nothing)
6531 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6532 second_reload_reg));
6537 /* See if we need a scratch register to load the
6538 intermediate register (a tertiary reload). */
6539 enum insn_code tertiary_icode
6540 = rld[secondary_reload].secondary_in_icode;
6542 if (tertiary_icode != CODE_FOR_nothing)
6544 rtx third_reload_reg
6545 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6547 emit_insn ((GEN_FCN (tertiary_icode)
6548 (second_reload_reg, real_oldequiv,
6549 third_reload_reg)));
6552 gen_reload (second_reload_reg, real_oldequiv,
6556 oldequiv = second_reload_reg;
6562 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6564 rtx real_oldequiv = oldequiv;
6566 if ((REG_P (oldequiv)
6567 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6568 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6569 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6570 || (GET_CODE (oldequiv) == SUBREG
6571 && REG_P (SUBREG_REG (oldequiv))
6572 && (REGNO (SUBREG_REG (oldequiv))
6573 >= FIRST_PSEUDO_REGISTER)
6574 && ((reg_equiv_memory_loc
6575 [REGNO (SUBREG_REG (oldequiv))] != 0)
6576 || (reg_equiv_constant
6577 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6578 || (CONSTANT_P (oldequiv)
6579 && (PREFERRED_RELOAD_CLASS (oldequiv,
6580 REGNO_REG_CLASS (REGNO (reloadreg)))
6582 real_oldequiv = rl->in;
6583 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6587 if (flag_non_call_exceptions)
6588 copy_eh_notes (insn, get_insns ());
6590 /* End this sequence. */
6591 *where = get_insns ();
6594 /* Update reload_override_in so that delete_address_reloads_1
6595 can see the actual register usage. */
6597 reload_override_in[j] = oldequiv;
6600 /* Generate insns to for the output reload RL, which is for the insn described
6601 by CHAIN and has the number J. */
6603 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6606 rtx reloadreg = rl->reg_rtx;
6607 rtx insn = chain->insn;
6610 enum machine_mode mode = GET_MODE (old);
6613 if (rl->when_needed == RELOAD_OTHER)
6616 push_to_sequence (output_reload_insns[rl->opnum]);
6618 /* Determine the mode to reload in.
6619 See comments above (for input reloading). */
6621 if (mode == VOIDmode)
6623 /* VOIDmode should never happen for an output. */
6624 if (asm_noperands (PATTERN (insn)) < 0)
6625 /* It's the compiler's fault. */
6626 fatal_insn ("VOIDmode on an output", insn);
6627 error_for_asm (insn, "output operand is constant in %<asm%>");
6628 /* Prevent crash--use something we know is valid. */
6630 old = gen_rtx_REG (mode, REGNO (reloadreg));
6633 if (GET_MODE (reloadreg) != mode)
6634 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6636 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6638 /* If we need two reload regs, set RELOADREG to the intermediate
6639 one, since it will be stored into OLD. We might need a secondary
6640 register only for an input reload, so check again here. */
6642 if (rl->secondary_out_reload >= 0)
6646 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
6647 && reg_equiv_mem[REGNO (old)] != 0)
6648 real_old = reg_equiv_mem[REGNO (old)];
6650 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6654 rtx second_reloadreg = reloadreg;
6655 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6657 /* See if RELOADREG is to be used as a scratch register
6658 or as an intermediate register. */
6659 if (rl->secondary_out_icode != CODE_FOR_nothing)
6661 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6662 (real_old, second_reloadreg, reloadreg)));
6667 /* See if we need both a scratch and intermediate reload
6670 int secondary_reload = rl->secondary_out_reload;
6671 enum insn_code tertiary_icode
6672 = rld[secondary_reload].secondary_out_icode;
6674 if (GET_MODE (reloadreg) != mode)
6675 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6677 if (tertiary_icode != CODE_FOR_nothing)
6680 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6683 /* Copy primary reload reg to secondary reload reg.
6684 (Note that these have been swapped above, then
6685 secondary reload reg to OLD using our insn.) */
6687 /* If REAL_OLD is a paradoxical SUBREG, remove it
6688 and try to put the opposite SUBREG on
6690 if (GET_CODE (real_old) == SUBREG
6691 && (GET_MODE_SIZE (GET_MODE (real_old))
6692 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6693 && 0 != (tem = gen_lowpart_common
6694 (GET_MODE (SUBREG_REG (real_old)),
6696 real_old = SUBREG_REG (real_old), reloadreg = tem;
6698 gen_reload (reloadreg, second_reloadreg,
6699 rl->opnum, rl->when_needed);
6700 emit_insn ((GEN_FCN (tertiary_icode)
6701 (real_old, reloadreg, third_reloadreg)));
6706 /* Copy between the reload regs here and then to
6709 gen_reload (reloadreg, second_reloadreg,
6710 rl->opnum, rl->when_needed);
6716 /* Output the last reload insn. */
6721 /* Don't output the last reload if OLD is not the dest of
6722 INSN and is in the src and is clobbered by INSN. */
6723 if (! flag_expensive_optimizations
6725 || !(set = single_set (insn))
6726 || rtx_equal_p (old, SET_DEST (set))
6727 || !reg_mentioned_p (old, SET_SRC (set))
6728 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
6729 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
6730 gen_reload (old, reloadreg, rl->opnum,
6734 /* Look at all insns we emitted, just to be safe. */
6735 for (p = get_insns (); p; p = NEXT_INSN (p))
6738 rtx pat = PATTERN (p);
6740 /* If this output reload doesn't come from a spill reg,
6741 clear any memory of reloaded copies of the pseudo reg.
6742 If this output reload comes from a spill reg,
6743 reg_has_output_reload will make this do nothing. */
6744 note_stores (pat, forget_old_reloads_1, NULL);
6746 if (reg_mentioned_p (rl->reg_rtx, pat))
6748 rtx set = single_set (insn);
6749 if (reload_spill_index[j] < 0
6751 && SET_SRC (set) == rl->reg_rtx)
6753 int src = REGNO (SET_SRC (set));
6755 reload_spill_index[j] = src;
6756 SET_HARD_REG_BIT (reg_is_output_reload, src);
6757 if (find_regno_note (insn, REG_DEAD, src))
6758 SET_HARD_REG_BIT (reg_reloaded_died, src);
6760 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6762 int s = rl->secondary_out_reload;
6763 set = single_set (p);
6764 /* If this reload copies only to the secondary reload
6765 register, the secondary reload does the actual
6767 if (s >= 0 && set == NULL_RTX)
6768 /* We can't tell what function the secondary reload
6769 has and where the actual store to the pseudo is
6770 made; leave new_spill_reg_store alone. */
6773 && SET_SRC (set) == rl->reg_rtx
6774 && SET_DEST (set) == rld[s].reg_rtx)
6776 /* Usually the next instruction will be the
6777 secondary reload insn; if we can confirm
6778 that it is, setting new_spill_reg_store to
6779 that insn will allow an extra optimization. */
6780 rtx s_reg = rld[s].reg_rtx;
6781 rtx next = NEXT_INSN (p);
6782 rld[s].out = rl->out;
6783 rld[s].out_reg = rl->out_reg;
6784 set = single_set (next);
6785 if (set && SET_SRC (set) == s_reg
6786 && ! new_spill_reg_store[REGNO (s_reg)])
6788 SET_HARD_REG_BIT (reg_is_output_reload,
6790 new_spill_reg_store[REGNO (s_reg)] = next;
6794 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6799 if (rl->when_needed == RELOAD_OTHER)
6801 emit_insn (other_output_reload_insns[rl->opnum]);
6802 other_output_reload_insns[rl->opnum] = get_insns ();
6805 output_reload_insns[rl->opnum] = get_insns ();
6807 if (flag_non_call_exceptions)
6808 copy_eh_notes (insn, get_insns ());
6813 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6814 and has the number J. */
6816 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
6818 rtx insn = chain->insn;
6819 rtx old = (rl->in && MEM_P (rl->in)
6820 ? rl->in_reg : rl->in);
6823 /* AUTO_INC reloads need to be handled even if inherited. We got an
6824 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6825 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6826 && ! rtx_equal_p (rl->reg_rtx, old)
6827 && rl->reg_rtx != 0)
6828 emit_input_reload_insns (chain, rld + j, old, j);
6830 /* When inheriting a wider reload, we have a MEM in rl->in,
6831 e.g. inheriting a SImode output reload for
6832 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6833 if (optimize && reload_inherited[j] && rl->in
6835 && MEM_P (rl->in_reg)
6836 && reload_spill_index[j] >= 0
6837 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6838 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6840 /* If we are reloading a register that was recently stored in with an
6841 output-reload, see if we can prove there was
6842 actually no need to store the old value in it. */
6845 /* Only attempt this for input reloads; for RELOAD_OTHER we miss
6846 that there may be multiple uses of the previous output reload.
6847 Restricting to RELOAD_FOR_INPUT is mostly paranoia. */
6848 && rl->when_needed == RELOAD_FOR_INPUT
6849 && (reload_inherited[j] || reload_override_in[j])
6851 && REG_P (rl->reg_rtx)
6852 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6854 /* There doesn't seem to be any reason to restrict this to pseudos
6855 and doing so loses in the case where we are copying from a
6856 register of the wrong class. */
6857 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6858 >= FIRST_PSEUDO_REGISTER)
6860 /* The insn might have already some references to stackslots
6861 replaced by MEMs, while reload_out_reg still names the
6863 && (dead_or_set_p (insn,
6864 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6865 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6867 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6870 /* Do output reloading for reload RL, which is for the insn described by
6871 CHAIN and has the number J.
6872 ??? At some point we need to support handling output reloads of
6873 JUMP_INSNs or insns that set cc0. */
6875 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
6878 rtx insn = chain->insn;
6879 /* If this is an output reload that stores something that is
6880 not loaded in this same reload, see if we can eliminate a previous
6882 rtx pseudo = rl->out_reg;
6887 && ! rtx_equal_p (rl->in_reg, pseudo)
6888 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6889 && reg_last_reload_reg[REGNO (pseudo)])
6891 int pseudo_no = REGNO (pseudo);
6892 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6894 /* We don't need to test full validity of last_regno for
6895 inherit here; we only want to know if the store actually
6896 matches the pseudo. */
6897 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6898 && reg_reloaded_contents[last_regno] == pseudo_no
6899 && spill_reg_store[last_regno]
6900 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6901 delete_output_reload (insn, j, last_regno);
6906 || rl->reg_rtx == old
6907 || rl->reg_rtx == 0)
6910 /* An output operand that dies right away does need a reload,
6911 but need not be copied from it. Show the new location in the
6913 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
6914 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6916 XEXP (note, 0) = rl->reg_rtx;
6919 /* Likewise for a SUBREG of an operand that dies. */
6920 else if (GET_CODE (old) == SUBREG
6921 && REG_P (SUBREG_REG (old))
6922 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6925 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6929 else if (GET_CODE (old) == SCRATCH)
6930 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6931 but we don't want to make an output reload. */
6934 /* If is a JUMP_INSN, we can't support output reloads yet. */
6935 gcc_assert (!JUMP_P (insn));
6937 emit_output_reload_insns (chain, rld + j, j);
6940 /* Reload number R reloads from or to a group of hard registers starting at
6941 register REGNO. Return true if it can be treated for inheritance purposes
6942 like a group of reloads, each one reloading a single hard register.
6943 The caller has already checked that the spill register and REGNO use
6944 the same number of registers to store the reload value. */
6947 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
6949 #ifdef CANNOT_CHANGE_MODE_CLASS
6950 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
6951 GET_MODE (rld[r].reg_rtx),
6952 reg_raw_mode[reload_spill_index[r]])
6953 && !REG_CANNOT_CHANGE_MODE_P (regno,
6954 GET_MODE (rld[r].reg_rtx),
6955 reg_raw_mode[regno]));
6961 /* Output insns to reload values in and out of the chosen reload regs. */
6964 emit_reload_insns (struct insn_chain *chain)
6966 rtx insn = chain->insn;
6970 CLEAR_HARD_REG_SET (reg_reloaded_died);
6972 for (j = 0; j < reload_n_operands; j++)
6973 input_reload_insns[j] = input_address_reload_insns[j]
6974 = inpaddr_address_reload_insns[j]
6975 = output_reload_insns[j] = output_address_reload_insns[j]
6976 = outaddr_address_reload_insns[j]
6977 = other_output_reload_insns[j] = 0;
6978 other_input_address_reload_insns = 0;
6979 other_input_reload_insns = 0;
6980 operand_reload_insns = 0;
6981 other_operand_reload_insns = 0;
6983 /* Dump reloads into the dump file. */
6986 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6987 debug_reload_to_stream (dump_file);
6990 /* Now output the instructions to copy the data into and out of the
6991 reload registers. Do these in the order that the reloads were reported,
6992 since reloads of base and index registers precede reloads of operands
6993 and the operands may need the base and index registers reloaded. */
6995 for (j = 0; j < n_reloads; j++)
6998 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6999 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7001 do_input_reload (chain, rld + j, j);
7002 do_output_reload (chain, rld + j, j);
7005 /* Now write all the insns we made for reloads in the order expected by
7006 the allocation functions. Prior to the insn being reloaded, we write
7007 the following reloads:
7009 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7011 RELOAD_OTHER reloads.
7013 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7014 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7015 RELOAD_FOR_INPUT reload for the operand.
7017 RELOAD_FOR_OPADDR_ADDRS reloads.
7019 RELOAD_FOR_OPERAND_ADDRESS reloads.
7021 After the insn being reloaded, we write the following:
7023 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7024 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7025 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7026 reloads for the operand. The RELOAD_OTHER output reloads are
7027 output in descending order by reload number. */
7029 emit_insn_before (other_input_address_reload_insns, insn);
7030 emit_insn_before (other_input_reload_insns, insn);
7032 for (j = 0; j < reload_n_operands; j++)
7034 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7035 emit_insn_before (input_address_reload_insns[j], insn);
7036 emit_insn_before (input_reload_insns[j], insn);
7039 emit_insn_before (other_operand_reload_insns, insn);
7040 emit_insn_before (operand_reload_insns, insn);
7042 for (j = 0; j < reload_n_operands; j++)
7044 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7045 x = emit_insn_after (output_address_reload_insns[j], x);
7046 x = emit_insn_after (output_reload_insns[j], x);
7047 emit_insn_after (other_output_reload_insns[j], x);
7050 /* For all the spill regs newly reloaded in this instruction,
7051 record what they were reloaded from, so subsequent instructions
7052 can inherit the reloads.
7054 Update spill_reg_store for the reloads of this insn.
7055 Copy the elements that were updated in the loop above. */
7057 for (j = 0; j < n_reloads; j++)
7059 int r = reload_order[j];
7060 int i = reload_spill_index[r];
7062 /* If this is a non-inherited input reload from a pseudo, we must
7063 clear any memory of a previous store to the same pseudo. Only do
7064 something if there will not be an output reload for the pseudo
7066 if (rld[r].in_reg != 0
7067 && ! (reload_inherited[r] || reload_override_in[r]))
7069 rtx reg = rld[r].in_reg;
7071 if (GET_CODE (reg) == SUBREG)
7072 reg = SUBREG_REG (reg);
7075 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7076 && ! reg_has_output_reload[REGNO (reg)])
7078 int nregno = REGNO (reg);
7080 if (reg_last_reload_reg[nregno])
7082 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7084 if (reg_reloaded_contents[last_regno] == nregno)
7085 spill_reg_store[last_regno] = 0;
7090 /* I is nonneg if this reload used a register.
7091 If rld[r].reg_rtx is 0, this is an optional reload
7092 that we opted to ignore. */
7094 if (i >= 0 && rld[r].reg_rtx != 0)
7096 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7098 int part_reaches_end = 0;
7099 int all_reaches_end = 1;
7101 /* For a multi register reload, we need to check if all or part
7102 of the value lives to the end. */
7103 for (k = 0; k < nr; k++)
7105 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7106 rld[r].when_needed))
7107 part_reaches_end = 1;
7109 all_reaches_end = 0;
7112 /* Ignore reloads that don't reach the end of the insn in
7114 if (all_reaches_end)
7116 /* First, clear out memory of what used to be in this spill reg.
7117 If consecutive registers are used, clear them all. */
7119 for (k = 0; k < nr; k++)
7121 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7122 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7125 /* Maybe the spill reg contains a copy of reload_out. */
7127 && (REG_P (rld[r].out)
7131 || REG_P (rld[r].out_reg)))
7133 rtx out = (REG_P (rld[r].out)
7137 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7138 int nregno = REGNO (out);
7139 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7140 : hard_regno_nregs[nregno]
7141 [GET_MODE (rld[r].reg_rtx)]);
7144 spill_reg_store[i] = new_spill_reg_store[i];
7145 spill_reg_stored_to[i] = out;
7146 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7148 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7150 && inherit_piecemeal_p (r, nregno));
7152 /* If NREGNO is a hard register, it may occupy more than
7153 one register. If it does, say what is in the
7154 rest of the registers assuming that both registers
7155 agree on how many words the object takes. If not,
7156 invalidate the subsequent registers. */
7158 if (nregno < FIRST_PSEUDO_REGISTER)
7159 for (k = 1; k < nnr; k++)
7160 reg_last_reload_reg[nregno + k]
7162 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7165 /* Now do the inverse operation. */
7166 for (k = 0; k < nr; k++)
7168 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7169 reg_reloaded_contents[i + k]
7170 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7173 reg_reloaded_insn[i + k] = insn;
7174 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7175 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7176 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7180 /* Maybe the spill reg contains a copy of reload_in. Only do
7181 something if there will not be an output reload for
7182 the register being reloaded. */
7183 else if (rld[r].out_reg == 0
7185 && ((REG_P (rld[r].in)
7186 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7187 && ! reg_has_output_reload[REGNO (rld[r].in)])
7188 || (REG_P (rld[r].in_reg)
7189 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7190 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7197 if (REG_P (rld[r].in)
7198 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7200 else if (REG_P (rld[r].in_reg))
7203 in = XEXP (rld[r].in_reg, 0);
7204 nregno = REGNO (in);
7206 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7207 : hard_regno_nregs[nregno]
7208 [GET_MODE (rld[r].reg_rtx)]);
7210 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7212 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7214 && inherit_piecemeal_p (r, nregno));
7216 if (nregno < FIRST_PSEUDO_REGISTER)
7217 for (k = 1; k < nnr; k++)
7218 reg_last_reload_reg[nregno + k]
7220 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7223 /* Unless we inherited this reload, show we haven't
7224 recently done a store.
7225 Previous stores of inherited auto_inc expressions
7226 also have to be discarded. */
7227 if (! reload_inherited[r]
7228 || (rld[r].out && ! rld[r].out_reg))
7229 spill_reg_store[i] = 0;
7231 for (k = 0; k < nr; k++)
7233 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7234 reg_reloaded_contents[i + k]
7235 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7238 reg_reloaded_insn[i + k] = insn;
7239 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7240 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7241 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7246 /* However, if part of the reload reaches the end, then we must
7247 invalidate the old info for the part that survives to the end. */
7248 else if (part_reaches_end)
7250 for (k = 0; k < nr; k++)
7251 if (reload_reg_reaches_end_p (i + k,
7253 rld[r].when_needed))
7254 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7258 /* The following if-statement was #if 0'd in 1.34 (or before...).
7259 It's reenabled in 1.35 because supposedly nothing else
7260 deals with this problem. */
7262 /* If a register gets output-reloaded from a non-spill register,
7263 that invalidates any previous reloaded copy of it.
7264 But forget_old_reloads_1 won't get to see it, because
7265 it thinks only about the original insn. So invalidate it here. */
7266 if (i < 0 && rld[r].out != 0
7267 && (REG_P (rld[r].out)
7268 || (MEM_P (rld[r].out)
7269 && REG_P (rld[r].out_reg))))
7271 rtx out = (REG_P (rld[r].out)
7272 ? rld[r].out : rld[r].out_reg);
7273 int nregno = REGNO (out);
7274 if (nregno >= FIRST_PSEUDO_REGISTER)
7276 rtx src_reg, store_insn = NULL_RTX;
7278 reg_last_reload_reg[nregno] = 0;
7280 /* If we can find a hard register that is stored, record
7281 the storing insn so that we may delete this insn with
7282 delete_output_reload. */
7283 src_reg = rld[r].reg_rtx;
7285 /* If this is an optional reload, try to find the source reg
7286 from an input reload. */
7289 rtx set = single_set (insn);
7290 if (set && SET_DEST (set) == rld[r].out)
7294 src_reg = SET_SRC (set);
7296 for (k = 0; k < n_reloads; k++)
7298 if (rld[k].in == src_reg)
7300 src_reg = rld[k].reg_rtx;
7307 store_insn = new_spill_reg_store[REGNO (src_reg)];
7308 if (src_reg && REG_P (src_reg)
7309 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7311 int src_regno = REGNO (src_reg);
7312 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7313 /* The place where to find a death note varies with
7314 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7315 necessarily checked exactly in the code that moves
7316 notes, so just check both locations. */
7317 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7318 if (! note && store_insn)
7319 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7322 spill_reg_store[src_regno + nr] = store_insn;
7323 spill_reg_stored_to[src_regno + nr] = out;
7324 reg_reloaded_contents[src_regno + nr] = nregno;
7325 reg_reloaded_insn[src_regno + nr] = store_insn;
7326 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7327 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7328 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7329 GET_MODE (src_reg)))
7330 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7332 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7334 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7336 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7338 reg_last_reload_reg[nregno] = src_reg;
7339 /* We have to set reg_has_output_reload here, or else
7340 forget_old_reloads_1 will clear reg_last_reload_reg
7342 reg_has_output_reload[nregno] = 1;
7347 int num_regs = hard_regno_nregs[nregno][GET_MODE (rld[r].out)];
7349 while (num_regs-- > 0)
7350 reg_last_reload_reg[nregno + num_regs] = 0;
7354 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7357 /* Emit code to perform a reload from IN (which may be a reload register) to
7358 OUT (which may also be a reload register). IN or OUT is from operand
7359 OPNUM with reload type TYPE.
7361 Returns first insn emitted. */
7364 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7366 rtx last = get_last_insn ();
7369 /* If IN is a paradoxical SUBREG, remove it and try to put the
7370 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7371 if (GET_CODE (in) == SUBREG
7372 && (GET_MODE_SIZE (GET_MODE (in))
7373 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7374 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7375 in = SUBREG_REG (in), out = tem;
7376 else if (GET_CODE (out) == SUBREG
7377 && (GET_MODE_SIZE (GET_MODE (out))
7378 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7379 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7380 out = SUBREG_REG (out), in = tem;
7382 /* How to do this reload can get quite tricky. Normally, we are being
7383 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7384 register that didn't get a hard register. In that case we can just
7385 call emit_move_insn.
7387 We can also be asked to reload a PLUS that adds a register or a MEM to
7388 another register, constant or MEM. This can occur during frame pointer
7389 elimination and while reloading addresses. This case is handled by
7390 trying to emit a single insn to perform the add. If it is not valid,
7391 we use a two insn sequence.
7393 Finally, we could be called to handle an 'o' constraint by putting
7394 an address into a register. In that case, we first try to do this
7395 with a named pattern of "reload_load_address". If no such pattern
7396 exists, we just emit a SET insn and hope for the best (it will normally
7397 be valid on machines that use 'o').
7399 This entire process is made complex because reload will never
7400 process the insns we generate here and so we must ensure that
7401 they will fit their constraints and also by the fact that parts of
7402 IN might be being reloaded separately and replaced with spill registers.
7403 Because of this, we are, in some sense, just guessing the right approach
7404 here. The one listed above seems to work.
7406 ??? At some point, this whole thing needs to be rethought. */
7408 if (GET_CODE (in) == PLUS
7409 && (REG_P (XEXP (in, 0))
7410 || GET_CODE (XEXP (in, 0)) == SUBREG
7411 || MEM_P (XEXP (in, 0)))
7412 && (REG_P (XEXP (in, 1))
7413 || GET_CODE (XEXP (in, 1)) == SUBREG
7414 || CONSTANT_P (XEXP (in, 1))
7415 || MEM_P (XEXP (in, 1))))
7417 /* We need to compute the sum of a register or a MEM and another
7418 register, constant, or MEM, and put it into the reload
7419 register. The best possible way of doing this is if the machine
7420 has a three-operand ADD insn that accepts the required operands.
7422 The simplest approach is to try to generate such an insn and see if it
7423 is recognized and matches its constraints. If so, it can be used.
7425 It might be better not to actually emit the insn unless it is valid,
7426 but we need to pass the insn as an operand to `recog' and
7427 `extract_insn' and it is simpler to emit and then delete the insn if
7428 not valid than to dummy things up. */
7430 rtx op0, op1, tem, insn;
7433 op0 = find_replacement (&XEXP (in, 0));
7434 op1 = find_replacement (&XEXP (in, 1));
7436 /* Since constraint checking is strict, commutativity won't be
7437 checked, so we need to do that here to avoid spurious failure
7438 if the add instruction is two-address and the second operand
7439 of the add is the same as the reload reg, which is frequently
7440 the case. If the insn would be A = B + A, rearrange it so
7441 it will be A = A + B as constrain_operands expects. */
7443 if (REG_P (XEXP (in, 1))
7444 && REGNO (out) == REGNO (XEXP (in, 1)))
7445 tem = op0, op0 = op1, op1 = tem;
7447 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7448 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7450 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7451 code = recog_memoized (insn);
7455 extract_insn (insn);
7456 /* We want constrain operands to treat this insn strictly in
7457 its validity determination, i.e., the way it would after reload
7459 if (constrain_operands (1))
7463 delete_insns_since (last);
7465 /* If that failed, we must use a conservative two-insn sequence.
7467 Use a move to copy one operand into the reload register. Prefer
7468 to reload a constant, MEM or pseudo since the move patterns can
7469 handle an arbitrary operand. If OP1 is not a constant, MEM or
7470 pseudo and OP1 is not a valid operand for an add instruction, then
7473 After reloading one of the operands into the reload register, add
7474 the reload register to the output register.
7476 If there is another way to do this for a specific machine, a
7477 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7480 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7482 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7484 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7485 || (code != CODE_FOR_nothing
7486 && ! ((*insn_data[code].operand[2].predicate)
7487 (op1, insn_data[code].operand[2].mode))))
7488 tem = op0, op0 = op1, op1 = tem;
7490 gen_reload (out, op0, opnum, type);
7492 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7493 This fixes a problem on the 32K where the stack pointer cannot
7494 be used as an operand of an add insn. */
7496 if (rtx_equal_p (op0, op1))
7499 insn = emit_insn (gen_add2_insn (out, op1));
7501 /* If that failed, copy the address register to the reload register.
7502 Then add the constant to the reload register. */
7504 code = recog_memoized (insn);
7508 extract_insn (insn);
7509 /* We want constrain operands to treat this insn strictly in
7510 its validity determination, i.e., the way it would after reload
7512 if (constrain_operands (1))
7514 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7516 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7521 delete_insns_since (last);
7523 gen_reload (out, op1, opnum, type);
7524 insn = emit_insn (gen_add2_insn (out, op0));
7525 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7528 #ifdef SECONDARY_MEMORY_NEEDED
7529 /* If we need a memory location to do the move, do it that way. */
7530 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7531 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7532 && (REG_P (out) || GET_CODE (out) == SUBREG)
7533 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7534 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7535 REGNO_REG_CLASS (reg_or_subregno (out)),
7538 /* Get the memory to use and rewrite both registers to its mode. */
7539 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7541 if (GET_MODE (loc) != GET_MODE (out))
7542 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7544 if (GET_MODE (loc) != GET_MODE (in))
7545 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7547 gen_reload (loc, in, opnum, type);
7548 gen_reload (out, loc, opnum, type);
7552 /* If IN is a simple operand, use gen_move_insn. */
7553 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
7554 emit_insn (gen_move_insn (out, in));
7556 #ifdef HAVE_reload_load_address
7557 else if (HAVE_reload_load_address)
7558 emit_insn (gen_reload_load_address (out, in));
7561 /* Otherwise, just write (set OUT IN) and hope for the best. */
7563 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7565 /* Return the first insn emitted.
7566 We can not just return get_last_insn, because there may have
7567 been multiple instructions emitted. Also note that gen_move_insn may
7568 emit more than one insn itself, so we can not assume that there is one
7569 insn emitted per emit_insn_before call. */
7571 return last ? NEXT_INSN (last) : get_insns ();
7574 /* Delete a previously made output-reload whose result we now believe
7575 is not needed. First we double-check.
7577 INSN is the insn now being processed.
7578 LAST_RELOAD_REG is the hard register number for which we want to delete
7579 the last output reload.
7580 J is the reload-number that originally used REG. The caller has made
7581 certain that reload J doesn't use REG any longer for input. */
7584 delete_output_reload (rtx insn, int j, int last_reload_reg)
7586 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7587 rtx reg = spill_reg_stored_to[last_reload_reg];
7590 int n_inherited = 0;
7594 /* It is possible that this reload has been only used to set another reload
7595 we eliminated earlier and thus deleted this instruction too. */
7596 if (INSN_DELETED_P (output_reload_insn))
7599 /* Get the raw pseudo-register referred to. */
7601 while (GET_CODE (reg) == SUBREG)
7602 reg = SUBREG_REG (reg);
7603 substed = reg_equiv_memory_loc[REGNO (reg)];
7605 /* This is unsafe if the operand occurs more often in the current
7606 insn than it is inherited. */
7607 for (k = n_reloads - 1; k >= 0; k--)
7609 rtx reg2 = rld[k].in;
7612 if (MEM_P (reg2) || reload_override_in[k])
7613 reg2 = rld[k].in_reg;
7615 if (rld[k].out && ! rld[k].out_reg)
7616 reg2 = XEXP (rld[k].in_reg, 0);
7618 while (GET_CODE (reg2) == SUBREG)
7619 reg2 = SUBREG_REG (reg2);
7620 if (rtx_equal_p (reg2, reg))
7622 if (reload_inherited[k] || reload_override_in[k] || k == j)
7625 reg2 = rld[k].out_reg;
7628 while (GET_CODE (reg2) == SUBREG)
7629 reg2 = XEXP (reg2, 0);
7630 if (rtx_equal_p (reg2, reg))
7637 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7639 n_occurrences += count_occurrences (PATTERN (insn),
7640 eliminate_regs (substed, 0,
7642 if (n_occurrences > n_inherited)
7645 /* If the pseudo-reg we are reloading is no longer referenced
7646 anywhere between the store into it and here,
7647 and we're within the same basic block, then the value can only
7648 pass through the reload reg and end up here.
7649 Otherwise, give up--return. */
7650 for (i1 = NEXT_INSN (output_reload_insn);
7651 i1 != insn; i1 = NEXT_INSN (i1))
7653 if (NOTE_INSN_BASIC_BLOCK_P (i1))
7655 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
7656 && reg_mentioned_p (reg, PATTERN (i1)))
7658 /* If this is USE in front of INSN, we only have to check that
7659 there are no more references than accounted for by inheritance. */
7660 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
7662 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7663 i1 = NEXT_INSN (i1);
7665 if (n_occurrences <= n_inherited && i1 == insn)
7671 /* We will be deleting the insn. Remove the spill reg information. */
7672 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
7674 spill_reg_store[last_reload_reg + k] = 0;
7675 spill_reg_stored_to[last_reload_reg + k] = 0;
7678 /* The caller has already checked that REG dies or is set in INSN.
7679 It has also checked that we are optimizing, and thus some
7680 inaccuracies in the debugging information are acceptable.
7681 So we could just delete output_reload_insn. But in some cases
7682 we can improve the debugging information without sacrificing
7683 optimization - maybe even improving the code: See if the pseudo
7684 reg has been completely replaced with reload regs. If so, delete
7685 the store insn and forget we had a stack slot for the pseudo. */
7686 if (rld[j].out != rld[j].in
7687 && REG_N_DEATHS (REGNO (reg)) == 1
7688 && REG_N_SETS (REGNO (reg)) == 1
7689 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7690 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7694 /* We know that it was used only between here and the beginning of
7695 the current basic block. (We also know that the last use before
7696 INSN was the output reload we are thinking of deleting, but never
7697 mind that.) Search that range; see if any ref remains. */
7698 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7700 rtx set = single_set (i2);
7702 /* Uses which just store in the pseudo don't count,
7703 since if they are the only uses, they are dead. */
7704 if (set != 0 && SET_DEST (set) == reg)
7709 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
7710 && reg_mentioned_p (reg, PATTERN (i2)))
7712 /* Some other ref remains; just delete the output reload we
7714 delete_address_reloads (output_reload_insn, insn);
7715 delete_insn (output_reload_insn);
7720 /* Delete the now-dead stores into this pseudo. Note that this
7721 loop also takes care of deleting output_reload_insn. */
7722 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7724 rtx set = single_set (i2);
7726 if (set != 0 && SET_DEST (set) == reg)
7728 delete_address_reloads (i2, insn);
7736 /* For the debugging info, say the pseudo lives in this reload reg. */
7737 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7738 alter_reg (REGNO (reg), -1);
7742 delete_address_reloads (output_reload_insn, insn);
7743 delete_insn (output_reload_insn);
7747 /* We are going to delete DEAD_INSN. Recursively delete loads of
7748 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7749 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7751 delete_address_reloads (rtx dead_insn, rtx current_insn)
7753 rtx set = single_set (dead_insn);
7754 rtx set2, dst, prev, next;
7757 rtx dst = SET_DEST (set);
7759 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7761 /* If we deleted the store from a reloaded post_{in,de}c expression,
7762 we can delete the matching adds. */
7763 prev = PREV_INSN (dead_insn);
7764 next = NEXT_INSN (dead_insn);
7765 if (! prev || ! next)
7767 set = single_set (next);
7768 set2 = single_set (prev);
7770 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7771 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7772 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7774 dst = SET_DEST (set);
7775 if (! rtx_equal_p (dst, SET_DEST (set2))
7776 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7777 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7778 || (INTVAL (XEXP (SET_SRC (set), 1))
7779 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7781 delete_related_insns (prev);
7782 delete_related_insns (next);
7785 /* Subfunction of delete_address_reloads: process registers found in X. */
7787 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
7789 rtx prev, set, dst, i2;
7791 enum rtx_code code = GET_CODE (x);
7795 const char *fmt = GET_RTX_FORMAT (code);
7796 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7799 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7800 else if (fmt[i] == 'E')
7802 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7803 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7810 if (spill_reg_order[REGNO (x)] < 0)
7813 /* Scan backwards for the insn that sets x. This might be a way back due
7815 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7817 code = GET_CODE (prev);
7818 if (code == CODE_LABEL || code == JUMP_INSN)
7822 if (reg_set_p (x, PATTERN (prev)))
7824 if (reg_referenced_p (x, PATTERN (prev)))
7827 if (! prev || INSN_UID (prev) < reload_first_uid)
7829 /* Check that PREV only sets the reload register. */
7830 set = single_set (prev);
7833 dst = SET_DEST (set);
7835 || ! rtx_equal_p (dst, x))
7837 if (! reg_set_p (dst, PATTERN (dead_insn)))
7839 /* Check if DST was used in a later insn -
7840 it might have been inherited. */
7841 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7847 if (reg_referenced_p (dst, PATTERN (i2)))
7849 /* If there is a reference to the register in the current insn,
7850 it might be loaded in a non-inherited reload. If no other
7851 reload uses it, that means the register is set before
7853 if (i2 == current_insn)
7855 for (j = n_reloads - 1; j >= 0; j--)
7856 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7857 || reload_override_in[j] == dst)
7859 for (j = n_reloads - 1; j >= 0; j--)
7860 if (rld[j].in && rld[j].reg_rtx == dst)
7869 /* If DST is still live at CURRENT_INSN, check if it is used for
7870 any reload. Note that even if CURRENT_INSN sets DST, we still
7871 have to check the reloads. */
7872 if (i2 == current_insn)
7874 for (j = n_reloads - 1; j >= 0; j--)
7875 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7876 || reload_override_in[j] == dst)
7878 /* ??? We can't finish the loop here, because dst might be
7879 allocated to a pseudo in this block if no reload in this
7880 block needs any of the classes containing DST - see
7881 spill_hard_reg. There is no easy way to tell this, so we
7882 have to scan till the end of the basic block. */
7884 if (reg_set_p (dst, PATTERN (i2)))
7888 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7889 reg_reloaded_contents[REGNO (dst)] = -1;
7893 /* Output reload-insns to reload VALUE into RELOADREG.
7894 VALUE is an autoincrement or autodecrement RTX whose operand
7895 is a register or memory location;
7896 so reloading involves incrementing that location.
7897 IN is either identical to VALUE, or some cheaper place to reload from.
7899 INC_AMOUNT is the number to increment or decrement by (always positive).
7900 This cannot be deduced from VALUE.
7902 Return the instruction that stores into RELOADREG. */
7905 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
7907 /* REG or MEM to be copied and incremented. */
7908 rtx incloc = XEXP (value, 0);
7909 /* Nonzero if increment after copying. */
7910 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7916 rtx real_in = in == value ? XEXP (in, 0) : in;
7918 /* No hard register is equivalent to this register after
7919 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7920 we could inc/dec that register as well (maybe even using it for
7921 the source), but I'm not sure it's worth worrying about. */
7923 reg_last_reload_reg[REGNO (incloc)] = 0;
7925 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7926 inc_amount = -inc_amount;
7928 inc = GEN_INT (inc_amount);
7930 /* If this is post-increment, first copy the location to the reload reg. */
7931 if (post && real_in != reloadreg)
7932 emit_insn (gen_move_insn (reloadreg, real_in));
7936 /* See if we can directly increment INCLOC. Use a method similar to
7937 that in gen_reload. */
7939 last = get_last_insn ();
7940 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7941 gen_rtx_PLUS (GET_MODE (incloc),
7944 code = recog_memoized (add_insn);
7947 extract_insn (add_insn);
7948 if (constrain_operands (1))
7950 /* If this is a pre-increment and we have incremented the value
7951 where it lives, copy the incremented value to RELOADREG to
7952 be used as an address. */
7955 emit_insn (gen_move_insn (reloadreg, incloc));
7960 delete_insns_since (last);
7963 /* If couldn't do the increment directly, must increment in RELOADREG.
7964 The way we do this depends on whether this is pre- or post-increment.
7965 For pre-increment, copy INCLOC to the reload register, increment it
7966 there, then save back. */
7970 if (in != reloadreg)
7971 emit_insn (gen_move_insn (reloadreg, real_in));
7972 emit_insn (gen_add2_insn (reloadreg, inc));
7973 store = emit_insn (gen_move_insn (incloc, reloadreg));
7978 Because this might be a jump insn or a compare, and because RELOADREG
7979 may not be available after the insn in an input reload, we must do
7980 the incrementation before the insn being reloaded for.
7982 We have already copied IN to RELOADREG. Increment the copy in
7983 RELOADREG, save that back, then decrement RELOADREG so it has
7984 the original value. */
7986 emit_insn (gen_add2_insn (reloadreg, inc));
7987 store = emit_insn (gen_move_insn (incloc, reloadreg));
7988 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7996 add_auto_inc_notes (rtx insn, rtx x)
7998 enum rtx_code code = GET_CODE (x);
8002 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8005 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8009 /* Scan all the operand sub-expressions. */
8010 fmt = GET_RTX_FORMAT (code);
8011 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8014 add_auto_inc_notes (insn, XEXP (x, i));
8015 else if (fmt[i] == 'E')
8016 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8017 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8022 /* Copy EH notes from an insn to its reloads. */
8024 copy_eh_notes (rtx insn, rtx x)
8026 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8029 for (; x != 0; x = NEXT_INSN (x))
8031 if (may_trap_p (PATTERN (x)))
8033 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8039 /* This is used by reload pass, that does emit some instructions after
8040 abnormal calls moving basic block end, but in fact it wants to emit
8041 them on the edge. Looks for abnormal call edges, find backward the
8042 proper call and fix the damage.
8044 Similar handle instructions throwing exceptions internally. */
8046 fixup_abnormal_edges (void)
8048 bool inserted = false;
8056 /* Look for cases we are interested in - calls or instructions causing
8058 FOR_EACH_EDGE (e, ei, bb->succs)
8060 if (e->flags & EDGE_ABNORMAL_CALL)
8062 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8063 == (EDGE_ABNORMAL | EDGE_EH))
8066 if (e && !CALL_P (BB_END (bb))
8067 && !can_throw_internal (BB_END (bb)))
8069 rtx insn = BB_END (bb), stop = NEXT_INSN (BB_END (bb));
8071 FOR_EACH_EDGE (e, ei, bb->succs)
8072 if (e->flags & EDGE_FALLTHRU)
8074 /* Get past the new insns generated. Allow notes, as the insns may
8075 be already deleted. */
8076 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8077 && !can_throw_internal (insn)
8078 && insn != BB_HEAD (bb))
8079 insn = PREV_INSN (insn);
8080 gcc_assert (CALL_P (insn) || can_throw_internal (insn));
8083 insn = NEXT_INSN (insn);
8084 while (insn && insn != stop)
8086 next = NEXT_INSN (insn);
8091 /* Sometimes there's still the return value USE.
8092 If it's placed after a trapping call (i.e. that
8093 call is the last insn anyway), we have no fallthru
8094 edge. Simply delete this use and don't try to insert
8095 on the non-existent edge. */
8096 if (GET_CODE (PATTERN (insn)) != USE)
8098 /* We're not deleting it, we're moving it. */
8099 INSN_DELETED_P (insn) = 0;
8100 PREV_INSN (insn) = NULL_RTX;
8101 NEXT_INSN (insn) = NULL_RTX;
8103 insert_insn_on_edge (insn, e);
8110 /* We've possibly turned single trapping insn into multiple ones. */
8111 if (flag_non_call_exceptions)
8114 blocks = sbitmap_alloc (last_basic_block);
8115 sbitmap_ones (blocks);
8116 find_many_sub_basic_blocks (blocks);
8119 commit_edge_insertions ();
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