1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 88, 89, 92-6, 1997 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "insn-config.h"
27 #include "insn-flags.h"
28 #include "insn-codes.h"
32 #include "hard-reg-set.h"
35 #include "basic-block.h"
39 /* This file contains the reload pass of the compiler, which is
40 run after register allocation has been done. It checks that
41 each insn is valid (operands required to be in registers really
42 are in registers of the proper class) and fixes up invalid ones
43 by copying values temporarily into registers for the insns
46 The results of register allocation are described by the vector
47 reg_renumber; the insns still contain pseudo regs, but reg_renumber
48 can be used to find which hard reg, if any, a pseudo reg is in.
50 The technique we always use is to free up a few hard regs that are
51 called ``reload regs'', and for each place where a pseudo reg
52 must be in a hard reg, copy it temporarily into one of the reload regs.
54 All the pseudos that were formerly allocated to the hard regs that
55 are now in use as reload regs must be ``spilled''. This means
56 that they go to other hard regs, or to stack slots if no other
57 available hard regs can be found. Spilling can invalidate more
58 insns, requiring additional need for reloads, so we must keep checking
59 until the process stabilizes.
61 For machines with different classes of registers, we must keep track
62 of the register class needed for each reload, and make sure that
63 we allocate enough reload registers of each class.
65 The file reload.c contains the code that checks one insn for
66 validity and reports the reloads that it needs. This file
67 is in charge of scanning the entire rtl code, accumulating the
68 reload needs, spilling, assigning reload registers to use for
69 fixing up each insn, and generating the new insns to copy values
70 into the reload registers. */
73 #ifndef REGISTER_MOVE_COST
74 #define REGISTER_MOVE_COST(x, y) 2
77 #ifndef MEMORY_MOVE_COST
78 #define MEMORY_MOVE_COST(x) 4
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx *reg_equiv_memory_loc;
105 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
106 This is used when the address is not valid as a memory address
107 (because its displacement is too big for the machine.) */
108 rtx *reg_equiv_address;
110 /* Element N is the memory slot to which pseudo reg N is equivalent,
111 or zero if pseudo reg N is not equivalent to a memory slot. */
114 /* Widest width in which each pseudo reg is referred to (via subreg). */
115 static int *reg_max_ref_width;
117 /* Element N is the insn that initialized reg N from its equivalent
118 constant or memory slot. */
119 static rtx *reg_equiv_init;
121 /* During reload_as_needed, element N contains the last pseudo regno
122 reloaded into the Nth reload register. This vector is in parallel
123 with spill_regs. If that pseudo reg occupied more than one register,
124 reg_reloaded_contents points to that pseudo for each spill register in
125 use; all of these must remain set for an inheritance to occur. */
126 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
128 /* During reload_as_needed, element N contains the insn for which
129 the Nth reload register was last used. This vector is in parallel
130 with spill_regs, and its contents are significant only when
131 reg_reloaded_contents is significant. */
132 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
134 /* Number of spill-regs so far; number of valid elements of spill_regs. */
137 /* In parallel with spill_regs, contains REG rtx's for those regs.
138 Holds the last rtx used for any given reg, or 0 if it has never
139 been used for spilling yet. This rtx is reused, provided it has
141 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
143 /* In parallel with spill_regs, contains nonzero for a spill reg
144 that was stored after the last time it was used.
145 The precise value is the insn generated to do the store. */
146 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
148 /* This table is the inverse mapping of spill_regs:
149 indexed by hard reg number,
150 it contains the position of that reg in spill_regs,
151 or -1 for something that is not in spill_regs. */
152 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
154 /* This reg set indicates registers that may not be used for retrying global
155 allocation. The registers that may not be used include all spill registers
156 and the frame pointer (if we are using one). */
157 HARD_REG_SET forbidden_regs;
159 /* This reg set indicates registers that are not good for spill registers.
160 They will not be used to complete groups of spill registers. This includes
161 all fixed registers, registers that may be eliminated, and, if
162 SMALL_REGISTER_CLASSES is not defined, registers explicitly used in the rtl.
164 (spill_reg_order prevents these registers from being used to start a
166 static HARD_REG_SET bad_spill_regs;
168 /* Describes order of use of registers for reloading
169 of spilled pseudo-registers. `spills' is the number of
170 elements that are actually valid; new ones are added at the end. */
171 static short spill_regs[FIRST_PSEUDO_REGISTER];
173 /* This reg set indicates those registers that have been used a spill
174 registers. This information is used in reorg.c, to help figure out
175 what registers are live at any point. It is assumed that all spill_regs
176 are dead at every CODE_LABEL. */
178 HARD_REG_SET used_spill_regs;
180 /* Index of last register assigned as a spill register. We allocate in
181 a round-robin fashion. */
183 static int last_spill_reg;
185 /* Describes order of preference for putting regs into spill_regs.
186 Contains the numbers of all the hard regs, in order most preferred first.
187 This order is different for each function.
188 It is set up by order_regs_for_reload.
189 Empty elements at the end contain -1. */
190 static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
192 /* 1 for a hard register that appears explicitly in the rtl
193 (for example, function value registers, special registers
194 used by insns, structure value pointer registers). */
195 static char regs_explicitly_used[FIRST_PSEUDO_REGISTER];
197 /* Indicates if a register was counted against the need for
198 groups. 0 means it can count against max_nongroup instead. */
199 static HARD_REG_SET counted_for_groups;
201 /* Indicates if a register was counted against the need for
202 non-groups. 0 means it can become part of a new group.
203 During choose_reload_regs, 1 here means don't use this reg
204 as part of a group, even if it seems to be otherwise ok. */
205 static HARD_REG_SET counted_for_nongroups;
207 /* Indexed by pseudo reg number N,
208 says may not delete stores into the real (memory) home of pseudo N.
209 This is set if we already substituted a memory equivalent in some uses,
210 which happens when we have to eliminate the fp from it. */
211 static char *cannot_omit_stores;
213 /* Nonzero if indirect addressing is supported on the machine; this means
214 that spilling (REG n) does not require reloading it into a register in
215 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
216 value indicates the level of indirect addressing supported, e.g., two
217 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
220 static char spill_indirect_levels;
222 /* Nonzero if indirect addressing is supported when the innermost MEM is
223 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
224 which these are valid is the same as spill_indirect_levels, above. */
226 char indirect_symref_ok;
228 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
230 char double_reg_address_ok;
232 /* Record the stack slot for each spilled hard register. */
234 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
236 /* Width allocated so far for that stack slot. */
238 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
240 /* Indexed by register class and basic block number, nonzero if there is
241 any need for a spill register of that class in that basic block.
242 The pointer is 0 if we did stupid allocation and don't know
243 the structure of basic blocks. */
245 char *basic_block_needs[N_REG_CLASSES];
247 /* First uid used by insns created by reload in this function.
248 Used in find_equiv_reg. */
249 int reload_first_uid;
251 /* Flag set by local-alloc or global-alloc if anything is live in
252 a call-clobbered reg across calls. */
254 int caller_save_needed;
256 /* The register class to use for a base register when reloading an
257 address. This is normally BASE_REG_CLASS, but it may be different
258 when using SMALL_REGISTER_CLASSES and passing parameters in
260 enum reg_class reload_address_base_reg_class;
262 /* The register class to use for an index register when reloading an
263 address. This is normally INDEX_REG_CLASS, but it may be different
264 when using SMALL_REGISTER_CLASSES and passing parameters in
266 enum reg_class reload_address_index_reg_class;
268 /* Set to 1 while reload_as_needed is operating.
269 Required by some machines to handle any generated moves differently. */
271 int reload_in_progress = 0;
273 /* These arrays record the insn_code of insns that may be needed to
274 perform input and output reloads of special objects. They provide a
275 place to pass a scratch register. */
277 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
278 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
280 /* This obstack is used for allocation of rtl during register elimination.
281 The allocated storage can be freed once find_reloads has processed the
284 struct obstack reload_obstack;
285 char *reload_firstobj;
287 #define obstack_chunk_alloc xmalloc
288 #define obstack_chunk_free free
290 /* List of labels that must never be deleted. */
291 extern rtx forced_labels;
293 /* Allocation number table from global register allocation. */
294 extern int *reg_allocno;
296 /* This structure is used to record information about register eliminations.
297 Each array entry describes one possible way of eliminating a register
298 in favor of another. If there is more than one way of eliminating a
299 particular register, the most preferred should be specified first. */
301 static struct elim_table
303 int from; /* Register number to be eliminated. */
304 int to; /* Register number used as replacement. */
305 int initial_offset; /* Initial difference between values. */
306 int can_eliminate; /* Non-zero if this elimination can be done. */
307 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
308 insns made by reload. */
309 int offset; /* Current offset between the two regs. */
310 int max_offset; /* Maximum offset between the two regs. */
311 int previous_offset; /* Offset at end of previous insn. */
312 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
313 rtx from_rtx; /* REG rtx for the register to be eliminated.
314 We cannot simply compare the number since
315 we might then spuriously replace a hard
316 register corresponding to a pseudo
317 assigned to the reg to be eliminated. */
318 rtx to_rtx; /* REG rtx for the replacement. */
321 /* If a set of eliminable registers was specified, define the table from it.
322 Otherwise, default to the normal case of the frame pointer being
323 replaced by the stack pointer. */
325 #ifdef ELIMINABLE_REGS
328 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
331 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate / sizeof reg_eliminate[0])
333 /* Record the number of pending eliminations that have an offset not equal
334 to their initial offset. If non-zero, we use a new copy of each
335 replacement result in any insns encountered. */
336 static int num_not_at_initial_offset;
338 /* Count the number of registers that we may be able to eliminate. */
339 static int num_eliminable;
341 /* For each label, we record the offset of each elimination. If we reach
342 a label by more than one path and an offset differs, we cannot do the
343 elimination. This information is indexed by the number of the label.
344 The first table is an array of flags that records whether we have yet
345 encountered a label and the second table is an array of arrays, one
346 entry in the latter array for each elimination. */
348 static char *offsets_known_at;
349 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
351 /* Number of labels in the current function. */
353 static int num_labels;
355 struct hard_reg_n_uses { int regno; int uses; };
357 static int possible_group_p PROTO((int, int *));
358 static void count_possible_groups PROTO((int *, enum machine_mode *,
360 static int modes_equiv_for_class_p PROTO((enum machine_mode,
363 static void spill_failure PROTO((rtx));
364 static int new_spill_reg PROTO((int, int, int *, int *, int,
366 static void delete_dead_insn PROTO((rtx));
367 static void alter_reg PROTO((int, int));
368 static void mark_scratch_live PROTO((rtx));
369 static void set_label_offsets PROTO((rtx, rtx, int));
370 static int eliminate_regs_in_insn PROTO((rtx, int));
371 static void mark_not_eliminable PROTO((rtx, rtx));
372 static int spill_hard_reg PROTO((int, int, FILE *, int));
373 static void scan_paradoxical_subregs PROTO((rtx));
374 static int hard_reg_use_compare PROTO((const GENERIC_PTR, const GENERIC_PTR));
375 static void order_regs_for_reload PROTO((int));
376 static int compare_spill_regs PROTO((const GENERIC_PTR, const GENERIC_PTR));
377 static void reload_as_needed PROTO((rtx, int));
378 static void forget_old_reloads_1 PROTO((rtx, rtx));
379 static int reload_reg_class_lower PROTO((const GENERIC_PTR, const GENERIC_PTR));
380 static void mark_reload_reg_in_use PROTO((int, int, enum reload_type,
382 static void clear_reload_reg_in_use PROTO((int, int, enum reload_type,
384 static int reload_reg_free_p PROTO((int, int, enum reload_type));
385 static int reload_reg_free_before_p PROTO((int, int, enum reload_type));
386 static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type));
387 static int reloads_conflict PROTO((int, int));
388 static int allocate_reload_reg PROTO((int, rtx, int, int));
389 static void choose_reload_regs PROTO((rtx, rtx));
390 static void merge_assigned_reloads PROTO((rtx));
391 static void emit_reload_insns PROTO((rtx));
392 static void delete_output_reload PROTO((rtx, int, rtx));
393 static void inc_for_reload PROTO((rtx, rtx, int));
394 static int constraint_accepts_reg_p PROTO((char *, rtx));
395 static int count_occurrences PROTO((rtx, rtx));
397 /* Initialize the reload pass once per compilation. */
404 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
405 Set spill_indirect_levels to the number of levels such addressing is
406 permitted, zero if it is not permitted at all. */
409 = gen_rtx (MEM, Pmode,
410 gen_rtx (PLUS, Pmode,
411 gen_rtx (REG, Pmode, LAST_VIRTUAL_REGISTER + 1),
413 spill_indirect_levels = 0;
415 while (memory_address_p (QImode, tem))
417 spill_indirect_levels++;
418 tem = gen_rtx (MEM, Pmode, tem);
421 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
423 tem = gen_rtx (MEM, Pmode, gen_rtx (SYMBOL_REF, Pmode, "foo"));
424 indirect_symref_ok = memory_address_p (QImode, tem);
426 /* See if reg+reg is a valid (and offsettable) address. */
428 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
430 tem = gen_rtx (PLUS, Pmode,
431 gen_rtx (REG, Pmode, HARD_FRAME_POINTER_REGNUM),
432 gen_rtx (REG, Pmode, i));
433 /* This way, we make sure that reg+reg is an offsettable address. */
434 tem = plus_constant (tem, 4);
436 if (memory_address_p (QImode, tem))
438 double_reg_address_ok = 1;
443 /* Initialize obstack for our rtl allocation. */
444 gcc_obstack_init (&reload_obstack);
445 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
447 /* Decide which register class should be used when reloading
448 addresses. If we are using SMALL_REGISTER_CLASSES, and any
449 parameters are passed in registers, then we do not want to use
450 those registers when reloading an address. Otherwise, if a
451 function argument needs a reload, we may wind up clobbering
452 another argument to the function which was already computed. If
453 we find a subset class which simply avoids those registers, we
454 use it instead. ??? It would be better to only use the
455 restricted class when we actually are loading function arguments,
456 but that is hard to determine. */
457 reload_address_base_reg_class = BASE_REG_CLASS;
458 reload_address_index_reg_class = INDEX_REG_CLASS;
459 #ifdef SMALL_REGISTER_CLASSES
460 if (SMALL_REGISTER_CLASSES)
463 HARD_REG_SET base, index;
466 COPY_HARD_REG_SET (base, reg_class_contents[BASE_REG_CLASS]);
467 COPY_HARD_REG_SET (index, reg_class_contents[INDEX_REG_CLASS]);
468 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
470 if (FUNCTION_ARG_REGNO_P (regno))
472 CLEAR_HARD_REG_BIT (base, regno);
473 CLEAR_HARD_REG_BIT (index, regno);
477 GO_IF_HARD_REG_EQUAL (base, reg_class_contents[BASE_REG_CLASS],
479 for (p = reg_class_subclasses[BASE_REG_CLASS];
480 *p != LIM_REG_CLASSES;
483 GO_IF_HARD_REG_EQUAL (base, reg_class_contents[*p], usebase);
486 reload_address_base_reg_class = *p;
491 GO_IF_HARD_REG_EQUAL (index, reg_class_contents[INDEX_REG_CLASS],
493 for (p = reg_class_subclasses[INDEX_REG_CLASS];
494 *p != LIM_REG_CLASSES;
497 GO_IF_HARD_REG_EQUAL (index, reg_class_contents[*p], useindex);
500 reload_address_index_reg_class = *p;
505 #endif /* SMALL_REGISTER_CLASSES */
508 /* Main entry point for the reload pass.
510 FIRST is the first insn of the function being compiled.
512 GLOBAL nonzero means we were called from global_alloc
513 and should attempt to reallocate any pseudoregs that we
514 displace from hard regs we will use for reloads.
515 If GLOBAL is zero, we do not have enough information to do that,
516 so any pseudo reg that is spilled must go to the stack.
518 DUMPFILE is the global-reg debugging dump file stream, or 0.
519 If it is nonzero, messages are written to it to describe
520 which registers are seized as reload regs, which pseudo regs
521 are spilled from them, and where the pseudo regs are reallocated to.
523 Return value is nonzero if reload failed
524 and we must not do any more for this function. */
527 reload (first, global, dumpfile)
533 register int i, j, k;
535 register struct elim_table *ep;
537 int something_changed;
538 int something_needs_reloads;
539 int something_needs_elimination;
540 int new_basic_block_needs;
541 enum reg_class caller_save_spill_class = NO_REGS;
542 int caller_save_group_size = 1;
544 /* Nonzero means we couldn't get enough spill regs. */
547 /* The basic block number currently being processed for INSN. */
550 /* Make sure even insns with volatile mem refs are recognizable. */
553 /* Enable find_equiv_reg to distinguish insns made by reload. */
554 reload_first_uid = get_max_uid ();
556 for (i = 0; i < N_REG_CLASSES; i++)
557 basic_block_needs[i] = 0;
559 #ifdef SECONDARY_MEMORY_NEEDED
560 /* Initialize the secondary memory table. */
561 clear_secondary_mem ();
564 /* Remember which hard regs appear explicitly
565 before we merge into `regs_ever_live' the ones in which
566 pseudo regs have been allocated. */
567 bcopy (regs_ever_live, regs_explicitly_used, sizeof regs_ever_live);
569 /* We don't have a stack slot for any spill reg yet. */
570 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
571 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
573 /* Initialize the save area information for caller-save, in case some
577 /* Compute which hard registers are now in use
578 as homes for pseudo registers.
579 This is done here rather than (eg) in global_alloc
580 because this point is reached even if not optimizing. */
582 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
585 for (i = 0; i < scratch_list_length; i++)
587 mark_scratch_live (scratch_list[i]);
589 /* Make sure that the last insn in the chain
590 is not something that needs reloading. */
591 emit_note (NULL_PTR, NOTE_INSN_DELETED);
593 /* Find all the pseudo registers that didn't get hard regs
594 but do have known equivalent constants or memory slots.
595 These include parameters (known equivalent to parameter slots)
596 and cse'd or loop-moved constant memory addresses.
598 Record constant equivalents in reg_equiv_constant
599 so they will be substituted by find_reloads.
600 Record memory equivalents in reg_mem_equiv so they can
601 be substituted eventually by altering the REG-rtx's. */
603 reg_equiv_constant = (rtx *) alloca (max_regno * sizeof (rtx));
604 bzero ((char *) reg_equiv_constant, max_regno * sizeof (rtx));
605 reg_equiv_memory_loc = (rtx *) alloca (max_regno * sizeof (rtx));
606 bzero ((char *) reg_equiv_memory_loc, max_regno * sizeof (rtx));
607 reg_equiv_mem = (rtx *) alloca (max_regno * sizeof (rtx));
608 bzero ((char *) reg_equiv_mem, max_regno * sizeof (rtx));
609 reg_equiv_init = (rtx *) alloca (max_regno * sizeof (rtx));
610 bzero ((char *) reg_equiv_init, max_regno * sizeof (rtx));
611 reg_equiv_address = (rtx *) alloca (max_regno * sizeof (rtx));
612 bzero ((char *) reg_equiv_address, max_regno * sizeof (rtx));
613 reg_max_ref_width = (int *) alloca (max_regno * sizeof (int));
614 bzero ((char *) reg_max_ref_width, max_regno * sizeof (int));
615 cannot_omit_stores = (char *) alloca (max_regno);
616 bzero (cannot_omit_stores, max_regno);
618 #ifdef SMALL_REGISTER_CLASSES
619 if (SMALL_REGISTER_CLASSES)
620 CLEAR_HARD_REG_SET (forbidden_regs);
623 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
624 Also find all paradoxical subregs and find largest such for each pseudo.
625 On machines with small register classes, record hard registers that
626 are used for user variables. These can never be used for spills.
627 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
628 caller-saved registers must be marked live. */
630 for (insn = first; insn; insn = NEXT_INSN (insn))
632 rtx set = single_set (insn);
634 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
635 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
636 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
637 if (! call_used_regs[i])
638 regs_ever_live[i] = 1;
640 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
642 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
644 #ifdef LEGITIMATE_PIC_OPERAND_P
645 && (! CONSTANT_P (XEXP (note, 0)) || ! flag_pic
646 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
650 rtx x = XEXP (note, 0);
651 i = REGNO (SET_DEST (set));
652 if (i > LAST_VIRTUAL_REGISTER)
654 if (GET_CODE (x) == MEM)
655 reg_equiv_memory_loc[i] = x;
656 else if (CONSTANT_P (x))
658 if (LEGITIMATE_CONSTANT_P (x))
659 reg_equiv_constant[i] = x;
661 reg_equiv_memory_loc[i]
662 = force_const_mem (GET_MODE (SET_DEST (set)), x);
667 /* If this register is being made equivalent to a MEM
668 and the MEM is not SET_SRC, the equivalencing insn
669 is one with the MEM as a SET_DEST and it occurs later.
670 So don't mark this insn now. */
671 if (GET_CODE (x) != MEM
672 || rtx_equal_p (SET_SRC (set), x))
673 reg_equiv_init[i] = insn;
678 /* If this insn is setting a MEM from a register equivalent to it,
679 this is the equivalencing insn. */
680 else if (set && GET_CODE (SET_DEST (set)) == MEM
681 && GET_CODE (SET_SRC (set)) == REG
682 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
683 && rtx_equal_p (SET_DEST (set),
684 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
685 reg_equiv_init[REGNO (SET_SRC (set))] = insn;
687 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
688 scan_paradoxical_subregs (PATTERN (insn));
691 /* Does this function require a frame pointer? */
693 frame_pointer_needed = (! flag_omit_frame_pointer
694 #ifdef EXIT_IGNORE_STACK
695 /* ?? If EXIT_IGNORE_STACK is set, we will not save
696 and restore sp for alloca. So we can't eliminate
697 the frame pointer in that case. At some point,
698 we should improve this by emitting the
699 sp-adjusting insns for this case. */
700 || (current_function_calls_alloca
701 && EXIT_IGNORE_STACK)
703 || FRAME_POINTER_REQUIRED);
707 /* Initialize the table of registers to eliminate. The way we do this
708 depends on how the eliminable registers were defined. */
709 #ifdef ELIMINABLE_REGS
710 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
712 ep->can_eliminate = ep->can_eliminate_previous
713 = (CAN_ELIMINATE (ep->from, ep->to)
714 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
717 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
718 = ! frame_pointer_needed;
721 /* Count the number of eliminable registers and build the FROM and TO
722 REG rtx's. Note that code in gen_rtx will cause, e.g.,
723 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
724 We depend on this. */
725 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
727 num_eliminable += ep->can_eliminate;
728 ep->from_rtx = gen_rtx (REG, Pmode, ep->from);
729 ep->to_rtx = gen_rtx (REG, Pmode, ep->to);
732 num_labels = max_label_num () - get_first_label_num ();
734 /* Allocate the tables used to store offset information at labels. */
735 offsets_known_at = (char *) alloca (num_labels);
737 = (int (*)[NUM_ELIMINABLE_REGS])
738 alloca (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
740 offsets_known_at -= get_first_label_num ();
741 offsets_at -= get_first_label_num ();
743 /* Alter each pseudo-reg rtx to contain its hard reg number.
744 Assign stack slots to the pseudos that lack hard regs or equivalents.
745 Do not touch virtual registers. */
747 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
750 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done here
751 because the stack size may be a part of the offset computation for
752 register elimination. */
753 assign_stack_local (BLKmode, 0, 0);
755 /* If we have some registers we think can be eliminated, scan all insns to
756 see if there is an insn that sets one of these registers to something
757 other than itself plus a constant. If so, the register cannot be
758 eliminated. Doing this scan here eliminates an extra pass through the
759 main reload loop in the most common case where register elimination
761 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
762 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
763 || GET_CODE (insn) == CALL_INSN)
764 note_stores (PATTERN (insn), mark_not_eliminable);
766 #ifndef REGISTER_CONSTRAINTS
767 /* If all the pseudo regs have hard regs,
768 except for those that are never referenced,
769 we know that no reloads are needed. */
770 /* But that is not true if there are register constraints, since
771 in that case some pseudos might be in the wrong kind of hard reg. */
773 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
774 if (reg_renumber[i] == -1 && reg_n_refs[i] != 0)
777 if (i == max_regno && num_eliminable == 0 && ! caller_save_needed)
781 /* Compute the order of preference for hard registers to spill.
782 Store them by decreasing preference in potential_reload_regs. */
784 order_regs_for_reload (global);
786 /* So far, no hard regs have been spilled. */
788 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
789 spill_reg_order[i] = -1;
791 /* Initialize to -1, which means take the first spill register. */
794 /* On most machines, we can't use any register explicitly used in the
795 rtl as a spill register. But on some, we have to. Those will have
796 taken care to keep the life of hard regs as short as possible. */
798 #ifdef SMALL_REGISTER_CLASSES
799 if (! SMALL_REGISTER_CLASSES)
801 COPY_HARD_REG_SET (forbidden_regs, bad_spill_regs);
803 /* Spill any hard regs that we know we can't eliminate. */
804 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
805 if (! ep->can_eliminate)
806 spill_hard_reg (ep->from, global, dumpfile, 1);
808 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
809 if (frame_pointer_needed)
810 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, global, dumpfile, 1);
814 for (i = 0; i < N_REG_CLASSES; i++)
816 basic_block_needs[i] = (char *) alloca (n_basic_blocks);
817 bzero (basic_block_needs[i], n_basic_blocks);
820 /* From now on, we need to emit any moves without making new pseudos. */
821 reload_in_progress = 1;
823 /* This loop scans the entire function each go-round
824 and repeats until one repetition spills no additional hard regs. */
826 /* This flag is set when a pseudo reg is spilled,
827 to require another pass. Note that getting an additional reload
828 reg does not necessarily imply any pseudo reg was spilled;
829 sometimes we find a reload reg that no pseudo reg was allocated in. */
830 something_changed = 1;
831 /* This flag is set if there are any insns that require reloading. */
832 something_needs_reloads = 0;
833 /* This flag is set if there are any insns that require register
835 something_needs_elimination = 0;
836 while (something_changed)
840 /* For each class, number of reload regs needed in that class.
841 This is the maximum over all insns of the needs in that class
842 of the individual insn. */
843 int max_needs[N_REG_CLASSES];
844 /* For each class, size of group of consecutive regs
845 that is needed for the reloads of this class. */
846 int group_size[N_REG_CLASSES];
847 /* For each class, max number of consecutive groups needed.
848 (Each group contains group_size[CLASS] consecutive registers.) */
849 int max_groups[N_REG_CLASSES];
850 /* For each class, max number needed of regs that don't belong
851 to any of the groups. */
852 int max_nongroups[N_REG_CLASSES];
853 /* For each class, the machine mode which requires consecutive
854 groups of regs of that class.
855 If two different modes ever require groups of one class,
856 they must be the same size and equally restrictive for that class,
857 otherwise we can't handle the complexity. */
858 enum machine_mode group_mode[N_REG_CLASSES];
859 /* Record the insn where each maximum need is first found. */
860 rtx max_needs_insn[N_REG_CLASSES];
861 rtx max_groups_insn[N_REG_CLASSES];
862 rtx max_nongroups_insn[N_REG_CLASSES];
864 HOST_WIDE_INT starting_frame_size = get_frame_size ();
865 int previous_frame_pointer_needed = frame_pointer_needed;
866 static char *reg_class_names[] = REG_CLASS_NAMES;
868 something_changed = 0;
869 bzero ((char *) max_needs, sizeof max_needs);
870 bzero ((char *) max_groups, sizeof max_groups);
871 bzero ((char *) max_nongroups, sizeof max_nongroups);
872 bzero ((char *) max_needs_insn, sizeof max_needs_insn);
873 bzero ((char *) max_groups_insn, sizeof max_groups_insn);
874 bzero ((char *) max_nongroups_insn, sizeof max_nongroups_insn);
875 bzero ((char *) group_size, sizeof group_size);
876 for (i = 0; i < N_REG_CLASSES; i++)
877 group_mode[i] = VOIDmode;
879 /* Keep track of which basic blocks are needing the reloads. */
882 /* Remember whether any element of basic_block_needs
883 changes from 0 to 1 in this pass. */
884 new_basic_block_needs = 0;
886 /* Reset all offsets on eliminable registers to their initial values. */
887 #ifdef ELIMINABLE_REGS
888 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
890 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
891 ep->previous_offset = ep->offset
892 = ep->max_offset = ep->initial_offset;
895 #ifdef INITIAL_FRAME_POINTER_OFFSET
896 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
898 if (!FRAME_POINTER_REQUIRED)
900 reg_eliminate[0].initial_offset = 0;
902 reg_eliminate[0].previous_offset = reg_eliminate[0].max_offset
903 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
906 num_not_at_initial_offset = 0;
908 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
910 /* Set a known offset for each forced label to be at the initial offset
911 of each elimination. We do this because we assume that all
912 computed jumps occur from a location where each elimination is
913 at its initial offset. */
915 for (x = forced_labels; x; x = XEXP (x, 1))
917 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
919 /* For each pseudo register that has an equivalent location defined,
920 try to eliminate any eliminable registers (such as the frame pointer)
921 assuming initial offsets for the replacement register, which
924 If the resulting location is directly addressable, substitute
925 the MEM we just got directly for the old REG.
927 If it is not addressable but is a constant or the sum of a hard reg
928 and constant, it is probably not addressable because the constant is
929 out of range, in that case record the address; we will generate
930 hairy code to compute the address in a register each time it is
931 needed. Similarly if it is a hard register, but one that is not
932 valid as an address register.
934 If the location is not addressable, but does not have one of the
935 above forms, assign a stack slot. We have to do this to avoid the
936 potential of producing lots of reloads if, e.g., a location involves
937 a pseudo that didn't get a hard register and has an equivalent memory
938 location that also involves a pseudo that didn't get a hard register.
940 Perhaps at some point we will improve reload_when_needed handling
941 so this problem goes away. But that's very hairy. */
943 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
944 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
946 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
948 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
950 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
951 else if (CONSTANT_P (XEXP (x, 0))
952 || (GET_CODE (XEXP (x, 0)) == REG
953 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
954 || (GET_CODE (XEXP (x, 0)) == PLUS
955 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
956 && (REGNO (XEXP (XEXP (x, 0), 0))
957 < FIRST_PSEUDO_REGISTER)
958 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
959 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
962 /* Make a new stack slot. Then indicate that something
963 changed so we go back and recompute offsets for
964 eliminable registers because the allocation of memory
965 below might change some offset. reg_equiv_{mem,address}
966 will be set up for this pseudo on the next pass around
968 reg_equiv_memory_loc[i] = 0;
969 reg_equiv_init[i] = 0;
971 something_changed = 1;
975 /* If we allocated another pseudo to the stack, redo elimination
977 if (something_changed)
980 /* If caller-saves needs a group, initialize the group to include
981 the size and mode required for caller-saves. */
983 if (caller_save_group_size > 1)
985 group_mode[(int) caller_save_spill_class] = Pmode;
986 group_size[(int) caller_save_spill_class] = caller_save_group_size;
989 /* Compute the most additional registers needed by any instruction.
990 Collect information separately for each class of regs. */
992 for (insn = first; insn; insn = NEXT_INSN (insn))
994 if (global && this_block + 1 < n_basic_blocks
995 && insn == basic_block_head[this_block+1])
998 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which
999 might include REG_LABEL), we need to see what effects this
1000 has on the known offsets at labels. */
1002 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1003 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1004 && REG_NOTES (insn) != 0))
1005 set_label_offsets (insn, insn, 0);
1007 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1009 /* Nonzero means don't use a reload reg that overlaps
1010 the place where a function value can be returned. */
1011 rtx avoid_return_reg = 0;
1013 rtx old_body = PATTERN (insn);
1014 int old_code = INSN_CODE (insn);
1015 rtx old_notes = REG_NOTES (insn);
1016 int did_elimination = 0;
1018 /* To compute the number of reload registers of each class
1019 needed for an insn, we must simulate what choose_reload_regs
1020 can do. We do this by splitting an insn into an "input" and
1021 an "output" part. RELOAD_OTHER reloads are used in both.
1022 The input part uses those reloads, RELOAD_FOR_INPUT reloads,
1023 which must be live over the entire input section of reloads,
1024 and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
1025 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the
1028 The registers needed for output are RELOAD_OTHER and
1029 RELOAD_FOR_OUTPUT, which are live for the entire output
1030 portion, and the maximum of all the RELOAD_FOR_OUTPUT_ADDRESS
1031 reloads for each operand.
1033 The total number of registers needed is the maximum of the
1034 inputs and outputs. */
1038 /* [0] is normal, [1] is nongroup. */
1039 int regs[2][N_REG_CLASSES];
1040 int groups[N_REG_CLASSES];
1043 /* Each `struct needs' corresponds to one RELOAD_... type. */
1047 struct needs output;
1049 struct needs other_addr;
1050 struct needs op_addr;
1051 struct needs op_addr_reload;
1052 struct needs in_addr[MAX_RECOG_OPERANDS];
1053 struct needs in_addr_addr[MAX_RECOG_OPERANDS];
1054 struct needs out_addr[MAX_RECOG_OPERANDS];
1055 struct needs out_addr_addr[MAX_RECOG_OPERANDS];
1058 /* If needed, eliminate any eliminable registers. */
1060 did_elimination = eliminate_regs_in_insn (insn, 0);
1062 #ifdef SMALL_REGISTER_CLASSES
1063 /* Set avoid_return_reg if this is an insn
1064 that might use the value of a function call. */
1065 if (SMALL_REGISTER_CLASSES && GET_CODE (insn) == CALL_INSN)
1067 if (GET_CODE (PATTERN (insn)) == SET)
1068 after_call = SET_DEST (PATTERN (insn));
1069 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1070 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1071 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
1075 else if (SMALL_REGISTER_CLASSES
1077 && !(GET_CODE (PATTERN (insn)) == SET
1078 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
1080 if (reg_referenced_p (after_call, PATTERN (insn)))
1081 avoid_return_reg = after_call;
1084 #endif /* SMALL_REGISTER_CLASSES */
1086 /* Analyze the instruction. */
1087 find_reloads (insn, 0, spill_indirect_levels, global,
1090 /* Remember for later shortcuts which insns had any reloads or
1091 register eliminations.
1093 One might think that it would be worthwhile to mark insns
1094 that need register replacements but not reloads, but this is
1095 not safe because find_reloads may do some manipulation of
1096 the insn (such as swapping commutative operands), which would
1097 be lost when we restore the old pattern after register
1098 replacement. So the actions of find_reloads must be redone in
1099 subsequent passes or in reload_as_needed.
1101 However, it is safe to mark insns that need reloads
1102 but not register replacement. */
1104 PUT_MODE (insn, (did_elimination ? QImode
1105 : n_reloads ? HImode
1106 : GET_MODE (insn) == DImode ? DImode
1109 /* Discard any register replacements done. */
1110 if (did_elimination)
1112 obstack_free (&reload_obstack, reload_firstobj);
1113 PATTERN (insn) = old_body;
1114 INSN_CODE (insn) = old_code;
1115 REG_NOTES (insn) = old_notes;
1116 something_needs_elimination = 1;
1119 /* If this insn has no reloads, we need not do anything except
1120 in the case of a CALL_INSN when we have caller-saves and
1121 caller-save needs reloads. */
1124 && ! (GET_CODE (insn) == CALL_INSN
1125 && caller_save_spill_class != NO_REGS))
1128 something_needs_reloads = 1;
1129 bzero ((char *) &insn_needs, sizeof insn_needs);
1131 /* Count each reload once in every class
1132 containing the reload's own class. */
1134 for (i = 0; i < n_reloads; i++)
1136 register enum reg_class *p;
1137 enum reg_class class = reload_reg_class[i];
1139 enum machine_mode mode;
1141 struct needs *this_needs;
1143 /* Don't count the dummy reloads, for which one of the
1144 regs mentioned in the insn can be used for reloading.
1145 Don't count optional reloads.
1146 Don't count reloads that got combined with others. */
1147 if (reload_reg_rtx[i] != 0
1148 || reload_optional[i] != 0
1149 || (reload_out[i] == 0 && reload_in[i] == 0
1150 && ! reload_secondary_p[i]))
1153 /* Show that a reload register of this class is needed
1154 in this basic block. We do not use insn_needs and
1155 insn_groups because they are overly conservative for
1157 if (global && ! basic_block_needs[(int) class][this_block])
1159 basic_block_needs[(int) class][this_block] = 1;
1160 new_basic_block_needs = 1;
1164 mode = reload_inmode[i];
1165 if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode))
1166 mode = reload_outmode[i];
1167 size = CLASS_MAX_NREGS (class, mode);
1169 /* If this class doesn't want a group, determine if we have
1170 a nongroup need or a regular need. We have a nongroup
1171 need if this reload conflicts with a group reload whose
1172 class intersects with this reload's class. */
1176 for (j = 0; j < n_reloads; j++)
1177 if ((CLASS_MAX_NREGS (reload_reg_class[j],
1178 (GET_MODE_SIZE (reload_outmode[j])
1179 > GET_MODE_SIZE (reload_inmode[j]))
1183 && (!reload_optional[j])
1184 && (reload_in[j] != 0 || reload_out[j] != 0
1185 || reload_secondary_p[j])
1186 && reloads_conflict (i, j)
1187 && reg_classes_intersect_p (class,
1188 reload_reg_class[j]))
1194 /* Decide which time-of-use to count this reload for. */
1195 switch (reload_when_needed[i])
1198 this_needs = &insn_needs.other;
1200 case RELOAD_FOR_INPUT:
1201 this_needs = &insn_needs.input;
1203 case RELOAD_FOR_OUTPUT:
1204 this_needs = &insn_needs.output;
1206 case RELOAD_FOR_INSN:
1207 this_needs = &insn_needs.insn;
1209 case RELOAD_FOR_OTHER_ADDRESS:
1210 this_needs = &insn_needs.other_addr;
1212 case RELOAD_FOR_INPUT_ADDRESS:
1213 this_needs = &insn_needs.in_addr[reload_opnum[i]];
1215 case RELOAD_FOR_INPADDR_ADDRESS:
1216 this_needs = &insn_needs.in_addr_addr[reload_opnum[i]];
1218 case RELOAD_FOR_OUTPUT_ADDRESS:
1219 this_needs = &insn_needs.out_addr[reload_opnum[i]];
1221 case RELOAD_FOR_OUTADDR_ADDRESS:
1222 this_needs = &insn_needs.out_addr_addr[reload_opnum[i]];
1224 case RELOAD_FOR_OPERAND_ADDRESS:
1225 this_needs = &insn_needs.op_addr;
1227 case RELOAD_FOR_OPADDR_ADDR:
1228 this_needs = &insn_needs.op_addr_reload;
1234 enum machine_mode other_mode, allocate_mode;
1236 /* Count number of groups needed separately from
1237 number of individual regs needed. */
1238 this_needs->groups[(int) class]++;
1239 p = reg_class_superclasses[(int) class];
1240 while (*p != LIM_REG_CLASSES)
1241 this_needs->groups[(int) *p++]++;
1243 /* Record size and mode of a group of this class. */
1244 /* If more than one size group is needed,
1245 make all groups the largest needed size. */
1246 if (group_size[(int) class] < size)
1248 other_mode = group_mode[(int) class];
1249 allocate_mode = mode;
1251 group_size[(int) class] = size;
1252 group_mode[(int) class] = mode;
1257 allocate_mode = group_mode[(int) class];
1260 /* Crash if two dissimilar machine modes both need
1261 groups of consecutive regs of the same class. */
1263 if (other_mode != VOIDmode && other_mode != allocate_mode
1264 && ! modes_equiv_for_class_p (allocate_mode,
1266 fatal_insn ("Two dissimilar machine modes both need groups of consecutive regs of the same class",
1271 this_needs->regs[nongroup_need][(int) class] += 1;
1272 p = reg_class_superclasses[(int) class];
1273 while (*p != LIM_REG_CLASSES)
1274 this_needs->regs[nongroup_need][(int) *p++] += 1;
1280 /* All reloads have been counted for this insn;
1281 now merge the various times of use.
1282 This sets insn_needs, etc., to the maximum total number
1283 of registers needed at any point in this insn. */
1285 for (i = 0; i < N_REG_CLASSES; i++)
1287 int in_max, out_max;
1289 /* Compute normal and nongroup needs. */
1290 for (j = 0; j <= 1; j++)
1292 for (in_max = 0, out_max = 0, k = 0;
1293 k < reload_n_operands; k++)
1296 = MAX (in_max, insn_needs.in_addr[k].regs[j][i]);
1299 insn_needs.in_addr_addr[k].regs[j][i]);
1301 = MAX (out_max, insn_needs.out_addr[k].regs[j][i]);
1304 insn_needs.out_addr_addr[k].regs[j][i]);
1307 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1308 and operand addresses but not things used to reload
1309 them. Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads
1310 don't conflict with things needed to reload inputs or
1313 in_max = MAX (MAX (insn_needs.op_addr.regs[j][i],
1314 insn_needs.op_addr_reload.regs[j][i]),
1317 out_max = MAX (out_max, insn_needs.insn.regs[j][i]);
1319 insn_needs.input.regs[j][i]
1320 = MAX (insn_needs.input.regs[j][i]
1321 + insn_needs.op_addr.regs[j][i]
1322 + insn_needs.insn.regs[j][i],
1323 in_max + insn_needs.input.regs[j][i]);
1325 insn_needs.output.regs[j][i] += out_max;
1326 insn_needs.other.regs[j][i]
1327 += MAX (MAX (insn_needs.input.regs[j][i],
1328 insn_needs.output.regs[j][i]),
1329 insn_needs.other_addr.regs[j][i]);
1333 /* Now compute group needs. */
1334 for (in_max = 0, out_max = 0, j = 0;
1335 j < reload_n_operands; j++)
1337 in_max = MAX (in_max, insn_needs.in_addr[j].groups[i]);
1338 in_max = MAX (in_max,
1339 insn_needs.in_addr_addr[j].groups[i]);
1341 = MAX (out_max, insn_needs.out_addr[j].groups[i]);
1343 = MAX (out_max, insn_needs.out_addr_addr[j].groups[i]);
1346 in_max = MAX (MAX (insn_needs.op_addr.groups[i],
1347 insn_needs.op_addr_reload.groups[i]),
1349 out_max = MAX (out_max, insn_needs.insn.groups[i]);
1351 insn_needs.input.groups[i]
1352 = MAX (insn_needs.input.groups[i]
1353 + insn_needs.op_addr.groups[i]
1354 + insn_needs.insn.groups[i],
1355 in_max + insn_needs.input.groups[i]);
1357 insn_needs.output.groups[i] += out_max;
1358 insn_needs.other.groups[i]
1359 += MAX (MAX (insn_needs.input.groups[i],
1360 insn_needs.output.groups[i]),
1361 insn_needs.other_addr.groups[i]);
1364 /* If this is a CALL_INSN and caller-saves will need
1365 a spill register, act as if the spill register is
1366 needed for this insn. However, the spill register
1367 can be used by any reload of this insn, so we only
1368 need do something if no need for that class has
1371 The assumption that every CALL_INSN will trigger a
1372 caller-save is highly conservative, however, the number
1373 of cases where caller-saves will need a spill register but
1374 a block containing a CALL_INSN won't need a spill register
1375 of that class should be quite rare.
1377 If a group is needed, the size and mode of the group will
1378 have been set up at the beginning of this loop. */
1380 if (GET_CODE (insn) == CALL_INSN
1381 && caller_save_spill_class != NO_REGS)
1383 /* See if this register would conflict with any reload
1384 that needs a group. */
1385 int nongroup_need = 0;
1386 int *caller_save_needs;
1388 for (j = 0; j < n_reloads; j++)
1389 if ((CLASS_MAX_NREGS (reload_reg_class[j],
1390 (GET_MODE_SIZE (reload_outmode[j])
1391 > GET_MODE_SIZE (reload_inmode[j]))
1395 && reg_classes_intersect_p (caller_save_spill_class,
1396 reload_reg_class[j]))
1403 = (caller_save_group_size > 1
1404 ? insn_needs.other.groups
1405 : insn_needs.other.regs[nongroup_need]);
1407 if (caller_save_needs[(int) caller_save_spill_class] == 0)
1409 register enum reg_class *p
1410 = reg_class_superclasses[(int) caller_save_spill_class];
1412 caller_save_needs[(int) caller_save_spill_class]++;
1414 while (*p != LIM_REG_CLASSES)
1415 caller_save_needs[(int) *p++] += 1;
1418 /* Show that this basic block will need a register of
1422 && ! (basic_block_needs[(int) caller_save_spill_class]
1425 basic_block_needs[(int) caller_save_spill_class]
1427 new_basic_block_needs = 1;
1431 #ifdef SMALL_REGISTER_CLASSES
1432 /* If this insn stores the value of a function call,
1433 and that value is in a register that has been spilled,
1434 and if the insn needs a reload in a class
1435 that might use that register as the reload register,
1436 then add add an extra need in that class.
1437 This makes sure we have a register available that does
1438 not overlap the return value. */
1440 if (SMALL_REGISTER_CLASSES && avoid_return_reg)
1442 int regno = REGNO (avoid_return_reg);
1444 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
1446 int basic_needs[N_REG_CLASSES], basic_groups[N_REG_CLASSES];
1448 /* First compute the "basic needs", which counts a
1449 need only in the smallest class in which it
1452 bcopy ((char *) insn_needs.other.regs[0],
1453 (char *) basic_needs, sizeof basic_needs);
1454 bcopy ((char *) insn_needs.other.groups,
1455 (char *) basic_groups, sizeof basic_groups);
1457 for (i = 0; i < N_REG_CLASSES; i++)
1461 if (basic_needs[i] >= 0)
1462 for (p = reg_class_superclasses[i];
1463 *p != LIM_REG_CLASSES; p++)
1464 basic_needs[(int) *p] -= basic_needs[i];
1466 if (basic_groups[i] >= 0)
1467 for (p = reg_class_superclasses[i];
1468 *p != LIM_REG_CLASSES; p++)
1469 basic_groups[(int) *p] -= basic_groups[i];
1472 /* Now count extra regs if there might be a conflict with
1473 the return value register. */
1475 for (r = regno; r < regno + nregs; r++)
1476 if (spill_reg_order[r] >= 0)
1477 for (i = 0; i < N_REG_CLASSES; i++)
1478 if (TEST_HARD_REG_BIT (reg_class_contents[i], r))
1480 if (basic_needs[i] > 0)
1484 insn_needs.other.regs[0][i]++;
1485 p = reg_class_superclasses[i];
1486 while (*p != LIM_REG_CLASSES)
1487 insn_needs.other.regs[0][(int) *p++]++;
1489 if (basic_groups[i] > 0)
1493 insn_needs.other.groups[i]++;
1494 p = reg_class_superclasses[i];
1495 while (*p != LIM_REG_CLASSES)
1496 insn_needs.other.groups[(int) *p++]++;
1500 #endif /* SMALL_REGISTER_CLASSES */
1502 /* For each class, collect maximum need of any insn. */
1504 for (i = 0; i < N_REG_CLASSES; i++)
1506 if (max_needs[i] < insn_needs.other.regs[0][i])
1508 max_needs[i] = insn_needs.other.regs[0][i];
1509 max_needs_insn[i] = insn;
1511 if (max_groups[i] < insn_needs.other.groups[i])
1513 max_groups[i] = insn_needs.other.groups[i];
1514 max_groups_insn[i] = insn;
1516 if (max_nongroups[i] < insn_needs.other.regs[1][i])
1518 max_nongroups[i] = insn_needs.other.regs[1][i];
1519 max_nongroups_insn[i] = insn;
1523 /* Note that there is a continue statement above. */
1526 /* If we allocated any new memory locations, make another pass
1527 since it might have changed elimination offsets. */
1528 if (starting_frame_size != get_frame_size ())
1529 something_changed = 1;
1532 for (i = 0; i < N_REG_CLASSES; i++)
1534 if (max_needs[i] > 0)
1536 ";; Need %d reg%s of class %s (for insn %d).\n",
1537 max_needs[i], max_needs[i] == 1 ? "" : "s",
1538 reg_class_names[i], INSN_UID (max_needs_insn[i]));
1539 if (max_nongroups[i] > 0)
1541 ";; Need %d nongroup reg%s of class %s (for insn %d).\n",
1542 max_nongroups[i], max_nongroups[i] == 1 ? "" : "s",
1543 reg_class_names[i], INSN_UID (max_nongroups_insn[i]));
1544 if (max_groups[i] > 0)
1546 ";; Need %d group%s (%smode) of class %s (for insn %d).\n",
1547 max_groups[i], max_groups[i] == 1 ? "" : "s",
1548 mode_name[(int) group_mode[i]],
1549 reg_class_names[i], INSN_UID (max_groups_insn[i]));
1552 /* If we have caller-saves, set up the save areas and see if caller-save
1553 will need a spill register. */
1555 if (caller_save_needed)
1557 /* Set the offsets for setup_save_areas. */
1558 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
1560 ep->previous_offset = ep->max_offset;
1562 if ( ! setup_save_areas (&something_changed)
1563 && caller_save_spill_class == NO_REGS)
1565 /* The class we will need depends on whether the machine
1566 supports the sum of two registers for an address; see
1567 find_address_reloads for details. */
1569 caller_save_spill_class
1570 = double_reg_address_ok ? INDEX_REG_CLASS : BASE_REG_CLASS;
1571 caller_save_group_size
1572 = CLASS_MAX_NREGS (caller_save_spill_class, Pmode);
1573 something_changed = 1;
1577 /* See if anything that happened changes which eliminations are valid.
1578 For example, on the Sparc, whether or not the frame pointer can
1579 be eliminated can depend on what registers have been used. We need
1580 not check some conditions again (such as flag_omit_frame_pointer)
1581 since they can't have changed. */
1583 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1584 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
1585 #ifdef ELIMINABLE_REGS
1586 || ! CAN_ELIMINATE (ep->from, ep->to)
1589 ep->can_eliminate = 0;
1591 /* Look for the case where we have discovered that we can't replace
1592 register A with register B and that means that we will now be
1593 trying to replace register A with register C. This means we can
1594 no longer replace register C with register B and we need to disable
1595 such an elimination, if it exists. This occurs often with A == ap,
1596 B == sp, and C == fp. */
1598 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1600 struct elim_table *op;
1601 register int new_to = -1;
1603 if (! ep->can_eliminate && ep->can_eliminate_previous)
1605 /* Find the current elimination for ep->from, if there is a
1607 for (op = reg_eliminate;
1608 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1609 if (op->from == ep->from && op->can_eliminate)
1615 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
1617 for (op = reg_eliminate;
1618 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1619 if (op->from == new_to && op->to == ep->to)
1620 op->can_eliminate = 0;
1624 /* See if any registers that we thought we could eliminate the previous
1625 time are no longer eliminable. If so, something has changed and we
1626 must spill the register. Also, recompute the number of eliminable
1627 registers and see if the frame pointer is needed; it is if there is
1628 no elimination of the frame pointer that we can perform. */
1630 frame_pointer_needed = 1;
1631 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1633 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
1634 && ep->to != HARD_FRAME_POINTER_REGNUM)
1635 frame_pointer_needed = 0;
1637 if (! ep->can_eliminate && ep->can_eliminate_previous)
1639 ep->can_eliminate_previous = 0;
1640 spill_hard_reg (ep->from, global, dumpfile, 1);
1641 something_changed = 1;
1646 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1647 /* If we didn't need a frame pointer last time, but we do now, spill
1648 the hard frame pointer. */
1649 if (frame_pointer_needed && ! previous_frame_pointer_needed)
1651 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, global, dumpfile, 1);
1652 something_changed = 1;
1656 /* If all needs are met, we win. */
1658 for (i = 0; i < N_REG_CLASSES; i++)
1659 if (max_needs[i] > 0 || max_groups[i] > 0 || max_nongroups[i] > 0)
1661 if (i == N_REG_CLASSES && !new_basic_block_needs && ! something_changed)
1664 /* Not all needs are met; must spill some hard regs. */
1666 /* Put all registers spilled so far back in potential_reload_regs, but
1667 put them at the front, since we've already spilled most of the
1668 pseudos in them (we might have left some pseudos unspilled if they
1669 were in a block that didn't need any spill registers of a conflicting
1670 class. We used to try to mark off the need for those registers,
1671 but doing so properly is very complex and reallocating them is the
1672 simpler approach. First, "pack" potential_reload_regs by pushing
1673 any nonnegative entries towards the end. That will leave room
1674 for the registers we already spilled.
1676 Also, undo the marking of the spill registers from the last time
1677 around in FORBIDDEN_REGS since we will be probably be allocating
1680 ??? It is theoretically possible that we might end up not using one
1681 of our previously-spilled registers in this allocation, even though
1682 they are at the head of the list. It's not clear what to do about
1683 this, but it was no better before, when we marked off the needs met
1684 by the previously-spilled registers. With the current code, globals
1685 can be allocated into these registers, but locals cannot. */
1689 for (i = j = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
1690 if (potential_reload_regs[i] != -1)
1691 potential_reload_regs[j--] = potential_reload_regs[i];
1693 for (i = 0; i < n_spills; i++)
1695 potential_reload_regs[i] = spill_regs[i];
1696 spill_reg_order[spill_regs[i]] = -1;
1697 CLEAR_HARD_REG_BIT (forbidden_regs, spill_regs[i]);
1703 /* Now find more reload regs to satisfy the remaining need
1704 Do it by ascending class number, since otherwise a reg
1705 might be spilled for a big class and might fail to count
1706 for a smaller class even though it belongs to that class.
1708 Count spilled regs in `spills', and add entries to
1709 `spill_regs' and `spill_reg_order'.
1711 ??? Note there is a problem here.
1712 When there is a need for a group in a high-numbered class,
1713 and also need for non-group regs that come from a lower class,
1714 the non-group regs are chosen first. If there aren't many regs,
1715 they might leave no room for a group.
1717 This was happening on the 386. To fix it, we added the code
1718 that calls possible_group_p, so that the lower class won't
1719 break up the last possible group.
1721 Really fixing the problem would require changes above
1722 in counting the regs already spilled, and in choose_reload_regs.
1723 It might be hard to avoid introducing bugs there. */
1725 CLEAR_HARD_REG_SET (counted_for_groups);
1726 CLEAR_HARD_REG_SET (counted_for_nongroups);
1728 for (class = 0; class < N_REG_CLASSES; class++)
1730 /* First get the groups of registers.
1731 If we got single registers first, we might fragment
1733 while (max_groups[class] > 0)
1735 /* If any single spilled regs happen to form groups,
1736 count them now. Maybe we don't really need
1737 to spill another group. */
1738 count_possible_groups (group_size, group_mode, max_groups,
1741 if (max_groups[class] <= 0)
1744 /* Groups of size 2 (the only groups used on most machines)
1745 are treated specially. */
1746 if (group_size[class] == 2)
1748 /* First, look for a register that will complete a group. */
1749 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1753 j = potential_reload_regs[i];
1754 if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1756 ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1757 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1758 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1759 && HARD_REGNO_MODE_OK (other, group_mode[class])
1760 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1762 /* We don't want one part of another group.
1763 We could get "two groups" that overlap! */
1764 && ! TEST_HARD_REG_BIT (counted_for_groups, other))
1766 (j < FIRST_PSEUDO_REGISTER - 1
1767 && (other = j + 1, spill_reg_order[other] >= 0)
1768 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1769 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1770 && HARD_REGNO_MODE_OK (j, group_mode[class])
1771 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1773 && ! TEST_HARD_REG_BIT (counted_for_groups,
1776 register enum reg_class *p;
1778 /* We have found one that will complete a group,
1779 so count off one group as provided. */
1780 max_groups[class]--;
1781 p = reg_class_superclasses[class];
1782 while (*p != LIM_REG_CLASSES)
1784 if (group_size [(int) *p] <= group_size [class])
1785 max_groups[(int) *p]--;
1789 /* Indicate both these regs are part of a group. */
1790 SET_HARD_REG_BIT (counted_for_groups, j);
1791 SET_HARD_REG_BIT (counted_for_groups, other);
1795 /* We can't complete a group, so start one. */
1796 #ifdef SMALL_REGISTER_CLASSES
1797 /* Look for a pair neither of which is explicitly used. */
1798 if (SMALL_REGISTER_CLASSES && i == FIRST_PSEUDO_REGISTER)
1799 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1802 j = potential_reload_regs[i];
1803 /* Verify that J+1 is a potential reload reg. */
1804 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1805 if (potential_reload_regs[k] == j + 1)
1807 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1808 && k < FIRST_PSEUDO_REGISTER
1809 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1810 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1811 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1812 && HARD_REGNO_MODE_OK (j, group_mode[class])
1813 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1815 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1)
1816 /* Reject J at this stage
1817 if J+1 was explicitly used. */
1818 && ! regs_explicitly_used[j + 1])
1822 /* Now try any group at all
1823 whose registers are not in bad_spill_regs. */
1824 if (i == FIRST_PSEUDO_REGISTER)
1825 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1828 j = potential_reload_regs[i];
1829 /* Verify that J+1 is a potential reload reg. */
1830 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1831 if (potential_reload_regs[k] == j + 1)
1833 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1834 && k < FIRST_PSEUDO_REGISTER
1835 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1836 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1837 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1838 && HARD_REGNO_MODE_OK (j, group_mode[class])
1839 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1841 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1))
1845 /* I should be the index in potential_reload_regs
1846 of the new reload reg we have found. */
1848 if (i >= FIRST_PSEUDO_REGISTER)
1850 /* There are no groups left to spill. */
1851 spill_failure (max_groups_insn[class]);
1857 |= new_spill_reg (i, class, max_needs, NULL_PTR,
1862 /* For groups of more than 2 registers,
1863 look for a sufficient sequence of unspilled registers,
1864 and spill them all at once. */
1865 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1869 j = potential_reload_regs[i];
1871 && j + group_size[class] <= FIRST_PSEUDO_REGISTER
1872 && HARD_REGNO_MODE_OK (j, group_mode[class]))
1874 /* Check each reg in the sequence. */
1875 for (k = 0; k < group_size[class]; k++)
1876 if (! (spill_reg_order[j + k] < 0
1877 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1878 && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1880 /* We got a full sequence, so spill them all. */
1881 if (k == group_size[class])
1883 register enum reg_class *p;
1884 for (k = 0; k < group_size[class]; k++)
1887 SET_HARD_REG_BIT (counted_for_groups, j + k);
1888 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1889 if (potential_reload_regs[idx] == j + k)
1892 |= new_spill_reg (idx, class,
1893 max_needs, NULL_PTR,
1897 /* We have found one that will complete a group,
1898 so count off one group as provided. */
1899 max_groups[class]--;
1900 p = reg_class_superclasses[class];
1901 while (*p != LIM_REG_CLASSES)
1903 if (group_size [(int) *p]
1904 <= group_size [class])
1905 max_groups[(int) *p]--;
1912 /* We couldn't find any registers for this reload.
1913 Avoid going into an infinite loop. */
1914 if (i >= FIRST_PSEUDO_REGISTER)
1916 /* There are no groups left. */
1917 spill_failure (max_groups_insn[class]);
1924 /* Now similarly satisfy all need for single registers. */
1926 while (max_needs[class] > 0 || max_nongroups[class] > 0)
1928 /* If we spilled enough regs, but they weren't counted
1929 against the non-group need, see if we can count them now.
1930 If so, we can avoid some actual spilling. */
1931 if (max_needs[class] <= 0 && max_nongroups[class] > 0)
1932 for (i = 0; i < n_spills; i++)
1933 if (TEST_HARD_REG_BIT (reg_class_contents[class],
1935 && !TEST_HARD_REG_BIT (counted_for_groups,
1937 && !TEST_HARD_REG_BIT (counted_for_nongroups,
1939 && max_nongroups[class] > 0)
1941 register enum reg_class *p;
1943 SET_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]);
1944 max_nongroups[class]--;
1945 p = reg_class_superclasses[class];
1946 while (*p != LIM_REG_CLASSES)
1947 max_nongroups[(int) *p++]--;
1949 if (max_needs[class] <= 0 && max_nongroups[class] <= 0)
1952 /* Consider the potential reload regs that aren't
1953 yet in use as reload regs, in order of preference.
1954 Find the most preferred one that's in this class. */
1956 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1957 if (potential_reload_regs[i] >= 0
1958 && TEST_HARD_REG_BIT (reg_class_contents[class],
1959 potential_reload_regs[i])
1960 /* If this reg will not be available for groups,
1961 pick one that does not foreclose possible groups.
1962 This is a kludge, and not very general,
1963 but it should be sufficient to make the 386 work,
1964 and the problem should not occur on machines with
1966 && (max_nongroups[class] == 0
1967 || possible_group_p (potential_reload_regs[i], max_groups)))
1970 /* If we couldn't get a register, try to get one even if we
1971 might foreclose possible groups. This may cause problems
1972 later, but that's better than aborting now, since it is
1973 possible that we will, in fact, be able to form the needed
1974 group even with this allocation. */
1976 if (i >= FIRST_PSEUDO_REGISTER
1977 && (asm_noperands (max_needs[class] > 0
1978 ? max_needs_insn[class]
1979 : max_nongroups_insn[class])
1981 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1982 if (potential_reload_regs[i] >= 0
1983 && TEST_HARD_REG_BIT (reg_class_contents[class],
1984 potential_reload_regs[i]))
1987 /* I should be the index in potential_reload_regs
1988 of the new reload reg we have found. */
1990 if (i >= FIRST_PSEUDO_REGISTER)
1992 /* There are no possible registers left to spill. */
1993 spill_failure (max_needs[class] > 0 ? max_needs_insn[class]
1994 : max_nongroups_insn[class]);
2000 |= new_spill_reg (i, class, max_needs, max_nongroups,
2006 /* If global-alloc was run, notify it of any register eliminations we have
2009 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2010 if (ep->can_eliminate)
2011 mark_elimination (ep->from, ep->to);
2013 /* Insert code to save and restore call-clobbered hard regs
2014 around calls. Tell if what mode to use so that we will process
2015 those insns in reload_as_needed if we have to. */
2017 if (caller_save_needed)
2018 save_call_clobbered_regs (num_eliminable ? QImode
2019 : caller_save_spill_class != NO_REGS ? HImode
2022 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
2023 If that insn didn't set the register (i.e., it copied the register to
2024 memory), just delete that insn instead of the equivalencing insn plus
2025 anything now dead. If we call delete_dead_insn on that insn, we may
2026 delete the insn that actually sets the register if the register die
2027 there and that is incorrect. */
2029 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2030 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0
2031 && GET_CODE (reg_equiv_init[i]) != NOTE)
2033 if (reg_set_p (regno_reg_rtx[i], PATTERN (reg_equiv_init[i])))
2034 delete_dead_insn (reg_equiv_init[i]);
2037 PUT_CODE (reg_equiv_init[i], NOTE);
2038 NOTE_SOURCE_FILE (reg_equiv_init[i]) = 0;
2039 NOTE_LINE_NUMBER (reg_equiv_init[i]) = NOTE_INSN_DELETED;
2043 /* Use the reload registers where necessary
2044 by generating move instructions to move the must-be-register
2045 values into or out of the reload registers. */
2047 if (something_needs_reloads || something_needs_elimination
2048 || (caller_save_needed && num_eliminable)
2049 || caller_save_spill_class != NO_REGS)
2050 reload_as_needed (first, global);
2052 /* If we were able to eliminate the frame pointer, show that it is no
2053 longer live at the start of any basic block. If it ls live by
2054 virtue of being in a pseudo, that pseudo will be marked live
2055 and hence the frame pointer will be known to be live via that
2058 if (! frame_pointer_needed)
2059 for (i = 0; i < n_basic_blocks; i++)
2060 basic_block_live_at_start[i][HARD_FRAME_POINTER_REGNUM / REGSET_ELT_BITS]
2061 &= ~ ((REGSET_ELT_TYPE) 1 << (HARD_FRAME_POINTER_REGNUM
2062 % REGSET_ELT_BITS));
2064 /* Come here (with failure set nonzero) if we can't get enough spill regs
2065 and we decide not to abort about it. */
2068 reload_in_progress = 0;
2070 /* Now eliminate all pseudo regs by modifying them into
2071 their equivalent memory references.
2072 The REG-rtx's for the pseudos are modified in place,
2073 so all insns that used to refer to them now refer to memory.
2075 For a reg that has a reg_equiv_address, all those insns
2076 were changed by reloading so that no insns refer to it any longer;
2077 but the DECL_RTL of a variable decl may refer to it,
2078 and if so this causes the debugging info to mention the variable. */
2080 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2084 if (reg_equiv_mem[i])
2086 addr = XEXP (reg_equiv_mem[i], 0);
2087 in_struct = MEM_IN_STRUCT_P (reg_equiv_mem[i]);
2089 if (reg_equiv_address[i])
2090 addr = reg_equiv_address[i];
2093 if (reg_renumber[i] < 0)
2095 rtx reg = regno_reg_rtx[i];
2096 XEXP (reg, 0) = addr;
2097 REG_USERVAR_P (reg) = 0;
2098 MEM_IN_STRUCT_P (reg) = in_struct;
2099 PUT_CODE (reg, MEM);
2101 else if (reg_equiv_mem[i])
2102 XEXP (reg_equiv_mem[i], 0) = addr;
2106 #ifdef PRESERVE_DEATH_INFO_REGNO_P
2107 /* Make a pass over all the insns and remove death notes for things that
2108 are no longer registers or no longer die in the insn (e.g., an input
2109 and output pseudo being tied). */
2111 for (insn = first; insn; insn = NEXT_INSN (insn))
2112 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
2116 for (note = REG_NOTES (insn); note; note = next)
2118 next = XEXP (note, 1);
2119 if (REG_NOTE_KIND (note) == REG_DEAD
2120 && (GET_CODE (XEXP (note, 0)) != REG
2121 || reg_set_p (XEXP (note, 0), PATTERN (insn))))
2122 remove_note (insn, note);
2127 /* Indicate that we no longer have known memory locations or constants. */
2128 reg_equiv_constant = 0;
2129 reg_equiv_memory_loc = 0;
2132 free (scratch_list);
2135 free (scratch_block);
2138 CLEAR_HARD_REG_SET (used_spill_regs);
2139 for (i = 0; i < n_spills; i++)
2140 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
2145 /* Nonzero if, after spilling reg REGNO for non-groups,
2146 it will still be possible to find a group if we still need one. */
2149 possible_group_p (regno, max_groups)
2154 int class = (int) NO_REGS;
2156 for (i = 0; i < (int) N_REG_CLASSES; i++)
2157 if (max_groups[i] > 0)
2163 if (class == (int) NO_REGS)
2166 /* Consider each pair of consecutive registers. */
2167 for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
2169 /* Ignore pairs that include reg REGNO. */
2170 if (i == regno || i + 1 == regno)
2173 /* Ignore pairs that are outside the class that needs the group.
2174 ??? Here we fail to handle the case where two different classes
2175 independently need groups. But this never happens with our
2176 current machine descriptions. */
2177 if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
2178 && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
2181 /* A pair of consecutive regs we can still spill does the trick. */
2182 if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
2183 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2184 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
2187 /* A pair of one already spilled and one we can spill does it
2188 provided the one already spilled is not otherwise reserved. */
2189 if (spill_reg_order[i] < 0
2190 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2191 && spill_reg_order[i + 1] >= 0
2192 && ! TEST_HARD_REG_BIT (counted_for_groups, i + 1)
2193 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i + 1))
2195 if (spill_reg_order[i + 1] < 0
2196 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
2197 && spill_reg_order[i] >= 0
2198 && ! TEST_HARD_REG_BIT (counted_for_groups, i)
2199 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i))
2206 /* Count any groups of CLASS that can be formed from the registers recently
2210 count_possible_groups (group_size, group_mode, max_groups, class)
2212 enum machine_mode *group_mode;
2219 /* Now find all consecutive groups of spilled registers
2220 and mark each group off against the need for such groups.
2221 But don't count them against ordinary need, yet. */
2223 if (group_size[class] == 0)
2226 CLEAR_HARD_REG_SET (new);
2228 /* Make a mask of all the regs that are spill regs in class I. */
2229 for (i = 0; i < n_spills; i++)
2230 if (TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i])
2231 && ! TEST_HARD_REG_BIT (counted_for_groups, spill_regs[i])
2232 && ! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
2233 SET_HARD_REG_BIT (new, spill_regs[i]);
2235 /* Find each consecutive group of them. */
2236 for (i = 0; i < FIRST_PSEUDO_REGISTER && max_groups[class] > 0; i++)
2237 if (TEST_HARD_REG_BIT (new, i)
2238 && i + group_size[class] <= FIRST_PSEUDO_REGISTER
2239 && HARD_REGNO_MODE_OK (i, group_mode[class]))
2241 for (j = 1; j < group_size[class]; j++)
2242 if (! TEST_HARD_REG_BIT (new, i + j))
2245 if (j == group_size[class])
2247 /* We found a group. Mark it off against this class's need for
2248 groups, and against each superclass too. */
2249 register enum reg_class *p;
2251 max_groups[class]--;
2252 p = reg_class_superclasses[class];
2253 while (*p != LIM_REG_CLASSES)
2255 if (group_size [(int) *p] <= group_size [class])
2256 max_groups[(int) *p]--;
2260 /* Don't count these registers again. */
2261 for (j = 0; j < group_size[class]; j++)
2262 SET_HARD_REG_BIT (counted_for_groups, i + j);
2265 /* Skip to the last reg in this group. When i is incremented above,
2266 it will then point to the first reg of the next possible group. */
2271 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2272 another mode that needs to be reloaded for the same register class CLASS.
2273 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2274 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2276 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2277 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2278 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2279 causes unnecessary failures on machines requiring alignment of register
2280 groups when the two modes are different sizes, because the larger mode has
2281 more strict alignment rules than the smaller mode. */
2284 modes_equiv_for_class_p (allocate_mode, other_mode, class)
2285 enum machine_mode allocate_mode, other_mode;
2286 enum reg_class class;
2289 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2291 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
2292 && HARD_REGNO_MODE_OK (regno, allocate_mode)
2293 && ! HARD_REGNO_MODE_OK (regno, other_mode))
2299 /* Handle the failure to find a register to spill.
2300 INSN should be one of the insns which needed this particular spill reg. */
2303 spill_failure (insn)
2306 if (asm_noperands (PATTERN (insn)) >= 0)
2307 error_for_asm (insn, "`asm' needs too many reloads");
2309 fatal_insn ("Unable to find a register to spill.", insn);
2312 /* Add a new register to the tables of available spill-registers
2313 (as well as spilling all pseudos allocated to the register).
2314 I is the index of this register in potential_reload_regs.
2315 CLASS is the regclass whose need is being satisfied.
2316 MAX_NEEDS and MAX_NONGROUPS are the vectors of needs,
2317 so that this register can count off against them.
2318 MAX_NONGROUPS is 0 if this register is part of a group.
2319 GLOBAL and DUMPFILE are the same as the args that `reload' got. */
2322 new_spill_reg (i, class, max_needs, max_nongroups, global, dumpfile)
2330 register enum reg_class *p;
2332 int regno = potential_reload_regs[i];
2334 if (i >= FIRST_PSEUDO_REGISTER)
2335 abort (); /* Caller failed to find any register. */
2337 if (fixed_regs[regno] || TEST_HARD_REG_BIT (forbidden_regs, regno))
2338 fatal ("fixed or forbidden register was spilled.\n\
2339 This may be due to a compiler bug or to impossible asm\n\
2340 statements or clauses.");
2342 /* Make reg REGNO an additional reload reg. */
2344 potential_reload_regs[i] = -1;
2345 spill_regs[n_spills] = regno;
2346 spill_reg_order[regno] = n_spills;
2348 fprintf (dumpfile, "Spilling reg %d.\n", spill_regs[n_spills]);
2350 /* Clear off the needs we just satisfied. */
2353 p = reg_class_superclasses[class];
2354 while (*p != LIM_REG_CLASSES)
2355 max_needs[(int) *p++]--;
2357 if (max_nongroups && max_nongroups[class] > 0)
2359 SET_HARD_REG_BIT (counted_for_nongroups, regno);
2360 max_nongroups[class]--;
2361 p = reg_class_superclasses[class];
2362 while (*p != LIM_REG_CLASSES)
2363 max_nongroups[(int) *p++]--;
2366 /* Spill every pseudo reg that was allocated to this reg
2367 or to something that overlaps this reg. */
2369 val = spill_hard_reg (spill_regs[n_spills], global, dumpfile, 0);
2371 /* If there are some registers still to eliminate and this register
2372 wasn't ever used before, additional stack space may have to be
2373 allocated to store this register. Thus, we may have changed the offset
2374 between the stack and frame pointers, so mark that something has changed.
2375 (If new pseudos were spilled, thus requiring more space, VAL would have
2376 been set non-zero by the call to spill_hard_reg above since additional
2377 reloads may be needed in that case.
2379 One might think that we need only set VAL to 1 if this is a call-used
2380 register. However, the set of registers that must be saved by the
2381 prologue is not identical to the call-used set. For example, the
2382 register used by the call insn for the return PC is a call-used register,
2383 but must be saved by the prologue. */
2384 if (num_eliminable && ! regs_ever_live[spill_regs[n_spills]])
2387 regs_ever_live[spill_regs[n_spills]] = 1;
2393 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2394 data that is dead in INSN. */
2397 delete_dead_insn (insn)
2400 rtx prev = prev_real_insn (insn);
2403 /* If the previous insn sets a register that dies in our insn, delete it
2405 if (prev && GET_CODE (PATTERN (prev)) == SET
2406 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
2407 && reg_mentioned_p (prev_dest, PATTERN (insn))
2408 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)))
2409 delete_dead_insn (prev);
2411 PUT_CODE (insn, NOTE);
2412 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2413 NOTE_SOURCE_FILE (insn) = 0;
2416 /* Modify the home of pseudo-reg I.
2417 The new home is present in reg_renumber[I].
2419 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2420 or it may be -1, meaning there is none or it is not relevant.
2421 This is used so that all pseudos spilled from a given hard reg
2422 can share one stack slot. */
2425 alter_reg (i, from_reg)
2429 /* When outputting an inline function, this can happen
2430 for a reg that isn't actually used. */
2431 if (regno_reg_rtx[i] == 0)
2434 /* If the reg got changed to a MEM at rtl-generation time,
2436 if (GET_CODE (regno_reg_rtx[i]) != REG)
2439 /* Modify the reg-rtx to contain the new hard reg
2440 number or else to contain its pseudo reg number. */
2441 REGNO (regno_reg_rtx[i])
2442 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2444 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2445 allocate a stack slot for it. */
2447 if (reg_renumber[i] < 0
2448 && reg_n_refs[i] > 0
2449 && reg_equiv_constant[i] == 0
2450 && reg_equiv_memory_loc[i] == 0)
2453 int inherent_size = PSEUDO_REGNO_BYTES (i);
2454 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2457 /* Each pseudo reg has an inherent size which comes from its own mode,
2458 and a total size which provides room for paradoxical subregs
2459 which refer to the pseudo reg in wider modes.
2461 We can use a slot already allocated if it provides both
2462 enough inherent space and enough total space.
2463 Otherwise, we allocate a new slot, making sure that it has no less
2464 inherent space, and no less total space, then the previous slot. */
2467 /* No known place to spill from => no slot to reuse. */
2468 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
2469 inherent_size == total_size ? 0 : -1);
2470 if (BYTES_BIG_ENDIAN)
2471 /* Cancel the big-endian correction done in assign_stack_local.
2472 Get the address of the beginning of the slot.
2473 This is so we can do a big-endian correction unconditionally
2475 adjust = inherent_size - total_size;
2477 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2479 /* Reuse a stack slot if possible. */
2480 else if (spill_stack_slot[from_reg] != 0
2481 && spill_stack_slot_width[from_reg] >= total_size
2482 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2484 x = spill_stack_slot[from_reg];
2485 /* Allocate a bigger slot. */
2488 /* Compute maximum size needed, both for inherent size
2489 and for total size. */
2490 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2492 if (spill_stack_slot[from_reg])
2494 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2496 mode = GET_MODE (spill_stack_slot[from_reg]);
2497 if (spill_stack_slot_width[from_reg] > total_size)
2498 total_size = spill_stack_slot_width[from_reg];
2500 /* Make a slot with that size. */
2501 x = assign_stack_local (mode, total_size,
2502 inherent_size == total_size ? 0 : -1);
2504 if (BYTES_BIG_ENDIAN)
2506 /* Cancel the big-endian correction done in assign_stack_local.
2507 Get the address of the beginning of the slot.
2508 This is so we can do a big-endian correction unconditionally
2510 adjust = GET_MODE_SIZE (mode) - total_size;
2512 stack_slot = gen_rtx (MEM, mode_for_size (total_size
2515 plus_constant (XEXP (x, 0), adjust));
2517 spill_stack_slot[from_reg] = stack_slot;
2518 spill_stack_slot_width[from_reg] = total_size;
2521 /* On a big endian machine, the "address" of the slot
2522 is the address of the low part that fits its inherent mode. */
2523 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2524 adjust += (total_size - inherent_size);
2526 /* If we have any adjustment to make, or if the stack slot is the
2527 wrong mode, make a new stack slot. */
2528 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2530 x = gen_rtx (MEM, GET_MODE (regno_reg_rtx[i]),
2531 plus_constant (XEXP (x, 0), adjust));
2532 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2535 /* Save the stack slot for later. */
2536 reg_equiv_memory_loc[i] = x;
2540 /* Mark the slots in regs_ever_live for the hard regs
2541 used by pseudo-reg number REGNO. */
2544 mark_home_live (regno)
2547 register int i, lim;
2548 i = reg_renumber[regno];
2551 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2553 regs_ever_live[i++] = 1;
2556 /* Mark the registers used in SCRATCH as being live. */
2559 mark_scratch_live (scratch)
2563 int regno = REGNO (scratch);
2564 int lim = regno + HARD_REGNO_NREGS (regno, GET_MODE (scratch));
2566 for (i = regno; i < lim; i++)
2567 regs_ever_live[i] = 1;
2570 /* This function handles the tracking of elimination offsets around branches.
2572 X is a piece of RTL being scanned.
2574 INSN is the insn that it came from, if any.
2576 INITIAL_P is non-zero if we are to set the offset to be the initial
2577 offset and zero if we are setting the offset of the label to be the
2581 set_label_offsets (x, insn, initial_p)
2586 enum rtx_code code = GET_CODE (x);
2589 struct elim_table *p;
2594 if (LABEL_REF_NONLOCAL_P (x))
2599 /* ... fall through ... */
2602 /* If we know nothing about this label, set the desired offsets. Note
2603 that this sets the offset at a label to be the offset before a label
2604 if we don't know anything about the label. This is not correct for
2605 the label after a BARRIER, but is the best guess we can make. If
2606 we guessed wrong, we will suppress an elimination that might have
2607 been possible had we been able to guess correctly. */
2609 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2611 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2612 offsets_at[CODE_LABEL_NUMBER (x)][i]
2613 = (initial_p ? reg_eliminate[i].initial_offset
2614 : reg_eliminate[i].offset);
2615 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2618 /* Otherwise, if this is the definition of a label and it is
2619 preceded by a BARRIER, set our offsets to the known offset of
2623 && (tem = prev_nonnote_insn (insn)) != 0
2624 && GET_CODE (tem) == BARRIER)
2626 num_not_at_initial_offset = 0;
2627 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2629 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
2630 = offsets_at[CODE_LABEL_NUMBER (x)][i];
2631 if (reg_eliminate[i].can_eliminate
2632 && (reg_eliminate[i].offset
2633 != reg_eliminate[i].initial_offset))
2634 num_not_at_initial_offset++;
2639 /* If neither of the above cases is true, compare each offset
2640 with those previously recorded and suppress any eliminations
2641 where the offsets disagree. */
2643 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2644 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2645 != (initial_p ? reg_eliminate[i].initial_offset
2646 : reg_eliminate[i].offset))
2647 reg_eliminate[i].can_eliminate = 0;
2652 set_label_offsets (PATTERN (insn), insn, initial_p);
2654 /* ... fall through ... */
2658 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2659 and hence must have all eliminations at their initial offsets. */
2660 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2661 if (REG_NOTE_KIND (tem) == REG_LABEL)
2662 set_label_offsets (XEXP (tem, 0), insn, 1);
2667 /* Each of the labels in the address vector must be at their initial
2668 offsets. We want the first first for ADDR_VEC and the second
2669 field for ADDR_DIFF_VEC. */
2671 for (i = 0; i < XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2672 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2677 /* We only care about setting PC. If the source is not RETURN,
2678 IF_THEN_ELSE, or a label, disable any eliminations not at
2679 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2680 isn't one of those possibilities. For branches to a label,
2681 call ourselves recursively.
2683 Note that this can disable elimination unnecessarily when we have
2684 a non-local goto since it will look like a non-constant jump to
2685 someplace in the current function. This isn't a significant
2686 problem since such jumps will normally be when all elimination
2687 pairs are back to their initial offsets. */
2689 if (SET_DEST (x) != pc_rtx)
2692 switch (GET_CODE (SET_SRC (x)))
2699 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2703 tem = XEXP (SET_SRC (x), 1);
2704 if (GET_CODE (tem) == LABEL_REF)
2705 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2706 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2709 tem = XEXP (SET_SRC (x), 2);
2710 if (GET_CODE (tem) == LABEL_REF)
2711 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2712 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2717 /* If we reach here, all eliminations must be at their initial
2718 offset because we are doing a jump to a variable address. */
2719 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2720 if (p->offset != p->initial_offset)
2721 p->can_eliminate = 0;
2725 /* Used for communication between the next two function to properly share
2726 the vector for an ASM_OPERANDS. */
2728 static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec;
2730 /* Scan X and replace any eliminable registers (such as fp) with a
2731 replacement (such as sp), plus an offset.
2733 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2734 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2735 MEM, we are allowed to replace a sum of a register and the constant zero
2736 with the register, which we cannot do outside a MEM. In addition, we need
2737 to record the fact that a register is referenced outside a MEM.
2739 If INSN is an insn, it is the insn containing X. If we replace a REG
2740 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2741 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2742 that the REG is being modified.
2744 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2745 That's used when we eliminate in expressions stored in notes.
2746 This means, do not set ref_outside_mem even if the reference
2749 If we see a modification to a register we know about, take the
2750 appropriate action (see case SET, below).
2752 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2753 replacements done assuming all offsets are at their initial values. If
2754 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2755 encounter, return the actual location so that find_reloads will do
2756 the proper thing. */
2759 eliminate_regs (x, mem_mode, insn)
2761 enum machine_mode mem_mode;
2764 enum rtx_code code = GET_CODE (x);
2765 struct elim_table *ep;
2790 /* First handle the case where we encounter a bare register that
2791 is eliminable. Replace it with a PLUS. */
2792 if (regno < FIRST_PSEUDO_REGISTER)
2794 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2796 if (ep->from_rtx == x && ep->can_eliminate)
2799 /* Refs inside notes don't count for this purpose. */
2800 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2801 || GET_CODE (insn) == INSN_LIST)))
2802 ep->ref_outside_mem = 1;
2803 return plus_constant (ep->to_rtx, ep->previous_offset);
2807 else if (reg_equiv_memory_loc && reg_equiv_memory_loc[regno]
2808 && (reg_equiv_address[regno] || num_not_at_initial_offset))
2810 /* In this case, find_reloads would attempt to either use an
2811 incorrect address (if something is not at its initial offset)
2812 or substitute an replaced address into an insn (which loses
2813 if the offset is changed by some later action). So we simply
2814 return the replaced stack slot (assuming it is changed by
2815 elimination) and ignore the fact that this is actually a
2816 reference to the pseudo. Ensure we make a copy of the
2817 address in case it is shared. */
2818 new = eliminate_regs (reg_equiv_memory_loc[regno],
2820 if (new != reg_equiv_memory_loc[regno])
2822 cannot_omit_stores[regno] = 1;
2823 return copy_rtx (new);
2829 /* If this is the sum of an eliminable register and a constant, rework
2831 if (GET_CODE (XEXP (x, 0)) == REG
2832 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2833 && CONSTANT_P (XEXP (x, 1)))
2835 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2837 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2840 /* Refs inside notes don't count for this purpose. */
2841 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2842 || GET_CODE (insn) == INSN_LIST)))
2843 ep->ref_outside_mem = 1;
2845 /* The only time we want to replace a PLUS with a REG (this
2846 occurs when the constant operand of the PLUS is the negative
2847 of the offset) is when we are inside a MEM. We won't want
2848 to do so at other times because that would change the
2849 structure of the insn in a way that reload can't handle.
2850 We special-case the commonest situation in
2851 eliminate_regs_in_insn, so just replace a PLUS with a
2852 PLUS here, unless inside a MEM. */
2853 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2854 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2857 return gen_rtx (PLUS, Pmode, ep->to_rtx,
2858 plus_constant (XEXP (x, 1),
2859 ep->previous_offset));
2862 /* If the register is not eliminable, we are done since the other
2863 operand is a constant. */
2867 /* If this is part of an address, we want to bring any constant to the
2868 outermost PLUS. We will do this by doing register replacement in
2869 our operands and seeing if a constant shows up in one of them.
2871 We assume here this is part of an address (or a "load address" insn)
2872 since an eliminable register is not likely to appear in any other
2875 If we have (plus (eliminable) (reg)), we want to produce
2876 (plus (plus (replacement) (reg) (const))). If this was part of a
2877 normal add insn, (plus (replacement) (reg)) will be pushed as a
2878 reload. This is the desired action. */
2881 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2882 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2884 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2886 /* If one side is a PLUS and the other side is a pseudo that
2887 didn't get a hard register but has a reg_equiv_constant,
2888 we must replace the constant here since it may no longer
2889 be in the position of any operand. */
2890 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2891 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2892 && reg_renumber[REGNO (new1)] < 0
2893 && reg_equiv_constant != 0
2894 && reg_equiv_constant[REGNO (new1)] != 0)
2895 new1 = reg_equiv_constant[REGNO (new1)];
2896 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2897 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2898 && reg_renumber[REGNO (new0)] < 0
2899 && reg_equiv_constant[REGNO (new0)] != 0)
2900 new0 = reg_equiv_constant[REGNO (new0)];
2902 new = form_sum (new0, new1);
2904 /* As above, if we are not inside a MEM we do not want to
2905 turn a PLUS into something else. We might try to do so here
2906 for an addition of 0 if we aren't optimizing. */
2907 if (! mem_mode && GET_CODE (new) != PLUS)
2908 return gen_rtx (PLUS, GET_MODE (x), new, const0_rtx);
2916 /* If this is the product of an eliminable register and a
2917 constant, apply the distribute law and move the constant out
2918 so that we have (plus (mult ..) ..). This is needed in order
2919 to keep load-address insns valid. This case is pathological.
2920 We ignore the possibility of overflow here. */
2921 if (GET_CODE (XEXP (x, 0)) == REG
2922 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2923 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2924 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2926 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2929 /* Refs inside notes don't count for this purpose. */
2930 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2931 || GET_CODE (insn) == INSN_LIST)))
2932 ep->ref_outside_mem = 1;
2935 plus_constant (gen_rtx (MULT, Pmode, ep->to_rtx, XEXP (x, 1)),
2936 ep->previous_offset * INTVAL (XEXP (x, 1)));
2939 /* ... fall through ... */
2944 case DIV: case UDIV:
2945 case MOD: case UMOD:
2946 case AND: case IOR: case XOR:
2947 case ROTATERT: case ROTATE:
2948 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2950 case GE: case GT: case GEU: case GTU:
2951 case LE: case LT: case LEU: case LTU:
2953 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2955 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2957 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2958 return gen_rtx (code, GET_MODE (x), new0, new1);
2963 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2966 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2967 if (new != XEXP (x, 0))
2968 x = gen_rtx (EXPR_LIST, REG_NOTE_KIND (x), new, XEXP (x, 1));
2971 /* ... fall through ... */
2974 /* Now do eliminations in the rest of the chain. If this was
2975 an EXPR_LIST, this might result in allocating more memory than is
2976 strictly needed, but it simplifies the code. */
2979 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2980 if (new != XEXP (x, 1))
2981 return gen_rtx (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2989 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2990 if (ep->to_rtx == XEXP (x, 0))
2992 int size = GET_MODE_SIZE (mem_mode);
2994 /* If more bytes than MEM_MODE are pushed, account for them. */
2995 #ifdef PUSH_ROUNDING
2996 if (ep->to_rtx == stack_pointer_rtx)
2997 size = PUSH_ROUNDING (size);
2999 if (code == PRE_DEC || code == POST_DEC)
3005 /* Fall through to generic unary operation case. */
3006 case STRICT_LOW_PART:
3008 case SIGN_EXTEND: case ZERO_EXTEND:
3009 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3010 case FLOAT: case FIX:
3011 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3015 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3016 if (new != XEXP (x, 0))
3017 return gen_rtx (code, GET_MODE (x), new);
3021 /* Similar to above processing, but preserve SUBREG_WORD.
3022 Convert (subreg (mem)) to (mem) if not paradoxical.
3023 Also, if we have a non-paradoxical (subreg (pseudo)) and the
3024 pseudo didn't get a hard reg, we must replace this with the
3025 eliminated version of the memory location because push_reloads
3026 may do the replacement in certain circumstances. */
3027 if (GET_CODE (SUBREG_REG (x)) == REG
3028 && (GET_MODE_SIZE (GET_MODE (x))
3029 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3030 && reg_equiv_memory_loc != 0
3031 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
3033 new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))],
3036 /* If we didn't change anything, we must retain the pseudo. */
3037 if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))])
3038 new = SUBREG_REG (x);
3041 /* Otherwise, ensure NEW isn't shared in case we have to reload
3043 new = copy_rtx (new);
3045 /* In this case, we must show that the pseudo is used in this
3046 insn so that delete_output_reload will do the right thing. */
3047 if (insn != 0 && GET_CODE (insn) != EXPR_LIST
3048 && GET_CODE (insn) != INSN_LIST)
3049 emit_insn_before (gen_rtx (USE, VOIDmode, SUBREG_REG (x)),
3054 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
3056 if (new != XEXP (x, 0))
3058 if (GET_CODE (new) == MEM
3059 && (GET_MODE_SIZE (GET_MODE (x))
3060 <= GET_MODE_SIZE (GET_MODE (new)))
3061 #ifdef LOAD_EXTEND_OP
3062 /* On these machines we will be reloading what is
3063 inside the SUBREG if it originally was a pseudo and
3064 the inner and outer modes are both a word or
3065 smaller. So leave the SUBREG then. */
3066 && ! (GET_CODE (SUBREG_REG (x)) == REG
3067 && GET_MODE_SIZE (GET_MODE (x)) <= UNITS_PER_WORD
3068 && GET_MODE_SIZE (GET_MODE (new)) <= UNITS_PER_WORD
3069 && (GET_MODE_SIZE (GET_MODE (x))
3070 > GET_MODE_SIZE (GET_MODE (new)))
3071 && INTEGRAL_MODE_P (GET_MODE (new))
3072 && LOAD_EXTEND_OP (GET_MODE (new)) != NIL)
3076 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
3077 enum machine_mode mode = GET_MODE (x);
3079 if (BYTES_BIG_ENDIAN)
3080 offset += (MIN (UNITS_PER_WORD,
3081 GET_MODE_SIZE (GET_MODE (new)))
3082 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
3084 PUT_MODE (new, mode);
3085 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
3089 return gen_rtx (SUBREG, GET_MODE (x), new, SUBREG_WORD (x));
3095 /* If using a register that is the source of an eliminate we still
3096 think can be performed, note it cannot be performed since we don't
3097 know how this register is used. */
3098 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3099 if (ep->from_rtx == XEXP (x, 0))
3100 ep->can_eliminate = 0;
3102 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3103 if (new != XEXP (x, 0))
3104 return gen_rtx (code, GET_MODE (x), new);
3108 /* If clobbering a register that is the replacement register for an
3109 elimination we still think can be performed, note that it cannot
3110 be performed. Otherwise, we need not be concerned about it. */
3111 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3112 if (ep->to_rtx == XEXP (x, 0))
3113 ep->can_eliminate = 0;
3115 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3116 if (new != XEXP (x, 0))
3117 return gen_rtx (code, GET_MODE (x), new);
3123 /* Properly handle sharing input and constraint vectors. */
3124 if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec)
3126 /* When we come to a new vector not seen before,
3127 scan all its elements; keep the old vector if none
3128 of them changes; otherwise, make a copy. */
3129 old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x);
3130 temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx));
3131 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3132 temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i),
3135 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3136 if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i))
3139 if (i == ASM_OPERANDS_INPUT_LENGTH (x))
3140 new_asm_operands_vec = old_asm_operands_vec;
3142 new_asm_operands_vec
3143 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec);
3146 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
3147 if (new_asm_operands_vec == old_asm_operands_vec)
3150 new = gen_rtx (ASM_OPERANDS, VOIDmode, ASM_OPERANDS_TEMPLATE (x),
3151 ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
3152 ASM_OPERANDS_OUTPUT_IDX (x), new_asm_operands_vec,
3153 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x),
3154 ASM_OPERANDS_SOURCE_FILE (x),
3155 ASM_OPERANDS_SOURCE_LINE (x));
3156 new->volatil = x->volatil;
3161 /* Check for setting a register that we know about. */
3162 if (GET_CODE (SET_DEST (x)) == REG)
3164 /* See if this is setting the replacement register for an
3167 If DEST is the hard frame pointer, we do nothing because we
3168 assume that all assignments to the frame pointer are for
3169 non-local gotos and are being done at a time when they are valid
3170 and do not disturb anything else. Some machines want to
3171 eliminate a fake argument pointer (or even a fake frame pointer)
3172 with either the real frame or the stack pointer. Assignments to
3173 the hard frame pointer must not prevent this elimination. */
3175 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3177 if (ep->to_rtx == SET_DEST (x)
3178 && SET_DEST (x) != hard_frame_pointer_rtx)
3180 /* If it is being incremented, adjust the offset. Otherwise,
3181 this elimination can't be done. */
3182 rtx src = SET_SRC (x);
3184 if (GET_CODE (src) == PLUS
3185 && XEXP (src, 0) == SET_DEST (x)
3186 && GET_CODE (XEXP (src, 1)) == CONST_INT)
3187 ep->offset -= INTVAL (XEXP (src, 1));
3189 ep->can_eliminate = 0;
3192 /* Now check to see we are assigning to a register that can be
3193 eliminated. If so, it must be as part of a PARALLEL, since we
3194 will not have been called if this is a single SET. So indicate
3195 that we can no longer eliminate this reg. */
3196 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3198 if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate)
3199 ep->can_eliminate = 0;
3202 /* Now avoid the loop below in this common case. */
3204 rtx new0 = eliminate_regs (SET_DEST (x), 0, insn);
3205 rtx new1 = eliminate_regs (SET_SRC (x), 0, insn);
3207 /* If SET_DEST changed from a REG to a MEM and INSN is an insn,
3208 write a CLOBBER insn. */
3209 if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM
3210 && insn != 0 && GET_CODE (insn) != EXPR_LIST
3211 && GET_CODE (insn) != INSN_LIST)
3212 emit_insn_after (gen_rtx (CLOBBER, VOIDmode, SET_DEST (x)), insn);
3214 if (new0 != SET_DEST (x) || new1 != SET_SRC (x))
3215 return gen_rtx (SET, VOIDmode, new0, new1);
3221 /* Our only special processing is to pass the mode of the MEM to our
3222 recursive call and copy the flags. While we are here, handle this
3223 case more efficiently. */
3224 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
3225 if (new != XEXP (x, 0))
3227 new = gen_rtx (MEM, GET_MODE (x), new);
3228 new->volatil = x->volatil;
3229 new->unchanging = x->unchanging;
3230 new->in_struct = x->in_struct;
3237 /* Process each of our operands recursively. If any have changed, make a
3239 fmt = GET_RTX_FORMAT (code);
3240 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3244 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
3245 if (new != XEXP (x, i) && ! copied)
3247 rtx new_x = rtx_alloc (code);
3248 bcopy ((char *) x, (char *) new_x,
3249 (sizeof (*new_x) - sizeof (new_x->fld)
3250 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
3256 else if (*fmt == 'E')
3259 for (j = 0; j < XVECLEN (x, i); j++)
3261 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
3262 if (new != XVECEXP (x, i, j) && ! copied_vec)
3264 rtvec new_v = gen_rtvec_vv (XVECLEN (x, i),
3268 rtx new_x = rtx_alloc (code);
3269 bcopy ((char *) x, (char *) new_x,
3270 (sizeof (*new_x) - sizeof (new_x->fld)
3271 + (sizeof (new_x->fld[0])
3272 * GET_RTX_LENGTH (code))));
3276 XVEC (x, i) = new_v;
3279 XVECEXP (x, i, j) = new;
3287 /* Scan INSN and eliminate all eliminable registers in it.
3289 If REPLACE is nonzero, do the replacement destructively. Also
3290 delete the insn as dead it if it is setting an eliminable register.
3292 If REPLACE is zero, do all our allocations in reload_obstack.
3294 If no eliminations were done and this insn doesn't require any elimination
3295 processing (these are not identical conditions: it might be updating sp,
3296 but not referencing fp; this needs to be seen during reload_as_needed so
3297 that the offset between fp and sp can be taken into consideration), zero
3298 is returned. Otherwise, 1 is returned. */
3301 eliminate_regs_in_insn (insn, replace)
3305 rtx old_body = PATTERN (insn);
3306 rtx old_set = single_set (insn);
3309 struct elim_table *ep;
3312 push_obstacks (&reload_obstack, &reload_obstack);
3314 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
3315 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3317 /* Check for setting an eliminable register. */
3318 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3319 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3321 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3322 /* If this is setting the frame pointer register to the
3323 hardware frame pointer register and this is an elimination
3324 that will be done (tested above), this insn is really
3325 adjusting the frame pointer downward to compensate for
3326 the adjustment done before a nonlocal goto. */
3327 if (ep->from == FRAME_POINTER_REGNUM
3328 && ep->to == HARD_FRAME_POINTER_REGNUM)
3330 rtx src = SET_SRC (old_set);
3332 rtx prev_insn, prev_set;
3334 if (src == ep->to_rtx)
3336 else if (GET_CODE (src) == PLUS
3337 && GET_CODE (XEXP (src, 0)) == CONST_INT)
3338 offset = INTVAL (XEXP (src, 0)), ok = 1;
3339 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
3340 && (prev_set = single_set (prev_insn)) != 0
3341 && rtx_equal_p (SET_DEST (prev_set), src))
3343 src = SET_SRC (prev_set);
3344 if (src == ep->to_rtx)
3346 else if (GET_CODE (src) == PLUS
3347 && GET_CODE (XEXP (src, 0)) == CONST_INT
3348 && XEXP (src, 1) == ep->to_rtx)
3349 offset = INTVAL (XEXP (src, 0)), ok = 1;
3350 else if (GET_CODE (src) == PLUS
3351 && GET_CODE (XEXP (src, 1)) == CONST_INT
3352 && XEXP (src, 0) == ep->to_rtx)
3353 offset = INTVAL (XEXP (src, 1)), ok = 1;
3361 = plus_constant (ep->to_rtx, offset - ep->offset);
3363 /* First see if this insn remains valid when we
3364 make the change. If not, keep the INSN_CODE
3365 the same and let reload fit it up. */
3366 validate_change (insn, &SET_SRC (old_set), src, 1);
3367 validate_change (insn, &SET_DEST (old_set),
3369 if (! apply_change_group ())
3371 SET_SRC (old_set) = src;
3372 SET_DEST (old_set) = ep->to_rtx;
3382 /* In this case this insn isn't serving a useful purpose. We
3383 will delete it in reload_as_needed once we know that this
3384 elimination is, in fact, being done.
3386 If REPLACE isn't set, we can't delete this insn, but needn't
3387 process it since it won't be used unless something changes. */
3389 delete_dead_insn (insn);
3394 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3395 in the insn is the negative of the offset in FROM. Substitute
3396 (set (reg) (reg to)) for the insn and change its code.
3398 We have to do this here, rather than in eliminate_regs, do that we can
3399 change the insn code. */
3401 if (GET_CODE (SET_SRC (old_set)) == PLUS
3402 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3403 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT)
3404 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3406 if (ep->from_rtx == XEXP (SET_SRC (old_set), 0)
3407 && ep->can_eliminate)
3409 /* We must stop at the first elimination that will be used.
3410 If this one would replace the PLUS with a REG, do it
3411 now. Otherwise, quit the loop and let eliminate_regs
3412 do its normal replacement. */
3413 if (ep->offset == - INTVAL (XEXP (SET_SRC (old_set), 1)))
3415 /* We assume here that we don't need a PARALLEL of
3416 any CLOBBERs for this assignment. There's not
3417 much we can do if we do need it. */
3418 PATTERN (insn) = gen_rtx (SET, VOIDmode,
3419 SET_DEST (old_set), ep->to_rtx);
3420 INSN_CODE (insn) = -1;
3429 old_asm_operands_vec = 0;
3431 /* Replace the body of this insn with a substituted form. If we changed
3432 something, return non-zero.
3434 If we are replacing a body that was a (set X (plus Y Z)), try to
3435 re-recognize the insn. We do this in case we had a simple addition
3436 but now can do this as a load-address. This saves an insn in this
3439 new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX);
3440 if (new_body != old_body)
3442 /* If we aren't replacing things permanently and we changed something,
3443 make another copy to ensure that all the RTL is new. Otherwise
3444 things can go wrong if find_reload swaps commutative operands
3445 and one is inside RTL that has been copied while the other is not. */
3447 /* Don't copy an asm_operands because (1) there's no need and (2)
3448 copy_rtx can't do it properly when there are multiple outputs. */
3449 if (! replace && asm_noperands (old_body) < 0)
3450 new_body = copy_rtx (new_body);
3452 /* If we had a move insn but now we don't, rerecognize it. This will
3453 cause spurious re-recognition if the old move had a PARALLEL since
3454 the new one still will, but we can't call single_set without
3455 having put NEW_BODY into the insn and the re-recognition won't
3456 hurt in this rare case. */
3458 && ((GET_CODE (SET_SRC (old_set)) == REG
3459 && (GET_CODE (new_body) != SET
3460 || GET_CODE (SET_SRC (new_body)) != REG))
3461 /* If this was a load from or store to memory, compare
3462 the MEM in recog_operand to the one in the insn. If they
3463 are not equal, then rerecognize the insn. */
3465 && ((GET_CODE (SET_SRC (old_set)) == MEM
3466 && SET_SRC (old_set) != recog_operand[1])
3467 || (GET_CODE (SET_DEST (old_set)) == MEM
3468 && SET_DEST (old_set) != recog_operand[0])))
3469 /* If this was an add insn before, rerecognize. */
3470 || GET_CODE (SET_SRC (old_set)) == PLUS))
3472 if (! validate_change (insn, &PATTERN (insn), new_body, 0))
3473 /* If recognition fails, store the new body anyway.
3474 It's normal to have recognition failures here
3475 due to bizarre memory addresses; reloading will fix them. */
3476 PATTERN (insn) = new_body;
3479 PATTERN (insn) = new_body;
3484 /* Loop through all elimination pairs. See if any have changed and
3485 recalculate the number not at initial offset.
3487 Compute the maximum offset (minimum offset if the stack does not
3488 grow downward) for each elimination pair.
3490 We also detect a cases where register elimination cannot be done,
3491 namely, if a register would be both changed and referenced outside a MEM
3492 in the resulting insn since such an insn is often undefined and, even if
3493 not, we cannot know what meaning will be given to it. Note that it is
3494 valid to have a register used in an address in an insn that changes it
3495 (presumably with a pre- or post-increment or decrement).
3497 If anything changes, return nonzero. */
3499 num_not_at_initial_offset = 0;
3500 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3502 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3503 ep->can_eliminate = 0;
3505 ep->ref_outside_mem = 0;
3507 if (ep->previous_offset != ep->offset)
3510 ep->previous_offset = ep->offset;
3511 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3512 num_not_at_initial_offset++;
3514 #ifdef STACK_GROWS_DOWNWARD
3515 ep->max_offset = MAX (ep->max_offset, ep->offset);
3517 ep->max_offset = MIN (ep->max_offset, ep->offset);
3522 /* If we changed something, perform elimination in REG_NOTES. This is
3523 needed even when REPLACE is zero because a REG_DEAD note might refer
3524 to a register that we eliminate and could cause a different number
3525 of spill registers to be needed in the final reload pass than in
3527 if (val && REG_NOTES (insn) != 0)
3528 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3536 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3537 replacement we currently believe is valid, mark it as not eliminable if X
3538 modifies DEST in any way other than by adding a constant integer to it.
3540 If DEST is the frame pointer, we do nothing because we assume that
3541 all assignments to the hard frame pointer are nonlocal gotos and are being
3542 done at a time when they are valid and do not disturb anything else.
3543 Some machines want to eliminate a fake argument pointer with either the
3544 frame or stack pointer. Assignments to the hard frame pointer must not
3545 prevent this elimination.
3547 Called via note_stores from reload before starting its passes to scan
3548 the insns of the function. */
3551 mark_not_eliminable (dest, x)
3557 /* A SUBREG of a hard register here is just changing its mode. We should
3558 not see a SUBREG of an eliminable hard register, but check just in
3560 if (GET_CODE (dest) == SUBREG)
3561 dest = SUBREG_REG (dest);
3563 if (dest == hard_frame_pointer_rtx)
3566 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3567 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3568 && (GET_CODE (x) != SET
3569 || GET_CODE (SET_SRC (x)) != PLUS
3570 || XEXP (SET_SRC (x), 0) != dest
3571 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3573 reg_eliminate[i].can_eliminate_previous
3574 = reg_eliminate[i].can_eliminate = 0;
3579 /* Kick all pseudos out of hard register REGNO.
3580 If GLOBAL is nonzero, try to find someplace else to put them.
3581 If DUMPFILE is nonzero, log actions taken on that file.
3583 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3584 because we found we can't eliminate some register. In the case, no pseudos
3585 are allowed to be in the register, even if they are only in a block that
3586 doesn't require spill registers, unlike the case when we are spilling this
3587 hard reg to produce another spill register.
3589 Return nonzero if any pseudos needed to be kicked out. */
3592 spill_hard_reg (regno, global, dumpfile, cant_eliminate)
3598 enum reg_class class = REGNO_REG_CLASS (regno);
3599 int something_changed = 0;
3602 SET_HARD_REG_BIT (forbidden_regs, regno);
3605 regs_ever_live[regno] = 1;
3607 /* Spill every pseudo reg that was allocated to this reg
3608 or to something that overlaps this reg. */
3610 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3611 if (reg_renumber[i] >= 0
3612 && reg_renumber[i] <= regno
3614 + HARD_REGNO_NREGS (reg_renumber[i],
3615 PSEUDO_REGNO_MODE (i))
3618 /* If this register belongs solely to a basic block which needed no
3619 spilling of any class that this register is contained in,
3620 leave it be, unless we are spilling this register because
3621 it was a hard register that can't be eliminated. */
3623 if (! cant_eliminate
3624 && basic_block_needs[0]
3625 && reg_basic_block[i] >= 0
3626 && basic_block_needs[(int) class][reg_basic_block[i]] == 0)
3630 for (p = reg_class_superclasses[(int) class];
3631 *p != LIM_REG_CLASSES; p++)
3632 if (basic_block_needs[(int) *p][reg_basic_block[i]] > 0)
3635 if (*p == LIM_REG_CLASSES)
3639 /* Mark it as no longer having a hard register home. */
3640 reg_renumber[i] = -1;
3641 /* We will need to scan everything again. */
3642 something_changed = 1;
3644 retry_global_alloc (i, forbidden_regs);
3646 alter_reg (i, regno);
3649 if (reg_renumber[i] == -1)
3650 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3652 fprintf (dumpfile, " Register %d now in %d.\n\n",
3653 i, reg_renumber[i]);
3656 for (i = 0; i < scratch_list_length; i++)
3658 if (scratch_list[i] && REGNO (scratch_list[i]) == regno)
3660 if (! cant_eliminate && basic_block_needs[0]
3661 && ! basic_block_needs[(int) class][scratch_block[i]])
3665 for (p = reg_class_superclasses[(int) class];
3666 *p != LIM_REG_CLASSES; p++)
3667 if (basic_block_needs[(int) *p][scratch_block[i]] > 0)
3670 if (*p == LIM_REG_CLASSES)
3673 PUT_CODE (scratch_list[i], SCRATCH);
3674 scratch_list[i] = 0;
3675 something_changed = 1;
3680 return something_changed;
3683 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3684 Also mark any hard registers used to store user variables as
3685 forbidden from being used for spill registers. */
3688 scan_paradoxical_subregs (x)
3693 register enum rtx_code code = GET_CODE (x);
3698 #ifdef SMALL_REGISTER_CLASSES
3699 if (SMALL_REGISTER_CLASSES
3700 && REGNO (x) < FIRST_PSEUDO_REGISTER
3701 && REG_USERVAR_P (x))
3702 SET_HARD_REG_BIT (forbidden_regs, REGNO (x));
3718 if (GET_CODE (SUBREG_REG (x)) == REG
3719 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3720 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3721 = GET_MODE_SIZE (GET_MODE (x));
3725 fmt = GET_RTX_FORMAT (code);
3726 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3729 scan_paradoxical_subregs (XEXP (x, i));
3730 else if (fmt[i] == 'E')
3733 for (j = XVECLEN (x, i) - 1; j >=0; j--)
3734 scan_paradoxical_subregs (XVECEXP (x, i, j));
3740 hard_reg_use_compare (p1p, p2p)
3741 const GENERIC_PTR p1p;
3742 const GENERIC_PTR p2p;
3744 struct hard_reg_n_uses *p1 = (struct hard_reg_n_uses *)p1p,
3745 *p2 = (struct hard_reg_n_uses *)p2p;
3746 int tem = p1->uses - p2->uses;
3747 if (tem != 0) return tem;
3748 /* If regs are equally good, sort by regno,
3749 so that the results of qsort leave nothing to chance. */
3750 return p1->regno - p2->regno;
3753 /* Choose the order to consider regs for use as reload registers
3754 based on how much trouble would be caused by spilling one.
3755 Store them in order of decreasing preference in potential_reload_regs. */
3758 order_regs_for_reload (global)
3765 struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
3767 CLEAR_HARD_REG_SET (bad_spill_regs);
3769 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3770 potential_reload_regs[i] = -1;
3772 /* Count number of uses of each hard reg by pseudo regs allocated to it
3773 and then order them by decreasing use. */
3775 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3777 hard_reg_n_uses[i].uses = 0;
3778 hard_reg_n_uses[i].regno = i;
3781 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3783 int regno = reg_renumber[i];
3786 int lim = regno + HARD_REGNO_NREGS (regno, PSEUDO_REGNO_MODE (i));
3789 /* If allocated by local-alloc, show more uses since
3790 we're not going to be able to reallocate it, but
3791 we might if allocated by global alloc. */
3792 if (global && reg_allocno[i] < 0)
3793 hard_reg_n_uses[regno].uses += (reg_n_refs[i] + 1) / 2;
3795 hard_reg_n_uses[regno++].uses += reg_n_refs[i];
3798 large += reg_n_refs[i];
3801 /* Now fixed registers (which cannot safely be used for reloading)
3802 get a very high use count so they will be considered least desirable.
3803 Registers used explicitly in the rtl code are almost as bad. */
3805 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3809 hard_reg_n_uses[i].uses += 2 * large + 2;
3810 SET_HARD_REG_BIT (bad_spill_regs, i);
3812 else if (regs_explicitly_used[i])
3814 hard_reg_n_uses[i].uses += large + 1;
3815 /* ??? We are doing this here because of the potential that
3816 bad code may be generated if a register explicitly used in
3817 an insn was used as a spill register for that insn. But
3818 not using these are spill registers may lose on some machine.
3819 We'll have to see how this works out. */
3820 #ifdef SMALL_REGISTER_CLASSES
3821 if (! SMALL_REGISTER_CLASSES)
3823 SET_HARD_REG_BIT (bad_spill_regs, i);
3826 hard_reg_n_uses[HARD_FRAME_POINTER_REGNUM].uses += 2 * large + 2;
3827 SET_HARD_REG_BIT (bad_spill_regs, HARD_FRAME_POINTER_REGNUM);
3829 #ifdef ELIMINABLE_REGS
3830 /* If registers other than the frame pointer are eliminable, mark them as
3832 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3834 hard_reg_n_uses[reg_eliminate[i].from].uses += 2 * large + 2;
3835 SET_HARD_REG_BIT (bad_spill_regs, reg_eliminate[i].from);
3839 /* Prefer registers not so far used, for use in temporary loading.
3840 Among them, if REG_ALLOC_ORDER is defined, use that order.
3841 Otherwise, prefer registers not preserved by calls. */
3843 #ifdef REG_ALLOC_ORDER
3844 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3846 int regno = reg_alloc_order[i];
3848 if (hard_reg_n_uses[regno].uses == 0)
3849 potential_reload_regs[o++] = regno;
3852 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3854 if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i])
3855 potential_reload_regs[o++] = i;
3857 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3859 if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i])
3860 potential_reload_regs[o++] = i;
3864 qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
3865 sizeof hard_reg_n_uses[0], hard_reg_use_compare);
3867 /* Now add the regs that are already used,
3868 preferring those used less often. The fixed and otherwise forbidden
3869 registers will be at the end of this list. */
3871 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3872 if (hard_reg_n_uses[i].uses != 0)
3873 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
3876 /* Used in reload_as_needed to sort the spilled regs. */
3879 compare_spill_regs (r1p, r2p)
3880 const GENERIC_PTR r1p;
3881 const GENERIC_PTR r2p;
3883 short r1 = *(short *)r1p, r2 = *(short *)r2p;
3887 /* Reload pseudo-registers into hard regs around each insn as needed.
3888 Additional register load insns are output before the insn that needs it
3889 and perhaps store insns after insns that modify the reloaded pseudo reg.
3891 reg_last_reload_reg and reg_reloaded_contents keep track of
3892 which registers are already available in reload registers.
3893 We update these for the reloads that we perform,
3894 as the insns are scanned. */
3897 reload_as_needed (first, live_known)
3907 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
3908 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
3909 reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
3910 bzero ((char *) reg_last_reload_reg, max_regno * sizeof (rtx));
3911 reg_has_output_reload = (char *) alloca (max_regno);
3912 for (i = 0; i < n_spills; i++)
3914 reg_reloaded_contents[i] = -1;
3915 reg_reloaded_insn[i] = 0;
3918 /* Reset all offsets on eliminable registers to their initial values. */
3919 #ifdef ELIMINABLE_REGS
3920 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3922 INITIAL_ELIMINATION_OFFSET (reg_eliminate[i].from, reg_eliminate[i].to,
3923 reg_eliminate[i].initial_offset);
3924 reg_eliminate[i].previous_offset
3925 = reg_eliminate[i].offset = reg_eliminate[i].initial_offset;
3928 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
3929 reg_eliminate[0].previous_offset
3930 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
3933 num_not_at_initial_offset = 0;
3935 /* Order the spilled regs, so that allocate_reload_regs can guarantee to
3936 pack registers with group needs. */
3939 qsort (spill_regs, n_spills, sizeof (short), compare_spill_regs);
3940 for (i = 0; i < n_spills; i++)
3941 spill_reg_order[spill_regs[i]] = i;
3944 for (insn = first; insn;)
3946 register rtx next = NEXT_INSN (insn);
3948 /* Notice when we move to a new basic block. */
3949 if (live_known && this_block + 1 < n_basic_blocks
3950 && insn == basic_block_head[this_block+1])
3953 /* If we pass a label, copy the offsets from the label information
3954 into the current offsets of each elimination. */
3955 if (GET_CODE (insn) == CODE_LABEL)
3957 num_not_at_initial_offset = 0;
3958 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3960 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
3961 = offsets_at[CODE_LABEL_NUMBER (insn)][i];
3962 if (reg_eliminate[i].can_eliminate
3963 && (reg_eliminate[i].offset
3964 != reg_eliminate[i].initial_offset))
3965 num_not_at_initial_offset++;
3969 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
3971 rtx avoid_return_reg = 0;
3972 rtx oldpat = PATTERN (insn);
3974 #ifdef SMALL_REGISTER_CLASSES
3975 /* Set avoid_return_reg if this is an insn
3976 that might use the value of a function call. */
3977 if (SMALL_REGISTER_CLASSES && GET_CODE (insn) == CALL_INSN)
3979 if (GET_CODE (PATTERN (insn)) == SET)
3980 after_call = SET_DEST (PATTERN (insn));
3981 else if (GET_CODE (PATTERN (insn)) == PARALLEL
3982 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
3983 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
3987 else if (SMALL_REGISTER_CLASSES
3989 && !(GET_CODE (PATTERN (insn)) == SET
3990 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
3992 if (reg_referenced_p (after_call, PATTERN (insn)))
3993 avoid_return_reg = after_call;
3996 #endif /* SMALL_REGISTER_CLASSES */
3998 /* If this is a USE and CLOBBER of a MEM, ensure that any
3999 references to eliminable registers have been removed. */
4001 if ((GET_CODE (PATTERN (insn)) == USE
4002 || GET_CODE (PATTERN (insn)) == CLOBBER)
4003 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
4004 XEXP (XEXP (PATTERN (insn), 0), 0)
4005 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4006 GET_MODE (XEXP (PATTERN (insn), 0)), NULL_RTX);
4008 /* If we need to do register elimination processing, do so.
4009 This might delete the insn, in which case we are done. */
4010 if (num_eliminable && GET_MODE (insn) == QImode)
4012 eliminate_regs_in_insn (insn, 1);
4013 if (GET_CODE (insn) == NOTE)
4020 if (GET_MODE (insn) == VOIDmode)
4022 /* First find the pseudo regs that must be reloaded for this insn.
4023 This info is returned in the tables reload_... (see reload.h).
4024 Also modify the body of INSN by substituting RELOAD
4025 rtx's for those pseudo regs. */
4028 bzero (reg_has_output_reload, max_regno);
4029 CLEAR_HARD_REG_SET (reg_is_output_reload);
4031 find_reloads (insn, 1, spill_indirect_levels, live_known,
4037 rtx prev = PREV_INSN (insn), next = NEXT_INSN (insn);
4041 /* If this block has not had spilling done for a
4042 particular clas and we have any non-optionals that need a
4043 spill reg in that class, abort. */
4045 for (class = 0; class < N_REG_CLASSES; class++)
4046 if (basic_block_needs[class] != 0
4047 && basic_block_needs[class][this_block] == 0)
4048 for (i = 0; i < n_reloads; i++)
4049 if (class == (int) reload_reg_class[i]
4050 && reload_reg_rtx[i] == 0
4051 && ! reload_optional[i]
4052 && (reload_in[i] != 0 || reload_out[i] != 0
4053 || reload_secondary_p[i] != 0))
4054 fatal_insn ("Non-optional registers need a spill register", insn);
4056 /* Now compute which reload regs to reload them into. Perhaps
4057 reusing reload regs from previous insns, or else output
4058 load insns to reload them. Maybe output store insns too.
4059 Record the choices of reload reg in reload_reg_rtx. */
4060 choose_reload_regs (insn, avoid_return_reg);
4062 #ifdef SMALL_REGISTER_CLASSES
4063 /* Merge any reloads that we didn't combine for fear of
4064 increasing the number of spill registers needed but now
4065 discover can be safely merged. */
4066 if (SMALL_REGISTER_CLASSES)
4067 merge_assigned_reloads (insn);
4070 /* Generate the insns to reload operands into or out of
4071 their reload regs. */
4072 emit_reload_insns (insn);
4074 /* Substitute the chosen reload regs from reload_reg_rtx
4075 into the insn's body (or perhaps into the bodies of other
4076 load and store insn that we just made for reloading
4077 and that we moved the structure into). */
4080 /* If this was an ASM, make sure that all the reload insns
4081 we have generated are valid. If not, give an error
4084 if (asm_noperands (PATTERN (insn)) >= 0)
4085 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4086 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
4087 && (recog_memoized (p) < 0
4088 || (insn_extract (p),
4089 ! constrain_operands (INSN_CODE (p), 1))))
4091 error_for_asm (insn,
4092 "`asm' operand requires impossible reload");
4094 NOTE_SOURCE_FILE (p) = 0;
4095 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
4098 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4099 is no longer validly lying around to save a future reload.
4100 Note that this does not detect pseudos that were reloaded
4101 for this insn in order to be stored in
4102 (obeying register constraints). That is correct; such reload
4103 registers ARE still valid. */
4104 note_stores (oldpat, forget_old_reloads_1);
4106 /* There may have been CLOBBER insns placed after INSN. So scan
4107 between INSN and NEXT and use them to forget old reloads. */
4108 for (x = NEXT_INSN (insn); x != next; x = NEXT_INSN (x))
4109 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
4110 note_stores (PATTERN (x), forget_old_reloads_1);
4113 /* Likewise for regs altered by auto-increment in this insn.
4114 But note that the reg-notes are not changed by reloading:
4115 they still contain the pseudo-regs, not the spill regs. */
4116 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4117 if (REG_NOTE_KIND (x) == REG_INC)
4119 /* See if this pseudo reg was reloaded in this insn.
4120 If so, its last-reload info is still valid
4121 because it is based on this insn's reload. */
4122 for (i = 0; i < n_reloads; i++)
4123 if (reload_out[i] == XEXP (x, 0))
4127 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX);
4131 /* A reload reg's contents are unknown after a label. */
4132 if (GET_CODE (insn) == CODE_LABEL)
4133 for (i = 0; i < n_spills; i++)
4135 reg_reloaded_contents[i] = -1;
4136 reg_reloaded_insn[i] = 0;
4139 /* Don't assume a reload reg is still good after a call insn
4140 if it is a call-used reg. */
4141 else if (GET_CODE (insn) == CALL_INSN)
4142 for (i = 0; i < n_spills; i++)
4143 if (call_used_regs[spill_regs[i]])
4145 reg_reloaded_contents[i] = -1;
4146 reg_reloaded_insn[i] = 0;
4149 /* In case registers overlap, allow certain insns to invalidate
4150 particular hard registers. */
4152 #ifdef INSN_CLOBBERS_REGNO_P
4153 for (i = 0 ; i < n_spills ; i++)
4154 if (INSN_CLOBBERS_REGNO_P (insn, spill_regs[i]))
4156 reg_reloaded_contents[i] = -1;
4157 reg_reloaded_insn[i] = 0;
4169 /* Discard all record of any value reloaded from X,
4170 or reloaded in X from someplace else;
4171 unless X is an output reload reg of the current insn.
4173 X may be a hard reg (the reload reg)
4174 or it may be a pseudo reg that was reloaded from. */
4177 forget_old_reloads_1 (x, ignored)
4185 /* note_stores does give us subregs of hard regs. */
4186 while (GET_CODE (x) == SUBREG)
4188 offset += SUBREG_WORD (x);
4192 if (GET_CODE (x) != REG)
4195 regno = REGNO (x) + offset;
4197 if (regno >= FIRST_PSEUDO_REGISTER)
4202 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4203 /* Storing into a spilled-reg invalidates its contents.
4204 This can happen if a block-local pseudo is allocated to that reg
4205 and it wasn't spilled because this block's total need is 0.
4206 Then some insn might have an optional reload and use this reg. */
4207 for (i = 0; i < nr; i++)
4208 if (spill_reg_order[regno + i] >= 0
4209 /* But don't do this if the reg actually serves as an output
4210 reload reg in the current instruction. */
4212 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i)))
4214 reg_reloaded_contents[spill_reg_order[regno + i]] = -1;
4215 reg_reloaded_insn[spill_reg_order[regno + i]] = 0;
4219 /* Since value of X has changed,
4220 forget any value previously copied from it. */
4223 /* But don't forget a copy if this is the output reload
4224 that establishes the copy's validity. */
4225 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4226 reg_last_reload_reg[regno + nr] = 0;
4229 /* For each reload, the mode of the reload register. */
4230 static enum machine_mode reload_mode[MAX_RELOADS];
4232 /* For each reload, the largest number of registers it will require. */
4233 static int reload_nregs[MAX_RELOADS];
4235 /* Comparison function for qsort to decide which of two reloads
4236 should be handled first. *P1 and *P2 are the reload numbers. */
4239 reload_reg_class_lower (r1p, r2p)
4240 const GENERIC_PTR r1p;
4241 const GENERIC_PTR r2p;
4243 register int r1 = *(short *)r1p, r2 = *(short *)r2p;
4246 /* Consider required reloads before optional ones. */
4247 t = reload_optional[r1] - reload_optional[r2];
4251 /* Count all solitary classes before non-solitary ones. */
4252 t = ((reg_class_size[(int) reload_reg_class[r2]] == 1)
4253 - (reg_class_size[(int) reload_reg_class[r1]] == 1));
4257 /* Aside from solitaires, consider all multi-reg groups first. */
4258 t = reload_nregs[r2] - reload_nregs[r1];
4262 /* Consider reloads in order of increasing reg-class number. */
4263 t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2];
4267 /* If reloads are equally urgent, sort by reload number,
4268 so that the results of qsort leave nothing to chance. */
4272 /* The following HARD_REG_SETs indicate when each hard register is
4273 used for a reload of various parts of the current insn. */
4275 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4276 static HARD_REG_SET reload_reg_used;
4277 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4278 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4279 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4280 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4281 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4282 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4283 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4284 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4285 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4286 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4287 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4288 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4289 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4290 static HARD_REG_SET reload_reg_used_in_op_addr;
4291 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4292 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4293 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4294 static HARD_REG_SET reload_reg_used_in_insn;
4295 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4296 static HARD_REG_SET reload_reg_used_in_other_addr;
4298 /* If reg is in use as a reload reg for any sort of reload. */
4299 static HARD_REG_SET reload_reg_used_at_all;
4301 /* If reg is use as an inherited reload. We just mark the first register
4303 static HARD_REG_SET reload_reg_used_for_inherit;
4305 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4306 TYPE. MODE is used to indicate how many consecutive regs are
4310 mark_reload_reg_in_use (regno, opnum, type, mode)
4313 enum reload_type type;
4314 enum machine_mode mode;
4316 int nregs = HARD_REGNO_NREGS (regno, mode);
4319 for (i = regno; i < nregs + regno; i++)
4324 SET_HARD_REG_BIT (reload_reg_used, i);
4327 case RELOAD_FOR_INPUT_ADDRESS:
4328 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4331 case RELOAD_FOR_INPADDR_ADDRESS:
4332 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4335 case RELOAD_FOR_OUTPUT_ADDRESS:
4336 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4339 case RELOAD_FOR_OUTADDR_ADDRESS:
4340 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4343 case RELOAD_FOR_OPERAND_ADDRESS:
4344 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4347 case RELOAD_FOR_OPADDR_ADDR:
4348 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4351 case RELOAD_FOR_OTHER_ADDRESS:
4352 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4355 case RELOAD_FOR_INPUT:
4356 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4359 case RELOAD_FOR_OUTPUT:
4360 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4363 case RELOAD_FOR_INSN:
4364 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4368 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4372 /* Similarly, but show REGNO is no longer in use for a reload. */
4375 clear_reload_reg_in_use (regno, opnum, type, mode)
4378 enum reload_type type;
4379 enum machine_mode mode;
4381 int nregs = HARD_REGNO_NREGS (regno, mode);
4384 for (i = regno; i < nregs + regno; i++)
4389 CLEAR_HARD_REG_BIT (reload_reg_used, i);
4392 case RELOAD_FOR_INPUT_ADDRESS:
4393 CLEAR_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4396 case RELOAD_FOR_INPADDR_ADDRESS:
4397 CLEAR_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4400 case RELOAD_FOR_OUTPUT_ADDRESS:
4401 CLEAR_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4404 case RELOAD_FOR_OUTADDR_ADDRESS:
4405 CLEAR_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4408 case RELOAD_FOR_OPERAND_ADDRESS:
4409 CLEAR_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4412 case RELOAD_FOR_OPADDR_ADDR:
4413 CLEAR_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4416 case RELOAD_FOR_OTHER_ADDRESS:
4417 CLEAR_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4420 case RELOAD_FOR_INPUT:
4421 CLEAR_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4424 case RELOAD_FOR_OUTPUT:
4425 CLEAR_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4428 case RELOAD_FOR_INSN:
4429 CLEAR_HARD_REG_BIT (reload_reg_used_in_insn, i);
4435 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4436 specified by OPNUM and TYPE. */
4439 reload_reg_free_p (regno, opnum, type)
4442 enum reload_type type;
4446 /* In use for a RELOAD_OTHER means it's not available for anything. */
4447 if (TEST_HARD_REG_BIT (reload_reg_used, regno))
4453 /* In use for anything means we can't use it for RELOAD_OTHER. */
4454 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4455 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4456 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4459 for (i = 0; i < reload_n_operands; i++)
4460 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4461 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4462 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4463 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4464 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4465 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4470 case RELOAD_FOR_INPUT:
4471 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4472 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4475 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4478 /* If it is used for some other input, can't use it. */
4479 for (i = 0; i < reload_n_operands; i++)
4480 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4483 /* If it is used in a later operand's address, can't use it. */
4484 for (i = opnum + 1; i < reload_n_operands; i++)
4485 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4486 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4491 case RELOAD_FOR_INPUT_ADDRESS:
4492 /* Can't use a register if it is used for an input address for this
4493 operand or used as an input in an earlier one. */
4494 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4495 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4498 for (i = 0; i < opnum; i++)
4499 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4504 case RELOAD_FOR_INPADDR_ADDRESS:
4505 /* Can't use a register if it is used for an input address
4506 address for this operand or used as an input in an earlier
4508 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4511 for (i = 0; i < opnum; i++)
4512 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4517 case RELOAD_FOR_OUTPUT_ADDRESS:
4518 /* Can't use a register if it is used for an output address for this
4519 operand or used as an output in this or a later operand. */
4520 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4523 for (i = opnum; i < reload_n_operands; i++)
4524 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4529 case RELOAD_FOR_OUTADDR_ADDRESS:
4530 /* Can't use a register if it is used for an output address
4531 address for this operand or used as an output in this or a
4533 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4536 for (i = opnum; i < reload_n_operands; i++)
4537 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4542 case RELOAD_FOR_OPERAND_ADDRESS:
4543 for (i = 0; i < reload_n_operands; i++)
4544 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4547 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4548 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4550 case RELOAD_FOR_OPADDR_ADDR:
4551 for (i = 0; i < reload_n_operands; i++)
4552 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4555 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4557 case RELOAD_FOR_OUTPUT:
4558 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4559 outputs, or an operand address for this or an earlier output. */
4560 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4563 for (i = 0; i < reload_n_operands; i++)
4564 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4567 for (i = 0; i <= opnum; i++)
4568 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4569 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4574 case RELOAD_FOR_INSN:
4575 for (i = 0; i < reload_n_operands; i++)
4576 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4577 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4580 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4581 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4583 case RELOAD_FOR_OTHER_ADDRESS:
4584 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4589 /* Return 1 if the value in reload reg REGNO, as used by a reload
4590 needed for the part of the insn specified by OPNUM and TYPE,
4591 is not in use for a reload in any prior part of the insn.
4593 We can assume that the reload reg was already tested for availability
4594 at the time it is needed, and we should not check this again,
4595 in case the reg has already been marked in use. */
4598 reload_reg_free_before_p (regno, opnum, type)
4601 enum reload_type type;
4607 case RELOAD_FOR_OTHER_ADDRESS:
4608 /* These always come first. */
4612 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4614 /* If this use is for part of the insn,
4615 check the reg is not in use for any prior part. It is tempting
4616 to try to do this by falling through from objecs that occur
4617 later in the insn to ones that occur earlier, but that will not
4618 correctly take into account the fact that here we MUST ignore
4619 things that would prevent the register from being allocated in
4620 the first place, since we know that it was allocated. */
4622 case RELOAD_FOR_OUTPUT_ADDRESS:
4623 case RELOAD_FOR_OUTADDR_ADDRESS:
4624 /* Earlier reloads are for earlier outputs or their addresses,
4625 any RELOAD_FOR_INSN reloads, any inputs or their addresses, or any
4626 RELOAD_FOR_OTHER_ADDRESS reloads (we know it can't conflict with
4628 for (i = 0; i < opnum; i++)
4629 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4630 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4631 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4634 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4637 for (i = 0; i < reload_n_operands; i++)
4638 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4639 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4640 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4643 return (! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4644 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4645 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4647 case RELOAD_FOR_OUTPUT:
4648 /* This can't be used in the output address for this operand and
4649 anything that can't be used for it, except that we've already
4650 tested for RELOAD_FOR_INSN objects. */
4652 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno)
4653 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4656 for (i = 0; i < opnum; i++)
4657 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4658 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4659 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4662 for (i = 0; i < reload_n_operands; i++)
4663 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4664 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4665 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4666 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4669 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4671 case RELOAD_FOR_OPERAND_ADDRESS:
4672 case RELOAD_FOR_OPADDR_ADDR:
4673 case RELOAD_FOR_INSN:
4674 /* These can't conflict with inputs, or each other, so all we have to
4675 test is input addresses and the addresses of OTHER items. */
4677 for (i = 0; i < reload_n_operands; i++)
4678 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4679 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4682 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4684 case RELOAD_FOR_INPUT:
4685 /* The only things earlier are the address for this and
4686 earlier inputs, other inputs (which we know we don't conflict
4687 with), and addresses of RELOAD_OTHER objects. */
4689 for (i = 0; i <= opnum; i++)
4690 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4691 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4694 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4696 case RELOAD_FOR_INPUT_ADDRESS:
4697 case RELOAD_FOR_INPADDR_ADDRESS:
4698 /* Similarly, all we have to check is for use in earlier inputs'
4700 for (i = 0; i < opnum; i++)
4701 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4702 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4705 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4710 /* Return 1 if the value in reload reg REGNO, as used by a reload
4711 needed for the part of the insn specified by OPNUM and TYPE,
4712 is still available in REGNO at the end of the insn.
4714 We can assume that the reload reg was already tested for availability
4715 at the time it is needed, and we should not check this again,
4716 in case the reg has already been marked in use. */
4719 reload_reg_reaches_end_p (regno, opnum, type)
4722 enum reload_type type;
4729 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4730 its value must reach the end. */
4733 /* If this use is for part of the insn,
4734 its value reaches if no subsequent part uses the same register.
4735 Just like the above function, don't try to do this with lots
4738 case RELOAD_FOR_OTHER_ADDRESS:
4739 /* Here we check for everything else, since these don't conflict
4740 with anything else and everything comes later. */
4742 for (i = 0; i < reload_n_operands; i++)
4743 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4744 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4745 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4746 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4747 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4748 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4751 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4752 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4753 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4755 case RELOAD_FOR_INPUT_ADDRESS:
4756 case RELOAD_FOR_INPADDR_ADDRESS:
4757 /* Similar, except that we check only for this and subsequent inputs
4758 and the address of only subsequent inputs and we do not need
4759 to check for RELOAD_OTHER objects since they are known not to
4762 for (i = opnum; i < reload_n_operands; i++)
4763 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4766 for (i = opnum + 1; i < reload_n_operands; i++)
4767 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4768 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4771 for (i = 0; i < reload_n_operands; i++)
4772 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4773 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4774 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4777 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4780 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4781 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4783 case RELOAD_FOR_INPUT:
4784 /* Similar to input address, except we start at the next operand for
4785 both input and input address and we do not check for
4786 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4789 for (i = opnum + 1; i < reload_n_operands; i++)
4790 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4791 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4792 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4795 /* ... fall through ... */
4797 case RELOAD_FOR_OPERAND_ADDRESS:
4798 /* Check outputs and their addresses. */
4800 for (i = 0; i < reload_n_operands; i++)
4801 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4802 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4803 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4808 case RELOAD_FOR_OPADDR_ADDR:
4809 for (i = 0; i < reload_n_operands; i++)
4810 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4811 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4812 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4815 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4816 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4818 case RELOAD_FOR_INSN:
4819 /* These conflict with other outputs with RELOAD_OTHER. So
4820 we need only check for output addresses. */
4824 /* ... fall through ... */
4826 case RELOAD_FOR_OUTPUT:
4827 case RELOAD_FOR_OUTPUT_ADDRESS:
4828 case RELOAD_FOR_OUTADDR_ADDRESS:
4829 /* We already know these can't conflict with a later output. So the
4830 only thing to check are later output addresses. */
4831 for (i = opnum + 1; i < reload_n_operands; i++)
4832 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4833 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4842 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4845 This function uses the same algorithm as reload_reg_free_p above. */
4848 reloads_conflict (r1, r2)
4851 enum reload_type r1_type = reload_when_needed[r1];
4852 enum reload_type r2_type = reload_when_needed[r2];
4853 int r1_opnum = reload_opnum[r1];
4854 int r2_opnum = reload_opnum[r2];
4856 /* RELOAD_OTHER conflicts with everything. */
4857 if (r2_type == RELOAD_OTHER)
4860 /* Otherwise, check conflicts differently for each type. */
4864 case RELOAD_FOR_INPUT:
4865 return (r2_type == RELOAD_FOR_INSN
4866 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4867 || r2_type == RELOAD_FOR_OPADDR_ADDR
4868 || r2_type == RELOAD_FOR_INPUT
4869 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4870 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4871 && r2_opnum > r1_opnum));
4873 case RELOAD_FOR_INPUT_ADDRESS:
4874 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4875 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4877 case RELOAD_FOR_INPADDR_ADDRESS:
4878 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4879 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4881 case RELOAD_FOR_OUTPUT_ADDRESS:
4882 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4883 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4885 case RELOAD_FOR_OUTADDR_ADDRESS:
4886 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4887 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4889 case RELOAD_FOR_OPERAND_ADDRESS:
4890 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4891 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4893 case RELOAD_FOR_OPADDR_ADDR:
4894 return (r2_type == RELOAD_FOR_INPUT
4895 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4897 case RELOAD_FOR_OUTPUT:
4898 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4899 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4900 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4901 && r2_opnum >= r1_opnum));
4903 case RELOAD_FOR_INSN:
4904 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4905 || r2_type == RELOAD_FOR_INSN
4906 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4908 case RELOAD_FOR_OTHER_ADDRESS:
4909 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4919 /* Vector of reload-numbers showing the order in which the reloads should
4921 short reload_order[MAX_RELOADS];
4923 /* Indexed by reload number, 1 if incoming value
4924 inherited from previous insns. */
4925 char reload_inherited[MAX_RELOADS];
4927 /* For an inherited reload, this is the insn the reload was inherited from,
4928 if we know it. Otherwise, this is 0. */
4929 rtx reload_inheritance_insn[MAX_RELOADS];
4931 /* If non-zero, this is a place to get the value of the reload,
4932 rather than using reload_in. */
4933 rtx reload_override_in[MAX_RELOADS];
4935 /* For each reload, the index in spill_regs of the spill register used,
4936 or -1 if we did not need one of the spill registers for this reload. */
4937 int reload_spill_index[MAX_RELOADS];
4939 /* Find a spill register to use as a reload register for reload R.
4940 LAST_RELOAD is non-zero if this is the last reload for the insn being
4943 Set reload_reg_rtx[R] to the register allocated.
4945 If NOERROR is nonzero, we return 1 if successful,
4946 or 0 if we couldn't find a spill reg and we didn't change anything. */
4949 allocate_reload_reg (r, insn, last_reload, noerror)
4961 /* If we put this reload ahead, thinking it is a group,
4962 then insist on finding a group. Otherwise we can grab a
4963 reg that some other reload needs.
4964 (That can happen when we have a 68000 DATA_OR_FP_REG
4965 which is a group of data regs or one fp reg.)
4966 We need not be so restrictive if there are no more reloads
4969 ??? Really it would be nicer to have smarter handling
4970 for that kind of reg class, where a problem like this is normal.
4971 Perhaps those classes should be avoided for reloading
4972 by use of more alternatives. */
4974 int force_group = reload_nregs[r] > 1 && ! last_reload;
4976 /* If we want a single register and haven't yet found one,
4977 take any reg in the right class and not in use.
4978 If we want a consecutive group, here is where we look for it.
4980 We use two passes so we can first look for reload regs to
4981 reuse, which are already in use for other reloads in this insn,
4982 and only then use additional registers.
4983 I think that maximizing reuse is needed to make sure we don't
4984 run out of reload regs. Suppose we have three reloads, and
4985 reloads A and B can share regs. These need two regs.
4986 Suppose A and B are given different regs.
4987 That leaves none for C. */
4988 for (pass = 0; pass < 2; pass++)
4990 /* I is the index in spill_regs.
4991 We advance it round-robin between insns to use all spill regs
4992 equally, so that inherited reloads have a chance
4993 of leapfrogging each other. Don't do this, however, when we have
4994 group needs and failure would be fatal; if we only have a relatively
4995 small number of spill registers, and more than one of them has
4996 group needs, then by starting in the middle, we may end up
4997 allocating the first one in such a way that we are not left with
4998 sufficient groups to handle the rest. */
5000 if (noerror || ! force_group)
5005 for (count = 0; count < n_spills; count++)
5007 int class = (int) reload_reg_class[r];
5009 i = (i + 1) % n_spills;
5011 if (reload_reg_free_p (spill_regs[i], reload_opnum[r],
5012 reload_when_needed[r])
5013 && TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i])
5014 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
5015 /* Look first for regs to share, then for unshared. But
5016 don't share regs used for inherited reloads; they are
5017 the ones we want to preserve. */
5019 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5021 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5024 int nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
5025 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5026 (on 68000) got us two FP regs. If NR is 1,
5027 we would reject both of them. */
5029 nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]);
5030 /* If we need only one reg, we have already won. */
5033 /* But reject a single reg if we demand a group. */
5038 /* Otherwise check that as many consecutive regs as we need
5040 Also, don't use for a group registers that are
5041 needed for nongroups. */
5042 if (! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
5045 regno = spill_regs[i] + nr - 1;
5046 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5047 && spill_reg_order[regno] >= 0
5048 && reload_reg_free_p (regno, reload_opnum[r],
5049 reload_when_needed[r])
5050 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
5060 /* If we found something on pass 1, omit pass 2. */
5061 if (count < n_spills)
5065 /* We should have found a spill register by now. */
5066 if (count == n_spills)
5073 /* I is the index in SPILL_REG_RTX of the reload register we are to
5074 allocate. Get an rtx for it and find its register number. */
5076 new = spill_reg_rtx[i];
5078 if (new == 0 || GET_MODE (new) != reload_mode[r])
5079 spill_reg_rtx[i] = new
5080 = gen_rtx (REG, reload_mode[r], spill_regs[i]);
5082 regno = true_regnum (new);
5084 /* Detect when the reload reg can't hold the reload mode.
5085 This used to be one `if', but Sequent compiler can't handle that. */
5086 if (HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5088 enum machine_mode test_mode = VOIDmode;
5090 test_mode = GET_MODE (reload_in[r]);
5091 /* If reload_in[r] has VOIDmode, it means we will load it
5092 in whatever mode the reload reg has: to wit, reload_mode[r].
5093 We have already tested that for validity. */
5094 /* Aside from that, we need to test that the expressions
5095 to reload from or into have modes which are valid for this
5096 reload register. Otherwise the reload insns would be invalid. */
5097 if (! (reload_in[r] != 0 && test_mode != VOIDmode
5098 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5099 if (! (reload_out[r] != 0
5100 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r]))))
5102 /* The reg is OK. */
5105 /* Mark as in use for this insn the reload regs we use
5107 mark_reload_reg_in_use (spill_regs[i], reload_opnum[r],
5108 reload_when_needed[r], reload_mode[r]);
5110 reload_reg_rtx[r] = new;
5111 reload_spill_index[r] = i;
5116 /* The reg is not OK. */
5121 if (asm_noperands (PATTERN (insn)) < 0)
5122 /* It's the compiler's fault. */
5123 fatal_insn ("Could not find a spill register", insn);
5125 /* It's the user's fault; the operand's mode and constraint
5126 don't match. Disable this reload so we don't crash in final. */
5127 error_for_asm (insn,
5128 "`asm' operand constraint incompatible with operand size");
5131 reload_reg_rtx[r] = 0;
5132 reload_optional[r] = 1;
5133 reload_secondary_p[r] = 1;
5138 /* Assign hard reg targets for the pseudo-registers we must reload
5139 into hard regs for this insn.
5140 Also output the instructions to copy them in and out of the hard regs.
5142 For machines with register classes, we are responsible for
5143 finding a reload reg in the proper class. */
5146 choose_reload_regs (insn, avoid_return_reg)
5148 rtx avoid_return_reg;
5151 int max_group_size = 1;
5152 enum reg_class group_class = NO_REGS;
5155 rtx save_reload_reg_rtx[MAX_RELOADS];
5156 char save_reload_inherited[MAX_RELOADS];
5157 rtx save_reload_inheritance_insn[MAX_RELOADS];
5158 rtx save_reload_override_in[MAX_RELOADS];
5159 int save_reload_spill_index[MAX_RELOADS];
5160 HARD_REG_SET save_reload_reg_used;
5161 HARD_REG_SET save_reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
5162 HARD_REG_SET save_reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
5163 HARD_REG_SET save_reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
5164 HARD_REG_SET save_reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
5165 HARD_REG_SET save_reload_reg_used_in_input[MAX_RECOG_OPERANDS];
5166 HARD_REG_SET save_reload_reg_used_in_output[MAX_RECOG_OPERANDS];
5167 HARD_REG_SET save_reload_reg_used_in_op_addr;
5168 HARD_REG_SET save_reload_reg_used_in_op_addr_reload;
5169 HARD_REG_SET save_reload_reg_used_in_insn;
5170 HARD_REG_SET save_reload_reg_used_in_other_addr;
5171 HARD_REG_SET save_reload_reg_used_at_all;
5173 bzero (reload_inherited, MAX_RELOADS);
5174 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
5175 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
5177 CLEAR_HARD_REG_SET (reload_reg_used);
5178 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5179 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5180 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5181 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5182 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5184 for (i = 0; i < reload_n_operands; i++)
5186 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5187 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5188 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5189 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5190 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5191 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5194 #ifdef SMALL_REGISTER_CLASSES
5195 /* Don't bother with avoiding the return reg
5196 if we have no mandatory reload that could use it. */
5197 if (SMALL_REGISTER_CLASSES && avoid_return_reg)
5200 int regno = REGNO (avoid_return_reg);
5202 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
5205 for (r = regno; r < regno + nregs; r++)
5206 if (spill_reg_order[r] >= 0)
5207 for (j = 0; j < n_reloads; j++)
5208 if (!reload_optional[j] && reload_reg_rtx[j] == 0
5209 && (reload_in[j] != 0 || reload_out[j] != 0
5210 || reload_secondary_p[j])
5212 TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[j]], r))
5215 avoid_return_reg = 0;
5217 #endif /* SMALL_REGISTER_CLASSES */
5219 #if 0 /* Not needed, now that we can always retry without inheritance. */
5220 /* See if we have more mandatory reloads than spill regs.
5221 If so, then we cannot risk optimizations that could prevent
5222 reloads from sharing one spill register.
5224 Since we will try finding a better register than reload_reg_rtx
5225 unless it is equal to reload_in or reload_out, count such reloads. */
5229 #ifdef SMALL_REGISTER_CLASSES
5230 if (SMALL_REGISTER_CLASSES)
5231 tem = (avoid_return_reg != 0);
5233 for (j = 0; j < n_reloads; j++)
5234 if (! reload_optional[j]
5235 && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j])
5236 && (reload_reg_rtx[j] == 0
5237 || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j])
5238 && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j]))))
5245 #ifdef SMALL_REGISTER_CLASSES
5246 /* Don't use the subroutine call return reg for a reload
5247 if we are supposed to avoid it. */
5248 if (SMALL_REGISTER_CLASSES && avoid_return_reg)
5250 int regno = REGNO (avoid_return_reg);
5252 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
5255 for (r = regno; r < regno + nregs; r++)
5256 if (spill_reg_order[r] >= 0)
5257 SET_HARD_REG_BIT (reload_reg_used, r);
5259 #endif /* SMALL_REGISTER_CLASSES */
5261 /* In order to be certain of getting the registers we need,
5262 we must sort the reloads into order of increasing register class.
5263 Then our grabbing of reload registers will parallel the process
5264 that provided the reload registers.
5266 Also note whether any of the reloads wants a consecutive group of regs.
5267 If so, record the maximum size of the group desired and what
5268 register class contains all the groups needed by this insn. */
5270 for (j = 0; j < n_reloads; j++)
5272 reload_order[j] = j;
5273 reload_spill_index[j] = -1;
5276 = (reload_inmode[j] == VOIDmode
5277 || (GET_MODE_SIZE (reload_outmode[j])
5278 > GET_MODE_SIZE (reload_inmode[j])))
5279 ? reload_outmode[j] : reload_inmode[j];
5281 reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]);
5283 if (reload_nregs[j] > 1)
5285 max_group_size = MAX (reload_nregs[j], max_group_size);
5286 group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class];
5289 /* If we have already decided to use a certain register,
5290 don't use it in another way. */
5291 if (reload_reg_rtx[j])
5292 mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]), reload_opnum[j],
5293 reload_when_needed[j], reload_mode[j]);
5297 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5299 bcopy ((char *) reload_reg_rtx, (char *) save_reload_reg_rtx,
5300 sizeof reload_reg_rtx);
5301 bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited);
5302 bcopy ((char *) reload_inheritance_insn,
5303 (char *) save_reload_inheritance_insn,
5304 sizeof reload_inheritance_insn);
5305 bcopy ((char *) reload_override_in, (char *) save_reload_override_in,
5306 sizeof reload_override_in);
5307 bcopy ((char *) reload_spill_index, (char *) save_reload_spill_index,
5308 sizeof reload_spill_index);
5309 COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used);
5310 COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all);
5311 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr,
5312 reload_reg_used_in_op_addr);
5314 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr_reload,
5315 reload_reg_used_in_op_addr_reload);
5317 COPY_HARD_REG_SET (save_reload_reg_used_in_insn,
5318 reload_reg_used_in_insn);
5319 COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr,
5320 reload_reg_used_in_other_addr);
5322 for (i = 0; i < reload_n_operands; i++)
5324 COPY_HARD_REG_SET (save_reload_reg_used_in_output[i],
5325 reload_reg_used_in_output[i]);
5326 COPY_HARD_REG_SET (save_reload_reg_used_in_input[i],
5327 reload_reg_used_in_input[i]);
5328 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr[i],
5329 reload_reg_used_in_input_addr[i]);
5330 COPY_HARD_REG_SET (save_reload_reg_used_in_inpaddr_addr[i],
5331 reload_reg_used_in_inpaddr_addr[i]);
5332 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr[i],
5333 reload_reg_used_in_output_addr[i]);
5334 COPY_HARD_REG_SET (save_reload_reg_used_in_outaddr_addr[i],
5335 reload_reg_used_in_outaddr_addr[i]);
5338 /* If -O, try first with inheritance, then turning it off.
5339 If not -O, don't do inheritance.
5340 Using inheritance when not optimizing leads to paradoxes
5341 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5342 because one side of the comparison might be inherited. */
5344 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5346 /* Process the reloads in order of preference just found.
5347 Beyond this point, subregs can be found in reload_reg_rtx.
5349 This used to look for an existing reloaded home for all
5350 of the reloads, and only then perform any new reloads.
5351 But that could lose if the reloads were done out of reg-class order
5352 because a later reload with a looser constraint might have an old
5353 home in a register needed by an earlier reload with a tighter constraint.
5355 To solve this, we make two passes over the reloads, in the order
5356 described above. In the first pass we try to inherit a reload
5357 from a previous insn. If there is a later reload that needs a
5358 class that is a proper subset of the class being processed, we must
5359 also allocate a spill register during the first pass.
5361 Then make a second pass over the reloads to allocate any reloads
5362 that haven't been given registers yet. */
5364 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5366 for (j = 0; j < n_reloads; j++)
5368 register int r = reload_order[j];
5370 /* Ignore reloads that got marked inoperative. */
5371 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
5374 /* If find_reloads chose a to use reload_in or reload_out as a reload
5375 register, we don't need to chose one. Otherwise, try even if it found
5376 one since we might save an insn if we find the value lying around. */
5377 if (reload_in[r] != 0 && reload_reg_rtx[r] != 0
5378 && (rtx_equal_p (reload_in[r], reload_reg_rtx[r])
5379 || rtx_equal_p (reload_out[r], reload_reg_rtx[r])))
5382 #if 0 /* No longer needed for correct operation.
5383 It might give better code, or might not; worth an experiment? */
5384 /* If this is an optional reload, we can't inherit from earlier insns
5385 until we are sure that any non-optional reloads have been allocated.
5386 The following code takes advantage of the fact that optional reloads
5387 are at the end of reload_order. */
5388 if (reload_optional[r] != 0)
5389 for (i = 0; i < j; i++)
5390 if ((reload_out[reload_order[i]] != 0
5391 || reload_in[reload_order[i]] != 0
5392 || reload_secondary_p[reload_order[i]])
5393 && ! reload_optional[reload_order[i]]
5394 && reload_reg_rtx[reload_order[i]] == 0)
5395 allocate_reload_reg (reload_order[i], insn, 0, inheritance);
5398 /* First see if this pseudo is already available as reloaded
5399 for a previous insn. We cannot try to inherit for reloads
5400 that are smaller than the maximum number of registers needed
5401 for groups unless the register we would allocate cannot be used
5404 We could check here to see if this is a secondary reload for
5405 an object that is already in a register of the desired class.
5406 This would avoid the need for the secondary reload register.
5407 But this is complex because we can't easily determine what
5408 objects might want to be loaded via this reload. So let a register
5409 be allocated here. In `emit_reload_insns' we suppress one of the
5410 loads in the case described above. */
5414 register int regno = -1;
5415 enum machine_mode mode;
5417 if (reload_in[r] == 0)
5419 else if (GET_CODE (reload_in[r]) == REG)
5421 regno = REGNO (reload_in[r]);
5422 mode = GET_MODE (reload_in[r]);
5424 else if (GET_CODE (reload_in_reg[r]) == REG)
5426 regno = REGNO (reload_in_reg[r]);
5427 mode = GET_MODE (reload_in_reg[r]);
5430 /* This won't work, since REGNO can be a pseudo reg number.
5431 Also, it takes much more hair to keep track of all the things
5432 that can invalidate an inherited reload of part of a pseudoreg. */
5433 else if (GET_CODE (reload_in[r]) == SUBREG
5434 && GET_CODE (SUBREG_REG (reload_in[r])) == REG)
5435 regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]);
5438 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5440 i = spill_reg_order[REGNO (reg_last_reload_reg[regno])];
5442 if (reg_reloaded_contents[i] == regno
5443 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno]))
5444 >= GET_MODE_SIZE (mode))
5445 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
5446 && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5448 && (reload_nregs[r] == max_group_size
5449 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5451 && reload_reg_free_p (spill_regs[i], reload_opnum[r],
5452 reload_when_needed[r])
5453 && reload_reg_free_before_p (spill_regs[i],
5455 reload_when_needed[r]))
5457 /* If a group is needed, verify that all the subsequent
5458 registers still have their values intact. */
5460 = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
5463 for (k = 1; k < nr; k++)
5464 if (reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
5472 /* We found a register that contains the
5473 value we need. If this register is the
5474 same as an `earlyclobber' operand of the
5475 current insn, just mark it as a place to
5476 reload from since we can't use it as the
5477 reload register itself. */
5479 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5480 if (reg_overlap_mentioned_for_reload_p
5481 (reg_last_reload_reg[regno],
5482 reload_earlyclobbers[i1]))
5485 if (i1 != n_earlyclobbers
5486 /* Don't really use the inherited spill reg
5487 if we need it wider than we've got it. */
5488 || (GET_MODE_SIZE (reload_mode[r])
5489 > GET_MODE_SIZE (mode)))
5490 reload_override_in[r] = reg_last_reload_reg[regno];
5494 /* We can use this as a reload reg. */
5495 /* Mark the register as in use for this part of
5497 mark_reload_reg_in_use (spill_regs[i],
5499 reload_when_needed[r],
5501 reload_reg_rtx[r] = reg_last_reload_reg[regno];
5502 reload_inherited[r] = 1;
5503 reload_inheritance_insn[r]
5504 = reg_reloaded_insn[i];
5505 reload_spill_index[r] = i;
5506 for (k = 0; k < nr; k++)
5507 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5515 /* Here's another way to see if the value is already lying around. */
5517 && reload_in[r] != 0
5518 && ! reload_inherited[r]
5519 && reload_out[r] == 0
5520 && (CONSTANT_P (reload_in[r])
5521 || GET_CODE (reload_in[r]) == PLUS
5522 || GET_CODE (reload_in[r]) == REG
5523 || GET_CODE (reload_in[r]) == MEM)
5524 && (reload_nregs[r] == max_group_size
5525 || ! reg_classes_intersect_p (reload_reg_class[r], group_class)))
5528 = find_equiv_reg (reload_in[r], insn, reload_reg_class[r],
5529 -1, NULL_PTR, 0, reload_mode[r]);
5534 if (GET_CODE (equiv) == REG)
5535 regno = REGNO (equiv);
5536 else if (GET_CODE (equiv) == SUBREG)
5538 /* This must be a SUBREG of a hard register.
5539 Make a new REG since this might be used in an
5540 address and not all machines support SUBREGs
5542 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
5543 equiv = gen_rtx (REG, reload_mode[r], regno);
5549 /* If we found a spill reg, reject it unless it is free
5550 and of the desired class. */
5552 && ((spill_reg_order[regno] >= 0
5553 && ! reload_reg_free_before_p (regno, reload_opnum[r],
5554 reload_when_needed[r]))
5555 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5559 if (equiv != 0 && TEST_HARD_REG_BIT (reload_reg_used_at_all, regno))
5562 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5565 /* We found a register that contains the value we need.
5566 If this register is the same as an `earlyclobber' operand
5567 of the current insn, just mark it as a place to reload from
5568 since we can't use it as the reload register itself. */
5571 for (i = 0; i < n_earlyclobbers; i++)
5572 if (reg_overlap_mentioned_for_reload_p (equiv,
5573 reload_earlyclobbers[i]))
5575 reload_override_in[r] = equiv;
5580 /* JRV: If the equiv register we have found is
5581 explicitly clobbered in the current insn, mark but
5582 don't use, as above. */
5584 if (equiv != 0 && regno_clobbered_p (regno, insn))
5586 reload_override_in[r] = equiv;
5590 /* If we found an equivalent reg, say no code need be generated
5591 to load it, and use it as our reload reg. */
5592 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5594 int nr = HARD_REGNO_NREGS (regno, reload_mode[r]);
5596 reload_reg_rtx[r] = equiv;
5597 reload_inherited[r] = 1;
5599 /* If any of the hard registers in EQUIV are spill
5600 registers, mark them as in use for this insn. */
5601 for (k = 0; k < nr; k++)
5603 i = spill_reg_order[regno + k];
5606 mark_reload_reg_in_use (regno, reload_opnum[r],
5607 reload_when_needed[r],
5609 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5616 /* If we found a register to use already, or if this is an optional
5617 reload, we are done. */
5618 if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0)
5621 #if 0 /* No longer needed for correct operation. Might or might not
5622 give better code on the average. Want to experiment? */
5624 /* See if there is a later reload that has a class different from our
5625 class that intersects our class or that requires less register
5626 than our reload. If so, we must allocate a register to this
5627 reload now, since that reload might inherit a previous reload
5628 and take the only available register in our class. Don't do this
5629 for optional reloads since they will force all previous reloads
5630 to be allocated. Also don't do this for reloads that have been
5633 for (i = j + 1; i < n_reloads; i++)
5635 int s = reload_order[i];
5637 if ((reload_in[s] == 0 && reload_out[s] == 0
5638 && ! reload_secondary_p[s])
5639 || reload_optional[s])
5642 if ((reload_reg_class[s] != reload_reg_class[r]
5643 && reg_classes_intersect_p (reload_reg_class[r],
5644 reload_reg_class[s]))
5645 || reload_nregs[s] < reload_nregs[r])
5652 allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance);
5656 /* Now allocate reload registers for anything non-optional that
5657 didn't get one yet. */
5658 for (j = 0; j < n_reloads; j++)
5660 register int r = reload_order[j];
5662 /* Ignore reloads that got marked inoperative. */
5663 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
5666 /* Skip reloads that already have a register allocated or are
5668 if (reload_reg_rtx[r] != 0 || reload_optional[r])
5671 if (! allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance))
5675 /* If that loop got all the way, we have won. */
5680 /* Loop around and try without any inheritance. */
5681 /* First undo everything done by the failed attempt
5682 to allocate with inheritance. */
5683 bcopy ((char *) save_reload_reg_rtx, (char *) reload_reg_rtx,
5684 sizeof reload_reg_rtx);
5685 bcopy ((char *) save_reload_inherited, (char *) reload_inherited,
5686 sizeof reload_inherited);
5687 bcopy ((char *) save_reload_inheritance_insn,
5688 (char *) reload_inheritance_insn,
5689 sizeof reload_inheritance_insn);
5690 bcopy ((char *) save_reload_override_in, (char *) reload_override_in,
5691 sizeof reload_override_in);
5692 bcopy ((char *) save_reload_spill_index, (char *) reload_spill_index,
5693 sizeof reload_spill_index);
5694 COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used);
5695 COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all);
5696 COPY_HARD_REG_SET (reload_reg_used_in_op_addr,
5697 save_reload_reg_used_in_op_addr);
5698 COPY_HARD_REG_SET (reload_reg_used_in_op_addr_reload,
5699 save_reload_reg_used_in_op_addr_reload);
5700 COPY_HARD_REG_SET (reload_reg_used_in_insn,
5701 save_reload_reg_used_in_insn);
5702 COPY_HARD_REG_SET (reload_reg_used_in_other_addr,
5703 save_reload_reg_used_in_other_addr);
5705 for (i = 0; i < reload_n_operands; i++)
5707 COPY_HARD_REG_SET (reload_reg_used_in_input[i],
5708 save_reload_reg_used_in_input[i]);
5709 COPY_HARD_REG_SET (reload_reg_used_in_output[i],
5710 save_reload_reg_used_in_output[i]);
5711 COPY_HARD_REG_SET (reload_reg_used_in_input_addr[i],
5712 save_reload_reg_used_in_input_addr[i]);
5713 COPY_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i],
5714 save_reload_reg_used_in_inpaddr_addr[i]);
5715 COPY_HARD_REG_SET (reload_reg_used_in_output_addr[i],
5716 save_reload_reg_used_in_output_addr[i]);
5717 COPY_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i],
5718 save_reload_reg_used_in_outaddr_addr[i]);
5722 /* If we thought we could inherit a reload, because it seemed that
5723 nothing else wanted the same reload register earlier in the insn,
5724 verify that assumption, now that all reloads have been assigned. */
5726 for (j = 0; j < n_reloads; j++)
5728 register int r = reload_order[j];
5730 if (reload_inherited[r] && reload_reg_rtx[r] != 0
5731 && ! reload_reg_free_before_p (true_regnum (reload_reg_rtx[r]),
5733 reload_when_needed[r]))
5734 reload_inherited[r] = 0;
5736 /* If we found a better place to reload from,
5737 validate it in the same fashion, if it is a reload reg. */
5738 if (reload_override_in[r]
5739 && (GET_CODE (reload_override_in[r]) == REG
5740 || GET_CODE (reload_override_in[r]) == SUBREG))
5742 int regno = true_regnum (reload_override_in[r]);
5743 if (spill_reg_order[regno] >= 0
5744 && ! reload_reg_free_before_p (regno, reload_opnum[r],
5745 reload_when_needed[r]))
5746 reload_override_in[r] = 0;
5750 /* Now that reload_override_in is known valid,
5751 actually override reload_in. */
5752 for (j = 0; j < n_reloads; j++)
5753 if (reload_override_in[j])
5754 reload_in[j] = reload_override_in[j];
5756 /* If this reload won't be done because it has been cancelled or is
5757 optional and not inherited, clear reload_reg_rtx so other
5758 routines (such as subst_reloads) don't get confused. */
5759 for (j = 0; j < n_reloads; j++)
5760 if (reload_reg_rtx[j] != 0
5761 && ((reload_optional[j] && ! reload_inherited[j])
5762 || (reload_in[j] == 0 && reload_out[j] == 0
5763 && ! reload_secondary_p[j])))
5765 int regno = true_regnum (reload_reg_rtx[j]);
5767 if (spill_reg_order[regno] >= 0)
5768 clear_reload_reg_in_use (regno, reload_opnum[j],
5769 reload_when_needed[j], reload_mode[j]);
5770 reload_reg_rtx[j] = 0;
5773 /* Record which pseudos and which spill regs have output reloads. */
5774 for (j = 0; j < n_reloads; j++)
5776 register int r = reload_order[j];
5778 i = reload_spill_index[r];
5780 /* I is nonneg if this reload used one of the spill regs.
5781 If reload_reg_rtx[r] is 0, this is an optional reload
5782 that we opted to ignore. */
5783 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG
5784 && reload_reg_rtx[r] != 0)
5786 register int nregno = REGNO (reload_out[r]);
5789 if (nregno < FIRST_PSEUDO_REGISTER)
5790 nr = HARD_REGNO_NREGS (nregno, reload_mode[r]);
5793 reg_has_output_reload[nregno + nr] = 1;
5797 nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
5799 SET_HARD_REG_BIT (reg_is_output_reload, spill_regs[i] + nr);
5802 if (reload_when_needed[r] != RELOAD_OTHER
5803 && reload_when_needed[r] != RELOAD_FOR_OUTPUT
5804 && reload_when_needed[r] != RELOAD_FOR_INSN)
5810 /* If SMALL_REGISTER_CLASSES are defined, we may not have merged two
5811 reloads of the same item for fear that we might not have enough reload
5812 registers. However, normally they will get the same reload register
5813 and hence actually need not be loaded twice.
5815 Here we check for the most common case of this phenomenon: when we have
5816 a number of reloads for the same object, each of which were allocated
5817 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5818 reload, and is not modified in the insn itself. If we find such,
5819 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5820 This will not increase the number of spill registers needed and will
5821 prevent redundant code. */
5823 #ifdef SMALL_REGISTER_CLASSES
5826 merge_assigned_reloads (insn)
5831 /* Scan all the reloads looking for ones that only load values and
5832 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5833 assigned and not modified by INSN. */
5835 for (i = 0; i < n_reloads; i++)
5837 if (reload_in[i] == 0 || reload_when_needed[i] == RELOAD_OTHER
5838 || reload_out[i] != 0 || reload_reg_rtx[i] == 0
5839 || reg_set_p (reload_reg_rtx[i], insn))
5842 /* Look at all other reloads. Ensure that the only use of this
5843 reload_reg_rtx is in a reload that just loads the same value
5844 as we do. Note that any secondary reloads must be of the identical
5845 class since the values, modes, and result registers are the
5846 same, so we need not do anything with any secondary reloads. */
5848 for (j = 0; j < n_reloads; j++)
5850 if (i == j || reload_reg_rtx[j] == 0
5851 || ! reg_overlap_mentioned_p (reload_reg_rtx[j],
5855 /* If the reload regs aren't exactly the same (e.g, different modes)
5856 or if the values are different, we can't merge anything with this
5859 if (! rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
5860 || reload_out[j] != 0 || reload_in[j] == 0
5861 || ! rtx_equal_p (reload_in[i], reload_in[j]))
5865 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5866 we, in fact, found any matching reloads. */
5870 for (j = 0; j < n_reloads; j++)
5871 if (i != j && reload_reg_rtx[j] != 0
5872 && rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j]))
5874 reload_when_needed[i] = RELOAD_OTHER;
5876 transfer_replacements (i, j);
5879 /* If this is now RELOAD_OTHER, look for any reloads that load
5880 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
5881 if they were for inputs, RELOAD_OTHER for outputs. Note that
5882 this test is equivalent to looking for reloads for this operand
5885 if (reload_when_needed[i] == RELOAD_OTHER)
5886 for (j = 0; j < n_reloads; j++)
5887 if (reload_in[j] != 0
5888 && reload_when_needed[i] != RELOAD_OTHER
5889 && reg_overlap_mentioned_for_reload_p (reload_in[j],
5891 reload_when_needed[j]
5892 = ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS
5893 || reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS)
5894 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
5898 #endif /* SMALL_RELOAD_CLASSES */
5900 /* Output insns to reload values in and out of the chosen reload regs. */
5903 emit_reload_insns (insn)
5907 rtx input_reload_insns[MAX_RECOG_OPERANDS];
5908 rtx other_input_address_reload_insns = 0;
5909 rtx other_input_reload_insns = 0;
5910 rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
5911 rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
5912 rtx output_reload_insns[MAX_RECOG_OPERANDS];
5913 rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
5914 rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
5915 rtx operand_reload_insns = 0;
5916 rtx other_operand_reload_insns = 0;
5917 rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
5918 rtx following_insn = NEXT_INSN (insn);
5919 rtx before_insn = insn;
5921 /* Values to be put in spill_reg_store are put here first. */
5922 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
5924 for (j = 0; j < reload_n_operands; j++)
5925 input_reload_insns[j] = input_address_reload_insns[j]
5926 = inpaddr_address_reload_insns[j]
5927 = output_reload_insns[j] = output_address_reload_insns[j]
5928 = outaddr_address_reload_insns[j]
5929 = other_output_reload_insns[j] = 0;
5931 /* Now output the instructions to copy the data into and out of the
5932 reload registers. Do these in the order that the reloads were reported,
5933 since reloads of base and index registers precede reloads of operands
5934 and the operands may need the base and index registers reloaded. */
5936 for (j = 0; j < n_reloads; j++)
5939 rtx oldequiv_reg = 0;
5940 rtx this_reload_insn = 0;
5942 if (reload_spill_index[j] >= 0)
5943 new_spill_reg_store[reload_spill_index[j]] = 0;
5946 if (old != 0 && ! reload_inherited[j]
5947 && ! rtx_equal_p (reload_reg_rtx[j], old)
5948 && reload_reg_rtx[j] != 0)
5950 register rtx reloadreg = reload_reg_rtx[j];
5952 enum machine_mode mode;
5955 /* Determine the mode to reload in.
5956 This is very tricky because we have three to choose from.
5957 There is the mode the insn operand wants (reload_inmode[J]).
5958 There is the mode of the reload register RELOADREG.
5959 There is the intrinsic mode of the operand, which we could find
5960 by stripping some SUBREGs.
5961 It turns out that RELOADREG's mode is irrelevant:
5962 we can change that arbitrarily.
5964 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
5965 then the reload reg may not support QImode moves, so use SImode.
5966 If foo is in memory due to spilling a pseudo reg, this is safe,
5967 because the QImode value is in the least significant part of a
5968 slot big enough for a SImode. If foo is some other sort of
5969 memory reference, then it is impossible to reload this case,
5970 so previous passes had better make sure this never happens.
5972 Then consider a one-word union which has SImode and one of its
5973 members is a float, being fetched as (SUBREG:SF union:SI).
5974 We must fetch that as SFmode because we could be loading into
5975 a float-only register. In this case OLD's mode is correct.
5977 Consider an immediate integer: it has VOIDmode. Here we need
5978 to get a mode from something else.
5980 In some cases, there is a fourth mode, the operand's
5981 containing mode. If the insn specifies a containing mode for
5982 this operand, it overrides all others.
5984 I am not sure whether the algorithm here is always right,
5985 but it does the right things in those cases. */
5987 mode = GET_MODE (old);
5988 if (mode == VOIDmode)
5989 mode = reload_inmode[j];
5991 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5992 /* If we need a secondary register for this operation, see if
5993 the value is already in a register in that class. Don't
5994 do this if the secondary register will be used as a scratch
5997 if (reload_secondary_in_reload[j] >= 0
5998 && reload_secondary_in_icode[j] == CODE_FOR_nothing
6001 = find_equiv_reg (old, insn,
6002 reload_reg_class[reload_secondary_in_reload[j]],
6003 -1, NULL_PTR, 0, mode);
6006 /* If reloading from memory, see if there is a register
6007 that already holds the same value. If so, reload from there.
6008 We can pass 0 as the reload_reg_p argument because
6009 any other reload has either already been emitted,
6010 in which case find_equiv_reg will see the reload-insn,
6011 or has yet to be emitted, in which case it doesn't matter
6012 because we will use this equiv reg right away. */
6014 if (oldequiv == 0 && optimize
6015 && (GET_CODE (old) == MEM
6016 || (GET_CODE (old) == REG
6017 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6018 && reg_renumber[REGNO (old)] < 0)))
6019 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
6020 -1, NULL_PTR, 0, mode);
6024 int regno = true_regnum (oldequiv);
6026 /* If OLDEQUIV is a spill register, don't use it for this
6027 if any other reload needs it at an earlier stage of this insn
6028 or at this stage. */
6029 if (spill_reg_order[regno] >= 0
6030 && (! reload_reg_free_p (regno, reload_opnum[j],
6031 reload_when_needed[j])
6032 || ! reload_reg_free_before_p (regno, reload_opnum[j],
6033 reload_when_needed[j])))
6036 /* If OLDEQUIV is not a spill register,
6037 don't use it if any other reload wants it. */
6038 if (spill_reg_order[regno] < 0)
6041 for (k = 0; k < n_reloads; k++)
6042 if (reload_reg_rtx[k] != 0 && k != j
6043 && reg_overlap_mentioned_for_reload_p (reload_reg_rtx[k],
6051 /* If it is no cheaper to copy from OLDEQUIV into the
6052 reload register than it would be to move from memory,
6053 don't use it. Likewise, if we need a secondary register
6057 && ((REGNO_REG_CLASS (regno) != reload_reg_class[j]
6058 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
6059 reload_reg_class[j])
6060 >= MEMORY_MOVE_COST (mode)))
6061 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6062 || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6066 #ifdef SECONDARY_MEMORY_NEEDED
6067 || SECONDARY_MEMORY_NEEDED (reload_reg_class[j],
6068 REGNO_REG_CLASS (regno),
6077 else if (GET_CODE (oldequiv) == REG)
6078 oldequiv_reg = oldequiv;
6079 else if (GET_CODE (oldequiv) == SUBREG)
6080 oldequiv_reg = SUBREG_REG (oldequiv);
6082 /* If we are reloading from a register that was recently stored in
6083 with an output-reload, see if we can prove there was
6084 actually no need to store the old value in it. */
6086 if (optimize && GET_CODE (oldequiv) == REG
6087 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6088 && spill_reg_order[REGNO (oldequiv)] >= 0
6089 && spill_reg_store[spill_reg_order[REGNO (oldequiv)]] != 0
6090 && find_reg_note (insn, REG_DEAD, reload_in[j])
6091 /* This is unsafe if operand occurs more than once in current
6092 insn. Perhaps some occurrences weren't reloaded. */
6093 && count_occurrences (PATTERN (insn), reload_in[j]) == 1)
6094 delete_output_reload
6095 (insn, j, spill_reg_store[spill_reg_order[REGNO (oldequiv)]]);
6097 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6098 then load RELOADREG from OLDEQUIV. Note that we cannot use
6099 gen_lowpart_common since it can do the wrong thing when
6100 RELOADREG has a multi-word mode. Note that RELOADREG
6101 must always be a REG here. */
6103 if (GET_MODE (reloadreg) != mode)
6104 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
6105 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6106 oldequiv = SUBREG_REG (oldequiv);
6107 if (GET_MODE (oldequiv) != VOIDmode
6108 && mode != GET_MODE (oldequiv))
6109 oldequiv = gen_rtx (SUBREG, mode, oldequiv, 0);
6111 /* Switch to the right place to emit the reload insns. */
6112 switch (reload_when_needed[j])
6115 where = &other_input_reload_insns;
6117 case RELOAD_FOR_INPUT:
6118 where = &input_reload_insns[reload_opnum[j]];
6120 case RELOAD_FOR_INPUT_ADDRESS:
6121 where = &input_address_reload_insns[reload_opnum[j]];
6123 case RELOAD_FOR_INPADDR_ADDRESS:
6124 where = &inpaddr_address_reload_insns[reload_opnum[j]];
6126 case RELOAD_FOR_OUTPUT_ADDRESS:
6127 where = &output_address_reload_insns[reload_opnum[j]];
6129 case RELOAD_FOR_OUTADDR_ADDRESS:
6130 where = &outaddr_address_reload_insns[reload_opnum[j]];
6132 case RELOAD_FOR_OPERAND_ADDRESS:
6133 where = &operand_reload_insns;
6135 case RELOAD_FOR_OPADDR_ADDR:
6136 where = &other_operand_reload_insns;
6138 case RELOAD_FOR_OTHER_ADDRESS:
6139 where = &other_input_address_reload_insns;
6145 push_to_sequence (*where);
6148 /* Auto-increment addresses must be reloaded in a special way. */
6149 if (GET_CODE (oldequiv) == POST_INC
6150 || GET_CODE (oldequiv) == POST_DEC
6151 || GET_CODE (oldequiv) == PRE_INC
6152 || GET_CODE (oldequiv) == PRE_DEC)
6154 /* We are not going to bother supporting the case where a
6155 incremented register can't be copied directly from
6156 OLDEQUIV since this seems highly unlikely. */
6157 if (reload_secondary_in_reload[j] >= 0)
6159 /* Prevent normal processing of this reload. */
6161 /* Output a special code sequence for this case. */
6162 inc_for_reload (reloadreg, oldequiv, reload_inc[j]);
6165 /* If we are reloading a pseudo-register that was set by the previous
6166 insn, see if we can get rid of that pseudo-register entirely
6167 by redirecting the previous insn into our reload register. */
6169 else if (optimize && GET_CODE (old) == REG
6170 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6171 && dead_or_set_p (insn, old)
6172 /* This is unsafe if some other reload
6173 uses the same reg first. */
6174 && reload_reg_free_before_p (REGNO (reloadreg),
6176 reload_when_needed[j]))
6178 rtx temp = PREV_INSN (insn);
6179 while (temp && GET_CODE (temp) == NOTE)
6180 temp = PREV_INSN (temp);
6182 && GET_CODE (temp) == INSN
6183 && GET_CODE (PATTERN (temp)) == SET
6184 && SET_DEST (PATTERN (temp)) == old
6185 /* Make sure we can access insn_operand_constraint. */
6186 && asm_noperands (PATTERN (temp)) < 0
6187 /* This is unsafe if prev insn rejects our reload reg. */
6188 && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0],
6190 /* This is unsafe if operand occurs more than once in current
6191 insn. Perhaps some occurrences aren't reloaded. */
6192 && count_occurrences (PATTERN (insn), old) == 1
6193 /* Don't risk splitting a matching pair of operands. */
6194 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6196 /* Store into the reload register instead of the pseudo. */
6197 SET_DEST (PATTERN (temp)) = reloadreg;
6198 /* If these are the only uses of the pseudo reg,
6199 pretend for GDB it lives in the reload reg we used. */
6200 if (reg_n_deaths[REGNO (old)] == 1
6201 && reg_n_sets[REGNO (old)] == 1)
6203 reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]);
6204 alter_reg (REGNO (old), -1);
6210 /* We can't do that, so output an insn to load RELOADREG. */
6214 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6215 rtx second_reload_reg = 0;
6216 enum insn_code icode;
6218 /* If we have a secondary reload, pick up the secondary register
6219 and icode, if any. If OLDEQUIV and OLD are different or
6220 if this is an in-out reload, recompute whether or not we
6221 still need a secondary register and what the icode should
6222 be. If we still need a secondary register and the class or
6223 icode is different, go back to reloading from OLD if using
6224 OLDEQUIV means that we got the wrong type of register. We
6225 cannot have different class or icode due to an in-out reload
6226 because we don't make such reloads when both the input and
6227 output need secondary reload registers. */
6229 if (reload_secondary_in_reload[j] >= 0)
6231 int secondary_reload = reload_secondary_in_reload[j];
6232 rtx real_oldequiv = oldequiv;
6235 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6236 and similarly for OLD.
6237 See comments in get_secondary_reload in reload.c. */
6238 if (GET_CODE (oldequiv) == REG
6239 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6240 && reg_equiv_mem[REGNO (oldequiv)] != 0)
6241 real_oldequiv = reg_equiv_mem[REGNO (oldequiv)];
6243 if (GET_CODE (old) == REG
6244 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6245 && reg_equiv_mem[REGNO (old)] != 0)
6246 real_old = reg_equiv_mem[REGNO (old)];
6248 second_reload_reg = reload_reg_rtx[secondary_reload];
6249 icode = reload_secondary_in_icode[j];
6251 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6252 || (reload_in[j] != 0 && reload_out[j] != 0))
6254 enum reg_class new_class
6255 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6256 mode, real_oldequiv);
6258 if (new_class == NO_REGS)
6259 second_reload_reg = 0;
6262 enum insn_code new_icode;
6263 enum machine_mode new_mode;
6265 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6266 REGNO (second_reload_reg)))
6267 oldequiv = old, real_oldequiv = real_old;
6270 new_icode = reload_in_optab[(int) mode];
6271 if (new_icode != CODE_FOR_nothing
6272 && ((insn_operand_predicate[(int) new_icode][0]
6273 && ! ((*insn_operand_predicate[(int) new_icode][0])
6275 || (insn_operand_predicate[(int) new_icode][1]
6276 && ! ((*insn_operand_predicate[(int) new_icode][1])
6277 (real_oldequiv, mode)))))
6278 new_icode = CODE_FOR_nothing;
6280 if (new_icode == CODE_FOR_nothing)
6283 new_mode = insn_operand_mode[(int) new_icode][2];
6285 if (GET_MODE (second_reload_reg) != new_mode)
6287 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6289 oldequiv = old, real_oldequiv = real_old;
6292 = gen_rtx (REG, new_mode,
6293 REGNO (second_reload_reg));
6299 /* If we still need a secondary reload register, check
6300 to see if it is being used as a scratch or intermediate
6301 register and generate code appropriately. If we need
6302 a scratch register, use REAL_OLDEQUIV since the form of
6303 the insn may depend on the actual address if it is
6306 if (second_reload_reg)
6308 if (icode != CODE_FOR_nothing)
6310 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6311 second_reload_reg));
6316 /* See if we need a scratch register to load the
6317 intermediate register (a tertiary reload). */
6318 enum insn_code tertiary_icode
6319 = reload_secondary_in_icode[secondary_reload];
6321 if (tertiary_icode != CODE_FOR_nothing)
6323 rtx third_reload_reg
6324 = reload_reg_rtx[reload_secondary_in_reload[secondary_reload]];
6326 emit_insn ((GEN_FCN (tertiary_icode)
6327 (second_reload_reg, real_oldequiv,
6328 third_reload_reg)));
6331 gen_reload (second_reload_reg, oldequiv,
6333 reload_when_needed[j]);
6335 oldequiv = second_reload_reg;
6341 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6342 gen_reload (reloadreg, oldequiv, reload_opnum[j],
6343 reload_when_needed[j]);
6345 #if defined(SECONDARY_INPUT_RELOAD_CLASS) && defined(PRESERVE_DEATH_INFO_REGNO_P)
6346 /* We may have to make a REG_DEAD note for the secondary reload
6347 register in the insns we just made. Find the last insn that
6348 mentioned the register. */
6349 if (! special && second_reload_reg
6350 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reload_reg)))
6354 for (prev = get_last_insn (); prev;
6355 prev = PREV_INSN (prev))
6356 if (GET_RTX_CLASS (GET_CODE (prev) == 'i')
6357 && reg_overlap_mentioned_for_reload_p (second_reload_reg,
6360 REG_NOTES (prev) = gen_rtx (EXPR_LIST, REG_DEAD,
6369 this_reload_insn = get_last_insn ();
6370 /* End this sequence. */
6371 *where = get_insns ();
6375 /* Add a note saying the input reload reg
6376 dies in this insn, if anyone cares. */
6377 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6379 && reload_reg_rtx[j] != old
6380 && reload_reg_rtx[j] != 0
6381 && reload_out[j] == 0
6382 && ! reload_inherited[j]
6383 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j])))
6385 register rtx reloadreg = reload_reg_rtx[j];
6388 /* We can't abort here because we need to support this for sched.c.
6389 It's not terrible to miss a REG_DEAD note, but we should try
6390 to figure out how to do this correctly. */
6391 /* The code below is incorrect for address-only reloads. */
6392 if (reload_when_needed[j] != RELOAD_OTHER
6393 && reload_when_needed[j] != RELOAD_FOR_INPUT)
6397 /* Add a death note to this insn, for an input reload. */
6399 if ((reload_when_needed[j] == RELOAD_OTHER
6400 || reload_when_needed[j] == RELOAD_FOR_INPUT)
6401 && ! dead_or_set_p (insn, reloadreg))
6403 = gen_rtx (EXPR_LIST, REG_DEAD,
6404 reloadreg, REG_NOTES (insn));
6407 /* When we inherit a reload, the last marked death of the reload reg
6408 may no longer really be a death. */
6409 if (reload_reg_rtx[j] != 0
6410 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j]))
6411 && reload_inherited[j])
6413 /* Handle inheriting an output reload.
6414 Remove the death note from the output reload insn. */
6415 if (reload_spill_index[j] >= 0
6416 && GET_CODE (reload_in[j]) == REG
6417 && spill_reg_store[reload_spill_index[j]] != 0
6418 && find_regno_note (spill_reg_store[reload_spill_index[j]],
6419 REG_DEAD, REGNO (reload_reg_rtx[j])))
6420 remove_death (REGNO (reload_reg_rtx[j]),
6421 spill_reg_store[reload_spill_index[j]]);
6422 /* Likewise for input reloads that were inherited. */
6423 else if (reload_spill_index[j] >= 0
6424 && GET_CODE (reload_in[j]) == REG
6425 && spill_reg_store[reload_spill_index[j]] == 0
6426 && reload_inheritance_insn[j] != 0
6427 && find_regno_note (reload_inheritance_insn[j], REG_DEAD,
6428 REGNO (reload_reg_rtx[j])))
6429 remove_death (REGNO (reload_reg_rtx[j]),
6430 reload_inheritance_insn[j]);
6435 /* We got this register from find_equiv_reg.
6436 Search back for its last death note and get rid of it.
6437 But don't search back too far.
6438 Don't go past a place where this reg is set,
6439 since a death note before that remains valid. */
6440 for (prev = PREV_INSN (insn);
6441 prev && GET_CODE (prev) != CODE_LABEL;
6442 prev = PREV_INSN (prev))
6443 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
6444 && dead_or_set_p (prev, reload_reg_rtx[j]))
6446 if (find_regno_note (prev, REG_DEAD,
6447 REGNO (reload_reg_rtx[j])))
6448 remove_death (REGNO (reload_reg_rtx[j]), prev);
6454 /* We might have used find_equiv_reg above to choose an alternate
6455 place from which to reload. If so, and it died, we need to remove
6456 that death and move it to one of the insns we just made. */
6458 if (oldequiv_reg != 0
6459 && PRESERVE_DEATH_INFO_REGNO_P (true_regnum (oldequiv_reg)))
6463 for (prev = PREV_INSN (insn); prev && GET_CODE (prev) != CODE_LABEL;
6464 prev = PREV_INSN (prev))
6465 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
6466 && dead_or_set_p (prev, oldequiv_reg))
6468 if (find_regno_note (prev, REG_DEAD, REGNO (oldequiv_reg)))
6470 for (prev1 = this_reload_insn;
6471 prev1; prev1 = PREV_INSN (prev1))
6472 if (GET_RTX_CLASS (GET_CODE (prev1) == 'i')
6473 && reg_overlap_mentioned_for_reload_p (oldequiv_reg,
6476 REG_NOTES (prev1) = gen_rtx (EXPR_LIST, REG_DEAD,
6481 remove_death (REGNO (oldequiv_reg), prev);
6488 /* If we are reloading a register that was recently stored in with an
6489 output-reload, see if we can prove there was
6490 actually no need to store the old value in it. */
6492 if (optimize && reload_inherited[j] && reload_spill_index[j] >= 0
6493 && reload_in[j] != 0
6494 && GET_CODE (reload_in[j]) == REG
6496 /* There doesn't seem to be any reason to restrict this to pseudos
6497 and doing so loses in the case where we are copying from a
6498 register of the wrong class. */
6499 && REGNO (reload_in[j]) >= FIRST_PSEUDO_REGISTER
6501 && spill_reg_store[reload_spill_index[j]] != 0
6502 /* This is unsafe if some other reload uses the same reg first. */
6503 && reload_reg_free_before_p (spill_regs[reload_spill_index[j]],
6504 reload_opnum[j], reload_when_needed[j])
6505 && dead_or_set_p (insn, reload_in[j])
6506 /* This is unsafe if operand occurs more than once in current
6507 insn. Perhaps some occurrences weren't reloaded. */
6508 && count_occurrences (PATTERN (insn), reload_in[j]) == 1)
6509 delete_output_reload (insn, j,
6510 spill_reg_store[reload_spill_index[j]]);
6512 /* Input-reloading is done. Now do output-reloading,
6513 storing the value from the reload-register after the main insn
6514 if reload_out[j] is nonzero.
6516 ??? At some point we need to support handling output reloads of
6517 JUMP_INSNs or insns that set cc0. */
6518 old = reload_out[j];
6520 && reload_reg_rtx[j] != old
6521 && reload_reg_rtx[j] != 0)
6523 register rtx reloadreg = reload_reg_rtx[j];
6524 register rtx second_reloadreg = 0;
6526 enum machine_mode mode;
6529 /* An output operand that dies right away does need a reload,
6530 but need not be copied from it. Show the new location in the
6532 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6533 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6535 XEXP (note, 0) = reload_reg_rtx[j];
6538 /* Likewise for a SUBREG of an operand that dies. */
6539 else if (GET_CODE (old) == SUBREG
6540 && GET_CODE (SUBREG_REG (old)) == REG
6541 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6544 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6548 else if (GET_CODE (old) == SCRATCH)
6549 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6550 but we don't want to make an output reload. */
6554 /* Strip off of OLD any size-increasing SUBREGs such as
6555 (SUBREG:SI foo:QI 0). */
6557 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
6558 && (GET_MODE_SIZE (GET_MODE (old))
6559 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
6560 old = SUBREG_REG (old);
6563 /* If is a JUMP_INSN, we can't support output reloads yet. */
6564 if (GET_CODE (insn) == JUMP_INSN)
6567 if (reload_when_needed[j] == RELOAD_OTHER)
6570 push_to_sequence (output_reload_insns[reload_opnum[j]]);
6572 /* Determine the mode to reload in.
6573 See comments above (for input reloading). */
6575 mode = GET_MODE (old);
6576 if (mode == VOIDmode)
6578 /* VOIDmode should never happen for an output. */
6579 if (asm_noperands (PATTERN (insn)) < 0)
6580 /* It's the compiler's fault. */
6581 fatal_insn ("VOIDmode on an output", insn);
6582 error_for_asm (insn, "output operand is constant in `asm'");
6583 /* Prevent crash--use something we know is valid. */
6585 old = gen_rtx (REG, mode, REGNO (reloadreg));
6588 if (GET_MODE (reloadreg) != mode)
6589 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
6591 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6593 /* If we need two reload regs, set RELOADREG to the intermediate
6594 one, since it will be stored into OLD. We might need a secondary
6595 register only for an input reload, so check again here. */
6597 if (reload_secondary_out_reload[j] >= 0)
6601 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6602 && reg_equiv_mem[REGNO (old)] != 0)
6603 real_old = reg_equiv_mem[REGNO (old)];
6605 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j],
6609 second_reloadreg = reloadreg;
6610 reloadreg = reload_reg_rtx[reload_secondary_out_reload[j]];
6612 /* See if RELOADREG is to be used as a scratch register
6613 or as an intermediate register. */
6614 if (reload_secondary_out_icode[j] != CODE_FOR_nothing)
6616 emit_insn ((GEN_FCN (reload_secondary_out_icode[j])
6617 (real_old, second_reloadreg, reloadreg)));
6622 /* See if we need both a scratch and intermediate reload
6625 int secondary_reload = reload_secondary_out_reload[j];
6626 enum insn_code tertiary_icode
6627 = reload_secondary_out_icode[secondary_reload];
6629 if (GET_MODE (reloadreg) != mode)
6630 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
6632 if (tertiary_icode != CODE_FOR_nothing)
6635 = reload_reg_rtx[reload_secondary_out_reload[secondary_reload]];
6638 /* Copy primary reload reg to secondary reload reg.
6639 (Note that these have been swapped above, then
6640 secondary reload reg to OLD using our insn. */
6642 /* If REAL_OLD is a paradoxical SUBREG, remove it
6643 and try to put the opposite SUBREG on
6645 if (GET_CODE (real_old) == SUBREG
6646 && (GET_MODE_SIZE (GET_MODE (real_old))
6647 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6648 && 0 != (tem = gen_lowpart_common
6649 (GET_MODE (SUBREG_REG (real_old)),
6651 real_old = SUBREG_REG (real_old), reloadreg = tem;
6653 gen_reload (reloadreg, second_reloadreg,
6654 reload_opnum[j], reload_when_needed[j]);
6655 emit_insn ((GEN_FCN (tertiary_icode)
6656 (real_old, reloadreg, third_reloadreg)));
6661 /* Copy between the reload regs here and then to
6664 gen_reload (reloadreg, second_reloadreg,
6665 reload_opnum[j], reload_when_needed[j]);
6671 /* Output the last reload insn. */
6673 gen_reload (old, reloadreg, reload_opnum[j],
6674 reload_when_needed[j]);
6676 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6677 /* If final will look at death notes for this reg,
6678 put one on the last output-reload insn to use it. Similarly
6679 for any secondary register. */
6680 if (PRESERVE_DEATH_INFO_REGNO_P (REGNO (reloadreg)))
6681 for (p = get_last_insn (); p; p = PREV_INSN (p))
6682 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
6683 && reg_overlap_mentioned_for_reload_p (reloadreg,
6685 REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
6686 reloadreg, REG_NOTES (p));
6688 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6689 if (! special && second_reloadreg
6690 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reloadreg)))
6691 for (p = get_last_insn (); p; p = PREV_INSN (p))
6692 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
6693 && reg_overlap_mentioned_for_reload_p (second_reloadreg,
6695 REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
6696 second_reloadreg, REG_NOTES (p));
6699 /* Look at all insns we emitted, just to be safe. */
6700 for (p = get_insns (); p; p = NEXT_INSN (p))
6701 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
6703 /* If this output reload doesn't come from a spill reg,
6704 clear any memory of reloaded copies of the pseudo reg.
6705 If this output reload comes from a spill reg,
6706 reg_has_output_reload will make this do nothing. */
6707 note_stores (PATTERN (p), forget_old_reloads_1);
6709 if (reg_mentioned_p (reload_reg_rtx[j], PATTERN (p))
6710 && reload_spill_index[j] >= 0)
6711 new_spill_reg_store[reload_spill_index[j]] = p;
6714 if (reload_when_needed[j] == RELOAD_OTHER)
6716 emit_insns (other_output_reload_insns[reload_opnum[j]]);
6717 other_output_reload_insns[reload_opnum[j]] = get_insns ();
6720 output_reload_insns[reload_opnum[j]] = get_insns ();
6726 /* Now write all the insns we made for reloads in the order expected by
6727 the allocation functions. Prior to the insn being reloaded, we write
6728 the following reloads:
6730 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6732 RELOAD_OTHER reloads.
6734 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6735 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6736 RELOAD_FOR_INPUT reload for the operand.
6738 RELOAD_FOR_OPADDR_ADDRS reloads.
6740 RELOAD_FOR_OPERAND_ADDRESS reloads.
6742 After the insn being reloaded, we write the following:
6744 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6745 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6746 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6747 reloads for the operand. The RELOAD_OTHER output reloads are
6748 output in descending order by reload number. */
6750 emit_insns_before (other_input_address_reload_insns, before_insn);
6751 emit_insns_before (other_input_reload_insns, before_insn);
6753 for (j = 0; j < reload_n_operands; j++)
6755 emit_insns_before (inpaddr_address_reload_insns[j], before_insn);
6756 emit_insns_before (input_address_reload_insns[j], before_insn);
6757 emit_insns_before (input_reload_insns[j], before_insn);
6760 emit_insns_before (other_operand_reload_insns, before_insn);
6761 emit_insns_before (operand_reload_insns, before_insn);
6763 for (j = 0; j < reload_n_operands; j++)
6765 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
6766 emit_insns_before (output_address_reload_insns[j], following_insn);
6767 emit_insns_before (output_reload_insns[j], following_insn);
6768 emit_insns_before (other_output_reload_insns[j], following_insn);
6771 /* Move death notes from INSN
6772 to output-operand-address and output reload insns. */
6773 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6776 /* Loop over those insns, last ones first. */
6777 for (insn1 = PREV_INSN (following_insn); insn1 != insn;
6778 insn1 = PREV_INSN (insn1))
6779 if (GET_CODE (insn1) == INSN && GET_CODE (PATTERN (insn1)) == SET)
6781 rtx source = SET_SRC (PATTERN (insn1));
6782 rtx dest = SET_DEST (PATTERN (insn1));
6784 /* The note we will examine next. */
6785 rtx reg_notes = REG_NOTES (insn);
6786 /* The place that pointed to this note. */
6787 rtx *prev_reg_note = ®_NOTES (insn);
6789 /* If the note is for something used in the source of this
6790 reload insn, or in the output address, move the note. */
6793 rtx next_reg_notes = XEXP (reg_notes, 1);
6794 if (REG_NOTE_KIND (reg_notes) == REG_DEAD
6795 && GET_CODE (XEXP (reg_notes, 0)) == REG
6796 && ((GET_CODE (dest) != REG
6797 && reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
6799 || reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
6802 *prev_reg_note = next_reg_notes;
6803 XEXP (reg_notes, 1) = REG_NOTES (insn1);
6804 REG_NOTES (insn1) = reg_notes;
6807 prev_reg_note = &XEXP (reg_notes, 1);
6809 reg_notes = next_reg_notes;
6815 /* For all the spill regs newly reloaded in this instruction,
6816 record what they were reloaded from, so subsequent instructions
6817 can inherit the reloads.
6819 Update spill_reg_store for the reloads of this insn.
6820 Copy the elements that were updated in the loop above. */
6822 for (j = 0; j < n_reloads; j++)
6824 register int r = reload_order[j];
6825 register int i = reload_spill_index[r];
6827 /* I is nonneg if this reload used one of the spill regs.
6828 If reload_reg_rtx[r] is 0, this is an optional reload
6829 that we opted to ignore. */
6831 if (i >= 0 && reload_reg_rtx[r] != 0)
6834 = HARD_REGNO_NREGS (spill_regs[i], GET_MODE (reload_reg_rtx[r]));
6836 int part_reaches_end = 0;
6837 int all_reaches_end = 1;
6839 /* For a multi register reload, we need to check if all or part
6840 of the value lives to the end. */
6841 for (k = 0; k < nr; k++)
6843 if (reload_reg_reaches_end_p (spill_regs[i] + k, reload_opnum[r],
6844 reload_when_needed[r]))
6845 part_reaches_end = 1;
6847 all_reaches_end = 0;
6850 /* Ignore reloads that don't reach the end of the insn in
6852 if (all_reaches_end)
6854 /* First, clear out memory of what used to be in this spill reg.
6855 If consecutive registers are used, clear them all. */
6857 for (k = 0; k < nr; k++)
6859 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] = -1;
6860 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = 0;
6863 /* Maybe the spill reg contains a copy of reload_out. */
6864 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
6866 register int nregno = REGNO (reload_out[r]);
6867 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6868 : HARD_REGNO_NREGS (nregno,
6869 GET_MODE (reload_reg_rtx[r])));
6871 spill_reg_store[i] = new_spill_reg_store[i];
6872 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
6874 /* If NREGNO is a hard register, it may occupy more than
6875 one register. If it does, say what is in the
6876 rest of the registers assuming that both registers
6877 agree on how many words the object takes. If not,
6878 invalidate the subsequent registers. */
6880 if (nregno < FIRST_PSEUDO_REGISTER)
6881 for (k = 1; k < nnr; k++)
6882 reg_last_reload_reg[nregno + k]
6885 reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
6886 REGNO (reload_reg_rtx[r]) + k)
6889 /* Now do the inverse operation. */
6890 for (k = 0; k < nr; k++)
6892 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
6893 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
6896 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = insn;
6900 /* Maybe the spill reg contains a copy of reload_in. Only do
6901 something if there will not be an output reload for
6902 the register being reloaded. */
6903 else if (reload_out[r] == 0
6904 && reload_in[r] != 0
6905 && ((GET_CODE (reload_in[r]) == REG
6906 && ! reg_has_output_reload[REGNO (reload_in[r])])
6907 || (GET_CODE (reload_in_reg[r]) == REG
6908 && ! reg_has_output_reload[REGNO (reload_in_reg[r])])))
6910 register int nregno;
6913 if (GET_CODE (reload_in[r]) == REG)
6914 nregno = REGNO (reload_in[r]);
6916 nregno = REGNO (reload_in_reg[r]);
6918 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6919 : HARD_REGNO_NREGS (nregno,
6920 GET_MODE (reload_reg_rtx[r])));
6922 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
6924 if (nregno < FIRST_PSEUDO_REGISTER)
6925 for (k = 1; k < nnr; k++)
6926 reg_last_reload_reg[nregno + k]
6929 reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
6930 REGNO (reload_reg_rtx[r]) + k)
6933 /* Unless we inherited this reload, show we haven't
6934 recently done a store. */
6935 if (! reload_inherited[r])
6936 spill_reg_store[i] = 0;
6938 for (k = 0; k < nr; k++)
6940 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
6941 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
6944 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]]
6950 /* However, if part of the reload reaches the end, then we must
6951 invalidate the old info for the part that survives to the end. */
6952 else if (part_reaches_end)
6954 for (k = 0; k < nr; k++)
6955 if (reload_reg_reaches_end_p (spill_regs[i] + k,
6957 reload_when_needed[r]))
6959 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] = -1;
6960 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = 0;
6965 /* The following if-statement was #if 0'd in 1.34 (or before...).
6966 It's reenabled in 1.35 because supposedly nothing else
6967 deals with this problem. */
6969 /* If a register gets output-reloaded from a non-spill register,
6970 that invalidates any previous reloaded copy of it.
6971 But forget_old_reloads_1 won't get to see it, because
6972 it thinks only about the original insn. So invalidate it here. */
6973 if (i < 0 && reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
6975 register int nregno = REGNO (reload_out[r]);
6976 if (nregno >= FIRST_PSEUDO_REGISTER)
6977 reg_last_reload_reg[nregno] = 0;
6980 int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (reload_out[r]));
6982 while (num_regs-- > 0)
6983 reg_last_reload_reg[nregno + num_regs] = 0;
6989 /* Emit code to perform a reload from IN (which may be a reload register) to
6990 OUT (which may also be a reload register). IN or OUT is from operand
6991 OPNUM with reload type TYPE.
6993 Returns first insn emitted. */
6996 gen_reload (out, in, opnum, type)
7000 enum reload_type type;
7002 rtx last = get_last_insn ();
7005 /* If IN is a paradoxical SUBREG, remove it and try to put the
7006 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7007 if (GET_CODE (in) == SUBREG
7008 && (GET_MODE_SIZE (GET_MODE (in))
7009 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7010 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7011 in = SUBREG_REG (in), out = tem;
7012 else if (GET_CODE (out) == SUBREG
7013 && (GET_MODE_SIZE (GET_MODE (out))
7014 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7015 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7016 out = SUBREG_REG (out), in = tem;
7018 /* How to do this reload can get quite tricky. Normally, we are being
7019 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7020 register that didn't get a hard register. In that case we can just
7021 call emit_move_insn.
7023 We can also be asked to reload a PLUS that adds a register or a MEM to
7024 another register, constant or MEM. This can occur during frame pointer
7025 elimination and while reloading addresses. This case is handled by
7026 trying to emit a single insn to perform the add. If it is not valid,
7027 we use a two insn sequence.
7029 Finally, we could be called to handle an 'o' constraint by putting
7030 an address into a register. In that case, we first try to do this
7031 with a named pattern of "reload_load_address". If no such pattern
7032 exists, we just emit a SET insn and hope for the best (it will normally
7033 be valid on machines that use 'o').
7035 This entire process is made complex because reload will never
7036 process the insns we generate here and so we must ensure that
7037 they will fit their constraints and also by the fact that parts of
7038 IN might be being reloaded separately and replaced with spill registers.
7039 Because of this, we are, in some sense, just guessing the right approach
7040 here. The one listed above seems to work.
7042 ??? At some point, this whole thing needs to be rethought. */
7044 if (GET_CODE (in) == PLUS
7045 && (GET_CODE (XEXP (in, 0)) == REG
7046 || GET_CODE (XEXP (in, 0)) == SUBREG
7047 || GET_CODE (XEXP (in, 0)) == MEM)
7048 && (GET_CODE (XEXP (in, 1)) == REG
7049 || GET_CODE (XEXP (in, 1)) == SUBREG
7050 || CONSTANT_P (XEXP (in, 1))
7051 || GET_CODE (XEXP (in, 1)) == MEM))
7053 /* We need to compute the sum of a register or a MEM and another
7054 register, constant, or MEM, and put it into the reload
7055 register. The best possible way of doing this is if the machine
7056 has a three-operand ADD insn that accepts the required operands.
7058 The simplest approach is to try to generate such an insn and see if it
7059 is recognized and matches its constraints. If so, it can be used.
7061 It might be better not to actually emit the insn unless it is valid,
7062 but we need to pass the insn as an operand to `recog' and
7063 `insn_extract' and it is simpler to emit and then delete the insn if
7064 not valid than to dummy things up. */
7066 rtx op0, op1, tem, insn;
7069 op0 = find_replacement (&XEXP (in, 0));
7070 op1 = find_replacement (&XEXP (in, 1));
7072 /* Since constraint checking is strict, commutativity won't be
7073 checked, so we need to do that here to avoid spurious failure
7074 if the add instruction is two-address and the second operand
7075 of the add is the same as the reload reg, which is frequently
7076 the case. If the insn would be A = B + A, rearrange it so
7077 it will be A = A + B as constrain_operands expects. */
7079 if (GET_CODE (XEXP (in, 1)) == REG
7080 && REGNO (out) == REGNO (XEXP (in, 1)))
7081 tem = op0, op0 = op1, op1 = tem;
7083 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7084 in = gen_rtx (PLUS, GET_MODE (in), op0, op1);
7086 insn = emit_insn (gen_rtx (SET, VOIDmode, out, in));
7087 code = recog_memoized (insn);
7091 insn_extract (insn);
7092 /* We want constrain operands to treat this insn strictly in
7093 its validity determination, i.e., the way it would after reload
7095 if (constrain_operands (code, 1))
7099 delete_insns_since (last);
7101 /* If that failed, we must use a conservative two-insn sequence.
7102 use move to copy constant, MEM, or pseudo register to the reload
7103 register since "move" will be able to handle an arbitrary operand,
7104 unlike add which can't, in general. Then add the registers.
7106 If there is another way to do this for a specific machine, a
7107 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7110 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7111 || (GET_CODE (op1) == REG
7112 && REGNO (op1) >= FIRST_PSEUDO_REGISTER))
7113 tem = op0, op0 = op1, op1 = tem;
7115 gen_reload (out, op0, opnum, type);
7117 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7118 This fixes a problem on the 32K where the stack pointer cannot
7119 be used as an operand of an add insn. */
7121 if (rtx_equal_p (op0, op1))
7124 insn = emit_insn (gen_add2_insn (out, op1));
7126 /* If that failed, copy the address register to the reload register.
7127 Then add the constant to the reload register. */
7129 code = recog_memoized (insn);
7133 insn_extract (insn);
7134 /* We want constrain operands to treat this insn strictly in
7135 its validity determination, i.e., the way it would after reload
7137 if (constrain_operands (code, 1))
7141 delete_insns_since (last);
7143 gen_reload (out, op1, opnum, type);
7144 emit_insn (gen_add2_insn (out, op0));
7147 #ifdef SECONDARY_MEMORY_NEEDED
7148 /* If we need a memory location to do the move, do it that way. */
7149 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7150 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7151 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7152 REGNO_REG_CLASS (REGNO (out)),
7155 /* Get the memory to use and rewrite both registers to its mode. */
7156 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7158 if (GET_MODE (loc) != GET_MODE (out))
7159 out = gen_rtx (REG, GET_MODE (loc), REGNO (out));
7161 if (GET_MODE (loc) != GET_MODE (in))
7162 in = gen_rtx (REG, GET_MODE (loc), REGNO (in));
7164 gen_reload (loc, in, opnum, type);
7165 gen_reload (out, loc, opnum, type);
7169 /* If IN is a simple operand, use gen_move_insn. */
7170 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7171 emit_insn (gen_move_insn (out, in));
7173 #ifdef HAVE_reload_load_address
7174 else if (HAVE_reload_load_address)
7175 emit_insn (gen_reload_load_address (out, in));
7178 /* Otherwise, just write (set OUT IN) and hope for the best. */
7180 emit_insn (gen_rtx (SET, VOIDmode, out, in));
7182 /* Return the first insn emitted.
7183 We can not just return get_last_insn, because there may have
7184 been multiple instructions emitted. Also note that gen_move_insn may
7185 emit more than one insn itself, so we can not assume that there is one
7186 insn emitted per emit_insn_before call. */
7188 return last ? NEXT_INSN (last) : get_insns ();
7191 /* Delete a previously made output-reload
7192 whose result we now believe is not needed.
7193 First we double-check.
7195 INSN is the insn now being processed.
7196 OUTPUT_RELOAD_INSN is the insn of the output reload.
7197 J is the reload-number for this insn. */
7200 delete_output_reload (insn, j, output_reload_insn)
7203 rtx output_reload_insn;
7207 /* Get the raw pseudo-register referred to. */
7209 rtx reg = reload_in[j];
7210 while (GET_CODE (reg) == SUBREG)
7211 reg = SUBREG_REG (reg);
7213 /* If the pseudo-reg we are reloading is no longer referenced
7214 anywhere between the store into it and here,
7215 and no jumps or labels intervene, then the value can get
7216 here through the reload reg alone.
7217 Otherwise, give up--return. */
7218 for (i1 = NEXT_INSN (output_reload_insn);
7219 i1 != insn; i1 = NEXT_INSN (i1))
7221 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7223 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7224 && reg_mentioned_p (reg, PATTERN (i1)))
7228 if (cannot_omit_stores[REGNO (reg)])
7231 /* If this insn will store in the pseudo again,
7232 the previous store can be removed. */
7233 if (reload_out[j] == reload_in[j])
7234 delete_insn (output_reload_insn);
7236 /* See if the pseudo reg has been completely replaced
7237 with reload regs. If so, delete the store insn
7238 and forget we had a stack slot for the pseudo. */
7239 else if (reg_n_deaths[REGNO (reg)] == 1
7240 && reg_basic_block[REGNO (reg)] >= 0
7241 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7245 /* We know that it was used only between here
7246 and the beginning of the current basic block.
7247 (We also know that the last use before INSN was
7248 the output reload we are thinking of deleting, but never mind that.)
7249 Search that range; see if any ref remains. */
7250 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7252 rtx set = single_set (i2);
7254 /* Uses which just store in the pseudo don't count,
7255 since if they are the only uses, they are dead. */
7256 if (set != 0 && SET_DEST (set) == reg)
7258 if (GET_CODE (i2) == CODE_LABEL
7259 || GET_CODE (i2) == JUMP_INSN)
7261 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7262 && reg_mentioned_p (reg, PATTERN (i2)))
7263 /* Some other ref remains;
7264 we can't do anything. */
7268 /* Delete the now-dead stores into this pseudo. */
7269 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7271 rtx set = single_set (i2);
7273 if (set != 0 && SET_DEST (set) == reg)
7275 /* This might be a basic block head,
7276 thus don't use delete_insn. */
7277 PUT_CODE (i2, NOTE);
7278 NOTE_SOURCE_FILE (i2) = 0;
7279 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7281 if (GET_CODE (i2) == CODE_LABEL
7282 || GET_CODE (i2) == JUMP_INSN)
7286 /* For the debugging info,
7287 say the pseudo lives in this reload reg. */
7288 reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]);
7289 alter_reg (REGNO (reg), -1);
7293 /* Output reload-insns to reload VALUE into RELOADREG.
7294 VALUE is an autoincrement or autodecrement RTX whose operand
7295 is a register or memory location;
7296 so reloading involves incrementing that location.
7298 INC_AMOUNT is the number to increment or decrement by (always positive).
7299 This cannot be deduced from VALUE. */
7302 inc_for_reload (reloadreg, value, inc_amount)
7307 /* REG or MEM to be copied and incremented. */
7308 rtx incloc = XEXP (value, 0);
7309 /* Nonzero if increment after copying. */
7310 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7316 /* No hard register is equivalent to this register after
7317 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7318 we could inc/dec that register as well (maybe even using it for
7319 the source), but I'm not sure it's worth worrying about. */
7320 if (GET_CODE (incloc) == REG)
7321 reg_last_reload_reg[REGNO (incloc)] = 0;
7323 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7324 inc_amount = - inc_amount;
7326 inc = GEN_INT (inc_amount);
7328 /* If this is post-increment, first copy the location to the reload reg. */
7330 emit_insn (gen_move_insn (reloadreg, incloc));
7332 /* See if we can directly increment INCLOC. Use a method similar to that
7335 last = get_last_insn ();
7336 add_insn = emit_insn (gen_rtx (SET, VOIDmode, incloc,
7337 gen_rtx (PLUS, GET_MODE (incloc),
7340 code = recog_memoized (add_insn);
7343 insn_extract (add_insn);
7344 if (constrain_operands (code, 1))
7346 /* If this is a pre-increment and we have incremented the value
7347 where it lives, copy the incremented value to RELOADREG to
7348 be used as an address. */
7351 emit_insn (gen_move_insn (reloadreg, incloc));
7357 delete_insns_since (last);
7359 /* If couldn't do the increment directly, must increment in RELOADREG.
7360 The way we do this depends on whether this is pre- or post-increment.
7361 For pre-increment, copy INCLOC to the reload register, increment it
7362 there, then save back. */
7366 emit_insn (gen_move_insn (reloadreg, incloc));
7367 emit_insn (gen_add2_insn (reloadreg, inc));
7368 emit_insn (gen_move_insn (incloc, reloadreg));
7373 Because this might be a jump insn or a compare, and because RELOADREG
7374 may not be available after the insn in an input reload, we must do
7375 the incrementation before the insn being reloaded for.
7377 We have already copied INCLOC to RELOADREG. Increment the copy in
7378 RELOADREG, save that back, then decrement RELOADREG so it has
7379 the original value. */
7381 emit_insn (gen_add2_insn (reloadreg, inc));
7382 emit_insn (gen_move_insn (incloc, reloadreg));
7383 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7389 /* Return 1 if we are certain that the constraint-string STRING allows
7390 the hard register REG. Return 0 if we can't be sure of this. */
7393 constraint_accepts_reg_p (string, reg)
7398 int regno = true_regnum (reg);
7401 /* Initialize for first alternative. */
7403 /* Check that each alternative contains `g' or `r'. */
7405 switch (c = *string++)
7408 /* If an alternative lacks `g' or `r', we lose. */
7411 /* If an alternative lacks `g' or `r', we lose. */
7414 /* Initialize for next alternative. */
7419 /* Any general reg wins for this alternative. */
7420 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7424 /* Any reg in specified class wins for this alternative. */
7426 enum reg_class class = REG_CLASS_FROM_LETTER (c);
7428 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
7434 /* Return the number of places FIND appears within X, but don't count
7435 an occurrence if some SET_DEST is FIND. */
7438 count_occurrences (x, find)
7439 register rtx x, find;
7442 register enum rtx_code code;
7443 register char *format_ptr;
7451 code = GET_CODE (x);
7466 if (SET_DEST (x) == find)
7467 return count_occurrences (SET_SRC (x), find);
7471 format_ptr = GET_RTX_FORMAT (code);
7474 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7476 switch (*format_ptr++)
7479 count += count_occurrences (XEXP (x, i), find);
7483 if (XVEC (x, i) != NULL)
7485 for (j = 0; j < XVECLEN (x, i); j++)
7486 count += count_occurrences (XVECEXP (x, i, j), find);
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