1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
48 /* This file contains the reload pass of the compiler, which is
49 run after register allocation has been done. It checks that
50 each insn is valid (operands required to be in registers really
51 are in registers of the proper class) and fixes up invalid ones
52 by copying values temporarily into registers for the insns
55 The results of register allocation are described by the vector
56 reg_renumber; the insns still contain pseudo regs, but reg_renumber
57 can be used to find which hard reg, if any, a pseudo reg is in.
59 The technique we always use is to free up a few hard regs that are
60 called ``reload regs'', and for each place where a pseudo reg
61 must be in a hard reg, copy it temporarily into one of the reload regs.
63 Reload regs are allocated locally for every instruction that needs
64 reloads. When there are pseudos which are allocated to a register that
65 has been chosen as a reload reg, such pseudos must be ``spilled''.
66 This means that they go to other hard regs, or to stack slots if no other
67 available hard regs can be found. Spilling can invalidate more
68 insns, requiring additional need for reloads, so we must keep checking
69 until the process stabilizes.
71 For machines with different classes of registers, we must keep track
72 of the register class needed for each reload, and make sure that
73 we allocate enough reload registers of each class.
75 The file reload.c contains the code that checks one insn for
76 validity and reports the reloads that it needs. This file
77 is in charge of scanning the entire rtl code, accumulating the
78 reload needs, spilling, assigning reload registers to use for
79 fixing up each insn, and generating the new insns to copy values
80 into the reload registers. */
82 /* During reload_as_needed, element N contains a REG rtx for the hard reg
83 into which reg N has been reloaded (perhaps for a previous insn). */
84 static rtx *reg_last_reload_reg;
86 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
87 for an output reload that stores into reg N. */
88 static char *reg_has_output_reload;
90 /* Indicates which hard regs are reload-registers for an output reload
91 in the current insn. */
92 static HARD_REG_SET reg_is_output_reload;
94 /* Element N is the constant value to which pseudo reg N is equivalent,
95 or zero if pseudo reg N is not equivalent to a constant.
96 find_reloads looks at this in order to replace pseudo reg N
97 with the constant it stands for. */
98 rtx *reg_equiv_constant;
100 /* Element N is an invariant value to which pseudo reg N is equivalent.
101 eliminate_regs_in_insn uses this to replace pseudos in particular
103 rtx *reg_equiv_invariant;
105 /* Element N is a memory location to which pseudo reg N is equivalent,
106 prior to any register elimination (such as frame pointer to stack
107 pointer). Depending on whether or not it is a valid address, this value
108 is transferred to either reg_equiv_address or reg_equiv_mem. */
109 rtx *reg_equiv_memory_loc;
111 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
112 collector can keep track of what is inside. */
113 varray_type reg_equiv_memory_loc_varray;
115 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
116 This is used when the address is not valid as a memory address
117 (because its displacement is too big for the machine.) */
118 rtx *reg_equiv_address;
120 /* Element N is the memory slot to which pseudo reg N is equivalent,
121 or zero if pseudo reg N is not equivalent to a memory slot. */
124 /* Widest width in which each pseudo reg is referred to (via subreg). */
125 static unsigned int *reg_max_ref_width;
127 /* Element N is the list of insns that initialized reg N from its equivalent
128 constant or memory slot. */
130 int reg_equiv_init_size;
132 /* Vector to remember old contents of reg_renumber before spilling. */
133 static short *reg_old_renumber;
135 /* During reload_as_needed, element N contains the last pseudo regno reloaded
136 into hard register N. If that pseudo reg occupied more than one register,
137 reg_reloaded_contents points to that pseudo for each spill register in
138 use; all of these must remain set for an inheritance to occur. */
139 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
141 /* During reload_as_needed, element N contains the insn for which
142 hard register N was last used. Its contents are significant only
143 when reg_reloaded_valid is set for this register. */
144 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
146 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
147 static HARD_REG_SET reg_reloaded_valid;
148 /* Indicate if the register was dead at the end of the reload.
149 This is only valid if reg_reloaded_contents is set and valid. */
150 static HARD_REG_SET reg_reloaded_dead;
152 /* Indicate whether the register's current value is one that is not
153 safe to retain across a call, even for registers that are normally
155 static HARD_REG_SET reg_reloaded_call_part_clobbered;
157 /* Number of spill-regs so far; number of valid elements of spill_regs. */
160 /* In parallel with spill_regs, contains REG rtx's for those regs.
161 Holds the last rtx used for any given reg, or 0 if it has never
162 been used for spilling yet. This rtx is reused, provided it has
164 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
166 /* In parallel with spill_regs, contains nonzero for a spill reg
167 that was stored after the last time it was used.
168 The precise value is the insn generated to do the store. */
169 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
171 /* This is the register that was stored with spill_reg_store. This is a
172 copy of reload_out / reload_out_reg when the value was stored; if
173 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
174 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
176 /* This table is the inverse mapping of spill_regs:
177 indexed by hard reg number,
178 it contains the position of that reg in spill_regs,
179 or -1 for something that is not in spill_regs.
181 ?!? This is no longer accurate. */
182 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
184 /* This reg set indicates registers that can't be used as spill registers for
185 the currently processed insn. These are the hard registers which are live
186 during the insn, but not allocated to pseudos, as well as fixed
188 static HARD_REG_SET bad_spill_regs;
190 /* These are the hard registers that can't be used as spill register for any
191 insn. This includes registers used for user variables and registers that
192 we can't eliminate. A register that appears in this set also can't be used
193 to retry register allocation. */
194 static HARD_REG_SET bad_spill_regs_global;
196 /* Describes order of use of registers for reloading
197 of spilled pseudo-registers. `n_spills' is the number of
198 elements that are actually valid; new ones are added at the end.
200 Both spill_regs and spill_reg_order are used on two occasions:
201 once during find_reload_regs, where they keep track of the spill registers
202 for a single insn, but also during reload_as_needed where they show all
203 the registers ever used by reload. For the latter case, the information
204 is calculated during finish_spills. */
205 static short spill_regs[FIRST_PSEUDO_REGISTER];
207 /* This vector of reg sets indicates, for each pseudo, which hard registers
208 may not be used for retrying global allocation because the register was
209 formerly spilled from one of them. If we allowed reallocating a pseudo to
210 a register that it was already allocated to, reload might not
212 static HARD_REG_SET *pseudo_previous_regs;
214 /* This vector of reg sets indicates, for each pseudo, which hard
215 registers may not be used for retrying global allocation because they
216 are used as spill registers during one of the insns in which the
218 static HARD_REG_SET *pseudo_forbidden_regs;
220 /* All hard regs that have been used as spill registers for any insn are
221 marked in this set. */
222 static HARD_REG_SET used_spill_regs;
224 /* Index of last register assigned as a spill register. We allocate in
225 a round-robin fashion. */
226 static int last_spill_reg;
228 /* Nonzero if indirect addressing is supported on the machine; this means
229 that spilling (REG n) does not require reloading it into a register in
230 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
231 value indicates the level of indirect addressing supported, e.g., two
232 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
234 static char spill_indirect_levels;
236 /* Nonzero if indirect addressing is supported when the innermost MEM is
237 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
238 which these are valid is the same as spill_indirect_levels, above. */
239 char indirect_symref_ok;
241 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
242 char double_reg_address_ok;
244 /* Record the stack slot for each spilled hard register. */
245 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
247 /* Width allocated so far for that stack slot. */
248 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
250 /* Record which pseudos needed to be spilled. */
251 static regset_head spilled_pseudos;
253 /* Used for communication between order_regs_for_reload and count_pseudo.
254 Used to avoid counting one pseudo twice. */
255 static regset_head pseudos_counted;
257 /* First uid used by insns created by reload in this function.
258 Used in find_equiv_reg. */
259 int reload_first_uid;
261 /* Flag set by local-alloc or global-alloc if anything is live in
262 a call-clobbered reg across calls. */
263 int caller_save_needed;
265 /* Set to 1 while reload_as_needed is operating.
266 Required by some machines to handle any generated moves differently. */
267 int reload_in_progress = 0;
269 /* These arrays record the insn_code of insns that may be needed to
270 perform input and output reloads of special objects. They provide a
271 place to pass a scratch register. */
272 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
273 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
275 /* This obstack is used for allocation of rtl during register elimination.
276 The allocated storage can be freed once find_reloads has processed the
278 static struct obstack reload_obstack;
280 /* Points to the beginning of the reload_obstack. All insn_chain structures
281 are allocated first. */
282 static char *reload_startobj;
284 /* The point after all insn_chain structures. Used to quickly deallocate
285 memory allocated in copy_reloads during calculate_needs_all_insns. */
286 static char *reload_firstobj;
288 /* This points before all local rtl generated by register elimination.
289 Used to quickly free all memory after processing one insn. */
290 static char *reload_insn_firstobj;
292 /* List of insn_chain instructions, one for every insn that reload needs to
294 struct insn_chain *reload_insn_chain;
296 /* List of all insns needing reloads. */
297 static struct insn_chain *insns_need_reload;
299 /* This structure is used to record information about register eliminations.
300 Each array entry describes one possible way of eliminating a register
301 in favor of another. If there is more than one way of eliminating a
302 particular register, the most preferred should be specified first. */
306 int from; /* Register number to be eliminated. */
307 int to; /* Register number used as replacement. */
308 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
309 int can_eliminate; /* Nonzero if this elimination can be done. */
310 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
311 insns made by reload. */
312 HOST_WIDE_INT offset; /* Current offset between the two regs. */
313 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
314 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
315 rtx from_rtx; /* REG rtx for the register to be eliminated.
316 We cannot simply compare the number since
317 we might then spuriously replace a hard
318 register corresponding to a pseudo
319 assigned to the reg to be eliminated. */
320 rtx to_rtx; /* REG rtx for the replacement. */
323 static struct elim_table *reg_eliminate = 0;
325 /* This is an intermediate structure to initialize the table. It has
326 exactly the members provided by ELIMINABLE_REGS. */
327 static const struct elim_table_1
331 } reg_eliminate_1[] =
333 /* If a set of eliminable registers was specified, define the table from it.
334 Otherwise, default to the normal case of the frame pointer being
335 replaced by the stack pointer. */
337 #ifdef ELIMINABLE_REGS
340 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
343 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
345 /* Record the number of pending eliminations that have an offset not equal
346 to their initial offset. If nonzero, we use a new copy of each
347 replacement result in any insns encountered. */
348 int num_not_at_initial_offset;
350 /* Count the number of registers that we may be able to eliminate. */
351 static int num_eliminable;
352 /* And the number of registers that are equivalent to a constant that
353 can be eliminated to frame_pointer / arg_pointer + constant. */
354 static int num_eliminable_invariants;
356 /* For each label, we record the offset of each elimination. If we reach
357 a label by more than one path and an offset differs, we cannot do the
358 elimination. This information is indexed by the difference of the
359 number of the label and the first label number. We can't offset the
360 pointer itself as this can cause problems on machines with segmented
361 memory. The first table is an array of flags that records whether we
362 have yet encountered a label and the second table is an array of arrays,
363 one entry in the latter array for each elimination. */
365 static int first_label_num;
366 static char *offsets_known_at;
367 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
369 /* Number of labels in the current function. */
371 static int num_labels;
373 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
374 static void maybe_fix_stack_asms (void);
375 static void copy_reloads (struct insn_chain *);
376 static void calculate_needs_all_insns (int);
377 static int find_reg (struct insn_chain *, int);
378 static void find_reload_regs (struct insn_chain *);
379 static void select_reload_regs (void);
380 static void delete_caller_save_insns (void);
382 static void spill_failure (rtx, enum reg_class);
383 static void count_spilled_pseudo (int, int, int);
384 static void delete_dead_insn (rtx);
385 static void alter_reg (int, int);
386 static void set_label_offsets (rtx, rtx, int);
387 static void check_eliminable_occurrences (rtx);
388 static void elimination_effects (rtx, enum machine_mode);
389 static int eliminate_regs_in_insn (rtx, int);
390 static void update_eliminable_offsets (void);
391 static void mark_not_eliminable (rtx, rtx, void *);
392 static void set_initial_elim_offsets (void);
393 static bool verify_initial_elim_offsets (void);
394 static void set_initial_label_offsets (void);
395 static void set_offsets_for_label (rtx);
396 static void init_elim_table (void);
397 static void update_eliminables (HARD_REG_SET *);
398 static void spill_hard_reg (unsigned int, int);
399 static int finish_spills (int);
400 static void scan_paradoxical_subregs (rtx);
401 static void count_pseudo (int);
402 static void order_regs_for_reload (struct insn_chain *);
403 static void reload_as_needed (int);
404 static void forget_old_reloads_1 (rtx, rtx, void *);
405 static int reload_reg_class_lower (const void *, const void *);
406 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
408 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
410 static int reload_reg_free_p (unsigned int, int, enum reload_type);
411 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
413 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
415 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
416 static int allocate_reload_reg (struct insn_chain *, int, int);
417 static int conflicts_with_override (rtx);
418 static void failed_reload (rtx, int);
419 static int set_reload_reg (int, int);
420 static void choose_reload_regs_init (struct insn_chain *, rtx *);
421 static void choose_reload_regs (struct insn_chain *);
422 static void merge_assigned_reloads (rtx);
423 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
425 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
427 static void do_input_reload (struct insn_chain *, struct reload *, int);
428 static void do_output_reload (struct insn_chain *, struct reload *, int);
429 static bool inherit_piecemeal_p (int, int);
430 static void emit_reload_insns (struct insn_chain *);
431 static void delete_output_reload (rtx, int, int);
432 static void delete_address_reloads (rtx, rtx);
433 static void delete_address_reloads_1 (rtx, rtx, rtx);
434 static rtx inc_for_reload (rtx, rtx, rtx, int);
436 static void add_auto_inc_notes (rtx, rtx);
438 static void copy_eh_notes (rtx, rtx);
439 static int reloads_conflict (int, int);
440 static rtx gen_reload (rtx, rtx, int, enum reload_type);
441 static rtx emit_insn_if_valid_for_reload (rtx);
443 /* Initialize the reload pass once per compilation. */
450 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
451 Set spill_indirect_levels to the number of levels such addressing is
452 permitted, zero if it is not permitted at all. */
455 = gen_rtx_MEM (Pmode,
458 LAST_VIRTUAL_REGISTER + 1),
460 spill_indirect_levels = 0;
462 while (memory_address_p (QImode, tem))
464 spill_indirect_levels++;
465 tem = gen_rtx_MEM (Pmode, tem);
468 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
470 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
471 indirect_symref_ok = memory_address_p (QImode, tem);
473 /* See if reg+reg is a valid (and offsettable) address. */
475 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
477 tem = gen_rtx_PLUS (Pmode,
478 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
479 gen_rtx_REG (Pmode, i));
481 /* This way, we make sure that reg+reg is an offsettable address. */
482 tem = plus_constant (tem, 4);
484 if (memory_address_p (QImode, tem))
486 double_reg_address_ok = 1;
491 /* Initialize obstack for our rtl allocation. */
492 gcc_obstack_init (&reload_obstack);
493 reload_startobj = obstack_alloc (&reload_obstack, 0);
495 INIT_REG_SET (&spilled_pseudos);
496 INIT_REG_SET (&pseudos_counted);
497 VARRAY_RTX_INIT (reg_equiv_memory_loc_varray, 0, "reg_equiv_memory_loc");
500 /* List of insn chains that are currently unused. */
501 static struct insn_chain *unused_insn_chains = 0;
503 /* Allocate an empty insn_chain structure. */
505 new_insn_chain (void)
507 struct insn_chain *c;
509 if (unused_insn_chains == 0)
511 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
512 INIT_REG_SET (&c->live_throughout);
513 INIT_REG_SET (&c->dead_or_set);
517 c = unused_insn_chains;
518 unused_insn_chains = c->next;
520 c->is_caller_save_insn = 0;
521 c->need_operand_change = 0;
527 /* Small utility function to set all regs in hard reg set TO which are
528 allocated to pseudos in regset FROM. */
531 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
534 reg_set_iterator rsi;
536 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
538 int r = reg_renumber[regno];
543 /* reload_combine uses the information from
544 BASIC_BLOCK->global_live_at_start, which might still
545 contain registers that have not actually been allocated
546 since they have an equivalence. */
547 gcc_assert (reload_completed);
551 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)];
553 SET_HARD_REG_BIT (*to, r + nregs);
558 /* Replace all pseudos found in LOC with their corresponding
562 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
575 unsigned int regno = REGNO (x);
577 if (regno < FIRST_PSEUDO_REGISTER)
580 x = eliminate_regs (x, mem_mode, usage);
584 replace_pseudos_in (loc, mem_mode, usage);
588 if (reg_equiv_constant[regno])
589 *loc = reg_equiv_constant[regno];
590 else if (reg_equiv_mem[regno])
591 *loc = reg_equiv_mem[regno];
592 else if (reg_equiv_address[regno])
593 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
596 gcc_assert (!REG_P (regno_reg_rtx[regno])
597 || REGNO (regno_reg_rtx[regno]) != regno);
598 *loc = regno_reg_rtx[regno];
603 else if (code == MEM)
605 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
609 /* Process each of our operands recursively. */
610 fmt = GET_RTX_FORMAT (code);
611 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
613 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
614 else if (*fmt == 'E')
615 for (j = 0; j < XVECLEN (x, i); j++)
616 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
620 /* Global variables used by reload and its subroutines. */
622 /* Set during calculate_needs if an insn needs register elimination. */
623 static int something_needs_elimination;
624 /* Set during calculate_needs if an insn needs an operand changed. */
625 static int something_needs_operands_changed;
627 /* Nonzero means we couldn't get enough spill regs. */
630 /* Main entry point for the reload pass.
632 FIRST is the first insn of the function being compiled.
634 GLOBAL nonzero means we were called from global_alloc
635 and should attempt to reallocate any pseudoregs that we
636 displace from hard regs we will use for reloads.
637 If GLOBAL is zero, we do not have enough information to do that,
638 so any pseudo reg that is spilled must go to the stack.
640 Return value is nonzero if reload failed
641 and we must not do any more for this function. */
644 reload (rtx first, int global)
648 struct elim_table *ep;
651 /* Make sure even insns with volatile mem refs are recognizable. */
656 reload_firstobj = obstack_alloc (&reload_obstack, 0);
658 /* Make sure that the last insn in the chain
659 is not something that needs reloading. */
660 emit_note (NOTE_INSN_DELETED);
662 /* Enable find_equiv_reg to distinguish insns made by reload. */
663 reload_first_uid = get_max_uid ();
665 #ifdef SECONDARY_MEMORY_NEEDED
666 /* Initialize the secondary memory table. */
667 clear_secondary_mem ();
670 /* We don't have a stack slot for any spill reg yet. */
671 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
672 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
674 /* Initialize the save area information for caller-save, in case some
678 /* Compute which hard registers are now in use
679 as homes for pseudo registers.
680 This is done here rather than (eg) in global_alloc
681 because this point is reached even if not optimizing. */
682 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
685 /* A function that receives a nonlocal goto must save all call-saved
687 if (current_function_has_nonlocal_label)
688 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
689 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
690 regs_ever_live[i] = 1;
692 /* Find all the pseudo registers that didn't get hard regs
693 but do have known equivalent constants or memory slots.
694 These include parameters (known equivalent to parameter slots)
695 and cse'd or loop-moved constant memory addresses.
697 Record constant equivalents in reg_equiv_constant
698 so they will be substituted by find_reloads.
699 Record memory equivalents in reg_mem_equiv so they can
700 be substituted eventually by altering the REG-rtx's. */
702 reg_equiv_constant = xcalloc (max_regno, sizeof (rtx));
703 reg_equiv_invariant = xcalloc (max_regno, sizeof (rtx));
704 reg_equiv_mem = xcalloc (max_regno, sizeof (rtx));
705 reg_equiv_address = xcalloc (max_regno, sizeof (rtx));
706 reg_max_ref_width = xcalloc (max_regno, sizeof (int));
707 reg_old_renumber = xcalloc (max_regno, sizeof (short));
708 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
709 pseudo_forbidden_regs = xmalloc (max_regno * sizeof (HARD_REG_SET));
710 pseudo_previous_regs = xcalloc (max_regno, sizeof (HARD_REG_SET));
712 CLEAR_HARD_REG_SET (bad_spill_regs_global);
714 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
715 to. Also find all paradoxical subregs and find largest such for
718 num_eliminable_invariants = 0;
719 for (insn = first; insn; insn = NEXT_INSN (insn))
721 rtx set = single_set (insn);
723 /* We may introduce USEs that we want to remove at the end, so
724 we'll mark them with QImode. Make sure there are no
725 previously-marked insns left by say regmove. */
726 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
727 && GET_MODE (insn) != VOIDmode)
728 PUT_MODE (insn, VOIDmode);
731 scan_paradoxical_subregs (PATTERN (insn));
733 if (set != 0 && REG_P (SET_DEST (set)))
735 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
741 i = REGNO (SET_DEST (set));
744 if (i <= LAST_VIRTUAL_REGISTER)
747 if (! function_invariant_p (x)
749 /* A function invariant is often CONSTANT_P but may
750 include a register. We promise to only pass
751 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
753 && LEGITIMATE_PIC_OPERAND_P (x)))
755 /* It can happen that a REG_EQUIV note contains a MEM
756 that is not a legitimate memory operand. As later
757 stages of reload assume that all addresses found
758 in the reg_equiv_* arrays were originally legitimate,
759 we ignore such REG_EQUIV notes. */
760 if (memory_operand (x, VOIDmode))
762 /* Always unshare the equivalence, so we can
763 substitute into this insn without touching the
765 reg_equiv_memory_loc[i] = copy_rtx (x);
767 else if (function_invariant_p (x))
769 if (GET_CODE (x) == PLUS)
771 /* This is PLUS of frame pointer and a constant,
772 and might be shared. Unshare it. */
773 reg_equiv_invariant[i] = copy_rtx (x);
774 num_eliminable_invariants++;
776 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
778 reg_equiv_invariant[i] = x;
779 num_eliminable_invariants++;
781 else if (LEGITIMATE_CONSTANT_P (x))
782 reg_equiv_constant[i] = x;
785 reg_equiv_memory_loc[i]
786 = force_const_mem (GET_MODE (SET_DEST (set)), x);
787 if (! reg_equiv_memory_loc[i])
788 reg_equiv_init[i] = NULL_RTX;
793 reg_equiv_init[i] = NULL_RTX;
798 reg_equiv_init[i] = NULL_RTX;
803 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
804 if (reg_equiv_init[i])
806 fprintf (dump_file, "init_insns for %u: ", i);
807 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
808 fprintf (dump_file, "\n");
813 first_label_num = get_first_label_num ();
814 num_labels = max_label_num () - first_label_num;
816 /* Allocate the tables used to store offset information at labels. */
817 /* We used to use alloca here, but the size of what it would try to
818 allocate would occasionally cause it to exceed the stack limit and
819 cause a core dump. */
820 offsets_known_at = xmalloc (num_labels);
821 offsets_at = xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
823 /* Alter each pseudo-reg rtx to contain its hard reg number.
824 Assign stack slots to the pseudos that lack hard regs or equivalents.
825 Do not touch virtual registers. */
827 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
830 /* If we have some registers we think can be eliminated, scan all insns to
831 see if there is an insn that sets one of these registers to something
832 other than itself plus a constant. If so, the register cannot be
833 eliminated. Doing this scan here eliminates an extra pass through the
834 main reload loop in the most common case where register elimination
836 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
838 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
840 maybe_fix_stack_asms ();
842 insns_need_reload = 0;
843 something_needs_elimination = 0;
845 /* Initialize to -1, which means take the first spill register. */
848 /* Spill any hard regs that we know we can't eliminate. */
849 CLEAR_HARD_REG_SET (used_spill_regs);
850 /* There can be multiple ways to eliminate a register;
851 they should be listed adjacently.
852 Elimination for any register fails only if all possible ways fail. */
853 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
856 int can_eliminate = 0;
859 can_eliminate |= ep->can_eliminate;
862 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
864 spill_hard_reg (from, 1);
867 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
868 if (frame_pointer_needed)
869 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
871 finish_spills (global);
873 /* From now on, we may need to generate moves differently. We may also
874 allow modifications of insns which cause them to not be recognized.
875 Any such modifications will be cleaned up during reload itself. */
876 reload_in_progress = 1;
878 /* This loop scans the entire function each go-round
879 and repeats until one repetition spills no additional hard regs. */
882 int something_changed;
885 HOST_WIDE_INT starting_frame_size;
887 /* Round size of stack frame to stack_alignment_needed. This must be done
888 here because the stack size may be a part of the offset computation
889 for register elimination, and there might have been new stack slots
890 created in the last iteration of this loop. */
891 if (cfun->stack_alignment_needed)
892 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
894 starting_frame_size = get_frame_size ();
896 set_initial_elim_offsets ();
897 set_initial_label_offsets ();
899 /* For each pseudo register that has an equivalent location defined,
900 try to eliminate any eliminable registers (such as the frame pointer)
901 assuming initial offsets for the replacement register, which
904 If the resulting location is directly addressable, substitute
905 the MEM we just got directly for the old REG.
907 If it is not addressable but is a constant or the sum of a hard reg
908 and constant, it is probably not addressable because the constant is
909 out of range, in that case record the address; we will generate
910 hairy code to compute the address in a register each time it is
911 needed. Similarly if it is a hard register, but one that is not
912 valid as an address register.
914 If the location is not addressable, but does not have one of the
915 above forms, assign a stack slot. We have to do this to avoid the
916 potential of producing lots of reloads if, e.g., a location involves
917 a pseudo that didn't get a hard register and has an equivalent memory
918 location that also involves a pseudo that didn't get a hard register.
920 Perhaps at some point we will improve reload_when_needed handling
921 so this problem goes away. But that's very hairy. */
923 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
924 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
926 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
928 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
930 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
931 else if (CONSTANT_P (XEXP (x, 0))
932 || (REG_P (XEXP (x, 0))
933 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
934 || (GET_CODE (XEXP (x, 0)) == PLUS
935 && REG_P (XEXP (XEXP (x, 0), 0))
936 && (REGNO (XEXP (XEXP (x, 0), 0))
937 < FIRST_PSEUDO_REGISTER)
938 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
939 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
942 /* Make a new stack slot. Then indicate that something
943 changed so we go back and recompute offsets for
944 eliminable registers because the allocation of memory
945 below might change some offset. reg_equiv_{mem,address}
946 will be set up for this pseudo on the next pass around
948 reg_equiv_memory_loc[i] = 0;
949 reg_equiv_init[i] = 0;
954 if (caller_save_needed)
957 /* If we allocated another stack slot, redo elimination bookkeeping. */
958 if (starting_frame_size != get_frame_size ())
961 if (caller_save_needed)
963 save_call_clobbered_regs ();
964 /* That might have allocated new insn_chain structures. */
965 reload_firstobj = obstack_alloc (&reload_obstack, 0);
968 calculate_needs_all_insns (global);
970 CLEAR_REG_SET (&spilled_pseudos);
973 something_changed = 0;
975 /* If we allocated any new memory locations, make another pass
976 since it might have changed elimination offsets. */
977 if (starting_frame_size != get_frame_size ())
978 something_changed = 1;
980 /* Even if the frame size remained the same, we might still have
981 changed elimination offsets, e.g. if find_reloads called
982 force_const_mem requiring the back end to allocate a constant
983 pool base register that needs to be saved on the stack. */
984 else if (!verify_initial_elim_offsets ())
985 something_changed = 1;
988 HARD_REG_SET to_spill;
989 CLEAR_HARD_REG_SET (to_spill);
990 update_eliminables (&to_spill);
991 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
992 if (TEST_HARD_REG_BIT (to_spill, i))
994 spill_hard_reg (i, 1);
997 /* Regardless of the state of spills, if we previously had
998 a register that we thought we could eliminate, but now can
999 not eliminate, we must run another pass.
1001 Consider pseudos which have an entry in reg_equiv_* which
1002 reference an eliminable register. We must make another pass
1003 to update reg_equiv_* so that we do not substitute in the
1004 old value from when we thought the elimination could be
1006 something_changed = 1;
1010 select_reload_regs ();
1014 if (insns_need_reload != 0 || did_spill)
1015 something_changed |= finish_spills (global);
1017 if (! something_changed)
1020 if (caller_save_needed)
1021 delete_caller_save_insns ();
1023 obstack_free (&reload_obstack, reload_firstobj);
1026 /* If global-alloc was run, notify it of any register eliminations we have
1029 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1030 if (ep->can_eliminate)
1031 mark_elimination (ep->from, ep->to);
1033 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1034 If that insn didn't set the register (i.e., it copied the register to
1035 memory), just delete that insn instead of the equivalencing insn plus
1036 anything now dead. If we call delete_dead_insn on that insn, we may
1037 delete the insn that actually sets the register if the register dies
1038 there and that is incorrect. */
1040 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1042 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1045 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1047 rtx equiv_insn = XEXP (list, 0);
1049 /* If we already deleted the insn or if it may trap, we can't
1050 delete it. The latter case shouldn't happen, but can
1051 if an insn has a variable address, gets a REG_EH_REGION
1052 note added to it, and then gets converted into a load
1053 from a constant address. */
1054 if (NOTE_P (equiv_insn)
1055 || can_throw_internal (equiv_insn))
1057 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1058 delete_dead_insn (equiv_insn);
1060 SET_INSN_DELETED (equiv_insn);
1065 /* Use the reload registers where necessary
1066 by generating move instructions to move the must-be-register
1067 values into or out of the reload registers. */
1069 if (insns_need_reload != 0 || something_needs_elimination
1070 || something_needs_operands_changed)
1072 HOST_WIDE_INT old_frame_size = get_frame_size ();
1074 reload_as_needed (global);
1076 gcc_assert (old_frame_size == get_frame_size ());
1078 gcc_assert (verify_initial_elim_offsets ());
1081 /* If we were able to eliminate the frame pointer, show that it is no
1082 longer live at the start of any basic block. If it ls live by
1083 virtue of being in a pseudo, that pseudo will be marked live
1084 and hence the frame pointer will be known to be live via that
1087 if (! frame_pointer_needed)
1089 CLEAR_REGNO_REG_SET (bb->il.rtl->global_live_at_start,
1090 HARD_FRAME_POINTER_REGNUM);
1092 /* Come here (with failure set nonzero) if we can't get enough spill
1096 CLEAR_REG_SET (&spilled_pseudos);
1097 reload_in_progress = 0;
1099 /* Now eliminate all pseudo regs by modifying them into
1100 their equivalent memory references.
1101 The REG-rtx's for the pseudos are modified in place,
1102 so all insns that used to refer to them now refer to memory.
1104 For a reg that has a reg_equiv_address, all those insns
1105 were changed by reloading so that no insns refer to it any longer;
1106 but the DECL_RTL of a variable decl may refer to it,
1107 and if so this causes the debugging info to mention the variable. */
1109 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1113 if (reg_equiv_mem[i])
1114 addr = XEXP (reg_equiv_mem[i], 0);
1116 if (reg_equiv_address[i])
1117 addr = reg_equiv_address[i];
1121 if (reg_renumber[i] < 0)
1123 rtx reg = regno_reg_rtx[i];
1125 REG_USERVAR_P (reg) = 0;
1126 PUT_CODE (reg, MEM);
1127 XEXP (reg, 0) = addr;
1128 if (reg_equiv_memory_loc[i])
1129 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1132 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1133 MEM_ATTRS (reg) = 0;
1135 MEM_NOTRAP_P (reg) = 1;
1137 else if (reg_equiv_mem[i])
1138 XEXP (reg_equiv_mem[i], 0) = addr;
1142 /* We must set reload_completed now since the cleanup_subreg_operands call
1143 below will re-recognize each insn and reload may have generated insns
1144 which are only valid during and after reload. */
1145 reload_completed = 1;
1147 /* Make a pass over all the insns and delete all USEs which we inserted
1148 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1149 notes. Delete all CLOBBER insns, except those that refer to the return
1150 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1151 from misarranging variable-array code, and simplify (subreg (reg))
1152 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1153 are no longer useful or accurate. Strip and regenerate REG_INC notes
1154 that may have been moved around. */
1156 for (insn = first; insn; insn = NEXT_INSN (insn))
1162 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1163 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1165 if ((GET_CODE (PATTERN (insn)) == USE
1166 /* We mark with QImode USEs introduced by reload itself. */
1167 && (GET_MODE (insn) == QImode
1168 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1169 || (GET_CODE (PATTERN (insn)) == CLOBBER
1170 && (!MEM_P (XEXP (PATTERN (insn), 0))
1171 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1172 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1173 && XEXP (XEXP (PATTERN (insn), 0), 0)
1174 != stack_pointer_rtx))
1175 && (!REG_P (XEXP (PATTERN (insn), 0))
1176 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1182 /* Some CLOBBERs may survive until here and still reference unassigned
1183 pseudos with const equivalent, which may in turn cause ICE in later
1184 passes if the reference remains in place. */
1185 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1186 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1187 VOIDmode, PATTERN (insn));
1189 /* Discard obvious no-ops, even without -O. This optimization
1190 is fast and doesn't interfere with debugging. */
1191 if (NONJUMP_INSN_P (insn)
1192 && GET_CODE (PATTERN (insn)) == SET
1193 && REG_P (SET_SRC (PATTERN (insn)))
1194 && REG_P (SET_DEST (PATTERN (insn)))
1195 && (REGNO (SET_SRC (PATTERN (insn)))
1196 == REGNO (SET_DEST (PATTERN (insn)))))
1202 pnote = ®_NOTES (insn);
1205 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1206 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1207 || REG_NOTE_KIND (*pnote) == REG_INC
1208 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1209 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1210 *pnote = XEXP (*pnote, 1);
1212 pnote = &XEXP (*pnote, 1);
1216 add_auto_inc_notes (insn, PATTERN (insn));
1219 /* And simplify (subreg (reg)) if it appears as an operand. */
1220 cleanup_subreg_operands (insn);
1223 /* If we are doing stack checking, give a warning if this function's
1224 frame size is larger than we expect. */
1225 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1227 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1228 static int verbose_warned = 0;
1230 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1231 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1232 size += UNITS_PER_WORD;
1234 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1236 warning (0, "frame size too large for reliable stack checking");
1237 if (! verbose_warned)
1239 warning (0, "try reducing the number of local variables");
1245 /* Indicate that we no longer have known memory locations or constants. */
1246 if (reg_equiv_constant)
1247 free (reg_equiv_constant);
1248 if (reg_equiv_invariant)
1249 free (reg_equiv_invariant);
1250 reg_equiv_constant = 0;
1251 reg_equiv_invariant = 0;
1252 VARRAY_GROW (reg_equiv_memory_loc_varray, 0);
1253 reg_equiv_memory_loc = 0;
1255 if (offsets_known_at)
1256 free (offsets_known_at);
1260 free (reg_equiv_mem);
1262 free (reg_equiv_address);
1263 free (reg_max_ref_width);
1264 free (reg_old_renumber);
1265 free (pseudo_previous_regs);
1266 free (pseudo_forbidden_regs);
1268 CLEAR_HARD_REG_SET (used_spill_regs);
1269 for (i = 0; i < n_spills; i++)
1270 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1272 /* Free all the insn_chain structures at once. */
1273 obstack_free (&reload_obstack, reload_startobj);
1274 unused_insn_chains = 0;
1275 fixup_abnormal_edges ();
1277 /* Replacing pseudos with their memory equivalents might have
1278 created shared rtx. Subsequent passes would get confused
1279 by this, so unshare everything here. */
1280 unshare_all_rtl_again (first);
1282 #ifdef STACK_BOUNDARY
1283 /* init_emit has set the alignment of the hard frame pointer
1284 to STACK_BOUNDARY. It is very likely no longer valid if
1285 the hard frame pointer was used for register allocation. */
1286 if (!frame_pointer_needed)
1287 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1293 /* Yet another special case. Unfortunately, reg-stack forces people to
1294 write incorrect clobbers in asm statements. These clobbers must not
1295 cause the register to appear in bad_spill_regs, otherwise we'll call
1296 fatal_insn later. We clear the corresponding regnos in the live
1297 register sets to avoid this.
1298 The whole thing is rather sick, I'm afraid. */
1301 maybe_fix_stack_asms (void)
1304 const char *constraints[MAX_RECOG_OPERANDS];
1305 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1306 struct insn_chain *chain;
1308 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1311 HARD_REG_SET clobbered, allowed;
1314 if (! INSN_P (chain->insn)
1315 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1317 pat = PATTERN (chain->insn);
1318 if (GET_CODE (pat) != PARALLEL)
1321 CLEAR_HARD_REG_SET (clobbered);
1322 CLEAR_HARD_REG_SET (allowed);
1324 /* First, make a mask of all stack regs that are clobbered. */
1325 for (i = 0; i < XVECLEN (pat, 0); i++)
1327 rtx t = XVECEXP (pat, 0, i);
1328 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1329 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1332 /* Get the operand values and constraints out of the insn. */
1333 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1334 constraints, operand_mode);
1336 /* For every operand, see what registers are allowed. */
1337 for (i = 0; i < noperands; i++)
1339 const char *p = constraints[i];
1340 /* For every alternative, we compute the class of registers allowed
1341 for reloading in CLS, and merge its contents into the reg set
1343 int cls = (int) NO_REGS;
1349 if (c == '\0' || c == ',' || c == '#')
1351 /* End of one alternative - mark the regs in the current
1352 class, and reset the class. */
1353 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1359 } while (c != '\0' && c != ',');
1367 case '=': case '+': case '*': case '%': case '?': case '!':
1368 case '0': case '1': case '2': case '3': case '4': case 'm':
1369 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1370 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1371 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1376 cls = (int) reg_class_subunion[cls]
1377 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1382 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1386 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1387 cls = (int) reg_class_subunion[cls]
1388 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1390 cls = (int) reg_class_subunion[cls]
1391 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1393 p += CONSTRAINT_LEN (c, p);
1396 /* Those of the registers which are clobbered, but allowed by the
1397 constraints, must be usable as reload registers. So clear them
1398 out of the life information. */
1399 AND_HARD_REG_SET (allowed, clobbered);
1400 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1401 if (TEST_HARD_REG_BIT (allowed, i))
1403 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1404 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1411 /* Copy the global variables n_reloads and rld into the corresponding elts
1414 copy_reloads (struct insn_chain *chain)
1416 chain->n_reloads = n_reloads;
1417 chain->rld = obstack_alloc (&reload_obstack,
1418 n_reloads * sizeof (struct reload));
1419 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1420 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1423 /* Walk the chain of insns, and determine for each whether it needs reloads
1424 and/or eliminations. Build the corresponding insns_need_reload list, and
1425 set something_needs_elimination as appropriate. */
1427 calculate_needs_all_insns (int global)
1429 struct insn_chain **pprev_reload = &insns_need_reload;
1430 struct insn_chain *chain, *next = 0;
1432 something_needs_elimination = 0;
1434 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1435 for (chain = reload_insn_chain; chain != 0; chain = next)
1437 rtx insn = chain->insn;
1441 /* Clear out the shortcuts. */
1442 chain->n_reloads = 0;
1443 chain->need_elim = 0;
1444 chain->need_reload = 0;
1445 chain->need_operand_change = 0;
1447 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1448 include REG_LABEL), we need to see what effects this has on the
1449 known offsets at labels. */
1451 if (LABEL_P (insn) || JUMP_P (insn)
1452 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1453 set_label_offsets (insn, insn, 0);
1457 rtx old_body = PATTERN (insn);
1458 int old_code = INSN_CODE (insn);
1459 rtx old_notes = REG_NOTES (insn);
1460 int did_elimination = 0;
1461 int operands_changed = 0;
1462 rtx set = single_set (insn);
1464 /* Skip insns that only set an equivalence. */
1465 if (set && REG_P (SET_DEST (set))
1466 && reg_renumber[REGNO (SET_DEST (set))] < 0
1467 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1468 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1469 && reg_equiv_init[REGNO (SET_DEST (set))])
1472 /* If needed, eliminate any eliminable registers. */
1473 if (num_eliminable || num_eliminable_invariants)
1474 did_elimination = eliminate_regs_in_insn (insn, 0);
1476 /* Analyze the instruction. */
1477 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1478 global, spill_reg_order);
1480 /* If a no-op set needs more than one reload, this is likely
1481 to be something that needs input address reloads. We
1482 can't get rid of this cleanly later, and it is of no use
1483 anyway, so discard it now.
1484 We only do this when expensive_optimizations is enabled,
1485 since this complements reload inheritance / output
1486 reload deletion, and it can make debugging harder. */
1487 if (flag_expensive_optimizations && n_reloads > 1)
1489 rtx set = single_set (insn);
1491 && SET_SRC (set) == SET_DEST (set)
1492 && REG_P (SET_SRC (set))
1493 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1496 /* Delete it from the reload chain. */
1498 chain->prev->next = next;
1500 reload_insn_chain = next;
1502 next->prev = chain->prev;
1503 chain->next = unused_insn_chains;
1504 unused_insn_chains = chain;
1509 update_eliminable_offsets ();
1511 /* Remember for later shortcuts which insns had any reloads or
1512 register eliminations. */
1513 chain->need_elim = did_elimination;
1514 chain->need_reload = n_reloads > 0;
1515 chain->need_operand_change = operands_changed;
1517 /* Discard any register replacements done. */
1518 if (did_elimination)
1520 obstack_free (&reload_obstack, reload_insn_firstobj);
1521 PATTERN (insn) = old_body;
1522 INSN_CODE (insn) = old_code;
1523 REG_NOTES (insn) = old_notes;
1524 something_needs_elimination = 1;
1527 something_needs_operands_changed |= operands_changed;
1531 copy_reloads (chain);
1532 *pprev_reload = chain;
1533 pprev_reload = &chain->next_need_reload;
1540 /* Comparison function for qsort to decide which of two reloads
1541 should be handled first. *P1 and *P2 are the reload numbers. */
1544 reload_reg_class_lower (const void *r1p, const void *r2p)
1546 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1549 /* Consider required reloads before optional ones. */
1550 t = rld[r1].optional - rld[r2].optional;
1554 /* Count all solitary classes before non-solitary ones. */
1555 t = ((reg_class_size[(int) rld[r2].class] == 1)
1556 - (reg_class_size[(int) rld[r1].class] == 1));
1560 /* Aside from solitaires, consider all multi-reg groups first. */
1561 t = rld[r2].nregs - rld[r1].nregs;
1565 /* Consider reloads in order of increasing reg-class number. */
1566 t = (int) rld[r1].class - (int) rld[r2].class;
1570 /* If reloads are equally urgent, sort by reload number,
1571 so that the results of qsort leave nothing to chance. */
1575 /* The cost of spilling each hard reg. */
1576 static int spill_cost[FIRST_PSEUDO_REGISTER];
1578 /* When spilling multiple hard registers, we use SPILL_COST for the first
1579 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1580 only the first hard reg for a multi-reg pseudo. */
1581 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1583 /* Update the spill cost arrays, considering that pseudo REG is live. */
1586 count_pseudo (int reg)
1588 int freq = REG_FREQ (reg);
1589 int r = reg_renumber[reg];
1592 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1593 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1596 SET_REGNO_REG_SET (&pseudos_counted, reg);
1598 gcc_assert (r >= 0);
1600 spill_add_cost[r] += freq;
1602 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1604 spill_cost[r + nregs] += freq;
1607 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1608 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1611 order_regs_for_reload (struct insn_chain *chain)
1614 HARD_REG_SET used_by_pseudos;
1615 HARD_REG_SET used_by_pseudos2;
1616 reg_set_iterator rsi;
1618 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1620 memset (spill_cost, 0, sizeof spill_cost);
1621 memset (spill_add_cost, 0, sizeof spill_add_cost);
1623 /* Count number of uses of each hard reg by pseudo regs allocated to it
1624 and then order them by decreasing use. First exclude hard registers
1625 that are live in or across this insn. */
1627 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1628 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1629 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1630 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1632 /* Now find out which pseudos are allocated to it, and update
1634 CLEAR_REG_SET (&pseudos_counted);
1636 EXECUTE_IF_SET_IN_REG_SET
1637 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1641 EXECUTE_IF_SET_IN_REG_SET
1642 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1646 CLEAR_REG_SET (&pseudos_counted);
1649 /* Vector of reload-numbers showing the order in which the reloads should
1651 static short reload_order[MAX_RELOADS];
1653 /* This is used to keep track of the spill regs used in one insn. */
1654 static HARD_REG_SET used_spill_regs_local;
1656 /* We decided to spill hard register SPILLED, which has a size of
1657 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1658 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1659 update SPILL_COST/SPILL_ADD_COST. */
1662 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1664 int r = reg_renumber[reg];
1665 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1667 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1668 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1671 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1673 spill_add_cost[r] -= REG_FREQ (reg);
1675 spill_cost[r + nregs] -= REG_FREQ (reg);
1678 /* Find reload register to use for reload number ORDER. */
1681 find_reg (struct insn_chain *chain, int order)
1683 int rnum = reload_order[order];
1684 struct reload *rl = rld + rnum;
1685 int best_cost = INT_MAX;
1689 HARD_REG_SET not_usable;
1690 HARD_REG_SET used_by_other_reload;
1691 reg_set_iterator rsi;
1693 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1694 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1695 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1697 CLEAR_HARD_REG_SET (used_by_other_reload);
1698 for (k = 0; k < order; k++)
1700 int other = reload_order[k];
1702 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1703 for (j = 0; j < rld[other].nregs; j++)
1704 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1707 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1709 unsigned int regno = i;
1711 if (! TEST_HARD_REG_BIT (not_usable, regno)
1712 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1713 && HARD_REGNO_MODE_OK (regno, rl->mode))
1715 int this_cost = spill_cost[regno];
1717 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1719 for (j = 1; j < this_nregs; j++)
1721 this_cost += spill_add_cost[regno + j];
1722 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1723 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1728 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1730 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1732 if (this_cost < best_cost
1733 /* Among registers with equal cost, prefer caller-saved ones, or
1734 use REG_ALLOC_ORDER if it is defined. */
1735 || (this_cost == best_cost
1736 #ifdef REG_ALLOC_ORDER
1737 && (inv_reg_alloc_order[regno]
1738 < inv_reg_alloc_order[best_reg])
1740 && call_used_regs[regno]
1741 && ! call_used_regs[best_reg]
1746 best_cost = this_cost;
1754 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1756 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1757 rl->regno = best_reg;
1759 EXECUTE_IF_SET_IN_REG_SET
1760 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1762 count_spilled_pseudo (best_reg, rl->nregs, j);
1765 EXECUTE_IF_SET_IN_REG_SET
1766 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1768 count_spilled_pseudo (best_reg, rl->nregs, j);
1771 for (i = 0; i < rl->nregs; i++)
1773 gcc_assert (spill_cost[best_reg + i] == 0);
1774 gcc_assert (spill_add_cost[best_reg + i] == 0);
1775 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1780 /* Find more reload regs to satisfy the remaining need of an insn, which
1782 Do it by ascending class number, since otherwise a reg
1783 might be spilled for a big class and might fail to count
1784 for a smaller class even though it belongs to that class. */
1787 find_reload_regs (struct insn_chain *chain)
1791 /* In order to be certain of getting the registers we need,
1792 we must sort the reloads into order of increasing register class.
1793 Then our grabbing of reload registers will parallel the process
1794 that provided the reload registers. */
1795 for (i = 0; i < chain->n_reloads; i++)
1797 /* Show whether this reload already has a hard reg. */
1798 if (chain->rld[i].reg_rtx)
1800 int regno = REGNO (chain->rld[i].reg_rtx);
1801 chain->rld[i].regno = regno;
1803 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1806 chain->rld[i].regno = -1;
1807 reload_order[i] = i;
1810 n_reloads = chain->n_reloads;
1811 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1813 CLEAR_HARD_REG_SET (used_spill_regs_local);
1816 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1818 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1820 /* Compute the order of preference for hard registers to spill. */
1822 order_regs_for_reload (chain);
1824 for (i = 0; i < n_reloads; i++)
1826 int r = reload_order[i];
1828 /* Ignore reloads that got marked inoperative. */
1829 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1830 && ! rld[r].optional
1831 && rld[r].regno == -1)
1832 if (! find_reg (chain, i))
1835 fprintf(dump_file, "reload failure for reload %d\n", r);
1836 spill_failure (chain->insn, rld[r].class);
1842 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1843 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1845 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1849 select_reload_regs (void)
1851 struct insn_chain *chain;
1853 /* Try to satisfy the needs for each insn. */
1854 for (chain = insns_need_reload; chain != 0;
1855 chain = chain->next_need_reload)
1856 find_reload_regs (chain);
1859 /* Delete all insns that were inserted by emit_caller_save_insns during
1862 delete_caller_save_insns (void)
1864 struct insn_chain *c = reload_insn_chain;
1868 while (c != 0 && c->is_caller_save_insn)
1870 struct insn_chain *next = c->next;
1873 if (c == reload_insn_chain)
1874 reload_insn_chain = next;
1878 next->prev = c->prev;
1880 c->prev->next = next;
1881 c->next = unused_insn_chains;
1882 unused_insn_chains = c;
1890 /* Handle the failure to find a register to spill.
1891 INSN should be one of the insns which needed this particular spill reg. */
1894 spill_failure (rtx insn, enum reg_class class)
1896 if (asm_noperands (PATTERN (insn)) >= 0)
1897 error_for_asm (insn, "can't find a register in class %qs while "
1898 "reloading %<asm%>",
1899 reg_class_names[class]);
1902 error ("unable to find a register to spill in class %qs",
1903 reg_class_names[class]);
1907 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
1908 debug_reload_to_stream (dump_file);
1910 fatal_insn ("this is the insn:", insn);
1914 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1915 data that is dead in INSN. */
1918 delete_dead_insn (rtx insn)
1920 rtx prev = prev_real_insn (insn);
1923 /* If the previous insn sets a register that dies in our insn, delete it
1925 if (prev && GET_CODE (PATTERN (prev)) == SET
1926 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
1927 && reg_mentioned_p (prev_dest, PATTERN (insn))
1928 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1929 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1930 delete_dead_insn (prev);
1932 SET_INSN_DELETED (insn);
1935 /* Modify the home of pseudo-reg I.
1936 The new home is present in reg_renumber[I].
1938 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1939 or it may be -1, meaning there is none or it is not relevant.
1940 This is used so that all pseudos spilled from a given hard reg
1941 can share one stack slot. */
1944 alter_reg (int i, int from_reg)
1946 /* When outputting an inline function, this can happen
1947 for a reg that isn't actually used. */
1948 if (regno_reg_rtx[i] == 0)
1951 /* If the reg got changed to a MEM at rtl-generation time,
1953 if (!REG_P (regno_reg_rtx[i]))
1956 /* Modify the reg-rtx to contain the new hard reg
1957 number or else to contain its pseudo reg number. */
1958 REGNO (regno_reg_rtx[i])
1959 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1961 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1962 allocate a stack slot for it. */
1964 if (reg_renumber[i] < 0
1965 && REG_N_REFS (i) > 0
1966 && reg_equiv_constant[i] == 0
1967 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
1968 && reg_equiv_memory_loc[i] == 0)
1971 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1972 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1975 /* Each pseudo reg has an inherent size which comes from its own mode,
1976 and a total size which provides room for paradoxical subregs
1977 which refer to the pseudo reg in wider modes.
1979 We can use a slot already allocated if it provides both
1980 enough inherent space and enough total space.
1981 Otherwise, we allocate a new slot, making sure that it has no less
1982 inherent space, and no less total space, then the previous slot. */
1985 /* No known place to spill from => no slot to reuse. */
1986 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1987 inherent_size == total_size ? 0 : -1);
1988 if (BYTES_BIG_ENDIAN)
1989 /* Cancel the big-endian correction done in assign_stack_local.
1990 Get the address of the beginning of the slot.
1991 This is so we can do a big-endian correction unconditionally
1993 adjust = inherent_size - total_size;
1995 /* Nothing can alias this slot except this pseudo. */
1996 set_mem_alias_set (x, new_alias_set ());
1999 /* Reuse a stack slot if possible. */
2000 else if (spill_stack_slot[from_reg] != 0
2001 && spill_stack_slot_width[from_reg] >= total_size
2002 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2004 x = spill_stack_slot[from_reg];
2006 /* Allocate a bigger slot. */
2009 /* Compute maximum size needed, both for inherent size
2010 and for total size. */
2011 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2014 if (spill_stack_slot[from_reg])
2016 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2018 mode = GET_MODE (spill_stack_slot[from_reg]);
2019 if (spill_stack_slot_width[from_reg] > total_size)
2020 total_size = spill_stack_slot_width[from_reg];
2023 /* Make a slot with that size. */
2024 x = assign_stack_local (mode, total_size,
2025 inherent_size == total_size ? 0 : -1);
2028 /* All pseudos mapped to this slot can alias each other. */
2029 if (spill_stack_slot[from_reg])
2030 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2032 set_mem_alias_set (x, new_alias_set ());
2034 if (BYTES_BIG_ENDIAN)
2036 /* Cancel the big-endian correction done in assign_stack_local.
2037 Get the address of the beginning of the slot.
2038 This is so we can do a big-endian correction unconditionally
2040 adjust = GET_MODE_SIZE (mode) - total_size;
2043 = adjust_address_nv (x, mode_for_size (total_size
2049 spill_stack_slot[from_reg] = stack_slot;
2050 spill_stack_slot_width[from_reg] = total_size;
2053 /* On a big endian machine, the "address" of the slot
2054 is the address of the low part that fits its inherent mode. */
2055 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2056 adjust += (total_size - inherent_size);
2058 /* If we have any adjustment to make, or if the stack slot is the
2059 wrong mode, make a new stack slot. */
2060 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2062 /* If we have a decl for the original register, set it for the
2063 memory. If this is a shared MEM, make a copy. */
2064 if (REG_EXPR (regno_reg_rtx[i])
2065 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2067 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2069 /* We can do this only for the DECLs home pseudo, not for
2070 any copies of it, since otherwise when the stack slot
2071 is reused, nonoverlapping_memrefs_p might think they
2073 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2075 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2078 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2082 /* Save the stack slot for later. */
2083 reg_equiv_memory_loc[i] = x;
2087 /* Mark the slots in regs_ever_live for the hard regs
2088 used by pseudo-reg number REGNO. */
2091 mark_home_live (int regno)
2095 i = reg_renumber[regno];
2098 lim = i + hard_regno_nregs[i][PSEUDO_REGNO_MODE (regno)];
2100 regs_ever_live[i++] = 1;
2103 /* This function handles the tracking of elimination offsets around branches.
2105 X is a piece of RTL being scanned.
2107 INSN is the insn that it came from, if any.
2109 INITIAL_P is nonzero if we are to set the offset to be the initial
2110 offset and zero if we are setting the offset of the label to be the
2114 set_label_offsets (rtx x, rtx insn, int initial_p)
2116 enum rtx_code code = GET_CODE (x);
2119 struct elim_table *p;
2124 if (LABEL_REF_NONLOCAL_P (x))
2129 /* ... fall through ... */
2132 /* If we know nothing about this label, set the desired offsets. Note
2133 that this sets the offset at a label to be the offset before a label
2134 if we don't know anything about the label. This is not correct for
2135 the label after a BARRIER, but is the best guess we can make. If
2136 we guessed wrong, we will suppress an elimination that might have
2137 been possible had we been able to guess correctly. */
2139 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2141 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2142 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2143 = (initial_p ? reg_eliminate[i].initial_offset
2144 : reg_eliminate[i].offset);
2145 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2148 /* Otherwise, if this is the definition of a label and it is
2149 preceded by a BARRIER, set our offsets to the known offset of
2153 && (tem = prev_nonnote_insn (insn)) != 0
2155 set_offsets_for_label (insn);
2157 /* If neither of the above cases is true, compare each offset
2158 with those previously recorded and suppress any eliminations
2159 where the offsets disagree. */
2161 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2162 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2163 != (initial_p ? reg_eliminate[i].initial_offset
2164 : reg_eliminate[i].offset))
2165 reg_eliminate[i].can_eliminate = 0;
2170 set_label_offsets (PATTERN (insn), insn, initial_p);
2172 /* ... fall through ... */
2176 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2177 and hence must have all eliminations at their initial offsets. */
2178 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2179 if (REG_NOTE_KIND (tem) == REG_LABEL)
2180 set_label_offsets (XEXP (tem, 0), insn, 1);
2186 /* Each of the labels in the parallel or address vector must be
2187 at their initial offsets. We want the first field for PARALLEL
2188 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2190 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2191 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2196 /* We only care about setting PC. If the source is not RETURN,
2197 IF_THEN_ELSE, or a label, disable any eliminations not at
2198 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2199 isn't one of those possibilities. For branches to a label,
2200 call ourselves recursively.
2202 Note that this can disable elimination unnecessarily when we have
2203 a non-local goto since it will look like a non-constant jump to
2204 someplace in the current function. This isn't a significant
2205 problem since such jumps will normally be when all elimination
2206 pairs are back to their initial offsets. */
2208 if (SET_DEST (x) != pc_rtx)
2211 switch (GET_CODE (SET_SRC (x)))
2218 set_label_offsets (SET_SRC (x), insn, initial_p);
2222 tem = XEXP (SET_SRC (x), 1);
2223 if (GET_CODE (tem) == LABEL_REF)
2224 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2225 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2228 tem = XEXP (SET_SRC (x), 2);
2229 if (GET_CODE (tem) == LABEL_REF)
2230 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2231 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2239 /* If we reach here, all eliminations must be at their initial
2240 offset because we are doing a jump to a variable address. */
2241 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2242 if (p->offset != p->initial_offset)
2243 p->can_eliminate = 0;
2251 /* Scan X and replace any eliminable registers (such as fp) with a
2252 replacement (such as sp), plus an offset.
2254 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2255 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2256 MEM, we are allowed to replace a sum of a register and the constant zero
2257 with the register, which we cannot do outside a MEM. In addition, we need
2258 to record the fact that a register is referenced outside a MEM.
2260 If INSN is an insn, it is the insn containing X. If we replace a REG
2261 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2262 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2263 the REG is being modified.
2265 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2266 That's used when we eliminate in expressions stored in notes.
2267 This means, do not set ref_outside_mem even if the reference
2270 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2271 replacements done assuming all offsets are at their initial values. If
2272 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2273 encounter, return the actual location so that find_reloads will do
2274 the proper thing. */
2277 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2278 bool may_use_invariant)
2280 enum rtx_code code = GET_CODE (x);
2281 struct elim_table *ep;
2288 if (! current_function_decl)
2310 /* First handle the case where we encounter a bare register that
2311 is eliminable. Replace it with a PLUS. */
2312 if (regno < FIRST_PSEUDO_REGISTER)
2314 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2316 if (ep->from_rtx == x && ep->can_eliminate)
2317 return plus_constant (ep->to_rtx, ep->previous_offset);
2320 else if (reg_renumber && reg_renumber[regno] < 0
2321 && reg_equiv_invariant && reg_equiv_invariant[regno])
2323 if (may_use_invariant)
2324 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2325 mem_mode, insn, true);
2326 /* There exists at least one use of REGNO that cannot be
2327 eliminated. Prevent the defining insn from being deleted. */
2328 reg_equiv_init[regno] = NULL_RTX;
2329 alter_reg (regno, -1);
2333 /* You might think handling MINUS in a manner similar to PLUS is a
2334 good idea. It is not. It has been tried multiple times and every
2335 time the change has had to have been reverted.
2337 Other parts of reload know a PLUS is special (gen_reload for example)
2338 and require special code to handle code a reloaded PLUS operand.
2340 Also consider backends where the flags register is clobbered by a
2341 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2342 lea instruction comes to mind). If we try to reload a MINUS, we
2343 may kill the flags register that was holding a useful value.
2345 So, please before trying to handle MINUS, consider reload as a
2346 whole instead of this little section as well as the backend issues. */
2348 /* If this is the sum of an eliminable register and a constant, rework
2350 if (REG_P (XEXP (x, 0))
2351 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2352 && CONSTANT_P (XEXP (x, 1)))
2354 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2356 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2358 /* The only time we want to replace a PLUS with a REG (this
2359 occurs when the constant operand of the PLUS is the negative
2360 of the offset) is when we are inside a MEM. We won't want
2361 to do so at other times because that would change the
2362 structure of the insn in a way that reload can't handle.
2363 We special-case the commonest situation in
2364 eliminate_regs_in_insn, so just replace a PLUS with a
2365 PLUS here, unless inside a MEM. */
2366 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2367 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2370 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2371 plus_constant (XEXP (x, 1),
2372 ep->previous_offset));
2375 /* If the register is not eliminable, we are done since the other
2376 operand is a constant. */
2380 /* If this is part of an address, we want to bring any constant to the
2381 outermost PLUS. We will do this by doing register replacement in
2382 our operands and seeing if a constant shows up in one of them.
2384 Note that there is no risk of modifying the structure of the insn,
2385 since we only get called for its operands, thus we are either
2386 modifying the address inside a MEM, or something like an address
2387 operand of a load-address insn. */
2390 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2391 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2393 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2395 /* If one side is a PLUS and the other side is a pseudo that
2396 didn't get a hard register but has a reg_equiv_constant,
2397 we must replace the constant here since it may no longer
2398 be in the position of any operand. */
2399 if (GET_CODE (new0) == PLUS && REG_P (new1)
2400 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2401 && reg_renumber[REGNO (new1)] < 0
2402 && reg_equiv_constant != 0
2403 && reg_equiv_constant[REGNO (new1)] != 0)
2404 new1 = reg_equiv_constant[REGNO (new1)];
2405 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2406 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2407 && reg_renumber[REGNO (new0)] < 0
2408 && reg_equiv_constant[REGNO (new0)] != 0)
2409 new0 = reg_equiv_constant[REGNO (new0)];
2411 new = form_sum (new0, new1);
2413 /* As above, if we are not inside a MEM we do not want to
2414 turn a PLUS into something else. We might try to do so here
2415 for an addition of 0 if we aren't optimizing. */
2416 if (! mem_mode && GET_CODE (new) != PLUS)
2417 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2425 /* If this is the product of an eliminable register and a
2426 constant, apply the distribute law and move the constant out
2427 so that we have (plus (mult ..) ..). This is needed in order
2428 to keep load-address insns valid. This case is pathological.
2429 We ignore the possibility of overflow here. */
2430 if (REG_P (XEXP (x, 0))
2431 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2432 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2433 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2435 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2438 /* Refs inside notes don't count for this purpose. */
2439 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2440 || GET_CODE (insn) == INSN_LIST)))
2441 ep->ref_outside_mem = 1;
2444 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2445 ep->previous_offset * INTVAL (XEXP (x, 1)));
2448 /* ... fall through ... */
2452 /* See comments before PLUS about handling MINUS. */
2454 case DIV: case UDIV:
2455 case MOD: case UMOD:
2456 case AND: case IOR: case XOR:
2457 case ROTATERT: case ROTATE:
2458 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2460 case GE: case GT: case GEU: case GTU:
2461 case LE: case LT: case LEU: case LTU:
2463 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2464 rtx new1 = XEXP (x, 1)
2465 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2467 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2468 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2473 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2476 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2477 if (new != XEXP (x, 0))
2479 /* If this is a REG_DEAD note, it is not valid anymore.
2480 Using the eliminated version could result in creating a
2481 REG_DEAD note for the stack or frame pointer. */
2482 if (GET_MODE (x) == REG_DEAD)
2484 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2487 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2491 /* ... fall through ... */
2494 /* Now do eliminations in the rest of the chain. If this was
2495 an EXPR_LIST, this might result in allocating more memory than is
2496 strictly needed, but it simplifies the code. */
2499 new = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2500 if (new != XEXP (x, 1))
2502 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2510 case STRICT_LOW_PART:
2512 case SIGN_EXTEND: case ZERO_EXTEND:
2513 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2514 case FLOAT: case FIX:
2515 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2523 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2524 if (new != XEXP (x, 0))
2525 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2529 /* Similar to above processing, but preserve SUBREG_BYTE.
2530 Convert (subreg (mem)) to (mem) if not paradoxical.
2531 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2532 pseudo didn't get a hard reg, we must replace this with the
2533 eliminated version of the memory location because push_reload
2534 may do the replacement in certain circumstances. */
2535 if (REG_P (SUBREG_REG (x))
2536 && (GET_MODE_SIZE (GET_MODE (x))
2537 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2538 && reg_equiv_memory_loc != 0
2539 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2541 new = SUBREG_REG (x);
2544 new = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2546 if (new != SUBREG_REG (x))
2548 int x_size = GET_MODE_SIZE (GET_MODE (x));
2549 int new_size = GET_MODE_SIZE (GET_MODE (new));
2552 && ((x_size < new_size
2553 #ifdef WORD_REGISTER_OPERATIONS
2554 /* On these machines, combine can create rtl of the form
2555 (set (subreg:m1 (reg:m2 R) 0) ...)
2556 where m1 < m2, and expects something interesting to
2557 happen to the entire word. Moreover, it will use the
2558 (reg:m2 R) later, expecting all bits to be preserved.
2559 So if the number of words is the same, preserve the
2560 subreg so that push_reload can see it. */
2561 && ! ((x_size - 1) / UNITS_PER_WORD
2562 == (new_size -1 ) / UNITS_PER_WORD)
2565 || x_size == new_size)
2567 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2569 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2575 /* Our only special processing is to pass the mode of the MEM to our
2576 recursive call and copy the flags. While we are here, handle this
2577 case more efficiently. */
2579 replace_equiv_address_nv (x,
2580 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2584 /* Handle insn_list USE that a call to a pure function may generate. */
2585 new = eliminate_regs_1 (XEXP (x, 0), 0, insn, false);
2586 if (new != XEXP (x, 0))
2587 return gen_rtx_USE (GET_MODE (x), new);
2599 /* Process each of our operands recursively. If any have changed, make a
2601 fmt = GET_RTX_FORMAT (code);
2602 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2606 new = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2607 if (new != XEXP (x, i) && ! copied)
2609 rtx new_x = rtx_alloc (code);
2610 memcpy (new_x, x, RTX_SIZE (code));
2616 else if (*fmt == 'E')
2619 for (j = 0; j < XVECLEN (x, i); j++)
2621 new = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2622 if (new != XVECEXP (x, i, j) && ! copied_vec)
2624 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2628 rtx new_x = rtx_alloc (code);
2629 memcpy (new_x, x, RTX_SIZE (code));
2633 XVEC (x, i) = new_v;
2636 XVECEXP (x, i, j) = new;
2645 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2647 return eliminate_regs_1 (x, mem_mode, insn, false);
2650 /* Scan rtx X for modifications of elimination target registers. Update
2651 the table of eliminables to reflect the changed state. MEM_MODE is
2652 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2655 elimination_effects (rtx x, enum machine_mode mem_mode)
2657 enum rtx_code code = GET_CODE (x);
2658 struct elim_table *ep;
2682 /* First handle the case where we encounter a bare register that
2683 is eliminable. Replace it with a PLUS. */
2684 if (regno < FIRST_PSEUDO_REGISTER)
2686 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2688 if (ep->from_rtx == x && ep->can_eliminate)
2691 ep->ref_outside_mem = 1;
2696 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2697 && reg_equiv_constant[regno]
2698 && ! function_invariant_p (reg_equiv_constant[regno]))
2699 elimination_effects (reg_equiv_constant[regno], mem_mode);
2708 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2709 if (ep->to_rtx == XEXP (x, 0))
2711 int size = GET_MODE_SIZE (mem_mode);
2713 /* If more bytes than MEM_MODE are pushed, account for them. */
2714 #ifdef PUSH_ROUNDING
2715 if (ep->to_rtx == stack_pointer_rtx)
2716 size = PUSH_ROUNDING (size);
2718 if (code == PRE_DEC || code == POST_DEC)
2720 else if (code == PRE_INC || code == POST_INC)
2722 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2723 && GET_CODE (XEXP (x, 1)) == PLUS
2724 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2725 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2726 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2729 /* These two aren't unary operators. */
2730 if (code == POST_MODIFY || code == PRE_MODIFY)
2733 /* Fall through to generic unary operation case. */
2734 case STRICT_LOW_PART:
2736 case SIGN_EXTEND: case ZERO_EXTEND:
2737 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2738 case FLOAT: case FIX:
2739 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2747 elimination_effects (XEXP (x, 0), mem_mode);
2751 if (REG_P (SUBREG_REG (x))
2752 && (GET_MODE_SIZE (GET_MODE (x))
2753 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2754 && reg_equiv_memory_loc != 0
2755 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2758 elimination_effects (SUBREG_REG (x), mem_mode);
2762 /* If using a register that is the source of an eliminate we still
2763 think can be performed, note it cannot be performed since we don't
2764 know how this register is used. */
2765 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2766 if (ep->from_rtx == XEXP (x, 0))
2767 ep->can_eliminate = 0;
2769 elimination_effects (XEXP (x, 0), mem_mode);
2773 /* If clobbering a register that is the replacement register for an
2774 elimination we still think can be performed, note that it cannot
2775 be performed. Otherwise, we need not be concerned about it. */
2776 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2777 if (ep->to_rtx == XEXP (x, 0))
2778 ep->can_eliminate = 0;
2780 elimination_effects (XEXP (x, 0), mem_mode);
2784 /* Check for setting a register that we know about. */
2785 if (REG_P (SET_DEST (x)))
2787 /* See if this is setting the replacement register for an
2790 If DEST is the hard frame pointer, we do nothing because we
2791 assume that all assignments to the frame pointer are for
2792 non-local gotos and are being done at a time when they are valid
2793 and do not disturb anything else. Some machines want to
2794 eliminate a fake argument pointer (or even a fake frame pointer)
2795 with either the real frame or the stack pointer. Assignments to
2796 the hard frame pointer must not prevent this elimination. */
2798 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2800 if (ep->to_rtx == SET_DEST (x)
2801 && SET_DEST (x) != hard_frame_pointer_rtx)
2803 /* If it is being incremented, adjust the offset. Otherwise,
2804 this elimination can't be done. */
2805 rtx src = SET_SRC (x);
2807 if (GET_CODE (src) == PLUS
2808 && XEXP (src, 0) == SET_DEST (x)
2809 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2810 ep->offset -= INTVAL (XEXP (src, 1));
2812 ep->can_eliminate = 0;
2816 elimination_effects (SET_DEST (x), 0);
2817 elimination_effects (SET_SRC (x), 0);
2821 /* Our only special processing is to pass the mode of the MEM to our
2823 elimination_effects (XEXP (x, 0), GET_MODE (x));
2830 fmt = GET_RTX_FORMAT (code);
2831 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2834 elimination_effects (XEXP (x, i), mem_mode);
2835 else if (*fmt == 'E')
2836 for (j = 0; j < XVECLEN (x, i); j++)
2837 elimination_effects (XVECEXP (x, i, j), mem_mode);
2841 /* Descend through rtx X and verify that no references to eliminable registers
2842 remain. If any do remain, mark the involved register as not
2846 check_eliminable_occurrences (rtx x)
2855 code = GET_CODE (x);
2857 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2859 struct elim_table *ep;
2861 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2862 if (ep->from_rtx == x)
2863 ep->can_eliminate = 0;
2867 fmt = GET_RTX_FORMAT (code);
2868 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2871 check_eliminable_occurrences (XEXP (x, i));
2872 else if (*fmt == 'E')
2875 for (j = 0; j < XVECLEN (x, i); j++)
2876 check_eliminable_occurrences (XVECEXP (x, i, j));
2881 /* Scan INSN and eliminate all eliminable registers in it.
2883 If REPLACE is nonzero, do the replacement destructively. Also
2884 delete the insn as dead it if it is setting an eliminable register.
2886 If REPLACE is zero, do all our allocations in reload_obstack.
2888 If no eliminations were done and this insn doesn't require any elimination
2889 processing (these are not identical conditions: it might be updating sp,
2890 but not referencing fp; this needs to be seen during reload_as_needed so
2891 that the offset between fp and sp can be taken into consideration), zero
2892 is returned. Otherwise, 1 is returned. */
2895 eliminate_regs_in_insn (rtx insn, int replace)
2897 int icode = recog_memoized (insn);
2898 rtx old_body = PATTERN (insn);
2899 int insn_is_asm = asm_noperands (old_body) >= 0;
2900 rtx old_set = single_set (insn);
2904 rtx substed_operand[MAX_RECOG_OPERANDS];
2905 rtx orig_operand[MAX_RECOG_OPERANDS];
2906 struct elim_table *ep;
2907 rtx plus_src, plus_cst_src;
2909 if (! insn_is_asm && icode < 0)
2911 gcc_assert (GET_CODE (PATTERN (insn)) == USE
2912 || GET_CODE (PATTERN (insn)) == CLOBBER
2913 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2914 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2915 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
2919 if (old_set != 0 && REG_P (SET_DEST (old_set))
2920 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2922 /* Check for setting an eliminable register. */
2923 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2924 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2926 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2927 /* If this is setting the frame pointer register to the
2928 hardware frame pointer register and this is an elimination
2929 that will be done (tested above), this insn is really
2930 adjusting the frame pointer downward to compensate for
2931 the adjustment done before a nonlocal goto. */
2932 if (ep->from == FRAME_POINTER_REGNUM
2933 && ep->to == HARD_FRAME_POINTER_REGNUM)
2935 rtx base = SET_SRC (old_set);
2936 rtx base_insn = insn;
2937 HOST_WIDE_INT offset = 0;
2939 while (base != ep->to_rtx)
2941 rtx prev_insn, prev_set;
2943 if (GET_CODE (base) == PLUS
2944 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2946 offset += INTVAL (XEXP (base, 1));
2947 base = XEXP (base, 0);
2949 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2950 && (prev_set = single_set (prev_insn)) != 0
2951 && rtx_equal_p (SET_DEST (prev_set), base))
2953 base = SET_SRC (prev_set);
2954 base_insn = prev_insn;
2960 if (base == ep->to_rtx)
2963 = plus_constant (ep->to_rtx, offset - ep->offset);
2965 new_body = old_body;
2968 new_body = copy_insn (old_body);
2969 if (REG_NOTES (insn))
2970 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2972 PATTERN (insn) = new_body;
2973 old_set = single_set (insn);
2975 /* First see if this insn remains valid when we
2976 make the change. If not, keep the INSN_CODE
2977 the same and let reload fit it up. */
2978 validate_change (insn, &SET_SRC (old_set), src, 1);
2979 validate_change (insn, &SET_DEST (old_set),
2981 if (! apply_change_group ())
2983 SET_SRC (old_set) = src;
2984 SET_DEST (old_set) = ep->to_rtx;
2993 /* In this case this insn isn't serving a useful purpose. We
2994 will delete it in reload_as_needed once we know that this
2995 elimination is, in fact, being done.
2997 If REPLACE isn't set, we can't delete this insn, but needn't
2998 process it since it won't be used unless something changes. */
3001 delete_dead_insn (insn);
3009 /* We allow one special case which happens to work on all machines we
3010 currently support: a single set with the source or a REG_EQUAL
3011 note being a PLUS of an eliminable register and a constant. */
3012 plus_src = plus_cst_src = 0;
3013 if (old_set && REG_P (SET_DEST (old_set)))
3015 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3016 plus_src = SET_SRC (old_set);
3017 /* First see if the source is of the form (plus (...) CST). */
3019 && GET_CODE (XEXP (plus_src, 1)) == CONST_INT)
3020 plus_cst_src = plus_src;
3021 else if (REG_P (SET_SRC (old_set))
3024 /* Otherwise, see if we have a REG_EQUAL note of the form
3025 (plus (...) CST). */
3027 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3029 if (REG_NOTE_KIND (links) == REG_EQUAL
3030 && GET_CODE (XEXP (links, 0)) == PLUS
3031 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT)
3033 plus_cst_src = XEXP (links, 0);
3039 /* Check that the first operand of the PLUS is a hard reg or
3040 the lowpart subreg of one. */
3043 rtx reg = XEXP (plus_cst_src, 0);
3044 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3045 reg = SUBREG_REG (reg);
3047 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3053 rtx reg = XEXP (plus_cst_src, 0);
3054 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3056 if (GET_CODE (reg) == SUBREG)
3057 reg = SUBREG_REG (reg);
3059 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3060 if (ep->from_rtx == reg && ep->can_eliminate)
3062 rtx to_rtx = ep->to_rtx;
3063 offset += ep->offset;
3065 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3066 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3071 /* We assume here that if we need a PARALLEL with
3072 CLOBBERs for this assignment, we can do with the
3073 MATCH_SCRATCHes that add_clobbers allocates.
3074 There's not much we can do if that doesn't work. */
3075 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3079 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3082 rtvec vec = rtvec_alloc (num_clobbers + 1);
3084 vec->elem[0] = PATTERN (insn);
3085 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3086 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3088 gcc_assert (INSN_CODE (insn) >= 0);
3090 /* If we have a nonzero offset, and the source is already
3091 a simple REG, the following transformation would
3092 increase the cost of the insn by replacing a simple REG
3093 with (plus (reg sp) CST). So try only when we already
3094 had a PLUS before. */
3097 new_body = old_body;
3100 new_body = copy_insn (old_body);
3101 if (REG_NOTES (insn))
3102 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3104 PATTERN (insn) = new_body;
3105 old_set = single_set (insn);
3107 XEXP (SET_SRC (old_set), 0) = to_rtx;
3108 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3114 /* This can't have an effect on elimination offsets, so skip right
3120 /* Determine the effects of this insn on elimination offsets. */
3121 elimination_effects (old_body, 0);
3123 /* Eliminate all eliminable registers occurring in operands that
3124 can be handled by reload. */
3125 extract_insn (insn);
3126 for (i = 0; i < recog_data.n_operands; i++)
3128 orig_operand[i] = recog_data.operand[i];
3129 substed_operand[i] = recog_data.operand[i];
3131 /* For an asm statement, every operand is eliminable. */
3132 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3134 bool is_set_src, in_plus;
3136 /* Check for setting a register that we know about. */
3137 if (recog_data.operand_type[i] != OP_IN
3138 && REG_P (orig_operand[i]))
3140 /* If we are assigning to a register that can be eliminated, it
3141 must be as part of a PARALLEL, since the code above handles
3142 single SETs. We must indicate that we can no longer
3143 eliminate this reg. */
3144 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3146 if (ep->from_rtx == orig_operand[i])
3147 ep->can_eliminate = 0;
3150 /* Companion to the above plus substitution, we can allow
3151 invariants as the source of a plain move. */
3153 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3157 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3158 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3162 = eliminate_regs_1 (recog_data.operand[i], 0,
3163 replace ? insn : NULL_RTX,
3164 is_set_src || in_plus);
3165 if (substed_operand[i] != orig_operand[i])
3167 /* Terminate the search in check_eliminable_occurrences at
3169 *recog_data.operand_loc[i] = 0;
3171 /* If an output operand changed from a REG to a MEM and INSN is an
3172 insn, write a CLOBBER insn. */
3173 if (recog_data.operand_type[i] != OP_IN
3174 && REG_P (orig_operand[i])
3175 && MEM_P (substed_operand[i])
3177 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3182 for (i = 0; i < recog_data.n_dups; i++)
3183 *recog_data.dup_loc[i]
3184 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3186 /* If any eliminable remain, they aren't eliminable anymore. */
3187 check_eliminable_occurrences (old_body);
3189 /* Substitute the operands; the new values are in the substed_operand
3191 for (i = 0; i < recog_data.n_operands; i++)
3192 *recog_data.operand_loc[i] = substed_operand[i];
3193 for (i = 0; i < recog_data.n_dups; i++)
3194 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3196 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3197 re-recognize the insn. We do this in case we had a simple addition
3198 but now can do this as a load-address. This saves an insn in this
3200 If re-recognition fails, the old insn code number will still be used,
3201 and some register operands may have changed into PLUS expressions.
3202 These will be handled by find_reloads by loading them into a register
3207 /* If we aren't replacing things permanently and we changed something,
3208 make another copy to ensure that all the RTL is new. Otherwise
3209 things can go wrong if find_reload swaps commutative operands
3210 and one is inside RTL that has been copied while the other is not. */
3211 new_body = old_body;
3214 new_body = copy_insn (old_body);
3215 if (REG_NOTES (insn))
3216 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3218 PATTERN (insn) = new_body;
3220 /* If we had a move insn but now we don't, rerecognize it. This will
3221 cause spurious re-recognition if the old move had a PARALLEL since
3222 the new one still will, but we can't call single_set without
3223 having put NEW_BODY into the insn and the re-recognition won't
3224 hurt in this rare case. */
3225 /* ??? Why this huge if statement - why don't we just rerecognize the
3229 && ((REG_P (SET_SRC (old_set))
3230 && (GET_CODE (new_body) != SET
3231 || !REG_P (SET_SRC (new_body))))
3232 /* If this was a load from or store to memory, compare
3233 the MEM in recog_data.operand to the one in the insn.
3234 If they are not equal, then rerecognize the insn. */
3236 && ((MEM_P (SET_SRC (old_set))
3237 && SET_SRC (old_set) != recog_data.operand[1])
3238 || (MEM_P (SET_DEST (old_set))
3239 && SET_DEST (old_set) != recog_data.operand[0])))
3240 /* If this was an add insn before, rerecognize. */
3241 || GET_CODE (SET_SRC (old_set)) == PLUS))
3243 int new_icode = recog (PATTERN (insn), insn, 0);
3245 INSN_CODE (insn) = new_icode;
3249 /* Restore the old body. If there were any changes to it, we made a copy
3250 of it while the changes were still in place, so we'll correctly return
3251 a modified insn below. */
3254 /* Restore the old body. */
3255 for (i = 0; i < recog_data.n_operands; i++)
3256 *recog_data.operand_loc[i] = orig_operand[i];
3257 for (i = 0; i < recog_data.n_dups; i++)
3258 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3261 /* Update all elimination pairs to reflect the status after the current
3262 insn. The changes we make were determined by the earlier call to
3263 elimination_effects.
3265 We also detect cases where register elimination cannot be done,
3266 namely, if a register would be both changed and referenced outside a MEM
3267 in the resulting insn since such an insn is often undefined and, even if
3268 not, we cannot know what meaning will be given to it. Note that it is
3269 valid to have a register used in an address in an insn that changes it
3270 (presumably with a pre- or post-increment or decrement).
3272 If anything changes, return nonzero. */
3274 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3276 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3277 ep->can_eliminate = 0;
3279 ep->ref_outside_mem = 0;
3281 if (ep->previous_offset != ep->offset)
3286 /* If we changed something, perform elimination in REG_NOTES. This is
3287 needed even when REPLACE is zero because a REG_DEAD note might refer
3288 to a register that we eliminate and could cause a different number
3289 of spill registers to be needed in the final reload pass than in
3291 if (val && REG_NOTES (insn) != 0)
3293 = eliminate_regs_1 (REG_NOTES (insn), 0, REG_NOTES (insn), true);
3298 /* Loop through all elimination pairs.
3299 Recalculate the number not at initial offset.
3301 Compute the maximum offset (minimum offset if the stack does not
3302 grow downward) for each elimination pair. */
3305 update_eliminable_offsets (void)
3307 struct elim_table *ep;
3309 num_not_at_initial_offset = 0;
3310 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3312 ep->previous_offset = ep->offset;
3313 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3314 num_not_at_initial_offset++;
3318 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3319 replacement we currently believe is valid, mark it as not eliminable if X
3320 modifies DEST in any way other than by adding a constant integer to it.
3322 If DEST is the frame pointer, we do nothing because we assume that
3323 all assignments to the hard frame pointer are nonlocal gotos and are being
3324 done at a time when they are valid and do not disturb anything else.
3325 Some machines want to eliminate a fake argument pointer with either the
3326 frame or stack pointer. Assignments to the hard frame pointer must not
3327 prevent this elimination.
3329 Called via note_stores from reload before starting its passes to scan
3330 the insns of the function. */
3333 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3337 /* A SUBREG of a hard register here is just changing its mode. We should
3338 not see a SUBREG of an eliminable hard register, but check just in
3340 if (GET_CODE (dest) == SUBREG)
3341 dest = SUBREG_REG (dest);
3343 if (dest == hard_frame_pointer_rtx)
3346 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3347 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3348 && (GET_CODE (x) != SET
3349 || GET_CODE (SET_SRC (x)) != PLUS
3350 || XEXP (SET_SRC (x), 0) != dest
3351 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3353 reg_eliminate[i].can_eliminate_previous
3354 = reg_eliminate[i].can_eliminate = 0;
3359 /* Verify that the initial elimination offsets did not change since the
3360 last call to set_initial_elim_offsets. This is used to catch cases
3361 where something illegal happened during reload_as_needed that could
3362 cause incorrect code to be generated if we did not check for it. */
3365 verify_initial_elim_offsets (void)
3369 if (!num_eliminable)
3372 #ifdef ELIMINABLE_REGS
3374 struct elim_table *ep;
3376 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3378 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3379 if (t != ep->initial_offset)
3384 INITIAL_FRAME_POINTER_OFFSET (t);
3385 if (t != reg_eliminate[0].initial_offset)
3392 /* Reset all offsets on eliminable registers to their initial values. */
3395 set_initial_elim_offsets (void)
3397 struct elim_table *ep = reg_eliminate;
3399 #ifdef ELIMINABLE_REGS
3400 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3402 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3403 ep->previous_offset = ep->offset = ep->initial_offset;
3406 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3407 ep->previous_offset = ep->offset = ep->initial_offset;
3410 num_not_at_initial_offset = 0;
3413 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3416 set_initial_eh_label_offset (rtx label)
3418 set_label_offsets (label, NULL_RTX, 1);
3421 /* Initialize the known label offsets.
3422 Set a known offset for each forced label to be at the initial offset
3423 of each elimination. We do this because we assume that all
3424 computed jumps occur from a location where each elimination is
3425 at its initial offset.
3426 For all other labels, show that we don't know the offsets. */
3429 set_initial_label_offsets (void)
3432 memset (offsets_known_at, 0, num_labels);
3434 for (x = forced_labels; x; x = XEXP (x, 1))
3436 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3438 for_each_eh_label (set_initial_eh_label_offset);
3441 /* Set all elimination offsets to the known values for the code label given
3445 set_offsets_for_label (rtx insn)
3448 int label_nr = CODE_LABEL_NUMBER (insn);
3449 struct elim_table *ep;
3451 num_not_at_initial_offset = 0;
3452 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3454 ep->offset = ep->previous_offset
3455 = offsets_at[label_nr - first_label_num][i];
3456 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3457 num_not_at_initial_offset++;
3461 /* See if anything that happened changes which eliminations are valid.
3462 For example, on the SPARC, whether or not the frame pointer can
3463 be eliminated can depend on what registers have been used. We need
3464 not check some conditions again (such as flag_omit_frame_pointer)
3465 since they can't have changed. */
3468 update_eliminables (HARD_REG_SET *pset)
3470 int previous_frame_pointer_needed = frame_pointer_needed;
3471 struct elim_table *ep;
3473 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3474 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3475 #ifdef ELIMINABLE_REGS
3476 || ! CAN_ELIMINATE (ep->from, ep->to)
3479 ep->can_eliminate = 0;
3481 /* Look for the case where we have discovered that we can't replace
3482 register A with register B and that means that we will now be
3483 trying to replace register A with register C. This means we can
3484 no longer replace register C with register B and we need to disable
3485 such an elimination, if it exists. This occurs often with A == ap,
3486 B == sp, and C == fp. */
3488 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3490 struct elim_table *op;
3493 if (! ep->can_eliminate && ep->can_eliminate_previous)
3495 /* Find the current elimination for ep->from, if there is a
3497 for (op = reg_eliminate;
3498 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3499 if (op->from == ep->from && op->can_eliminate)
3505 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3507 for (op = reg_eliminate;
3508 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3509 if (op->from == new_to && op->to == ep->to)
3510 op->can_eliminate = 0;
3514 /* See if any registers that we thought we could eliminate the previous
3515 time are no longer eliminable. If so, something has changed and we
3516 must spill the register. Also, recompute the number of eliminable
3517 registers and see if the frame pointer is needed; it is if there is
3518 no elimination of the frame pointer that we can perform. */
3520 frame_pointer_needed = 1;
3521 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3523 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3524 && ep->to != HARD_FRAME_POINTER_REGNUM)
3525 frame_pointer_needed = 0;
3527 if (! ep->can_eliminate && ep->can_eliminate_previous)
3529 ep->can_eliminate_previous = 0;
3530 SET_HARD_REG_BIT (*pset, ep->from);
3535 /* If we didn't need a frame pointer last time, but we do now, spill
3536 the hard frame pointer. */
3537 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3538 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3541 /* Initialize the table of registers to eliminate. */
3544 init_elim_table (void)
3546 struct elim_table *ep;
3547 #ifdef ELIMINABLE_REGS
3548 const struct elim_table_1 *ep1;
3552 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3554 /* Does this function require a frame pointer? */
3556 frame_pointer_needed = (! flag_omit_frame_pointer
3557 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3558 and restore sp for alloca. So we can't eliminate
3559 the frame pointer in that case. At some point,
3560 we should improve this by emitting the
3561 sp-adjusting insns for this case. */
3562 || (current_function_calls_alloca
3563 && EXIT_IGNORE_STACK)
3564 || current_function_accesses_prior_frames
3565 || FRAME_POINTER_REQUIRED);
3569 #ifdef ELIMINABLE_REGS
3570 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3571 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3573 ep->from = ep1->from;
3575 ep->can_eliminate = ep->can_eliminate_previous
3576 = (CAN_ELIMINATE (ep->from, ep->to)
3577 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3580 reg_eliminate[0].from = reg_eliminate_1[0].from;
3581 reg_eliminate[0].to = reg_eliminate_1[0].to;
3582 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3583 = ! frame_pointer_needed;
3586 /* Count the number of eliminable registers and build the FROM and TO
3587 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3588 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3589 We depend on this. */
3590 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3592 num_eliminable += ep->can_eliminate;
3593 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3594 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3598 /* Kick all pseudos out of hard register REGNO.
3600 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3601 because we found we can't eliminate some register. In the case, no pseudos
3602 are allowed to be in the register, even if they are only in a block that
3603 doesn't require spill registers, unlike the case when we are spilling this
3604 hard reg to produce another spill register.
3606 Return nonzero if any pseudos needed to be kicked out. */
3609 spill_hard_reg (unsigned int regno, int cant_eliminate)
3615 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3616 regs_ever_live[regno] = 1;
3619 /* Spill every pseudo reg that was allocated to this reg
3620 or to something that overlaps this reg. */
3622 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3623 if (reg_renumber[i] >= 0
3624 && (unsigned int) reg_renumber[i] <= regno
3625 && ((unsigned int) reg_renumber[i]
3626 + hard_regno_nregs[(unsigned int) reg_renumber[i]]
3627 [PSEUDO_REGNO_MODE (i)]
3629 SET_REGNO_REG_SET (&spilled_pseudos, i);
3632 /* After find_reload_regs has been run for all insn that need reloads,
3633 and/or spill_hard_regs was called, this function is used to actually
3634 spill pseudo registers and try to reallocate them. It also sets up the
3635 spill_regs array for use by choose_reload_regs. */
3638 finish_spills (int global)
3640 struct insn_chain *chain;
3641 int something_changed = 0;
3643 reg_set_iterator rsi;
3645 /* Build the spill_regs array for the function. */
3646 /* If there are some registers still to eliminate and one of the spill regs
3647 wasn't ever used before, additional stack space may have to be
3648 allocated to store this register. Thus, we may have changed the offset
3649 between the stack and frame pointers, so mark that something has changed.
3651 One might think that we need only set VAL to 1 if this is a call-used
3652 register. However, the set of registers that must be saved by the
3653 prologue is not identical to the call-used set. For example, the
3654 register used by the call insn for the return PC is a call-used register,
3655 but must be saved by the prologue. */
3658 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3659 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3661 spill_reg_order[i] = n_spills;
3662 spill_regs[n_spills++] = i;
3663 if (num_eliminable && ! regs_ever_live[i])
3664 something_changed = 1;
3665 regs_ever_live[i] = 1;
3668 spill_reg_order[i] = -1;
3670 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3672 /* Record the current hard register the pseudo is allocated to in
3673 pseudo_previous_regs so we avoid reallocating it to the same
3674 hard reg in a later pass. */
3675 gcc_assert (reg_renumber[i] >= 0);
3677 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3678 /* Mark it as no longer having a hard register home. */
3679 reg_renumber[i] = -1;
3680 /* We will need to scan everything again. */
3681 something_changed = 1;
3684 /* Retry global register allocation if possible. */
3687 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3688 /* For every insn that needs reloads, set the registers used as spill
3689 regs in pseudo_forbidden_regs for every pseudo live across the
3691 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3693 EXECUTE_IF_SET_IN_REG_SET
3694 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3696 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3697 chain->used_spill_regs);
3699 EXECUTE_IF_SET_IN_REG_SET
3700 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3702 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3703 chain->used_spill_regs);
3707 /* Retry allocating the spilled pseudos. For each reg, merge the
3708 various reg sets that indicate which hard regs can't be used,
3709 and call retry_global_alloc.
3710 We change spill_pseudos here to only contain pseudos that did not
3711 get a new hard register. */
3712 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3713 if (reg_old_renumber[i] != reg_renumber[i])
3715 HARD_REG_SET forbidden;
3716 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3717 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3718 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3719 retry_global_alloc (i, forbidden);
3720 if (reg_renumber[i] >= 0)
3721 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3725 /* Fix up the register information in the insn chain.
3726 This involves deleting those of the spilled pseudos which did not get
3727 a new hard register home from the live_{before,after} sets. */
3728 for (chain = reload_insn_chain; chain; chain = chain->next)
3730 HARD_REG_SET used_by_pseudos;
3731 HARD_REG_SET used_by_pseudos2;
3733 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3734 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3736 /* Mark any unallocated hard regs as available for spills. That
3737 makes inheritance work somewhat better. */
3738 if (chain->need_reload)
3740 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3741 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3742 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3744 /* Save the old value for the sanity test below. */
3745 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3747 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3748 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3749 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3750 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3752 /* Make sure we only enlarge the set. */
3753 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3759 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3760 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3762 int regno = reg_renumber[i];
3763 if (reg_old_renumber[i] == regno)
3766 alter_reg (i, reg_old_renumber[i]);
3767 reg_old_renumber[i] = regno;
3771 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3773 fprintf (dump_file, " Register %d now in %d.\n\n",
3774 i, reg_renumber[i]);
3778 return something_changed;
3781 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3784 scan_paradoxical_subregs (rtx x)
3788 enum rtx_code code = GET_CODE (x);
3798 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3806 if (REG_P (SUBREG_REG (x))
3807 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3808 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3809 = GET_MODE_SIZE (GET_MODE (x));
3816 fmt = GET_RTX_FORMAT (code);
3817 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3820 scan_paradoxical_subregs (XEXP (x, i));
3821 else if (fmt[i] == 'E')
3824 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3825 scan_paradoxical_subregs (XVECEXP (x, i, j));
3830 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
3831 examine all of the reload insns between PREV and NEXT exclusive, and
3832 annotate all that may trap. */
3835 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
3837 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
3838 unsigned int trap_count;
3844 if (may_trap_p (PATTERN (insn)))
3848 remove_note (insn, note);
3852 for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i))
3853 if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i)))
3857 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (note, 0), REG_NOTES (i));
3861 /* Reload pseudo-registers into hard regs around each insn as needed.
3862 Additional register load insns are output before the insn that needs it
3863 and perhaps store insns after insns that modify the reloaded pseudo reg.
3865 reg_last_reload_reg and reg_reloaded_contents keep track of
3866 which registers are already available in reload registers.
3867 We update these for the reloads that we perform,
3868 as the insns are scanned. */
3871 reload_as_needed (int live_known)
3873 struct insn_chain *chain;
3874 #if defined (AUTO_INC_DEC)
3879 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3880 memset (spill_reg_store, 0, sizeof spill_reg_store);
3881 reg_last_reload_reg = xcalloc (max_regno, sizeof (rtx));
3882 reg_has_output_reload = xmalloc (max_regno);
3883 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3884 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
3886 set_initial_elim_offsets ();
3888 for (chain = reload_insn_chain; chain; chain = chain->next)
3891 rtx insn = chain->insn;
3892 rtx old_next = NEXT_INSN (insn);
3894 /* If we pass a label, copy the offsets from the label information
3895 into the current offsets of each elimination. */
3897 set_offsets_for_label (insn);
3899 else if (INSN_P (insn))
3901 rtx oldpat = copy_rtx (PATTERN (insn));
3903 /* If this is a USE and CLOBBER of a MEM, ensure that any
3904 references to eliminable registers have been removed. */
3906 if ((GET_CODE (PATTERN (insn)) == USE
3907 || GET_CODE (PATTERN (insn)) == CLOBBER)
3908 && MEM_P (XEXP (PATTERN (insn), 0)))
3909 XEXP (XEXP (PATTERN (insn), 0), 0)
3910 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3911 GET_MODE (XEXP (PATTERN (insn), 0)),
3914 /* If we need to do register elimination processing, do so.
3915 This might delete the insn, in which case we are done. */
3916 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3918 eliminate_regs_in_insn (insn, 1);
3921 update_eliminable_offsets ();
3926 /* If need_elim is nonzero but need_reload is zero, one might think
3927 that we could simply set n_reloads to 0. However, find_reloads
3928 could have done some manipulation of the insn (such as swapping
3929 commutative operands), and these manipulations are lost during
3930 the first pass for every insn that needs register elimination.
3931 So the actions of find_reloads must be redone here. */
3933 if (! chain->need_elim && ! chain->need_reload
3934 && ! chain->need_operand_change)
3936 /* First find the pseudo regs that must be reloaded for this insn.
3937 This info is returned in the tables reload_... (see reload.h).
3938 Also modify the body of INSN by substituting RELOAD
3939 rtx's for those pseudo regs. */
3942 memset (reg_has_output_reload, 0, max_regno);
3943 CLEAR_HARD_REG_SET (reg_is_output_reload);
3945 find_reloads (insn, 1, spill_indirect_levels, live_known,
3951 rtx next = NEXT_INSN (insn);
3954 prev = PREV_INSN (insn);
3956 /* Now compute which reload regs to reload them into. Perhaps
3957 reusing reload regs from previous insns, or else output
3958 load insns to reload them. Maybe output store insns too.
3959 Record the choices of reload reg in reload_reg_rtx. */
3960 choose_reload_regs (chain);
3962 /* Merge any reloads that we didn't combine for fear of
3963 increasing the number of spill registers needed but now
3964 discover can be safely merged. */
3965 if (SMALL_REGISTER_CLASSES)
3966 merge_assigned_reloads (insn);
3968 /* Generate the insns to reload operands into or out of
3969 their reload regs. */
3970 emit_reload_insns (chain);
3972 /* Substitute the chosen reload regs from reload_reg_rtx
3973 into the insn's body (or perhaps into the bodies of other
3974 load and store insn that we just made for reloading
3975 and that we moved the structure into). */
3976 subst_reloads (insn);
3978 /* Adjust the exception region notes for loads and stores. */
3979 if (flag_non_call_exceptions && !CALL_P (insn))
3980 fixup_eh_region_note (insn, prev, next);
3982 /* If this was an ASM, make sure that all the reload insns
3983 we have generated are valid. If not, give an error
3985 if (asm_noperands (PATTERN (insn)) >= 0)
3986 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3987 if (p != insn && INSN_P (p)
3988 && GET_CODE (PATTERN (p)) != USE
3989 && (recog_memoized (p) < 0
3990 || (extract_insn (p), ! constrain_operands (1))))
3992 error_for_asm (insn,
3993 "%<asm%> operand requires "
3994 "impossible reload");
3999 if (num_eliminable && chain->need_elim)
4000 update_eliminable_offsets ();
4002 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4003 is no longer validly lying around to save a future reload.
4004 Note that this does not detect pseudos that were reloaded
4005 for this insn in order to be stored in
4006 (obeying register constraints). That is correct; such reload
4007 registers ARE still valid. */
4008 note_stores (oldpat, forget_old_reloads_1, NULL);
4010 /* There may have been CLOBBER insns placed after INSN. So scan
4011 between INSN and NEXT and use them to forget old reloads. */
4012 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4013 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4014 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4017 /* Likewise for regs altered by auto-increment in this insn.
4018 REG_INC notes have been changed by reloading:
4019 find_reloads_address_1 records substitutions for them,
4020 which have been performed by subst_reloads above. */
4021 for (i = n_reloads - 1; i >= 0; i--)
4023 rtx in_reg = rld[i].in_reg;
4026 enum rtx_code code = GET_CODE (in_reg);
4027 /* PRE_INC / PRE_DEC will have the reload register ending up
4028 with the same value as the stack slot, but that doesn't
4029 hold true for POST_INC / POST_DEC. Either we have to
4030 convert the memory access to a true POST_INC / POST_DEC,
4031 or we can't use the reload register for inheritance. */
4032 if ((code == POST_INC || code == POST_DEC)
4033 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4034 REGNO (rld[i].reg_rtx))
4035 /* Make sure it is the inc/dec pseudo, and not
4036 some other (e.g. output operand) pseudo. */
4037 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4038 == REGNO (XEXP (in_reg, 0))))
4041 rtx reload_reg = rld[i].reg_rtx;
4042 enum machine_mode mode = GET_MODE (reload_reg);
4046 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4048 /* We really want to ignore REG_INC notes here, so
4049 use PATTERN (p) as argument to reg_set_p . */
4050 if (reg_set_p (reload_reg, PATTERN (p)))
4052 n = count_occurrences (PATTERN (p), reload_reg, 0);
4057 n = validate_replace_rtx (reload_reg,
4058 gen_rtx_fmt_e (code,
4063 /* We must also verify that the constraints
4064 are met after the replacement. */
4067 n = constrain_operands (1);
4071 /* If the constraints were not met, then
4072 undo the replacement. */
4075 validate_replace_rtx (gen_rtx_fmt_e (code,
4088 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4090 /* Mark this as having an output reload so that the
4091 REG_INC processing code below won't invalidate
4092 the reload for inheritance. */
4093 SET_HARD_REG_BIT (reg_is_output_reload,
4094 REGNO (reload_reg));
4095 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4098 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4101 else if ((code == PRE_INC || code == PRE_DEC)
4102 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4103 REGNO (rld[i].reg_rtx))
4104 /* Make sure it is the inc/dec pseudo, and not
4105 some other (e.g. output operand) pseudo. */
4106 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4107 == REGNO (XEXP (in_reg, 0))))
4109 SET_HARD_REG_BIT (reg_is_output_reload,
4110 REGNO (rld[i].reg_rtx));
4111 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4115 /* If a pseudo that got a hard register is auto-incremented,
4116 we must purge records of copying it into pseudos without
4118 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4119 if (REG_NOTE_KIND (x) == REG_INC)
4121 /* See if this pseudo reg was reloaded in this insn.
4122 If so, its last-reload info is still valid
4123 because it is based on this insn's reload. */
4124 for (i = 0; i < n_reloads; i++)
4125 if (rld[i].out == XEXP (x, 0))
4129 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4133 /* A reload reg's contents are unknown after a label. */
4135 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4137 /* Don't assume a reload reg is still good after a call insn
4138 if it is a call-used reg, or if it contains a value that will
4139 be partially clobbered by the call. */
4140 else if (CALL_P (insn))
4142 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4143 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4148 free (reg_last_reload_reg);
4149 free (reg_has_output_reload);
4152 /* Discard all record of any value reloaded from X,
4153 or reloaded in X from someplace else;
4154 unless X is an output reload reg of the current insn.
4156 X may be a hard reg (the reload reg)
4157 or it may be a pseudo reg that was reloaded from. */
4160 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4161 void *data ATTRIBUTE_UNUSED)
4166 /* note_stores does give us subregs of hard regs,
4167 subreg_regno_offset requires a hard reg. */
4168 while (GET_CODE (x) == SUBREG)
4170 /* We ignore the subreg offset when calculating the regno,
4171 because we are using the entire underlying hard register
4181 if (regno >= FIRST_PSEUDO_REGISTER)
4187 nr = hard_regno_nregs[regno][GET_MODE (x)];
4188 /* Storing into a spilled-reg invalidates its contents.
4189 This can happen if a block-local pseudo is allocated to that reg
4190 and it wasn't spilled because this block's total need is 0.
4191 Then some insn might have an optional reload and use this reg. */
4192 for (i = 0; i < nr; i++)
4193 /* But don't do this if the reg actually serves as an output
4194 reload reg in the current instruction. */
4196 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4198 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4199 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4200 spill_reg_store[regno + i] = 0;
4204 /* Since value of X has changed,
4205 forget any value previously copied from it. */
4208 /* But don't forget a copy if this is the output reload
4209 that establishes the copy's validity. */
4210 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4211 reg_last_reload_reg[regno + nr] = 0;
4214 /* The following HARD_REG_SETs indicate when each hard register is
4215 used for a reload of various parts of the current insn. */
4217 /* If reg is unavailable for all reloads. */
4218 static HARD_REG_SET reload_reg_unavailable;
4219 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4220 static HARD_REG_SET reload_reg_used;
4221 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4222 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4223 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4224 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4225 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4226 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4227 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4228 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4229 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4230 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4231 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4232 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4233 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4234 static HARD_REG_SET reload_reg_used_in_op_addr;
4235 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4236 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4237 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4238 static HARD_REG_SET reload_reg_used_in_insn;
4239 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4240 static HARD_REG_SET reload_reg_used_in_other_addr;
4242 /* If reg is in use as a reload reg for any sort of reload. */
4243 static HARD_REG_SET reload_reg_used_at_all;
4245 /* If reg is use as an inherited reload. We just mark the first register
4247 static HARD_REG_SET reload_reg_used_for_inherit;
4249 /* Records which hard regs are used in any way, either as explicit use or
4250 by being allocated to a pseudo during any point of the current insn. */
4251 static HARD_REG_SET reg_used_in_insn;
4253 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4254 TYPE. MODE is used to indicate how many consecutive regs are
4258 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4259 enum machine_mode mode)
4261 unsigned int nregs = hard_regno_nregs[regno][mode];
4264 for (i = regno; i < nregs + regno; i++)
4269 SET_HARD_REG_BIT (reload_reg_used, i);
4272 case RELOAD_FOR_INPUT_ADDRESS:
4273 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4276 case RELOAD_FOR_INPADDR_ADDRESS:
4277 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4280 case RELOAD_FOR_OUTPUT_ADDRESS:
4281 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4284 case RELOAD_FOR_OUTADDR_ADDRESS:
4285 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4288 case RELOAD_FOR_OPERAND_ADDRESS:
4289 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4292 case RELOAD_FOR_OPADDR_ADDR:
4293 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4296 case RELOAD_FOR_OTHER_ADDRESS:
4297 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4300 case RELOAD_FOR_INPUT:
4301 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4304 case RELOAD_FOR_OUTPUT:
4305 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4308 case RELOAD_FOR_INSN:
4309 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4313 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4317 /* Similarly, but show REGNO is no longer in use for a reload. */
4320 clear_reload_reg_in_use (unsigned int regno, int opnum,
4321 enum reload_type type, enum machine_mode mode)
4323 unsigned int nregs = hard_regno_nregs[regno][mode];
4324 unsigned int start_regno, end_regno, r;
4326 /* A complication is that for some reload types, inheritance might
4327 allow multiple reloads of the same types to share a reload register.
4328 We set check_opnum if we have to check only reloads with the same
4329 operand number, and check_any if we have to check all reloads. */
4330 int check_opnum = 0;
4332 HARD_REG_SET *used_in_set;
4337 used_in_set = &reload_reg_used;
4340 case RELOAD_FOR_INPUT_ADDRESS:
4341 used_in_set = &reload_reg_used_in_input_addr[opnum];
4344 case RELOAD_FOR_INPADDR_ADDRESS:
4346 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4349 case RELOAD_FOR_OUTPUT_ADDRESS:
4350 used_in_set = &reload_reg_used_in_output_addr[opnum];
4353 case RELOAD_FOR_OUTADDR_ADDRESS:
4355 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4358 case RELOAD_FOR_OPERAND_ADDRESS:
4359 used_in_set = &reload_reg_used_in_op_addr;
4362 case RELOAD_FOR_OPADDR_ADDR:
4364 used_in_set = &reload_reg_used_in_op_addr_reload;
4367 case RELOAD_FOR_OTHER_ADDRESS:
4368 used_in_set = &reload_reg_used_in_other_addr;
4372 case RELOAD_FOR_INPUT:
4373 used_in_set = &reload_reg_used_in_input[opnum];
4376 case RELOAD_FOR_OUTPUT:
4377 used_in_set = &reload_reg_used_in_output[opnum];
4380 case RELOAD_FOR_INSN:
4381 used_in_set = &reload_reg_used_in_insn;
4386 /* We resolve conflicts with remaining reloads of the same type by
4387 excluding the intervals of reload registers by them from the
4388 interval of freed reload registers. Since we only keep track of
4389 one set of interval bounds, we might have to exclude somewhat
4390 more than what would be necessary if we used a HARD_REG_SET here.
4391 But this should only happen very infrequently, so there should
4392 be no reason to worry about it. */
4394 start_regno = regno;
4395 end_regno = regno + nregs;
4396 if (check_opnum || check_any)
4398 for (i = n_reloads - 1; i >= 0; i--)
4400 if (rld[i].when_needed == type
4401 && (check_any || rld[i].opnum == opnum)
4404 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4405 unsigned int conflict_end
4407 + hard_regno_nregs[conflict_start][rld[i].mode]);
4409 /* If there is an overlap with the first to-be-freed register,
4410 adjust the interval start. */
4411 if (conflict_start <= start_regno && conflict_end > start_regno)
4412 start_regno = conflict_end;
4413 /* Otherwise, if there is a conflict with one of the other
4414 to-be-freed registers, adjust the interval end. */
4415 if (conflict_start > start_regno && conflict_start < end_regno)
4416 end_regno = conflict_start;
4421 for (r = start_regno; r < end_regno; r++)
4422 CLEAR_HARD_REG_BIT (*used_in_set, r);
4425 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4426 specified by OPNUM and TYPE. */
4429 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4433 /* In use for a RELOAD_OTHER means it's not available for anything. */
4434 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4435 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4441 /* In use for anything means we can't use it for RELOAD_OTHER. */
4442 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4443 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4444 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4445 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4448 for (i = 0; i < reload_n_operands; i++)
4449 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4450 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4451 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4452 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4453 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4454 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4459 case RELOAD_FOR_INPUT:
4460 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4461 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4464 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4467 /* If it is used for some other input, can't use it. */
4468 for (i = 0; i < reload_n_operands; i++)
4469 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4472 /* If it is used in a later operand's address, can't use it. */
4473 for (i = opnum + 1; i < reload_n_operands; i++)
4474 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4475 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4480 case RELOAD_FOR_INPUT_ADDRESS:
4481 /* Can't use a register if it is used for an input address for this
4482 operand or used as an input in an earlier one. */
4483 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4484 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4487 for (i = 0; i < opnum; i++)
4488 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4493 case RELOAD_FOR_INPADDR_ADDRESS:
4494 /* Can't use a register if it is used for an input address
4495 for this operand or used as an input in an earlier
4497 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4500 for (i = 0; i < opnum; i++)
4501 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4506 case RELOAD_FOR_OUTPUT_ADDRESS:
4507 /* Can't use a register if it is used for an output address for this
4508 operand or used as an output in this or a later operand. Note
4509 that multiple output operands are emitted in reverse order, so
4510 the conflicting ones are those with lower indices. */
4511 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4514 for (i = 0; i <= opnum; i++)
4515 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4520 case RELOAD_FOR_OUTADDR_ADDRESS:
4521 /* Can't use a register if it is used for an output address
4522 for this operand or used as an output in this or a
4523 later operand. Note that multiple output operands are
4524 emitted in reverse order, so the conflicting ones are
4525 those with lower indices. */
4526 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4529 for (i = 0; i <= opnum; i++)
4530 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4535 case RELOAD_FOR_OPERAND_ADDRESS:
4536 for (i = 0; i < reload_n_operands; i++)
4537 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4540 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4541 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4543 case RELOAD_FOR_OPADDR_ADDR:
4544 for (i = 0; i < reload_n_operands; i++)
4545 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4548 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4550 case RELOAD_FOR_OUTPUT:
4551 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4552 outputs, or an operand address for this or an earlier output.
4553 Note that multiple output operands are emitted in reverse order,
4554 so the conflicting ones are those with higher indices. */
4555 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4558 for (i = 0; i < reload_n_operands; i++)
4559 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4562 for (i = opnum; i < reload_n_operands; i++)
4563 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4564 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4569 case RELOAD_FOR_INSN:
4570 for (i = 0; i < reload_n_operands; i++)
4571 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4572 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4575 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4576 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4578 case RELOAD_FOR_OTHER_ADDRESS:
4579 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4586 /* Return 1 if the value in reload reg REGNO, as used by a reload
4587 needed for the part of the insn specified by OPNUM and TYPE,
4588 is still available in REGNO at the end of the insn.
4590 We can assume that the reload reg was already tested for availability
4591 at the time it is needed, and we should not check this again,
4592 in case the reg has already been marked in use. */
4595 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4602 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4603 its value must reach the end. */
4606 /* If this use is for part of the insn,
4607 its value reaches if no subsequent part uses the same register.
4608 Just like the above function, don't try to do this with lots
4611 case RELOAD_FOR_OTHER_ADDRESS:
4612 /* Here we check for everything else, since these don't conflict
4613 with anything else and everything comes later. */
4615 for (i = 0; i < reload_n_operands; i++)
4616 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4617 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4618 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4619 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4620 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4621 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4624 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4625 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4626 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4627 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4629 case RELOAD_FOR_INPUT_ADDRESS:
4630 case RELOAD_FOR_INPADDR_ADDRESS:
4631 /* Similar, except that we check only for this and subsequent inputs
4632 and the address of only subsequent inputs and we do not need
4633 to check for RELOAD_OTHER objects since they are known not to
4636 for (i = opnum; i < reload_n_operands; i++)
4637 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4640 for (i = opnum + 1; i < reload_n_operands; i++)
4641 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4642 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4645 for (i = 0; i < reload_n_operands; i++)
4646 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4647 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4648 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4651 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4654 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4655 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4656 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4658 case RELOAD_FOR_INPUT:
4659 /* Similar to input address, except we start at the next operand for
4660 both input and input address and we do not check for
4661 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4664 for (i = opnum + 1; i < reload_n_operands; i++)
4665 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4666 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4667 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4670 /* ... fall through ... */
4672 case RELOAD_FOR_OPERAND_ADDRESS:
4673 /* Check outputs and their addresses. */
4675 for (i = 0; i < reload_n_operands; i++)
4676 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4677 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4678 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4681 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4683 case RELOAD_FOR_OPADDR_ADDR:
4684 for (i = 0; i < reload_n_operands; i++)
4685 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4686 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4687 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4690 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4691 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4692 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4694 case RELOAD_FOR_INSN:
4695 /* These conflict with other outputs with RELOAD_OTHER. So
4696 we need only check for output addresses. */
4698 opnum = reload_n_operands;
4700 /* ... fall through ... */
4702 case RELOAD_FOR_OUTPUT:
4703 case RELOAD_FOR_OUTPUT_ADDRESS:
4704 case RELOAD_FOR_OUTADDR_ADDRESS:
4705 /* We already know these can't conflict with a later output. So the
4706 only thing to check are later output addresses.
4707 Note that multiple output operands are emitted in reverse order,
4708 so the conflicting ones are those with lower indices. */
4709 for (i = 0; i < opnum; i++)
4710 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4711 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4721 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4724 This function uses the same algorithm as reload_reg_free_p above. */
4727 reloads_conflict (int r1, int r2)
4729 enum reload_type r1_type = rld[r1].when_needed;
4730 enum reload_type r2_type = rld[r2].when_needed;
4731 int r1_opnum = rld[r1].opnum;
4732 int r2_opnum = rld[r2].opnum;
4734 /* RELOAD_OTHER conflicts with everything. */
4735 if (r2_type == RELOAD_OTHER)
4738 /* Otherwise, check conflicts differently for each type. */
4742 case RELOAD_FOR_INPUT:
4743 return (r2_type == RELOAD_FOR_INSN
4744 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4745 || r2_type == RELOAD_FOR_OPADDR_ADDR
4746 || r2_type == RELOAD_FOR_INPUT
4747 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4748 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4749 && r2_opnum > r1_opnum));
4751 case RELOAD_FOR_INPUT_ADDRESS:
4752 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4753 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4755 case RELOAD_FOR_INPADDR_ADDRESS:
4756 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4757 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4759 case RELOAD_FOR_OUTPUT_ADDRESS:
4760 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4761 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4763 case RELOAD_FOR_OUTADDR_ADDRESS:
4764 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4765 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4767 case RELOAD_FOR_OPERAND_ADDRESS:
4768 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4769 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4771 case RELOAD_FOR_OPADDR_ADDR:
4772 return (r2_type == RELOAD_FOR_INPUT
4773 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4775 case RELOAD_FOR_OUTPUT:
4776 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4777 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4778 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4779 && r2_opnum >= r1_opnum));
4781 case RELOAD_FOR_INSN:
4782 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4783 || r2_type == RELOAD_FOR_INSN
4784 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4786 case RELOAD_FOR_OTHER_ADDRESS:
4787 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4797 /* Indexed by reload number, 1 if incoming value
4798 inherited from previous insns. */
4799 static char reload_inherited[MAX_RELOADS];
4801 /* For an inherited reload, this is the insn the reload was inherited from,
4802 if we know it. Otherwise, this is 0. */
4803 static rtx reload_inheritance_insn[MAX_RELOADS];
4805 /* If nonzero, this is a place to get the value of the reload,
4806 rather than using reload_in. */
4807 static rtx reload_override_in[MAX_RELOADS];
4809 /* For each reload, the hard register number of the register used,
4810 or -1 if we did not need a register for this reload. */
4811 static int reload_spill_index[MAX_RELOADS];
4813 /* Subroutine of free_for_value_p, used to check a single register.
4814 START_REGNO is the starting regno of the full reload register
4815 (possibly comprising multiple hard registers) that we are considering. */
4818 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4819 enum reload_type type, rtx value, rtx out,
4820 int reloadnum, int ignore_address_reloads)
4823 /* Set if we see an input reload that must not share its reload register
4824 with any new earlyclobber, but might otherwise share the reload
4825 register with an output or input-output reload. */
4826 int check_earlyclobber = 0;
4830 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4833 if (out == const0_rtx)
4839 /* We use some pseudo 'time' value to check if the lifetimes of the
4840 new register use would overlap with the one of a previous reload
4841 that is not read-only or uses a different value.
4842 The 'time' used doesn't have to be linear in any shape or form, just
4844 Some reload types use different 'buckets' for each operand.
4845 So there are MAX_RECOG_OPERANDS different time values for each
4847 We compute TIME1 as the time when the register for the prospective
4848 new reload ceases to be live, and TIME2 for each existing
4849 reload as the time when that the reload register of that reload
4851 Where there is little to be gained by exact lifetime calculations,
4852 we just make conservative assumptions, i.e. a longer lifetime;
4853 this is done in the 'default:' cases. */
4856 case RELOAD_FOR_OTHER_ADDRESS:
4857 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4858 time1 = copy ? 0 : 1;
4861 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4863 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4864 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4865 respectively, to the time values for these, we get distinct time
4866 values. To get distinct time values for each operand, we have to
4867 multiply opnum by at least three. We round that up to four because
4868 multiply by four is often cheaper. */
4869 case RELOAD_FOR_INPADDR_ADDRESS:
4870 time1 = opnum * 4 + 2;
4872 case RELOAD_FOR_INPUT_ADDRESS:
4873 time1 = opnum * 4 + 3;
4875 case RELOAD_FOR_INPUT:
4876 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4877 executes (inclusive). */
4878 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4880 case RELOAD_FOR_OPADDR_ADDR:
4882 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4883 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4885 case RELOAD_FOR_OPERAND_ADDRESS:
4886 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4888 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4890 case RELOAD_FOR_OUTADDR_ADDRESS:
4891 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4893 case RELOAD_FOR_OUTPUT_ADDRESS:
4894 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4897 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4900 for (i = 0; i < n_reloads; i++)
4902 rtx reg = rld[i].reg_rtx;
4903 if (reg && REG_P (reg)
4904 && ((unsigned) regno - true_regnum (reg)
4905 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
4908 rtx other_input = rld[i].in;
4910 /* If the other reload loads the same input value, that
4911 will not cause a conflict only if it's loading it into
4912 the same register. */
4913 if (true_regnum (reg) != start_regno)
4914 other_input = NULL_RTX;
4915 if (! other_input || ! rtx_equal_p (other_input, value)
4916 || rld[i].out || out)
4919 switch (rld[i].when_needed)
4921 case RELOAD_FOR_OTHER_ADDRESS:
4924 case RELOAD_FOR_INPADDR_ADDRESS:
4925 /* find_reloads makes sure that a
4926 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4927 by at most one - the first -
4928 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4929 address reload is inherited, the address address reload
4930 goes away, so we can ignore this conflict. */
4931 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4932 && ignore_address_reloads
4933 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4934 Then the address address is still needed to store
4935 back the new address. */
4936 && ! rld[reloadnum].out)
4938 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4939 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4941 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4942 && ignore_address_reloads
4943 /* Unless we are reloading an auto_inc expression. */
4944 && ! rld[reloadnum].out)
4946 time2 = rld[i].opnum * 4 + 2;
4948 case RELOAD_FOR_INPUT_ADDRESS:
4949 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4950 && ignore_address_reloads
4951 && ! rld[reloadnum].out)
4953 time2 = rld[i].opnum * 4 + 3;
4955 case RELOAD_FOR_INPUT:
4956 time2 = rld[i].opnum * 4 + 4;
4957 check_earlyclobber = 1;
4959 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4960 == MAX_RECOG_OPERAND * 4 */
4961 case RELOAD_FOR_OPADDR_ADDR:
4962 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4963 && ignore_address_reloads
4964 && ! rld[reloadnum].out)
4966 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4968 case RELOAD_FOR_OPERAND_ADDRESS:
4969 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4970 check_earlyclobber = 1;
4972 case RELOAD_FOR_INSN:
4973 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4975 case RELOAD_FOR_OUTPUT:
4976 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4977 instruction is executed. */
4978 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4980 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4981 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4983 case RELOAD_FOR_OUTADDR_ADDRESS:
4984 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4985 && ignore_address_reloads
4986 && ! rld[reloadnum].out)
4988 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4990 case RELOAD_FOR_OUTPUT_ADDRESS:
4991 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4994 /* If there is no conflict in the input part, handle this
4995 like an output reload. */
4996 if (! rld[i].in || rtx_equal_p (other_input, value))
4998 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4999 /* Earlyclobbered outputs must conflict with inputs. */
5000 if (earlyclobber_operand_p (rld[i].out))
5001 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5006 /* RELOAD_OTHER might be live beyond instruction execution,
5007 but this is not obvious when we set time2 = 1. So check
5008 here if there might be a problem with the new reload
5009 clobbering the register used by the RELOAD_OTHER. */
5017 && (! rld[i].in || rld[i].out
5018 || ! rtx_equal_p (other_input, value)))
5019 || (out && rld[reloadnum].out_reg
5020 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5026 /* Earlyclobbered outputs must conflict with inputs. */
5027 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5033 /* Return 1 if the value in reload reg REGNO, as used by a reload
5034 needed for the part of the insn specified by OPNUM and TYPE,
5035 may be used to load VALUE into it.
5037 MODE is the mode in which the register is used, this is needed to
5038 determine how many hard regs to test.
5040 Other read-only reloads with the same value do not conflict
5041 unless OUT is nonzero and these other reloads have to live while
5042 output reloads live.
5043 If OUT is CONST0_RTX, this is a special case: it means that the
5044 test should not be for using register REGNO as reload register, but
5045 for copying from register REGNO into the reload register.
5047 RELOADNUM is the number of the reload we want to load this value for;
5048 a reload does not conflict with itself.
5050 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5051 reloads that load an address for the very reload we are considering.
5053 The caller has to make sure that there is no conflict with the return
5057 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5058 enum reload_type type, rtx value, rtx out, int reloadnum,
5059 int ignore_address_reloads)
5061 int nregs = hard_regno_nregs[regno][mode];
5063 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5064 value, out, reloadnum,
5065 ignore_address_reloads))
5070 /* Return nonzero if the rtx X is invariant over the current function. */
5071 /* ??? Actually, the places where we use this expect exactly what is
5072 tested here, and not everything that is function invariant. In
5073 particular, the frame pointer and arg pointer are special cased;
5074 pic_offset_table_rtx is not, and we must not spill these things to
5078 function_invariant_p (rtx x)
5082 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5084 if (GET_CODE (x) == PLUS
5085 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5086 && CONSTANT_P (XEXP (x, 1)))
5091 /* Determine whether the reload reg X overlaps any rtx'es used for
5092 overriding inheritance. Return nonzero if so. */
5095 conflicts_with_override (rtx x)
5098 for (i = 0; i < n_reloads; i++)
5099 if (reload_override_in[i]
5100 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5105 /* Give an error message saying we failed to find a reload for INSN,
5106 and clear out reload R. */
5108 failed_reload (rtx insn, int r)
5110 if (asm_noperands (PATTERN (insn)) < 0)
5111 /* It's the compiler's fault. */
5112 fatal_insn ("could not find a spill register", insn);
5114 /* It's the user's fault; the operand's mode and constraint
5115 don't match. Disable this reload so we don't crash in final. */
5116 error_for_asm (insn,
5117 "%<asm%> operand constraint incompatible with operand size");
5121 rld[r].optional = 1;
5122 rld[r].secondary_p = 1;
5125 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5126 for reload R. If it's valid, get an rtx for it. Return nonzero if
5129 set_reload_reg (int i, int r)
5132 rtx reg = spill_reg_rtx[i];
5134 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5135 spill_reg_rtx[i] = reg
5136 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5138 regno = true_regnum (reg);
5140 /* Detect when the reload reg can't hold the reload mode.
5141 This used to be one `if', but Sequent compiler can't handle that. */
5142 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5144 enum machine_mode test_mode = VOIDmode;
5146 test_mode = GET_MODE (rld[r].in);
5147 /* If rld[r].in has VOIDmode, it means we will load it
5148 in whatever mode the reload reg has: to wit, rld[r].mode.
5149 We have already tested that for validity. */
5150 /* Aside from that, we need to test that the expressions
5151 to reload from or into have modes which are valid for this
5152 reload register. Otherwise the reload insns would be invalid. */
5153 if (! (rld[r].in != 0 && test_mode != VOIDmode
5154 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5155 if (! (rld[r].out != 0
5156 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5158 /* The reg is OK. */
5161 /* Mark as in use for this insn the reload regs we use
5163 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5164 rld[r].when_needed, rld[r].mode);
5166 rld[r].reg_rtx = reg;
5167 reload_spill_index[r] = spill_regs[i];
5174 /* Find a spill register to use as a reload register for reload R.
5175 LAST_RELOAD is nonzero if this is the last reload for the insn being
5178 Set rld[R].reg_rtx to the register allocated.
5180 We return 1 if successful, or 0 if we couldn't find a spill reg and
5181 we didn't change anything. */
5184 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5189 /* If we put this reload ahead, thinking it is a group,
5190 then insist on finding a group. Otherwise we can grab a
5191 reg that some other reload needs.
5192 (That can happen when we have a 68000 DATA_OR_FP_REG
5193 which is a group of data regs or one fp reg.)
5194 We need not be so restrictive if there are no more reloads
5197 ??? Really it would be nicer to have smarter handling
5198 for that kind of reg class, where a problem like this is normal.
5199 Perhaps those classes should be avoided for reloading
5200 by use of more alternatives. */
5202 int force_group = rld[r].nregs > 1 && ! last_reload;
5204 /* If we want a single register and haven't yet found one,
5205 take any reg in the right class and not in use.
5206 If we want a consecutive group, here is where we look for it.
5208 We use two passes so we can first look for reload regs to
5209 reuse, which are already in use for other reloads in this insn,
5210 and only then use additional registers.
5211 I think that maximizing reuse is needed to make sure we don't
5212 run out of reload regs. Suppose we have three reloads, and
5213 reloads A and B can share regs. These need two regs.
5214 Suppose A and B are given different regs.
5215 That leaves none for C. */
5216 for (pass = 0; pass < 2; pass++)
5218 /* I is the index in spill_regs.
5219 We advance it round-robin between insns to use all spill regs
5220 equally, so that inherited reloads have a chance
5221 of leapfrogging each other. */
5225 for (count = 0; count < n_spills; count++)
5227 int class = (int) rld[r].class;
5233 regnum = spill_regs[i];
5235 if ((reload_reg_free_p (regnum, rld[r].opnum,
5238 /* We check reload_reg_used to make sure we
5239 don't clobber the return register. */
5240 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5241 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5242 rld[r].when_needed, rld[r].in,
5244 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5245 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5246 /* Look first for regs to share, then for unshared. But
5247 don't share regs used for inherited reloads; they are
5248 the ones we want to preserve. */
5250 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5252 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5255 int nr = hard_regno_nregs[regnum][rld[r].mode];
5256 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5257 (on 68000) got us two FP regs. If NR is 1,
5258 we would reject both of them. */
5261 /* If we need only one reg, we have already won. */
5264 /* But reject a single reg if we demand a group. */
5269 /* Otherwise check that as many consecutive regs as we need
5270 are available here. */
5273 int regno = regnum + nr - 1;
5274 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5275 && spill_reg_order[regno] >= 0
5276 && reload_reg_free_p (regno, rld[r].opnum,
5277 rld[r].when_needed)))
5286 /* If we found something on pass 1, omit pass 2. */
5287 if (count < n_spills)
5291 /* We should have found a spill register by now. */
5292 if (count >= n_spills)
5295 /* I is the index in SPILL_REG_RTX of the reload register we are to
5296 allocate. Get an rtx for it and find its register number. */
5298 return set_reload_reg (i, r);
5301 /* Initialize all the tables needed to allocate reload registers.
5302 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5303 is the array we use to restore the reg_rtx field for every reload. */
5306 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5310 for (i = 0; i < n_reloads; i++)
5311 rld[i].reg_rtx = save_reload_reg_rtx[i];
5313 memset (reload_inherited, 0, MAX_RELOADS);
5314 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5315 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5317 CLEAR_HARD_REG_SET (reload_reg_used);
5318 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5319 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5320 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5321 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5322 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5324 CLEAR_HARD_REG_SET (reg_used_in_insn);
5327 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5328 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5329 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5330 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5331 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5332 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5335 for (i = 0; i < reload_n_operands; i++)
5337 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5338 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5339 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5340 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5341 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5342 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5345 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5347 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5349 for (i = 0; i < n_reloads; i++)
5350 /* If we have already decided to use a certain register,
5351 don't use it in another way. */
5353 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5354 rld[i].when_needed, rld[i].mode);
5357 /* Assign hard reg targets for the pseudo-registers we must reload
5358 into hard regs for this insn.
5359 Also output the instructions to copy them in and out of the hard regs.
5361 For machines with register classes, we are responsible for
5362 finding a reload reg in the proper class. */
5365 choose_reload_regs (struct insn_chain *chain)
5367 rtx insn = chain->insn;
5369 unsigned int max_group_size = 1;
5370 enum reg_class group_class = NO_REGS;
5371 int pass, win, inheritance;
5373 rtx save_reload_reg_rtx[MAX_RELOADS];
5375 /* In order to be certain of getting the registers we need,
5376 we must sort the reloads into order of increasing register class.
5377 Then our grabbing of reload registers will parallel the process
5378 that provided the reload registers.
5380 Also note whether any of the reloads wants a consecutive group of regs.
5381 If so, record the maximum size of the group desired and what
5382 register class contains all the groups needed by this insn. */
5384 for (j = 0; j < n_reloads; j++)
5386 reload_order[j] = j;
5387 reload_spill_index[j] = -1;
5389 if (rld[j].nregs > 1)
5391 max_group_size = MAX (rld[j].nregs, max_group_size);
5393 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5396 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5400 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5402 /* If -O, try first with inheritance, then turning it off.
5403 If not -O, don't do inheritance.
5404 Using inheritance when not optimizing leads to paradoxes
5405 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5406 because one side of the comparison might be inherited. */
5408 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5410 choose_reload_regs_init (chain, save_reload_reg_rtx);
5412 /* Process the reloads in order of preference just found.
5413 Beyond this point, subregs can be found in reload_reg_rtx.
5415 This used to look for an existing reloaded home for all of the
5416 reloads, and only then perform any new reloads. But that could lose
5417 if the reloads were done out of reg-class order because a later
5418 reload with a looser constraint might have an old home in a register
5419 needed by an earlier reload with a tighter constraint.
5421 To solve this, we make two passes over the reloads, in the order
5422 described above. In the first pass we try to inherit a reload
5423 from a previous insn. If there is a later reload that needs a
5424 class that is a proper subset of the class being processed, we must
5425 also allocate a spill register during the first pass.
5427 Then make a second pass over the reloads to allocate any reloads
5428 that haven't been given registers yet. */
5430 for (j = 0; j < n_reloads; j++)
5432 int r = reload_order[j];
5433 rtx search_equiv = NULL_RTX;
5435 /* Ignore reloads that got marked inoperative. */
5436 if (rld[r].out == 0 && rld[r].in == 0
5437 && ! rld[r].secondary_p)
5440 /* If find_reloads chose to use reload_in or reload_out as a reload
5441 register, we don't need to chose one. Otherwise, try even if it
5442 found one since we might save an insn if we find the value lying
5444 Try also when reload_in is a pseudo without a hard reg. */
5445 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5446 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5447 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5448 && !MEM_P (rld[r].in)
5449 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5452 #if 0 /* No longer needed for correct operation.
5453 It might give better code, or might not; worth an experiment? */
5454 /* If this is an optional reload, we can't inherit from earlier insns
5455 until we are sure that any non-optional reloads have been allocated.
5456 The following code takes advantage of the fact that optional reloads
5457 are at the end of reload_order. */
5458 if (rld[r].optional != 0)
5459 for (i = 0; i < j; i++)
5460 if ((rld[reload_order[i]].out != 0
5461 || rld[reload_order[i]].in != 0
5462 || rld[reload_order[i]].secondary_p)
5463 && ! rld[reload_order[i]].optional
5464 && rld[reload_order[i]].reg_rtx == 0)
5465 allocate_reload_reg (chain, reload_order[i], 0);
5468 /* First see if this pseudo is already available as reloaded
5469 for a previous insn. We cannot try to inherit for reloads
5470 that are smaller than the maximum number of registers needed
5471 for groups unless the register we would allocate cannot be used
5474 We could check here to see if this is a secondary reload for
5475 an object that is already in a register of the desired class.
5476 This would avoid the need for the secondary reload register.
5477 But this is complex because we can't easily determine what
5478 objects might want to be loaded via this reload. So let a
5479 register be allocated here. In `emit_reload_insns' we suppress
5480 one of the loads in the case described above. */
5486 enum machine_mode mode = VOIDmode;
5490 else if (REG_P (rld[r].in))
5492 regno = REGNO (rld[r].in);
5493 mode = GET_MODE (rld[r].in);
5495 else if (REG_P (rld[r].in_reg))
5497 regno = REGNO (rld[r].in_reg);
5498 mode = GET_MODE (rld[r].in_reg);
5500 else if (GET_CODE (rld[r].in_reg) == SUBREG
5501 && REG_P (SUBREG_REG (rld[r].in_reg)))
5503 byte = SUBREG_BYTE (rld[r].in_reg);
5504 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5505 if (regno < FIRST_PSEUDO_REGISTER)
5506 regno = subreg_regno (rld[r].in_reg);
5507 mode = GET_MODE (rld[r].in_reg);
5510 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5511 || GET_CODE (rld[r].in_reg) == PRE_DEC
5512 || GET_CODE (rld[r].in_reg) == POST_INC
5513 || GET_CODE (rld[r].in_reg) == POST_DEC)
5514 && REG_P (XEXP (rld[r].in_reg, 0)))
5516 regno = REGNO (XEXP (rld[r].in_reg, 0));
5517 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5518 rld[r].out = rld[r].in;
5522 /* This won't work, since REGNO can be a pseudo reg number.
5523 Also, it takes much more hair to keep track of all the things
5524 that can invalidate an inherited reload of part of a pseudoreg. */
5525 else if (GET_CODE (rld[r].in) == SUBREG
5526 && REG_P (SUBREG_REG (rld[r].in)))
5527 regno = subreg_regno (rld[r].in);
5530 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5532 enum reg_class class = rld[r].class, last_class;
5533 rtx last_reg = reg_last_reload_reg[regno];
5534 enum machine_mode need_mode;
5536 i = REGNO (last_reg);
5537 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5538 last_class = REGNO_REG_CLASS (i);
5544 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
5545 + byte * BITS_PER_UNIT,
5546 GET_MODE_CLASS (mode));
5548 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5549 >= GET_MODE_SIZE (need_mode))
5550 #ifdef CANNOT_CHANGE_MODE_CLASS
5551 /* Verify that the register in "i" can be obtained
5553 && !REG_CANNOT_CHANGE_MODE_P (REGNO (last_reg),
5554 GET_MODE (last_reg),
5557 && reg_reloaded_contents[i] == regno
5558 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5559 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5560 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5561 /* Even if we can't use this register as a reload
5562 register, we might use it for reload_override_in,
5563 if copying it to the desired class is cheap
5565 || ((REGISTER_MOVE_COST (mode, last_class, class)
5566 < MEMORY_MOVE_COST (mode, class, 1))
5567 && (secondary_reload_class (1, class, mode,
5570 #ifdef SECONDARY_MEMORY_NEEDED
5571 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5576 && (rld[r].nregs == max_group_size
5577 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5579 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5580 rld[r].when_needed, rld[r].in,
5583 /* If a group is needed, verify that all the subsequent
5584 registers still have their values intact. */
5585 int nr = hard_regno_nregs[i][rld[r].mode];
5588 for (k = 1; k < nr; k++)
5589 if (reg_reloaded_contents[i + k] != regno
5590 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5598 last_reg = (GET_MODE (last_reg) == mode
5599 ? last_reg : gen_rtx_REG (mode, i));
5602 for (k = 0; k < nr; k++)
5603 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5606 /* We found a register that contains the
5607 value we need. If this register is the
5608 same as an `earlyclobber' operand of the
5609 current insn, just mark it as a place to
5610 reload from since we can't use it as the
5611 reload register itself. */
5613 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5614 if (reg_overlap_mentioned_for_reload_p
5615 (reg_last_reload_reg[regno],
5616 reload_earlyclobbers[i1]))
5619 if (i1 != n_earlyclobbers
5620 || ! (free_for_value_p (i, rld[r].mode,
5622 rld[r].when_needed, rld[r].in,
5624 /* Don't use it if we'd clobber a pseudo reg. */
5625 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5627 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5628 /* Don't clobber the frame pointer. */
5629 || (i == HARD_FRAME_POINTER_REGNUM
5630 && frame_pointer_needed
5632 /* Don't really use the inherited spill reg
5633 if we need it wider than we've got it. */
5634 || (GET_MODE_SIZE (rld[r].mode)
5635 > GET_MODE_SIZE (mode))
5638 /* If find_reloads chose reload_out as reload
5639 register, stay with it - that leaves the
5640 inherited register for subsequent reloads. */
5641 || (rld[r].out && rld[r].reg_rtx
5642 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5644 if (! rld[r].optional)
5646 reload_override_in[r] = last_reg;
5647 reload_inheritance_insn[r]
5648 = reg_reloaded_insn[i];
5654 /* We can use this as a reload reg. */
5655 /* Mark the register as in use for this part of
5657 mark_reload_reg_in_use (i,
5661 rld[r].reg_rtx = last_reg;
5662 reload_inherited[r] = 1;
5663 reload_inheritance_insn[r]
5664 = reg_reloaded_insn[i];
5665 reload_spill_index[r] = i;
5666 for (k = 0; k < nr; k++)
5667 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5675 /* Here's another way to see if the value is already lying around. */
5678 && ! reload_inherited[r]
5680 && (CONSTANT_P (rld[r].in)
5681 || GET_CODE (rld[r].in) == PLUS
5682 || REG_P (rld[r].in)
5683 || MEM_P (rld[r].in))
5684 && (rld[r].nregs == max_group_size
5685 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5686 search_equiv = rld[r].in;
5687 /* If this is an output reload from a simple move insn, look
5688 if an equivalence for the input is available. */
5689 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5691 rtx set = single_set (insn);
5694 && rtx_equal_p (rld[r].out, SET_DEST (set))
5695 && CONSTANT_P (SET_SRC (set)))
5696 search_equiv = SET_SRC (set);
5702 = find_equiv_reg (search_equiv, insn, rld[r].class,
5703 -1, NULL, 0, rld[r].mode);
5709 regno = REGNO (equiv);
5712 /* This must be a SUBREG of a hard register.
5713 Make a new REG since this might be used in an
5714 address and not all machines support SUBREGs
5716 gcc_assert (GET_CODE (equiv) == SUBREG);
5717 regno = subreg_regno (equiv);
5718 equiv = gen_rtx_REG (rld[r].mode, regno);
5719 /* If we choose EQUIV as the reload register, but the
5720 loop below decides to cancel the inheritance, we'll
5721 end up reloading EQUIV in rld[r].mode, not the mode
5722 it had originally. That isn't safe when EQUIV isn't
5723 available as a spill register since its value might
5724 still be live at this point. */
5725 for (i = regno; i < regno + (int) rld[r].nregs; i++)
5726 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
5731 /* If we found a spill reg, reject it unless it is free
5732 and of the desired class. */
5736 int bad_for_class = 0;
5737 int max_regno = regno + rld[r].nregs;
5739 for (i = regno; i < max_regno; i++)
5741 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5743 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5748 && ! free_for_value_p (regno, rld[r].mode,
5749 rld[r].opnum, rld[r].when_needed,
5750 rld[r].in, rld[r].out, r, 1))
5755 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5758 /* We found a register that contains the value we need.
5759 If this register is the same as an `earlyclobber' operand
5760 of the current insn, just mark it as a place to reload from
5761 since we can't use it as the reload register itself. */
5764 for (i = 0; i < n_earlyclobbers; i++)
5765 if (reg_overlap_mentioned_for_reload_p (equiv,
5766 reload_earlyclobbers[i]))
5768 if (! rld[r].optional)
5769 reload_override_in[r] = equiv;
5774 /* If the equiv register we have found is explicitly clobbered
5775 in the current insn, it depends on the reload type if we
5776 can use it, use it for reload_override_in, or not at all.
5777 In particular, we then can't use EQUIV for a
5778 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5782 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5783 switch (rld[r].when_needed)
5785 case RELOAD_FOR_OTHER_ADDRESS:
5786 case RELOAD_FOR_INPADDR_ADDRESS:
5787 case RELOAD_FOR_INPUT_ADDRESS:
5788 case RELOAD_FOR_OPADDR_ADDR:
5791 case RELOAD_FOR_INPUT:
5792 case RELOAD_FOR_OPERAND_ADDRESS:
5793 if (! rld[r].optional)
5794 reload_override_in[r] = equiv;
5800 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5801 switch (rld[r].when_needed)
5803 case RELOAD_FOR_OTHER_ADDRESS:
5804 case RELOAD_FOR_INPADDR_ADDRESS:
5805 case RELOAD_FOR_INPUT_ADDRESS:
5806 case RELOAD_FOR_OPADDR_ADDR:
5807 case RELOAD_FOR_OPERAND_ADDRESS:
5808 case RELOAD_FOR_INPUT:
5811 if (! rld[r].optional)
5812 reload_override_in[r] = equiv;
5820 /* If we found an equivalent reg, say no code need be generated
5821 to load it, and use it as our reload reg. */
5823 && (regno != HARD_FRAME_POINTER_REGNUM
5824 || !frame_pointer_needed))
5826 int nr = hard_regno_nregs[regno][rld[r].mode];
5828 rld[r].reg_rtx = equiv;
5829 reload_inherited[r] = 1;
5831 /* If reg_reloaded_valid is not set for this register,
5832 there might be a stale spill_reg_store lying around.
5833 We must clear it, since otherwise emit_reload_insns
5834 might delete the store. */
5835 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5836 spill_reg_store[regno] = NULL_RTX;
5837 /* If any of the hard registers in EQUIV are spill
5838 registers, mark them as in use for this insn. */
5839 for (k = 0; k < nr; k++)
5841 i = spill_reg_order[regno + k];
5844 mark_reload_reg_in_use (regno, rld[r].opnum,
5847 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5854 /* If we found a register to use already, or if this is an optional
5855 reload, we are done. */
5856 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5860 /* No longer needed for correct operation. Might or might
5861 not give better code on the average. Want to experiment? */
5863 /* See if there is a later reload that has a class different from our
5864 class that intersects our class or that requires less register
5865 than our reload. If so, we must allocate a register to this
5866 reload now, since that reload might inherit a previous reload
5867 and take the only available register in our class. Don't do this
5868 for optional reloads since they will force all previous reloads
5869 to be allocated. Also don't do this for reloads that have been
5872 for (i = j + 1; i < n_reloads; i++)
5874 int s = reload_order[i];
5876 if ((rld[s].in == 0 && rld[s].out == 0
5877 && ! rld[s].secondary_p)
5881 if ((rld[s].class != rld[r].class
5882 && reg_classes_intersect_p (rld[r].class,
5884 || rld[s].nregs < rld[r].nregs)
5891 allocate_reload_reg (chain, r, j == n_reloads - 1);
5895 /* Now allocate reload registers for anything non-optional that
5896 didn't get one yet. */
5897 for (j = 0; j < n_reloads; j++)
5899 int r = reload_order[j];
5901 /* Ignore reloads that got marked inoperative. */
5902 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5905 /* Skip reloads that already have a register allocated or are
5907 if (rld[r].reg_rtx != 0 || rld[r].optional)
5910 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5914 /* If that loop got all the way, we have won. */
5921 /* Loop around and try without any inheritance. */
5926 /* First undo everything done by the failed attempt
5927 to allocate with inheritance. */
5928 choose_reload_regs_init (chain, save_reload_reg_rtx);
5930 /* Some sanity tests to verify that the reloads found in the first
5931 pass are identical to the ones we have now. */
5932 gcc_assert (chain->n_reloads == n_reloads);
5934 for (i = 0; i < n_reloads; i++)
5936 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5938 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
5939 for (j = 0; j < n_spills; j++)
5940 if (spill_regs[j] == chain->rld[i].regno)
5941 if (! set_reload_reg (j, i))
5942 failed_reload (chain->insn, i);
5946 /* If we thought we could inherit a reload, because it seemed that
5947 nothing else wanted the same reload register earlier in the insn,
5948 verify that assumption, now that all reloads have been assigned.
5949 Likewise for reloads where reload_override_in has been set. */
5951 /* If doing expensive optimizations, do one preliminary pass that doesn't
5952 cancel any inheritance, but removes reloads that have been needed only
5953 for reloads that we know can be inherited. */
5954 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5956 for (j = 0; j < n_reloads; j++)
5958 int r = reload_order[j];
5960 if (reload_inherited[r] && rld[r].reg_rtx)
5961 check_reg = rld[r].reg_rtx;
5962 else if (reload_override_in[r]
5963 && (REG_P (reload_override_in[r])
5964 || GET_CODE (reload_override_in[r]) == SUBREG))
5965 check_reg = reload_override_in[r];
5968 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5969 rld[r].opnum, rld[r].when_needed, rld[r].in,
5970 (reload_inherited[r]
5971 ? rld[r].out : const0_rtx),
5976 reload_inherited[r] = 0;
5977 reload_override_in[r] = 0;
5979 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5980 reload_override_in, then we do not need its related
5981 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5982 likewise for other reload types.
5983 We handle this by removing a reload when its only replacement
5984 is mentioned in reload_in of the reload we are going to inherit.
5985 A special case are auto_inc expressions; even if the input is
5986 inherited, we still need the address for the output. We can
5987 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5988 If we succeeded removing some reload and we are doing a preliminary
5989 pass just to remove such reloads, make another pass, since the
5990 removal of one reload might allow us to inherit another one. */
5992 && rld[r].out != rld[r].in
5993 && remove_address_replacements (rld[r].in) && pass)
5998 /* Now that reload_override_in is known valid,
5999 actually override reload_in. */
6000 for (j = 0; j < n_reloads; j++)
6001 if (reload_override_in[j])
6002 rld[j].in = reload_override_in[j];
6004 /* If this reload won't be done because it has been canceled or is
6005 optional and not inherited, clear reload_reg_rtx so other
6006 routines (such as subst_reloads) don't get confused. */
6007 for (j = 0; j < n_reloads; j++)
6008 if (rld[j].reg_rtx != 0
6009 && ((rld[j].optional && ! reload_inherited[j])
6010 || (rld[j].in == 0 && rld[j].out == 0
6011 && ! rld[j].secondary_p)))
6013 int regno = true_regnum (rld[j].reg_rtx);
6015 if (spill_reg_order[regno] >= 0)
6016 clear_reload_reg_in_use (regno, rld[j].opnum,
6017 rld[j].when_needed, rld[j].mode);
6019 reload_spill_index[j] = -1;
6022 /* Record which pseudos and which spill regs have output reloads. */
6023 for (j = 0; j < n_reloads; j++)
6025 int r = reload_order[j];
6027 i = reload_spill_index[r];
6029 /* I is nonneg if this reload uses a register.
6030 If rld[r].reg_rtx is 0, this is an optional reload
6031 that we opted to ignore. */
6032 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6033 && rld[r].reg_rtx != 0)
6035 int nregno = REGNO (rld[r].out_reg);
6038 if (nregno < FIRST_PSEUDO_REGISTER)
6039 nr = hard_regno_nregs[nregno][rld[r].mode];
6042 reg_has_output_reload[nregno + nr] = 1;
6046 nr = hard_regno_nregs[i][rld[r].mode];
6048 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6051 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6052 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6053 || rld[r].when_needed == RELOAD_FOR_INSN);
6058 /* Deallocate the reload register for reload R. This is called from
6059 remove_address_replacements. */
6062 deallocate_reload_reg (int r)
6066 if (! rld[r].reg_rtx)
6068 regno = true_regnum (rld[r].reg_rtx);
6070 if (spill_reg_order[regno] >= 0)
6071 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6073 reload_spill_index[r] = -1;
6076 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6077 reloads of the same item for fear that we might not have enough reload
6078 registers. However, normally they will get the same reload register
6079 and hence actually need not be loaded twice.
6081 Here we check for the most common case of this phenomenon: when we have
6082 a number of reloads for the same object, each of which were allocated
6083 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6084 reload, and is not modified in the insn itself. If we find such,
6085 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6086 This will not increase the number of spill registers needed and will
6087 prevent redundant code. */
6090 merge_assigned_reloads (rtx insn)
6094 /* Scan all the reloads looking for ones that only load values and
6095 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6096 assigned and not modified by INSN. */
6098 for (i = 0; i < n_reloads; i++)
6100 int conflicting_input = 0;
6101 int max_input_address_opnum = -1;
6102 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6104 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6105 || rld[i].out != 0 || rld[i].reg_rtx == 0
6106 || reg_set_p (rld[i].reg_rtx, insn))
6109 /* Look at all other reloads. Ensure that the only use of this
6110 reload_reg_rtx is in a reload that just loads the same value
6111 as we do. Note that any secondary reloads must be of the identical
6112 class since the values, modes, and result registers are the
6113 same, so we need not do anything with any secondary reloads. */
6115 for (j = 0; j < n_reloads; j++)
6117 if (i == j || rld[j].reg_rtx == 0
6118 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6122 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6123 && rld[j].opnum > max_input_address_opnum)
6124 max_input_address_opnum = rld[j].opnum;
6126 /* If the reload regs aren't exactly the same (e.g, different modes)
6127 or if the values are different, we can't merge this reload.
6128 But if it is an input reload, we might still merge
6129 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6131 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6132 || rld[j].out != 0 || rld[j].in == 0
6133 || ! rtx_equal_p (rld[i].in, rld[j].in))
6135 if (rld[j].when_needed != RELOAD_FOR_INPUT
6136 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6137 || rld[i].opnum > rld[j].opnum)
6138 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6140 conflicting_input = 1;
6141 if (min_conflicting_input_opnum > rld[j].opnum)
6142 min_conflicting_input_opnum = rld[j].opnum;
6146 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6147 we, in fact, found any matching reloads. */
6150 && max_input_address_opnum <= min_conflicting_input_opnum)
6152 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6154 for (j = 0; j < n_reloads; j++)
6155 if (i != j && rld[j].reg_rtx != 0
6156 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6157 && (! conflicting_input
6158 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6159 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6161 rld[i].when_needed = RELOAD_OTHER;
6163 reload_spill_index[j] = -1;
6164 transfer_replacements (i, j);
6167 /* If this is now RELOAD_OTHER, look for any reloads that load
6168 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6169 if they were for inputs, RELOAD_OTHER for outputs. Note that
6170 this test is equivalent to looking for reloads for this operand
6172 /* We must take special care with RELOAD_FOR_OUTPUT_ADDRESS; it may
6173 share registers with a RELOAD_FOR_INPUT, so we can not change it
6174 to RELOAD_FOR_OTHER_ADDRESS. We should never need to, since we
6175 do not modify RELOAD_FOR_OUTPUT. */
6177 if (rld[i].when_needed == RELOAD_OTHER)
6178 for (j = 0; j < n_reloads; j++)
6180 && rld[j].when_needed != RELOAD_OTHER
6181 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6182 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6183 && (! conflicting_input
6184 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6185 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6186 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6192 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6193 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6194 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6196 /* Check to see if we accidentally converted two
6197 reloads that use the same reload register with
6198 different inputs to the same type. If so, the
6199 resulting code won't work. */
6201 for (k = 0; k < j; k++)
6202 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6203 || rld[k].when_needed != rld[j].when_needed
6204 || !rtx_equal_p (rld[k].reg_rtx,
6206 || rtx_equal_p (rld[k].in,
6213 /* These arrays are filled by emit_reload_insns and its subroutines. */
6214 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6215 static rtx other_input_address_reload_insns = 0;
6216 static rtx other_input_reload_insns = 0;
6217 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6218 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6219 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6220 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6221 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6222 static rtx operand_reload_insns = 0;
6223 static rtx other_operand_reload_insns = 0;
6224 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6226 /* Values to be put in spill_reg_store are put here first. */
6227 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6228 static HARD_REG_SET reg_reloaded_died;
6230 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6231 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6232 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6233 adjusted register, and return true. Otherwise, return false. */
6235 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6236 enum reg_class new_class,
6237 enum machine_mode new_mode)
6242 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6244 unsigned regno = REGNO (reg);
6246 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6248 if (GET_MODE (reg) != new_mode)
6250 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6252 if (hard_regno_nregs[regno][new_mode]
6253 > hard_regno_nregs[regno][GET_MODE (reg)])
6255 reg = reload_adjust_reg_for_mode (reg, new_mode);
6263 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6264 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6265 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6266 adjusted register, and return true. Otherwise, return false. */
6268 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6269 enum insn_code icode)
6272 enum reg_class new_class = scratch_reload_class (icode);
6273 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6275 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6276 new_class, new_mode);
6279 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6280 has the number J. OLD contains the value to be used as input. */
6283 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6286 rtx insn = chain->insn;
6287 rtx reloadreg = rl->reg_rtx;
6288 rtx oldequiv_reg = 0;
6291 enum machine_mode mode;
6294 /* Determine the mode to reload in.
6295 This is very tricky because we have three to choose from.
6296 There is the mode the insn operand wants (rl->inmode).
6297 There is the mode of the reload register RELOADREG.
6298 There is the intrinsic mode of the operand, which we could find
6299 by stripping some SUBREGs.
6300 It turns out that RELOADREG's mode is irrelevant:
6301 we can change that arbitrarily.
6303 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6304 then the reload reg may not support QImode moves, so use SImode.
6305 If foo is in memory due to spilling a pseudo reg, this is safe,
6306 because the QImode value is in the least significant part of a
6307 slot big enough for a SImode. If foo is some other sort of
6308 memory reference, then it is impossible to reload this case,
6309 so previous passes had better make sure this never happens.
6311 Then consider a one-word union which has SImode and one of its
6312 members is a float, being fetched as (SUBREG:SF union:SI).
6313 We must fetch that as SFmode because we could be loading into
6314 a float-only register. In this case OLD's mode is correct.
6316 Consider an immediate integer: it has VOIDmode. Here we need
6317 to get a mode from something else.
6319 In some cases, there is a fourth mode, the operand's
6320 containing mode. If the insn specifies a containing mode for
6321 this operand, it overrides all others.
6323 I am not sure whether the algorithm here is always right,
6324 but it does the right things in those cases. */
6326 mode = GET_MODE (old);
6327 if (mode == VOIDmode)
6330 /* If we need a secondary register for this operation, see if
6331 the value is already in a register in that class. Don't
6332 do this if the secondary register will be used as a scratch
6335 if (rl->secondary_in_reload >= 0
6336 && rl->secondary_in_icode == CODE_FOR_nothing
6339 = find_equiv_reg (old, insn,
6340 rld[rl->secondary_in_reload].class,
6343 /* If reloading from memory, see if there is a register
6344 that already holds the same value. If so, reload from there.
6345 We can pass 0 as the reload_reg_p argument because
6346 any other reload has either already been emitted,
6347 in which case find_equiv_reg will see the reload-insn,
6348 or has yet to be emitted, in which case it doesn't matter
6349 because we will use this equiv reg right away. */
6351 if (oldequiv == 0 && optimize
6354 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6355 && reg_renumber[REGNO (old)] < 0)))
6356 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6360 unsigned int regno = true_regnum (oldequiv);
6362 /* Don't use OLDEQUIV if any other reload changes it at an
6363 earlier stage of this insn or at this stage. */
6364 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6365 rl->in, const0_rtx, j, 0))
6368 /* If it is no cheaper to copy from OLDEQUIV into the
6369 reload register than it would be to move from memory,
6370 don't use it. Likewise, if we need a secondary register
6374 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6375 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6377 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6378 || (secondary_reload_class (1, rl->class, mode, oldequiv)
6380 #ifdef SECONDARY_MEMORY_NEEDED
6381 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6389 /* delete_output_reload is only invoked properly if old contains
6390 the original pseudo register. Since this is replaced with a
6391 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6392 find the pseudo in RELOAD_IN_REG. */
6394 && reload_override_in[j]
6395 && REG_P (rl->in_reg))
6402 else if (REG_P (oldequiv))
6403 oldequiv_reg = oldequiv;
6404 else if (GET_CODE (oldequiv) == SUBREG)
6405 oldequiv_reg = SUBREG_REG (oldequiv);
6407 /* If we are reloading from a register that was recently stored in
6408 with an output-reload, see if we can prove there was
6409 actually no need to store the old value in it. */
6411 if (optimize && REG_P (oldequiv)
6412 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6413 && spill_reg_store[REGNO (oldequiv)]
6415 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6416 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6418 delete_output_reload (insn, j, REGNO (oldequiv));
6420 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6421 then load RELOADREG from OLDEQUIV. Note that we cannot use
6422 gen_lowpart_common since it can do the wrong thing when
6423 RELOADREG has a multi-word mode. Note that RELOADREG
6424 must always be a REG here. */
6426 if (GET_MODE (reloadreg) != mode)
6427 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6428 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6429 oldequiv = SUBREG_REG (oldequiv);
6430 if (GET_MODE (oldequiv) != VOIDmode
6431 && mode != GET_MODE (oldequiv))
6432 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6434 /* Switch to the right place to emit the reload insns. */
6435 switch (rl->when_needed)
6438 where = &other_input_reload_insns;
6440 case RELOAD_FOR_INPUT:
6441 where = &input_reload_insns[rl->opnum];
6443 case RELOAD_FOR_INPUT_ADDRESS:
6444 where = &input_address_reload_insns[rl->opnum];
6446 case RELOAD_FOR_INPADDR_ADDRESS:
6447 where = &inpaddr_address_reload_insns[rl->opnum];
6449 case RELOAD_FOR_OUTPUT_ADDRESS:
6450 where = &output_address_reload_insns[rl->opnum];
6452 case RELOAD_FOR_OUTADDR_ADDRESS:
6453 where = &outaddr_address_reload_insns[rl->opnum];
6455 case RELOAD_FOR_OPERAND_ADDRESS:
6456 where = &operand_reload_insns;
6458 case RELOAD_FOR_OPADDR_ADDR:
6459 where = &other_operand_reload_insns;
6461 case RELOAD_FOR_OTHER_ADDRESS:
6462 where = &other_input_address_reload_insns;
6468 push_to_sequence (*where);
6470 /* Auto-increment addresses must be reloaded in a special way. */
6471 if (rl->out && ! rl->out_reg)
6473 /* We are not going to bother supporting the case where a
6474 incremented register can't be copied directly from
6475 OLDEQUIV since this seems highly unlikely. */
6476 gcc_assert (rl->secondary_in_reload < 0);
6478 if (reload_inherited[j])
6479 oldequiv = reloadreg;
6481 old = XEXP (rl->in_reg, 0);
6483 if (optimize && REG_P (oldequiv)
6484 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6485 && spill_reg_store[REGNO (oldequiv)]
6487 && (dead_or_set_p (insn,
6488 spill_reg_stored_to[REGNO (oldequiv)])
6489 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6491 delete_output_reload (insn, j, REGNO (oldequiv));
6493 /* Prevent normal processing of this reload. */
6495 /* Output a special code sequence for this case. */
6496 new_spill_reg_store[REGNO (reloadreg)]
6497 = inc_for_reload (reloadreg, oldequiv, rl->out,
6501 /* If we are reloading a pseudo-register that was set by the previous
6502 insn, see if we can get rid of that pseudo-register entirely
6503 by redirecting the previous insn into our reload register. */
6505 else if (optimize && REG_P (old)
6506 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6507 && dead_or_set_p (insn, old)
6508 /* This is unsafe if some other reload
6509 uses the same reg first. */
6510 && ! conflicts_with_override (reloadreg)
6511 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6512 rl->when_needed, old, rl->out, j, 0))
6514 rtx temp = PREV_INSN (insn);
6515 while (temp && NOTE_P (temp))
6516 temp = PREV_INSN (temp);
6518 && NONJUMP_INSN_P (temp)
6519 && GET_CODE (PATTERN (temp)) == SET
6520 && SET_DEST (PATTERN (temp)) == old
6521 /* Make sure we can access insn_operand_constraint. */
6522 && asm_noperands (PATTERN (temp)) < 0
6523 /* This is unsafe if operand occurs more than once in current
6524 insn. Perhaps some occurrences aren't reloaded. */
6525 && count_occurrences (PATTERN (insn), old, 0) == 1)
6527 rtx old = SET_DEST (PATTERN (temp));
6528 /* Store into the reload register instead of the pseudo. */
6529 SET_DEST (PATTERN (temp)) = reloadreg;
6531 /* Verify that resulting insn is valid. */
6532 extract_insn (temp);
6533 if (constrain_operands (1))
6535 /* If the previous insn is an output reload, the source is
6536 a reload register, and its spill_reg_store entry will
6537 contain the previous destination. This is now
6539 if (REG_P (SET_SRC (PATTERN (temp)))
6540 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6542 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6543 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6546 /* If these are the only uses of the pseudo reg,
6547 pretend for GDB it lives in the reload reg we used. */
6548 if (REG_N_DEATHS (REGNO (old)) == 1
6549 && REG_N_SETS (REGNO (old)) == 1)
6551 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6552 alter_reg (REGNO (old), -1);
6558 SET_DEST (PATTERN (temp)) = old;
6563 /* We can't do that, so output an insn to load RELOADREG. */
6565 /* If we have a secondary reload, pick up the secondary register
6566 and icode, if any. If OLDEQUIV and OLD are different or
6567 if this is an in-out reload, recompute whether or not we
6568 still need a secondary register and what the icode should
6569 be. If we still need a secondary register and the class or
6570 icode is different, go back to reloading from OLD if using
6571 OLDEQUIV means that we got the wrong type of register. We
6572 cannot have different class or icode due to an in-out reload
6573 because we don't make such reloads when both the input and
6574 output need secondary reload registers. */
6576 if (! special && rl->secondary_in_reload >= 0)
6578 rtx second_reload_reg = 0;
6579 rtx third_reload_reg = 0;
6580 int secondary_reload = rl->secondary_in_reload;
6581 rtx real_oldequiv = oldequiv;
6584 enum insn_code icode;
6585 enum insn_code tertiary_icode = CODE_FOR_nothing;
6587 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6588 and similarly for OLD.
6589 See comments in get_secondary_reload in reload.c. */
6590 /* If it is a pseudo that cannot be replaced with its
6591 equivalent MEM, we must fall back to reload_in, which
6592 will have all the necessary substitutions registered.
6593 Likewise for a pseudo that can't be replaced with its
6594 equivalent constant.
6596 Take extra care for subregs of such pseudos. Note that
6597 we cannot use reg_equiv_mem in this case because it is
6598 not in the right mode. */
6601 if (GET_CODE (tmp) == SUBREG)
6602 tmp = SUBREG_REG (tmp);
6604 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6605 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6606 || reg_equiv_constant[REGNO (tmp)] != 0))
6608 if (! reg_equiv_mem[REGNO (tmp)]
6609 || num_not_at_initial_offset
6610 || GET_CODE (oldequiv) == SUBREG)
6611 real_oldequiv = rl->in;
6613 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6617 if (GET_CODE (tmp) == SUBREG)
6618 tmp = SUBREG_REG (tmp);
6620 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6621 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6622 || reg_equiv_constant[REGNO (tmp)] != 0))
6624 if (! reg_equiv_mem[REGNO (tmp)]
6625 || num_not_at_initial_offset
6626 || GET_CODE (old) == SUBREG)
6629 real_old = reg_equiv_mem[REGNO (tmp)];
6632 second_reload_reg = rld[secondary_reload].reg_rtx;
6633 if (rld[secondary_reload].secondary_in_reload >= 0)
6635 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
6637 third_reload_reg = rld[tertiary_reload].reg_rtx;
6638 tertiary_icode = rld[secondary_reload].secondary_in_icode;
6639 /* We'd have to add more code for quartary reloads. */
6640 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
6642 icode = rl->secondary_in_icode;
6644 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6645 || (rl->in != 0 && rl->out != 0))
6647 secondary_reload_info sri, sri2;
6648 enum reg_class new_class, new_t_class;
6650 sri.icode = CODE_FOR_nothing;
6651 sri.prev_sri = NULL;
6652 new_class = targetm.secondary_reload (1, real_oldequiv, rl->class,
6655 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
6656 second_reload_reg = 0;
6657 else if (new_class == NO_REGS)
6659 if (reload_adjust_reg_for_icode (&second_reload_reg,
6660 third_reload_reg, sri.icode))
6661 icode = sri.icode, third_reload_reg = 0;
6663 oldequiv = old, real_oldequiv = real_old;
6665 else if (sri.icode != CODE_FOR_nothing)
6666 /* We currently lack a way to express this in reloads. */
6670 sri2.icode = CODE_FOR_nothing;
6671 sri2.prev_sri = &sri;
6672 new_t_class = targetm.secondary_reload (1, real_oldequiv,
6673 new_class, mode, &sri);
6674 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
6676 if (reload_adjust_reg_for_temp (&second_reload_reg,
6679 third_reload_reg = 0, tertiary_icode = sri2.icode;
6681 oldequiv = old, real_oldequiv = real_old;
6683 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
6685 rtx intermediate = second_reload_reg;
6687 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6689 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
6692 second_reload_reg = intermediate;
6693 tertiary_icode = sri2.icode;
6696 oldequiv = old, real_oldequiv = real_old;
6698 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
6700 rtx intermediate = second_reload_reg;
6702 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6704 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
6707 second_reload_reg = intermediate;
6708 tertiary_icode = sri2.icode;
6711 oldequiv = old, real_oldequiv = real_old;
6714 /* This could be handled more intelligently too. */
6715 oldequiv = old, real_oldequiv = real_old;
6719 /* If we still need a secondary reload register, check
6720 to see if it is being used as a scratch or intermediate
6721 register and generate code appropriately. If we need
6722 a scratch register, use REAL_OLDEQUIV since the form of
6723 the insn may depend on the actual address if it is
6726 if (second_reload_reg)
6728 if (icode != CODE_FOR_nothing)
6730 /* We'd have to add extra code to handle this case. */
6731 gcc_assert (!third_reload_reg);
6733 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6734 second_reload_reg));
6739 /* See if we need a scratch register to load the
6740 intermediate register (a tertiary reload). */
6741 if (tertiary_icode != CODE_FOR_nothing)
6743 emit_insn ((GEN_FCN (tertiary_icode)
6744 (second_reload_reg, real_oldequiv,
6745 third_reload_reg)));
6747 else if (third_reload_reg)
6749 gen_reload (third_reload_reg, real_oldequiv,
6752 gen_reload (second_reload_reg, third_reload_reg,
6757 gen_reload (second_reload_reg, real_oldequiv,
6761 oldequiv = second_reload_reg;
6766 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6768 rtx real_oldequiv = oldequiv;
6770 if ((REG_P (oldequiv)
6771 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6772 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6773 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6774 || (GET_CODE (oldequiv) == SUBREG
6775 && REG_P (SUBREG_REG (oldequiv))
6776 && (REGNO (SUBREG_REG (oldequiv))
6777 >= FIRST_PSEUDO_REGISTER)
6778 && ((reg_equiv_memory_loc
6779 [REGNO (SUBREG_REG (oldequiv))] != 0)
6780 || (reg_equiv_constant
6781 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6782 || (CONSTANT_P (oldequiv)
6783 && (PREFERRED_RELOAD_CLASS (oldequiv,
6784 REGNO_REG_CLASS (REGNO (reloadreg)))
6786 real_oldequiv = rl->in;
6787 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6791 if (flag_non_call_exceptions)
6792 copy_eh_notes (insn, get_insns ());
6794 /* End this sequence. */
6795 *where = get_insns ();
6798 /* Update reload_override_in so that delete_address_reloads_1
6799 can see the actual register usage. */
6801 reload_override_in[j] = oldequiv;
6804 /* Generate insns to for the output reload RL, which is for the insn described
6805 by CHAIN and has the number J. */
6807 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6810 rtx reloadreg = rl->reg_rtx;
6811 rtx insn = chain->insn;
6814 enum machine_mode mode = GET_MODE (old);
6817 if (rl->when_needed == RELOAD_OTHER)
6820 push_to_sequence (output_reload_insns[rl->opnum]);
6822 /* Determine the mode to reload in.
6823 See comments above (for input reloading). */
6825 if (mode == VOIDmode)
6827 /* VOIDmode should never happen for an output. */
6828 if (asm_noperands (PATTERN (insn)) < 0)
6829 /* It's the compiler's fault. */
6830 fatal_insn ("VOIDmode on an output", insn);
6831 error_for_asm (insn, "output operand is constant in %<asm%>");
6832 /* Prevent crash--use something we know is valid. */
6834 old = gen_rtx_REG (mode, REGNO (reloadreg));
6837 if (GET_MODE (reloadreg) != mode)
6838 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6840 /* If we need two reload regs, set RELOADREG to the intermediate
6841 one, since it will be stored into OLD. We might need a secondary
6842 register only for an input reload, so check again here. */
6844 if (rl->secondary_out_reload >= 0)
6847 int secondary_reload = rl->secondary_out_reload;
6848 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
6850 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
6851 && reg_equiv_mem[REGNO (old)] != 0)
6852 real_old = reg_equiv_mem[REGNO (old)];
6854 if (secondary_reload_class (0, rl->class, mode, real_old) != NO_REGS)
6856 rtx second_reloadreg = reloadreg;
6857 reloadreg = rld[secondary_reload].reg_rtx;
6859 /* See if RELOADREG is to be used as a scratch register
6860 or as an intermediate register. */
6861 if (rl->secondary_out_icode != CODE_FOR_nothing)
6863 /* We'd have to add extra code to handle this case. */
6864 gcc_assert (tertiary_reload < 0);
6866 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6867 (real_old, second_reloadreg, reloadreg)));
6872 /* See if we need both a scratch and intermediate reload
6875 enum insn_code tertiary_icode
6876 = rld[secondary_reload].secondary_out_icode;
6878 /* We'd have to add more code for quartary reloads. */
6879 gcc_assert (tertiary_reload < 0
6880 || rld[tertiary_reload].secondary_out_reload < 0);
6882 if (GET_MODE (reloadreg) != mode)
6883 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6885 if (tertiary_icode != CODE_FOR_nothing)
6887 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
6890 /* Copy primary reload reg to secondary reload reg.
6891 (Note that these have been swapped above, then
6892 secondary reload reg to OLD using our insn.) */
6894 /* If REAL_OLD is a paradoxical SUBREG, remove it
6895 and try to put the opposite SUBREG on
6897 if (GET_CODE (real_old) == SUBREG
6898 && (GET_MODE_SIZE (GET_MODE (real_old))
6899 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6900 && 0 != (tem = gen_lowpart_common
6901 (GET_MODE (SUBREG_REG (real_old)),
6903 real_old = SUBREG_REG (real_old), reloadreg = tem;
6905 gen_reload (reloadreg, second_reloadreg,
6906 rl->opnum, rl->when_needed);
6907 emit_insn ((GEN_FCN (tertiary_icode)
6908 (real_old, reloadreg, third_reloadreg)));
6914 /* Copy between the reload regs here and then to
6917 gen_reload (reloadreg, second_reloadreg,
6918 rl->opnum, rl->when_needed);
6919 if (tertiary_reload >= 0)
6921 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
6923 gen_reload (third_reloadreg, reloadreg,
6924 rl->opnum, rl->when_needed);
6925 reloadreg = third_reloadreg;
6932 /* Output the last reload insn. */
6937 /* Don't output the last reload if OLD is not the dest of
6938 INSN and is in the src and is clobbered by INSN. */
6939 if (! flag_expensive_optimizations
6941 || !(set = single_set (insn))
6942 || rtx_equal_p (old, SET_DEST (set))
6943 || !reg_mentioned_p (old, SET_SRC (set))
6944 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
6945 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
6946 gen_reload (old, reloadreg, rl->opnum,
6950 /* Look at all insns we emitted, just to be safe. */
6951 for (p = get_insns (); p; p = NEXT_INSN (p))
6954 rtx pat = PATTERN (p);
6956 /* If this output reload doesn't come from a spill reg,
6957 clear any memory of reloaded copies of the pseudo reg.
6958 If this output reload comes from a spill reg,
6959 reg_has_output_reload will make this do nothing. */
6960 note_stores (pat, forget_old_reloads_1, NULL);
6962 if (reg_mentioned_p (rl->reg_rtx, pat))
6964 rtx set = single_set (insn);
6965 if (reload_spill_index[j] < 0
6967 && SET_SRC (set) == rl->reg_rtx)
6969 int src = REGNO (SET_SRC (set));
6971 reload_spill_index[j] = src;
6972 SET_HARD_REG_BIT (reg_is_output_reload, src);
6973 if (find_regno_note (insn, REG_DEAD, src))
6974 SET_HARD_REG_BIT (reg_reloaded_died, src);
6976 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6978 int s = rl->secondary_out_reload;
6979 set = single_set (p);
6980 /* If this reload copies only to the secondary reload
6981 register, the secondary reload does the actual
6983 if (s >= 0 && set == NULL_RTX)
6984 /* We can't tell what function the secondary reload
6985 has and where the actual store to the pseudo is
6986 made; leave new_spill_reg_store alone. */
6989 && SET_SRC (set) == rl->reg_rtx
6990 && SET_DEST (set) == rld[s].reg_rtx)
6992 /* Usually the next instruction will be the
6993 secondary reload insn; if we can confirm
6994 that it is, setting new_spill_reg_store to
6995 that insn will allow an extra optimization. */
6996 rtx s_reg = rld[s].reg_rtx;
6997 rtx next = NEXT_INSN (p);
6998 rld[s].out = rl->out;
6999 rld[s].out_reg = rl->out_reg;
7000 set = single_set (next);
7001 if (set && SET_SRC (set) == s_reg
7002 && ! new_spill_reg_store[REGNO (s_reg)])
7004 SET_HARD_REG_BIT (reg_is_output_reload,
7006 new_spill_reg_store[REGNO (s_reg)] = next;
7010 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
7015 if (rl->when_needed == RELOAD_OTHER)
7017 emit_insn (other_output_reload_insns[rl->opnum]);
7018 other_output_reload_insns[rl->opnum] = get_insns ();
7021 output_reload_insns[rl->opnum] = get_insns ();
7023 if (flag_non_call_exceptions)
7024 copy_eh_notes (insn, get_insns ());
7029 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7030 and has the number J. */
7032 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7034 rtx insn = chain->insn;
7035 rtx old = (rl->in && MEM_P (rl->in)
7036 ? rl->in_reg : rl->in);
7039 /* AUTO_INC reloads need to be handled even if inherited. We got an
7040 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7041 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7042 && ! rtx_equal_p (rl->reg_rtx, old)
7043 && rl->reg_rtx != 0)
7044 emit_input_reload_insns (chain, rld + j, old, j);
7046 /* When inheriting a wider reload, we have a MEM in rl->in,
7047 e.g. inheriting a SImode output reload for
7048 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7049 if (optimize && reload_inherited[j] && rl->in
7051 && MEM_P (rl->in_reg)
7052 && reload_spill_index[j] >= 0
7053 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7054 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7056 /* If we are reloading a register that was recently stored in with an
7057 output-reload, see if we can prove there was
7058 actually no need to store the old value in it. */
7061 /* Only attempt this for input reloads; for RELOAD_OTHER we miss
7062 that there may be multiple uses of the previous output reload.
7063 Restricting to RELOAD_FOR_INPUT is mostly paranoia. */
7064 && rl->when_needed == RELOAD_FOR_INPUT
7065 && (reload_inherited[j] || reload_override_in[j])
7067 && REG_P (rl->reg_rtx)
7068 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
7070 /* There doesn't seem to be any reason to restrict this to pseudos
7071 and doing so loses in the case where we are copying from a
7072 register of the wrong class. */
7073 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
7074 >= FIRST_PSEUDO_REGISTER)
7076 /* The insn might have already some references to stackslots
7077 replaced by MEMs, while reload_out_reg still names the
7079 && (dead_or_set_p (insn,
7080 spill_reg_stored_to[REGNO (rl->reg_rtx)])
7081 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
7083 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
7086 /* Do output reloading for reload RL, which is for the insn described by
7087 CHAIN and has the number J.
7088 ??? At some point we need to support handling output reloads of
7089 JUMP_INSNs or insns that set cc0. */
7091 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7094 rtx insn = chain->insn;
7095 /* If this is an output reload that stores something that is
7096 not loaded in this same reload, see if we can eliminate a previous
7098 rtx pseudo = rl->out_reg;
7103 && ! rtx_equal_p (rl->in_reg, pseudo)
7104 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7105 && reg_last_reload_reg[REGNO (pseudo)])
7107 int pseudo_no = REGNO (pseudo);
7108 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7110 /* We don't need to test full validity of last_regno for
7111 inherit here; we only want to know if the store actually
7112 matches the pseudo. */
7113 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7114 && reg_reloaded_contents[last_regno] == pseudo_no
7115 && spill_reg_store[last_regno]
7116 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7117 delete_output_reload (insn, j, last_regno);
7122 || rl->reg_rtx == old
7123 || rl->reg_rtx == 0)
7126 /* An output operand that dies right away does need a reload,
7127 but need not be copied from it. Show the new location in the
7129 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7130 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7132 XEXP (note, 0) = rl->reg_rtx;
7135 /* Likewise for a SUBREG of an operand that dies. */
7136 else if (GET_CODE (old) == SUBREG
7137 && REG_P (SUBREG_REG (old))
7138 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7141 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
7145 else if (GET_CODE (old) == SCRATCH)
7146 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7147 but we don't want to make an output reload. */
7150 /* If is a JUMP_INSN, we can't support output reloads yet. */
7151 gcc_assert (NONJUMP_INSN_P (insn));
7153 emit_output_reload_insns (chain, rld + j, j);
7156 /* Reload number R reloads from or to a group of hard registers starting at
7157 register REGNO. Return true if it can be treated for inheritance purposes
7158 like a group of reloads, each one reloading a single hard register.
7159 The caller has already checked that the spill register and REGNO use
7160 the same number of registers to store the reload value. */
7163 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
7165 #ifdef CANNOT_CHANGE_MODE_CLASS
7166 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
7167 GET_MODE (rld[r].reg_rtx),
7168 reg_raw_mode[reload_spill_index[r]])
7169 && !REG_CANNOT_CHANGE_MODE_P (regno,
7170 GET_MODE (rld[r].reg_rtx),
7171 reg_raw_mode[regno]));
7177 /* Output insns to reload values in and out of the chosen reload regs. */
7180 emit_reload_insns (struct insn_chain *chain)
7182 rtx insn = chain->insn;
7186 CLEAR_HARD_REG_SET (reg_reloaded_died);
7188 for (j = 0; j < reload_n_operands; j++)
7189 input_reload_insns[j] = input_address_reload_insns[j]
7190 = inpaddr_address_reload_insns[j]
7191 = output_reload_insns[j] = output_address_reload_insns[j]
7192 = outaddr_address_reload_insns[j]
7193 = other_output_reload_insns[j] = 0;
7194 other_input_address_reload_insns = 0;
7195 other_input_reload_insns = 0;
7196 operand_reload_insns = 0;
7197 other_operand_reload_insns = 0;
7199 /* Dump reloads into the dump file. */
7202 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7203 debug_reload_to_stream (dump_file);
7206 /* Now output the instructions to copy the data into and out of the
7207 reload registers. Do these in the order that the reloads were reported,
7208 since reloads of base and index registers precede reloads of operands
7209 and the operands may need the base and index registers reloaded. */
7211 for (j = 0; j < n_reloads; j++)
7214 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7215 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7217 do_input_reload (chain, rld + j, j);
7218 do_output_reload (chain, rld + j, j);
7221 /* Now write all the insns we made for reloads in the order expected by
7222 the allocation functions. Prior to the insn being reloaded, we write
7223 the following reloads:
7225 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7227 RELOAD_OTHER reloads.
7229 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7230 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7231 RELOAD_FOR_INPUT reload for the operand.
7233 RELOAD_FOR_OPADDR_ADDRS reloads.
7235 RELOAD_FOR_OPERAND_ADDRESS reloads.
7237 After the insn being reloaded, we write the following:
7239 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7240 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7241 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7242 reloads for the operand. The RELOAD_OTHER output reloads are
7243 output in descending order by reload number. */
7245 emit_insn_before (other_input_address_reload_insns, insn);
7246 emit_insn_before (other_input_reload_insns, insn);
7248 for (j = 0; j < reload_n_operands; j++)
7250 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7251 emit_insn_before (input_address_reload_insns[j], insn);
7252 emit_insn_before (input_reload_insns[j], insn);
7255 emit_insn_before (other_operand_reload_insns, insn);
7256 emit_insn_before (operand_reload_insns, insn);
7258 for (j = 0; j < reload_n_operands; j++)
7260 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7261 x = emit_insn_after (output_address_reload_insns[j], x);
7262 x = emit_insn_after (output_reload_insns[j], x);
7263 emit_insn_after (other_output_reload_insns[j], x);
7266 /* For all the spill regs newly reloaded in this instruction,
7267 record what they were reloaded from, so subsequent instructions
7268 can inherit the reloads.
7270 Update spill_reg_store for the reloads of this insn.
7271 Copy the elements that were updated in the loop above. */
7273 for (j = 0; j < n_reloads; j++)
7275 int r = reload_order[j];
7276 int i = reload_spill_index[r];
7278 /* If this is a non-inherited input reload from a pseudo, we must
7279 clear any memory of a previous store to the same pseudo. Only do
7280 something if there will not be an output reload for the pseudo
7282 if (rld[r].in_reg != 0
7283 && ! (reload_inherited[r] || reload_override_in[r]))
7285 rtx reg = rld[r].in_reg;
7287 if (GET_CODE (reg) == SUBREG)
7288 reg = SUBREG_REG (reg);
7291 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7292 && ! reg_has_output_reload[REGNO (reg)])
7294 int nregno = REGNO (reg);
7296 if (reg_last_reload_reg[nregno])
7298 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7300 if (reg_reloaded_contents[last_regno] == nregno)
7301 spill_reg_store[last_regno] = 0;
7306 /* I is nonneg if this reload used a register.
7307 If rld[r].reg_rtx is 0, this is an optional reload
7308 that we opted to ignore. */
7310 if (i >= 0 && rld[r].reg_rtx != 0)
7312 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7314 int part_reaches_end = 0;
7315 int all_reaches_end = 1;
7317 /* For a multi register reload, we need to check if all or part
7318 of the value lives to the end. */
7319 for (k = 0; k < nr; k++)
7321 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7322 rld[r].when_needed))
7323 part_reaches_end = 1;
7325 all_reaches_end = 0;
7328 /* Ignore reloads that don't reach the end of the insn in
7330 if (all_reaches_end)
7332 /* First, clear out memory of what used to be in this spill reg.
7333 If consecutive registers are used, clear them all. */
7335 for (k = 0; k < nr; k++)
7337 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7338 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7341 /* Maybe the spill reg contains a copy of reload_out. */
7343 && (REG_P (rld[r].out)
7347 || REG_P (rld[r].out_reg)))
7349 rtx out = (REG_P (rld[r].out)
7353 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7354 int nregno = REGNO (out);
7355 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7356 : hard_regno_nregs[nregno]
7357 [GET_MODE (rld[r].reg_rtx)]);
7360 spill_reg_store[i] = new_spill_reg_store[i];
7361 spill_reg_stored_to[i] = out;
7362 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7364 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7366 && inherit_piecemeal_p (r, nregno));
7368 /* If NREGNO is a hard register, it may occupy more than
7369 one register. If it does, say what is in the
7370 rest of the registers assuming that both registers
7371 agree on how many words the object takes. If not,
7372 invalidate the subsequent registers. */
7374 if (nregno < FIRST_PSEUDO_REGISTER)
7375 for (k = 1; k < nnr; k++)
7376 reg_last_reload_reg[nregno + k]
7378 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7381 /* Now do the inverse operation. */
7382 for (k = 0; k < nr; k++)
7384 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7385 reg_reloaded_contents[i + k]
7386 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7389 reg_reloaded_insn[i + k] = insn;
7390 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7391 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7392 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7396 /* Maybe the spill reg contains a copy of reload_in. Only do
7397 something if there will not be an output reload for
7398 the register being reloaded. */
7399 else if (rld[r].out_reg == 0
7401 && ((REG_P (rld[r].in)
7402 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7403 && ! reg_has_output_reload[REGNO (rld[r].in)])
7404 || (REG_P (rld[r].in_reg)
7405 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7406 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7413 if (REG_P (rld[r].in)
7414 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7416 else if (REG_P (rld[r].in_reg))
7419 in = XEXP (rld[r].in_reg, 0);
7420 nregno = REGNO (in);
7422 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7423 : hard_regno_nregs[nregno]
7424 [GET_MODE (rld[r].reg_rtx)]);
7426 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7428 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7430 && inherit_piecemeal_p (r, nregno));
7432 if (nregno < FIRST_PSEUDO_REGISTER)
7433 for (k = 1; k < nnr; k++)
7434 reg_last_reload_reg[nregno + k]
7436 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7439 /* Unless we inherited this reload, show we haven't
7440 recently done a store.
7441 Previous stores of inherited auto_inc expressions
7442 also have to be discarded. */
7443 if (! reload_inherited[r]
7444 || (rld[r].out && ! rld[r].out_reg))
7445 spill_reg_store[i] = 0;
7447 for (k = 0; k < nr; k++)
7449 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7450 reg_reloaded_contents[i + k]
7451 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7454 reg_reloaded_insn[i + k] = insn;
7455 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7456 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7457 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7462 /* However, if part of the reload reaches the end, then we must
7463 invalidate the old info for the part that survives to the end. */
7464 else if (part_reaches_end)
7466 for (k = 0; k < nr; k++)
7467 if (reload_reg_reaches_end_p (i + k,
7469 rld[r].when_needed))
7470 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7474 /* The following if-statement was #if 0'd in 1.34 (or before...).
7475 It's reenabled in 1.35 because supposedly nothing else
7476 deals with this problem. */
7478 /* If a register gets output-reloaded from a non-spill register,
7479 that invalidates any previous reloaded copy of it.
7480 But forget_old_reloads_1 won't get to see it, because
7481 it thinks only about the original insn. So invalidate it here. */
7482 if (i < 0 && rld[r].out != 0
7483 && (REG_P (rld[r].out)
7484 || (MEM_P (rld[r].out)
7485 && REG_P (rld[r].out_reg))))
7487 rtx out = (REG_P (rld[r].out)
7488 ? rld[r].out : rld[r].out_reg);
7489 int nregno = REGNO (out);
7490 if (nregno >= FIRST_PSEUDO_REGISTER)
7492 rtx src_reg, store_insn = NULL_RTX;
7494 reg_last_reload_reg[nregno] = 0;
7496 /* If we can find a hard register that is stored, record
7497 the storing insn so that we may delete this insn with
7498 delete_output_reload. */
7499 src_reg = rld[r].reg_rtx;
7501 /* If this is an optional reload, try to find the source reg
7502 from an input reload. */
7505 rtx set = single_set (insn);
7506 if (set && SET_DEST (set) == rld[r].out)
7510 src_reg = SET_SRC (set);
7512 for (k = 0; k < n_reloads; k++)
7514 if (rld[k].in == src_reg)
7516 src_reg = rld[k].reg_rtx;
7523 store_insn = new_spill_reg_store[REGNO (src_reg)];
7524 if (src_reg && REG_P (src_reg)
7525 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7527 int src_regno = REGNO (src_reg);
7528 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7529 /* The place where to find a death note varies with
7530 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7531 necessarily checked exactly in the code that moves
7532 notes, so just check both locations. */
7533 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7534 if (! note && store_insn)
7535 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7538 spill_reg_store[src_regno + nr] = store_insn;
7539 spill_reg_stored_to[src_regno + nr] = out;
7540 reg_reloaded_contents[src_regno + nr] = nregno;
7541 reg_reloaded_insn[src_regno + nr] = store_insn;
7542 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7543 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7544 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7545 GET_MODE (src_reg)))
7546 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7548 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7550 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7552 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7554 reg_last_reload_reg[nregno] = src_reg;
7555 /* We have to set reg_has_output_reload here, or else
7556 forget_old_reloads_1 will clear reg_last_reload_reg
7558 reg_has_output_reload[nregno] = 1;
7563 int num_regs = hard_regno_nregs[nregno][GET_MODE (rld[r].out)];
7565 while (num_regs-- > 0)
7566 reg_last_reload_reg[nregno + num_regs] = 0;
7570 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7573 /* Go through the motions to emit INSN and test if it is strictly valid.
7574 Return the emitted insn if valid, else return NULL. */
7577 emit_insn_if_valid_for_reload (rtx insn)
7579 rtx last = get_last_insn ();
7582 insn = emit_insn (insn);
7583 code = recog_memoized (insn);
7587 extract_insn (insn);
7588 /* We want constrain operands to treat this insn strictly in its
7589 validity determination, i.e., the way it would after reload has
7591 if (constrain_operands (1))
7595 delete_insns_since (last);
7599 /* Emit code to perform a reload from IN (which may be a reload register) to
7600 OUT (which may also be a reload register). IN or OUT is from operand
7601 OPNUM with reload type TYPE.
7603 Returns first insn emitted. */
7606 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7608 rtx last = get_last_insn ();
7611 /* If IN is a paradoxical SUBREG, remove it and try to put the
7612 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7613 if (GET_CODE (in) == SUBREG
7614 && (GET_MODE_SIZE (GET_MODE (in))
7615 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7616 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7617 in = SUBREG_REG (in), out = tem;
7618 else if (GET_CODE (out) == SUBREG
7619 && (GET_MODE_SIZE (GET_MODE (out))
7620 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7621 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7622 out = SUBREG_REG (out), in = tem;
7624 /* How to do this reload can get quite tricky. Normally, we are being
7625 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7626 register that didn't get a hard register. In that case we can just
7627 call emit_move_insn.
7629 We can also be asked to reload a PLUS that adds a register or a MEM to
7630 another register, constant or MEM. This can occur during frame pointer
7631 elimination and while reloading addresses. This case is handled by
7632 trying to emit a single insn to perform the add. If it is not valid,
7633 we use a two insn sequence.
7635 Or we can be asked to reload an unary operand that was a fragment of
7636 an addressing mode, into a register. If it isn't recognized as-is,
7637 we try making the unop operand and the reload-register the same:
7638 (set reg:X (unop:X expr:Y))
7639 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
7641 Finally, we could be called to handle an 'o' constraint by putting
7642 an address into a register. In that case, we first try to do this
7643 with a named pattern of "reload_load_address". If no such pattern
7644 exists, we just emit a SET insn and hope for the best (it will normally
7645 be valid on machines that use 'o').
7647 This entire process is made complex because reload will never
7648 process the insns we generate here and so we must ensure that
7649 they will fit their constraints and also by the fact that parts of
7650 IN might be being reloaded separately and replaced with spill registers.
7651 Because of this, we are, in some sense, just guessing the right approach
7652 here. The one listed above seems to work.
7654 ??? At some point, this whole thing needs to be rethought. */
7656 if (GET_CODE (in) == PLUS
7657 && (REG_P (XEXP (in, 0))
7658 || GET_CODE (XEXP (in, 0)) == SUBREG
7659 || MEM_P (XEXP (in, 0)))
7660 && (REG_P (XEXP (in, 1))
7661 || GET_CODE (XEXP (in, 1)) == SUBREG
7662 || CONSTANT_P (XEXP (in, 1))
7663 || MEM_P (XEXP (in, 1))))
7665 /* We need to compute the sum of a register or a MEM and another
7666 register, constant, or MEM, and put it into the reload
7667 register. The best possible way of doing this is if the machine
7668 has a three-operand ADD insn that accepts the required operands.
7670 The simplest approach is to try to generate such an insn and see if it
7671 is recognized and matches its constraints. If so, it can be used.
7673 It might be better not to actually emit the insn unless it is valid,
7674 but we need to pass the insn as an operand to `recog' and
7675 `extract_insn' and it is simpler to emit and then delete the insn if
7676 not valid than to dummy things up. */
7678 rtx op0, op1, tem, insn;
7681 op0 = find_replacement (&XEXP (in, 0));
7682 op1 = find_replacement (&XEXP (in, 1));
7684 /* Since constraint checking is strict, commutativity won't be
7685 checked, so we need to do that here to avoid spurious failure
7686 if the add instruction is two-address and the second operand
7687 of the add is the same as the reload reg, which is frequently
7688 the case. If the insn would be A = B + A, rearrange it so
7689 it will be A = A + B as constrain_operands expects. */
7691 if (REG_P (XEXP (in, 1))
7692 && REGNO (out) == REGNO (XEXP (in, 1)))
7693 tem = op0, op0 = op1, op1 = tem;
7695 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7696 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7698 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7702 /* If that failed, we must use a conservative two-insn sequence.
7704 Use a move to copy one operand into the reload register. Prefer
7705 to reload a constant, MEM or pseudo since the move patterns can
7706 handle an arbitrary operand. If OP1 is not a constant, MEM or
7707 pseudo and OP1 is not a valid operand for an add instruction, then
7710 After reloading one of the operands into the reload register, add
7711 the reload register to the output register.
7713 If there is another way to do this for a specific machine, a
7714 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7717 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7719 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7721 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7722 || (code != CODE_FOR_nothing
7723 && ! ((*insn_data[code].operand[2].predicate)
7724 (op1, insn_data[code].operand[2].mode))))
7725 tem = op0, op0 = op1, op1 = tem;
7727 gen_reload (out, op0, opnum, type);
7729 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7730 This fixes a problem on the 32K where the stack pointer cannot
7731 be used as an operand of an add insn. */
7733 if (rtx_equal_p (op0, op1))
7736 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
7739 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7741 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7745 /* If that failed, copy the address register to the reload register.
7746 Then add the constant to the reload register. */
7748 gen_reload (out, op1, opnum, type);
7749 insn = emit_insn (gen_add2_insn (out, op0));
7750 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7753 #ifdef SECONDARY_MEMORY_NEEDED
7754 /* If we need a memory location to do the move, do it that way. */
7755 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7756 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7757 && (REG_P (out) || GET_CODE (out) == SUBREG)
7758 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7759 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7760 REGNO_REG_CLASS (reg_or_subregno (out)),
7763 /* Get the memory to use and rewrite both registers to its mode. */
7764 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7766 if (GET_MODE (loc) != GET_MODE (out))
7767 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7769 if (GET_MODE (loc) != GET_MODE (in))
7770 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7772 gen_reload (loc, in, opnum, type);
7773 gen_reload (out, loc, opnum, type);
7776 else if (REG_P (out) && UNARY_P (in))
7783 /* First, try a plain SET. */
7784 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7788 /* If that failed, move the inner operand to the reload
7789 register, and try the same unop with the inner expression
7790 replaced with the reload register. */
7793 if (GET_MODE (op1) != GET_MODE (out))
7794 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
7798 gen_reload (out_moded, op1, opnum, type);
7801 = gen_rtx_SET (VOIDmode, out,
7802 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
7804 insn = emit_insn_if_valid_for_reload (insn);
7808 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7812 fatal_insn ("Failure trying to reload:", set);
7814 /* If IN is a simple operand, use gen_move_insn. */
7815 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
7816 emit_insn (gen_move_insn (out, in));
7818 #ifdef HAVE_reload_load_address
7819 else if (HAVE_reload_load_address)
7820 emit_insn (gen_reload_load_address (out, in));
7823 /* Otherwise, just write (set OUT IN) and hope for the best. */
7825 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7827 /* Return the first insn emitted.
7828 We can not just return get_last_insn, because there may have
7829 been multiple instructions emitted. Also note that gen_move_insn may
7830 emit more than one insn itself, so we can not assume that there is one
7831 insn emitted per emit_insn_before call. */
7833 return last ? NEXT_INSN (last) : get_insns ();
7836 /* Delete a previously made output-reload whose result we now believe
7837 is not needed. First we double-check.
7839 INSN is the insn now being processed.
7840 LAST_RELOAD_REG is the hard register number for which we want to delete
7841 the last output reload.
7842 J is the reload-number that originally used REG. The caller has made
7843 certain that reload J doesn't use REG any longer for input. */
7846 delete_output_reload (rtx insn, int j, int last_reload_reg)
7848 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7849 rtx reg = spill_reg_stored_to[last_reload_reg];
7852 int n_inherited = 0;
7856 /* It is possible that this reload has been only used to set another reload
7857 we eliminated earlier and thus deleted this instruction too. */
7858 if (INSN_DELETED_P (output_reload_insn))
7861 /* Get the raw pseudo-register referred to. */
7863 while (GET_CODE (reg) == SUBREG)
7864 reg = SUBREG_REG (reg);
7865 substed = reg_equiv_memory_loc[REGNO (reg)];
7867 /* This is unsafe if the operand occurs more often in the current
7868 insn than it is inherited. */
7869 for (k = n_reloads - 1; k >= 0; k--)
7871 rtx reg2 = rld[k].in;
7874 if (MEM_P (reg2) || reload_override_in[k])
7875 reg2 = rld[k].in_reg;
7877 if (rld[k].out && ! rld[k].out_reg)
7878 reg2 = XEXP (rld[k].in_reg, 0);
7880 while (GET_CODE (reg2) == SUBREG)
7881 reg2 = SUBREG_REG (reg2);
7882 if (rtx_equal_p (reg2, reg))
7884 if (reload_inherited[k] || reload_override_in[k] || k == j)
7887 reg2 = rld[k].out_reg;
7890 while (GET_CODE (reg2) == SUBREG)
7891 reg2 = XEXP (reg2, 0);
7892 if (rtx_equal_p (reg2, reg))
7899 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7901 n_occurrences += count_occurrences (PATTERN (insn),
7902 eliminate_regs (substed, 0,
7904 if (n_occurrences > n_inherited)
7907 /* If the pseudo-reg we are reloading is no longer referenced
7908 anywhere between the store into it and here,
7909 and we're within the same basic block, then the value can only
7910 pass through the reload reg and end up here.
7911 Otherwise, give up--return. */
7912 for (i1 = NEXT_INSN (output_reload_insn);
7913 i1 != insn; i1 = NEXT_INSN (i1))
7915 if (NOTE_INSN_BASIC_BLOCK_P (i1))
7917 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
7918 && reg_mentioned_p (reg, PATTERN (i1)))
7920 /* If this is USE in front of INSN, we only have to check that
7921 there are no more references than accounted for by inheritance. */
7922 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
7924 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7925 i1 = NEXT_INSN (i1);
7927 if (n_occurrences <= n_inherited && i1 == insn)
7933 /* We will be deleting the insn. Remove the spill reg information. */
7934 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
7936 spill_reg_store[last_reload_reg + k] = 0;
7937 spill_reg_stored_to[last_reload_reg + k] = 0;
7940 /* The caller has already checked that REG dies or is set in INSN.
7941 It has also checked that we are optimizing, and thus some
7942 inaccuracies in the debugging information are acceptable.
7943 So we could just delete output_reload_insn. But in some cases
7944 we can improve the debugging information without sacrificing
7945 optimization - maybe even improving the code: See if the pseudo
7946 reg has been completely replaced with reload regs. If so, delete
7947 the store insn and forget we had a stack slot for the pseudo. */
7948 if (rld[j].out != rld[j].in
7949 && REG_N_DEATHS (REGNO (reg)) == 1
7950 && REG_N_SETS (REGNO (reg)) == 1
7951 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7952 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7956 /* We know that it was used only between here and the beginning of
7957 the current basic block. (We also know that the last use before
7958 INSN was the output reload we are thinking of deleting, but never
7959 mind that.) Search that range; see if any ref remains. */
7960 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7962 rtx set = single_set (i2);
7964 /* Uses which just store in the pseudo don't count,
7965 since if they are the only uses, they are dead. */
7966 if (set != 0 && SET_DEST (set) == reg)
7971 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
7972 && reg_mentioned_p (reg, PATTERN (i2)))
7974 /* Some other ref remains; just delete the output reload we
7976 delete_address_reloads (output_reload_insn, insn);
7977 delete_insn (output_reload_insn);
7982 /* Delete the now-dead stores into this pseudo. Note that this
7983 loop also takes care of deleting output_reload_insn. */
7984 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7986 rtx set = single_set (i2);
7988 if (set != 0 && SET_DEST (set) == reg)
7990 delete_address_reloads (i2, insn);
7998 /* For the debugging info, say the pseudo lives in this reload reg. */
7999 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
8000 alter_reg (REGNO (reg), -1);
8004 delete_address_reloads (output_reload_insn, insn);
8005 delete_insn (output_reload_insn);
8009 /* We are going to delete DEAD_INSN. Recursively delete loads of
8010 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8011 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8013 delete_address_reloads (rtx dead_insn, rtx current_insn)
8015 rtx set = single_set (dead_insn);
8016 rtx set2, dst, prev, next;
8019 rtx dst = SET_DEST (set);
8021 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8023 /* If we deleted the store from a reloaded post_{in,de}c expression,
8024 we can delete the matching adds. */
8025 prev = PREV_INSN (dead_insn);
8026 next = NEXT_INSN (dead_insn);
8027 if (! prev || ! next)
8029 set = single_set (next);
8030 set2 = single_set (prev);
8032 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8033 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8034 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8036 dst = SET_DEST (set);
8037 if (! rtx_equal_p (dst, SET_DEST (set2))
8038 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8039 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8040 || (INTVAL (XEXP (SET_SRC (set), 1))
8041 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8043 delete_related_insns (prev);
8044 delete_related_insns (next);
8047 /* Subfunction of delete_address_reloads: process registers found in X. */
8049 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8051 rtx prev, set, dst, i2;
8053 enum rtx_code code = GET_CODE (x);
8057 const char *fmt = GET_RTX_FORMAT (code);
8058 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8061 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8062 else if (fmt[i] == 'E')
8064 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8065 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8072 if (spill_reg_order[REGNO (x)] < 0)
8075 /* Scan backwards for the insn that sets x. This might be a way back due
8077 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8079 code = GET_CODE (prev);
8080 if (code == CODE_LABEL || code == JUMP_INSN)
8084 if (reg_set_p (x, PATTERN (prev)))
8086 if (reg_referenced_p (x, PATTERN (prev)))
8089 if (! prev || INSN_UID (prev) < reload_first_uid)
8091 /* Check that PREV only sets the reload register. */
8092 set = single_set (prev);
8095 dst = SET_DEST (set);
8097 || ! rtx_equal_p (dst, x))
8099 if (! reg_set_p (dst, PATTERN (dead_insn)))
8101 /* Check if DST was used in a later insn -
8102 it might have been inherited. */
8103 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8109 if (reg_referenced_p (dst, PATTERN (i2)))
8111 /* If there is a reference to the register in the current insn,
8112 it might be loaded in a non-inherited reload. If no other
8113 reload uses it, that means the register is set before
8115 if (i2 == current_insn)
8117 for (j = n_reloads - 1; j >= 0; j--)
8118 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8119 || reload_override_in[j] == dst)
8121 for (j = n_reloads - 1; j >= 0; j--)
8122 if (rld[j].in && rld[j].reg_rtx == dst)
8131 /* If DST is still live at CURRENT_INSN, check if it is used for
8132 any reload. Note that even if CURRENT_INSN sets DST, we still
8133 have to check the reloads. */
8134 if (i2 == current_insn)
8136 for (j = n_reloads - 1; j >= 0; j--)
8137 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8138 || reload_override_in[j] == dst)
8140 /* ??? We can't finish the loop here, because dst might be
8141 allocated to a pseudo in this block if no reload in this
8142 block needs any of the classes containing DST - see
8143 spill_hard_reg. There is no easy way to tell this, so we
8144 have to scan till the end of the basic block. */
8146 if (reg_set_p (dst, PATTERN (i2)))
8150 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8151 reg_reloaded_contents[REGNO (dst)] = -1;
8155 /* Output reload-insns to reload VALUE into RELOADREG.
8156 VALUE is an autoincrement or autodecrement RTX whose operand
8157 is a register or memory location;
8158 so reloading involves incrementing that location.
8159 IN is either identical to VALUE, or some cheaper place to reload from.
8161 INC_AMOUNT is the number to increment or decrement by (always positive).
8162 This cannot be deduced from VALUE.
8164 Return the instruction that stores into RELOADREG. */
8167 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8169 /* REG or MEM to be copied and incremented. */
8170 rtx incloc = XEXP (value, 0);
8171 /* Nonzero if increment after copying. */
8172 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
8178 rtx real_in = in == value ? XEXP (in, 0) : in;
8180 /* No hard register is equivalent to this register after
8181 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8182 we could inc/dec that register as well (maybe even using it for
8183 the source), but I'm not sure it's worth worrying about. */
8185 reg_last_reload_reg[REGNO (incloc)] = 0;
8187 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8188 inc_amount = -inc_amount;
8190 inc = GEN_INT (inc_amount);
8192 /* If this is post-increment, first copy the location to the reload reg. */
8193 if (post && real_in != reloadreg)
8194 emit_insn (gen_move_insn (reloadreg, real_in));
8198 /* See if we can directly increment INCLOC. Use a method similar to
8199 that in gen_reload. */
8201 last = get_last_insn ();
8202 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8203 gen_rtx_PLUS (GET_MODE (incloc),
8206 code = recog_memoized (add_insn);
8209 extract_insn (add_insn);
8210 if (constrain_operands (1))
8212 /* If this is a pre-increment and we have incremented the value
8213 where it lives, copy the incremented value to RELOADREG to
8214 be used as an address. */
8217 emit_insn (gen_move_insn (reloadreg, incloc));
8222 delete_insns_since (last);
8225 /* If couldn't do the increment directly, must increment in RELOADREG.
8226 The way we do this depends on whether this is pre- or post-increment.
8227 For pre-increment, copy INCLOC to the reload register, increment it
8228 there, then save back. */
8232 if (in != reloadreg)
8233 emit_insn (gen_move_insn (reloadreg, real_in));
8234 emit_insn (gen_add2_insn (reloadreg, inc));
8235 store = emit_insn (gen_move_insn (incloc, reloadreg));
8240 Because this might be a jump insn or a compare, and because RELOADREG
8241 may not be available after the insn in an input reload, we must do
8242 the incrementation before the insn being reloaded for.
8244 We have already copied IN to RELOADREG. Increment the copy in
8245 RELOADREG, save that back, then decrement RELOADREG so it has
8246 the original value. */
8248 emit_insn (gen_add2_insn (reloadreg, inc));
8249 store = emit_insn (gen_move_insn (incloc, reloadreg));
8250 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8258 add_auto_inc_notes (rtx insn, rtx x)
8260 enum rtx_code code = GET_CODE (x);
8264 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8267 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8271 /* Scan all the operand sub-expressions. */
8272 fmt = GET_RTX_FORMAT (code);
8273 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8276 add_auto_inc_notes (insn, XEXP (x, i));
8277 else if (fmt[i] == 'E')
8278 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8279 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8284 /* Copy EH notes from an insn to its reloads. */
8286 copy_eh_notes (rtx insn, rtx x)
8288 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8291 for (; x != 0; x = NEXT_INSN (x))
8293 if (may_trap_p (PATTERN (x)))
8295 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8301 /* This is used by reload pass, that does emit some instructions after
8302 abnormal calls moving basic block end, but in fact it wants to emit
8303 them on the edge. Looks for abnormal call edges, find backward the
8304 proper call and fix the damage.
8306 Similar handle instructions throwing exceptions internally. */
8308 fixup_abnormal_edges (void)
8310 bool inserted = false;
8318 /* Look for cases we are interested in - calls or instructions causing
8320 FOR_EACH_EDGE (e, ei, bb->succs)
8322 if (e->flags & EDGE_ABNORMAL_CALL)
8324 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8325 == (EDGE_ABNORMAL | EDGE_EH))
8328 if (e && !CALL_P (BB_END (bb))
8329 && !can_throw_internal (BB_END (bb)))
8333 /* Get past the new insns generated. Allow notes, as the insns
8334 may be already deleted. */
8336 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8337 && !can_throw_internal (insn)
8338 && insn != BB_HEAD (bb))
8339 insn = PREV_INSN (insn);
8341 if (CALL_P (insn) || can_throw_internal (insn))
8345 stop = NEXT_INSN (BB_END (bb));
8347 insn = NEXT_INSN (insn);
8349 FOR_EACH_EDGE (e, ei, bb->succs)
8350 if (e->flags & EDGE_FALLTHRU)
8353 while (insn && insn != stop)
8355 next = NEXT_INSN (insn);
8360 /* Sometimes there's still the return value USE.
8361 If it's placed after a trapping call (i.e. that
8362 call is the last insn anyway), we have no fallthru
8363 edge. Simply delete this use and don't try to insert
8364 on the non-existent edge. */
8365 if (GET_CODE (PATTERN (insn)) != USE)
8367 /* We're not deleting it, we're moving it. */
8368 INSN_DELETED_P (insn) = 0;
8369 PREV_INSN (insn) = NULL_RTX;
8370 NEXT_INSN (insn) = NULL_RTX;
8372 insert_insn_on_edge (insn, e);
8380 /* It may be that we don't find any such trapping insn. In this
8381 case we discovered quite late that the insn that had been
8382 marked as can_throw_internal in fact couldn't trap at all.
8383 So we should in fact delete the EH edges out of the block. */
8385 purge_dead_edges (bb);
8389 /* We've possibly turned single trapping insn into multiple ones. */
8390 if (flag_non_call_exceptions)
8393 blocks = sbitmap_alloc (last_basic_block);
8394 sbitmap_ones (blocks);
8395 find_many_sub_basic_blocks (blocks);
8399 commit_edge_insertions ();
8401 #ifdef ENABLE_CHECKING
8402 /* Verify that we didn't turn one trapping insn into many, and that
8403 we found and corrected all of the problems wrt fixups on the
8405 verify_flow_info ();
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