1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "insn-flags.h"
33 #include "insn-codes.h"
38 #include "basic-block.h"
46 #if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY
47 #define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY
50 /* This file contains the reload pass of the compiler, which is
51 run after register allocation has been done. It checks that
52 each insn is valid (operands required to be in registers really
53 are in registers of the proper class) and fixes up invalid ones
54 by copying values temporarily into registers for the insns
57 The results of register allocation are described by the vector
58 reg_renumber; the insns still contain pseudo regs, but reg_renumber
59 can be used to find which hard reg, if any, a pseudo reg is in.
61 The technique we always use is to free up a few hard regs that are
62 called ``reload regs'', and for each place where a pseudo reg
63 must be in a hard reg, copy it temporarily into one of the reload regs.
65 Reload regs are allocated locally for every instruction that needs
66 reloads. When there are pseudos which are allocated to a register that
67 has been chosen as a reload reg, such pseudos must be ``spilled''.
68 This means that they go to other hard regs, or to stack slots if no other
69 available hard regs can be found. Spilling can invalidate more
70 insns, requiring additional need for reloads, so we must keep checking
71 until the process stabilizes.
73 For machines with different classes of registers, we must keep track
74 of the register class needed for each reload, and make sure that
75 we allocate enough reload registers of each class.
77 The file reload.c contains the code that checks one insn for
78 validity and reports the reloads that it needs. This file
79 is in charge of scanning the entire rtl code, accumulating the
80 reload needs, spilling, assigning reload registers to use for
81 fixing up each insn, and generating the new insns to copy values
82 into the reload registers. */
85 #ifndef REGISTER_MOVE_COST
86 #define REGISTER_MOVE_COST(x, y) 2
89 /* During reload_as_needed, element N contains a REG rtx for the hard reg
90 into which reg N has been reloaded (perhaps for a previous insn). */
91 static rtx *reg_last_reload_reg;
93 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
94 for an output reload that stores into reg N. */
95 static char *reg_has_output_reload;
97 /* Indicates which hard regs are reload-registers for an output reload
98 in the current insn. */
99 static HARD_REG_SET reg_is_output_reload;
101 /* Element N is the constant value to which pseudo reg N is equivalent,
102 or zero if pseudo reg N is not equivalent to a constant.
103 find_reloads looks at this in order to replace pseudo reg N
104 with the constant it stands for. */
105 rtx *reg_equiv_constant;
107 /* Element N is a memory location to which pseudo reg N is equivalent,
108 prior to any register elimination (such as frame pointer to stack
109 pointer). Depending on whether or not it is a valid address, this value
110 is transferred to either reg_equiv_address or reg_equiv_mem. */
111 rtx *reg_equiv_memory_loc;
113 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
114 This is used when the address is not valid as a memory address
115 (because its displacement is too big for the machine.) */
116 rtx *reg_equiv_address;
118 /* Element N is the memory slot to which pseudo reg N is equivalent,
119 or zero if pseudo reg N is not equivalent to a memory slot. */
122 /* Widest width in which each pseudo reg is referred to (via subreg). */
123 static unsigned int *reg_max_ref_width;
125 /* Element N is the list of insns that initialized reg N from its equivalent
126 constant or memory slot. */
127 static rtx *reg_equiv_init;
129 /* Vector to remember old contents of reg_renumber before spilling. */
130 static short *reg_old_renumber;
132 /* During reload_as_needed, element N contains the last pseudo regno reloaded
133 into hard register N. If that pseudo reg occupied more than one register,
134 reg_reloaded_contents points to that pseudo for each spill register in
135 use; all of these must remain set for an inheritance to occur. */
136 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
138 /* During reload_as_needed, element N contains the insn for which
139 hard register N was last used. Its contents are significant only
140 when reg_reloaded_valid is set for this register. */
141 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
143 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
144 static HARD_REG_SET reg_reloaded_valid;
145 /* Indicate if the register was dead at the end of the reload.
146 This is only valid if reg_reloaded_contents is set and valid. */
147 static HARD_REG_SET reg_reloaded_dead;
149 /* Number of spill-regs so far; number of valid elements of spill_regs. */
152 /* In parallel with spill_regs, contains REG rtx's for those regs.
153 Holds the last rtx used for any given reg, or 0 if it has never
154 been used for spilling yet. This rtx is reused, provided it has
156 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
158 /* In parallel with spill_regs, contains nonzero for a spill reg
159 that was stored after the last time it was used.
160 The precise value is the insn generated to do the store. */
161 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
163 /* This is the register that was stored with spill_reg_store. This is a
164 copy of reload_out / reload_out_reg when the value was stored; if
165 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
166 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
168 /* This table is the inverse mapping of spill_regs:
169 indexed by hard reg number,
170 it contains the position of that reg in spill_regs,
171 or -1 for something that is not in spill_regs.
173 ?!? This is no longer accurate. */
174 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
176 /* This reg set indicates registers that can't be used as spill registers for
177 the currently processed insn. These are the hard registers which are live
178 during the insn, but not allocated to pseudos, as well as fixed
180 static HARD_REG_SET bad_spill_regs;
182 /* These are the hard registers that can't be used as spill register for any
183 insn. This includes registers used for user variables and registers that
184 we can't eliminate. A register that appears in this set also can't be used
185 to retry register allocation. */
186 static HARD_REG_SET bad_spill_regs_global;
188 /* Describes order of use of registers for reloading
189 of spilled pseudo-registers. `n_spills' is the number of
190 elements that are actually valid; new ones are added at the end.
192 Both spill_regs and spill_reg_order are used on two occasions:
193 once during find_reload_regs, where they keep track of the spill registers
194 for a single insn, but also during reload_as_needed where they show all
195 the registers ever used by reload. For the latter case, the information
196 is calculated during finish_spills. */
197 static short spill_regs[FIRST_PSEUDO_REGISTER];
199 /* This vector of reg sets indicates, for each pseudo, which hard registers
200 may not be used for retrying global allocation because the register was
201 formerly spilled from one of them. If we allowed reallocating a pseudo to
202 a register that it was already allocated to, reload might not
204 static HARD_REG_SET *pseudo_previous_regs;
206 /* This vector of reg sets indicates, for each pseudo, which hard
207 registers may not be used for retrying global allocation because they
208 are used as spill registers during one of the insns in which the
210 static HARD_REG_SET *pseudo_forbidden_regs;
212 /* All hard regs that have been used as spill registers for any insn are
213 marked in this set. */
214 static HARD_REG_SET used_spill_regs;
216 /* Index of last register assigned as a spill register. We allocate in
217 a round-robin fashion. */
218 static int last_spill_reg;
220 /* Nonzero if indirect addressing is supported on the machine; this means
221 that spilling (REG n) does not require reloading it into a register in
222 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
223 value indicates the level of indirect addressing supported, e.g., two
224 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
226 static char spill_indirect_levels;
228 /* Nonzero if indirect addressing is supported when the innermost MEM is
229 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
230 which these are valid is the same as spill_indirect_levels, above. */
231 char indirect_symref_ok;
233 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
234 char double_reg_address_ok;
236 /* Record the stack slot for each spilled hard register. */
237 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
239 /* Width allocated so far for that stack slot. */
240 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
242 /* Record which pseudos needed to be spilled. */
243 static regset_head spilled_pseudos;
245 /* Used for communication between order_regs_for_reload and count_pseudo.
246 Used to avoid counting one pseudo twice. */
247 static regset_head pseudos_counted;
249 /* First uid used by insns created by reload in this function.
250 Used in find_equiv_reg. */
251 int reload_first_uid;
253 /* Flag set by local-alloc or global-alloc if anything is live in
254 a call-clobbered reg across calls. */
255 int caller_save_needed;
257 /* Set to 1 while reload_as_needed is operating.
258 Required by some machines to handle any generated moves differently. */
259 int reload_in_progress = 0;
261 /* These arrays record the insn_code of insns that may be needed to
262 perform input and output reloads of special objects. They provide a
263 place to pass a scratch register. */
264 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
265 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
267 /* This obstack is used for allocation of rtl during register elimination.
268 The allocated storage can be freed once find_reloads has processed the
270 struct obstack reload_obstack;
272 /* Points to the beginning of the reload_obstack. All insn_chain structures
273 are allocated first. */
274 char *reload_startobj;
276 /* The point after all insn_chain structures. Used to quickly deallocate
277 memory allocated in copy_reloads during calculate_needs_all_insns. */
278 char *reload_firstobj;
280 /* This points before all local rtl generated by register elimination.
281 Used to quickly free all memory after processing one insn. */
282 static char *reload_insn_firstobj;
284 #define obstack_chunk_alloc xmalloc
285 #define obstack_chunk_free free
287 /* List of insn_chain instructions, one for every insn that reload needs to
289 struct insn_chain *reload_insn_chain;
292 extern tree current_function_decl;
294 extern union tree_node *current_function_decl;
297 /* List of all insns needing reloads. */
298 static struct insn_chain *insns_need_reload;
300 /* This structure is used to record information about register eliminations.
301 Each array entry describes one possible way of eliminating a register
302 in favor of another. If there is more than one way of eliminating a
303 particular register, the most preferred should be specified first. */
307 int from; /* Register number to be eliminated. */
308 int to; /* Register number used as replacement. */
309 int initial_offset; /* Initial difference between values. */
310 int can_eliminate; /* Non-zero if this elimination can be done. */
311 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
312 insns made by reload. */
313 int offset; /* Current offset between the two regs. */
314 int previous_offset; /* Offset at end of previous insn. */
315 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
316 rtx from_rtx; /* REG rtx for the register to be eliminated.
317 We cannot simply compare the number since
318 we might then spuriously replace a hard
319 register corresponding to a pseudo
320 assigned to the reg to be eliminated. */
321 rtx to_rtx; /* REG rtx for the replacement. */
324 static struct elim_table * reg_eliminate = 0;
326 /* This is an intermediate structure to initialize the table. It has
327 exactly the members provided by ELIMINABLE_REGS. */
328 static struct elim_table_1
332 } reg_eliminate_1[] =
334 /* If a set of eliminable registers was specified, define the table from it.
335 Otherwise, default to the normal case of the frame pointer being
336 replaced by the stack pointer. */
338 #ifdef ELIMINABLE_REGS
341 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
344 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate_1/sizeof reg_eliminate_1[0])
346 /* Record the number of pending eliminations that have an offset not equal
347 to their initial offset. If non-zero, we use a new copy of each
348 replacement result in any insns encountered. */
349 int num_not_at_initial_offset;
351 /* Count the number of registers that we may be able to eliminate. */
352 static int num_eliminable;
353 /* And the number of registers that are equivalent to a constant that
354 can be eliminated to frame_pointer / arg_pointer + constant. */
355 static int num_eliminable_invariants;
357 /* For each label, we record the offset of each elimination. If we reach
358 a label by more than one path and an offset differs, we cannot do the
359 elimination. This information is indexed by the number of the label.
360 The first table is an array of flags that records whether we have yet
361 encountered a label and the second table is an array of arrays, one
362 entry in the latter array for each elimination. */
364 static char *offsets_known_at;
365 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
367 /* Number of labels in the current function. */
369 static int num_labels;
371 static void maybe_fix_stack_asms PARAMS ((void));
372 static void copy_reloads PARAMS ((struct insn_chain *));
373 static void calculate_needs_all_insns PARAMS ((int));
374 static int find_reg PARAMS ((struct insn_chain *, int,
376 static void find_reload_regs PARAMS ((struct insn_chain *, FILE *));
377 static void select_reload_regs PARAMS ((FILE *));
378 static void delete_caller_save_insns PARAMS ((void));
380 static void spill_failure PARAMS ((rtx, enum reg_class));
381 static void count_spilled_pseudo PARAMS ((int, int, int));
382 static void delete_dead_insn PARAMS ((rtx));
383 static void alter_reg PARAMS ((int, int));
384 static void set_label_offsets PARAMS ((rtx, rtx, int));
385 static void check_eliminable_occurrences PARAMS ((rtx));
386 static void elimination_effects PARAMS ((rtx, enum machine_mode));
387 static int eliminate_regs_in_insn PARAMS ((rtx, int));
388 static void update_eliminable_offsets PARAMS ((void));
389 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
390 static void set_initial_elim_offsets PARAMS ((void));
391 static void verify_initial_elim_offsets PARAMS ((void));
392 static void set_initial_label_offsets PARAMS ((void));
393 static void set_offsets_for_label PARAMS ((rtx));
394 static void init_elim_table PARAMS ((void));
395 static void update_eliminables PARAMS ((HARD_REG_SET *));
396 static void spill_hard_reg PARAMS ((unsigned int, FILE *, int));
397 static int finish_spills PARAMS ((int, FILE *));
398 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
399 static void scan_paradoxical_subregs PARAMS ((rtx));
400 static void count_pseudo PARAMS ((int));
401 static void order_regs_for_reload PARAMS ((struct insn_chain *));
402 static void reload_as_needed PARAMS ((int));
403 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
404 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
405 static void mark_reload_reg_in_use PARAMS ((unsigned int, int,
408 static void clear_reload_reg_in_use PARAMS ((unsigned int, int,
411 static int reload_reg_free_p PARAMS ((unsigned int, int,
413 static int reload_reg_free_for_value_p PARAMS ((int, int, enum reload_type,
414 rtx, rtx, int, int));
415 static int reload_reg_reaches_end_p PARAMS ((unsigned int, int,
417 static int allocate_reload_reg PARAMS ((struct insn_chain *, int,
419 static void failed_reload PARAMS ((rtx, int));
420 static int set_reload_reg PARAMS ((int, int));
421 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
422 static void choose_reload_regs PARAMS ((struct insn_chain *));
423 static void merge_assigned_reloads PARAMS ((rtx));
424 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
425 struct reload *, rtx, int));
426 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
427 struct reload *, int));
428 static void do_input_reload PARAMS ((struct insn_chain *,
429 struct reload *, int));
430 static void do_output_reload PARAMS ((struct insn_chain *,
431 struct reload *, int));
432 static void emit_reload_insns PARAMS ((struct insn_chain *));
433 static void delete_output_reload PARAMS ((rtx, int, int));
434 static void delete_address_reloads PARAMS ((rtx, rtx));
435 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
436 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
437 static int constraint_accepts_reg_p PARAMS ((const char *, rtx));
438 static void reload_cse_regs_1 PARAMS ((rtx));
439 static int reload_cse_noop_set_p PARAMS ((rtx));
440 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
441 static int reload_cse_simplify_operands PARAMS ((rtx));
442 static void reload_combine PARAMS ((void));
443 static void reload_combine_note_use PARAMS ((rtx *, rtx));
444 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
445 static void reload_cse_move2add PARAMS ((rtx));
446 static void move2add_note_store PARAMS ((rtx, rtx, void *));
448 static void add_auto_inc_notes PARAMS ((rtx, rtx));
450 static rtx gen_mode_int PARAMS ((enum machine_mode,
452 static void failed_reload PARAMS ((rtx, int));
453 static int set_reload_reg PARAMS ((int, int));
454 static void reload_cse_delete_noop_set PARAMS ((rtx, rtx));
455 static void reload_cse_simplify PARAMS ((rtx));
456 extern void dump_needs PARAMS ((struct insn_chain *, FILE *));
458 /* Initialize the reload pass once per compilation. */
465 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
466 Set spill_indirect_levels to the number of levels such addressing is
467 permitted, zero if it is not permitted at all. */
470 = gen_rtx_MEM (Pmode,
473 LAST_VIRTUAL_REGISTER + 1),
475 spill_indirect_levels = 0;
477 while (memory_address_p (QImode, tem))
479 spill_indirect_levels++;
480 tem = gen_rtx_MEM (Pmode, tem);
483 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
485 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
486 indirect_symref_ok = memory_address_p (QImode, tem);
488 /* See if reg+reg is a valid (and offsettable) address. */
490 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
492 tem = gen_rtx_PLUS (Pmode,
493 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
494 gen_rtx_REG (Pmode, i));
496 /* This way, we make sure that reg+reg is an offsettable address. */
497 tem = plus_constant (tem, 4);
499 if (memory_address_p (QImode, tem))
501 double_reg_address_ok = 1;
506 /* Initialize obstack for our rtl allocation. */
507 gcc_obstack_init (&reload_obstack);
508 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
510 INIT_REG_SET (&spilled_pseudos);
511 INIT_REG_SET (&pseudos_counted);
514 /* List of insn chains that are currently unused. */
515 static struct insn_chain *unused_insn_chains = 0;
517 /* Allocate an empty insn_chain structure. */
521 struct insn_chain *c;
523 if (unused_insn_chains == 0)
525 c = (struct insn_chain *)
526 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
527 INIT_REG_SET (&c->live_throughout);
528 INIT_REG_SET (&c->dead_or_set);
532 c = unused_insn_chains;
533 unused_insn_chains = c->next;
535 c->is_caller_save_insn = 0;
536 c->need_operand_change = 0;
542 /* Small utility function to set all regs in hard reg set TO which are
543 allocated to pseudos in regset FROM. */
546 compute_use_by_pseudos (to, from)
552 EXECUTE_IF_SET_IN_REG_SET
553 (from, FIRST_PSEUDO_REGISTER, regno,
555 int r = reg_renumber[regno];
560 /* reload_combine uses the information from
561 BASIC_BLOCK->global_live_at_start, which might still
562 contain registers that have not actually been allocated
563 since they have an equivalence. */
564 if (! reload_completed)
569 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
571 SET_HARD_REG_BIT (*to, r + nregs);
576 /* Global variables used by reload and its subroutines. */
578 /* Set during calculate_needs if an insn needs register elimination. */
579 static int something_needs_elimination;
580 /* Set during calculate_needs if an insn needs an operand changed. */
581 int something_needs_operands_changed;
583 /* Nonzero means we couldn't get enough spill regs. */
586 /* Main entry point for the reload pass.
588 FIRST is the first insn of the function being compiled.
590 GLOBAL nonzero means we were called from global_alloc
591 and should attempt to reallocate any pseudoregs that we
592 displace from hard regs we will use for reloads.
593 If GLOBAL is zero, we do not have enough information to do that,
594 so any pseudo reg that is spilled must go to the stack.
596 DUMPFILE is the global-reg debugging dump file stream, or 0.
597 If it is nonzero, messages are written to it to describe
598 which registers are seized as reload regs, which pseudo regs
599 are spilled from them, and where the pseudo regs are reallocated to.
601 Return value is nonzero if reload failed
602 and we must not do any more for this function. */
605 reload (first, global, dumpfile)
612 register struct elim_table *ep;
614 /* The two pointers used to track the true location of the memory used
615 for label offsets. */
616 char *real_known_ptr = NULL_PTR;
617 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
619 /* Make sure even insns with volatile mem refs are recognizable. */
624 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
626 /* Make sure that the last insn in the chain
627 is not something that needs reloading. */
628 emit_note (NULL_PTR, NOTE_INSN_DELETED);
630 /* Enable find_equiv_reg to distinguish insns made by reload. */
631 reload_first_uid = get_max_uid ();
633 #ifdef SECONDARY_MEMORY_NEEDED
634 /* Initialize the secondary memory table. */
635 clear_secondary_mem ();
638 /* We don't have a stack slot for any spill reg yet. */
639 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
640 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
642 /* Initialize the save area information for caller-save, in case some
646 /* Compute which hard registers are now in use
647 as homes for pseudo registers.
648 This is done here rather than (eg) in global_alloc
649 because this point is reached even if not optimizing. */
650 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
653 /* A function that receives a nonlocal goto must save all call-saved
655 if (current_function_has_nonlocal_label)
656 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
658 if (! call_used_regs[i] && ! fixed_regs[i])
659 regs_ever_live[i] = 1;
662 /* Find all the pseudo registers that didn't get hard regs
663 but do have known equivalent constants or memory slots.
664 These include parameters (known equivalent to parameter slots)
665 and cse'd or loop-moved constant memory addresses.
667 Record constant equivalents in reg_equiv_constant
668 so they will be substituted by find_reloads.
669 Record memory equivalents in reg_mem_equiv so they can
670 be substituted eventually by altering the REG-rtx's. */
672 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
673 reg_equiv_memory_loc = (rtx *) xcalloc (max_regno, sizeof (rtx));
674 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
675 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
676 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
677 reg_max_ref_width = (int *) xcalloc (max_regno, sizeof (int));
678 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
679 bcopy ((PTR) reg_renumber, (PTR) reg_old_renumber, max_regno * sizeof (short));
680 pseudo_forbidden_regs
681 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
683 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
685 CLEAR_HARD_REG_SET (bad_spill_regs_global);
687 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
688 Also find all paradoxical subregs and find largest such for each pseudo.
689 On machines with small register classes, record hard registers that
690 are used for user variables. These can never be used for spills.
691 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
692 caller-saved registers must be marked live. */
694 num_eliminable_invariants = 0;
695 for (insn = first; insn; insn = NEXT_INSN (insn))
697 rtx set = single_set (insn);
699 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
700 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
701 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
702 if (! call_used_regs[i])
703 regs_ever_live[i] = 1;
705 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
707 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
709 #ifdef LEGITIMATE_PIC_OPERAND_P
710 && (! function_invariant_p (XEXP (note, 0))
712 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
716 rtx x = XEXP (note, 0);
717 i = REGNO (SET_DEST (set));
718 if (i > LAST_VIRTUAL_REGISTER)
720 if (GET_CODE (x) == MEM)
722 /* If the operand is a PLUS, the MEM may be shared,
723 so make sure we have an unshared copy here. */
724 if (GET_CODE (XEXP (x, 0)) == PLUS)
727 reg_equiv_memory_loc[i] = x;
729 else if (function_invariant_p (x))
731 if (GET_CODE (x) == PLUS)
733 /* This is PLUS of frame pointer and a constant,
734 and might be shared. Unshare it. */
735 reg_equiv_constant[i] = copy_rtx (x);
736 num_eliminable_invariants++;
738 else if (x == frame_pointer_rtx
739 || x == arg_pointer_rtx)
741 reg_equiv_constant[i] = x;
742 num_eliminable_invariants++;
744 else if (LEGITIMATE_CONSTANT_P (x))
745 reg_equiv_constant[i] = x;
747 reg_equiv_memory_loc[i]
748 = force_const_mem (GET_MODE (SET_DEST (set)), x);
753 /* If this register is being made equivalent to a MEM
754 and the MEM is not SET_SRC, the equivalencing insn
755 is one with the MEM as a SET_DEST and it occurs later.
756 So don't mark this insn now. */
757 if (GET_CODE (x) != MEM
758 || rtx_equal_p (SET_SRC (set), x))
760 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
765 /* If this insn is setting a MEM from a register equivalent to it,
766 this is the equivalencing insn. */
767 else if (set && GET_CODE (SET_DEST (set)) == MEM
768 && GET_CODE (SET_SRC (set)) == REG
769 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
770 && rtx_equal_p (SET_DEST (set),
771 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
772 reg_equiv_init[REGNO (SET_SRC (set))]
773 = gen_rtx_INSN_LIST (VOIDmode, insn,
774 reg_equiv_init[REGNO (SET_SRC (set))]);
776 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
777 scan_paradoxical_subregs (PATTERN (insn));
782 num_labels = max_label_num () - get_first_label_num ();
784 /* Allocate the tables used to store offset information at labels. */
785 /* We used to use alloca here, but the size of what it would try to
786 allocate would occasionally cause it to exceed the stack limit and
787 cause a core dump. */
788 real_known_ptr = xmalloc (num_labels);
790 = (int (*)[NUM_ELIMINABLE_REGS])
791 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
793 offsets_known_at = real_known_ptr - get_first_label_num ();
795 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
797 /* Alter each pseudo-reg rtx to contain its hard reg number.
798 Assign stack slots to the pseudos that lack hard regs or equivalents.
799 Do not touch virtual registers. */
801 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
804 /* If we have some registers we think can be eliminated, scan all insns to
805 see if there is an insn that sets one of these registers to something
806 other than itself plus a constant. If so, the register cannot be
807 eliminated. Doing this scan here eliminates an extra pass through the
808 main reload loop in the most common case where register elimination
810 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
811 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
812 || GET_CODE (insn) == CALL_INSN)
813 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
815 maybe_fix_stack_asms ();
817 insns_need_reload = 0;
818 something_needs_elimination = 0;
820 /* Initialize to -1, which means take the first spill register. */
823 /* Spill any hard regs that we know we can't eliminate. */
824 CLEAR_HARD_REG_SET (used_spill_regs);
825 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
826 if (! ep->can_eliminate)
827 spill_hard_reg (ep->from, dumpfile, 1);
829 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
830 if (frame_pointer_needed)
831 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, dumpfile, 1);
833 finish_spills (global, dumpfile);
835 /* From now on, we may need to generate moves differently. We may also
836 allow modifications of insns which cause them to not be recognized.
837 Any such modifications will be cleaned up during reload itself. */
838 reload_in_progress = 1;
840 /* This loop scans the entire function each go-round
841 and repeats until one repetition spills no additional hard regs. */
844 int something_changed;
847 HOST_WIDE_INT starting_frame_size;
849 /* Round size of stack frame to stack_alignment_needed. This must be done
850 here because the stack size may be a part of the offset computation
851 for register elimination, and there might have been new stack slots
852 created in the last iteration of this loop. */
853 if (cfun->stack_alignment_needed)
854 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
856 starting_frame_size = get_frame_size ();
858 set_initial_elim_offsets ();
859 set_initial_label_offsets ();
861 /* For each pseudo register that has an equivalent location defined,
862 try to eliminate any eliminable registers (such as the frame pointer)
863 assuming initial offsets for the replacement register, which
866 If the resulting location is directly addressable, substitute
867 the MEM we just got directly for the old REG.
869 If it is not addressable but is a constant or the sum of a hard reg
870 and constant, it is probably not addressable because the constant is
871 out of range, in that case record the address; we will generate
872 hairy code to compute the address in a register each time it is
873 needed. Similarly if it is a hard register, but one that is not
874 valid as an address register.
876 If the location is not addressable, but does not have one of the
877 above forms, assign a stack slot. We have to do this to avoid the
878 potential of producing lots of reloads if, e.g., a location involves
879 a pseudo that didn't get a hard register and has an equivalent memory
880 location that also involves a pseudo that didn't get a hard register.
882 Perhaps at some point we will improve reload_when_needed handling
883 so this problem goes away. But that's very hairy. */
885 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
886 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
888 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
890 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
892 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
893 else if (CONSTANT_P (XEXP (x, 0))
894 || (GET_CODE (XEXP (x, 0)) == REG
895 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
896 || (GET_CODE (XEXP (x, 0)) == PLUS
897 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
898 && (REGNO (XEXP (XEXP (x, 0), 0))
899 < FIRST_PSEUDO_REGISTER)
900 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
901 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
904 /* Make a new stack slot. Then indicate that something
905 changed so we go back and recompute offsets for
906 eliminable registers because the allocation of memory
907 below might change some offset. reg_equiv_{mem,address}
908 will be set up for this pseudo on the next pass around
910 reg_equiv_memory_loc[i] = 0;
911 reg_equiv_init[i] = 0;
916 if (caller_save_needed)
919 /* If we allocated another stack slot, redo elimination bookkeeping. */
920 if (starting_frame_size != get_frame_size ())
923 if (caller_save_needed)
925 save_call_clobbered_regs ();
926 /* That might have allocated new insn_chain structures. */
927 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
930 calculate_needs_all_insns (global);
932 CLEAR_REG_SET (&spilled_pseudos);
935 something_changed = 0;
937 /* If we allocated any new memory locations, make another pass
938 since it might have changed elimination offsets. */
939 if (starting_frame_size != get_frame_size ())
940 something_changed = 1;
943 HARD_REG_SET to_spill;
944 CLEAR_HARD_REG_SET (to_spill);
945 update_eliminables (&to_spill);
946 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
947 if (TEST_HARD_REG_BIT (to_spill, i))
949 spill_hard_reg (i, dumpfile, 1);
952 /* Regardless of the state of spills, if we previously had
953 a register that we thought we could eliminate, but no can
954 not eliminate, we must run another pass.
956 Consider pseudos which have an entry in reg_equiv_* which
957 reference an eliminable register. We must make another pass
958 to update reg_equiv_* so that we do not substitute in the
959 old value from when we thought the elimination could be
961 something_changed = 1;
965 select_reload_regs (dumpfile);
969 if (insns_need_reload != 0 || did_spill)
970 something_changed |= finish_spills (global, dumpfile);
972 if (! something_changed)
975 if (caller_save_needed)
976 delete_caller_save_insns ();
978 obstack_free (&reload_obstack, reload_firstobj);
981 /* If global-alloc was run, notify it of any register eliminations we have
984 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
985 if (ep->can_eliminate)
986 mark_elimination (ep->from, ep->to);
988 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
989 If that insn didn't set the register (i.e., it copied the register to
990 memory), just delete that insn instead of the equivalencing insn plus
991 anything now dead. If we call delete_dead_insn on that insn, we may
992 delete the insn that actually sets the register if the register dies
993 there and that is incorrect. */
995 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
997 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1000 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1002 rtx equiv_insn = XEXP (list, 0);
1003 if (GET_CODE (equiv_insn) == NOTE)
1005 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1006 delete_dead_insn (equiv_insn);
1009 PUT_CODE (equiv_insn, NOTE);
1010 NOTE_SOURCE_FILE (equiv_insn) = 0;
1011 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1017 /* Use the reload registers where necessary
1018 by generating move instructions to move the must-be-register
1019 values into or out of the reload registers. */
1021 if (insns_need_reload != 0 || something_needs_elimination
1022 || something_needs_operands_changed)
1024 int old_frame_size = get_frame_size ();
1026 reload_as_needed (global);
1028 if (old_frame_size != get_frame_size ())
1032 verify_initial_elim_offsets ();
1035 /* If we were able to eliminate the frame pointer, show that it is no
1036 longer live at the start of any basic block. If it ls live by
1037 virtue of being in a pseudo, that pseudo will be marked live
1038 and hence the frame pointer will be known to be live via that
1041 if (! frame_pointer_needed)
1042 for (i = 0; i < n_basic_blocks; i++)
1043 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
1044 HARD_FRAME_POINTER_REGNUM);
1046 /* Come here (with failure set nonzero) if we can't get enough spill regs
1047 and we decide not to abort about it. */
1050 CLEAR_REG_SET (&spilled_pseudos);
1051 reload_in_progress = 0;
1053 /* Now eliminate all pseudo regs by modifying them into
1054 their equivalent memory references.
1055 The REG-rtx's for the pseudos are modified in place,
1056 so all insns that used to refer to them now refer to memory.
1058 For a reg that has a reg_equiv_address, all those insns
1059 were changed by reloading so that no insns refer to it any longer;
1060 but the DECL_RTL of a variable decl may refer to it,
1061 and if so this causes the debugging info to mention the variable. */
1063 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1068 int is_readonly = 0;
1070 if (reg_equiv_memory_loc[i])
1072 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1073 is_scalar = MEM_SCALAR_P (reg_equiv_memory_loc[i]);
1074 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1077 if (reg_equiv_mem[i])
1078 addr = XEXP (reg_equiv_mem[i], 0);
1080 if (reg_equiv_address[i])
1081 addr = reg_equiv_address[i];
1085 if (reg_renumber[i] < 0)
1087 rtx reg = regno_reg_rtx[i];
1088 PUT_CODE (reg, MEM);
1089 XEXP (reg, 0) = addr;
1090 REG_USERVAR_P (reg) = 0;
1091 RTX_UNCHANGING_P (reg) = is_readonly;
1092 MEM_IN_STRUCT_P (reg) = in_struct;
1093 MEM_SCALAR_P (reg) = is_scalar;
1094 /* We have no alias information about this newly created
1096 MEM_ALIAS_SET (reg) = 0;
1098 else if (reg_equiv_mem[i])
1099 XEXP (reg_equiv_mem[i], 0) = addr;
1103 /* We must set reload_completed now since the cleanup_subreg_operands call
1104 below will re-recognize each insn and reload may have generated insns
1105 which are only valid during and after reload. */
1106 reload_completed = 1;
1108 /* Make a pass over all the insns and delete all USEs which we inserted
1109 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1110 notes. Delete all CLOBBER insns that don't refer to the return value
1111 and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1112 REG_LIBCALL notes since they are no longer useful or accurate. Strip
1113 and regenerate REG_INC notes that may have been moved around. */
1115 for (insn = first; insn; insn = NEXT_INSN (insn))
1116 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1120 if ((GET_CODE (PATTERN (insn)) == USE
1121 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1122 || (GET_CODE (PATTERN (insn)) == CLOBBER
1123 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1124 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1126 PUT_CODE (insn, NOTE);
1127 NOTE_SOURCE_FILE (insn) = 0;
1128 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1132 pnote = ®_NOTES (insn);
1135 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1136 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1137 || REG_NOTE_KIND (*pnote) == REG_INC
1138 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1139 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1140 *pnote = XEXP (*pnote, 1);
1142 pnote = &XEXP (*pnote, 1);
1146 add_auto_inc_notes (insn, PATTERN (insn));
1149 /* And simplify (subreg (reg)) if it appears as an operand. */
1150 cleanup_subreg_operands (insn);
1153 /* If we are doing stack checking, give a warning if this function's
1154 frame size is larger than we expect. */
1155 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1157 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1158 static int verbose_warned = 0;
1160 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1161 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1162 size += UNITS_PER_WORD;
1164 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1166 warning ("frame size too large for reliable stack checking");
1167 if (! verbose_warned)
1169 warning ("try reducing the number of local variables");
1175 /* Indicate that we no longer have known memory locations or constants. */
1176 if (reg_equiv_constant)
1177 free (reg_equiv_constant);
1178 reg_equiv_constant = 0;
1179 if (reg_equiv_memory_loc)
1180 free (reg_equiv_memory_loc);
1181 reg_equiv_memory_loc = 0;
1184 free (real_known_ptr);
1188 free (reg_equiv_mem);
1189 free (reg_equiv_init);
1190 free (reg_equiv_address);
1191 free (reg_max_ref_width);
1192 free (reg_old_renumber);
1193 free (pseudo_previous_regs);
1194 free (pseudo_forbidden_regs);
1196 CLEAR_HARD_REG_SET (used_spill_regs);
1197 for (i = 0; i < n_spills; i++)
1198 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1200 /* Free all the insn_chain structures at once. */
1201 obstack_free (&reload_obstack, reload_startobj);
1202 unused_insn_chains = 0;
1207 /* Yet another special case. Unfortunately, reg-stack forces people to
1208 write incorrect clobbers in asm statements. These clobbers must not
1209 cause the register to appear in bad_spill_regs, otherwise we'll call
1210 fatal_insn later. We clear the corresponding regnos in the live
1211 register sets to avoid this.
1212 The whole thing is rather sick, I'm afraid. */
1214 maybe_fix_stack_asms ()
1217 const char *constraints[MAX_RECOG_OPERANDS];
1218 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1219 struct insn_chain *chain;
1221 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1224 HARD_REG_SET clobbered, allowed;
1227 if (GET_RTX_CLASS (GET_CODE (chain->insn)) != 'i'
1228 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1230 pat = PATTERN (chain->insn);
1231 if (GET_CODE (pat) != PARALLEL)
1234 CLEAR_HARD_REG_SET (clobbered);
1235 CLEAR_HARD_REG_SET (allowed);
1237 /* First, make a mask of all stack regs that are clobbered. */
1238 for (i = 0; i < XVECLEN (pat, 0); i++)
1240 rtx t = XVECEXP (pat, 0, i);
1241 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1242 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1245 /* Get the operand values and constraints out of the insn. */
1246 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1247 constraints, operand_mode);
1249 /* For every operand, see what registers are allowed. */
1250 for (i = 0; i < noperands; i++)
1252 const char *p = constraints[i];
1253 /* For every alternative, we compute the class of registers allowed
1254 for reloading in CLS, and merge its contents into the reg set
1256 int cls = (int) NO_REGS;
1262 if (c == '\0' || c == ',' || c == '#')
1264 /* End of one alternative - mark the regs in the current
1265 class, and reset the class. */
1266 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1271 } while (c != '\0' && c != ',');
1279 case '=': case '+': case '*': case '%': case '?': case '!':
1280 case '0': case '1': case '2': case '3': case '4': case 'm':
1281 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1282 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1283 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1285 #ifdef EXTRA_CONSTRAINT
1286 case 'Q': case 'R': case 'S': case 'T': case 'U':
1291 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1296 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1300 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1305 /* Those of the registers which are clobbered, but allowed by the
1306 constraints, must be usable as reload registers. So clear them
1307 out of the life information. */
1308 AND_HARD_REG_SET (allowed, clobbered);
1309 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1310 if (TEST_HARD_REG_BIT (allowed, i))
1312 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1313 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1320 /* Copy the global variables n_reloads and rld into the corresponding elts
1323 copy_reloads (chain)
1324 struct insn_chain *chain;
1326 chain->n_reloads = n_reloads;
1328 = (struct reload *) obstack_alloc (&reload_obstack,
1329 n_reloads * sizeof (struct reload));
1330 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1331 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1334 /* Walk the chain of insns, and determine for each whether it needs reloads
1335 and/or eliminations. Build the corresponding insns_need_reload list, and
1336 set something_needs_elimination as appropriate. */
1338 calculate_needs_all_insns (global)
1341 struct insn_chain **pprev_reload = &insns_need_reload;
1342 struct insn_chain *chain;
1344 something_needs_elimination = 0;
1346 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1347 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1349 rtx insn = chain->insn;
1351 /* Clear out the shortcuts. */
1352 chain->n_reloads = 0;
1353 chain->need_elim = 0;
1354 chain->need_reload = 0;
1355 chain->need_operand_change = 0;
1357 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1358 include REG_LABEL), we need to see what effects this has on the
1359 known offsets at labels. */
1361 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1362 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1363 && REG_NOTES (insn) != 0))
1364 set_label_offsets (insn, insn, 0);
1366 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1368 rtx old_body = PATTERN (insn);
1369 int old_code = INSN_CODE (insn);
1370 rtx old_notes = REG_NOTES (insn);
1371 int did_elimination = 0;
1372 int operands_changed = 0;
1373 rtx set = single_set (insn);
1375 /* Skip insns that only set an equivalence. */
1376 if (set && GET_CODE (SET_DEST (set)) == REG
1377 && reg_renumber[REGNO (SET_DEST (set))] < 0
1378 && reg_equiv_constant[REGNO (SET_DEST (set))])
1381 /* If needed, eliminate any eliminable registers. */
1382 if (num_eliminable || num_eliminable_invariants)
1383 did_elimination = eliminate_regs_in_insn (insn, 0);
1385 /* Analyze the instruction. */
1386 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1387 global, spill_reg_order);
1389 /* If a no-op set needs more than one reload, this is likely
1390 to be something that needs input address reloads. We
1391 can't get rid of this cleanly later, and it is of no use
1392 anyway, so discard it now.
1393 We only do this when expensive_optimizations is enabled,
1394 since this complements reload inheritance / output
1395 reload deletion, and it can make debugging harder. */
1396 if (flag_expensive_optimizations && n_reloads > 1)
1398 rtx set = single_set (insn);
1400 && SET_SRC (set) == SET_DEST (set)
1401 && GET_CODE (SET_SRC (set)) == REG
1402 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1404 PUT_CODE (insn, NOTE);
1405 NOTE_SOURCE_FILE (insn) = 0;
1406 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1411 update_eliminable_offsets ();
1413 /* Remember for later shortcuts which insns had any reloads or
1414 register eliminations. */
1415 chain->need_elim = did_elimination;
1416 chain->need_reload = n_reloads > 0;
1417 chain->need_operand_change = operands_changed;
1419 /* Discard any register replacements done. */
1420 if (did_elimination)
1422 obstack_free (&reload_obstack, reload_insn_firstobj);
1423 PATTERN (insn) = old_body;
1424 INSN_CODE (insn) = old_code;
1425 REG_NOTES (insn) = old_notes;
1426 something_needs_elimination = 1;
1429 something_needs_operands_changed |= operands_changed;
1433 copy_reloads (chain);
1434 *pprev_reload = chain;
1435 pprev_reload = &chain->next_need_reload;
1442 /* Comparison function for qsort to decide which of two reloads
1443 should be handled first. *P1 and *P2 are the reload numbers. */
1446 reload_reg_class_lower (r1p, r2p)
1450 register int r1 = *(const short *)r1p, r2 = *(const short *)r2p;
1453 /* Consider required reloads before optional ones. */
1454 t = rld[r1].optional - rld[r2].optional;
1458 /* Count all solitary classes before non-solitary ones. */
1459 t = ((reg_class_size[(int) rld[r2].class] == 1)
1460 - (reg_class_size[(int) rld[r1].class] == 1));
1464 /* Aside from solitaires, consider all multi-reg groups first. */
1465 t = rld[r2].nregs - rld[r1].nregs;
1469 /* Consider reloads in order of increasing reg-class number. */
1470 t = (int) rld[r1].class - (int) rld[r2].class;
1474 /* If reloads are equally urgent, sort by reload number,
1475 so that the results of qsort leave nothing to chance. */
1479 /* The cost of spilling each hard reg. */
1480 static int spill_cost[FIRST_PSEUDO_REGISTER];
1482 /* When spilling multiple hard registers, we use SPILL_COST for the first
1483 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1484 only the first hard reg for a multi-reg pseudo. */
1485 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1487 /* Update the spill cost arrays, considering that pseudo REG is live. */
1493 int n_refs = REG_N_REFS (reg);
1494 int r = reg_renumber[reg];
1497 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1498 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1501 SET_REGNO_REG_SET (&pseudos_counted, reg);
1506 spill_add_cost[r] += n_refs;
1508 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1510 spill_cost[r + nregs] += n_refs;
1513 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1514 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1516 order_regs_for_reload (chain)
1517 struct insn_chain *chain;
1521 COPY_HARD_REG_SET (bad_spill_regs, bad_spill_regs_global);
1523 memset (spill_cost, 0, sizeof spill_cost);
1524 memset (spill_add_cost, 0, sizeof spill_add_cost);
1526 /* Count number of uses of each hard reg by pseudo regs allocated to it
1527 and then order them by decreasing use. */
1529 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1531 /* Test the various reasons why we can't use a register for
1532 spilling in this insn. */
1534 || REGNO_REG_SET_P (&chain->live_throughout, i)
1535 || REGNO_REG_SET_P (&chain->dead_or_set, i))
1536 SET_HARD_REG_BIT (bad_spill_regs, i);
1538 /* Now find out which pseudos are allocated to it, and update
1540 CLEAR_REG_SET (&pseudos_counted);
1542 EXECUTE_IF_SET_IN_REG_SET
1543 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1547 EXECUTE_IF_SET_IN_REG_SET
1548 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1552 CLEAR_REG_SET (&pseudos_counted);
1555 /* Vector of reload-numbers showing the order in which the reloads should
1557 static short reload_order[MAX_RELOADS];
1559 /* This is used to keep track of the spill regs used in one insn. */
1560 static HARD_REG_SET used_spill_regs_local;
1562 /* We decided to spill hard register SPILLED, which has a size of
1563 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1564 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1565 update SPILL_COST/SPILL_ADD_COST. */
1568 count_spilled_pseudo (spilled, spilled_nregs, reg)
1569 int spilled, spilled_nregs, reg;
1571 int r = reg_renumber[reg];
1572 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1574 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1575 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1578 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1580 spill_add_cost[r] -= REG_N_REFS (reg);
1582 spill_cost[r + nregs] -= REG_N_REFS (reg);
1585 /* Find reload register to use for reload number ORDER. */
1588 find_reg (chain, order, dumpfile)
1589 struct insn_chain *chain;
1593 int rnum = reload_order[order];
1594 struct reload *rl = rld + rnum;
1595 int best_cost = INT_MAX;
1599 HARD_REG_SET not_usable;
1600 HARD_REG_SET used_by_other_reload;
1602 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1603 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1604 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1606 CLEAR_HARD_REG_SET (used_by_other_reload);
1607 for (k = 0; k < order; k++)
1609 int other = reload_order[k];
1611 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1612 for (j = 0; j < rld[other].nregs; j++)
1613 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1616 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1618 unsigned int regno = i;
1620 if (! TEST_HARD_REG_BIT (not_usable, regno)
1621 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1622 && HARD_REGNO_MODE_OK (regno, rl->mode))
1624 int this_cost = spill_cost[regno];
1626 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1628 for (j = 1; j < this_nregs; j++)
1630 this_cost += spill_add_cost[regno + j];
1631 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1632 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1637 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1639 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1641 if (this_cost < best_cost
1642 /* Among registers with equal cost, prefer caller-saved ones, or
1643 use REG_ALLOC_ORDER if it is defined. */
1644 || (this_cost == best_cost
1645 #ifdef REG_ALLOC_ORDER
1646 && (inv_reg_alloc_order[regno]
1647 < inv_reg_alloc_order[best_reg])
1649 && call_used_regs[regno]
1650 && ! call_used_regs[best_reg]
1655 best_cost = this_cost;
1663 fprintf (dumpfile, "Using reg %d for reload %d\n", best_reg, rnum);
1665 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1666 rl->regno = best_reg;
1668 EXECUTE_IF_SET_IN_REG_SET
1669 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1671 count_spilled_pseudo (best_reg, rl->nregs, j);
1674 EXECUTE_IF_SET_IN_REG_SET
1675 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1677 count_spilled_pseudo (best_reg, rl->nregs, j);
1680 for (i = 0; i < rl->nregs; i++)
1682 if (spill_cost[best_reg + i] != 0
1683 || spill_add_cost[best_reg + i] != 0)
1685 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1690 /* Find more reload regs to satisfy the remaining need of an insn, which
1692 Do it by ascending class number, since otherwise a reg
1693 might be spilled for a big class and might fail to count
1694 for a smaller class even though it belongs to that class. */
1697 find_reload_regs (chain, dumpfile)
1698 struct insn_chain *chain;
1703 /* In order to be certain of getting the registers we need,
1704 we must sort the reloads into order of increasing register class.
1705 Then our grabbing of reload registers will parallel the process
1706 that provided the reload registers. */
1707 for (i = 0; i < chain->n_reloads; i++)
1709 /* Show whether this reload already has a hard reg. */
1710 if (chain->rld[i].reg_rtx)
1712 int regno = REGNO (chain->rld[i].reg_rtx);
1713 chain->rld[i].regno = regno;
1715 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1718 chain->rld[i].regno = -1;
1719 reload_order[i] = i;
1722 n_reloads = chain->n_reloads;
1723 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1725 CLEAR_HARD_REG_SET (used_spill_regs_local);
1728 fprintf (dumpfile, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1730 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1732 /* Compute the order of preference for hard registers to spill. */
1734 order_regs_for_reload (chain);
1736 for (i = 0; i < n_reloads; i++)
1738 int r = reload_order[i];
1740 /* Ignore reloads that got marked inoperative. */
1741 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1742 && ! rld[r].optional
1743 && rld[r].regno == -1)
1744 if (! find_reg (chain, i, dumpfile))
1746 spill_failure (chain->insn, rld[r].class);
1752 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1753 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1755 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1759 select_reload_regs (dumpfile)
1762 struct insn_chain *chain;
1764 /* Try to satisfy the needs for each insn. */
1765 for (chain = insns_need_reload; chain != 0;
1766 chain = chain->next_need_reload)
1767 find_reload_regs (chain, dumpfile);
1770 /* Delete all insns that were inserted by emit_caller_save_insns during
1773 delete_caller_save_insns ()
1775 struct insn_chain *c = reload_insn_chain;
1779 while (c != 0 && c->is_caller_save_insn)
1781 struct insn_chain *next = c->next;
1784 if (insn == BLOCK_HEAD (c->block))
1785 BLOCK_HEAD (c->block) = NEXT_INSN (insn);
1786 if (insn == BLOCK_END (c->block))
1787 BLOCK_END (c->block) = PREV_INSN (insn);
1788 if (c == reload_insn_chain)
1789 reload_insn_chain = next;
1791 if (NEXT_INSN (insn) != 0)
1792 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
1793 if (PREV_INSN (insn) != 0)
1794 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
1797 next->prev = c->prev;
1799 c->prev->next = next;
1800 c->next = unused_insn_chains;
1801 unused_insn_chains = c;
1809 /* Handle the failure to find a register to spill.
1810 INSN should be one of the insns which needed this particular spill reg. */
1813 spill_failure (insn, class)
1815 enum reg_class class;
1817 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1818 if (asm_noperands (PATTERN (insn)) >= 0)
1819 error_for_asm (insn, "Can't find a register in class `%s' while reloading `asm'.",
1820 reg_class_names[class]);
1823 error ("Unable to find a register to spill in class `%s'.",
1824 reg_class_names[class]);
1825 fatal_insn ("This is the insn:", insn);
1829 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1830 data that is dead in INSN. */
1833 delete_dead_insn (insn)
1836 rtx prev = prev_real_insn (insn);
1839 /* If the previous insn sets a register that dies in our insn, delete it
1841 if (prev && GET_CODE (PATTERN (prev)) == SET
1842 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1843 && reg_mentioned_p (prev_dest, PATTERN (insn))
1844 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1845 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1846 delete_dead_insn (prev);
1848 PUT_CODE (insn, NOTE);
1849 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1850 NOTE_SOURCE_FILE (insn) = 0;
1853 /* Modify the home of pseudo-reg I.
1854 The new home is present in reg_renumber[I].
1856 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1857 or it may be -1, meaning there is none or it is not relevant.
1858 This is used so that all pseudos spilled from a given hard reg
1859 can share one stack slot. */
1862 alter_reg (i, from_reg)
1866 /* When outputting an inline function, this can happen
1867 for a reg that isn't actually used. */
1868 if (regno_reg_rtx[i] == 0)
1871 /* If the reg got changed to a MEM at rtl-generation time,
1873 if (GET_CODE (regno_reg_rtx[i]) != REG)
1876 /* Modify the reg-rtx to contain the new hard reg
1877 number or else to contain its pseudo reg number. */
1878 REGNO (regno_reg_rtx[i])
1879 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1881 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1882 allocate a stack slot for it. */
1884 if (reg_renumber[i] < 0
1885 && REG_N_REFS (i) > 0
1886 && reg_equiv_constant[i] == 0
1887 && reg_equiv_memory_loc[i] == 0)
1890 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1891 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1894 /* Each pseudo reg has an inherent size which comes from its own mode,
1895 and a total size which provides room for paradoxical subregs
1896 which refer to the pseudo reg in wider modes.
1898 We can use a slot already allocated if it provides both
1899 enough inherent space and enough total space.
1900 Otherwise, we allocate a new slot, making sure that it has no less
1901 inherent space, and no less total space, then the previous slot. */
1904 /* No known place to spill from => no slot to reuse. */
1905 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1906 inherent_size == total_size ? 0 : -1);
1907 if (BYTES_BIG_ENDIAN)
1908 /* Cancel the big-endian correction done in assign_stack_local.
1909 Get the address of the beginning of the slot.
1910 This is so we can do a big-endian correction unconditionally
1912 adjust = inherent_size - total_size;
1914 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1916 /* Reuse a stack slot if possible. */
1917 else if (spill_stack_slot[from_reg] != 0
1918 && spill_stack_slot_width[from_reg] >= total_size
1919 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1921 x = spill_stack_slot[from_reg];
1922 /* Allocate a bigger slot. */
1925 /* Compute maximum size needed, both for inherent size
1926 and for total size. */
1927 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1929 if (spill_stack_slot[from_reg])
1931 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1933 mode = GET_MODE (spill_stack_slot[from_reg]);
1934 if (spill_stack_slot_width[from_reg] > total_size)
1935 total_size = spill_stack_slot_width[from_reg];
1937 /* Make a slot with that size. */
1938 x = assign_stack_local (mode, total_size,
1939 inherent_size == total_size ? 0 : -1);
1941 if (BYTES_BIG_ENDIAN)
1943 /* Cancel the big-endian correction done in assign_stack_local.
1944 Get the address of the beginning of the slot.
1945 This is so we can do a big-endian correction unconditionally
1947 adjust = GET_MODE_SIZE (mode) - total_size;
1949 stack_slot = gen_rtx_MEM (mode_for_size (total_size
1952 plus_constant (XEXP (x, 0), adjust));
1954 spill_stack_slot[from_reg] = stack_slot;
1955 spill_stack_slot_width[from_reg] = total_size;
1958 /* On a big endian machine, the "address" of the slot
1959 is the address of the low part that fits its inherent mode. */
1960 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
1961 adjust += (total_size - inherent_size);
1963 /* If we have any adjustment to make, or if the stack slot is the
1964 wrong mode, make a new stack slot. */
1965 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
1967 x = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
1968 plus_constant (XEXP (x, 0), adjust));
1970 /* If this was shared among registers, must ensure we never
1971 set it readonly since that can cause scheduling
1972 problems. Note we would only have in this adjustment
1973 case in any event, since the code above doesn't set it. */
1976 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1979 /* Save the stack slot for later. */
1980 reg_equiv_memory_loc[i] = x;
1984 /* Mark the slots in regs_ever_live for the hard regs
1985 used by pseudo-reg number REGNO. */
1988 mark_home_live (regno)
1991 register int i, lim;
1993 i = reg_renumber[regno];
1996 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
1998 regs_ever_live[i++] = 1;
2001 /* This function handles the tracking of elimination offsets around branches.
2003 X is a piece of RTL being scanned.
2005 INSN is the insn that it came from, if any.
2007 INITIAL_P is non-zero if we are to set the offset to be the initial
2008 offset and zero if we are setting the offset of the label to be the
2012 set_label_offsets (x, insn, initial_p)
2017 enum rtx_code code = GET_CODE (x);
2020 struct elim_table *p;
2025 if (LABEL_REF_NONLOCAL_P (x))
2030 /* ... fall through ... */
2033 /* If we know nothing about this label, set the desired offsets. Note
2034 that this sets the offset at a label to be the offset before a label
2035 if we don't know anything about the label. This is not correct for
2036 the label after a BARRIER, but is the best guess we can make. If
2037 we guessed wrong, we will suppress an elimination that might have
2038 been possible had we been able to guess correctly. */
2040 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2042 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2043 offsets_at[CODE_LABEL_NUMBER (x)][i]
2044 = (initial_p ? reg_eliminate[i].initial_offset
2045 : reg_eliminate[i].offset);
2046 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2049 /* Otherwise, if this is the definition of a label and it is
2050 preceded by a BARRIER, set our offsets to the known offset of
2054 && (tem = prev_nonnote_insn (insn)) != 0
2055 && GET_CODE (tem) == BARRIER)
2056 set_offsets_for_label (insn);
2058 /* If neither of the above cases is true, compare each offset
2059 with those previously recorded and suppress any eliminations
2060 where the offsets disagree. */
2062 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2063 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2064 != (initial_p ? reg_eliminate[i].initial_offset
2065 : reg_eliminate[i].offset))
2066 reg_eliminate[i].can_eliminate = 0;
2071 set_label_offsets (PATTERN (insn), insn, initial_p);
2073 /* ... fall through ... */
2077 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2078 and hence must have all eliminations at their initial offsets. */
2079 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2080 if (REG_NOTE_KIND (tem) == REG_LABEL)
2081 set_label_offsets (XEXP (tem, 0), insn, 1);
2086 /* Each of the labels in the address vector must be at their initial
2087 offsets. We want the first field for ADDR_VEC and the second
2088 field for ADDR_DIFF_VEC. */
2090 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2091 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2096 /* We only care about setting PC. If the source is not RETURN,
2097 IF_THEN_ELSE, or a label, disable any eliminations not at
2098 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2099 isn't one of those possibilities. For branches to a label,
2100 call ourselves recursively.
2102 Note that this can disable elimination unnecessarily when we have
2103 a non-local goto since it will look like a non-constant jump to
2104 someplace in the current function. This isn't a significant
2105 problem since such jumps will normally be when all elimination
2106 pairs are back to their initial offsets. */
2108 if (SET_DEST (x) != pc_rtx)
2111 switch (GET_CODE (SET_SRC (x)))
2118 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2122 tem = XEXP (SET_SRC (x), 1);
2123 if (GET_CODE (tem) == LABEL_REF)
2124 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2125 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2128 tem = XEXP (SET_SRC (x), 2);
2129 if (GET_CODE (tem) == LABEL_REF)
2130 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2131 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2139 /* If we reach here, all eliminations must be at their initial
2140 offset because we are doing a jump to a variable address. */
2141 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2142 if (p->offset != p->initial_offset)
2143 p->can_eliminate = 0;
2151 /* Scan X and replace any eliminable registers (such as fp) with a
2152 replacement (such as sp), plus an offset.
2154 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2155 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2156 MEM, we are allowed to replace a sum of a register and the constant zero
2157 with the register, which we cannot do outside a MEM. In addition, we need
2158 to record the fact that a register is referenced outside a MEM.
2160 If INSN is an insn, it is the insn containing X. If we replace a REG
2161 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2162 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2163 the REG is being modified.
2165 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2166 That's used when we eliminate in expressions stored in notes.
2167 This means, do not set ref_outside_mem even if the reference
2170 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2171 replacements done assuming all offsets are at their initial values. If
2172 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2173 encounter, return the actual location so that find_reloads will do
2174 the proper thing. */
2177 eliminate_regs (x, mem_mode, insn)
2179 enum machine_mode mem_mode;
2182 enum rtx_code code = GET_CODE (x);
2183 struct elim_table *ep;
2190 if (! current_function_decl)
2209 /* This is only for the benefit of the debugging backends, which call
2210 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2211 removed after CSE. */
2212 new = eliminate_regs (XEXP (x, 0), 0, insn);
2213 if (GET_CODE (new) == MEM)
2214 return XEXP (new, 0);
2220 /* First handle the case where we encounter a bare register that
2221 is eliminable. Replace it with a PLUS. */
2222 if (regno < FIRST_PSEUDO_REGISTER)
2224 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2226 if (ep->from_rtx == x && ep->can_eliminate)
2227 return plus_constant (ep->to_rtx, ep->previous_offset);
2230 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2231 && reg_equiv_constant[regno]
2232 && ! CONSTANT_P (reg_equiv_constant[regno]))
2233 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2237 /* You might think handling MINUS in a manner similar to PLUS is a
2238 good idea. It is not. It has been tried multiple times and every
2239 time the change has had to have been reverted.
2241 Other parts of reload know a PLUS is special (gen_reload for example)
2242 and require special code to handle code a reloaded PLUS operand.
2244 Also consider backends where the flags register is clobbered by a
2245 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2246 lea instruction comes to mind). If we try to reload a MINUS, we
2247 may kill the flags register that was holding a useful value.
2249 So, please before trying to handle MINUS, consider reload as a
2250 whole instead of this little section as well as the backend issues. */
2252 /* If this is the sum of an eliminable register and a constant, rework
2254 if (GET_CODE (XEXP (x, 0)) == REG
2255 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2256 && CONSTANT_P (XEXP (x, 1)))
2258 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2260 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2262 /* The only time we want to replace a PLUS with a REG (this
2263 occurs when the constant operand of the PLUS is the negative
2264 of the offset) is when we are inside a MEM. We won't want
2265 to do so at other times because that would change the
2266 structure of the insn in a way that reload can't handle.
2267 We special-case the commonest situation in
2268 eliminate_regs_in_insn, so just replace a PLUS with a
2269 PLUS here, unless inside a MEM. */
2270 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2271 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2274 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2275 plus_constant (XEXP (x, 1),
2276 ep->previous_offset));
2279 /* If the register is not eliminable, we are done since the other
2280 operand is a constant. */
2284 /* If this is part of an address, we want to bring any constant to the
2285 outermost PLUS. We will do this by doing register replacement in
2286 our operands and seeing if a constant shows up in one of them.
2288 Note that there is no risk of modifying the structure of the insn,
2289 since we only get called for its operands, thus we are either
2290 modifying the address inside a MEM, or something like an address
2291 operand of a load-address insn. */
2294 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2295 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2297 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2299 /* If one side is a PLUS and the other side is a pseudo that
2300 didn't get a hard register but has a reg_equiv_constant,
2301 we must replace the constant here since it may no longer
2302 be in the position of any operand. */
2303 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2304 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2305 && reg_renumber[REGNO (new1)] < 0
2306 && reg_equiv_constant != 0
2307 && reg_equiv_constant[REGNO (new1)] != 0)
2308 new1 = reg_equiv_constant[REGNO (new1)];
2309 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2310 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2311 && reg_renumber[REGNO (new0)] < 0
2312 && reg_equiv_constant[REGNO (new0)] != 0)
2313 new0 = reg_equiv_constant[REGNO (new0)];
2315 new = form_sum (new0, new1);
2317 /* As above, if we are not inside a MEM we do not want to
2318 turn a PLUS into something else. We might try to do so here
2319 for an addition of 0 if we aren't optimizing. */
2320 if (! mem_mode && GET_CODE (new) != PLUS)
2321 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2329 /* If this is the product of an eliminable register and a
2330 constant, apply the distribute law and move the constant out
2331 so that we have (plus (mult ..) ..). This is needed in order
2332 to keep load-address insns valid. This case is pathological.
2333 We ignore the possibility of overflow here. */
2334 if (GET_CODE (XEXP (x, 0)) == REG
2335 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2336 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2337 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2339 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2342 /* Refs inside notes don't count for this purpose. */
2343 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2344 || GET_CODE (insn) == INSN_LIST)))
2345 ep->ref_outside_mem = 1;
2348 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2349 ep->previous_offset * INTVAL (XEXP (x, 1)));
2352 /* ... fall through ... */
2356 /* See comments before PLUS about handling MINUS. */
2358 case DIV: case UDIV:
2359 case MOD: case UMOD:
2360 case AND: case IOR: case XOR:
2361 case ROTATERT: case ROTATE:
2362 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2364 case GE: case GT: case GEU: case GTU:
2365 case LE: case LT: case LEU: case LTU:
2367 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2369 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2371 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2372 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2377 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2380 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2381 if (new != XEXP (x, 0))
2383 /* If this is a REG_DEAD note, it is not valid anymore.
2384 Using the eliminated version could result in creating a
2385 REG_DEAD note for the stack or frame pointer. */
2386 if (GET_MODE (x) == REG_DEAD)
2388 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2391 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2395 /* ... fall through ... */
2398 /* Now do eliminations in the rest of the chain. If this was
2399 an EXPR_LIST, this might result in allocating more memory than is
2400 strictly needed, but it simplifies the code. */
2403 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2404 if (new != XEXP (x, 1))
2405 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2413 case STRICT_LOW_PART:
2415 case SIGN_EXTEND: case ZERO_EXTEND:
2416 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2417 case FLOAT: case FIX:
2418 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2422 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2423 if (new != XEXP (x, 0))
2424 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2428 /* Similar to above processing, but preserve SUBREG_WORD.
2429 Convert (subreg (mem)) to (mem) if not paradoxical.
2430 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2431 pseudo didn't get a hard reg, we must replace this with the
2432 eliminated version of the memory location because push_reloads
2433 may do the replacement in certain circumstances. */
2434 if (GET_CODE (SUBREG_REG (x)) == REG
2435 && (GET_MODE_SIZE (GET_MODE (x))
2436 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2437 && reg_equiv_memory_loc != 0
2438 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2440 new = SUBREG_REG (x);
2443 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2445 if (new != XEXP (x, 0))
2447 int x_size = GET_MODE_SIZE (GET_MODE (x));
2448 int new_size = GET_MODE_SIZE (GET_MODE (new));
2450 if (GET_CODE (new) == MEM
2451 && ((x_size < new_size
2452 #ifdef WORD_REGISTER_OPERATIONS
2453 /* On these machines, combine can create rtl of the form
2454 (set (subreg:m1 (reg:m2 R) 0) ...)
2455 where m1 < m2, and expects something interesting to
2456 happen to the entire word. Moreover, it will use the
2457 (reg:m2 R) later, expecting all bits to be preserved.
2458 So if the number of words is the same, preserve the
2459 subreg so that push_reloads can see it. */
2460 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
2463 || (x_size == new_size))
2466 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2467 enum machine_mode mode = GET_MODE (x);
2469 if (BYTES_BIG_ENDIAN)
2470 offset += (MIN (UNITS_PER_WORD,
2471 GET_MODE_SIZE (GET_MODE (new)))
2472 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2474 PUT_MODE (new, mode);
2475 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2479 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x));
2485 /* This is only for the benefit of the debugging backends, which call
2486 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2487 removed after CSE. */
2488 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2489 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2491 /* Our only special processing is to pass the mode of the MEM to our
2492 recursive call and copy the flags. While we are here, handle this
2493 case more efficiently. */
2494 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
2495 if (new != XEXP (x, 0))
2497 new = gen_rtx_MEM (GET_MODE (x), new);
2498 new->volatil = x->volatil;
2499 new->unchanging = x->unchanging;
2500 new->in_struct = x->in_struct;
2516 /* Process each of our operands recursively. If any have changed, make a
2518 fmt = GET_RTX_FORMAT (code);
2519 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2523 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2524 if (new != XEXP (x, i) && ! copied)
2526 rtx new_x = rtx_alloc (code);
2527 bcopy ((char *) x, (char *) new_x,
2528 (sizeof (*new_x) - sizeof (new_x->fld)
2529 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2535 else if (*fmt == 'E')
2538 for (j = 0; j < XVECLEN (x, i); j++)
2540 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2541 if (new != XVECEXP (x, i, j) && ! copied_vec)
2543 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2547 rtx new_x = rtx_alloc (code);
2548 bcopy ((char *) x, (char *) new_x,
2549 (sizeof (*new_x) - sizeof (new_x->fld)
2550 + (sizeof (new_x->fld[0])
2551 * GET_RTX_LENGTH (code))));
2555 XVEC (x, i) = new_v;
2558 XVECEXP (x, i, j) = new;
2566 /* Scan rtx X for modifications of elimination target registers. Update
2567 the table of eliminables to reflect the changed state. MEM_MODE is
2568 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2571 elimination_effects (x, mem_mode)
2573 enum machine_mode mem_mode;
2576 enum rtx_code code = GET_CODE (x);
2577 struct elim_table *ep;
2603 /* First handle the case where we encounter a bare register that
2604 is eliminable. Replace it with a PLUS. */
2605 if (regno < FIRST_PSEUDO_REGISTER)
2607 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2609 if (ep->from_rtx == x && ep->can_eliminate)
2612 ep->ref_outside_mem = 1;
2617 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2618 && reg_equiv_constant[regno]
2619 && ! CONSTANT_P (reg_equiv_constant[regno]))
2620 elimination_effects (reg_equiv_constant[regno], mem_mode);
2627 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2628 if (ep->to_rtx == XEXP (x, 0))
2630 int size = GET_MODE_SIZE (mem_mode);
2632 /* If more bytes than MEM_MODE are pushed, account for them. */
2633 #ifdef PUSH_ROUNDING
2634 if (ep->to_rtx == stack_pointer_rtx)
2635 size = PUSH_ROUNDING (size);
2637 if (code == PRE_DEC || code == POST_DEC)
2643 /* Fall through to generic unary operation case. */
2644 case STRICT_LOW_PART:
2646 case SIGN_EXTEND: case ZERO_EXTEND:
2647 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2648 case FLOAT: case FIX:
2649 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2653 elimination_effects (XEXP (x, 0), mem_mode);
2657 if (GET_CODE (SUBREG_REG (x)) == REG
2658 && (GET_MODE_SIZE (GET_MODE (x))
2659 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2660 && reg_equiv_memory_loc != 0
2661 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2664 elimination_effects (SUBREG_REG (x), mem_mode);
2668 /* If using a register that is the source of an eliminate we still
2669 think can be performed, note it cannot be performed since we don't
2670 know how this register is used. */
2671 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2672 if (ep->from_rtx == XEXP (x, 0))
2673 ep->can_eliminate = 0;
2675 elimination_effects (XEXP (x, 0), mem_mode);
2679 /* If clobbering a register that is the replacement register for an
2680 elimination we still think can be performed, note that it cannot
2681 be performed. Otherwise, we need not be concerned about it. */
2682 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2683 if (ep->to_rtx == XEXP (x, 0))
2684 ep->can_eliminate = 0;
2686 elimination_effects (XEXP (x, 0), mem_mode);
2690 /* Check for setting a register that we know about. */
2691 if (GET_CODE (SET_DEST (x)) == REG)
2693 /* See if this is setting the replacement register for an
2696 If DEST is the hard frame pointer, we do nothing because we
2697 assume that all assignments to the frame pointer are for
2698 non-local gotos and are being done at a time when they are valid
2699 and do not disturb anything else. Some machines want to
2700 eliminate a fake argument pointer (or even a fake frame pointer)
2701 with either the real frame or the stack pointer. Assignments to
2702 the hard frame pointer must not prevent this elimination. */
2704 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2706 if (ep->to_rtx == SET_DEST (x)
2707 && SET_DEST (x) != hard_frame_pointer_rtx)
2709 /* If it is being incremented, adjust the offset. Otherwise,
2710 this elimination can't be done. */
2711 rtx src = SET_SRC (x);
2713 if (GET_CODE (src) == PLUS
2714 && XEXP (src, 0) == SET_DEST (x)
2715 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2716 ep->offset -= INTVAL (XEXP (src, 1));
2718 ep->can_eliminate = 0;
2722 elimination_effects (SET_DEST (x), 0);
2723 elimination_effects (SET_SRC (x), 0);
2727 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2730 /* Our only special processing is to pass the mode of the MEM to our
2732 elimination_effects (XEXP (x, 0), GET_MODE (x));
2739 fmt = GET_RTX_FORMAT (code);
2740 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2743 elimination_effects (XEXP (x, i), mem_mode);
2744 else if (*fmt == 'E')
2745 for (j = 0; j < XVECLEN (x, i); j++)
2746 elimination_effects (XVECEXP (x, i, j), mem_mode);
2750 /* Descend through rtx X and verify that no references to eliminable registers
2751 remain. If any do remain, mark the involved register as not
2755 check_eliminable_occurrences (x)
2765 code = GET_CODE (x);
2767 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2769 struct elim_table *ep;
2771 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2772 if (ep->from_rtx == x && ep->can_eliminate)
2773 ep->can_eliminate = 0;
2777 fmt = GET_RTX_FORMAT (code);
2778 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2781 check_eliminable_occurrences (XEXP (x, i));
2782 else if (*fmt == 'E')
2785 for (j = 0; j < XVECLEN (x, i); j++)
2786 check_eliminable_occurrences (XVECEXP (x, i, j));
2791 /* Scan INSN and eliminate all eliminable registers in it.
2793 If REPLACE is nonzero, do the replacement destructively. Also
2794 delete the insn as dead it if it is setting an eliminable register.
2796 If REPLACE is zero, do all our allocations in reload_obstack.
2798 If no eliminations were done and this insn doesn't require any elimination
2799 processing (these are not identical conditions: it might be updating sp,
2800 but not referencing fp; this needs to be seen during reload_as_needed so
2801 that the offset between fp and sp can be taken into consideration), zero
2802 is returned. Otherwise, 1 is returned. */
2805 eliminate_regs_in_insn (insn, replace)
2809 int icode = recog_memoized (insn);
2810 rtx old_body = PATTERN (insn);
2811 int insn_is_asm = asm_noperands (old_body) >= 0;
2812 rtx old_set = single_set (insn);
2816 rtx substed_operand[MAX_RECOG_OPERANDS];
2817 rtx orig_operand[MAX_RECOG_OPERANDS];
2818 struct elim_table *ep;
2820 if (! insn_is_asm && icode < 0)
2822 if (GET_CODE (PATTERN (insn)) == USE
2823 || GET_CODE (PATTERN (insn)) == CLOBBER
2824 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2825 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2826 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2832 push_obstacks (&reload_obstack, &reload_obstack);
2834 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2835 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2837 /* Check for setting an eliminable register. */
2838 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2839 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2841 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2842 /* If this is setting the frame pointer register to the
2843 hardware frame pointer register and this is an elimination
2844 that will be done (tested above), this insn is really
2845 adjusting the frame pointer downward to compensate for
2846 the adjustment done before a nonlocal goto. */
2847 if (ep->from == FRAME_POINTER_REGNUM
2848 && ep->to == HARD_FRAME_POINTER_REGNUM)
2850 rtx src = SET_SRC (old_set);
2851 int offset = 0, ok = 0;
2852 rtx prev_insn, prev_set;
2854 if (src == ep->to_rtx)
2856 else if (GET_CODE (src) == PLUS
2857 && GET_CODE (XEXP (src, 0)) == CONST_INT
2858 && XEXP (src, 1) == ep->to_rtx)
2859 offset = INTVAL (XEXP (src, 0)), ok = 1;
2860 else if (GET_CODE (src) == PLUS
2861 && GET_CODE (XEXP (src, 1)) == CONST_INT
2862 && XEXP (src, 0) == ep->to_rtx)
2863 offset = INTVAL (XEXP (src, 1)), ok = 1;
2864 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
2865 && (prev_set = single_set (prev_insn)) != 0
2866 && rtx_equal_p (SET_DEST (prev_set), src))
2868 src = SET_SRC (prev_set);
2869 if (src == ep->to_rtx)
2871 else if (GET_CODE (src) == PLUS
2872 && GET_CODE (XEXP (src, 0)) == CONST_INT
2873 && XEXP (src, 1) == ep->to_rtx)
2874 offset = INTVAL (XEXP (src, 0)), ok = 1;
2875 else if (GET_CODE (src) == PLUS
2876 && GET_CODE (XEXP (src, 1)) == CONST_INT
2877 && XEXP (src, 0) == ep->to_rtx)
2878 offset = INTVAL (XEXP (src, 1)), ok = 1;
2886 = plus_constant (ep->to_rtx, offset - ep->offset);
2888 /* First see if this insn remains valid when we
2889 make the change. If not, keep the INSN_CODE
2890 the same and let reload fit it up. */
2891 validate_change (insn, &SET_SRC (old_set), src, 1);
2892 validate_change (insn, &SET_DEST (old_set),
2894 if (! apply_change_group ())
2896 SET_SRC (old_set) = src;
2897 SET_DEST (old_set) = ep->to_rtx;
2907 /* In this case this insn isn't serving a useful purpose. We
2908 will delete it in reload_as_needed once we know that this
2909 elimination is, in fact, being done.
2911 If REPLACE isn't set, we can't delete this insn, but needn't
2912 process it since it won't be used unless something changes. */
2915 delete_dead_insn (insn);
2923 /* We allow one special case which happens to work on all machines we
2924 currently support: a single set with the source being a PLUS of an
2925 eliminable register and a constant. */
2927 && GET_CODE (SET_SRC (old_set)) == PLUS
2928 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
2929 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
2930 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
2932 rtx reg = XEXP (SET_SRC (old_set), 0);
2933 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
2935 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2936 if (ep->from_rtx == reg && ep->can_eliminate)
2938 offset += ep->offset;
2942 /* We assume here that we don't need a PARALLEL of
2943 any CLOBBERs for this assignment. There's not
2944 much we can do if we do need it. */
2945 PATTERN (insn) = gen_rtx_SET (VOIDmode,
2948 INSN_CODE (insn) = recog (PATTERN (insn), insn, 0);
2949 if (INSN_CODE (insn) < 0)
2954 new_body = old_body;
2957 new_body = copy_insn (old_body);
2958 if (REG_NOTES (insn))
2959 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2961 PATTERN (insn) = new_body;
2962 old_set = single_set (insn);
2964 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
2965 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
2968 /* This can't have an effect on elimination offsets, so skip right
2974 /* Determine the effects of this insn on elimination offsets. */
2975 elimination_effects (old_body, 0);
2977 /* Eliminate all eliminable registers occurring in operands that
2978 can be handled by reload. */
2979 extract_insn (insn);
2981 for (i = 0; i < recog_data.n_operands; i++)
2983 orig_operand[i] = recog_data.operand[i];
2984 substed_operand[i] = recog_data.operand[i];
2986 /* For an asm statement, every operand is eliminable. */
2987 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
2989 /* Check for setting a register that we know about. */
2990 if (recog_data.operand_type[i] != OP_IN
2991 && GET_CODE (orig_operand[i]) == REG)
2993 /* If we are assigning to a register that can be eliminated, it
2994 must be as part of a PARALLEL, since the code above handles
2995 single SETs. We must indicate that we can no longer
2996 eliminate this reg. */
2997 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2999 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3000 ep->can_eliminate = 0;
3003 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3004 replace ? insn : NULL_RTX);
3005 if (substed_operand[i] != orig_operand[i])
3006 val = any_changes = 1;
3007 /* Terminate the search in check_eliminable_occurrences at
3009 *recog_data.operand_loc[i] = 0;
3011 /* If an output operand changed from a REG to a MEM and INSN is an
3012 insn, write a CLOBBER insn. */
3013 if (recog_data.operand_type[i] != OP_IN
3014 && GET_CODE (orig_operand[i]) == REG
3015 && GET_CODE (substed_operand[i]) == MEM
3017 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3022 for (i = 0; i < recog_data.n_dups; i++)
3023 *recog_data.dup_loc[i]
3024 = *recog_data.operand_loc[(int)recog_data.dup_num[i]];
3026 /* If any eliminable remain, they aren't eliminable anymore. */
3027 check_eliminable_occurrences (old_body);
3029 /* Substitute the operands; the new values are in the substed_operand
3031 for (i = 0; i < recog_data.n_operands; i++)
3032 *recog_data.operand_loc[i] = substed_operand[i];
3033 for (i = 0; i < recog_data.n_dups; i++)
3034 *recog_data.dup_loc[i] = substed_operand[(int)recog_data.dup_num[i]];
3036 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3037 re-recognize the insn. We do this in case we had a simple addition
3038 but now can do this as a load-address. This saves an insn in this
3040 If re-recognition fails, the old insn code number will still be used,
3041 and some register operands may have changed into PLUS expressions.
3042 These will be handled by find_reloads by loading them into a register
3047 /* If we aren't replacing things permanently and we changed something,
3048 make another copy to ensure that all the RTL is new. Otherwise
3049 things can go wrong if find_reload swaps commutative operands
3050 and one is inside RTL that has been copied while the other is not. */
3051 new_body = old_body;
3054 new_body = copy_insn (old_body);
3055 if (REG_NOTES (insn))
3056 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3058 PATTERN (insn) = new_body;
3060 /* If we had a move insn but now we don't, rerecognize it. This will
3061 cause spurious re-recognition if the old move had a PARALLEL since
3062 the new one still will, but we can't call single_set without
3063 having put NEW_BODY into the insn and the re-recognition won't
3064 hurt in this rare case. */
3065 /* ??? Why this huge if statement - why don't we just rerecognize the
3069 && ((GET_CODE (SET_SRC (old_set)) == REG
3070 && (GET_CODE (new_body) != SET
3071 || GET_CODE (SET_SRC (new_body)) != REG))
3072 /* If this was a load from or store to memory, compare
3073 the MEM in recog_data.operand to the one in the insn.
3074 If they are not equal, then rerecognize the insn. */
3076 && ((GET_CODE (SET_SRC (old_set)) == MEM
3077 && SET_SRC (old_set) != recog_data.operand[1])
3078 || (GET_CODE (SET_DEST (old_set)) == MEM
3079 && SET_DEST (old_set) != recog_data.operand[0])))
3080 /* If this was an add insn before, rerecognize. */
3081 || GET_CODE (SET_SRC (old_set)) == PLUS))
3083 int new_icode = recog (PATTERN (insn), insn, 0);
3085 INSN_CODE (insn) = icode;
3089 /* Restore the old body. If there were any changes to it, we made a copy
3090 of it while the changes were still in place, so we'll correctly return
3091 a modified insn below. */
3094 /* Restore the old body. */
3095 for (i = 0; i < recog_data.n_operands; i++)
3096 *recog_data.operand_loc[i] = orig_operand[i];
3097 for (i = 0; i < recog_data.n_dups; i++)
3098 *recog_data.dup_loc[i] = orig_operand[(int)recog_data.dup_num[i]];
3101 /* Update all elimination pairs to reflect the status after the current
3102 insn. The changes we make were determined by the earlier call to
3103 elimination_effects.
3105 We also detect a cases where register elimination cannot be done,
3106 namely, if a register would be both changed and referenced outside a MEM
3107 in the resulting insn since such an insn is often undefined and, even if
3108 not, we cannot know what meaning will be given to it. Note that it is
3109 valid to have a register used in an address in an insn that changes it
3110 (presumably with a pre- or post-increment or decrement).
3112 If anything changes, return nonzero. */
3114 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3116 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3117 ep->can_eliminate = 0;
3119 ep->ref_outside_mem = 0;
3121 if (ep->previous_offset != ep->offset)
3126 /* If we changed something, perform elimination in REG_NOTES. This is
3127 needed even when REPLACE is zero because a REG_DEAD note might refer
3128 to a register that we eliminate and could cause a different number
3129 of spill registers to be needed in the final reload pass than in
3131 if (val && REG_NOTES (insn) != 0)
3132 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3140 /* Loop through all elimination pairs.
3141 Recalculate the number not at initial offset.
3143 Compute the maximum offset (minimum offset if the stack does not
3144 grow downward) for each elimination pair. */
3147 update_eliminable_offsets ()
3149 struct elim_table *ep;
3151 num_not_at_initial_offset = 0;
3152 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3154 ep->previous_offset = ep->offset;
3155 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3156 num_not_at_initial_offset++;
3160 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3161 replacement we currently believe is valid, mark it as not eliminable if X
3162 modifies DEST in any way other than by adding a constant integer to it.
3164 If DEST is the frame pointer, we do nothing because we assume that
3165 all assignments to the hard frame pointer are nonlocal gotos and are being
3166 done at a time when they are valid and do not disturb anything else.
3167 Some machines want to eliminate a fake argument pointer with either the
3168 frame or stack pointer. Assignments to the hard frame pointer must not
3169 prevent this elimination.
3171 Called via note_stores from reload before starting its passes to scan
3172 the insns of the function. */
3175 mark_not_eliminable (dest, x, data)
3178 void *data ATTRIBUTE_UNUSED;
3180 register unsigned int i;
3182 /* A SUBREG of a hard register here is just changing its mode. We should
3183 not see a SUBREG of an eliminable hard register, but check just in
3185 if (GET_CODE (dest) == SUBREG)
3186 dest = SUBREG_REG (dest);
3188 if (dest == hard_frame_pointer_rtx)
3191 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3192 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3193 && (GET_CODE (x) != SET
3194 || GET_CODE (SET_SRC (x)) != PLUS
3195 || XEXP (SET_SRC (x), 0) != dest
3196 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3198 reg_eliminate[i].can_eliminate_previous
3199 = reg_eliminate[i].can_eliminate = 0;
3204 /* Verify that the initial elimination offsets did not change since the
3205 last call to set_initial_elim_offsets. This is used to catch cases
3206 where something illegal happened during reload_as_needed that could
3207 cause incorrect code to be generated if we did not check for it. */
3210 verify_initial_elim_offsets ()
3214 #ifdef ELIMINABLE_REGS
3215 struct elim_table *ep;
3217 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3219 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3220 if (t != ep->initial_offset)
3224 INITIAL_FRAME_POINTER_OFFSET (t);
3225 if (t != reg_eliminate[0].initial_offset)
3230 /* Reset all offsets on eliminable registers to their initial values. */
3233 set_initial_elim_offsets ()
3235 struct elim_table *ep = reg_eliminate;
3237 #ifdef ELIMINABLE_REGS
3238 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3240 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3241 ep->previous_offset = ep->offset = ep->initial_offset;
3244 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3245 ep->previous_offset = ep->offset = ep->initial_offset;
3248 num_not_at_initial_offset = 0;
3251 /* Initialize the known label offsets.
3252 Set a known offset for each forced label to be at the initial offset
3253 of each elimination. We do this because we assume that all
3254 computed jumps occur from a location where each elimination is
3255 at its initial offset.
3256 For all other labels, show that we don't know the offsets. */
3259 set_initial_label_offsets ()
3262 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
3264 for (x = forced_labels; x; x = XEXP (x, 1))
3266 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3269 /* Set all elimination offsets to the known values for the code label given
3273 set_offsets_for_label (insn)
3277 int label_nr = CODE_LABEL_NUMBER (insn);
3278 struct elim_table *ep;
3280 num_not_at_initial_offset = 0;
3281 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3283 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3284 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3285 num_not_at_initial_offset++;
3289 /* See if anything that happened changes which eliminations are valid.
3290 For example, on the Sparc, whether or not the frame pointer can
3291 be eliminated can depend on what registers have been used. We need
3292 not check some conditions again (such as flag_omit_frame_pointer)
3293 since they can't have changed. */
3296 update_eliminables (pset)
3299 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3300 int previous_frame_pointer_needed = frame_pointer_needed;
3302 struct elim_table *ep;
3304 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3305 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3306 #ifdef ELIMINABLE_REGS
3307 || ! CAN_ELIMINATE (ep->from, ep->to)
3310 ep->can_eliminate = 0;
3312 /* Look for the case where we have discovered that we can't replace
3313 register A with register B and that means that we will now be
3314 trying to replace register A with register C. This means we can
3315 no longer replace register C with register B and we need to disable
3316 such an elimination, if it exists. This occurs often with A == ap,
3317 B == sp, and C == fp. */
3319 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3321 struct elim_table *op;
3322 register int new_to = -1;
3324 if (! ep->can_eliminate && ep->can_eliminate_previous)
3326 /* Find the current elimination for ep->from, if there is a
3328 for (op = reg_eliminate;
3329 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3330 if (op->from == ep->from && op->can_eliminate)
3336 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3338 for (op = reg_eliminate;
3339 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3340 if (op->from == new_to && op->to == ep->to)
3341 op->can_eliminate = 0;
3345 /* See if any registers that we thought we could eliminate the previous
3346 time are no longer eliminable. If so, something has changed and we
3347 must spill the register. Also, recompute the number of eliminable
3348 registers and see if the frame pointer is needed; it is if there is
3349 no elimination of the frame pointer that we can perform. */
3351 frame_pointer_needed = 1;
3352 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3354 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3355 && ep->to != HARD_FRAME_POINTER_REGNUM)
3356 frame_pointer_needed = 0;
3358 if (! ep->can_eliminate && ep->can_eliminate_previous)
3360 ep->can_eliminate_previous = 0;
3361 SET_HARD_REG_BIT (*pset, ep->from);
3366 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3367 /* If we didn't need a frame pointer last time, but we do now, spill
3368 the hard frame pointer. */
3369 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3370 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3374 /* Initialize the table of registers to eliminate. */
3379 struct elim_table *ep;
3380 #ifdef ELIMINABLE_REGS
3381 struct elim_table_1 *ep1;
3385 reg_eliminate = (struct elim_table *)
3386 xcalloc(sizeof(struct elim_table), NUM_ELIMINABLE_REGS);
3388 /* Does this function require a frame pointer? */
3390 frame_pointer_needed = (! flag_omit_frame_pointer
3391 #ifdef EXIT_IGNORE_STACK
3392 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3393 and restore sp for alloca. So we can't eliminate
3394 the frame pointer in that case. At some point,
3395 we should improve this by emitting the
3396 sp-adjusting insns for this case. */
3397 || (current_function_calls_alloca
3398 && EXIT_IGNORE_STACK)
3400 || FRAME_POINTER_REQUIRED);
3404 #ifdef ELIMINABLE_REGS
3405 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3406 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3408 ep->from = ep1->from;
3410 ep->can_eliminate = ep->can_eliminate_previous
3411 = (CAN_ELIMINATE (ep->from, ep->to)
3412 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3415 reg_eliminate[0].from = reg_eliminate_1[0].from;
3416 reg_eliminate[0].to = reg_eliminate_1[0].to;
3417 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3418 = ! frame_pointer_needed;
3421 /* Count the number of eliminable registers and build the FROM and TO
3422 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3423 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3424 We depend on this. */
3425 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3427 num_eliminable += ep->can_eliminate;
3428 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3429 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3433 /* Kick all pseudos out of hard register REGNO.
3434 If DUMPFILE is nonzero, log actions taken on that file.
3436 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3437 because we found we can't eliminate some register. In the case, no pseudos
3438 are allowed to be in the register, even if they are only in a block that
3439 doesn't require spill registers, unlike the case when we are spilling this
3440 hard reg to produce another spill register.
3442 Return nonzero if any pseudos needed to be kicked out. */
3445 spill_hard_reg (regno, dumpfile, cant_eliminate)
3447 FILE *dumpfile ATTRIBUTE_UNUSED;
3454 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3455 regs_ever_live[regno] = 1;
3458 /* Spill every pseudo reg that was allocated to this reg
3459 or to something that overlaps this reg. */
3461 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3462 if (reg_renumber[i] >= 0
3463 && (unsigned int) reg_renumber[i] <= regno
3464 && ((unsigned int) reg_renumber[i]
3465 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3466 PSEUDO_REGNO_MODE (i))
3468 SET_REGNO_REG_SET (&spilled_pseudos, i);
3471 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3472 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3475 ior_hard_reg_set (set1, set2)
3476 HARD_REG_SET *set1, *set2;
3478 IOR_HARD_REG_SET (*set1, *set2);
3481 /* After find_reload_regs has been run for all insn that need reloads,
3482 and/or spill_hard_regs was called, this function is used to actually
3483 spill pseudo registers and try to reallocate them. It also sets up the
3484 spill_regs array for use by choose_reload_regs. */
3487 finish_spills (global, dumpfile)
3491 struct insn_chain *chain;
3492 int something_changed = 0;
3495 /* Build the spill_regs array for the function. */
3496 /* If there are some registers still to eliminate and one of the spill regs
3497 wasn't ever used before, additional stack space may have to be
3498 allocated to store this register. Thus, we may have changed the offset
3499 between the stack and frame pointers, so mark that something has changed.
3501 One might think that we need only set VAL to 1 if this is a call-used
3502 register. However, the set of registers that must be saved by the
3503 prologue is not identical to the call-used set. For example, the
3504 register used by the call insn for the return PC is a call-used register,
3505 but must be saved by the prologue. */
3508 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3509 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3511 spill_reg_order[i] = n_spills;
3512 spill_regs[n_spills++] = i;
3513 if (num_eliminable && ! regs_ever_live[i])
3514 something_changed = 1;
3515 regs_ever_live[i] = 1;
3518 spill_reg_order[i] = -1;
3520 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3521 if (REGNO_REG_SET_P (&spilled_pseudos, i))
3523 /* Record the current hard register the pseudo is allocated to in
3524 pseudo_previous_regs so we avoid reallocating it to the same
3525 hard reg in a later pass. */
3526 if (reg_renumber[i] < 0)
3528 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3529 /* Mark it as no longer having a hard register home. */
3530 reg_renumber[i] = -1;
3531 /* We will need to scan everything again. */
3532 something_changed = 1;
3535 /* Retry global register allocation if possible. */
3538 bzero ((char *) pseudo_forbidden_regs, max_regno * sizeof (HARD_REG_SET));
3539 /* For every insn that needs reloads, set the registers used as spill
3540 regs in pseudo_forbidden_regs for every pseudo live across the
3542 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3544 EXECUTE_IF_SET_IN_REG_SET
3545 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3547 ior_hard_reg_set (pseudo_forbidden_regs + i,
3548 &chain->used_spill_regs);
3550 EXECUTE_IF_SET_IN_REG_SET
3551 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3553 ior_hard_reg_set (pseudo_forbidden_regs + i,
3554 &chain->used_spill_regs);
3558 /* Retry allocating the spilled pseudos. For each reg, merge the
3559 various reg sets that indicate which hard regs can't be used,
3560 and call retry_global_alloc.
3561 We change spill_pseudos here to only contain pseudos that did not
3562 get a new hard register. */
3563 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3564 if (reg_old_renumber[i] != reg_renumber[i])
3566 HARD_REG_SET forbidden;
3567 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3568 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3569 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3570 retry_global_alloc (i, forbidden);
3571 if (reg_renumber[i] >= 0)
3572 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3576 /* Fix up the register information in the insn chain.
3577 This involves deleting those of the spilled pseudos which did not get
3578 a new hard register home from the live_{before,after} sets. */
3579 for (chain = reload_insn_chain; chain; chain = chain->next)
3581 HARD_REG_SET used_by_pseudos;
3582 HARD_REG_SET used_by_pseudos2;
3584 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3585 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3587 /* Mark any unallocated hard regs as available for spills. That
3588 makes inheritance work somewhat better. */
3589 if (chain->need_reload)
3591 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3592 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3593 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3595 /* Save the old value for the sanity test below. */
3596 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3598 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3599 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3600 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3601 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3603 /* Make sure we only enlarge the set. */
3604 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3610 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3611 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3613 int regno = reg_renumber[i];
3614 if (reg_old_renumber[i] == regno)
3617 alter_reg (i, reg_old_renumber[i]);
3618 reg_old_renumber[i] = regno;
3622 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3624 fprintf (dumpfile, " Register %d now in %d.\n\n",
3625 i, reg_renumber[i]);
3629 return something_changed;
3632 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3633 Also mark any hard registers used to store user variables as
3634 forbidden from being used for spill registers. */
3637 scan_paradoxical_subregs (x)
3641 register const char *fmt;
3642 register enum rtx_code code = GET_CODE (x);
3648 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3649 && REG_USERVAR_P (x))
3650 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3666 if (GET_CODE (SUBREG_REG (x)) == REG
3667 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3668 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3669 = GET_MODE_SIZE (GET_MODE (x));
3676 fmt = GET_RTX_FORMAT (code);
3677 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3680 scan_paradoxical_subregs (XEXP (x, i));
3681 else if (fmt[i] == 'E')
3684 for (j = XVECLEN (x, i) - 1; j >=0; j--)
3685 scan_paradoxical_subregs (XVECEXP (x, i, j));
3690 /* Reload pseudo-registers into hard regs around each insn as needed.
3691 Additional register load insns are output before the insn that needs it
3692 and perhaps store insns after insns that modify the reloaded pseudo reg.
3694 reg_last_reload_reg and reg_reloaded_contents keep track of
3695 which registers are already available in reload registers.
3696 We update these for the reloads that we perform,
3697 as the insns are scanned. */
3700 reload_as_needed (live_known)
3703 struct insn_chain *chain;
3704 #if defined (AUTO_INC_DEC)
3709 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
3710 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
3711 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3712 reg_has_output_reload = (char *) xmalloc (max_regno);
3713 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3715 set_initial_elim_offsets ();
3717 for (chain = reload_insn_chain; chain; chain = chain->next)
3720 rtx insn = chain->insn;
3721 rtx old_next = NEXT_INSN (insn);
3723 /* If we pass a label, copy the offsets from the label information
3724 into the current offsets of each elimination. */
3725 if (GET_CODE (insn) == CODE_LABEL)
3726 set_offsets_for_label (insn);
3728 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
3730 rtx oldpat = PATTERN (insn);
3732 /* If this is a USE and CLOBBER of a MEM, ensure that any
3733 references to eliminable registers have been removed. */
3735 if ((GET_CODE (PATTERN (insn)) == USE
3736 || GET_CODE (PATTERN (insn)) == CLOBBER)
3737 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3738 XEXP (XEXP (PATTERN (insn), 0), 0)
3739 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3740 GET_MODE (XEXP (PATTERN (insn), 0)),
3743 /* If we need to do register elimination processing, do so.
3744 This might delete the insn, in which case we are done. */
3745 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3747 eliminate_regs_in_insn (insn, 1);
3748 if (GET_CODE (insn) == NOTE)
3750 update_eliminable_offsets ();
3755 /* If need_elim is nonzero but need_reload is zero, one might think
3756 that we could simply set n_reloads to 0. However, find_reloads
3757 could have done some manipulation of the insn (such as swapping
3758 commutative operands), and these manipulations are lost during
3759 the first pass for every insn that needs register elimination.
3760 So the actions of find_reloads must be redone here. */
3762 if (! chain->need_elim && ! chain->need_reload
3763 && ! chain->need_operand_change)
3765 /* First find the pseudo regs that must be reloaded for this insn.
3766 This info is returned in the tables reload_... (see reload.h).
3767 Also modify the body of INSN by substituting RELOAD
3768 rtx's for those pseudo regs. */
3771 bzero (reg_has_output_reload, max_regno);
3772 CLEAR_HARD_REG_SET (reg_is_output_reload);
3774 find_reloads (insn, 1, spill_indirect_levels, live_known,
3778 if (num_eliminable && chain->need_elim)
3779 update_eliminable_offsets ();
3783 rtx next = NEXT_INSN (insn);
3786 prev = PREV_INSN (insn);
3788 /* Now compute which reload regs to reload them into. Perhaps
3789 reusing reload regs from previous insns, or else output
3790 load insns to reload them. Maybe output store insns too.
3791 Record the choices of reload reg in reload_reg_rtx. */
3792 choose_reload_regs (chain);
3794 /* Merge any reloads that we didn't combine for fear of
3795 increasing the number of spill registers needed but now
3796 discover can be safely merged. */
3797 if (SMALL_REGISTER_CLASSES)
3798 merge_assigned_reloads (insn);
3800 /* Generate the insns to reload operands into or out of
3801 their reload regs. */
3802 emit_reload_insns (chain);
3804 /* Substitute the chosen reload regs from reload_reg_rtx
3805 into the insn's body (or perhaps into the bodies of other
3806 load and store insn that we just made for reloading
3807 and that we moved the structure into). */
3810 /* If this was an ASM, make sure that all the reload insns
3811 we have generated are valid. If not, give an error
3814 if (asm_noperands (PATTERN (insn)) >= 0)
3815 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3816 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
3817 && (recog_memoized (p) < 0
3818 || (extract_insn (p), ! constrain_operands (1))))
3820 error_for_asm (insn,
3821 "`asm' operand requires impossible reload");
3823 NOTE_SOURCE_FILE (p) = 0;
3824 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
3827 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3828 is no longer validly lying around to save a future reload.
3829 Note that this does not detect pseudos that were reloaded
3830 for this insn in order to be stored in
3831 (obeying register constraints). That is correct; such reload
3832 registers ARE still valid. */
3833 note_stores (oldpat, forget_old_reloads_1, NULL);
3835 /* There may have been CLOBBER insns placed after INSN. So scan
3836 between INSN and NEXT and use them to forget old reloads. */
3837 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3838 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3839 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3842 /* Likewise for regs altered by auto-increment in this insn.
3843 REG_INC notes have been changed by reloading:
3844 find_reloads_address_1 records substitutions for them,
3845 which have been performed by subst_reloads above. */
3846 for (i = n_reloads - 1; i >= 0; i--)
3848 rtx in_reg = rld[i].in_reg;
3851 enum rtx_code code = GET_CODE (in_reg);
3852 /* PRE_INC / PRE_DEC will have the reload register ending up
3853 with the same value as the stack slot, but that doesn't
3854 hold true for POST_INC / POST_DEC. Either we have to
3855 convert the memory access to a true POST_INC / POST_DEC,
3856 or we can't use the reload register for inheritance. */
3857 if ((code == POST_INC || code == POST_DEC)
3858 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3859 REGNO (rld[i].reg_rtx))
3860 /* Make sure it is the inc/dec pseudo, and not
3861 some other (e.g. output operand) pseudo. */
3862 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3863 == REGNO (XEXP (in_reg, 0))))
3866 rtx reload_reg = rld[i].reg_rtx;
3867 enum machine_mode mode = GET_MODE (reload_reg);
3871 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3873 /* We really want to ignore REG_INC notes here, so
3874 use PATTERN (p) as argument to reg_set_p . */
3875 if (reg_set_p (reload_reg, PATTERN (p)))
3877 n = count_occurrences (PATTERN (p), reload_reg);
3882 n = validate_replace_rtx (reload_reg,
3883 gen_rtx (code, mode,
3887 /* We must also verify that the constraints
3888 are met after the replacement. */
3891 n = constrain_operands (1);
3895 /* If the constraints were not met, then
3896 undo the replacement. */
3899 validate_replace_rtx (gen_rtx (code, mode,
3911 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3913 /* Mark this as having an output reload so that the
3914 REG_INC processing code below won't invalidate
3915 the reload for inheritance. */
3916 SET_HARD_REG_BIT (reg_is_output_reload,
3917 REGNO (reload_reg));
3918 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3921 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
3924 else if ((code == PRE_INC || code == PRE_DEC)
3925 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3926 REGNO (rld[i].reg_rtx))
3927 /* Make sure it is the inc/dec pseudo, and not
3928 some other (e.g. output operand) pseudo. */
3929 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3930 == REGNO (XEXP (in_reg, 0))))
3932 SET_HARD_REG_BIT (reg_is_output_reload,
3933 REGNO (rld[i].reg_rtx));
3934 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3938 /* If a pseudo that got a hard register is auto-incremented,
3939 we must purge records of copying it into pseudos without
3941 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3942 if (REG_NOTE_KIND (x) == REG_INC)
3944 /* See if this pseudo reg was reloaded in this insn.
3945 If so, its last-reload info is still valid
3946 because it is based on this insn's reload. */
3947 for (i = 0; i < n_reloads; i++)
3948 if (rld[i].out == XEXP (x, 0))
3952 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
3956 /* A reload reg's contents are unknown after a label. */
3957 if (GET_CODE (insn) == CODE_LABEL)
3958 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3960 /* Don't assume a reload reg is still good after a call insn
3961 if it is a call-used reg. */
3962 else if (GET_CODE (insn) == CALL_INSN)
3963 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
3967 free (reg_last_reload_reg);
3968 free (reg_has_output_reload);
3971 /* Discard all record of any value reloaded from X,
3972 or reloaded in X from someplace else;
3973 unless X is an output reload reg of the current insn.
3975 X may be a hard reg (the reload reg)
3976 or it may be a pseudo reg that was reloaded from. */
3979 forget_old_reloads_1 (x, ignored, data)
3981 rtx ignored ATTRIBUTE_UNUSED;
3982 void *data ATTRIBUTE_UNUSED;
3988 /* note_stores does give us subregs of hard regs. */
3989 while (GET_CODE (x) == SUBREG)
3991 offset += SUBREG_WORD (x);
3995 if (GET_CODE (x) != REG)
3998 regno = REGNO (x) + offset;
4000 if (regno >= FIRST_PSEUDO_REGISTER)
4006 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4007 /* Storing into a spilled-reg invalidates its contents.
4008 This can happen if a block-local pseudo is allocated to that reg
4009 and it wasn't spilled because this block's total need is 0.
4010 Then some insn might have an optional reload and use this reg. */
4011 for (i = 0; i < nr; i++)
4012 /* But don't do this if the reg actually serves as an output
4013 reload reg in the current instruction. */
4015 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4016 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4019 /* Since value of X has changed,
4020 forget any value previously copied from it. */
4023 /* But don't forget a copy if this is the output reload
4024 that establishes the copy's validity. */
4025 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4026 reg_last_reload_reg[regno + nr] = 0;
4029 /* The following HARD_REG_SETs indicate when each hard register is
4030 used for a reload of various parts of the current insn. */
4032 /* If reg is unavailable for all reloads. */
4033 static HARD_REG_SET reload_reg_unavailable;
4034 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4035 static HARD_REG_SET reload_reg_used;
4036 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4037 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4038 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4039 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4040 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4041 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4042 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4043 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4044 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4045 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4046 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4047 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4048 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4049 static HARD_REG_SET reload_reg_used_in_op_addr;
4050 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4051 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4052 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4053 static HARD_REG_SET reload_reg_used_in_insn;
4054 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4055 static HARD_REG_SET reload_reg_used_in_other_addr;
4057 /* If reg is in use as a reload reg for any sort of reload. */
4058 static HARD_REG_SET reload_reg_used_at_all;
4060 /* If reg is use as an inherited reload. We just mark the first register
4062 static HARD_REG_SET reload_reg_used_for_inherit;
4064 /* Records which hard regs are used in any way, either as explicit use or
4065 by being allocated to a pseudo during any point of the current insn. */
4066 static HARD_REG_SET reg_used_in_insn;
4068 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4069 TYPE. MODE is used to indicate how many consecutive regs are
4073 mark_reload_reg_in_use (regno, opnum, type, mode)
4076 enum reload_type type;
4077 enum machine_mode mode;
4079 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4082 for (i = regno; i < nregs + regno; i++)
4087 SET_HARD_REG_BIT (reload_reg_used, i);
4090 case RELOAD_FOR_INPUT_ADDRESS:
4091 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4094 case RELOAD_FOR_INPADDR_ADDRESS:
4095 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4098 case RELOAD_FOR_OUTPUT_ADDRESS:
4099 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4102 case RELOAD_FOR_OUTADDR_ADDRESS:
4103 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4106 case RELOAD_FOR_OPERAND_ADDRESS:
4107 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4110 case RELOAD_FOR_OPADDR_ADDR:
4111 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4114 case RELOAD_FOR_OTHER_ADDRESS:
4115 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4118 case RELOAD_FOR_INPUT:
4119 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4122 case RELOAD_FOR_OUTPUT:
4123 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4126 case RELOAD_FOR_INSN:
4127 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4131 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4135 /* Similarly, but show REGNO is no longer in use for a reload. */
4138 clear_reload_reg_in_use (regno, opnum, type, mode)
4141 enum reload_type type;
4142 enum machine_mode mode;
4144 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4145 unsigned int start_regno, end_regno, r;
4147 /* A complication is that for some reload types, inheritance might
4148 allow multiple reloads of the same types to share a reload register.
4149 We set check_opnum if we have to check only reloads with the same
4150 operand number, and check_any if we have to check all reloads. */
4151 int check_opnum = 0;
4153 HARD_REG_SET *used_in_set;
4158 used_in_set = &reload_reg_used;
4161 case RELOAD_FOR_INPUT_ADDRESS:
4162 used_in_set = &reload_reg_used_in_input_addr[opnum];
4165 case RELOAD_FOR_INPADDR_ADDRESS:
4167 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4170 case RELOAD_FOR_OUTPUT_ADDRESS:
4171 used_in_set = &reload_reg_used_in_output_addr[opnum];
4174 case RELOAD_FOR_OUTADDR_ADDRESS:
4176 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4179 case RELOAD_FOR_OPERAND_ADDRESS:
4180 used_in_set = &reload_reg_used_in_op_addr;
4183 case RELOAD_FOR_OPADDR_ADDR:
4185 used_in_set = &reload_reg_used_in_op_addr_reload;
4188 case RELOAD_FOR_OTHER_ADDRESS:
4189 used_in_set = &reload_reg_used_in_other_addr;
4193 case RELOAD_FOR_INPUT:
4194 used_in_set = &reload_reg_used_in_input[opnum];
4197 case RELOAD_FOR_OUTPUT:
4198 used_in_set = &reload_reg_used_in_output[opnum];
4201 case RELOAD_FOR_INSN:
4202 used_in_set = &reload_reg_used_in_insn;
4207 /* We resolve conflicts with remaining reloads of the same type by
4208 excluding the intervals of of reload registers by them from the
4209 interval of freed reload registers. Since we only keep track of
4210 one set of interval bounds, we might have to exclude somewhat
4211 more then what would be necessary if we used a HARD_REG_SET here.
4212 But this should only happen very infrequently, so there should
4213 be no reason to worry about it. */
4215 start_regno = regno;
4216 end_regno = regno + nregs;
4217 if (check_opnum || check_any)
4219 for (i = n_reloads - 1; i >= 0; i--)
4221 if (rld[i].when_needed == type
4222 && (check_any || rld[i].opnum == opnum)
4225 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4226 unsigned int conflict_end
4228 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4230 /* If there is an overlap with the first to-be-freed register,
4231 adjust the interval start. */
4232 if (conflict_start <= start_regno && conflict_end > start_regno)
4233 start_regno = conflict_end;
4234 /* Otherwise, if there is a conflict with one of the other
4235 to-be-freed registers, adjust the interval end. */
4236 if (conflict_start > start_regno && conflict_start < end_regno)
4237 end_regno = conflict_start;
4242 for (r = start_regno; r < end_regno; r++)
4243 CLEAR_HARD_REG_BIT (*used_in_set, r);
4246 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4247 specified by OPNUM and TYPE. */
4250 reload_reg_free_p (regno, opnum, type)
4253 enum reload_type type;
4257 /* In use for a RELOAD_OTHER means it's not available for anything. */
4258 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4259 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4265 /* In use for anything means we can't use it for RELOAD_OTHER. */
4266 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4267 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4268 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4271 for (i = 0; i < reload_n_operands; i++)
4272 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4273 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4274 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4275 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4276 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4277 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4282 case RELOAD_FOR_INPUT:
4283 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4284 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4287 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4290 /* If it is used for some other input, can't use it. */
4291 for (i = 0; i < reload_n_operands; i++)
4292 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4295 /* If it is used in a later operand's address, can't use it. */
4296 for (i = opnum + 1; i < reload_n_operands; i++)
4297 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4298 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4303 case RELOAD_FOR_INPUT_ADDRESS:
4304 /* Can't use a register if it is used for an input address for this
4305 operand or used as an input in an earlier one. */
4306 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4307 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4310 for (i = 0; i < opnum; i++)
4311 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4316 case RELOAD_FOR_INPADDR_ADDRESS:
4317 /* Can't use a register if it is used for an input address
4318 for this operand or used as an input in an earlier
4320 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4323 for (i = 0; i < opnum; i++)
4324 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4329 case RELOAD_FOR_OUTPUT_ADDRESS:
4330 /* Can't use a register if it is used for an output address for this
4331 operand or used as an output in this or a later operand. */
4332 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4335 for (i = opnum; i < reload_n_operands; i++)
4336 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4341 case RELOAD_FOR_OUTADDR_ADDRESS:
4342 /* Can't use a register if it is used for an output address
4343 for this operand or used as an output in this or a
4345 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4348 for (i = opnum; i < reload_n_operands; i++)
4349 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4354 case RELOAD_FOR_OPERAND_ADDRESS:
4355 for (i = 0; i < reload_n_operands; i++)
4356 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4359 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4360 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4362 case RELOAD_FOR_OPADDR_ADDR:
4363 for (i = 0; i < reload_n_operands; i++)
4364 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4367 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4369 case RELOAD_FOR_OUTPUT:
4370 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4371 outputs, or an operand address for this or an earlier output. */
4372 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4375 for (i = 0; i < reload_n_operands; i++)
4376 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4379 for (i = 0; i <= opnum; i++)
4380 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4381 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4386 case RELOAD_FOR_INSN:
4387 for (i = 0; i < reload_n_operands; i++)
4388 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4389 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4392 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4393 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4395 case RELOAD_FOR_OTHER_ADDRESS:
4396 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4401 /* Return 1 if the value in reload reg REGNO, as used by a reload
4402 needed for the part of the insn specified by OPNUM and TYPE,
4403 is still available in REGNO at the end of the insn.
4405 We can assume that the reload reg was already tested for availability
4406 at the time it is needed, and we should not check this again,
4407 in case the reg has already been marked in use. */
4410 reload_reg_reaches_end_p (regno, opnum, type)
4413 enum reload_type type;
4420 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4421 its value must reach the end. */
4424 /* If this use is for part of the insn,
4425 its value reaches if no subsequent part uses the same register.
4426 Just like the above function, don't try to do this with lots
4429 case RELOAD_FOR_OTHER_ADDRESS:
4430 /* Here we check for everything else, since these don't conflict
4431 with anything else and everything comes later. */
4433 for (i = 0; i < reload_n_operands; i++)
4434 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4435 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4436 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4437 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4438 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4439 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4442 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4443 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4444 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4446 case RELOAD_FOR_INPUT_ADDRESS:
4447 case RELOAD_FOR_INPADDR_ADDRESS:
4448 /* Similar, except that we check only for this and subsequent inputs
4449 and the address of only subsequent inputs and we do not need
4450 to check for RELOAD_OTHER objects since they are known not to
4453 for (i = opnum; i < reload_n_operands; i++)
4454 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4457 for (i = opnum + 1; i < reload_n_operands; i++)
4458 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4459 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4462 for (i = 0; i < reload_n_operands; i++)
4463 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4464 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4465 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4468 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4471 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4472 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4474 case RELOAD_FOR_INPUT:
4475 /* Similar to input address, except we start at the next operand for
4476 both input and input address and we do not check for
4477 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4480 for (i = opnum + 1; i < reload_n_operands; i++)
4481 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4482 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4483 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4486 /* ... fall through ... */
4488 case RELOAD_FOR_OPERAND_ADDRESS:
4489 /* Check outputs and their addresses. */
4491 for (i = 0; i < reload_n_operands; i++)
4492 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4493 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4494 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4499 case RELOAD_FOR_OPADDR_ADDR:
4500 for (i = 0; i < reload_n_operands; i++)
4501 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4502 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4503 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4506 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4507 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4509 case RELOAD_FOR_INSN:
4510 /* These conflict with other outputs with RELOAD_OTHER. So
4511 we need only check for output addresses. */
4515 /* ... fall through ... */
4517 case RELOAD_FOR_OUTPUT:
4518 case RELOAD_FOR_OUTPUT_ADDRESS:
4519 case RELOAD_FOR_OUTADDR_ADDRESS:
4520 /* We already know these can't conflict with a later output. So the
4521 only thing to check are later output addresses. */
4522 for (i = opnum + 1; i < reload_n_operands; i++)
4523 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4524 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4533 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4536 This function uses the same algorithm as reload_reg_free_p above. */
4539 reloads_conflict (r1, r2)
4542 enum reload_type r1_type = rld[r1].when_needed;
4543 enum reload_type r2_type = rld[r2].when_needed;
4544 int r1_opnum = rld[r1].opnum;
4545 int r2_opnum = rld[r2].opnum;
4547 /* RELOAD_OTHER conflicts with everything. */
4548 if (r2_type == RELOAD_OTHER)
4551 /* Otherwise, check conflicts differently for each type. */
4555 case RELOAD_FOR_INPUT:
4556 return (r2_type == RELOAD_FOR_INSN
4557 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4558 || r2_type == RELOAD_FOR_OPADDR_ADDR
4559 || r2_type == RELOAD_FOR_INPUT
4560 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4561 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4562 && r2_opnum > r1_opnum));
4564 case RELOAD_FOR_INPUT_ADDRESS:
4565 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4566 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4568 case RELOAD_FOR_INPADDR_ADDRESS:
4569 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4570 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4572 case RELOAD_FOR_OUTPUT_ADDRESS:
4573 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4574 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4576 case RELOAD_FOR_OUTADDR_ADDRESS:
4577 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4578 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4580 case RELOAD_FOR_OPERAND_ADDRESS:
4581 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4582 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4584 case RELOAD_FOR_OPADDR_ADDR:
4585 return (r2_type == RELOAD_FOR_INPUT
4586 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4588 case RELOAD_FOR_OUTPUT:
4589 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4590 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4591 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4592 && r2_opnum <= r1_opnum));
4594 case RELOAD_FOR_INSN:
4595 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4596 || r2_type == RELOAD_FOR_INSN
4597 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4599 case RELOAD_FOR_OTHER_ADDRESS:
4600 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4610 /* Indexed by reload number, 1 if incoming value
4611 inherited from previous insns. */
4612 char reload_inherited[MAX_RELOADS];
4614 /* For an inherited reload, this is the insn the reload was inherited from,
4615 if we know it. Otherwise, this is 0. */
4616 rtx reload_inheritance_insn[MAX_RELOADS];
4618 /* If non-zero, this is a place to get the value of the reload,
4619 rather than using reload_in. */
4620 rtx reload_override_in[MAX_RELOADS];
4622 /* For each reload, the hard register number of the register used,
4623 or -1 if we did not need a register for this reload. */
4624 int reload_spill_index[MAX_RELOADS];
4626 /* Return 1 if the value in reload reg REGNO, as used by a reload
4627 needed for the part of the insn specified by OPNUM and TYPE,
4628 may be used to load VALUE into it.
4630 Other read-only reloads with the same value do not conflict
4631 unless OUT is non-zero and these other reloads have to live while
4632 output reloads live.
4633 If OUT is CONST0_RTX, this is a special case: it means that the
4634 test should not be for using register REGNO as reload register, but
4635 for copying from register REGNO into the reload register.
4637 RELOADNUM is the number of the reload we want to load this value for;
4638 a reload does not conflict with itself.
4640 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4641 reloads that load an address for the very reload we are considering.
4643 The caller has to make sure that there is no conflict with the return
4646 reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum,
4647 ignore_address_reloads)
4650 enum reload_type type;
4653 int ignore_address_reloads;
4656 /* Set if we see an input reload that must not share its reload register
4657 with any new earlyclobber, but might otherwise share the reload
4658 register with an output or input-output reload. */
4659 int check_earlyclobber = 0;
4663 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4666 if (out == const0_rtx)
4672 /* We use some pseudo 'time' value to check if the lifetimes of the
4673 new register use would overlap with the one of a previous reload
4674 that is not read-only or uses a different value.
4675 The 'time' used doesn't have to be linear in any shape or form, just
4677 Some reload types use different 'buckets' for each operand.
4678 So there are MAX_RECOG_OPERANDS different time values for each
4680 We compute TIME1 as the time when the register for the prospective
4681 new reload ceases to be live, and TIME2 for each existing
4682 reload as the time when that the reload register of that reload
4684 Where there is little to be gained by exact lifetime calculations,
4685 we just make conservative assumptions, i.e. a longer lifetime;
4686 this is done in the 'default:' cases. */
4689 case RELOAD_FOR_OTHER_ADDRESS:
4690 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4691 time1 = copy ? 0 : 1;
4694 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4696 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4697 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4698 respectively, to the time values for these, we get distinct time
4699 values. To get distinct time values for each operand, we have to
4700 multiply opnum by at least three. We round that up to four because
4701 multiply by four is often cheaper. */
4702 case RELOAD_FOR_INPADDR_ADDRESS:
4703 time1 = opnum * 4 + 2;
4705 case RELOAD_FOR_INPUT_ADDRESS:
4706 time1 = opnum * 4 + 3;
4708 case RELOAD_FOR_INPUT:
4709 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4710 executes (inclusive). */
4711 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4713 case RELOAD_FOR_OPADDR_ADDR:
4715 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4716 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4718 case RELOAD_FOR_OPERAND_ADDRESS:
4719 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4721 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4723 case RELOAD_FOR_OUTADDR_ADDRESS:
4724 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4726 case RELOAD_FOR_OUTPUT_ADDRESS:
4727 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4730 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4733 for (i = 0; i < n_reloads; i++)
4735 rtx reg = rld[i].reg_rtx;
4736 if (reg && GET_CODE (reg) == REG
4737 && ((unsigned) regno - true_regnum (reg)
4738 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
4741 if (! rld[i].in || ! rtx_equal_p (rld[i].in, value)
4742 || rld[i].out || out)
4745 switch (rld[i].when_needed)
4747 case RELOAD_FOR_OTHER_ADDRESS:
4750 case RELOAD_FOR_INPADDR_ADDRESS:
4751 /* find_reloads makes sure that a
4752 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4753 by at most one - the first -
4754 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4755 address reload is inherited, the address address reload
4756 goes away, so we can ignore this conflict. */
4757 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4758 && ignore_address_reloads
4759 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4760 Then the address address is still needed to store
4761 back the new address. */
4762 && ! rld[reloadnum].out)
4764 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4765 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4767 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4768 && ignore_address_reloads
4769 /* Unless we are reloading an auto_inc expression. */
4770 && ! rld[reloadnum].out)
4772 time2 = rld[i].opnum * 4 + 2;
4774 case RELOAD_FOR_INPUT_ADDRESS:
4775 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4776 && ignore_address_reloads
4777 && ! rld[reloadnum].out)
4779 time2 = rld[i].opnum * 4 + 3;
4781 case RELOAD_FOR_INPUT:
4782 time2 = rld[i].opnum * 4 + 4;
4783 check_earlyclobber = 1;
4785 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4786 == MAX_RECOG_OPERAND * 4 */
4787 case RELOAD_FOR_OPADDR_ADDR:
4788 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4789 && ignore_address_reloads
4790 && ! rld[reloadnum].out)
4792 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4794 case RELOAD_FOR_OPERAND_ADDRESS:
4795 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4796 check_earlyclobber = 1;
4798 case RELOAD_FOR_INSN:
4799 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4801 case RELOAD_FOR_OUTPUT:
4802 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4803 instruction is executed. */
4804 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4806 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4807 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4809 case RELOAD_FOR_OUTADDR_ADDRESS:
4810 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4811 && ignore_address_reloads
4812 && ! rld[reloadnum].out)
4814 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4816 case RELOAD_FOR_OUTPUT_ADDRESS:
4817 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4820 /* If there is no conflict in the input part, handle this
4821 like an output reload. */
4822 if (! rld[i].in || rtx_equal_p (rld[i].in, value))
4824 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4825 /* Earlyclobbered outputs must conflict with inputs. */
4826 if (earlyclobber_operand_p (rld[i].out))
4827 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4832 /* RELOAD_OTHER might be live beyond instruction execution,
4833 but this is not obvious when we set time2 = 1. So check
4834 here if there might be a problem with the new reload
4835 clobbering the register used by the RELOAD_OTHER. */
4843 && (! rld[i].in || rld[i].out
4844 || ! rtx_equal_p (rld[i].in, value)))
4845 || (out && rld[reloadnum].out_reg
4846 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4852 /* Earlyclobbered outputs must conflict with inputs. */
4853 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4859 /* Give an error message saying we failed to find a reload for INSN,
4860 and clear out reload R. */
4862 failed_reload (insn, r)
4866 if (asm_noperands (PATTERN (insn)) < 0)
4867 /* It's the compiler's fault. */
4868 fatal_insn ("Could not find a spill register", insn);
4870 /* It's the user's fault; the operand's mode and constraint
4871 don't match. Disable this reload so we don't crash in final. */
4872 error_for_asm (insn,
4873 "`asm' operand constraint incompatible with operand size");
4877 rld[r].optional = 1;
4878 rld[r].secondary_p = 1;
4881 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
4882 for reload R. If it's valid, get an rtx for it. Return nonzero if
4885 set_reload_reg (i, r)
4889 rtx reg = spill_reg_rtx[i];
4891 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
4892 spill_reg_rtx[i] = reg
4893 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
4895 regno = true_regnum (reg);
4897 /* Detect when the reload reg can't hold the reload mode.
4898 This used to be one `if', but Sequent compiler can't handle that. */
4899 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
4901 enum machine_mode test_mode = VOIDmode;
4903 test_mode = GET_MODE (rld[r].in);
4904 /* If rld[r].in has VOIDmode, it means we will load it
4905 in whatever mode the reload reg has: to wit, rld[r].mode.
4906 We have already tested that for validity. */
4907 /* Aside from that, we need to test that the expressions
4908 to reload from or into have modes which are valid for this
4909 reload register. Otherwise the reload insns would be invalid. */
4910 if (! (rld[r].in != 0 && test_mode != VOIDmode
4911 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
4912 if (! (rld[r].out != 0
4913 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
4915 /* The reg is OK. */
4918 /* Mark as in use for this insn the reload regs we use
4920 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
4921 rld[r].when_needed, rld[r].mode);
4923 rld[r].reg_rtx = reg;
4924 reload_spill_index[r] = spill_regs[i];
4931 /* Find a spill register to use as a reload register for reload R.
4932 LAST_RELOAD is non-zero if this is the last reload for the insn being
4935 Set rld[R].reg_rtx to the register allocated.
4937 We return 1 if successful, or 0 if we couldn't find a spill reg and
4938 we didn't change anything. */
4941 allocate_reload_reg (chain, r, last_reload)
4942 struct insn_chain *chain ATTRIBUTE_UNUSED;
4948 /* If we put this reload ahead, thinking it is a group,
4949 then insist on finding a group. Otherwise we can grab a
4950 reg that some other reload needs.
4951 (That can happen when we have a 68000 DATA_OR_FP_REG
4952 which is a group of data regs or one fp reg.)
4953 We need not be so restrictive if there are no more reloads
4956 ??? Really it would be nicer to have smarter handling
4957 for that kind of reg class, where a problem like this is normal.
4958 Perhaps those classes should be avoided for reloading
4959 by use of more alternatives. */
4961 int force_group = rld[r].nregs > 1 && ! last_reload;
4963 /* If we want a single register and haven't yet found one,
4964 take any reg in the right class and not in use.
4965 If we want a consecutive group, here is where we look for it.
4967 We use two passes so we can first look for reload regs to
4968 reuse, which are already in use for other reloads in this insn,
4969 and only then use additional registers.
4970 I think that maximizing reuse is needed to make sure we don't
4971 run out of reload regs. Suppose we have three reloads, and
4972 reloads A and B can share regs. These need two regs.
4973 Suppose A and B are given different regs.
4974 That leaves none for C. */
4975 for (pass = 0; pass < 2; pass++)
4977 /* I is the index in spill_regs.
4978 We advance it round-robin between insns to use all spill regs
4979 equally, so that inherited reloads have a chance
4980 of leapfrogging each other. */
4984 for (count = 0; count < n_spills; count++)
4986 int class = (int) rld[r].class;
4992 regnum = spill_regs[i];
4994 if ((reload_reg_free_p (regnum, rld[r].opnum,
4997 /* We check reload_reg_used to make sure we
4998 don't clobber the return register. */
4999 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5000 && reload_reg_free_for_value_p (regnum,
5005 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5006 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5007 /* Look first for regs to share, then for unshared. But
5008 don't share regs used for inherited reloads; they are
5009 the ones we want to preserve. */
5011 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5013 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5016 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5017 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5018 (on 68000) got us two FP regs. If NR is 1,
5019 we would reject both of them. */
5022 /* If we need only one reg, we have already won. */
5025 /* But reject a single reg if we demand a group. */
5030 /* Otherwise check that as many consecutive regs as we need
5031 are available here. */
5034 int regno = regnum + nr - 1;
5035 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5036 && spill_reg_order[regno] >= 0
5037 && reload_reg_free_p (regno, rld[r].opnum,
5038 rld[r].when_needed)))
5047 /* If we found something on pass 1, omit pass 2. */
5048 if (count < n_spills)
5052 /* We should have found a spill register by now. */
5053 if (count >= n_spills)
5056 /* I is the index in SPILL_REG_RTX of the reload register we are to
5057 allocate. Get an rtx for it and find its register number. */
5059 return set_reload_reg (i, r);
5062 /* Initialize all the tables needed to allocate reload registers.
5063 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5064 is the array we use to restore the reg_rtx field for every reload. */
5066 choose_reload_regs_init (chain, save_reload_reg_rtx)
5067 struct insn_chain *chain;
5068 rtx *save_reload_reg_rtx;
5072 for (i = 0; i < n_reloads; i++)
5073 rld[i].reg_rtx = save_reload_reg_rtx[i];
5075 bzero (reload_inherited, MAX_RELOADS);
5076 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
5077 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
5079 CLEAR_HARD_REG_SET (reload_reg_used);
5080 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5081 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5082 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5083 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5084 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5086 CLEAR_HARD_REG_SET (reg_used_in_insn);
5089 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5090 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5091 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5092 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5093 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5094 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5096 for (i = 0; i < reload_n_operands; i++)
5098 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5099 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5100 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5101 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5102 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5103 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5106 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5108 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5110 for (i = 0; i < n_reloads; i++)
5111 /* If we have already decided to use a certain register,
5112 don't use it in another way. */
5114 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5115 rld[i].when_needed, rld[i].mode);
5118 /* Assign hard reg targets for the pseudo-registers we must reload
5119 into hard regs for this insn.
5120 Also output the instructions to copy them in and out of the hard regs.
5122 For machines with register classes, we are responsible for
5123 finding a reload reg in the proper class. */
5126 choose_reload_regs (chain)
5127 struct insn_chain *chain;
5129 rtx insn = chain->insn;
5131 unsigned int max_group_size = 1;
5132 enum reg_class group_class = NO_REGS;
5133 int pass, win, inheritance;
5135 rtx save_reload_reg_rtx[MAX_RELOADS];
5137 /* In order to be certain of getting the registers we need,
5138 we must sort the reloads into order of increasing register class.
5139 Then our grabbing of reload registers will parallel the process
5140 that provided the reload registers.
5142 Also note whether any of the reloads wants a consecutive group of regs.
5143 If so, record the maximum size of the group desired and what
5144 register class contains all the groups needed by this insn. */
5146 for (j = 0; j < n_reloads; j++)
5148 reload_order[j] = j;
5149 reload_spill_index[j] = -1;
5151 if (rld[j].nregs > 1)
5153 max_group_size = MAX (rld[j].nregs, max_group_size);
5155 = reg_class_superunion[(int)rld[j].class][(int)group_class];
5158 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5162 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5164 /* If -O, try first with inheritance, then turning it off.
5165 If not -O, don't do inheritance.
5166 Using inheritance when not optimizing leads to paradoxes
5167 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5168 because one side of the comparison might be inherited. */
5170 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5172 choose_reload_regs_init (chain, save_reload_reg_rtx);
5174 /* Process the reloads in order of preference just found.
5175 Beyond this point, subregs can be found in reload_reg_rtx.
5177 This used to look for an existing reloaded home for all of the
5178 reloads, and only then perform any new reloads. But that could lose
5179 if the reloads were done out of reg-class order because a later
5180 reload with a looser constraint might have an old home in a register
5181 needed by an earlier reload with a tighter constraint.
5183 To solve this, we make two passes over the reloads, in the order
5184 described above. In the first pass we try to inherit a reload
5185 from a previous insn. If there is a later reload that needs a
5186 class that is a proper subset of the class being processed, we must
5187 also allocate a spill register during the first pass.
5189 Then make a second pass over the reloads to allocate any reloads
5190 that haven't been given registers yet. */
5192 for (j = 0; j < n_reloads; j++)
5194 register int r = reload_order[j];
5195 rtx search_equiv = NULL_RTX;
5197 /* Ignore reloads that got marked inoperative. */
5198 if (rld[r].out == 0 && rld[r].in == 0
5199 && ! rld[r].secondary_p)
5202 /* If find_reloads chose to use reload_in or reload_out as a reload
5203 register, we don't need to chose one. Otherwise, try even if it
5204 found one since we might save an insn if we find the value lying
5206 Try also when reload_in is a pseudo without a hard reg. */
5207 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5208 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5209 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5210 && GET_CODE (rld[r].in) != MEM
5211 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5214 #if 0 /* No longer needed for correct operation.
5215 It might give better code, or might not; worth an experiment? */
5216 /* If this is an optional reload, we can't inherit from earlier insns
5217 until we are sure that any non-optional reloads have been allocated.
5218 The following code takes advantage of the fact that optional reloads
5219 are at the end of reload_order. */
5220 if (rld[r].optional != 0)
5221 for (i = 0; i < j; i++)
5222 if ((rld[reload_order[i]].out != 0
5223 || rld[reload_order[i]].in != 0
5224 || rld[reload_order[i]].secondary_p)
5225 && ! rld[reload_order[i]].optional
5226 && rld[reload_order[i]].reg_rtx == 0)
5227 allocate_reload_reg (chain, reload_order[i], 0);
5230 /* First see if this pseudo is already available as reloaded
5231 for a previous insn. We cannot try to inherit for reloads
5232 that are smaller than the maximum number of registers needed
5233 for groups unless the register we would allocate cannot be used
5236 We could check here to see if this is a secondary reload for
5237 an object that is already in a register of the desired class.
5238 This would avoid the need for the secondary reload register.
5239 But this is complex because we can't easily determine what
5240 objects might want to be loaded via this reload. So let a
5241 register be allocated here. In `emit_reload_insns' we suppress
5242 one of the loads in the case described above. */
5247 register int regno = -1;
5248 enum machine_mode mode = VOIDmode;
5252 else if (GET_CODE (rld[r].in) == REG)
5254 regno = REGNO (rld[r].in);
5255 mode = GET_MODE (rld[r].in);
5257 else if (GET_CODE (rld[r].in_reg) == REG)
5259 regno = REGNO (rld[r].in_reg);
5260 mode = GET_MODE (rld[r].in_reg);
5262 else if (GET_CODE (rld[r].in_reg) == SUBREG
5263 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5265 word = SUBREG_WORD (rld[r].in_reg);
5266 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5267 if (regno < FIRST_PSEUDO_REGISTER)
5269 mode = GET_MODE (rld[r].in_reg);
5272 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5273 || GET_CODE (rld[r].in_reg) == PRE_DEC
5274 || GET_CODE (rld[r].in_reg) == POST_INC
5275 || GET_CODE (rld[r].in_reg) == POST_DEC)
5276 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5278 regno = REGNO (XEXP (rld[r].in_reg, 0));
5279 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5280 rld[r].out = rld[r].in;
5284 /* This won't work, since REGNO can be a pseudo reg number.
5285 Also, it takes much more hair to keep track of all the things
5286 that can invalidate an inherited reload of part of a pseudoreg. */
5287 else if (GET_CODE (rld[r].in) == SUBREG
5288 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5289 regno = REGNO (SUBREG_REG (rld[r].in)) + SUBREG_WORD (rld[r].in);
5292 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5294 enum reg_class class = rld[r].class, last_class;
5295 rtx last_reg = reg_last_reload_reg[regno];
5297 i = REGNO (last_reg) + word;
5298 last_class = REGNO_REG_CLASS (i);
5299 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5300 >= GET_MODE_SIZE (mode) + word * UNITS_PER_WORD)
5301 && reg_reloaded_contents[i] == regno
5302 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5303 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5304 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5305 /* Even if we can't use this register as a reload
5306 register, we might use it for reload_override_in,
5307 if copying it to the desired class is cheap
5309 || ((REGISTER_MOVE_COST (last_class, class)
5310 < MEMORY_MOVE_COST (mode, class, 1))
5311 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5312 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5316 #ifdef SECONDARY_MEMORY_NEEDED
5317 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5322 && (rld[r].nregs == max_group_size
5323 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5325 && reload_reg_free_for_value_p (i, rld[r].opnum,
5330 /* If a group is needed, verify that all the subsequent
5331 registers still have their values intact. */
5333 = HARD_REGNO_NREGS (i, rld[r].mode);
5336 for (k = 1; k < nr; k++)
5337 if (reg_reloaded_contents[i + k] != regno
5338 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5345 last_reg = (GET_MODE (last_reg) == mode
5346 ? last_reg : gen_rtx_REG (mode, i));
5348 /* We found a register that contains the
5349 value we need. If this register is the
5350 same as an `earlyclobber' operand of the
5351 current insn, just mark it as a place to
5352 reload from since we can't use it as the
5353 reload register itself. */
5355 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5356 if (reg_overlap_mentioned_for_reload_p
5357 (reg_last_reload_reg[regno],
5358 reload_earlyclobbers[i1]))
5361 if (i1 != n_earlyclobbers
5362 || ! (reload_reg_free_for_value_p
5363 (i, rld[r].opnum, rld[r].when_needed,
5364 rld[r].in, rld[r].out, r, 1))
5365 /* Don't use it if we'd clobber a pseudo reg. */
5366 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5368 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5369 /* Don't clobber the frame pointer. */
5370 || (i == HARD_FRAME_POINTER_REGNUM && rld[r].out)
5371 /* Don't really use the inherited spill reg
5372 if we need it wider than we've got it. */
5373 || (GET_MODE_SIZE (rld[r].mode)
5374 > GET_MODE_SIZE (mode))
5375 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5378 /* If find_reloads chose reload_out as reload
5379 register, stay with it - that leaves the
5380 inherited register for subsequent reloads. */
5381 || (rld[r].out && rld[r].reg_rtx
5382 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5384 reload_override_in[r] = last_reg;
5385 reload_inheritance_insn[r]
5386 = reg_reloaded_insn[i];
5391 /* We can use this as a reload reg. */
5392 /* Mark the register as in use for this part of
5394 mark_reload_reg_in_use (i,
5398 rld[r].reg_rtx = last_reg;
5399 reload_inherited[r] = 1;
5400 reload_inheritance_insn[r]
5401 = reg_reloaded_insn[i];
5402 reload_spill_index[r] = i;
5403 for (k = 0; k < nr; k++)
5404 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5412 /* Here's another way to see if the value is already lying around. */
5415 && ! reload_inherited[r]
5417 && (CONSTANT_P (rld[r].in)
5418 || GET_CODE (rld[r].in) == PLUS
5419 || GET_CODE (rld[r].in) == REG
5420 || GET_CODE (rld[r].in) == MEM)
5421 && (rld[r].nregs == max_group_size
5422 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5423 search_equiv = rld[r].in;
5424 /* If this is an output reload from a simple move insn, look
5425 if an equivalence for the input is available. */
5426 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5428 rtx set = single_set (insn);
5431 && rtx_equal_p (rld[r].out, SET_DEST (set))
5432 && CONSTANT_P (SET_SRC (set)))
5433 search_equiv = SET_SRC (set);
5439 = find_equiv_reg (search_equiv, insn, rld[r].class,
5440 -1, NULL_PTR, 0, rld[r].mode);
5445 if (GET_CODE (equiv) == REG)
5446 regno = REGNO (equiv);
5447 else if (GET_CODE (equiv) == SUBREG)
5449 /* This must be a SUBREG of a hard register.
5450 Make a new REG since this might be used in an
5451 address and not all machines support SUBREGs
5453 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
5454 equiv = gen_rtx_REG (rld[r].mode, regno);
5460 /* If we found a spill reg, reject it unless it is free
5461 and of the desired class. */
5463 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5464 && ! reload_reg_free_for_value_p (regno, rld[r].opnum,
5468 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5472 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5475 /* We found a register that contains the value we need.
5476 If this register is the same as an `earlyclobber' operand
5477 of the current insn, just mark it as a place to reload from
5478 since we can't use it as the reload register itself. */
5481 for (i = 0; i < n_earlyclobbers; i++)
5482 if (reg_overlap_mentioned_for_reload_p (equiv,
5483 reload_earlyclobbers[i]))
5485 reload_override_in[r] = equiv;
5490 /* If the equiv register we have found is explicitly clobbered
5491 in the current insn, it depends on the reload type if we
5492 can use it, use it for reload_override_in, or not at all.
5493 In particular, we then can't use EQUIV for a
5494 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5496 if (equiv != 0 && regno_clobbered_p (regno, insn))
5498 switch (rld[r].when_needed)
5500 case RELOAD_FOR_OTHER_ADDRESS:
5501 case RELOAD_FOR_INPADDR_ADDRESS:
5502 case RELOAD_FOR_INPUT_ADDRESS:
5503 case RELOAD_FOR_OPADDR_ADDR:
5506 case RELOAD_FOR_INPUT:
5507 case RELOAD_FOR_OPERAND_ADDRESS:
5508 reload_override_in[r] = equiv;
5516 /* If we found an equivalent reg, say no code need be generated
5517 to load it, and use it as our reload reg. */
5518 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5520 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5522 rld[r].reg_rtx = equiv;
5523 reload_inherited[r] = 1;
5525 /* If reg_reloaded_valid is not set for this register,
5526 there might be a stale spill_reg_store lying around.
5527 We must clear it, since otherwise emit_reload_insns
5528 might delete the store. */
5529 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5530 spill_reg_store[regno] = NULL_RTX;
5531 /* If any of the hard registers in EQUIV are spill
5532 registers, mark them as in use for this insn. */
5533 for (k = 0; k < nr; k++)
5535 i = spill_reg_order[regno + k];
5538 mark_reload_reg_in_use (regno, rld[r].opnum,
5541 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5548 /* If we found a register to use already, or if this is an optional
5549 reload, we are done. */
5550 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5553 #if 0 /* No longer needed for correct operation. Might or might not
5554 give better code on the average. Want to experiment? */
5556 /* See if there is a later reload that has a class different from our
5557 class that intersects our class or that requires less register
5558 than our reload. If so, we must allocate a register to this
5559 reload now, since that reload might inherit a previous reload
5560 and take the only available register in our class. Don't do this
5561 for optional reloads since they will force all previous reloads
5562 to be allocated. Also don't do this for reloads that have been
5565 for (i = j + 1; i < n_reloads; i++)
5567 int s = reload_order[i];
5569 if ((rld[s].in == 0 && rld[s].out == 0
5570 && ! rld[s].secondary_p)
5574 if ((rld[s].class != rld[r].class
5575 && reg_classes_intersect_p (rld[r].class,
5577 || rld[s].nregs < rld[r].nregs)
5584 allocate_reload_reg (chain, r, j == n_reloads - 1);
5588 /* Now allocate reload registers for anything non-optional that
5589 didn't get one yet. */
5590 for (j = 0; j < n_reloads; j++)
5592 register int r = reload_order[j];
5594 /* Ignore reloads that got marked inoperative. */
5595 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5598 /* Skip reloads that already have a register allocated or are
5600 if (rld[r].reg_rtx != 0 || rld[r].optional)
5603 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5607 /* If that loop got all the way, we have won. */
5614 /* Loop around and try without any inheritance. */
5619 /* First undo everything done by the failed attempt
5620 to allocate with inheritance. */
5621 choose_reload_regs_init (chain, save_reload_reg_rtx);
5623 /* Some sanity tests to verify that the reloads found in the first
5624 pass are identical to the ones we have now. */
5625 if (chain->n_reloads != n_reloads)
5628 for (i = 0; i < n_reloads; i++)
5630 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5632 if (chain->rld[i].when_needed != rld[i].when_needed)
5634 for (j = 0; j < n_spills; j++)
5635 if (spill_regs[j] == chain->rld[i].regno)
5636 if (! set_reload_reg (j, i))
5637 failed_reload (chain->insn, i);
5641 /* If we thought we could inherit a reload, because it seemed that
5642 nothing else wanted the same reload register earlier in the insn,
5643 verify that assumption, now that all reloads have been assigned.
5644 Likewise for reloads where reload_override_in has been set. */
5646 /* If doing expensive optimizations, do one preliminary pass that doesn't
5647 cancel any inheritance, but removes reloads that have been needed only
5648 for reloads that we know can be inherited. */
5649 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5651 for (j = 0; j < n_reloads; j++)
5653 register int r = reload_order[j];
5655 if (reload_inherited[r] && rld[r].reg_rtx)
5656 check_reg = rld[r].reg_rtx;
5657 else if (reload_override_in[r]
5658 && (GET_CODE (reload_override_in[r]) == REG
5659 || GET_CODE (reload_override_in[r]) == SUBREG))
5660 check_reg = reload_override_in[r];
5663 if (! reload_reg_free_for_value_p (true_regnum (check_reg),
5667 (reload_inherited[r]
5668 ? rld[r].out : const0_rtx),
5673 reload_inherited[r] = 0;
5674 reload_override_in[r] = 0;
5676 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5677 reload_override_in, then we do not need its related
5678 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5679 likewise for other reload types.
5680 We handle this by removing a reload when its only replacement
5681 is mentioned in reload_in of the reload we are going to inherit.
5682 A special case are auto_inc expressions; even if the input is
5683 inherited, we still need the address for the output. We can
5684 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5685 If we suceeded removing some reload and we are doing a preliminary
5686 pass just to remove such reloads, make another pass, since the
5687 removal of one reload might allow us to inherit another one. */
5689 && rld[r].out != rld[r].in
5690 && remove_address_replacements (rld[r].in) && pass)
5695 /* Now that reload_override_in is known valid,
5696 actually override reload_in. */
5697 for (j = 0; j < n_reloads; j++)
5698 if (reload_override_in[j])
5699 rld[j].in = reload_override_in[j];
5701 /* If this reload won't be done because it has been cancelled or is
5702 optional and not inherited, clear reload_reg_rtx so other
5703 routines (such as subst_reloads) don't get confused. */
5704 for (j = 0; j < n_reloads; j++)
5705 if (rld[j].reg_rtx != 0
5706 && ((rld[j].optional && ! reload_inherited[j])
5707 || (rld[j].in == 0 && rld[j].out == 0
5708 && ! rld[j].secondary_p)))
5710 int regno = true_regnum (rld[j].reg_rtx);
5712 if (spill_reg_order[regno] >= 0)
5713 clear_reload_reg_in_use (regno, rld[j].opnum,
5714 rld[j].when_needed, rld[j].mode);
5716 reload_spill_index[j] = -1;
5719 /* Record which pseudos and which spill regs have output reloads. */
5720 for (j = 0; j < n_reloads; j++)
5722 register int r = reload_order[j];
5724 i = reload_spill_index[r];
5726 /* I is nonneg if this reload uses a register.
5727 If rld[r].reg_rtx is 0, this is an optional reload
5728 that we opted to ignore. */
5729 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5730 && rld[r].reg_rtx != 0)
5732 register int nregno = REGNO (rld[r].out_reg);
5735 if (nregno < FIRST_PSEUDO_REGISTER)
5736 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5739 reg_has_output_reload[nregno + nr] = 1;
5743 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5745 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5748 if (rld[r].when_needed != RELOAD_OTHER
5749 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5750 && rld[r].when_needed != RELOAD_FOR_INSN)
5756 /* Deallocate the reload register for reload R. This is called from
5757 remove_address_replacements. */
5760 deallocate_reload_reg (r)
5765 if (! rld[r].reg_rtx)
5767 regno = true_regnum (rld[r].reg_rtx);
5769 if (spill_reg_order[regno] >= 0)
5770 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5772 reload_spill_index[r] = -1;
5775 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
5776 reloads of the same item for fear that we might not have enough reload
5777 registers. However, normally they will get the same reload register
5778 and hence actually need not be loaded twice.
5780 Here we check for the most common case of this phenomenon: when we have
5781 a number of reloads for the same object, each of which were allocated
5782 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5783 reload, and is not modified in the insn itself. If we find such,
5784 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5785 This will not increase the number of spill registers needed and will
5786 prevent redundant code. */
5789 merge_assigned_reloads (insn)
5794 /* Scan all the reloads looking for ones that only load values and
5795 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5796 assigned and not modified by INSN. */
5798 for (i = 0; i < n_reloads; i++)
5800 int conflicting_input = 0;
5801 int max_input_address_opnum = -1;
5802 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
5804 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
5805 || rld[i].out != 0 || rld[i].reg_rtx == 0
5806 || reg_set_p (rld[i].reg_rtx, insn))
5809 /* Look at all other reloads. Ensure that the only use of this
5810 reload_reg_rtx is in a reload that just loads the same value
5811 as we do. Note that any secondary reloads must be of the identical
5812 class since the values, modes, and result registers are the
5813 same, so we need not do anything with any secondary reloads. */
5815 for (j = 0; j < n_reloads; j++)
5817 if (i == j || rld[j].reg_rtx == 0
5818 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
5822 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5823 && rld[j].opnum > max_input_address_opnum)
5824 max_input_address_opnum = rld[j].opnum;
5826 /* If the reload regs aren't exactly the same (e.g, different modes)
5827 or if the values are different, we can't merge this reload.
5828 But if it is an input reload, we might still merge
5829 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
5831 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5832 || rld[j].out != 0 || rld[j].in == 0
5833 || ! rtx_equal_p (rld[i].in, rld[j].in))
5835 if (rld[j].when_needed != RELOAD_FOR_INPUT
5836 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
5837 || rld[i].opnum > rld[j].opnum)
5838 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
5840 conflicting_input = 1;
5841 if (min_conflicting_input_opnum > rld[j].opnum)
5842 min_conflicting_input_opnum = rld[j].opnum;
5846 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5847 we, in fact, found any matching reloads. */
5850 && max_input_address_opnum <= min_conflicting_input_opnum)
5852 for (j = 0; j < n_reloads; j++)
5853 if (i != j && rld[j].reg_rtx != 0
5854 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5855 && (! conflicting_input
5856 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5857 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
5859 rld[i].when_needed = RELOAD_OTHER;
5861 reload_spill_index[j] = -1;
5862 transfer_replacements (i, j);
5865 /* If this is now RELOAD_OTHER, look for any reloads that load
5866 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
5867 if they were for inputs, RELOAD_OTHER for outputs. Note that
5868 this test is equivalent to looking for reloads for this operand
5871 if (rld[i].when_needed == RELOAD_OTHER)
5872 for (j = 0; j < n_reloads; j++)
5874 && rld[i].when_needed != RELOAD_OTHER
5875 && reg_overlap_mentioned_for_reload_p (rld[j].in,
5878 = ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
5879 || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
5880 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
5886 /* These arrays are filled by emit_reload_insns and its subroutines. */
5887 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
5888 static rtx other_input_address_reload_insns = 0;
5889 static rtx other_input_reload_insns = 0;
5890 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
5891 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
5892 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
5893 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
5894 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
5895 static rtx operand_reload_insns = 0;
5896 static rtx other_operand_reload_insns = 0;
5897 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
5899 /* Values to be put in spill_reg_store are put here first. */
5900 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
5901 static HARD_REG_SET reg_reloaded_died;
5903 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
5904 has the number J. OLD contains the value to be used as input. */
5907 emit_input_reload_insns (chain, rl, old, j)
5908 struct insn_chain *chain;
5913 rtx insn = chain->insn;
5914 register rtx reloadreg = rl->reg_rtx;
5915 rtx oldequiv_reg = 0;
5918 enum machine_mode mode;
5921 /* Determine the mode to reload in.
5922 This is very tricky because we have three to choose from.
5923 There is the mode the insn operand wants (rl->inmode).
5924 There is the mode of the reload register RELOADREG.
5925 There is the intrinsic mode of the operand, which we could find
5926 by stripping some SUBREGs.
5927 It turns out that RELOADREG's mode is irrelevant:
5928 we can change that arbitrarily.
5930 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
5931 then the reload reg may not support QImode moves, so use SImode.
5932 If foo is in memory due to spilling a pseudo reg, this is safe,
5933 because the QImode value is in the least significant part of a
5934 slot big enough for a SImode. If foo is some other sort of
5935 memory reference, then it is impossible to reload this case,
5936 so previous passes had better make sure this never happens.
5938 Then consider a one-word union which has SImode and one of its
5939 members is a float, being fetched as (SUBREG:SF union:SI).
5940 We must fetch that as SFmode because we could be loading into
5941 a float-only register. In this case OLD's mode is correct.
5943 Consider an immediate integer: it has VOIDmode. Here we need
5944 to get a mode from something else.
5946 In some cases, there is a fourth mode, the operand's
5947 containing mode. If the insn specifies a containing mode for
5948 this operand, it overrides all others.
5950 I am not sure whether the algorithm here is always right,
5951 but it does the right things in those cases. */
5953 mode = GET_MODE (old);
5954 if (mode == VOIDmode)
5957 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5958 /* If we need a secondary register for this operation, see if
5959 the value is already in a register in that class. Don't
5960 do this if the secondary register will be used as a scratch
5963 if (rl->secondary_in_reload >= 0
5964 && rl->secondary_in_icode == CODE_FOR_nothing
5967 = find_equiv_reg (old, insn,
5968 rld[rl->secondary_in_reload].class,
5969 -1, NULL_PTR, 0, mode);
5972 /* If reloading from memory, see if there is a register
5973 that already holds the same value. If so, reload from there.
5974 We can pass 0 as the reload_reg_p argument because
5975 any other reload has either already been emitted,
5976 in which case find_equiv_reg will see the reload-insn,
5977 or has yet to be emitted, in which case it doesn't matter
5978 because we will use this equiv reg right away. */
5980 if (oldequiv == 0 && optimize
5981 && (GET_CODE (old) == MEM
5982 || (GET_CODE (old) == REG
5983 && REGNO (old) >= FIRST_PSEUDO_REGISTER
5984 && reg_renumber[REGNO (old)] < 0)))
5985 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
5986 -1, NULL_PTR, 0, mode);
5990 unsigned int regno = true_regnum (oldequiv);
5992 /* Don't use OLDEQUIV if any other reload changes it at an
5993 earlier stage of this insn or at this stage. */
5994 if (! reload_reg_free_for_value_p (regno, rl->opnum,
5996 rl->in, const0_rtx, j,
6000 /* If it is no cheaper to copy from OLDEQUIV into the
6001 reload register than it would be to move from memory,
6002 don't use it. Likewise, if we need a secondary register
6006 && ((REGNO_REG_CLASS (regno) != rl->class
6007 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
6009 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6010 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6011 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6015 #ifdef SECONDARY_MEMORY_NEEDED
6016 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6024 /* delete_output_reload is only invoked properly if old contains
6025 the original pseudo register. Since this is replaced with a
6026 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6027 find the pseudo in RELOAD_IN_REG. */
6029 && reload_override_in[j]
6030 && GET_CODE (rl->in_reg) == REG)
6037 else if (GET_CODE (oldequiv) == REG)
6038 oldequiv_reg = oldequiv;
6039 else if (GET_CODE (oldequiv) == SUBREG)
6040 oldequiv_reg = SUBREG_REG (oldequiv);
6042 /* If we are reloading from a register that was recently stored in
6043 with an output-reload, see if we can prove there was
6044 actually no need to store the old value in it. */
6046 if (optimize && GET_CODE (oldequiv) == REG
6047 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6048 && spill_reg_store[REGNO (oldequiv)]
6049 && GET_CODE (old) == REG
6050 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6051 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6053 delete_output_reload (insn, j, REGNO (oldequiv));
6055 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6056 then load RELOADREG from OLDEQUIV. Note that we cannot use
6057 gen_lowpart_common since it can do the wrong thing when
6058 RELOADREG has a multi-word mode. Note that RELOADREG
6059 must always be a REG here. */
6061 if (GET_MODE (reloadreg) != mode)
6062 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6063 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6064 oldequiv = SUBREG_REG (oldequiv);
6065 if (GET_MODE (oldequiv) != VOIDmode
6066 && mode != GET_MODE (oldequiv))
6067 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
6069 /* Switch to the right place to emit the reload insns. */
6070 switch (rl->when_needed)
6073 where = &other_input_reload_insns;
6075 case RELOAD_FOR_INPUT:
6076 where = &input_reload_insns[rl->opnum];
6078 case RELOAD_FOR_INPUT_ADDRESS:
6079 where = &input_address_reload_insns[rl->opnum];
6081 case RELOAD_FOR_INPADDR_ADDRESS:
6082 where = &inpaddr_address_reload_insns[rl->opnum];
6084 case RELOAD_FOR_OUTPUT_ADDRESS:
6085 where = &output_address_reload_insns[rl->opnum];
6087 case RELOAD_FOR_OUTADDR_ADDRESS:
6088 where = &outaddr_address_reload_insns[rl->opnum];
6090 case RELOAD_FOR_OPERAND_ADDRESS:
6091 where = &operand_reload_insns;
6093 case RELOAD_FOR_OPADDR_ADDR:
6094 where = &other_operand_reload_insns;
6096 case RELOAD_FOR_OTHER_ADDRESS:
6097 where = &other_input_address_reload_insns;
6103 push_to_sequence (*where);
6105 /* Auto-increment addresses must be reloaded in a special way. */
6106 if (rl->out && ! rl->out_reg)
6108 /* We are not going to bother supporting the case where a
6109 incremented register can't be copied directly from
6110 OLDEQUIV since this seems highly unlikely. */
6111 if (rl->secondary_in_reload >= 0)
6114 if (reload_inherited[j])
6115 oldequiv = reloadreg;
6117 old = XEXP (rl->in_reg, 0);
6119 if (optimize && GET_CODE (oldequiv) == REG
6120 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6121 && spill_reg_store[REGNO (oldequiv)]
6122 && GET_CODE (old) == REG
6123 && (dead_or_set_p (insn,
6124 spill_reg_stored_to[REGNO (oldequiv)])
6125 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6127 delete_output_reload (insn, j, REGNO (oldequiv));
6129 /* Prevent normal processing of this reload. */
6131 /* Output a special code sequence for this case. */
6132 new_spill_reg_store[REGNO (reloadreg)]
6133 = inc_for_reload (reloadreg, oldequiv, rl->out,
6137 /* If we are reloading a pseudo-register that was set by the previous
6138 insn, see if we can get rid of that pseudo-register entirely
6139 by redirecting the previous insn into our reload register. */
6141 else if (optimize && GET_CODE (old) == REG
6142 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6143 && dead_or_set_p (insn, old)
6144 /* This is unsafe if some other reload
6145 uses the same reg first. */
6146 && reload_reg_free_for_value_p (REGNO (reloadreg),
6152 rtx temp = PREV_INSN (insn);
6153 while (temp && GET_CODE (temp) == NOTE)
6154 temp = PREV_INSN (temp);
6156 && GET_CODE (temp) == INSN
6157 && GET_CODE (PATTERN (temp)) == SET
6158 && SET_DEST (PATTERN (temp)) == old
6159 /* Make sure we can access insn_operand_constraint. */
6160 && asm_noperands (PATTERN (temp)) < 0
6161 /* This is unsafe if prev insn rejects our reload reg. */
6162 && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint,
6164 /* This is unsafe if operand occurs more than once in current
6165 insn. Perhaps some occurrences aren't reloaded. */
6166 && count_occurrences (PATTERN (insn), old) == 1
6167 /* Don't risk splitting a matching pair of operands. */
6168 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6170 /* Store into the reload register instead of the pseudo. */
6171 SET_DEST (PATTERN (temp)) = reloadreg;
6173 /* If the previous insn is an output reload, the source is
6174 a reload register, and its spill_reg_store entry will
6175 contain the previous destination. This is now
6177 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6178 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6180 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6181 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6184 /* If these are the only uses of the pseudo reg,
6185 pretend for GDB it lives in the reload reg we used. */
6186 if (REG_N_DEATHS (REGNO (old)) == 1
6187 && REG_N_SETS (REGNO (old)) == 1)
6189 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6190 alter_reg (REGNO (old), -1);
6196 /* We can't do that, so output an insn to load RELOADREG. */
6198 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6199 /* If we have a secondary reload, pick up the secondary register
6200 and icode, if any. If OLDEQUIV and OLD are different or
6201 if this is an in-out reload, recompute whether or not we
6202 still need a secondary register and what the icode should
6203 be. If we still need a secondary register and the class or
6204 icode is different, go back to reloading from OLD if using
6205 OLDEQUIV means that we got the wrong type of register. We
6206 cannot have different class or icode due to an in-out reload
6207 because we don't make such reloads when both the input and
6208 output need secondary reload registers. */
6210 if (! special && rl->secondary_in_reload >= 0)
6212 rtx second_reload_reg = 0;
6213 int secondary_reload = rl->secondary_in_reload;
6214 rtx real_oldequiv = oldequiv;
6217 enum insn_code icode;
6219 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6220 and similarly for OLD.
6221 See comments in get_secondary_reload in reload.c. */
6222 /* If it is a pseudo that cannot be replaced with its
6223 equivalent MEM, we must fall back to reload_in, which
6224 will have all the necessary substitutions registered.
6225 Likewise for a pseudo that can't be replaced with its
6226 equivalent constant.
6228 Take extra care for subregs of such pseudos. Note that
6229 we cannot use reg_equiv_mem in this case because it is
6230 not in the right mode. */
6233 if (GET_CODE (tmp) == SUBREG)
6234 tmp = SUBREG_REG (tmp);
6235 if (GET_CODE (tmp) == REG
6236 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6237 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6238 || reg_equiv_constant[REGNO (tmp)] != 0))
6240 if (! reg_equiv_mem[REGNO (tmp)]
6241 || num_not_at_initial_offset
6242 || GET_CODE (oldequiv) == SUBREG)
6243 real_oldequiv = rl->in;
6245 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6249 if (GET_CODE (tmp) == SUBREG)
6250 tmp = SUBREG_REG (tmp);
6251 if (GET_CODE (tmp) == REG
6252 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6253 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6254 || reg_equiv_constant[REGNO (tmp)] != 0))
6256 if (! reg_equiv_mem[REGNO (tmp)]
6257 || num_not_at_initial_offset
6258 || GET_CODE (old) == SUBREG)
6261 real_old = reg_equiv_mem[REGNO (tmp)];
6264 second_reload_reg = rld[secondary_reload].reg_rtx;
6265 icode = rl->secondary_in_icode;
6267 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6268 || (rl->in != 0 && rl->out != 0))
6270 enum reg_class new_class
6271 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6272 mode, real_oldequiv);
6274 if (new_class == NO_REGS)
6275 second_reload_reg = 0;
6278 enum insn_code new_icode;
6279 enum machine_mode new_mode;
6281 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6282 REGNO (second_reload_reg)))
6283 oldequiv = old, real_oldequiv = real_old;
6286 new_icode = reload_in_optab[(int) mode];
6287 if (new_icode != CODE_FOR_nothing
6288 && ((insn_data[(int) new_icode].operand[0].predicate
6289 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6291 || (insn_data[(int) new_icode].operand[1].predicate
6292 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6293 (real_oldequiv, mode)))))
6294 new_icode = CODE_FOR_nothing;
6296 if (new_icode == CODE_FOR_nothing)
6299 new_mode = insn_data[(int) new_icode].operand[2].mode;
6301 if (GET_MODE (second_reload_reg) != new_mode)
6303 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6305 oldequiv = old, real_oldequiv = real_old;
6308 = gen_rtx_REG (new_mode,
6309 REGNO (second_reload_reg));
6315 /* If we still need a secondary reload register, check
6316 to see if it is being used as a scratch or intermediate
6317 register and generate code appropriately. If we need
6318 a scratch register, use REAL_OLDEQUIV since the form of
6319 the insn may depend on the actual address if it is
6322 if (second_reload_reg)
6324 if (icode != CODE_FOR_nothing)
6326 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6327 second_reload_reg));
6332 /* See if we need a scratch register to load the
6333 intermediate register (a tertiary reload). */
6334 enum insn_code tertiary_icode
6335 = rld[secondary_reload].secondary_in_icode;
6337 if (tertiary_icode != CODE_FOR_nothing)
6339 rtx third_reload_reg
6340 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6342 emit_insn ((GEN_FCN (tertiary_icode)
6343 (second_reload_reg, real_oldequiv,
6344 third_reload_reg)));
6347 gen_reload (second_reload_reg, real_oldequiv,
6351 oldequiv = second_reload_reg;
6357 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6359 rtx real_oldequiv = oldequiv;
6361 if ((GET_CODE (oldequiv) == REG
6362 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6363 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6364 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6365 || (GET_CODE (oldequiv) == SUBREG
6366 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6367 && (REGNO (SUBREG_REG (oldequiv))
6368 >= FIRST_PSEUDO_REGISTER)
6369 && ((reg_equiv_memory_loc
6370 [REGNO (SUBREG_REG (oldequiv))] != 0)
6371 || (reg_equiv_constant
6372 [REGNO (SUBREG_REG (oldequiv))] != 0))))
6373 real_oldequiv = rl->in;
6374 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6378 /* End this sequence. */
6379 *where = get_insns ();
6382 /* Update reload_override_in so that delete_address_reloads_1
6383 can see the actual register usage. */
6385 reload_override_in[j] = oldequiv;
6388 /* Generate insns to for the output reload RL, which is for the insn described
6389 by CHAIN and has the number J. */
6391 emit_output_reload_insns (chain, rl, j)
6392 struct insn_chain *chain;
6396 rtx reloadreg = rl->reg_rtx;
6397 rtx insn = chain->insn;
6400 enum machine_mode mode = GET_MODE (old);
6403 if (rl->when_needed == RELOAD_OTHER)
6406 push_to_sequence (output_reload_insns[rl->opnum]);
6408 /* Determine the mode to reload in.
6409 See comments above (for input reloading). */
6411 if (mode == VOIDmode)
6413 /* VOIDmode should never happen for an output. */
6414 if (asm_noperands (PATTERN (insn)) < 0)
6415 /* It's the compiler's fault. */
6416 fatal_insn ("VOIDmode on an output", insn);
6417 error_for_asm (insn, "output operand is constant in `asm'");
6418 /* Prevent crash--use something we know is valid. */
6420 old = gen_rtx_REG (mode, REGNO (reloadreg));
6423 if (GET_MODE (reloadreg) != mode)
6424 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6426 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6428 /* If we need two reload regs, set RELOADREG to the intermediate
6429 one, since it will be stored into OLD. We might need a secondary
6430 register only for an input reload, so check again here. */
6432 if (rl->secondary_out_reload >= 0)
6436 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6437 && reg_equiv_mem[REGNO (old)] != 0)
6438 real_old = reg_equiv_mem[REGNO (old)];
6440 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6444 rtx second_reloadreg = reloadreg;
6445 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6447 /* See if RELOADREG is to be used as a scratch register
6448 or as an intermediate register. */
6449 if (rl->secondary_out_icode != CODE_FOR_nothing)
6451 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6452 (real_old, second_reloadreg, reloadreg)));
6457 /* See if we need both a scratch and intermediate reload
6460 int secondary_reload = rl->secondary_out_reload;
6461 enum insn_code tertiary_icode
6462 = rld[secondary_reload].secondary_out_icode;
6464 if (GET_MODE (reloadreg) != mode)
6465 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6467 if (tertiary_icode != CODE_FOR_nothing)
6470 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6473 /* Copy primary reload reg to secondary reload reg.
6474 (Note that these have been swapped above, then
6475 secondary reload reg to OLD using our insn. */
6477 /* If REAL_OLD is a paradoxical SUBREG, remove it
6478 and try to put the opposite SUBREG on
6480 if (GET_CODE (real_old) == SUBREG
6481 && (GET_MODE_SIZE (GET_MODE (real_old))
6482 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6483 && 0 != (tem = gen_lowpart_common
6484 (GET_MODE (SUBREG_REG (real_old)),
6486 real_old = SUBREG_REG (real_old), reloadreg = tem;
6488 gen_reload (reloadreg, second_reloadreg,
6489 rl->opnum, rl->when_needed);
6490 emit_insn ((GEN_FCN (tertiary_icode)
6491 (real_old, reloadreg, third_reloadreg)));
6496 /* Copy between the reload regs here and then to
6499 gen_reload (reloadreg, second_reloadreg,
6500 rl->opnum, rl->when_needed);
6506 /* Output the last reload insn. */
6511 /* Don't output the last reload if OLD is not the dest of
6512 INSN and is in the src and is clobbered by INSN. */
6513 if (! flag_expensive_optimizations
6514 || GET_CODE (old) != REG
6515 || !(set = single_set (insn))
6516 || rtx_equal_p (old, SET_DEST (set))
6517 || !reg_mentioned_p (old, SET_SRC (set))
6518 || !regno_clobbered_p (REGNO (old), insn))
6519 gen_reload (old, reloadreg, rl->opnum,
6523 /* Look at all insns we emitted, just to be safe. */
6524 for (p = get_insns (); p; p = NEXT_INSN (p))
6525 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
6527 rtx pat = PATTERN (p);
6529 /* If this output reload doesn't come from a spill reg,
6530 clear any memory of reloaded copies of the pseudo reg.
6531 If this output reload comes from a spill reg,
6532 reg_has_output_reload will make this do nothing. */
6533 note_stores (pat, forget_old_reloads_1, NULL);
6535 if (reg_mentioned_p (rl->reg_rtx, pat))
6537 rtx set = single_set (insn);
6538 if (reload_spill_index[j] < 0
6540 && SET_SRC (set) == rl->reg_rtx)
6542 int src = REGNO (SET_SRC (set));
6544 reload_spill_index[j] = src;
6545 SET_HARD_REG_BIT (reg_is_output_reload, src);
6546 if (find_regno_note (insn, REG_DEAD, src))
6547 SET_HARD_REG_BIT (reg_reloaded_died, src);
6549 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6551 int s = rl->secondary_out_reload;
6552 set = single_set (p);
6553 /* If this reload copies only to the secondary reload
6554 register, the secondary reload does the actual
6556 if (s >= 0 && set == NULL_RTX)
6557 ; /* We can't tell what function the secondary reload
6558 has and where the actual store to the pseudo is
6559 made; leave new_spill_reg_store alone. */
6561 && SET_SRC (set) == rl->reg_rtx
6562 && SET_DEST (set) == rld[s].reg_rtx)
6564 /* Usually the next instruction will be the
6565 secondary reload insn; if we can confirm
6566 that it is, setting new_spill_reg_store to
6567 that insn will allow an extra optimization. */
6568 rtx s_reg = rld[s].reg_rtx;
6569 rtx next = NEXT_INSN (p);
6570 rld[s].out = rl->out;
6571 rld[s].out_reg = rl->out_reg;
6572 set = single_set (next);
6573 if (set && SET_SRC (set) == s_reg
6574 && ! new_spill_reg_store[REGNO (s_reg)])
6576 SET_HARD_REG_BIT (reg_is_output_reload,
6578 new_spill_reg_store[REGNO (s_reg)] = next;
6582 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6587 if (rl->when_needed == RELOAD_OTHER)
6589 emit_insns (other_output_reload_insns[rl->opnum]);
6590 other_output_reload_insns[rl->opnum] = get_insns ();
6593 output_reload_insns[rl->opnum] = get_insns ();
6598 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6599 and has the number J. */
6601 do_input_reload (chain, rl, j)
6602 struct insn_chain *chain;
6606 int expect_occurrences = 1;
6607 rtx insn = chain->insn;
6608 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6609 ? rl->in_reg : rl->in);
6612 /* AUTO_INC reloads need to be handled even if inherited. We got an
6613 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6614 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6615 && ! rtx_equal_p (rl->reg_rtx, old)
6616 && rl->reg_rtx != 0)
6617 emit_input_reload_insns (chain, rld + j, old, j);
6619 /* When inheriting a wider reload, we have a MEM in rl->in,
6620 e.g. inheriting a SImode output reload for
6621 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6622 if (optimize && reload_inherited[j] && rl->in
6623 && GET_CODE (rl->in) == MEM
6624 && GET_CODE (rl->in_reg) == MEM
6625 && reload_spill_index[j] >= 0
6626 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6629 = count_occurrences (PATTERN (insn), rl->in) == 1 ? 0 : -1;
6631 = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6634 /* If we are reloading a register that was recently stored in with an
6635 output-reload, see if we can prove there was
6636 actually no need to store the old value in it. */
6639 && (reload_inherited[j] || reload_override_in[j])
6641 && GET_CODE (rl->reg_rtx) == REG
6642 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6644 /* There doesn't seem to be any reason to restrict this to pseudos
6645 and doing so loses in the case where we are copying from a
6646 register of the wrong class. */
6647 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6648 >= FIRST_PSEUDO_REGISTER)
6650 /* The insn might have already some references to stackslots
6651 replaced by MEMs, while reload_out_reg still names the
6653 && (dead_or_set_p (insn,
6654 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6655 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6657 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6660 /* Do output reloading for reload RL, which is for the insn described by
6661 CHAIN and has the number J.
6662 ??? At some point we need to support handling output reloads of
6663 JUMP_INSNs or insns that set cc0. */
6665 do_output_reload (chain, rl, j)
6666 struct insn_chain *chain;
6671 rtx insn = chain->insn;
6672 /* If this is an output reload that stores something that is
6673 not loaded in this same reload, see if we can eliminate a previous
6675 rtx pseudo = rl->out_reg;
6678 && GET_CODE (pseudo) == REG
6679 && ! rtx_equal_p (rl->in_reg, pseudo)
6680 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6681 && reg_last_reload_reg[REGNO (pseudo)])
6683 int pseudo_no = REGNO (pseudo);
6684 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6686 /* We don't need to test full validity of last_regno for
6687 inherit here; we only want to know if the store actually
6688 matches the pseudo. */
6689 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6690 && reg_reloaded_contents[last_regno] == pseudo_no
6691 && spill_reg_store[last_regno]
6692 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6693 delete_output_reload (insn, j, last_regno);
6698 || rl->reg_rtx == old
6699 || rl->reg_rtx == 0)
6702 /* An output operand that dies right away does need a reload,
6703 but need not be copied from it. Show the new location in the
6705 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6706 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6708 XEXP (note, 0) = rl->reg_rtx;
6711 /* Likewise for a SUBREG of an operand that dies. */
6712 else if (GET_CODE (old) == SUBREG
6713 && GET_CODE (SUBREG_REG (old)) == REG
6714 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6717 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6721 else if (GET_CODE (old) == SCRATCH)
6722 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6723 but we don't want to make an output reload. */
6726 /* If is a JUMP_INSN, we can't support output reloads yet. */
6727 if (GET_CODE (insn) == JUMP_INSN)
6730 emit_output_reload_insns (chain, rld + j, j);
6733 /* Output insns to reload values in and out of the chosen reload regs. */
6736 emit_reload_insns (chain)
6737 struct insn_chain *chain;
6739 rtx insn = chain->insn;
6742 rtx following_insn = NEXT_INSN (insn);
6743 rtx before_insn = PREV_INSN (insn);
6745 CLEAR_HARD_REG_SET (reg_reloaded_died);
6747 for (j = 0; j < reload_n_operands; j++)
6748 input_reload_insns[j] = input_address_reload_insns[j]
6749 = inpaddr_address_reload_insns[j]
6750 = output_reload_insns[j] = output_address_reload_insns[j]
6751 = outaddr_address_reload_insns[j]
6752 = other_output_reload_insns[j] = 0;
6753 other_input_address_reload_insns = 0;
6754 other_input_reload_insns = 0;
6755 operand_reload_insns = 0;
6756 other_operand_reload_insns = 0;
6758 /* Now output the instructions to copy the data into and out of the
6759 reload registers. Do these in the order that the reloads were reported,
6760 since reloads of base and index registers precede reloads of operands
6761 and the operands may need the base and index registers reloaded. */
6763 for (j = 0; j < n_reloads; j++)
6766 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6767 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6769 do_input_reload (chain, rld + j, j);
6770 do_output_reload (chain, rld + j, j);
6773 /* Now write all the insns we made for reloads in the order expected by
6774 the allocation functions. Prior to the insn being reloaded, we write
6775 the following reloads:
6777 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6779 RELOAD_OTHER reloads.
6781 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6782 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6783 RELOAD_FOR_INPUT reload for the operand.
6785 RELOAD_FOR_OPADDR_ADDRS reloads.
6787 RELOAD_FOR_OPERAND_ADDRESS reloads.
6789 After the insn being reloaded, we write the following:
6791 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6792 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6793 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6794 reloads for the operand. The RELOAD_OTHER output reloads are
6795 output in descending order by reload number. */
6797 emit_insns_before (other_input_address_reload_insns, insn);
6798 emit_insns_before (other_input_reload_insns, insn);
6800 for (j = 0; j < reload_n_operands; j++)
6802 emit_insns_before (inpaddr_address_reload_insns[j], insn);
6803 emit_insns_before (input_address_reload_insns[j], insn);
6804 emit_insns_before (input_reload_insns[j], insn);
6807 emit_insns_before (other_operand_reload_insns, insn);
6808 emit_insns_before (operand_reload_insns, insn);
6810 for (j = 0; j < reload_n_operands; j++)
6812 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
6813 emit_insns_before (output_address_reload_insns[j], following_insn);
6814 emit_insns_before (output_reload_insns[j], following_insn);
6815 emit_insns_before (other_output_reload_insns[j], following_insn);
6818 /* Keep basic block info up to date. */
6821 if (BLOCK_HEAD (chain->block) == insn)
6822 BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn);
6823 if (BLOCK_END (chain->block) == insn)
6824 BLOCK_END (chain->block) = PREV_INSN (following_insn);
6827 /* For all the spill regs newly reloaded in this instruction,
6828 record what they were reloaded from, so subsequent instructions
6829 can inherit the reloads.
6831 Update spill_reg_store for the reloads of this insn.
6832 Copy the elements that were updated in the loop above. */
6834 for (j = 0; j < n_reloads; j++)
6836 register int r = reload_order[j];
6837 register int i = reload_spill_index[r];
6839 /* If this is a non-inherited input reload from a pseudo, we must
6840 clear any memory of a previous store to the same pseudo. Only do
6841 something if there will not be an output reload for the pseudo
6843 if (rld[r].in_reg != 0
6844 && ! (reload_inherited[r] || reload_override_in[r]))
6846 rtx reg = rld[r].in_reg;
6848 if (GET_CODE (reg) == SUBREG)
6849 reg = SUBREG_REG (reg);
6851 if (GET_CODE (reg) == REG
6852 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
6853 && ! reg_has_output_reload[REGNO (reg)])
6855 int nregno = REGNO (reg);
6857 if (reg_last_reload_reg[nregno])
6859 int last_regno = REGNO (reg_last_reload_reg[nregno]);
6861 if (reg_reloaded_contents[last_regno] == nregno)
6862 spill_reg_store[last_regno] = 0;
6867 /* I is nonneg if this reload used a register.
6868 If rld[r].reg_rtx is 0, this is an optional reload
6869 that we opted to ignore. */
6871 if (i >= 0 && rld[r].reg_rtx != 0)
6874 = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
6876 int part_reaches_end = 0;
6877 int all_reaches_end = 1;
6879 /* For a multi register reload, we need to check if all or part
6880 of the value lives to the end. */
6881 for (k = 0; k < nr; k++)
6883 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
6884 rld[r].when_needed))
6885 part_reaches_end = 1;
6887 all_reaches_end = 0;
6890 /* Ignore reloads that don't reach the end of the insn in
6892 if (all_reaches_end)
6894 /* First, clear out memory of what used to be in this spill reg.
6895 If consecutive registers are used, clear them all. */
6897 for (k = 0; k < nr; k++)
6898 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
6900 /* Maybe the spill reg contains a copy of reload_out. */
6902 && (GET_CODE (rld[r].out) == REG
6906 || GET_CODE (rld[r].out_reg) == REG))
6908 rtx out = (GET_CODE (rld[r].out) == REG
6912 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
6913 register int nregno = REGNO (out);
6914 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6915 : HARD_REGNO_NREGS (nregno,
6916 GET_MODE (rld[r].reg_rtx)));
6918 spill_reg_store[i] = new_spill_reg_store[i];
6919 spill_reg_stored_to[i] = out;
6920 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
6922 /* If NREGNO is a hard register, it may occupy more than
6923 one register. If it does, say what is in the
6924 rest of the registers assuming that both registers
6925 agree on how many words the object takes. If not,
6926 invalidate the subsequent registers. */
6928 if (nregno < FIRST_PSEUDO_REGISTER)
6929 for (k = 1; k < nnr; k++)
6930 reg_last_reload_reg[nregno + k]
6932 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
6933 REGNO (rld[r].reg_rtx) + k)
6936 /* Now do the inverse operation. */
6937 for (k = 0; k < nr; k++)
6939 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
6940 reg_reloaded_contents[i + k]
6941 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
6944 reg_reloaded_insn[i + k] = insn;
6945 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
6949 /* Maybe the spill reg contains a copy of reload_in. Only do
6950 something if there will not be an output reload for
6951 the register being reloaded. */
6952 else if (rld[r].out_reg == 0
6954 && ((GET_CODE (rld[r].in) == REG
6955 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
6956 && ! reg_has_output_reload[REGNO (rld[r].in)])
6957 || (GET_CODE (rld[r].in_reg) == REG
6958 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
6959 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
6961 register int nregno;
6964 if (GET_CODE (rld[r].in) == REG
6965 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
6966 nregno = REGNO (rld[r].in);
6967 else if (GET_CODE (rld[r].in_reg) == REG)
6968 nregno = REGNO (rld[r].in_reg);
6970 nregno = REGNO (XEXP (rld[r].in_reg, 0));
6972 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6973 : HARD_REGNO_NREGS (nregno,
6974 GET_MODE (rld[r].reg_rtx)));
6976 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
6978 if (nregno < FIRST_PSEUDO_REGISTER)
6979 for (k = 1; k < nnr; k++)
6980 reg_last_reload_reg[nregno + k]
6982 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
6983 REGNO (rld[r].reg_rtx) + k)
6986 /* Unless we inherited this reload, show we haven't
6987 recently done a store.
6988 Previous stores of inherited auto_inc expressions
6989 also have to be discarded. */
6990 if (! reload_inherited[r]
6991 || (rld[r].out && ! rld[r].out_reg))
6992 spill_reg_store[i] = 0;
6994 for (k = 0; k < nr; k++)
6996 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
6997 reg_reloaded_contents[i + k]
6998 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7001 reg_reloaded_insn[i + k] = insn;
7002 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7007 /* However, if part of the reload reaches the end, then we must
7008 invalidate the old info for the part that survives to the end. */
7009 else if (part_reaches_end)
7011 for (k = 0; k < nr; k++)
7012 if (reload_reg_reaches_end_p (i + k,
7014 rld[r].when_needed))
7015 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7019 /* The following if-statement was #if 0'd in 1.34 (or before...).
7020 It's reenabled in 1.35 because supposedly nothing else
7021 deals with this problem. */
7023 /* If a register gets output-reloaded from a non-spill register,
7024 that invalidates any previous reloaded copy of it.
7025 But forget_old_reloads_1 won't get to see it, because
7026 it thinks only about the original insn. So invalidate it here. */
7027 if (i < 0 && rld[r].out != 0
7028 && (GET_CODE (rld[r].out) == REG
7029 || (GET_CODE (rld[r].out) == MEM
7030 && GET_CODE (rld[r].out_reg) == REG)))
7032 rtx out = (GET_CODE (rld[r].out) == REG
7033 ? rld[r].out : rld[r].out_reg);
7034 register int nregno = REGNO (out);
7035 if (nregno >= FIRST_PSEUDO_REGISTER)
7037 rtx src_reg, store_insn = NULL_RTX;
7039 reg_last_reload_reg[nregno] = 0;
7041 /* If we can find a hard register that is stored, record
7042 the storing insn so that we may delete this insn with
7043 delete_output_reload. */
7044 src_reg = rld[r].reg_rtx;
7046 /* If this is an optional reload, try to find the source reg
7047 from an input reload. */
7050 rtx set = single_set (insn);
7051 if (set && SET_DEST (set) == rld[r].out)
7055 src_reg = SET_SRC (set);
7057 for (k = 0; k < n_reloads; k++)
7059 if (rld[k].in == src_reg)
7061 src_reg = rld[k].reg_rtx;
7068 store_insn = new_spill_reg_store[REGNO (src_reg)];
7069 if (src_reg && GET_CODE (src_reg) == REG
7070 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7072 int src_regno = REGNO (src_reg);
7073 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7074 /* The place where to find a death note varies with
7075 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7076 necessarily checked exactly in the code that moves
7077 notes, so just check both locations. */
7078 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7080 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7083 spill_reg_store[src_regno + nr] = store_insn;
7084 spill_reg_stored_to[src_regno + nr] = out;
7085 reg_reloaded_contents[src_regno + nr] = nregno;
7086 reg_reloaded_insn[src_regno + nr] = store_insn;
7087 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7088 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7089 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7091 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7093 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7095 reg_last_reload_reg[nregno] = src_reg;
7100 int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (rld[r].out));
7102 while (num_regs-- > 0)
7103 reg_last_reload_reg[nregno + num_regs] = 0;
7107 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7110 /* Emit code to perform a reload from IN (which may be a reload register) to
7111 OUT (which may also be a reload register). IN or OUT is from operand
7112 OPNUM with reload type TYPE.
7114 Returns first insn emitted. */
7117 gen_reload (out, in, opnum, type)
7121 enum reload_type type;
7123 rtx last = get_last_insn ();
7126 /* If IN is a paradoxical SUBREG, remove it and try to put the
7127 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7128 if (GET_CODE (in) == SUBREG
7129 && (GET_MODE_SIZE (GET_MODE (in))
7130 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7131 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7132 in = SUBREG_REG (in), out = tem;
7133 else if (GET_CODE (out) == SUBREG
7134 && (GET_MODE_SIZE (GET_MODE (out))
7135 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7136 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7137 out = SUBREG_REG (out), in = tem;
7139 /* How to do this reload can get quite tricky. Normally, we are being
7140 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7141 register that didn't get a hard register. In that case we can just
7142 call emit_move_insn.
7144 We can also be asked to reload a PLUS that adds a register or a MEM to
7145 another register, constant or MEM. This can occur during frame pointer
7146 elimination and while reloading addresses. This case is handled by
7147 trying to emit a single insn to perform the add. If it is not valid,
7148 we use a two insn sequence.
7150 Finally, we could be called to handle an 'o' constraint by putting
7151 an address into a register. In that case, we first try to do this
7152 with a named pattern of "reload_load_address". If no such pattern
7153 exists, we just emit a SET insn and hope for the best (it will normally
7154 be valid on machines that use 'o').
7156 This entire process is made complex because reload will never
7157 process the insns we generate here and so we must ensure that
7158 they will fit their constraints and also by the fact that parts of
7159 IN might be being reloaded separately and replaced with spill registers.
7160 Because of this, we are, in some sense, just guessing the right approach
7161 here. The one listed above seems to work.
7163 ??? At some point, this whole thing needs to be rethought. */
7165 if (GET_CODE (in) == PLUS
7166 && (GET_CODE (XEXP (in, 0)) == REG
7167 || GET_CODE (XEXP (in, 0)) == SUBREG
7168 || GET_CODE (XEXP (in, 0)) == MEM)
7169 && (GET_CODE (XEXP (in, 1)) == REG
7170 || GET_CODE (XEXP (in, 1)) == SUBREG
7171 || CONSTANT_P (XEXP (in, 1))
7172 || GET_CODE (XEXP (in, 1)) == MEM))
7174 /* We need to compute the sum of a register or a MEM and another
7175 register, constant, or MEM, and put it into the reload
7176 register. The best possible way of doing this is if the machine
7177 has a three-operand ADD insn that accepts the required operands.
7179 The simplest approach is to try to generate such an insn and see if it
7180 is recognized and matches its constraints. If so, it can be used.
7182 It might be better not to actually emit the insn unless it is valid,
7183 but we need to pass the insn as an operand to `recog' and
7184 `extract_insn' and it is simpler to emit and then delete the insn if
7185 not valid than to dummy things up. */
7187 rtx op0, op1, tem, insn;
7190 op0 = find_replacement (&XEXP (in, 0));
7191 op1 = find_replacement (&XEXP (in, 1));
7193 /* Since constraint checking is strict, commutativity won't be
7194 checked, so we need to do that here to avoid spurious failure
7195 if the add instruction is two-address and the second operand
7196 of the add is the same as the reload reg, which is frequently
7197 the case. If the insn would be A = B + A, rearrange it so
7198 it will be A = A + B as constrain_operands expects. */
7200 if (GET_CODE (XEXP (in, 1)) == REG
7201 && REGNO (out) == REGNO (XEXP (in, 1)))
7202 tem = op0, op0 = op1, op1 = tem;
7204 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7205 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7207 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7208 code = recog_memoized (insn);
7212 extract_insn (insn);
7213 /* We want constrain operands to treat this insn strictly in
7214 its validity determination, i.e., the way it would after reload
7216 if (constrain_operands (1))
7220 delete_insns_since (last);
7222 /* If that failed, we must use a conservative two-insn sequence.
7224 Use a move to copy one operand into the reload register. Prefer
7225 to reload a constant, MEM or pseudo since the move patterns can
7226 handle an arbitrary operand. If OP1 is not a constant, MEM or
7227 pseudo and OP1 is not a valid operand for an add instruction, then
7230 After reloading one of the operands into the reload register, add
7231 the reload register to the output register.
7233 If there is another way to do this for a specific machine, a
7234 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7237 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7239 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7240 || (GET_CODE (op1) == REG
7241 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7242 || (code != CODE_FOR_nothing
7243 && ! ((*insn_data[code].operand[2].predicate)
7244 (op1, insn_data[code].operand[2].mode))))
7245 tem = op0, op0 = op1, op1 = tem;
7247 gen_reload (out, op0, opnum, type);
7249 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7250 This fixes a problem on the 32K where the stack pointer cannot
7251 be used as an operand of an add insn. */
7253 if (rtx_equal_p (op0, op1))
7256 insn = emit_insn (gen_add2_insn (out, op1));
7258 /* If that failed, copy the address register to the reload register.
7259 Then add the constant to the reload register. */
7261 code = recog_memoized (insn);
7265 extract_insn (insn);
7266 /* We want constrain operands to treat this insn strictly in
7267 its validity determination, i.e., the way it would after reload
7269 if (constrain_operands (1))
7271 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7273 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7278 delete_insns_since (last);
7280 gen_reload (out, op1, opnum, type);
7281 insn = emit_insn (gen_add2_insn (out, op0));
7282 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7285 #ifdef SECONDARY_MEMORY_NEEDED
7286 /* If we need a memory location to do the move, do it that way. */
7287 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7288 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7289 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7290 REGNO_REG_CLASS (REGNO (out)),
7293 /* Get the memory to use and rewrite both registers to its mode. */
7294 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7296 if (GET_MODE (loc) != GET_MODE (out))
7297 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7299 if (GET_MODE (loc) != GET_MODE (in))
7300 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7302 gen_reload (loc, in, opnum, type);
7303 gen_reload (out, loc, opnum, type);
7307 /* If IN is a simple operand, use gen_move_insn. */
7308 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7309 emit_insn (gen_move_insn (out, in));
7311 #ifdef HAVE_reload_load_address
7312 else if (HAVE_reload_load_address)
7313 emit_insn (gen_reload_load_address (out, in));
7316 /* Otherwise, just write (set OUT IN) and hope for the best. */
7318 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7320 /* Return the first insn emitted.
7321 We can not just return get_last_insn, because there may have
7322 been multiple instructions emitted. Also note that gen_move_insn may
7323 emit more than one insn itself, so we can not assume that there is one
7324 insn emitted per emit_insn_before call. */
7326 return last ? NEXT_INSN (last) : get_insns ();
7329 /* Delete a previously made output-reload
7330 whose result we now believe is not needed.
7331 First we double-check.
7333 INSN is the insn now being processed.
7334 LAST_RELOAD_REG is the hard register number for which we want to delete
7335 the last output reload.
7336 J is the reload-number that originally used REG. The caller has made
7337 certain that reload J doesn't use REG any longer for input. */
7340 delete_output_reload (insn, j, last_reload_reg)
7343 int last_reload_reg;
7345 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7346 rtx reg = spill_reg_stored_to[last_reload_reg];
7349 int n_inherited = 0;
7353 /* Get the raw pseudo-register referred to. */
7355 while (GET_CODE (reg) == SUBREG)
7356 reg = SUBREG_REG (reg);
7357 substed = reg_equiv_memory_loc[REGNO (reg)];
7359 /* This is unsafe if the operand occurs more often in the current
7360 insn than it is inherited. */
7361 for (k = n_reloads - 1; k >= 0; k--)
7363 rtx reg2 = rld[k].in;
7366 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7367 reg2 = rld[k].in_reg;
7369 if (rld[k].out && ! rld[k].out_reg)
7370 reg2 = XEXP (rld[k].in_reg, 0);
7372 while (GET_CODE (reg2) == SUBREG)
7373 reg2 = SUBREG_REG (reg2);
7374 if (rtx_equal_p (reg2, reg))
7376 if (reload_inherited[k] || reload_override_in[k] || k == j)
7379 reg2 = rld[k].out_reg;
7382 while (GET_CODE (reg2) == SUBREG)
7383 reg2 = XEXP (reg2, 0);
7384 if (rtx_equal_p (reg2, reg))
7391 n_occurrences = count_occurrences (PATTERN (insn), reg);
7393 n_occurrences += count_occurrences (PATTERN (insn), substed);
7394 if (n_occurrences > n_inherited)
7397 /* If the pseudo-reg we are reloading is no longer referenced
7398 anywhere between the store into it and here,
7399 and no jumps or labels intervene, then the value can get
7400 here through the reload reg alone.
7401 Otherwise, give up--return. */
7402 for (i1 = NEXT_INSN (output_reload_insn);
7403 i1 != insn; i1 = NEXT_INSN (i1))
7405 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7407 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7408 && reg_mentioned_p (reg, PATTERN (i1)))
7410 /* If this is USE in front of INSN, we only have to check that
7411 there are no more references than accounted for by inheritance. */
7412 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7414 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7415 i1 = NEXT_INSN (i1);
7417 if (n_occurrences <= n_inherited && i1 == insn)
7423 /* The caller has already checked that REG dies or is set in INSN.
7424 It has also checked that we are optimizing, and thus some inaccurancies
7425 in the debugging information are acceptable.
7426 So we could just delete output_reload_insn.
7427 But in some cases we can improve the debugging information without
7428 sacrificing optimization - maybe even improving the code:
7429 See if the pseudo reg has been completely replaced
7430 with reload regs. If so, delete the store insn
7431 and forget we had a stack slot for the pseudo. */
7432 if (rld[j].out != rld[j].in
7433 && REG_N_DEATHS (REGNO (reg)) == 1
7434 && REG_N_SETS (REGNO (reg)) == 1
7435 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7436 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7440 /* We know that it was used only between here
7441 and the beginning of the current basic block.
7442 (We also know that the last use before INSN was
7443 the output reload we are thinking of deleting, but never mind that.)
7444 Search that range; see if any ref remains. */
7445 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7447 rtx set = single_set (i2);
7449 /* Uses which just store in the pseudo don't count,
7450 since if they are the only uses, they are dead. */
7451 if (set != 0 && SET_DEST (set) == reg)
7453 if (GET_CODE (i2) == CODE_LABEL
7454 || GET_CODE (i2) == JUMP_INSN)
7456 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7457 && reg_mentioned_p (reg, PATTERN (i2)))
7459 /* Some other ref remains; just delete the output reload we
7461 delete_address_reloads (output_reload_insn, insn);
7462 PUT_CODE (output_reload_insn, NOTE);
7463 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7464 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7469 /* Delete the now-dead stores into this pseudo. */
7470 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7472 rtx set = single_set (i2);
7474 if (set != 0 && SET_DEST (set) == reg)
7476 delete_address_reloads (i2, insn);
7477 /* This might be a basic block head,
7478 thus don't use delete_insn. */
7479 PUT_CODE (i2, NOTE);
7480 NOTE_SOURCE_FILE (i2) = 0;
7481 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7483 if (GET_CODE (i2) == CODE_LABEL
7484 || GET_CODE (i2) == JUMP_INSN)
7488 /* For the debugging info,
7489 say the pseudo lives in this reload reg. */
7490 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7491 alter_reg (REGNO (reg), -1);
7493 delete_address_reloads (output_reload_insn, insn);
7494 PUT_CODE (output_reload_insn, NOTE);
7495 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7496 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7500 /* We are going to delete DEAD_INSN. Recursively delete loads of
7501 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7502 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7504 delete_address_reloads (dead_insn, current_insn)
7505 rtx dead_insn, current_insn;
7507 rtx set = single_set (dead_insn);
7508 rtx set2, dst, prev, next;
7511 rtx dst = SET_DEST (set);
7512 if (GET_CODE (dst) == MEM)
7513 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7515 /* If we deleted the store from a reloaded post_{in,de}c expression,
7516 we can delete the matching adds. */
7517 prev = PREV_INSN (dead_insn);
7518 next = NEXT_INSN (dead_insn);
7519 if (! prev || ! next)
7521 set = single_set (next);
7522 set2 = single_set (prev);
7524 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7525 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7526 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7528 dst = SET_DEST (set);
7529 if (! rtx_equal_p (dst, SET_DEST (set2))
7530 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7531 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7532 || (INTVAL (XEXP (SET_SRC (set), 1))
7533 != - INTVAL (XEXP (SET_SRC (set2), 1))))
7539 /* Subfunction of delete_address_reloads: process registers found in X. */
7541 delete_address_reloads_1 (dead_insn, x, current_insn)
7542 rtx dead_insn, x, current_insn;
7544 rtx prev, set, dst, i2;
7546 enum rtx_code code = GET_CODE (x);
7550 const char *fmt= GET_RTX_FORMAT (code);
7551 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7554 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7555 else if (fmt[i] == 'E')
7557 for (j = XVECLEN (x, i) - 1; j >=0; j--)
7558 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7565 if (spill_reg_order[REGNO (x)] < 0)
7568 /* Scan backwards for the insn that sets x. This might be a way back due
7570 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7572 code = GET_CODE (prev);
7573 if (code == CODE_LABEL || code == JUMP_INSN)
7575 if (GET_RTX_CLASS (code) != 'i')
7577 if (reg_set_p (x, PATTERN (prev)))
7579 if (reg_referenced_p (x, PATTERN (prev)))
7582 if (! prev || INSN_UID (prev) < reload_first_uid)
7584 /* Check that PREV only sets the reload register. */
7585 set = single_set (prev);
7588 dst = SET_DEST (set);
7589 if (GET_CODE (dst) != REG
7590 || ! rtx_equal_p (dst, x))
7592 if (! reg_set_p (dst, PATTERN (dead_insn)))
7594 /* Check if DST was used in a later insn -
7595 it might have been inherited. */
7596 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7598 if (GET_CODE (i2) == CODE_LABEL)
7600 if (GET_RTX_CLASS (GET_CODE (i2)) != 'i')
7602 if (reg_referenced_p (dst, PATTERN (i2)))
7604 /* If there is a reference to the register in the current insn,
7605 it might be loaded in a non-inherited reload. If no other
7606 reload uses it, that means the register is set before
7608 if (i2 == current_insn)
7610 for (j = n_reloads - 1; j >= 0; j--)
7611 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7612 || reload_override_in[j] == dst)
7614 for (j = n_reloads - 1; j >= 0; j--)
7615 if (rld[j].in && rld[j].reg_rtx == dst)
7622 if (GET_CODE (i2) == JUMP_INSN)
7624 /* If DST is still live at CURRENT_INSN, check if it is used for
7625 any reload. Note that even if CURRENT_INSN sets DST, we still
7626 have to check the reloads. */
7627 if (i2 == current_insn)
7629 for (j = n_reloads - 1; j >= 0; j--)
7630 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7631 || reload_override_in[j] == dst)
7633 /* ??? We can't finish the loop here, because dst might be
7634 allocated to a pseudo in this block if no reload in this
7635 block needs any of the clsses containing DST - see
7636 spill_hard_reg. There is no easy way to tell this, so we
7637 have to scan till the end of the basic block. */
7639 if (reg_set_p (dst, PATTERN (i2)))
7643 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7644 reg_reloaded_contents[REGNO (dst)] = -1;
7645 /* Can't use delete_insn here because PREV might be a basic block head. */
7646 PUT_CODE (prev, NOTE);
7647 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
7648 NOTE_SOURCE_FILE (prev) = 0;
7651 /* Output reload-insns to reload VALUE into RELOADREG.
7652 VALUE is an autoincrement or autodecrement RTX whose operand
7653 is a register or memory location;
7654 so reloading involves incrementing that location.
7655 IN is either identical to VALUE, or some cheaper place to reload from.
7657 INC_AMOUNT is the number to increment or decrement by (always positive).
7658 This cannot be deduced from VALUE.
7660 Return the instruction that stores into RELOADREG. */
7663 inc_for_reload (reloadreg, in, value, inc_amount)
7668 /* REG or MEM to be copied and incremented. */
7669 rtx incloc = XEXP (value, 0);
7670 /* Nonzero if increment after copying. */
7671 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7677 rtx real_in = in == value ? XEXP (in, 0) : in;
7679 /* No hard register is equivalent to this register after
7680 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7681 we could inc/dec that register as well (maybe even using it for
7682 the source), but I'm not sure it's worth worrying about. */
7683 if (GET_CODE (incloc) == REG)
7684 reg_last_reload_reg[REGNO (incloc)] = 0;
7686 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7687 inc_amount = - inc_amount;
7689 inc = GEN_INT (inc_amount);
7691 /* If this is post-increment, first copy the location to the reload reg. */
7692 if (post && real_in != reloadreg)
7693 emit_insn (gen_move_insn (reloadreg, real_in));
7697 /* See if we can directly increment INCLOC. Use a method similar to
7698 that in gen_reload. */
7700 last = get_last_insn ();
7701 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7702 gen_rtx_PLUS (GET_MODE (incloc),
7705 code = recog_memoized (add_insn);
7708 extract_insn (add_insn);
7709 if (constrain_operands (1))
7711 /* If this is a pre-increment and we have incremented the value
7712 where it lives, copy the incremented value to RELOADREG to
7713 be used as an address. */
7716 emit_insn (gen_move_insn (reloadreg, incloc));
7721 delete_insns_since (last);
7724 /* If couldn't do the increment directly, must increment in RELOADREG.
7725 The way we do this depends on whether this is pre- or post-increment.
7726 For pre-increment, copy INCLOC to the reload register, increment it
7727 there, then save back. */
7731 if (in != reloadreg)
7732 emit_insn (gen_move_insn (reloadreg, real_in));
7733 emit_insn (gen_add2_insn (reloadreg, inc));
7734 store = emit_insn (gen_move_insn (incloc, reloadreg));
7739 Because this might be a jump insn or a compare, and because RELOADREG
7740 may not be available after the insn in an input reload, we must do
7741 the incrementation before the insn being reloaded for.
7743 We have already copied IN to RELOADREG. Increment the copy in
7744 RELOADREG, save that back, then decrement RELOADREG so it has
7745 the original value. */
7747 emit_insn (gen_add2_insn (reloadreg, inc));
7748 store = emit_insn (gen_move_insn (incloc, reloadreg));
7749 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7755 /* Return 1 if we are certain that the constraint-string STRING allows
7756 the hard register REG. Return 0 if we can't be sure of this. */
7759 constraint_accepts_reg_p (string, reg)
7764 int regno = true_regnum (reg);
7767 /* Initialize for first alternative. */
7769 /* Check that each alternative contains `g' or `r'. */
7771 switch (c = *string++)
7774 /* If an alternative lacks `g' or `r', we lose. */
7777 /* If an alternative lacks `g' or `r', we lose. */
7780 /* Initialize for next alternative. */
7785 /* Any general reg wins for this alternative. */
7786 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7790 /* Any reg in specified class wins for this alternative. */
7792 enum reg_class class = REG_CLASS_FROM_LETTER (c);
7794 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
7800 /* Return the number of places FIND appears within X, but don't count
7801 an occurrence if some SET_DEST is FIND. */
7804 count_occurrences (x, find)
7805 register rtx x, find;
7808 register enum rtx_code code;
7809 register const char *format_ptr;
7817 code = GET_CODE (x);
7832 if (GET_CODE (find) == MEM && rtx_equal_p (x, find))
7836 if (SET_DEST (x) == find)
7837 return count_occurrences (SET_SRC (x), find);
7844 format_ptr = GET_RTX_FORMAT (code);
7847 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7849 switch (*format_ptr++)
7852 count += count_occurrences (XEXP (x, i), find);
7856 if (XVEC (x, i) != NULL)
7858 for (j = 0; j < XVECLEN (x, i); j++)
7859 count += count_occurrences (XVECEXP (x, i, j), find);
7867 /* INSN is a no-op; delete it.
7868 If this sets the return value of the function, we must keep a USE around,
7869 in case this is in a different basic block than the final USE. Otherwise,
7870 we could loose important register lifeness information on
7871 SMALL_REGISTER_CLASSES machines, where return registers might be used as
7872 spills: subsequent passes assume that spill registers are dead at the end
7874 VALUE must be the return value in such a case, NULL otherwise. */
7876 reload_cse_delete_noop_set (insn, value)
7881 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
7882 INSN_CODE (insn) = -1;
7883 REG_NOTES (insn) = NULL_RTX;
7887 PUT_CODE (insn, NOTE);
7888 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
7889 NOTE_SOURCE_FILE (insn) = 0;
7893 /* See whether a single set SET is a noop. */
7895 reload_cse_noop_set_p (set)
7898 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
7901 /* Try to simplify INSN. */
7903 reload_cse_simplify (insn)
7906 rtx body = PATTERN (insn);
7908 if (GET_CODE (body) == SET)
7911 if (reload_cse_noop_set_p (body))
7913 rtx value = SET_DEST (body);
7914 if (! REG_FUNCTION_VALUE_P (SET_DEST (body)))
7916 reload_cse_delete_noop_set (insn, value);
7920 /* It's not a no-op, but we can try to simplify it. */
7921 count += reload_cse_simplify_set (body, insn);
7924 apply_change_group ();
7926 reload_cse_simplify_operands (insn);
7928 else if (GET_CODE (body) == PARALLEL)
7932 rtx value = NULL_RTX;
7934 /* If every action in a PARALLEL is a noop, we can delete
7935 the entire PARALLEL. */
7936 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
7938 rtx part = XVECEXP (body, 0, i);
7939 if (GET_CODE (part) == SET)
7941 if (! reload_cse_noop_set_p (part))
7943 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
7947 value = SET_DEST (part);
7950 else if (GET_CODE (part) != CLOBBER)
7956 reload_cse_delete_noop_set (insn, value);
7957 /* We're done with this insn. */
7961 /* It's not a no-op, but we can try to simplify it. */
7962 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
7963 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
7964 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
7967 apply_change_group ();
7969 reload_cse_simplify_operands (insn);
7973 /* Do a very simple CSE pass over the hard registers.
7975 This function detects no-op moves where we happened to assign two
7976 different pseudo-registers to the same hard register, and then
7977 copied one to the other. Reload will generate a useless
7978 instruction copying a register to itself.
7980 This function also detects cases where we load a value from memory
7981 into two different registers, and (if memory is more expensive than
7982 registers) changes it to simply copy the first register into the
7985 Another optimization is performed that scans the operands of each
7986 instruction to see whether the value is already available in a
7987 hard register. It then replaces the operand with the hard register
7988 if possible, much like an optional reload would. */
7991 reload_cse_regs_1 (first)
7997 init_alias_analysis ();
7999 for (insn = first; insn; insn = NEXT_INSN (insn))
8001 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
8002 reload_cse_simplify (insn);
8004 cselib_process_insn (insn);
8008 end_alias_analysis ();
8012 /* Call cse / combine like post-reload optimization phases.
8013 FIRST is the first instruction. */
8015 reload_cse_regs (first)
8018 reload_cse_regs_1 (first);
8020 reload_cse_move2add (first);
8021 if (flag_expensive_optimizations)
8022 reload_cse_regs_1 (first);
8025 /* Try to simplify a single SET instruction. SET is the set pattern.
8026 INSN is the instruction it came from.
8027 This function only handles one case: if we set a register to a value
8028 which is not a register, we try to find that value in some other register
8029 and change the set into a register copy. */
8032 reload_cse_simplify_set (set, insn)
8039 enum reg_class dclass;
8042 struct elt_loc_list *l;
8044 dreg = true_regnum (SET_DEST (set));
8048 src = SET_SRC (set);
8049 if (side_effects_p (src) || true_regnum (src) >= 0)
8052 dclass = REGNO_REG_CLASS (dreg);
8054 /* If memory loads are cheaper than register copies, don't change them. */
8055 if (GET_CODE (src) == MEM)
8056 old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
8057 else if (CONSTANT_P (src))
8058 old_cost = rtx_cost (src, SET);
8059 else if (GET_CODE (src) == REG)
8060 old_cost = REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (src)), dclass);
8063 old_cost = rtx_cost (src, SET);
8065 val = cselib_lookup (src, VOIDmode, 0);
8068 for (l = val->locs; l; l = l->next)
8071 if (CONSTANT_P (l->loc) && ! references_value_p (l->loc, 0))
8072 this_cost = rtx_cost (l->loc, SET);
8073 else if (GET_CODE (l->loc) == REG)
8074 this_cost = REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (l->loc)),
8078 /* If equal costs, prefer registers over anything else. That tends to
8079 lead to smaller instructions on some machines. */
8080 if ((this_cost < old_cost
8081 || (this_cost == old_cost
8082 && GET_CODE (l->loc) == REG
8083 && GET_CODE (SET_SRC (set)) != REG))
8084 && validate_change (insn, &SET_SRC (set), copy_rtx (l->loc), 1))
8085 old_cost = this_cost, did_change = 1;
8091 /* Try to replace operands in INSN with equivalent values that are already
8092 in registers. This can be viewed as optional reloading.
8094 For each non-register operand in the insn, see if any hard regs are
8095 known to be equivalent to that operand. Record the alternatives which
8096 can accept these hard registers. Among all alternatives, select the
8097 ones which are better or equal to the one currently matching, where
8098 "better" is in terms of '?' and '!' constraints. Among the remaining
8099 alternatives, select the one which replaces most operands with
8103 reload_cse_simplify_operands (insn)
8108 /* For each operand, all registers that are equivalent to it. */
8109 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
8111 const char *constraints[MAX_RECOG_OPERANDS];
8113 /* Vector recording how bad an alternative is. */
8114 int *alternative_reject;
8115 /* Vector recording how many registers can be introduced by choosing
8116 this alternative. */
8117 int *alternative_nregs;
8118 /* Array of vectors recording, for each operand and each alternative,
8119 which hard register to substitute, or -1 if the operand should be
8121 int *op_alt_regno[MAX_RECOG_OPERANDS];
8122 /* Array of alternatives, sorted in order of decreasing desirability. */
8123 int *alternative_order;
8124 rtx reg = gen_rtx_REG (VOIDmode, -1);
8126 extract_insn (insn);
8128 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8131 /* Figure out which alternative currently matches. */
8132 if (! constrain_operands (1))
8133 fatal_insn_not_found (insn);
8135 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8136 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8137 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8138 bzero ((char *)alternative_reject, recog_data.n_alternatives * sizeof (int));
8139 bzero ((char *)alternative_nregs, recog_data.n_alternatives * sizeof (int));
8141 /* For each operand, find out which regs are equivalent. */
8142 for (i = 0; i < recog_data.n_operands; i++)
8145 struct elt_loc_list *l;
8147 CLEAR_HARD_REG_SET (equiv_regs[i]);
8149 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8150 right, so avoid the problem here. */
8151 if (GET_CODE (recog_data.operand[i]) == CODE_LABEL)
8154 v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0);
8158 for (l = v->locs; l; l = l->next)
8159 if (GET_CODE (l->loc) == REG)
8160 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
8163 for (i = 0; i < recog_data.n_operands; i++)
8165 enum machine_mode mode;
8169 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8170 for (j = 0; j < recog_data.n_alternatives; j++)
8171 op_alt_regno[i][j] = -1;
8173 p = constraints[i] = recog_data.constraints[i];
8174 mode = recog_data.operand_mode[i];
8176 /* Add the reject values for each alternative given by the constraints
8177 for this operand. */
8185 alternative_reject[j] += 3;
8187 alternative_reject[j] += 300;
8190 /* We won't change operands which are already registers. We
8191 also don't want to modify output operands. */
8192 regno = true_regnum (recog_data.operand[i]);
8194 || constraints[i][0] == '='
8195 || constraints[i][0] == '+')
8198 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8200 int class = (int) NO_REGS;
8202 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
8205 REGNO (reg) = regno;
8206 PUT_MODE (reg, mode);
8208 /* We found a register equal to this operand. Now look for all
8209 alternatives that can accept this register and have not been
8210 assigned a register they can use yet. */
8219 case '=': case '+': case '?':
8220 case '#': case '&': case '!':
8222 case '0': case '1': case '2': case '3': case '4':
8223 case '5': case '6': case '7': case '8': case '9':
8224 case 'm': case '<': case '>': case 'V': case 'o':
8225 case 'E': case 'F': case 'G': case 'H':
8226 case 's': case 'i': case 'n':
8227 case 'I': case 'J': case 'K': case 'L':
8228 case 'M': case 'N': case 'O': case 'P':
8229 #ifdef EXTRA_CONSTRAINT
8230 case 'Q': case 'R': case 'S': case 'T': case 'U':
8233 /* These don't say anything we care about. */
8237 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8242 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
8245 case ',': case '\0':
8246 /* See if REGNO fits this alternative, and set it up as the
8247 replacement register if we don't have one for this
8248 alternative yet and the operand being replaced is not
8249 a cheap CONST_INT. */
8250 if (op_alt_regno[i][j] == -1
8251 && reg_fits_class_p (reg, class, 0, mode)
8252 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8253 || (rtx_cost (recog_data.operand[i], SET)
8254 > rtx_cost (reg, SET))))
8256 alternative_nregs[j]++;
8257 op_alt_regno[i][j] = regno;
8269 /* Record all alternatives which are better or equal to the currently
8270 matching one in the alternative_order array. */
8271 for (i = j = 0; i < recog_data.n_alternatives; i++)
8272 if (alternative_reject[i] <= alternative_reject[which_alternative])
8273 alternative_order[j++] = i;
8274 recog_data.n_alternatives = j;
8276 /* Sort it. Given a small number of alternatives, a dumb algorithm
8277 won't hurt too much. */
8278 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8281 int best_reject = alternative_reject[alternative_order[i]];
8282 int best_nregs = alternative_nregs[alternative_order[i]];
8285 for (j = i + 1; j < recog_data.n_alternatives; j++)
8287 int this_reject = alternative_reject[alternative_order[j]];
8288 int this_nregs = alternative_nregs[alternative_order[j]];
8290 if (this_reject < best_reject
8291 || (this_reject == best_reject && this_nregs < best_nregs))
8294 best_reject = this_reject;
8295 best_nregs = this_nregs;
8299 tmp = alternative_order[best];
8300 alternative_order[best] = alternative_order[i];
8301 alternative_order[i] = tmp;
8304 /* Substitute the operands as determined by op_alt_regno for the best
8306 j = alternative_order[0];
8308 for (i = 0; i < recog_data.n_operands; i++)
8310 enum machine_mode mode = recog_data.operand_mode[i];
8311 if (op_alt_regno[i][j] == -1)
8314 validate_change (insn, recog_data.operand_loc[i],
8315 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8318 for (i = recog_data.n_dups - 1; i >= 0; i--)
8320 int op = recog_data.dup_num[i];
8321 enum machine_mode mode = recog_data.operand_mode[op];
8323 if (op_alt_regno[op][j] == -1)
8326 validate_change (insn, recog_data.dup_loc[i],
8327 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8330 return apply_change_group ();
8333 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8335 This code might also be useful when reload gave up on reg+reg addresssing
8336 because of clashes between the return register and INDEX_REG_CLASS. */
8338 /* The maximum number of uses of a register we can keep track of to
8339 replace them with reg+reg addressing. */
8340 #define RELOAD_COMBINE_MAX_USES 6
8342 /* INSN is the insn where a register has ben used, and USEP points to the
8343 location of the register within the rtl. */
8344 struct reg_use { rtx insn, *usep; };
8346 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8347 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8348 indicates where it becomes live again.
8349 Otherwise, USE_INDEX is the index of the last encountered use of the
8350 register (which is first among these we have seen since we scan backwards),
8351 OFFSET contains the constant offset that is added to the register in
8352 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8353 last, of these uses.
8354 STORE_RUID is always meaningful if we only want to use a value in a
8355 register in a different place: it denotes the next insn in the insn
8356 stream (i.e. the last ecountered) that sets or clobbers the register. */
8359 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8364 } reg_state[FIRST_PSEUDO_REGISTER];
8366 /* Reverse linear uid. This is increased in reload_combine while scanning
8367 the instructions from last to first. It is used to set last_label_ruid
8368 and the store_ruid / use_ruid fields in reg_state. */
8369 static int reload_combine_ruid;
8371 #define LABEL_LIVE(LABEL) \
8372 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8378 int first_index_reg = 1, last_index_reg = 0;
8380 int last_label_ruid;
8381 int min_labelno, n_labels;
8382 HARD_REG_SET ever_live_at_start, *label_live;
8384 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
8385 reload has already used it where appropriate, so there is no use in
8386 trying to generate it now. */
8387 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8390 /* To avoid wasting too much time later searching for an index register,
8391 determine the minimum and maximum index register numbers. */
8392 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8394 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i))
8396 if (! last_index_reg)
8398 first_index_reg = i;
8401 /* If no index register is available, we can quit now. */
8402 if (first_index_reg > last_index_reg)
8405 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8406 information is a bit fuzzy immediately after reload, but it's
8407 still good enough to determine which registers are live at a jump
8409 min_labelno = get_first_label_num ();
8410 n_labels = max_label_num () - min_labelno;
8411 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8412 CLEAR_HARD_REG_SET (ever_live_at_start);
8413 for (i = n_basic_blocks - 1; i >= 0; i--)
8415 insn = BLOCK_HEAD (i);
8416 if (GET_CODE (insn) == CODE_LABEL)
8420 REG_SET_TO_HARD_REG_SET (live, BASIC_BLOCK (i)->global_live_at_start);
8421 compute_use_by_pseudos (&live, BASIC_BLOCK (i)->global_live_at_start);
8422 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8423 IOR_HARD_REG_SET (ever_live_at_start, live);
8427 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8428 last_label_ruid = reload_combine_ruid = 0;
8429 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8431 reg_state[i].store_ruid = reload_combine_ruid;
8433 reg_state[i].use_index = -1;
8435 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8438 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8442 /* We cannot do our optimization across labels. Invalidating all the use
8443 information we have would be costly, so we just note where the label
8444 is and then later disable any optimization that would cross it. */
8445 if (GET_CODE (insn) == CODE_LABEL)
8446 last_label_ruid = reload_combine_ruid;
8447 if (GET_CODE (insn) == BARRIER)
8449 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8450 if (! fixed_regs[i])
8451 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8453 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8455 reload_combine_ruid++;
8457 /* Look for (set (REGX) (CONST_INT))
8458 (set (REGX) (PLUS (REGX) (REGY)))
8460 ... (MEM (REGX)) ...
8462 (set (REGZ) (CONST_INT))
8464 ... (MEM (PLUS (REGZ) (REGY)))... .
8466 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8467 and that we know all uses of REGX before it dies. */
8468 set = single_set (insn);
8470 && GET_CODE (SET_DEST (set)) == REG
8471 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
8472 GET_MODE (SET_DEST (set)))
8474 && GET_CODE (SET_SRC (set)) == PLUS
8475 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
8476 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
8477 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
8479 rtx reg = SET_DEST (set);
8480 rtx plus = SET_SRC (set);
8481 rtx base = XEXP (plus, 1);
8482 rtx prev = prev_nonnote_insn (insn);
8483 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
8484 int regno = REGNO (reg);
8485 rtx const_reg = NULL_RTX;
8486 rtx reg_sum = NULL_RTX;
8488 /* Now, we need an index register.
8489 We'll set index_reg to this index register, const_reg to the
8490 register that is to be loaded with the constant
8491 (denoted as REGZ in the substitution illustration above),
8492 and reg_sum to the register-register that we want to use to
8493 substitute uses of REG (typically in MEMs) with.
8494 First check REG and BASE for being index registers;
8495 we can use them even if they are not dead. */
8496 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
8497 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8505 /* Otherwise, look for a free index register. Since we have
8506 checked above that neiter REG nor BASE are index registers,
8507 if we find anything at all, it will be different from these
8509 for (i = first_index_reg; i <= last_index_reg; i++)
8511 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i)
8512 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
8513 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
8514 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
8516 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
8517 const_reg = index_reg;
8518 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
8523 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8524 (REGY), i.e. BASE, is not clobbered before the last use we'll
8527 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
8528 && rtx_equal_p (SET_DEST (prev_set), reg)
8529 && reg_state[regno].use_index >= 0
8530 && reg_state[REGNO (base)].store_ruid <= reg_state[regno].use_ruid
8535 /* Change destination register and - if necessary - the
8536 constant value in PREV, the constant loading instruction. */
8537 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
8538 if (reg_state[regno].offset != const0_rtx)
8539 validate_change (prev,
8540 &SET_SRC (prev_set),
8541 GEN_INT (INTVAL (SET_SRC (prev_set))
8542 + INTVAL (reg_state[regno].offset)),
8544 /* Now for every use of REG that we have recorded, replace REG
8546 for (i = reg_state[regno].use_index;
8547 i < RELOAD_COMBINE_MAX_USES; i++)
8548 validate_change (reg_state[regno].reg_use[i].insn,
8549 reg_state[regno].reg_use[i].usep,
8552 if (apply_change_group ())
8556 /* Delete the reg-reg addition. */
8557 PUT_CODE (insn, NOTE);
8558 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8559 NOTE_SOURCE_FILE (insn) = 0;
8561 if (reg_state[regno].offset != const0_rtx)
8563 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8565 for (np = ®_NOTES (prev); *np; )
8567 if (REG_NOTE_KIND (*np) == REG_EQUAL
8568 || REG_NOTE_KIND (*np) == REG_EQUIV)
8569 *np = XEXP (*np, 1);
8571 np = &XEXP (*np, 1);
8574 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8575 reg_state[REGNO (const_reg)].store_ruid = reload_combine_ruid;
8580 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
8581 if (GET_CODE (insn) == CALL_INSN)
8585 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8587 if (call_used_regs[i])
8589 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8590 reg_state[i].store_ruid = reload_combine_ruid;
8593 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
8594 link = XEXP (link, 1))
8596 rtx use = XEXP (link, 0);
8597 int regno = REGNO (XEXP (use, 0));
8598 if (GET_CODE (use) == CLOBBER)
8600 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8601 reg_state[regno].store_ruid = reload_combine_ruid;
8604 reg_state[regno].use_index = -1;
8607 if (GET_CODE (insn) == JUMP_INSN && GET_CODE (PATTERN (insn)) != RETURN)
8609 /* Non-spill registers might be used at the call destination in
8610 some unknown fashion, so we have to mark the unknown use. */
8612 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
8613 && JUMP_LABEL (insn))
8614 live = &LABEL_LIVE (JUMP_LABEL (insn));
8616 live = &ever_live_at_start;
8617 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8619 if (TEST_HARD_REG_BIT (*live, i))
8620 reg_state[i].use_index = -1;
8623 reload_combine_note_use (&PATTERN (insn), insn);
8624 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8626 if (REG_NOTE_KIND (note) == REG_INC
8627 && GET_CODE (XEXP (note, 0)) == REG)
8629 int regno = REGNO (XEXP (note, 0));
8631 reg_state[regno].store_ruid = reload_combine_ruid;
8632 reg_state[regno].use_index = -1;
8639 /* Check if DST is a register or a subreg of a register; if it is,
8640 update reg_state[regno].store_ruid and reg_state[regno].use_index
8641 accordingly. Called via note_stores from reload_combine. */
8643 reload_combine_note_store (dst, set, data)
8645 void *data ATTRIBUTE_UNUSED;
8649 enum machine_mode mode = GET_MODE (dst);
8651 if (GET_CODE (dst) == SUBREG)
8653 regno = SUBREG_WORD (dst);
8654 dst = SUBREG_REG (dst);
8656 if (GET_CODE (dst) != REG)
8658 regno += REGNO (dst);
8660 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8661 careful with registers / register parts that are not full words.
8663 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8664 if (GET_CODE (set) != SET
8665 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
8666 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
8667 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
8669 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8671 reg_state[i].use_index = -1;
8672 reg_state[i].store_ruid = reload_combine_ruid;
8677 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8679 reg_state[i].store_ruid = reload_combine_ruid;
8680 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8685 /* XP points to a piece of rtl that has to be checked for any uses of
8687 *XP is the pattern of INSN, or a part of it.
8688 Called from reload_combine, and recursively by itself. */
8690 reload_combine_note_use (xp, insn)
8694 enum rtx_code code = x->code;
8697 rtx offset = const0_rtx; /* For the REG case below. */
8702 if (GET_CODE (SET_DEST (x)) == REG)
8704 reload_combine_note_use (&SET_SRC (x), insn);
8710 /* If this is the USE of a return value, we can't change it. */
8711 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
8713 /* Mark the return register as used in an unknown fashion. */
8714 rtx reg = XEXP (x, 0);
8715 int regno = REGNO (reg);
8716 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
8718 while (--nregs >= 0)
8719 reg_state[regno + nregs].use_index = -1;
8725 if (GET_CODE (SET_DEST (x)) == REG)
8730 /* We are interested in (plus (reg) (const_int)) . */
8731 if (GET_CODE (XEXP (x, 0)) != REG || GET_CODE (XEXP (x, 1)) != CONST_INT)
8733 offset = XEXP (x, 1);
8738 int regno = REGNO (x);
8742 /* Some spurious USEs of pseudo registers might remain.
8743 Just ignore them. */
8744 if (regno >= FIRST_PSEUDO_REGISTER)
8747 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x));
8749 /* We can't substitute into multi-hard-reg uses. */
8752 while (--nregs >= 0)
8753 reg_state[regno + nregs].use_index = -1;
8757 /* If this register is already used in some unknown fashion, we
8759 If we decrement the index from zero to -1, we can't store more
8760 uses, so this register becomes used in an unknown fashion. */
8761 use_index = --reg_state[regno].use_index;
8765 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
8767 /* We have found another use for a register that is already
8768 used later. Check if the offsets match; if not, mark the
8769 register as used in an unknown fashion. */
8770 if (! rtx_equal_p (offset, reg_state[regno].offset))
8772 reg_state[regno].use_index = -1;
8778 /* This is the first use of this register we have seen since we
8779 marked it as dead. */
8780 reg_state[regno].offset = offset;
8781 reg_state[regno].use_ruid = reload_combine_ruid;
8783 reg_state[regno].reg_use[use_index].insn = insn;
8784 reg_state[regno].reg_use[use_index].usep = xp;
8792 /* Recursively process the components of X. */
8793 fmt = GET_RTX_FORMAT (code);
8794 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8797 reload_combine_note_use (&XEXP (x, i), insn);
8798 else if (fmt[i] == 'E')
8800 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8801 reload_combine_note_use (&XVECEXP (x, i, j), insn);
8806 /* See if we can reduce the cost of a constant by replacing a move with
8808 /* We cannot do our optimization across labels. Invalidating all the
8809 information about register contents we have would be costly, so we
8810 use last_label_luid (local variable of reload_cse_move2add) to note
8811 where the label is and then later disable any optimization that would
8813 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
8814 reg_set_luid[n] is larger than last_label_luid[n] . */
8815 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
8817 /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] /
8818 reg_mode[n] to be valid.
8819 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n
8820 has been set to reg_offset[n] in mode reg_mode[n] .
8821 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative,
8822 register n has been set to the sum of reg_offset[n] and register
8823 reg_base_reg[n], calculated in mode reg_mode[n] . */
8824 static rtx reg_offset[FIRST_PSEUDO_REGISTER];
8825 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
8826 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
8828 /* move2add_luid is linearily increased while scanning the instructions
8829 from first to last. It is used to set reg_set_luid in
8830 reload_cse_move2add and move2add_note_store. */
8831 static int move2add_luid;
8833 /* Generate a CONST_INT and force it in the range of MODE. */
8836 gen_mode_int (mode, value)
8837 enum machine_mode mode;
8838 HOST_WIDE_INT value;
8840 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
8841 int width = GET_MODE_BITSIZE (mode);
8843 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
8845 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
8846 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
8847 cval |= (HOST_WIDE_INT) -1 << width;
8849 return GEN_INT (cval);
8853 reload_cse_move2add (first)
8858 int last_label_luid;
8860 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
8861 reg_set_luid[i] = 0;
8863 last_label_luid = 0;
8865 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
8869 if (GET_CODE (insn) == CODE_LABEL)
8870 last_label_luid = move2add_luid;
8871 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8873 pat = PATTERN (insn);
8874 /* For simplicity, we only perform this optimization on
8875 straightforward SETs. */
8876 if (GET_CODE (pat) == SET
8877 && GET_CODE (SET_DEST (pat)) == REG)
8879 rtx reg = SET_DEST (pat);
8880 int regno = REGNO (reg);
8881 rtx src = SET_SRC (pat);
8883 /* Check if we have valid information on the contents of this
8884 register in the mode of REG. */
8885 /* ??? We don't know how zero / sign extension is handled, hence
8886 we can't go from a narrower to a wider mode. */
8887 if (reg_set_luid[regno] > last_label_luid
8888 && (GET_MODE_SIZE (GET_MODE (reg))
8889 <= GET_MODE_SIZE (reg_mode[regno]))
8890 && GET_CODE (reg_offset[regno]) == CONST_INT)
8892 /* Try to transform (set (REGX) (CONST_INT A))
8894 (set (REGX) (CONST_INT B))
8896 (set (REGX) (CONST_INT A))
8898 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
8900 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
8904 = gen_mode_int (GET_MODE (reg),
8905 INTVAL (src) - INTVAL (reg_offset[regno]));
8906 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
8907 use (set (reg) (reg)) instead.
8908 We don't delete this insn, nor do we convert it into a
8909 note, to avoid losing register notes or the return
8910 value flag. jump2 already knowns how to get rid of
8912 if (new_src == const0_rtx)
8913 success = validate_change (insn, &SET_SRC (pat), reg, 0);
8914 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
8915 && have_add2_insn (GET_MODE (reg)))
8916 success = validate_change (insn, &PATTERN (insn),
8917 gen_add2_insn (reg, new_src), 0);
8918 reg_set_luid[regno] = move2add_luid;
8919 reg_mode[regno] = GET_MODE (reg);
8920 reg_offset[regno] = src;
8924 /* Try to transform (set (REGX) (REGY))
8925 (set (REGX) (PLUS (REGX) (CONST_INT A)))
8928 (set (REGX) (PLUS (REGX) (CONST_INT B)))
8931 (set (REGX) (PLUS (REGX) (CONST_INT A)))
8933 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
8934 else if (GET_CODE (src) == REG
8935 && reg_base_reg[regno] == (int) REGNO (src)
8936 && reg_set_luid[regno] > reg_set_luid[REGNO (src)])
8938 rtx next = next_nonnote_insn (insn);
8941 set = single_set (next);
8944 && SET_DEST (set) == reg
8945 && GET_CODE (SET_SRC (set)) == PLUS
8946 && XEXP (SET_SRC (set), 0) == reg
8947 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
8949 rtx src3 = XEXP (SET_SRC (set), 1);
8951 = gen_mode_int (GET_MODE (reg),
8953 - INTVAL (reg_offset[regno]));
8956 if (new_src == const0_rtx)
8957 /* See above why we create (set (reg) (reg)) here. */
8959 = validate_change (next, &SET_SRC (set), reg, 0);
8960 else if ((rtx_cost (new_src, PLUS)
8961 < 2 + rtx_cost (src3, SET))
8962 && have_add2_insn (GET_MODE (reg)))
8964 = validate_change (next, &PATTERN (next),
8965 gen_add2_insn (reg, new_src), 0);
8968 /* INSN might be the first insn in a basic block
8969 if the preceding insn is a conditional jump
8970 or a possible-throwing call. */
8971 PUT_CODE (insn, NOTE);
8972 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8973 NOTE_SOURCE_FILE (insn) = 0;
8976 reg_set_luid[regno] = move2add_luid;
8977 reg_mode[regno] = GET_MODE (reg);
8978 reg_offset[regno] = src3;
8985 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8987 if (REG_NOTE_KIND (note) == REG_INC
8988 && GET_CODE (XEXP (note, 0)) == REG)
8990 /* Indicate that this register has been recently written to,
8991 but the exact contents are not available. */
8992 int regno = REGNO (XEXP (note, 0));
8993 if (regno < FIRST_PSEUDO_REGISTER)
8995 reg_set_luid[regno] = move2add_luid;
8996 reg_offset[regno] = note;
9000 note_stores (PATTERN (insn), move2add_note_store, NULL);
9001 /* If this is a CALL_INSN, all call used registers are stored with
9003 if (GET_CODE (insn) == CALL_INSN)
9005 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
9007 if (call_used_regs[i])
9009 reg_set_luid[i] = move2add_luid;
9010 reg_offset[i] = insn; /* Invalidate contents. */
9017 /* SET is a SET or CLOBBER that sets DST.
9018 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9019 Called from reload_cse_move2add via note_stores. */
9022 move2add_note_store (dst, set, data)
9024 void *data ATTRIBUTE_UNUSED;
9026 unsigned int regno = 0;
9028 enum machine_mode mode = GET_MODE (dst);
9030 if (GET_CODE (dst) == SUBREG)
9032 regno = SUBREG_WORD (dst);
9033 dst = SUBREG_REG (dst);
9036 if (GET_CODE (dst) != REG)
9039 regno += REGNO (dst);
9041 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9042 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9043 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9044 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9046 rtx src = SET_SRC (set);
9048 reg_mode[regno] = mode;
9049 switch (GET_CODE (src))
9053 rtx src0 = XEXP (src, 0);
9055 if (GET_CODE (src0) == REG)
9057 if (REGNO (src0) != regno
9058 || reg_offset[regno] != const0_rtx)
9060 reg_base_reg[regno] = REGNO (src0);
9061 reg_set_luid[regno] = move2add_luid;
9064 reg_offset[regno] = XEXP (src, 1);
9068 reg_set_luid[regno] = move2add_luid;
9069 reg_offset[regno] = set; /* Invalidate contents. */
9074 reg_base_reg[regno] = REGNO (SET_SRC (set));
9075 reg_offset[regno] = const0_rtx;
9076 reg_set_luid[regno] = move2add_luid;
9080 reg_base_reg[regno] = -1;
9081 reg_offset[regno] = SET_SRC (set);
9082 reg_set_luid[regno] = move2add_luid;
9088 unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode);
9090 for (i = regno; i < endregno; i++)
9092 /* Indicate that this register has been recently written to,
9093 but the exact contents are not available. */
9094 reg_set_luid[i] = move2add_luid;
9095 reg_offset[i] = dst;
9102 add_auto_inc_notes (insn, x)
9106 enum rtx_code code = GET_CODE (x);
9110 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9113 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9117 /* Scan all the operand sub-expressions. */
9118 fmt = GET_RTX_FORMAT (code);
9119 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9122 add_auto_inc_notes (insn, XEXP (x, i));
9123 else if (fmt[i] == 'E')
9124 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9125 add_auto_inc_notes (insn, XVECEXP (x, i, j));
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