1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx *reg_equiv_memory_loc;
105 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
106 collector can keep track of what is inside. */
107 varray_type reg_equiv_memory_loc_varray;
109 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
110 This is used when the address is not valid as a memory address
111 (because its displacement is too big for the machine.) */
112 rtx *reg_equiv_address;
114 /* Element N is the memory slot to which pseudo reg N is equivalent,
115 or zero if pseudo reg N is not equivalent to a memory slot. */
118 /* Widest width in which each pseudo reg is referred to (via subreg). */
119 static unsigned int *reg_max_ref_width;
121 /* Element N is the list of insns that initialized reg N from its equivalent
122 constant or memory slot. */
123 static rtx *reg_equiv_init;
125 /* Vector to remember old contents of reg_renumber before spilling. */
126 static short *reg_old_renumber;
128 /* During reload_as_needed, element N contains the last pseudo regno reloaded
129 into hard register N. If that pseudo reg occupied more than one register,
130 reg_reloaded_contents points to that pseudo for each spill register in
131 use; all of these must remain set for an inheritance to occur. */
132 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
134 /* During reload_as_needed, element N contains the insn for which
135 hard register N was last used. Its contents are significant only
136 when reg_reloaded_valid is set for this register. */
137 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
139 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
140 static HARD_REG_SET reg_reloaded_valid;
141 /* Indicate if the register was dead at the end of the reload.
142 This is only valid if reg_reloaded_contents is set and valid. */
143 static HARD_REG_SET reg_reloaded_dead;
145 /* Indicate whether the register's current value is one that is not
146 safe to retain across a call, even for registers that are normally
148 static HARD_REG_SET reg_reloaded_call_part_clobbered;
150 /* Number of spill-regs so far; number of valid elements of spill_regs. */
153 /* In parallel with spill_regs, contains REG rtx's for those regs.
154 Holds the last rtx used for any given reg, or 0 if it has never
155 been used for spilling yet. This rtx is reused, provided it has
157 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
159 /* In parallel with spill_regs, contains nonzero for a spill reg
160 that was stored after the last time it was used.
161 The precise value is the insn generated to do the store. */
162 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
164 /* This is the register that was stored with spill_reg_store. This is a
165 copy of reload_out / reload_out_reg when the value was stored; if
166 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
167 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
169 /* This table is the inverse mapping of spill_regs:
170 indexed by hard reg number,
171 it contains the position of that reg in spill_regs,
172 or -1 for something that is not in spill_regs.
174 ?!? This is no longer accurate. */
175 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
177 /* This reg set indicates registers that can't be used as spill registers for
178 the currently processed insn. These are the hard registers which are live
179 during the insn, but not allocated to pseudos, as well as fixed
181 static HARD_REG_SET bad_spill_regs;
183 /* These are the hard registers that can't be used as spill register for any
184 insn. This includes registers used for user variables and registers that
185 we can't eliminate. A register that appears in this set also can't be used
186 to retry register allocation. */
187 static HARD_REG_SET bad_spill_regs_global;
189 /* Describes order of use of registers for reloading
190 of spilled pseudo-registers. `n_spills' is the number of
191 elements that are actually valid; new ones are added at the end.
193 Both spill_regs and spill_reg_order are used on two occasions:
194 once during find_reload_regs, where they keep track of the spill registers
195 for a single insn, but also during reload_as_needed where they show all
196 the registers ever used by reload. For the latter case, the information
197 is calculated during finish_spills. */
198 static short spill_regs[FIRST_PSEUDO_REGISTER];
200 /* This vector of reg sets indicates, for each pseudo, which hard registers
201 may not be used for retrying global allocation because the register was
202 formerly spilled from one of them. If we allowed reallocating a pseudo to
203 a register that it was already allocated to, reload might not
205 static HARD_REG_SET *pseudo_previous_regs;
207 /* This vector of reg sets indicates, for each pseudo, which hard
208 registers may not be used for retrying global allocation because they
209 are used as spill registers during one of the insns in which the
211 static HARD_REG_SET *pseudo_forbidden_regs;
213 /* All hard regs that have been used as spill registers for any insn are
214 marked in this set. */
215 static HARD_REG_SET used_spill_regs;
217 /* Index of last register assigned as a spill register. We allocate in
218 a round-robin fashion. */
219 static int last_spill_reg;
221 /* Nonzero if indirect addressing is supported on the machine; this means
222 that spilling (REG n) does not require reloading it into a register in
223 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
224 value indicates the level of indirect addressing supported, e.g., two
225 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
227 static char spill_indirect_levels;
229 /* Nonzero if indirect addressing is supported when the innermost MEM is
230 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
231 which these are valid is the same as spill_indirect_levels, above. */
232 char indirect_symref_ok;
234 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
235 char double_reg_address_ok;
237 /* Record the stack slot for each spilled hard register. */
238 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
240 /* Width allocated so far for that stack slot. */
241 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
243 /* Record which pseudos needed to be spilled. */
244 static regset_head spilled_pseudos;
246 /* Used for communication between order_regs_for_reload and count_pseudo.
247 Used to avoid counting one pseudo twice. */
248 static regset_head pseudos_counted;
250 /* First uid used by insns created by reload in this function.
251 Used in find_equiv_reg. */
252 int reload_first_uid;
254 /* Flag set by local-alloc or global-alloc if anything is live in
255 a call-clobbered reg across calls. */
256 int caller_save_needed;
258 /* Set to 1 while reload_as_needed is operating.
259 Required by some machines to handle any generated moves differently. */
260 int reload_in_progress = 0;
262 /* These arrays record the insn_code of insns that may be needed to
263 perform input and output reloads of special objects. They provide a
264 place to pass a scratch register. */
265 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
266 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
268 /* This obstack is used for allocation of rtl during register elimination.
269 The allocated storage can be freed once find_reloads has processed the
271 struct obstack reload_obstack;
273 /* Points to the beginning of the reload_obstack. All insn_chain structures
274 are allocated first. */
275 char *reload_startobj;
277 /* The point after all insn_chain structures. Used to quickly deallocate
278 memory allocated in copy_reloads during calculate_needs_all_insns. */
279 char *reload_firstobj;
281 /* This points before all local rtl generated by register elimination.
282 Used to quickly free all memory after processing one insn. */
283 static char *reload_insn_firstobj;
285 /* List of insn_chain instructions, one for every insn that reload needs to
287 struct insn_chain *reload_insn_chain;
289 /* List of all insns needing reloads. */
290 static struct insn_chain *insns_need_reload;
292 /* This structure is used to record information about register eliminations.
293 Each array entry describes one possible way of eliminating a register
294 in favor of another. If there is more than one way of eliminating a
295 particular register, the most preferred should be specified first. */
299 int from; /* Register number to be eliminated. */
300 int to; /* Register number used as replacement. */
301 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
302 int can_eliminate; /* Nonzero if this elimination can be done. */
303 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
304 insns made by reload. */
305 HOST_WIDE_INT offset; /* Current offset between the two regs. */
306 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
307 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
308 rtx from_rtx; /* REG rtx for the register to be eliminated.
309 We cannot simply compare the number since
310 we might then spuriously replace a hard
311 register corresponding to a pseudo
312 assigned to the reg to be eliminated. */
313 rtx to_rtx; /* REG rtx for the replacement. */
316 static struct elim_table *reg_eliminate = 0;
318 /* This is an intermediate structure to initialize the table. It has
319 exactly the members provided by ELIMINABLE_REGS. */
320 static const struct elim_table_1
324 } reg_eliminate_1[] =
326 /* If a set of eliminable registers was specified, define the table from it.
327 Otherwise, default to the normal case of the frame pointer being
328 replaced by the stack pointer. */
330 #ifdef ELIMINABLE_REGS
333 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
336 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
338 /* Record the number of pending eliminations that have an offset not equal
339 to their initial offset. If nonzero, we use a new copy of each
340 replacement result in any insns encountered. */
341 int num_not_at_initial_offset;
343 /* Count the number of registers that we may be able to eliminate. */
344 static int num_eliminable;
345 /* And the number of registers that are equivalent to a constant that
346 can be eliminated to frame_pointer / arg_pointer + constant. */
347 static int num_eliminable_invariants;
349 /* For each label, we record the offset of each elimination. If we reach
350 a label by more than one path and an offset differs, we cannot do the
351 elimination. This information is indexed by the difference of the
352 number of the label and the first label number. We can't offset the
353 pointer itself as this can cause problems on machines with segmented
354 memory. The first table is an array of flags that records whether we
355 have yet encountered a label and the second table is an array of arrays,
356 one entry in the latter array for each elimination. */
358 static int first_label_num;
359 static char *offsets_known_at;
360 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
362 /* Number of labels in the current function. */
364 static int num_labels;
366 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
367 static void maybe_fix_stack_asms (void);
368 static void copy_reloads (struct insn_chain *);
369 static void calculate_needs_all_insns (int);
370 static int find_reg (struct insn_chain *, int);
371 static void find_reload_regs (struct insn_chain *);
372 static void select_reload_regs (void);
373 static void delete_caller_save_insns (void);
375 static void spill_failure (rtx, enum reg_class);
376 static void count_spilled_pseudo (int, int, int);
377 static void delete_dead_insn (rtx);
378 static void alter_reg (int, int);
379 static void set_label_offsets (rtx, rtx, int);
380 static void check_eliminable_occurrences (rtx);
381 static void elimination_effects (rtx, enum machine_mode);
382 static int eliminate_regs_in_insn (rtx, int);
383 static void update_eliminable_offsets (void);
384 static void mark_not_eliminable (rtx, rtx, void *);
385 static void set_initial_elim_offsets (void);
386 static void verify_initial_elim_offsets (void);
387 static void set_initial_label_offsets (void);
388 static void set_offsets_for_label (rtx);
389 static void init_elim_table (void);
390 static void update_eliminables (HARD_REG_SET *);
391 static void spill_hard_reg (unsigned int, int);
392 static int finish_spills (int);
393 static void ior_hard_reg_set (HARD_REG_SET *, HARD_REG_SET *);
394 static void scan_paradoxical_subregs (rtx);
395 static void count_pseudo (int);
396 static void order_regs_for_reload (struct insn_chain *);
397 static void reload_as_needed (int);
398 static void forget_old_reloads_1 (rtx, rtx, void *);
399 static int reload_reg_class_lower (const void *, const void *);
400 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
402 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
404 static int reload_reg_free_p (unsigned int, int, enum reload_type);
405 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
407 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
409 static int function_invariant_p (rtx);
410 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
411 static int allocate_reload_reg (struct insn_chain *, int, int);
412 static int conflicts_with_override (rtx);
413 static void failed_reload (rtx, int);
414 static int set_reload_reg (int, int);
415 static void choose_reload_regs_init (struct insn_chain *, rtx *);
416 static void choose_reload_regs (struct insn_chain *);
417 static void merge_assigned_reloads (rtx);
418 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
420 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
422 static void do_input_reload (struct insn_chain *, struct reload *, int);
423 static void do_output_reload (struct insn_chain *, struct reload *, int);
424 static bool inherit_piecemeal_p (int, int);
425 static void emit_reload_insns (struct insn_chain *);
426 static void delete_output_reload (rtx, int, int);
427 static void delete_address_reloads (rtx, rtx);
428 static void delete_address_reloads_1 (rtx, rtx, rtx);
429 static rtx inc_for_reload (rtx, rtx, rtx, int);
431 static void add_auto_inc_notes (rtx, rtx);
433 static void copy_eh_notes (rtx, rtx);
435 /* Initialize the reload pass once per compilation. */
442 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
443 Set spill_indirect_levels to the number of levels such addressing is
444 permitted, zero if it is not permitted at all. */
447 = gen_rtx_MEM (Pmode,
450 LAST_VIRTUAL_REGISTER + 1),
452 spill_indirect_levels = 0;
454 while (memory_address_p (QImode, tem))
456 spill_indirect_levels++;
457 tem = gen_rtx_MEM (Pmode, tem);
460 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
462 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
463 indirect_symref_ok = memory_address_p (QImode, tem);
465 /* See if reg+reg is a valid (and offsettable) address. */
467 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
469 tem = gen_rtx_PLUS (Pmode,
470 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
471 gen_rtx_REG (Pmode, i));
473 /* This way, we make sure that reg+reg is an offsettable address. */
474 tem = plus_constant (tem, 4);
476 if (memory_address_p (QImode, tem))
478 double_reg_address_ok = 1;
483 /* Initialize obstack for our rtl allocation. */
484 gcc_obstack_init (&reload_obstack);
485 reload_startobj = obstack_alloc (&reload_obstack, 0);
487 INIT_REG_SET (&spilled_pseudos);
488 INIT_REG_SET (&pseudos_counted);
489 VARRAY_RTX_INIT (reg_equiv_memory_loc_varray, 0, "reg_equiv_memory_loc");
492 /* List of insn chains that are currently unused. */
493 static struct insn_chain *unused_insn_chains = 0;
495 /* Allocate an empty insn_chain structure. */
497 new_insn_chain (void)
499 struct insn_chain *c;
501 if (unused_insn_chains == 0)
503 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
504 INIT_REG_SET (&c->live_throughout);
505 INIT_REG_SET (&c->dead_or_set);
509 c = unused_insn_chains;
510 unused_insn_chains = c->next;
512 c->is_caller_save_insn = 0;
513 c->need_operand_change = 0;
519 /* Small utility function to set all regs in hard reg set TO which are
520 allocated to pseudos in regset FROM. */
523 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
527 EXECUTE_IF_SET_IN_REG_SET
528 (from, FIRST_PSEUDO_REGISTER, regno,
530 int r = reg_renumber[regno];
535 /* reload_combine uses the information from
536 BASIC_BLOCK->global_live_at_start, which might still
537 contain registers that have not actually been allocated
538 since they have an equivalence. */
539 if (! reload_completed)
544 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)];
546 SET_HARD_REG_BIT (*to, r + nregs);
551 /* Replace all pseudos found in LOC with their corresponding
555 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
568 unsigned int regno = REGNO (x);
570 if (regno < FIRST_PSEUDO_REGISTER)
573 x = eliminate_regs (x, mem_mode, usage);
577 replace_pseudos_in (loc, mem_mode, usage);
581 if (reg_equiv_constant[regno])
582 *loc = reg_equiv_constant[regno];
583 else if (reg_equiv_mem[regno])
584 *loc = reg_equiv_mem[regno];
585 else if (reg_equiv_address[regno])
586 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
587 else if (GET_CODE (regno_reg_rtx[regno]) != REG
588 || REGNO (regno_reg_rtx[regno]) != regno)
589 *loc = regno_reg_rtx[regno];
595 else if (code == MEM)
597 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
601 /* Process each of our operands recursively. */
602 fmt = GET_RTX_FORMAT (code);
603 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
605 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
606 else if (*fmt == 'E')
607 for (j = 0; j < XVECLEN (x, i); j++)
608 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
612 /* Global variables used by reload and its subroutines. */
614 /* Set during calculate_needs if an insn needs register elimination. */
615 static int something_needs_elimination;
616 /* Set during calculate_needs if an insn needs an operand changed. */
617 int something_needs_operands_changed;
619 /* Nonzero means we couldn't get enough spill regs. */
622 /* Main entry point for the reload pass.
624 FIRST is the first insn of the function being compiled.
626 GLOBAL nonzero means we were called from global_alloc
627 and should attempt to reallocate any pseudoregs that we
628 displace from hard regs we will use for reloads.
629 If GLOBAL is zero, we do not have enough information to do that,
630 so any pseudo reg that is spilled must go to the stack.
632 Return value is nonzero if reload failed
633 and we must not do any more for this function. */
636 reload (rtx first, int global)
640 struct elim_table *ep;
643 /* Make sure even insns with volatile mem refs are recognizable. */
648 reload_firstobj = obstack_alloc (&reload_obstack, 0);
650 /* Make sure that the last insn in the chain
651 is not something that needs reloading. */
652 emit_note (NOTE_INSN_DELETED);
654 /* Enable find_equiv_reg to distinguish insns made by reload. */
655 reload_first_uid = get_max_uid ();
657 #ifdef SECONDARY_MEMORY_NEEDED
658 /* Initialize the secondary memory table. */
659 clear_secondary_mem ();
662 /* We don't have a stack slot for any spill reg yet. */
663 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
664 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
666 /* Initialize the save area information for caller-save, in case some
670 /* Compute which hard registers are now in use
671 as homes for pseudo registers.
672 This is done here rather than (eg) in global_alloc
673 because this point is reached even if not optimizing. */
674 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
677 /* A function that receives a nonlocal goto must save all call-saved
679 if (current_function_has_nonlocal_label)
680 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
681 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
682 regs_ever_live[i] = 1;
684 #ifdef NON_SAVING_SETJMP
685 /* A function that calls setjmp should save and restore all the
686 call-saved registers on a system where longjmp clobbers them. */
687 if (NON_SAVING_SETJMP && current_function_calls_setjmp)
689 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
690 if (! call_used_regs[i])
691 regs_ever_live[i] = 1;
695 /* Find all the pseudo registers that didn't get hard regs
696 but do have known equivalent constants or memory slots.
697 These include parameters (known equivalent to parameter slots)
698 and cse'd or loop-moved constant memory addresses.
700 Record constant equivalents in reg_equiv_constant
701 so they will be substituted by find_reloads.
702 Record memory equivalents in reg_mem_equiv so they can
703 be substituted eventually by altering the REG-rtx's. */
705 reg_equiv_constant = xcalloc (max_regno, sizeof (rtx));
706 reg_equiv_mem = xcalloc (max_regno, sizeof (rtx));
707 reg_equiv_init = xcalloc (max_regno, sizeof (rtx));
708 reg_equiv_address = xcalloc (max_regno, sizeof (rtx));
709 reg_max_ref_width = xcalloc (max_regno, sizeof (int));
710 reg_old_renumber = xcalloc (max_regno, sizeof (short));
711 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
712 pseudo_forbidden_regs = xmalloc (max_regno * sizeof (HARD_REG_SET));
713 pseudo_previous_regs = xcalloc (max_regno, sizeof (HARD_REG_SET));
715 CLEAR_HARD_REG_SET (bad_spill_regs_global);
717 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
718 to. Also find all paradoxical subregs and find largest such for
721 num_eliminable_invariants = 0;
722 for (insn = first; insn; insn = NEXT_INSN (insn))
724 rtx set = single_set (insn);
726 /* We may introduce USEs that we want to remove at the end, so
727 we'll mark them with QImode. Make sure there are no
728 previously-marked insns left by say regmove. */
729 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
730 && GET_MODE (insn) != VOIDmode)
731 PUT_MODE (insn, VOIDmode);
733 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
735 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
737 #ifdef LEGITIMATE_PIC_OPERAND_P
738 && (! function_invariant_p (XEXP (note, 0))
740 /* A function invariant is often CONSTANT_P but may
741 include a register. We promise to only pass
742 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
743 || (CONSTANT_P (XEXP (note, 0))
744 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))))
748 rtx x = XEXP (note, 0);
749 i = REGNO (SET_DEST (set));
750 if (i > LAST_VIRTUAL_REGISTER)
752 /* It can happen that a REG_EQUIV note contains a MEM
753 that is not a legitimate memory operand. As later
754 stages of reload assume that all addresses found
755 in the reg_equiv_* arrays were originally legitimate,
756 we ignore such REG_EQUIV notes. */
757 if (memory_operand (x, VOIDmode))
759 /* Always unshare the equivalence, so we can
760 substitute into this insn without touching the
762 reg_equiv_memory_loc[i] = copy_rtx (x);
764 else if (function_invariant_p (x))
766 if (GET_CODE (x) == PLUS)
768 /* This is PLUS of frame pointer and a constant,
769 and might be shared. Unshare it. */
770 reg_equiv_constant[i] = copy_rtx (x);
771 num_eliminable_invariants++;
773 else if (x == frame_pointer_rtx
774 || x == arg_pointer_rtx)
776 reg_equiv_constant[i] = x;
777 num_eliminable_invariants++;
779 else if (LEGITIMATE_CONSTANT_P (x))
780 reg_equiv_constant[i] = x;
783 reg_equiv_memory_loc[i]
784 = force_const_mem (GET_MODE (SET_DEST (set)), x);
785 if (!reg_equiv_memory_loc[i])
792 /* If this register is being made equivalent to a MEM
793 and the MEM is not SET_SRC, the equivalencing insn
794 is one with the MEM as a SET_DEST and it occurs later.
795 So don't mark this insn now. */
796 if (GET_CODE (x) != MEM
797 || rtx_equal_p (SET_SRC (set), x))
799 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
804 /* If this insn is setting a MEM from a register equivalent to it,
805 this is the equivalencing insn. */
806 else if (set && GET_CODE (SET_DEST (set)) == MEM
807 && GET_CODE (SET_SRC (set)) == REG
808 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
809 && rtx_equal_p (SET_DEST (set),
810 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
811 reg_equiv_init[REGNO (SET_SRC (set))]
812 = gen_rtx_INSN_LIST (VOIDmode, insn,
813 reg_equiv_init[REGNO (SET_SRC (set))]);
816 scan_paradoxical_subregs (PATTERN (insn));
821 first_label_num = get_first_label_num ();
822 num_labels = max_label_num () - first_label_num;
824 /* Allocate the tables used to store offset information at labels. */
825 /* We used to use alloca here, but the size of what it would try to
826 allocate would occasionally cause it to exceed the stack limit and
827 cause a core dump. */
828 offsets_known_at = xmalloc (num_labels);
829 offsets_at = xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
831 /* Alter each pseudo-reg rtx to contain its hard reg number.
832 Assign stack slots to the pseudos that lack hard regs or equivalents.
833 Do not touch virtual registers. */
835 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
838 /* If we have some registers we think can be eliminated, scan all insns to
839 see if there is an insn that sets one of these registers to something
840 other than itself plus a constant. If so, the register cannot be
841 eliminated. Doing this scan here eliminates an extra pass through the
842 main reload loop in the most common case where register elimination
844 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
845 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
846 || GET_CODE (insn) == CALL_INSN)
847 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
849 maybe_fix_stack_asms ();
851 insns_need_reload = 0;
852 something_needs_elimination = 0;
854 /* Initialize to -1, which means take the first spill register. */
857 /* Spill any hard regs that we know we can't eliminate. */
858 CLEAR_HARD_REG_SET (used_spill_regs);
859 /* There can be multiple ways to eliminate a register;
860 they should be listed adjacently.
861 Elimination for any register fails only if all possible ways fail. */
862 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
865 int can_eliminate = 0;
868 can_eliminate |= ep->can_eliminate;
871 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
873 spill_hard_reg (from, 1);
876 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
877 if (frame_pointer_needed)
878 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
880 finish_spills (global);
882 /* From now on, we may need to generate moves differently. We may also
883 allow modifications of insns which cause them to not be recognized.
884 Any such modifications will be cleaned up during reload itself. */
885 reload_in_progress = 1;
887 /* This loop scans the entire function each go-round
888 and repeats until one repetition spills no additional hard regs. */
891 int something_changed;
894 HOST_WIDE_INT starting_frame_size;
896 /* Round size of stack frame to stack_alignment_needed. This must be done
897 here because the stack size may be a part of the offset computation
898 for register elimination, and there might have been new stack slots
899 created in the last iteration of this loop. */
900 if (cfun->stack_alignment_needed)
901 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
903 starting_frame_size = get_frame_size ();
905 set_initial_elim_offsets ();
906 set_initial_label_offsets ();
908 /* For each pseudo register that has an equivalent location defined,
909 try to eliminate any eliminable registers (such as the frame pointer)
910 assuming initial offsets for the replacement register, which
913 If the resulting location is directly addressable, substitute
914 the MEM we just got directly for the old REG.
916 If it is not addressable but is a constant or the sum of a hard reg
917 and constant, it is probably not addressable because the constant is
918 out of range, in that case record the address; we will generate
919 hairy code to compute the address in a register each time it is
920 needed. Similarly if it is a hard register, but one that is not
921 valid as an address register.
923 If the location is not addressable, but does not have one of the
924 above forms, assign a stack slot. We have to do this to avoid the
925 potential of producing lots of reloads if, e.g., a location involves
926 a pseudo that didn't get a hard register and has an equivalent memory
927 location that also involves a pseudo that didn't get a hard register.
929 Perhaps at some point we will improve reload_when_needed handling
930 so this problem goes away. But that's very hairy. */
932 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
933 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
935 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
937 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
939 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
940 else if (CONSTANT_P (XEXP (x, 0))
941 || (GET_CODE (XEXP (x, 0)) == REG
942 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
943 || (GET_CODE (XEXP (x, 0)) == PLUS
944 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
945 && (REGNO (XEXP (XEXP (x, 0), 0))
946 < FIRST_PSEUDO_REGISTER)
947 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
948 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
951 /* Make a new stack slot. Then indicate that something
952 changed so we go back and recompute offsets for
953 eliminable registers because the allocation of memory
954 below might change some offset. reg_equiv_{mem,address}
955 will be set up for this pseudo on the next pass around
957 reg_equiv_memory_loc[i] = 0;
958 reg_equiv_init[i] = 0;
963 if (caller_save_needed)
966 /* If we allocated another stack slot, redo elimination bookkeeping. */
967 if (starting_frame_size != get_frame_size ())
970 if (caller_save_needed)
972 save_call_clobbered_regs ();
973 /* That might have allocated new insn_chain structures. */
974 reload_firstobj = obstack_alloc (&reload_obstack, 0);
977 calculate_needs_all_insns (global);
979 CLEAR_REG_SET (&spilled_pseudos);
982 something_changed = 0;
984 /* If we allocated any new memory locations, make another pass
985 since it might have changed elimination offsets. */
986 if (starting_frame_size != get_frame_size ())
987 something_changed = 1;
990 HARD_REG_SET to_spill;
991 CLEAR_HARD_REG_SET (to_spill);
992 update_eliminables (&to_spill);
993 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
994 if (TEST_HARD_REG_BIT (to_spill, i))
996 spill_hard_reg (i, 1);
999 /* Regardless of the state of spills, if we previously had
1000 a register that we thought we could eliminate, but now can
1001 not eliminate, we must run another pass.
1003 Consider pseudos which have an entry in reg_equiv_* which
1004 reference an eliminable register. We must make another pass
1005 to update reg_equiv_* so that we do not substitute in the
1006 old value from when we thought the elimination could be
1008 something_changed = 1;
1012 select_reload_regs ();
1016 if (insns_need_reload != 0 || did_spill)
1017 something_changed |= finish_spills (global);
1019 if (! something_changed)
1022 if (caller_save_needed)
1023 delete_caller_save_insns ();
1025 obstack_free (&reload_obstack, reload_firstobj);
1028 /* If global-alloc was run, notify it of any register eliminations we have
1031 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1032 if (ep->can_eliminate)
1033 mark_elimination (ep->from, ep->to);
1035 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1036 If that insn didn't set the register (i.e., it copied the register to
1037 memory), just delete that insn instead of the equivalencing insn plus
1038 anything now dead. If we call delete_dead_insn on that insn, we may
1039 delete the insn that actually sets the register if the register dies
1040 there and that is incorrect. */
1042 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1044 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1047 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1049 rtx equiv_insn = XEXP (list, 0);
1051 /* If we already deleted the insn or if it may trap, we can't
1052 delete it. The latter case shouldn't happen, but can
1053 if an insn has a variable address, gets a REG_EH_REGION
1054 note added to it, and then gets converted into an load
1055 from a constant address. */
1056 if (GET_CODE (equiv_insn) == NOTE
1057 || can_throw_internal (equiv_insn))
1059 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1060 delete_dead_insn (equiv_insn);
1063 PUT_CODE (equiv_insn, NOTE);
1064 NOTE_SOURCE_FILE (equiv_insn) = 0;
1065 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1071 /* Use the reload registers where necessary
1072 by generating move instructions to move the must-be-register
1073 values into or out of the reload registers. */
1075 if (insns_need_reload != 0 || something_needs_elimination
1076 || something_needs_operands_changed)
1078 HOST_WIDE_INT old_frame_size = get_frame_size ();
1080 reload_as_needed (global);
1082 if (old_frame_size != get_frame_size ())
1086 verify_initial_elim_offsets ();
1089 /* If we were able to eliminate the frame pointer, show that it is no
1090 longer live at the start of any basic block. If it ls live by
1091 virtue of being in a pseudo, that pseudo will be marked live
1092 and hence the frame pointer will be known to be live via that
1095 if (! frame_pointer_needed)
1097 CLEAR_REGNO_REG_SET (bb->global_live_at_start,
1098 HARD_FRAME_POINTER_REGNUM);
1100 /* Come here (with failure set nonzero) if we can't get enough spill regs
1101 and we decide not to abort about it. */
1104 CLEAR_REG_SET (&spilled_pseudos);
1105 reload_in_progress = 0;
1107 /* Now eliminate all pseudo regs by modifying them into
1108 their equivalent memory references.
1109 The REG-rtx's for the pseudos are modified in place,
1110 so all insns that used to refer to them now refer to memory.
1112 For a reg that has a reg_equiv_address, all those insns
1113 were changed by reloading so that no insns refer to it any longer;
1114 but the DECL_RTL of a variable decl may refer to it,
1115 and if so this causes the debugging info to mention the variable. */
1117 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1121 if (reg_equiv_mem[i])
1122 addr = XEXP (reg_equiv_mem[i], 0);
1124 if (reg_equiv_address[i])
1125 addr = reg_equiv_address[i];
1129 if (reg_renumber[i] < 0)
1131 rtx reg = regno_reg_rtx[i];
1133 REG_USERVAR_P (reg) = 0;
1134 PUT_CODE (reg, MEM);
1135 XEXP (reg, 0) = addr;
1136 if (reg_equiv_memory_loc[i])
1137 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1140 RTX_UNCHANGING_P (reg) = MEM_IN_STRUCT_P (reg)
1141 = MEM_SCALAR_P (reg) = 0;
1142 MEM_ATTRS (reg) = 0;
1145 else if (reg_equiv_mem[i])
1146 XEXP (reg_equiv_mem[i], 0) = addr;
1150 /* We must set reload_completed now since the cleanup_subreg_operands call
1151 below will re-recognize each insn and reload may have generated insns
1152 which are only valid during and after reload. */
1153 reload_completed = 1;
1155 /* Make a pass over all the insns and delete all USEs which we inserted
1156 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1157 notes. Delete all CLOBBER insns, except those that refer to the return
1158 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1159 from misarranging variable-array code, and simplify (subreg (reg))
1160 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1161 are no longer useful or accurate. Strip and regenerate REG_INC notes
1162 that may have been moved around. */
1164 for (insn = first; insn; insn = NEXT_INSN (insn))
1169 if (GET_CODE (insn) == CALL_INSN)
1170 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1171 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1173 if ((GET_CODE (PATTERN (insn)) == USE
1174 /* We mark with QImode USEs introduced by reload itself. */
1175 && (GET_MODE (insn) == QImode
1176 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1177 || (GET_CODE (PATTERN (insn)) == CLOBBER
1178 && (GET_CODE (XEXP (PATTERN (insn), 0)) != MEM
1179 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1180 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1181 && XEXP (XEXP (PATTERN (insn), 0), 0)
1182 != stack_pointer_rtx))
1183 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1184 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1190 /* Some CLOBBERs may survive until here and still reference unassigned
1191 pseudos with const equivalent, which may in turn cause ICE in later
1192 passes if the reference remains in place. */
1193 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1194 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1195 VOIDmode, PATTERN (insn));
1197 pnote = ®_NOTES (insn);
1200 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1201 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1202 || REG_NOTE_KIND (*pnote) == REG_INC
1203 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1204 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1205 *pnote = XEXP (*pnote, 1);
1207 pnote = &XEXP (*pnote, 1);
1211 add_auto_inc_notes (insn, PATTERN (insn));
1214 /* And simplify (subreg (reg)) if it appears as an operand. */
1215 cleanup_subreg_operands (insn);
1218 /* If we are doing stack checking, give a warning if this function's
1219 frame size is larger than we expect. */
1220 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1222 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1223 static int verbose_warned = 0;
1225 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1226 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1227 size += UNITS_PER_WORD;
1229 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1231 warning ("frame size too large for reliable stack checking");
1232 if (! verbose_warned)
1234 warning ("try reducing the number of local variables");
1240 /* Indicate that we no longer have known memory locations or constants. */
1241 if (reg_equiv_constant)
1242 free (reg_equiv_constant);
1243 reg_equiv_constant = 0;
1244 VARRAY_GROW (reg_equiv_memory_loc_varray, 0);
1245 reg_equiv_memory_loc = 0;
1247 if (offsets_known_at)
1248 free (offsets_known_at);
1252 free (reg_equiv_mem);
1253 free (reg_equiv_init);
1254 free (reg_equiv_address);
1255 free (reg_max_ref_width);
1256 free (reg_old_renumber);
1257 free (pseudo_previous_regs);
1258 free (pseudo_forbidden_regs);
1260 CLEAR_HARD_REG_SET (used_spill_regs);
1261 for (i = 0; i < n_spills; i++)
1262 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1264 /* Free all the insn_chain structures at once. */
1265 obstack_free (&reload_obstack, reload_startobj);
1266 unused_insn_chains = 0;
1267 fixup_abnormal_edges ();
1269 /* Replacing pseudos with their memory equivalents might have
1270 created shared rtx. Subsequent passes would get confused
1271 by this, so unshare everything here. */
1272 unshare_all_rtl_again (first);
1274 #ifdef STACK_BOUNDARY
1275 /* init_emit has set the alignment of the hard frame pointer
1276 to STACK_BOUNDARY. It is very likely no longer valid if
1277 the hard frame pointer was used for register allocation. */
1278 if (!frame_pointer_needed)
1279 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1285 /* Yet another special case. Unfortunately, reg-stack forces people to
1286 write incorrect clobbers in asm statements. These clobbers must not
1287 cause the register to appear in bad_spill_regs, otherwise we'll call
1288 fatal_insn later. We clear the corresponding regnos in the live
1289 register sets to avoid this.
1290 The whole thing is rather sick, I'm afraid. */
1293 maybe_fix_stack_asms (void)
1296 const char *constraints[MAX_RECOG_OPERANDS];
1297 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1298 struct insn_chain *chain;
1300 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1303 HARD_REG_SET clobbered, allowed;
1306 if (! INSN_P (chain->insn)
1307 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1309 pat = PATTERN (chain->insn);
1310 if (GET_CODE (pat) != PARALLEL)
1313 CLEAR_HARD_REG_SET (clobbered);
1314 CLEAR_HARD_REG_SET (allowed);
1316 /* First, make a mask of all stack regs that are clobbered. */
1317 for (i = 0; i < XVECLEN (pat, 0); i++)
1319 rtx t = XVECEXP (pat, 0, i);
1320 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1321 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1324 /* Get the operand values and constraints out of the insn. */
1325 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1326 constraints, operand_mode);
1328 /* For every operand, see what registers are allowed. */
1329 for (i = 0; i < noperands; i++)
1331 const char *p = constraints[i];
1332 /* For every alternative, we compute the class of registers allowed
1333 for reloading in CLS, and merge its contents into the reg set
1335 int cls = (int) NO_REGS;
1341 if (c == '\0' || c == ',' || c == '#')
1343 /* End of one alternative - mark the regs in the current
1344 class, and reset the class. */
1345 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1351 } while (c != '\0' && c != ',');
1359 case '=': case '+': case '*': case '%': case '?': case '!':
1360 case '0': case '1': case '2': case '3': case '4': case 'm':
1361 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1362 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1363 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1368 cls = (int) reg_class_subunion[cls]
1369 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1374 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1378 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1379 cls = (int) reg_class_subunion[cls]
1380 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1382 cls = (int) reg_class_subunion[cls]
1383 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1385 p += CONSTRAINT_LEN (c, p);
1388 /* Those of the registers which are clobbered, but allowed by the
1389 constraints, must be usable as reload registers. So clear them
1390 out of the life information. */
1391 AND_HARD_REG_SET (allowed, clobbered);
1392 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1393 if (TEST_HARD_REG_BIT (allowed, i))
1395 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1396 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1403 /* Copy the global variables n_reloads and rld into the corresponding elts
1406 copy_reloads (struct insn_chain *chain)
1408 chain->n_reloads = n_reloads;
1409 chain->rld = obstack_alloc (&reload_obstack,
1410 n_reloads * sizeof (struct reload));
1411 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1412 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1415 /* Walk the chain of insns, and determine for each whether it needs reloads
1416 and/or eliminations. Build the corresponding insns_need_reload list, and
1417 set something_needs_elimination as appropriate. */
1419 calculate_needs_all_insns (int global)
1421 struct insn_chain **pprev_reload = &insns_need_reload;
1422 struct insn_chain *chain, *next = 0;
1424 something_needs_elimination = 0;
1426 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1427 for (chain = reload_insn_chain; chain != 0; chain = next)
1429 rtx insn = chain->insn;
1433 /* Clear out the shortcuts. */
1434 chain->n_reloads = 0;
1435 chain->need_elim = 0;
1436 chain->need_reload = 0;
1437 chain->need_operand_change = 0;
1439 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1440 include REG_LABEL), we need to see what effects this has on the
1441 known offsets at labels. */
1443 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1444 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1445 set_label_offsets (insn, insn, 0);
1449 rtx old_body = PATTERN (insn);
1450 int old_code = INSN_CODE (insn);
1451 rtx old_notes = REG_NOTES (insn);
1452 int did_elimination = 0;
1453 int operands_changed = 0;
1454 rtx set = single_set (insn);
1456 /* Skip insns that only set an equivalence. */
1457 if (set && GET_CODE (SET_DEST (set)) == REG
1458 && reg_renumber[REGNO (SET_DEST (set))] < 0
1459 && reg_equiv_constant[REGNO (SET_DEST (set))])
1462 /* If needed, eliminate any eliminable registers. */
1463 if (num_eliminable || num_eliminable_invariants)
1464 did_elimination = eliminate_regs_in_insn (insn, 0);
1466 /* Analyze the instruction. */
1467 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1468 global, spill_reg_order);
1470 /* If a no-op set needs more than one reload, this is likely
1471 to be something that needs input address reloads. We
1472 can't get rid of this cleanly later, and it is of no use
1473 anyway, so discard it now.
1474 We only do this when expensive_optimizations is enabled,
1475 since this complements reload inheritance / output
1476 reload deletion, and it can make debugging harder. */
1477 if (flag_expensive_optimizations && n_reloads > 1)
1479 rtx set = single_set (insn);
1481 && SET_SRC (set) == SET_DEST (set)
1482 && GET_CODE (SET_SRC (set)) == REG
1483 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1486 /* Delete it from the reload chain. */
1488 chain->prev->next = next;
1490 reload_insn_chain = next;
1492 next->prev = chain->prev;
1493 chain->next = unused_insn_chains;
1494 unused_insn_chains = chain;
1499 update_eliminable_offsets ();
1501 /* Remember for later shortcuts which insns had any reloads or
1502 register eliminations. */
1503 chain->need_elim = did_elimination;
1504 chain->need_reload = n_reloads > 0;
1505 chain->need_operand_change = operands_changed;
1507 /* Discard any register replacements done. */
1508 if (did_elimination)
1510 obstack_free (&reload_obstack, reload_insn_firstobj);
1511 PATTERN (insn) = old_body;
1512 INSN_CODE (insn) = old_code;
1513 REG_NOTES (insn) = old_notes;
1514 something_needs_elimination = 1;
1517 something_needs_operands_changed |= operands_changed;
1521 copy_reloads (chain);
1522 *pprev_reload = chain;
1523 pprev_reload = &chain->next_need_reload;
1530 /* Comparison function for qsort to decide which of two reloads
1531 should be handled first. *P1 and *P2 are the reload numbers. */
1534 reload_reg_class_lower (const void *r1p, const void *r2p)
1536 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1539 /* Consider required reloads before optional ones. */
1540 t = rld[r1].optional - rld[r2].optional;
1544 /* Count all solitary classes before non-solitary ones. */
1545 t = ((reg_class_size[(int) rld[r2].class] == 1)
1546 - (reg_class_size[(int) rld[r1].class] == 1));
1550 /* Aside from solitaires, consider all multi-reg groups first. */
1551 t = rld[r2].nregs - rld[r1].nregs;
1555 /* Consider reloads in order of increasing reg-class number. */
1556 t = (int) rld[r1].class - (int) rld[r2].class;
1560 /* If reloads are equally urgent, sort by reload number,
1561 so that the results of qsort leave nothing to chance. */
1565 /* The cost of spilling each hard reg. */
1566 static int spill_cost[FIRST_PSEUDO_REGISTER];
1568 /* When spilling multiple hard registers, we use SPILL_COST for the first
1569 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1570 only the first hard reg for a multi-reg pseudo. */
1571 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1573 /* Update the spill cost arrays, considering that pseudo REG is live. */
1576 count_pseudo (int reg)
1578 int freq = REG_FREQ (reg);
1579 int r = reg_renumber[reg];
1582 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1583 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1586 SET_REGNO_REG_SET (&pseudos_counted, reg);
1591 spill_add_cost[r] += freq;
1593 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1595 spill_cost[r + nregs] += freq;
1598 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1599 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1602 order_regs_for_reload (struct insn_chain *chain)
1605 HARD_REG_SET used_by_pseudos;
1606 HARD_REG_SET used_by_pseudos2;
1608 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1610 memset (spill_cost, 0, sizeof spill_cost);
1611 memset (spill_add_cost, 0, sizeof spill_add_cost);
1613 /* Count number of uses of each hard reg by pseudo regs allocated to it
1614 and then order them by decreasing use. First exclude hard registers
1615 that are live in or across this insn. */
1617 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1618 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1619 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1620 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1622 /* Now find out which pseudos are allocated to it, and update
1624 CLEAR_REG_SET (&pseudos_counted);
1626 EXECUTE_IF_SET_IN_REG_SET
1627 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1631 EXECUTE_IF_SET_IN_REG_SET
1632 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1636 CLEAR_REG_SET (&pseudos_counted);
1639 /* Vector of reload-numbers showing the order in which the reloads should
1641 static short reload_order[MAX_RELOADS];
1643 /* This is used to keep track of the spill regs used in one insn. */
1644 static HARD_REG_SET used_spill_regs_local;
1646 /* We decided to spill hard register SPILLED, which has a size of
1647 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1648 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1649 update SPILL_COST/SPILL_ADD_COST. */
1652 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1654 int r = reg_renumber[reg];
1655 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1657 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1658 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1661 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1663 spill_add_cost[r] -= REG_FREQ (reg);
1665 spill_cost[r + nregs] -= REG_FREQ (reg);
1668 /* Find reload register to use for reload number ORDER. */
1671 find_reg (struct insn_chain *chain, int order)
1673 int rnum = reload_order[order];
1674 struct reload *rl = rld + rnum;
1675 int best_cost = INT_MAX;
1679 HARD_REG_SET not_usable;
1680 HARD_REG_SET used_by_other_reload;
1682 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1683 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1684 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1686 CLEAR_HARD_REG_SET (used_by_other_reload);
1687 for (k = 0; k < order; k++)
1689 int other = reload_order[k];
1691 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1692 for (j = 0; j < rld[other].nregs; j++)
1693 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1696 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1698 unsigned int regno = i;
1700 if (! TEST_HARD_REG_BIT (not_usable, regno)
1701 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1702 && HARD_REGNO_MODE_OK (regno, rl->mode))
1704 int this_cost = spill_cost[regno];
1706 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1708 for (j = 1; j < this_nregs; j++)
1710 this_cost += spill_add_cost[regno + j];
1711 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1712 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1717 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1719 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1721 if (this_cost < best_cost
1722 /* Among registers with equal cost, prefer caller-saved ones, or
1723 use REG_ALLOC_ORDER if it is defined. */
1724 || (this_cost == best_cost
1725 #ifdef REG_ALLOC_ORDER
1726 && (inv_reg_alloc_order[regno]
1727 < inv_reg_alloc_order[best_reg])
1729 && call_used_regs[regno]
1730 && ! call_used_regs[best_reg]
1735 best_cost = this_cost;
1743 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1745 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1746 rl->regno = best_reg;
1748 EXECUTE_IF_SET_IN_REG_SET
1749 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1751 count_spilled_pseudo (best_reg, rl->nregs, j);
1754 EXECUTE_IF_SET_IN_REG_SET
1755 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1757 count_spilled_pseudo (best_reg, rl->nregs, j);
1760 for (i = 0; i < rl->nregs; i++)
1762 if (spill_cost[best_reg + i] != 0
1763 || spill_add_cost[best_reg + i] != 0)
1765 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1770 /* Find more reload regs to satisfy the remaining need of an insn, which
1772 Do it by ascending class number, since otherwise a reg
1773 might be spilled for a big class and might fail to count
1774 for a smaller class even though it belongs to that class. */
1777 find_reload_regs (struct insn_chain *chain)
1781 /* In order to be certain of getting the registers we need,
1782 we must sort the reloads into order of increasing register class.
1783 Then our grabbing of reload registers will parallel the process
1784 that provided the reload registers. */
1785 for (i = 0; i < chain->n_reloads; i++)
1787 /* Show whether this reload already has a hard reg. */
1788 if (chain->rld[i].reg_rtx)
1790 int regno = REGNO (chain->rld[i].reg_rtx);
1791 chain->rld[i].regno = regno;
1793 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1796 chain->rld[i].regno = -1;
1797 reload_order[i] = i;
1800 n_reloads = chain->n_reloads;
1801 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1803 CLEAR_HARD_REG_SET (used_spill_regs_local);
1806 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1808 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1810 /* Compute the order of preference for hard registers to spill. */
1812 order_regs_for_reload (chain);
1814 for (i = 0; i < n_reloads; i++)
1816 int r = reload_order[i];
1818 /* Ignore reloads that got marked inoperative. */
1819 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1820 && ! rld[r].optional
1821 && rld[r].regno == -1)
1822 if (! find_reg (chain, i))
1824 spill_failure (chain->insn, rld[r].class);
1830 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1831 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1833 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1837 select_reload_regs (void)
1839 struct insn_chain *chain;
1841 /* Try to satisfy the needs for each insn. */
1842 for (chain = insns_need_reload; chain != 0;
1843 chain = chain->next_need_reload)
1844 find_reload_regs (chain);
1847 /* Delete all insns that were inserted by emit_caller_save_insns during
1850 delete_caller_save_insns (void)
1852 struct insn_chain *c = reload_insn_chain;
1856 while (c != 0 && c->is_caller_save_insn)
1858 struct insn_chain *next = c->next;
1861 if (c == reload_insn_chain)
1862 reload_insn_chain = next;
1866 next->prev = c->prev;
1868 c->prev->next = next;
1869 c->next = unused_insn_chains;
1870 unused_insn_chains = c;
1878 /* Handle the failure to find a register to spill.
1879 INSN should be one of the insns which needed this particular spill reg. */
1882 spill_failure (rtx insn, enum reg_class class)
1884 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1885 if (asm_noperands (PATTERN (insn)) >= 0)
1886 error_for_asm (insn, "can't find a register in class `%s' while reloading `asm'",
1887 reg_class_names[class]);
1890 error ("unable to find a register to spill in class `%s'",
1891 reg_class_names[class]);
1892 fatal_insn ("this is the insn:", insn);
1896 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1897 data that is dead in INSN. */
1900 delete_dead_insn (rtx insn)
1902 rtx prev = prev_real_insn (insn);
1905 /* If the previous insn sets a register that dies in our insn, delete it
1907 if (prev && GET_CODE (PATTERN (prev)) == SET
1908 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1909 && reg_mentioned_p (prev_dest, PATTERN (insn))
1910 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1911 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1912 delete_dead_insn (prev);
1914 PUT_CODE (insn, NOTE);
1915 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1916 NOTE_SOURCE_FILE (insn) = 0;
1919 /* Modify the home of pseudo-reg I.
1920 The new home is present in reg_renumber[I].
1922 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1923 or it may be -1, meaning there is none or it is not relevant.
1924 This is used so that all pseudos spilled from a given hard reg
1925 can share one stack slot. */
1928 alter_reg (int i, int from_reg)
1930 /* When outputting an inline function, this can happen
1931 for a reg that isn't actually used. */
1932 if (regno_reg_rtx[i] == 0)
1935 /* If the reg got changed to a MEM at rtl-generation time,
1937 if (GET_CODE (regno_reg_rtx[i]) != REG)
1940 /* Modify the reg-rtx to contain the new hard reg
1941 number or else to contain its pseudo reg number. */
1942 REGNO (regno_reg_rtx[i])
1943 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1945 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1946 allocate a stack slot for it. */
1948 if (reg_renumber[i] < 0
1949 && REG_N_REFS (i) > 0
1950 && reg_equiv_constant[i] == 0
1951 && reg_equiv_memory_loc[i] == 0)
1954 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1955 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1958 /* Each pseudo reg has an inherent size which comes from its own mode,
1959 and a total size which provides room for paradoxical subregs
1960 which refer to the pseudo reg in wider modes.
1962 We can use a slot already allocated if it provides both
1963 enough inherent space and enough total space.
1964 Otherwise, we allocate a new slot, making sure that it has no less
1965 inherent space, and no less total space, then the previous slot. */
1968 /* No known place to spill from => no slot to reuse. */
1969 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1970 inherent_size == total_size ? 0 : -1);
1971 if (BYTES_BIG_ENDIAN)
1972 /* Cancel the big-endian correction done in assign_stack_local.
1973 Get the address of the beginning of the slot.
1974 This is so we can do a big-endian correction unconditionally
1976 adjust = inherent_size - total_size;
1978 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1980 /* Nothing can alias this slot except this pseudo. */
1981 set_mem_alias_set (x, new_alias_set ());
1984 /* Reuse a stack slot if possible. */
1985 else if (spill_stack_slot[from_reg] != 0
1986 && spill_stack_slot_width[from_reg] >= total_size
1987 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1989 x = spill_stack_slot[from_reg];
1991 /* Allocate a bigger slot. */
1994 /* Compute maximum size needed, both for inherent size
1995 and for total size. */
1996 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1999 if (spill_stack_slot[from_reg])
2001 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2003 mode = GET_MODE (spill_stack_slot[from_reg]);
2004 if (spill_stack_slot_width[from_reg] > total_size)
2005 total_size = spill_stack_slot_width[from_reg];
2008 /* Make a slot with that size. */
2009 x = assign_stack_local (mode, total_size,
2010 inherent_size == total_size ? 0 : -1);
2013 /* All pseudos mapped to this slot can alias each other. */
2014 if (spill_stack_slot[from_reg])
2015 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2017 set_mem_alias_set (x, new_alias_set ());
2019 if (BYTES_BIG_ENDIAN)
2021 /* Cancel the big-endian correction done in assign_stack_local.
2022 Get the address of the beginning of the slot.
2023 This is so we can do a big-endian correction unconditionally
2025 adjust = GET_MODE_SIZE (mode) - total_size;
2028 = adjust_address_nv (x, mode_for_size (total_size
2034 spill_stack_slot[from_reg] = stack_slot;
2035 spill_stack_slot_width[from_reg] = total_size;
2038 /* On a big endian machine, the "address" of the slot
2039 is the address of the low part that fits its inherent mode. */
2040 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2041 adjust += (total_size - inherent_size);
2043 /* If we have any adjustment to make, or if the stack slot is the
2044 wrong mode, make a new stack slot. */
2045 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2047 /* If we have a decl for the original register, set it for the
2048 memory. If this is a shared MEM, make a copy. */
2049 if (REG_EXPR (regno_reg_rtx[i])
2050 && TREE_CODE_CLASS (TREE_CODE (REG_EXPR (regno_reg_rtx[i]))) == 'd')
2052 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2054 /* We can do this only for the DECLs home pseudo, not for
2055 any copies of it, since otherwise when the stack slot
2056 is reused, nonoverlapping_memrefs_p might think they
2058 if (decl && GET_CODE (decl) == REG && REGNO (decl) == (unsigned) i)
2060 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2063 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2067 /* Save the stack slot for later. */
2068 reg_equiv_memory_loc[i] = x;
2072 /* Mark the slots in regs_ever_live for the hard regs
2073 used by pseudo-reg number REGNO. */
2076 mark_home_live (int regno)
2080 i = reg_renumber[regno];
2083 lim = i + hard_regno_nregs[i][PSEUDO_REGNO_MODE (regno)];
2085 regs_ever_live[i++] = 1;
2088 /* This function handles the tracking of elimination offsets around branches.
2090 X is a piece of RTL being scanned.
2092 INSN is the insn that it came from, if any.
2094 INITIAL_P is nonzero if we are to set the offset to be the initial
2095 offset and zero if we are setting the offset of the label to be the
2099 set_label_offsets (rtx x, rtx insn, int initial_p)
2101 enum rtx_code code = GET_CODE (x);
2104 struct elim_table *p;
2109 if (LABEL_REF_NONLOCAL_P (x))
2114 /* ... fall through ... */
2117 /* If we know nothing about this label, set the desired offsets. Note
2118 that this sets the offset at a label to be the offset before a label
2119 if we don't know anything about the label. This is not correct for
2120 the label after a BARRIER, but is the best guess we can make. If
2121 we guessed wrong, we will suppress an elimination that might have
2122 been possible had we been able to guess correctly. */
2124 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2126 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2127 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2128 = (initial_p ? reg_eliminate[i].initial_offset
2129 : reg_eliminate[i].offset);
2130 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2133 /* Otherwise, if this is the definition of a label and it is
2134 preceded by a BARRIER, set our offsets to the known offset of
2138 && (tem = prev_nonnote_insn (insn)) != 0
2139 && GET_CODE (tem) == BARRIER)
2140 set_offsets_for_label (insn);
2142 /* If neither of the above cases is true, compare each offset
2143 with those previously recorded and suppress any eliminations
2144 where the offsets disagree. */
2146 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2147 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2148 != (initial_p ? reg_eliminate[i].initial_offset
2149 : reg_eliminate[i].offset))
2150 reg_eliminate[i].can_eliminate = 0;
2155 set_label_offsets (PATTERN (insn), insn, initial_p);
2157 /* ... fall through ... */
2161 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2162 and hence must have all eliminations at their initial offsets. */
2163 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2164 if (REG_NOTE_KIND (tem) == REG_LABEL)
2165 set_label_offsets (XEXP (tem, 0), insn, 1);
2171 /* Each of the labels in the parallel or address vector must be
2172 at their initial offsets. We want the first field for PARALLEL
2173 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2175 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2176 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2181 /* We only care about setting PC. If the source is not RETURN,
2182 IF_THEN_ELSE, or a label, disable any eliminations not at
2183 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2184 isn't one of those possibilities. For branches to a label,
2185 call ourselves recursively.
2187 Note that this can disable elimination unnecessarily when we have
2188 a non-local goto since it will look like a non-constant jump to
2189 someplace in the current function. This isn't a significant
2190 problem since such jumps will normally be when all elimination
2191 pairs are back to their initial offsets. */
2193 if (SET_DEST (x) != pc_rtx)
2196 switch (GET_CODE (SET_SRC (x)))
2203 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2207 tem = XEXP (SET_SRC (x), 1);
2208 if (GET_CODE (tem) == LABEL_REF)
2209 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2210 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2213 tem = XEXP (SET_SRC (x), 2);
2214 if (GET_CODE (tem) == LABEL_REF)
2215 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2216 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2224 /* If we reach here, all eliminations must be at their initial
2225 offset because we are doing a jump to a variable address. */
2226 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2227 if (p->offset != p->initial_offset)
2228 p->can_eliminate = 0;
2236 /* Scan X and replace any eliminable registers (such as fp) with a
2237 replacement (such as sp), plus an offset.
2239 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2240 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2241 MEM, we are allowed to replace a sum of a register and the constant zero
2242 with the register, which we cannot do outside a MEM. In addition, we need
2243 to record the fact that a register is referenced outside a MEM.
2245 If INSN is an insn, it is the insn containing X. If we replace a REG
2246 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2247 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2248 the REG is being modified.
2250 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2251 That's used when we eliminate in expressions stored in notes.
2252 This means, do not set ref_outside_mem even if the reference
2255 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2256 replacements done assuming all offsets are at their initial values. If
2257 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2258 encounter, return the actual location so that find_reloads will do
2259 the proper thing. */
2262 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2264 enum rtx_code code = GET_CODE (x);
2265 struct elim_table *ep;
2272 if (! current_function_decl)
2292 /* This is only for the benefit of the debugging backends, which call
2293 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2294 removed after CSE. */
2295 new = eliminate_regs (XEXP (x, 0), 0, insn);
2296 if (GET_CODE (new) == MEM)
2297 return XEXP (new, 0);
2303 /* First handle the case where we encounter a bare register that
2304 is eliminable. Replace it with a PLUS. */
2305 if (regno < FIRST_PSEUDO_REGISTER)
2307 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2309 if (ep->from_rtx == x && ep->can_eliminate)
2310 return plus_constant (ep->to_rtx, ep->previous_offset);
2313 else if (reg_renumber && reg_renumber[regno] < 0
2314 && reg_equiv_constant && reg_equiv_constant[regno]
2315 && ! CONSTANT_P (reg_equiv_constant[regno]))
2316 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2320 /* You might think handling MINUS in a manner similar to PLUS is a
2321 good idea. It is not. It has been tried multiple times and every
2322 time the change has had to have been reverted.
2324 Other parts of reload know a PLUS is special (gen_reload for example)
2325 and require special code to handle code a reloaded PLUS operand.
2327 Also consider backends where the flags register is clobbered by a
2328 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2329 lea instruction comes to mind). If we try to reload a MINUS, we
2330 may kill the flags register that was holding a useful value.
2332 So, please before trying to handle MINUS, consider reload as a
2333 whole instead of this little section as well as the backend issues. */
2335 /* If this is the sum of an eliminable register and a constant, rework
2337 if (GET_CODE (XEXP (x, 0)) == REG
2338 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2339 && CONSTANT_P (XEXP (x, 1)))
2341 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2343 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2345 /* The only time we want to replace a PLUS with a REG (this
2346 occurs when the constant operand of the PLUS is the negative
2347 of the offset) is when we are inside a MEM. We won't want
2348 to do so at other times because that would change the
2349 structure of the insn in a way that reload can't handle.
2350 We special-case the commonest situation in
2351 eliminate_regs_in_insn, so just replace a PLUS with a
2352 PLUS here, unless inside a MEM. */
2353 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2354 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2357 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2358 plus_constant (XEXP (x, 1),
2359 ep->previous_offset));
2362 /* If the register is not eliminable, we are done since the other
2363 operand is a constant. */
2367 /* If this is part of an address, we want to bring any constant to the
2368 outermost PLUS. We will do this by doing register replacement in
2369 our operands and seeing if a constant shows up in one of them.
2371 Note that there is no risk of modifying the structure of the insn,
2372 since we only get called for its operands, thus we are either
2373 modifying the address inside a MEM, or something like an address
2374 operand of a load-address insn. */
2377 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2378 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2380 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2382 /* If one side is a PLUS and the other side is a pseudo that
2383 didn't get a hard register but has a reg_equiv_constant,
2384 we must replace the constant here since it may no longer
2385 be in the position of any operand. */
2386 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2387 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2388 && reg_renumber[REGNO (new1)] < 0
2389 && reg_equiv_constant != 0
2390 && reg_equiv_constant[REGNO (new1)] != 0)
2391 new1 = reg_equiv_constant[REGNO (new1)];
2392 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2393 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2394 && reg_renumber[REGNO (new0)] < 0
2395 && reg_equiv_constant[REGNO (new0)] != 0)
2396 new0 = reg_equiv_constant[REGNO (new0)];
2398 new = form_sum (new0, new1);
2400 /* As above, if we are not inside a MEM we do not want to
2401 turn a PLUS into something else. We might try to do so here
2402 for an addition of 0 if we aren't optimizing. */
2403 if (! mem_mode && GET_CODE (new) != PLUS)
2404 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2412 /* If this is the product of an eliminable register and a
2413 constant, apply the distribute law and move the constant out
2414 so that we have (plus (mult ..) ..). This is needed in order
2415 to keep load-address insns valid. This case is pathological.
2416 We ignore the possibility of overflow here. */
2417 if (GET_CODE (XEXP (x, 0)) == REG
2418 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2419 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2420 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2422 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2425 /* Refs inside notes don't count for this purpose. */
2426 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2427 || GET_CODE (insn) == INSN_LIST)))
2428 ep->ref_outside_mem = 1;
2431 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2432 ep->previous_offset * INTVAL (XEXP (x, 1)));
2435 /* ... fall through ... */
2439 /* See comments before PLUS about handling MINUS. */
2441 case DIV: case UDIV:
2442 case MOD: case UMOD:
2443 case AND: case IOR: case XOR:
2444 case ROTATERT: case ROTATE:
2445 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2447 case GE: case GT: case GEU: case GTU:
2448 case LE: case LT: case LEU: case LTU:
2450 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2452 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2454 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2455 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2460 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2463 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2464 if (new != XEXP (x, 0))
2466 /* If this is a REG_DEAD note, it is not valid anymore.
2467 Using the eliminated version could result in creating a
2468 REG_DEAD note for the stack or frame pointer. */
2469 if (GET_MODE (x) == REG_DEAD)
2471 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2474 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2478 /* ... fall through ... */
2481 /* Now do eliminations in the rest of the chain. If this was
2482 an EXPR_LIST, this might result in allocating more memory than is
2483 strictly needed, but it simplifies the code. */
2486 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2487 if (new != XEXP (x, 1))
2489 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2497 case STRICT_LOW_PART:
2499 case SIGN_EXTEND: case ZERO_EXTEND:
2500 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2501 case FLOAT: case FIX:
2502 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2510 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2511 if (new != XEXP (x, 0))
2512 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2516 /* Similar to above processing, but preserve SUBREG_BYTE.
2517 Convert (subreg (mem)) to (mem) if not paradoxical.
2518 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2519 pseudo didn't get a hard reg, we must replace this with the
2520 eliminated version of the memory location because push_reload
2521 may do the replacement in certain circumstances. */
2522 if (GET_CODE (SUBREG_REG (x)) == REG
2523 && (GET_MODE_SIZE (GET_MODE (x))
2524 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2525 && reg_equiv_memory_loc != 0
2526 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2528 new = SUBREG_REG (x);
2531 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2533 if (new != SUBREG_REG (x))
2535 int x_size = GET_MODE_SIZE (GET_MODE (x));
2536 int new_size = GET_MODE_SIZE (GET_MODE (new));
2538 if (GET_CODE (new) == MEM
2539 && ((x_size < new_size
2540 #ifdef WORD_REGISTER_OPERATIONS
2541 /* On these machines, combine can create rtl of the form
2542 (set (subreg:m1 (reg:m2 R) 0) ...)
2543 where m1 < m2, and expects something interesting to
2544 happen to the entire word. Moreover, it will use the
2545 (reg:m2 R) later, expecting all bits to be preserved.
2546 So if the number of words is the same, preserve the
2547 subreg so that push_reload can see it. */
2548 && ! ((x_size - 1) / UNITS_PER_WORD
2549 == (new_size -1 ) / UNITS_PER_WORD)
2552 || x_size == new_size)
2554 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2556 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2562 /* This is only for the benefit of the debugging backends, which call
2563 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2564 removed after CSE. */
2565 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2566 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2568 /* Our only special processing is to pass the mode of the MEM to our
2569 recursive call and copy the flags. While we are here, handle this
2570 case more efficiently. */
2572 replace_equiv_address_nv (x,
2573 eliminate_regs (XEXP (x, 0),
2574 GET_MODE (x), insn));
2577 /* Handle insn_list USE that a call to a pure function may generate. */
2578 new = eliminate_regs (XEXP (x, 0), 0, insn);
2579 if (new != XEXP (x, 0))
2580 return gen_rtx_USE (GET_MODE (x), new);
2592 /* Process each of our operands recursively. If any have changed, make a
2594 fmt = GET_RTX_FORMAT (code);
2595 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2599 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2600 if (new != XEXP (x, i) && ! copied)
2602 rtx new_x = rtx_alloc (code);
2603 memcpy (new_x, x, RTX_SIZE (code));
2609 else if (*fmt == 'E')
2612 for (j = 0; j < XVECLEN (x, i); j++)
2614 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2615 if (new != XVECEXP (x, i, j) && ! copied_vec)
2617 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2621 rtx new_x = rtx_alloc (code);
2622 memcpy (new_x, x, RTX_SIZE (code));
2626 XVEC (x, i) = new_v;
2629 XVECEXP (x, i, j) = new;
2637 /* Scan rtx X for modifications of elimination target registers. Update
2638 the table of eliminables to reflect the changed state. MEM_MODE is
2639 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2642 elimination_effects (rtx x, enum machine_mode mem_mode)
2644 enum rtx_code code = GET_CODE (x);
2645 struct elim_table *ep;
2672 /* First handle the case where we encounter a bare register that
2673 is eliminable. Replace it with a PLUS. */
2674 if (regno < FIRST_PSEUDO_REGISTER)
2676 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2678 if (ep->from_rtx == x && ep->can_eliminate)
2681 ep->ref_outside_mem = 1;
2686 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2687 && reg_equiv_constant[regno]
2688 && ! function_invariant_p (reg_equiv_constant[regno]))
2689 elimination_effects (reg_equiv_constant[regno], mem_mode);
2698 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2699 if (ep->to_rtx == XEXP (x, 0))
2701 int size = GET_MODE_SIZE (mem_mode);
2703 /* If more bytes than MEM_MODE are pushed, account for them. */
2704 #ifdef PUSH_ROUNDING
2705 if (ep->to_rtx == stack_pointer_rtx)
2706 size = PUSH_ROUNDING (size);
2708 if (code == PRE_DEC || code == POST_DEC)
2710 else if (code == PRE_INC || code == POST_INC)
2712 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2713 && GET_CODE (XEXP (x, 1)) == PLUS
2714 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2715 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2716 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2719 /* These two aren't unary operators. */
2720 if (code == POST_MODIFY || code == PRE_MODIFY)
2723 /* Fall through to generic unary operation case. */
2724 case STRICT_LOW_PART:
2726 case SIGN_EXTEND: case ZERO_EXTEND:
2727 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2728 case FLOAT: case FIX:
2729 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2737 elimination_effects (XEXP (x, 0), mem_mode);
2741 if (GET_CODE (SUBREG_REG (x)) == REG
2742 && (GET_MODE_SIZE (GET_MODE (x))
2743 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2744 && reg_equiv_memory_loc != 0
2745 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2748 elimination_effects (SUBREG_REG (x), mem_mode);
2752 /* If using a register that is the source of an eliminate we still
2753 think can be performed, note it cannot be performed since we don't
2754 know how this register is used. */
2755 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2756 if (ep->from_rtx == XEXP (x, 0))
2757 ep->can_eliminate = 0;
2759 elimination_effects (XEXP (x, 0), mem_mode);
2763 /* If clobbering a register that is the replacement register for an
2764 elimination we still think can be performed, note that it cannot
2765 be performed. Otherwise, we need not be concerned about it. */
2766 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2767 if (ep->to_rtx == XEXP (x, 0))
2768 ep->can_eliminate = 0;
2770 elimination_effects (XEXP (x, 0), mem_mode);
2774 /* Check for setting a register that we know about. */
2775 if (GET_CODE (SET_DEST (x)) == REG)
2777 /* See if this is setting the replacement register for an
2780 If DEST is the hard frame pointer, we do nothing because we
2781 assume that all assignments to the frame pointer are for
2782 non-local gotos and are being done at a time when they are valid
2783 and do not disturb anything else. Some machines want to
2784 eliminate a fake argument pointer (or even a fake frame pointer)
2785 with either the real frame or the stack pointer. Assignments to
2786 the hard frame pointer must not prevent this elimination. */
2788 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2790 if (ep->to_rtx == SET_DEST (x)
2791 && SET_DEST (x) != hard_frame_pointer_rtx)
2793 /* If it is being incremented, adjust the offset. Otherwise,
2794 this elimination can't be done. */
2795 rtx src = SET_SRC (x);
2797 if (GET_CODE (src) == PLUS
2798 && XEXP (src, 0) == SET_DEST (x)
2799 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2800 ep->offset -= INTVAL (XEXP (src, 1));
2802 ep->can_eliminate = 0;
2806 elimination_effects (SET_DEST (x), 0);
2807 elimination_effects (SET_SRC (x), 0);
2811 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2814 /* Our only special processing is to pass the mode of the MEM to our
2816 elimination_effects (XEXP (x, 0), GET_MODE (x));
2823 fmt = GET_RTX_FORMAT (code);
2824 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2827 elimination_effects (XEXP (x, i), mem_mode);
2828 else if (*fmt == 'E')
2829 for (j = 0; j < XVECLEN (x, i); j++)
2830 elimination_effects (XVECEXP (x, i, j), mem_mode);
2834 /* Descend through rtx X and verify that no references to eliminable registers
2835 remain. If any do remain, mark the involved register as not
2839 check_eliminable_occurrences (rtx x)
2848 code = GET_CODE (x);
2850 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2852 struct elim_table *ep;
2854 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2855 if (ep->from_rtx == x)
2856 ep->can_eliminate = 0;
2860 fmt = GET_RTX_FORMAT (code);
2861 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2864 check_eliminable_occurrences (XEXP (x, i));
2865 else if (*fmt == 'E')
2868 for (j = 0; j < XVECLEN (x, i); j++)
2869 check_eliminable_occurrences (XVECEXP (x, i, j));
2874 /* Scan INSN and eliminate all eliminable registers in it.
2876 If REPLACE is nonzero, do the replacement destructively. Also
2877 delete the insn as dead it if it is setting an eliminable register.
2879 If REPLACE is zero, do all our allocations in reload_obstack.
2881 If no eliminations were done and this insn doesn't require any elimination
2882 processing (these are not identical conditions: it might be updating sp,
2883 but not referencing fp; this needs to be seen during reload_as_needed so
2884 that the offset between fp and sp can be taken into consideration), zero
2885 is returned. Otherwise, 1 is returned. */
2888 eliminate_regs_in_insn (rtx insn, int replace)
2890 int icode = recog_memoized (insn);
2891 rtx old_body = PATTERN (insn);
2892 int insn_is_asm = asm_noperands (old_body) >= 0;
2893 rtx old_set = single_set (insn);
2897 rtx substed_operand[MAX_RECOG_OPERANDS];
2898 rtx orig_operand[MAX_RECOG_OPERANDS];
2899 struct elim_table *ep;
2902 if (! insn_is_asm && icode < 0)
2904 if (GET_CODE (PATTERN (insn)) == USE
2905 || GET_CODE (PATTERN (insn)) == CLOBBER
2906 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2907 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2908 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2913 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2914 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2916 /* Check for setting an eliminable register. */
2917 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2918 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2920 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2921 /* If this is setting the frame pointer register to the
2922 hardware frame pointer register and this is an elimination
2923 that will be done (tested above), this insn is really
2924 adjusting the frame pointer downward to compensate for
2925 the adjustment done before a nonlocal goto. */
2926 if (ep->from == FRAME_POINTER_REGNUM
2927 && ep->to == HARD_FRAME_POINTER_REGNUM)
2929 rtx base = SET_SRC (old_set);
2930 rtx base_insn = insn;
2931 HOST_WIDE_INT offset = 0;
2933 while (base != ep->to_rtx)
2935 rtx prev_insn, prev_set;
2937 if (GET_CODE (base) == PLUS
2938 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2940 offset += INTVAL (XEXP (base, 1));
2941 base = XEXP (base, 0);
2943 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2944 && (prev_set = single_set (prev_insn)) != 0
2945 && rtx_equal_p (SET_DEST (prev_set), base))
2947 base = SET_SRC (prev_set);
2948 base_insn = prev_insn;
2954 if (base == ep->to_rtx)
2957 = plus_constant (ep->to_rtx, offset - ep->offset);
2959 new_body = old_body;
2962 new_body = copy_insn (old_body);
2963 if (REG_NOTES (insn))
2964 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2966 PATTERN (insn) = new_body;
2967 old_set = single_set (insn);
2969 /* First see if this insn remains valid when we
2970 make the change. If not, keep the INSN_CODE
2971 the same and let reload fit it up. */
2972 validate_change (insn, &SET_SRC (old_set), src, 1);
2973 validate_change (insn, &SET_DEST (old_set),
2975 if (! apply_change_group ())
2977 SET_SRC (old_set) = src;
2978 SET_DEST (old_set) = ep->to_rtx;
2987 /* In this case this insn isn't serving a useful purpose. We
2988 will delete it in reload_as_needed once we know that this
2989 elimination is, in fact, being done.
2991 If REPLACE isn't set, we can't delete this insn, but needn't
2992 process it since it won't be used unless something changes. */
2995 delete_dead_insn (insn);
3003 /* We allow one special case which happens to work on all machines we
3004 currently support: a single set with the source or a REG_EQUAL
3005 note being a PLUS of an eliminable register and a constant. */
3007 if (old_set && GET_CODE (SET_DEST (old_set)) == REG)
3009 /* First see if the source is of the form (plus (reg) CST). */
3010 if (GET_CODE (SET_SRC (old_set)) == PLUS
3011 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3012 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
3013 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
3014 plus_src = SET_SRC (old_set);
3015 else if (GET_CODE (SET_SRC (old_set)) == REG)
3017 /* Otherwise, see if we have a REG_EQUAL note of the form
3018 (plus (reg) CST). */
3020 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3022 if (REG_NOTE_KIND (links) == REG_EQUAL
3023 && GET_CODE (XEXP (links, 0)) == PLUS
3024 && GET_CODE (XEXP (XEXP (links, 0), 0)) == REG
3025 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT
3026 && REGNO (XEXP (XEXP (links, 0), 0)) < FIRST_PSEUDO_REGISTER)
3028 plus_src = XEXP (links, 0);
3036 rtx reg = XEXP (plus_src, 0);
3037 HOST_WIDE_INT offset = INTVAL (XEXP (plus_src, 1));
3039 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3040 if (ep->from_rtx == reg && ep->can_eliminate)
3042 offset += ep->offset;
3047 /* We assume here that if we need a PARALLEL with
3048 CLOBBERs for this assignment, we can do with the
3049 MATCH_SCRATCHes that add_clobbers allocates.
3050 There's not much we can do if that doesn't work. */
3051 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3055 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3058 rtvec vec = rtvec_alloc (num_clobbers + 1);
3060 vec->elem[0] = PATTERN (insn);
3061 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3062 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3064 if (INSN_CODE (insn) < 0)
3067 /* If we have a nonzero offset, and the source is already
3068 a simple REG, the following transformation would
3069 increase the cost of the insn by replacing a simple REG
3070 with (plus (reg sp) CST). So try only when plus_src
3071 comes from old_set proper, not REG_NOTES. */
3072 else if (SET_SRC (old_set) == plus_src)
3074 new_body = old_body;
3077 new_body = copy_insn (old_body);
3078 if (REG_NOTES (insn))
3079 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3081 PATTERN (insn) = new_body;
3082 old_set = single_set (insn);
3084 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3085 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3091 /* This can't have an effect on elimination offsets, so skip right
3097 /* Determine the effects of this insn on elimination offsets. */
3098 elimination_effects (old_body, 0);
3100 /* Eliminate all eliminable registers occurring in operands that
3101 can be handled by reload. */
3102 extract_insn (insn);
3103 for (i = 0; i < recog_data.n_operands; i++)
3105 orig_operand[i] = recog_data.operand[i];
3106 substed_operand[i] = recog_data.operand[i];
3108 /* For an asm statement, every operand is eliminable. */
3109 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3111 /* Check for setting a register that we know about. */
3112 if (recog_data.operand_type[i] != OP_IN
3113 && GET_CODE (orig_operand[i]) == REG)
3115 /* If we are assigning to a register that can be eliminated, it
3116 must be as part of a PARALLEL, since the code above handles
3117 single SETs. We must indicate that we can no longer
3118 eliminate this reg. */
3119 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3121 if (ep->from_rtx == orig_operand[i])
3122 ep->can_eliminate = 0;
3125 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3126 replace ? insn : NULL_RTX);
3127 if (substed_operand[i] != orig_operand[i])
3129 /* Terminate the search in check_eliminable_occurrences at
3131 *recog_data.operand_loc[i] = 0;
3133 /* If an output operand changed from a REG to a MEM and INSN is an
3134 insn, write a CLOBBER insn. */
3135 if (recog_data.operand_type[i] != OP_IN
3136 && GET_CODE (orig_operand[i]) == REG
3137 && GET_CODE (substed_operand[i]) == MEM
3139 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3144 for (i = 0; i < recog_data.n_dups; i++)
3145 *recog_data.dup_loc[i]
3146 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3148 /* If any eliminable remain, they aren't eliminable anymore. */
3149 check_eliminable_occurrences (old_body);
3151 /* Substitute the operands; the new values are in the substed_operand
3153 for (i = 0; i < recog_data.n_operands; i++)
3154 *recog_data.operand_loc[i] = substed_operand[i];
3155 for (i = 0; i < recog_data.n_dups; i++)
3156 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3158 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3159 re-recognize the insn. We do this in case we had a simple addition
3160 but now can do this as a load-address. This saves an insn in this
3162 If re-recognition fails, the old insn code number will still be used,
3163 and some register operands may have changed into PLUS expressions.
3164 These will be handled by find_reloads by loading them into a register
3169 /* If we aren't replacing things permanently and we changed something,
3170 make another copy to ensure that all the RTL is new. Otherwise
3171 things can go wrong if find_reload swaps commutative operands
3172 and one is inside RTL that has been copied while the other is not. */
3173 new_body = old_body;
3176 new_body = copy_insn (old_body);
3177 if (REG_NOTES (insn))
3178 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3180 PATTERN (insn) = new_body;
3182 /* If we had a move insn but now we don't, rerecognize it. This will
3183 cause spurious re-recognition if the old move had a PARALLEL since
3184 the new one still will, but we can't call single_set without
3185 having put NEW_BODY into the insn and the re-recognition won't
3186 hurt in this rare case. */
3187 /* ??? Why this huge if statement - why don't we just rerecognize the
3191 && ((GET_CODE (SET_SRC (old_set)) == REG
3192 && (GET_CODE (new_body) != SET
3193 || GET_CODE (SET_SRC (new_body)) != REG))
3194 /* If this was a load from or store to memory, compare
3195 the MEM in recog_data.operand to the one in the insn.
3196 If they are not equal, then rerecognize the insn. */
3198 && ((GET_CODE (SET_SRC (old_set)) == MEM
3199 && SET_SRC (old_set) != recog_data.operand[1])
3200 || (GET_CODE (SET_DEST (old_set)) == MEM
3201 && SET_DEST (old_set) != recog_data.operand[0])))
3202 /* If this was an add insn before, rerecognize. */
3203 || GET_CODE (SET_SRC (old_set)) == PLUS))
3205 int new_icode = recog (PATTERN (insn), insn, 0);
3207 INSN_CODE (insn) = icode;
3211 /* Restore the old body. If there were any changes to it, we made a copy
3212 of it while the changes were still in place, so we'll correctly return
3213 a modified insn below. */
3216 /* Restore the old body. */
3217 for (i = 0; i < recog_data.n_operands; i++)
3218 *recog_data.operand_loc[i] = orig_operand[i];
3219 for (i = 0; i < recog_data.n_dups; i++)
3220 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3223 /* Update all elimination pairs to reflect the status after the current
3224 insn. The changes we make were determined by the earlier call to
3225 elimination_effects.
3227 We also detect cases where register elimination cannot be done,
3228 namely, if a register would be both changed and referenced outside a MEM
3229 in the resulting insn since such an insn is often undefined and, even if
3230 not, we cannot know what meaning will be given to it. Note that it is
3231 valid to have a register used in an address in an insn that changes it
3232 (presumably with a pre- or post-increment or decrement).
3234 If anything changes, return nonzero. */
3236 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3238 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3239 ep->can_eliminate = 0;
3241 ep->ref_outside_mem = 0;
3243 if (ep->previous_offset != ep->offset)
3248 /* If we changed something, perform elimination in REG_NOTES. This is
3249 needed even when REPLACE is zero because a REG_DEAD note might refer
3250 to a register that we eliminate and could cause a different number
3251 of spill registers to be needed in the final reload pass than in
3253 if (val && REG_NOTES (insn) != 0)
3254 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3259 /* Loop through all elimination pairs.
3260 Recalculate the number not at initial offset.
3262 Compute the maximum offset (minimum offset if the stack does not
3263 grow downward) for each elimination pair. */
3266 update_eliminable_offsets (void)
3268 struct elim_table *ep;
3270 num_not_at_initial_offset = 0;
3271 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3273 ep->previous_offset = ep->offset;
3274 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3275 num_not_at_initial_offset++;
3279 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3280 replacement we currently believe is valid, mark it as not eliminable if X
3281 modifies DEST in any way other than by adding a constant integer to it.
3283 If DEST is the frame pointer, we do nothing because we assume that
3284 all assignments to the hard frame pointer are nonlocal gotos and are being
3285 done at a time when they are valid and do not disturb anything else.
3286 Some machines want to eliminate a fake argument pointer with either the
3287 frame or stack pointer. Assignments to the hard frame pointer must not
3288 prevent this elimination.
3290 Called via note_stores from reload before starting its passes to scan
3291 the insns of the function. */
3294 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3298 /* A SUBREG of a hard register here is just changing its mode. We should
3299 not see a SUBREG of an eliminable hard register, but check just in
3301 if (GET_CODE (dest) == SUBREG)
3302 dest = SUBREG_REG (dest);
3304 if (dest == hard_frame_pointer_rtx)
3307 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3308 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3309 && (GET_CODE (x) != SET
3310 || GET_CODE (SET_SRC (x)) != PLUS
3311 || XEXP (SET_SRC (x), 0) != dest
3312 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3314 reg_eliminate[i].can_eliminate_previous
3315 = reg_eliminate[i].can_eliminate = 0;
3320 /* Verify that the initial elimination offsets did not change since the
3321 last call to set_initial_elim_offsets. This is used to catch cases
3322 where something illegal happened during reload_as_needed that could
3323 cause incorrect code to be generated if we did not check for it. */
3326 verify_initial_elim_offsets (void)
3330 #ifdef ELIMINABLE_REGS
3331 struct elim_table *ep;
3333 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3335 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3336 if (t != ep->initial_offset)
3340 INITIAL_FRAME_POINTER_OFFSET (t);
3341 if (t != reg_eliminate[0].initial_offset)
3346 /* Reset all offsets on eliminable registers to their initial values. */
3349 set_initial_elim_offsets (void)
3351 struct elim_table *ep = reg_eliminate;
3353 #ifdef ELIMINABLE_REGS
3354 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3356 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3357 ep->previous_offset = ep->offset = ep->initial_offset;
3360 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3361 ep->previous_offset = ep->offset = ep->initial_offset;
3364 num_not_at_initial_offset = 0;
3367 /* Initialize the known label offsets.
3368 Set a known offset for each forced label to be at the initial offset
3369 of each elimination. We do this because we assume that all
3370 computed jumps occur from a location where each elimination is
3371 at its initial offset.
3372 For all other labels, show that we don't know the offsets. */
3375 set_initial_label_offsets (void)
3378 memset (offsets_known_at, 0, num_labels);
3380 for (x = forced_labels; x; x = XEXP (x, 1))
3382 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3385 /* Set all elimination offsets to the known values for the code label given
3389 set_offsets_for_label (rtx insn)
3392 int label_nr = CODE_LABEL_NUMBER (insn);
3393 struct elim_table *ep;
3395 num_not_at_initial_offset = 0;
3396 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3398 ep->offset = ep->previous_offset
3399 = offsets_at[label_nr - first_label_num][i];
3400 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3401 num_not_at_initial_offset++;
3405 /* See if anything that happened changes which eliminations are valid.
3406 For example, on the SPARC, whether or not the frame pointer can
3407 be eliminated can depend on what registers have been used. We need
3408 not check some conditions again (such as flag_omit_frame_pointer)
3409 since they can't have changed. */
3412 update_eliminables (HARD_REG_SET *pset)
3414 int previous_frame_pointer_needed = frame_pointer_needed;
3415 struct elim_table *ep;
3417 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3418 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3419 #ifdef ELIMINABLE_REGS
3420 || ! CAN_ELIMINATE (ep->from, ep->to)
3423 ep->can_eliminate = 0;
3425 /* Look for the case where we have discovered that we can't replace
3426 register A with register B and that means that we will now be
3427 trying to replace register A with register C. This means we can
3428 no longer replace register C with register B and we need to disable
3429 such an elimination, if it exists. This occurs often with A == ap,
3430 B == sp, and C == fp. */
3432 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3434 struct elim_table *op;
3437 if (! ep->can_eliminate && ep->can_eliminate_previous)
3439 /* Find the current elimination for ep->from, if there is a
3441 for (op = reg_eliminate;
3442 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3443 if (op->from == ep->from && op->can_eliminate)
3449 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3451 for (op = reg_eliminate;
3452 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3453 if (op->from == new_to && op->to == ep->to)
3454 op->can_eliminate = 0;
3458 /* See if any registers that we thought we could eliminate the previous
3459 time are no longer eliminable. If so, something has changed and we
3460 must spill the register. Also, recompute the number of eliminable
3461 registers and see if the frame pointer is needed; it is if there is
3462 no elimination of the frame pointer that we can perform. */
3464 frame_pointer_needed = 1;
3465 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3467 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3468 && ep->to != HARD_FRAME_POINTER_REGNUM)
3469 frame_pointer_needed = 0;
3471 if (! ep->can_eliminate && ep->can_eliminate_previous)
3473 ep->can_eliminate_previous = 0;
3474 SET_HARD_REG_BIT (*pset, ep->from);
3479 /* If we didn't need a frame pointer last time, but we do now, spill
3480 the hard frame pointer. */
3481 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3482 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3485 /* Initialize the table of registers to eliminate. */
3488 init_elim_table (void)
3490 struct elim_table *ep;
3491 #ifdef ELIMINABLE_REGS
3492 const struct elim_table_1 *ep1;
3496 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3498 /* Does this function require a frame pointer? */
3500 frame_pointer_needed = (! flag_omit_frame_pointer
3501 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3502 and restore sp for alloca. So we can't eliminate
3503 the frame pointer in that case. At some point,
3504 we should improve this by emitting the
3505 sp-adjusting insns for this case. */
3506 || (current_function_calls_alloca
3507 && EXIT_IGNORE_STACK)
3508 || FRAME_POINTER_REQUIRED);
3512 #ifdef ELIMINABLE_REGS
3513 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3514 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3516 ep->from = ep1->from;
3518 ep->can_eliminate = ep->can_eliminate_previous
3519 = (CAN_ELIMINATE (ep->from, ep->to)
3520 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3523 reg_eliminate[0].from = reg_eliminate_1[0].from;
3524 reg_eliminate[0].to = reg_eliminate_1[0].to;
3525 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3526 = ! frame_pointer_needed;
3529 /* Count the number of eliminable registers and build the FROM and TO
3530 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3531 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3532 We depend on this. */
3533 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3535 num_eliminable += ep->can_eliminate;
3536 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3537 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3541 /* Kick all pseudos out of hard register REGNO.
3543 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3544 because we found we can't eliminate some register. In the case, no pseudos
3545 are allowed to be in the register, even if they are only in a block that
3546 doesn't require spill registers, unlike the case when we are spilling this
3547 hard reg to produce another spill register.
3549 Return nonzero if any pseudos needed to be kicked out. */
3552 spill_hard_reg (unsigned int regno, int cant_eliminate)
3558 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3559 regs_ever_live[regno] = 1;
3562 /* Spill every pseudo reg that was allocated to this reg
3563 or to something that overlaps this reg. */
3565 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3566 if (reg_renumber[i] >= 0
3567 && (unsigned int) reg_renumber[i] <= regno
3568 && ((unsigned int) reg_renumber[i]
3569 + hard_regno_nregs[(unsigned int) reg_renumber[i]]
3570 [PSEUDO_REGNO_MODE (i)]
3572 SET_REGNO_REG_SET (&spilled_pseudos, i);
3575 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3576 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3579 ior_hard_reg_set (HARD_REG_SET *set1, HARD_REG_SET *set2)
3581 IOR_HARD_REG_SET (*set1, *set2);
3584 /* After find_reload_regs has been run for all insn that need reloads,
3585 and/or spill_hard_regs was called, this function is used to actually
3586 spill pseudo registers and try to reallocate them. It also sets up the
3587 spill_regs array for use by choose_reload_regs. */
3590 finish_spills (int global)
3592 struct insn_chain *chain;
3593 int something_changed = 0;
3596 /* Build the spill_regs array for the function. */
3597 /* If there are some registers still to eliminate and one of the spill regs
3598 wasn't ever used before, additional stack space may have to be
3599 allocated to store this register. Thus, we may have changed the offset
3600 between the stack and frame pointers, so mark that something has changed.
3602 One might think that we need only set VAL to 1 if this is a call-used
3603 register. However, the set of registers that must be saved by the
3604 prologue is not identical to the call-used set. For example, the
3605 register used by the call insn for the return PC is a call-used register,
3606 but must be saved by the prologue. */
3609 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3610 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3612 spill_reg_order[i] = n_spills;
3613 spill_regs[n_spills++] = i;
3614 if (num_eliminable && ! regs_ever_live[i])
3615 something_changed = 1;
3616 regs_ever_live[i] = 1;
3619 spill_reg_order[i] = -1;
3621 EXECUTE_IF_SET_IN_REG_SET
3622 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3624 /* Record the current hard register the pseudo is allocated to in
3625 pseudo_previous_regs so we avoid reallocating it to the same
3626 hard reg in a later pass. */
3627 if (reg_renumber[i] < 0)
3630 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3631 /* Mark it as no longer having a hard register home. */
3632 reg_renumber[i] = -1;
3633 /* We will need to scan everything again. */
3634 something_changed = 1;
3637 /* Retry global register allocation if possible. */
3640 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3641 /* For every insn that needs reloads, set the registers used as spill
3642 regs in pseudo_forbidden_regs for every pseudo live across the
3644 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3646 EXECUTE_IF_SET_IN_REG_SET
3647 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3649 ior_hard_reg_set (pseudo_forbidden_regs + i,
3650 &chain->used_spill_regs);
3652 EXECUTE_IF_SET_IN_REG_SET
3653 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3655 ior_hard_reg_set (pseudo_forbidden_regs + i,
3656 &chain->used_spill_regs);
3660 /* Retry allocating the spilled pseudos. For each reg, merge the
3661 various reg sets that indicate which hard regs can't be used,
3662 and call retry_global_alloc.
3663 We change spill_pseudos here to only contain pseudos that did not
3664 get a new hard register. */
3665 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3666 if (reg_old_renumber[i] != reg_renumber[i])
3668 HARD_REG_SET forbidden;
3669 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3670 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3671 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3672 retry_global_alloc (i, forbidden);
3673 if (reg_renumber[i] >= 0)
3674 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3678 /* Fix up the register information in the insn chain.
3679 This involves deleting those of the spilled pseudos which did not get
3680 a new hard register home from the live_{before,after} sets. */
3681 for (chain = reload_insn_chain; chain; chain = chain->next)
3683 HARD_REG_SET used_by_pseudos;
3684 HARD_REG_SET used_by_pseudos2;
3686 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3687 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3689 /* Mark any unallocated hard regs as available for spills. That
3690 makes inheritance work somewhat better. */
3691 if (chain->need_reload)
3693 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3694 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3695 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3697 /* Save the old value for the sanity test below. */
3698 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3700 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3701 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3702 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3703 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3705 /* Make sure we only enlarge the set. */
3706 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3712 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3713 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3715 int regno = reg_renumber[i];
3716 if (reg_old_renumber[i] == regno)
3719 alter_reg (i, reg_old_renumber[i]);
3720 reg_old_renumber[i] = regno;
3724 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3726 fprintf (dump_file, " Register %d now in %d.\n\n",
3727 i, reg_renumber[i]);
3731 return something_changed;
3734 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3737 scan_paradoxical_subregs (rtx x)
3741 enum rtx_code code = GET_CODE (x);
3751 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3759 if (GET_CODE (SUBREG_REG (x)) == REG
3760 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3761 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3762 = GET_MODE_SIZE (GET_MODE (x));
3769 fmt = GET_RTX_FORMAT (code);
3770 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3773 scan_paradoxical_subregs (XEXP (x, i));
3774 else if (fmt[i] == 'E')
3777 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3778 scan_paradoxical_subregs (XVECEXP (x, i, j));
3783 /* Reload pseudo-registers into hard regs around each insn as needed.
3784 Additional register load insns are output before the insn that needs it
3785 and perhaps store insns after insns that modify the reloaded pseudo reg.
3787 reg_last_reload_reg and reg_reloaded_contents keep track of
3788 which registers are already available in reload registers.
3789 We update these for the reloads that we perform,
3790 as the insns are scanned. */
3793 reload_as_needed (int live_known)
3795 struct insn_chain *chain;
3796 #if defined (AUTO_INC_DEC)
3801 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3802 memset (spill_reg_store, 0, sizeof spill_reg_store);
3803 reg_last_reload_reg = xcalloc (max_regno, sizeof (rtx));
3804 reg_has_output_reload = xmalloc (max_regno);
3805 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3806 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
3808 set_initial_elim_offsets ();
3810 for (chain = reload_insn_chain; chain; chain = chain->next)
3813 rtx insn = chain->insn;
3814 rtx old_next = NEXT_INSN (insn);
3816 /* If we pass a label, copy the offsets from the label information
3817 into the current offsets of each elimination. */
3818 if (GET_CODE (insn) == CODE_LABEL)
3819 set_offsets_for_label (insn);
3821 else if (INSN_P (insn))
3823 rtx oldpat = copy_rtx (PATTERN (insn));
3825 /* If this is a USE and CLOBBER of a MEM, ensure that any
3826 references to eliminable registers have been removed. */
3828 if ((GET_CODE (PATTERN (insn)) == USE
3829 || GET_CODE (PATTERN (insn)) == CLOBBER)
3830 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3831 XEXP (XEXP (PATTERN (insn), 0), 0)
3832 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3833 GET_MODE (XEXP (PATTERN (insn), 0)),
3836 /* If we need to do register elimination processing, do so.
3837 This might delete the insn, in which case we are done. */
3838 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3840 eliminate_regs_in_insn (insn, 1);
3841 if (GET_CODE (insn) == NOTE)
3843 update_eliminable_offsets ();
3848 /* If need_elim is nonzero but need_reload is zero, one might think
3849 that we could simply set n_reloads to 0. However, find_reloads
3850 could have done some manipulation of the insn (such as swapping
3851 commutative operands), and these manipulations are lost during
3852 the first pass for every insn that needs register elimination.
3853 So the actions of find_reloads must be redone here. */
3855 if (! chain->need_elim && ! chain->need_reload
3856 && ! chain->need_operand_change)
3858 /* First find the pseudo regs that must be reloaded for this insn.
3859 This info is returned in the tables reload_... (see reload.h).
3860 Also modify the body of INSN by substituting RELOAD
3861 rtx's for those pseudo regs. */
3864 memset (reg_has_output_reload, 0, max_regno);
3865 CLEAR_HARD_REG_SET (reg_is_output_reload);
3867 find_reloads (insn, 1, spill_indirect_levels, live_known,
3873 rtx next = NEXT_INSN (insn);
3876 prev = PREV_INSN (insn);
3878 /* Now compute which reload regs to reload them into. Perhaps
3879 reusing reload regs from previous insns, or else output
3880 load insns to reload them. Maybe output store insns too.
3881 Record the choices of reload reg in reload_reg_rtx. */
3882 choose_reload_regs (chain);
3884 /* Merge any reloads that we didn't combine for fear of
3885 increasing the number of spill registers needed but now
3886 discover can be safely merged. */
3887 if (SMALL_REGISTER_CLASSES)
3888 merge_assigned_reloads (insn);
3890 /* Generate the insns to reload operands into or out of
3891 their reload regs. */
3892 emit_reload_insns (chain);
3894 /* Substitute the chosen reload regs from reload_reg_rtx
3895 into the insn's body (or perhaps into the bodies of other
3896 load and store insn that we just made for reloading
3897 and that we moved the structure into). */
3898 subst_reloads (insn);
3900 /* If this was an ASM, make sure that all the reload insns
3901 we have generated are valid. If not, give an error
3904 if (asm_noperands (PATTERN (insn)) >= 0)
3905 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3906 if (p != insn && INSN_P (p)
3907 && GET_CODE (PATTERN (p)) != USE
3908 && (recog_memoized (p) < 0
3909 || (extract_insn (p), ! constrain_operands (1))))
3911 error_for_asm (insn,
3912 "`asm' operand requires impossible reload");
3917 if (num_eliminable && chain->need_elim)
3918 update_eliminable_offsets ();
3920 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3921 is no longer validly lying around to save a future reload.
3922 Note that this does not detect pseudos that were reloaded
3923 for this insn in order to be stored in
3924 (obeying register constraints). That is correct; such reload
3925 registers ARE still valid. */
3926 note_stores (oldpat, forget_old_reloads_1, NULL);
3928 /* There may have been CLOBBER insns placed after INSN. So scan
3929 between INSN and NEXT and use them to forget old reloads. */
3930 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3931 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3932 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3935 /* Likewise for regs altered by auto-increment in this insn.
3936 REG_INC notes have been changed by reloading:
3937 find_reloads_address_1 records substitutions for them,
3938 which have been performed by subst_reloads above. */
3939 for (i = n_reloads - 1; i >= 0; i--)
3941 rtx in_reg = rld[i].in_reg;
3944 enum rtx_code code = GET_CODE (in_reg);
3945 /* PRE_INC / PRE_DEC will have the reload register ending up
3946 with the same value as the stack slot, but that doesn't
3947 hold true for POST_INC / POST_DEC. Either we have to
3948 convert the memory access to a true POST_INC / POST_DEC,
3949 or we can't use the reload register for inheritance. */
3950 if ((code == POST_INC || code == POST_DEC)
3951 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3952 REGNO (rld[i].reg_rtx))
3953 /* Make sure it is the inc/dec pseudo, and not
3954 some other (e.g. output operand) pseudo. */
3955 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3956 == REGNO (XEXP (in_reg, 0))))
3959 rtx reload_reg = rld[i].reg_rtx;
3960 enum machine_mode mode = GET_MODE (reload_reg);
3964 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3966 /* We really want to ignore REG_INC notes here, so
3967 use PATTERN (p) as argument to reg_set_p . */
3968 if (reg_set_p (reload_reg, PATTERN (p)))
3970 n = count_occurrences (PATTERN (p), reload_reg, 0);
3975 n = validate_replace_rtx (reload_reg,
3976 gen_rtx_fmt_e (code,
3981 /* We must also verify that the constraints
3982 are met after the replacement. */
3985 n = constrain_operands (1);
3989 /* If the constraints were not met, then
3990 undo the replacement. */
3993 validate_replace_rtx (gen_rtx_fmt_e (code,
4006 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4008 /* Mark this as having an output reload so that the
4009 REG_INC processing code below won't invalidate
4010 the reload for inheritance. */
4011 SET_HARD_REG_BIT (reg_is_output_reload,
4012 REGNO (reload_reg));
4013 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4016 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4019 else if ((code == PRE_INC || code == PRE_DEC)
4020 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4021 REGNO (rld[i].reg_rtx))
4022 /* Make sure it is the inc/dec pseudo, and not
4023 some other (e.g. output operand) pseudo. */
4024 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4025 == REGNO (XEXP (in_reg, 0))))
4027 SET_HARD_REG_BIT (reg_is_output_reload,
4028 REGNO (rld[i].reg_rtx));
4029 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4033 /* If a pseudo that got a hard register is auto-incremented,
4034 we must purge records of copying it into pseudos without
4036 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4037 if (REG_NOTE_KIND (x) == REG_INC)
4039 /* See if this pseudo reg was reloaded in this insn.
4040 If so, its last-reload info is still valid
4041 because it is based on this insn's reload. */
4042 for (i = 0; i < n_reloads; i++)
4043 if (rld[i].out == XEXP (x, 0))
4047 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4051 /* A reload reg's contents are unknown after a label. */
4052 if (GET_CODE (insn) == CODE_LABEL)
4053 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4055 /* Don't assume a reload reg is still good after a call insn
4056 if it is a call-used reg, or if it contains a value that will
4057 be partially clobbered by the call. */
4058 else if (GET_CODE (insn) == CALL_INSN)
4060 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4061 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4066 free (reg_last_reload_reg);
4067 free (reg_has_output_reload);
4070 /* Discard all record of any value reloaded from X,
4071 or reloaded in X from someplace else;
4072 unless X is an output reload reg of the current insn.
4074 X may be a hard reg (the reload reg)
4075 or it may be a pseudo reg that was reloaded from. */
4078 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4079 void *data ATTRIBUTE_UNUSED)
4084 /* note_stores does give us subregs of hard regs,
4085 subreg_regno_offset will abort if it is not a hard reg. */
4086 while (GET_CODE (x) == SUBREG)
4088 /* We ignore the subreg offset when calculating the regno,
4089 because we are using the entire underlying hard register
4094 if (GET_CODE (x) != REG)
4099 if (regno >= FIRST_PSEUDO_REGISTER)
4105 nr = hard_regno_nregs[regno][GET_MODE (x)];
4106 /* Storing into a spilled-reg invalidates its contents.
4107 This can happen if a block-local pseudo is allocated to that reg
4108 and it wasn't spilled because this block's total need is 0.
4109 Then some insn might have an optional reload and use this reg. */
4110 for (i = 0; i < nr; i++)
4111 /* But don't do this if the reg actually serves as an output
4112 reload reg in the current instruction. */
4114 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4116 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4117 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4118 spill_reg_store[regno + i] = 0;
4122 /* Since value of X has changed,
4123 forget any value previously copied from it. */
4126 /* But don't forget a copy if this is the output reload
4127 that establishes the copy's validity. */
4128 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4129 reg_last_reload_reg[regno + nr] = 0;
4132 /* The following HARD_REG_SETs indicate when each hard register is
4133 used for a reload of various parts of the current insn. */
4135 /* If reg is unavailable for all reloads. */
4136 static HARD_REG_SET reload_reg_unavailable;
4137 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4138 static HARD_REG_SET reload_reg_used;
4139 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4140 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4141 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4142 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4143 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4144 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4145 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4146 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4147 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4148 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4149 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4150 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4151 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4152 static HARD_REG_SET reload_reg_used_in_op_addr;
4153 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4154 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4155 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4156 static HARD_REG_SET reload_reg_used_in_insn;
4157 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4158 static HARD_REG_SET reload_reg_used_in_other_addr;
4160 /* If reg is in use as a reload reg for any sort of reload. */
4161 static HARD_REG_SET reload_reg_used_at_all;
4163 /* If reg is use as an inherited reload. We just mark the first register
4165 static HARD_REG_SET reload_reg_used_for_inherit;
4167 /* Records which hard regs are used in any way, either as explicit use or
4168 by being allocated to a pseudo during any point of the current insn. */
4169 static HARD_REG_SET reg_used_in_insn;
4171 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4172 TYPE. MODE is used to indicate how many consecutive regs are
4176 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4177 enum machine_mode mode)
4179 unsigned int nregs = hard_regno_nregs[regno][mode];
4182 for (i = regno; i < nregs + regno; i++)
4187 SET_HARD_REG_BIT (reload_reg_used, i);
4190 case RELOAD_FOR_INPUT_ADDRESS:
4191 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4194 case RELOAD_FOR_INPADDR_ADDRESS:
4195 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4198 case RELOAD_FOR_OUTPUT_ADDRESS:
4199 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4202 case RELOAD_FOR_OUTADDR_ADDRESS:
4203 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4206 case RELOAD_FOR_OPERAND_ADDRESS:
4207 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4210 case RELOAD_FOR_OPADDR_ADDR:
4211 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4214 case RELOAD_FOR_OTHER_ADDRESS:
4215 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4218 case RELOAD_FOR_INPUT:
4219 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4222 case RELOAD_FOR_OUTPUT:
4223 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4226 case RELOAD_FOR_INSN:
4227 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4231 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4235 /* Similarly, but show REGNO is no longer in use for a reload. */
4238 clear_reload_reg_in_use (unsigned int regno, int opnum,
4239 enum reload_type type, enum machine_mode mode)
4241 unsigned int nregs = hard_regno_nregs[regno][mode];
4242 unsigned int start_regno, end_regno, r;
4244 /* A complication is that for some reload types, inheritance might
4245 allow multiple reloads of the same types to share a reload register.
4246 We set check_opnum if we have to check only reloads with the same
4247 operand number, and check_any if we have to check all reloads. */
4248 int check_opnum = 0;
4250 HARD_REG_SET *used_in_set;
4255 used_in_set = &reload_reg_used;
4258 case RELOAD_FOR_INPUT_ADDRESS:
4259 used_in_set = &reload_reg_used_in_input_addr[opnum];
4262 case RELOAD_FOR_INPADDR_ADDRESS:
4264 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4267 case RELOAD_FOR_OUTPUT_ADDRESS:
4268 used_in_set = &reload_reg_used_in_output_addr[opnum];
4271 case RELOAD_FOR_OUTADDR_ADDRESS:
4273 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4276 case RELOAD_FOR_OPERAND_ADDRESS:
4277 used_in_set = &reload_reg_used_in_op_addr;
4280 case RELOAD_FOR_OPADDR_ADDR:
4282 used_in_set = &reload_reg_used_in_op_addr_reload;
4285 case RELOAD_FOR_OTHER_ADDRESS:
4286 used_in_set = &reload_reg_used_in_other_addr;
4290 case RELOAD_FOR_INPUT:
4291 used_in_set = &reload_reg_used_in_input[opnum];
4294 case RELOAD_FOR_OUTPUT:
4295 used_in_set = &reload_reg_used_in_output[opnum];
4298 case RELOAD_FOR_INSN:
4299 used_in_set = &reload_reg_used_in_insn;
4304 /* We resolve conflicts with remaining reloads of the same type by
4305 excluding the intervals of reload registers by them from the
4306 interval of freed reload registers. Since we only keep track of
4307 one set of interval bounds, we might have to exclude somewhat
4308 more than what would be necessary if we used a HARD_REG_SET here.
4309 But this should only happen very infrequently, so there should
4310 be no reason to worry about it. */
4312 start_regno = regno;
4313 end_regno = regno + nregs;
4314 if (check_opnum || check_any)
4316 for (i = n_reloads - 1; i >= 0; i--)
4318 if (rld[i].when_needed == type
4319 && (check_any || rld[i].opnum == opnum)
4322 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4323 unsigned int conflict_end
4325 + hard_regno_nregs[conflict_start][rld[i].mode]);
4327 /* If there is an overlap with the first to-be-freed register,
4328 adjust the interval start. */
4329 if (conflict_start <= start_regno && conflict_end > start_regno)
4330 start_regno = conflict_end;
4331 /* Otherwise, if there is a conflict with one of the other
4332 to-be-freed registers, adjust the interval end. */
4333 if (conflict_start > start_regno && conflict_start < end_regno)
4334 end_regno = conflict_start;
4339 for (r = start_regno; r < end_regno; r++)
4340 CLEAR_HARD_REG_BIT (*used_in_set, r);
4343 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4344 specified by OPNUM and TYPE. */
4347 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4351 /* In use for a RELOAD_OTHER means it's not available for anything. */
4352 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4353 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4359 /* In use for anything means we can't use it for RELOAD_OTHER. */
4360 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4361 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4362 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4363 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4366 for (i = 0; i < reload_n_operands; i++)
4367 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4368 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4369 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4370 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4371 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4372 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4377 case RELOAD_FOR_INPUT:
4378 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4379 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4382 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4385 /* If it is used for some other input, can't use it. */
4386 for (i = 0; i < reload_n_operands; i++)
4387 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4390 /* If it is used in a later operand's address, can't use it. */
4391 for (i = opnum + 1; i < reload_n_operands; i++)
4392 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4393 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4398 case RELOAD_FOR_INPUT_ADDRESS:
4399 /* Can't use a register if it is used for an input address for this
4400 operand or used as an input in an earlier one. */
4401 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4402 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4405 for (i = 0; i < opnum; i++)
4406 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4411 case RELOAD_FOR_INPADDR_ADDRESS:
4412 /* Can't use a register if it is used for an input address
4413 for this operand or used as an input in an earlier
4415 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4418 for (i = 0; i < opnum; i++)
4419 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4424 case RELOAD_FOR_OUTPUT_ADDRESS:
4425 /* Can't use a register if it is used for an output address for this
4426 operand or used as an output in this or a later operand. Note
4427 that multiple output operands are emitted in reverse order, so
4428 the conflicting ones are those with lower indices. */
4429 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4432 for (i = 0; i <= opnum; i++)
4433 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4438 case RELOAD_FOR_OUTADDR_ADDRESS:
4439 /* Can't use a register if it is used for an output address
4440 for this operand or used as an output in this or a
4441 later operand. Note that multiple output operands are
4442 emitted in reverse order, so the conflicting ones are
4443 those with lower indices. */
4444 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4447 for (i = 0; i <= opnum; i++)
4448 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4453 case RELOAD_FOR_OPERAND_ADDRESS:
4454 for (i = 0; i < reload_n_operands; i++)
4455 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4458 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4459 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4461 case RELOAD_FOR_OPADDR_ADDR:
4462 for (i = 0; i < reload_n_operands; i++)
4463 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4466 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4468 case RELOAD_FOR_OUTPUT:
4469 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4470 outputs, or an operand address for this or an earlier output.
4471 Note that multiple output operands are emitted in reverse order,
4472 so the conflicting ones are those with higher indices. */
4473 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4476 for (i = 0; i < reload_n_operands; i++)
4477 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4480 for (i = opnum; i < reload_n_operands; i++)
4481 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4482 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4487 case RELOAD_FOR_INSN:
4488 for (i = 0; i < reload_n_operands; i++)
4489 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4490 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4493 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4494 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4496 case RELOAD_FOR_OTHER_ADDRESS:
4497 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4502 /* Return 1 if the value in reload reg REGNO, as used by a reload
4503 needed for the part of the insn specified by OPNUM and TYPE,
4504 is still available in REGNO at the end of the insn.
4506 We can assume that the reload reg was already tested for availability
4507 at the time it is needed, and we should not check this again,
4508 in case the reg has already been marked in use. */
4511 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4518 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4519 its value must reach the end. */
4522 /* If this use is for part of the insn,
4523 its value reaches if no subsequent part uses the same register.
4524 Just like the above function, don't try to do this with lots
4527 case RELOAD_FOR_OTHER_ADDRESS:
4528 /* Here we check for everything else, since these don't conflict
4529 with anything else and everything comes later. */
4531 for (i = 0; i < reload_n_operands; i++)
4532 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4533 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4534 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4535 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4536 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4537 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4540 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4541 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4542 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4543 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4545 case RELOAD_FOR_INPUT_ADDRESS:
4546 case RELOAD_FOR_INPADDR_ADDRESS:
4547 /* Similar, except that we check only for this and subsequent inputs
4548 and the address of only subsequent inputs and we do not need
4549 to check for RELOAD_OTHER objects since they are known not to
4552 for (i = opnum; i < reload_n_operands; i++)
4553 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4556 for (i = opnum + 1; i < reload_n_operands; i++)
4557 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4558 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4561 for (i = 0; i < reload_n_operands; i++)
4562 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4563 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4564 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4567 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4570 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4571 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4572 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4574 case RELOAD_FOR_INPUT:
4575 /* Similar to input address, except we start at the next operand for
4576 both input and input address and we do not check for
4577 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4580 for (i = opnum + 1; i < reload_n_operands; i++)
4581 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4582 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4583 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4586 /* ... fall through ... */
4588 case RELOAD_FOR_OPERAND_ADDRESS:
4589 /* Check outputs and their addresses. */
4591 for (i = 0; i < reload_n_operands; i++)
4592 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4593 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4594 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4597 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4599 case RELOAD_FOR_OPADDR_ADDR:
4600 for (i = 0; i < reload_n_operands; i++)
4601 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4602 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4603 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4606 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4607 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4608 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4610 case RELOAD_FOR_INSN:
4611 /* These conflict with other outputs with RELOAD_OTHER. So
4612 we need only check for output addresses. */
4614 opnum = reload_n_operands;
4616 /* ... fall through ... */
4618 case RELOAD_FOR_OUTPUT:
4619 case RELOAD_FOR_OUTPUT_ADDRESS:
4620 case RELOAD_FOR_OUTADDR_ADDRESS:
4621 /* We already know these can't conflict with a later output. So the
4622 only thing to check are later output addresses.
4623 Note that multiple output operands are emitted in reverse order,
4624 so the conflicting ones are those with lower indices. */
4625 for (i = 0; i < opnum; i++)
4626 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4627 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4636 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4639 This function uses the same algorithm as reload_reg_free_p above. */
4642 reloads_conflict (int r1, int r2)
4644 enum reload_type r1_type = rld[r1].when_needed;
4645 enum reload_type r2_type = rld[r2].when_needed;
4646 int r1_opnum = rld[r1].opnum;
4647 int r2_opnum = rld[r2].opnum;
4649 /* RELOAD_OTHER conflicts with everything. */
4650 if (r2_type == RELOAD_OTHER)
4653 /* Otherwise, check conflicts differently for each type. */
4657 case RELOAD_FOR_INPUT:
4658 return (r2_type == RELOAD_FOR_INSN
4659 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4660 || r2_type == RELOAD_FOR_OPADDR_ADDR
4661 || r2_type == RELOAD_FOR_INPUT
4662 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4663 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4664 && r2_opnum > r1_opnum));
4666 case RELOAD_FOR_INPUT_ADDRESS:
4667 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4668 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4670 case RELOAD_FOR_INPADDR_ADDRESS:
4671 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4672 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4674 case RELOAD_FOR_OUTPUT_ADDRESS:
4675 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4676 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4678 case RELOAD_FOR_OUTADDR_ADDRESS:
4679 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4680 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4682 case RELOAD_FOR_OPERAND_ADDRESS:
4683 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4684 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4686 case RELOAD_FOR_OPADDR_ADDR:
4687 return (r2_type == RELOAD_FOR_INPUT
4688 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4690 case RELOAD_FOR_OUTPUT:
4691 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4692 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4693 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4694 && r2_opnum >= r1_opnum));
4696 case RELOAD_FOR_INSN:
4697 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4698 || r2_type == RELOAD_FOR_INSN
4699 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4701 case RELOAD_FOR_OTHER_ADDRESS:
4702 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4712 /* Indexed by reload number, 1 if incoming value
4713 inherited from previous insns. */
4714 char reload_inherited[MAX_RELOADS];
4716 /* For an inherited reload, this is the insn the reload was inherited from,
4717 if we know it. Otherwise, this is 0. */
4718 rtx reload_inheritance_insn[MAX_RELOADS];
4720 /* If nonzero, this is a place to get the value of the reload,
4721 rather than using reload_in. */
4722 rtx reload_override_in[MAX_RELOADS];
4724 /* For each reload, the hard register number of the register used,
4725 or -1 if we did not need a register for this reload. */
4726 int reload_spill_index[MAX_RELOADS];
4728 /* Subroutine of free_for_value_p, used to check a single register.
4729 START_REGNO is the starting regno of the full reload register
4730 (possibly comprising multiple hard registers) that we are considering. */
4733 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4734 enum reload_type type, rtx value, rtx out,
4735 int reloadnum, int ignore_address_reloads)
4738 /* Set if we see an input reload that must not share its reload register
4739 with any new earlyclobber, but might otherwise share the reload
4740 register with an output or input-output reload. */
4741 int check_earlyclobber = 0;
4745 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4748 if (out == const0_rtx)
4754 /* We use some pseudo 'time' value to check if the lifetimes of the
4755 new register use would overlap with the one of a previous reload
4756 that is not read-only or uses a different value.
4757 The 'time' used doesn't have to be linear in any shape or form, just
4759 Some reload types use different 'buckets' for each operand.
4760 So there are MAX_RECOG_OPERANDS different time values for each
4762 We compute TIME1 as the time when the register for the prospective
4763 new reload ceases to be live, and TIME2 for each existing
4764 reload as the time when that the reload register of that reload
4766 Where there is little to be gained by exact lifetime calculations,
4767 we just make conservative assumptions, i.e. a longer lifetime;
4768 this is done in the 'default:' cases. */
4771 case RELOAD_FOR_OTHER_ADDRESS:
4772 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4773 time1 = copy ? 0 : 1;
4776 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4778 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4779 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4780 respectively, to the time values for these, we get distinct time
4781 values. To get distinct time values for each operand, we have to
4782 multiply opnum by at least three. We round that up to four because
4783 multiply by four is often cheaper. */
4784 case RELOAD_FOR_INPADDR_ADDRESS:
4785 time1 = opnum * 4 + 2;
4787 case RELOAD_FOR_INPUT_ADDRESS:
4788 time1 = opnum * 4 + 3;
4790 case RELOAD_FOR_INPUT:
4791 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4792 executes (inclusive). */
4793 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4795 case RELOAD_FOR_OPADDR_ADDR:
4797 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4798 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4800 case RELOAD_FOR_OPERAND_ADDRESS:
4801 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4803 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4805 case RELOAD_FOR_OUTADDR_ADDRESS:
4806 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4808 case RELOAD_FOR_OUTPUT_ADDRESS:
4809 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4812 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4815 for (i = 0; i < n_reloads; i++)
4817 rtx reg = rld[i].reg_rtx;
4818 if (reg && GET_CODE (reg) == REG
4819 && ((unsigned) regno - true_regnum (reg)
4820 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
4823 rtx other_input = rld[i].in;
4825 /* If the other reload loads the same input value, that
4826 will not cause a conflict only if it's loading it into
4827 the same register. */
4828 if (true_regnum (reg) != start_regno)
4829 other_input = NULL_RTX;
4830 if (! other_input || ! rtx_equal_p (other_input, value)
4831 || rld[i].out || out)
4834 switch (rld[i].when_needed)
4836 case RELOAD_FOR_OTHER_ADDRESS:
4839 case RELOAD_FOR_INPADDR_ADDRESS:
4840 /* find_reloads makes sure that a
4841 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4842 by at most one - the first -
4843 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4844 address reload is inherited, the address address reload
4845 goes away, so we can ignore this conflict. */
4846 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4847 && ignore_address_reloads
4848 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4849 Then the address address is still needed to store
4850 back the new address. */
4851 && ! rld[reloadnum].out)
4853 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4854 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4856 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4857 && ignore_address_reloads
4858 /* Unless we are reloading an auto_inc expression. */
4859 && ! rld[reloadnum].out)
4861 time2 = rld[i].opnum * 4 + 2;
4863 case RELOAD_FOR_INPUT_ADDRESS:
4864 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4865 && ignore_address_reloads
4866 && ! rld[reloadnum].out)
4868 time2 = rld[i].opnum * 4 + 3;
4870 case RELOAD_FOR_INPUT:
4871 time2 = rld[i].opnum * 4 + 4;
4872 check_earlyclobber = 1;
4874 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4875 == MAX_RECOG_OPERAND * 4 */
4876 case RELOAD_FOR_OPADDR_ADDR:
4877 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4878 && ignore_address_reloads
4879 && ! rld[reloadnum].out)
4881 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4883 case RELOAD_FOR_OPERAND_ADDRESS:
4884 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4885 check_earlyclobber = 1;
4887 case RELOAD_FOR_INSN:
4888 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4890 case RELOAD_FOR_OUTPUT:
4891 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4892 instruction is executed. */
4893 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4895 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4896 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4898 case RELOAD_FOR_OUTADDR_ADDRESS:
4899 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4900 && ignore_address_reloads
4901 && ! rld[reloadnum].out)
4903 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4905 case RELOAD_FOR_OUTPUT_ADDRESS:
4906 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4909 /* If there is no conflict in the input part, handle this
4910 like an output reload. */
4911 if (! rld[i].in || rtx_equal_p (other_input, value))
4913 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4914 /* Earlyclobbered outputs must conflict with inputs. */
4915 if (earlyclobber_operand_p (rld[i].out))
4916 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4921 /* RELOAD_OTHER might be live beyond instruction execution,
4922 but this is not obvious when we set time2 = 1. So check
4923 here if there might be a problem with the new reload
4924 clobbering the register used by the RELOAD_OTHER. */
4932 && (! rld[i].in || rld[i].out
4933 || ! rtx_equal_p (other_input, value)))
4934 || (out && rld[reloadnum].out_reg
4935 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4941 /* Earlyclobbered outputs must conflict with inputs. */
4942 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4948 /* Return 1 if the value in reload reg REGNO, as used by a reload
4949 needed for the part of the insn specified by OPNUM and TYPE,
4950 may be used to load VALUE into it.
4952 MODE is the mode in which the register is used, this is needed to
4953 determine how many hard regs to test.
4955 Other read-only reloads with the same value do not conflict
4956 unless OUT is nonzero and these other reloads have to live while
4957 output reloads live.
4958 If OUT is CONST0_RTX, this is a special case: it means that the
4959 test should not be for using register REGNO as reload register, but
4960 for copying from register REGNO into the reload register.
4962 RELOADNUM is the number of the reload we want to load this value for;
4963 a reload does not conflict with itself.
4965 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4966 reloads that load an address for the very reload we are considering.
4968 The caller has to make sure that there is no conflict with the return
4972 free_for_value_p (int regno, enum machine_mode mode, int opnum,
4973 enum reload_type type, rtx value, rtx out, int reloadnum,
4974 int ignore_address_reloads)
4976 int nregs = hard_regno_nregs[regno][mode];
4978 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
4979 value, out, reloadnum,
4980 ignore_address_reloads))
4985 /* Return nonzero if the rtx X is invariant over the current function. */
4986 /* ??? Actually, the places where we use this expect exactly what
4987 * is tested here, and not everything that is function invariant. In
4988 * particular, the frame pointer and arg pointer are special cased;
4989 * pic_offset_table_rtx is not, and this will cause aborts when we
4990 * go to spill these things to memory. */
4993 function_invariant_p (rtx x)
4997 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4999 if (GET_CODE (x) == PLUS
5000 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5001 && CONSTANT_P (XEXP (x, 1)))
5006 /* Determine whether the reload reg X overlaps any rtx'es used for
5007 overriding inheritance. Return nonzero if so. */
5010 conflicts_with_override (rtx x)
5013 for (i = 0; i < n_reloads; i++)
5014 if (reload_override_in[i]
5015 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5020 /* Give an error message saying we failed to find a reload for INSN,
5021 and clear out reload R. */
5023 failed_reload (rtx insn, int r)
5025 if (asm_noperands (PATTERN (insn)) < 0)
5026 /* It's the compiler's fault. */
5027 fatal_insn ("could not find a spill register", insn);
5029 /* It's the user's fault; the operand's mode and constraint
5030 don't match. Disable this reload so we don't crash in final. */
5031 error_for_asm (insn,
5032 "`asm' operand constraint incompatible with operand size");
5036 rld[r].optional = 1;
5037 rld[r].secondary_p = 1;
5040 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5041 for reload R. If it's valid, get an rtx for it. Return nonzero if
5044 set_reload_reg (int i, int r)
5047 rtx reg = spill_reg_rtx[i];
5049 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5050 spill_reg_rtx[i] = reg
5051 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5053 regno = true_regnum (reg);
5055 /* Detect when the reload reg can't hold the reload mode.
5056 This used to be one `if', but Sequent compiler can't handle that. */
5057 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5059 enum machine_mode test_mode = VOIDmode;
5061 test_mode = GET_MODE (rld[r].in);
5062 /* If rld[r].in has VOIDmode, it means we will load it
5063 in whatever mode the reload reg has: to wit, rld[r].mode.
5064 We have already tested that for validity. */
5065 /* Aside from that, we need to test that the expressions
5066 to reload from or into have modes which are valid for this
5067 reload register. Otherwise the reload insns would be invalid. */
5068 if (! (rld[r].in != 0 && test_mode != VOIDmode
5069 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5070 if (! (rld[r].out != 0
5071 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5073 /* The reg is OK. */
5076 /* Mark as in use for this insn the reload regs we use
5078 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5079 rld[r].when_needed, rld[r].mode);
5081 rld[r].reg_rtx = reg;
5082 reload_spill_index[r] = spill_regs[i];
5089 /* Find a spill register to use as a reload register for reload R.
5090 LAST_RELOAD is nonzero if this is the last reload for the insn being
5093 Set rld[R].reg_rtx to the register allocated.
5095 We return 1 if successful, or 0 if we couldn't find a spill reg and
5096 we didn't change anything. */
5099 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5104 /* If we put this reload ahead, thinking it is a group,
5105 then insist on finding a group. Otherwise we can grab a
5106 reg that some other reload needs.
5107 (That can happen when we have a 68000 DATA_OR_FP_REG
5108 which is a group of data regs or one fp reg.)
5109 We need not be so restrictive if there are no more reloads
5112 ??? Really it would be nicer to have smarter handling
5113 for that kind of reg class, where a problem like this is normal.
5114 Perhaps those classes should be avoided for reloading
5115 by use of more alternatives. */
5117 int force_group = rld[r].nregs > 1 && ! last_reload;
5119 /* If we want a single register and haven't yet found one,
5120 take any reg in the right class and not in use.
5121 If we want a consecutive group, here is where we look for it.
5123 We use two passes so we can first look for reload regs to
5124 reuse, which are already in use for other reloads in this insn,
5125 and only then use additional registers.
5126 I think that maximizing reuse is needed to make sure we don't
5127 run out of reload regs. Suppose we have three reloads, and
5128 reloads A and B can share regs. These need two regs.
5129 Suppose A and B are given different regs.
5130 That leaves none for C. */
5131 for (pass = 0; pass < 2; pass++)
5133 /* I is the index in spill_regs.
5134 We advance it round-robin between insns to use all spill regs
5135 equally, so that inherited reloads have a chance
5136 of leapfrogging each other. */
5140 for (count = 0; count < n_spills; count++)
5142 int class = (int) rld[r].class;
5148 regnum = spill_regs[i];
5150 if ((reload_reg_free_p (regnum, rld[r].opnum,
5153 /* We check reload_reg_used to make sure we
5154 don't clobber the return register. */
5155 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5156 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5157 rld[r].when_needed, rld[r].in,
5159 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5160 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5161 /* Look first for regs to share, then for unshared. But
5162 don't share regs used for inherited reloads; they are
5163 the ones we want to preserve. */
5165 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5167 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5170 int nr = hard_regno_nregs[regnum][rld[r].mode];
5171 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5172 (on 68000) got us two FP regs. If NR is 1,
5173 we would reject both of them. */
5176 /* If we need only one reg, we have already won. */
5179 /* But reject a single reg if we demand a group. */
5184 /* Otherwise check that as many consecutive regs as we need
5185 are available here. */
5188 int regno = regnum + nr - 1;
5189 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5190 && spill_reg_order[regno] >= 0
5191 && reload_reg_free_p (regno, rld[r].opnum,
5192 rld[r].when_needed)))
5201 /* If we found something on pass 1, omit pass 2. */
5202 if (count < n_spills)
5206 /* We should have found a spill register by now. */
5207 if (count >= n_spills)
5210 /* I is the index in SPILL_REG_RTX of the reload register we are to
5211 allocate. Get an rtx for it and find its register number. */
5213 return set_reload_reg (i, r);
5216 /* Initialize all the tables needed to allocate reload registers.
5217 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5218 is the array we use to restore the reg_rtx field for every reload. */
5221 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5225 for (i = 0; i < n_reloads; i++)
5226 rld[i].reg_rtx = save_reload_reg_rtx[i];
5228 memset (reload_inherited, 0, MAX_RELOADS);
5229 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5230 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5232 CLEAR_HARD_REG_SET (reload_reg_used);
5233 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5234 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5235 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5236 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5237 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5239 CLEAR_HARD_REG_SET (reg_used_in_insn);
5242 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5243 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5244 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5245 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5246 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5247 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5250 for (i = 0; i < reload_n_operands; i++)
5252 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5253 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5254 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5255 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5256 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5257 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5260 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5262 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5264 for (i = 0; i < n_reloads; i++)
5265 /* If we have already decided to use a certain register,
5266 don't use it in another way. */
5268 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5269 rld[i].when_needed, rld[i].mode);
5272 /* Assign hard reg targets for the pseudo-registers we must reload
5273 into hard regs for this insn.
5274 Also output the instructions to copy them in and out of the hard regs.
5276 For machines with register classes, we are responsible for
5277 finding a reload reg in the proper class. */
5280 choose_reload_regs (struct insn_chain *chain)
5282 rtx insn = chain->insn;
5284 unsigned int max_group_size = 1;
5285 enum reg_class group_class = NO_REGS;
5286 int pass, win, inheritance;
5288 rtx save_reload_reg_rtx[MAX_RELOADS];
5290 /* In order to be certain of getting the registers we need,
5291 we must sort the reloads into order of increasing register class.
5292 Then our grabbing of reload registers will parallel the process
5293 that provided the reload registers.
5295 Also note whether any of the reloads wants a consecutive group of regs.
5296 If so, record the maximum size of the group desired and what
5297 register class contains all the groups needed by this insn. */
5299 for (j = 0; j < n_reloads; j++)
5301 reload_order[j] = j;
5302 reload_spill_index[j] = -1;
5304 if (rld[j].nregs > 1)
5306 max_group_size = MAX (rld[j].nregs, max_group_size);
5308 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5311 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5315 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5317 /* If -O, try first with inheritance, then turning it off.
5318 If not -O, don't do inheritance.
5319 Using inheritance when not optimizing leads to paradoxes
5320 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5321 because one side of the comparison might be inherited. */
5323 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5325 choose_reload_regs_init (chain, save_reload_reg_rtx);
5327 /* Process the reloads in order of preference just found.
5328 Beyond this point, subregs can be found in reload_reg_rtx.
5330 This used to look for an existing reloaded home for all of the
5331 reloads, and only then perform any new reloads. But that could lose
5332 if the reloads were done out of reg-class order because a later
5333 reload with a looser constraint might have an old home in a register
5334 needed by an earlier reload with a tighter constraint.
5336 To solve this, we make two passes over the reloads, in the order
5337 described above. In the first pass we try to inherit a reload
5338 from a previous insn. If there is a later reload that needs a
5339 class that is a proper subset of the class being processed, we must
5340 also allocate a spill register during the first pass.
5342 Then make a second pass over the reloads to allocate any reloads
5343 that haven't been given registers yet. */
5345 for (j = 0; j < n_reloads; j++)
5347 int r = reload_order[j];
5348 rtx search_equiv = NULL_RTX;
5350 /* Ignore reloads that got marked inoperative. */
5351 if (rld[r].out == 0 && rld[r].in == 0
5352 && ! rld[r].secondary_p)
5355 /* If find_reloads chose to use reload_in or reload_out as a reload
5356 register, we don't need to chose one. Otherwise, try even if it
5357 found one since we might save an insn if we find the value lying
5359 Try also when reload_in is a pseudo without a hard reg. */
5360 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5361 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5362 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5363 && GET_CODE (rld[r].in) != MEM
5364 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5367 #if 0 /* No longer needed for correct operation.
5368 It might give better code, or might not; worth an experiment? */
5369 /* If this is an optional reload, we can't inherit from earlier insns
5370 until we are sure that any non-optional reloads have been allocated.
5371 The following code takes advantage of the fact that optional reloads
5372 are at the end of reload_order. */
5373 if (rld[r].optional != 0)
5374 for (i = 0; i < j; i++)
5375 if ((rld[reload_order[i]].out != 0
5376 || rld[reload_order[i]].in != 0
5377 || rld[reload_order[i]].secondary_p)
5378 && ! rld[reload_order[i]].optional
5379 && rld[reload_order[i]].reg_rtx == 0)
5380 allocate_reload_reg (chain, reload_order[i], 0);
5383 /* First see if this pseudo is already available as reloaded
5384 for a previous insn. We cannot try to inherit for reloads
5385 that are smaller than the maximum number of registers needed
5386 for groups unless the register we would allocate cannot be used
5389 We could check here to see if this is a secondary reload for
5390 an object that is already in a register of the desired class.
5391 This would avoid the need for the secondary reload register.
5392 But this is complex because we can't easily determine what
5393 objects might want to be loaded via this reload. So let a
5394 register be allocated here. In `emit_reload_insns' we suppress
5395 one of the loads in the case described above. */
5401 enum machine_mode mode = VOIDmode;
5405 else if (GET_CODE (rld[r].in) == REG)
5407 regno = REGNO (rld[r].in);
5408 mode = GET_MODE (rld[r].in);
5410 else if (GET_CODE (rld[r].in_reg) == REG)
5412 regno = REGNO (rld[r].in_reg);
5413 mode = GET_MODE (rld[r].in_reg);
5415 else if (GET_CODE (rld[r].in_reg) == SUBREG
5416 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5418 byte = SUBREG_BYTE (rld[r].in_reg);
5419 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5420 if (regno < FIRST_PSEUDO_REGISTER)
5421 regno = subreg_regno (rld[r].in_reg);
5422 mode = GET_MODE (rld[r].in_reg);
5425 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5426 || GET_CODE (rld[r].in_reg) == PRE_DEC
5427 || GET_CODE (rld[r].in_reg) == POST_INC
5428 || GET_CODE (rld[r].in_reg) == POST_DEC)
5429 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5431 regno = REGNO (XEXP (rld[r].in_reg, 0));
5432 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5433 rld[r].out = rld[r].in;
5437 /* This won't work, since REGNO can be a pseudo reg number.
5438 Also, it takes much more hair to keep track of all the things
5439 that can invalidate an inherited reload of part of a pseudoreg. */
5440 else if (GET_CODE (rld[r].in) == SUBREG
5441 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5442 regno = subreg_regno (rld[r].in);
5445 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5447 enum reg_class class = rld[r].class, last_class;
5448 rtx last_reg = reg_last_reload_reg[regno];
5449 enum machine_mode need_mode;
5451 i = REGNO (last_reg);
5452 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5453 last_class = REGNO_REG_CLASS (i);
5459 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5460 GET_MODE_CLASS (mode));
5463 #ifdef CANNOT_CHANGE_MODE_CLASS
5464 (!REG_CANNOT_CHANGE_MODE_P (i, GET_MODE (last_reg),
5468 (GET_MODE_SIZE (GET_MODE (last_reg))
5469 >= GET_MODE_SIZE (need_mode))
5470 #ifdef CANNOT_CHANGE_MODE_CLASS
5473 && reg_reloaded_contents[i] == regno
5474 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5475 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5476 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5477 /* Even if we can't use this register as a reload
5478 register, we might use it for reload_override_in,
5479 if copying it to the desired class is cheap
5481 || ((REGISTER_MOVE_COST (mode, last_class, class)
5482 < MEMORY_MOVE_COST (mode, class, 1))
5483 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5484 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5488 #ifdef SECONDARY_MEMORY_NEEDED
5489 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5494 && (rld[r].nregs == max_group_size
5495 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5497 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5498 rld[r].when_needed, rld[r].in,
5501 /* If a group is needed, verify that all the subsequent
5502 registers still have their values intact. */
5503 int nr = hard_regno_nregs[i][rld[r].mode];
5506 for (k = 1; k < nr; k++)
5507 if (reg_reloaded_contents[i + k] != regno
5508 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5516 last_reg = (GET_MODE (last_reg) == mode
5517 ? last_reg : gen_rtx_REG (mode, i));
5520 for (k = 0; k < nr; k++)
5521 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5524 /* We found a register that contains the
5525 value we need. If this register is the
5526 same as an `earlyclobber' operand of the
5527 current insn, just mark it as a place to
5528 reload from since we can't use it as the
5529 reload register itself. */
5531 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5532 if (reg_overlap_mentioned_for_reload_p
5533 (reg_last_reload_reg[regno],
5534 reload_earlyclobbers[i1]))
5537 if (i1 != n_earlyclobbers
5538 || ! (free_for_value_p (i, rld[r].mode,
5540 rld[r].when_needed, rld[r].in,
5542 /* Don't use it if we'd clobber a pseudo reg. */
5543 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5545 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5546 /* Don't clobber the frame pointer. */
5547 || (i == HARD_FRAME_POINTER_REGNUM
5548 && frame_pointer_needed
5550 /* Don't really use the inherited spill reg
5551 if we need it wider than we've got it. */
5552 || (GET_MODE_SIZE (rld[r].mode)
5553 > GET_MODE_SIZE (mode))
5556 /* If find_reloads chose reload_out as reload
5557 register, stay with it - that leaves the
5558 inherited register for subsequent reloads. */
5559 || (rld[r].out && rld[r].reg_rtx
5560 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5562 if (! rld[r].optional)
5564 reload_override_in[r] = last_reg;
5565 reload_inheritance_insn[r]
5566 = reg_reloaded_insn[i];
5572 /* We can use this as a reload reg. */
5573 /* Mark the register as in use for this part of
5575 mark_reload_reg_in_use (i,
5579 rld[r].reg_rtx = last_reg;
5580 reload_inherited[r] = 1;
5581 reload_inheritance_insn[r]
5582 = reg_reloaded_insn[i];
5583 reload_spill_index[r] = i;
5584 for (k = 0; k < nr; k++)
5585 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5593 /* Here's another way to see if the value is already lying around. */
5596 && ! reload_inherited[r]
5598 && (CONSTANT_P (rld[r].in)
5599 || GET_CODE (rld[r].in) == PLUS
5600 || GET_CODE (rld[r].in) == REG
5601 || GET_CODE (rld[r].in) == MEM)
5602 && (rld[r].nregs == max_group_size
5603 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5604 search_equiv = rld[r].in;
5605 /* If this is an output reload from a simple move insn, look
5606 if an equivalence for the input is available. */
5607 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5609 rtx set = single_set (insn);
5612 && rtx_equal_p (rld[r].out, SET_DEST (set))
5613 && CONSTANT_P (SET_SRC (set)))
5614 search_equiv = SET_SRC (set);
5620 = find_equiv_reg (search_equiv, insn, rld[r].class,
5621 -1, NULL, 0, rld[r].mode);
5626 if (GET_CODE (equiv) == REG)
5627 regno = REGNO (equiv);
5628 else if (GET_CODE (equiv) == SUBREG)
5630 /* This must be a SUBREG of a hard register.
5631 Make a new REG since this might be used in an
5632 address and not all machines support SUBREGs
5634 regno = subreg_regno (equiv);
5635 equiv = gen_rtx_REG (rld[r].mode, regno);
5641 /* If we found a spill reg, reject it unless it is free
5642 and of the desired class. */
5646 int bad_for_class = 0;
5647 int max_regno = regno + rld[r].nregs;
5649 for (i = regno; i < max_regno; i++)
5651 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5653 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5658 && ! free_for_value_p (regno, rld[r].mode,
5659 rld[r].opnum, rld[r].when_needed,
5660 rld[r].in, rld[r].out, r, 1))
5665 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5668 /* We found a register that contains the value we need.
5669 If this register is the same as an `earlyclobber' operand
5670 of the current insn, just mark it as a place to reload from
5671 since we can't use it as the reload register itself. */
5674 for (i = 0; i < n_earlyclobbers; i++)
5675 if (reg_overlap_mentioned_for_reload_p (equiv,
5676 reload_earlyclobbers[i]))
5678 if (! rld[r].optional)
5679 reload_override_in[r] = equiv;
5684 /* If the equiv register we have found is explicitly clobbered
5685 in the current insn, it depends on the reload type if we
5686 can use it, use it for reload_override_in, or not at all.
5687 In particular, we then can't use EQUIV for a
5688 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5692 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5693 switch (rld[r].when_needed)
5695 case RELOAD_FOR_OTHER_ADDRESS:
5696 case RELOAD_FOR_INPADDR_ADDRESS:
5697 case RELOAD_FOR_INPUT_ADDRESS:
5698 case RELOAD_FOR_OPADDR_ADDR:
5701 case RELOAD_FOR_INPUT:
5702 case RELOAD_FOR_OPERAND_ADDRESS:
5703 if (! rld[r].optional)
5704 reload_override_in[r] = equiv;
5710 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5711 switch (rld[r].when_needed)
5713 case RELOAD_FOR_OTHER_ADDRESS:
5714 case RELOAD_FOR_INPADDR_ADDRESS:
5715 case RELOAD_FOR_INPUT_ADDRESS:
5716 case RELOAD_FOR_OPADDR_ADDR:
5717 case RELOAD_FOR_OPERAND_ADDRESS:
5718 case RELOAD_FOR_INPUT:
5721 if (! rld[r].optional)
5722 reload_override_in[r] = equiv;
5730 /* If we found an equivalent reg, say no code need be generated
5731 to load it, and use it as our reload reg. */
5733 && (regno != HARD_FRAME_POINTER_REGNUM
5734 || !frame_pointer_needed))
5736 int nr = hard_regno_nregs[regno][rld[r].mode];
5738 rld[r].reg_rtx = equiv;
5739 reload_inherited[r] = 1;
5741 /* If reg_reloaded_valid is not set for this register,
5742 there might be a stale spill_reg_store lying around.
5743 We must clear it, since otherwise emit_reload_insns
5744 might delete the store. */
5745 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5746 spill_reg_store[regno] = NULL_RTX;
5747 /* If any of the hard registers in EQUIV are spill
5748 registers, mark them as in use for this insn. */
5749 for (k = 0; k < nr; k++)
5751 i = spill_reg_order[regno + k];
5754 mark_reload_reg_in_use (regno, rld[r].opnum,
5757 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5764 /* If we found a register to use already, or if this is an optional
5765 reload, we are done. */
5766 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5770 /* No longer needed for correct operation. Might or might
5771 not give better code on the average. Want to experiment? */
5773 /* See if there is a later reload that has a class different from our
5774 class that intersects our class or that requires less register
5775 than our reload. If so, we must allocate a register to this
5776 reload now, since that reload might inherit a previous reload
5777 and take the only available register in our class. Don't do this
5778 for optional reloads since they will force all previous reloads
5779 to be allocated. Also don't do this for reloads that have been
5782 for (i = j + 1; i < n_reloads; i++)
5784 int s = reload_order[i];
5786 if ((rld[s].in == 0 && rld[s].out == 0
5787 && ! rld[s].secondary_p)
5791 if ((rld[s].class != rld[r].class
5792 && reg_classes_intersect_p (rld[r].class,
5794 || rld[s].nregs < rld[r].nregs)
5801 allocate_reload_reg (chain, r, j == n_reloads - 1);
5805 /* Now allocate reload registers for anything non-optional that
5806 didn't get one yet. */
5807 for (j = 0; j < n_reloads; j++)
5809 int r = reload_order[j];
5811 /* Ignore reloads that got marked inoperative. */
5812 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5815 /* Skip reloads that already have a register allocated or are
5817 if (rld[r].reg_rtx != 0 || rld[r].optional)
5820 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5824 /* If that loop got all the way, we have won. */
5831 /* Loop around and try without any inheritance. */
5836 /* First undo everything done by the failed attempt
5837 to allocate with inheritance. */
5838 choose_reload_regs_init (chain, save_reload_reg_rtx);
5840 /* Some sanity tests to verify that the reloads found in the first
5841 pass are identical to the ones we have now. */
5842 if (chain->n_reloads != n_reloads)
5845 for (i = 0; i < n_reloads; i++)
5847 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5849 if (chain->rld[i].when_needed != rld[i].when_needed)
5851 for (j = 0; j < n_spills; j++)
5852 if (spill_regs[j] == chain->rld[i].regno)
5853 if (! set_reload_reg (j, i))
5854 failed_reload (chain->insn, i);
5858 /* If we thought we could inherit a reload, because it seemed that
5859 nothing else wanted the same reload register earlier in the insn,
5860 verify that assumption, now that all reloads have been assigned.
5861 Likewise for reloads where reload_override_in has been set. */
5863 /* If doing expensive optimizations, do one preliminary pass that doesn't
5864 cancel any inheritance, but removes reloads that have been needed only
5865 for reloads that we know can be inherited. */
5866 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5868 for (j = 0; j < n_reloads; j++)
5870 int r = reload_order[j];
5872 if (reload_inherited[r] && rld[r].reg_rtx)
5873 check_reg = rld[r].reg_rtx;
5874 else if (reload_override_in[r]
5875 && (GET_CODE (reload_override_in[r]) == REG
5876 || GET_CODE (reload_override_in[r]) == SUBREG))
5877 check_reg = reload_override_in[r];
5880 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5881 rld[r].opnum, rld[r].when_needed, rld[r].in,
5882 (reload_inherited[r]
5883 ? rld[r].out : const0_rtx),
5888 reload_inherited[r] = 0;
5889 reload_override_in[r] = 0;
5891 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5892 reload_override_in, then we do not need its related
5893 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5894 likewise for other reload types.
5895 We handle this by removing a reload when its only replacement
5896 is mentioned in reload_in of the reload we are going to inherit.
5897 A special case are auto_inc expressions; even if the input is
5898 inherited, we still need the address for the output. We can
5899 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5900 If we succeeded removing some reload and we are doing a preliminary
5901 pass just to remove such reloads, make another pass, since the
5902 removal of one reload might allow us to inherit another one. */
5904 && rld[r].out != rld[r].in
5905 && remove_address_replacements (rld[r].in) && pass)
5910 /* Now that reload_override_in is known valid,
5911 actually override reload_in. */
5912 for (j = 0; j < n_reloads; j++)
5913 if (reload_override_in[j])
5914 rld[j].in = reload_override_in[j];
5916 /* If this reload won't be done because it has been canceled or is
5917 optional and not inherited, clear reload_reg_rtx so other
5918 routines (such as subst_reloads) don't get confused. */
5919 for (j = 0; j < n_reloads; j++)
5920 if (rld[j].reg_rtx != 0
5921 && ((rld[j].optional && ! reload_inherited[j])
5922 || (rld[j].in == 0 && rld[j].out == 0
5923 && ! rld[j].secondary_p)))
5925 int regno = true_regnum (rld[j].reg_rtx);
5927 if (spill_reg_order[regno] >= 0)
5928 clear_reload_reg_in_use (regno, rld[j].opnum,
5929 rld[j].when_needed, rld[j].mode);
5931 reload_spill_index[j] = -1;
5934 /* Record which pseudos and which spill regs have output reloads. */
5935 for (j = 0; j < n_reloads; j++)
5937 int r = reload_order[j];
5939 i = reload_spill_index[r];
5941 /* I is nonneg if this reload uses a register.
5942 If rld[r].reg_rtx is 0, this is an optional reload
5943 that we opted to ignore. */
5944 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5945 && rld[r].reg_rtx != 0)
5947 int nregno = REGNO (rld[r].out_reg);
5950 if (nregno < FIRST_PSEUDO_REGISTER)
5951 nr = hard_regno_nregs[nregno][rld[r].mode];
5954 reg_has_output_reload[nregno + nr] = 1;
5958 nr = hard_regno_nregs[i][rld[r].mode];
5960 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5963 if (rld[r].when_needed != RELOAD_OTHER
5964 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5965 && rld[r].when_needed != RELOAD_FOR_INSN)
5971 /* Deallocate the reload register for reload R. This is called from
5972 remove_address_replacements. */
5975 deallocate_reload_reg (int r)
5979 if (! rld[r].reg_rtx)
5981 regno = true_regnum (rld[r].reg_rtx);
5983 if (spill_reg_order[regno] >= 0)
5984 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5986 reload_spill_index[r] = -1;
5989 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
5990 reloads of the same item for fear that we might not have enough reload
5991 registers. However, normally they will get the same reload register
5992 and hence actually need not be loaded twice.
5994 Here we check for the most common case of this phenomenon: when we have
5995 a number of reloads for the same object, each of which were allocated
5996 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5997 reload, and is not modified in the insn itself. If we find such,
5998 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5999 This will not increase the number of spill registers needed and will
6000 prevent redundant code. */
6003 merge_assigned_reloads (rtx insn)
6007 /* Scan all the reloads looking for ones that only load values and
6008 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6009 assigned and not modified by INSN. */
6011 for (i = 0; i < n_reloads; i++)
6013 int conflicting_input = 0;
6014 int max_input_address_opnum = -1;
6015 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6017 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6018 || rld[i].out != 0 || rld[i].reg_rtx == 0
6019 || reg_set_p (rld[i].reg_rtx, insn))
6022 /* Look at all other reloads. Ensure that the only use of this
6023 reload_reg_rtx is in a reload that just loads the same value
6024 as we do. Note that any secondary reloads must be of the identical
6025 class since the values, modes, and result registers are the
6026 same, so we need not do anything with any secondary reloads. */
6028 for (j = 0; j < n_reloads; j++)
6030 if (i == j || rld[j].reg_rtx == 0
6031 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6035 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6036 && rld[j].opnum > max_input_address_opnum)
6037 max_input_address_opnum = rld[j].opnum;
6039 /* If the reload regs aren't exactly the same (e.g, different modes)
6040 or if the values are different, we can't merge this reload.
6041 But if it is an input reload, we might still merge
6042 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6044 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6045 || rld[j].out != 0 || rld[j].in == 0
6046 || ! rtx_equal_p (rld[i].in, rld[j].in))
6048 if (rld[j].when_needed != RELOAD_FOR_INPUT
6049 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6050 || rld[i].opnum > rld[j].opnum)
6051 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6053 conflicting_input = 1;
6054 if (min_conflicting_input_opnum > rld[j].opnum)
6055 min_conflicting_input_opnum = rld[j].opnum;
6059 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6060 we, in fact, found any matching reloads. */
6063 && max_input_address_opnum <= min_conflicting_input_opnum)
6065 for (j = 0; j < n_reloads; j++)
6066 if (i != j && rld[j].reg_rtx != 0
6067 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6068 && (! conflicting_input
6069 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6070 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6072 rld[i].when_needed = RELOAD_OTHER;
6074 reload_spill_index[j] = -1;
6075 transfer_replacements (i, j);
6078 /* If this is now RELOAD_OTHER, look for any reloads that load
6079 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6080 if they were for inputs, RELOAD_OTHER for outputs. Note that
6081 this test is equivalent to looking for reloads for this operand
6083 /* We must take special care when there are two or more reloads to
6084 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6085 same value or a part of it; we must not change its type if there
6086 is a conflicting input. */
6088 if (rld[i].when_needed == RELOAD_OTHER)
6089 for (j = 0; j < n_reloads; j++)
6091 && rld[j].when_needed != RELOAD_OTHER
6092 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6093 && (! conflicting_input
6094 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6095 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6096 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6102 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6103 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6104 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6106 /* Check to see if we accidentally converted two reloads
6107 that use the same reload register with different inputs
6108 to the same type. If so, the resulting code won't work,
6111 for (k = 0; k < j; k++)
6112 if (rld[k].in != 0 && rld[k].reg_rtx != 0
6113 && rld[k].when_needed == rld[j].when_needed
6114 && rtx_equal_p (rld[k].reg_rtx, rld[j].reg_rtx)
6115 && ! rtx_equal_p (rld[k].in, rld[j].in))
6122 /* These arrays are filled by emit_reload_insns and its subroutines. */
6123 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6124 static rtx other_input_address_reload_insns = 0;
6125 static rtx other_input_reload_insns = 0;
6126 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6127 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6128 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6129 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6130 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6131 static rtx operand_reload_insns = 0;
6132 static rtx other_operand_reload_insns = 0;
6133 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6135 /* Values to be put in spill_reg_store are put here first. */
6136 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6137 static HARD_REG_SET reg_reloaded_died;
6139 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6140 has the number J. OLD contains the value to be used as input. */
6143 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6146 rtx insn = chain->insn;
6147 rtx reloadreg = rl->reg_rtx;
6148 rtx oldequiv_reg = 0;
6151 enum machine_mode mode;
6154 /* Determine the mode to reload in.
6155 This is very tricky because we have three to choose from.
6156 There is the mode the insn operand wants (rl->inmode).
6157 There is the mode of the reload register RELOADREG.
6158 There is the intrinsic mode of the operand, which we could find
6159 by stripping some SUBREGs.
6160 It turns out that RELOADREG's mode is irrelevant:
6161 we can change that arbitrarily.
6163 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6164 then the reload reg may not support QImode moves, so use SImode.
6165 If foo is in memory due to spilling a pseudo reg, this is safe,
6166 because the QImode value is in the least significant part of a
6167 slot big enough for a SImode. If foo is some other sort of
6168 memory reference, then it is impossible to reload this case,
6169 so previous passes had better make sure this never happens.
6171 Then consider a one-word union which has SImode and one of its
6172 members is a float, being fetched as (SUBREG:SF union:SI).
6173 We must fetch that as SFmode because we could be loading into
6174 a float-only register. In this case OLD's mode is correct.
6176 Consider an immediate integer: it has VOIDmode. Here we need
6177 to get a mode from something else.
6179 In some cases, there is a fourth mode, the operand's
6180 containing mode. If the insn specifies a containing mode for
6181 this operand, it overrides all others.
6183 I am not sure whether the algorithm here is always right,
6184 but it does the right things in those cases. */
6186 mode = GET_MODE (old);
6187 if (mode == VOIDmode)
6190 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6191 /* If we need a secondary register for this operation, see if
6192 the value is already in a register in that class. Don't
6193 do this if the secondary register will be used as a scratch
6196 if (rl->secondary_in_reload >= 0
6197 && rl->secondary_in_icode == CODE_FOR_nothing
6200 = find_equiv_reg (old, insn,
6201 rld[rl->secondary_in_reload].class,
6205 /* If reloading from memory, see if there is a register
6206 that already holds the same value. If so, reload from there.
6207 We can pass 0 as the reload_reg_p argument because
6208 any other reload has either already been emitted,
6209 in which case find_equiv_reg will see the reload-insn,
6210 or has yet to be emitted, in which case it doesn't matter
6211 because we will use this equiv reg right away. */
6213 if (oldequiv == 0 && optimize
6214 && (GET_CODE (old) == MEM
6215 || (GET_CODE (old) == REG
6216 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6217 && reg_renumber[REGNO (old)] < 0)))
6218 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6222 unsigned int regno = true_regnum (oldequiv);
6224 /* Don't use OLDEQUIV if any other reload changes it at an
6225 earlier stage of this insn or at this stage. */
6226 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6227 rl->in, const0_rtx, j, 0))
6230 /* If it is no cheaper to copy from OLDEQUIV into the
6231 reload register than it would be to move from memory,
6232 don't use it. Likewise, if we need a secondary register
6236 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6237 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6239 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6240 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6241 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6245 #ifdef SECONDARY_MEMORY_NEEDED
6246 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6254 /* delete_output_reload is only invoked properly if old contains
6255 the original pseudo register. Since this is replaced with a
6256 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6257 find the pseudo in RELOAD_IN_REG. */
6259 && reload_override_in[j]
6260 && GET_CODE (rl->in_reg) == REG)
6267 else if (GET_CODE (oldequiv) == REG)
6268 oldequiv_reg = oldequiv;
6269 else if (GET_CODE (oldequiv) == SUBREG)
6270 oldequiv_reg = SUBREG_REG (oldequiv);
6272 /* If we are reloading from a register that was recently stored in
6273 with an output-reload, see if we can prove there was
6274 actually no need to store the old value in it. */
6276 if (optimize && GET_CODE (oldequiv) == REG
6277 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6278 && spill_reg_store[REGNO (oldequiv)]
6279 && GET_CODE (old) == REG
6280 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6281 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6283 delete_output_reload (insn, j, REGNO (oldequiv));
6285 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6286 then load RELOADREG from OLDEQUIV. Note that we cannot use
6287 gen_lowpart_common since it can do the wrong thing when
6288 RELOADREG has a multi-word mode. Note that RELOADREG
6289 must always be a REG here. */
6291 if (GET_MODE (reloadreg) != mode)
6292 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6293 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6294 oldequiv = SUBREG_REG (oldequiv);
6295 if (GET_MODE (oldequiv) != VOIDmode
6296 && mode != GET_MODE (oldequiv))
6297 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6299 /* Switch to the right place to emit the reload insns. */
6300 switch (rl->when_needed)
6303 where = &other_input_reload_insns;
6305 case RELOAD_FOR_INPUT:
6306 where = &input_reload_insns[rl->opnum];
6308 case RELOAD_FOR_INPUT_ADDRESS:
6309 where = &input_address_reload_insns[rl->opnum];
6311 case RELOAD_FOR_INPADDR_ADDRESS:
6312 where = &inpaddr_address_reload_insns[rl->opnum];
6314 case RELOAD_FOR_OUTPUT_ADDRESS:
6315 where = &output_address_reload_insns[rl->opnum];
6317 case RELOAD_FOR_OUTADDR_ADDRESS:
6318 where = &outaddr_address_reload_insns[rl->opnum];
6320 case RELOAD_FOR_OPERAND_ADDRESS:
6321 where = &operand_reload_insns;
6323 case RELOAD_FOR_OPADDR_ADDR:
6324 where = &other_operand_reload_insns;
6326 case RELOAD_FOR_OTHER_ADDRESS:
6327 where = &other_input_address_reload_insns;
6333 push_to_sequence (*where);
6335 /* Auto-increment addresses must be reloaded in a special way. */
6336 if (rl->out && ! rl->out_reg)
6338 /* We are not going to bother supporting the case where a
6339 incremented register can't be copied directly from
6340 OLDEQUIV since this seems highly unlikely. */
6341 if (rl->secondary_in_reload >= 0)
6344 if (reload_inherited[j])
6345 oldequiv = reloadreg;
6347 old = XEXP (rl->in_reg, 0);
6349 if (optimize && GET_CODE (oldequiv) == REG
6350 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6351 && spill_reg_store[REGNO (oldequiv)]
6352 && GET_CODE (old) == REG
6353 && (dead_or_set_p (insn,
6354 spill_reg_stored_to[REGNO (oldequiv)])
6355 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6357 delete_output_reload (insn, j, REGNO (oldequiv));
6359 /* Prevent normal processing of this reload. */
6361 /* Output a special code sequence for this case. */
6362 new_spill_reg_store[REGNO (reloadreg)]
6363 = inc_for_reload (reloadreg, oldequiv, rl->out,
6367 /* If we are reloading a pseudo-register that was set by the previous
6368 insn, see if we can get rid of that pseudo-register entirely
6369 by redirecting the previous insn into our reload register. */
6371 else if (optimize && GET_CODE (old) == REG
6372 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6373 && dead_or_set_p (insn, old)
6374 /* This is unsafe if some other reload
6375 uses the same reg first. */
6376 && ! conflicts_with_override (reloadreg)
6377 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6378 rl->when_needed, old, rl->out, j, 0))
6380 rtx temp = PREV_INSN (insn);
6381 while (temp && GET_CODE (temp) == NOTE)
6382 temp = PREV_INSN (temp);
6384 && GET_CODE (temp) == INSN
6385 && GET_CODE (PATTERN (temp)) == SET
6386 && SET_DEST (PATTERN (temp)) == old
6387 /* Make sure we can access insn_operand_constraint. */
6388 && asm_noperands (PATTERN (temp)) < 0
6389 /* This is unsafe if operand occurs more than once in current
6390 insn. Perhaps some occurrences aren't reloaded. */
6391 && count_occurrences (PATTERN (insn), old, 0) == 1)
6393 rtx old = SET_DEST (PATTERN (temp));
6394 /* Store into the reload register instead of the pseudo. */
6395 SET_DEST (PATTERN (temp)) = reloadreg;
6397 /* Verify that resulting insn is valid. */
6398 extract_insn (temp);
6399 if (constrain_operands (1))
6401 /* If the previous insn is an output reload, the source is
6402 a reload register, and its spill_reg_store entry will
6403 contain the previous destination. This is now
6405 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6406 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6408 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6409 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6412 /* If these are the only uses of the pseudo reg,
6413 pretend for GDB it lives in the reload reg we used. */
6414 if (REG_N_DEATHS (REGNO (old)) == 1
6415 && REG_N_SETS (REGNO (old)) == 1)
6417 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6418 alter_reg (REGNO (old), -1);
6424 SET_DEST (PATTERN (temp)) = old;
6429 /* We can't do that, so output an insn to load RELOADREG. */
6431 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6432 /* If we have a secondary reload, pick up the secondary register
6433 and icode, if any. If OLDEQUIV and OLD are different or
6434 if this is an in-out reload, recompute whether or not we
6435 still need a secondary register and what the icode should
6436 be. If we still need a secondary register and the class or
6437 icode is different, go back to reloading from OLD if using
6438 OLDEQUIV means that we got the wrong type of register. We
6439 cannot have different class or icode due to an in-out reload
6440 because we don't make such reloads when both the input and
6441 output need secondary reload registers. */
6443 if (! special && rl->secondary_in_reload >= 0)
6445 rtx second_reload_reg = 0;
6446 int secondary_reload = rl->secondary_in_reload;
6447 rtx real_oldequiv = oldequiv;
6450 enum insn_code icode;
6452 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6453 and similarly for OLD.
6454 See comments in get_secondary_reload in reload.c. */
6455 /* If it is a pseudo that cannot be replaced with its
6456 equivalent MEM, we must fall back to reload_in, which
6457 will have all the necessary substitutions registered.
6458 Likewise for a pseudo that can't be replaced with its
6459 equivalent constant.
6461 Take extra care for subregs of such pseudos. Note that
6462 we cannot use reg_equiv_mem in this case because it is
6463 not in the right mode. */
6466 if (GET_CODE (tmp) == SUBREG)
6467 tmp = SUBREG_REG (tmp);
6468 if (GET_CODE (tmp) == REG
6469 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6470 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6471 || reg_equiv_constant[REGNO (tmp)] != 0))
6473 if (! reg_equiv_mem[REGNO (tmp)]
6474 || num_not_at_initial_offset
6475 || GET_CODE (oldequiv) == SUBREG)
6476 real_oldequiv = rl->in;
6478 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6482 if (GET_CODE (tmp) == SUBREG)
6483 tmp = SUBREG_REG (tmp);
6484 if (GET_CODE (tmp) == REG
6485 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6486 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6487 || reg_equiv_constant[REGNO (tmp)] != 0))
6489 if (! reg_equiv_mem[REGNO (tmp)]
6490 || num_not_at_initial_offset
6491 || GET_CODE (old) == SUBREG)
6494 real_old = reg_equiv_mem[REGNO (tmp)];
6497 second_reload_reg = rld[secondary_reload].reg_rtx;
6498 icode = rl->secondary_in_icode;
6500 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6501 || (rl->in != 0 && rl->out != 0))
6503 enum reg_class new_class
6504 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6505 mode, real_oldequiv);
6507 if (new_class == NO_REGS)
6508 second_reload_reg = 0;
6511 enum insn_code new_icode;
6512 enum machine_mode new_mode;
6514 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6515 REGNO (second_reload_reg)))
6516 oldequiv = old, real_oldequiv = real_old;
6519 new_icode = reload_in_optab[(int) mode];
6520 if (new_icode != CODE_FOR_nothing
6521 && ((insn_data[(int) new_icode].operand[0].predicate
6522 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6524 || (insn_data[(int) new_icode].operand[1].predicate
6525 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6526 (real_oldequiv, mode)))))
6527 new_icode = CODE_FOR_nothing;
6529 if (new_icode == CODE_FOR_nothing)
6532 new_mode = insn_data[(int) new_icode].operand[2].mode;
6534 if (GET_MODE (second_reload_reg) != new_mode)
6536 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6538 oldequiv = old, real_oldequiv = real_old;
6541 = reload_adjust_reg_for_mode (second_reload_reg,
6548 /* If we still need a secondary reload register, check
6549 to see if it is being used as a scratch or intermediate
6550 register and generate code appropriately. If we need
6551 a scratch register, use REAL_OLDEQUIV since the form of
6552 the insn may depend on the actual address if it is
6555 if (second_reload_reg)
6557 if (icode != CODE_FOR_nothing)
6559 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6560 second_reload_reg));
6565 /* See if we need a scratch register to load the
6566 intermediate register (a tertiary reload). */
6567 enum insn_code tertiary_icode
6568 = rld[secondary_reload].secondary_in_icode;
6570 if (tertiary_icode != CODE_FOR_nothing)
6572 rtx third_reload_reg
6573 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6575 emit_insn ((GEN_FCN (tertiary_icode)
6576 (second_reload_reg, real_oldequiv,
6577 third_reload_reg)));
6580 gen_reload (second_reload_reg, real_oldequiv,
6584 oldequiv = second_reload_reg;
6590 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6592 rtx real_oldequiv = oldequiv;
6594 if ((GET_CODE (oldequiv) == REG
6595 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6596 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6597 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6598 || (GET_CODE (oldequiv) == SUBREG
6599 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6600 && (REGNO (SUBREG_REG (oldequiv))
6601 >= FIRST_PSEUDO_REGISTER)
6602 && ((reg_equiv_memory_loc
6603 [REGNO (SUBREG_REG (oldequiv))] != 0)
6604 || (reg_equiv_constant
6605 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6606 || (CONSTANT_P (oldequiv)
6607 && (PREFERRED_RELOAD_CLASS (oldequiv,
6608 REGNO_REG_CLASS (REGNO (reloadreg)))
6610 real_oldequiv = rl->in;
6611 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6615 if (flag_non_call_exceptions)
6616 copy_eh_notes (insn, get_insns ());
6618 /* End this sequence. */
6619 *where = get_insns ();
6622 /* Update reload_override_in so that delete_address_reloads_1
6623 can see the actual register usage. */
6625 reload_override_in[j] = oldequiv;
6628 /* Generate insns to for the output reload RL, which is for the insn described
6629 by CHAIN and has the number J. */
6631 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6634 rtx reloadreg = rl->reg_rtx;
6635 rtx insn = chain->insn;
6638 enum machine_mode mode = GET_MODE (old);
6641 if (rl->when_needed == RELOAD_OTHER)
6644 push_to_sequence (output_reload_insns[rl->opnum]);
6646 /* Determine the mode to reload in.
6647 See comments above (for input reloading). */
6649 if (mode == VOIDmode)
6651 /* VOIDmode should never happen for an output. */
6652 if (asm_noperands (PATTERN (insn)) < 0)
6653 /* It's the compiler's fault. */
6654 fatal_insn ("VOIDmode on an output", insn);
6655 error_for_asm (insn, "output operand is constant in `asm'");
6656 /* Prevent crash--use something we know is valid. */
6658 old = gen_rtx_REG (mode, REGNO (reloadreg));
6661 if (GET_MODE (reloadreg) != mode)
6662 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6664 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6666 /* If we need two reload regs, set RELOADREG to the intermediate
6667 one, since it will be stored into OLD. We might need a secondary
6668 register only for an input reload, so check again here. */
6670 if (rl->secondary_out_reload >= 0)
6674 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6675 && reg_equiv_mem[REGNO (old)] != 0)
6676 real_old = reg_equiv_mem[REGNO (old)];
6678 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6682 rtx second_reloadreg = reloadreg;
6683 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6685 /* See if RELOADREG is to be used as a scratch register
6686 or as an intermediate register. */
6687 if (rl->secondary_out_icode != CODE_FOR_nothing)
6689 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6690 (real_old, second_reloadreg, reloadreg)));
6695 /* See if we need both a scratch and intermediate reload
6698 int secondary_reload = rl->secondary_out_reload;
6699 enum insn_code tertiary_icode
6700 = rld[secondary_reload].secondary_out_icode;
6702 if (GET_MODE (reloadreg) != mode)
6703 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6705 if (tertiary_icode != CODE_FOR_nothing)
6708 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6711 /* Copy primary reload reg to secondary reload reg.
6712 (Note that these have been swapped above, then
6713 secondary reload reg to OLD using our insn.) */
6715 /* If REAL_OLD is a paradoxical SUBREG, remove it
6716 and try to put the opposite SUBREG on
6718 if (GET_CODE (real_old) == SUBREG
6719 && (GET_MODE_SIZE (GET_MODE (real_old))
6720 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6721 && 0 != (tem = gen_lowpart_common
6722 (GET_MODE (SUBREG_REG (real_old)),
6724 real_old = SUBREG_REG (real_old), reloadreg = tem;
6726 gen_reload (reloadreg, second_reloadreg,
6727 rl->opnum, rl->when_needed);
6728 emit_insn ((GEN_FCN (tertiary_icode)
6729 (real_old, reloadreg, third_reloadreg)));
6734 /* Copy between the reload regs here and then to
6737 gen_reload (reloadreg, second_reloadreg,
6738 rl->opnum, rl->when_needed);
6744 /* Output the last reload insn. */
6749 /* Don't output the last reload if OLD is not the dest of
6750 INSN and is in the src and is clobbered by INSN. */
6751 if (! flag_expensive_optimizations
6752 || GET_CODE (old) != REG
6753 || !(set = single_set (insn))
6754 || rtx_equal_p (old, SET_DEST (set))
6755 || !reg_mentioned_p (old, SET_SRC (set))
6756 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6757 gen_reload (old, reloadreg, rl->opnum,
6761 /* Look at all insns we emitted, just to be safe. */
6762 for (p = get_insns (); p; p = NEXT_INSN (p))
6765 rtx pat = PATTERN (p);
6767 /* If this output reload doesn't come from a spill reg,
6768 clear any memory of reloaded copies of the pseudo reg.
6769 If this output reload comes from a spill reg,
6770 reg_has_output_reload will make this do nothing. */
6771 note_stores (pat, forget_old_reloads_1, NULL);
6773 if (reg_mentioned_p (rl->reg_rtx, pat))
6775 rtx set = single_set (insn);
6776 if (reload_spill_index[j] < 0
6778 && SET_SRC (set) == rl->reg_rtx)
6780 int src = REGNO (SET_SRC (set));
6782 reload_spill_index[j] = src;
6783 SET_HARD_REG_BIT (reg_is_output_reload, src);
6784 if (find_regno_note (insn, REG_DEAD, src))
6785 SET_HARD_REG_BIT (reg_reloaded_died, src);
6787 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6789 int s = rl->secondary_out_reload;
6790 set = single_set (p);
6791 /* If this reload copies only to the secondary reload
6792 register, the secondary reload does the actual
6794 if (s >= 0 && set == NULL_RTX)
6795 /* We can't tell what function the secondary reload
6796 has and where the actual store to the pseudo is
6797 made; leave new_spill_reg_store alone. */
6800 && SET_SRC (set) == rl->reg_rtx
6801 && SET_DEST (set) == rld[s].reg_rtx)
6803 /* Usually the next instruction will be the
6804 secondary reload insn; if we can confirm
6805 that it is, setting new_spill_reg_store to
6806 that insn will allow an extra optimization. */
6807 rtx s_reg = rld[s].reg_rtx;
6808 rtx next = NEXT_INSN (p);
6809 rld[s].out = rl->out;
6810 rld[s].out_reg = rl->out_reg;
6811 set = single_set (next);
6812 if (set && SET_SRC (set) == s_reg
6813 && ! new_spill_reg_store[REGNO (s_reg)])
6815 SET_HARD_REG_BIT (reg_is_output_reload,
6817 new_spill_reg_store[REGNO (s_reg)] = next;
6821 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6826 if (rl->when_needed == RELOAD_OTHER)
6828 emit_insn (other_output_reload_insns[rl->opnum]);
6829 other_output_reload_insns[rl->opnum] = get_insns ();
6832 output_reload_insns[rl->opnum] = get_insns ();
6834 if (flag_non_call_exceptions)
6835 copy_eh_notes (insn, get_insns ());
6840 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6841 and has the number J. */
6843 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
6845 rtx insn = chain->insn;
6846 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6847 ? rl->in_reg : rl->in);
6850 /* AUTO_INC reloads need to be handled even if inherited. We got an
6851 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6852 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6853 && ! rtx_equal_p (rl->reg_rtx, old)
6854 && rl->reg_rtx != 0)
6855 emit_input_reload_insns (chain, rld + j, old, j);
6857 /* When inheriting a wider reload, we have a MEM in rl->in,
6858 e.g. inheriting a SImode output reload for
6859 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6860 if (optimize && reload_inherited[j] && rl->in
6861 && GET_CODE (rl->in) == MEM
6862 && GET_CODE (rl->in_reg) == MEM
6863 && reload_spill_index[j] >= 0
6864 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6865 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6867 /* If we are reloading a register that was recently stored in with an
6868 output-reload, see if we can prove there was
6869 actually no need to store the old value in it. */
6872 && (reload_inherited[j] || reload_override_in[j])
6874 && GET_CODE (rl->reg_rtx) == REG
6875 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6877 /* There doesn't seem to be any reason to restrict this to pseudos
6878 and doing so loses in the case where we are copying from a
6879 register of the wrong class. */
6880 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6881 >= FIRST_PSEUDO_REGISTER)
6883 /* The insn might have already some references to stackslots
6884 replaced by MEMs, while reload_out_reg still names the
6886 && (dead_or_set_p (insn,
6887 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6888 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6890 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6893 /* Do output reloading for reload RL, which is for the insn described by
6894 CHAIN and has the number J.
6895 ??? At some point we need to support handling output reloads of
6896 JUMP_INSNs or insns that set cc0. */
6898 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
6901 rtx insn = chain->insn;
6902 /* If this is an output reload that stores something that is
6903 not loaded in this same reload, see if we can eliminate a previous
6905 rtx pseudo = rl->out_reg;
6909 && GET_CODE (pseudo) == REG
6910 && ! rtx_equal_p (rl->in_reg, pseudo)
6911 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6912 && reg_last_reload_reg[REGNO (pseudo)])
6914 int pseudo_no = REGNO (pseudo);
6915 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6917 /* We don't need to test full validity of last_regno for
6918 inherit here; we only want to know if the store actually
6919 matches the pseudo. */
6920 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6921 && reg_reloaded_contents[last_regno] == pseudo_no
6922 && spill_reg_store[last_regno]
6923 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6924 delete_output_reload (insn, j, last_regno);
6929 || rl->reg_rtx == old
6930 || rl->reg_rtx == 0)
6933 /* An output operand that dies right away does need a reload,
6934 but need not be copied from it. Show the new location in the
6936 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6937 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6939 XEXP (note, 0) = rl->reg_rtx;
6942 /* Likewise for a SUBREG of an operand that dies. */
6943 else if (GET_CODE (old) == SUBREG
6944 && GET_CODE (SUBREG_REG (old)) == REG
6945 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6948 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6952 else if (GET_CODE (old) == SCRATCH)
6953 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6954 but we don't want to make an output reload. */
6957 /* If is a JUMP_INSN, we can't support output reloads yet. */
6958 if (GET_CODE (insn) == JUMP_INSN)
6961 emit_output_reload_insns (chain, rld + j, j);
6964 /* Reload number R reloads from or to a group of hard registers starting at
6965 register REGNO. Return true if it can be treated for inheritance purposes
6966 like a group of reloads, each one reloading a single hard register.
6967 The caller has already checked that the spill register and REGNO use
6968 the same number of registers to store the reload value. */
6971 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
6973 #ifdef CANNOT_CHANGE_MODE_CLASS
6974 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
6975 GET_MODE (rld[r].reg_rtx),
6976 reg_raw_mode[reload_spill_index[r]])
6977 && !REG_CANNOT_CHANGE_MODE_P (regno,
6978 GET_MODE (rld[r].reg_rtx),
6979 reg_raw_mode[regno]));
6985 /* Output insns to reload values in and out of the chosen reload regs. */
6988 emit_reload_insns (struct insn_chain *chain)
6990 rtx insn = chain->insn;
6994 CLEAR_HARD_REG_SET (reg_reloaded_died);
6996 for (j = 0; j < reload_n_operands; j++)
6997 input_reload_insns[j] = input_address_reload_insns[j]
6998 = inpaddr_address_reload_insns[j]
6999 = output_reload_insns[j] = output_address_reload_insns[j]
7000 = outaddr_address_reload_insns[j]
7001 = other_output_reload_insns[j] = 0;
7002 other_input_address_reload_insns = 0;
7003 other_input_reload_insns = 0;
7004 operand_reload_insns = 0;
7005 other_operand_reload_insns = 0;
7007 /* Dump reloads into the dump file. */
7010 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7011 debug_reload_to_stream (dump_file);
7014 /* Now output the instructions to copy the data into and out of the
7015 reload registers. Do these in the order that the reloads were reported,
7016 since reloads of base and index registers precede reloads of operands
7017 and the operands may need the base and index registers reloaded. */
7019 for (j = 0; j < n_reloads; j++)
7022 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7023 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7025 do_input_reload (chain, rld + j, j);
7026 do_output_reload (chain, rld + j, j);
7029 /* Now write all the insns we made for reloads in the order expected by
7030 the allocation functions. Prior to the insn being reloaded, we write
7031 the following reloads:
7033 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7035 RELOAD_OTHER reloads.
7037 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7038 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7039 RELOAD_FOR_INPUT reload for the operand.
7041 RELOAD_FOR_OPADDR_ADDRS reloads.
7043 RELOAD_FOR_OPERAND_ADDRESS reloads.
7045 After the insn being reloaded, we write the following:
7047 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7048 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7049 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7050 reloads for the operand. The RELOAD_OTHER output reloads are
7051 output in descending order by reload number. */
7053 emit_insn_before_sameloc (other_input_address_reload_insns, insn);
7054 emit_insn_before_sameloc (other_input_reload_insns, insn);
7056 for (j = 0; j < reload_n_operands; j++)
7058 emit_insn_before_sameloc (inpaddr_address_reload_insns[j], insn);
7059 emit_insn_before_sameloc (input_address_reload_insns[j], insn);
7060 emit_insn_before_sameloc (input_reload_insns[j], insn);
7063 emit_insn_before_sameloc (other_operand_reload_insns, insn);
7064 emit_insn_before_sameloc (operand_reload_insns, insn);
7066 for (j = 0; j < reload_n_operands; j++)
7068 rtx x = emit_insn_after_sameloc (outaddr_address_reload_insns[j], insn);
7069 x = emit_insn_after_sameloc (output_address_reload_insns[j], x);
7070 x = emit_insn_after_sameloc (output_reload_insns[j], x);
7071 emit_insn_after_sameloc (other_output_reload_insns[j], x);
7074 /* For all the spill regs newly reloaded in this instruction,
7075 record what they were reloaded from, so subsequent instructions
7076 can inherit the reloads.
7078 Update spill_reg_store for the reloads of this insn.
7079 Copy the elements that were updated in the loop above. */
7081 for (j = 0; j < n_reloads; j++)
7083 int r = reload_order[j];
7084 int i = reload_spill_index[r];
7086 /* If this is a non-inherited input reload from a pseudo, we must
7087 clear any memory of a previous store to the same pseudo. Only do
7088 something if there will not be an output reload for the pseudo
7090 if (rld[r].in_reg != 0
7091 && ! (reload_inherited[r] || reload_override_in[r]))
7093 rtx reg = rld[r].in_reg;
7095 if (GET_CODE (reg) == SUBREG)
7096 reg = SUBREG_REG (reg);
7098 if (GET_CODE (reg) == REG
7099 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7100 && ! reg_has_output_reload[REGNO (reg)])
7102 int nregno = REGNO (reg);
7104 if (reg_last_reload_reg[nregno])
7106 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7108 if (reg_reloaded_contents[last_regno] == nregno)
7109 spill_reg_store[last_regno] = 0;
7114 /* I is nonneg if this reload used a register.
7115 If rld[r].reg_rtx is 0, this is an optional reload
7116 that we opted to ignore. */
7118 if (i >= 0 && rld[r].reg_rtx != 0)
7120 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7122 int part_reaches_end = 0;
7123 int all_reaches_end = 1;
7125 /* For a multi register reload, we need to check if all or part
7126 of the value lives to the end. */
7127 for (k = 0; k < nr; k++)
7129 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7130 rld[r].when_needed))
7131 part_reaches_end = 1;
7133 all_reaches_end = 0;
7136 /* Ignore reloads that don't reach the end of the insn in
7138 if (all_reaches_end)
7140 /* First, clear out memory of what used to be in this spill reg.
7141 If consecutive registers are used, clear them all. */
7143 for (k = 0; k < nr; k++)
7145 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7146 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7149 /* Maybe the spill reg contains a copy of reload_out. */
7151 && (GET_CODE (rld[r].out) == REG
7155 || GET_CODE (rld[r].out_reg) == REG))
7157 rtx out = (GET_CODE (rld[r].out) == REG
7161 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7162 int nregno = REGNO (out);
7163 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7164 : hard_regno_nregs[nregno]
7165 [GET_MODE (rld[r].reg_rtx)]);
7168 spill_reg_store[i] = new_spill_reg_store[i];
7169 spill_reg_stored_to[i] = out;
7170 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7172 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7174 && inherit_piecemeal_p (r, nregno));
7176 /* If NREGNO is a hard register, it may occupy more than
7177 one register. If it does, say what is in the
7178 rest of the registers assuming that both registers
7179 agree on how many words the object takes. If not,
7180 invalidate the subsequent registers. */
7182 if (nregno < FIRST_PSEUDO_REGISTER)
7183 for (k = 1; k < nnr; k++)
7184 reg_last_reload_reg[nregno + k]
7186 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7189 /* Now do the inverse operation. */
7190 for (k = 0; k < nr; k++)
7192 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7193 reg_reloaded_contents[i + k]
7194 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7197 reg_reloaded_insn[i + k] = insn;
7198 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7199 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7200 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7204 /* Maybe the spill reg contains a copy of reload_in. Only do
7205 something if there will not be an output reload for
7206 the register being reloaded. */
7207 else if (rld[r].out_reg == 0
7209 && ((GET_CODE (rld[r].in) == REG
7210 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7211 && ! reg_has_output_reload[REGNO (rld[r].in)])
7212 || (GET_CODE (rld[r].in_reg) == REG
7213 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7214 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7221 if (GET_CODE (rld[r].in) == REG
7222 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7224 else if (GET_CODE (rld[r].in_reg) == REG)
7227 in = XEXP (rld[r].in_reg, 0);
7228 nregno = REGNO (in);
7230 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7231 : hard_regno_nregs[nregno]
7232 [GET_MODE (rld[r].reg_rtx)]);
7234 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7236 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7238 && inherit_piecemeal_p (r, nregno));
7240 if (nregno < FIRST_PSEUDO_REGISTER)
7241 for (k = 1; k < nnr; k++)
7242 reg_last_reload_reg[nregno + k]
7244 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7247 /* Unless we inherited this reload, show we haven't
7248 recently done a store.
7249 Previous stores of inherited auto_inc expressions
7250 also have to be discarded. */
7251 if (! reload_inherited[r]
7252 || (rld[r].out && ! rld[r].out_reg))
7253 spill_reg_store[i] = 0;
7255 for (k = 0; k < nr; k++)
7257 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7258 reg_reloaded_contents[i + k]
7259 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7262 reg_reloaded_insn[i + k] = insn;
7263 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7264 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7265 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7270 /* However, if part of the reload reaches the end, then we must
7271 invalidate the old info for the part that survives to the end. */
7272 else if (part_reaches_end)
7274 for (k = 0; k < nr; k++)
7275 if (reload_reg_reaches_end_p (i + k,
7277 rld[r].when_needed))
7278 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7282 /* The following if-statement was #if 0'd in 1.34 (or before...).
7283 It's reenabled in 1.35 because supposedly nothing else
7284 deals with this problem. */
7286 /* If a register gets output-reloaded from a non-spill register,
7287 that invalidates any previous reloaded copy of it.
7288 But forget_old_reloads_1 won't get to see it, because
7289 it thinks only about the original insn. So invalidate it here. */
7290 if (i < 0 && rld[r].out != 0
7291 && (GET_CODE (rld[r].out) == REG
7292 || (GET_CODE (rld[r].out) == MEM
7293 && GET_CODE (rld[r].out_reg) == REG)))
7295 rtx out = (GET_CODE (rld[r].out) == REG
7296 ? rld[r].out : rld[r].out_reg);
7297 int nregno = REGNO (out);
7298 if (nregno >= FIRST_PSEUDO_REGISTER)
7300 rtx src_reg, store_insn = NULL_RTX;
7302 reg_last_reload_reg[nregno] = 0;
7304 /* If we can find a hard register that is stored, record
7305 the storing insn so that we may delete this insn with
7306 delete_output_reload. */
7307 src_reg = rld[r].reg_rtx;
7309 /* If this is an optional reload, try to find the source reg
7310 from an input reload. */
7313 rtx set = single_set (insn);
7314 if (set && SET_DEST (set) == rld[r].out)
7318 src_reg = SET_SRC (set);
7320 for (k = 0; k < n_reloads; k++)
7322 if (rld[k].in == src_reg)
7324 src_reg = rld[k].reg_rtx;
7331 store_insn = new_spill_reg_store[REGNO (src_reg)];
7332 if (src_reg && GET_CODE (src_reg) == REG
7333 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7335 int src_regno = REGNO (src_reg);
7336 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7337 /* The place where to find a death note varies with
7338 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7339 necessarily checked exactly in the code that moves
7340 notes, so just check both locations. */
7341 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7342 if (! note && store_insn)
7343 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7346 spill_reg_store[src_regno + nr] = store_insn;
7347 spill_reg_stored_to[src_regno + nr] = out;
7348 reg_reloaded_contents[src_regno + nr] = nregno;
7349 reg_reloaded_insn[src_regno + nr] = store_insn;
7350 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7351 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7352 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7353 GET_MODE (src_reg)))
7354 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7356 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7358 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7360 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7362 reg_last_reload_reg[nregno] = src_reg;
7363 /* We have to set reg_has_output_reload here, or else
7364 forget_old_reloads_1 will clear reg_last_reload_reg
7366 reg_has_output_reload[nregno] = 1;
7371 int num_regs = hard_regno_nregs[nregno][GET_MODE (rld[r].out)];
7373 while (num_regs-- > 0)
7374 reg_last_reload_reg[nregno + num_regs] = 0;
7378 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7381 /* Emit code to perform a reload from IN (which may be a reload register) to
7382 OUT (which may also be a reload register). IN or OUT is from operand
7383 OPNUM with reload type TYPE.
7385 Returns first insn emitted. */
7388 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7390 rtx last = get_last_insn ();
7393 /* If IN is a paradoxical SUBREG, remove it and try to put the
7394 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7395 if (GET_CODE (in) == SUBREG
7396 && (GET_MODE_SIZE (GET_MODE (in))
7397 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7398 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7399 in = SUBREG_REG (in), out = tem;
7400 else if (GET_CODE (out) == SUBREG
7401 && (GET_MODE_SIZE (GET_MODE (out))
7402 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7403 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7404 out = SUBREG_REG (out), in = tem;
7406 /* How to do this reload can get quite tricky. Normally, we are being
7407 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7408 register that didn't get a hard register. In that case we can just
7409 call emit_move_insn.
7411 We can also be asked to reload a PLUS that adds a register or a MEM to
7412 another register, constant or MEM. This can occur during frame pointer
7413 elimination and while reloading addresses. This case is handled by
7414 trying to emit a single insn to perform the add. If it is not valid,
7415 we use a two insn sequence.
7417 Finally, we could be called to handle an 'o' constraint by putting
7418 an address into a register. In that case, we first try to do this
7419 with a named pattern of "reload_load_address". If no such pattern
7420 exists, we just emit a SET insn and hope for the best (it will normally
7421 be valid on machines that use 'o').
7423 This entire process is made complex because reload will never
7424 process the insns we generate here and so we must ensure that
7425 they will fit their constraints and also by the fact that parts of
7426 IN might be being reloaded separately and replaced with spill registers.
7427 Because of this, we are, in some sense, just guessing the right approach
7428 here. The one listed above seems to work.
7430 ??? At some point, this whole thing needs to be rethought. */
7432 if (GET_CODE (in) == PLUS
7433 && (GET_CODE (XEXP (in, 0)) == REG
7434 || GET_CODE (XEXP (in, 0)) == SUBREG
7435 || GET_CODE (XEXP (in, 0)) == MEM)
7436 && (GET_CODE (XEXP (in, 1)) == REG
7437 || GET_CODE (XEXP (in, 1)) == SUBREG
7438 || CONSTANT_P (XEXP (in, 1))
7439 || GET_CODE (XEXP (in, 1)) == MEM))
7441 /* We need to compute the sum of a register or a MEM and another
7442 register, constant, or MEM, and put it into the reload
7443 register. The best possible way of doing this is if the machine
7444 has a three-operand ADD insn that accepts the required operands.
7446 The simplest approach is to try to generate such an insn and see if it
7447 is recognized and matches its constraints. If so, it can be used.
7449 It might be better not to actually emit the insn unless it is valid,
7450 but we need to pass the insn as an operand to `recog' and
7451 `extract_insn' and it is simpler to emit and then delete the insn if
7452 not valid than to dummy things up. */
7454 rtx op0, op1, tem, insn;
7457 op0 = find_replacement (&XEXP (in, 0));
7458 op1 = find_replacement (&XEXP (in, 1));
7460 /* Since constraint checking is strict, commutativity won't be
7461 checked, so we need to do that here to avoid spurious failure
7462 if the add instruction is two-address and the second operand
7463 of the add is the same as the reload reg, which is frequently
7464 the case. If the insn would be A = B + A, rearrange it so
7465 it will be A = A + B as constrain_operands expects. */
7467 if (GET_CODE (XEXP (in, 1)) == REG
7468 && REGNO (out) == REGNO (XEXP (in, 1)))
7469 tem = op0, op0 = op1, op1 = tem;
7471 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7472 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7474 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7475 code = recog_memoized (insn);
7479 extract_insn (insn);
7480 /* We want constrain operands to treat this insn strictly in
7481 its validity determination, i.e., the way it would after reload
7483 if (constrain_operands (1))
7487 delete_insns_since (last);
7489 /* If that failed, we must use a conservative two-insn sequence.
7491 Use a move to copy one operand into the reload register. Prefer
7492 to reload a constant, MEM or pseudo since the move patterns can
7493 handle an arbitrary operand. If OP1 is not a constant, MEM or
7494 pseudo and OP1 is not a valid operand for an add instruction, then
7497 After reloading one of the operands into the reload register, add
7498 the reload register to the output register.
7500 If there is another way to do this for a specific machine, a
7501 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7504 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7506 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7507 || (GET_CODE (op1) == REG
7508 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7509 || (code != CODE_FOR_nothing
7510 && ! ((*insn_data[code].operand[2].predicate)
7511 (op1, insn_data[code].operand[2].mode))))
7512 tem = op0, op0 = op1, op1 = tem;
7514 gen_reload (out, op0, opnum, type);
7516 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7517 This fixes a problem on the 32K where the stack pointer cannot
7518 be used as an operand of an add insn. */
7520 if (rtx_equal_p (op0, op1))
7523 insn = emit_insn (gen_add2_insn (out, op1));
7525 /* If that failed, copy the address register to the reload register.
7526 Then add the constant to the reload register. */
7528 code = recog_memoized (insn);
7532 extract_insn (insn);
7533 /* We want constrain operands to treat this insn strictly in
7534 its validity determination, i.e., the way it would after reload
7536 if (constrain_operands (1))
7538 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7540 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7545 delete_insns_since (last);
7547 gen_reload (out, op1, opnum, type);
7548 insn = emit_insn (gen_add2_insn (out, op0));
7549 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7552 #ifdef SECONDARY_MEMORY_NEEDED
7553 /* If we need a memory location to do the move, do it that way. */
7554 else if ((GET_CODE (in) == REG || GET_CODE (in) == SUBREG)
7555 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7556 && (GET_CODE (out) == REG || GET_CODE (out) == SUBREG)
7557 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7558 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7559 REGNO_REG_CLASS (reg_or_subregno (out)),
7562 /* Get the memory to use and rewrite both registers to its mode. */
7563 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7565 if (GET_MODE (loc) != GET_MODE (out))
7566 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7568 if (GET_MODE (loc) != GET_MODE (in))
7569 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7571 gen_reload (loc, in, opnum, type);
7572 gen_reload (out, loc, opnum, type);
7576 /* If IN is a simple operand, use gen_move_insn. */
7577 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
7578 emit_insn (gen_move_insn (out, in));
7580 #ifdef HAVE_reload_load_address
7581 else if (HAVE_reload_load_address)
7582 emit_insn (gen_reload_load_address (out, in));
7585 /* Otherwise, just write (set OUT IN) and hope for the best. */
7587 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7589 /* Return the first insn emitted.
7590 We can not just return get_last_insn, because there may have
7591 been multiple instructions emitted. Also note that gen_move_insn may
7592 emit more than one insn itself, so we can not assume that there is one
7593 insn emitted per emit_insn_before call. */
7595 return last ? NEXT_INSN (last) : get_insns ();
7598 /* Delete a previously made output-reload whose result we now believe
7599 is not needed. First we double-check.
7601 INSN is the insn now being processed.
7602 LAST_RELOAD_REG is the hard register number for which we want to delete
7603 the last output reload.
7604 J is the reload-number that originally used REG. The caller has made
7605 certain that reload J doesn't use REG any longer for input. */
7608 delete_output_reload (rtx insn, int j, int last_reload_reg)
7610 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7611 rtx reg = spill_reg_stored_to[last_reload_reg];
7614 int n_inherited = 0;
7618 /* It is possible that this reload has been only used to set another reload
7619 we eliminated earlier and thus deleted this instruction too. */
7620 if (INSN_DELETED_P (output_reload_insn))
7623 /* Get the raw pseudo-register referred to. */
7625 while (GET_CODE (reg) == SUBREG)
7626 reg = SUBREG_REG (reg);
7627 substed = reg_equiv_memory_loc[REGNO (reg)];
7629 /* This is unsafe if the operand occurs more often in the current
7630 insn than it is inherited. */
7631 for (k = n_reloads - 1; k >= 0; k--)
7633 rtx reg2 = rld[k].in;
7636 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7637 reg2 = rld[k].in_reg;
7639 if (rld[k].out && ! rld[k].out_reg)
7640 reg2 = XEXP (rld[k].in_reg, 0);
7642 while (GET_CODE (reg2) == SUBREG)
7643 reg2 = SUBREG_REG (reg2);
7644 if (rtx_equal_p (reg2, reg))
7646 if (reload_inherited[k] || reload_override_in[k] || k == j)
7649 reg2 = rld[k].out_reg;
7652 while (GET_CODE (reg2) == SUBREG)
7653 reg2 = XEXP (reg2, 0);
7654 if (rtx_equal_p (reg2, reg))
7661 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7663 n_occurrences += count_occurrences (PATTERN (insn),
7664 eliminate_regs (substed, 0,
7666 if (n_occurrences > n_inherited)
7669 /* If the pseudo-reg we are reloading is no longer referenced
7670 anywhere between the store into it and here,
7671 and no jumps or labels intervene, then the value can get
7672 here through the reload reg alone.
7673 Otherwise, give up--return. */
7674 for (i1 = NEXT_INSN (output_reload_insn);
7675 i1 != insn; i1 = NEXT_INSN (i1))
7677 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7679 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7680 && reg_mentioned_p (reg, PATTERN (i1)))
7682 /* If this is USE in front of INSN, we only have to check that
7683 there are no more references than accounted for by inheritance. */
7684 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7686 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7687 i1 = NEXT_INSN (i1);
7689 if (n_occurrences <= n_inherited && i1 == insn)
7695 /* We will be deleting the insn. Remove the spill reg information. */
7696 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
7698 spill_reg_store[last_reload_reg + k] = 0;
7699 spill_reg_stored_to[last_reload_reg + k] = 0;
7702 /* The caller has already checked that REG dies or is set in INSN.
7703 It has also checked that we are optimizing, and thus some
7704 inaccuracies in the debugging information are acceptable.
7705 So we could just delete output_reload_insn. But in some cases
7706 we can improve the debugging information without sacrificing
7707 optimization - maybe even improving the code: See if the pseudo
7708 reg has been completely replaced with reload regs. If so, delete
7709 the store insn and forget we had a stack slot for the pseudo. */
7710 if (rld[j].out != rld[j].in
7711 && REG_N_DEATHS (REGNO (reg)) == 1
7712 && REG_N_SETS (REGNO (reg)) == 1
7713 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7714 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7718 /* We know that it was used only between here and the beginning of
7719 the current basic block. (We also know that the last use before
7720 INSN was the output reload we are thinking of deleting, but never
7721 mind that.) Search that range; see if any ref remains. */
7722 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7724 rtx set = single_set (i2);
7726 /* Uses which just store in the pseudo don't count,
7727 since if they are the only uses, they are dead. */
7728 if (set != 0 && SET_DEST (set) == reg)
7730 if (GET_CODE (i2) == CODE_LABEL
7731 || GET_CODE (i2) == JUMP_INSN)
7733 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7734 && reg_mentioned_p (reg, PATTERN (i2)))
7736 /* Some other ref remains; just delete the output reload we
7738 delete_address_reloads (output_reload_insn, insn);
7739 delete_insn (output_reload_insn);
7744 /* Delete the now-dead stores into this pseudo. Note that this
7745 loop also takes care of deleting output_reload_insn. */
7746 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7748 rtx set = single_set (i2);
7750 if (set != 0 && SET_DEST (set) == reg)
7752 delete_address_reloads (i2, insn);
7755 if (GET_CODE (i2) == CODE_LABEL
7756 || GET_CODE (i2) == JUMP_INSN)
7760 /* For the debugging info, say the pseudo lives in this reload reg. */
7761 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7762 alter_reg (REGNO (reg), -1);
7766 delete_address_reloads (output_reload_insn, insn);
7767 delete_insn (output_reload_insn);
7771 /* We are going to delete DEAD_INSN. Recursively delete loads of
7772 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7773 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7775 delete_address_reloads (rtx dead_insn, rtx current_insn)
7777 rtx set = single_set (dead_insn);
7778 rtx set2, dst, prev, next;
7781 rtx dst = SET_DEST (set);
7782 if (GET_CODE (dst) == MEM)
7783 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7785 /* If we deleted the store from a reloaded post_{in,de}c expression,
7786 we can delete the matching adds. */
7787 prev = PREV_INSN (dead_insn);
7788 next = NEXT_INSN (dead_insn);
7789 if (! prev || ! next)
7791 set = single_set (next);
7792 set2 = single_set (prev);
7794 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7795 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7796 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7798 dst = SET_DEST (set);
7799 if (! rtx_equal_p (dst, SET_DEST (set2))
7800 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7801 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7802 || (INTVAL (XEXP (SET_SRC (set), 1))
7803 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7805 delete_related_insns (prev);
7806 delete_related_insns (next);
7809 /* Subfunction of delete_address_reloads: process registers found in X. */
7811 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
7813 rtx prev, set, dst, i2;
7815 enum rtx_code code = GET_CODE (x);
7819 const char *fmt = GET_RTX_FORMAT (code);
7820 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7823 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7824 else if (fmt[i] == 'E')
7826 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7827 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7834 if (spill_reg_order[REGNO (x)] < 0)
7837 /* Scan backwards for the insn that sets x. This might be a way back due
7839 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7841 code = GET_CODE (prev);
7842 if (code == CODE_LABEL || code == JUMP_INSN)
7846 if (reg_set_p (x, PATTERN (prev)))
7848 if (reg_referenced_p (x, PATTERN (prev)))
7851 if (! prev || INSN_UID (prev) < reload_first_uid)
7853 /* Check that PREV only sets the reload register. */
7854 set = single_set (prev);
7857 dst = SET_DEST (set);
7858 if (GET_CODE (dst) != REG
7859 || ! rtx_equal_p (dst, x))
7861 if (! reg_set_p (dst, PATTERN (dead_insn)))
7863 /* Check if DST was used in a later insn -
7864 it might have been inherited. */
7865 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7867 if (GET_CODE (i2) == CODE_LABEL)
7871 if (reg_referenced_p (dst, PATTERN (i2)))
7873 /* If there is a reference to the register in the current insn,
7874 it might be loaded in a non-inherited reload. If no other
7875 reload uses it, that means the register is set before
7877 if (i2 == current_insn)
7879 for (j = n_reloads - 1; j >= 0; j--)
7880 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7881 || reload_override_in[j] == dst)
7883 for (j = n_reloads - 1; j >= 0; j--)
7884 if (rld[j].in && rld[j].reg_rtx == dst)
7891 if (GET_CODE (i2) == JUMP_INSN)
7893 /* If DST is still live at CURRENT_INSN, check if it is used for
7894 any reload. Note that even if CURRENT_INSN sets DST, we still
7895 have to check the reloads. */
7896 if (i2 == current_insn)
7898 for (j = n_reloads - 1; j >= 0; j--)
7899 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7900 || reload_override_in[j] == dst)
7902 /* ??? We can't finish the loop here, because dst might be
7903 allocated to a pseudo in this block if no reload in this
7904 block needs any of the classes containing DST - see
7905 spill_hard_reg. There is no easy way to tell this, so we
7906 have to scan till the end of the basic block. */
7908 if (reg_set_p (dst, PATTERN (i2)))
7912 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7913 reg_reloaded_contents[REGNO (dst)] = -1;
7917 /* Output reload-insns to reload VALUE into RELOADREG.
7918 VALUE is an autoincrement or autodecrement RTX whose operand
7919 is a register or memory location;
7920 so reloading involves incrementing that location.
7921 IN is either identical to VALUE, or some cheaper place to reload from.
7923 INC_AMOUNT is the number to increment or decrement by (always positive).
7924 This cannot be deduced from VALUE.
7926 Return the instruction that stores into RELOADREG. */
7929 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
7931 /* REG or MEM to be copied and incremented. */
7932 rtx incloc = XEXP (value, 0);
7933 /* Nonzero if increment after copying. */
7934 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7940 rtx real_in = in == value ? XEXP (in, 0) : in;
7942 /* No hard register is equivalent to this register after
7943 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7944 we could inc/dec that register as well (maybe even using it for
7945 the source), but I'm not sure it's worth worrying about. */
7946 if (GET_CODE (incloc) == REG)
7947 reg_last_reload_reg[REGNO (incloc)] = 0;
7949 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7950 inc_amount = -inc_amount;
7952 inc = GEN_INT (inc_amount);
7954 /* If this is post-increment, first copy the location to the reload reg. */
7955 if (post && real_in != reloadreg)
7956 emit_insn (gen_move_insn (reloadreg, real_in));
7960 /* See if we can directly increment INCLOC. Use a method similar to
7961 that in gen_reload. */
7963 last = get_last_insn ();
7964 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7965 gen_rtx_PLUS (GET_MODE (incloc),
7968 code = recog_memoized (add_insn);
7971 extract_insn (add_insn);
7972 if (constrain_operands (1))
7974 /* If this is a pre-increment and we have incremented the value
7975 where it lives, copy the incremented value to RELOADREG to
7976 be used as an address. */
7979 emit_insn (gen_move_insn (reloadreg, incloc));
7984 delete_insns_since (last);
7987 /* If couldn't do the increment directly, must increment in RELOADREG.
7988 The way we do this depends on whether this is pre- or post-increment.
7989 For pre-increment, copy INCLOC to the reload register, increment it
7990 there, then save back. */
7994 if (in != reloadreg)
7995 emit_insn (gen_move_insn (reloadreg, real_in));
7996 emit_insn (gen_add2_insn (reloadreg, inc));
7997 store = emit_insn (gen_move_insn (incloc, reloadreg));
8002 Because this might be a jump insn or a compare, and because RELOADREG
8003 may not be available after the insn in an input reload, we must do
8004 the incrementation before the insn being reloaded for.
8006 We have already copied IN to RELOADREG. Increment the copy in
8007 RELOADREG, save that back, then decrement RELOADREG so it has
8008 the original value. */
8010 emit_insn (gen_add2_insn (reloadreg, inc));
8011 store = emit_insn (gen_move_insn (incloc, reloadreg));
8012 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8020 add_auto_inc_notes (rtx insn, rtx x)
8022 enum rtx_code code = GET_CODE (x);
8026 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8029 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8033 /* Scan all the operand sub-expressions. */
8034 fmt = GET_RTX_FORMAT (code);
8035 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8038 add_auto_inc_notes (insn, XEXP (x, i));
8039 else if (fmt[i] == 'E')
8040 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8041 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8046 /* Copy EH notes from an insn to its reloads. */
8048 copy_eh_notes (rtx insn, rtx x)
8050 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8053 for (; x != 0; x = NEXT_INSN (x))
8055 if (may_trap_p (PATTERN (x)))
8057 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8063 /* This is used by reload pass, that does emit some instructions after
8064 abnormal calls moving basic block end, but in fact it wants to emit
8065 them on the edge. Looks for abnormal call edges, find backward the
8066 proper call and fix the damage.
8068 Similar handle instructions throwing exceptions internally. */
8070 fixup_abnormal_edges (void)
8072 bool inserted = false;
8079 /* Look for cases we are interested in - calls or instructions causing
8081 for (e = bb->succ; e; e = e->succ_next)
8083 if (e->flags & EDGE_ABNORMAL_CALL)
8085 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8086 == (EDGE_ABNORMAL | EDGE_EH))
8089 if (e && GET_CODE (BB_END (bb)) != CALL_INSN
8090 && !can_throw_internal (BB_END (bb)))
8092 rtx insn = BB_END (bb), stop = NEXT_INSN (BB_END (bb));
8094 for (e = bb->succ; e; e = e->succ_next)
8095 if (e->flags & EDGE_FALLTHRU)
8097 /* Get past the new insns generated. Allow notes, as the insns may
8098 be already deleted. */
8099 while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE)
8100 && !can_throw_internal (insn)
8101 && insn != BB_HEAD (bb))
8102 insn = PREV_INSN (insn);
8103 if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn))
8107 insn = NEXT_INSN (insn);
8108 while (insn && insn != stop)
8110 next = NEXT_INSN (insn);
8115 /* Sometimes there's still the return value USE.
8116 If it's placed after a trapping call (i.e. that
8117 call is the last insn anyway), we have no fallthru
8118 edge. Simply delete this use and don't try to insert
8119 on the non-existent edge. */
8120 if (GET_CODE (PATTERN (insn)) != USE)
8122 /* We're not deleting it, we're moving it. */
8123 INSN_DELETED_P (insn) = 0;
8124 PREV_INSN (insn) = NULL_RTX;
8125 NEXT_INSN (insn) = NULL_RTX;
8127 insert_insn_on_edge (insn, e);
8134 /* We've possibly turned single trapping insn into multiple ones. */
8135 if (flag_non_call_exceptions)
8138 blocks = sbitmap_alloc (last_basic_block);
8139 sbitmap_ones (blocks);
8140 find_many_sub_basic_blocks (blocks);
8143 commit_edge_insertions ();
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