1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "addresses.h"
39 #include "basic-block.h"
51 /* This file contains the reload pass of the compiler, which is
52 run after register allocation has been done. It checks that
53 each insn is valid (operands required to be in registers really
54 are in registers of the proper class) and fixes up invalid ones
55 by copying values temporarily into registers for the insns
58 The results of register allocation are described by the vector
59 reg_renumber; the insns still contain pseudo regs, but reg_renumber
60 can be used to find which hard reg, if any, a pseudo reg is in.
62 The technique we always use is to free up a few hard regs that are
63 called ``reload regs'', and for each place where a pseudo reg
64 must be in a hard reg, copy it temporarily into one of the reload regs.
66 Reload regs are allocated locally for every instruction that needs
67 reloads. When there are pseudos which are allocated to a register that
68 has been chosen as a reload reg, such pseudos must be ``spilled''.
69 This means that they go to other hard regs, or to stack slots if no other
70 available hard regs can be found. Spilling can invalidate more
71 insns, requiring additional need for reloads, so we must keep checking
72 until the process stabilizes.
74 For machines with different classes of registers, we must keep track
75 of the register class needed for each reload, and make sure that
76 we allocate enough reload registers of each class.
78 The file reload.c contains the code that checks one insn for
79 validity and reports the reloads that it needs. This file
80 is in charge of scanning the entire rtl code, accumulating the
81 reload needs, spilling, assigning reload registers to use for
82 fixing up each insn, and generating the new insns to copy values
83 into the reload registers. */
85 /* During reload_as_needed, element N contains a REG rtx for the hard reg
86 into which reg N has been reloaded (perhaps for a previous insn). */
87 static rtx *reg_last_reload_reg;
89 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
90 for an output reload that stores into reg N. */
91 static regset_head reg_has_output_reload;
93 /* Indicates which hard regs are reload-registers for an output reload
94 in the current insn. */
95 static HARD_REG_SET reg_is_output_reload;
97 /* Element N is the constant value to which pseudo reg N is equivalent,
98 or zero if pseudo reg N is not equivalent to a constant.
99 find_reloads looks at this in order to replace pseudo reg N
100 with the constant it stands for. */
101 rtx *reg_equiv_constant;
103 /* Element N is an invariant value to which pseudo reg N is equivalent.
104 eliminate_regs_in_insn uses this to replace pseudos in particular
106 rtx *reg_equiv_invariant;
108 /* Element N is a memory location to which pseudo reg N is equivalent,
109 prior to any register elimination (such as frame pointer to stack
110 pointer). Depending on whether or not it is a valid address, this value
111 is transferred to either reg_equiv_address or reg_equiv_mem. */
112 rtx *reg_equiv_memory_loc;
114 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
115 collector can keep track of what is inside. */
116 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
118 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
119 This is used when the address is not valid as a memory address
120 (because its displacement is too big for the machine.) */
121 rtx *reg_equiv_address;
123 /* Element N is the memory slot to which pseudo reg N is equivalent,
124 or zero if pseudo reg N is not equivalent to a memory slot. */
127 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
128 alternate representations of the location of pseudo reg N. */
129 rtx *reg_equiv_alt_mem_list;
131 /* Widest width in which each pseudo reg is referred to (via subreg). */
132 static unsigned int *reg_max_ref_width;
134 /* Element N is the list of insns that initialized reg N from its equivalent
135 constant or memory slot. */
137 int reg_equiv_init_size;
139 /* Vector to remember old contents of reg_renumber before spilling. */
140 static short *reg_old_renumber;
142 /* During reload_as_needed, element N contains the last pseudo regno reloaded
143 into hard register N. If that pseudo reg occupied more than one register,
144 reg_reloaded_contents points to that pseudo for each spill register in
145 use; all of these must remain set for an inheritance to occur. */
146 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
148 /* During reload_as_needed, element N contains the insn for which
149 hard register N was last used. Its contents are significant only
150 when reg_reloaded_valid is set for this register. */
151 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
153 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
154 static HARD_REG_SET reg_reloaded_valid;
155 /* Indicate if the register was dead at the end of the reload.
156 This is only valid if reg_reloaded_contents is set and valid. */
157 static HARD_REG_SET reg_reloaded_dead;
159 /* Indicate whether the register's current value is one that is not
160 safe to retain across a call, even for registers that are normally
162 static HARD_REG_SET reg_reloaded_call_part_clobbered;
164 /* Number of spill-regs so far; number of valid elements of spill_regs. */
167 /* In parallel with spill_regs, contains REG rtx's for those regs.
168 Holds the last rtx used for any given reg, or 0 if it has never
169 been used for spilling yet. This rtx is reused, provided it has
171 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
173 /* In parallel with spill_regs, contains nonzero for a spill reg
174 that was stored after the last time it was used.
175 The precise value is the insn generated to do the store. */
176 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
178 /* This is the register that was stored with spill_reg_store. This is a
179 copy of reload_out / reload_out_reg when the value was stored; if
180 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
181 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
183 /* This table is the inverse mapping of spill_regs:
184 indexed by hard reg number,
185 it contains the position of that reg in spill_regs,
186 or -1 for something that is not in spill_regs.
188 ?!? This is no longer accurate. */
189 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
191 /* This reg set indicates registers that can't be used as spill registers for
192 the currently processed insn. These are the hard registers which are live
193 during the insn, but not allocated to pseudos, as well as fixed
195 static HARD_REG_SET bad_spill_regs;
197 /* These are the hard registers that can't be used as spill register for any
198 insn. This includes registers used for user variables and registers that
199 we can't eliminate. A register that appears in this set also can't be used
200 to retry register allocation. */
201 static HARD_REG_SET bad_spill_regs_global;
203 /* Describes order of use of registers for reloading
204 of spilled pseudo-registers. `n_spills' is the number of
205 elements that are actually valid; new ones are added at the end.
207 Both spill_regs and spill_reg_order are used on two occasions:
208 once during find_reload_regs, where they keep track of the spill registers
209 for a single insn, but also during reload_as_needed where they show all
210 the registers ever used by reload. For the latter case, the information
211 is calculated during finish_spills. */
212 static short spill_regs[FIRST_PSEUDO_REGISTER];
214 /* This vector of reg sets indicates, for each pseudo, which hard registers
215 may not be used for retrying global allocation because the register was
216 formerly spilled from one of them. If we allowed reallocating a pseudo to
217 a register that it was already allocated to, reload might not
219 static HARD_REG_SET *pseudo_previous_regs;
221 /* This vector of reg sets indicates, for each pseudo, which hard
222 registers may not be used for retrying global allocation because they
223 are used as spill registers during one of the insns in which the
225 static HARD_REG_SET *pseudo_forbidden_regs;
227 /* All hard regs that have been used as spill registers for any insn are
228 marked in this set. */
229 static HARD_REG_SET used_spill_regs;
231 /* Index of last register assigned as a spill register. We allocate in
232 a round-robin fashion. */
233 static int last_spill_reg;
235 /* Nonzero if indirect addressing is supported on the machine; this means
236 that spilling (REG n) does not require reloading it into a register in
237 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
238 value indicates the level of indirect addressing supported, e.g., two
239 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
241 static char spill_indirect_levels;
243 /* Nonzero if indirect addressing is supported when the innermost MEM is
244 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
245 which these are valid is the same as spill_indirect_levels, above. */
246 char indirect_symref_ok;
248 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
249 char double_reg_address_ok;
251 /* Record the stack slot for each spilled hard register. */
252 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
254 /* Width allocated so far for that stack slot. */
255 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
257 /* Record which pseudos needed to be spilled. */
258 static regset_head spilled_pseudos;
260 /* Used for communication between order_regs_for_reload and count_pseudo.
261 Used to avoid counting one pseudo twice. */
262 static regset_head pseudos_counted;
264 /* First uid used by insns created by reload in this function.
265 Used in find_equiv_reg. */
266 int reload_first_uid;
268 /* Flag set by local-alloc or global-alloc if anything is live in
269 a call-clobbered reg across calls. */
270 int caller_save_needed;
272 /* Set to 1 while reload_as_needed is operating.
273 Required by some machines to handle any generated moves differently. */
274 int reload_in_progress = 0;
276 /* These arrays record the insn_code of insns that may be needed to
277 perform input and output reloads of special objects. They provide a
278 place to pass a scratch register. */
279 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
280 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
282 /* This obstack is used for allocation of rtl during register elimination.
283 The allocated storage can be freed once find_reloads has processed the
285 static struct obstack reload_obstack;
287 /* Points to the beginning of the reload_obstack. All insn_chain structures
288 are allocated first. */
289 static char *reload_startobj;
291 /* The point after all insn_chain structures. Used to quickly deallocate
292 memory allocated in copy_reloads during calculate_needs_all_insns. */
293 static char *reload_firstobj;
295 /* This points before all local rtl generated by register elimination.
296 Used to quickly free all memory after processing one insn. */
297 static char *reload_insn_firstobj;
299 /* List of insn_chain instructions, one for every insn that reload needs to
301 struct insn_chain *reload_insn_chain;
303 /* List of all insns needing reloads. */
304 static struct insn_chain *insns_need_reload;
306 /* This structure is used to record information about register eliminations.
307 Each array entry describes one possible way of eliminating a register
308 in favor of another. If there is more than one way of eliminating a
309 particular register, the most preferred should be specified first. */
313 int from; /* Register number to be eliminated. */
314 int to; /* Register number used as replacement. */
315 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
316 int can_eliminate; /* Nonzero if this elimination can be done. */
317 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
318 insns made by reload. */
319 HOST_WIDE_INT offset; /* Current offset between the two regs. */
320 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
321 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
322 rtx from_rtx; /* REG rtx for the register to be eliminated.
323 We cannot simply compare the number since
324 we might then spuriously replace a hard
325 register corresponding to a pseudo
326 assigned to the reg to be eliminated. */
327 rtx to_rtx; /* REG rtx for the replacement. */
330 static struct elim_table *reg_eliminate = 0;
332 /* This is an intermediate structure to initialize the table. It has
333 exactly the members provided by ELIMINABLE_REGS. */
334 static const struct elim_table_1
338 } reg_eliminate_1[] =
340 /* If a set of eliminable registers was specified, define the table from it.
341 Otherwise, default to the normal case of the frame pointer being
342 replaced by the stack pointer. */
344 #ifdef ELIMINABLE_REGS
347 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
350 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
352 /* Record the number of pending eliminations that have an offset not equal
353 to their initial offset. If nonzero, we use a new copy of each
354 replacement result in any insns encountered. */
355 int num_not_at_initial_offset;
357 /* Count the number of registers that we may be able to eliminate. */
358 static int num_eliminable;
359 /* And the number of registers that are equivalent to a constant that
360 can be eliminated to frame_pointer / arg_pointer + constant. */
361 static int num_eliminable_invariants;
363 /* For each label, we record the offset of each elimination. If we reach
364 a label by more than one path and an offset differs, we cannot do the
365 elimination. This information is indexed by the difference of the
366 number of the label and the first label number. We can't offset the
367 pointer itself as this can cause problems on machines with segmented
368 memory. The first table is an array of flags that records whether we
369 have yet encountered a label and the second table is an array of arrays,
370 one entry in the latter array for each elimination. */
372 static int first_label_num;
373 static char *offsets_known_at;
374 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
376 /* Number of labels in the current function. */
378 static int num_labels;
380 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
381 static void maybe_fix_stack_asms (void);
382 static void copy_reloads (struct insn_chain *);
383 static void calculate_needs_all_insns (int);
384 static int find_reg (struct insn_chain *, int);
385 static void find_reload_regs (struct insn_chain *);
386 static void select_reload_regs (void);
387 static void delete_caller_save_insns (void);
389 static void spill_failure (rtx, enum reg_class);
390 static void count_spilled_pseudo (int, int, int);
391 static void delete_dead_insn (rtx);
392 static void alter_reg (int, int);
393 static void set_label_offsets (rtx, rtx, int);
394 static void check_eliminable_occurrences (rtx);
395 static void elimination_effects (rtx, enum machine_mode);
396 static int eliminate_regs_in_insn (rtx, int);
397 static void update_eliminable_offsets (void);
398 static void mark_not_eliminable (rtx, const_rtx, void *);
399 static void set_initial_elim_offsets (void);
400 static bool verify_initial_elim_offsets (void);
401 static void set_initial_label_offsets (void);
402 static void set_offsets_for_label (rtx);
403 static void init_elim_table (void);
404 static void update_eliminables (HARD_REG_SET *);
405 static void spill_hard_reg (unsigned int, int);
406 static int finish_spills (int);
407 static void scan_paradoxical_subregs (rtx);
408 static void count_pseudo (int);
409 static void order_regs_for_reload (struct insn_chain *);
410 static void reload_as_needed (int);
411 static void forget_old_reloads_1 (rtx, const_rtx, void *);
412 static void forget_marked_reloads (regset);
413 static int reload_reg_class_lower (const void *, const void *);
414 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
416 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
418 static int reload_reg_free_p (unsigned int, int, enum reload_type);
419 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
421 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
423 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
424 static int allocate_reload_reg (struct insn_chain *, int, int);
425 static int conflicts_with_override (rtx);
426 static void failed_reload (rtx, int);
427 static int set_reload_reg (int, int);
428 static void choose_reload_regs_init (struct insn_chain *, rtx *);
429 static void choose_reload_regs (struct insn_chain *);
430 static void merge_assigned_reloads (rtx);
431 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
433 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
435 static void do_input_reload (struct insn_chain *, struct reload *, int);
436 static void do_output_reload (struct insn_chain *, struct reload *, int);
437 static bool inherit_piecemeal_p (int, int);
438 static void emit_reload_insns (struct insn_chain *);
439 static void delete_output_reload (rtx, int, int);
440 static void delete_address_reloads (rtx, rtx);
441 static void delete_address_reloads_1 (rtx, rtx, rtx);
442 static rtx inc_for_reload (rtx, rtx, rtx, int);
444 static void add_auto_inc_notes (rtx, rtx);
446 static void copy_eh_notes (rtx, rtx);
447 static int reloads_conflict (int, int);
448 static rtx gen_reload (rtx, rtx, int, enum reload_type);
449 static rtx emit_insn_if_valid_for_reload (rtx);
451 /* Initialize the reload pass once per compilation. */
458 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
459 Set spill_indirect_levels to the number of levels such addressing is
460 permitted, zero if it is not permitted at all. */
463 = gen_rtx_MEM (Pmode,
466 LAST_VIRTUAL_REGISTER + 1),
468 spill_indirect_levels = 0;
470 while (memory_address_p (QImode, tem))
472 spill_indirect_levels++;
473 tem = gen_rtx_MEM (Pmode, tem);
476 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
478 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
479 indirect_symref_ok = memory_address_p (QImode, tem);
481 /* See if reg+reg is a valid (and offsettable) address. */
483 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
485 tem = gen_rtx_PLUS (Pmode,
486 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
487 gen_rtx_REG (Pmode, i));
489 /* This way, we make sure that reg+reg is an offsettable address. */
490 tem = plus_constant (tem, 4);
492 if (memory_address_p (QImode, tem))
494 double_reg_address_ok = 1;
499 /* Initialize obstack for our rtl allocation. */
500 gcc_obstack_init (&reload_obstack);
501 reload_startobj = obstack_alloc (&reload_obstack, 0);
503 INIT_REG_SET (&spilled_pseudos);
504 INIT_REG_SET (&pseudos_counted);
507 /* List of insn chains that are currently unused. */
508 static struct insn_chain *unused_insn_chains = 0;
510 /* Allocate an empty insn_chain structure. */
512 new_insn_chain (void)
514 struct insn_chain *c;
516 if (unused_insn_chains == 0)
518 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
519 INIT_REG_SET (&c->live_throughout);
520 INIT_REG_SET (&c->dead_or_set);
524 c = unused_insn_chains;
525 unused_insn_chains = c->next;
527 c->is_caller_save_insn = 0;
528 c->need_operand_change = 0;
534 /* Small utility function to set all regs in hard reg set TO which are
535 allocated to pseudos in regset FROM. */
538 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
541 reg_set_iterator rsi;
543 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
545 int r = reg_renumber[regno];
549 /* reload_combine uses the information from
550 DF_RA_LIVE_IN (BASIC_BLOCK), which might still
551 contain registers that have not actually been allocated
552 since they have an equivalence. */
553 gcc_assert (reload_completed);
556 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
560 /* Replace all pseudos found in LOC with their corresponding
564 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
577 unsigned int regno = REGNO (x);
579 if (regno < FIRST_PSEUDO_REGISTER)
582 x = eliminate_regs (x, mem_mode, usage);
586 replace_pseudos_in (loc, mem_mode, usage);
590 if (reg_equiv_constant[regno])
591 *loc = reg_equiv_constant[regno];
592 else if (reg_equiv_mem[regno])
593 *loc = reg_equiv_mem[regno];
594 else if (reg_equiv_address[regno])
595 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
598 gcc_assert (!REG_P (regno_reg_rtx[regno])
599 || REGNO (regno_reg_rtx[regno]) != regno);
600 *loc = regno_reg_rtx[regno];
605 else if (code == MEM)
607 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
611 /* Process each of our operands recursively. */
612 fmt = GET_RTX_FORMAT (code);
613 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
615 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
616 else if (*fmt == 'E')
617 for (j = 0; j < XVECLEN (x, i); j++)
618 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
621 /* Determine if the current function has an exception receiver block
622 that reaches the exit block via non-exceptional edges */
625 has_nonexceptional_receiver (void)
629 basic_block *tos, *worklist, bb;
631 /* If we're not optimizing, then just err on the safe side. */
635 /* First determine which blocks can reach exit via normal paths. */
636 tos = worklist = xmalloc (sizeof (basic_block) * (n_basic_blocks + 1));
639 bb->flags &= ~BB_REACHABLE;
641 /* Place the exit block on our worklist. */
642 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
643 *tos++ = EXIT_BLOCK_PTR;
645 /* Iterate: find everything reachable from what we've already seen. */
646 while (tos != worklist)
650 FOR_EACH_EDGE (e, ei, bb->preds)
651 if (!(e->flags & EDGE_ABNORMAL))
653 basic_block src = e->src;
655 if (!(src->flags & BB_REACHABLE))
657 src->flags |= BB_REACHABLE;
664 /* Now see if there's a reachable block with an exceptional incoming
667 if (bb->flags & BB_REACHABLE)
668 FOR_EACH_EDGE (e, ei, bb->preds)
669 if (e->flags & EDGE_ABNORMAL)
672 /* No exceptional block reached exit unexceptionally. */
677 /* Global variables used by reload and its subroutines. */
679 /* Set during calculate_needs if an insn needs register elimination. */
680 static int something_needs_elimination;
681 /* Set during calculate_needs if an insn needs an operand changed. */
682 static int something_needs_operands_changed;
684 /* Nonzero means we couldn't get enough spill regs. */
687 /* Main entry point for the reload pass.
689 FIRST is the first insn of the function being compiled.
691 GLOBAL nonzero means we were called from global_alloc
692 and should attempt to reallocate any pseudoregs that we
693 displace from hard regs we will use for reloads.
694 If GLOBAL is zero, we do not have enough information to do that,
695 so any pseudo reg that is spilled must go to the stack.
697 Return value is nonzero if reload failed
698 and we must not do any more for this function. */
701 reload (rtx first, int global)
705 struct elim_table *ep;
708 /* Make sure even insns with volatile mem refs are recognizable. */
713 reload_firstobj = obstack_alloc (&reload_obstack, 0);
715 /* Make sure that the last insn in the chain
716 is not something that needs reloading. */
717 emit_note (NOTE_INSN_DELETED);
719 /* Enable find_equiv_reg to distinguish insns made by reload. */
720 reload_first_uid = get_max_uid ();
722 #ifdef SECONDARY_MEMORY_NEEDED
723 /* Initialize the secondary memory table. */
724 clear_secondary_mem ();
727 /* We don't have a stack slot for any spill reg yet. */
728 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
729 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
731 /* Initialize the save area information for caller-save, in case some
735 /* Compute which hard registers are now in use
736 as homes for pseudo registers.
737 This is done here rather than (eg) in global_alloc
738 because this point is reached even if not optimizing. */
739 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
742 /* A function that has a nonlocal label that can reach the exit
743 block via non-exceptional paths must save all call-saved
745 if (current_function_calls_unwind_init
746 || (current_function_has_nonlocal_label
747 && has_nonexceptional_receiver ()))
748 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
749 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
750 df_set_regs_ever_live (i, true);
752 /* Find all the pseudo registers that didn't get hard regs
753 but do have known equivalent constants or memory slots.
754 These include parameters (known equivalent to parameter slots)
755 and cse'd or loop-moved constant memory addresses.
757 Record constant equivalents in reg_equiv_constant
758 so they will be substituted by find_reloads.
759 Record memory equivalents in reg_mem_equiv so they can
760 be substituted eventually by altering the REG-rtx's. */
762 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
763 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
764 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
765 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
766 reg_equiv_address = XCNEWVEC (rtx, max_regno);
767 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
768 reg_old_renumber = XCNEWVEC (short, max_regno);
769 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
770 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
771 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
773 CLEAR_HARD_REG_SET (bad_spill_regs_global);
775 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
776 to. Also find all paradoxical subregs and find largest such for
779 num_eliminable_invariants = 0;
780 for (insn = first; insn; insn = NEXT_INSN (insn))
782 rtx set = single_set (insn);
784 /* We may introduce USEs that we want to remove at the end, so
785 we'll mark them with QImode. Make sure there are no
786 previously-marked insns left by say regmove. */
787 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
788 && GET_MODE (insn) != VOIDmode)
789 PUT_MODE (insn, VOIDmode);
792 scan_paradoxical_subregs (PATTERN (insn));
794 if (set != 0 && REG_P (SET_DEST (set)))
796 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
802 i = REGNO (SET_DEST (set));
805 if (i <= LAST_VIRTUAL_REGISTER)
808 if (! function_invariant_p (x)
810 /* A function invariant is often CONSTANT_P but may
811 include a register. We promise to only pass
812 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
814 && LEGITIMATE_PIC_OPERAND_P (x)))
816 /* It can happen that a REG_EQUIV note contains a MEM
817 that is not a legitimate memory operand. As later
818 stages of reload assume that all addresses found
819 in the reg_equiv_* arrays were originally legitimate,
820 we ignore such REG_EQUIV notes. */
821 if (memory_operand (x, VOIDmode))
823 /* Always unshare the equivalence, so we can
824 substitute into this insn without touching the
826 reg_equiv_memory_loc[i] = copy_rtx (x);
828 else if (function_invariant_p (x))
830 if (GET_CODE (x) == PLUS)
832 /* This is PLUS of frame pointer and a constant,
833 and might be shared. Unshare it. */
834 reg_equiv_invariant[i] = copy_rtx (x);
835 num_eliminable_invariants++;
837 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
839 reg_equiv_invariant[i] = x;
840 num_eliminable_invariants++;
842 else if (LEGITIMATE_CONSTANT_P (x))
843 reg_equiv_constant[i] = x;
846 reg_equiv_memory_loc[i]
847 = force_const_mem (GET_MODE (SET_DEST (set)), x);
848 if (! reg_equiv_memory_loc[i])
849 reg_equiv_init[i] = NULL_RTX;
854 reg_equiv_init[i] = NULL_RTX;
859 reg_equiv_init[i] = NULL_RTX;
864 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
865 if (reg_equiv_init[i])
867 fprintf (dump_file, "init_insns for %u: ", i);
868 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
869 fprintf (dump_file, "\n");
874 first_label_num = get_first_label_num ();
875 num_labels = max_label_num () - first_label_num;
877 /* Allocate the tables used to store offset information at labels. */
878 /* We used to use alloca here, but the size of what it would try to
879 allocate would occasionally cause it to exceed the stack limit and
880 cause a core dump. */
881 offsets_known_at = XNEWVEC (char, num_labels);
882 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
884 /* Alter each pseudo-reg rtx to contain its hard reg number.
885 Assign stack slots to the pseudos that lack hard regs or equivalents.
886 Do not touch virtual registers. */
888 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
891 /* If we have some registers we think can be eliminated, scan all insns to
892 see if there is an insn that sets one of these registers to something
893 other than itself plus a constant. If so, the register cannot be
894 eliminated. Doing this scan here eliminates an extra pass through the
895 main reload loop in the most common case where register elimination
897 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
899 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
901 maybe_fix_stack_asms ();
903 insns_need_reload = 0;
904 something_needs_elimination = 0;
906 /* Initialize to -1, which means take the first spill register. */
909 /* Spill any hard regs that we know we can't eliminate. */
910 CLEAR_HARD_REG_SET (used_spill_regs);
911 /* There can be multiple ways to eliminate a register;
912 they should be listed adjacently.
913 Elimination for any register fails only if all possible ways fail. */
914 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
917 int can_eliminate = 0;
920 can_eliminate |= ep->can_eliminate;
923 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
925 spill_hard_reg (from, 1);
928 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
929 if (frame_pointer_needed)
930 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
932 finish_spills (global);
934 /* From now on, we may need to generate moves differently. We may also
935 allow modifications of insns which cause them to not be recognized.
936 Any such modifications will be cleaned up during reload itself. */
937 reload_in_progress = 1;
939 /* This loop scans the entire function each go-round
940 and repeats until one repetition spills no additional hard regs. */
943 int something_changed;
945 HOST_WIDE_INT starting_frame_size;
947 starting_frame_size = get_frame_size ();
949 set_initial_elim_offsets ();
950 set_initial_label_offsets ();
952 /* For each pseudo register that has an equivalent location defined,
953 try to eliminate any eliminable registers (such as the frame pointer)
954 assuming initial offsets for the replacement register, which
957 If the resulting location is directly addressable, substitute
958 the MEM we just got directly for the old REG.
960 If it is not addressable but is a constant or the sum of a hard reg
961 and constant, it is probably not addressable because the constant is
962 out of range, in that case record the address; we will generate
963 hairy code to compute the address in a register each time it is
964 needed. Similarly if it is a hard register, but one that is not
965 valid as an address register.
967 If the location is not addressable, but does not have one of the
968 above forms, assign a stack slot. We have to do this to avoid the
969 potential of producing lots of reloads if, e.g., a location involves
970 a pseudo that didn't get a hard register and has an equivalent memory
971 location that also involves a pseudo that didn't get a hard register.
973 Perhaps at some point we will improve reload_when_needed handling
974 so this problem goes away. But that's very hairy. */
976 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
977 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
979 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
981 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
983 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
984 else if (CONSTANT_P (XEXP (x, 0))
985 || (REG_P (XEXP (x, 0))
986 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
987 || (GET_CODE (XEXP (x, 0)) == PLUS
988 && REG_P (XEXP (XEXP (x, 0), 0))
989 && (REGNO (XEXP (XEXP (x, 0), 0))
990 < FIRST_PSEUDO_REGISTER)
991 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
992 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
995 /* Make a new stack slot. Then indicate that something
996 changed so we go back and recompute offsets for
997 eliminable registers because the allocation of memory
998 below might change some offset. reg_equiv_{mem,address}
999 will be set up for this pseudo on the next pass around
1001 reg_equiv_memory_loc[i] = 0;
1002 reg_equiv_init[i] = 0;
1007 if (caller_save_needed)
1008 setup_save_areas ();
1010 /* If we allocated another stack slot, redo elimination bookkeeping. */
1011 if (starting_frame_size != get_frame_size ())
1013 if (starting_frame_size && cfun->stack_alignment_needed)
1015 /* If we have a stack frame, we must align it now. The
1016 stack size may be a part of the offset computation for
1017 register elimination. So if this changes the stack size,
1018 then repeat the elimination bookkeeping. We don't
1019 realign when there is no stack, as that will cause a
1020 stack frame when none is needed should
1021 STARTING_FRAME_OFFSET not be already aligned to
1023 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
1024 if (starting_frame_size != get_frame_size ())
1028 if (caller_save_needed)
1030 save_call_clobbered_regs ();
1031 /* That might have allocated new insn_chain structures. */
1032 reload_firstobj = obstack_alloc (&reload_obstack, 0);
1035 calculate_needs_all_insns (global);
1037 CLEAR_REG_SET (&spilled_pseudos);
1040 something_changed = 0;
1042 /* If we allocated any new memory locations, make another pass
1043 since it might have changed elimination offsets. */
1044 if (starting_frame_size != get_frame_size ())
1045 something_changed = 1;
1047 /* Even if the frame size remained the same, we might still have
1048 changed elimination offsets, e.g. if find_reloads called
1049 force_const_mem requiring the back end to allocate a constant
1050 pool base register that needs to be saved on the stack. */
1051 else if (!verify_initial_elim_offsets ())
1052 something_changed = 1;
1055 HARD_REG_SET to_spill;
1056 CLEAR_HARD_REG_SET (to_spill);
1057 update_eliminables (&to_spill);
1058 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
1060 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1061 if (TEST_HARD_REG_BIT (to_spill, i))
1063 spill_hard_reg (i, 1);
1066 /* Regardless of the state of spills, if we previously had
1067 a register that we thought we could eliminate, but now can
1068 not eliminate, we must run another pass.
1070 Consider pseudos which have an entry in reg_equiv_* which
1071 reference an eliminable register. We must make another pass
1072 to update reg_equiv_* so that we do not substitute in the
1073 old value from when we thought the elimination could be
1075 something_changed = 1;
1079 select_reload_regs ();
1083 if (insns_need_reload != 0 || did_spill)
1084 something_changed |= finish_spills (global);
1086 if (! something_changed)
1089 if (caller_save_needed)
1090 delete_caller_save_insns ();
1092 obstack_free (&reload_obstack, reload_firstobj);
1095 /* If global-alloc was run, notify it of any register eliminations we have
1098 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1099 if (ep->can_eliminate)
1100 mark_elimination (ep->from, ep->to);
1102 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1103 If that insn didn't set the register (i.e., it copied the register to
1104 memory), just delete that insn instead of the equivalencing insn plus
1105 anything now dead. If we call delete_dead_insn on that insn, we may
1106 delete the insn that actually sets the register if the register dies
1107 there and that is incorrect. */
1109 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1111 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1114 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1116 rtx equiv_insn = XEXP (list, 0);
1118 /* If we already deleted the insn or if it may trap, we can't
1119 delete it. The latter case shouldn't happen, but can
1120 if an insn has a variable address, gets a REG_EH_REGION
1121 note added to it, and then gets converted into a load
1122 from a constant address. */
1123 if (NOTE_P (equiv_insn)
1124 || can_throw_internal (equiv_insn))
1126 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1127 delete_dead_insn (equiv_insn);
1129 SET_INSN_DELETED (equiv_insn);
1134 /* Use the reload registers where necessary
1135 by generating move instructions to move the must-be-register
1136 values into or out of the reload registers. */
1138 if (insns_need_reload != 0 || something_needs_elimination
1139 || something_needs_operands_changed)
1141 HOST_WIDE_INT old_frame_size = get_frame_size ();
1143 reload_as_needed (global);
1145 gcc_assert (old_frame_size == get_frame_size ());
1147 gcc_assert (verify_initial_elim_offsets ());
1150 /* If we were able to eliminate the frame pointer, show that it is no
1151 longer live at the start of any basic block. If it ls live by
1152 virtue of being in a pseudo, that pseudo will be marked live
1153 and hence the frame pointer will be known to be live via that
1156 if (! frame_pointer_needed)
1159 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1160 bitmap_clear_bit (df_get_live_top (bb), HARD_FRAME_POINTER_REGNUM);
1163 /* Come here (with failure set nonzero) if we can't get enough spill
1167 CLEAR_REG_SET (&spilled_pseudos);
1168 reload_in_progress = 0;
1170 /* Now eliminate all pseudo regs by modifying them into
1171 their equivalent memory references.
1172 The REG-rtx's for the pseudos are modified in place,
1173 so all insns that used to refer to them now refer to memory.
1175 For a reg that has a reg_equiv_address, all those insns
1176 were changed by reloading so that no insns refer to it any longer;
1177 but the DECL_RTL of a variable decl may refer to it,
1178 and if so this causes the debugging info to mention the variable. */
1180 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1184 if (reg_equiv_mem[i])
1185 addr = XEXP (reg_equiv_mem[i], 0);
1187 if (reg_equiv_address[i])
1188 addr = reg_equiv_address[i];
1192 if (reg_renumber[i] < 0)
1194 rtx reg = regno_reg_rtx[i];
1196 REG_USERVAR_P (reg) = 0;
1197 PUT_CODE (reg, MEM);
1198 XEXP (reg, 0) = addr;
1199 if (reg_equiv_memory_loc[i])
1200 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1203 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1204 MEM_ATTRS (reg) = 0;
1206 MEM_NOTRAP_P (reg) = 1;
1208 else if (reg_equiv_mem[i])
1209 XEXP (reg_equiv_mem[i], 0) = addr;
1213 /* We must set reload_completed now since the cleanup_subreg_operands call
1214 below will re-recognize each insn and reload may have generated insns
1215 which are only valid during and after reload. */
1216 reload_completed = 1;
1218 /* Make a pass over all the insns and delete all USEs which we inserted
1219 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1220 notes. Delete all CLOBBER insns, except those that refer to the return
1221 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1222 from misarranging variable-array code, and simplify (subreg (reg))
1223 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1224 are no longer useful or accurate. Strip and regenerate REG_INC notes
1225 that may have been moved around. */
1227 for (insn = first; insn; insn = NEXT_INSN (insn))
1233 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1234 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1236 if ((GET_CODE (PATTERN (insn)) == USE
1237 /* We mark with QImode USEs introduced by reload itself. */
1238 && (GET_MODE (insn) == QImode
1239 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1240 || (GET_CODE (PATTERN (insn)) == CLOBBER
1241 && (!MEM_P (XEXP (PATTERN (insn), 0))
1242 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1243 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1244 && XEXP (XEXP (PATTERN (insn), 0), 0)
1245 != stack_pointer_rtx))
1246 && (!REG_P (XEXP (PATTERN (insn), 0))
1247 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1253 /* Some CLOBBERs may survive until here and still reference unassigned
1254 pseudos with const equivalent, which may in turn cause ICE in later
1255 passes if the reference remains in place. */
1256 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1257 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1258 VOIDmode, PATTERN (insn));
1260 /* Discard obvious no-ops, even without -O. This optimization
1261 is fast and doesn't interfere with debugging. */
1262 if (NONJUMP_INSN_P (insn)
1263 && GET_CODE (PATTERN (insn)) == SET
1264 && REG_P (SET_SRC (PATTERN (insn)))
1265 && REG_P (SET_DEST (PATTERN (insn)))
1266 && (REGNO (SET_SRC (PATTERN (insn)))
1267 == REGNO (SET_DEST (PATTERN (insn)))))
1273 pnote = ®_NOTES (insn);
1276 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1277 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1278 || REG_NOTE_KIND (*pnote) == REG_INC
1279 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1280 || REG_NOTE_KIND (*pnote) == REG_LIBCALL_ID
1281 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1282 *pnote = XEXP (*pnote, 1);
1284 pnote = &XEXP (*pnote, 1);
1288 add_auto_inc_notes (insn, PATTERN (insn));
1291 /* Simplify (subreg (reg)) if it appears as an operand. */
1292 cleanup_subreg_operands (insn);
1294 /* Clean up invalid ASMs so that they don't confuse later passes.
1296 if (asm_noperands (PATTERN (insn)) >= 0)
1298 extract_insn (insn);
1299 if (!constrain_operands (1))
1301 error_for_asm (insn,
1302 "%<asm%> operand has impossible constraints");
1309 /* If we are doing stack checking, give a warning if this function's
1310 frame size is larger than we expect. */
1311 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1313 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1314 static int verbose_warned = 0;
1316 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1317 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1318 size += UNITS_PER_WORD;
1320 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1322 warning (0, "frame size too large for reliable stack checking");
1323 if (! verbose_warned)
1325 warning (0, "try reducing the number of local variables");
1331 /* Indicate that we no longer have known memory locations or constants. */
1332 if (reg_equiv_constant)
1333 free (reg_equiv_constant);
1334 if (reg_equiv_invariant)
1335 free (reg_equiv_invariant);
1336 reg_equiv_constant = 0;
1337 reg_equiv_invariant = 0;
1338 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
1339 reg_equiv_memory_loc = 0;
1341 if (offsets_known_at)
1342 free (offsets_known_at);
1346 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1347 if (reg_equiv_alt_mem_list[i])
1348 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
1349 free (reg_equiv_alt_mem_list);
1351 free (reg_equiv_mem);
1353 free (reg_equiv_address);
1354 free (reg_max_ref_width);
1355 free (reg_old_renumber);
1356 free (pseudo_previous_regs);
1357 free (pseudo_forbidden_regs);
1359 CLEAR_HARD_REG_SET (used_spill_regs);
1360 for (i = 0; i < n_spills; i++)
1361 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1363 /* Free all the insn_chain structures at once. */
1364 obstack_free (&reload_obstack, reload_startobj);
1365 unused_insn_chains = 0;
1366 fixup_abnormal_edges ();
1368 /* Replacing pseudos with their memory equivalents might have
1369 created shared rtx. Subsequent passes would get confused
1370 by this, so unshare everything here. */
1371 unshare_all_rtl_again (first);
1373 #ifdef STACK_BOUNDARY
1374 /* init_emit has set the alignment of the hard frame pointer
1375 to STACK_BOUNDARY. It is very likely no longer valid if
1376 the hard frame pointer was used for register allocation. */
1377 if (!frame_pointer_needed)
1378 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1384 /* Yet another special case. Unfortunately, reg-stack forces people to
1385 write incorrect clobbers in asm statements. These clobbers must not
1386 cause the register to appear in bad_spill_regs, otherwise we'll call
1387 fatal_insn later. We clear the corresponding regnos in the live
1388 register sets to avoid this.
1389 The whole thing is rather sick, I'm afraid. */
1392 maybe_fix_stack_asms (void)
1395 const char *constraints[MAX_RECOG_OPERANDS];
1396 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1397 struct insn_chain *chain;
1399 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1402 HARD_REG_SET clobbered, allowed;
1405 if (! INSN_P (chain->insn)
1406 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1408 pat = PATTERN (chain->insn);
1409 if (GET_CODE (pat) != PARALLEL)
1412 CLEAR_HARD_REG_SET (clobbered);
1413 CLEAR_HARD_REG_SET (allowed);
1415 /* First, make a mask of all stack regs that are clobbered. */
1416 for (i = 0; i < XVECLEN (pat, 0); i++)
1418 rtx t = XVECEXP (pat, 0, i);
1419 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1420 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1423 /* Get the operand values and constraints out of the insn. */
1424 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1425 constraints, operand_mode, NULL);
1427 /* For every operand, see what registers are allowed. */
1428 for (i = 0; i < noperands; i++)
1430 const char *p = constraints[i];
1431 /* For every alternative, we compute the class of registers allowed
1432 for reloading in CLS, and merge its contents into the reg set
1434 int cls = (int) NO_REGS;
1440 if (c == '\0' || c == ',' || c == '#')
1442 /* End of one alternative - mark the regs in the current
1443 class, and reset the class. */
1444 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1450 } while (c != '\0' && c != ',');
1458 case '=': case '+': case '*': case '%': case '?': case '!':
1459 case '0': case '1': case '2': case '3': case '4': case 'm':
1460 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1461 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1462 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1467 cls = (int) reg_class_subunion[cls]
1468 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1473 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1477 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1478 cls = (int) reg_class_subunion[cls]
1479 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1481 cls = (int) reg_class_subunion[cls]
1482 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1484 p += CONSTRAINT_LEN (c, p);
1487 /* Those of the registers which are clobbered, but allowed by the
1488 constraints, must be usable as reload registers. So clear them
1489 out of the life information. */
1490 AND_HARD_REG_SET (allowed, clobbered);
1491 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1492 if (TEST_HARD_REG_BIT (allowed, i))
1494 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1495 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1502 /* Copy the global variables n_reloads and rld into the corresponding elts
1505 copy_reloads (struct insn_chain *chain)
1507 chain->n_reloads = n_reloads;
1508 chain->rld = obstack_alloc (&reload_obstack,
1509 n_reloads * sizeof (struct reload));
1510 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1511 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1514 /* Walk the chain of insns, and determine for each whether it needs reloads
1515 and/or eliminations. Build the corresponding insns_need_reload list, and
1516 set something_needs_elimination as appropriate. */
1518 calculate_needs_all_insns (int global)
1520 struct insn_chain **pprev_reload = &insns_need_reload;
1521 struct insn_chain *chain, *next = 0;
1523 something_needs_elimination = 0;
1525 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1526 for (chain = reload_insn_chain; chain != 0; chain = next)
1528 rtx insn = chain->insn;
1532 /* Clear out the shortcuts. */
1533 chain->n_reloads = 0;
1534 chain->need_elim = 0;
1535 chain->need_reload = 0;
1536 chain->need_operand_change = 0;
1538 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1539 include REG_LABEL), we need to see what effects this has on the
1540 known offsets at labels. */
1542 if (LABEL_P (insn) || JUMP_P (insn)
1543 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1544 set_label_offsets (insn, insn, 0);
1548 rtx old_body = PATTERN (insn);
1549 int old_code = INSN_CODE (insn);
1550 rtx old_notes = REG_NOTES (insn);
1551 int did_elimination = 0;
1552 int operands_changed = 0;
1553 rtx set = single_set (insn);
1555 /* Skip insns that only set an equivalence. */
1556 if (set && REG_P (SET_DEST (set))
1557 && reg_renumber[REGNO (SET_DEST (set))] < 0
1558 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1559 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1560 && reg_equiv_init[REGNO (SET_DEST (set))])
1563 /* If needed, eliminate any eliminable registers. */
1564 if (num_eliminable || num_eliminable_invariants)
1565 did_elimination = eliminate_regs_in_insn (insn, 0);
1567 /* Analyze the instruction. */
1568 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1569 global, spill_reg_order);
1571 /* If a no-op set needs more than one reload, this is likely
1572 to be something that needs input address reloads. We
1573 can't get rid of this cleanly later, and it is of no use
1574 anyway, so discard it now.
1575 We only do this when expensive_optimizations is enabled,
1576 since this complements reload inheritance / output
1577 reload deletion, and it can make debugging harder. */
1578 if (flag_expensive_optimizations && n_reloads > 1)
1580 rtx set = single_set (insn);
1582 && SET_SRC (set) == SET_DEST (set)
1583 && REG_P (SET_SRC (set))
1584 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1587 /* Delete it from the reload chain. */
1589 chain->prev->next = next;
1591 reload_insn_chain = next;
1593 next->prev = chain->prev;
1594 chain->next = unused_insn_chains;
1595 unused_insn_chains = chain;
1600 update_eliminable_offsets ();
1602 /* Remember for later shortcuts which insns had any reloads or
1603 register eliminations. */
1604 chain->need_elim = did_elimination;
1605 chain->need_reload = n_reloads > 0;
1606 chain->need_operand_change = operands_changed;
1608 /* Discard any register replacements done. */
1609 if (did_elimination)
1611 obstack_free (&reload_obstack, reload_insn_firstobj);
1612 PATTERN (insn) = old_body;
1613 INSN_CODE (insn) = old_code;
1614 REG_NOTES (insn) = old_notes;
1615 something_needs_elimination = 1;
1618 something_needs_operands_changed |= operands_changed;
1622 copy_reloads (chain);
1623 *pprev_reload = chain;
1624 pprev_reload = &chain->next_need_reload;
1631 /* Comparison function for qsort to decide which of two reloads
1632 should be handled first. *P1 and *P2 are the reload numbers. */
1635 reload_reg_class_lower (const void *r1p, const void *r2p)
1637 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1640 /* Consider required reloads before optional ones. */
1641 t = rld[r1].optional - rld[r2].optional;
1645 /* Count all solitary classes before non-solitary ones. */
1646 t = ((reg_class_size[(int) rld[r2].class] == 1)
1647 - (reg_class_size[(int) rld[r1].class] == 1));
1651 /* Aside from solitaires, consider all multi-reg groups first. */
1652 t = rld[r2].nregs - rld[r1].nregs;
1656 /* Consider reloads in order of increasing reg-class number. */
1657 t = (int) rld[r1].class - (int) rld[r2].class;
1661 /* If reloads are equally urgent, sort by reload number,
1662 so that the results of qsort leave nothing to chance. */
1666 /* The cost of spilling each hard reg. */
1667 static int spill_cost[FIRST_PSEUDO_REGISTER];
1669 /* When spilling multiple hard registers, we use SPILL_COST for the first
1670 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1671 only the first hard reg for a multi-reg pseudo. */
1672 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1674 /* Update the spill cost arrays, considering that pseudo REG is live. */
1677 count_pseudo (int reg)
1679 int freq = REG_FREQ (reg);
1680 int r = reg_renumber[reg];
1683 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1684 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1687 SET_REGNO_REG_SET (&pseudos_counted, reg);
1689 gcc_assert (r >= 0);
1691 spill_add_cost[r] += freq;
1693 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1695 spill_cost[r + nregs] += freq;
1698 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1699 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1702 order_regs_for_reload (struct insn_chain *chain)
1705 HARD_REG_SET used_by_pseudos;
1706 HARD_REG_SET used_by_pseudos2;
1707 reg_set_iterator rsi;
1709 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1711 memset (spill_cost, 0, sizeof spill_cost);
1712 memset (spill_add_cost, 0, sizeof spill_add_cost);
1714 /* Count number of uses of each hard reg by pseudo regs allocated to it
1715 and then order them by decreasing use. First exclude hard registers
1716 that are live in or across this insn. */
1718 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1719 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1720 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1721 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1723 /* Now find out which pseudos are allocated to it, and update
1725 CLEAR_REG_SET (&pseudos_counted);
1727 EXECUTE_IF_SET_IN_REG_SET
1728 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1732 EXECUTE_IF_SET_IN_REG_SET
1733 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1737 CLEAR_REG_SET (&pseudos_counted);
1740 /* Vector of reload-numbers showing the order in which the reloads should
1742 static short reload_order[MAX_RELOADS];
1744 /* This is used to keep track of the spill regs used in one insn. */
1745 static HARD_REG_SET used_spill_regs_local;
1747 /* We decided to spill hard register SPILLED, which has a size of
1748 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1749 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1750 update SPILL_COST/SPILL_ADD_COST. */
1753 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1755 int r = reg_renumber[reg];
1756 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1758 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1759 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1762 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1764 spill_add_cost[r] -= REG_FREQ (reg);
1766 spill_cost[r + nregs] -= REG_FREQ (reg);
1769 /* Find reload register to use for reload number ORDER. */
1772 find_reg (struct insn_chain *chain, int order)
1774 int rnum = reload_order[order];
1775 struct reload *rl = rld + rnum;
1776 int best_cost = INT_MAX;
1780 HARD_REG_SET not_usable;
1781 HARD_REG_SET used_by_other_reload;
1782 reg_set_iterator rsi;
1784 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1785 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1786 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1788 CLEAR_HARD_REG_SET (used_by_other_reload);
1789 for (k = 0; k < order; k++)
1791 int other = reload_order[k];
1793 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1794 for (j = 0; j < rld[other].nregs; j++)
1795 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1798 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1800 unsigned int regno = i;
1802 if (! TEST_HARD_REG_BIT (not_usable, regno)
1803 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1804 && HARD_REGNO_MODE_OK (regno, rl->mode))
1806 int this_cost = spill_cost[regno];
1808 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1810 for (j = 1; j < this_nregs; j++)
1812 this_cost += spill_add_cost[regno + j];
1813 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1814 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1819 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1821 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1823 if (this_cost < best_cost
1824 /* Among registers with equal cost, prefer caller-saved ones, or
1825 use REG_ALLOC_ORDER if it is defined. */
1826 || (this_cost == best_cost
1827 #ifdef REG_ALLOC_ORDER
1828 && (inv_reg_alloc_order[regno]
1829 < inv_reg_alloc_order[best_reg])
1831 && call_used_regs[regno]
1832 && ! call_used_regs[best_reg]
1837 best_cost = this_cost;
1845 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1847 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1848 rl->regno = best_reg;
1850 EXECUTE_IF_SET_IN_REG_SET
1851 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1853 count_spilled_pseudo (best_reg, rl->nregs, j);
1856 EXECUTE_IF_SET_IN_REG_SET
1857 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1859 count_spilled_pseudo (best_reg, rl->nregs, j);
1862 for (i = 0; i < rl->nregs; i++)
1864 gcc_assert (spill_cost[best_reg + i] == 0);
1865 gcc_assert (spill_add_cost[best_reg + i] == 0);
1866 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1871 /* Find more reload regs to satisfy the remaining need of an insn, which
1873 Do it by ascending class number, since otherwise a reg
1874 might be spilled for a big class and might fail to count
1875 for a smaller class even though it belongs to that class. */
1878 find_reload_regs (struct insn_chain *chain)
1882 /* In order to be certain of getting the registers we need,
1883 we must sort the reloads into order of increasing register class.
1884 Then our grabbing of reload registers will parallel the process
1885 that provided the reload registers. */
1886 for (i = 0; i < chain->n_reloads; i++)
1888 /* Show whether this reload already has a hard reg. */
1889 if (chain->rld[i].reg_rtx)
1891 int regno = REGNO (chain->rld[i].reg_rtx);
1892 chain->rld[i].regno = regno;
1894 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1897 chain->rld[i].regno = -1;
1898 reload_order[i] = i;
1901 n_reloads = chain->n_reloads;
1902 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1904 CLEAR_HARD_REG_SET (used_spill_regs_local);
1907 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1909 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1911 /* Compute the order of preference for hard registers to spill. */
1913 order_regs_for_reload (chain);
1915 for (i = 0; i < n_reloads; i++)
1917 int r = reload_order[i];
1919 /* Ignore reloads that got marked inoperative. */
1920 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1921 && ! rld[r].optional
1922 && rld[r].regno == -1)
1923 if (! find_reg (chain, i))
1926 fprintf (dump_file, "reload failure for reload %d\n", r);
1927 spill_failure (chain->insn, rld[r].class);
1933 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1934 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1936 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1940 select_reload_regs (void)
1942 struct insn_chain *chain;
1944 /* Try to satisfy the needs for each insn. */
1945 for (chain = insns_need_reload; chain != 0;
1946 chain = chain->next_need_reload)
1947 find_reload_regs (chain);
1950 /* Delete all insns that were inserted by emit_caller_save_insns during
1953 delete_caller_save_insns (void)
1955 struct insn_chain *c = reload_insn_chain;
1959 while (c != 0 && c->is_caller_save_insn)
1961 struct insn_chain *next = c->next;
1964 if (c == reload_insn_chain)
1965 reload_insn_chain = next;
1969 next->prev = c->prev;
1971 c->prev->next = next;
1972 c->next = unused_insn_chains;
1973 unused_insn_chains = c;
1981 /* Handle the failure to find a register to spill.
1982 INSN should be one of the insns which needed this particular spill reg. */
1985 spill_failure (rtx insn, enum reg_class class)
1987 if (asm_noperands (PATTERN (insn)) >= 0)
1988 error_for_asm (insn, "can't find a register in class %qs while "
1989 "reloading %<asm%>",
1990 reg_class_names[class]);
1993 error ("unable to find a register to spill in class %qs",
1994 reg_class_names[class]);
1998 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
1999 debug_reload_to_stream (dump_file);
2001 fatal_insn ("this is the insn:", insn);
2005 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2006 data that is dead in INSN. */
2009 delete_dead_insn (rtx insn)
2011 rtx prev = prev_real_insn (insn);
2014 /* If the previous insn sets a register that dies in our insn, delete it
2016 if (prev && GET_CODE (PATTERN (prev)) == SET
2017 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2018 && reg_mentioned_p (prev_dest, PATTERN (insn))
2019 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2020 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2021 delete_dead_insn (prev);
2023 SET_INSN_DELETED (insn);
2026 /* Modify the home of pseudo-reg I.
2027 The new home is present in reg_renumber[I].
2029 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2030 or it may be -1, meaning there is none or it is not relevant.
2031 This is used so that all pseudos spilled from a given hard reg
2032 can share one stack slot. */
2035 alter_reg (int i, int from_reg)
2037 /* When outputting an inline function, this can happen
2038 for a reg that isn't actually used. */
2039 if (regno_reg_rtx[i] == 0)
2042 /* If the reg got changed to a MEM at rtl-generation time,
2044 if (!REG_P (regno_reg_rtx[i]))
2047 /* Modify the reg-rtx to contain the new hard reg
2048 number or else to contain its pseudo reg number. */
2049 SET_REGNO (regno_reg_rtx[i],
2050 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2052 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2053 allocate a stack slot for it. */
2055 if (reg_renumber[i] < 0
2056 && REG_N_REFS (i) > 0
2057 && reg_equiv_constant[i] == 0
2058 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
2059 && reg_equiv_memory_loc[i] == 0)
2062 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2063 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2064 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2065 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2066 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2069 /* Each pseudo reg has an inherent size which comes from its own mode,
2070 and a total size which provides room for paradoxical subregs
2071 which refer to the pseudo reg in wider modes.
2073 We can use a slot already allocated if it provides both
2074 enough inherent space and enough total space.
2075 Otherwise, we allocate a new slot, making sure that it has no less
2076 inherent space, and no less total space, then the previous slot. */
2079 alias_set_type alias_set = new_alias_set ();
2081 /* No known place to spill from => no slot to reuse. */
2082 x = assign_stack_local (mode, total_size,
2083 min_align > inherent_align
2084 || total_size > inherent_size ? -1 : 0);
2085 if (BYTES_BIG_ENDIAN)
2086 /* Cancel the big-endian correction done in assign_stack_local.
2087 Get the address of the beginning of the slot.
2088 This is so we can do a big-endian correction unconditionally
2090 adjust = inherent_size - total_size;
2092 /* Nothing can alias this slot except this pseudo. */
2093 set_mem_alias_set (x, alias_set);
2094 dse_record_singleton_alias_set (alias_set, mode);
2097 /* Reuse a stack slot if possible. */
2098 else if (spill_stack_slot[from_reg] != 0
2099 && spill_stack_slot_width[from_reg] >= total_size
2100 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2102 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2103 x = spill_stack_slot[from_reg];
2104 /* Allocate a bigger slot. */
2107 /* Compute maximum size needed, both for inherent size
2108 and for total size. */
2111 if (spill_stack_slot[from_reg])
2113 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2115 mode = GET_MODE (spill_stack_slot[from_reg]);
2116 if (spill_stack_slot_width[from_reg] > total_size)
2117 total_size = spill_stack_slot_width[from_reg];
2118 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2119 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2122 /* Make a slot with that size. */
2123 x = assign_stack_local (mode, total_size,
2124 min_align > inherent_align
2125 || total_size > inherent_size ? -1 : 0);
2128 /* All pseudos mapped to this slot can alias each other. */
2129 if (spill_stack_slot[from_reg])
2131 alias_set_type alias_set
2132 = MEM_ALIAS_SET (spill_stack_slot[from_reg]);
2133 set_mem_alias_set (x, alias_set);
2134 dse_invalidate_singleton_alias_set (alias_set);
2138 alias_set_type alias_set = new_alias_set ();
2139 set_mem_alias_set (x, alias_set);
2140 dse_record_singleton_alias_set (alias_set, mode);
2143 if (BYTES_BIG_ENDIAN)
2145 /* Cancel the big-endian correction done in assign_stack_local.
2146 Get the address of the beginning of the slot.
2147 This is so we can do a big-endian correction unconditionally
2149 adjust = GET_MODE_SIZE (mode) - total_size;
2152 = adjust_address_nv (x, mode_for_size (total_size
2158 spill_stack_slot[from_reg] = stack_slot;
2159 spill_stack_slot_width[from_reg] = total_size;
2162 /* On a big endian machine, the "address" of the slot
2163 is the address of the low part that fits its inherent mode. */
2164 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2165 adjust += (total_size - inherent_size);
2167 /* If we have any adjustment to make, or if the stack slot is the
2168 wrong mode, make a new stack slot. */
2169 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2171 /* If we have a decl for the original register, set it for the
2172 memory. If this is a shared MEM, make a copy. */
2173 if (REG_EXPR (regno_reg_rtx[i])
2174 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2176 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2178 /* We can do this only for the DECLs home pseudo, not for
2179 any copies of it, since otherwise when the stack slot
2180 is reused, nonoverlapping_memrefs_p might think they
2182 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2184 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2187 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2191 /* Save the stack slot for later. */
2192 reg_equiv_memory_loc[i] = x;
2196 /* Mark the slots in regs_ever_live for the hard regs used by
2197 pseudo-reg number REGNO, accessed in MODE. */
2200 mark_home_live_1 (int regno, enum machine_mode mode)
2204 i = reg_renumber[regno];
2207 lim = end_hard_regno (mode, i);
2209 df_set_regs_ever_live(i++, true);
2212 /* Mark the slots in regs_ever_live for the hard regs
2213 used by pseudo-reg number REGNO. */
2216 mark_home_live (int regno)
2218 if (reg_renumber[regno] >= 0)
2219 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2222 /* This function handles the tracking of elimination offsets around branches.
2224 X is a piece of RTL being scanned.
2226 INSN is the insn that it came from, if any.
2228 INITIAL_P is nonzero if we are to set the offset to be the initial
2229 offset and zero if we are setting the offset of the label to be the
2233 set_label_offsets (rtx x, rtx insn, int initial_p)
2235 enum rtx_code code = GET_CODE (x);
2238 struct elim_table *p;
2243 if (LABEL_REF_NONLOCAL_P (x))
2248 /* ... fall through ... */
2251 /* If we know nothing about this label, set the desired offsets. Note
2252 that this sets the offset at a label to be the offset before a label
2253 if we don't know anything about the label. This is not correct for
2254 the label after a BARRIER, but is the best guess we can make. If
2255 we guessed wrong, we will suppress an elimination that might have
2256 been possible had we been able to guess correctly. */
2258 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2260 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2261 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2262 = (initial_p ? reg_eliminate[i].initial_offset
2263 : reg_eliminate[i].offset);
2264 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2267 /* Otherwise, if this is the definition of a label and it is
2268 preceded by a BARRIER, set our offsets to the known offset of
2272 && (tem = prev_nonnote_insn (insn)) != 0
2274 set_offsets_for_label (insn);
2276 /* If neither of the above cases is true, compare each offset
2277 with those previously recorded and suppress any eliminations
2278 where the offsets disagree. */
2280 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2281 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2282 != (initial_p ? reg_eliminate[i].initial_offset
2283 : reg_eliminate[i].offset))
2284 reg_eliminate[i].can_eliminate = 0;
2289 set_label_offsets (PATTERN (insn), insn, initial_p);
2291 /* ... fall through ... */
2295 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2296 and hence must have all eliminations at their initial offsets. */
2297 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2298 if (REG_NOTE_KIND (tem) == REG_LABEL)
2299 set_label_offsets (XEXP (tem, 0), insn, 1);
2305 /* Each of the labels in the parallel or address vector must be
2306 at their initial offsets. We want the first field for PARALLEL
2307 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2309 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2310 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2315 /* We only care about setting PC. If the source is not RETURN,
2316 IF_THEN_ELSE, or a label, disable any eliminations not at
2317 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2318 isn't one of those possibilities. For branches to a label,
2319 call ourselves recursively.
2321 Note that this can disable elimination unnecessarily when we have
2322 a non-local goto since it will look like a non-constant jump to
2323 someplace in the current function. This isn't a significant
2324 problem since such jumps will normally be when all elimination
2325 pairs are back to their initial offsets. */
2327 if (SET_DEST (x) != pc_rtx)
2330 switch (GET_CODE (SET_SRC (x)))
2337 set_label_offsets (SET_SRC (x), insn, initial_p);
2341 tem = XEXP (SET_SRC (x), 1);
2342 if (GET_CODE (tem) == LABEL_REF)
2343 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2344 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2347 tem = XEXP (SET_SRC (x), 2);
2348 if (GET_CODE (tem) == LABEL_REF)
2349 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2350 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2358 /* If we reach here, all eliminations must be at their initial
2359 offset because we are doing a jump to a variable address. */
2360 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2361 if (p->offset != p->initial_offset)
2362 p->can_eliminate = 0;
2370 /* Scan X and replace any eliminable registers (such as fp) with a
2371 replacement (such as sp), plus an offset.
2373 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2374 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2375 MEM, we are allowed to replace a sum of a register and the constant zero
2376 with the register, which we cannot do outside a MEM. In addition, we need
2377 to record the fact that a register is referenced outside a MEM.
2379 If INSN is an insn, it is the insn containing X. If we replace a REG
2380 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2381 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2382 the REG is being modified.
2384 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2385 That's used when we eliminate in expressions stored in notes.
2386 This means, do not set ref_outside_mem even if the reference
2389 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2390 replacements done assuming all offsets are at their initial values. If
2391 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2392 encounter, return the actual location so that find_reloads will do
2393 the proper thing. */
2396 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2397 bool may_use_invariant)
2399 enum rtx_code code = GET_CODE (x);
2400 struct elim_table *ep;
2407 if (! current_function_decl)
2429 /* First handle the case where we encounter a bare register that
2430 is eliminable. Replace it with a PLUS. */
2431 if (regno < FIRST_PSEUDO_REGISTER)
2433 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2435 if (ep->from_rtx == x && ep->can_eliminate)
2436 return plus_constant (ep->to_rtx, ep->previous_offset);
2439 else if (reg_renumber && reg_renumber[regno] < 0
2440 && reg_equiv_invariant && reg_equiv_invariant[regno])
2442 if (may_use_invariant)
2443 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2444 mem_mode, insn, true);
2445 /* There exists at least one use of REGNO that cannot be
2446 eliminated. Prevent the defining insn from being deleted. */
2447 reg_equiv_init[regno] = NULL_RTX;
2448 alter_reg (regno, -1);
2452 /* You might think handling MINUS in a manner similar to PLUS is a
2453 good idea. It is not. It has been tried multiple times and every
2454 time the change has had to have been reverted.
2456 Other parts of reload know a PLUS is special (gen_reload for example)
2457 and require special code to handle code a reloaded PLUS operand.
2459 Also consider backends where the flags register is clobbered by a
2460 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2461 lea instruction comes to mind). If we try to reload a MINUS, we
2462 may kill the flags register that was holding a useful value.
2464 So, please before trying to handle MINUS, consider reload as a
2465 whole instead of this little section as well as the backend issues. */
2467 /* If this is the sum of an eliminable register and a constant, rework
2469 if (REG_P (XEXP (x, 0))
2470 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2471 && CONSTANT_P (XEXP (x, 1)))
2473 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2475 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2477 /* The only time we want to replace a PLUS with a REG (this
2478 occurs when the constant operand of the PLUS is the negative
2479 of the offset) is when we are inside a MEM. We won't want
2480 to do so at other times because that would change the
2481 structure of the insn in a way that reload can't handle.
2482 We special-case the commonest situation in
2483 eliminate_regs_in_insn, so just replace a PLUS with a
2484 PLUS here, unless inside a MEM. */
2485 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2486 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2489 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2490 plus_constant (XEXP (x, 1),
2491 ep->previous_offset));
2494 /* If the register is not eliminable, we are done since the other
2495 operand is a constant. */
2499 /* If this is part of an address, we want to bring any constant to the
2500 outermost PLUS. We will do this by doing register replacement in
2501 our operands and seeing if a constant shows up in one of them.
2503 Note that there is no risk of modifying the structure of the insn,
2504 since we only get called for its operands, thus we are either
2505 modifying the address inside a MEM, or something like an address
2506 operand of a load-address insn. */
2509 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2510 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2512 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2514 /* If one side is a PLUS and the other side is a pseudo that
2515 didn't get a hard register but has a reg_equiv_constant,
2516 we must replace the constant here since it may no longer
2517 be in the position of any operand. */
2518 if (GET_CODE (new0) == PLUS && REG_P (new1)
2519 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2520 && reg_renumber[REGNO (new1)] < 0
2521 && reg_equiv_constant != 0
2522 && reg_equiv_constant[REGNO (new1)] != 0)
2523 new1 = reg_equiv_constant[REGNO (new1)];
2524 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2525 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2526 && reg_renumber[REGNO (new0)] < 0
2527 && reg_equiv_constant[REGNO (new0)] != 0)
2528 new0 = reg_equiv_constant[REGNO (new0)];
2530 new = form_sum (new0, new1);
2532 /* As above, if we are not inside a MEM we do not want to
2533 turn a PLUS into something else. We might try to do so here
2534 for an addition of 0 if we aren't optimizing. */
2535 if (! mem_mode && GET_CODE (new) != PLUS)
2536 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2544 /* If this is the product of an eliminable register and a
2545 constant, apply the distribute law and move the constant out
2546 so that we have (plus (mult ..) ..). This is needed in order
2547 to keep load-address insns valid. This case is pathological.
2548 We ignore the possibility of overflow here. */
2549 if (REG_P (XEXP (x, 0))
2550 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2551 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2552 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2554 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2557 /* Refs inside notes don't count for this purpose. */
2558 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2559 || GET_CODE (insn) == INSN_LIST)))
2560 ep->ref_outside_mem = 1;
2563 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2564 ep->previous_offset * INTVAL (XEXP (x, 1)));
2567 /* ... fall through ... */
2571 /* See comments before PLUS about handling MINUS. */
2573 case DIV: case UDIV:
2574 case MOD: case UMOD:
2575 case AND: case IOR: case XOR:
2576 case ROTATERT: case ROTATE:
2577 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2579 case GE: case GT: case GEU: case GTU:
2580 case LE: case LT: case LEU: case LTU:
2582 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2583 rtx new1 = XEXP (x, 1)
2584 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2586 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2587 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2592 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2595 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2596 if (new != XEXP (x, 0))
2598 /* If this is a REG_DEAD note, it is not valid anymore.
2599 Using the eliminated version could result in creating a
2600 REG_DEAD note for the stack or frame pointer. */
2601 if (GET_MODE (x) == REG_DEAD)
2603 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2606 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2610 /* ... fall through ... */
2613 /* Now do eliminations in the rest of the chain. If this was
2614 an EXPR_LIST, this might result in allocating more memory than is
2615 strictly needed, but it simplifies the code. */
2618 new = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2619 if (new != XEXP (x, 1))
2621 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2629 /* We do not support elimination of a register that is modified.
2630 elimination_effects has already make sure that this does not
2636 /* We do not support elimination of a register that is modified.
2637 elimination_effects has already make sure that this does not
2638 happen. The only remaining case we need to consider here is
2639 that the increment value may be an eliminable register. */
2640 if (GET_CODE (XEXP (x, 1)) == PLUS
2641 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2643 rtx new = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2646 if (new != XEXP (XEXP (x, 1), 1))
2647 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2648 gen_rtx_PLUS (GET_MODE (x),
2653 case STRICT_LOW_PART:
2655 case SIGN_EXTEND: case ZERO_EXTEND:
2656 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2657 case FLOAT: case FIX:
2658 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2667 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2668 if (new != XEXP (x, 0))
2669 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2673 /* Similar to above processing, but preserve SUBREG_BYTE.
2674 Convert (subreg (mem)) to (mem) if not paradoxical.
2675 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2676 pseudo didn't get a hard reg, we must replace this with the
2677 eliminated version of the memory location because push_reload
2678 may do the replacement in certain circumstances. */
2679 if (REG_P (SUBREG_REG (x))
2680 && (GET_MODE_SIZE (GET_MODE (x))
2681 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2682 && reg_equiv_memory_loc != 0
2683 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2685 new = SUBREG_REG (x);
2688 new = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2690 if (new != SUBREG_REG (x))
2692 int x_size = GET_MODE_SIZE (GET_MODE (x));
2693 int new_size = GET_MODE_SIZE (GET_MODE (new));
2696 && ((x_size < new_size
2697 #ifdef WORD_REGISTER_OPERATIONS
2698 /* On these machines, combine can create rtl of the form
2699 (set (subreg:m1 (reg:m2 R) 0) ...)
2700 where m1 < m2, and expects something interesting to
2701 happen to the entire word. Moreover, it will use the
2702 (reg:m2 R) later, expecting all bits to be preserved.
2703 So if the number of words is the same, preserve the
2704 subreg so that push_reload can see it. */
2705 && ! ((x_size - 1) / UNITS_PER_WORD
2706 == (new_size -1 ) / UNITS_PER_WORD)
2709 || x_size == new_size)
2711 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2713 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2719 /* Our only special processing is to pass the mode of the MEM to our
2720 recursive call and copy the flags. While we are here, handle this
2721 case more efficiently. */
2723 replace_equiv_address_nv (x,
2724 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2728 /* Handle insn_list USE that a call to a pure function may generate. */
2729 new = eliminate_regs_1 (XEXP (x, 0), 0, insn, false);
2730 if (new != XEXP (x, 0))
2731 return gen_rtx_USE (GET_MODE (x), new);
2743 /* Process each of our operands recursively. If any have changed, make a
2745 fmt = GET_RTX_FORMAT (code);
2746 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2750 new = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2751 if (new != XEXP (x, i) && ! copied)
2753 x = shallow_copy_rtx (x);
2758 else if (*fmt == 'E')
2761 for (j = 0; j < XVECLEN (x, i); j++)
2763 new = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2764 if (new != XVECEXP (x, i, j) && ! copied_vec)
2766 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2770 x = shallow_copy_rtx (x);
2773 XVEC (x, i) = new_v;
2776 XVECEXP (x, i, j) = new;
2785 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2787 return eliminate_regs_1 (x, mem_mode, insn, false);
2790 /* Scan rtx X for modifications of elimination target registers. Update
2791 the table of eliminables to reflect the changed state. MEM_MODE is
2792 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2795 elimination_effects (rtx x, enum machine_mode mem_mode)
2797 enum rtx_code code = GET_CODE (x);
2798 struct elim_table *ep;
2822 /* First handle the case where we encounter a bare register that
2823 is eliminable. Replace it with a PLUS. */
2824 if (regno < FIRST_PSEUDO_REGISTER)
2826 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2828 if (ep->from_rtx == x && ep->can_eliminate)
2831 ep->ref_outside_mem = 1;
2836 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2837 && reg_equiv_constant[regno]
2838 && ! function_invariant_p (reg_equiv_constant[regno]))
2839 elimination_effects (reg_equiv_constant[regno], mem_mode);
2848 /* If we modify the source of an elimination rule, disable it. */
2849 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2850 if (ep->from_rtx == XEXP (x, 0))
2851 ep->can_eliminate = 0;
2853 /* If we modify the target of an elimination rule by adding a constant,
2854 update its offset. If we modify the target in any other way, we'll
2855 have to disable the rule as well. */
2856 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2857 if (ep->to_rtx == XEXP (x, 0))
2859 int size = GET_MODE_SIZE (mem_mode);
2861 /* If more bytes than MEM_MODE are pushed, account for them. */
2862 #ifdef PUSH_ROUNDING
2863 if (ep->to_rtx == stack_pointer_rtx)
2864 size = PUSH_ROUNDING (size);
2866 if (code == PRE_DEC || code == POST_DEC)
2868 else if (code == PRE_INC || code == POST_INC)
2870 else if (code == PRE_MODIFY || code == POST_MODIFY)
2872 if (GET_CODE (XEXP (x, 1)) == PLUS
2873 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2874 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
2875 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2877 ep->can_eliminate = 0;
2881 /* These two aren't unary operators. */
2882 if (code == POST_MODIFY || code == PRE_MODIFY)
2885 /* Fall through to generic unary operation case. */
2886 case STRICT_LOW_PART:
2888 case SIGN_EXTEND: case ZERO_EXTEND:
2889 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2890 case FLOAT: case FIX:
2891 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2900 elimination_effects (XEXP (x, 0), mem_mode);
2904 if (REG_P (SUBREG_REG (x))
2905 && (GET_MODE_SIZE (GET_MODE (x))
2906 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2907 && reg_equiv_memory_loc != 0
2908 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2911 elimination_effects (SUBREG_REG (x), mem_mode);
2915 /* If using a register that is the source of an eliminate we still
2916 think can be performed, note it cannot be performed since we don't
2917 know how this register is used. */
2918 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2919 if (ep->from_rtx == XEXP (x, 0))
2920 ep->can_eliminate = 0;
2922 elimination_effects (XEXP (x, 0), mem_mode);
2926 /* If clobbering a register that is the replacement register for an
2927 elimination we still think can be performed, note that it cannot
2928 be performed. Otherwise, we need not be concerned about it. */
2929 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2930 if (ep->to_rtx == XEXP (x, 0))
2931 ep->can_eliminate = 0;
2933 elimination_effects (XEXP (x, 0), mem_mode);
2937 /* Check for setting a register that we know about. */
2938 if (REG_P (SET_DEST (x)))
2940 /* See if this is setting the replacement register for an
2943 If DEST is the hard frame pointer, we do nothing because we
2944 assume that all assignments to the frame pointer are for
2945 non-local gotos and are being done at a time when they are valid
2946 and do not disturb anything else. Some machines want to
2947 eliminate a fake argument pointer (or even a fake frame pointer)
2948 with either the real frame or the stack pointer. Assignments to
2949 the hard frame pointer must not prevent this elimination. */
2951 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2953 if (ep->to_rtx == SET_DEST (x)
2954 && SET_DEST (x) != hard_frame_pointer_rtx)
2956 /* If it is being incremented, adjust the offset. Otherwise,
2957 this elimination can't be done. */
2958 rtx src = SET_SRC (x);
2960 if (GET_CODE (src) == PLUS
2961 && XEXP (src, 0) == SET_DEST (x)
2962 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2963 ep->offset -= INTVAL (XEXP (src, 1));
2965 ep->can_eliminate = 0;
2969 elimination_effects (SET_DEST (x), 0);
2970 elimination_effects (SET_SRC (x), 0);
2974 /* Our only special processing is to pass the mode of the MEM to our
2976 elimination_effects (XEXP (x, 0), GET_MODE (x));
2983 fmt = GET_RTX_FORMAT (code);
2984 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2987 elimination_effects (XEXP (x, i), mem_mode);
2988 else if (*fmt == 'E')
2989 for (j = 0; j < XVECLEN (x, i); j++)
2990 elimination_effects (XVECEXP (x, i, j), mem_mode);
2994 /* Descend through rtx X and verify that no references to eliminable registers
2995 remain. If any do remain, mark the involved register as not
2999 check_eliminable_occurrences (rtx x)
3008 code = GET_CODE (x);
3010 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3012 struct elim_table *ep;
3014 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3015 if (ep->from_rtx == x)
3016 ep->can_eliminate = 0;
3020 fmt = GET_RTX_FORMAT (code);
3021 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3024 check_eliminable_occurrences (XEXP (x, i));
3025 else if (*fmt == 'E')
3028 for (j = 0; j < XVECLEN (x, i); j++)
3029 check_eliminable_occurrences (XVECEXP (x, i, j));
3034 /* Scan INSN and eliminate all eliminable registers in it.
3036 If REPLACE is nonzero, do the replacement destructively. Also
3037 delete the insn as dead it if it is setting an eliminable register.
3039 If REPLACE is zero, do all our allocations in reload_obstack.
3041 If no eliminations were done and this insn doesn't require any elimination
3042 processing (these are not identical conditions: it might be updating sp,
3043 but not referencing fp; this needs to be seen during reload_as_needed so
3044 that the offset between fp and sp can be taken into consideration), zero
3045 is returned. Otherwise, 1 is returned. */
3048 eliminate_regs_in_insn (rtx insn, int replace)
3050 int icode = recog_memoized (insn);
3051 rtx old_body = PATTERN (insn);
3052 int insn_is_asm = asm_noperands (old_body) >= 0;
3053 rtx old_set = single_set (insn);
3057 rtx substed_operand[MAX_RECOG_OPERANDS];
3058 rtx orig_operand[MAX_RECOG_OPERANDS];
3059 struct elim_table *ep;
3060 rtx plus_src, plus_cst_src;
3062 if (! insn_is_asm && icode < 0)
3064 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3065 || GET_CODE (PATTERN (insn)) == CLOBBER
3066 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3067 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3068 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3072 if (old_set != 0 && REG_P (SET_DEST (old_set))
3073 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3075 /* Check for setting an eliminable register. */
3076 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3077 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3079 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3080 /* If this is setting the frame pointer register to the
3081 hardware frame pointer register and this is an elimination
3082 that will be done (tested above), this insn is really
3083 adjusting the frame pointer downward to compensate for
3084 the adjustment done before a nonlocal goto. */
3085 if (ep->from == FRAME_POINTER_REGNUM
3086 && ep->to == HARD_FRAME_POINTER_REGNUM)
3088 rtx base = SET_SRC (old_set);
3089 rtx base_insn = insn;
3090 HOST_WIDE_INT offset = 0;
3092 while (base != ep->to_rtx)
3094 rtx prev_insn, prev_set;
3096 if (GET_CODE (base) == PLUS
3097 && GET_CODE (XEXP (base, 1)) == CONST_INT)
3099 offset += INTVAL (XEXP (base, 1));
3100 base = XEXP (base, 0);
3102 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3103 && (prev_set = single_set (prev_insn)) != 0
3104 && rtx_equal_p (SET_DEST (prev_set), base))
3106 base = SET_SRC (prev_set);
3107 base_insn = prev_insn;
3113 if (base == ep->to_rtx)
3116 = plus_constant (ep->to_rtx, offset - ep->offset);
3118 new_body = old_body;
3121 new_body = copy_insn (old_body);
3122 if (REG_NOTES (insn))
3123 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3125 PATTERN (insn) = new_body;
3126 old_set = single_set (insn);
3128 /* First see if this insn remains valid when we
3129 make the change. If not, keep the INSN_CODE
3130 the same and let reload fit it up. */
3131 validate_change (insn, &SET_SRC (old_set), src, 1);
3132 validate_change (insn, &SET_DEST (old_set),
3134 if (! apply_change_group ())
3136 SET_SRC (old_set) = src;
3137 SET_DEST (old_set) = ep->to_rtx;
3146 /* In this case this insn isn't serving a useful purpose. We
3147 will delete it in reload_as_needed once we know that this
3148 elimination is, in fact, being done.
3150 If REPLACE isn't set, we can't delete this insn, but needn't
3151 process it since it won't be used unless something changes. */
3154 delete_dead_insn (insn);
3162 /* We allow one special case which happens to work on all machines we
3163 currently support: a single set with the source or a REG_EQUAL
3164 note being a PLUS of an eliminable register and a constant. */
3165 plus_src = plus_cst_src = 0;
3166 if (old_set && REG_P (SET_DEST (old_set)))
3168 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3169 plus_src = SET_SRC (old_set);
3170 /* First see if the source is of the form (plus (...) CST). */
3172 && GET_CODE (XEXP (plus_src, 1)) == CONST_INT)
3173 plus_cst_src = plus_src;
3174 else if (REG_P (SET_SRC (old_set))
3177 /* Otherwise, see if we have a REG_EQUAL note of the form
3178 (plus (...) CST). */
3180 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3182 if ((REG_NOTE_KIND (links) == REG_EQUAL
3183 || REG_NOTE_KIND (links) == REG_EQUIV)
3184 && GET_CODE (XEXP (links, 0)) == PLUS
3185 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT)
3187 plus_cst_src = XEXP (links, 0);
3193 /* Check that the first operand of the PLUS is a hard reg or
3194 the lowpart subreg of one. */
3197 rtx reg = XEXP (plus_cst_src, 0);
3198 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3199 reg = SUBREG_REG (reg);
3201 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3207 rtx reg = XEXP (plus_cst_src, 0);
3208 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3210 if (GET_CODE (reg) == SUBREG)
3211 reg = SUBREG_REG (reg);
3213 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3214 if (ep->from_rtx == reg && ep->can_eliminate)
3216 rtx to_rtx = ep->to_rtx;
3217 offset += ep->offset;
3218 offset = trunc_int_for_mode (offset, GET_MODE (reg));
3220 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3221 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3223 /* If we have a nonzero offset, and the source is already
3224 a simple REG, the following transformation would
3225 increase the cost of the insn by replacing a simple REG
3226 with (plus (reg sp) CST). So try only when we already
3227 had a PLUS before. */
3228 if (offset == 0 || plus_src)
3230 rtx new_src = plus_constant (to_rtx, offset);
3232 new_body = old_body;
3235 new_body = copy_insn (old_body);
3236 if (REG_NOTES (insn))
3237 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3239 PATTERN (insn) = new_body;
3240 old_set = single_set (insn);
3242 /* First see if this insn remains valid when we make the
3243 change. If not, try to replace the whole pattern with
3244 a simple set (this may help if the original insn was a
3245 PARALLEL that was only recognized as single_set due to
3246 REG_UNUSED notes). If this isn't valid either, keep
3247 the INSN_CODE the same and let reload fix it up. */
3248 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3250 rtx new_pat = gen_rtx_SET (VOIDmode,
3251 SET_DEST (old_set), new_src);
3253 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3254 SET_SRC (old_set) = new_src;
3261 /* This can't have an effect on elimination offsets, so skip right
3267 /* Determine the effects of this insn on elimination offsets. */
3268 elimination_effects (old_body, 0);
3270 /* Eliminate all eliminable registers occurring in operands that
3271 can be handled by reload. */
3272 extract_insn (insn);
3273 for (i = 0; i < recog_data.n_operands; i++)
3275 orig_operand[i] = recog_data.operand[i];
3276 substed_operand[i] = recog_data.operand[i];
3278 /* For an asm statement, every operand is eliminable. */
3279 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3281 bool is_set_src, in_plus;
3283 /* Check for setting a register that we know about. */
3284 if (recog_data.operand_type[i] != OP_IN
3285 && REG_P (orig_operand[i]))
3287 /* If we are assigning to a register that can be eliminated, it
3288 must be as part of a PARALLEL, since the code above handles
3289 single SETs. We must indicate that we can no longer
3290 eliminate this reg. */
3291 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3293 if (ep->from_rtx == orig_operand[i])
3294 ep->can_eliminate = 0;
3297 /* Companion to the above plus substitution, we can allow
3298 invariants as the source of a plain move. */
3300 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3304 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3305 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3309 = eliminate_regs_1 (recog_data.operand[i], 0,
3310 replace ? insn : NULL_RTX,
3311 is_set_src || in_plus);
3312 if (substed_operand[i] != orig_operand[i])
3314 /* Terminate the search in check_eliminable_occurrences at
3316 *recog_data.operand_loc[i] = 0;
3318 /* If an output operand changed from a REG to a MEM and INSN is an
3319 insn, write a CLOBBER insn. */
3320 if (recog_data.operand_type[i] != OP_IN
3321 && REG_P (orig_operand[i])
3322 && MEM_P (substed_operand[i])
3324 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3329 for (i = 0; i < recog_data.n_dups; i++)
3330 *recog_data.dup_loc[i]
3331 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3333 /* If any eliminable remain, they aren't eliminable anymore. */
3334 check_eliminable_occurrences (old_body);
3336 /* Substitute the operands; the new values are in the substed_operand
3338 for (i = 0; i < recog_data.n_operands; i++)
3339 *recog_data.operand_loc[i] = substed_operand[i];
3340 for (i = 0; i < recog_data.n_dups; i++)
3341 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3343 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3344 re-recognize the insn. We do this in case we had a simple addition
3345 but now can do this as a load-address. This saves an insn in this
3347 If re-recognition fails, the old insn code number will still be used,
3348 and some register operands may have changed into PLUS expressions.
3349 These will be handled by find_reloads by loading them into a register
3354 /* If we aren't replacing things permanently and we changed something,
3355 make another copy to ensure that all the RTL is new. Otherwise
3356 things can go wrong if find_reload swaps commutative operands
3357 and one is inside RTL that has been copied while the other is not. */
3358 new_body = old_body;
3361 new_body = copy_insn (old_body);
3362 if (REG_NOTES (insn))
3363 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3365 PATTERN (insn) = new_body;
3367 /* If we had a move insn but now we don't, rerecognize it. This will
3368 cause spurious re-recognition if the old move had a PARALLEL since
3369 the new one still will, but we can't call single_set without
3370 having put NEW_BODY into the insn and the re-recognition won't
3371 hurt in this rare case. */
3372 /* ??? Why this huge if statement - why don't we just rerecognize the
3376 && ((REG_P (SET_SRC (old_set))
3377 && (GET_CODE (new_body) != SET
3378 || !REG_P (SET_SRC (new_body))))
3379 /* If this was a load from or store to memory, compare
3380 the MEM in recog_data.operand to the one in the insn.
3381 If they are not equal, then rerecognize the insn. */
3383 && ((MEM_P (SET_SRC (old_set))
3384 && SET_SRC (old_set) != recog_data.operand[1])
3385 || (MEM_P (SET_DEST (old_set))
3386 && SET_DEST (old_set) != recog_data.operand[0])))
3387 /* If this was an add insn before, rerecognize. */
3388 || GET_CODE (SET_SRC (old_set)) == PLUS))
3390 int new_icode = recog (PATTERN (insn), insn, 0);
3392 INSN_CODE (insn) = new_icode;
3396 /* Restore the old body. If there were any changes to it, we made a copy
3397 of it while the changes were still in place, so we'll correctly return
3398 a modified insn below. */
3401 /* Restore the old body. */
3402 for (i = 0; i < recog_data.n_operands; i++)
3403 *recog_data.operand_loc[i] = orig_operand[i];
3404 for (i = 0; i < recog_data.n_dups; i++)
3405 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3408 /* Update all elimination pairs to reflect the status after the current
3409 insn. The changes we make were determined by the earlier call to
3410 elimination_effects.
3412 We also detect cases where register elimination cannot be done,
3413 namely, if a register would be both changed and referenced outside a MEM
3414 in the resulting insn since such an insn is often undefined and, even if
3415 not, we cannot know what meaning will be given to it. Note that it is
3416 valid to have a register used in an address in an insn that changes it
3417 (presumably with a pre- or post-increment or decrement).
3419 If anything changes, return nonzero. */
3421 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3423 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3424 ep->can_eliminate = 0;
3426 ep->ref_outside_mem = 0;
3428 if (ep->previous_offset != ep->offset)
3433 /* If we changed something, perform elimination in REG_NOTES. This is
3434 needed even when REPLACE is zero because a REG_DEAD note might refer
3435 to a register that we eliminate and could cause a different number
3436 of spill registers to be needed in the final reload pass than in
3438 if (val && REG_NOTES (insn) != 0)
3440 = eliminate_regs_1 (REG_NOTES (insn), 0, REG_NOTES (insn), true);
3445 /* Loop through all elimination pairs.
3446 Recalculate the number not at initial offset.
3448 Compute the maximum offset (minimum offset if the stack does not
3449 grow downward) for each elimination pair. */
3452 update_eliminable_offsets (void)
3454 struct elim_table *ep;
3456 num_not_at_initial_offset = 0;
3457 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3459 ep->previous_offset = ep->offset;
3460 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3461 num_not_at_initial_offset++;
3465 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3466 replacement we currently believe is valid, mark it as not eliminable if X
3467 modifies DEST in any way other than by adding a constant integer to it.
3469 If DEST is the frame pointer, we do nothing because we assume that
3470 all assignments to the hard frame pointer are nonlocal gotos and are being
3471 done at a time when they are valid and do not disturb anything else.
3472 Some machines want to eliminate a fake argument pointer with either the
3473 frame or stack pointer. Assignments to the hard frame pointer must not
3474 prevent this elimination.
3476 Called via note_stores from reload before starting its passes to scan
3477 the insns of the function. */
3480 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3484 /* A SUBREG of a hard register here is just changing its mode. We should
3485 not see a SUBREG of an eliminable hard register, but check just in
3487 if (GET_CODE (dest) == SUBREG)
3488 dest = SUBREG_REG (dest);
3490 if (dest == hard_frame_pointer_rtx)
3493 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3494 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3495 && (GET_CODE (x) != SET
3496 || GET_CODE (SET_SRC (x)) != PLUS
3497 || XEXP (SET_SRC (x), 0) != dest
3498 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3500 reg_eliminate[i].can_eliminate_previous
3501 = reg_eliminate[i].can_eliminate = 0;
3506 /* Verify that the initial elimination offsets did not change since the
3507 last call to set_initial_elim_offsets. This is used to catch cases
3508 where something illegal happened during reload_as_needed that could
3509 cause incorrect code to be generated if we did not check for it. */
3512 verify_initial_elim_offsets (void)
3516 if (!num_eliminable)
3519 #ifdef ELIMINABLE_REGS
3521 struct elim_table *ep;
3523 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3525 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3526 if (t != ep->initial_offset)
3531 INITIAL_FRAME_POINTER_OFFSET (t);
3532 if (t != reg_eliminate[0].initial_offset)
3539 /* Reset all offsets on eliminable registers to their initial values. */
3542 set_initial_elim_offsets (void)
3544 struct elim_table *ep = reg_eliminate;
3546 #ifdef ELIMINABLE_REGS
3547 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3549 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3550 ep->previous_offset = ep->offset = ep->initial_offset;
3553 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3554 ep->previous_offset = ep->offset = ep->initial_offset;
3557 num_not_at_initial_offset = 0;
3560 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3563 set_initial_eh_label_offset (rtx label)
3565 set_label_offsets (label, NULL_RTX, 1);
3568 /* Initialize the known label offsets.
3569 Set a known offset for each forced label to be at the initial offset
3570 of each elimination. We do this because we assume that all
3571 computed jumps occur from a location where each elimination is
3572 at its initial offset.
3573 For all other labels, show that we don't know the offsets. */
3576 set_initial_label_offsets (void)
3579 memset (offsets_known_at, 0, num_labels);
3581 for (x = forced_labels; x; x = XEXP (x, 1))
3583 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3585 for_each_eh_label (set_initial_eh_label_offset);
3588 /* Set all elimination offsets to the known values for the code label given
3592 set_offsets_for_label (rtx insn)
3595 int label_nr = CODE_LABEL_NUMBER (insn);
3596 struct elim_table *ep;
3598 num_not_at_initial_offset = 0;
3599 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3601 ep->offset = ep->previous_offset
3602 = offsets_at[label_nr - first_label_num][i];
3603 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3604 num_not_at_initial_offset++;
3608 /* See if anything that happened changes which eliminations are valid.
3609 For example, on the SPARC, whether or not the frame pointer can
3610 be eliminated can depend on what registers have been used. We need
3611 not check some conditions again (such as flag_omit_frame_pointer)
3612 since they can't have changed. */
3615 update_eliminables (HARD_REG_SET *pset)
3617 int previous_frame_pointer_needed = frame_pointer_needed;
3618 struct elim_table *ep;
3620 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3621 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3622 #ifdef ELIMINABLE_REGS
3623 || ! CAN_ELIMINATE (ep->from, ep->to)
3626 ep->can_eliminate = 0;
3628 /* Look for the case where we have discovered that we can't replace
3629 register A with register B and that means that we will now be
3630 trying to replace register A with register C. This means we can
3631 no longer replace register C with register B and we need to disable
3632 such an elimination, if it exists. This occurs often with A == ap,
3633 B == sp, and C == fp. */
3635 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3637 struct elim_table *op;
3640 if (! ep->can_eliminate && ep->can_eliminate_previous)
3642 /* Find the current elimination for ep->from, if there is a
3644 for (op = reg_eliminate;
3645 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3646 if (op->from == ep->from && op->can_eliminate)
3652 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3654 for (op = reg_eliminate;
3655 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3656 if (op->from == new_to && op->to == ep->to)
3657 op->can_eliminate = 0;
3661 /* See if any registers that we thought we could eliminate the previous
3662 time are no longer eliminable. If so, something has changed and we
3663 must spill the register. Also, recompute the number of eliminable
3664 registers and see if the frame pointer is needed; it is if there is
3665 no elimination of the frame pointer that we can perform. */
3667 frame_pointer_needed = 1;
3668 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3670 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3671 && ep->to != HARD_FRAME_POINTER_REGNUM)
3672 frame_pointer_needed = 0;
3674 if (! ep->can_eliminate && ep->can_eliminate_previous)
3676 ep->can_eliminate_previous = 0;
3677 SET_HARD_REG_BIT (*pset, ep->from);
3682 /* If we didn't need a frame pointer last time, but we do now, spill
3683 the hard frame pointer. */
3684 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3685 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3688 /* Return true if X is used as the target register of an elimination. */
3691 elimination_target_reg_p (rtx x)
3693 struct elim_table *ep;
3695 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3696 if (ep->to_rtx == x && ep->can_eliminate)
3702 /* Initialize the table of registers to eliminate. */
3705 init_elim_table (void)
3707 struct elim_table *ep;
3708 #ifdef ELIMINABLE_REGS
3709 const struct elim_table_1 *ep1;
3713 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3715 /* Does this function require a frame pointer? */
3717 frame_pointer_needed = (! flag_omit_frame_pointer
3718 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3719 and restore sp for alloca. So we can't eliminate
3720 the frame pointer in that case. At some point,
3721 we should improve this by emitting the
3722 sp-adjusting insns for this case. */
3723 || (current_function_calls_alloca
3724 && EXIT_IGNORE_STACK)
3725 || current_function_accesses_prior_frames
3726 || FRAME_POINTER_REQUIRED);
3730 #ifdef ELIMINABLE_REGS
3731 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3732 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3734 ep->from = ep1->from;
3736 ep->can_eliminate = ep->can_eliminate_previous
3737 = (CAN_ELIMINATE (ep->from, ep->to)
3738 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3741 reg_eliminate[0].from = reg_eliminate_1[0].from;
3742 reg_eliminate[0].to = reg_eliminate_1[0].to;
3743 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3744 = ! frame_pointer_needed;
3747 /* Count the number of eliminable registers and build the FROM and TO
3748 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3749 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3750 We depend on this. */
3751 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3753 num_eliminable += ep->can_eliminate;
3754 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3755 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3759 /* Kick all pseudos out of hard register REGNO.
3761 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3762 because we found we can't eliminate some register. In the case, no pseudos
3763 are allowed to be in the register, even if they are only in a block that
3764 doesn't require spill registers, unlike the case when we are spilling this
3765 hard reg to produce another spill register.
3767 Return nonzero if any pseudos needed to be kicked out. */
3770 spill_hard_reg (unsigned int regno, int cant_eliminate)
3776 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3777 df_set_regs_ever_live (regno, true);
3780 /* Spill every pseudo reg that was allocated to this reg
3781 or to something that overlaps this reg. */
3783 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3784 if (reg_renumber[i] >= 0
3785 && (unsigned int) reg_renumber[i] <= regno
3786 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
3787 SET_REGNO_REG_SET (&spilled_pseudos, i);
3790 /* After find_reload_regs has been run for all insn that need reloads,
3791 and/or spill_hard_regs was called, this function is used to actually
3792 spill pseudo registers and try to reallocate them. It also sets up the
3793 spill_regs array for use by choose_reload_regs. */
3796 finish_spills (int global)
3798 struct insn_chain *chain;
3799 int something_changed = 0;
3801 reg_set_iterator rsi;
3803 /* Build the spill_regs array for the function. */
3804 /* If there are some registers still to eliminate and one of the spill regs
3805 wasn't ever used before, additional stack space may have to be
3806 allocated to store this register. Thus, we may have changed the offset
3807 between the stack and frame pointers, so mark that something has changed.
3809 One might think that we need only set VAL to 1 if this is a call-used
3810 register. However, the set of registers that must be saved by the
3811 prologue is not identical to the call-used set. For example, the
3812 register used by the call insn for the return PC is a call-used register,
3813 but must be saved by the prologue. */
3816 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3817 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3819 spill_reg_order[i] = n_spills;
3820 spill_regs[n_spills++] = i;
3821 if (num_eliminable && ! df_regs_ever_live_p (i))
3822 something_changed = 1;
3823 df_set_regs_ever_live (i, true);
3826 spill_reg_order[i] = -1;
3828 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3830 /* Record the current hard register the pseudo is allocated to in
3831 pseudo_previous_regs so we avoid reallocating it to the same
3832 hard reg in a later pass. */
3833 gcc_assert (reg_renumber[i] >= 0);
3835 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3836 /* Mark it as no longer having a hard register home. */
3837 reg_renumber[i] = -1;
3838 /* We will need to scan everything again. */
3839 something_changed = 1;
3842 /* Retry global register allocation if possible. */
3845 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3846 /* For every insn that needs reloads, set the registers used as spill
3847 regs in pseudo_forbidden_regs for every pseudo live across the
3849 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3851 EXECUTE_IF_SET_IN_REG_SET
3852 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3854 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3855 chain->used_spill_regs);
3857 EXECUTE_IF_SET_IN_REG_SET
3858 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3860 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3861 chain->used_spill_regs);
3865 /* Retry allocating the spilled pseudos. For each reg, merge the
3866 various reg sets that indicate which hard regs can't be used,
3867 and call retry_global_alloc.
3868 We change spill_pseudos here to only contain pseudos that did not
3869 get a new hard register. */
3870 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3871 if (reg_old_renumber[i] != reg_renumber[i])
3873 HARD_REG_SET forbidden;
3874 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3875 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3876 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3877 retry_global_alloc (i, forbidden);
3878 if (reg_renumber[i] >= 0)
3879 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3883 /* Fix up the register information in the insn chain.
3884 This involves deleting those of the spilled pseudos which did not get
3885 a new hard register home from the live_{before,after} sets. */
3886 for (chain = reload_insn_chain; chain; chain = chain->next)
3888 HARD_REG_SET used_by_pseudos;
3889 HARD_REG_SET used_by_pseudos2;
3891 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3892 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3894 /* Mark any unallocated hard regs as available for spills. That
3895 makes inheritance work somewhat better. */
3896 if (chain->need_reload)
3898 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3899 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3900 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3902 /* Save the old value for the sanity test below. */
3903 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3905 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3906 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3907 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3908 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3910 /* Make sure we only enlarge the set. */
3911 gcc_assert (hard_reg_set_subset_p (used_by_pseudos2,
3912 chain->used_spill_regs));
3916 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3917 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3919 int regno = reg_renumber[i];
3920 if (reg_old_renumber[i] == regno)
3923 alter_reg (i, reg_old_renumber[i]);
3924 reg_old_renumber[i] = regno;
3928 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3930 fprintf (dump_file, " Register %d now in %d.\n\n",
3931 i, reg_renumber[i]);
3935 return something_changed;
3938 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3941 scan_paradoxical_subregs (rtx x)
3945 enum rtx_code code = GET_CODE (x);
3955 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3963 if (REG_P (SUBREG_REG (x))
3964 && (GET_MODE_SIZE (GET_MODE (x))
3965 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
3967 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3968 = GET_MODE_SIZE (GET_MODE (x));
3969 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
3977 fmt = GET_RTX_FORMAT (code);
3978 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3981 scan_paradoxical_subregs (XEXP (x, i));
3982 else if (fmt[i] == 'E')
3985 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3986 scan_paradoxical_subregs (XVECEXP (x, i, j));
3991 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
3992 examine all of the reload insns between PREV and NEXT exclusive, and
3993 annotate all that may trap. */
3996 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
3998 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
3999 unsigned int trap_count;
4005 if (may_trap_p (PATTERN (insn)))
4009 remove_note (insn, note);
4013 for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i))
4014 if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i)))
4018 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (note, 0), REG_NOTES (i));
4022 /* Reload pseudo-registers into hard regs around each insn as needed.
4023 Additional register load insns are output before the insn that needs it
4024 and perhaps store insns after insns that modify the reloaded pseudo reg.
4026 reg_last_reload_reg and reg_reloaded_contents keep track of
4027 which registers are already available in reload registers.
4028 We update these for the reloads that we perform,
4029 as the insns are scanned. */
4032 reload_as_needed (int live_known)
4034 struct insn_chain *chain;
4035 #if defined (AUTO_INC_DEC)
4040 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4041 memset (spill_reg_store, 0, sizeof spill_reg_store);
4042 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4043 INIT_REG_SET (®_has_output_reload);
4044 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4045 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4047 set_initial_elim_offsets ();
4049 for (chain = reload_insn_chain; chain; chain = chain->next)
4052 rtx insn = chain->insn;
4053 rtx old_next = NEXT_INSN (insn);
4055 /* If we pass a label, copy the offsets from the label information
4056 into the current offsets of each elimination. */
4058 set_offsets_for_label (insn);
4060 else if (INSN_P (insn))
4062 regset_head regs_to_forget;
4063 INIT_REG_SET (®s_to_forget);
4064 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4066 /* If this is a USE and CLOBBER of a MEM, ensure that any
4067 references to eliminable registers have been removed. */
4069 if ((GET_CODE (PATTERN (insn)) == USE
4070 || GET_CODE (PATTERN (insn)) == CLOBBER)
4071 && MEM_P (XEXP (PATTERN (insn), 0)))
4072 XEXP (XEXP (PATTERN (insn), 0), 0)
4073 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4074 GET_MODE (XEXP (PATTERN (insn), 0)),
4077 /* If we need to do register elimination processing, do so.
4078 This might delete the insn, in which case we are done. */
4079 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4081 eliminate_regs_in_insn (insn, 1);
4084 update_eliminable_offsets ();
4085 CLEAR_REG_SET (®s_to_forget);
4090 /* If need_elim is nonzero but need_reload is zero, one might think
4091 that we could simply set n_reloads to 0. However, find_reloads
4092 could have done some manipulation of the insn (such as swapping
4093 commutative operands), and these manipulations are lost during
4094 the first pass for every insn that needs register elimination.
4095 So the actions of find_reloads must be redone here. */
4097 if (! chain->need_elim && ! chain->need_reload
4098 && ! chain->need_operand_change)
4100 /* First find the pseudo regs that must be reloaded for this insn.
4101 This info is returned in the tables reload_... (see reload.h).
4102 Also modify the body of INSN by substituting RELOAD
4103 rtx's for those pseudo regs. */
4106 CLEAR_REG_SET (®_has_output_reload);
4107 CLEAR_HARD_REG_SET (reg_is_output_reload);
4109 find_reloads (insn, 1, spill_indirect_levels, live_known,
4115 rtx next = NEXT_INSN (insn);
4118 prev = PREV_INSN (insn);
4120 /* Now compute which reload regs to reload them into. Perhaps
4121 reusing reload regs from previous insns, or else output
4122 load insns to reload them. Maybe output store insns too.
4123 Record the choices of reload reg in reload_reg_rtx. */
4124 choose_reload_regs (chain);
4126 /* Merge any reloads that we didn't combine for fear of
4127 increasing the number of spill registers needed but now
4128 discover can be safely merged. */
4129 if (SMALL_REGISTER_CLASSES)
4130 merge_assigned_reloads (insn);
4132 /* Generate the insns to reload operands into or out of
4133 their reload regs. */
4134 emit_reload_insns (chain);
4136 /* Substitute the chosen reload regs from reload_reg_rtx
4137 into the insn's body (or perhaps into the bodies of other
4138 load and store insn that we just made for reloading
4139 and that we moved the structure into). */
4140 subst_reloads (insn);
4142 /* Adjust the exception region notes for loads and stores. */
4143 if (flag_non_call_exceptions && !CALL_P (insn))
4144 fixup_eh_region_note (insn, prev, next);
4146 /* If this was an ASM, make sure that all the reload insns
4147 we have generated are valid. If not, give an error
4149 if (asm_noperands (PATTERN (insn)) >= 0)
4150 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4151 if (p != insn && INSN_P (p)
4152 && GET_CODE (PATTERN (p)) != USE
4153 && (recog_memoized (p) < 0
4154 || (extract_insn (p), ! constrain_operands (1))))
4156 error_for_asm (insn,
4157 "%<asm%> operand requires "
4158 "impossible reload");
4163 if (num_eliminable && chain->need_elim)
4164 update_eliminable_offsets ();
4166 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4167 is no longer validly lying around to save a future reload.
4168 Note that this does not detect pseudos that were reloaded
4169 for this insn in order to be stored in
4170 (obeying register constraints). That is correct; such reload
4171 registers ARE still valid. */
4172 forget_marked_reloads (®s_to_forget);
4173 CLEAR_REG_SET (®s_to_forget);
4175 /* There may have been CLOBBER insns placed after INSN. So scan
4176 between INSN and NEXT and use them to forget old reloads. */
4177 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4178 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4179 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4182 /* Likewise for regs altered by auto-increment in this insn.
4183 REG_INC notes have been changed by reloading:
4184 find_reloads_address_1 records substitutions for them,
4185 which have been performed by subst_reloads above. */
4186 for (i = n_reloads - 1; i >= 0; i--)
4188 rtx in_reg = rld[i].in_reg;
4191 enum rtx_code code = GET_CODE (in_reg);
4192 /* PRE_INC / PRE_DEC will have the reload register ending up
4193 with the same value as the stack slot, but that doesn't
4194 hold true for POST_INC / POST_DEC. Either we have to
4195 convert the memory access to a true POST_INC / POST_DEC,
4196 or we can't use the reload register for inheritance. */
4197 if ((code == POST_INC || code == POST_DEC)
4198 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4199 REGNO (rld[i].reg_rtx))
4200 /* Make sure it is the inc/dec pseudo, and not
4201 some other (e.g. output operand) pseudo. */
4202 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4203 == REGNO (XEXP (in_reg, 0))))
4206 rtx reload_reg = rld[i].reg_rtx;
4207 enum machine_mode mode = GET_MODE (reload_reg);
4211 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4213 /* We really want to ignore REG_INC notes here, so
4214 use PATTERN (p) as argument to reg_set_p . */
4215 if (reg_set_p (reload_reg, PATTERN (p)))
4217 n = count_occurrences (PATTERN (p), reload_reg, 0);
4222 n = validate_replace_rtx (reload_reg,
4223 gen_rtx_fmt_e (code,
4228 /* We must also verify that the constraints
4229 are met after the replacement. */
4232 n = constrain_operands (1);
4236 /* If the constraints were not met, then
4237 undo the replacement. */
4240 validate_replace_rtx (gen_rtx_fmt_e (code,
4253 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4255 /* Mark this as having an output reload so that the
4256 REG_INC processing code below won't invalidate
4257 the reload for inheritance. */
4258 SET_HARD_REG_BIT (reg_is_output_reload,
4259 REGNO (reload_reg));
4260 SET_REGNO_REG_SET (®_has_output_reload,
4261 REGNO (XEXP (in_reg, 0)));
4264 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4267 else if ((code == PRE_INC || code == PRE_DEC)
4268 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4269 REGNO (rld[i].reg_rtx))
4270 /* Make sure it is the inc/dec pseudo, and not
4271 some other (e.g. output operand) pseudo. */
4272 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4273 == REGNO (XEXP (in_reg, 0))))
4275 SET_HARD_REG_BIT (reg_is_output_reload,
4276 REGNO (rld[i].reg_rtx));
4277 SET_REGNO_REG_SET (®_has_output_reload,
4278 REGNO (XEXP (in_reg, 0)));
4282 /* If a pseudo that got a hard register is auto-incremented,
4283 we must purge records of copying it into pseudos without
4285 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4286 if (REG_NOTE_KIND (x) == REG_INC)
4288 /* See if this pseudo reg was reloaded in this insn.
4289 If so, its last-reload info is still valid
4290 because it is based on this insn's reload. */
4291 for (i = 0; i < n_reloads; i++)
4292 if (rld[i].out == XEXP (x, 0))
4296 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4300 /* A reload reg's contents are unknown after a label. */
4302 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4304 /* Don't assume a reload reg is still good after a call insn
4305 if it is a call-used reg, or if it contains a value that will
4306 be partially clobbered by the call. */
4307 else if (CALL_P (insn))
4309 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4310 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4315 free (reg_last_reload_reg);
4316 CLEAR_REG_SET (®_has_output_reload);
4319 /* Discard all record of any value reloaded from X,
4320 or reloaded in X from someplace else;
4321 unless X is an output reload reg of the current insn.
4323 X may be a hard reg (the reload reg)
4324 or it may be a pseudo reg that was reloaded from.
4326 When DATA is non-NULL just mark the registers in regset
4327 to be forgotten later. */
4330 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4335 regset regs = (regset) data;
4337 /* note_stores does give us subregs of hard regs,
4338 subreg_regno_offset requires a hard reg. */
4339 while (GET_CODE (x) == SUBREG)
4341 /* We ignore the subreg offset when calculating the regno,
4342 because we are using the entire underlying hard register
4352 if (regno >= FIRST_PSEUDO_REGISTER)
4358 nr = hard_regno_nregs[regno][GET_MODE (x)];
4359 /* Storing into a spilled-reg invalidates its contents.
4360 This can happen if a block-local pseudo is allocated to that reg
4361 and it wasn't spilled because this block's total need is 0.
4362 Then some insn might have an optional reload and use this reg. */
4364 for (i = 0; i < nr; i++)
4365 /* But don't do this if the reg actually serves as an output
4366 reload reg in the current instruction. */
4368 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4370 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4371 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4372 spill_reg_store[regno + i] = 0;
4378 SET_REGNO_REG_SET (regs, regno + nr);
4381 /* Since value of X has changed,
4382 forget any value previously copied from it. */
4385 /* But don't forget a copy if this is the output reload
4386 that establishes the copy's validity. */
4388 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4389 reg_last_reload_reg[regno + nr] = 0;
4393 /* Forget the reloads marked in regset by previous function. */
4395 forget_marked_reloads (regset regs)
4398 reg_set_iterator rsi;
4399 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4401 if (reg < FIRST_PSEUDO_REGISTER
4402 /* But don't do this if the reg actually serves as an output
4403 reload reg in the current instruction. */
4405 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4407 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4408 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, reg);
4409 spill_reg_store[reg] = 0;
4412 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4413 reg_last_reload_reg[reg] = 0;
4417 /* The following HARD_REG_SETs indicate when each hard register is
4418 used for a reload of various parts of the current insn. */
4420 /* If reg is unavailable for all reloads. */
4421 static HARD_REG_SET reload_reg_unavailable;
4422 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4423 static HARD_REG_SET reload_reg_used;
4424 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4425 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4426 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4427 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4428 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4429 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4430 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4431 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4432 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4433 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4434 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4435 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4436 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4437 static HARD_REG_SET reload_reg_used_in_op_addr;
4438 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4439 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4440 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4441 static HARD_REG_SET reload_reg_used_in_insn;
4442 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4443 static HARD_REG_SET reload_reg_used_in_other_addr;
4445 /* If reg is in use as a reload reg for any sort of reload. */
4446 static HARD_REG_SET reload_reg_used_at_all;
4448 /* If reg is use as an inherited reload. We just mark the first register
4450 static HARD_REG_SET reload_reg_used_for_inherit;
4452 /* Records which hard regs are used in any way, either as explicit use or
4453 by being allocated to a pseudo during any point of the current insn. */
4454 static HARD_REG_SET reg_used_in_insn;
4456 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4457 TYPE. MODE is used to indicate how many consecutive regs are
4461 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4462 enum machine_mode mode)
4464 unsigned int nregs = hard_regno_nregs[regno][mode];
4467 for (i = regno; i < nregs + regno; i++)
4472 SET_HARD_REG_BIT (reload_reg_used, i);
4475 case RELOAD_FOR_INPUT_ADDRESS:
4476 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4479 case RELOAD_FOR_INPADDR_ADDRESS:
4480 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4483 case RELOAD_FOR_OUTPUT_ADDRESS:
4484 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4487 case RELOAD_FOR_OUTADDR_ADDRESS:
4488 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4491 case RELOAD_FOR_OPERAND_ADDRESS:
4492 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4495 case RELOAD_FOR_OPADDR_ADDR:
4496 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4499 case RELOAD_FOR_OTHER_ADDRESS:
4500 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4503 case RELOAD_FOR_INPUT:
4504 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4507 case RELOAD_FOR_OUTPUT:
4508 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4511 case RELOAD_FOR_INSN:
4512 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4516 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4520 /* Similarly, but show REGNO is no longer in use for a reload. */
4523 clear_reload_reg_in_use (unsigned int regno, int opnum,
4524 enum reload_type type, enum machine_mode mode)
4526 unsigned int nregs = hard_regno_nregs[regno][mode];
4527 unsigned int start_regno, end_regno, r;
4529 /* A complication is that for some reload types, inheritance might
4530 allow multiple reloads of the same types to share a reload register.
4531 We set check_opnum if we have to check only reloads with the same
4532 operand number, and check_any if we have to check all reloads. */
4533 int check_opnum = 0;
4535 HARD_REG_SET *used_in_set;
4540 used_in_set = &reload_reg_used;
4543 case RELOAD_FOR_INPUT_ADDRESS:
4544 used_in_set = &reload_reg_used_in_input_addr[opnum];
4547 case RELOAD_FOR_INPADDR_ADDRESS:
4549 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4552 case RELOAD_FOR_OUTPUT_ADDRESS:
4553 used_in_set = &reload_reg_used_in_output_addr[opnum];
4556 case RELOAD_FOR_OUTADDR_ADDRESS:
4558 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4561 case RELOAD_FOR_OPERAND_ADDRESS:
4562 used_in_set = &reload_reg_used_in_op_addr;
4565 case RELOAD_FOR_OPADDR_ADDR:
4567 used_in_set = &reload_reg_used_in_op_addr_reload;
4570 case RELOAD_FOR_OTHER_ADDRESS:
4571 used_in_set = &reload_reg_used_in_other_addr;
4575 case RELOAD_FOR_INPUT:
4576 used_in_set = &reload_reg_used_in_input[opnum];
4579 case RELOAD_FOR_OUTPUT:
4580 used_in_set = &reload_reg_used_in_output[opnum];
4583 case RELOAD_FOR_INSN:
4584 used_in_set = &reload_reg_used_in_insn;
4589 /* We resolve conflicts with remaining reloads of the same type by
4590 excluding the intervals of reload registers by them from the
4591 interval of freed reload registers. Since we only keep track of
4592 one set of interval bounds, we might have to exclude somewhat
4593 more than what would be necessary if we used a HARD_REG_SET here.
4594 But this should only happen very infrequently, so there should
4595 be no reason to worry about it. */
4597 start_regno = regno;
4598 end_regno = regno + nregs;
4599 if (check_opnum || check_any)
4601 for (i = n_reloads - 1; i >= 0; i--)
4603 if (rld[i].when_needed == type
4604 && (check_any || rld[i].opnum == opnum)
4607 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4608 unsigned int conflict_end
4609 = end_hard_regno (rld[i].mode, conflict_start);
4611 /* If there is an overlap with the first to-be-freed register,
4612 adjust the interval start. */
4613 if (conflict_start <= start_regno && conflict_end > start_regno)
4614 start_regno = conflict_end;
4615 /* Otherwise, if there is a conflict with one of the other
4616 to-be-freed registers, adjust the interval end. */
4617 if (conflict_start > start_regno && conflict_start < end_regno)
4618 end_regno = conflict_start;
4623 for (r = start_regno; r < end_regno; r++)
4624 CLEAR_HARD_REG_BIT (*used_in_set, r);
4627 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4628 specified by OPNUM and TYPE. */
4631 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4635 /* In use for a RELOAD_OTHER means it's not available for anything. */
4636 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4637 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4643 /* In use for anything means we can't use it for RELOAD_OTHER. */
4644 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4645 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4646 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4647 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4650 for (i = 0; i < reload_n_operands; i++)
4651 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4652 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4653 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4654 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4655 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4656 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4661 case RELOAD_FOR_INPUT:
4662 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4663 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4666 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4669 /* If it is used for some other input, can't use it. */
4670 for (i = 0; i < reload_n_operands; i++)
4671 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4674 /* If it is used in a later operand's address, can't use it. */
4675 for (i = opnum + 1; i < reload_n_operands; i++)
4676 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4677 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4682 case RELOAD_FOR_INPUT_ADDRESS:
4683 /* Can't use a register if it is used for an input address for this
4684 operand or used as an input in an earlier one. */
4685 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4686 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4689 for (i = 0; i < opnum; i++)
4690 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4695 case RELOAD_FOR_INPADDR_ADDRESS:
4696 /* Can't use a register if it is used for an input address
4697 for this operand or used as an input in an earlier
4699 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4702 for (i = 0; i < opnum; i++)
4703 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4708 case RELOAD_FOR_OUTPUT_ADDRESS:
4709 /* Can't use a register if it is used for an output address for this
4710 operand or used as an output in this or a later operand. Note
4711 that multiple output operands are emitted in reverse order, so
4712 the conflicting ones are those with lower indices. */
4713 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4716 for (i = 0; i <= opnum; i++)
4717 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4722 case RELOAD_FOR_OUTADDR_ADDRESS:
4723 /* Can't use a register if it is used for an output address
4724 for this operand or used as an output in this or a
4725 later operand. Note that multiple output operands are
4726 emitted in reverse order, so the conflicting ones are
4727 those with lower indices. */
4728 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4731 for (i = 0; i <= opnum; i++)
4732 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4737 case RELOAD_FOR_OPERAND_ADDRESS:
4738 for (i = 0; i < reload_n_operands; i++)
4739 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4742 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4743 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4745 case RELOAD_FOR_OPADDR_ADDR:
4746 for (i = 0; i < reload_n_operands; i++)
4747 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4750 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4752 case RELOAD_FOR_OUTPUT:
4753 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4754 outputs, or an operand address for this or an earlier output.
4755 Note that multiple output operands are emitted in reverse order,
4756 so the conflicting ones are those with higher indices. */
4757 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4760 for (i = 0; i < reload_n_operands; i++)
4761 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4764 for (i = opnum; i < reload_n_operands; i++)
4765 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4766 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4771 case RELOAD_FOR_INSN:
4772 for (i = 0; i < reload_n_operands; i++)
4773 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4774 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4777 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4778 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4780 case RELOAD_FOR_OTHER_ADDRESS:
4781 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4788 /* Return 1 if the value in reload reg REGNO, as used by a reload
4789 needed for the part of the insn specified by OPNUM and TYPE,
4790 is still available in REGNO at the end of the insn.
4792 We can assume that the reload reg was already tested for availability
4793 at the time it is needed, and we should not check this again,
4794 in case the reg has already been marked in use. */
4797 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4804 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4805 its value must reach the end. */
4808 /* If this use is for part of the insn,
4809 its value reaches if no subsequent part uses the same register.
4810 Just like the above function, don't try to do this with lots
4813 case RELOAD_FOR_OTHER_ADDRESS:
4814 /* Here we check for everything else, since these don't conflict
4815 with anything else and everything comes later. */
4817 for (i = 0; i < reload_n_operands; i++)
4818 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4819 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4820 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4821 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4822 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4823 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4826 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4827 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4828 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4829 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4831 case RELOAD_FOR_INPUT_ADDRESS:
4832 case RELOAD_FOR_INPADDR_ADDRESS:
4833 /* Similar, except that we check only for this and subsequent inputs
4834 and the address of only subsequent inputs and we do not need
4835 to check for RELOAD_OTHER objects since they are known not to
4838 for (i = opnum; i < reload_n_operands; i++)
4839 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4842 for (i = opnum + 1; i < reload_n_operands; i++)
4843 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4844 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4847 for (i = 0; i < reload_n_operands; i++)
4848 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4849 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4850 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4853 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4856 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4857 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4858 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4860 case RELOAD_FOR_INPUT:
4861 /* Similar to input address, except we start at the next operand for
4862 both input and input address and we do not check for
4863 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4866 for (i = opnum + 1; i < reload_n_operands; i++)
4867 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4868 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4869 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4872 /* ... fall through ... */
4874 case RELOAD_FOR_OPERAND_ADDRESS:
4875 /* Check outputs and their addresses. */
4877 for (i = 0; i < reload_n_operands; i++)
4878 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4879 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4880 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4883 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4885 case RELOAD_FOR_OPADDR_ADDR:
4886 for (i = 0; i < reload_n_operands; i++)
4887 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4888 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4889 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4892 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4893 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4894 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4896 case RELOAD_FOR_INSN:
4897 /* These conflict with other outputs with RELOAD_OTHER. So
4898 we need only check for output addresses. */
4900 opnum = reload_n_operands;
4902 /* ... fall through ... */
4904 case RELOAD_FOR_OUTPUT:
4905 case RELOAD_FOR_OUTPUT_ADDRESS:
4906 case RELOAD_FOR_OUTADDR_ADDRESS:
4907 /* We already know these can't conflict with a later output. So the
4908 only thing to check are later output addresses.
4909 Note that multiple output operands are emitted in reverse order,
4910 so the conflicting ones are those with lower indices. */
4911 for (i = 0; i < opnum; i++)
4912 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4913 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4924 /* Returns whether R1 and R2 are uniquely chained: the value of one
4925 is used by the other, and that value is not used by any other
4926 reload for this insn. This is used to partially undo the decision
4927 made in find_reloads when in the case of multiple
4928 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
4929 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
4930 reloads. This code tries to avoid the conflict created by that
4931 change. It might be cleaner to explicitly keep track of which
4932 RELOAD_FOR_OPADDR_ADDR reload is associated with which
4933 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
4934 this after the fact. */
4936 reloads_unique_chain_p (int r1, int r2)
4940 /* We only check input reloads. */
4941 if (! rld[r1].in || ! rld[r2].in)
4944 /* Avoid anything with output reloads. */
4945 if (rld[r1].out || rld[r2].out)
4948 /* "chained" means one reload is a component of the other reload,
4949 not the same as the other reload. */
4950 if (rld[r1].opnum != rld[r2].opnum
4951 || rtx_equal_p (rld[r1].in, rld[r2].in)
4952 || rld[r1].optional || rld[r2].optional
4953 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
4954 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
4957 for (i = 0; i < n_reloads; i ++)
4958 /* Look for input reloads that aren't our two */
4959 if (i != r1 && i != r2 && rld[i].in)
4961 /* If our reload is mentioned at all, it isn't a simple chain. */
4962 if (reg_mentioned_p (rld[r1].in, rld[i].in))
4968 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4971 This function uses the same algorithm as reload_reg_free_p above. */
4974 reloads_conflict (int r1, int r2)
4976 enum reload_type r1_type = rld[r1].when_needed;
4977 enum reload_type r2_type = rld[r2].when_needed;
4978 int r1_opnum = rld[r1].opnum;
4979 int r2_opnum = rld[r2].opnum;
4981 /* RELOAD_OTHER conflicts with everything. */
4982 if (r2_type == RELOAD_OTHER)
4985 /* Otherwise, check conflicts differently for each type. */
4989 case RELOAD_FOR_INPUT:
4990 return (r2_type == RELOAD_FOR_INSN
4991 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4992 || r2_type == RELOAD_FOR_OPADDR_ADDR
4993 || r2_type == RELOAD_FOR_INPUT
4994 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4995 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4996 && r2_opnum > r1_opnum));
4998 case RELOAD_FOR_INPUT_ADDRESS:
4999 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5000 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5002 case RELOAD_FOR_INPADDR_ADDRESS:
5003 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5004 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5006 case RELOAD_FOR_OUTPUT_ADDRESS:
5007 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5008 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5010 case RELOAD_FOR_OUTADDR_ADDRESS:
5011 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5012 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5014 case RELOAD_FOR_OPERAND_ADDRESS:
5015 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5016 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5017 && !reloads_unique_chain_p (r1, r2)));
5019 case RELOAD_FOR_OPADDR_ADDR:
5020 return (r2_type == RELOAD_FOR_INPUT
5021 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5023 case RELOAD_FOR_OUTPUT:
5024 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5025 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5026 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5027 && r2_opnum >= r1_opnum));
5029 case RELOAD_FOR_INSN:
5030 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5031 || r2_type == RELOAD_FOR_INSN
5032 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5034 case RELOAD_FOR_OTHER_ADDRESS:
5035 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5045 /* Indexed by reload number, 1 if incoming value
5046 inherited from previous insns. */
5047 static char reload_inherited[MAX_RELOADS];
5049 /* For an inherited reload, this is the insn the reload was inherited from,
5050 if we know it. Otherwise, this is 0. */
5051 static rtx reload_inheritance_insn[MAX_RELOADS];
5053 /* If nonzero, this is a place to get the value of the reload,
5054 rather than using reload_in. */
5055 static rtx reload_override_in[MAX_RELOADS];
5057 /* For each reload, the hard register number of the register used,
5058 or -1 if we did not need a register for this reload. */
5059 static int reload_spill_index[MAX_RELOADS];
5061 /* Subroutine of free_for_value_p, used to check a single register.
5062 START_REGNO is the starting regno of the full reload register
5063 (possibly comprising multiple hard registers) that we are considering. */
5066 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5067 enum reload_type type, rtx value, rtx out,
5068 int reloadnum, int ignore_address_reloads)
5071 /* Set if we see an input reload that must not share its reload register
5072 with any new earlyclobber, but might otherwise share the reload
5073 register with an output or input-output reload. */
5074 int check_earlyclobber = 0;
5078 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5081 if (out == const0_rtx)
5087 /* We use some pseudo 'time' value to check if the lifetimes of the
5088 new register use would overlap with the one of a previous reload
5089 that is not read-only or uses a different value.
5090 The 'time' used doesn't have to be linear in any shape or form, just
5092 Some reload types use different 'buckets' for each operand.
5093 So there are MAX_RECOG_OPERANDS different time values for each
5095 We compute TIME1 as the time when the register for the prospective
5096 new reload ceases to be live, and TIME2 for each existing
5097 reload as the time when that the reload register of that reload
5099 Where there is little to be gained by exact lifetime calculations,
5100 we just make conservative assumptions, i.e. a longer lifetime;
5101 this is done in the 'default:' cases. */
5104 case RELOAD_FOR_OTHER_ADDRESS:
5105 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5106 time1 = copy ? 0 : 1;
5109 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5111 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5112 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5113 respectively, to the time values for these, we get distinct time
5114 values. To get distinct time values for each operand, we have to
5115 multiply opnum by at least three. We round that up to four because
5116 multiply by four is often cheaper. */
5117 case RELOAD_FOR_INPADDR_ADDRESS:
5118 time1 = opnum * 4 + 2;
5120 case RELOAD_FOR_INPUT_ADDRESS:
5121 time1 = opnum * 4 + 3;
5123 case RELOAD_FOR_INPUT:
5124 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5125 executes (inclusive). */
5126 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5128 case RELOAD_FOR_OPADDR_ADDR:
5130 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5131 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5133 case RELOAD_FOR_OPERAND_ADDRESS:
5134 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5136 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5138 case RELOAD_FOR_OUTADDR_ADDRESS:
5139 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5141 case RELOAD_FOR_OUTPUT_ADDRESS:
5142 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5145 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5148 for (i = 0; i < n_reloads; i++)
5150 rtx reg = rld[i].reg_rtx;
5151 if (reg && REG_P (reg)
5152 && ((unsigned) regno - true_regnum (reg)
5153 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5156 rtx other_input = rld[i].in;
5158 /* If the other reload loads the same input value, that
5159 will not cause a conflict only if it's loading it into
5160 the same register. */
5161 if (true_regnum (reg) != start_regno)
5162 other_input = NULL_RTX;
5163 if (! other_input || ! rtx_equal_p (other_input, value)
5164 || rld[i].out || out)
5167 switch (rld[i].when_needed)
5169 case RELOAD_FOR_OTHER_ADDRESS:
5172 case RELOAD_FOR_INPADDR_ADDRESS:
5173 /* find_reloads makes sure that a
5174 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5175 by at most one - the first -
5176 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5177 address reload is inherited, the address address reload
5178 goes away, so we can ignore this conflict. */
5179 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5180 && ignore_address_reloads
5181 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5182 Then the address address is still needed to store
5183 back the new address. */
5184 && ! rld[reloadnum].out)
5186 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5187 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5189 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5190 && ignore_address_reloads
5191 /* Unless we are reloading an auto_inc expression. */
5192 && ! rld[reloadnum].out)
5194 time2 = rld[i].opnum * 4 + 2;
5196 case RELOAD_FOR_INPUT_ADDRESS:
5197 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5198 && ignore_address_reloads
5199 && ! rld[reloadnum].out)
5201 time2 = rld[i].opnum * 4 + 3;
5203 case RELOAD_FOR_INPUT:
5204 time2 = rld[i].opnum * 4 + 4;
5205 check_earlyclobber = 1;
5207 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5208 == MAX_RECOG_OPERAND * 4 */
5209 case RELOAD_FOR_OPADDR_ADDR:
5210 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5211 && ignore_address_reloads
5212 && ! rld[reloadnum].out)
5214 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5216 case RELOAD_FOR_OPERAND_ADDRESS:
5217 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5218 check_earlyclobber = 1;
5220 case RELOAD_FOR_INSN:
5221 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5223 case RELOAD_FOR_OUTPUT:
5224 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5225 instruction is executed. */
5226 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5228 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5229 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5231 case RELOAD_FOR_OUTADDR_ADDRESS:
5232 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5233 && ignore_address_reloads
5234 && ! rld[reloadnum].out)
5236 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5238 case RELOAD_FOR_OUTPUT_ADDRESS:
5239 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5242 /* If there is no conflict in the input part, handle this
5243 like an output reload. */
5244 if (! rld[i].in || rtx_equal_p (other_input, value))
5246 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5247 /* Earlyclobbered outputs must conflict with inputs. */
5248 if (earlyclobber_operand_p (rld[i].out))
5249 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5254 /* RELOAD_OTHER might be live beyond instruction execution,
5255 but this is not obvious when we set time2 = 1. So check
5256 here if there might be a problem with the new reload
5257 clobbering the register used by the RELOAD_OTHER. */
5265 && (! rld[i].in || rld[i].out
5266 || ! rtx_equal_p (other_input, value)))
5267 || (out && rld[reloadnum].out_reg
5268 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5274 /* Earlyclobbered outputs must conflict with inputs. */
5275 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5281 /* Return 1 if the value in reload reg REGNO, as used by a reload
5282 needed for the part of the insn specified by OPNUM and TYPE,
5283 may be used to load VALUE into it.
5285 MODE is the mode in which the register is used, this is needed to
5286 determine how many hard regs to test.
5288 Other read-only reloads with the same value do not conflict
5289 unless OUT is nonzero and these other reloads have to live while
5290 output reloads live.
5291 If OUT is CONST0_RTX, this is a special case: it means that the
5292 test should not be for using register REGNO as reload register, but
5293 for copying from register REGNO into the reload register.
5295 RELOADNUM is the number of the reload we want to load this value for;
5296 a reload does not conflict with itself.
5298 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5299 reloads that load an address for the very reload we are considering.
5301 The caller has to make sure that there is no conflict with the return
5305 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5306 enum reload_type type, rtx value, rtx out, int reloadnum,
5307 int ignore_address_reloads)
5309 int nregs = hard_regno_nregs[regno][mode];
5311 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5312 value, out, reloadnum,
5313 ignore_address_reloads))
5318 /* Return nonzero if the rtx X is invariant over the current function. */
5319 /* ??? Actually, the places where we use this expect exactly what is
5320 tested here, and not everything that is function invariant. In
5321 particular, the frame pointer and arg pointer are special cased;
5322 pic_offset_table_rtx is not, and we must not spill these things to
5326 function_invariant_p (const_rtx x)
5330 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5332 if (GET_CODE (x) == PLUS
5333 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5334 && CONSTANT_P (XEXP (x, 1)))
5339 /* Determine whether the reload reg X overlaps any rtx'es used for
5340 overriding inheritance. Return nonzero if so. */
5343 conflicts_with_override (rtx x)
5346 for (i = 0; i < n_reloads; i++)
5347 if (reload_override_in[i]
5348 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5353 /* Give an error message saying we failed to find a reload for INSN,
5354 and clear out reload R. */
5356 failed_reload (rtx insn, int r)
5358 if (asm_noperands (PATTERN (insn)) < 0)
5359 /* It's the compiler's fault. */
5360 fatal_insn ("could not find a spill register", insn);
5362 /* It's the user's fault; the operand's mode and constraint
5363 don't match. Disable this reload so we don't crash in final. */
5364 error_for_asm (insn,
5365 "%<asm%> operand constraint incompatible with operand size");
5369 rld[r].optional = 1;
5370 rld[r].secondary_p = 1;
5373 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5374 for reload R. If it's valid, get an rtx for it. Return nonzero if
5377 set_reload_reg (int i, int r)
5380 rtx reg = spill_reg_rtx[i];
5382 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5383 spill_reg_rtx[i] = reg
5384 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5386 regno = true_regnum (reg);
5388 /* Detect when the reload reg can't hold the reload mode.
5389 This used to be one `if', but Sequent compiler can't handle that. */
5390 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5392 enum machine_mode test_mode = VOIDmode;
5394 test_mode = GET_MODE (rld[r].in);
5395 /* If rld[r].in has VOIDmode, it means we will load it
5396 in whatever mode the reload reg has: to wit, rld[r].mode.
5397 We have already tested that for validity. */
5398 /* Aside from that, we need to test that the expressions
5399 to reload from or into have modes which are valid for this
5400 reload register. Otherwise the reload insns would be invalid. */
5401 if (! (rld[r].in != 0 && test_mode != VOIDmode
5402 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5403 if (! (rld[r].out != 0
5404 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5406 /* The reg is OK. */
5409 /* Mark as in use for this insn the reload regs we use
5411 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5412 rld[r].when_needed, rld[r].mode);
5414 rld[r].reg_rtx = reg;
5415 reload_spill_index[r] = spill_regs[i];
5422 /* Find a spill register to use as a reload register for reload R.
5423 LAST_RELOAD is nonzero if this is the last reload for the insn being
5426 Set rld[R].reg_rtx to the register allocated.
5428 We return 1 if successful, or 0 if we couldn't find a spill reg and
5429 we didn't change anything. */
5432 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5437 /* If we put this reload ahead, thinking it is a group,
5438 then insist on finding a group. Otherwise we can grab a
5439 reg that some other reload needs.
5440 (That can happen when we have a 68000 DATA_OR_FP_REG
5441 which is a group of data regs or one fp reg.)
5442 We need not be so restrictive if there are no more reloads
5445 ??? Really it would be nicer to have smarter handling
5446 for that kind of reg class, where a problem like this is normal.
5447 Perhaps those classes should be avoided for reloading
5448 by use of more alternatives. */
5450 int force_group = rld[r].nregs > 1 && ! last_reload;
5452 /* If we want a single register and haven't yet found one,
5453 take any reg in the right class and not in use.
5454 If we want a consecutive group, here is where we look for it.
5456 We use two passes so we can first look for reload regs to
5457 reuse, which are already in use for other reloads in this insn,
5458 and only then use additional registers.
5459 I think that maximizing reuse is needed to make sure we don't
5460 run out of reload regs. Suppose we have three reloads, and
5461 reloads A and B can share regs. These need two regs.
5462 Suppose A and B are given different regs.
5463 That leaves none for C. */
5464 for (pass = 0; pass < 2; pass++)
5466 /* I is the index in spill_regs.
5467 We advance it round-robin between insns to use all spill regs
5468 equally, so that inherited reloads have a chance
5469 of leapfrogging each other. */
5473 for (count = 0; count < n_spills; count++)
5475 int class = (int) rld[r].class;
5481 regnum = spill_regs[i];
5483 if ((reload_reg_free_p (regnum, rld[r].opnum,
5486 /* We check reload_reg_used to make sure we
5487 don't clobber the return register. */
5488 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5489 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5490 rld[r].when_needed, rld[r].in,
5492 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5493 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5494 /* Look first for regs to share, then for unshared. But
5495 don't share regs used for inherited reloads; they are
5496 the ones we want to preserve. */
5498 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5500 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5503 int nr = hard_regno_nregs[regnum][rld[r].mode];
5504 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5505 (on 68000) got us two FP regs. If NR is 1,
5506 we would reject both of them. */
5509 /* If we need only one reg, we have already won. */
5512 /* But reject a single reg if we demand a group. */
5517 /* Otherwise check that as many consecutive regs as we need
5518 are available here. */
5521 int regno = regnum + nr - 1;
5522 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5523 && spill_reg_order[regno] >= 0
5524 && reload_reg_free_p (regno, rld[r].opnum,
5525 rld[r].when_needed)))
5534 /* If we found something on pass 1, omit pass 2. */
5535 if (count < n_spills)
5539 /* We should have found a spill register by now. */
5540 if (count >= n_spills)
5543 /* I is the index in SPILL_REG_RTX of the reload register we are to
5544 allocate. Get an rtx for it and find its register number. */
5546 return set_reload_reg (i, r);
5549 /* Initialize all the tables needed to allocate reload registers.
5550 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5551 is the array we use to restore the reg_rtx field for every reload. */
5554 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5558 for (i = 0; i < n_reloads; i++)
5559 rld[i].reg_rtx = save_reload_reg_rtx[i];
5561 memset (reload_inherited, 0, MAX_RELOADS);
5562 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5563 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5565 CLEAR_HARD_REG_SET (reload_reg_used);
5566 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5567 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5568 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5569 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5570 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5572 CLEAR_HARD_REG_SET (reg_used_in_insn);
5575 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5576 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5577 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5578 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5579 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5580 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5583 for (i = 0; i < reload_n_operands; i++)
5585 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5586 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5587 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5588 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5589 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5590 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5593 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5595 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5597 for (i = 0; i < n_reloads; i++)
5598 /* If we have already decided to use a certain register,
5599 don't use it in another way. */
5601 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5602 rld[i].when_needed, rld[i].mode);
5605 /* Assign hard reg targets for the pseudo-registers we must reload
5606 into hard regs for this insn.
5607 Also output the instructions to copy them in and out of the hard regs.
5609 For machines with register classes, we are responsible for
5610 finding a reload reg in the proper class. */
5613 choose_reload_regs (struct insn_chain *chain)
5615 rtx insn = chain->insn;
5617 unsigned int max_group_size = 1;
5618 enum reg_class group_class = NO_REGS;
5619 int pass, win, inheritance;
5621 rtx save_reload_reg_rtx[MAX_RELOADS];
5623 /* In order to be certain of getting the registers we need,
5624 we must sort the reloads into order of increasing register class.
5625 Then our grabbing of reload registers will parallel the process
5626 that provided the reload registers.
5628 Also note whether any of the reloads wants a consecutive group of regs.
5629 If so, record the maximum size of the group desired and what
5630 register class contains all the groups needed by this insn. */
5632 for (j = 0; j < n_reloads; j++)
5634 reload_order[j] = j;
5635 if (rld[j].reg_rtx != NULL_RTX)
5637 gcc_assert (REG_P (rld[j].reg_rtx)
5638 && HARD_REGISTER_P (rld[j].reg_rtx));
5639 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
5642 reload_spill_index[j] = -1;
5644 if (rld[j].nregs > 1)
5646 max_group_size = MAX (rld[j].nregs, max_group_size);
5648 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5651 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5655 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5657 /* If -O, try first with inheritance, then turning it off.
5658 If not -O, don't do inheritance.
5659 Using inheritance when not optimizing leads to paradoxes
5660 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5661 because one side of the comparison might be inherited. */
5663 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5665 choose_reload_regs_init (chain, save_reload_reg_rtx);
5667 /* Process the reloads in order of preference just found.
5668 Beyond this point, subregs can be found in reload_reg_rtx.
5670 This used to look for an existing reloaded home for all of the
5671 reloads, and only then perform any new reloads. But that could lose
5672 if the reloads were done out of reg-class order because a later
5673 reload with a looser constraint might have an old home in a register
5674 needed by an earlier reload with a tighter constraint.
5676 To solve this, we make two passes over the reloads, in the order
5677 described above. In the first pass we try to inherit a reload
5678 from a previous insn. If there is a later reload that needs a
5679 class that is a proper subset of the class being processed, we must
5680 also allocate a spill register during the first pass.
5682 Then make a second pass over the reloads to allocate any reloads
5683 that haven't been given registers yet. */
5685 for (j = 0; j < n_reloads; j++)
5687 int r = reload_order[j];
5688 rtx search_equiv = NULL_RTX;
5690 /* Ignore reloads that got marked inoperative. */
5691 if (rld[r].out == 0 && rld[r].in == 0
5692 && ! rld[r].secondary_p)
5695 /* If find_reloads chose to use reload_in or reload_out as a reload
5696 register, we don't need to chose one. Otherwise, try even if it
5697 found one since we might save an insn if we find the value lying
5699 Try also when reload_in is a pseudo without a hard reg. */
5700 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5701 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5702 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5703 && !MEM_P (rld[r].in)
5704 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5707 #if 0 /* No longer needed for correct operation.
5708 It might give better code, or might not; worth an experiment? */
5709 /* If this is an optional reload, we can't inherit from earlier insns
5710 until we are sure that any non-optional reloads have been allocated.
5711 The following code takes advantage of the fact that optional reloads
5712 are at the end of reload_order. */
5713 if (rld[r].optional != 0)
5714 for (i = 0; i < j; i++)
5715 if ((rld[reload_order[i]].out != 0
5716 || rld[reload_order[i]].in != 0
5717 || rld[reload_order[i]].secondary_p)
5718 && ! rld[reload_order[i]].optional
5719 && rld[reload_order[i]].reg_rtx == 0)
5720 allocate_reload_reg (chain, reload_order[i], 0);
5723 /* First see if this pseudo is already available as reloaded
5724 for a previous insn. We cannot try to inherit for reloads
5725 that are smaller than the maximum number of registers needed
5726 for groups unless the register we would allocate cannot be used
5729 We could check here to see if this is a secondary reload for
5730 an object that is already in a register of the desired class.
5731 This would avoid the need for the secondary reload register.
5732 But this is complex because we can't easily determine what
5733 objects might want to be loaded via this reload. So let a
5734 register be allocated here. In `emit_reload_insns' we suppress
5735 one of the loads in the case described above. */
5741 enum machine_mode mode = VOIDmode;
5745 else if (REG_P (rld[r].in))
5747 regno = REGNO (rld[r].in);
5748 mode = GET_MODE (rld[r].in);
5750 else if (REG_P (rld[r].in_reg))
5752 regno = REGNO (rld[r].in_reg);
5753 mode = GET_MODE (rld[r].in_reg);
5755 else if (GET_CODE (rld[r].in_reg) == SUBREG
5756 && REG_P (SUBREG_REG (rld[r].in_reg)))
5758 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5759 if (regno < FIRST_PSEUDO_REGISTER)
5760 regno = subreg_regno (rld[r].in_reg);
5762 byte = SUBREG_BYTE (rld[r].in_reg);
5763 mode = GET_MODE (rld[r].in_reg);
5766 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
5767 && REG_P (XEXP (rld[r].in_reg, 0)))
5769 regno = REGNO (XEXP (rld[r].in_reg, 0));
5770 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5771 rld[r].out = rld[r].in;
5775 /* This won't work, since REGNO can be a pseudo reg number.
5776 Also, it takes much more hair to keep track of all the things
5777 that can invalidate an inherited reload of part of a pseudoreg. */
5778 else if (GET_CODE (rld[r].in) == SUBREG
5779 && REG_P (SUBREG_REG (rld[r].in)))
5780 regno = subreg_regno (rld[r].in);
5784 && reg_last_reload_reg[regno] != 0
5785 #ifdef CANNOT_CHANGE_MODE_CLASS
5786 /* Verify that the register it's in can be used in
5788 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
5789 GET_MODE (reg_last_reload_reg[regno]),
5794 enum reg_class class = rld[r].class, last_class;
5795 rtx last_reg = reg_last_reload_reg[regno];
5796 enum machine_mode need_mode;
5798 i = REGNO (last_reg);
5799 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5800 last_class = REGNO_REG_CLASS (i);
5806 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
5807 + byte * BITS_PER_UNIT,
5808 GET_MODE_CLASS (mode));
5810 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5811 >= GET_MODE_SIZE (need_mode))
5812 && reg_reloaded_contents[i] == regno
5813 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5814 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5815 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5816 /* Even if we can't use this register as a reload
5817 register, we might use it for reload_override_in,
5818 if copying it to the desired class is cheap
5820 || ((REGISTER_MOVE_COST (mode, last_class, class)
5821 < MEMORY_MOVE_COST (mode, class, 1))
5822 && (secondary_reload_class (1, class, mode,
5825 #ifdef SECONDARY_MEMORY_NEEDED
5826 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5831 && (rld[r].nregs == max_group_size
5832 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5834 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5835 rld[r].when_needed, rld[r].in,
5838 /* If a group is needed, verify that all the subsequent
5839 registers still have their values intact. */
5840 int nr = hard_regno_nregs[i][rld[r].mode];
5843 for (k = 1; k < nr; k++)
5844 if (reg_reloaded_contents[i + k] != regno
5845 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5853 last_reg = (GET_MODE (last_reg) == mode
5854 ? last_reg : gen_rtx_REG (mode, i));
5857 for (k = 0; k < nr; k++)
5858 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5861 /* We found a register that contains the
5862 value we need. If this register is the
5863 same as an `earlyclobber' operand of the
5864 current insn, just mark it as a place to
5865 reload from since we can't use it as the
5866 reload register itself. */
5868 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5869 if (reg_overlap_mentioned_for_reload_p
5870 (reg_last_reload_reg[regno],
5871 reload_earlyclobbers[i1]))
5874 if (i1 != n_earlyclobbers
5875 || ! (free_for_value_p (i, rld[r].mode,
5877 rld[r].when_needed, rld[r].in,
5879 /* Don't use it if we'd clobber a pseudo reg. */
5880 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5882 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5883 /* Don't clobber the frame pointer. */
5884 || (i == HARD_FRAME_POINTER_REGNUM
5885 && frame_pointer_needed
5887 /* Don't really use the inherited spill reg
5888 if we need it wider than we've got it. */
5889 || (GET_MODE_SIZE (rld[r].mode)
5890 > GET_MODE_SIZE (mode))
5893 /* If find_reloads chose reload_out as reload
5894 register, stay with it - that leaves the
5895 inherited register for subsequent reloads. */
5896 || (rld[r].out && rld[r].reg_rtx
5897 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5899 if (! rld[r].optional)
5901 reload_override_in[r] = last_reg;
5902 reload_inheritance_insn[r]
5903 = reg_reloaded_insn[i];
5909 /* We can use this as a reload reg. */
5910 /* Mark the register as in use for this part of
5912 mark_reload_reg_in_use (i,
5916 rld[r].reg_rtx = last_reg;
5917 reload_inherited[r] = 1;
5918 reload_inheritance_insn[r]
5919 = reg_reloaded_insn[i];
5920 reload_spill_index[r] = i;
5921 for (k = 0; k < nr; k++)
5922 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5930 /* Here's another way to see if the value is already lying around. */
5933 && ! reload_inherited[r]
5935 && (CONSTANT_P (rld[r].in)
5936 || GET_CODE (rld[r].in) == PLUS
5937 || REG_P (rld[r].in)
5938 || MEM_P (rld[r].in))
5939 && (rld[r].nregs == max_group_size
5940 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5941 search_equiv = rld[r].in;
5942 /* If this is an output reload from a simple move insn, look
5943 if an equivalence for the input is available. */
5944 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5946 rtx set = single_set (insn);
5949 && rtx_equal_p (rld[r].out, SET_DEST (set))
5950 && CONSTANT_P (SET_SRC (set)))
5951 search_equiv = SET_SRC (set);
5957 = find_equiv_reg (search_equiv, insn, rld[r].class,
5958 -1, NULL, 0, rld[r].mode);
5964 regno = REGNO (equiv);
5967 /* This must be a SUBREG of a hard register.
5968 Make a new REG since this might be used in an
5969 address and not all machines support SUBREGs
5971 gcc_assert (GET_CODE (equiv) == SUBREG);
5972 regno = subreg_regno (equiv);
5973 equiv = gen_rtx_REG (rld[r].mode, regno);
5974 /* If we choose EQUIV as the reload register, but the
5975 loop below decides to cancel the inheritance, we'll
5976 end up reloading EQUIV in rld[r].mode, not the mode
5977 it had originally. That isn't safe when EQUIV isn't
5978 available as a spill register since its value might
5979 still be live at this point. */
5980 for (i = regno; i < regno + (int) rld[r].nregs; i++)
5981 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
5986 /* If we found a spill reg, reject it unless it is free
5987 and of the desired class. */
5991 int bad_for_class = 0;
5992 int max_regno = regno + rld[r].nregs;
5994 for (i = regno; i < max_regno; i++)
5996 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5998 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
6003 && ! free_for_value_p (regno, rld[r].mode,
6004 rld[r].opnum, rld[r].when_needed,
6005 rld[r].in, rld[r].out, r, 1))
6010 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6013 /* We found a register that contains the value we need.
6014 If this register is the same as an `earlyclobber' operand
6015 of the current insn, just mark it as a place to reload from
6016 since we can't use it as the reload register itself. */
6019 for (i = 0; i < n_earlyclobbers; i++)
6020 if (reg_overlap_mentioned_for_reload_p (equiv,
6021 reload_earlyclobbers[i]))
6023 if (! rld[r].optional)
6024 reload_override_in[r] = equiv;
6029 /* If the equiv register we have found is explicitly clobbered
6030 in the current insn, it depends on the reload type if we
6031 can use it, use it for reload_override_in, or not at all.
6032 In particular, we then can't use EQUIV for a
6033 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6037 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6038 switch (rld[r].when_needed)
6040 case RELOAD_FOR_OTHER_ADDRESS:
6041 case RELOAD_FOR_INPADDR_ADDRESS:
6042 case RELOAD_FOR_INPUT_ADDRESS:
6043 case RELOAD_FOR_OPADDR_ADDR:
6046 case RELOAD_FOR_INPUT:
6047 case RELOAD_FOR_OPERAND_ADDRESS:
6048 if (! rld[r].optional)
6049 reload_override_in[r] = equiv;
6055 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6056 switch (rld[r].when_needed)
6058 case RELOAD_FOR_OTHER_ADDRESS:
6059 case RELOAD_FOR_INPADDR_ADDRESS:
6060 case RELOAD_FOR_INPUT_ADDRESS:
6061 case RELOAD_FOR_OPADDR_ADDR:
6062 case RELOAD_FOR_OPERAND_ADDRESS:
6063 case RELOAD_FOR_INPUT:
6066 if (! rld[r].optional)
6067 reload_override_in[r] = equiv;
6075 /* If we found an equivalent reg, say no code need be generated
6076 to load it, and use it as our reload reg. */
6078 && (regno != HARD_FRAME_POINTER_REGNUM
6079 || !frame_pointer_needed))
6081 int nr = hard_regno_nregs[regno][rld[r].mode];
6083 rld[r].reg_rtx = equiv;
6084 reload_inherited[r] = 1;
6086 /* If reg_reloaded_valid is not set for this register,
6087 there might be a stale spill_reg_store lying around.
6088 We must clear it, since otherwise emit_reload_insns
6089 might delete the store. */
6090 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6091 spill_reg_store[regno] = NULL_RTX;
6092 /* If any of the hard registers in EQUIV are spill
6093 registers, mark them as in use for this insn. */
6094 for (k = 0; k < nr; k++)
6096 i = spill_reg_order[regno + k];
6099 mark_reload_reg_in_use (regno, rld[r].opnum,
6102 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6109 /* If we found a register to use already, or if this is an optional
6110 reload, we are done. */
6111 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6115 /* No longer needed for correct operation. Might or might
6116 not give better code on the average. Want to experiment? */
6118 /* See if there is a later reload that has a class different from our
6119 class that intersects our class or that requires less register
6120 than our reload. If so, we must allocate a register to this
6121 reload now, since that reload might inherit a previous reload
6122 and take the only available register in our class. Don't do this
6123 for optional reloads since they will force all previous reloads
6124 to be allocated. Also don't do this for reloads that have been
6127 for (i = j + 1; i < n_reloads; i++)
6129 int s = reload_order[i];
6131 if ((rld[s].in == 0 && rld[s].out == 0
6132 && ! rld[s].secondary_p)
6136 if ((rld[s].class != rld[r].class
6137 && reg_classes_intersect_p (rld[r].class,
6139 || rld[s].nregs < rld[r].nregs)
6146 allocate_reload_reg (chain, r, j == n_reloads - 1);
6150 /* Now allocate reload registers for anything non-optional that
6151 didn't get one yet. */
6152 for (j = 0; j < n_reloads; j++)
6154 int r = reload_order[j];
6156 /* Ignore reloads that got marked inoperative. */
6157 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6160 /* Skip reloads that already have a register allocated or are
6162 if (rld[r].reg_rtx != 0 || rld[r].optional)
6165 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6169 /* If that loop got all the way, we have won. */
6176 /* Loop around and try without any inheritance. */
6181 /* First undo everything done by the failed attempt
6182 to allocate with inheritance. */
6183 choose_reload_regs_init (chain, save_reload_reg_rtx);
6185 /* Some sanity tests to verify that the reloads found in the first
6186 pass are identical to the ones we have now. */
6187 gcc_assert (chain->n_reloads == n_reloads);
6189 for (i = 0; i < n_reloads; i++)
6191 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6193 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6194 for (j = 0; j < n_spills; j++)
6195 if (spill_regs[j] == chain->rld[i].regno)
6196 if (! set_reload_reg (j, i))
6197 failed_reload (chain->insn, i);
6201 /* If we thought we could inherit a reload, because it seemed that
6202 nothing else wanted the same reload register earlier in the insn,
6203 verify that assumption, now that all reloads have been assigned.
6204 Likewise for reloads where reload_override_in has been set. */
6206 /* If doing expensive optimizations, do one preliminary pass that doesn't
6207 cancel any inheritance, but removes reloads that have been needed only
6208 for reloads that we know can be inherited. */
6209 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6211 for (j = 0; j < n_reloads; j++)
6213 int r = reload_order[j];
6215 if (reload_inherited[r] && rld[r].reg_rtx)
6216 check_reg = rld[r].reg_rtx;
6217 else if (reload_override_in[r]
6218 && (REG_P (reload_override_in[r])
6219 || GET_CODE (reload_override_in[r]) == SUBREG))
6220 check_reg = reload_override_in[r];
6223 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6224 rld[r].opnum, rld[r].when_needed, rld[r].in,
6225 (reload_inherited[r]
6226 ? rld[r].out : const0_rtx),
6231 reload_inherited[r] = 0;
6232 reload_override_in[r] = 0;
6234 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6235 reload_override_in, then we do not need its related
6236 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6237 likewise for other reload types.
6238 We handle this by removing a reload when its only replacement
6239 is mentioned in reload_in of the reload we are going to inherit.
6240 A special case are auto_inc expressions; even if the input is
6241 inherited, we still need the address for the output. We can
6242 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6243 If we succeeded removing some reload and we are doing a preliminary
6244 pass just to remove such reloads, make another pass, since the
6245 removal of one reload might allow us to inherit another one. */
6247 && rld[r].out != rld[r].in
6248 && remove_address_replacements (rld[r].in) && pass)
6253 /* Now that reload_override_in is known valid,
6254 actually override reload_in. */
6255 for (j = 0; j < n_reloads; j++)
6256 if (reload_override_in[j])
6257 rld[j].in = reload_override_in[j];
6259 /* If this reload won't be done because it has been canceled or is
6260 optional and not inherited, clear reload_reg_rtx so other
6261 routines (such as subst_reloads) don't get confused. */
6262 for (j = 0; j < n_reloads; j++)
6263 if (rld[j].reg_rtx != 0
6264 && ((rld[j].optional && ! reload_inherited[j])
6265 || (rld[j].in == 0 && rld[j].out == 0
6266 && ! rld[j].secondary_p)))
6268 int regno = true_regnum (rld[j].reg_rtx);
6270 if (spill_reg_order[regno] >= 0)
6271 clear_reload_reg_in_use (regno, rld[j].opnum,
6272 rld[j].when_needed, rld[j].mode);
6274 reload_spill_index[j] = -1;
6277 /* Record which pseudos and which spill regs have output reloads. */
6278 for (j = 0; j < n_reloads; j++)
6280 int r = reload_order[j];
6282 i = reload_spill_index[r];
6284 /* I is nonneg if this reload uses a register.
6285 If rld[r].reg_rtx is 0, this is an optional reload
6286 that we opted to ignore. */
6287 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6288 && rld[r].reg_rtx != 0)
6290 int nregno = REGNO (rld[r].out_reg);
6293 if (nregno < FIRST_PSEUDO_REGISTER)
6294 nr = hard_regno_nregs[nregno][rld[r].mode];
6297 SET_REGNO_REG_SET (®_has_output_reload,
6302 nr = hard_regno_nregs[i][rld[r].mode];
6304 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6307 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6308 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6309 || rld[r].when_needed == RELOAD_FOR_INSN);
6314 /* Deallocate the reload register for reload R. This is called from
6315 remove_address_replacements. */
6318 deallocate_reload_reg (int r)
6322 if (! rld[r].reg_rtx)
6324 regno = true_regnum (rld[r].reg_rtx);
6326 if (spill_reg_order[regno] >= 0)
6327 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6329 reload_spill_index[r] = -1;
6332 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6333 reloads of the same item for fear that we might not have enough reload
6334 registers. However, normally they will get the same reload register
6335 and hence actually need not be loaded twice.
6337 Here we check for the most common case of this phenomenon: when we have
6338 a number of reloads for the same object, each of which were allocated
6339 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6340 reload, and is not modified in the insn itself. If we find such,
6341 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6342 This will not increase the number of spill registers needed and will
6343 prevent redundant code. */
6346 merge_assigned_reloads (rtx insn)
6350 /* Scan all the reloads looking for ones that only load values and
6351 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6352 assigned and not modified by INSN. */
6354 for (i = 0; i < n_reloads; i++)
6356 int conflicting_input = 0;
6357 int max_input_address_opnum = -1;
6358 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6360 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6361 || rld[i].out != 0 || rld[i].reg_rtx == 0
6362 || reg_set_p (rld[i].reg_rtx, insn))
6365 /* Look at all other reloads. Ensure that the only use of this
6366 reload_reg_rtx is in a reload that just loads the same value
6367 as we do. Note that any secondary reloads must be of the identical
6368 class since the values, modes, and result registers are the
6369 same, so we need not do anything with any secondary reloads. */
6371 for (j = 0; j < n_reloads; j++)
6373 if (i == j || rld[j].reg_rtx == 0
6374 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6378 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6379 && rld[j].opnum > max_input_address_opnum)
6380 max_input_address_opnum = rld[j].opnum;
6382 /* If the reload regs aren't exactly the same (e.g, different modes)
6383 or if the values are different, we can't merge this reload.
6384 But if it is an input reload, we might still merge
6385 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6387 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6388 || rld[j].out != 0 || rld[j].in == 0
6389 || ! rtx_equal_p (rld[i].in, rld[j].in))
6391 if (rld[j].when_needed != RELOAD_FOR_INPUT
6392 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6393 || rld[i].opnum > rld[j].opnum)
6394 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6396 conflicting_input = 1;
6397 if (min_conflicting_input_opnum > rld[j].opnum)
6398 min_conflicting_input_opnum = rld[j].opnum;
6402 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6403 we, in fact, found any matching reloads. */
6406 && max_input_address_opnum <= min_conflicting_input_opnum)
6408 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6410 for (j = 0; j < n_reloads; j++)
6411 if (i != j && rld[j].reg_rtx != 0
6412 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6413 && (! conflicting_input
6414 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6415 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6417 rld[i].when_needed = RELOAD_OTHER;
6419 reload_spill_index[j] = -1;
6420 transfer_replacements (i, j);
6423 /* If this is now RELOAD_OTHER, look for any reloads that
6424 load parts of this operand and set them to
6425 RELOAD_FOR_OTHER_ADDRESS if they were for inputs,
6426 RELOAD_OTHER for outputs. Note that this test is
6427 equivalent to looking for reloads for this operand
6430 We must take special care with RELOAD_FOR_OUTPUT_ADDRESS;
6431 it may share registers with a RELOAD_FOR_INPUT, so we can
6432 not change it to RELOAD_FOR_OTHER_ADDRESS. We should
6433 never need to, since we do not modify RELOAD_FOR_OUTPUT.
6435 It is possible that the RELOAD_FOR_OPERAND_ADDRESS
6436 instruction is assigned the same register as the earlier
6437 RELOAD_FOR_OTHER_ADDRESS instruction. Merging these two
6438 instructions will cause the RELOAD_FOR_OTHER_ADDRESS
6439 instruction to be deleted later on. */
6441 if (rld[i].when_needed == RELOAD_OTHER)
6442 for (j = 0; j < n_reloads; j++)
6444 && rld[j].when_needed != RELOAD_OTHER
6445 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6446 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6447 && rld[j].when_needed != RELOAD_FOR_OPERAND_ADDRESS
6448 && (! conflicting_input
6449 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6450 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6451 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6457 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6458 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6459 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6461 /* Check to see if we accidentally converted two
6462 reloads that use the same reload register with
6463 different inputs to the same type. If so, the
6464 resulting code won't work. */
6466 for (k = 0; k < j; k++)
6467 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6468 || rld[k].when_needed != rld[j].when_needed
6469 || !rtx_equal_p (rld[k].reg_rtx,
6471 || rtx_equal_p (rld[k].in,
6478 /* These arrays are filled by emit_reload_insns and its subroutines. */
6479 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6480 static rtx other_input_address_reload_insns = 0;
6481 static rtx other_input_reload_insns = 0;
6482 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6483 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6484 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6485 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6486 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6487 static rtx operand_reload_insns = 0;
6488 static rtx other_operand_reload_insns = 0;
6489 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6491 /* Values to be put in spill_reg_store are put here first. */
6492 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6493 static HARD_REG_SET reg_reloaded_died;
6495 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6496 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6497 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6498 adjusted register, and return true. Otherwise, return false. */
6500 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6501 enum reg_class new_class,
6502 enum machine_mode new_mode)
6507 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6509 unsigned regno = REGNO (reg);
6511 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6513 if (GET_MODE (reg) != new_mode)
6515 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6517 if (hard_regno_nregs[regno][new_mode]
6518 > hard_regno_nregs[regno][GET_MODE (reg)])
6520 reg = reload_adjust_reg_for_mode (reg, new_mode);
6528 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6529 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6530 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6531 adjusted register, and return true. Otherwise, return false. */
6533 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6534 enum insn_code icode)
6537 enum reg_class new_class = scratch_reload_class (icode);
6538 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6540 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6541 new_class, new_mode);
6544 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6545 has the number J. OLD contains the value to be used as input. */
6548 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6551 rtx insn = chain->insn;
6552 rtx reloadreg = rl->reg_rtx;
6553 rtx oldequiv_reg = 0;
6556 enum machine_mode mode;
6559 /* Determine the mode to reload in.
6560 This is very tricky because we have three to choose from.
6561 There is the mode the insn operand wants (rl->inmode).
6562 There is the mode of the reload register RELOADREG.
6563 There is the intrinsic mode of the operand, which we could find
6564 by stripping some SUBREGs.
6565 It turns out that RELOADREG's mode is irrelevant:
6566 we can change that arbitrarily.
6568 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6569 then the reload reg may not support QImode moves, so use SImode.
6570 If foo is in memory due to spilling a pseudo reg, this is safe,
6571 because the QImode value is in the least significant part of a
6572 slot big enough for a SImode. If foo is some other sort of
6573 memory reference, then it is impossible to reload this case,
6574 so previous passes had better make sure this never happens.
6576 Then consider a one-word union which has SImode and one of its
6577 members is a float, being fetched as (SUBREG:SF union:SI).
6578 We must fetch that as SFmode because we could be loading into
6579 a float-only register. In this case OLD's mode is correct.
6581 Consider an immediate integer: it has VOIDmode. Here we need
6582 to get a mode from something else.
6584 In some cases, there is a fourth mode, the operand's
6585 containing mode. If the insn specifies a containing mode for
6586 this operand, it overrides all others.
6588 I am not sure whether the algorithm here is always right,
6589 but it does the right things in those cases. */
6591 mode = GET_MODE (old);
6592 if (mode == VOIDmode)
6595 /* delete_output_reload is only invoked properly if old contains
6596 the original pseudo register. Since this is replaced with a
6597 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6598 find the pseudo in RELOAD_IN_REG. */
6599 if (reload_override_in[j]
6600 && REG_P (rl->in_reg))
6607 else if (REG_P (oldequiv))
6608 oldequiv_reg = oldequiv;
6609 else if (GET_CODE (oldequiv) == SUBREG)
6610 oldequiv_reg = SUBREG_REG (oldequiv);
6612 /* If we are reloading from a register that was recently stored in
6613 with an output-reload, see if we can prove there was
6614 actually no need to store the old value in it. */
6616 if (optimize && REG_P (oldequiv)
6617 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6618 && spill_reg_store[REGNO (oldequiv)]
6620 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6621 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6623 delete_output_reload (insn, j, REGNO (oldequiv));
6625 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6626 then load RELOADREG from OLDEQUIV. Note that we cannot use
6627 gen_lowpart_common since it can do the wrong thing when
6628 RELOADREG has a multi-word mode. Note that RELOADREG
6629 must always be a REG here. */
6631 if (GET_MODE (reloadreg) != mode)
6632 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6633 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6634 oldequiv = SUBREG_REG (oldequiv);
6635 if (GET_MODE (oldequiv) != VOIDmode
6636 && mode != GET_MODE (oldequiv))
6637 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6639 /* Switch to the right place to emit the reload insns. */
6640 switch (rl->when_needed)
6643 where = &other_input_reload_insns;
6645 case RELOAD_FOR_INPUT:
6646 where = &input_reload_insns[rl->opnum];
6648 case RELOAD_FOR_INPUT_ADDRESS:
6649 where = &input_address_reload_insns[rl->opnum];
6651 case RELOAD_FOR_INPADDR_ADDRESS:
6652 where = &inpaddr_address_reload_insns[rl->opnum];
6654 case RELOAD_FOR_OUTPUT_ADDRESS:
6655 where = &output_address_reload_insns[rl->opnum];
6657 case RELOAD_FOR_OUTADDR_ADDRESS:
6658 where = &outaddr_address_reload_insns[rl->opnum];
6660 case RELOAD_FOR_OPERAND_ADDRESS:
6661 where = &operand_reload_insns;
6663 case RELOAD_FOR_OPADDR_ADDR:
6664 where = &other_operand_reload_insns;
6666 case RELOAD_FOR_OTHER_ADDRESS:
6667 where = &other_input_address_reload_insns;
6673 push_to_sequence (*where);
6675 /* Auto-increment addresses must be reloaded in a special way. */
6676 if (rl->out && ! rl->out_reg)
6678 /* We are not going to bother supporting the case where a
6679 incremented register can't be copied directly from
6680 OLDEQUIV since this seems highly unlikely. */
6681 gcc_assert (rl->secondary_in_reload < 0);
6683 if (reload_inherited[j])
6684 oldequiv = reloadreg;
6686 old = XEXP (rl->in_reg, 0);
6688 if (optimize && REG_P (oldequiv)
6689 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6690 && spill_reg_store[REGNO (oldequiv)]
6692 && (dead_or_set_p (insn,
6693 spill_reg_stored_to[REGNO (oldequiv)])
6694 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6696 delete_output_reload (insn, j, REGNO (oldequiv));
6698 /* Prevent normal processing of this reload. */
6700 /* Output a special code sequence for this case. */
6701 new_spill_reg_store[REGNO (reloadreg)]
6702 = inc_for_reload (reloadreg, oldequiv, rl->out,
6706 /* If we are reloading a pseudo-register that was set by the previous
6707 insn, see if we can get rid of that pseudo-register entirely
6708 by redirecting the previous insn into our reload register. */
6710 else if (optimize && REG_P (old)
6711 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6712 && dead_or_set_p (insn, old)
6713 /* This is unsafe if some other reload
6714 uses the same reg first. */
6715 && ! conflicts_with_override (reloadreg)
6716 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6717 rl->when_needed, old, rl->out, j, 0))
6719 rtx temp = PREV_INSN (insn);
6720 while (temp && NOTE_P (temp))
6721 temp = PREV_INSN (temp);
6723 && NONJUMP_INSN_P (temp)
6724 && GET_CODE (PATTERN (temp)) == SET
6725 && SET_DEST (PATTERN (temp)) == old
6726 /* Make sure we can access insn_operand_constraint. */
6727 && asm_noperands (PATTERN (temp)) < 0
6728 /* This is unsafe if operand occurs more than once in current
6729 insn. Perhaps some occurrences aren't reloaded. */
6730 && count_occurrences (PATTERN (insn), old, 0) == 1)
6732 rtx old = SET_DEST (PATTERN (temp));
6733 /* Store into the reload register instead of the pseudo. */
6734 SET_DEST (PATTERN (temp)) = reloadreg;
6736 /* Verify that resulting insn is valid. */
6737 extract_insn (temp);
6738 if (constrain_operands (1))
6740 /* If the previous insn is an output reload, the source is
6741 a reload register, and its spill_reg_store entry will
6742 contain the previous destination. This is now
6744 if (REG_P (SET_SRC (PATTERN (temp)))
6745 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6747 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6748 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6751 /* If these are the only uses of the pseudo reg,
6752 pretend for GDB it lives in the reload reg we used. */
6753 if (REG_N_DEATHS (REGNO (old)) == 1
6754 && REG_N_SETS (REGNO (old)) == 1)
6756 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6757 alter_reg (REGNO (old), -1);
6763 SET_DEST (PATTERN (temp)) = old;
6768 /* We can't do that, so output an insn to load RELOADREG. */
6770 /* If we have a secondary reload, pick up the secondary register
6771 and icode, if any. If OLDEQUIV and OLD are different or
6772 if this is an in-out reload, recompute whether or not we
6773 still need a secondary register and what the icode should
6774 be. If we still need a secondary register and the class or
6775 icode is different, go back to reloading from OLD if using
6776 OLDEQUIV means that we got the wrong type of register. We
6777 cannot have different class or icode due to an in-out reload
6778 because we don't make such reloads when both the input and
6779 output need secondary reload registers. */
6781 if (! special && rl->secondary_in_reload >= 0)
6783 rtx second_reload_reg = 0;
6784 rtx third_reload_reg = 0;
6785 int secondary_reload = rl->secondary_in_reload;
6786 rtx real_oldequiv = oldequiv;
6789 enum insn_code icode;
6790 enum insn_code tertiary_icode = CODE_FOR_nothing;
6792 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6793 and similarly for OLD.
6794 See comments in get_secondary_reload in reload.c. */
6795 /* If it is a pseudo that cannot be replaced with its
6796 equivalent MEM, we must fall back to reload_in, which
6797 will have all the necessary substitutions registered.
6798 Likewise for a pseudo that can't be replaced with its
6799 equivalent constant.
6801 Take extra care for subregs of such pseudos. Note that
6802 we cannot use reg_equiv_mem in this case because it is
6803 not in the right mode. */
6806 if (GET_CODE (tmp) == SUBREG)
6807 tmp = SUBREG_REG (tmp);
6809 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6810 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6811 || reg_equiv_constant[REGNO (tmp)] != 0))
6813 if (! reg_equiv_mem[REGNO (tmp)]
6814 || num_not_at_initial_offset
6815 || GET_CODE (oldequiv) == SUBREG)
6816 real_oldequiv = rl->in;
6818 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6822 if (GET_CODE (tmp) == SUBREG)
6823 tmp = SUBREG_REG (tmp);
6825 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6826 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6827 || reg_equiv_constant[REGNO (tmp)] != 0))
6829 if (! reg_equiv_mem[REGNO (tmp)]
6830 || num_not_at_initial_offset
6831 || GET_CODE (old) == SUBREG)
6834 real_old = reg_equiv_mem[REGNO (tmp)];
6837 second_reload_reg = rld[secondary_reload].reg_rtx;
6838 if (rld[secondary_reload].secondary_in_reload >= 0)
6840 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
6842 third_reload_reg = rld[tertiary_reload].reg_rtx;
6843 tertiary_icode = rld[secondary_reload].secondary_in_icode;
6844 /* We'd have to add more code for quartary reloads. */
6845 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
6847 icode = rl->secondary_in_icode;
6849 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6850 || (rl->in != 0 && rl->out != 0))
6852 secondary_reload_info sri, sri2;
6853 enum reg_class new_class, new_t_class;
6855 sri.icode = CODE_FOR_nothing;
6856 sri.prev_sri = NULL;
6857 new_class = targetm.secondary_reload (1, real_oldequiv, rl->class,
6860 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
6861 second_reload_reg = 0;
6862 else if (new_class == NO_REGS)
6864 if (reload_adjust_reg_for_icode (&second_reload_reg,
6865 third_reload_reg, sri.icode))
6866 icode = sri.icode, third_reload_reg = 0;
6868 oldequiv = old, real_oldequiv = real_old;
6870 else if (sri.icode != CODE_FOR_nothing)
6871 /* We currently lack a way to express this in reloads. */
6875 sri2.icode = CODE_FOR_nothing;
6876 sri2.prev_sri = &sri;
6877 new_t_class = targetm.secondary_reload (1, real_oldequiv,
6878 new_class, mode, &sri);
6879 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
6881 if (reload_adjust_reg_for_temp (&second_reload_reg,
6884 third_reload_reg = 0, tertiary_icode = sri2.icode;
6886 oldequiv = old, real_oldequiv = real_old;
6888 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
6890 rtx intermediate = second_reload_reg;
6892 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6894 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
6897 second_reload_reg = intermediate;
6898 tertiary_icode = sri2.icode;
6901 oldequiv = old, real_oldequiv = real_old;
6903 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
6905 rtx intermediate = second_reload_reg;
6907 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6909 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
6912 second_reload_reg = intermediate;
6913 tertiary_icode = sri2.icode;
6916 oldequiv = old, real_oldequiv = real_old;
6919 /* This could be handled more intelligently too. */
6920 oldequiv = old, real_oldequiv = real_old;
6924 /* If we still need a secondary reload register, check
6925 to see if it is being used as a scratch or intermediate
6926 register and generate code appropriately. If we need
6927 a scratch register, use REAL_OLDEQUIV since the form of
6928 the insn may depend on the actual address if it is
6931 if (second_reload_reg)
6933 if (icode != CODE_FOR_nothing)
6935 /* We'd have to add extra code to handle this case. */
6936 gcc_assert (!third_reload_reg);
6938 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6939 second_reload_reg));
6944 /* See if we need a scratch register to load the
6945 intermediate register (a tertiary reload). */
6946 if (tertiary_icode != CODE_FOR_nothing)
6948 emit_insn ((GEN_FCN (tertiary_icode)
6949 (second_reload_reg, real_oldequiv,
6950 third_reload_reg)));
6952 else if (third_reload_reg)
6954 gen_reload (third_reload_reg, real_oldequiv,
6957 gen_reload (second_reload_reg, third_reload_reg,
6962 gen_reload (second_reload_reg, real_oldequiv,
6966 oldequiv = second_reload_reg;
6971 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6973 rtx real_oldequiv = oldequiv;
6975 if ((REG_P (oldequiv)
6976 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6977 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6978 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6979 || (GET_CODE (oldequiv) == SUBREG
6980 && REG_P (SUBREG_REG (oldequiv))
6981 && (REGNO (SUBREG_REG (oldequiv))
6982 >= FIRST_PSEUDO_REGISTER)
6983 && ((reg_equiv_memory_loc
6984 [REGNO (SUBREG_REG (oldequiv))] != 0)
6985 || (reg_equiv_constant
6986 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6987 || (CONSTANT_P (oldequiv)
6988 && (PREFERRED_RELOAD_CLASS (oldequiv,
6989 REGNO_REG_CLASS (REGNO (reloadreg)))
6991 real_oldequiv = rl->in;
6992 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6996 if (flag_non_call_exceptions)
6997 copy_eh_notes (insn, get_insns ());
6999 /* End this sequence. */
7000 *where = get_insns ();
7003 /* Update reload_override_in so that delete_address_reloads_1
7004 can see the actual register usage. */
7006 reload_override_in[j] = oldequiv;
7009 /* Generate insns to for the output reload RL, which is for the insn described
7010 by CHAIN and has the number J. */
7012 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7015 rtx reloadreg = rl->reg_rtx;
7016 rtx insn = chain->insn;
7019 enum machine_mode mode = GET_MODE (old);
7022 if (rl->when_needed == RELOAD_OTHER)
7025 push_to_sequence (output_reload_insns[rl->opnum]);
7027 /* Determine the mode to reload in.
7028 See comments above (for input reloading). */
7030 if (mode == VOIDmode)
7032 /* VOIDmode should never happen for an output. */
7033 if (asm_noperands (PATTERN (insn)) < 0)
7034 /* It's the compiler's fault. */
7035 fatal_insn ("VOIDmode on an output", insn);
7036 error_for_asm (insn, "output operand is constant in %<asm%>");
7037 /* Prevent crash--use something we know is valid. */
7039 old = gen_rtx_REG (mode, REGNO (reloadreg));
7042 if (GET_MODE (reloadreg) != mode)
7043 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7045 /* If we need two reload regs, set RELOADREG to the intermediate
7046 one, since it will be stored into OLD. We might need a secondary
7047 register only for an input reload, so check again here. */
7049 if (rl->secondary_out_reload >= 0)
7052 int secondary_reload = rl->secondary_out_reload;
7053 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7055 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7056 && reg_equiv_mem[REGNO (old)] != 0)
7057 real_old = reg_equiv_mem[REGNO (old)];
7059 if (secondary_reload_class (0, rl->class, mode, real_old) != NO_REGS)
7061 rtx second_reloadreg = reloadreg;
7062 reloadreg = rld[secondary_reload].reg_rtx;
7064 /* See if RELOADREG is to be used as a scratch register
7065 or as an intermediate register. */
7066 if (rl->secondary_out_icode != CODE_FOR_nothing)
7068 /* We'd have to add extra code to handle this case. */
7069 gcc_assert (tertiary_reload < 0);
7071 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7072 (real_old, second_reloadreg, reloadreg)));
7077 /* See if we need both a scratch and intermediate reload
7080 enum insn_code tertiary_icode
7081 = rld[secondary_reload].secondary_out_icode;
7083 /* We'd have to add more code for quartary reloads. */
7084 gcc_assert (tertiary_reload < 0
7085 || rld[tertiary_reload].secondary_out_reload < 0);
7087 if (GET_MODE (reloadreg) != mode)
7088 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7090 if (tertiary_icode != CODE_FOR_nothing)
7092 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7095 /* Copy primary reload reg to secondary reload reg.
7096 (Note that these have been swapped above, then
7097 secondary reload reg to OLD using our insn.) */
7099 /* If REAL_OLD is a paradoxical SUBREG, remove it
7100 and try to put the opposite SUBREG on
7102 if (GET_CODE (real_old) == SUBREG
7103 && (GET_MODE_SIZE (GET_MODE (real_old))
7104 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7105 && 0 != (tem = gen_lowpart_common
7106 (GET_MODE (SUBREG_REG (real_old)),
7108 real_old = SUBREG_REG (real_old), reloadreg = tem;
7110 gen_reload (reloadreg, second_reloadreg,
7111 rl->opnum, rl->when_needed);
7112 emit_insn ((GEN_FCN (tertiary_icode)
7113 (real_old, reloadreg, third_reloadreg)));
7119 /* Copy between the reload regs here and then to
7122 gen_reload (reloadreg, second_reloadreg,
7123 rl->opnum, rl->when_needed);
7124 if (tertiary_reload >= 0)
7126 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7128 gen_reload (third_reloadreg, reloadreg,
7129 rl->opnum, rl->when_needed);
7130 reloadreg = third_reloadreg;
7137 /* Output the last reload insn. */
7142 /* Don't output the last reload if OLD is not the dest of
7143 INSN and is in the src and is clobbered by INSN. */
7144 if (! flag_expensive_optimizations
7146 || !(set = single_set (insn))
7147 || rtx_equal_p (old, SET_DEST (set))
7148 || !reg_mentioned_p (old, SET_SRC (set))
7149 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7150 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7151 gen_reload (old, reloadreg, rl->opnum,
7155 /* Look at all insns we emitted, just to be safe. */
7156 for (p = get_insns (); p; p = NEXT_INSN (p))
7159 rtx pat = PATTERN (p);
7161 /* If this output reload doesn't come from a spill reg,
7162 clear any memory of reloaded copies of the pseudo reg.
7163 If this output reload comes from a spill reg,
7164 reg_has_output_reload will make this do nothing. */
7165 note_stores (pat, forget_old_reloads_1, NULL);
7167 if (reg_mentioned_p (rl->reg_rtx, pat))
7169 rtx set = single_set (insn);
7170 if (reload_spill_index[j] < 0
7172 && SET_SRC (set) == rl->reg_rtx)
7174 int src = REGNO (SET_SRC (set));
7176 reload_spill_index[j] = src;
7177 SET_HARD_REG_BIT (reg_is_output_reload, src);
7178 if (find_regno_note (insn, REG_DEAD, src))
7179 SET_HARD_REG_BIT (reg_reloaded_died, src);
7181 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
7183 int s = rl->secondary_out_reload;
7184 set = single_set (p);
7185 /* If this reload copies only to the secondary reload
7186 register, the secondary reload does the actual
7188 if (s >= 0 && set == NULL_RTX)
7189 /* We can't tell what function the secondary reload
7190 has and where the actual store to the pseudo is
7191 made; leave new_spill_reg_store alone. */
7194 && SET_SRC (set) == rl->reg_rtx
7195 && SET_DEST (set) == rld[s].reg_rtx)
7197 /* Usually the next instruction will be the
7198 secondary reload insn; if we can confirm
7199 that it is, setting new_spill_reg_store to
7200 that insn will allow an extra optimization. */
7201 rtx s_reg = rld[s].reg_rtx;
7202 rtx next = NEXT_INSN (p);
7203 rld[s].out = rl->out;
7204 rld[s].out_reg = rl->out_reg;
7205 set = single_set (next);
7206 if (set && SET_SRC (set) == s_reg
7207 && ! new_spill_reg_store[REGNO (s_reg)])
7209 SET_HARD_REG_BIT (reg_is_output_reload,
7211 new_spill_reg_store[REGNO (s_reg)] = next;
7215 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
7220 if (rl->when_needed == RELOAD_OTHER)
7222 emit_insn (other_output_reload_insns[rl->opnum]);
7223 other_output_reload_insns[rl->opnum] = get_insns ();
7226 output_reload_insns[rl->opnum] = get_insns ();
7228 if (flag_non_call_exceptions)
7229 copy_eh_notes (insn, get_insns ());
7234 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7235 and has the number J. */
7237 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7239 rtx insn = chain->insn;
7240 rtx old = (rl->in && MEM_P (rl->in)
7241 ? rl->in_reg : rl->in);
7244 /* AUTO_INC reloads need to be handled even if inherited. We got an
7245 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7246 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7247 && ! rtx_equal_p (rl->reg_rtx, old)
7248 && rl->reg_rtx != 0)
7249 emit_input_reload_insns (chain, rld + j, old, j);
7251 /* When inheriting a wider reload, we have a MEM in rl->in,
7252 e.g. inheriting a SImode output reload for
7253 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7254 if (optimize && reload_inherited[j] && rl->in
7256 && MEM_P (rl->in_reg)
7257 && reload_spill_index[j] >= 0
7258 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7259 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7261 /* If we are reloading a register that was recently stored in with an
7262 output-reload, see if we can prove there was
7263 actually no need to store the old value in it. */
7266 && (reload_inherited[j] || reload_override_in[j])
7268 && REG_P (rl->reg_rtx)
7269 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
7271 /* There doesn't seem to be any reason to restrict this to pseudos
7272 and doing so loses in the case where we are copying from a
7273 register of the wrong class. */
7274 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
7275 >= FIRST_PSEUDO_REGISTER)
7277 /* The insn might have already some references to stackslots
7278 replaced by MEMs, while reload_out_reg still names the
7280 && (dead_or_set_p (insn,
7281 spill_reg_stored_to[REGNO (rl->reg_rtx)])
7282 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
7284 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
7287 /* Do output reloading for reload RL, which is for the insn described by
7288 CHAIN and has the number J.
7289 ??? At some point we need to support handling output reloads of
7290 JUMP_INSNs or insns that set cc0. */
7292 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7295 rtx insn = chain->insn;
7296 /* If this is an output reload that stores something that is
7297 not loaded in this same reload, see if we can eliminate a previous
7299 rtx pseudo = rl->out_reg;
7304 && ! rtx_equal_p (rl->in_reg, pseudo)
7305 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7306 && reg_last_reload_reg[REGNO (pseudo)])
7308 int pseudo_no = REGNO (pseudo);
7309 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7311 /* We don't need to test full validity of last_regno for
7312 inherit here; we only want to know if the store actually
7313 matches the pseudo. */
7314 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7315 && reg_reloaded_contents[last_regno] == pseudo_no
7316 && spill_reg_store[last_regno]
7317 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7318 delete_output_reload (insn, j, last_regno);
7323 || rl->reg_rtx == old
7324 || rl->reg_rtx == 0)
7327 /* An output operand that dies right away does need a reload,
7328 but need not be copied from it. Show the new location in the
7330 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7331 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7333 XEXP (note, 0) = rl->reg_rtx;
7336 /* Likewise for a SUBREG of an operand that dies. */
7337 else if (GET_CODE (old) == SUBREG
7338 && REG_P (SUBREG_REG (old))
7339 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7342 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
7346 else if (GET_CODE (old) == SCRATCH)
7347 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7348 but we don't want to make an output reload. */
7351 /* If is a JUMP_INSN, we can't support output reloads yet. */
7352 gcc_assert (NONJUMP_INSN_P (insn));
7354 emit_output_reload_insns (chain, rld + j, j);
7357 /* Reload number R reloads from or to a group of hard registers starting at
7358 register REGNO. Return true if it can be treated for inheritance purposes
7359 like a group of reloads, each one reloading a single hard register.
7360 The caller has already checked that the spill register and REGNO use
7361 the same number of registers to store the reload value. */
7364 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
7366 #ifdef CANNOT_CHANGE_MODE_CLASS
7367 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
7368 GET_MODE (rld[r].reg_rtx),
7369 reg_raw_mode[reload_spill_index[r]])
7370 && !REG_CANNOT_CHANGE_MODE_P (regno,
7371 GET_MODE (rld[r].reg_rtx),
7372 reg_raw_mode[regno]));
7378 /* Output insns to reload values in and out of the chosen reload regs. */
7381 emit_reload_insns (struct insn_chain *chain)
7383 rtx insn = chain->insn;
7387 CLEAR_HARD_REG_SET (reg_reloaded_died);
7389 for (j = 0; j < reload_n_operands; j++)
7390 input_reload_insns[j] = input_address_reload_insns[j]
7391 = inpaddr_address_reload_insns[j]
7392 = output_reload_insns[j] = output_address_reload_insns[j]
7393 = outaddr_address_reload_insns[j]
7394 = other_output_reload_insns[j] = 0;
7395 other_input_address_reload_insns = 0;
7396 other_input_reload_insns = 0;
7397 operand_reload_insns = 0;
7398 other_operand_reload_insns = 0;
7400 /* Dump reloads into the dump file. */
7403 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7404 debug_reload_to_stream (dump_file);
7407 /* Now output the instructions to copy the data into and out of the
7408 reload registers. Do these in the order that the reloads were reported,
7409 since reloads of base and index registers precede reloads of operands
7410 and the operands may need the base and index registers reloaded. */
7412 for (j = 0; j < n_reloads; j++)
7415 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7416 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7418 do_input_reload (chain, rld + j, j);
7419 do_output_reload (chain, rld + j, j);
7422 /* Now write all the insns we made for reloads in the order expected by
7423 the allocation functions. Prior to the insn being reloaded, we write
7424 the following reloads:
7426 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7428 RELOAD_OTHER reloads.
7430 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7431 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7432 RELOAD_FOR_INPUT reload for the operand.
7434 RELOAD_FOR_OPADDR_ADDRS reloads.
7436 RELOAD_FOR_OPERAND_ADDRESS reloads.
7438 After the insn being reloaded, we write the following:
7440 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7441 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7442 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7443 reloads for the operand. The RELOAD_OTHER output reloads are
7444 output in descending order by reload number. */
7446 emit_insn_before (other_input_address_reload_insns, insn);
7447 emit_insn_before (other_input_reload_insns, insn);
7449 for (j = 0; j < reload_n_operands; j++)
7451 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7452 emit_insn_before (input_address_reload_insns[j], insn);
7453 emit_insn_before (input_reload_insns[j], insn);
7456 emit_insn_before (other_operand_reload_insns, insn);
7457 emit_insn_before (operand_reload_insns, insn);
7459 for (j = 0; j < reload_n_operands; j++)
7461 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7462 x = emit_insn_after (output_address_reload_insns[j], x);
7463 x = emit_insn_after (output_reload_insns[j], x);
7464 emit_insn_after (other_output_reload_insns[j], x);
7467 /* For all the spill regs newly reloaded in this instruction,
7468 record what they were reloaded from, so subsequent instructions
7469 can inherit the reloads.
7471 Update spill_reg_store for the reloads of this insn.
7472 Copy the elements that were updated in the loop above. */
7474 for (j = 0; j < n_reloads; j++)
7476 int r = reload_order[j];
7477 int i = reload_spill_index[r];
7479 /* If this is a non-inherited input reload from a pseudo, we must
7480 clear any memory of a previous store to the same pseudo. Only do
7481 something if there will not be an output reload for the pseudo
7483 if (rld[r].in_reg != 0
7484 && ! (reload_inherited[r] || reload_override_in[r]))
7486 rtx reg = rld[r].in_reg;
7488 if (GET_CODE (reg) == SUBREG)
7489 reg = SUBREG_REG (reg);
7492 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7493 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
7495 int nregno = REGNO (reg);
7497 if (reg_last_reload_reg[nregno])
7499 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7501 if (reg_reloaded_contents[last_regno] == nregno)
7502 spill_reg_store[last_regno] = 0;
7507 /* I is nonneg if this reload used a register.
7508 If rld[r].reg_rtx is 0, this is an optional reload
7509 that we opted to ignore. */
7511 if (i >= 0 && rld[r].reg_rtx != 0)
7513 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7515 int part_reaches_end = 0;
7516 int all_reaches_end = 1;
7518 /* For a multi register reload, we need to check if all or part
7519 of the value lives to the end. */
7520 for (k = 0; k < nr; k++)
7522 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7523 rld[r].when_needed))
7524 part_reaches_end = 1;
7526 all_reaches_end = 0;
7529 /* Ignore reloads that don't reach the end of the insn in
7531 if (all_reaches_end)
7533 /* First, clear out memory of what used to be in this spill reg.
7534 If consecutive registers are used, clear them all. */
7536 for (k = 0; k < nr; k++)
7538 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7539 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7542 /* Maybe the spill reg contains a copy of reload_out. */
7544 && (REG_P (rld[r].out)
7548 || REG_P (rld[r].out_reg)))
7550 rtx out = (REG_P (rld[r].out)
7554 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7555 int nregno = REGNO (out);
7556 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7557 : hard_regno_nregs[nregno]
7558 [GET_MODE (rld[r].reg_rtx)]);
7561 spill_reg_store[i] = new_spill_reg_store[i];
7562 spill_reg_stored_to[i] = out;
7563 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7565 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7567 && inherit_piecemeal_p (r, nregno));
7569 /* If NREGNO is a hard register, it may occupy more than
7570 one register. If it does, say what is in the
7571 rest of the registers assuming that both registers
7572 agree on how many words the object takes. If not,
7573 invalidate the subsequent registers. */
7575 if (nregno < FIRST_PSEUDO_REGISTER)
7576 for (k = 1; k < nnr; k++)
7577 reg_last_reload_reg[nregno + k]
7579 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7582 /* Now do the inverse operation. */
7583 for (k = 0; k < nr; k++)
7585 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7586 reg_reloaded_contents[i + k]
7587 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7590 reg_reloaded_insn[i + k] = insn;
7591 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7592 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7593 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7597 /* Maybe the spill reg contains a copy of reload_in. Only do
7598 something if there will not be an output reload for
7599 the register being reloaded. */
7600 else if (rld[r].out_reg == 0
7602 && ((REG_P (rld[r].in)
7603 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7604 && !REGNO_REG_SET_P (®_has_output_reload,
7606 || (REG_P (rld[r].in_reg)
7607 && !REGNO_REG_SET_P (®_has_output_reload,
7608 REGNO (rld[r].in_reg))))
7609 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7616 if (REG_P (rld[r].in)
7617 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7619 else if (REG_P (rld[r].in_reg))
7622 in = XEXP (rld[r].in_reg, 0);
7623 nregno = REGNO (in);
7625 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7626 : hard_regno_nregs[nregno]
7627 [GET_MODE (rld[r].reg_rtx)]);
7629 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7631 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7633 && inherit_piecemeal_p (r, nregno));
7635 if (nregno < FIRST_PSEUDO_REGISTER)
7636 for (k = 1; k < nnr; k++)
7637 reg_last_reload_reg[nregno + k]
7639 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7642 /* Unless we inherited this reload, show we haven't
7643 recently done a store.
7644 Previous stores of inherited auto_inc expressions
7645 also have to be discarded. */
7646 if (! reload_inherited[r]
7647 || (rld[r].out && ! rld[r].out_reg))
7648 spill_reg_store[i] = 0;
7650 for (k = 0; k < nr; k++)
7652 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7653 reg_reloaded_contents[i + k]
7654 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7657 reg_reloaded_insn[i + k] = insn;
7658 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7659 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7660 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7665 /* However, if part of the reload reaches the end, then we must
7666 invalidate the old info for the part that survives to the end. */
7667 else if (part_reaches_end)
7669 for (k = 0; k < nr; k++)
7670 if (reload_reg_reaches_end_p (i + k,
7672 rld[r].when_needed))
7673 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7677 /* The following if-statement was #if 0'd in 1.34 (or before...).
7678 It's reenabled in 1.35 because supposedly nothing else
7679 deals with this problem. */
7681 /* If a register gets output-reloaded from a non-spill register,
7682 that invalidates any previous reloaded copy of it.
7683 But forget_old_reloads_1 won't get to see it, because
7684 it thinks only about the original insn. So invalidate it here.
7685 Also do the same thing for RELOAD_OTHER constraints where the
7686 output is discarded. */
7688 && ((rld[r].out != 0
7689 && (REG_P (rld[r].out)
7690 || (MEM_P (rld[r].out)
7691 && REG_P (rld[r].out_reg))))
7692 || (rld[r].out == 0 && rld[r].out_reg
7693 && REG_P (rld[r].out_reg))))
7695 rtx out = ((rld[r].out && REG_P (rld[r].out))
7696 ? rld[r].out : rld[r].out_reg);
7697 int nregno = REGNO (out);
7699 /* REG_RTX is now set or clobbered by the main instruction.
7700 As the comment above explains, forget_old_reloads_1 only
7701 sees the original instruction, and there is no guarantee
7702 that the original instruction also clobbered REG_RTX.
7703 For example, if find_reloads sees that the input side of
7704 a matched operand pair dies in this instruction, it may
7705 use the input register as the reload register.
7707 Calling forget_old_reloads_1 is a waste of effort if
7708 REG_RTX is also the output register.
7710 If we know that REG_RTX holds the value of a pseudo
7711 register, the code after the call will record that fact. */
7712 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
7713 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
7715 if (nregno >= FIRST_PSEUDO_REGISTER)
7717 rtx src_reg, store_insn = NULL_RTX;
7719 reg_last_reload_reg[nregno] = 0;
7721 /* If we can find a hard register that is stored, record
7722 the storing insn so that we may delete this insn with
7723 delete_output_reload. */
7724 src_reg = rld[r].reg_rtx;
7726 /* If this is an optional reload, try to find the source reg
7727 from an input reload. */
7730 rtx set = single_set (insn);
7731 if (set && SET_DEST (set) == rld[r].out)
7735 src_reg = SET_SRC (set);
7737 for (k = 0; k < n_reloads; k++)
7739 if (rld[k].in == src_reg)
7741 src_reg = rld[k].reg_rtx;
7748 store_insn = new_spill_reg_store[REGNO (src_reg)];
7749 if (src_reg && REG_P (src_reg)
7750 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7752 int src_regno = REGNO (src_reg);
7753 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7754 /* The place where to find a death note varies with
7755 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7756 necessarily checked exactly in the code that moves
7757 notes, so just check both locations. */
7758 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7759 if (! note && store_insn)
7760 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7763 spill_reg_store[src_regno + nr] = store_insn;
7764 spill_reg_stored_to[src_regno + nr] = out;
7765 reg_reloaded_contents[src_regno + nr] = nregno;
7766 reg_reloaded_insn[src_regno + nr] = store_insn;
7767 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7768 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7769 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7770 GET_MODE (src_reg)))
7771 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7773 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7775 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7777 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7779 reg_last_reload_reg[nregno] = src_reg;
7780 /* We have to set reg_has_output_reload here, or else
7781 forget_old_reloads_1 will clear reg_last_reload_reg
7783 SET_REGNO_REG_SET (®_has_output_reload,
7789 int num_regs = hard_regno_nregs[nregno][GET_MODE (out)];
7791 while (num_regs-- > 0)
7792 reg_last_reload_reg[nregno + num_regs] = 0;
7796 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7799 /* Go through the motions to emit INSN and test if it is strictly valid.
7800 Return the emitted insn if valid, else return NULL. */
7803 emit_insn_if_valid_for_reload (rtx insn)
7805 rtx last = get_last_insn ();
7808 insn = emit_insn (insn);
7809 code = recog_memoized (insn);
7813 extract_insn (insn);
7814 /* We want constrain operands to treat this insn strictly in its
7815 validity determination, i.e., the way it would after reload has
7817 if (constrain_operands (1))
7821 delete_insns_since (last);
7825 /* Emit code to perform a reload from IN (which may be a reload register) to
7826 OUT (which may also be a reload register). IN or OUT is from operand
7827 OPNUM with reload type TYPE.
7829 Returns first insn emitted. */
7832 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7834 rtx last = get_last_insn ();
7837 /* If IN is a paradoxical SUBREG, remove it and try to put the
7838 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7839 if (GET_CODE (in) == SUBREG
7840 && (GET_MODE_SIZE (GET_MODE (in))
7841 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7842 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7843 in = SUBREG_REG (in), out = tem;
7844 else if (GET_CODE (out) == SUBREG
7845 && (GET_MODE_SIZE (GET_MODE (out))
7846 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7847 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7848 out = SUBREG_REG (out), in = tem;
7850 /* How to do this reload can get quite tricky. Normally, we are being
7851 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7852 register that didn't get a hard register. In that case we can just
7853 call emit_move_insn.
7855 We can also be asked to reload a PLUS that adds a register or a MEM to
7856 another register, constant or MEM. This can occur during frame pointer
7857 elimination and while reloading addresses. This case is handled by
7858 trying to emit a single insn to perform the add. If it is not valid,
7859 we use a two insn sequence.
7861 Or we can be asked to reload an unary operand that was a fragment of
7862 an addressing mode, into a register. If it isn't recognized as-is,
7863 we try making the unop operand and the reload-register the same:
7864 (set reg:X (unop:X expr:Y))
7865 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
7867 Finally, we could be called to handle an 'o' constraint by putting
7868 an address into a register. In that case, we first try to do this
7869 with a named pattern of "reload_load_address". If no such pattern
7870 exists, we just emit a SET insn and hope for the best (it will normally
7871 be valid on machines that use 'o').
7873 This entire process is made complex because reload will never
7874 process the insns we generate here and so we must ensure that
7875 they will fit their constraints and also by the fact that parts of
7876 IN might be being reloaded separately and replaced with spill registers.
7877 Because of this, we are, in some sense, just guessing the right approach
7878 here. The one listed above seems to work.
7880 ??? At some point, this whole thing needs to be rethought. */
7882 if (GET_CODE (in) == PLUS
7883 && (REG_P (XEXP (in, 0))
7884 || GET_CODE (XEXP (in, 0)) == SUBREG
7885 || MEM_P (XEXP (in, 0)))
7886 && (REG_P (XEXP (in, 1))
7887 || GET_CODE (XEXP (in, 1)) == SUBREG
7888 || CONSTANT_P (XEXP (in, 1))
7889 || MEM_P (XEXP (in, 1))))
7891 /* We need to compute the sum of a register or a MEM and another
7892 register, constant, or MEM, and put it into the reload
7893 register. The best possible way of doing this is if the machine
7894 has a three-operand ADD insn that accepts the required operands.
7896 The simplest approach is to try to generate such an insn and see if it
7897 is recognized and matches its constraints. If so, it can be used.
7899 It might be better not to actually emit the insn unless it is valid,
7900 but we need to pass the insn as an operand to `recog' and
7901 `extract_insn' and it is simpler to emit and then delete the insn if
7902 not valid than to dummy things up. */
7904 rtx op0, op1, tem, insn;
7907 op0 = find_replacement (&XEXP (in, 0));
7908 op1 = find_replacement (&XEXP (in, 1));
7910 /* Since constraint checking is strict, commutativity won't be
7911 checked, so we need to do that here to avoid spurious failure
7912 if the add instruction is two-address and the second operand
7913 of the add is the same as the reload reg, which is frequently
7914 the case. If the insn would be A = B + A, rearrange it so
7915 it will be A = A + B as constrain_operands expects. */
7917 if (REG_P (XEXP (in, 1))
7918 && REGNO (out) == REGNO (XEXP (in, 1)))
7919 tem = op0, op0 = op1, op1 = tem;
7921 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7922 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7924 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7928 /* If that failed, we must use a conservative two-insn sequence.
7930 Use a move to copy one operand into the reload register. Prefer
7931 to reload a constant, MEM or pseudo since the move patterns can
7932 handle an arbitrary operand. If OP1 is not a constant, MEM or
7933 pseudo and OP1 is not a valid operand for an add instruction, then
7936 After reloading one of the operands into the reload register, add
7937 the reload register to the output register.
7939 If there is another way to do this for a specific machine, a
7940 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7943 code = (int) optab_handler (add_optab, GET_MODE (out))->insn_code;
7945 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7947 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7948 || (code != CODE_FOR_nothing
7949 && ! ((*insn_data[code].operand[2].predicate)
7950 (op1, insn_data[code].operand[2].mode))))
7951 tem = op0, op0 = op1, op1 = tem;
7953 gen_reload (out, op0, opnum, type);
7955 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7956 This fixes a problem on the 32K where the stack pointer cannot
7957 be used as an operand of an add insn. */
7959 if (rtx_equal_p (op0, op1))
7962 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
7965 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7966 set_unique_reg_note (insn, REG_EQUIV, in);
7970 /* If that failed, copy the address register to the reload register.
7971 Then add the constant to the reload register. */
7973 gcc_assert (!reg_overlap_mentioned_p (out, op0));
7974 gen_reload (out, op1, opnum, type);
7975 insn = emit_insn (gen_add2_insn (out, op0));
7976 set_unique_reg_note (insn, REG_EQUIV, in);
7979 #ifdef SECONDARY_MEMORY_NEEDED
7980 /* If we need a memory location to do the move, do it that way. */
7981 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7982 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7983 && (REG_P (out) || GET_CODE (out) == SUBREG)
7984 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7985 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7986 REGNO_REG_CLASS (reg_or_subregno (out)),
7989 /* Get the memory to use and rewrite both registers to its mode. */
7990 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7992 if (GET_MODE (loc) != GET_MODE (out))
7993 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7995 if (GET_MODE (loc) != GET_MODE (in))
7996 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7998 gen_reload (loc, in, opnum, type);
7999 gen_reload (out, loc, opnum, type);
8002 else if (REG_P (out) && UNARY_P (in))
8009 op1 = find_replacement (&XEXP (in, 0));
8010 if (op1 != XEXP (in, 0))
8011 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8013 /* First, try a plain SET. */
8014 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8018 /* If that failed, move the inner operand to the reload
8019 register, and try the same unop with the inner expression
8020 replaced with the reload register. */
8022 if (GET_MODE (op1) != GET_MODE (out))
8023 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8027 gen_reload (out_moded, op1, opnum, type);
8030 = gen_rtx_SET (VOIDmode, out,
8031 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8033 insn = emit_insn_if_valid_for_reload (insn);
8036 set_unique_reg_note (insn, REG_EQUIV, in);
8040 fatal_insn ("Failure trying to reload:", set);
8042 /* If IN is a simple operand, use gen_move_insn. */
8043 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8045 tem = emit_insn (gen_move_insn (out, in));
8046 /* IN may contain a LABEL_REF, if so add a REG_LABEL note. */
8047 mark_jump_label (in, tem, 0);
8050 #ifdef HAVE_reload_load_address
8051 else if (HAVE_reload_load_address)
8052 emit_insn (gen_reload_load_address (out, in));
8055 /* Otherwise, just write (set OUT IN) and hope for the best. */
8057 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8059 /* Return the first insn emitted.
8060 We can not just return get_last_insn, because there may have
8061 been multiple instructions emitted. Also note that gen_move_insn may
8062 emit more than one insn itself, so we can not assume that there is one
8063 insn emitted per emit_insn_before call. */
8065 return last ? NEXT_INSN (last) : get_insns ();
8068 /* Delete a previously made output-reload whose result we now believe
8069 is not needed. First we double-check.
8071 INSN is the insn now being processed.
8072 LAST_RELOAD_REG is the hard register number for which we want to delete
8073 the last output reload.
8074 J is the reload-number that originally used REG. The caller has made
8075 certain that reload J doesn't use REG any longer for input. */
8078 delete_output_reload (rtx insn, int j, int last_reload_reg)
8080 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8081 rtx reg = spill_reg_stored_to[last_reload_reg];
8084 int n_inherited = 0;
8088 /* It is possible that this reload has been only used to set another reload
8089 we eliminated earlier and thus deleted this instruction too. */
8090 if (INSN_DELETED_P (output_reload_insn))
8093 /* Get the raw pseudo-register referred to. */
8095 while (GET_CODE (reg) == SUBREG)
8096 reg = SUBREG_REG (reg);
8097 substed = reg_equiv_memory_loc[REGNO (reg)];
8099 /* This is unsafe if the operand occurs more often in the current
8100 insn than it is inherited. */
8101 for (k = n_reloads - 1; k >= 0; k--)
8103 rtx reg2 = rld[k].in;
8106 if (MEM_P (reg2) || reload_override_in[k])
8107 reg2 = rld[k].in_reg;
8109 if (rld[k].out && ! rld[k].out_reg)
8110 reg2 = XEXP (rld[k].in_reg, 0);
8112 while (GET_CODE (reg2) == SUBREG)
8113 reg2 = SUBREG_REG (reg2);
8114 if (rtx_equal_p (reg2, reg))
8116 if (reload_inherited[k] || reload_override_in[k] || k == j)
8122 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8123 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8124 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8127 n_occurrences += count_occurrences (PATTERN (insn),
8128 eliminate_regs (substed, 0,
8130 for (i1 = reg_equiv_alt_mem_list [REGNO (reg)]; i1; i1 = XEXP (i1, 1))
8132 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8133 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8135 if (n_occurrences > n_inherited)
8138 /* If the pseudo-reg we are reloading is no longer referenced
8139 anywhere between the store into it and here,
8140 and we're within the same basic block, then the value can only
8141 pass through the reload reg and end up here.
8142 Otherwise, give up--return. */
8143 for (i1 = NEXT_INSN (output_reload_insn);
8144 i1 != insn; i1 = NEXT_INSN (i1))
8146 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8148 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8149 && reg_mentioned_p (reg, PATTERN (i1)))
8151 /* If this is USE in front of INSN, we only have to check that
8152 there are no more references than accounted for by inheritance. */
8153 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8155 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8156 i1 = NEXT_INSN (i1);
8158 if (n_occurrences <= n_inherited && i1 == insn)
8164 /* We will be deleting the insn. Remove the spill reg information. */
8165 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8167 spill_reg_store[last_reload_reg + k] = 0;
8168 spill_reg_stored_to[last_reload_reg + k] = 0;
8171 /* The caller has already checked that REG dies or is set in INSN.
8172 It has also checked that we are optimizing, and thus some
8173 inaccuracies in the debugging information are acceptable.
8174 So we could just delete output_reload_insn. But in some cases
8175 we can improve the debugging information without sacrificing
8176 optimization - maybe even improving the code: See if the pseudo
8177 reg has been completely replaced with reload regs. If so, delete
8178 the store insn and forget we had a stack slot for the pseudo. */
8179 if (rld[j].out != rld[j].in
8180 && REG_N_DEATHS (REGNO (reg)) == 1
8181 && REG_N_SETS (REGNO (reg)) == 1
8182 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8183 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8187 /* We know that it was used only between here and the beginning of
8188 the current basic block. (We also know that the last use before
8189 INSN was the output reload we are thinking of deleting, but never
8190 mind that.) Search that range; see if any ref remains. */
8191 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8193 rtx set = single_set (i2);
8195 /* Uses which just store in the pseudo don't count,
8196 since if they are the only uses, they are dead. */
8197 if (set != 0 && SET_DEST (set) == reg)
8202 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8203 && reg_mentioned_p (reg, PATTERN (i2)))
8205 /* Some other ref remains; just delete the output reload we
8207 delete_address_reloads (output_reload_insn, insn);
8208 delete_insn (output_reload_insn);
8213 /* Delete the now-dead stores into this pseudo. Note that this
8214 loop also takes care of deleting output_reload_insn. */
8215 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8217 rtx set = single_set (i2);
8219 if (set != 0 && SET_DEST (set) == reg)
8221 delete_address_reloads (i2, insn);
8229 /* For the debugging info, say the pseudo lives in this reload reg. */
8230 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
8231 alter_reg (REGNO (reg), -1);
8235 delete_address_reloads (output_reload_insn, insn);
8236 delete_insn (output_reload_insn);
8240 /* We are going to delete DEAD_INSN. Recursively delete loads of
8241 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8242 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8244 delete_address_reloads (rtx dead_insn, rtx current_insn)
8246 rtx set = single_set (dead_insn);
8247 rtx set2, dst, prev, next;
8250 rtx dst = SET_DEST (set);
8252 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8254 /* If we deleted the store from a reloaded post_{in,de}c expression,
8255 we can delete the matching adds. */
8256 prev = PREV_INSN (dead_insn);
8257 next = NEXT_INSN (dead_insn);
8258 if (! prev || ! next)
8260 set = single_set (next);
8261 set2 = single_set (prev);
8263 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8264 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8265 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8267 dst = SET_DEST (set);
8268 if (! rtx_equal_p (dst, SET_DEST (set2))
8269 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8270 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8271 || (INTVAL (XEXP (SET_SRC (set), 1))
8272 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8274 delete_related_insns (prev);
8275 delete_related_insns (next);
8278 /* Subfunction of delete_address_reloads: process registers found in X. */
8280 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8282 rtx prev, set, dst, i2;
8284 enum rtx_code code = GET_CODE (x);
8288 const char *fmt = GET_RTX_FORMAT (code);
8289 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8292 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8293 else if (fmt[i] == 'E')
8295 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8296 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8303 if (spill_reg_order[REGNO (x)] < 0)
8306 /* Scan backwards for the insn that sets x. This might be a way back due
8308 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8310 code = GET_CODE (prev);
8311 if (code == CODE_LABEL || code == JUMP_INSN)
8315 if (reg_set_p (x, PATTERN (prev)))
8317 if (reg_referenced_p (x, PATTERN (prev)))
8320 if (! prev || INSN_UID (prev) < reload_first_uid)
8322 /* Check that PREV only sets the reload register. */
8323 set = single_set (prev);
8326 dst = SET_DEST (set);
8328 || ! rtx_equal_p (dst, x))
8330 if (! reg_set_p (dst, PATTERN (dead_insn)))
8332 /* Check if DST was used in a later insn -
8333 it might have been inherited. */
8334 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8340 if (reg_referenced_p (dst, PATTERN (i2)))
8342 /* If there is a reference to the register in the current insn,
8343 it might be loaded in a non-inherited reload. If no other
8344 reload uses it, that means the register is set before
8346 if (i2 == current_insn)
8348 for (j = n_reloads - 1; j >= 0; j--)
8349 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8350 || reload_override_in[j] == dst)
8352 for (j = n_reloads - 1; j >= 0; j--)
8353 if (rld[j].in && rld[j].reg_rtx == dst)
8362 /* If DST is still live at CURRENT_INSN, check if it is used for
8363 any reload. Note that even if CURRENT_INSN sets DST, we still
8364 have to check the reloads. */
8365 if (i2 == current_insn)
8367 for (j = n_reloads - 1; j >= 0; j--)
8368 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8369 || reload_override_in[j] == dst)
8371 /* ??? We can't finish the loop here, because dst might be
8372 allocated to a pseudo in this block if no reload in this
8373 block needs any of the classes containing DST - see
8374 spill_hard_reg. There is no easy way to tell this, so we
8375 have to scan till the end of the basic block. */
8377 if (reg_set_p (dst, PATTERN (i2)))
8381 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8382 reg_reloaded_contents[REGNO (dst)] = -1;
8386 /* Output reload-insns to reload VALUE into RELOADREG.
8387 VALUE is an autoincrement or autodecrement RTX whose operand
8388 is a register or memory location;
8389 so reloading involves incrementing that location.
8390 IN is either identical to VALUE, or some cheaper place to reload from.
8392 INC_AMOUNT is the number to increment or decrement by (always positive).
8393 This cannot be deduced from VALUE.
8395 Return the instruction that stores into RELOADREG. */
8398 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8400 /* REG or MEM to be copied and incremented. */
8401 rtx incloc = find_replacement (&XEXP (value, 0));
8402 /* Nonzero if increment after copying. */
8403 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8404 || GET_CODE (value) == POST_MODIFY);
8410 rtx real_in = in == value ? incloc : in;
8412 /* No hard register is equivalent to this register after
8413 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8414 we could inc/dec that register as well (maybe even using it for
8415 the source), but I'm not sure it's worth worrying about. */
8417 reg_last_reload_reg[REGNO (incloc)] = 0;
8419 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8421 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8422 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
8426 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8427 inc_amount = -inc_amount;
8429 inc = GEN_INT (inc_amount);
8432 /* If this is post-increment, first copy the location to the reload reg. */
8433 if (post && real_in != reloadreg)
8434 emit_insn (gen_move_insn (reloadreg, real_in));
8438 /* See if we can directly increment INCLOC. Use a method similar to
8439 that in gen_reload. */
8441 last = get_last_insn ();
8442 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8443 gen_rtx_PLUS (GET_MODE (incloc),
8446 code = recog_memoized (add_insn);
8449 extract_insn (add_insn);
8450 if (constrain_operands (1))
8452 /* If this is a pre-increment and we have incremented the value
8453 where it lives, copy the incremented value to RELOADREG to
8454 be used as an address. */
8457 emit_insn (gen_move_insn (reloadreg, incloc));
8462 delete_insns_since (last);
8465 /* If couldn't do the increment directly, must increment in RELOADREG.
8466 The way we do this depends on whether this is pre- or post-increment.
8467 For pre-increment, copy INCLOC to the reload register, increment it
8468 there, then save back. */
8472 if (in != reloadreg)
8473 emit_insn (gen_move_insn (reloadreg, real_in));
8474 emit_insn (gen_add2_insn (reloadreg, inc));
8475 store = emit_insn (gen_move_insn (incloc, reloadreg));
8480 Because this might be a jump insn or a compare, and because RELOADREG
8481 may not be available after the insn in an input reload, we must do
8482 the incrementation before the insn being reloaded for.
8484 We have already copied IN to RELOADREG. Increment the copy in
8485 RELOADREG, save that back, then decrement RELOADREG so it has
8486 the original value. */
8488 emit_insn (gen_add2_insn (reloadreg, inc));
8489 store = emit_insn (gen_move_insn (incloc, reloadreg));
8490 if (GET_CODE (inc) == CONST_INT)
8491 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
8493 emit_insn (gen_sub2_insn (reloadreg, inc));
8501 add_auto_inc_notes (rtx insn, rtx x)
8503 enum rtx_code code = GET_CODE (x);
8507 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8510 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8514 /* Scan all the operand sub-expressions. */
8515 fmt = GET_RTX_FORMAT (code);
8516 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8519 add_auto_inc_notes (insn, XEXP (x, i));
8520 else if (fmt[i] == 'E')
8521 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8522 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8527 /* Copy EH notes from an insn to its reloads. */
8529 copy_eh_notes (rtx insn, rtx x)
8531 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8534 for (; x != 0; x = NEXT_INSN (x))
8536 if (may_trap_p (PATTERN (x)))
8538 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8544 /* This is used by reload pass, that does emit some instructions after
8545 abnormal calls moving basic block end, but in fact it wants to emit
8546 them on the edge. Looks for abnormal call edges, find backward the
8547 proper call and fix the damage.
8549 Similar handle instructions throwing exceptions internally. */
8551 fixup_abnormal_edges (void)
8553 bool inserted = false;
8561 /* Look for cases we are interested in - calls or instructions causing
8563 FOR_EACH_EDGE (e, ei, bb->succs)
8565 if (e->flags & EDGE_ABNORMAL_CALL)
8567 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8568 == (EDGE_ABNORMAL | EDGE_EH))
8571 if (e && !CALL_P (BB_END (bb))
8572 && !can_throw_internal (BB_END (bb)))
8576 /* Get past the new insns generated. Allow notes, as the insns
8577 may be already deleted. */
8579 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8580 && !can_throw_internal (insn)
8581 && insn != BB_HEAD (bb))
8582 insn = PREV_INSN (insn);
8584 if (CALL_P (insn) || can_throw_internal (insn))
8588 stop = NEXT_INSN (BB_END (bb));
8590 insn = NEXT_INSN (insn);
8592 FOR_EACH_EDGE (e, ei, bb->succs)
8593 if (e->flags & EDGE_FALLTHRU)
8596 while (insn && insn != stop)
8598 next = NEXT_INSN (insn);
8603 /* Sometimes there's still the return value USE.
8604 If it's placed after a trapping call (i.e. that
8605 call is the last insn anyway), we have no fallthru
8606 edge. Simply delete this use and don't try to insert
8607 on the non-existent edge. */
8608 if (GET_CODE (PATTERN (insn)) != USE)
8610 /* We're not deleting it, we're moving it. */
8611 INSN_DELETED_P (insn) = 0;
8612 PREV_INSN (insn) = NULL_RTX;
8613 NEXT_INSN (insn) = NULL_RTX;
8615 insert_insn_on_edge (insn, e);
8619 else if (!BARRIER_P (insn))
8620 set_block_for_insn (insn, NULL);
8625 /* It may be that we don't find any such trapping insn. In this
8626 case we discovered quite late that the insn that had been
8627 marked as can_throw_internal in fact couldn't trap at all.
8628 So we should in fact delete the EH edges out of the block. */
8630 purge_dead_edges (bb);
8634 /* We've possibly turned single trapping insn into multiple ones. */
8635 if (flag_non_call_exceptions)
8638 blocks = sbitmap_alloc (last_basic_block);
8639 sbitmap_ones (blocks);
8640 find_many_sub_basic_blocks (blocks);
8641 sbitmap_free (blocks);
8645 commit_edge_insertions ();
8647 #ifdef ENABLE_CHECKING
8648 /* Verify that we didn't turn one trapping insn into many, and that
8649 we found and corrected all of the problems wrt fixups on the
8651 verify_flow_info ();
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