1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "addresses.h"
39 #include "basic-block.h"
52 /* This file contains the reload pass of the compiler, which is
53 run after register allocation has been done. It checks that
54 each insn is valid (operands required to be in registers really
55 are in registers of the proper class) and fixes up invalid ones
56 by copying values temporarily into registers for the insns
59 The results of register allocation are described by the vector
60 reg_renumber; the insns still contain pseudo regs, but reg_renumber
61 can be used to find which hard reg, if any, a pseudo reg is in.
63 The technique we always use is to free up a few hard regs that are
64 called ``reload regs'', and for each place where a pseudo reg
65 must be in a hard reg, copy it temporarily into one of the reload regs.
67 Reload regs are allocated locally for every instruction that needs
68 reloads. When there are pseudos which are allocated to a register that
69 has been chosen as a reload reg, such pseudos must be ``spilled''.
70 This means that they go to other hard regs, or to stack slots if no other
71 available hard regs can be found. Spilling can invalidate more
72 insns, requiring additional need for reloads, so we must keep checking
73 until the process stabilizes.
75 For machines with different classes of registers, we must keep track
76 of the register class needed for each reload, and make sure that
77 we allocate enough reload registers of each class.
79 The file reload.c contains the code that checks one insn for
80 validity and reports the reloads that it needs. This file
81 is in charge of scanning the entire rtl code, accumulating the
82 reload needs, spilling, assigning reload registers to use for
83 fixing up each insn, and generating the new insns to copy values
84 into the reload registers. */
86 /* During reload_as_needed, element N contains a REG rtx for the hard reg
87 into which reg N has been reloaded (perhaps for a previous insn). */
88 static rtx *reg_last_reload_reg;
90 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
91 for an output reload that stores into reg N. */
92 static regset_head reg_has_output_reload;
94 /* Indicates which hard regs are reload-registers for an output reload
95 in the current insn. */
96 static HARD_REG_SET reg_is_output_reload;
98 /* Element N is the constant value to which pseudo reg N is equivalent,
99 or zero if pseudo reg N is not equivalent to a constant.
100 find_reloads looks at this in order to replace pseudo reg N
101 with the constant it stands for. */
102 rtx *reg_equiv_constant;
104 /* Element N is an invariant value to which pseudo reg N is equivalent.
105 eliminate_regs_in_insn uses this to replace pseudos in particular
107 rtx *reg_equiv_invariant;
109 /* Element N is a memory location to which pseudo reg N is equivalent,
110 prior to any register elimination (such as frame pointer to stack
111 pointer). Depending on whether or not it is a valid address, this value
112 is transferred to either reg_equiv_address or reg_equiv_mem. */
113 rtx *reg_equiv_memory_loc;
115 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
116 collector can keep track of what is inside. */
117 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
119 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
120 This is used when the address is not valid as a memory address
121 (because its displacement is too big for the machine.) */
122 rtx *reg_equiv_address;
124 /* Element N is the memory slot to which pseudo reg N is equivalent,
125 or zero if pseudo reg N is not equivalent to a memory slot. */
128 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
129 alternate representations of the location of pseudo reg N. */
130 rtx *reg_equiv_alt_mem_list;
132 /* Widest width in which each pseudo reg is referred to (via subreg). */
133 static unsigned int *reg_max_ref_width;
135 /* Element N is the list of insns that initialized reg N from its equivalent
136 constant or memory slot. */
138 int reg_equiv_init_size;
140 /* Vector to remember old contents of reg_renumber before spilling. */
141 static short *reg_old_renumber;
143 /* During reload_as_needed, element N contains the last pseudo regno reloaded
144 into hard register N. If that pseudo reg occupied more than one register,
145 reg_reloaded_contents points to that pseudo for each spill register in
146 use; all of these must remain set for an inheritance to occur. */
147 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
149 /* During reload_as_needed, element N contains the insn for which
150 hard register N was last used. Its contents are significant only
151 when reg_reloaded_valid is set for this register. */
152 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
154 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
155 static HARD_REG_SET reg_reloaded_valid;
156 /* Indicate if the register was dead at the end of the reload.
157 This is only valid if reg_reloaded_contents is set and valid. */
158 static HARD_REG_SET reg_reloaded_dead;
160 /* Indicate whether the register's current value is one that is not
161 safe to retain across a call, even for registers that are normally
162 call-saved. This is only meaningful for members of reg_reloaded_valid. */
163 static HARD_REG_SET reg_reloaded_call_part_clobbered;
165 /* Number of spill-regs so far; number of valid elements of spill_regs. */
168 /* In parallel with spill_regs, contains REG rtx's for those regs.
169 Holds the last rtx used for any given reg, or 0 if it has never
170 been used for spilling yet. This rtx is reused, provided it has
172 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
174 /* In parallel with spill_regs, contains nonzero for a spill reg
175 that was stored after the last time it was used.
176 The precise value is the insn generated to do the store. */
177 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
179 /* This is the register that was stored with spill_reg_store. This is a
180 copy of reload_out / reload_out_reg when the value was stored; if
181 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
182 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
184 /* This table is the inverse mapping of spill_regs:
185 indexed by hard reg number,
186 it contains the position of that reg in spill_regs,
187 or -1 for something that is not in spill_regs.
189 ?!? This is no longer accurate. */
190 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
192 /* This reg set indicates registers that can't be used as spill registers for
193 the currently processed insn. These are the hard registers which are live
194 during the insn, but not allocated to pseudos, as well as fixed
196 static HARD_REG_SET bad_spill_regs;
198 /* These are the hard registers that can't be used as spill register for any
199 insn. This includes registers used for user variables and registers that
200 we can't eliminate. A register that appears in this set also can't be used
201 to retry register allocation. */
202 static HARD_REG_SET bad_spill_regs_global;
204 /* Describes order of use of registers for reloading
205 of spilled pseudo-registers. `n_spills' is the number of
206 elements that are actually valid; new ones are added at the end.
208 Both spill_regs and spill_reg_order are used on two occasions:
209 once during find_reload_regs, where they keep track of the spill registers
210 for a single insn, but also during reload_as_needed where they show all
211 the registers ever used by reload. For the latter case, the information
212 is calculated during finish_spills. */
213 static short spill_regs[FIRST_PSEUDO_REGISTER];
215 /* This vector of reg sets indicates, for each pseudo, which hard registers
216 may not be used for retrying global allocation because the register was
217 formerly spilled from one of them. If we allowed reallocating a pseudo to
218 a register that it was already allocated to, reload might not
220 static HARD_REG_SET *pseudo_previous_regs;
222 /* This vector of reg sets indicates, for each pseudo, which hard
223 registers may not be used for retrying global allocation because they
224 are used as spill registers during one of the insns in which the
226 static HARD_REG_SET *pseudo_forbidden_regs;
228 /* All hard regs that have been used as spill registers for any insn are
229 marked in this set. */
230 static HARD_REG_SET used_spill_regs;
232 /* Index of last register assigned as a spill register. We allocate in
233 a round-robin fashion. */
234 static int last_spill_reg;
236 /* Nonzero if indirect addressing is supported on the machine; this means
237 that spilling (REG n) does not require reloading it into a register in
238 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
239 value indicates the level of indirect addressing supported, e.g., two
240 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
242 static char spill_indirect_levels;
244 /* Nonzero if indirect addressing is supported when the innermost MEM is
245 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
246 which these are valid is the same as spill_indirect_levels, above. */
247 char indirect_symref_ok;
249 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
250 char double_reg_address_ok;
252 /* Record the stack slot for each spilled hard register. */
253 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
255 /* Width allocated so far for that stack slot. */
256 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
258 /* Record which pseudos needed to be spilled. */
259 static regset_head spilled_pseudos;
261 /* Record which pseudos changed their allocation in finish_spills. */
262 static regset_head changed_allocation_pseudos;
264 /* Used for communication between order_regs_for_reload and count_pseudo.
265 Used to avoid counting one pseudo twice. */
266 static regset_head pseudos_counted;
268 /* First uid used by insns created by reload in this function.
269 Used in find_equiv_reg. */
270 int reload_first_uid;
272 /* Flag set by local-alloc or global-alloc if anything is live in
273 a call-clobbered reg across calls. */
274 int caller_save_needed;
276 /* Set to 1 while reload_as_needed is operating.
277 Required by some machines to handle any generated moves differently. */
278 int reload_in_progress = 0;
280 /* These arrays record the insn_code of insns that may be needed to
281 perform input and output reloads of special objects. They provide a
282 place to pass a scratch register. */
283 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
284 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
286 /* This obstack is used for allocation of rtl during register elimination.
287 The allocated storage can be freed once find_reloads has processed the
289 static struct obstack reload_obstack;
291 /* Points to the beginning of the reload_obstack. All insn_chain structures
292 are allocated first. */
293 static char *reload_startobj;
295 /* The point after all insn_chain structures. Used to quickly deallocate
296 memory allocated in copy_reloads during calculate_needs_all_insns. */
297 static char *reload_firstobj;
299 /* This points before all local rtl generated by register elimination.
300 Used to quickly free all memory after processing one insn. */
301 static char *reload_insn_firstobj;
303 /* List of insn_chain instructions, one for every insn that reload needs to
305 struct insn_chain *reload_insn_chain;
307 /* List of all insns needing reloads. */
308 static struct insn_chain *insns_need_reload;
310 /* This structure is used to record information about register eliminations.
311 Each array entry describes one possible way of eliminating a register
312 in favor of another. If there is more than one way of eliminating a
313 particular register, the most preferred should be specified first. */
317 int from; /* Register number to be eliminated. */
318 int to; /* Register number used as replacement. */
319 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
320 int can_eliminate; /* Nonzero if this elimination can be done. */
321 int can_eliminate_previous; /* Value returned by TARGET_CAN_ELIMINATE
322 target hook in previous scan over insns
324 HOST_WIDE_INT offset; /* Current offset between the two regs. */
325 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
326 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
327 rtx from_rtx; /* REG rtx for the register to be eliminated.
328 We cannot simply compare the number since
329 we might then spuriously replace a hard
330 register corresponding to a pseudo
331 assigned to the reg to be eliminated. */
332 rtx to_rtx; /* REG rtx for the replacement. */
335 static struct elim_table *reg_eliminate = 0;
337 /* This is an intermediate structure to initialize the table. It has
338 exactly the members provided by ELIMINABLE_REGS. */
339 static const struct elim_table_1
343 } reg_eliminate_1[] =
345 /* If a set of eliminable registers was specified, define the table from it.
346 Otherwise, default to the normal case of the frame pointer being
347 replaced by the stack pointer. */
349 #ifdef ELIMINABLE_REGS
352 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
355 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
357 /* Record the number of pending eliminations that have an offset not equal
358 to their initial offset. If nonzero, we use a new copy of each
359 replacement result in any insns encountered. */
360 int num_not_at_initial_offset;
362 /* Count the number of registers that we may be able to eliminate. */
363 static int num_eliminable;
364 /* And the number of registers that are equivalent to a constant that
365 can be eliminated to frame_pointer / arg_pointer + constant. */
366 static int num_eliminable_invariants;
368 /* For each label, we record the offset of each elimination. If we reach
369 a label by more than one path and an offset differs, we cannot do the
370 elimination. This information is indexed by the difference of the
371 number of the label and the first label number. We can't offset the
372 pointer itself as this can cause problems on machines with segmented
373 memory. The first table is an array of flags that records whether we
374 have yet encountered a label and the second table is an array of arrays,
375 one entry in the latter array for each elimination. */
377 static int first_label_num;
378 static char *offsets_known_at;
379 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
381 /* Number of labels in the current function. */
383 static int num_labels;
385 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
386 static void maybe_fix_stack_asms (void);
387 static void copy_reloads (struct insn_chain *);
388 static void calculate_needs_all_insns (int);
389 static int find_reg (struct insn_chain *, int);
390 static void find_reload_regs (struct insn_chain *);
391 static void select_reload_regs (void);
392 static void delete_caller_save_insns (void);
394 static void spill_failure (rtx, enum reg_class);
395 static void count_spilled_pseudo (int, int, int);
396 static void delete_dead_insn (rtx);
397 static void alter_reg (int, int, bool);
398 static void set_label_offsets (rtx, rtx, int);
399 static void check_eliminable_occurrences (rtx);
400 static void elimination_effects (rtx, enum machine_mode);
401 static int eliminate_regs_in_insn (rtx, int);
402 static void update_eliminable_offsets (void);
403 static void mark_not_eliminable (rtx, const_rtx, void *);
404 static void set_initial_elim_offsets (void);
405 static bool verify_initial_elim_offsets (void);
406 static void set_initial_label_offsets (void);
407 static void set_offsets_for_label (rtx);
408 static void init_elim_table (void);
409 static void update_eliminables (HARD_REG_SET *);
410 static void spill_hard_reg (unsigned int, int);
411 static int finish_spills (int);
412 static void scan_paradoxical_subregs (rtx);
413 static void count_pseudo (int);
414 static void order_regs_for_reload (struct insn_chain *);
415 static void reload_as_needed (int);
416 static void forget_old_reloads_1 (rtx, const_rtx, void *);
417 static void forget_marked_reloads (regset);
418 static int reload_reg_class_lower (const void *, const void *);
419 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
421 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
423 static int reload_reg_free_p (unsigned int, int, enum reload_type);
424 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
426 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
428 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
429 static int allocate_reload_reg (struct insn_chain *, int, int);
430 static int conflicts_with_override (rtx);
431 static void failed_reload (rtx, int);
432 static int set_reload_reg (int, int);
433 static void choose_reload_regs_init (struct insn_chain *, rtx *);
434 static void choose_reload_regs (struct insn_chain *);
435 static void merge_assigned_reloads (rtx);
436 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
438 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
440 static void do_input_reload (struct insn_chain *, struct reload *, int);
441 static void do_output_reload (struct insn_chain *, struct reload *, int);
442 static void emit_reload_insns (struct insn_chain *);
443 static void delete_output_reload (rtx, int, int, rtx);
444 static void delete_address_reloads (rtx, rtx);
445 static void delete_address_reloads_1 (rtx, rtx, rtx);
446 static rtx inc_for_reload (rtx, rtx, rtx, int);
448 static void add_auto_inc_notes (rtx, rtx);
450 static void substitute (rtx *, const_rtx, rtx);
451 static bool gen_reload_chain_without_interm_reg_p (int, int);
452 static int reloads_conflict (int, int);
453 static rtx gen_reload (rtx, rtx, int, enum reload_type);
454 static rtx emit_insn_if_valid_for_reload (rtx);
456 /* Initialize the reload pass. This is called at the beginning of compilation
457 and may be called again if the target is reinitialized. */
464 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
465 Set spill_indirect_levels to the number of levels such addressing is
466 permitted, zero if it is not permitted at all. */
469 = gen_rtx_MEM (Pmode,
472 LAST_VIRTUAL_REGISTER + 1),
474 spill_indirect_levels = 0;
476 while (memory_address_p (QImode, tem))
478 spill_indirect_levels++;
479 tem = gen_rtx_MEM (Pmode, tem);
482 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
484 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
485 indirect_symref_ok = memory_address_p (QImode, tem);
487 /* See if reg+reg is a valid (and offsettable) address. */
489 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
491 tem = gen_rtx_PLUS (Pmode,
492 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
493 gen_rtx_REG (Pmode, i));
495 /* This way, we make sure that reg+reg is an offsettable address. */
496 tem = plus_constant (tem, 4);
498 if (memory_address_p (QImode, tem))
500 double_reg_address_ok = 1;
505 /* Initialize obstack for our rtl allocation. */
506 gcc_obstack_init (&reload_obstack);
507 reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
509 INIT_REG_SET (&spilled_pseudos);
510 INIT_REG_SET (&changed_allocation_pseudos);
511 INIT_REG_SET (&pseudos_counted);
514 /* List of insn chains that are currently unused. */
515 static struct insn_chain *unused_insn_chains = 0;
517 /* Allocate an empty insn_chain structure. */
519 new_insn_chain (void)
521 struct insn_chain *c;
523 if (unused_insn_chains == 0)
525 c = XOBNEW (&reload_obstack, struct insn_chain);
526 INIT_REG_SET (&c->live_throughout);
527 INIT_REG_SET (&c->dead_or_set);
531 c = unused_insn_chains;
532 unused_insn_chains = c->next;
534 c->is_caller_save_insn = 0;
535 c->need_operand_change = 0;
541 /* Small utility function to set all regs in hard reg set TO which are
542 allocated to pseudos in regset FROM. */
545 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
548 reg_set_iterator rsi;
550 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
552 int r = reg_renumber[regno];
556 /* reload_combine uses the information from DF_LIVE_IN,
557 which might still contain registers that have not
558 actually been allocated since they have an
560 gcc_assert (ira_conflicts_p || reload_completed);
563 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
567 /* Replace all pseudos found in LOC with their corresponding
571 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
584 unsigned int regno = REGNO (x);
586 if (regno < FIRST_PSEUDO_REGISTER)
589 x = eliminate_regs (x, mem_mode, usage);
593 replace_pseudos_in (loc, mem_mode, usage);
597 if (reg_equiv_constant[regno])
598 *loc = reg_equiv_constant[regno];
599 else if (reg_equiv_mem[regno])
600 *loc = reg_equiv_mem[regno];
601 else if (reg_equiv_address[regno])
602 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
605 gcc_assert (!REG_P (regno_reg_rtx[regno])
606 || REGNO (regno_reg_rtx[regno]) != regno);
607 *loc = regno_reg_rtx[regno];
612 else if (code == MEM)
614 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
618 /* Process each of our operands recursively. */
619 fmt = GET_RTX_FORMAT (code);
620 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
622 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
623 else if (*fmt == 'E')
624 for (j = 0; j < XVECLEN (x, i); j++)
625 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
628 /* Determine if the current function has an exception receiver block
629 that reaches the exit block via non-exceptional edges */
632 has_nonexceptional_receiver (void)
636 basic_block *tos, *worklist, bb;
638 /* If we're not optimizing, then just err on the safe side. */
642 /* First determine which blocks can reach exit via normal paths. */
643 tos = worklist = XNEWVEC (basic_block, n_basic_blocks + 1);
646 bb->flags &= ~BB_REACHABLE;
648 /* Place the exit block on our worklist. */
649 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
650 *tos++ = EXIT_BLOCK_PTR;
652 /* Iterate: find everything reachable from what we've already seen. */
653 while (tos != worklist)
657 FOR_EACH_EDGE (e, ei, bb->preds)
658 if (!(e->flags & EDGE_ABNORMAL))
660 basic_block src = e->src;
662 if (!(src->flags & BB_REACHABLE))
664 src->flags |= BB_REACHABLE;
671 /* Now see if there's a reachable block with an exceptional incoming
674 if (bb->flags & BB_REACHABLE)
675 FOR_EACH_EDGE (e, ei, bb->preds)
676 if (e->flags & EDGE_ABNORMAL)
679 /* No exceptional block reached exit unexceptionally. */
684 /* Global variables used by reload and its subroutines. */
686 /* Set during calculate_needs if an insn needs register elimination. */
687 static int something_needs_elimination;
688 /* Set during calculate_needs if an insn needs an operand changed. */
689 static int something_needs_operands_changed;
691 /* Nonzero means we couldn't get enough spill regs. */
694 /* Temporary array of pseudo-register number. */
695 static int *temp_pseudo_reg_arr;
697 /* Main entry point for the reload pass.
699 FIRST is the first insn of the function being compiled.
701 GLOBAL nonzero means we were called from global_alloc
702 and should attempt to reallocate any pseudoregs that we
703 displace from hard regs we will use for reloads.
704 If GLOBAL is zero, we do not have enough information to do that,
705 so any pseudo reg that is spilled must go to the stack.
707 Return value is nonzero if reload failed
708 and we must not do any more for this function. */
711 reload (rtx first, int global)
715 struct elim_table *ep;
718 /* Make sure even insns with volatile mem refs are recognizable. */
723 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
725 /* Make sure that the last insn in the chain
726 is not something that needs reloading. */
727 emit_note (NOTE_INSN_DELETED);
729 /* Enable find_equiv_reg to distinguish insns made by reload. */
730 reload_first_uid = get_max_uid ();
732 #ifdef SECONDARY_MEMORY_NEEDED
733 /* Initialize the secondary memory table. */
734 clear_secondary_mem ();
737 /* We don't have a stack slot for any spill reg yet. */
738 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
739 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
741 /* Initialize the save area information for caller-save, in case some
745 /* Compute which hard registers are now in use
746 as homes for pseudo registers.
747 This is done here rather than (eg) in global_alloc
748 because this point is reached even if not optimizing. */
749 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
752 /* A function that has a nonlocal label that can reach the exit
753 block via non-exceptional paths must save all call-saved
755 if (cfun->has_nonlocal_label
756 && has_nonexceptional_receiver ())
757 crtl->saves_all_registers = 1;
759 if (crtl->saves_all_registers)
760 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
761 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
762 df_set_regs_ever_live (i, true);
764 /* Find all the pseudo registers that didn't get hard regs
765 but do have known equivalent constants or memory slots.
766 These include parameters (known equivalent to parameter slots)
767 and cse'd or loop-moved constant memory addresses.
769 Record constant equivalents in reg_equiv_constant
770 so they will be substituted by find_reloads.
771 Record memory equivalents in reg_mem_equiv so they can
772 be substituted eventually by altering the REG-rtx's. */
774 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
775 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
776 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
777 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
778 reg_equiv_address = XCNEWVEC (rtx, max_regno);
779 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
780 reg_old_renumber = XCNEWVEC (short, max_regno);
781 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
782 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
783 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
785 CLEAR_HARD_REG_SET (bad_spill_regs_global);
787 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
788 to. Also find all paradoxical subregs and find largest such for
791 num_eliminable_invariants = 0;
792 for (insn = first; insn; insn = NEXT_INSN (insn))
794 rtx set = single_set (insn);
796 /* We may introduce USEs that we want to remove at the end, so
797 we'll mark them with QImode. Make sure there are no
798 previously-marked insns left by say regmove. */
799 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
800 && GET_MODE (insn) != VOIDmode)
801 PUT_MODE (insn, VOIDmode);
803 if (NONDEBUG_INSN_P (insn))
804 scan_paradoxical_subregs (PATTERN (insn));
806 if (set != 0 && REG_P (SET_DEST (set)))
808 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
814 i = REGNO (SET_DEST (set));
817 if (i <= LAST_VIRTUAL_REGISTER)
820 if (! function_invariant_p (x)
822 /* A function invariant is often CONSTANT_P but may
823 include a register. We promise to only pass
824 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
826 && LEGITIMATE_PIC_OPERAND_P (x)))
828 /* It can happen that a REG_EQUIV note contains a MEM
829 that is not a legitimate memory operand. As later
830 stages of reload assume that all addresses found
831 in the reg_equiv_* arrays were originally legitimate,
832 we ignore such REG_EQUIV notes. */
833 if (memory_operand (x, VOIDmode))
835 /* Always unshare the equivalence, so we can
836 substitute into this insn without touching the
838 reg_equiv_memory_loc[i] = copy_rtx (x);
840 else if (function_invariant_p (x))
842 if (GET_CODE (x) == PLUS)
844 /* This is PLUS of frame pointer and a constant,
845 and might be shared. Unshare it. */
846 reg_equiv_invariant[i] = copy_rtx (x);
847 num_eliminable_invariants++;
849 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
851 reg_equiv_invariant[i] = x;
852 num_eliminable_invariants++;
854 else if (LEGITIMATE_CONSTANT_P (x))
855 reg_equiv_constant[i] = x;
858 reg_equiv_memory_loc[i]
859 = force_const_mem (GET_MODE (SET_DEST (set)), x);
860 if (! reg_equiv_memory_loc[i])
861 reg_equiv_init[i] = NULL_RTX;
866 reg_equiv_init[i] = NULL_RTX;
871 reg_equiv_init[i] = NULL_RTX;
876 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
877 if (reg_equiv_init[i])
879 fprintf (dump_file, "init_insns for %u: ", i);
880 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
881 fprintf (dump_file, "\n");
886 first_label_num = get_first_label_num ();
887 num_labels = max_label_num () - first_label_num;
889 /* Allocate the tables used to store offset information at labels. */
890 /* We used to use alloca here, but the size of what it would try to
891 allocate would occasionally cause it to exceed the stack limit and
892 cause a core dump. */
893 offsets_known_at = XNEWVEC (char, num_labels);
894 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
896 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
897 stack slots to the pseudos that lack hard regs or equivalents.
898 Do not touch virtual registers. */
900 temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
901 for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
902 temp_pseudo_reg_arr[n++] = i;
905 /* Ask IRA to order pseudo-registers for better stack slot
907 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width);
909 for (i = 0; i < n; i++)
910 alter_reg (temp_pseudo_reg_arr[i], -1, false);
912 /* If we have some registers we think can be eliminated, scan all insns to
913 see if there is an insn that sets one of these registers to something
914 other than itself plus a constant. If so, the register cannot be
915 eliminated. Doing this scan here eliminates an extra pass through the
916 main reload loop in the most common case where register elimination
918 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
920 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
922 maybe_fix_stack_asms ();
924 insns_need_reload = 0;
925 something_needs_elimination = 0;
927 /* Initialize to -1, which means take the first spill register. */
930 /* Spill any hard regs that we know we can't eliminate. */
931 CLEAR_HARD_REG_SET (used_spill_regs);
932 /* There can be multiple ways to eliminate a register;
933 they should be listed adjacently.
934 Elimination for any register fails only if all possible ways fail. */
935 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
938 int can_eliminate = 0;
941 can_eliminate |= ep->can_eliminate;
944 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
946 spill_hard_reg (from, 1);
949 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
950 if (frame_pointer_needed)
951 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
953 finish_spills (global);
955 /* From now on, we may need to generate moves differently. We may also
956 allow modifications of insns which cause them to not be recognized.
957 Any such modifications will be cleaned up during reload itself. */
958 reload_in_progress = 1;
960 /* This loop scans the entire function each go-round
961 and repeats until one repetition spills no additional hard regs. */
964 int something_changed;
966 HOST_WIDE_INT starting_frame_size;
968 starting_frame_size = get_frame_size ();
970 set_initial_elim_offsets ();
971 set_initial_label_offsets ();
973 /* For each pseudo register that has an equivalent location defined,
974 try to eliminate any eliminable registers (such as the frame pointer)
975 assuming initial offsets for the replacement register, which
978 If the resulting location is directly addressable, substitute
979 the MEM we just got directly for the old REG.
981 If it is not addressable but is a constant or the sum of a hard reg
982 and constant, it is probably not addressable because the constant is
983 out of range, in that case record the address; we will generate
984 hairy code to compute the address in a register each time it is
985 needed. Similarly if it is a hard register, but one that is not
986 valid as an address register.
988 If the location is not addressable, but does not have one of the
989 above forms, assign a stack slot. We have to do this to avoid the
990 potential of producing lots of reloads if, e.g., a location involves
991 a pseudo that didn't get a hard register and has an equivalent memory
992 location that also involves a pseudo that didn't get a hard register.
994 Perhaps at some point we will improve reload_when_needed handling
995 so this problem goes away. But that's very hairy. */
997 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
998 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
1000 rtx x = eliminate_regs (reg_equiv_memory_loc[i], VOIDmode,
1003 if (strict_memory_address_addr_space_p
1004 (GET_MODE (regno_reg_rtx[i]), XEXP (x, 0),
1005 MEM_ADDR_SPACE (x)))
1006 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
1007 else if (CONSTANT_P (XEXP (x, 0))
1008 || (REG_P (XEXP (x, 0))
1009 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
1010 || (GET_CODE (XEXP (x, 0)) == PLUS
1011 && REG_P (XEXP (XEXP (x, 0), 0))
1012 && (REGNO (XEXP (XEXP (x, 0), 0))
1013 < FIRST_PSEUDO_REGISTER)
1014 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
1015 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
1018 /* Make a new stack slot. Then indicate that something
1019 changed so we go back and recompute offsets for
1020 eliminable registers because the allocation of memory
1021 below might change some offset. reg_equiv_{mem,address}
1022 will be set up for this pseudo on the next pass around
1024 reg_equiv_memory_loc[i] = 0;
1025 reg_equiv_init[i] = 0;
1026 alter_reg (i, -1, true);
1030 if (caller_save_needed)
1031 setup_save_areas ();
1033 /* If we allocated another stack slot, redo elimination bookkeeping. */
1034 if (starting_frame_size != get_frame_size ())
1036 if (starting_frame_size && crtl->stack_alignment_needed)
1038 /* If we have a stack frame, we must align it now. The
1039 stack size may be a part of the offset computation for
1040 register elimination. So if this changes the stack size,
1041 then repeat the elimination bookkeeping. We don't
1042 realign when there is no stack, as that will cause a
1043 stack frame when none is needed should
1044 STARTING_FRAME_OFFSET not be already aligned to
1046 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
1047 if (starting_frame_size != get_frame_size ())
1051 if (caller_save_needed)
1053 save_call_clobbered_regs ();
1054 /* That might have allocated new insn_chain structures. */
1055 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1058 calculate_needs_all_insns (global);
1060 if (! ira_conflicts_p)
1061 /* Don't do it for IRA. We need this info because we don't
1062 change live_throughout and dead_or_set for chains when IRA
1064 CLEAR_REG_SET (&spilled_pseudos);
1068 something_changed = 0;
1070 /* If we allocated any new memory locations, make another pass
1071 since it might have changed elimination offsets. */
1072 if (starting_frame_size != get_frame_size ())
1073 something_changed = 1;
1075 /* Even if the frame size remained the same, we might still have
1076 changed elimination offsets, e.g. if find_reloads called
1077 force_const_mem requiring the back end to allocate a constant
1078 pool base register that needs to be saved on the stack. */
1079 else if (!verify_initial_elim_offsets ())
1080 something_changed = 1;
1083 HARD_REG_SET to_spill;
1084 CLEAR_HARD_REG_SET (to_spill);
1085 update_eliminables (&to_spill);
1086 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
1088 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1089 if (TEST_HARD_REG_BIT (to_spill, i))
1091 spill_hard_reg (i, 1);
1094 /* Regardless of the state of spills, if we previously had
1095 a register that we thought we could eliminate, but now can
1096 not eliminate, we must run another pass.
1098 Consider pseudos which have an entry in reg_equiv_* which
1099 reference an eliminable register. We must make another pass
1100 to update reg_equiv_* so that we do not substitute in the
1101 old value from when we thought the elimination could be
1103 something_changed = 1;
1107 select_reload_regs ();
1111 if (insns_need_reload != 0 || did_spill)
1112 something_changed |= finish_spills (global);
1114 if (! something_changed)
1117 if (caller_save_needed)
1118 delete_caller_save_insns ();
1120 obstack_free (&reload_obstack, reload_firstobj);
1123 /* If global-alloc was run, notify it of any register eliminations we have
1126 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1127 if (ep->can_eliminate)
1128 mark_elimination (ep->from, ep->to);
1130 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1131 If that insn didn't set the register (i.e., it copied the register to
1132 memory), just delete that insn instead of the equivalencing insn plus
1133 anything now dead. If we call delete_dead_insn on that insn, we may
1134 delete the insn that actually sets the register if the register dies
1135 there and that is incorrect. */
1137 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1139 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1142 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1144 rtx equiv_insn = XEXP (list, 0);
1146 /* If we already deleted the insn or if it may trap, we can't
1147 delete it. The latter case shouldn't happen, but can
1148 if an insn has a variable address, gets a REG_EH_REGION
1149 note added to it, and then gets converted into a load
1150 from a constant address. */
1151 if (NOTE_P (equiv_insn)
1152 || can_throw_internal (equiv_insn))
1154 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1155 delete_dead_insn (equiv_insn);
1157 SET_INSN_DELETED (equiv_insn);
1162 /* Use the reload registers where necessary
1163 by generating move instructions to move the must-be-register
1164 values into or out of the reload registers. */
1166 if (insns_need_reload != 0 || something_needs_elimination
1167 || something_needs_operands_changed)
1169 HOST_WIDE_INT old_frame_size = get_frame_size ();
1171 reload_as_needed (global);
1173 gcc_assert (old_frame_size == get_frame_size ());
1175 gcc_assert (verify_initial_elim_offsets ());
1178 /* If we were able to eliminate the frame pointer, show that it is no
1179 longer live at the start of any basic block. If it ls live by
1180 virtue of being in a pseudo, that pseudo will be marked live
1181 and hence the frame pointer will be known to be live via that
1184 if (! frame_pointer_needed)
1186 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1188 /* Come here (with failure set nonzero) if we can't get enough spill
1192 CLEAR_REG_SET (&changed_allocation_pseudos);
1193 CLEAR_REG_SET (&spilled_pseudos);
1194 reload_in_progress = 0;
1196 /* Now eliminate all pseudo regs by modifying them into
1197 their equivalent memory references.
1198 The REG-rtx's for the pseudos are modified in place,
1199 so all insns that used to refer to them now refer to memory.
1201 For a reg that has a reg_equiv_address, all those insns
1202 were changed by reloading so that no insns refer to it any longer;
1203 but the DECL_RTL of a variable decl may refer to it,
1204 and if so this causes the debugging info to mention the variable. */
1206 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1210 if (reg_equiv_mem[i])
1211 addr = XEXP (reg_equiv_mem[i], 0);
1213 if (reg_equiv_address[i])
1214 addr = reg_equiv_address[i];
1218 if (reg_renumber[i] < 0)
1220 rtx reg = regno_reg_rtx[i];
1222 REG_USERVAR_P (reg) = 0;
1223 PUT_CODE (reg, MEM);
1224 XEXP (reg, 0) = addr;
1225 if (reg_equiv_memory_loc[i])
1226 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1229 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1230 MEM_ATTRS (reg) = 0;
1232 MEM_NOTRAP_P (reg) = 1;
1234 else if (reg_equiv_mem[i])
1235 XEXP (reg_equiv_mem[i], 0) = addr;
1238 /* We don't want complex addressing modes in debug insns
1239 if simpler ones will do, so delegitimize equivalences
1241 if (MAY_HAVE_DEBUG_INSNS && reg_renumber[i] < 0)
1243 rtx reg = regno_reg_rtx[i];
1247 if (reg_equiv_constant[i])
1248 equiv = reg_equiv_constant[i];
1249 else if (reg_equiv_invariant[i])
1250 equiv = reg_equiv_invariant[i];
1251 else if (reg && MEM_P (reg))
1252 equiv = targetm.delegitimize_address (reg);
1253 else if (reg && REG_P (reg) && (int)REGNO (reg) != i)
1259 for (use = DF_REG_USE_CHAIN (i); use; use = next)
1261 insn = DF_REF_INSN (use);
1263 /* Make sure the next ref is for a different instruction,
1264 so that we're not affected by the rescan. */
1265 next = DF_REF_NEXT_REG (use);
1266 while (next && DF_REF_INSN (next) == insn)
1267 next = DF_REF_NEXT_REG (next);
1269 if (DEBUG_INSN_P (insn))
1273 INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
1274 df_insn_rescan_debug_internal (insn);
1277 INSN_VAR_LOCATION_LOC (insn)
1278 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn),
1285 /* We must set reload_completed now since the cleanup_subreg_operands call
1286 below will re-recognize each insn and reload may have generated insns
1287 which are only valid during and after reload. */
1288 reload_completed = 1;
1290 /* Make a pass over all the insns and delete all USEs which we inserted
1291 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1292 notes. Delete all CLOBBER insns, except those that refer to the return
1293 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1294 from misarranging variable-array code, and simplify (subreg (reg))
1295 operands. Strip and regenerate REG_INC notes that may have been moved
1298 for (insn = first; insn; insn = NEXT_INSN (insn))
1304 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1305 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1307 if ((GET_CODE (PATTERN (insn)) == USE
1308 /* We mark with QImode USEs introduced by reload itself. */
1309 && (GET_MODE (insn) == QImode
1310 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1311 || (GET_CODE (PATTERN (insn)) == CLOBBER
1312 && (!MEM_P (XEXP (PATTERN (insn), 0))
1313 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1314 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1315 && XEXP (XEXP (PATTERN (insn), 0), 0)
1316 != stack_pointer_rtx))
1317 && (!REG_P (XEXP (PATTERN (insn), 0))
1318 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1324 /* Some CLOBBERs may survive until here and still reference unassigned
1325 pseudos with const equivalent, which may in turn cause ICE in later
1326 passes if the reference remains in place. */
1327 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1328 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1329 VOIDmode, PATTERN (insn));
1331 /* Discard obvious no-ops, even without -O. This optimization
1332 is fast and doesn't interfere with debugging. */
1333 if (NONJUMP_INSN_P (insn)
1334 && GET_CODE (PATTERN (insn)) == SET
1335 && REG_P (SET_SRC (PATTERN (insn)))
1336 && REG_P (SET_DEST (PATTERN (insn)))
1337 && (REGNO (SET_SRC (PATTERN (insn)))
1338 == REGNO (SET_DEST (PATTERN (insn)))))
1344 pnote = ®_NOTES (insn);
1347 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1348 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1349 || REG_NOTE_KIND (*pnote) == REG_INC)
1350 *pnote = XEXP (*pnote, 1);
1352 pnote = &XEXP (*pnote, 1);
1356 add_auto_inc_notes (insn, PATTERN (insn));
1359 /* Simplify (subreg (reg)) if it appears as an operand. */
1360 cleanup_subreg_operands (insn);
1362 /* Clean up invalid ASMs so that they don't confuse later passes.
1364 if (asm_noperands (PATTERN (insn)) >= 0)
1366 extract_insn (insn);
1367 if (!constrain_operands (1))
1369 error_for_asm (insn,
1370 "%<asm%> operand has impossible constraints");
1377 /* If we are doing generic stack checking, give a warning if this
1378 function's frame size is larger than we expect. */
1379 if (flag_stack_check == GENERIC_STACK_CHECK)
1381 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1382 static int verbose_warned = 0;
1384 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1385 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1386 size += UNITS_PER_WORD;
1388 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1390 warning (0, "frame size too large for reliable stack checking");
1391 if (! verbose_warned)
1393 warning (0, "try reducing the number of local variables");
1399 /* Indicate that we no longer have known memory locations or constants. */
1400 if (reg_equiv_constant)
1401 free (reg_equiv_constant);
1402 if (reg_equiv_invariant)
1403 free (reg_equiv_invariant);
1404 reg_equiv_constant = 0;
1405 reg_equiv_invariant = 0;
1406 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
1407 reg_equiv_memory_loc = 0;
1409 free (temp_pseudo_reg_arr);
1411 if (offsets_known_at)
1412 free (offsets_known_at);
1416 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1417 if (reg_equiv_alt_mem_list[i])
1418 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
1419 free (reg_equiv_alt_mem_list);
1421 free (reg_equiv_mem);
1423 free (reg_equiv_address);
1424 free (reg_max_ref_width);
1425 free (reg_old_renumber);
1426 free (pseudo_previous_regs);
1427 free (pseudo_forbidden_regs);
1429 CLEAR_HARD_REG_SET (used_spill_regs);
1430 for (i = 0; i < n_spills; i++)
1431 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1433 /* Free all the insn_chain structures at once. */
1434 obstack_free (&reload_obstack, reload_startobj);
1435 unused_insn_chains = 0;
1436 fixup_abnormal_edges ();
1438 /* Replacing pseudos with their memory equivalents might have
1439 created shared rtx. Subsequent passes would get confused
1440 by this, so unshare everything here. */
1441 unshare_all_rtl_again (first);
1443 #ifdef STACK_BOUNDARY
1444 /* init_emit has set the alignment of the hard frame pointer
1445 to STACK_BOUNDARY. It is very likely no longer valid if
1446 the hard frame pointer was used for register allocation. */
1447 if (!frame_pointer_needed)
1448 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1454 /* Yet another special case. Unfortunately, reg-stack forces people to
1455 write incorrect clobbers in asm statements. These clobbers must not
1456 cause the register to appear in bad_spill_regs, otherwise we'll call
1457 fatal_insn later. We clear the corresponding regnos in the live
1458 register sets to avoid this.
1459 The whole thing is rather sick, I'm afraid. */
1462 maybe_fix_stack_asms (void)
1465 const char *constraints[MAX_RECOG_OPERANDS];
1466 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1467 struct insn_chain *chain;
1469 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1472 HARD_REG_SET clobbered, allowed;
1475 if (! INSN_P (chain->insn)
1476 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1478 pat = PATTERN (chain->insn);
1479 if (GET_CODE (pat) != PARALLEL)
1482 CLEAR_HARD_REG_SET (clobbered);
1483 CLEAR_HARD_REG_SET (allowed);
1485 /* First, make a mask of all stack regs that are clobbered. */
1486 for (i = 0; i < XVECLEN (pat, 0); i++)
1488 rtx t = XVECEXP (pat, 0, i);
1489 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1490 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1493 /* Get the operand values and constraints out of the insn. */
1494 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1495 constraints, operand_mode, NULL);
1497 /* For every operand, see what registers are allowed. */
1498 for (i = 0; i < noperands; i++)
1500 const char *p = constraints[i];
1501 /* For every alternative, we compute the class of registers allowed
1502 for reloading in CLS, and merge its contents into the reg set
1504 int cls = (int) NO_REGS;
1510 if (c == '\0' || c == ',' || c == '#')
1512 /* End of one alternative - mark the regs in the current
1513 class, and reset the class. */
1514 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1520 } while (c != '\0' && c != ',');
1528 case '=': case '+': case '*': case '%': case '?': case '!':
1529 case '0': case '1': case '2': case '3': case '4': case '<':
1530 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1531 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1532 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1533 case TARGET_MEM_CONSTRAINT:
1537 cls = (int) reg_class_subunion[cls]
1538 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1543 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1547 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1548 cls = (int) reg_class_subunion[cls]
1549 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1551 cls = (int) reg_class_subunion[cls]
1552 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1554 p += CONSTRAINT_LEN (c, p);
1557 /* Those of the registers which are clobbered, but allowed by the
1558 constraints, must be usable as reload registers. So clear them
1559 out of the life information. */
1560 AND_HARD_REG_SET (allowed, clobbered);
1561 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1562 if (TEST_HARD_REG_BIT (allowed, i))
1564 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1565 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1572 /* Copy the global variables n_reloads and rld into the corresponding elts
1575 copy_reloads (struct insn_chain *chain)
1577 chain->n_reloads = n_reloads;
1578 chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1579 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1580 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1583 /* Walk the chain of insns, and determine for each whether it needs reloads
1584 and/or eliminations. Build the corresponding insns_need_reload list, and
1585 set something_needs_elimination as appropriate. */
1587 calculate_needs_all_insns (int global)
1589 struct insn_chain **pprev_reload = &insns_need_reload;
1590 struct insn_chain *chain, *next = 0;
1592 something_needs_elimination = 0;
1594 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1595 for (chain = reload_insn_chain; chain != 0; chain = next)
1597 rtx insn = chain->insn;
1601 /* Clear out the shortcuts. */
1602 chain->n_reloads = 0;
1603 chain->need_elim = 0;
1604 chain->need_reload = 0;
1605 chain->need_operand_change = 0;
1607 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1608 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1609 what effects this has on the known offsets at labels. */
1611 if (LABEL_P (insn) || JUMP_P (insn)
1612 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1613 set_label_offsets (insn, insn, 0);
1617 rtx old_body = PATTERN (insn);
1618 int old_code = INSN_CODE (insn);
1619 rtx old_notes = REG_NOTES (insn);
1620 int did_elimination = 0;
1621 int operands_changed = 0;
1622 rtx set = single_set (insn);
1624 /* Skip insns that only set an equivalence. */
1625 if (set && REG_P (SET_DEST (set))
1626 && reg_renumber[REGNO (SET_DEST (set))] < 0
1627 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1628 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1629 && reg_equiv_init[REGNO (SET_DEST (set))])
1632 /* If needed, eliminate any eliminable registers. */
1633 if (num_eliminable || num_eliminable_invariants)
1634 did_elimination = eliminate_regs_in_insn (insn, 0);
1636 /* Analyze the instruction. */
1637 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1638 global, spill_reg_order);
1640 /* If a no-op set needs more than one reload, this is likely
1641 to be something that needs input address reloads. We
1642 can't get rid of this cleanly later, and it is of no use
1643 anyway, so discard it now.
1644 We only do this when expensive_optimizations is enabled,
1645 since this complements reload inheritance / output
1646 reload deletion, and it can make debugging harder. */
1647 if (flag_expensive_optimizations && n_reloads > 1)
1649 rtx set = single_set (insn);
1652 ((SET_SRC (set) == SET_DEST (set)
1653 && REG_P (SET_SRC (set))
1654 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1655 || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1656 && reg_renumber[REGNO (SET_SRC (set))] < 0
1657 && reg_renumber[REGNO (SET_DEST (set))] < 0
1658 && reg_equiv_memory_loc[REGNO (SET_SRC (set))] != NULL
1659 && reg_equiv_memory_loc[REGNO (SET_DEST (set))] != NULL
1660 && rtx_equal_p (reg_equiv_memory_loc
1661 [REGNO (SET_SRC (set))],
1662 reg_equiv_memory_loc
1663 [REGNO (SET_DEST (set))]))))
1665 if (ira_conflicts_p)
1666 /* Inform IRA about the insn deletion. */
1667 ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1668 REGNO (SET_SRC (set)));
1670 /* Delete it from the reload chain. */
1672 chain->prev->next = next;
1674 reload_insn_chain = next;
1676 next->prev = chain->prev;
1677 chain->next = unused_insn_chains;
1678 unused_insn_chains = chain;
1683 update_eliminable_offsets ();
1685 /* Remember for later shortcuts which insns had any reloads or
1686 register eliminations. */
1687 chain->need_elim = did_elimination;
1688 chain->need_reload = n_reloads > 0;
1689 chain->need_operand_change = operands_changed;
1691 /* Discard any register replacements done. */
1692 if (did_elimination)
1694 obstack_free (&reload_obstack, reload_insn_firstobj);
1695 PATTERN (insn) = old_body;
1696 INSN_CODE (insn) = old_code;
1697 REG_NOTES (insn) = old_notes;
1698 something_needs_elimination = 1;
1701 something_needs_operands_changed |= operands_changed;
1705 copy_reloads (chain);
1706 *pprev_reload = chain;
1707 pprev_reload = &chain->next_need_reload;
1714 /* Comparison function for qsort to decide which of two reloads
1715 should be handled first. *P1 and *P2 are the reload numbers. */
1718 reload_reg_class_lower (const void *r1p, const void *r2p)
1720 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1723 /* Consider required reloads before optional ones. */
1724 t = rld[r1].optional - rld[r2].optional;
1728 /* Count all solitary classes before non-solitary ones. */
1729 t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1730 - (reg_class_size[(int) rld[r1].rclass] == 1));
1734 /* Aside from solitaires, consider all multi-reg groups first. */
1735 t = rld[r2].nregs - rld[r1].nregs;
1739 /* Consider reloads in order of increasing reg-class number. */
1740 t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1744 /* If reloads are equally urgent, sort by reload number,
1745 so that the results of qsort leave nothing to chance. */
1749 /* The cost of spilling each hard reg. */
1750 static int spill_cost[FIRST_PSEUDO_REGISTER];
1752 /* When spilling multiple hard registers, we use SPILL_COST for the first
1753 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1754 only the first hard reg for a multi-reg pseudo. */
1755 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1757 /* Map of hard regno to pseudo regno currently occupying the hard
1759 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1761 /* Update the spill cost arrays, considering that pseudo REG is live. */
1764 count_pseudo (int reg)
1766 int freq = REG_FREQ (reg);
1767 int r = reg_renumber[reg];
1770 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1771 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1772 /* Ignore spilled pseudo-registers which can be here only if IRA
1774 || (ira_conflicts_p && r < 0))
1777 SET_REGNO_REG_SET (&pseudos_counted, reg);
1779 gcc_assert (r >= 0);
1781 spill_add_cost[r] += freq;
1782 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1785 hard_regno_to_pseudo_regno[r + nregs] = reg;
1786 spill_cost[r + nregs] += freq;
1790 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1791 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1794 order_regs_for_reload (struct insn_chain *chain)
1797 HARD_REG_SET used_by_pseudos;
1798 HARD_REG_SET used_by_pseudos2;
1799 reg_set_iterator rsi;
1801 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1803 memset (spill_cost, 0, sizeof spill_cost);
1804 memset (spill_add_cost, 0, sizeof spill_add_cost);
1805 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1806 hard_regno_to_pseudo_regno[i] = -1;
1808 /* Count number of uses of each hard reg by pseudo regs allocated to it
1809 and then order them by decreasing use. First exclude hard registers
1810 that are live in or across this insn. */
1812 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1813 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1814 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1815 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1817 /* Now find out which pseudos are allocated to it, and update
1819 CLEAR_REG_SET (&pseudos_counted);
1821 EXECUTE_IF_SET_IN_REG_SET
1822 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1826 EXECUTE_IF_SET_IN_REG_SET
1827 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1831 CLEAR_REG_SET (&pseudos_counted);
1834 /* Vector of reload-numbers showing the order in which the reloads should
1836 static short reload_order[MAX_RELOADS];
1838 /* This is used to keep track of the spill regs used in one insn. */
1839 static HARD_REG_SET used_spill_regs_local;
1841 /* We decided to spill hard register SPILLED, which has a size of
1842 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1843 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1844 update SPILL_COST/SPILL_ADD_COST. */
1847 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1849 int freq = REG_FREQ (reg);
1850 int r = reg_renumber[reg];
1851 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1853 /* Ignore spilled pseudo-registers which can be here only if IRA is
1855 if ((ira_conflicts_p && r < 0)
1856 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1857 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1860 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1862 spill_add_cost[r] -= freq;
1865 hard_regno_to_pseudo_regno[r + nregs] = -1;
1866 spill_cost[r + nregs] -= freq;
1870 /* Find reload register to use for reload number ORDER. */
1873 find_reg (struct insn_chain *chain, int order)
1875 int rnum = reload_order[order];
1876 struct reload *rl = rld + rnum;
1877 int best_cost = INT_MAX;
1879 unsigned int i, j, n;
1881 HARD_REG_SET not_usable;
1882 HARD_REG_SET used_by_other_reload;
1883 reg_set_iterator rsi;
1884 static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1885 static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1887 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1888 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1889 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
1891 CLEAR_HARD_REG_SET (used_by_other_reload);
1892 for (k = 0; k < order; k++)
1894 int other = reload_order[k];
1896 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1897 for (j = 0; j < rld[other].nregs; j++)
1898 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1901 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1903 #ifdef REG_ALLOC_ORDER
1904 unsigned int regno = reg_alloc_order[i];
1906 unsigned int regno = i;
1909 if (! TEST_HARD_REG_BIT (not_usable, regno)
1910 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1911 && HARD_REGNO_MODE_OK (regno, rl->mode))
1913 int this_cost = spill_cost[regno];
1915 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1917 for (j = 1; j < this_nregs; j++)
1919 this_cost += spill_add_cost[regno + j];
1920 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1921 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1927 if (ira_conflicts_p)
1929 /* Ask IRA to find a better pseudo-register for
1931 for (n = j = 0; j < this_nregs; j++)
1933 int r = hard_regno_to_pseudo_regno[regno + j];
1937 if (n == 0 || regno_pseudo_regs[n - 1] != r)
1938 regno_pseudo_regs[n++] = r;
1940 regno_pseudo_regs[n++] = -1;
1942 || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1943 best_regno_pseudo_regs,
1950 best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1951 if (regno_pseudo_regs[j] < 0)
1958 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1960 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1962 if (this_cost < best_cost
1963 /* Among registers with equal cost, prefer caller-saved ones, or
1964 use REG_ALLOC_ORDER if it is defined. */
1965 || (this_cost == best_cost
1966 #ifdef REG_ALLOC_ORDER
1967 && (inv_reg_alloc_order[regno]
1968 < inv_reg_alloc_order[best_reg])
1970 && call_used_regs[regno]
1971 && ! call_used_regs[best_reg]
1976 best_cost = this_cost;
1984 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1986 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1987 rl->regno = best_reg;
1989 EXECUTE_IF_SET_IN_REG_SET
1990 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1992 count_spilled_pseudo (best_reg, rl->nregs, j);
1995 EXECUTE_IF_SET_IN_REG_SET
1996 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1998 count_spilled_pseudo (best_reg, rl->nregs, j);
2001 for (i = 0; i < rl->nregs; i++)
2003 gcc_assert (spill_cost[best_reg + i] == 0);
2004 gcc_assert (spill_add_cost[best_reg + i] == 0);
2005 gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
2006 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
2011 /* Find more reload regs to satisfy the remaining need of an insn, which
2013 Do it by ascending class number, since otherwise a reg
2014 might be spilled for a big class and might fail to count
2015 for a smaller class even though it belongs to that class. */
2018 find_reload_regs (struct insn_chain *chain)
2022 /* In order to be certain of getting the registers we need,
2023 we must sort the reloads into order of increasing register class.
2024 Then our grabbing of reload registers will parallel the process
2025 that provided the reload registers. */
2026 for (i = 0; i < chain->n_reloads; i++)
2028 /* Show whether this reload already has a hard reg. */
2029 if (chain->rld[i].reg_rtx)
2031 int regno = REGNO (chain->rld[i].reg_rtx);
2032 chain->rld[i].regno = regno;
2034 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
2037 chain->rld[i].regno = -1;
2038 reload_order[i] = i;
2041 n_reloads = chain->n_reloads;
2042 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
2044 CLEAR_HARD_REG_SET (used_spill_regs_local);
2047 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
2049 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
2051 /* Compute the order of preference for hard registers to spill. */
2053 order_regs_for_reload (chain);
2055 for (i = 0; i < n_reloads; i++)
2057 int r = reload_order[i];
2059 /* Ignore reloads that got marked inoperative. */
2060 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
2061 && ! rld[r].optional
2062 && rld[r].regno == -1)
2063 if (! find_reg (chain, i))
2066 fprintf (dump_file, "reload failure for reload %d\n", r);
2067 spill_failure (chain->insn, rld[r].rclass);
2073 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
2074 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
2076 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2080 select_reload_regs (void)
2082 struct insn_chain *chain;
2084 /* Try to satisfy the needs for each insn. */
2085 for (chain = insns_need_reload; chain != 0;
2086 chain = chain->next_need_reload)
2087 find_reload_regs (chain);
2090 /* Delete all insns that were inserted by emit_caller_save_insns during
2093 delete_caller_save_insns (void)
2095 struct insn_chain *c = reload_insn_chain;
2099 while (c != 0 && c->is_caller_save_insn)
2101 struct insn_chain *next = c->next;
2104 if (c == reload_insn_chain)
2105 reload_insn_chain = next;
2109 next->prev = c->prev;
2111 c->prev->next = next;
2112 c->next = unused_insn_chains;
2113 unused_insn_chains = c;
2121 /* Handle the failure to find a register to spill.
2122 INSN should be one of the insns which needed this particular spill reg. */
2125 spill_failure (rtx insn, enum reg_class rclass)
2127 if (asm_noperands (PATTERN (insn)) >= 0)
2128 error_for_asm (insn, "can't find a register in class %qs while "
2129 "reloading %<asm%>",
2130 reg_class_names[rclass]);
2133 error ("unable to find a register to spill in class %qs",
2134 reg_class_names[rclass]);
2138 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2139 debug_reload_to_stream (dump_file);
2141 fatal_insn ("this is the insn:", insn);
2145 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2146 data that is dead in INSN. */
2149 delete_dead_insn (rtx insn)
2151 rtx prev = prev_real_insn (insn);
2154 /* If the previous insn sets a register that dies in our insn, delete it
2156 if (prev && GET_CODE (PATTERN (prev)) == SET
2157 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2158 && reg_mentioned_p (prev_dest, PATTERN (insn))
2159 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2160 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2161 delete_dead_insn (prev);
2163 SET_INSN_DELETED (insn);
2166 /* Modify the home of pseudo-reg I.
2167 The new home is present in reg_renumber[I].
2169 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2170 or it may be -1, meaning there is none or it is not relevant.
2171 This is used so that all pseudos spilled from a given hard reg
2172 can share one stack slot. */
2175 alter_reg (int i, int from_reg, bool dont_share_p)
2177 /* When outputting an inline function, this can happen
2178 for a reg that isn't actually used. */
2179 if (regno_reg_rtx[i] == 0)
2182 /* If the reg got changed to a MEM at rtl-generation time,
2184 if (!REG_P (regno_reg_rtx[i]))
2187 /* Modify the reg-rtx to contain the new hard reg
2188 number or else to contain its pseudo reg number. */
2189 SET_REGNO (regno_reg_rtx[i],
2190 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2192 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2193 allocate a stack slot for it. */
2195 if (reg_renumber[i] < 0
2196 && REG_N_REFS (i) > 0
2197 && reg_equiv_constant[i] == 0
2198 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
2199 && reg_equiv_memory_loc[i] == 0)
2202 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2203 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2204 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2205 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2206 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2209 if (ira_conflicts_p)
2211 /* Mark the spill for IRA. */
2212 SET_REGNO_REG_SET (&spilled_pseudos, i);
2214 x = ira_reuse_stack_slot (i, inherent_size, total_size);
2220 /* Each pseudo reg has an inherent size which comes from its own mode,
2221 and a total size which provides room for paradoxical subregs
2222 which refer to the pseudo reg in wider modes.
2224 We can use a slot already allocated if it provides both
2225 enough inherent space and enough total space.
2226 Otherwise, we allocate a new slot, making sure that it has no less
2227 inherent space, and no less total space, then the previous slot. */
2228 else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
2232 /* No known place to spill from => no slot to reuse. */
2233 x = assign_stack_local (mode, total_size,
2234 min_align > inherent_align
2235 || total_size > inherent_size ? -1 : 0);
2239 /* Cancel the big-endian correction done in assign_stack_local.
2240 Get the address of the beginning of the slot. This is so we
2241 can do a big-endian correction unconditionally below. */
2242 if (BYTES_BIG_ENDIAN)
2244 adjust = inherent_size - total_size;
2247 = adjust_address_nv (x, mode_for_size (total_size
2253 if (! dont_share_p && ira_conflicts_p)
2254 /* Inform IRA about allocation a new stack slot. */
2255 ira_mark_new_stack_slot (stack_slot, i, total_size);
2258 /* Reuse a stack slot if possible. */
2259 else if (spill_stack_slot[from_reg] != 0
2260 && spill_stack_slot_width[from_reg] >= total_size
2261 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2263 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2264 x = spill_stack_slot[from_reg];
2266 /* Allocate a bigger slot. */
2269 /* Compute maximum size needed, both for inherent size
2270 and for total size. */
2273 if (spill_stack_slot[from_reg])
2275 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2277 mode = GET_MODE (spill_stack_slot[from_reg]);
2278 if (spill_stack_slot_width[from_reg] > total_size)
2279 total_size = spill_stack_slot_width[from_reg];
2280 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2281 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2284 /* Make a slot with that size. */
2285 x = assign_stack_local (mode, total_size,
2286 min_align > inherent_align
2287 || total_size > inherent_size ? -1 : 0);
2290 /* Cancel the big-endian correction done in assign_stack_local.
2291 Get the address of the beginning of the slot. This is so we
2292 can do a big-endian correction unconditionally below. */
2293 if (BYTES_BIG_ENDIAN)
2295 adjust = GET_MODE_SIZE (mode) - total_size;
2298 = adjust_address_nv (x, mode_for_size (total_size
2304 spill_stack_slot[from_reg] = stack_slot;
2305 spill_stack_slot_width[from_reg] = total_size;
2308 /* On a big endian machine, the "address" of the slot
2309 is the address of the low part that fits its inherent mode. */
2310 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2311 adjust += (total_size - inherent_size);
2313 /* If we have any adjustment to make, or if the stack slot is the
2314 wrong mode, make a new stack slot. */
2315 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2317 /* Set all of the memory attributes as appropriate for a spill. */
2318 set_mem_attrs_for_spill (x);
2320 /* Save the stack slot for later. */
2321 reg_equiv_memory_loc[i] = x;
2325 /* Mark the slots in regs_ever_live for the hard regs used by
2326 pseudo-reg number REGNO, accessed in MODE. */
2329 mark_home_live_1 (int regno, enum machine_mode mode)
2333 i = reg_renumber[regno];
2336 lim = end_hard_regno (mode, i);
2338 df_set_regs_ever_live(i++, true);
2341 /* Mark the slots in regs_ever_live for the hard regs
2342 used by pseudo-reg number REGNO. */
2345 mark_home_live (int regno)
2347 if (reg_renumber[regno] >= 0)
2348 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2351 /* This function handles the tracking of elimination offsets around branches.
2353 X is a piece of RTL being scanned.
2355 INSN is the insn that it came from, if any.
2357 INITIAL_P is nonzero if we are to set the offset to be the initial
2358 offset and zero if we are setting the offset of the label to be the
2362 set_label_offsets (rtx x, rtx insn, int initial_p)
2364 enum rtx_code code = GET_CODE (x);
2367 struct elim_table *p;
2372 if (LABEL_REF_NONLOCAL_P (x))
2377 /* ... fall through ... */
2380 /* If we know nothing about this label, set the desired offsets. Note
2381 that this sets the offset at a label to be the offset before a label
2382 if we don't know anything about the label. This is not correct for
2383 the label after a BARRIER, but is the best guess we can make. If
2384 we guessed wrong, we will suppress an elimination that might have
2385 been possible had we been able to guess correctly. */
2387 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2389 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2390 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2391 = (initial_p ? reg_eliminate[i].initial_offset
2392 : reg_eliminate[i].offset);
2393 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2396 /* Otherwise, if this is the definition of a label and it is
2397 preceded by a BARRIER, set our offsets to the known offset of
2401 && (tem = prev_nonnote_insn (insn)) != 0
2403 set_offsets_for_label (insn);
2405 /* If neither of the above cases is true, compare each offset
2406 with those previously recorded and suppress any eliminations
2407 where the offsets disagree. */
2409 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2410 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2411 != (initial_p ? reg_eliminate[i].initial_offset
2412 : reg_eliminate[i].offset))
2413 reg_eliminate[i].can_eliminate = 0;
2418 set_label_offsets (PATTERN (insn), insn, initial_p);
2420 /* ... fall through ... */
2424 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2425 to indirectly and hence must have all eliminations at their
2427 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2428 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2429 set_label_offsets (XEXP (tem, 0), insn, 1);
2435 /* Each of the labels in the parallel or address vector must be
2436 at their initial offsets. We want the first field for PARALLEL
2437 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2439 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2440 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2445 /* We only care about setting PC. If the source is not RETURN,
2446 IF_THEN_ELSE, or a label, disable any eliminations not at
2447 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2448 isn't one of those possibilities. For branches to a label,
2449 call ourselves recursively.
2451 Note that this can disable elimination unnecessarily when we have
2452 a non-local goto since it will look like a non-constant jump to
2453 someplace in the current function. This isn't a significant
2454 problem since such jumps will normally be when all elimination
2455 pairs are back to their initial offsets. */
2457 if (SET_DEST (x) != pc_rtx)
2460 switch (GET_CODE (SET_SRC (x)))
2467 set_label_offsets (SET_SRC (x), insn, initial_p);
2471 tem = XEXP (SET_SRC (x), 1);
2472 if (GET_CODE (tem) == LABEL_REF)
2473 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2474 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2477 tem = XEXP (SET_SRC (x), 2);
2478 if (GET_CODE (tem) == LABEL_REF)
2479 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2480 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2488 /* If we reach here, all eliminations must be at their initial
2489 offset because we are doing a jump to a variable address. */
2490 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2491 if (p->offset != p->initial_offset)
2492 p->can_eliminate = 0;
2500 /* Scan X and replace any eliminable registers (such as fp) with a
2501 replacement (such as sp), plus an offset.
2503 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2504 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2505 MEM, we are allowed to replace a sum of a register and the constant zero
2506 with the register, which we cannot do outside a MEM. In addition, we need
2507 to record the fact that a register is referenced outside a MEM.
2509 If INSN is an insn, it is the insn containing X. If we replace a REG
2510 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2511 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2512 the REG is being modified.
2514 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2515 That's used when we eliminate in expressions stored in notes.
2516 This means, do not set ref_outside_mem even if the reference
2519 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2520 replacements done assuming all offsets are at their initial values. If
2521 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2522 encounter, return the actual location so that find_reloads will do
2523 the proper thing. */
2526 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2527 bool may_use_invariant)
2529 enum rtx_code code = GET_CODE (x);
2530 struct elim_table *ep;
2537 if (! current_function_decl)
2560 /* First handle the case where we encounter a bare register that
2561 is eliminable. Replace it with a PLUS. */
2562 if (regno < FIRST_PSEUDO_REGISTER)
2564 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2566 if (ep->from_rtx == x && ep->can_eliminate)
2567 return plus_constant (ep->to_rtx, ep->previous_offset);
2570 else if (reg_renumber && reg_renumber[regno] < 0
2571 && reg_equiv_invariant && reg_equiv_invariant[regno])
2573 if (may_use_invariant)
2574 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2575 mem_mode, insn, true);
2576 /* There exists at least one use of REGNO that cannot be
2577 eliminated. Prevent the defining insn from being deleted. */
2578 reg_equiv_init[regno] = NULL_RTX;
2579 alter_reg (regno, -1, true);
2583 /* You might think handling MINUS in a manner similar to PLUS is a
2584 good idea. It is not. It has been tried multiple times and every
2585 time the change has had to have been reverted.
2587 Other parts of reload know a PLUS is special (gen_reload for example)
2588 and require special code to handle code a reloaded PLUS operand.
2590 Also consider backends where the flags register is clobbered by a
2591 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2592 lea instruction comes to mind). If we try to reload a MINUS, we
2593 may kill the flags register that was holding a useful value.
2595 So, please before trying to handle MINUS, consider reload as a
2596 whole instead of this little section as well as the backend issues. */
2598 /* If this is the sum of an eliminable register and a constant, rework
2600 if (REG_P (XEXP (x, 0))
2601 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2602 && CONSTANT_P (XEXP (x, 1)))
2604 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2606 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2608 /* The only time we want to replace a PLUS with a REG (this
2609 occurs when the constant operand of the PLUS is the negative
2610 of the offset) is when we are inside a MEM. We won't want
2611 to do so at other times because that would change the
2612 structure of the insn in a way that reload can't handle.
2613 We special-case the commonest situation in
2614 eliminate_regs_in_insn, so just replace a PLUS with a
2615 PLUS here, unless inside a MEM. */
2616 if (mem_mode != 0 && CONST_INT_P (XEXP (x, 1))
2617 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2620 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2621 plus_constant (XEXP (x, 1),
2622 ep->previous_offset));
2625 /* If the register is not eliminable, we are done since the other
2626 operand is a constant. */
2630 /* If this is part of an address, we want to bring any constant to the
2631 outermost PLUS. We will do this by doing register replacement in
2632 our operands and seeing if a constant shows up in one of them.
2634 Note that there is no risk of modifying the structure of the insn,
2635 since we only get called for its operands, thus we are either
2636 modifying the address inside a MEM, or something like an address
2637 operand of a load-address insn. */
2640 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2641 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2643 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2645 /* If one side is a PLUS and the other side is a pseudo that
2646 didn't get a hard register but has a reg_equiv_constant,
2647 we must replace the constant here since it may no longer
2648 be in the position of any operand. */
2649 if (GET_CODE (new0) == PLUS && REG_P (new1)
2650 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2651 && reg_renumber[REGNO (new1)] < 0
2652 && reg_equiv_constant != 0
2653 && reg_equiv_constant[REGNO (new1)] != 0)
2654 new1 = reg_equiv_constant[REGNO (new1)];
2655 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2656 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2657 && reg_renumber[REGNO (new0)] < 0
2658 && reg_equiv_constant[REGNO (new0)] != 0)
2659 new0 = reg_equiv_constant[REGNO (new0)];
2661 new_rtx = form_sum (GET_MODE (x), new0, new1);
2663 /* As above, if we are not inside a MEM we do not want to
2664 turn a PLUS into something else. We might try to do so here
2665 for an addition of 0 if we aren't optimizing. */
2666 if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2667 return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2675 /* If this is the product of an eliminable register and a
2676 constant, apply the distribute law and move the constant out
2677 so that we have (plus (mult ..) ..). This is needed in order
2678 to keep load-address insns valid. This case is pathological.
2679 We ignore the possibility of overflow here. */
2680 if (REG_P (XEXP (x, 0))
2681 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2682 && CONST_INT_P (XEXP (x, 1)))
2683 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2685 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2688 /* Refs inside notes don't count for this purpose. */
2689 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2690 || GET_CODE (insn) == INSN_LIST)))
2691 ep->ref_outside_mem = 1;
2694 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2695 ep->previous_offset * INTVAL (XEXP (x, 1)));
2698 /* ... fall through ... */
2702 /* See comments before PLUS about handling MINUS. */
2704 case DIV: case UDIV:
2705 case MOD: case UMOD:
2706 case AND: case IOR: case XOR:
2707 case ROTATERT: case ROTATE:
2708 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2710 case GE: case GT: case GEU: case GTU:
2711 case LE: case LT: case LEU: case LTU:
2713 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2714 rtx new1 = XEXP (x, 1)
2715 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2717 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2718 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2723 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2726 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2727 if (new_rtx != XEXP (x, 0))
2729 /* If this is a REG_DEAD note, it is not valid anymore.
2730 Using the eliminated version could result in creating a
2731 REG_DEAD note for the stack or frame pointer. */
2732 if (REG_NOTE_KIND (x) == REG_DEAD)
2734 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2737 x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2741 /* ... fall through ... */
2744 /* Now do eliminations in the rest of the chain. If this was
2745 an EXPR_LIST, this might result in allocating more memory than is
2746 strictly needed, but it simplifies the code. */
2749 new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2750 if (new_rtx != XEXP (x, 1))
2752 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2760 /* We do not support elimination of a register that is modified.
2761 elimination_effects has already make sure that this does not
2767 /* We do not support elimination of a register that is modified.
2768 elimination_effects has already make sure that this does not
2769 happen. The only remaining case we need to consider here is
2770 that the increment value may be an eliminable register. */
2771 if (GET_CODE (XEXP (x, 1)) == PLUS
2772 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2774 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2777 if (new_rtx != XEXP (XEXP (x, 1), 1))
2778 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2779 gen_rtx_PLUS (GET_MODE (x),
2780 XEXP (x, 0), new_rtx));
2784 case STRICT_LOW_PART:
2786 case SIGN_EXTEND: case ZERO_EXTEND:
2787 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2788 case FLOAT: case FIX:
2789 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2798 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2799 if (new_rtx != XEXP (x, 0))
2800 return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2804 /* Similar to above processing, but preserve SUBREG_BYTE.
2805 Convert (subreg (mem)) to (mem) if not paradoxical.
2806 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2807 pseudo didn't get a hard reg, we must replace this with the
2808 eliminated version of the memory location because push_reload
2809 may do the replacement in certain circumstances. */
2810 if (REG_P (SUBREG_REG (x))
2811 && (GET_MODE_SIZE (GET_MODE (x))
2812 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2813 && reg_equiv_memory_loc != 0
2814 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2816 new_rtx = SUBREG_REG (x);
2819 new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2821 if (new_rtx != SUBREG_REG (x))
2823 int x_size = GET_MODE_SIZE (GET_MODE (x));
2824 int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2827 && ((x_size < new_size
2828 #ifdef WORD_REGISTER_OPERATIONS
2829 /* On these machines, combine can create rtl of the form
2830 (set (subreg:m1 (reg:m2 R) 0) ...)
2831 where m1 < m2, and expects something interesting to
2832 happen to the entire word. Moreover, it will use the
2833 (reg:m2 R) later, expecting all bits to be preserved.
2834 So if the number of words is the same, preserve the
2835 subreg so that push_reload can see it. */
2836 && ! ((x_size - 1) / UNITS_PER_WORD
2837 == (new_size -1 ) / UNITS_PER_WORD)
2840 || x_size == new_size)
2842 return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2844 return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2850 /* Our only special processing is to pass the mode of the MEM to our
2851 recursive call and copy the flags. While we are here, handle this
2852 case more efficiently. */
2854 replace_equiv_address_nv (x,
2855 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2859 /* Handle insn_list USE that a call to a pure function may generate. */
2860 new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false);
2861 if (new_rtx != XEXP (x, 0))
2862 return gen_rtx_USE (GET_MODE (x), new_rtx);
2874 /* Process each of our operands recursively. If any have changed, make a
2876 fmt = GET_RTX_FORMAT (code);
2877 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2881 new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2882 if (new_rtx != XEXP (x, i) && ! copied)
2884 x = shallow_copy_rtx (x);
2887 XEXP (x, i) = new_rtx;
2889 else if (*fmt == 'E')
2892 for (j = 0; j < XVECLEN (x, i); j++)
2894 new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2895 if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2897 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2901 x = shallow_copy_rtx (x);
2904 XVEC (x, i) = new_v;
2907 XVECEXP (x, i, j) = new_rtx;
2916 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2918 return eliminate_regs_1 (x, mem_mode, insn, false);
2921 /* Scan rtx X for modifications of elimination target registers. Update
2922 the table of eliminables to reflect the changed state. MEM_MODE is
2923 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2926 elimination_effects (rtx x, enum machine_mode mem_mode)
2928 enum rtx_code code = GET_CODE (x);
2929 struct elim_table *ep;
2954 /* First handle the case where we encounter a bare register that
2955 is eliminable. Replace it with a PLUS. */
2956 if (regno < FIRST_PSEUDO_REGISTER)
2958 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2960 if (ep->from_rtx == x && ep->can_eliminate)
2963 ep->ref_outside_mem = 1;
2968 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2969 && reg_equiv_constant[regno]
2970 && ! function_invariant_p (reg_equiv_constant[regno]))
2971 elimination_effects (reg_equiv_constant[regno], mem_mode);
2980 /* If we modify the source of an elimination rule, disable it. */
2981 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2982 if (ep->from_rtx == XEXP (x, 0))
2983 ep->can_eliminate = 0;
2985 /* If we modify the target of an elimination rule by adding a constant,
2986 update its offset. If we modify the target in any other way, we'll
2987 have to disable the rule as well. */
2988 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2989 if (ep->to_rtx == XEXP (x, 0))
2991 int size = GET_MODE_SIZE (mem_mode);
2993 /* If more bytes than MEM_MODE are pushed, account for them. */
2994 #ifdef PUSH_ROUNDING
2995 if (ep->to_rtx == stack_pointer_rtx)
2996 size = PUSH_ROUNDING (size);
2998 if (code == PRE_DEC || code == POST_DEC)
3000 else if (code == PRE_INC || code == POST_INC)
3002 else if (code == PRE_MODIFY || code == POST_MODIFY)
3004 if (GET_CODE (XEXP (x, 1)) == PLUS
3005 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
3006 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
3007 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
3009 ep->can_eliminate = 0;
3013 /* These two aren't unary operators. */
3014 if (code == POST_MODIFY || code == PRE_MODIFY)
3017 /* Fall through to generic unary operation case. */
3018 case STRICT_LOW_PART:
3020 case SIGN_EXTEND: case ZERO_EXTEND:
3021 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3022 case FLOAT: case FIX:
3023 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3032 elimination_effects (XEXP (x, 0), mem_mode);
3036 if (REG_P (SUBREG_REG (x))
3037 && (GET_MODE_SIZE (GET_MODE (x))
3038 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3039 && reg_equiv_memory_loc != 0
3040 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
3043 elimination_effects (SUBREG_REG (x), mem_mode);
3047 /* If using a register that is the source of an eliminate we still
3048 think can be performed, note it cannot be performed since we don't
3049 know how this register is used. */
3050 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3051 if (ep->from_rtx == XEXP (x, 0))
3052 ep->can_eliminate = 0;
3054 elimination_effects (XEXP (x, 0), mem_mode);
3058 /* If clobbering a register that is the replacement register for an
3059 elimination we still think can be performed, note that it cannot
3060 be performed. Otherwise, we need not be concerned about it. */
3061 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3062 if (ep->to_rtx == XEXP (x, 0))
3063 ep->can_eliminate = 0;
3065 elimination_effects (XEXP (x, 0), mem_mode);
3069 /* Check for setting a register that we know about. */
3070 if (REG_P (SET_DEST (x)))
3072 /* See if this is setting the replacement register for an
3075 If DEST is the hard frame pointer, we do nothing because we
3076 assume that all assignments to the frame pointer are for
3077 non-local gotos and are being done at a time when they are valid
3078 and do not disturb anything else. Some machines want to
3079 eliminate a fake argument pointer (or even a fake frame pointer)
3080 with either the real frame or the stack pointer. Assignments to
3081 the hard frame pointer must not prevent this elimination. */
3083 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3085 if (ep->to_rtx == SET_DEST (x)
3086 && SET_DEST (x) != hard_frame_pointer_rtx)
3088 /* If it is being incremented, adjust the offset. Otherwise,
3089 this elimination can't be done. */
3090 rtx src = SET_SRC (x);
3092 if (GET_CODE (src) == PLUS
3093 && XEXP (src, 0) == SET_DEST (x)
3094 && CONST_INT_P (XEXP (src, 1)))
3095 ep->offset -= INTVAL (XEXP (src, 1));
3097 ep->can_eliminate = 0;
3101 elimination_effects (SET_DEST (x), VOIDmode);
3102 elimination_effects (SET_SRC (x), VOIDmode);
3106 /* Our only special processing is to pass the mode of the MEM to our
3108 elimination_effects (XEXP (x, 0), GET_MODE (x));
3115 fmt = GET_RTX_FORMAT (code);
3116 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3119 elimination_effects (XEXP (x, i), mem_mode);
3120 else if (*fmt == 'E')
3121 for (j = 0; j < XVECLEN (x, i); j++)
3122 elimination_effects (XVECEXP (x, i, j), mem_mode);
3126 /* Descend through rtx X and verify that no references to eliminable registers
3127 remain. If any do remain, mark the involved register as not
3131 check_eliminable_occurrences (rtx x)
3140 code = GET_CODE (x);
3142 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3144 struct elim_table *ep;
3146 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3147 if (ep->from_rtx == x)
3148 ep->can_eliminate = 0;
3152 fmt = GET_RTX_FORMAT (code);
3153 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3156 check_eliminable_occurrences (XEXP (x, i));
3157 else if (*fmt == 'E')
3160 for (j = 0; j < XVECLEN (x, i); j++)
3161 check_eliminable_occurrences (XVECEXP (x, i, j));
3166 /* Scan INSN and eliminate all eliminable registers in it.
3168 If REPLACE is nonzero, do the replacement destructively. Also
3169 delete the insn as dead it if it is setting an eliminable register.
3171 If REPLACE is zero, do all our allocations in reload_obstack.
3173 If no eliminations were done and this insn doesn't require any elimination
3174 processing (these are not identical conditions: it might be updating sp,
3175 but not referencing fp; this needs to be seen during reload_as_needed so
3176 that the offset between fp and sp can be taken into consideration), zero
3177 is returned. Otherwise, 1 is returned. */
3180 eliminate_regs_in_insn (rtx insn, int replace)
3182 int icode = recog_memoized (insn);
3183 rtx old_body = PATTERN (insn);
3184 int insn_is_asm = asm_noperands (old_body) >= 0;
3185 rtx old_set = single_set (insn);
3189 rtx substed_operand[MAX_RECOG_OPERANDS];
3190 rtx orig_operand[MAX_RECOG_OPERANDS];
3191 struct elim_table *ep;
3192 rtx plus_src, plus_cst_src;
3194 if (! insn_is_asm && icode < 0)
3196 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3197 || GET_CODE (PATTERN (insn)) == CLOBBER
3198 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3199 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3200 || GET_CODE (PATTERN (insn)) == ASM_INPUT
3201 || DEBUG_INSN_P (insn));
3205 if (old_set != 0 && REG_P (SET_DEST (old_set))
3206 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3208 /* Check for setting an eliminable register. */
3209 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3210 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3212 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3213 /* If this is setting the frame pointer register to the
3214 hardware frame pointer register and this is an elimination
3215 that will be done (tested above), this insn is really
3216 adjusting the frame pointer downward to compensate for
3217 the adjustment done before a nonlocal goto. */
3218 if (ep->from == FRAME_POINTER_REGNUM
3219 && ep->to == HARD_FRAME_POINTER_REGNUM)
3221 rtx base = SET_SRC (old_set);
3222 rtx base_insn = insn;
3223 HOST_WIDE_INT offset = 0;
3225 while (base != ep->to_rtx)
3227 rtx prev_insn, prev_set;
3229 if (GET_CODE (base) == PLUS
3230 && CONST_INT_P (XEXP (base, 1)))
3232 offset += INTVAL (XEXP (base, 1));
3233 base = XEXP (base, 0);
3235 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3236 && (prev_set = single_set (prev_insn)) != 0
3237 && rtx_equal_p (SET_DEST (prev_set), base))
3239 base = SET_SRC (prev_set);
3240 base_insn = prev_insn;
3246 if (base == ep->to_rtx)
3249 = plus_constant (ep->to_rtx, offset - ep->offset);
3251 new_body = old_body;
3254 new_body = copy_insn (old_body);
3255 if (REG_NOTES (insn))
3256 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3258 PATTERN (insn) = new_body;
3259 old_set = single_set (insn);
3261 /* First see if this insn remains valid when we
3262 make the change. If not, keep the INSN_CODE
3263 the same and let reload fit it up. */
3264 validate_change (insn, &SET_SRC (old_set), src, 1);
3265 validate_change (insn, &SET_DEST (old_set),
3267 if (! apply_change_group ())
3269 SET_SRC (old_set) = src;
3270 SET_DEST (old_set) = ep->to_rtx;
3279 /* In this case this insn isn't serving a useful purpose. We
3280 will delete it in reload_as_needed once we know that this
3281 elimination is, in fact, being done.
3283 If REPLACE isn't set, we can't delete this insn, but needn't
3284 process it since it won't be used unless something changes. */
3287 delete_dead_insn (insn);
3295 /* We allow one special case which happens to work on all machines we
3296 currently support: a single set with the source or a REG_EQUAL
3297 note being a PLUS of an eliminable register and a constant. */
3298 plus_src = plus_cst_src = 0;
3299 if (old_set && REG_P (SET_DEST (old_set)))
3301 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3302 plus_src = SET_SRC (old_set);
3303 /* First see if the source is of the form (plus (...) CST). */
3305 && CONST_INT_P (XEXP (plus_src, 1)))
3306 plus_cst_src = plus_src;
3307 else if (REG_P (SET_SRC (old_set))
3310 /* Otherwise, see if we have a REG_EQUAL note of the form
3311 (plus (...) CST). */
3313 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3315 if ((REG_NOTE_KIND (links) == REG_EQUAL
3316 || REG_NOTE_KIND (links) == REG_EQUIV)
3317 && GET_CODE (XEXP (links, 0)) == PLUS
3318 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3320 plus_cst_src = XEXP (links, 0);
3326 /* Check that the first operand of the PLUS is a hard reg or
3327 the lowpart subreg of one. */
3330 rtx reg = XEXP (plus_cst_src, 0);
3331 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3332 reg = SUBREG_REG (reg);
3334 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3340 rtx reg = XEXP (plus_cst_src, 0);
3341 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3343 if (GET_CODE (reg) == SUBREG)
3344 reg = SUBREG_REG (reg);
3346 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3347 if (ep->from_rtx == reg && ep->can_eliminate)
3349 rtx to_rtx = ep->to_rtx;
3350 offset += ep->offset;
3351 offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
3353 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3354 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3356 /* If we have a nonzero offset, and the source is already
3357 a simple REG, the following transformation would
3358 increase the cost of the insn by replacing a simple REG
3359 with (plus (reg sp) CST). So try only when we already
3360 had a PLUS before. */
3361 if (offset == 0 || plus_src)
3363 rtx new_src = plus_constant (to_rtx, offset);
3365 new_body = old_body;
3368 new_body = copy_insn (old_body);
3369 if (REG_NOTES (insn))
3370 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3372 PATTERN (insn) = new_body;
3373 old_set = single_set (insn);
3375 /* First see if this insn remains valid when we make the
3376 change. If not, try to replace the whole pattern with
3377 a simple set (this may help if the original insn was a
3378 PARALLEL that was only recognized as single_set due to
3379 REG_UNUSED notes). If this isn't valid either, keep
3380 the INSN_CODE the same and let reload fix it up. */
3381 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3383 rtx new_pat = gen_rtx_SET (VOIDmode,
3384 SET_DEST (old_set), new_src);
3386 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3387 SET_SRC (old_set) = new_src;
3394 /* This can't have an effect on elimination offsets, so skip right
3400 /* Determine the effects of this insn on elimination offsets. */
3401 elimination_effects (old_body, VOIDmode);
3403 /* Eliminate all eliminable registers occurring in operands that
3404 can be handled by reload. */
3405 extract_insn (insn);
3406 for (i = 0; i < recog_data.n_operands; i++)
3408 orig_operand[i] = recog_data.operand[i];
3409 substed_operand[i] = recog_data.operand[i];
3411 /* For an asm statement, every operand is eliminable. */
3412 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3414 bool is_set_src, in_plus;
3416 /* Check for setting a register that we know about. */
3417 if (recog_data.operand_type[i] != OP_IN
3418 && REG_P (orig_operand[i]))
3420 /* If we are assigning to a register that can be eliminated, it
3421 must be as part of a PARALLEL, since the code above handles
3422 single SETs. We must indicate that we can no longer
3423 eliminate this reg. */
3424 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3426 if (ep->from_rtx == orig_operand[i])
3427 ep->can_eliminate = 0;
3430 /* Companion to the above plus substitution, we can allow
3431 invariants as the source of a plain move. */
3433 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3437 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3438 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3442 = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3443 replace ? insn : NULL_RTX,
3444 is_set_src || in_plus);
3445 if (substed_operand[i] != orig_operand[i])
3447 /* Terminate the search in check_eliminable_occurrences at
3449 *recog_data.operand_loc[i] = 0;
3451 /* If an output operand changed from a REG to a MEM and INSN is an
3452 insn, write a CLOBBER insn. */
3453 if (recog_data.operand_type[i] != OP_IN
3454 && REG_P (orig_operand[i])
3455 && MEM_P (substed_operand[i])
3457 emit_insn_after (gen_clobber (orig_operand[i]), insn);
3461 for (i = 0; i < recog_data.n_dups; i++)
3462 *recog_data.dup_loc[i]
3463 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3465 /* If any eliminable remain, they aren't eliminable anymore. */
3466 check_eliminable_occurrences (old_body);
3468 /* Substitute the operands; the new values are in the substed_operand
3470 for (i = 0; i < recog_data.n_operands; i++)
3471 *recog_data.operand_loc[i] = substed_operand[i];
3472 for (i = 0; i < recog_data.n_dups; i++)
3473 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3475 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3476 re-recognize the insn. We do this in case we had a simple addition
3477 but now can do this as a load-address. This saves an insn in this
3479 If re-recognition fails, the old insn code number will still be used,
3480 and some register operands may have changed into PLUS expressions.
3481 These will be handled by find_reloads by loading them into a register
3486 /* If we aren't replacing things permanently and we changed something,
3487 make another copy to ensure that all the RTL is new. Otherwise
3488 things can go wrong if find_reload swaps commutative operands
3489 and one is inside RTL that has been copied while the other is not. */
3490 new_body = old_body;
3493 new_body = copy_insn (old_body);
3494 if (REG_NOTES (insn))
3495 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3497 PATTERN (insn) = new_body;
3499 /* If we had a move insn but now we don't, rerecognize it. This will
3500 cause spurious re-recognition if the old move had a PARALLEL since
3501 the new one still will, but we can't call single_set without
3502 having put NEW_BODY into the insn and the re-recognition won't
3503 hurt in this rare case. */
3504 /* ??? Why this huge if statement - why don't we just rerecognize the
3508 && ((REG_P (SET_SRC (old_set))
3509 && (GET_CODE (new_body) != SET
3510 || !REG_P (SET_SRC (new_body))))
3511 /* If this was a load from or store to memory, compare
3512 the MEM in recog_data.operand to the one in the insn.
3513 If they are not equal, then rerecognize the insn. */
3515 && ((MEM_P (SET_SRC (old_set))
3516 && SET_SRC (old_set) != recog_data.operand[1])
3517 || (MEM_P (SET_DEST (old_set))
3518 && SET_DEST (old_set) != recog_data.operand[0])))
3519 /* If this was an add insn before, rerecognize. */
3520 || GET_CODE (SET_SRC (old_set)) == PLUS))
3522 int new_icode = recog (PATTERN (insn), insn, 0);
3524 INSN_CODE (insn) = new_icode;
3528 /* Restore the old body. If there were any changes to it, we made a copy
3529 of it while the changes were still in place, so we'll correctly return
3530 a modified insn below. */
3533 /* Restore the old body. */
3534 for (i = 0; i < recog_data.n_operands; i++)
3535 *recog_data.operand_loc[i] = orig_operand[i];
3536 for (i = 0; i < recog_data.n_dups; i++)
3537 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3540 /* Update all elimination pairs to reflect the status after the current
3541 insn. The changes we make were determined by the earlier call to
3542 elimination_effects.
3544 We also detect cases where register elimination cannot be done,
3545 namely, if a register would be both changed and referenced outside a MEM
3546 in the resulting insn since such an insn is often undefined and, even if
3547 not, we cannot know what meaning will be given to it. Note that it is
3548 valid to have a register used in an address in an insn that changes it
3549 (presumably with a pre- or post-increment or decrement).
3551 If anything changes, return nonzero. */
3553 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3555 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3556 ep->can_eliminate = 0;
3558 ep->ref_outside_mem = 0;
3560 if (ep->previous_offset != ep->offset)
3565 /* If we changed something, perform elimination in REG_NOTES. This is
3566 needed even when REPLACE is zero because a REG_DEAD note might refer
3567 to a register that we eliminate and could cause a different number
3568 of spill registers to be needed in the final reload pass than in
3570 if (val && REG_NOTES (insn) != 0)
3572 = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true);
3577 /* Loop through all elimination pairs.
3578 Recalculate the number not at initial offset.
3580 Compute the maximum offset (minimum offset if the stack does not
3581 grow downward) for each elimination pair. */
3584 update_eliminable_offsets (void)
3586 struct elim_table *ep;
3588 num_not_at_initial_offset = 0;
3589 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3591 ep->previous_offset = ep->offset;
3592 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3593 num_not_at_initial_offset++;
3597 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3598 replacement we currently believe is valid, mark it as not eliminable if X
3599 modifies DEST in any way other than by adding a constant integer to it.
3601 If DEST is the frame pointer, we do nothing because we assume that
3602 all assignments to the hard frame pointer are nonlocal gotos and are being
3603 done at a time when they are valid and do not disturb anything else.
3604 Some machines want to eliminate a fake argument pointer with either the
3605 frame or stack pointer. Assignments to the hard frame pointer must not
3606 prevent this elimination.
3608 Called via note_stores from reload before starting its passes to scan
3609 the insns of the function. */
3612 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3616 /* A SUBREG of a hard register here is just changing its mode. We should
3617 not see a SUBREG of an eliminable hard register, but check just in
3619 if (GET_CODE (dest) == SUBREG)
3620 dest = SUBREG_REG (dest);
3622 if (dest == hard_frame_pointer_rtx)
3625 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3626 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3627 && (GET_CODE (x) != SET
3628 || GET_CODE (SET_SRC (x)) != PLUS
3629 || XEXP (SET_SRC (x), 0) != dest
3630 || !CONST_INT_P (XEXP (SET_SRC (x), 1))))
3632 reg_eliminate[i].can_eliminate_previous
3633 = reg_eliminate[i].can_eliminate = 0;
3638 /* Verify that the initial elimination offsets did not change since the
3639 last call to set_initial_elim_offsets. This is used to catch cases
3640 where something illegal happened during reload_as_needed that could
3641 cause incorrect code to be generated if we did not check for it. */
3644 verify_initial_elim_offsets (void)
3648 if (!num_eliminable)
3651 #ifdef ELIMINABLE_REGS
3653 struct elim_table *ep;
3655 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3657 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3658 if (t != ep->initial_offset)
3663 INITIAL_FRAME_POINTER_OFFSET (t);
3664 if (t != reg_eliminate[0].initial_offset)
3671 /* Reset all offsets on eliminable registers to their initial values. */
3674 set_initial_elim_offsets (void)
3676 struct elim_table *ep = reg_eliminate;
3678 #ifdef ELIMINABLE_REGS
3679 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3681 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3682 ep->previous_offset = ep->offset = ep->initial_offset;
3685 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3686 ep->previous_offset = ep->offset = ep->initial_offset;
3689 num_not_at_initial_offset = 0;
3692 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3695 set_initial_eh_label_offset (rtx label)
3697 set_label_offsets (label, NULL_RTX, 1);
3700 /* Initialize the known label offsets.
3701 Set a known offset for each forced label to be at the initial offset
3702 of each elimination. We do this because we assume that all
3703 computed jumps occur from a location where each elimination is
3704 at its initial offset.
3705 For all other labels, show that we don't know the offsets. */
3708 set_initial_label_offsets (void)
3711 memset (offsets_known_at, 0, num_labels);
3713 for (x = forced_labels; x; x = XEXP (x, 1))
3715 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3717 for_each_eh_label (set_initial_eh_label_offset);
3720 /* Set all elimination offsets to the known values for the code label given
3724 set_offsets_for_label (rtx insn)
3727 int label_nr = CODE_LABEL_NUMBER (insn);
3728 struct elim_table *ep;
3730 num_not_at_initial_offset = 0;
3731 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3733 ep->offset = ep->previous_offset
3734 = offsets_at[label_nr - first_label_num][i];
3735 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3736 num_not_at_initial_offset++;
3740 /* See if anything that happened changes which eliminations are valid.
3741 For example, on the SPARC, whether or not the frame pointer can
3742 be eliminated can depend on what registers have been used. We need
3743 not check some conditions again (such as flag_omit_frame_pointer)
3744 since they can't have changed. */
3747 update_eliminables (HARD_REG_SET *pset)
3749 int previous_frame_pointer_needed = frame_pointer_needed;
3750 struct elim_table *ep;
3752 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3753 if ((ep->from == HARD_FRAME_POINTER_REGNUM
3754 && targetm.frame_pointer_required ())
3755 #ifdef ELIMINABLE_REGS
3756 || ! targetm.can_eliminate (ep->from, ep->to)
3759 ep->can_eliminate = 0;
3761 /* Look for the case where we have discovered that we can't replace
3762 register A with register B and that means that we will now be
3763 trying to replace register A with register C. This means we can
3764 no longer replace register C with register B and we need to disable
3765 such an elimination, if it exists. This occurs often with A == ap,
3766 B == sp, and C == fp. */
3768 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3770 struct elim_table *op;
3773 if (! ep->can_eliminate && ep->can_eliminate_previous)
3775 /* Find the current elimination for ep->from, if there is a
3777 for (op = reg_eliminate;
3778 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3779 if (op->from == ep->from && op->can_eliminate)
3785 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3787 for (op = reg_eliminate;
3788 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3789 if (op->from == new_to && op->to == ep->to)
3790 op->can_eliminate = 0;
3794 /* See if any registers that we thought we could eliminate the previous
3795 time are no longer eliminable. If so, something has changed and we
3796 must spill the register. Also, recompute the number of eliminable
3797 registers and see if the frame pointer is needed; it is if there is
3798 no elimination of the frame pointer that we can perform. */
3800 frame_pointer_needed = 1;
3801 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3803 if (ep->can_eliminate
3804 && ep->from == FRAME_POINTER_REGNUM
3805 && ep->to != HARD_FRAME_POINTER_REGNUM
3806 && (! SUPPORTS_STACK_ALIGNMENT
3807 || ! crtl->stack_realign_needed))
3808 frame_pointer_needed = 0;
3810 if (! ep->can_eliminate && ep->can_eliminate_previous)
3812 ep->can_eliminate_previous = 0;
3813 SET_HARD_REG_BIT (*pset, ep->from);
3818 /* If we didn't need a frame pointer last time, but we do now, spill
3819 the hard frame pointer. */
3820 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3821 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3824 /* Return true if X is used as the target register of an elimination. */
3827 elimination_target_reg_p (rtx x)
3829 struct elim_table *ep;
3831 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3832 if (ep->to_rtx == x && ep->can_eliminate)
3838 /* Initialize the table of registers to eliminate.
3839 Pre-condition: global flag frame_pointer_needed has been set before
3840 calling this function. */
3843 init_elim_table (void)
3845 struct elim_table *ep;
3846 #ifdef ELIMINABLE_REGS
3847 const struct elim_table_1 *ep1;
3851 reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
3855 #ifdef ELIMINABLE_REGS
3856 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3857 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3859 ep->from = ep1->from;
3861 ep->can_eliminate = ep->can_eliminate_previous
3862 = (targetm.can_eliminate (ep->from, ep->to)
3863 && ! (ep->to == STACK_POINTER_REGNUM
3864 && frame_pointer_needed
3865 && (! SUPPORTS_STACK_ALIGNMENT
3866 || ! stack_realign_fp)));
3869 reg_eliminate[0].from = reg_eliminate_1[0].from;
3870 reg_eliminate[0].to = reg_eliminate_1[0].to;
3871 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3872 = ! frame_pointer_needed;
3875 /* Count the number of eliminable registers and build the FROM and TO
3876 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3877 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3878 We depend on this. */
3879 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3881 num_eliminable += ep->can_eliminate;
3882 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3883 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3887 /* Kick all pseudos out of hard register REGNO.
3889 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3890 because we found we can't eliminate some register. In the case, no pseudos
3891 are allowed to be in the register, even if they are only in a block that
3892 doesn't require spill registers, unlike the case when we are spilling this
3893 hard reg to produce another spill register.
3895 Return nonzero if any pseudos needed to be kicked out. */
3898 spill_hard_reg (unsigned int regno, int cant_eliminate)
3904 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3905 df_set_regs_ever_live (regno, true);
3908 /* Spill every pseudo reg that was allocated to this reg
3909 or to something that overlaps this reg. */
3911 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3912 if (reg_renumber[i] >= 0
3913 && (unsigned int) reg_renumber[i] <= regno
3914 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
3915 SET_REGNO_REG_SET (&spilled_pseudos, i);
3918 /* After find_reload_regs has been run for all insn that need reloads,
3919 and/or spill_hard_regs was called, this function is used to actually
3920 spill pseudo registers and try to reallocate them. It also sets up the
3921 spill_regs array for use by choose_reload_regs. */
3924 finish_spills (int global)
3926 struct insn_chain *chain;
3927 int something_changed = 0;
3929 reg_set_iterator rsi;
3931 /* Build the spill_regs array for the function. */
3932 /* If there are some registers still to eliminate and one of the spill regs
3933 wasn't ever used before, additional stack space may have to be
3934 allocated to store this register. Thus, we may have changed the offset
3935 between the stack and frame pointers, so mark that something has changed.
3937 One might think that we need only set VAL to 1 if this is a call-used
3938 register. However, the set of registers that must be saved by the
3939 prologue is not identical to the call-used set. For example, the
3940 register used by the call insn for the return PC is a call-used register,
3941 but must be saved by the prologue. */
3944 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3945 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3947 spill_reg_order[i] = n_spills;
3948 spill_regs[n_spills++] = i;
3949 if (num_eliminable && ! df_regs_ever_live_p (i))
3950 something_changed = 1;
3951 df_set_regs_ever_live (i, true);
3954 spill_reg_order[i] = -1;
3956 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3957 if (! ira_conflicts_p || reg_renumber[i] >= 0)
3959 /* Record the current hard register the pseudo is allocated to
3960 in pseudo_previous_regs so we avoid reallocating it to the
3961 same hard reg in a later pass. */
3962 gcc_assert (reg_renumber[i] >= 0);
3964 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3965 /* Mark it as no longer having a hard register home. */
3966 reg_renumber[i] = -1;
3967 if (ira_conflicts_p)
3968 /* Inform IRA about the change. */
3969 ira_mark_allocation_change (i);
3970 /* We will need to scan everything again. */
3971 something_changed = 1;
3974 /* Retry global register allocation if possible. */
3975 if (global && ira_conflicts_p)
3979 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3980 /* For every insn that needs reloads, set the registers used as spill
3981 regs in pseudo_forbidden_regs for every pseudo live across the
3983 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3985 EXECUTE_IF_SET_IN_REG_SET
3986 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3988 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3989 chain->used_spill_regs);
3991 EXECUTE_IF_SET_IN_REG_SET
3992 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3994 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3995 chain->used_spill_regs);
3999 /* Retry allocating the pseudos spilled in IRA and the
4000 reload. For each reg, merge the various reg sets that
4001 indicate which hard regs can't be used, and call
4002 ira_reassign_pseudos. */
4003 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
4004 if (reg_old_renumber[i] != reg_renumber[i])
4006 if (reg_renumber[i] < 0)
4007 temp_pseudo_reg_arr[n++] = i;
4009 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4011 if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
4012 bad_spill_regs_global,
4013 pseudo_forbidden_regs, pseudo_previous_regs,
4015 something_changed = 1;
4017 /* Fix up the register information in the insn chain.
4018 This involves deleting those of the spilled pseudos which did not get
4019 a new hard register home from the live_{before,after} sets. */
4020 for (chain = reload_insn_chain; chain; chain = chain->next)
4022 HARD_REG_SET used_by_pseudos;
4023 HARD_REG_SET used_by_pseudos2;
4025 if (! ira_conflicts_p)
4027 /* Don't do it for IRA because IRA and the reload still can
4028 assign hard registers to the spilled pseudos on next
4029 reload iterations. */
4030 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
4031 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
4033 /* Mark any unallocated hard regs as available for spills. That
4034 makes inheritance work somewhat better. */
4035 if (chain->need_reload)
4037 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
4038 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
4039 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
4041 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
4042 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
4043 /* Value of chain->used_spill_regs from previous iteration
4044 may be not included in the value calculated here because
4045 of possible removing caller-saves insns (see function
4046 delete_caller_save_insns. */
4047 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
4048 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4052 CLEAR_REG_SET (&changed_allocation_pseudos);
4053 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4054 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4056 int regno = reg_renumber[i];
4057 if (reg_old_renumber[i] == regno)
4060 SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4062 alter_reg (i, reg_old_renumber[i], false);
4063 reg_old_renumber[i] = regno;
4067 fprintf (dump_file, " Register %d now on stack.\n\n", i);
4069 fprintf (dump_file, " Register %d now in %d.\n\n",
4070 i, reg_renumber[i]);
4074 return something_changed;
4077 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4080 scan_paradoxical_subregs (rtx x)
4084 enum rtx_code code = GET_CODE (x);
4095 case CONST_VECTOR: /* shouldn't happen, but just in case. */
4103 if (REG_P (SUBREG_REG (x))
4104 && (GET_MODE_SIZE (GET_MODE (x))
4105 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
4107 reg_max_ref_width[REGNO (SUBREG_REG (x))]
4108 = GET_MODE_SIZE (GET_MODE (x));
4109 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
4117 fmt = GET_RTX_FORMAT (code);
4118 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4121 scan_paradoxical_subregs (XEXP (x, i));
4122 else if (fmt[i] == 'E')
4125 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4126 scan_paradoxical_subregs (XVECEXP (x, i, j));
4131 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4132 examine all of the reload insns between PREV and NEXT exclusive, and
4133 annotate all that may trap. */
4136 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
4138 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4141 if (!insn_could_throw_p (insn))
4142 remove_note (insn, note);
4143 copy_reg_eh_region_note_forward (note, NEXT_INSN (prev), next);
4146 /* Reload pseudo-registers into hard regs around each insn as needed.
4147 Additional register load insns are output before the insn that needs it
4148 and perhaps store insns after insns that modify the reloaded pseudo reg.
4150 reg_last_reload_reg and reg_reloaded_contents keep track of
4151 which registers are already available in reload registers.
4152 We update these for the reloads that we perform,
4153 as the insns are scanned. */
4156 reload_as_needed (int live_known)
4158 struct insn_chain *chain;
4159 #if defined (AUTO_INC_DEC)
4164 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4165 memset (spill_reg_store, 0, sizeof spill_reg_store);
4166 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4167 INIT_REG_SET (®_has_output_reload);
4168 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4169 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4171 set_initial_elim_offsets ();
4173 for (chain = reload_insn_chain; chain; chain = chain->next)
4176 rtx insn = chain->insn;
4177 rtx old_next = NEXT_INSN (insn);
4179 rtx old_prev = PREV_INSN (insn);
4182 /* If we pass a label, copy the offsets from the label information
4183 into the current offsets of each elimination. */
4185 set_offsets_for_label (insn);
4187 else if (INSN_P (insn))
4189 regset_head regs_to_forget;
4190 INIT_REG_SET (®s_to_forget);
4191 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4193 /* If this is a USE and CLOBBER of a MEM, ensure that any
4194 references to eliminable registers have been removed. */
4196 if ((GET_CODE (PATTERN (insn)) == USE
4197 || GET_CODE (PATTERN (insn)) == CLOBBER)
4198 && MEM_P (XEXP (PATTERN (insn), 0)))
4199 XEXP (XEXP (PATTERN (insn), 0), 0)
4200 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4201 GET_MODE (XEXP (PATTERN (insn), 0)),
4204 /* If we need to do register elimination processing, do so.
4205 This might delete the insn, in which case we are done. */
4206 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4208 eliminate_regs_in_insn (insn, 1);
4211 update_eliminable_offsets ();
4212 CLEAR_REG_SET (®s_to_forget);
4217 /* If need_elim is nonzero but need_reload is zero, one might think
4218 that we could simply set n_reloads to 0. However, find_reloads
4219 could have done some manipulation of the insn (such as swapping
4220 commutative operands), and these manipulations are lost during
4221 the first pass for every insn that needs register elimination.
4222 So the actions of find_reloads must be redone here. */
4224 if (! chain->need_elim && ! chain->need_reload
4225 && ! chain->need_operand_change)
4227 /* First find the pseudo regs that must be reloaded for this insn.
4228 This info is returned in the tables reload_... (see reload.h).
4229 Also modify the body of INSN by substituting RELOAD
4230 rtx's for those pseudo regs. */
4233 CLEAR_REG_SET (®_has_output_reload);
4234 CLEAR_HARD_REG_SET (reg_is_output_reload);
4236 find_reloads (insn, 1, spill_indirect_levels, live_known,
4242 rtx next = NEXT_INSN (insn);
4245 prev = PREV_INSN (insn);
4247 /* Now compute which reload regs to reload them into. Perhaps
4248 reusing reload regs from previous insns, or else output
4249 load insns to reload them. Maybe output store insns too.
4250 Record the choices of reload reg in reload_reg_rtx. */
4251 choose_reload_regs (chain);
4253 /* Merge any reloads that we didn't combine for fear of
4254 increasing the number of spill registers needed but now
4255 discover can be safely merged. */
4256 if (SMALL_REGISTER_CLASSES)
4257 merge_assigned_reloads (insn);
4259 /* Generate the insns to reload operands into or out of
4260 their reload regs. */
4261 emit_reload_insns (chain);
4263 /* Substitute the chosen reload regs from reload_reg_rtx
4264 into the insn's body (or perhaps into the bodies of other
4265 load and store insn that we just made for reloading
4266 and that we moved the structure into). */
4267 subst_reloads (insn);
4269 /* Adjust the exception region notes for loads and stores. */
4270 if (flag_non_call_exceptions && !CALL_P (insn))
4271 fixup_eh_region_note (insn, prev, next);
4273 /* If this was an ASM, make sure that all the reload insns
4274 we have generated are valid. If not, give an error
4276 if (asm_noperands (PATTERN (insn)) >= 0)
4277 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4278 if (p != insn && INSN_P (p)
4279 && GET_CODE (PATTERN (p)) != USE
4280 && (recog_memoized (p) < 0
4281 || (extract_insn (p), ! constrain_operands (1))))
4283 error_for_asm (insn,
4284 "%<asm%> operand requires "
4285 "impossible reload");
4290 if (num_eliminable && chain->need_elim)
4291 update_eliminable_offsets ();
4293 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4294 is no longer validly lying around to save a future reload.
4295 Note that this does not detect pseudos that were reloaded
4296 for this insn in order to be stored in
4297 (obeying register constraints). That is correct; such reload
4298 registers ARE still valid. */
4299 forget_marked_reloads (®s_to_forget);
4300 CLEAR_REG_SET (®s_to_forget);
4302 /* There may have been CLOBBER insns placed after INSN. So scan
4303 between INSN and NEXT and use them to forget old reloads. */
4304 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4305 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4306 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4309 /* Likewise for regs altered by auto-increment in this insn.
4310 REG_INC notes have been changed by reloading:
4311 find_reloads_address_1 records substitutions for them,
4312 which have been performed by subst_reloads above. */
4313 for (i = n_reloads - 1; i >= 0; i--)
4315 rtx in_reg = rld[i].in_reg;
4318 enum rtx_code code = GET_CODE (in_reg);
4319 /* PRE_INC / PRE_DEC will have the reload register ending up
4320 with the same value as the stack slot, but that doesn't
4321 hold true for POST_INC / POST_DEC. Either we have to
4322 convert the memory access to a true POST_INC / POST_DEC,
4323 or we can't use the reload register for inheritance. */
4324 if ((code == POST_INC || code == POST_DEC)
4325 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4326 REGNO (rld[i].reg_rtx))
4327 /* Make sure it is the inc/dec pseudo, and not
4328 some other (e.g. output operand) pseudo. */
4329 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4330 == REGNO (XEXP (in_reg, 0))))
4333 rtx reload_reg = rld[i].reg_rtx;
4334 enum machine_mode mode = GET_MODE (reload_reg);
4338 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4340 /* We really want to ignore REG_INC notes here, so
4341 use PATTERN (p) as argument to reg_set_p . */
4342 if (reg_set_p (reload_reg, PATTERN (p)))
4344 n = count_occurrences (PATTERN (p), reload_reg, 0);
4350 = gen_rtx_fmt_e (code, mode, reload_reg);
4352 validate_replace_rtx_group (reload_reg,
4354 n = verify_changes (0);
4356 /* We must also verify that the constraints
4357 are met after the replacement. Make sure
4358 extract_insn is only called for an insn
4359 where the replacements were found to be
4364 n = constrain_operands (1);
4367 /* If the constraints were not met, then
4368 undo the replacement, else confirm it. */
4372 confirm_change_group ();
4378 add_reg_note (p, REG_INC, reload_reg);
4379 /* Mark this as having an output reload so that the
4380 REG_INC processing code below won't invalidate
4381 the reload for inheritance. */
4382 SET_HARD_REG_BIT (reg_is_output_reload,
4383 REGNO (reload_reg));
4384 SET_REGNO_REG_SET (®_has_output_reload,
4385 REGNO (XEXP (in_reg, 0)));
4388 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4391 else if ((code == PRE_INC || code == PRE_DEC)
4392 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4393 REGNO (rld[i].reg_rtx))
4394 /* Make sure it is the inc/dec pseudo, and not
4395 some other (e.g. output operand) pseudo. */
4396 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4397 == REGNO (XEXP (in_reg, 0))))
4399 SET_HARD_REG_BIT (reg_is_output_reload,
4400 REGNO (rld[i].reg_rtx));
4401 SET_REGNO_REG_SET (®_has_output_reload,
4402 REGNO (XEXP (in_reg, 0)));
4404 else if (code == PRE_INC || code == PRE_DEC
4405 || code == POST_INC || code == POST_DEC)
4407 int in_regno = REGNO (XEXP (in_reg, 0));
4409 if (reg_last_reload_reg[in_regno] != NULL_RTX)
4412 bool forget_p = true;
4414 in_hard_regno = REGNO (reg_last_reload_reg[in_regno]);
4415 if (TEST_HARD_REG_BIT (reg_reloaded_valid,
4418 for (x = old_prev ? NEXT_INSN (old_prev) : insn;
4421 if (x == reg_reloaded_insn[in_hard_regno])
4427 /* If for some reasons, we didn't set up
4428 reg_last_reload_reg in this insn,
4429 invalidate inheritance from previous
4430 insns for the incremented/decremented
4431 register. Such registers will be not in
4432 reg_has_output_reload. Invalidate it
4433 also if the corresponding element in
4434 reg_reloaded_insn is also
4437 forget_old_reloads_1 (XEXP (in_reg, 0),
4443 /* If a pseudo that got a hard register is auto-incremented,
4444 we must purge records of copying it into pseudos without
4446 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4447 if (REG_NOTE_KIND (x) == REG_INC)
4449 /* See if this pseudo reg was reloaded in this insn.
4450 If so, its last-reload info is still valid
4451 because it is based on this insn's reload. */
4452 for (i = 0; i < n_reloads; i++)
4453 if (rld[i].out == XEXP (x, 0))
4457 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4461 /* A reload reg's contents are unknown after a label. */
4463 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4465 /* Don't assume a reload reg is still good after a call insn
4466 if it is a call-used reg, or if it contains a value that will
4467 be partially clobbered by the call. */
4468 else if (CALL_P (insn))
4470 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4471 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4476 free (reg_last_reload_reg);
4477 CLEAR_REG_SET (®_has_output_reload);
4480 /* Discard all record of any value reloaded from X,
4481 or reloaded in X from someplace else;
4482 unless X is an output reload reg of the current insn.
4484 X may be a hard reg (the reload reg)
4485 or it may be a pseudo reg that was reloaded from.
4487 When DATA is non-NULL just mark the registers in regset
4488 to be forgotten later. */
4491 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4496 regset regs = (regset) data;
4498 /* note_stores does give us subregs of hard regs,
4499 subreg_regno_offset requires a hard reg. */
4500 while (GET_CODE (x) == SUBREG)
4502 /* We ignore the subreg offset when calculating the regno,
4503 because we are using the entire underlying hard register
4513 if (regno >= FIRST_PSEUDO_REGISTER)
4519 nr = hard_regno_nregs[regno][GET_MODE (x)];
4520 /* Storing into a spilled-reg invalidates its contents.
4521 This can happen if a block-local pseudo is allocated to that reg
4522 and it wasn't spilled because this block's total need is 0.
4523 Then some insn might have an optional reload and use this reg. */
4525 for (i = 0; i < nr; i++)
4526 /* But don't do this if the reg actually serves as an output
4527 reload reg in the current instruction. */
4529 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4531 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4532 spill_reg_store[regno + i] = 0;
4538 SET_REGNO_REG_SET (regs, regno + nr);
4541 /* Since value of X has changed,
4542 forget any value previously copied from it. */
4545 /* But don't forget a copy if this is the output reload
4546 that establishes the copy's validity. */
4548 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4549 reg_last_reload_reg[regno + nr] = 0;
4553 /* Forget the reloads marked in regset by previous function. */
4555 forget_marked_reloads (regset regs)
4558 reg_set_iterator rsi;
4559 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4561 if (reg < FIRST_PSEUDO_REGISTER
4562 /* But don't do this if the reg actually serves as an output
4563 reload reg in the current instruction. */
4565 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4567 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4568 spill_reg_store[reg] = 0;
4571 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4572 reg_last_reload_reg[reg] = 0;
4576 /* The following HARD_REG_SETs indicate when each hard register is
4577 used for a reload of various parts of the current insn. */
4579 /* If reg is unavailable for all reloads. */
4580 static HARD_REG_SET reload_reg_unavailable;
4581 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4582 static HARD_REG_SET reload_reg_used;
4583 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4584 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4585 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4586 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4587 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4588 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4589 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4590 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4591 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4592 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4593 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4594 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4595 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4596 static HARD_REG_SET reload_reg_used_in_op_addr;
4597 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4598 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4599 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4600 static HARD_REG_SET reload_reg_used_in_insn;
4601 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4602 static HARD_REG_SET reload_reg_used_in_other_addr;
4604 /* If reg is in use as a reload reg for any sort of reload. */
4605 static HARD_REG_SET reload_reg_used_at_all;
4607 /* If reg is use as an inherited reload. We just mark the first register
4609 static HARD_REG_SET reload_reg_used_for_inherit;
4611 /* Records which hard regs are used in any way, either as explicit use or
4612 by being allocated to a pseudo during any point of the current insn. */
4613 static HARD_REG_SET reg_used_in_insn;
4615 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4616 TYPE. MODE is used to indicate how many consecutive regs are
4620 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4621 enum machine_mode mode)
4623 unsigned int nregs = hard_regno_nregs[regno][mode];
4626 for (i = regno; i < nregs + regno; i++)
4631 SET_HARD_REG_BIT (reload_reg_used, i);
4634 case RELOAD_FOR_INPUT_ADDRESS:
4635 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4638 case RELOAD_FOR_INPADDR_ADDRESS:
4639 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4642 case RELOAD_FOR_OUTPUT_ADDRESS:
4643 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4646 case RELOAD_FOR_OUTADDR_ADDRESS:
4647 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4650 case RELOAD_FOR_OPERAND_ADDRESS:
4651 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4654 case RELOAD_FOR_OPADDR_ADDR:
4655 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4658 case RELOAD_FOR_OTHER_ADDRESS:
4659 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4662 case RELOAD_FOR_INPUT:
4663 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4666 case RELOAD_FOR_OUTPUT:
4667 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4670 case RELOAD_FOR_INSN:
4671 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4675 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4679 /* Similarly, but show REGNO is no longer in use for a reload. */
4682 clear_reload_reg_in_use (unsigned int regno, int opnum,
4683 enum reload_type type, enum machine_mode mode)
4685 unsigned int nregs = hard_regno_nregs[regno][mode];
4686 unsigned int start_regno, end_regno, r;
4688 /* A complication is that for some reload types, inheritance might
4689 allow multiple reloads of the same types to share a reload register.
4690 We set check_opnum if we have to check only reloads with the same
4691 operand number, and check_any if we have to check all reloads. */
4692 int check_opnum = 0;
4694 HARD_REG_SET *used_in_set;
4699 used_in_set = &reload_reg_used;
4702 case RELOAD_FOR_INPUT_ADDRESS:
4703 used_in_set = &reload_reg_used_in_input_addr[opnum];
4706 case RELOAD_FOR_INPADDR_ADDRESS:
4708 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4711 case RELOAD_FOR_OUTPUT_ADDRESS:
4712 used_in_set = &reload_reg_used_in_output_addr[opnum];
4715 case RELOAD_FOR_OUTADDR_ADDRESS:
4717 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4720 case RELOAD_FOR_OPERAND_ADDRESS:
4721 used_in_set = &reload_reg_used_in_op_addr;
4724 case RELOAD_FOR_OPADDR_ADDR:
4726 used_in_set = &reload_reg_used_in_op_addr_reload;
4729 case RELOAD_FOR_OTHER_ADDRESS:
4730 used_in_set = &reload_reg_used_in_other_addr;
4734 case RELOAD_FOR_INPUT:
4735 used_in_set = &reload_reg_used_in_input[opnum];
4738 case RELOAD_FOR_OUTPUT:
4739 used_in_set = &reload_reg_used_in_output[opnum];
4742 case RELOAD_FOR_INSN:
4743 used_in_set = &reload_reg_used_in_insn;
4748 /* We resolve conflicts with remaining reloads of the same type by
4749 excluding the intervals of reload registers by them from the
4750 interval of freed reload registers. Since we only keep track of
4751 one set of interval bounds, we might have to exclude somewhat
4752 more than what would be necessary if we used a HARD_REG_SET here.
4753 But this should only happen very infrequently, so there should
4754 be no reason to worry about it. */
4756 start_regno = regno;
4757 end_regno = regno + nregs;
4758 if (check_opnum || check_any)
4760 for (i = n_reloads - 1; i >= 0; i--)
4762 if (rld[i].when_needed == type
4763 && (check_any || rld[i].opnum == opnum)
4766 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4767 unsigned int conflict_end
4768 = end_hard_regno (rld[i].mode, conflict_start);
4770 /* If there is an overlap with the first to-be-freed register,
4771 adjust the interval start. */
4772 if (conflict_start <= start_regno && conflict_end > start_regno)
4773 start_regno = conflict_end;
4774 /* Otherwise, if there is a conflict with one of the other
4775 to-be-freed registers, adjust the interval end. */
4776 if (conflict_start > start_regno && conflict_start < end_regno)
4777 end_regno = conflict_start;
4782 for (r = start_regno; r < end_regno; r++)
4783 CLEAR_HARD_REG_BIT (*used_in_set, r);
4786 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4787 specified by OPNUM and TYPE. */
4790 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4794 /* In use for a RELOAD_OTHER means it's not available for anything. */
4795 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4796 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4802 /* In use for anything means we can't use it for RELOAD_OTHER. */
4803 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4804 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4805 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4806 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4809 for (i = 0; i < reload_n_operands; i++)
4810 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4811 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4812 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4813 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4814 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4815 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4820 case RELOAD_FOR_INPUT:
4821 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4822 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4825 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4828 /* If it is used for some other input, can't use it. */
4829 for (i = 0; i < reload_n_operands; i++)
4830 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4833 /* If it is used in a later operand's address, can't use it. */
4834 for (i = opnum + 1; i < reload_n_operands; i++)
4835 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4836 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4841 case RELOAD_FOR_INPUT_ADDRESS:
4842 /* Can't use a register if it is used for an input address for this
4843 operand or used as an input in an earlier one. */
4844 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4845 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4848 for (i = 0; i < opnum; i++)
4849 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4854 case RELOAD_FOR_INPADDR_ADDRESS:
4855 /* Can't use a register if it is used for an input address
4856 for this operand or used as an input in an earlier
4858 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4861 for (i = 0; i < opnum; i++)
4862 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4867 case RELOAD_FOR_OUTPUT_ADDRESS:
4868 /* Can't use a register if it is used for an output address for this
4869 operand or used as an output in this or a later operand. Note
4870 that multiple output operands are emitted in reverse order, so
4871 the conflicting ones are those with lower indices. */
4872 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4875 for (i = 0; i <= opnum; i++)
4876 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4881 case RELOAD_FOR_OUTADDR_ADDRESS:
4882 /* Can't use a register if it is used for an output address
4883 for this operand or used as an output in this or a
4884 later operand. Note that multiple output operands are
4885 emitted in reverse order, so the conflicting ones are
4886 those with lower indices. */
4887 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4890 for (i = 0; i <= opnum; i++)
4891 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4896 case RELOAD_FOR_OPERAND_ADDRESS:
4897 for (i = 0; i < reload_n_operands; i++)
4898 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4901 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4902 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4904 case RELOAD_FOR_OPADDR_ADDR:
4905 for (i = 0; i < reload_n_operands; i++)
4906 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4909 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4911 case RELOAD_FOR_OUTPUT:
4912 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4913 outputs, or an operand address for this or an earlier output.
4914 Note that multiple output operands are emitted in reverse order,
4915 so the conflicting ones are those with higher indices. */
4916 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4919 for (i = 0; i < reload_n_operands; i++)
4920 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4923 for (i = opnum; i < reload_n_operands; i++)
4924 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4925 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4930 case RELOAD_FOR_INSN:
4931 for (i = 0; i < reload_n_operands; i++)
4932 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4933 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4936 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4937 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4939 case RELOAD_FOR_OTHER_ADDRESS:
4940 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4947 /* Return 1 if the value in reload reg REGNO, as used by a reload
4948 needed for the part of the insn specified by OPNUM and TYPE,
4949 is still available in REGNO at the end of the insn.
4951 We can assume that the reload reg was already tested for availability
4952 at the time it is needed, and we should not check this again,
4953 in case the reg has already been marked in use. */
4956 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4963 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4964 its value must reach the end. */
4967 /* If this use is for part of the insn,
4968 its value reaches if no subsequent part uses the same register.
4969 Just like the above function, don't try to do this with lots
4972 case RELOAD_FOR_OTHER_ADDRESS:
4973 /* Here we check for everything else, since these don't conflict
4974 with anything else and everything comes later. */
4976 for (i = 0; i < reload_n_operands; i++)
4977 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4978 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4979 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4980 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4981 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4982 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4985 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4986 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4987 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4988 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4990 case RELOAD_FOR_INPUT_ADDRESS:
4991 case RELOAD_FOR_INPADDR_ADDRESS:
4992 /* Similar, except that we check only for this and subsequent inputs
4993 and the address of only subsequent inputs and we do not need
4994 to check for RELOAD_OTHER objects since they are known not to
4997 for (i = opnum; i < reload_n_operands; i++)
4998 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5001 for (i = opnum + 1; i < reload_n_operands; i++)
5002 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5003 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5006 for (i = 0; i < reload_n_operands; i++)
5007 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5008 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5009 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5012 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5015 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5016 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5017 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5019 case RELOAD_FOR_INPUT:
5020 /* Similar to input address, except we start at the next operand for
5021 both input and input address and we do not check for
5022 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5025 for (i = opnum + 1; i < reload_n_operands; i++)
5026 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5027 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5028 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5031 /* ... fall through ... */
5033 case RELOAD_FOR_OPERAND_ADDRESS:
5034 /* Check outputs and their addresses. */
5036 for (i = 0; i < reload_n_operands; i++)
5037 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5038 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5039 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5042 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5044 case RELOAD_FOR_OPADDR_ADDR:
5045 for (i = 0; i < reload_n_operands; i++)
5046 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5047 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5048 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5051 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5052 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5053 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5055 case RELOAD_FOR_INSN:
5056 /* These conflict with other outputs with RELOAD_OTHER. So
5057 we need only check for output addresses. */
5059 opnum = reload_n_operands;
5061 /* ... fall through ... */
5063 case RELOAD_FOR_OUTPUT:
5064 case RELOAD_FOR_OUTPUT_ADDRESS:
5065 case RELOAD_FOR_OUTADDR_ADDRESS:
5066 /* We already know these can't conflict with a later output. So the
5067 only thing to check are later output addresses.
5068 Note that multiple output operands are emitted in reverse order,
5069 so the conflicting ones are those with lower indices. */
5070 for (i = 0; i < opnum; i++)
5071 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5072 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5082 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5083 every register in the range [REGNO, REGNO + NREGS). */
5086 reload_regs_reach_end_p (unsigned int regno, int nregs,
5087 int opnum, enum reload_type type)
5091 for (i = 0; i < nregs; i++)
5092 if (!reload_reg_reaches_end_p (regno + i, opnum, type))
5098 /* Returns whether R1 and R2 are uniquely chained: the value of one
5099 is used by the other, and that value is not used by any other
5100 reload for this insn. This is used to partially undo the decision
5101 made in find_reloads when in the case of multiple
5102 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5103 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5104 reloads. This code tries to avoid the conflict created by that
5105 change. It might be cleaner to explicitly keep track of which
5106 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5107 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5108 this after the fact. */
5110 reloads_unique_chain_p (int r1, int r2)
5114 /* We only check input reloads. */
5115 if (! rld[r1].in || ! rld[r2].in)
5118 /* Avoid anything with output reloads. */
5119 if (rld[r1].out || rld[r2].out)
5122 /* "chained" means one reload is a component of the other reload,
5123 not the same as the other reload. */
5124 if (rld[r1].opnum != rld[r2].opnum
5125 || rtx_equal_p (rld[r1].in, rld[r2].in)
5126 || rld[r1].optional || rld[r2].optional
5127 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5128 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5131 for (i = 0; i < n_reloads; i ++)
5132 /* Look for input reloads that aren't our two */
5133 if (i != r1 && i != r2 && rld[i].in)
5135 /* If our reload is mentioned at all, it isn't a simple chain. */
5136 if (reg_mentioned_p (rld[r1].in, rld[i].in))
5143 /* The recursive function change all occurrences of WHAT in *WHERE
5146 substitute (rtx *where, const_rtx what, rtx repl)
5155 if (*where == what || rtx_equal_p (*where, what))
5161 code = GET_CODE (*where);
5162 fmt = GET_RTX_FORMAT (code);
5163 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5169 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5170 substitute (&XVECEXP (*where, i, j), what, repl);
5172 else if (fmt[i] == 'e')
5173 substitute (&XEXP (*where, i), what, repl);
5177 /* The function returns TRUE if chain of reload R1 and R2 (in any
5178 order) can be evaluated without usage of intermediate register for
5179 the reload containing another reload. It is important to see
5180 gen_reload to understand what the function is trying to do. As an
5181 example, let us have reload chain
5184 r1: <something> + const
5186 and reload R2 got reload reg HR. The function returns true if
5187 there is a correct insn HR = HR + <something>. Otherwise,
5188 gen_reload will use intermediate register (and this is the reload
5189 reg for R1) to reload <something>.
5191 We need this function to find a conflict for chain reloads. In our
5192 example, if HR = HR + <something> is incorrect insn, then we cannot
5193 use HR as a reload register for R2. If we do use it then we get a
5202 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5206 rtx out, in, tem, insn;
5207 rtx last = get_last_insn ();
5209 /* Make r2 a component of r1. */
5210 if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5216 gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5217 regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5218 gcc_assert (regno >= 0);
5219 out = gen_rtx_REG (rld[r1].mode, regno);
5220 in = copy_rtx (rld[r1].in);
5221 substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5223 /* If IN is a paradoxical SUBREG, remove it and try to put the
5224 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5225 if (GET_CODE (in) == SUBREG
5226 && (GET_MODE_SIZE (GET_MODE (in))
5227 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
5228 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
5229 in = SUBREG_REG (in), out = tem;
5231 if (GET_CODE (in) == PLUS
5232 && (REG_P (XEXP (in, 0))
5233 || GET_CODE (XEXP (in, 0)) == SUBREG
5234 || MEM_P (XEXP (in, 0)))
5235 && (REG_P (XEXP (in, 1))
5236 || GET_CODE (XEXP (in, 1)) == SUBREG
5237 || CONSTANT_P (XEXP (in, 1))
5238 || MEM_P (XEXP (in, 1))))
5240 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
5241 code = recog_memoized (insn);
5246 extract_insn (insn);
5247 /* We want constrain operands to treat this insn strictly in
5248 its validity determination, i.e., the way it would after
5249 reload has completed. */
5250 result = constrain_operands (1);
5253 delete_insns_since (last);
5257 /* It looks like other cases in gen_reload are not possible for
5258 chain reloads or do need an intermediate hard registers. */
5262 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5265 This function uses the same algorithm as reload_reg_free_p above. */
5268 reloads_conflict (int r1, int r2)
5270 enum reload_type r1_type = rld[r1].when_needed;
5271 enum reload_type r2_type = rld[r2].when_needed;
5272 int r1_opnum = rld[r1].opnum;
5273 int r2_opnum = rld[r2].opnum;
5275 /* RELOAD_OTHER conflicts with everything. */
5276 if (r2_type == RELOAD_OTHER)
5279 /* Otherwise, check conflicts differently for each type. */
5283 case RELOAD_FOR_INPUT:
5284 return (r2_type == RELOAD_FOR_INSN
5285 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5286 || r2_type == RELOAD_FOR_OPADDR_ADDR
5287 || r2_type == RELOAD_FOR_INPUT
5288 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5289 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5290 && r2_opnum > r1_opnum));
5292 case RELOAD_FOR_INPUT_ADDRESS:
5293 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5294 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5296 case RELOAD_FOR_INPADDR_ADDRESS:
5297 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5298 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5300 case RELOAD_FOR_OUTPUT_ADDRESS:
5301 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5302 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5304 case RELOAD_FOR_OUTADDR_ADDRESS:
5305 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5306 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5308 case RELOAD_FOR_OPERAND_ADDRESS:
5309 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5310 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5311 && (!reloads_unique_chain_p (r1, r2)
5312 || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5314 case RELOAD_FOR_OPADDR_ADDR:
5315 return (r2_type == RELOAD_FOR_INPUT
5316 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5318 case RELOAD_FOR_OUTPUT:
5319 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5320 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5321 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5322 && r2_opnum >= r1_opnum));
5324 case RELOAD_FOR_INSN:
5325 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5326 || r2_type == RELOAD_FOR_INSN
5327 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5329 case RELOAD_FOR_OTHER_ADDRESS:
5330 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5340 /* Indexed by reload number, 1 if incoming value
5341 inherited from previous insns. */
5342 static char reload_inherited[MAX_RELOADS];
5344 /* For an inherited reload, this is the insn the reload was inherited from,
5345 if we know it. Otherwise, this is 0. */
5346 static rtx reload_inheritance_insn[MAX_RELOADS];
5348 /* If nonzero, this is a place to get the value of the reload,
5349 rather than using reload_in. */
5350 static rtx reload_override_in[MAX_RELOADS];
5352 /* For each reload, the hard register number of the register used,
5353 or -1 if we did not need a register for this reload. */
5354 static int reload_spill_index[MAX_RELOADS];
5356 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5357 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5359 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5360 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5362 /* Subroutine of free_for_value_p, used to check a single register.
5363 START_REGNO is the starting regno of the full reload register
5364 (possibly comprising multiple hard registers) that we are considering. */
5367 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5368 enum reload_type type, rtx value, rtx out,
5369 int reloadnum, int ignore_address_reloads)
5372 /* Set if we see an input reload that must not share its reload register
5373 with any new earlyclobber, but might otherwise share the reload
5374 register with an output or input-output reload. */
5375 int check_earlyclobber = 0;
5379 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5382 if (out == const0_rtx)
5388 /* We use some pseudo 'time' value to check if the lifetimes of the
5389 new register use would overlap with the one of a previous reload
5390 that is not read-only or uses a different value.
5391 The 'time' used doesn't have to be linear in any shape or form, just
5393 Some reload types use different 'buckets' for each operand.
5394 So there are MAX_RECOG_OPERANDS different time values for each
5396 We compute TIME1 as the time when the register for the prospective
5397 new reload ceases to be live, and TIME2 for each existing
5398 reload as the time when that the reload register of that reload
5400 Where there is little to be gained by exact lifetime calculations,
5401 we just make conservative assumptions, i.e. a longer lifetime;
5402 this is done in the 'default:' cases. */
5405 case RELOAD_FOR_OTHER_ADDRESS:
5406 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5407 time1 = copy ? 0 : 1;
5410 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5412 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5413 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5414 respectively, to the time values for these, we get distinct time
5415 values. To get distinct time values for each operand, we have to
5416 multiply opnum by at least three. We round that up to four because
5417 multiply by four is often cheaper. */
5418 case RELOAD_FOR_INPADDR_ADDRESS:
5419 time1 = opnum * 4 + 2;
5421 case RELOAD_FOR_INPUT_ADDRESS:
5422 time1 = opnum * 4 + 3;
5424 case RELOAD_FOR_INPUT:
5425 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5426 executes (inclusive). */
5427 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5429 case RELOAD_FOR_OPADDR_ADDR:
5431 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5432 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5434 case RELOAD_FOR_OPERAND_ADDRESS:
5435 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5437 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5439 case RELOAD_FOR_OUTADDR_ADDRESS:
5440 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5442 case RELOAD_FOR_OUTPUT_ADDRESS:
5443 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5446 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5449 for (i = 0; i < n_reloads; i++)
5451 rtx reg = rld[i].reg_rtx;
5452 if (reg && REG_P (reg)
5453 && ((unsigned) regno - true_regnum (reg)
5454 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5457 rtx other_input = rld[i].in;
5459 /* If the other reload loads the same input value, that
5460 will not cause a conflict only if it's loading it into
5461 the same register. */
5462 if (true_regnum (reg) != start_regno)
5463 other_input = NULL_RTX;
5464 if (! other_input || ! rtx_equal_p (other_input, value)
5465 || rld[i].out || out)
5468 switch (rld[i].when_needed)
5470 case RELOAD_FOR_OTHER_ADDRESS:
5473 case RELOAD_FOR_INPADDR_ADDRESS:
5474 /* find_reloads makes sure that a
5475 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5476 by at most one - the first -
5477 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5478 address reload is inherited, the address address reload
5479 goes away, so we can ignore this conflict. */
5480 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5481 && ignore_address_reloads
5482 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5483 Then the address address is still needed to store
5484 back the new address. */
5485 && ! rld[reloadnum].out)
5487 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5488 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5490 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5491 && ignore_address_reloads
5492 /* Unless we are reloading an auto_inc expression. */
5493 && ! rld[reloadnum].out)
5495 time2 = rld[i].opnum * 4 + 2;
5497 case RELOAD_FOR_INPUT_ADDRESS:
5498 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5499 && ignore_address_reloads
5500 && ! rld[reloadnum].out)
5502 time2 = rld[i].opnum * 4 + 3;
5504 case RELOAD_FOR_INPUT:
5505 time2 = rld[i].opnum * 4 + 4;
5506 check_earlyclobber = 1;
5508 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5509 == MAX_RECOG_OPERAND * 4 */
5510 case RELOAD_FOR_OPADDR_ADDR:
5511 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5512 && ignore_address_reloads
5513 && ! rld[reloadnum].out)
5515 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5517 case RELOAD_FOR_OPERAND_ADDRESS:
5518 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5519 check_earlyclobber = 1;
5521 case RELOAD_FOR_INSN:
5522 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5524 case RELOAD_FOR_OUTPUT:
5525 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5526 instruction is executed. */
5527 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5529 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5530 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5532 case RELOAD_FOR_OUTADDR_ADDRESS:
5533 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5534 && ignore_address_reloads
5535 && ! rld[reloadnum].out)
5537 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5539 case RELOAD_FOR_OUTPUT_ADDRESS:
5540 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5543 /* If there is no conflict in the input part, handle this
5544 like an output reload. */
5545 if (! rld[i].in || rtx_equal_p (other_input, value))
5547 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5548 /* Earlyclobbered outputs must conflict with inputs. */
5549 if (earlyclobber_operand_p (rld[i].out))
5550 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5555 /* RELOAD_OTHER might be live beyond instruction execution,
5556 but this is not obvious when we set time2 = 1. So check
5557 here if there might be a problem with the new reload
5558 clobbering the register used by the RELOAD_OTHER. */
5566 && (! rld[i].in || rld[i].out
5567 || ! rtx_equal_p (other_input, value)))
5568 || (out && rld[reloadnum].out_reg
5569 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5575 /* Earlyclobbered outputs must conflict with inputs. */
5576 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5582 /* Return 1 if the value in reload reg REGNO, as used by a reload
5583 needed for the part of the insn specified by OPNUM and TYPE,
5584 may be used to load VALUE into it.
5586 MODE is the mode in which the register is used, this is needed to
5587 determine how many hard regs to test.
5589 Other read-only reloads with the same value do not conflict
5590 unless OUT is nonzero and these other reloads have to live while
5591 output reloads live.
5592 If OUT is CONST0_RTX, this is a special case: it means that the
5593 test should not be for using register REGNO as reload register, but
5594 for copying from register REGNO into the reload register.
5596 RELOADNUM is the number of the reload we want to load this value for;
5597 a reload does not conflict with itself.
5599 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5600 reloads that load an address for the very reload we are considering.
5602 The caller has to make sure that there is no conflict with the return
5606 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5607 enum reload_type type, rtx value, rtx out, int reloadnum,
5608 int ignore_address_reloads)
5610 int nregs = hard_regno_nregs[regno][mode];
5612 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5613 value, out, reloadnum,
5614 ignore_address_reloads))
5619 /* Return nonzero if the rtx X is invariant over the current function. */
5620 /* ??? Actually, the places where we use this expect exactly what is
5621 tested here, and not everything that is function invariant. In
5622 particular, the frame pointer and arg pointer are special cased;
5623 pic_offset_table_rtx is not, and we must not spill these things to
5627 function_invariant_p (const_rtx x)
5631 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5633 if (GET_CODE (x) == PLUS
5634 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5635 && CONSTANT_P (XEXP (x, 1)))
5640 /* Determine whether the reload reg X overlaps any rtx'es used for
5641 overriding inheritance. Return nonzero if so. */
5644 conflicts_with_override (rtx x)
5647 for (i = 0; i < n_reloads; i++)
5648 if (reload_override_in[i]
5649 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5654 /* Give an error message saying we failed to find a reload for INSN,
5655 and clear out reload R. */
5657 failed_reload (rtx insn, int r)
5659 if (asm_noperands (PATTERN (insn)) < 0)
5660 /* It's the compiler's fault. */
5661 fatal_insn ("could not find a spill register", insn);
5663 /* It's the user's fault; the operand's mode and constraint
5664 don't match. Disable this reload so we don't crash in final. */
5665 error_for_asm (insn,
5666 "%<asm%> operand constraint incompatible with operand size");
5670 rld[r].optional = 1;
5671 rld[r].secondary_p = 1;
5674 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5675 for reload R. If it's valid, get an rtx for it. Return nonzero if
5678 set_reload_reg (int i, int r)
5681 rtx reg = spill_reg_rtx[i];
5683 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5684 spill_reg_rtx[i] = reg
5685 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5687 regno = true_regnum (reg);
5689 /* Detect when the reload reg can't hold the reload mode.
5690 This used to be one `if', but Sequent compiler can't handle that. */
5691 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5693 enum machine_mode test_mode = VOIDmode;
5695 test_mode = GET_MODE (rld[r].in);
5696 /* If rld[r].in has VOIDmode, it means we will load it
5697 in whatever mode the reload reg has: to wit, rld[r].mode.
5698 We have already tested that for validity. */
5699 /* Aside from that, we need to test that the expressions
5700 to reload from or into have modes which are valid for this
5701 reload register. Otherwise the reload insns would be invalid. */
5702 if (! (rld[r].in != 0 && test_mode != VOIDmode
5703 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5704 if (! (rld[r].out != 0
5705 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5707 /* The reg is OK. */
5710 /* Mark as in use for this insn the reload regs we use
5712 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5713 rld[r].when_needed, rld[r].mode);
5715 rld[r].reg_rtx = reg;
5716 reload_spill_index[r] = spill_regs[i];
5723 /* Find a spill register to use as a reload register for reload R.
5724 LAST_RELOAD is nonzero if this is the last reload for the insn being
5727 Set rld[R].reg_rtx to the register allocated.
5729 We return 1 if successful, or 0 if we couldn't find a spill reg and
5730 we didn't change anything. */
5733 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5738 /* If we put this reload ahead, thinking it is a group,
5739 then insist on finding a group. Otherwise we can grab a
5740 reg that some other reload needs.
5741 (That can happen when we have a 68000 DATA_OR_FP_REG
5742 which is a group of data regs or one fp reg.)
5743 We need not be so restrictive if there are no more reloads
5746 ??? Really it would be nicer to have smarter handling
5747 for that kind of reg class, where a problem like this is normal.
5748 Perhaps those classes should be avoided for reloading
5749 by use of more alternatives. */
5751 int force_group = rld[r].nregs > 1 && ! last_reload;
5753 /* If we want a single register and haven't yet found one,
5754 take any reg in the right class and not in use.
5755 If we want a consecutive group, here is where we look for it.
5757 We use two passes so we can first look for reload regs to
5758 reuse, which are already in use for other reloads in this insn,
5759 and only then use additional registers.
5760 I think that maximizing reuse is needed to make sure we don't
5761 run out of reload regs. Suppose we have three reloads, and
5762 reloads A and B can share regs. These need two regs.
5763 Suppose A and B are given different regs.
5764 That leaves none for C. */
5765 for (pass = 0; pass < 2; pass++)
5767 /* I is the index in spill_regs.
5768 We advance it round-robin between insns to use all spill regs
5769 equally, so that inherited reloads have a chance
5770 of leapfrogging each other. */
5774 for (count = 0; count < n_spills; count++)
5776 int rclass = (int) rld[r].rclass;
5782 regnum = spill_regs[i];
5784 if ((reload_reg_free_p (regnum, rld[r].opnum,
5787 /* We check reload_reg_used to make sure we
5788 don't clobber the return register. */
5789 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5790 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5791 rld[r].when_needed, rld[r].in,
5793 && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
5794 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5795 /* Look first for regs to share, then for unshared. But
5796 don't share regs used for inherited reloads; they are
5797 the ones we want to preserve. */
5799 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5801 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5804 int nr = hard_regno_nregs[regnum][rld[r].mode];
5805 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5806 (on 68000) got us two FP regs. If NR is 1,
5807 we would reject both of them. */
5810 /* If we need only one reg, we have already won. */
5813 /* But reject a single reg if we demand a group. */
5818 /* Otherwise check that as many consecutive regs as we need
5819 are available here. */
5822 int regno = regnum + nr - 1;
5823 if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
5824 && spill_reg_order[regno] >= 0
5825 && reload_reg_free_p (regno, rld[r].opnum,
5826 rld[r].when_needed)))
5835 /* If we found something on pass 1, omit pass 2. */
5836 if (count < n_spills)
5840 /* We should have found a spill register by now. */
5841 if (count >= n_spills)
5844 /* I is the index in SPILL_REG_RTX of the reload register we are to
5845 allocate. Get an rtx for it and find its register number. */
5847 return set_reload_reg (i, r);
5850 /* Initialize all the tables needed to allocate reload registers.
5851 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5852 is the array we use to restore the reg_rtx field for every reload. */
5855 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5859 for (i = 0; i < n_reloads; i++)
5860 rld[i].reg_rtx = save_reload_reg_rtx[i];
5862 memset (reload_inherited, 0, MAX_RELOADS);
5863 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5864 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5866 CLEAR_HARD_REG_SET (reload_reg_used);
5867 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5868 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5869 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5870 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5871 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5873 CLEAR_HARD_REG_SET (reg_used_in_insn);
5876 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5877 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5878 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5879 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5880 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5881 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5884 for (i = 0; i < reload_n_operands; i++)
5886 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5887 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5888 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5889 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5890 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5891 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5894 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5896 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5898 for (i = 0; i < n_reloads; i++)
5899 /* If we have already decided to use a certain register,
5900 don't use it in another way. */
5902 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5903 rld[i].when_needed, rld[i].mode);
5906 /* Assign hard reg targets for the pseudo-registers we must reload
5907 into hard regs for this insn.
5908 Also output the instructions to copy them in and out of the hard regs.
5910 For machines with register classes, we are responsible for
5911 finding a reload reg in the proper class. */
5914 choose_reload_regs (struct insn_chain *chain)
5916 rtx insn = chain->insn;
5918 unsigned int max_group_size = 1;
5919 enum reg_class group_class = NO_REGS;
5920 int pass, win, inheritance;
5922 rtx save_reload_reg_rtx[MAX_RELOADS];
5924 /* In order to be certain of getting the registers we need,
5925 we must sort the reloads into order of increasing register class.
5926 Then our grabbing of reload registers will parallel the process
5927 that provided the reload registers.
5929 Also note whether any of the reloads wants a consecutive group of regs.
5930 If so, record the maximum size of the group desired and what
5931 register class contains all the groups needed by this insn. */
5933 for (j = 0; j < n_reloads; j++)
5935 reload_order[j] = j;
5936 if (rld[j].reg_rtx != NULL_RTX)
5938 gcc_assert (REG_P (rld[j].reg_rtx)
5939 && HARD_REGISTER_P (rld[j].reg_rtx));
5940 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
5943 reload_spill_index[j] = -1;
5945 if (rld[j].nregs > 1)
5947 max_group_size = MAX (rld[j].nregs, max_group_size);
5949 = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
5952 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5956 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5958 /* If -O, try first with inheritance, then turning it off.
5959 If not -O, don't do inheritance.
5960 Using inheritance when not optimizing leads to paradoxes
5961 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5962 because one side of the comparison might be inherited. */
5964 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5966 choose_reload_regs_init (chain, save_reload_reg_rtx);
5968 /* Process the reloads in order of preference just found.
5969 Beyond this point, subregs can be found in reload_reg_rtx.
5971 This used to look for an existing reloaded home for all of the
5972 reloads, and only then perform any new reloads. But that could lose
5973 if the reloads were done out of reg-class order because a later
5974 reload with a looser constraint might have an old home in a register
5975 needed by an earlier reload with a tighter constraint.
5977 To solve this, we make two passes over the reloads, in the order
5978 described above. In the first pass we try to inherit a reload
5979 from a previous insn. If there is a later reload that needs a
5980 class that is a proper subset of the class being processed, we must
5981 also allocate a spill register during the first pass.
5983 Then make a second pass over the reloads to allocate any reloads
5984 that haven't been given registers yet. */
5986 for (j = 0; j < n_reloads; j++)
5988 int r = reload_order[j];
5989 rtx search_equiv = NULL_RTX;
5991 /* Ignore reloads that got marked inoperative. */
5992 if (rld[r].out == 0 && rld[r].in == 0
5993 && ! rld[r].secondary_p)
5996 /* If find_reloads chose to use reload_in or reload_out as a reload
5997 register, we don't need to chose one. Otherwise, try even if it
5998 found one since we might save an insn if we find the value lying
6000 Try also when reload_in is a pseudo without a hard reg. */
6001 if (rld[r].in != 0 && rld[r].reg_rtx != 0
6002 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
6003 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
6004 && !MEM_P (rld[r].in)
6005 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
6008 #if 0 /* No longer needed for correct operation.
6009 It might give better code, or might not; worth an experiment? */
6010 /* If this is an optional reload, we can't inherit from earlier insns
6011 until we are sure that any non-optional reloads have been allocated.
6012 The following code takes advantage of the fact that optional reloads
6013 are at the end of reload_order. */
6014 if (rld[r].optional != 0)
6015 for (i = 0; i < j; i++)
6016 if ((rld[reload_order[i]].out != 0
6017 || rld[reload_order[i]].in != 0
6018 || rld[reload_order[i]].secondary_p)
6019 && ! rld[reload_order[i]].optional
6020 && rld[reload_order[i]].reg_rtx == 0)
6021 allocate_reload_reg (chain, reload_order[i], 0);
6024 /* First see if this pseudo is already available as reloaded
6025 for a previous insn. We cannot try to inherit for reloads
6026 that are smaller than the maximum number of registers needed
6027 for groups unless the register we would allocate cannot be used
6030 We could check here to see if this is a secondary reload for
6031 an object that is already in a register of the desired class.
6032 This would avoid the need for the secondary reload register.
6033 But this is complex because we can't easily determine what
6034 objects might want to be loaded via this reload. So let a
6035 register be allocated here. In `emit_reload_insns' we suppress
6036 one of the loads in the case described above. */
6042 enum machine_mode mode = VOIDmode;
6046 else if (REG_P (rld[r].in))
6048 regno = REGNO (rld[r].in);
6049 mode = GET_MODE (rld[r].in);
6051 else if (REG_P (rld[r].in_reg))
6053 regno = REGNO (rld[r].in_reg);
6054 mode = GET_MODE (rld[r].in_reg);
6056 else if (GET_CODE (rld[r].in_reg) == SUBREG
6057 && REG_P (SUBREG_REG (rld[r].in_reg)))
6059 regno = REGNO (SUBREG_REG (rld[r].in_reg));
6060 if (regno < FIRST_PSEUDO_REGISTER)
6061 regno = subreg_regno (rld[r].in_reg);
6063 byte = SUBREG_BYTE (rld[r].in_reg);
6064 mode = GET_MODE (rld[r].in_reg);
6067 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6068 && REG_P (XEXP (rld[r].in_reg, 0)))
6070 regno = REGNO (XEXP (rld[r].in_reg, 0));
6071 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6072 rld[r].out = rld[r].in;
6076 /* This won't work, since REGNO can be a pseudo reg number.
6077 Also, it takes much more hair to keep track of all the things
6078 that can invalidate an inherited reload of part of a pseudoreg. */
6079 else if (GET_CODE (rld[r].in) == SUBREG
6080 && REG_P (SUBREG_REG (rld[r].in)))
6081 regno = subreg_regno (rld[r].in);
6085 && reg_last_reload_reg[regno] != 0
6086 #ifdef CANNOT_CHANGE_MODE_CLASS
6087 /* Verify that the register it's in can be used in
6089 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
6090 GET_MODE (reg_last_reload_reg[regno]),
6095 enum reg_class rclass = rld[r].rclass, last_class;
6096 rtx last_reg = reg_last_reload_reg[regno];
6097 enum machine_mode need_mode;
6099 i = REGNO (last_reg);
6100 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6101 last_class = REGNO_REG_CLASS (i);
6107 = smallest_mode_for_size
6108 (GET_MODE_BITSIZE (mode) + byte * BITS_PER_UNIT,
6109 GET_MODE_CLASS (mode) == MODE_PARTIAL_INT
6110 ? MODE_INT : GET_MODE_CLASS (mode));
6112 if ((GET_MODE_SIZE (GET_MODE (last_reg))
6113 >= GET_MODE_SIZE (need_mode))
6114 && reg_reloaded_contents[i] == regno
6115 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6116 && HARD_REGNO_MODE_OK (i, rld[r].mode)
6117 && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6118 /* Even if we can't use this register as a reload
6119 register, we might use it for reload_override_in,
6120 if copying it to the desired class is cheap
6122 || ((REGISTER_MOVE_COST (mode, last_class, rclass)
6123 < MEMORY_MOVE_COST (mode, rclass, 1))
6124 && (secondary_reload_class (1, rclass, mode,
6127 #ifdef SECONDARY_MEMORY_NEEDED
6128 && ! SECONDARY_MEMORY_NEEDED (last_class, rclass,
6133 && (rld[r].nregs == max_group_size
6134 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6136 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6137 rld[r].when_needed, rld[r].in,
6140 /* If a group is needed, verify that all the subsequent
6141 registers still have their values intact. */
6142 int nr = hard_regno_nregs[i][rld[r].mode];
6145 for (k = 1; k < nr; k++)
6146 if (reg_reloaded_contents[i + k] != regno
6147 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6155 last_reg = (GET_MODE (last_reg) == mode
6156 ? last_reg : gen_rtx_REG (mode, i));
6159 for (k = 0; k < nr; k++)
6160 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6163 /* We found a register that contains the
6164 value we need. If this register is the
6165 same as an `earlyclobber' operand of the
6166 current insn, just mark it as a place to
6167 reload from since we can't use it as the
6168 reload register itself. */
6170 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6171 if (reg_overlap_mentioned_for_reload_p
6172 (reg_last_reload_reg[regno],
6173 reload_earlyclobbers[i1]))
6176 if (i1 != n_earlyclobbers
6177 || ! (free_for_value_p (i, rld[r].mode,
6179 rld[r].when_needed, rld[r].in,
6181 /* Don't use it if we'd clobber a pseudo reg. */
6182 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6184 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6185 /* Don't clobber the frame pointer. */
6186 || (i == HARD_FRAME_POINTER_REGNUM
6187 && frame_pointer_needed
6189 /* Don't really use the inherited spill reg
6190 if we need it wider than we've got it. */
6191 || (GET_MODE_SIZE (rld[r].mode)
6192 > GET_MODE_SIZE (mode))
6195 /* If find_reloads chose reload_out as reload
6196 register, stay with it - that leaves the
6197 inherited register for subsequent reloads. */
6198 || (rld[r].out && rld[r].reg_rtx
6199 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6201 if (! rld[r].optional)
6203 reload_override_in[r] = last_reg;
6204 reload_inheritance_insn[r]
6205 = reg_reloaded_insn[i];
6211 /* We can use this as a reload reg. */
6212 /* Mark the register as in use for this part of
6214 mark_reload_reg_in_use (i,
6218 rld[r].reg_rtx = last_reg;
6219 reload_inherited[r] = 1;
6220 reload_inheritance_insn[r]
6221 = reg_reloaded_insn[i];
6222 reload_spill_index[r] = i;
6223 for (k = 0; k < nr; k++)
6224 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6232 /* Here's another way to see if the value is already lying around. */
6235 && ! reload_inherited[r]
6237 && (CONSTANT_P (rld[r].in)
6238 || GET_CODE (rld[r].in) == PLUS
6239 || REG_P (rld[r].in)
6240 || MEM_P (rld[r].in))
6241 && (rld[r].nregs == max_group_size
6242 || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6243 search_equiv = rld[r].in;
6244 /* If this is an output reload from a simple move insn, look
6245 if an equivalence for the input is available. */
6246 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
6248 rtx set = single_set (insn);
6251 && rtx_equal_p (rld[r].out, SET_DEST (set))
6252 && CONSTANT_P (SET_SRC (set)))
6253 search_equiv = SET_SRC (set);
6259 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6260 -1, NULL, 0, rld[r].mode);
6266 regno = REGNO (equiv);
6269 /* This must be a SUBREG of a hard register.
6270 Make a new REG since this might be used in an
6271 address and not all machines support SUBREGs
6273 gcc_assert (GET_CODE (equiv) == SUBREG);
6274 regno = subreg_regno (equiv);
6275 equiv = gen_rtx_REG (rld[r].mode, regno);
6276 /* If we choose EQUIV as the reload register, but the
6277 loop below decides to cancel the inheritance, we'll
6278 end up reloading EQUIV in rld[r].mode, not the mode
6279 it had originally. That isn't safe when EQUIV isn't
6280 available as a spill register since its value might
6281 still be live at this point. */
6282 for (i = regno; i < regno + (int) rld[r].nregs; i++)
6283 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6288 /* If we found a spill reg, reject it unless it is free
6289 and of the desired class. */
6293 int bad_for_class = 0;
6294 int max_regno = regno + rld[r].nregs;
6296 for (i = regno; i < max_regno; i++)
6298 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6300 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6305 && ! free_for_value_p (regno, rld[r].mode,
6306 rld[r].opnum, rld[r].when_needed,
6307 rld[r].in, rld[r].out, r, 1))
6312 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6315 /* We found a register that contains the value we need.
6316 If this register is the same as an `earlyclobber' operand
6317 of the current insn, just mark it as a place to reload from
6318 since we can't use it as the reload register itself. */
6321 for (i = 0; i < n_earlyclobbers; i++)
6322 if (reg_overlap_mentioned_for_reload_p (equiv,
6323 reload_earlyclobbers[i]))
6325 if (! rld[r].optional)
6326 reload_override_in[r] = equiv;
6331 /* If the equiv register we have found is explicitly clobbered
6332 in the current insn, it depends on the reload type if we
6333 can use it, use it for reload_override_in, or not at all.
6334 In particular, we then can't use EQUIV for a
6335 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6339 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6340 switch (rld[r].when_needed)
6342 case RELOAD_FOR_OTHER_ADDRESS:
6343 case RELOAD_FOR_INPADDR_ADDRESS:
6344 case RELOAD_FOR_INPUT_ADDRESS:
6345 case RELOAD_FOR_OPADDR_ADDR:
6348 case RELOAD_FOR_INPUT:
6349 case RELOAD_FOR_OPERAND_ADDRESS:
6350 if (! rld[r].optional)
6351 reload_override_in[r] = equiv;
6357 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6358 switch (rld[r].when_needed)
6360 case RELOAD_FOR_OTHER_ADDRESS:
6361 case RELOAD_FOR_INPADDR_ADDRESS:
6362 case RELOAD_FOR_INPUT_ADDRESS:
6363 case RELOAD_FOR_OPADDR_ADDR:
6364 case RELOAD_FOR_OPERAND_ADDRESS:
6365 case RELOAD_FOR_INPUT:
6368 if (! rld[r].optional)
6369 reload_override_in[r] = equiv;
6377 /* If we found an equivalent reg, say no code need be generated
6378 to load it, and use it as our reload reg. */
6380 && (regno != HARD_FRAME_POINTER_REGNUM
6381 || !frame_pointer_needed))
6383 int nr = hard_regno_nregs[regno][rld[r].mode];
6385 rld[r].reg_rtx = equiv;
6386 reload_spill_index[r] = regno;
6387 reload_inherited[r] = 1;
6389 /* If reg_reloaded_valid is not set for this register,
6390 there might be a stale spill_reg_store lying around.
6391 We must clear it, since otherwise emit_reload_insns
6392 might delete the store. */
6393 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6394 spill_reg_store[regno] = NULL_RTX;
6395 /* If any of the hard registers in EQUIV are spill
6396 registers, mark them as in use for this insn. */
6397 for (k = 0; k < nr; k++)
6399 i = spill_reg_order[regno + k];
6402 mark_reload_reg_in_use (regno, rld[r].opnum,
6405 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6412 /* If we found a register to use already, or if this is an optional
6413 reload, we are done. */
6414 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6418 /* No longer needed for correct operation. Might or might
6419 not give better code on the average. Want to experiment? */
6421 /* See if there is a later reload that has a class different from our
6422 class that intersects our class or that requires less register
6423 than our reload. If so, we must allocate a register to this
6424 reload now, since that reload might inherit a previous reload
6425 and take the only available register in our class. Don't do this
6426 for optional reloads since they will force all previous reloads
6427 to be allocated. Also don't do this for reloads that have been
6430 for (i = j + 1; i < n_reloads; i++)
6432 int s = reload_order[i];
6434 if ((rld[s].in == 0 && rld[s].out == 0
6435 && ! rld[s].secondary_p)
6439 if ((rld[s].rclass != rld[r].rclass
6440 && reg_classes_intersect_p (rld[r].rclass,
6442 || rld[s].nregs < rld[r].nregs)
6449 allocate_reload_reg (chain, r, j == n_reloads - 1);
6453 /* Now allocate reload registers for anything non-optional that
6454 didn't get one yet. */
6455 for (j = 0; j < n_reloads; j++)
6457 int r = reload_order[j];
6459 /* Ignore reloads that got marked inoperative. */
6460 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6463 /* Skip reloads that already have a register allocated or are
6465 if (rld[r].reg_rtx != 0 || rld[r].optional)
6468 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6472 /* If that loop got all the way, we have won. */
6479 /* Loop around and try without any inheritance. */
6484 /* First undo everything done by the failed attempt
6485 to allocate with inheritance. */
6486 choose_reload_regs_init (chain, save_reload_reg_rtx);
6488 /* Some sanity tests to verify that the reloads found in the first
6489 pass are identical to the ones we have now. */
6490 gcc_assert (chain->n_reloads == n_reloads);
6492 for (i = 0; i < n_reloads; i++)
6494 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6496 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6497 for (j = 0; j < n_spills; j++)
6498 if (spill_regs[j] == chain->rld[i].regno)
6499 if (! set_reload_reg (j, i))
6500 failed_reload (chain->insn, i);
6504 /* If we thought we could inherit a reload, because it seemed that
6505 nothing else wanted the same reload register earlier in the insn,
6506 verify that assumption, now that all reloads have been assigned.
6507 Likewise for reloads where reload_override_in has been set. */
6509 /* If doing expensive optimizations, do one preliminary pass that doesn't
6510 cancel any inheritance, but removes reloads that have been needed only
6511 for reloads that we know can be inherited. */
6512 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6514 for (j = 0; j < n_reloads; j++)
6516 int r = reload_order[j];
6518 if (reload_inherited[r] && rld[r].reg_rtx)
6519 check_reg = rld[r].reg_rtx;
6520 else if (reload_override_in[r]
6521 && (REG_P (reload_override_in[r])
6522 || GET_CODE (reload_override_in[r]) == SUBREG))
6523 check_reg = reload_override_in[r];
6526 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6527 rld[r].opnum, rld[r].when_needed, rld[r].in,
6528 (reload_inherited[r]
6529 ? rld[r].out : const0_rtx),
6534 reload_inherited[r] = 0;
6535 reload_override_in[r] = 0;
6537 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6538 reload_override_in, then we do not need its related
6539 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6540 likewise for other reload types.
6541 We handle this by removing a reload when its only replacement
6542 is mentioned in reload_in of the reload we are going to inherit.
6543 A special case are auto_inc expressions; even if the input is
6544 inherited, we still need the address for the output. We can
6545 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6546 If we succeeded removing some reload and we are doing a preliminary
6547 pass just to remove such reloads, make another pass, since the
6548 removal of one reload might allow us to inherit another one. */
6550 && rld[r].out != rld[r].in
6551 && remove_address_replacements (rld[r].in) && pass)
6556 /* Now that reload_override_in is known valid,
6557 actually override reload_in. */
6558 for (j = 0; j < n_reloads; j++)
6559 if (reload_override_in[j])
6560 rld[j].in = reload_override_in[j];
6562 /* If this reload won't be done because it has been canceled or is
6563 optional and not inherited, clear reload_reg_rtx so other
6564 routines (such as subst_reloads) don't get confused. */
6565 for (j = 0; j < n_reloads; j++)
6566 if (rld[j].reg_rtx != 0
6567 && ((rld[j].optional && ! reload_inherited[j])
6568 || (rld[j].in == 0 && rld[j].out == 0
6569 && ! rld[j].secondary_p)))
6571 int regno = true_regnum (rld[j].reg_rtx);
6573 if (spill_reg_order[regno] >= 0)
6574 clear_reload_reg_in_use (regno, rld[j].opnum,
6575 rld[j].when_needed, rld[j].mode);
6577 reload_spill_index[j] = -1;
6580 /* Record which pseudos and which spill regs have output reloads. */
6581 for (j = 0; j < n_reloads; j++)
6583 int r = reload_order[j];
6585 i = reload_spill_index[r];
6587 /* I is nonneg if this reload uses a register.
6588 If rld[r].reg_rtx is 0, this is an optional reload
6589 that we opted to ignore. */
6590 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6591 && rld[r].reg_rtx != 0)
6593 int nregno = REGNO (rld[r].out_reg);
6596 if (nregno < FIRST_PSEUDO_REGISTER)
6597 nr = hard_regno_nregs[nregno][rld[r].mode];
6600 SET_REGNO_REG_SET (®_has_output_reload,
6605 nr = hard_regno_nregs[i][rld[r].mode];
6607 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6610 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6611 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6612 || rld[r].when_needed == RELOAD_FOR_INSN);
6617 /* Deallocate the reload register for reload R. This is called from
6618 remove_address_replacements. */
6621 deallocate_reload_reg (int r)
6625 if (! rld[r].reg_rtx)
6627 regno = true_regnum (rld[r].reg_rtx);
6629 if (spill_reg_order[regno] >= 0)
6630 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6632 reload_spill_index[r] = -1;
6635 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6636 reloads of the same item for fear that we might not have enough reload
6637 registers. However, normally they will get the same reload register
6638 and hence actually need not be loaded twice.
6640 Here we check for the most common case of this phenomenon: when we have
6641 a number of reloads for the same object, each of which were allocated
6642 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6643 reload, and is not modified in the insn itself. If we find such,
6644 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6645 This will not increase the number of spill registers needed and will
6646 prevent redundant code. */
6649 merge_assigned_reloads (rtx insn)
6653 /* Scan all the reloads looking for ones that only load values and
6654 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6655 assigned and not modified by INSN. */
6657 for (i = 0; i < n_reloads; i++)
6659 int conflicting_input = 0;
6660 int max_input_address_opnum = -1;
6661 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6663 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6664 || rld[i].out != 0 || rld[i].reg_rtx == 0
6665 || reg_set_p (rld[i].reg_rtx, insn))
6668 /* Look at all other reloads. Ensure that the only use of this
6669 reload_reg_rtx is in a reload that just loads the same value
6670 as we do. Note that any secondary reloads must be of the identical
6671 class since the values, modes, and result registers are the
6672 same, so we need not do anything with any secondary reloads. */
6674 for (j = 0; j < n_reloads; j++)
6676 if (i == j || rld[j].reg_rtx == 0
6677 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6681 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6682 && rld[j].opnum > max_input_address_opnum)
6683 max_input_address_opnum = rld[j].opnum;
6685 /* If the reload regs aren't exactly the same (e.g, different modes)
6686 or if the values are different, we can't merge this reload.
6687 But if it is an input reload, we might still merge
6688 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6690 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6691 || rld[j].out != 0 || rld[j].in == 0
6692 || ! rtx_equal_p (rld[i].in, rld[j].in))
6694 if (rld[j].when_needed != RELOAD_FOR_INPUT
6695 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6696 || rld[i].opnum > rld[j].opnum)
6697 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6699 conflicting_input = 1;
6700 if (min_conflicting_input_opnum > rld[j].opnum)
6701 min_conflicting_input_opnum = rld[j].opnum;
6705 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6706 we, in fact, found any matching reloads. */
6709 && max_input_address_opnum <= min_conflicting_input_opnum)
6711 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6713 for (j = 0; j < n_reloads; j++)
6714 if (i != j && rld[j].reg_rtx != 0
6715 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6716 && (! conflicting_input
6717 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6718 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6720 rld[i].when_needed = RELOAD_OTHER;
6722 reload_spill_index[j] = -1;
6723 transfer_replacements (i, j);
6726 /* If this is now RELOAD_OTHER, look for any reloads that
6727 load parts of this operand and set them to
6728 RELOAD_FOR_OTHER_ADDRESS if they were for inputs,
6729 RELOAD_OTHER for outputs. Note that this test is
6730 equivalent to looking for reloads for this operand
6733 We must take special care with RELOAD_FOR_OUTPUT_ADDRESS;
6734 it may share registers with a RELOAD_FOR_INPUT, so we can
6735 not change it to RELOAD_FOR_OTHER_ADDRESS. We should
6736 never need to, since we do not modify RELOAD_FOR_OUTPUT.
6738 It is possible that the RELOAD_FOR_OPERAND_ADDRESS
6739 instruction is assigned the same register as the earlier
6740 RELOAD_FOR_OTHER_ADDRESS instruction. Merging these two
6741 instructions will cause the RELOAD_FOR_OTHER_ADDRESS
6742 instruction to be deleted later on. */
6744 if (rld[i].when_needed == RELOAD_OTHER)
6745 for (j = 0; j < n_reloads; j++)
6747 && rld[j].when_needed != RELOAD_OTHER
6748 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6749 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6750 && rld[j].when_needed != RELOAD_FOR_OPERAND_ADDRESS
6751 && (! conflicting_input
6752 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6753 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6754 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6760 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6761 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6762 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6764 /* Check to see if we accidentally converted two
6765 reloads that use the same reload register with
6766 different inputs to the same type. If so, the
6767 resulting code won't work. */
6769 for (k = 0; k < j; k++)
6770 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6771 || rld[k].when_needed != rld[j].when_needed
6772 || !rtx_equal_p (rld[k].reg_rtx,
6774 || rtx_equal_p (rld[k].in,
6781 /* These arrays are filled by emit_reload_insns and its subroutines. */
6782 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6783 static rtx other_input_address_reload_insns = 0;
6784 static rtx other_input_reload_insns = 0;
6785 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6786 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6787 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6788 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6789 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6790 static rtx operand_reload_insns = 0;
6791 static rtx other_operand_reload_insns = 0;
6792 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6794 /* Values to be put in spill_reg_store are put here first. */
6795 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6796 static HARD_REG_SET reg_reloaded_died;
6798 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6799 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6800 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6801 adjusted register, and return true. Otherwise, return false. */
6803 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6804 enum reg_class new_class,
6805 enum machine_mode new_mode)
6810 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6812 unsigned regno = REGNO (reg);
6814 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6816 if (GET_MODE (reg) != new_mode)
6818 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6820 if (hard_regno_nregs[regno][new_mode]
6821 > hard_regno_nregs[regno][GET_MODE (reg)])
6823 reg = reload_adjust_reg_for_mode (reg, new_mode);
6831 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6832 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6833 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6834 adjusted register, and return true. Otherwise, return false. */
6836 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6837 enum insn_code icode)
6840 enum reg_class new_class = scratch_reload_class (icode);
6841 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6843 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6844 new_class, new_mode);
6847 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6848 has the number J. OLD contains the value to be used as input. */
6851 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6854 rtx insn = chain->insn;
6856 rtx oldequiv_reg = 0;
6859 enum machine_mode mode;
6862 /* delete_output_reload is only invoked properly if old contains
6863 the original pseudo register. Since this is replaced with a
6864 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6865 find the pseudo in RELOAD_IN_REG. */
6866 if (reload_override_in[j]
6867 && REG_P (rl->in_reg))
6874 else if (REG_P (oldequiv))
6875 oldequiv_reg = oldequiv;
6876 else if (GET_CODE (oldequiv) == SUBREG)
6877 oldequiv_reg = SUBREG_REG (oldequiv);
6879 reloadreg = reload_reg_rtx_for_input[j];
6880 mode = GET_MODE (reloadreg);
6882 /* If we are reloading from a register that was recently stored in
6883 with an output-reload, see if we can prove there was
6884 actually no need to store the old value in it. */
6886 if (optimize && REG_P (oldequiv)
6887 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6888 && spill_reg_store[REGNO (oldequiv)]
6890 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6891 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6893 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6895 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
6898 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6899 oldequiv = SUBREG_REG (oldequiv);
6900 if (GET_MODE (oldequiv) != VOIDmode
6901 && mode != GET_MODE (oldequiv))
6902 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6904 /* Switch to the right place to emit the reload insns. */
6905 switch (rl->when_needed)
6908 where = &other_input_reload_insns;
6910 case RELOAD_FOR_INPUT:
6911 where = &input_reload_insns[rl->opnum];
6913 case RELOAD_FOR_INPUT_ADDRESS:
6914 where = &input_address_reload_insns[rl->opnum];
6916 case RELOAD_FOR_INPADDR_ADDRESS:
6917 where = &inpaddr_address_reload_insns[rl->opnum];
6919 case RELOAD_FOR_OUTPUT_ADDRESS:
6920 where = &output_address_reload_insns[rl->opnum];
6922 case RELOAD_FOR_OUTADDR_ADDRESS:
6923 where = &outaddr_address_reload_insns[rl->opnum];
6925 case RELOAD_FOR_OPERAND_ADDRESS:
6926 where = &operand_reload_insns;
6928 case RELOAD_FOR_OPADDR_ADDR:
6929 where = &other_operand_reload_insns;
6931 case RELOAD_FOR_OTHER_ADDRESS:
6932 where = &other_input_address_reload_insns;
6938 push_to_sequence (*where);
6940 /* Auto-increment addresses must be reloaded in a special way. */
6941 if (rl->out && ! rl->out_reg)
6943 /* We are not going to bother supporting the case where a
6944 incremented register can't be copied directly from
6945 OLDEQUIV since this seems highly unlikely. */
6946 gcc_assert (rl->secondary_in_reload < 0);
6948 if (reload_inherited[j])
6949 oldequiv = reloadreg;
6951 old = XEXP (rl->in_reg, 0);
6953 if (optimize && REG_P (oldequiv)
6954 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6955 && spill_reg_store[REGNO (oldequiv)]
6957 && (dead_or_set_p (insn,
6958 spill_reg_stored_to[REGNO (oldequiv)])
6959 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6961 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6963 /* Prevent normal processing of this reload. */
6965 /* Output a special code sequence for this case. */
6966 new_spill_reg_store[REGNO (reloadreg)]
6967 = inc_for_reload (reloadreg, oldequiv, rl->out,
6971 /* If we are reloading a pseudo-register that was set by the previous
6972 insn, see if we can get rid of that pseudo-register entirely
6973 by redirecting the previous insn into our reload register. */
6975 else if (optimize && REG_P (old)
6976 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6977 && dead_or_set_p (insn, old)
6978 /* This is unsafe if some other reload
6979 uses the same reg first. */
6980 && ! conflicts_with_override (reloadreg)
6981 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6982 rl->when_needed, old, rl->out, j, 0))
6984 rtx temp = PREV_INSN (insn);
6985 while (temp && (NOTE_P (temp) || DEBUG_INSN_P (temp)))
6986 temp = PREV_INSN (temp);
6988 && NONJUMP_INSN_P (temp)
6989 && GET_CODE (PATTERN (temp)) == SET
6990 && SET_DEST (PATTERN (temp)) == old
6991 /* Make sure we can access insn_operand_constraint. */
6992 && asm_noperands (PATTERN (temp)) < 0
6993 /* This is unsafe if operand occurs more than once in current
6994 insn. Perhaps some occurrences aren't reloaded. */
6995 && count_occurrences (PATTERN (insn), old, 0) == 1)
6997 rtx old = SET_DEST (PATTERN (temp));
6998 /* Store into the reload register instead of the pseudo. */
6999 SET_DEST (PATTERN (temp)) = reloadreg;
7001 /* Verify that resulting insn is valid. */
7002 extract_insn (temp);
7003 if (constrain_operands (1))
7005 /* If the previous insn is an output reload, the source is
7006 a reload register, and its spill_reg_store entry will
7007 contain the previous destination. This is now
7009 if (REG_P (SET_SRC (PATTERN (temp)))
7010 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
7012 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7013 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7016 /* If these are the only uses of the pseudo reg,
7017 pretend for GDB it lives in the reload reg we used. */
7018 if (REG_N_DEATHS (REGNO (old)) == 1
7019 && REG_N_SETS (REGNO (old)) == 1)
7021 reg_renumber[REGNO (old)] = REGNO (reloadreg);
7022 if (ira_conflicts_p)
7023 /* Inform IRA about the change. */
7024 ira_mark_allocation_change (REGNO (old));
7025 alter_reg (REGNO (old), -1, false);
7029 /* Adjust any debug insns between temp and insn. */
7030 while ((temp = NEXT_INSN (temp)) != insn)
7031 if (DEBUG_INSN_P (temp))
7032 replace_rtx (PATTERN (temp), old, reloadreg);
7034 gcc_assert (NOTE_P (temp));
7038 SET_DEST (PATTERN (temp)) = old;
7043 /* We can't do that, so output an insn to load RELOADREG. */
7045 /* If we have a secondary reload, pick up the secondary register
7046 and icode, if any. If OLDEQUIV and OLD are different or
7047 if this is an in-out reload, recompute whether or not we
7048 still need a secondary register and what the icode should
7049 be. If we still need a secondary register and the class or
7050 icode is different, go back to reloading from OLD if using
7051 OLDEQUIV means that we got the wrong type of register. We
7052 cannot have different class or icode due to an in-out reload
7053 because we don't make such reloads when both the input and
7054 output need secondary reload registers. */
7056 if (! special && rl->secondary_in_reload >= 0)
7058 rtx second_reload_reg = 0;
7059 rtx third_reload_reg = 0;
7060 int secondary_reload = rl->secondary_in_reload;
7061 rtx real_oldequiv = oldequiv;
7064 enum insn_code icode;
7065 enum insn_code tertiary_icode = CODE_FOR_nothing;
7067 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7068 and similarly for OLD.
7069 See comments in get_secondary_reload in reload.c. */
7070 /* If it is a pseudo that cannot be replaced with its
7071 equivalent MEM, we must fall back to reload_in, which
7072 will have all the necessary substitutions registered.
7073 Likewise for a pseudo that can't be replaced with its
7074 equivalent constant.
7076 Take extra care for subregs of such pseudos. Note that
7077 we cannot use reg_equiv_mem in this case because it is
7078 not in the right mode. */
7081 if (GET_CODE (tmp) == SUBREG)
7082 tmp = SUBREG_REG (tmp);
7084 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7085 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
7086 || reg_equiv_constant[REGNO (tmp)] != 0))
7088 if (! reg_equiv_mem[REGNO (tmp)]
7089 || num_not_at_initial_offset
7090 || GET_CODE (oldequiv) == SUBREG)
7091 real_oldequiv = rl->in;
7093 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
7097 if (GET_CODE (tmp) == SUBREG)
7098 tmp = SUBREG_REG (tmp);
7100 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7101 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
7102 || reg_equiv_constant[REGNO (tmp)] != 0))
7104 if (! reg_equiv_mem[REGNO (tmp)]
7105 || num_not_at_initial_offset
7106 || GET_CODE (old) == SUBREG)
7109 real_old = reg_equiv_mem[REGNO (tmp)];
7112 second_reload_reg = rld[secondary_reload].reg_rtx;
7113 if (rld[secondary_reload].secondary_in_reload >= 0)
7115 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7117 third_reload_reg = rld[tertiary_reload].reg_rtx;
7118 tertiary_icode = rld[secondary_reload].secondary_in_icode;
7119 /* We'd have to add more code for quartary reloads. */
7120 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7122 icode = rl->secondary_in_icode;
7124 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7125 || (rl->in != 0 && rl->out != 0))
7127 secondary_reload_info sri, sri2;
7128 enum reg_class new_class, new_t_class;
7130 sri.icode = CODE_FOR_nothing;
7131 sri.prev_sri = NULL;
7132 new_class = targetm.secondary_reload (1, real_oldequiv, rl->rclass,
7135 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7136 second_reload_reg = 0;
7137 else if (new_class == NO_REGS)
7139 if (reload_adjust_reg_for_icode (&second_reload_reg,
7141 (enum insn_code) sri.icode))
7143 icode = (enum insn_code) sri.icode;
7144 third_reload_reg = 0;
7149 real_oldequiv = real_old;
7152 else if (sri.icode != CODE_FOR_nothing)
7153 /* We currently lack a way to express this in reloads. */
7157 sri2.icode = CODE_FOR_nothing;
7158 sri2.prev_sri = &sri;
7159 new_t_class = targetm.secondary_reload (1, real_oldequiv,
7160 new_class, mode, &sri);
7161 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7163 if (reload_adjust_reg_for_temp (&second_reload_reg,
7167 third_reload_reg = 0;
7168 tertiary_icode = (enum insn_code) sri2.icode;
7173 real_oldequiv = real_old;
7176 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7178 rtx intermediate = second_reload_reg;
7180 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7182 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7186 second_reload_reg = intermediate;
7187 tertiary_icode = (enum insn_code) sri2.icode;
7192 real_oldequiv = real_old;
7195 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7197 rtx intermediate = second_reload_reg;
7199 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7201 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7204 second_reload_reg = intermediate;
7205 tertiary_icode = (enum insn_code) sri2.icode;
7210 real_oldequiv = real_old;
7215 /* This could be handled more intelligently too. */
7217 real_oldequiv = real_old;
7222 /* If we still need a secondary reload register, check
7223 to see if it is being used as a scratch or intermediate
7224 register and generate code appropriately. If we need
7225 a scratch register, use REAL_OLDEQUIV since the form of
7226 the insn may depend on the actual address if it is
7229 if (second_reload_reg)
7231 if (icode != CODE_FOR_nothing)
7233 /* We'd have to add extra code to handle this case. */
7234 gcc_assert (!third_reload_reg);
7236 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7237 second_reload_reg));
7242 /* See if we need a scratch register to load the
7243 intermediate register (a tertiary reload). */
7244 if (tertiary_icode != CODE_FOR_nothing)
7246 emit_insn ((GEN_FCN (tertiary_icode)
7247 (second_reload_reg, real_oldequiv,
7248 third_reload_reg)));
7250 else if (third_reload_reg)
7252 gen_reload (third_reload_reg, real_oldequiv,
7255 gen_reload (second_reload_reg, third_reload_reg,
7260 gen_reload (second_reload_reg, real_oldequiv,
7264 oldequiv = second_reload_reg;
7269 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7271 rtx real_oldequiv = oldequiv;
7273 if ((REG_P (oldequiv)
7274 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7275 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
7276 || reg_equiv_constant[REGNO (oldequiv)] != 0))
7277 || (GET_CODE (oldequiv) == SUBREG
7278 && REG_P (SUBREG_REG (oldequiv))
7279 && (REGNO (SUBREG_REG (oldequiv))
7280 >= FIRST_PSEUDO_REGISTER)
7281 && ((reg_equiv_memory_loc
7282 [REGNO (SUBREG_REG (oldequiv))] != 0)
7283 || (reg_equiv_constant
7284 [REGNO (SUBREG_REG (oldequiv))] != 0)))
7285 || (CONSTANT_P (oldequiv)
7286 && (PREFERRED_RELOAD_CLASS (oldequiv,
7287 REGNO_REG_CLASS (REGNO (reloadreg)))
7289 real_oldequiv = rl->in;
7290 gen_reload (reloadreg, real_oldequiv, rl->opnum,
7294 if (flag_non_call_exceptions)
7295 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7297 /* End this sequence. */
7298 *where = get_insns ();
7301 /* Update reload_override_in so that delete_address_reloads_1
7302 can see the actual register usage. */
7304 reload_override_in[j] = oldequiv;
7307 /* Generate insns to for the output reload RL, which is for the insn described
7308 by CHAIN and has the number J. */
7310 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7314 rtx insn = chain->insn;
7317 enum machine_mode mode;
7321 if (rl->when_needed == RELOAD_OTHER)
7324 push_to_sequence (output_reload_insns[rl->opnum]);
7326 rl_reg_rtx = reload_reg_rtx_for_output[j];
7327 mode = GET_MODE (rl_reg_rtx);
7329 reloadreg = rl_reg_rtx;
7331 /* If we need two reload regs, set RELOADREG to the intermediate
7332 one, since it will be stored into OLD. We might need a secondary
7333 register only for an input reload, so check again here. */
7335 if (rl->secondary_out_reload >= 0)
7338 int secondary_reload = rl->secondary_out_reload;
7339 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7341 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7342 && reg_equiv_mem[REGNO (old)] != 0)
7343 real_old = reg_equiv_mem[REGNO (old)];
7345 if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7347 rtx second_reloadreg = reloadreg;
7348 reloadreg = rld[secondary_reload].reg_rtx;
7350 /* See if RELOADREG is to be used as a scratch register
7351 or as an intermediate register. */
7352 if (rl->secondary_out_icode != CODE_FOR_nothing)
7354 /* We'd have to add extra code to handle this case. */
7355 gcc_assert (tertiary_reload < 0);
7357 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7358 (real_old, second_reloadreg, reloadreg)));
7363 /* See if we need both a scratch and intermediate reload
7366 enum insn_code tertiary_icode
7367 = rld[secondary_reload].secondary_out_icode;
7369 /* We'd have to add more code for quartary reloads. */
7370 gcc_assert (tertiary_reload < 0
7371 || rld[tertiary_reload].secondary_out_reload < 0);
7373 if (GET_MODE (reloadreg) != mode)
7374 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7376 if (tertiary_icode != CODE_FOR_nothing)
7378 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7381 /* Copy primary reload reg to secondary reload reg.
7382 (Note that these have been swapped above, then
7383 secondary reload reg to OLD using our insn.) */
7385 /* If REAL_OLD is a paradoxical SUBREG, remove it
7386 and try to put the opposite SUBREG on
7388 if (GET_CODE (real_old) == SUBREG
7389 && (GET_MODE_SIZE (GET_MODE (real_old))
7390 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7391 && 0 != (tem = gen_lowpart_common
7392 (GET_MODE (SUBREG_REG (real_old)),
7394 real_old = SUBREG_REG (real_old), reloadreg = tem;
7396 gen_reload (reloadreg, second_reloadreg,
7397 rl->opnum, rl->when_needed);
7398 emit_insn ((GEN_FCN (tertiary_icode)
7399 (real_old, reloadreg, third_reloadreg)));
7405 /* Copy between the reload regs here and then to
7408 gen_reload (reloadreg, second_reloadreg,
7409 rl->opnum, rl->when_needed);
7410 if (tertiary_reload >= 0)
7412 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7414 gen_reload (third_reloadreg, reloadreg,
7415 rl->opnum, rl->when_needed);
7416 reloadreg = third_reloadreg;
7423 /* Output the last reload insn. */
7428 /* Don't output the last reload if OLD is not the dest of
7429 INSN and is in the src and is clobbered by INSN. */
7430 if (! flag_expensive_optimizations
7432 || !(set = single_set (insn))
7433 || rtx_equal_p (old, SET_DEST (set))
7434 || !reg_mentioned_p (old, SET_SRC (set))
7435 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7436 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7437 gen_reload (old, reloadreg, rl->opnum,
7441 /* Look at all insns we emitted, just to be safe. */
7442 for (p = get_insns (); p; p = NEXT_INSN (p))
7445 rtx pat = PATTERN (p);
7447 /* If this output reload doesn't come from a spill reg,
7448 clear any memory of reloaded copies of the pseudo reg.
7449 If this output reload comes from a spill reg,
7450 reg_has_output_reload will make this do nothing. */
7451 note_stores (pat, forget_old_reloads_1, NULL);
7453 if (reg_mentioned_p (rl_reg_rtx, pat))
7455 rtx set = single_set (insn);
7456 if (reload_spill_index[j] < 0
7458 && SET_SRC (set) == rl_reg_rtx)
7460 int src = REGNO (SET_SRC (set));
7462 reload_spill_index[j] = src;
7463 SET_HARD_REG_BIT (reg_is_output_reload, src);
7464 if (find_regno_note (insn, REG_DEAD, src))
7465 SET_HARD_REG_BIT (reg_reloaded_died, src);
7467 if (HARD_REGISTER_P (rl_reg_rtx))
7469 int s = rl->secondary_out_reload;
7470 set = single_set (p);
7471 /* If this reload copies only to the secondary reload
7472 register, the secondary reload does the actual
7474 if (s >= 0 && set == NULL_RTX)
7475 /* We can't tell what function the secondary reload
7476 has and where the actual store to the pseudo is
7477 made; leave new_spill_reg_store alone. */
7480 && SET_SRC (set) == rl_reg_rtx
7481 && SET_DEST (set) == rld[s].reg_rtx)
7483 /* Usually the next instruction will be the
7484 secondary reload insn; if we can confirm
7485 that it is, setting new_spill_reg_store to
7486 that insn will allow an extra optimization. */
7487 rtx s_reg = rld[s].reg_rtx;
7488 rtx next = NEXT_INSN (p);
7489 rld[s].out = rl->out;
7490 rld[s].out_reg = rl->out_reg;
7491 set = single_set (next);
7492 if (set && SET_SRC (set) == s_reg
7493 && ! new_spill_reg_store[REGNO (s_reg)])
7495 SET_HARD_REG_BIT (reg_is_output_reload,
7497 new_spill_reg_store[REGNO (s_reg)] = next;
7501 new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7506 if (rl->when_needed == RELOAD_OTHER)
7508 emit_insn (other_output_reload_insns[rl->opnum]);
7509 other_output_reload_insns[rl->opnum] = get_insns ();
7512 output_reload_insns[rl->opnum] = get_insns ();
7514 if (flag_non_call_exceptions)
7515 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7520 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7521 and has the number J. */
7523 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7525 rtx insn = chain->insn;
7526 rtx old = (rl->in && MEM_P (rl->in)
7527 ? rl->in_reg : rl->in);
7528 rtx reg_rtx = rl->reg_rtx;
7532 enum machine_mode mode;
7534 /* Determine the mode to reload in.
7535 This is very tricky because we have three to choose from.
7536 There is the mode the insn operand wants (rl->inmode).
7537 There is the mode of the reload register RELOADREG.
7538 There is the intrinsic mode of the operand, which we could find
7539 by stripping some SUBREGs.
7540 It turns out that RELOADREG's mode is irrelevant:
7541 we can change that arbitrarily.
7543 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7544 then the reload reg may not support QImode moves, so use SImode.
7545 If foo is in memory due to spilling a pseudo reg, this is safe,
7546 because the QImode value is in the least significant part of a
7547 slot big enough for a SImode. If foo is some other sort of
7548 memory reference, then it is impossible to reload this case,
7549 so previous passes had better make sure this never happens.
7551 Then consider a one-word union which has SImode and one of its
7552 members is a float, being fetched as (SUBREG:SF union:SI).
7553 We must fetch that as SFmode because we could be loading into
7554 a float-only register. In this case OLD's mode is correct.
7556 Consider an immediate integer: it has VOIDmode. Here we need
7557 to get a mode from something else.
7559 In some cases, there is a fourth mode, the operand's
7560 containing mode. If the insn specifies a containing mode for
7561 this operand, it overrides all others.
7563 I am not sure whether the algorithm here is always right,
7564 but it does the right things in those cases. */
7566 mode = GET_MODE (old);
7567 if (mode == VOIDmode)
7570 /* We cannot use gen_lowpart_common since it can do the wrong thing
7571 when REG_RTX has a multi-word mode. Note that REG_RTX must
7572 always be a REG here. */
7573 if (GET_MODE (reg_rtx) != mode)
7574 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7576 reload_reg_rtx_for_input[j] = reg_rtx;
7579 /* AUTO_INC reloads need to be handled even if inherited. We got an
7580 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7581 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7582 && ! rtx_equal_p (reg_rtx, old)
7584 emit_input_reload_insns (chain, rld + j, old, j);
7586 /* When inheriting a wider reload, we have a MEM in rl->in,
7587 e.g. inheriting a SImode output reload for
7588 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7589 if (optimize && reload_inherited[j] && rl->in
7591 && MEM_P (rl->in_reg)
7592 && reload_spill_index[j] >= 0
7593 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7594 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7596 /* If we are reloading a register that was recently stored in with an
7597 output-reload, see if we can prove there was
7598 actually no need to store the old value in it. */
7601 && (reload_inherited[j] || reload_override_in[j])
7604 && spill_reg_store[REGNO (reg_rtx)] != 0
7606 /* There doesn't seem to be any reason to restrict this to pseudos
7607 and doing so loses in the case where we are copying from a
7608 register of the wrong class. */
7609 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7611 /* The insn might have already some references to stackslots
7612 replaced by MEMs, while reload_out_reg still names the
7614 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7615 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7616 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7619 /* Do output reloading for reload RL, which is for the insn described by
7620 CHAIN and has the number J.
7621 ??? At some point we need to support handling output reloads of
7622 JUMP_INSNs or insns that set cc0. */
7624 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7627 rtx insn = chain->insn;
7628 /* If this is an output reload that stores something that is
7629 not loaded in this same reload, see if we can eliminate a previous
7631 rtx pseudo = rl->out_reg;
7632 rtx reg_rtx = rl->reg_rtx;
7634 if (rl->out && reg_rtx)
7636 enum machine_mode mode;
7638 /* Determine the mode to reload in.
7639 See comments above (for input reloading). */
7640 mode = GET_MODE (rl->out);
7641 if (mode == VOIDmode)
7643 /* VOIDmode should never happen for an output. */
7644 if (asm_noperands (PATTERN (insn)) < 0)
7645 /* It's the compiler's fault. */
7646 fatal_insn ("VOIDmode on an output", insn);
7647 error_for_asm (insn, "output operand is constant in %<asm%>");
7648 /* Prevent crash--use something we know is valid. */
7650 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7652 if (GET_MODE (reg_rtx) != mode)
7653 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7655 reload_reg_rtx_for_output[j] = reg_rtx;
7660 && ! rtx_equal_p (rl->in_reg, pseudo)
7661 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7662 && reg_last_reload_reg[REGNO (pseudo)])
7664 int pseudo_no = REGNO (pseudo);
7665 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7667 /* We don't need to test full validity of last_regno for
7668 inherit here; we only want to know if the store actually
7669 matches the pseudo. */
7670 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7671 && reg_reloaded_contents[last_regno] == pseudo_no
7672 && spill_reg_store[last_regno]
7673 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7674 delete_output_reload (insn, j, last_regno, reg_rtx);
7680 || rtx_equal_p (old, reg_rtx))
7683 /* An output operand that dies right away does need a reload,
7684 but need not be copied from it. Show the new location in the
7686 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7687 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7689 XEXP (note, 0) = reg_rtx;
7692 /* Likewise for a SUBREG of an operand that dies. */
7693 else if (GET_CODE (old) == SUBREG
7694 && REG_P (SUBREG_REG (old))
7695 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7698 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
7701 else if (GET_CODE (old) == SCRATCH)
7702 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7703 but we don't want to make an output reload. */
7706 /* If is a JUMP_INSN, we can't support output reloads yet. */
7707 gcc_assert (NONJUMP_INSN_P (insn));
7709 emit_output_reload_insns (chain, rld + j, j);
7712 /* A reload copies values of MODE from register SRC to register DEST.
7713 Return true if it can be treated for inheritance purposes like a
7714 group of reloads, each one reloading a single hard register. The
7715 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7716 occupy the same number of hard registers. */
7719 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
7720 int src ATTRIBUTE_UNUSED,
7721 enum machine_mode mode ATTRIBUTE_UNUSED)
7723 #ifdef CANNOT_CHANGE_MODE_CLASS
7724 return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
7725 && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
7731 /* Output insns to reload values in and out of the chosen reload regs. */
7734 emit_reload_insns (struct insn_chain *chain)
7736 rtx insn = chain->insn;
7740 CLEAR_HARD_REG_SET (reg_reloaded_died);
7742 for (j = 0; j < reload_n_operands; j++)
7743 input_reload_insns[j] = input_address_reload_insns[j]
7744 = inpaddr_address_reload_insns[j]
7745 = output_reload_insns[j] = output_address_reload_insns[j]
7746 = outaddr_address_reload_insns[j]
7747 = other_output_reload_insns[j] = 0;
7748 other_input_address_reload_insns = 0;
7749 other_input_reload_insns = 0;
7750 operand_reload_insns = 0;
7751 other_operand_reload_insns = 0;
7753 /* Dump reloads into the dump file. */
7756 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7757 debug_reload_to_stream (dump_file);
7760 /* Now output the instructions to copy the data into and out of the
7761 reload registers. Do these in the order that the reloads were reported,
7762 since reloads of base and index registers precede reloads of operands
7763 and the operands may need the base and index registers reloaded. */
7765 for (j = 0; j < n_reloads; j++)
7767 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
7771 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
7772 new_spill_reg_store[i] = 0;
7775 do_input_reload (chain, rld + j, j);
7776 do_output_reload (chain, rld + j, j);
7779 /* Now write all the insns we made for reloads in the order expected by
7780 the allocation functions. Prior to the insn being reloaded, we write
7781 the following reloads:
7783 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7785 RELOAD_OTHER reloads.
7787 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7788 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7789 RELOAD_FOR_INPUT reload for the operand.
7791 RELOAD_FOR_OPADDR_ADDRS reloads.
7793 RELOAD_FOR_OPERAND_ADDRESS reloads.
7795 After the insn being reloaded, we write the following:
7797 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7798 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7799 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7800 reloads for the operand. The RELOAD_OTHER output reloads are
7801 output in descending order by reload number. */
7803 emit_insn_before (other_input_address_reload_insns, insn);
7804 emit_insn_before (other_input_reload_insns, insn);
7806 for (j = 0; j < reload_n_operands; j++)
7808 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7809 emit_insn_before (input_address_reload_insns[j], insn);
7810 emit_insn_before (input_reload_insns[j], insn);
7813 emit_insn_before (other_operand_reload_insns, insn);
7814 emit_insn_before (operand_reload_insns, insn);
7816 for (j = 0; j < reload_n_operands; j++)
7818 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7819 x = emit_insn_after (output_address_reload_insns[j], x);
7820 x = emit_insn_after (output_reload_insns[j], x);
7821 emit_insn_after (other_output_reload_insns[j], x);
7824 /* For all the spill regs newly reloaded in this instruction,
7825 record what they were reloaded from, so subsequent instructions
7826 can inherit the reloads.
7828 Update spill_reg_store for the reloads of this insn.
7829 Copy the elements that were updated in the loop above. */
7831 for (j = 0; j < n_reloads; j++)
7833 int r = reload_order[j];
7834 int i = reload_spill_index[r];
7836 /* If this is a non-inherited input reload from a pseudo, we must
7837 clear any memory of a previous store to the same pseudo. Only do
7838 something if there will not be an output reload for the pseudo
7840 if (rld[r].in_reg != 0
7841 && ! (reload_inherited[r] || reload_override_in[r]))
7843 rtx reg = rld[r].in_reg;
7845 if (GET_CODE (reg) == SUBREG)
7846 reg = SUBREG_REG (reg);
7849 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7850 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
7852 int nregno = REGNO (reg);
7854 if (reg_last_reload_reg[nregno])
7856 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7858 if (reg_reloaded_contents[last_regno] == nregno)
7859 spill_reg_store[last_regno] = 0;
7864 /* I is nonneg if this reload used a register.
7865 If rld[r].reg_rtx is 0, this is an optional reload
7866 that we opted to ignore. */
7868 if (i >= 0 && rld[r].reg_rtx != 0)
7870 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7873 /* For a multi register reload, we need to check if all or part
7874 of the value lives to the end. */
7875 for (k = 0; k < nr; k++)
7876 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7877 rld[r].when_needed))
7878 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7880 /* Maybe the spill reg contains a copy of reload_out. */
7882 && (REG_P (rld[r].out)
7886 || REG_P (rld[r].out_reg)))
7889 enum machine_mode mode;
7892 reg = reload_reg_rtx_for_output[r];
7893 mode = GET_MODE (reg);
7894 regno = REGNO (reg);
7895 nregs = hard_regno_nregs[regno][mode];
7896 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
7897 rld[r].when_needed))
7899 rtx out = (REG_P (rld[r].out)
7903 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7904 int out_regno = REGNO (out);
7905 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
7906 : hard_regno_nregs[out_regno][mode]);
7909 spill_reg_store[regno] = new_spill_reg_store[regno];
7910 spill_reg_stored_to[regno] = out;
7911 reg_last_reload_reg[out_regno] = reg;
7913 piecemeal = (HARD_REGISTER_NUM_P (out_regno)
7914 && nregs == out_nregs
7915 && inherit_piecemeal_p (out_regno, regno, mode));
7917 /* If OUT_REGNO is a hard register, it may occupy more than
7918 one register. If it does, say what is in the
7919 rest of the registers assuming that both registers
7920 agree on how many words the object takes. If not,
7921 invalidate the subsequent registers. */
7923 if (HARD_REGISTER_NUM_P (out_regno))
7924 for (k = 1; k < out_nregs; k++)
7925 reg_last_reload_reg[out_regno + k]
7926 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
7928 /* Now do the inverse operation. */
7929 for (k = 0; k < nregs; k++)
7931 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
7932 reg_reloaded_contents[regno + k]
7933 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
7936 reg_reloaded_insn[regno + k] = insn;
7937 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
7938 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
7939 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7942 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7947 /* Maybe the spill reg contains a copy of reload_in. Only do
7948 something if there will not be an output reload for
7949 the register being reloaded. */
7950 else if (rld[r].out_reg == 0
7952 && ((REG_P (rld[r].in)
7953 && !HARD_REGISTER_P (rld[r].in)
7954 && !REGNO_REG_SET_P (®_has_output_reload,
7956 || (REG_P (rld[r].in_reg)
7957 && !REGNO_REG_SET_P (®_has_output_reload,
7958 REGNO (rld[r].in_reg))))
7959 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
7962 enum machine_mode mode;
7965 reg = reload_reg_rtx_for_input[r];
7966 mode = GET_MODE (reg);
7967 regno = REGNO (reg);
7968 nregs = hard_regno_nregs[regno][mode];
7969 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
7970 rld[r].when_needed))
7977 if (REG_P (rld[r].in)
7978 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7980 else if (REG_P (rld[r].in_reg))
7983 in = XEXP (rld[r].in_reg, 0);
7984 in_regno = REGNO (in);
7986 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
7987 : hard_regno_nregs[in_regno][mode]);
7989 reg_last_reload_reg[in_regno] = reg;
7991 piecemeal = (HARD_REGISTER_NUM_P (in_regno)
7992 && nregs == in_nregs
7993 && inherit_piecemeal_p (regno, in_regno, mode));
7995 if (HARD_REGISTER_NUM_P (in_regno))
7996 for (k = 1; k < in_nregs; k++)
7997 reg_last_reload_reg[in_regno + k]
7998 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8000 /* Unless we inherited this reload, show we haven't
8001 recently done a store.
8002 Previous stores of inherited auto_inc expressions
8003 also have to be discarded. */
8004 if (! reload_inherited[r]
8005 || (rld[r].out && ! rld[r].out_reg))
8006 spill_reg_store[regno] = 0;
8008 for (k = 0; k < nregs; k++)
8010 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8011 reg_reloaded_contents[regno + k]
8012 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
8015 reg_reloaded_insn[regno + k] = insn;
8016 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8017 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8018 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8021 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8028 /* The following if-statement was #if 0'd in 1.34 (or before...).
8029 It's reenabled in 1.35 because supposedly nothing else
8030 deals with this problem. */
8032 /* If a register gets output-reloaded from a non-spill register,
8033 that invalidates any previous reloaded copy of it.
8034 But forget_old_reloads_1 won't get to see it, because
8035 it thinks only about the original insn. So invalidate it here.
8036 Also do the same thing for RELOAD_OTHER constraints where the
8037 output is discarded. */
8039 && ((rld[r].out != 0
8040 && (REG_P (rld[r].out)
8041 || (MEM_P (rld[r].out)
8042 && REG_P (rld[r].out_reg))))
8043 || (rld[r].out == 0 && rld[r].out_reg
8044 && REG_P (rld[r].out_reg))))
8046 rtx out = ((rld[r].out && REG_P (rld[r].out))
8047 ? rld[r].out : rld[r].out_reg);
8048 int out_regno = REGNO (out);
8049 enum machine_mode mode = GET_MODE (out);
8051 /* REG_RTX is now set or clobbered by the main instruction.
8052 As the comment above explains, forget_old_reloads_1 only
8053 sees the original instruction, and there is no guarantee
8054 that the original instruction also clobbered REG_RTX.
8055 For example, if find_reloads sees that the input side of
8056 a matched operand pair dies in this instruction, it may
8057 use the input register as the reload register.
8059 Calling forget_old_reloads_1 is a waste of effort if
8060 REG_RTX is also the output register.
8062 If we know that REG_RTX holds the value of a pseudo
8063 register, the code after the call will record that fact. */
8064 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8065 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8067 if (!HARD_REGISTER_NUM_P (out_regno))
8069 rtx src_reg, store_insn = NULL_RTX;
8071 reg_last_reload_reg[out_regno] = 0;
8073 /* If we can find a hard register that is stored, record
8074 the storing insn so that we may delete this insn with
8075 delete_output_reload. */
8076 src_reg = reload_reg_rtx_for_output[r];
8078 /* If this is an optional reload, try to find the source reg
8079 from an input reload. */
8082 rtx set = single_set (insn);
8083 if (set && SET_DEST (set) == rld[r].out)
8087 src_reg = SET_SRC (set);
8089 for (k = 0; k < n_reloads; k++)
8091 if (rld[k].in == src_reg)
8093 src_reg = reload_reg_rtx_for_input[k];
8100 store_insn = new_spill_reg_store[REGNO (src_reg)];
8101 if (src_reg && REG_P (src_reg)
8102 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8104 int src_regno, src_nregs, k;
8107 gcc_assert (GET_MODE (src_reg) == mode);
8108 src_regno = REGNO (src_reg);
8109 src_nregs = hard_regno_nregs[src_regno][mode];
8110 /* The place where to find a death note varies with
8111 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8112 necessarily checked exactly in the code that moves
8113 notes, so just check both locations. */
8114 note = find_regno_note (insn, REG_DEAD, src_regno);
8115 if (! note && store_insn)
8116 note = find_regno_note (store_insn, REG_DEAD, src_regno);
8117 for (k = 0; k < src_nregs; k++)
8119 spill_reg_store[src_regno + k] = store_insn;
8120 spill_reg_stored_to[src_regno + k] = out;
8121 reg_reloaded_contents[src_regno + k] = out_regno;
8122 reg_reloaded_insn[src_regno + k] = store_insn;
8123 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8124 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8125 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
8127 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8130 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8132 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8134 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8136 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8138 reg_last_reload_reg[out_regno] = src_reg;
8139 /* We have to set reg_has_output_reload here, or else
8140 forget_old_reloads_1 will clear reg_last_reload_reg
8142 SET_REGNO_REG_SET (®_has_output_reload,
8148 int k, out_nregs = hard_regno_nregs[out_regno][mode];
8150 for (k = 0; k < out_nregs; k++)
8151 reg_last_reload_reg[out_regno + k] = 0;
8155 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
8158 /* Go through the motions to emit INSN and test if it is strictly valid.
8159 Return the emitted insn if valid, else return NULL. */
8162 emit_insn_if_valid_for_reload (rtx insn)
8164 rtx last = get_last_insn ();
8167 insn = emit_insn (insn);
8168 code = recog_memoized (insn);
8172 extract_insn (insn);
8173 /* We want constrain operands to treat this insn strictly in its
8174 validity determination, i.e., the way it would after reload has
8176 if (constrain_operands (1))
8180 delete_insns_since (last);
8184 /* Emit code to perform a reload from IN (which may be a reload register) to
8185 OUT (which may also be a reload register). IN or OUT is from operand
8186 OPNUM with reload type TYPE.
8188 Returns first insn emitted. */
8191 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8193 rtx last = get_last_insn ();
8196 /* If IN is a paradoxical SUBREG, remove it and try to put the
8197 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8198 if (GET_CODE (in) == SUBREG
8199 && (GET_MODE_SIZE (GET_MODE (in))
8200 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
8201 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
8202 in = SUBREG_REG (in), out = tem;
8203 else if (GET_CODE (out) == SUBREG
8204 && (GET_MODE_SIZE (GET_MODE (out))
8205 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
8206 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
8207 out = SUBREG_REG (out), in = tem;
8209 /* How to do this reload can get quite tricky. Normally, we are being
8210 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8211 register that didn't get a hard register. In that case we can just
8212 call emit_move_insn.
8214 We can also be asked to reload a PLUS that adds a register or a MEM to
8215 another register, constant or MEM. This can occur during frame pointer
8216 elimination and while reloading addresses. This case is handled by
8217 trying to emit a single insn to perform the add. If it is not valid,
8218 we use a two insn sequence.
8220 Or we can be asked to reload an unary operand that was a fragment of
8221 an addressing mode, into a register. If it isn't recognized as-is,
8222 we try making the unop operand and the reload-register the same:
8223 (set reg:X (unop:X expr:Y))
8224 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8226 Finally, we could be called to handle an 'o' constraint by putting
8227 an address into a register. In that case, we first try to do this
8228 with a named pattern of "reload_load_address". If no such pattern
8229 exists, we just emit a SET insn and hope for the best (it will normally
8230 be valid on machines that use 'o').
8232 This entire process is made complex because reload will never
8233 process the insns we generate here and so we must ensure that
8234 they will fit their constraints and also by the fact that parts of
8235 IN might be being reloaded separately and replaced with spill registers.
8236 Because of this, we are, in some sense, just guessing the right approach
8237 here. The one listed above seems to work.
8239 ??? At some point, this whole thing needs to be rethought. */
8241 if (GET_CODE (in) == PLUS
8242 && (REG_P (XEXP (in, 0))
8243 || GET_CODE (XEXP (in, 0)) == SUBREG
8244 || MEM_P (XEXP (in, 0)))
8245 && (REG_P (XEXP (in, 1))
8246 || GET_CODE (XEXP (in, 1)) == SUBREG
8247 || CONSTANT_P (XEXP (in, 1))
8248 || MEM_P (XEXP (in, 1))))
8250 /* We need to compute the sum of a register or a MEM and another
8251 register, constant, or MEM, and put it into the reload
8252 register. The best possible way of doing this is if the machine
8253 has a three-operand ADD insn that accepts the required operands.
8255 The simplest approach is to try to generate such an insn and see if it
8256 is recognized and matches its constraints. If so, it can be used.
8258 It might be better not to actually emit the insn unless it is valid,
8259 but we need to pass the insn as an operand to `recog' and
8260 `extract_insn' and it is simpler to emit and then delete the insn if
8261 not valid than to dummy things up. */
8263 rtx op0, op1, tem, insn;
8266 op0 = find_replacement (&XEXP (in, 0));
8267 op1 = find_replacement (&XEXP (in, 1));
8269 /* Since constraint checking is strict, commutativity won't be
8270 checked, so we need to do that here to avoid spurious failure
8271 if the add instruction is two-address and the second operand
8272 of the add is the same as the reload reg, which is frequently
8273 the case. If the insn would be A = B + A, rearrange it so
8274 it will be A = A + B as constrain_operands expects. */
8276 if (REG_P (XEXP (in, 1))
8277 && REGNO (out) == REGNO (XEXP (in, 1)))
8278 tem = op0, op0 = op1, op1 = tem;
8280 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8281 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8283 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8287 /* If that failed, we must use a conservative two-insn sequence.
8289 Use a move to copy one operand into the reload register. Prefer
8290 to reload a constant, MEM or pseudo since the move patterns can
8291 handle an arbitrary operand. If OP1 is not a constant, MEM or
8292 pseudo and OP1 is not a valid operand for an add instruction, then
8295 After reloading one of the operands into the reload register, add
8296 the reload register to the output register.
8298 If there is another way to do this for a specific machine, a
8299 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8302 code = (int) optab_handler (add_optab, GET_MODE (out))->insn_code;
8304 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8306 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8307 || (code != CODE_FOR_nothing
8308 && ! ((*insn_data[code].operand[2].predicate)
8309 (op1, insn_data[code].operand[2].mode))))
8310 tem = op0, op0 = op1, op1 = tem;
8312 gen_reload (out, op0, opnum, type);
8314 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8315 This fixes a problem on the 32K where the stack pointer cannot
8316 be used as an operand of an add insn. */
8318 if (rtx_equal_p (op0, op1))
8321 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8324 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8325 set_unique_reg_note (insn, REG_EQUIV, in);
8329 /* If that failed, copy the address register to the reload register.
8330 Then add the constant to the reload register. */
8332 gcc_assert (!reg_overlap_mentioned_p (out, op0));
8333 gen_reload (out, op1, opnum, type);
8334 insn = emit_insn (gen_add2_insn (out, op0));
8335 set_unique_reg_note (insn, REG_EQUIV, in);
8338 #ifdef SECONDARY_MEMORY_NEEDED
8339 /* If we need a memory location to do the move, do it that way. */
8340 else if ((REG_P (in)
8341 || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))))
8342 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
8344 || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out))))
8345 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
8346 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
8347 REGNO_REG_CLASS (reg_or_subregno (out)),
8350 /* Get the memory to use and rewrite both registers to its mode. */
8351 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8353 if (GET_MODE (loc) != GET_MODE (out))
8354 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
8356 if (GET_MODE (loc) != GET_MODE (in))
8357 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
8359 gen_reload (loc, in, opnum, type);
8360 gen_reload (out, loc, opnum, type);
8363 else if (REG_P (out) && UNARY_P (in))
8370 op1 = find_replacement (&XEXP (in, 0));
8371 if (op1 != XEXP (in, 0))
8372 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8374 /* First, try a plain SET. */
8375 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8379 /* If that failed, move the inner operand to the reload
8380 register, and try the same unop with the inner expression
8381 replaced with the reload register. */
8383 if (GET_MODE (op1) != GET_MODE (out))
8384 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8388 gen_reload (out_moded, op1, opnum, type);
8391 = gen_rtx_SET (VOIDmode, out,
8392 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8394 insn = emit_insn_if_valid_for_reload (insn);
8397 set_unique_reg_note (insn, REG_EQUIV, in);
8401 fatal_insn ("Failure trying to reload:", set);
8403 /* If IN is a simple operand, use gen_move_insn. */
8404 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8406 tem = emit_insn (gen_move_insn (out, in));
8407 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8408 mark_jump_label (in, tem, 0);
8411 #ifdef HAVE_reload_load_address
8412 else if (HAVE_reload_load_address)
8413 emit_insn (gen_reload_load_address (out, in));
8416 /* Otherwise, just write (set OUT IN) and hope for the best. */
8418 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8420 /* Return the first insn emitted.
8421 We can not just return get_last_insn, because there may have
8422 been multiple instructions emitted. Also note that gen_move_insn may
8423 emit more than one insn itself, so we can not assume that there is one
8424 insn emitted per emit_insn_before call. */
8426 return last ? NEXT_INSN (last) : get_insns ();
8429 /* Delete a previously made output-reload whose result we now believe
8430 is not needed. First we double-check.
8432 INSN is the insn now being processed.
8433 LAST_RELOAD_REG is the hard register number for which we want to delete
8434 the last output reload.
8435 J is the reload-number that originally used REG. The caller has made
8436 certain that reload J doesn't use REG any longer for input.
8437 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8440 delete_output_reload (rtx insn, int j, int last_reload_reg, rtx new_reload_reg)
8442 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8443 rtx reg = spill_reg_stored_to[last_reload_reg];
8446 int n_inherited = 0;
8450 /* It is possible that this reload has been only used to set another reload
8451 we eliminated earlier and thus deleted this instruction too. */
8452 if (INSN_DELETED_P (output_reload_insn))
8455 /* Get the raw pseudo-register referred to. */
8457 while (GET_CODE (reg) == SUBREG)
8458 reg = SUBREG_REG (reg);
8459 substed = reg_equiv_memory_loc[REGNO (reg)];
8461 /* This is unsafe if the operand occurs more often in the current
8462 insn than it is inherited. */
8463 for (k = n_reloads - 1; k >= 0; k--)
8465 rtx reg2 = rld[k].in;
8468 if (MEM_P (reg2) || reload_override_in[k])
8469 reg2 = rld[k].in_reg;
8471 if (rld[k].out && ! rld[k].out_reg)
8472 reg2 = XEXP (rld[k].in_reg, 0);
8474 while (GET_CODE (reg2) == SUBREG)
8475 reg2 = SUBREG_REG (reg2);
8476 if (rtx_equal_p (reg2, reg))
8478 if (reload_inherited[k] || reload_override_in[k] || k == j)
8484 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8485 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8486 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8489 n_occurrences += count_occurrences (PATTERN (insn),
8490 eliminate_regs (substed, VOIDmode,
8492 for (i1 = reg_equiv_alt_mem_list[REGNO (reg)]; i1; i1 = XEXP (i1, 1))
8494 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8495 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8497 if (n_occurrences > n_inherited)
8500 /* If the pseudo-reg we are reloading is no longer referenced
8501 anywhere between the store into it and here,
8502 and we're within the same basic block, then the value can only
8503 pass through the reload reg and end up here.
8504 Otherwise, give up--return. */
8505 for (i1 = NEXT_INSN (output_reload_insn);
8506 i1 != insn; i1 = NEXT_INSN (i1))
8508 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8510 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8511 && reg_mentioned_p (reg, PATTERN (i1)))
8513 /* If this is USE in front of INSN, we only have to check that
8514 there are no more references than accounted for by inheritance. */
8515 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8517 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8518 i1 = NEXT_INSN (i1);
8520 if (n_occurrences <= n_inherited && i1 == insn)
8526 /* We will be deleting the insn. Remove the spill reg information. */
8527 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8529 spill_reg_store[last_reload_reg + k] = 0;
8530 spill_reg_stored_to[last_reload_reg + k] = 0;
8533 /* The caller has already checked that REG dies or is set in INSN.
8534 It has also checked that we are optimizing, and thus some
8535 inaccuracies in the debugging information are acceptable.
8536 So we could just delete output_reload_insn. But in some cases
8537 we can improve the debugging information without sacrificing
8538 optimization - maybe even improving the code: See if the pseudo
8539 reg has been completely replaced with reload regs. If so, delete
8540 the store insn and forget we had a stack slot for the pseudo. */
8541 if (rld[j].out != rld[j].in
8542 && REG_N_DEATHS (REGNO (reg)) == 1
8543 && REG_N_SETS (REGNO (reg)) == 1
8544 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8545 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8549 /* We know that it was used only between here and the beginning of
8550 the current basic block. (We also know that the last use before
8551 INSN was the output reload we are thinking of deleting, but never
8552 mind that.) Search that range; see if any ref remains. */
8553 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8555 rtx set = single_set (i2);
8557 /* Uses which just store in the pseudo don't count,
8558 since if they are the only uses, they are dead. */
8559 if (set != 0 && SET_DEST (set) == reg)
8564 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8565 && reg_mentioned_p (reg, PATTERN (i2)))
8567 /* Some other ref remains; just delete the output reload we
8569 delete_address_reloads (output_reload_insn, insn);
8570 delete_insn (output_reload_insn);
8575 /* Delete the now-dead stores into this pseudo. Note that this
8576 loop also takes care of deleting output_reload_insn. */
8577 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8579 rtx set = single_set (i2);
8581 if (set != 0 && SET_DEST (set) == reg)
8583 delete_address_reloads (i2, insn);
8591 /* For the debugging info, say the pseudo lives in this reload reg. */
8592 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8593 if (ira_conflicts_p)
8594 /* Inform IRA about the change. */
8595 ira_mark_allocation_change (REGNO (reg));
8596 alter_reg (REGNO (reg), -1, false);
8600 delete_address_reloads (output_reload_insn, insn);
8601 delete_insn (output_reload_insn);
8605 /* We are going to delete DEAD_INSN. Recursively delete loads of
8606 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8607 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8609 delete_address_reloads (rtx dead_insn, rtx current_insn)
8611 rtx set = single_set (dead_insn);
8612 rtx set2, dst, prev, next;
8615 rtx dst = SET_DEST (set);
8617 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8619 /* If we deleted the store from a reloaded post_{in,de}c expression,
8620 we can delete the matching adds. */
8621 prev = PREV_INSN (dead_insn);
8622 next = NEXT_INSN (dead_insn);
8623 if (! prev || ! next)
8625 set = single_set (next);
8626 set2 = single_set (prev);
8628 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8629 || !CONST_INT_P (XEXP (SET_SRC (set), 1))
8630 || !CONST_INT_P (XEXP (SET_SRC (set2), 1)))
8632 dst = SET_DEST (set);
8633 if (! rtx_equal_p (dst, SET_DEST (set2))
8634 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8635 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8636 || (INTVAL (XEXP (SET_SRC (set), 1))
8637 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8639 delete_related_insns (prev);
8640 delete_related_insns (next);
8643 /* Subfunction of delete_address_reloads: process registers found in X. */
8645 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8647 rtx prev, set, dst, i2;
8649 enum rtx_code code = GET_CODE (x);
8653 const char *fmt = GET_RTX_FORMAT (code);
8654 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8657 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8658 else if (fmt[i] == 'E')
8660 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8661 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8668 if (spill_reg_order[REGNO (x)] < 0)
8671 /* Scan backwards for the insn that sets x. This might be a way back due
8673 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8675 code = GET_CODE (prev);
8676 if (code == CODE_LABEL || code == JUMP_INSN)
8680 if (reg_set_p (x, PATTERN (prev)))
8682 if (reg_referenced_p (x, PATTERN (prev)))
8685 if (! prev || INSN_UID (prev) < reload_first_uid)
8687 /* Check that PREV only sets the reload register. */
8688 set = single_set (prev);
8691 dst = SET_DEST (set);
8693 || ! rtx_equal_p (dst, x))
8695 if (! reg_set_p (dst, PATTERN (dead_insn)))
8697 /* Check if DST was used in a later insn -
8698 it might have been inherited. */
8699 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8705 if (reg_referenced_p (dst, PATTERN (i2)))
8707 /* If there is a reference to the register in the current insn,
8708 it might be loaded in a non-inherited reload. If no other
8709 reload uses it, that means the register is set before
8711 if (i2 == current_insn)
8713 for (j = n_reloads - 1; j >= 0; j--)
8714 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8715 || reload_override_in[j] == dst)
8717 for (j = n_reloads - 1; j >= 0; j--)
8718 if (rld[j].in && rld[j].reg_rtx == dst)
8727 /* If DST is still live at CURRENT_INSN, check if it is used for
8728 any reload. Note that even if CURRENT_INSN sets DST, we still
8729 have to check the reloads. */
8730 if (i2 == current_insn)
8732 for (j = n_reloads - 1; j >= 0; j--)
8733 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8734 || reload_override_in[j] == dst)
8736 /* ??? We can't finish the loop here, because dst might be
8737 allocated to a pseudo in this block if no reload in this
8738 block needs any of the classes containing DST - see
8739 spill_hard_reg. There is no easy way to tell this, so we
8740 have to scan till the end of the basic block. */
8742 if (reg_set_p (dst, PATTERN (i2)))
8746 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8747 reg_reloaded_contents[REGNO (dst)] = -1;
8751 /* Output reload-insns to reload VALUE into RELOADREG.
8752 VALUE is an autoincrement or autodecrement RTX whose operand
8753 is a register or memory location;
8754 so reloading involves incrementing that location.
8755 IN is either identical to VALUE, or some cheaper place to reload from.
8757 INC_AMOUNT is the number to increment or decrement by (always positive).
8758 This cannot be deduced from VALUE.
8760 Return the instruction that stores into RELOADREG. */
8763 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8765 /* REG or MEM to be copied and incremented. */
8766 rtx incloc = find_replacement (&XEXP (value, 0));
8767 /* Nonzero if increment after copying. */
8768 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8769 || GET_CODE (value) == POST_MODIFY);
8775 rtx real_in = in == value ? incloc : in;
8777 /* No hard register is equivalent to this register after
8778 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8779 we could inc/dec that register as well (maybe even using it for
8780 the source), but I'm not sure it's worth worrying about. */
8782 reg_last_reload_reg[REGNO (incloc)] = 0;
8784 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8786 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8787 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
8791 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8792 inc_amount = -inc_amount;
8794 inc = GEN_INT (inc_amount);
8797 /* If this is post-increment, first copy the location to the reload reg. */
8798 if (post && real_in != reloadreg)
8799 emit_insn (gen_move_insn (reloadreg, real_in));
8803 /* See if we can directly increment INCLOC. Use a method similar to
8804 that in gen_reload. */
8806 last = get_last_insn ();
8807 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8808 gen_rtx_PLUS (GET_MODE (incloc),
8811 code = recog_memoized (add_insn);
8814 extract_insn (add_insn);
8815 if (constrain_operands (1))
8817 /* If this is a pre-increment and we have incremented the value
8818 where it lives, copy the incremented value to RELOADREG to
8819 be used as an address. */
8822 emit_insn (gen_move_insn (reloadreg, incloc));
8827 delete_insns_since (last);
8830 /* If couldn't do the increment directly, must increment in RELOADREG.
8831 The way we do this depends on whether this is pre- or post-increment.
8832 For pre-increment, copy INCLOC to the reload register, increment it
8833 there, then save back. */
8837 if (in != reloadreg)
8838 emit_insn (gen_move_insn (reloadreg, real_in));
8839 emit_insn (gen_add2_insn (reloadreg, inc));
8840 store = emit_insn (gen_move_insn (incloc, reloadreg));
8845 Because this might be a jump insn or a compare, and because RELOADREG
8846 may not be available after the insn in an input reload, we must do
8847 the incrementation before the insn being reloaded for.
8849 We have already copied IN to RELOADREG. Increment the copy in
8850 RELOADREG, save that back, then decrement RELOADREG so it has
8851 the original value. */
8853 emit_insn (gen_add2_insn (reloadreg, inc));
8854 store = emit_insn (gen_move_insn (incloc, reloadreg));
8855 if (CONST_INT_P (inc))
8856 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
8858 emit_insn (gen_sub2_insn (reloadreg, inc));
8866 add_auto_inc_notes (rtx insn, rtx x)
8868 enum rtx_code code = GET_CODE (x);
8872 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8874 add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
8878 /* Scan all the operand sub-expressions. */
8879 fmt = GET_RTX_FORMAT (code);
8880 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8883 add_auto_inc_notes (insn, XEXP (x, i));
8884 else if (fmt[i] == 'E')
8885 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8886 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8891 /* This is used by reload pass, that does emit some instructions after
8892 abnormal calls moving basic block end, but in fact it wants to emit
8893 them on the edge. Looks for abnormal call edges, find backward the
8894 proper call and fix the damage.
8896 Similar handle instructions throwing exceptions internally. */
8898 fixup_abnormal_edges (void)
8900 bool inserted = false;
8908 /* Look for cases we are interested in - calls or instructions causing
8910 FOR_EACH_EDGE (e, ei, bb->succs)
8912 if (e->flags & EDGE_ABNORMAL_CALL)
8914 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8915 == (EDGE_ABNORMAL | EDGE_EH))
8918 if (e && !CALL_P (BB_END (bb))
8919 && !can_throw_internal (BB_END (bb)))
8923 /* Get past the new insns generated. Allow notes, as the insns
8924 may be already deleted. */
8926 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8927 && !can_throw_internal (insn)
8928 && insn != BB_HEAD (bb))
8929 insn = PREV_INSN (insn);
8931 if (CALL_P (insn) || can_throw_internal (insn))
8935 stop = NEXT_INSN (BB_END (bb));
8937 insn = NEXT_INSN (insn);
8939 FOR_EACH_EDGE (e, ei, bb->succs)
8940 if (e->flags & EDGE_FALLTHRU)
8943 while (insn && insn != stop)
8945 next = NEXT_INSN (insn);
8950 /* Sometimes there's still the return value USE.
8951 If it's placed after a trapping call (i.e. that
8952 call is the last insn anyway), we have no fallthru
8953 edge. Simply delete this use and don't try to insert
8954 on the non-existent edge. */
8955 if (GET_CODE (PATTERN (insn)) != USE)
8957 /* We're not deleting it, we're moving it. */
8958 INSN_DELETED_P (insn) = 0;
8959 PREV_INSN (insn) = NULL_RTX;
8960 NEXT_INSN (insn) = NULL_RTX;
8962 insert_insn_on_edge (insn, e);
8966 else if (!BARRIER_P (insn))
8967 set_block_for_insn (insn, NULL);
8972 /* It may be that we don't find any such trapping insn. In this
8973 case we discovered quite late that the insn that had been
8974 marked as can_throw_internal in fact couldn't trap at all.
8975 So we should in fact delete the EH edges out of the block. */
8977 purge_dead_edges (bb);
8981 /* We've possibly turned single trapping insn into multiple ones. */
8982 if (flag_non_call_exceptions)
8985 blocks = sbitmap_alloc (last_basic_block);
8986 sbitmap_ones (blocks);
8987 find_many_sub_basic_blocks (blocks);
8988 sbitmap_free (blocks);
8992 commit_edge_insertions ();
8994 #ifdef ENABLE_CHECKING
8995 /* Verify that we didn't turn one trapping insn into many, and that
8996 we found and corrected all of the problems wrt fixups on the
8998 verify_flow_info ();
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