1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "addresses.h"
39 #include "basic-block.h"
51 /* This file contains the reload pass of the compiler, which is
52 run after register allocation has been done. It checks that
53 each insn is valid (operands required to be in registers really
54 are in registers of the proper class) and fixes up invalid ones
55 by copying values temporarily into registers for the insns
58 The results of register allocation are described by the vector
59 reg_renumber; the insns still contain pseudo regs, but reg_renumber
60 can be used to find which hard reg, if any, a pseudo reg is in.
62 The technique we always use is to free up a few hard regs that are
63 called ``reload regs'', and for each place where a pseudo reg
64 must be in a hard reg, copy it temporarily into one of the reload regs.
66 Reload regs are allocated locally for every instruction that needs
67 reloads. When there are pseudos which are allocated to a register that
68 has been chosen as a reload reg, such pseudos must be ``spilled''.
69 This means that they go to other hard regs, or to stack slots if no other
70 available hard regs can be found. Spilling can invalidate more
71 insns, requiring additional need for reloads, so we must keep checking
72 until the process stabilizes.
74 For machines with different classes of registers, we must keep track
75 of the register class needed for each reload, and make sure that
76 we allocate enough reload registers of each class.
78 The file reload.c contains the code that checks one insn for
79 validity and reports the reloads that it needs. This file
80 is in charge of scanning the entire rtl code, accumulating the
81 reload needs, spilling, assigning reload registers to use for
82 fixing up each insn, and generating the new insns to copy values
83 into the reload registers. */
85 /* During reload_as_needed, element N contains a REG rtx for the hard reg
86 into which reg N has been reloaded (perhaps for a previous insn). */
87 static rtx *reg_last_reload_reg;
89 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
90 for an output reload that stores into reg N. */
91 static regset_head reg_has_output_reload;
93 /* Indicates which hard regs are reload-registers for an output reload
94 in the current insn. */
95 static HARD_REG_SET reg_is_output_reload;
97 /* Element N is the constant value to which pseudo reg N is equivalent,
98 or zero if pseudo reg N is not equivalent to a constant.
99 find_reloads looks at this in order to replace pseudo reg N
100 with the constant it stands for. */
101 rtx *reg_equiv_constant;
103 /* Element N is an invariant value to which pseudo reg N is equivalent.
104 eliminate_regs_in_insn uses this to replace pseudos in particular
106 rtx *reg_equiv_invariant;
108 /* Element N is a memory location to which pseudo reg N is equivalent,
109 prior to any register elimination (such as frame pointer to stack
110 pointer). Depending on whether or not it is a valid address, this value
111 is transferred to either reg_equiv_address or reg_equiv_mem. */
112 rtx *reg_equiv_memory_loc;
114 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
115 collector can keep track of what is inside. */
116 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
118 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
119 This is used when the address is not valid as a memory address
120 (because its displacement is too big for the machine.) */
121 rtx *reg_equiv_address;
123 /* Element N is the memory slot to which pseudo reg N is equivalent,
124 or zero if pseudo reg N is not equivalent to a memory slot. */
127 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
128 alternate representations of the location of pseudo reg N. */
129 rtx *reg_equiv_alt_mem_list;
131 /* Widest width in which each pseudo reg is referred to (via subreg). */
132 static unsigned int *reg_max_ref_width;
134 /* Element N is the list of insns that initialized reg N from its equivalent
135 constant or memory slot. */
137 int reg_equiv_init_size;
139 /* Vector to remember old contents of reg_renumber before spilling. */
140 static short *reg_old_renumber;
142 /* During reload_as_needed, element N contains the last pseudo regno reloaded
143 into hard register N. If that pseudo reg occupied more than one register,
144 reg_reloaded_contents points to that pseudo for each spill register in
145 use; all of these must remain set for an inheritance to occur. */
146 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
148 /* During reload_as_needed, element N contains the insn for which
149 hard register N was last used. Its contents are significant only
150 when reg_reloaded_valid is set for this register. */
151 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
153 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
154 static HARD_REG_SET reg_reloaded_valid;
155 /* Indicate if the register was dead at the end of the reload.
156 This is only valid if reg_reloaded_contents is set and valid. */
157 static HARD_REG_SET reg_reloaded_dead;
159 /* Indicate whether the register's current value is one that is not
160 safe to retain across a call, even for registers that are normally
161 call-saved. This is only meaningful for members of reg_reloaded_valid. */
162 static HARD_REG_SET reg_reloaded_call_part_clobbered;
164 /* Number of spill-regs so far; number of valid elements of spill_regs. */
167 /* In parallel with spill_regs, contains REG rtx's for those regs.
168 Holds the last rtx used for any given reg, or 0 if it has never
169 been used for spilling yet. This rtx is reused, provided it has
171 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
173 /* In parallel with spill_regs, contains nonzero for a spill reg
174 that was stored after the last time it was used.
175 The precise value is the insn generated to do the store. */
176 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
178 /* This is the register that was stored with spill_reg_store. This is a
179 copy of reload_out / reload_out_reg when the value was stored; if
180 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
181 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
183 /* This table is the inverse mapping of spill_regs:
184 indexed by hard reg number,
185 it contains the position of that reg in spill_regs,
186 or -1 for something that is not in spill_regs.
188 ?!? This is no longer accurate. */
189 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
191 /* This reg set indicates registers that can't be used as spill registers for
192 the currently processed insn. These are the hard registers which are live
193 during the insn, but not allocated to pseudos, as well as fixed
195 static HARD_REG_SET bad_spill_regs;
197 /* These are the hard registers that can't be used as spill register for any
198 insn. This includes registers used for user variables and registers that
199 we can't eliminate. A register that appears in this set also can't be used
200 to retry register allocation. */
201 static HARD_REG_SET bad_spill_regs_global;
203 /* Describes order of use of registers for reloading
204 of spilled pseudo-registers. `n_spills' is the number of
205 elements that are actually valid; new ones are added at the end.
207 Both spill_regs and spill_reg_order are used on two occasions:
208 once during find_reload_regs, where they keep track of the spill registers
209 for a single insn, but also during reload_as_needed where they show all
210 the registers ever used by reload. For the latter case, the information
211 is calculated during finish_spills. */
212 static short spill_regs[FIRST_PSEUDO_REGISTER];
214 /* This vector of reg sets indicates, for each pseudo, which hard registers
215 may not be used for retrying global allocation because the register was
216 formerly spilled from one of them. If we allowed reallocating a pseudo to
217 a register that it was already allocated to, reload might not
219 static HARD_REG_SET *pseudo_previous_regs;
221 /* This vector of reg sets indicates, for each pseudo, which hard
222 registers may not be used for retrying global allocation because they
223 are used as spill registers during one of the insns in which the
225 static HARD_REG_SET *pseudo_forbidden_regs;
227 /* All hard regs that have been used as spill registers for any insn are
228 marked in this set. */
229 static HARD_REG_SET used_spill_regs;
231 /* Index of last register assigned as a spill register. We allocate in
232 a round-robin fashion. */
233 static int last_spill_reg;
235 /* Nonzero if indirect addressing is supported on the machine; this means
236 that spilling (REG n) does not require reloading it into a register in
237 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
238 value indicates the level of indirect addressing supported, e.g., two
239 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
241 static char spill_indirect_levels;
243 /* Nonzero if indirect addressing is supported when the innermost MEM is
244 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
245 which these are valid is the same as spill_indirect_levels, above. */
246 char indirect_symref_ok;
248 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
249 char double_reg_address_ok;
251 /* Record the stack slot for each spilled hard register. */
252 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
254 /* Width allocated so far for that stack slot. */
255 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
257 /* Record which pseudos needed to be spilled. */
258 static regset_head spilled_pseudos;
260 /* Used for communication between order_regs_for_reload and count_pseudo.
261 Used to avoid counting one pseudo twice. */
262 static regset_head pseudos_counted;
264 /* First uid used by insns created by reload in this function.
265 Used in find_equiv_reg. */
266 int reload_first_uid;
268 /* Flag set by local-alloc or global-alloc if anything is live in
269 a call-clobbered reg across calls. */
270 int caller_save_needed;
272 /* Set to 1 while reload_as_needed is operating.
273 Required by some machines to handle any generated moves differently. */
274 int reload_in_progress = 0;
276 /* These arrays record the insn_code of insns that may be needed to
277 perform input and output reloads of special objects. They provide a
278 place to pass a scratch register. */
279 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
280 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
282 /* This obstack is used for allocation of rtl during register elimination.
283 The allocated storage can be freed once find_reloads has processed the
285 static struct obstack reload_obstack;
287 /* Points to the beginning of the reload_obstack. All insn_chain structures
288 are allocated first. */
289 static char *reload_startobj;
291 /* The point after all insn_chain structures. Used to quickly deallocate
292 memory allocated in copy_reloads during calculate_needs_all_insns. */
293 static char *reload_firstobj;
295 /* This points before all local rtl generated by register elimination.
296 Used to quickly free all memory after processing one insn. */
297 static char *reload_insn_firstobj;
299 /* List of insn_chain instructions, one for every insn that reload needs to
301 struct insn_chain *reload_insn_chain;
303 /* List of all insns needing reloads. */
304 static struct insn_chain *insns_need_reload;
306 /* This structure is used to record information about register eliminations.
307 Each array entry describes one possible way of eliminating a register
308 in favor of another. If there is more than one way of eliminating a
309 particular register, the most preferred should be specified first. */
313 int from; /* Register number to be eliminated. */
314 int to; /* Register number used as replacement. */
315 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
316 int can_eliminate; /* Nonzero if this elimination can be done. */
317 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
318 insns made by reload. */
319 HOST_WIDE_INT offset; /* Current offset between the two regs. */
320 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
321 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
322 rtx from_rtx; /* REG rtx for the register to be eliminated.
323 We cannot simply compare the number since
324 we might then spuriously replace a hard
325 register corresponding to a pseudo
326 assigned to the reg to be eliminated. */
327 rtx to_rtx; /* REG rtx for the replacement. */
330 static struct elim_table *reg_eliminate = 0;
332 /* This is an intermediate structure to initialize the table. It has
333 exactly the members provided by ELIMINABLE_REGS. */
334 static const struct elim_table_1
338 } reg_eliminate_1[] =
340 /* If a set of eliminable registers was specified, define the table from it.
341 Otherwise, default to the normal case of the frame pointer being
342 replaced by the stack pointer. */
344 #ifdef ELIMINABLE_REGS
347 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
350 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
352 /* Record the number of pending eliminations that have an offset not equal
353 to their initial offset. If nonzero, we use a new copy of each
354 replacement result in any insns encountered. */
355 int num_not_at_initial_offset;
357 /* Count the number of registers that we may be able to eliminate. */
358 static int num_eliminable;
359 /* And the number of registers that are equivalent to a constant that
360 can be eliminated to frame_pointer / arg_pointer + constant. */
361 static int num_eliminable_invariants;
363 /* For each label, we record the offset of each elimination. If we reach
364 a label by more than one path and an offset differs, we cannot do the
365 elimination. This information is indexed by the difference of the
366 number of the label and the first label number. We can't offset the
367 pointer itself as this can cause problems on machines with segmented
368 memory. The first table is an array of flags that records whether we
369 have yet encountered a label and the second table is an array of arrays,
370 one entry in the latter array for each elimination. */
372 static int first_label_num;
373 static char *offsets_known_at;
374 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
376 /* Number of labels in the current function. */
378 static int num_labels;
380 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
381 static void maybe_fix_stack_asms (void);
382 static void copy_reloads (struct insn_chain *);
383 static void calculate_needs_all_insns (int);
384 static int find_reg (struct insn_chain *, int);
385 static void find_reload_regs (struct insn_chain *);
386 static void select_reload_regs (void);
387 static void delete_caller_save_insns (void);
389 static void spill_failure (rtx, enum reg_class);
390 static void count_spilled_pseudo (int, int, int);
391 static void delete_dead_insn (rtx);
392 static void alter_reg (int, int);
393 static void set_label_offsets (rtx, rtx, int);
394 static void check_eliminable_occurrences (rtx);
395 static void elimination_effects (rtx, enum machine_mode);
396 static int eliminate_regs_in_insn (rtx, int);
397 static void update_eliminable_offsets (void);
398 static void mark_not_eliminable (rtx, const_rtx, void *);
399 static void set_initial_elim_offsets (void);
400 static bool verify_initial_elim_offsets (void);
401 static void set_initial_label_offsets (void);
402 static void set_offsets_for_label (rtx);
403 static void init_elim_table (void);
404 static void update_eliminables (HARD_REG_SET *);
405 static void spill_hard_reg (unsigned int, int);
406 static int finish_spills (int);
407 static void scan_paradoxical_subregs (rtx);
408 static void count_pseudo (int);
409 static void order_regs_for_reload (struct insn_chain *);
410 static void reload_as_needed (int);
411 static void forget_old_reloads_1 (rtx, const_rtx, void *);
412 static void forget_marked_reloads (regset);
413 static int reload_reg_class_lower (const void *, const void *);
414 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
416 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
418 static int reload_reg_free_p (unsigned int, int, enum reload_type);
419 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
421 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
423 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
424 static int allocate_reload_reg (struct insn_chain *, int, int);
425 static int conflicts_with_override (rtx);
426 static void failed_reload (rtx, int);
427 static int set_reload_reg (int, int);
428 static void choose_reload_regs_init (struct insn_chain *, rtx *);
429 static void choose_reload_regs (struct insn_chain *);
430 static void merge_assigned_reloads (rtx);
431 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
433 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
435 static void do_input_reload (struct insn_chain *, struct reload *, int);
436 static void do_output_reload (struct insn_chain *, struct reload *, int);
437 static void emit_reload_insns (struct insn_chain *);
438 static void delete_output_reload (rtx, int, int, rtx);
439 static void delete_address_reloads (rtx, rtx);
440 static void delete_address_reloads_1 (rtx, rtx, rtx);
441 static rtx inc_for_reload (rtx, rtx, rtx, int);
443 static void add_auto_inc_notes (rtx, rtx);
445 static void copy_eh_notes (rtx, rtx);
446 static int reloads_conflict (int, int);
447 static rtx gen_reload (rtx, rtx, int, enum reload_type);
448 static rtx emit_insn_if_valid_for_reload (rtx);
450 /* Initialize the reload pass. This is called at the beginning of compilation
451 and may be called again if the target is reinitialized. */
458 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
459 Set spill_indirect_levels to the number of levels such addressing is
460 permitted, zero if it is not permitted at all. */
463 = gen_rtx_MEM (Pmode,
466 LAST_VIRTUAL_REGISTER + 1),
468 spill_indirect_levels = 0;
470 while (memory_address_p (QImode, tem))
472 spill_indirect_levels++;
473 tem = gen_rtx_MEM (Pmode, tem);
476 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
478 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
479 indirect_symref_ok = memory_address_p (QImode, tem);
481 /* See if reg+reg is a valid (and offsettable) address. */
483 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
485 tem = gen_rtx_PLUS (Pmode,
486 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
487 gen_rtx_REG (Pmode, i));
489 /* This way, we make sure that reg+reg is an offsettable address. */
490 tem = plus_constant (tem, 4);
492 if (memory_address_p (QImode, tem))
494 double_reg_address_ok = 1;
499 /* Initialize obstack for our rtl allocation. */
500 gcc_obstack_init (&reload_obstack);
501 reload_startobj = obstack_alloc (&reload_obstack, 0);
503 INIT_REG_SET (&spilled_pseudos);
504 INIT_REG_SET (&pseudos_counted);
507 /* List of insn chains that are currently unused. */
508 static struct insn_chain *unused_insn_chains = 0;
510 /* Allocate an empty insn_chain structure. */
512 new_insn_chain (void)
514 struct insn_chain *c;
516 if (unused_insn_chains == 0)
518 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
519 INIT_REG_SET (&c->live_throughout);
520 INIT_REG_SET (&c->dead_or_set);
524 c = unused_insn_chains;
525 unused_insn_chains = c->next;
527 c->is_caller_save_insn = 0;
528 c->need_operand_change = 0;
534 /* Small utility function to set all regs in hard reg set TO which are
535 allocated to pseudos in regset FROM. */
538 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
541 reg_set_iterator rsi;
543 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
545 int r = reg_renumber[regno];
549 /* reload_combine uses the information from
550 DF_LIVE_IN (BASIC_BLOCK), which might still
551 contain registers that have not actually been allocated
552 since they have an equivalence. */
553 gcc_assert (reload_completed);
556 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
560 /* Replace all pseudos found in LOC with their corresponding
564 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
577 unsigned int regno = REGNO (x);
579 if (regno < FIRST_PSEUDO_REGISTER)
582 x = eliminate_regs (x, mem_mode, usage);
586 replace_pseudos_in (loc, mem_mode, usage);
590 if (reg_equiv_constant[regno])
591 *loc = reg_equiv_constant[regno];
592 else if (reg_equiv_mem[regno])
593 *loc = reg_equiv_mem[regno];
594 else if (reg_equiv_address[regno])
595 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
598 gcc_assert (!REG_P (regno_reg_rtx[regno])
599 || REGNO (regno_reg_rtx[regno]) != regno);
600 *loc = regno_reg_rtx[regno];
605 else if (code == MEM)
607 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
611 /* Process each of our operands recursively. */
612 fmt = GET_RTX_FORMAT (code);
613 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
615 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
616 else if (*fmt == 'E')
617 for (j = 0; j < XVECLEN (x, i); j++)
618 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
621 /* Determine if the current function has an exception receiver block
622 that reaches the exit block via non-exceptional edges */
625 has_nonexceptional_receiver (void)
629 basic_block *tos, *worklist, bb;
631 /* If we're not optimizing, then just err on the safe side. */
635 /* First determine which blocks can reach exit via normal paths. */
636 tos = worklist = xmalloc (sizeof (basic_block) * (n_basic_blocks + 1));
639 bb->flags &= ~BB_REACHABLE;
641 /* Place the exit block on our worklist. */
642 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
643 *tos++ = EXIT_BLOCK_PTR;
645 /* Iterate: find everything reachable from what we've already seen. */
646 while (tos != worklist)
650 FOR_EACH_EDGE (e, ei, bb->preds)
651 if (!(e->flags & EDGE_ABNORMAL))
653 basic_block src = e->src;
655 if (!(src->flags & BB_REACHABLE))
657 src->flags |= BB_REACHABLE;
664 /* Now see if there's a reachable block with an exceptional incoming
667 if (bb->flags & BB_REACHABLE)
668 FOR_EACH_EDGE (e, ei, bb->preds)
669 if (e->flags & EDGE_ABNORMAL)
672 /* No exceptional block reached exit unexceptionally. */
677 /* Global variables used by reload and its subroutines. */
679 /* Set during calculate_needs if an insn needs register elimination. */
680 static int something_needs_elimination;
681 /* Set during calculate_needs if an insn needs an operand changed. */
682 static int something_needs_operands_changed;
684 /* Nonzero means we couldn't get enough spill regs. */
687 /* Main entry point for the reload pass.
689 FIRST is the first insn of the function being compiled.
691 GLOBAL nonzero means we were called from global_alloc
692 and should attempt to reallocate any pseudoregs that we
693 displace from hard regs we will use for reloads.
694 If GLOBAL is zero, we do not have enough information to do that,
695 so any pseudo reg that is spilled must go to the stack.
697 Return value is nonzero if reload failed
698 and we must not do any more for this function. */
701 reload (rtx first, int global)
705 struct elim_table *ep;
708 /* Make sure even insns with volatile mem refs are recognizable. */
713 reload_firstobj = obstack_alloc (&reload_obstack, 0);
715 /* Make sure that the last insn in the chain
716 is not something that needs reloading. */
717 emit_note (NOTE_INSN_DELETED);
719 /* Enable find_equiv_reg to distinguish insns made by reload. */
720 reload_first_uid = get_max_uid ();
722 #ifdef SECONDARY_MEMORY_NEEDED
723 /* Initialize the secondary memory table. */
724 clear_secondary_mem ();
727 /* We don't have a stack slot for any spill reg yet. */
728 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
729 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
731 /* Initialize the save area information for caller-save, in case some
735 /* Compute which hard registers are now in use
736 as homes for pseudo registers.
737 This is done here rather than (eg) in global_alloc
738 because this point is reached even if not optimizing. */
739 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
742 /* A function that has a nonlocal label that can reach the exit
743 block via non-exceptional paths must save all call-saved
745 if (cfun->has_nonlocal_label
746 && has_nonexceptional_receiver ())
747 crtl->saves_all_registers = 1;
749 if (crtl->saves_all_registers)
750 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
751 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
752 df_set_regs_ever_live (i, true);
754 /* Find all the pseudo registers that didn't get hard regs
755 but do have known equivalent constants or memory slots.
756 These include parameters (known equivalent to parameter slots)
757 and cse'd or loop-moved constant memory addresses.
759 Record constant equivalents in reg_equiv_constant
760 so they will be substituted by find_reloads.
761 Record memory equivalents in reg_mem_equiv so they can
762 be substituted eventually by altering the REG-rtx's. */
764 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
765 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
766 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
767 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
768 reg_equiv_address = XCNEWVEC (rtx, max_regno);
769 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
770 reg_old_renumber = XCNEWVEC (short, max_regno);
771 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
772 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
773 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
775 CLEAR_HARD_REG_SET (bad_spill_regs_global);
777 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
778 to. Also find all paradoxical subregs and find largest such for
781 num_eliminable_invariants = 0;
782 for (insn = first; insn; insn = NEXT_INSN (insn))
784 rtx set = single_set (insn);
786 /* We may introduce USEs that we want to remove at the end, so
787 we'll mark them with QImode. Make sure there are no
788 previously-marked insns left by say regmove. */
789 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
790 && GET_MODE (insn) != VOIDmode)
791 PUT_MODE (insn, VOIDmode);
794 scan_paradoxical_subregs (PATTERN (insn));
796 if (set != 0 && REG_P (SET_DEST (set)))
798 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
804 i = REGNO (SET_DEST (set));
807 if (i <= LAST_VIRTUAL_REGISTER)
810 if (! function_invariant_p (x)
812 /* A function invariant is often CONSTANT_P but may
813 include a register. We promise to only pass
814 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
816 && LEGITIMATE_PIC_OPERAND_P (x)))
818 /* It can happen that a REG_EQUIV note contains a MEM
819 that is not a legitimate memory operand. As later
820 stages of reload assume that all addresses found
821 in the reg_equiv_* arrays were originally legitimate,
822 we ignore such REG_EQUIV notes. */
823 if (memory_operand (x, VOIDmode))
825 /* Always unshare the equivalence, so we can
826 substitute into this insn without touching the
828 reg_equiv_memory_loc[i] = copy_rtx (x);
830 else if (function_invariant_p (x))
832 if (GET_CODE (x) == PLUS)
834 /* This is PLUS of frame pointer and a constant,
835 and might be shared. Unshare it. */
836 reg_equiv_invariant[i] = copy_rtx (x);
837 num_eliminable_invariants++;
839 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
841 reg_equiv_invariant[i] = x;
842 num_eliminable_invariants++;
844 else if (LEGITIMATE_CONSTANT_P (x))
845 reg_equiv_constant[i] = x;
848 reg_equiv_memory_loc[i]
849 = force_const_mem (GET_MODE (SET_DEST (set)), x);
850 if (! reg_equiv_memory_loc[i])
851 reg_equiv_init[i] = NULL_RTX;
856 reg_equiv_init[i] = NULL_RTX;
861 reg_equiv_init[i] = NULL_RTX;
866 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
867 if (reg_equiv_init[i])
869 fprintf (dump_file, "init_insns for %u: ", i);
870 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
871 fprintf (dump_file, "\n");
876 first_label_num = get_first_label_num ();
877 num_labels = max_label_num () - first_label_num;
879 /* Allocate the tables used to store offset information at labels. */
880 /* We used to use alloca here, but the size of what it would try to
881 allocate would occasionally cause it to exceed the stack limit and
882 cause a core dump. */
883 offsets_known_at = XNEWVEC (char, num_labels);
884 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
886 /* Alter each pseudo-reg rtx to contain its hard reg number.
887 Assign stack slots to the pseudos that lack hard regs or equivalents.
888 Do not touch virtual registers. */
890 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
893 /* If we have some registers we think can be eliminated, scan all insns to
894 see if there is an insn that sets one of these registers to something
895 other than itself plus a constant. If so, the register cannot be
896 eliminated. Doing this scan here eliminates an extra pass through the
897 main reload loop in the most common case where register elimination
899 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
901 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
903 maybe_fix_stack_asms ();
905 insns_need_reload = 0;
906 something_needs_elimination = 0;
908 /* Initialize to -1, which means take the first spill register. */
911 /* Spill any hard regs that we know we can't eliminate. */
912 CLEAR_HARD_REG_SET (used_spill_regs);
913 /* There can be multiple ways to eliminate a register;
914 they should be listed adjacently.
915 Elimination for any register fails only if all possible ways fail. */
916 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
919 int can_eliminate = 0;
922 can_eliminate |= ep->can_eliminate;
925 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
927 spill_hard_reg (from, 1);
930 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
931 if (frame_pointer_needed)
932 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
934 finish_spills (global);
936 /* From now on, we may need to generate moves differently. We may also
937 allow modifications of insns which cause them to not be recognized.
938 Any such modifications will be cleaned up during reload itself. */
939 reload_in_progress = 1;
941 /* This loop scans the entire function each go-round
942 and repeats until one repetition spills no additional hard regs. */
945 int something_changed;
947 HOST_WIDE_INT starting_frame_size;
949 starting_frame_size = get_frame_size ();
951 set_initial_elim_offsets ();
952 set_initial_label_offsets ();
954 /* For each pseudo register that has an equivalent location defined,
955 try to eliminate any eliminable registers (such as the frame pointer)
956 assuming initial offsets for the replacement register, which
959 If the resulting location is directly addressable, substitute
960 the MEM we just got directly for the old REG.
962 If it is not addressable but is a constant or the sum of a hard reg
963 and constant, it is probably not addressable because the constant is
964 out of range, in that case record the address; we will generate
965 hairy code to compute the address in a register each time it is
966 needed. Similarly if it is a hard register, but one that is not
967 valid as an address register.
969 If the location is not addressable, but does not have one of the
970 above forms, assign a stack slot. We have to do this to avoid the
971 potential of producing lots of reloads if, e.g., a location involves
972 a pseudo that didn't get a hard register and has an equivalent memory
973 location that also involves a pseudo that didn't get a hard register.
975 Perhaps at some point we will improve reload_when_needed handling
976 so this problem goes away. But that's very hairy. */
978 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
979 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
981 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
983 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
985 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
986 else if (CONSTANT_P (XEXP (x, 0))
987 || (REG_P (XEXP (x, 0))
988 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
989 || (GET_CODE (XEXP (x, 0)) == PLUS
990 && REG_P (XEXP (XEXP (x, 0), 0))
991 && (REGNO (XEXP (XEXP (x, 0), 0))
992 < FIRST_PSEUDO_REGISTER)
993 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
994 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
997 /* Make a new stack slot. Then indicate that something
998 changed so we go back and recompute offsets for
999 eliminable registers because the allocation of memory
1000 below might change some offset. reg_equiv_{mem,address}
1001 will be set up for this pseudo on the next pass around
1003 reg_equiv_memory_loc[i] = 0;
1004 reg_equiv_init[i] = 0;
1009 if (caller_save_needed)
1010 setup_save_areas ();
1012 /* If we allocated another stack slot, redo elimination bookkeeping. */
1013 if (starting_frame_size != get_frame_size ())
1015 if (starting_frame_size && crtl->stack_alignment_needed)
1017 /* If we have a stack frame, we must align it now. The
1018 stack size may be a part of the offset computation for
1019 register elimination. So if this changes the stack size,
1020 then repeat the elimination bookkeeping. We don't
1021 realign when there is no stack, as that will cause a
1022 stack frame when none is needed should
1023 STARTING_FRAME_OFFSET not be already aligned to
1025 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
1026 if (starting_frame_size != get_frame_size ())
1030 if (caller_save_needed)
1032 save_call_clobbered_regs ();
1033 /* That might have allocated new insn_chain structures. */
1034 reload_firstobj = obstack_alloc (&reload_obstack, 0);
1037 calculate_needs_all_insns (global);
1039 CLEAR_REG_SET (&spilled_pseudos);
1042 something_changed = 0;
1044 /* If we allocated any new memory locations, make another pass
1045 since it might have changed elimination offsets. */
1046 if (starting_frame_size != get_frame_size ())
1047 something_changed = 1;
1049 /* Even if the frame size remained the same, we might still have
1050 changed elimination offsets, e.g. if find_reloads called
1051 force_const_mem requiring the back end to allocate a constant
1052 pool base register that needs to be saved on the stack. */
1053 else if (!verify_initial_elim_offsets ())
1054 something_changed = 1;
1057 HARD_REG_SET to_spill;
1058 CLEAR_HARD_REG_SET (to_spill);
1059 update_eliminables (&to_spill);
1060 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
1062 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1063 if (TEST_HARD_REG_BIT (to_spill, i))
1065 spill_hard_reg (i, 1);
1068 /* Regardless of the state of spills, if we previously had
1069 a register that we thought we could eliminate, but now can
1070 not eliminate, we must run another pass.
1072 Consider pseudos which have an entry in reg_equiv_* which
1073 reference an eliminable register. We must make another pass
1074 to update reg_equiv_* so that we do not substitute in the
1075 old value from when we thought the elimination could be
1077 something_changed = 1;
1081 select_reload_regs ();
1085 if (insns_need_reload != 0 || did_spill)
1086 something_changed |= finish_spills (global);
1088 if (! something_changed)
1091 if (caller_save_needed)
1092 delete_caller_save_insns ();
1094 obstack_free (&reload_obstack, reload_firstobj);
1097 /* If global-alloc was run, notify it of any register eliminations we have
1100 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1101 if (ep->can_eliminate)
1102 mark_elimination (ep->from, ep->to);
1104 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1105 If that insn didn't set the register (i.e., it copied the register to
1106 memory), just delete that insn instead of the equivalencing insn plus
1107 anything now dead. If we call delete_dead_insn on that insn, we may
1108 delete the insn that actually sets the register if the register dies
1109 there and that is incorrect. */
1111 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1113 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1116 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1118 rtx equiv_insn = XEXP (list, 0);
1120 /* If we already deleted the insn or if it may trap, we can't
1121 delete it. The latter case shouldn't happen, but can
1122 if an insn has a variable address, gets a REG_EH_REGION
1123 note added to it, and then gets converted into a load
1124 from a constant address. */
1125 if (NOTE_P (equiv_insn)
1126 || can_throw_internal (equiv_insn))
1128 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1129 delete_dead_insn (equiv_insn);
1131 SET_INSN_DELETED (equiv_insn);
1136 /* Use the reload registers where necessary
1137 by generating move instructions to move the must-be-register
1138 values into or out of the reload registers. */
1140 if (insns_need_reload != 0 || something_needs_elimination
1141 || something_needs_operands_changed)
1143 HOST_WIDE_INT old_frame_size = get_frame_size ();
1145 reload_as_needed (global);
1147 gcc_assert (old_frame_size == get_frame_size ());
1149 gcc_assert (verify_initial_elim_offsets ());
1152 /* If we were able to eliminate the frame pointer, show that it is no
1153 longer live at the start of any basic block. If it ls live by
1154 virtue of being in a pseudo, that pseudo will be marked live
1155 and hence the frame pointer will be known to be live via that
1158 if (! frame_pointer_needed)
1160 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1162 /* Come here (with failure set nonzero) if we can't get enough spill
1166 CLEAR_REG_SET (&spilled_pseudos);
1167 reload_in_progress = 0;
1169 /* Now eliminate all pseudo regs by modifying them into
1170 their equivalent memory references.
1171 The REG-rtx's for the pseudos are modified in place,
1172 so all insns that used to refer to them now refer to memory.
1174 For a reg that has a reg_equiv_address, all those insns
1175 were changed by reloading so that no insns refer to it any longer;
1176 but the DECL_RTL of a variable decl may refer to it,
1177 and if so this causes the debugging info to mention the variable. */
1179 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1183 if (reg_equiv_mem[i])
1184 addr = XEXP (reg_equiv_mem[i], 0);
1186 if (reg_equiv_address[i])
1187 addr = reg_equiv_address[i];
1191 if (reg_renumber[i] < 0)
1193 rtx reg = regno_reg_rtx[i];
1195 REG_USERVAR_P (reg) = 0;
1196 PUT_CODE (reg, MEM);
1197 XEXP (reg, 0) = addr;
1198 if (reg_equiv_memory_loc[i])
1199 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1202 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1203 MEM_ATTRS (reg) = 0;
1205 MEM_NOTRAP_P (reg) = 1;
1207 else if (reg_equiv_mem[i])
1208 XEXP (reg_equiv_mem[i], 0) = addr;
1212 /* We must set reload_completed now since the cleanup_subreg_operands call
1213 below will re-recognize each insn and reload may have generated insns
1214 which are only valid during and after reload. */
1215 reload_completed = 1;
1217 /* Make a pass over all the insns and delete all USEs which we inserted
1218 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1219 notes. Delete all CLOBBER insns, except those that refer to the return
1220 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1221 from misarranging variable-array code, and simplify (subreg (reg))
1222 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1223 are no longer useful or accurate. Strip and regenerate REG_INC notes
1224 that may have been moved around. */
1226 for (insn = first; insn; insn = NEXT_INSN (insn))
1232 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1233 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1235 if ((GET_CODE (PATTERN (insn)) == USE
1236 /* We mark with QImode USEs introduced by reload itself. */
1237 && (GET_MODE (insn) == QImode
1238 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1239 || (GET_CODE (PATTERN (insn)) == CLOBBER
1240 && (!MEM_P (XEXP (PATTERN (insn), 0))
1241 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1242 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1243 && XEXP (XEXP (PATTERN (insn), 0), 0)
1244 != stack_pointer_rtx))
1245 && (!REG_P (XEXP (PATTERN (insn), 0))
1246 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1252 /* Some CLOBBERs may survive until here and still reference unassigned
1253 pseudos with const equivalent, which may in turn cause ICE in later
1254 passes if the reference remains in place. */
1255 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1256 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1257 VOIDmode, PATTERN (insn));
1259 /* Discard obvious no-ops, even without -O. This optimization
1260 is fast and doesn't interfere with debugging. */
1261 if (NONJUMP_INSN_P (insn)
1262 && GET_CODE (PATTERN (insn)) == SET
1263 && REG_P (SET_SRC (PATTERN (insn)))
1264 && REG_P (SET_DEST (PATTERN (insn)))
1265 && (REGNO (SET_SRC (PATTERN (insn)))
1266 == REGNO (SET_DEST (PATTERN (insn)))))
1272 pnote = ®_NOTES (insn);
1275 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1276 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1277 || REG_NOTE_KIND (*pnote) == REG_INC
1278 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1279 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1280 *pnote = XEXP (*pnote, 1);
1282 pnote = &XEXP (*pnote, 1);
1286 add_auto_inc_notes (insn, PATTERN (insn));
1289 /* Simplify (subreg (reg)) if it appears as an operand. */
1290 cleanup_subreg_operands (insn);
1292 /* Clean up invalid ASMs so that they don't confuse later passes.
1294 if (asm_noperands (PATTERN (insn)) >= 0)
1296 extract_insn (insn);
1297 if (!constrain_operands (1))
1299 error_for_asm (insn,
1300 "%<asm%> operand has impossible constraints");
1307 /* If we are doing stack checking, give a warning if this function's
1308 frame size is larger than we expect. */
1309 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1311 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1312 static int verbose_warned = 0;
1314 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1315 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1316 size += UNITS_PER_WORD;
1318 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1320 warning (0, "frame size too large for reliable stack checking");
1321 if (! verbose_warned)
1323 warning (0, "try reducing the number of local variables");
1329 /* Indicate that we no longer have known memory locations or constants. */
1330 if (reg_equiv_constant)
1331 free (reg_equiv_constant);
1332 if (reg_equiv_invariant)
1333 free (reg_equiv_invariant);
1334 reg_equiv_constant = 0;
1335 reg_equiv_invariant = 0;
1336 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
1337 reg_equiv_memory_loc = 0;
1339 if (offsets_known_at)
1340 free (offsets_known_at);
1344 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1345 if (reg_equiv_alt_mem_list[i])
1346 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
1347 free (reg_equiv_alt_mem_list);
1349 free (reg_equiv_mem);
1351 free (reg_equiv_address);
1352 free (reg_max_ref_width);
1353 free (reg_old_renumber);
1354 free (pseudo_previous_regs);
1355 free (pseudo_forbidden_regs);
1357 CLEAR_HARD_REG_SET (used_spill_regs);
1358 for (i = 0; i < n_spills; i++)
1359 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1361 /* Free all the insn_chain structures at once. */
1362 obstack_free (&reload_obstack, reload_startobj);
1363 unused_insn_chains = 0;
1364 fixup_abnormal_edges ();
1366 /* Replacing pseudos with their memory equivalents might have
1367 created shared rtx. Subsequent passes would get confused
1368 by this, so unshare everything here. */
1369 unshare_all_rtl_again (first);
1371 #ifdef STACK_BOUNDARY
1372 /* init_emit has set the alignment of the hard frame pointer
1373 to STACK_BOUNDARY. It is very likely no longer valid if
1374 the hard frame pointer was used for register allocation. */
1375 if (!frame_pointer_needed)
1376 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1382 /* Yet another special case. Unfortunately, reg-stack forces people to
1383 write incorrect clobbers in asm statements. These clobbers must not
1384 cause the register to appear in bad_spill_regs, otherwise we'll call
1385 fatal_insn later. We clear the corresponding regnos in the live
1386 register sets to avoid this.
1387 The whole thing is rather sick, I'm afraid. */
1390 maybe_fix_stack_asms (void)
1393 const char *constraints[MAX_RECOG_OPERANDS];
1394 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1395 struct insn_chain *chain;
1397 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1400 HARD_REG_SET clobbered, allowed;
1403 if (! INSN_P (chain->insn)
1404 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1406 pat = PATTERN (chain->insn);
1407 if (GET_CODE (pat) != PARALLEL)
1410 CLEAR_HARD_REG_SET (clobbered);
1411 CLEAR_HARD_REG_SET (allowed);
1413 /* First, make a mask of all stack regs that are clobbered. */
1414 for (i = 0; i < XVECLEN (pat, 0); i++)
1416 rtx t = XVECEXP (pat, 0, i);
1417 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1418 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1421 /* Get the operand values and constraints out of the insn. */
1422 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1423 constraints, operand_mode, NULL);
1425 /* For every operand, see what registers are allowed. */
1426 for (i = 0; i < noperands; i++)
1428 const char *p = constraints[i];
1429 /* For every alternative, we compute the class of registers allowed
1430 for reloading in CLS, and merge its contents into the reg set
1432 int cls = (int) NO_REGS;
1438 if (c == '\0' || c == ',' || c == '#')
1440 /* End of one alternative - mark the regs in the current
1441 class, and reset the class. */
1442 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1448 } while (c != '\0' && c != ',');
1456 case '=': case '+': case '*': case '%': case '?': case '!':
1457 case '0': case '1': case '2': case '3': case '4': case 'm':
1458 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1459 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1460 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1465 cls = (int) reg_class_subunion[cls]
1466 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1471 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1475 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1476 cls = (int) reg_class_subunion[cls]
1477 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1479 cls = (int) reg_class_subunion[cls]
1480 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1482 p += CONSTRAINT_LEN (c, p);
1485 /* Those of the registers which are clobbered, but allowed by the
1486 constraints, must be usable as reload registers. So clear them
1487 out of the life information. */
1488 AND_HARD_REG_SET (allowed, clobbered);
1489 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1490 if (TEST_HARD_REG_BIT (allowed, i))
1492 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1493 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1500 /* Copy the global variables n_reloads and rld into the corresponding elts
1503 copy_reloads (struct insn_chain *chain)
1505 chain->n_reloads = n_reloads;
1506 chain->rld = obstack_alloc (&reload_obstack,
1507 n_reloads * sizeof (struct reload));
1508 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1509 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1512 /* Walk the chain of insns, and determine for each whether it needs reloads
1513 and/or eliminations. Build the corresponding insns_need_reload list, and
1514 set something_needs_elimination as appropriate. */
1516 calculate_needs_all_insns (int global)
1518 struct insn_chain **pprev_reload = &insns_need_reload;
1519 struct insn_chain *chain, *next = 0;
1521 something_needs_elimination = 0;
1523 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1524 for (chain = reload_insn_chain; chain != 0; chain = next)
1526 rtx insn = chain->insn;
1530 /* Clear out the shortcuts. */
1531 chain->n_reloads = 0;
1532 chain->need_elim = 0;
1533 chain->need_reload = 0;
1534 chain->need_operand_change = 0;
1536 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1537 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1538 what effects this has on the known offsets at labels. */
1540 if (LABEL_P (insn) || JUMP_P (insn)
1541 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1542 set_label_offsets (insn, insn, 0);
1546 rtx old_body = PATTERN (insn);
1547 int old_code = INSN_CODE (insn);
1548 rtx old_notes = REG_NOTES (insn);
1549 int did_elimination = 0;
1550 int operands_changed = 0;
1551 rtx set = single_set (insn);
1553 /* Skip insns that only set an equivalence. */
1554 if (set && REG_P (SET_DEST (set))
1555 && reg_renumber[REGNO (SET_DEST (set))] < 0
1556 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1557 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1558 && reg_equiv_init[REGNO (SET_DEST (set))])
1561 /* If needed, eliminate any eliminable registers. */
1562 if (num_eliminable || num_eliminable_invariants)
1563 did_elimination = eliminate_regs_in_insn (insn, 0);
1565 /* Analyze the instruction. */
1566 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1567 global, spill_reg_order);
1569 /* If a no-op set needs more than one reload, this is likely
1570 to be something that needs input address reloads. We
1571 can't get rid of this cleanly later, and it is of no use
1572 anyway, so discard it now.
1573 We only do this when expensive_optimizations is enabled,
1574 since this complements reload inheritance / output
1575 reload deletion, and it can make debugging harder. */
1576 if (flag_expensive_optimizations && n_reloads > 1)
1578 rtx set = single_set (insn);
1580 && SET_SRC (set) == SET_DEST (set)
1581 && REG_P (SET_SRC (set))
1582 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1585 /* Delete it from the reload chain. */
1587 chain->prev->next = next;
1589 reload_insn_chain = next;
1591 next->prev = chain->prev;
1592 chain->next = unused_insn_chains;
1593 unused_insn_chains = chain;
1598 update_eliminable_offsets ();
1600 /* Remember for later shortcuts which insns had any reloads or
1601 register eliminations. */
1602 chain->need_elim = did_elimination;
1603 chain->need_reload = n_reloads > 0;
1604 chain->need_operand_change = operands_changed;
1606 /* Discard any register replacements done. */
1607 if (did_elimination)
1609 obstack_free (&reload_obstack, reload_insn_firstobj);
1610 PATTERN (insn) = old_body;
1611 INSN_CODE (insn) = old_code;
1612 REG_NOTES (insn) = old_notes;
1613 something_needs_elimination = 1;
1616 something_needs_operands_changed |= operands_changed;
1620 copy_reloads (chain);
1621 *pprev_reload = chain;
1622 pprev_reload = &chain->next_need_reload;
1629 /* Comparison function for qsort to decide which of two reloads
1630 should be handled first. *P1 and *P2 are the reload numbers. */
1633 reload_reg_class_lower (const void *r1p, const void *r2p)
1635 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1638 /* Consider required reloads before optional ones. */
1639 t = rld[r1].optional - rld[r2].optional;
1643 /* Count all solitary classes before non-solitary ones. */
1644 t = ((reg_class_size[(int) rld[r2].class] == 1)
1645 - (reg_class_size[(int) rld[r1].class] == 1));
1649 /* Aside from solitaires, consider all multi-reg groups first. */
1650 t = rld[r2].nregs - rld[r1].nregs;
1654 /* Consider reloads in order of increasing reg-class number. */
1655 t = (int) rld[r1].class - (int) rld[r2].class;
1659 /* If reloads are equally urgent, sort by reload number,
1660 so that the results of qsort leave nothing to chance. */
1664 /* The cost of spilling each hard reg. */
1665 static int spill_cost[FIRST_PSEUDO_REGISTER];
1667 /* When spilling multiple hard registers, we use SPILL_COST for the first
1668 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1669 only the first hard reg for a multi-reg pseudo. */
1670 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1672 /* Update the spill cost arrays, considering that pseudo REG is live. */
1675 count_pseudo (int reg)
1677 int freq = REG_FREQ (reg);
1678 int r = reg_renumber[reg];
1681 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1682 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1685 SET_REGNO_REG_SET (&pseudos_counted, reg);
1687 gcc_assert (r >= 0);
1689 spill_add_cost[r] += freq;
1691 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1693 spill_cost[r + nregs] += freq;
1696 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1697 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1700 order_regs_for_reload (struct insn_chain *chain)
1703 HARD_REG_SET used_by_pseudos;
1704 HARD_REG_SET used_by_pseudos2;
1705 reg_set_iterator rsi;
1707 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1709 memset (spill_cost, 0, sizeof spill_cost);
1710 memset (spill_add_cost, 0, sizeof spill_add_cost);
1712 /* Count number of uses of each hard reg by pseudo regs allocated to it
1713 and then order them by decreasing use. First exclude hard registers
1714 that are live in or across this insn. */
1716 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1717 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1718 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1719 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1721 /* Now find out which pseudos are allocated to it, and update
1723 CLEAR_REG_SET (&pseudos_counted);
1725 EXECUTE_IF_SET_IN_REG_SET
1726 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1730 EXECUTE_IF_SET_IN_REG_SET
1731 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1735 CLEAR_REG_SET (&pseudos_counted);
1738 /* Vector of reload-numbers showing the order in which the reloads should
1740 static short reload_order[MAX_RELOADS];
1742 /* This is used to keep track of the spill regs used in one insn. */
1743 static HARD_REG_SET used_spill_regs_local;
1745 /* We decided to spill hard register SPILLED, which has a size of
1746 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1747 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1748 update SPILL_COST/SPILL_ADD_COST. */
1751 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1753 int r = reg_renumber[reg];
1754 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1756 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1757 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1760 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1762 spill_add_cost[r] -= REG_FREQ (reg);
1764 spill_cost[r + nregs] -= REG_FREQ (reg);
1767 /* Find reload register to use for reload number ORDER. */
1770 find_reg (struct insn_chain *chain, int order)
1772 int rnum = reload_order[order];
1773 struct reload *rl = rld + rnum;
1774 int best_cost = INT_MAX;
1778 HARD_REG_SET not_usable;
1779 HARD_REG_SET used_by_other_reload;
1780 reg_set_iterator rsi;
1782 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1783 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1784 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1786 CLEAR_HARD_REG_SET (used_by_other_reload);
1787 for (k = 0; k < order; k++)
1789 int other = reload_order[k];
1791 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1792 for (j = 0; j < rld[other].nregs; j++)
1793 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1796 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1798 unsigned int regno = i;
1800 if (! TEST_HARD_REG_BIT (not_usable, regno)
1801 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1802 && HARD_REGNO_MODE_OK (regno, rl->mode))
1804 int this_cost = spill_cost[regno];
1806 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1808 for (j = 1; j < this_nregs; j++)
1810 this_cost += spill_add_cost[regno + j];
1811 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1812 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1817 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1819 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1821 if (this_cost < best_cost
1822 /* Among registers with equal cost, prefer caller-saved ones, or
1823 use REG_ALLOC_ORDER if it is defined. */
1824 || (this_cost == best_cost
1825 #ifdef REG_ALLOC_ORDER
1826 && (inv_reg_alloc_order[regno]
1827 < inv_reg_alloc_order[best_reg])
1829 && call_used_regs[regno]
1830 && ! call_used_regs[best_reg]
1835 best_cost = this_cost;
1843 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1845 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1846 rl->regno = best_reg;
1848 EXECUTE_IF_SET_IN_REG_SET
1849 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1851 count_spilled_pseudo (best_reg, rl->nregs, j);
1854 EXECUTE_IF_SET_IN_REG_SET
1855 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1857 count_spilled_pseudo (best_reg, rl->nregs, j);
1860 for (i = 0; i < rl->nregs; i++)
1862 gcc_assert (spill_cost[best_reg + i] == 0);
1863 gcc_assert (spill_add_cost[best_reg + i] == 0);
1864 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1869 /* Find more reload regs to satisfy the remaining need of an insn, which
1871 Do it by ascending class number, since otherwise a reg
1872 might be spilled for a big class and might fail to count
1873 for a smaller class even though it belongs to that class. */
1876 find_reload_regs (struct insn_chain *chain)
1880 /* In order to be certain of getting the registers we need,
1881 we must sort the reloads into order of increasing register class.
1882 Then our grabbing of reload registers will parallel the process
1883 that provided the reload registers. */
1884 for (i = 0; i < chain->n_reloads; i++)
1886 /* Show whether this reload already has a hard reg. */
1887 if (chain->rld[i].reg_rtx)
1889 int regno = REGNO (chain->rld[i].reg_rtx);
1890 chain->rld[i].regno = regno;
1892 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1895 chain->rld[i].regno = -1;
1896 reload_order[i] = i;
1899 n_reloads = chain->n_reloads;
1900 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1902 CLEAR_HARD_REG_SET (used_spill_regs_local);
1905 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1907 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1909 /* Compute the order of preference for hard registers to spill. */
1911 order_regs_for_reload (chain);
1913 for (i = 0; i < n_reloads; i++)
1915 int r = reload_order[i];
1917 /* Ignore reloads that got marked inoperative. */
1918 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1919 && ! rld[r].optional
1920 && rld[r].regno == -1)
1921 if (! find_reg (chain, i))
1924 fprintf (dump_file, "reload failure for reload %d\n", r);
1925 spill_failure (chain->insn, rld[r].class);
1931 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1932 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1934 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1938 select_reload_regs (void)
1940 struct insn_chain *chain;
1942 /* Try to satisfy the needs for each insn. */
1943 for (chain = insns_need_reload; chain != 0;
1944 chain = chain->next_need_reload)
1945 find_reload_regs (chain);
1948 /* Delete all insns that were inserted by emit_caller_save_insns during
1951 delete_caller_save_insns (void)
1953 struct insn_chain *c = reload_insn_chain;
1957 while (c != 0 && c->is_caller_save_insn)
1959 struct insn_chain *next = c->next;
1962 if (c == reload_insn_chain)
1963 reload_insn_chain = next;
1967 next->prev = c->prev;
1969 c->prev->next = next;
1970 c->next = unused_insn_chains;
1971 unused_insn_chains = c;
1979 /* Handle the failure to find a register to spill.
1980 INSN should be one of the insns which needed this particular spill reg. */
1983 spill_failure (rtx insn, enum reg_class class)
1985 if (asm_noperands (PATTERN (insn)) >= 0)
1986 error_for_asm (insn, "can't find a register in class %qs while "
1987 "reloading %<asm%>",
1988 reg_class_names[class]);
1991 error ("unable to find a register to spill in class %qs",
1992 reg_class_names[class]);
1996 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
1997 debug_reload_to_stream (dump_file);
1999 fatal_insn ("this is the insn:", insn);
2003 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2004 data that is dead in INSN. */
2007 delete_dead_insn (rtx insn)
2009 rtx prev = prev_real_insn (insn);
2012 /* If the previous insn sets a register that dies in our insn, delete it
2014 if (prev && GET_CODE (PATTERN (prev)) == SET
2015 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2016 && reg_mentioned_p (prev_dest, PATTERN (insn))
2017 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2018 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2019 delete_dead_insn (prev);
2021 SET_INSN_DELETED (insn);
2024 /* Modify the home of pseudo-reg I.
2025 The new home is present in reg_renumber[I].
2027 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2028 or it may be -1, meaning there is none or it is not relevant.
2029 This is used so that all pseudos spilled from a given hard reg
2030 can share one stack slot. */
2033 alter_reg (int i, int from_reg)
2035 /* When outputting an inline function, this can happen
2036 for a reg that isn't actually used. */
2037 if (regno_reg_rtx[i] == 0)
2040 /* If the reg got changed to a MEM at rtl-generation time,
2042 if (!REG_P (regno_reg_rtx[i]))
2045 /* Modify the reg-rtx to contain the new hard reg
2046 number or else to contain its pseudo reg number. */
2047 SET_REGNO (regno_reg_rtx[i],
2048 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2050 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2051 allocate a stack slot for it. */
2053 if (reg_renumber[i] < 0
2054 && REG_N_REFS (i) > 0
2055 && reg_equiv_constant[i] == 0
2056 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
2057 && reg_equiv_memory_loc[i] == 0)
2060 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2061 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2062 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2063 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2064 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2067 /* Each pseudo reg has an inherent size which comes from its own mode,
2068 and a total size which provides room for paradoxical subregs
2069 which refer to the pseudo reg in wider modes.
2071 We can use a slot already allocated if it provides both
2072 enough inherent space and enough total space.
2073 Otherwise, we allocate a new slot, making sure that it has no less
2074 inherent space, and no less total space, then the previous slot. */
2077 alias_set_type alias_set = new_alias_set ();
2079 /* No known place to spill from => no slot to reuse. */
2080 x = assign_stack_local (mode, total_size,
2081 min_align > inherent_align
2082 || total_size > inherent_size ? -1 : 0);
2083 if (BYTES_BIG_ENDIAN)
2084 /* Cancel the big-endian correction done in assign_stack_local.
2085 Get the address of the beginning of the slot.
2086 This is so we can do a big-endian correction unconditionally
2088 adjust = inherent_size - total_size;
2090 /* Nothing can alias this slot except this pseudo. */
2091 set_mem_alias_set (x, alias_set);
2092 dse_record_singleton_alias_set (alias_set, mode);
2095 /* Reuse a stack slot if possible. */
2096 else if (spill_stack_slot[from_reg] != 0
2097 && spill_stack_slot_width[from_reg] >= total_size
2098 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2100 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2101 x = spill_stack_slot[from_reg];
2102 /* Allocate a bigger slot. */
2105 /* Compute maximum size needed, both for inherent size
2106 and for total size. */
2109 if (spill_stack_slot[from_reg])
2111 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2113 mode = GET_MODE (spill_stack_slot[from_reg]);
2114 if (spill_stack_slot_width[from_reg] > total_size)
2115 total_size = spill_stack_slot_width[from_reg];
2116 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2117 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2120 /* Make a slot with that size. */
2121 x = assign_stack_local (mode, total_size,
2122 min_align > inherent_align
2123 || total_size > inherent_size ? -1 : 0);
2126 /* All pseudos mapped to this slot can alias each other. */
2127 if (spill_stack_slot[from_reg])
2129 alias_set_type alias_set
2130 = MEM_ALIAS_SET (spill_stack_slot[from_reg]);
2131 set_mem_alias_set (x, alias_set);
2132 dse_invalidate_singleton_alias_set (alias_set);
2136 alias_set_type alias_set = new_alias_set ();
2137 set_mem_alias_set (x, alias_set);
2138 dse_record_singleton_alias_set (alias_set, mode);
2141 if (BYTES_BIG_ENDIAN)
2143 /* Cancel the big-endian correction done in assign_stack_local.
2144 Get the address of the beginning of the slot.
2145 This is so we can do a big-endian correction unconditionally
2147 adjust = GET_MODE_SIZE (mode) - total_size;
2150 = adjust_address_nv (x, mode_for_size (total_size
2156 spill_stack_slot[from_reg] = stack_slot;
2157 spill_stack_slot_width[from_reg] = total_size;
2160 /* On a big endian machine, the "address" of the slot
2161 is the address of the low part that fits its inherent mode. */
2162 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2163 adjust += (total_size - inherent_size);
2165 /* If we have any adjustment to make, or if the stack slot is the
2166 wrong mode, make a new stack slot. */
2167 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2169 /* If we have a decl for the original register, set it for the
2170 memory. If this is a shared MEM, make a copy. */
2171 if (REG_EXPR (regno_reg_rtx[i])
2172 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2174 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2176 /* We can do this only for the DECLs home pseudo, not for
2177 any copies of it, since otherwise when the stack slot
2178 is reused, nonoverlapping_memrefs_p might think they
2180 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2182 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2185 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2189 /* Save the stack slot for later. */
2190 reg_equiv_memory_loc[i] = x;
2194 /* Mark the slots in regs_ever_live for the hard regs used by
2195 pseudo-reg number REGNO, accessed in MODE. */
2198 mark_home_live_1 (int regno, enum machine_mode mode)
2202 i = reg_renumber[regno];
2205 lim = end_hard_regno (mode, i);
2207 df_set_regs_ever_live(i++, true);
2210 /* Mark the slots in regs_ever_live for the hard regs
2211 used by pseudo-reg number REGNO. */
2214 mark_home_live (int regno)
2216 if (reg_renumber[regno] >= 0)
2217 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2220 /* This function handles the tracking of elimination offsets around branches.
2222 X is a piece of RTL being scanned.
2224 INSN is the insn that it came from, if any.
2226 INITIAL_P is nonzero if we are to set the offset to be the initial
2227 offset and zero if we are setting the offset of the label to be the
2231 set_label_offsets (rtx x, rtx insn, int initial_p)
2233 enum rtx_code code = GET_CODE (x);
2236 struct elim_table *p;
2241 if (LABEL_REF_NONLOCAL_P (x))
2246 /* ... fall through ... */
2249 /* If we know nothing about this label, set the desired offsets. Note
2250 that this sets the offset at a label to be the offset before a label
2251 if we don't know anything about the label. This is not correct for
2252 the label after a BARRIER, but is the best guess we can make. If
2253 we guessed wrong, we will suppress an elimination that might have
2254 been possible had we been able to guess correctly. */
2256 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2258 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2259 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2260 = (initial_p ? reg_eliminate[i].initial_offset
2261 : reg_eliminate[i].offset);
2262 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2265 /* Otherwise, if this is the definition of a label and it is
2266 preceded by a BARRIER, set our offsets to the known offset of
2270 && (tem = prev_nonnote_insn (insn)) != 0
2272 set_offsets_for_label (insn);
2274 /* If neither of the above cases is true, compare each offset
2275 with those previously recorded and suppress any eliminations
2276 where the offsets disagree. */
2278 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2279 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2280 != (initial_p ? reg_eliminate[i].initial_offset
2281 : reg_eliminate[i].offset))
2282 reg_eliminate[i].can_eliminate = 0;
2287 set_label_offsets (PATTERN (insn), insn, initial_p);
2289 /* ... fall through ... */
2293 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2294 to indirectly and hence must have all eliminations at their
2296 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2297 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2298 set_label_offsets (XEXP (tem, 0), insn, 1);
2304 /* Each of the labels in the parallel or address vector must be
2305 at their initial offsets. We want the first field for PARALLEL
2306 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2308 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2309 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2314 /* We only care about setting PC. If the source is not RETURN,
2315 IF_THEN_ELSE, or a label, disable any eliminations not at
2316 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2317 isn't one of those possibilities. For branches to a label,
2318 call ourselves recursively.
2320 Note that this can disable elimination unnecessarily when we have
2321 a non-local goto since it will look like a non-constant jump to
2322 someplace in the current function. This isn't a significant
2323 problem since such jumps will normally be when all elimination
2324 pairs are back to their initial offsets. */
2326 if (SET_DEST (x) != pc_rtx)
2329 switch (GET_CODE (SET_SRC (x)))
2336 set_label_offsets (SET_SRC (x), insn, initial_p);
2340 tem = XEXP (SET_SRC (x), 1);
2341 if (GET_CODE (tem) == LABEL_REF)
2342 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2343 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2346 tem = XEXP (SET_SRC (x), 2);
2347 if (GET_CODE (tem) == LABEL_REF)
2348 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2349 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2357 /* If we reach here, all eliminations must be at their initial
2358 offset because we are doing a jump to a variable address. */
2359 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2360 if (p->offset != p->initial_offset)
2361 p->can_eliminate = 0;
2369 /* Scan X and replace any eliminable registers (such as fp) with a
2370 replacement (such as sp), plus an offset.
2372 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2373 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2374 MEM, we are allowed to replace a sum of a register and the constant zero
2375 with the register, which we cannot do outside a MEM. In addition, we need
2376 to record the fact that a register is referenced outside a MEM.
2378 If INSN is an insn, it is the insn containing X. If we replace a REG
2379 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2380 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2381 the REG is being modified.
2383 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2384 That's used when we eliminate in expressions stored in notes.
2385 This means, do not set ref_outside_mem even if the reference
2388 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2389 replacements done assuming all offsets are at their initial values. If
2390 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2391 encounter, return the actual location so that find_reloads will do
2392 the proper thing. */
2395 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2396 bool may_use_invariant)
2398 enum rtx_code code = GET_CODE (x);
2399 struct elim_table *ep;
2406 if (! current_function_decl)
2429 /* First handle the case where we encounter a bare register that
2430 is eliminable. Replace it with a PLUS. */
2431 if (regno < FIRST_PSEUDO_REGISTER)
2433 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2435 if (ep->from_rtx == x && ep->can_eliminate)
2436 return plus_constant (ep->to_rtx, ep->previous_offset);
2439 else if (reg_renumber && reg_renumber[regno] < 0
2440 && reg_equiv_invariant && reg_equiv_invariant[regno])
2442 if (may_use_invariant)
2443 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2444 mem_mode, insn, true);
2445 /* There exists at least one use of REGNO that cannot be
2446 eliminated. Prevent the defining insn from being deleted. */
2447 reg_equiv_init[regno] = NULL_RTX;
2448 alter_reg (regno, -1);
2452 /* You might think handling MINUS in a manner similar to PLUS is a
2453 good idea. It is not. It has been tried multiple times and every
2454 time the change has had to have been reverted.
2456 Other parts of reload know a PLUS is special (gen_reload for example)
2457 and require special code to handle code a reloaded PLUS operand.
2459 Also consider backends where the flags register is clobbered by a
2460 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2461 lea instruction comes to mind). If we try to reload a MINUS, we
2462 may kill the flags register that was holding a useful value.
2464 So, please before trying to handle MINUS, consider reload as a
2465 whole instead of this little section as well as the backend issues. */
2467 /* If this is the sum of an eliminable register and a constant, rework
2469 if (REG_P (XEXP (x, 0))
2470 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2471 && CONSTANT_P (XEXP (x, 1)))
2473 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2475 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2477 /* The only time we want to replace a PLUS with a REG (this
2478 occurs when the constant operand of the PLUS is the negative
2479 of the offset) is when we are inside a MEM. We won't want
2480 to do so at other times because that would change the
2481 structure of the insn in a way that reload can't handle.
2482 We special-case the commonest situation in
2483 eliminate_regs_in_insn, so just replace a PLUS with a
2484 PLUS here, unless inside a MEM. */
2485 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2486 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2489 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2490 plus_constant (XEXP (x, 1),
2491 ep->previous_offset));
2494 /* If the register is not eliminable, we are done since the other
2495 operand is a constant. */
2499 /* If this is part of an address, we want to bring any constant to the
2500 outermost PLUS. We will do this by doing register replacement in
2501 our operands and seeing if a constant shows up in one of them.
2503 Note that there is no risk of modifying the structure of the insn,
2504 since we only get called for its operands, thus we are either
2505 modifying the address inside a MEM, or something like an address
2506 operand of a load-address insn. */
2509 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2510 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2512 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2514 /* If one side is a PLUS and the other side is a pseudo that
2515 didn't get a hard register but has a reg_equiv_constant,
2516 we must replace the constant here since it may no longer
2517 be in the position of any operand. */
2518 if (GET_CODE (new0) == PLUS && REG_P (new1)
2519 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2520 && reg_renumber[REGNO (new1)] < 0
2521 && reg_equiv_constant != 0
2522 && reg_equiv_constant[REGNO (new1)] != 0)
2523 new1 = reg_equiv_constant[REGNO (new1)];
2524 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2525 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2526 && reg_renumber[REGNO (new0)] < 0
2527 && reg_equiv_constant[REGNO (new0)] != 0)
2528 new0 = reg_equiv_constant[REGNO (new0)];
2530 new = form_sum (new0, new1);
2532 /* As above, if we are not inside a MEM we do not want to
2533 turn a PLUS into something else. We might try to do so here
2534 for an addition of 0 if we aren't optimizing. */
2535 if (! mem_mode && GET_CODE (new) != PLUS)
2536 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2544 /* If this is the product of an eliminable register and a
2545 constant, apply the distribute law and move the constant out
2546 so that we have (plus (mult ..) ..). This is needed in order
2547 to keep load-address insns valid. This case is pathological.
2548 We ignore the possibility of overflow here. */
2549 if (REG_P (XEXP (x, 0))
2550 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2551 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2552 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2554 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2557 /* Refs inside notes don't count for this purpose. */
2558 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2559 || GET_CODE (insn) == INSN_LIST)))
2560 ep->ref_outside_mem = 1;
2563 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2564 ep->previous_offset * INTVAL (XEXP (x, 1)));
2567 /* ... fall through ... */
2571 /* See comments before PLUS about handling MINUS. */
2573 case DIV: case UDIV:
2574 case MOD: case UMOD:
2575 case AND: case IOR: case XOR:
2576 case ROTATERT: case ROTATE:
2577 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2579 case GE: case GT: case GEU: case GTU:
2580 case LE: case LT: case LEU: case LTU:
2582 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2583 rtx new1 = XEXP (x, 1)
2584 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2586 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2587 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2592 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2595 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2596 if (new != XEXP (x, 0))
2598 /* If this is a REG_DEAD note, it is not valid anymore.
2599 Using the eliminated version could result in creating a
2600 REG_DEAD note for the stack or frame pointer. */
2601 if (GET_MODE (x) == REG_DEAD)
2603 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2606 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2610 /* ... fall through ... */
2613 /* Now do eliminations in the rest of the chain. If this was
2614 an EXPR_LIST, this might result in allocating more memory than is
2615 strictly needed, but it simplifies the code. */
2618 new = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2619 if (new != XEXP (x, 1))
2621 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2629 /* We do not support elimination of a register that is modified.
2630 elimination_effects has already make sure that this does not
2636 /* We do not support elimination of a register that is modified.
2637 elimination_effects has already make sure that this does not
2638 happen. The only remaining case we need to consider here is
2639 that the increment value may be an eliminable register. */
2640 if (GET_CODE (XEXP (x, 1)) == PLUS
2641 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2643 rtx new = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2646 if (new != XEXP (XEXP (x, 1), 1))
2647 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2648 gen_rtx_PLUS (GET_MODE (x),
2653 case STRICT_LOW_PART:
2655 case SIGN_EXTEND: case ZERO_EXTEND:
2656 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2657 case FLOAT: case FIX:
2658 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2667 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2668 if (new != XEXP (x, 0))
2669 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2673 /* Similar to above processing, but preserve SUBREG_BYTE.
2674 Convert (subreg (mem)) to (mem) if not paradoxical.
2675 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2676 pseudo didn't get a hard reg, we must replace this with the
2677 eliminated version of the memory location because push_reload
2678 may do the replacement in certain circumstances. */
2679 if (REG_P (SUBREG_REG (x))
2680 && (GET_MODE_SIZE (GET_MODE (x))
2681 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2682 && reg_equiv_memory_loc != 0
2683 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2685 new = SUBREG_REG (x);
2688 new = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2690 if (new != SUBREG_REG (x))
2692 int x_size = GET_MODE_SIZE (GET_MODE (x));
2693 int new_size = GET_MODE_SIZE (GET_MODE (new));
2696 && ((x_size < new_size
2697 #ifdef WORD_REGISTER_OPERATIONS
2698 /* On these machines, combine can create rtl of the form
2699 (set (subreg:m1 (reg:m2 R) 0) ...)
2700 where m1 < m2, and expects something interesting to
2701 happen to the entire word. Moreover, it will use the
2702 (reg:m2 R) later, expecting all bits to be preserved.
2703 So if the number of words is the same, preserve the
2704 subreg so that push_reload can see it. */
2705 && ! ((x_size - 1) / UNITS_PER_WORD
2706 == (new_size -1 ) / UNITS_PER_WORD)
2709 || x_size == new_size)
2711 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2713 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2719 /* Our only special processing is to pass the mode of the MEM to our
2720 recursive call and copy the flags. While we are here, handle this
2721 case more efficiently. */
2723 replace_equiv_address_nv (x,
2724 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2728 /* Handle insn_list USE that a call to a pure function may generate. */
2729 new = eliminate_regs_1 (XEXP (x, 0), 0, insn, false);
2730 if (new != XEXP (x, 0))
2731 return gen_rtx_USE (GET_MODE (x), new);
2743 /* Process each of our operands recursively. If any have changed, make a
2745 fmt = GET_RTX_FORMAT (code);
2746 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2750 new = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2751 if (new != XEXP (x, i) && ! copied)
2753 x = shallow_copy_rtx (x);
2758 else if (*fmt == 'E')
2761 for (j = 0; j < XVECLEN (x, i); j++)
2763 new = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2764 if (new != XVECEXP (x, i, j) && ! copied_vec)
2766 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2770 x = shallow_copy_rtx (x);
2773 XVEC (x, i) = new_v;
2776 XVECEXP (x, i, j) = new;
2785 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2787 return eliminate_regs_1 (x, mem_mode, insn, false);
2790 /* Scan rtx X for modifications of elimination target registers. Update
2791 the table of eliminables to reflect the changed state. MEM_MODE is
2792 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2795 elimination_effects (rtx x, enum machine_mode mem_mode)
2797 enum rtx_code code = GET_CODE (x);
2798 struct elim_table *ep;
2823 /* First handle the case where we encounter a bare register that
2824 is eliminable. Replace it with a PLUS. */
2825 if (regno < FIRST_PSEUDO_REGISTER)
2827 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2829 if (ep->from_rtx == x && ep->can_eliminate)
2832 ep->ref_outside_mem = 1;
2837 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2838 && reg_equiv_constant[regno]
2839 && ! function_invariant_p (reg_equiv_constant[regno]))
2840 elimination_effects (reg_equiv_constant[regno], mem_mode);
2849 /* If we modify the source of an elimination rule, disable it. */
2850 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2851 if (ep->from_rtx == XEXP (x, 0))
2852 ep->can_eliminate = 0;
2854 /* If we modify the target of an elimination rule by adding a constant,
2855 update its offset. If we modify the target in any other way, we'll
2856 have to disable the rule as well. */
2857 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2858 if (ep->to_rtx == XEXP (x, 0))
2860 int size = GET_MODE_SIZE (mem_mode);
2862 /* If more bytes than MEM_MODE are pushed, account for them. */
2863 #ifdef PUSH_ROUNDING
2864 if (ep->to_rtx == stack_pointer_rtx)
2865 size = PUSH_ROUNDING (size);
2867 if (code == PRE_DEC || code == POST_DEC)
2869 else if (code == PRE_INC || code == POST_INC)
2871 else if (code == PRE_MODIFY || code == POST_MODIFY)
2873 if (GET_CODE (XEXP (x, 1)) == PLUS
2874 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2875 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
2876 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2878 ep->can_eliminate = 0;
2882 /* These two aren't unary operators. */
2883 if (code == POST_MODIFY || code == PRE_MODIFY)
2886 /* Fall through to generic unary operation case. */
2887 case STRICT_LOW_PART:
2889 case SIGN_EXTEND: case ZERO_EXTEND:
2890 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2891 case FLOAT: case FIX:
2892 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2901 elimination_effects (XEXP (x, 0), mem_mode);
2905 if (REG_P (SUBREG_REG (x))
2906 && (GET_MODE_SIZE (GET_MODE (x))
2907 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2908 && reg_equiv_memory_loc != 0
2909 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2912 elimination_effects (SUBREG_REG (x), mem_mode);
2916 /* If using a register that is the source of an eliminate we still
2917 think can be performed, note it cannot be performed since we don't
2918 know how this register is used. */
2919 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2920 if (ep->from_rtx == XEXP (x, 0))
2921 ep->can_eliminate = 0;
2923 elimination_effects (XEXP (x, 0), mem_mode);
2927 /* If clobbering a register that is the replacement register for an
2928 elimination we still think can be performed, note that it cannot
2929 be performed. Otherwise, we need not be concerned about it. */
2930 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2931 if (ep->to_rtx == XEXP (x, 0))
2932 ep->can_eliminate = 0;
2934 elimination_effects (XEXP (x, 0), mem_mode);
2938 /* Check for setting a register that we know about. */
2939 if (REG_P (SET_DEST (x)))
2941 /* See if this is setting the replacement register for an
2944 If DEST is the hard frame pointer, we do nothing because we
2945 assume that all assignments to the frame pointer are for
2946 non-local gotos and are being done at a time when they are valid
2947 and do not disturb anything else. Some machines want to
2948 eliminate a fake argument pointer (or even a fake frame pointer)
2949 with either the real frame or the stack pointer. Assignments to
2950 the hard frame pointer must not prevent this elimination. */
2952 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2954 if (ep->to_rtx == SET_DEST (x)
2955 && SET_DEST (x) != hard_frame_pointer_rtx)
2957 /* If it is being incremented, adjust the offset. Otherwise,
2958 this elimination can't be done. */
2959 rtx src = SET_SRC (x);
2961 if (GET_CODE (src) == PLUS
2962 && XEXP (src, 0) == SET_DEST (x)
2963 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2964 ep->offset -= INTVAL (XEXP (src, 1));
2966 ep->can_eliminate = 0;
2970 elimination_effects (SET_DEST (x), 0);
2971 elimination_effects (SET_SRC (x), 0);
2975 /* Our only special processing is to pass the mode of the MEM to our
2977 elimination_effects (XEXP (x, 0), GET_MODE (x));
2984 fmt = GET_RTX_FORMAT (code);
2985 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2988 elimination_effects (XEXP (x, i), mem_mode);
2989 else if (*fmt == 'E')
2990 for (j = 0; j < XVECLEN (x, i); j++)
2991 elimination_effects (XVECEXP (x, i, j), mem_mode);
2995 /* Descend through rtx X and verify that no references to eliminable registers
2996 remain. If any do remain, mark the involved register as not
3000 check_eliminable_occurrences (rtx x)
3009 code = GET_CODE (x);
3011 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3013 struct elim_table *ep;
3015 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3016 if (ep->from_rtx == x)
3017 ep->can_eliminate = 0;
3021 fmt = GET_RTX_FORMAT (code);
3022 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3025 check_eliminable_occurrences (XEXP (x, i));
3026 else if (*fmt == 'E')
3029 for (j = 0; j < XVECLEN (x, i); j++)
3030 check_eliminable_occurrences (XVECEXP (x, i, j));
3035 /* Scan INSN and eliminate all eliminable registers in it.
3037 If REPLACE is nonzero, do the replacement destructively. Also
3038 delete the insn as dead it if it is setting an eliminable register.
3040 If REPLACE is zero, do all our allocations in reload_obstack.
3042 If no eliminations were done and this insn doesn't require any elimination
3043 processing (these are not identical conditions: it might be updating sp,
3044 but not referencing fp; this needs to be seen during reload_as_needed so
3045 that the offset between fp and sp can be taken into consideration), zero
3046 is returned. Otherwise, 1 is returned. */
3049 eliminate_regs_in_insn (rtx insn, int replace)
3051 int icode = recog_memoized (insn);
3052 rtx old_body = PATTERN (insn);
3053 int insn_is_asm = asm_noperands (old_body) >= 0;
3054 rtx old_set = single_set (insn);
3058 rtx substed_operand[MAX_RECOG_OPERANDS];
3059 rtx orig_operand[MAX_RECOG_OPERANDS];
3060 struct elim_table *ep;
3061 rtx plus_src, plus_cst_src;
3063 if (! insn_is_asm && icode < 0)
3065 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3066 || GET_CODE (PATTERN (insn)) == CLOBBER
3067 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3068 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3069 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3073 if (old_set != 0 && REG_P (SET_DEST (old_set))
3074 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3076 /* Check for setting an eliminable register. */
3077 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3078 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3080 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3081 /* If this is setting the frame pointer register to the
3082 hardware frame pointer register and this is an elimination
3083 that will be done (tested above), this insn is really
3084 adjusting the frame pointer downward to compensate for
3085 the adjustment done before a nonlocal goto. */
3086 if (ep->from == FRAME_POINTER_REGNUM
3087 && ep->to == HARD_FRAME_POINTER_REGNUM)
3089 rtx base = SET_SRC (old_set);
3090 rtx base_insn = insn;
3091 HOST_WIDE_INT offset = 0;
3093 while (base != ep->to_rtx)
3095 rtx prev_insn, prev_set;
3097 if (GET_CODE (base) == PLUS
3098 && GET_CODE (XEXP (base, 1)) == CONST_INT)
3100 offset += INTVAL (XEXP (base, 1));
3101 base = XEXP (base, 0);
3103 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3104 && (prev_set = single_set (prev_insn)) != 0
3105 && rtx_equal_p (SET_DEST (prev_set), base))
3107 base = SET_SRC (prev_set);
3108 base_insn = prev_insn;
3114 if (base == ep->to_rtx)
3117 = plus_constant (ep->to_rtx, offset - ep->offset);
3119 new_body = old_body;
3122 new_body = copy_insn (old_body);
3123 if (REG_NOTES (insn))
3124 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3126 PATTERN (insn) = new_body;
3127 old_set = single_set (insn);
3129 /* First see if this insn remains valid when we
3130 make the change. If not, keep the INSN_CODE
3131 the same and let reload fit it up. */
3132 validate_change (insn, &SET_SRC (old_set), src, 1);
3133 validate_change (insn, &SET_DEST (old_set),
3135 if (! apply_change_group ())
3137 SET_SRC (old_set) = src;
3138 SET_DEST (old_set) = ep->to_rtx;
3147 /* In this case this insn isn't serving a useful purpose. We
3148 will delete it in reload_as_needed once we know that this
3149 elimination is, in fact, being done.
3151 If REPLACE isn't set, we can't delete this insn, but needn't
3152 process it since it won't be used unless something changes. */
3155 delete_dead_insn (insn);
3163 /* We allow one special case which happens to work on all machines we
3164 currently support: a single set with the source or a REG_EQUAL
3165 note being a PLUS of an eliminable register and a constant. */
3166 plus_src = plus_cst_src = 0;
3167 if (old_set && REG_P (SET_DEST (old_set)))
3169 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3170 plus_src = SET_SRC (old_set);
3171 /* First see if the source is of the form (plus (...) CST). */
3173 && GET_CODE (XEXP (plus_src, 1)) == CONST_INT)
3174 plus_cst_src = plus_src;
3175 else if (REG_P (SET_SRC (old_set))
3178 /* Otherwise, see if we have a REG_EQUAL note of the form
3179 (plus (...) CST). */
3181 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3183 if ((REG_NOTE_KIND (links) == REG_EQUAL
3184 || REG_NOTE_KIND (links) == REG_EQUIV)
3185 && GET_CODE (XEXP (links, 0)) == PLUS
3186 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT)
3188 plus_cst_src = XEXP (links, 0);
3194 /* Check that the first operand of the PLUS is a hard reg or
3195 the lowpart subreg of one. */
3198 rtx reg = XEXP (plus_cst_src, 0);
3199 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3200 reg = SUBREG_REG (reg);
3202 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3208 rtx reg = XEXP (plus_cst_src, 0);
3209 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3211 if (GET_CODE (reg) == SUBREG)
3212 reg = SUBREG_REG (reg);
3214 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3215 if (ep->from_rtx == reg && ep->can_eliminate)
3217 rtx to_rtx = ep->to_rtx;
3218 offset += ep->offset;
3219 offset = trunc_int_for_mode (offset, GET_MODE (reg));
3221 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3222 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3224 /* If we have a nonzero offset, and the source is already
3225 a simple REG, the following transformation would
3226 increase the cost of the insn by replacing a simple REG
3227 with (plus (reg sp) CST). So try only when we already
3228 had a PLUS before. */
3229 if (offset == 0 || plus_src)
3231 rtx new_src = plus_constant (to_rtx, offset);
3233 new_body = old_body;
3236 new_body = copy_insn (old_body);
3237 if (REG_NOTES (insn))
3238 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3240 PATTERN (insn) = new_body;
3241 old_set = single_set (insn);
3243 /* First see if this insn remains valid when we make the
3244 change. If not, try to replace the whole pattern with
3245 a simple set (this may help if the original insn was a
3246 PARALLEL that was only recognized as single_set due to
3247 REG_UNUSED notes). If this isn't valid either, keep
3248 the INSN_CODE the same and let reload fix it up. */
3249 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3251 rtx new_pat = gen_rtx_SET (VOIDmode,
3252 SET_DEST (old_set), new_src);
3254 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3255 SET_SRC (old_set) = new_src;
3262 /* This can't have an effect on elimination offsets, so skip right
3268 /* Determine the effects of this insn on elimination offsets. */
3269 elimination_effects (old_body, 0);
3271 /* Eliminate all eliminable registers occurring in operands that
3272 can be handled by reload. */
3273 extract_insn (insn);
3274 for (i = 0; i < recog_data.n_operands; i++)
3276 orig_operand[i] = recog_data.operand[i];
3277 substed_operand[i] = recog_data.operand[i];
3279 /* For an asm statement, every operand is eliminable. */
3280 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3282 bool is_set_src, in_plus;
3284 /* Check for setting a register that we know about. */
3285 if (recog_data.operand_type[i] != OP_IN
3286 && REG_P (orig_operand[i]))
3288 /* If we are assigning to a register that can be eliminated, it
3289 must be as part of a PARALLEL, since the code above handles
3290 single SETs. We must indicate that we can no longer
3291 eliminate this reg. */
3292 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3294 if (ep->from_rtx == orig_operand[i])
3295 ep->can_eliminate = 0;
3298 /* Companion to the above plus substitution, we can allow
3299 invariants as the source of a plain move. */
3301 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3305 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3306 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3310 = eliminate_regs_1 (recog_data.operand[i], 0,
3311 replace ? insn : NULL_RTX,
3312 is_set_src || in_plus);
3313 if (substed_operand[i] != orig_operand[i])
3315 /* Terminate the search in check_eliminable_occurrences at
3317 *recog_data.operand_loc[i] = 0;
3319 /* If an output operand changed from a REG to a MEM and INSN is an
3320 insn, write a CLOBBER insn. */
3321 if (recog_data.operand_type[i] != OP_IN
3322 && REG_P (orig_operand[i])
3323 && MEM_P (substed_operand[i])
3325 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3330 for (i = 0; i < recog_data.n_dups; i++)
3331 *recog_data.dup_loc[i]
3332 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3334 /* If any eliminable remain, they aren't eliminable anymore. */
3335 check_eliminable_occurrences (old_body);
3337 /* Substitute the operands; the new values are in the substed_operand
3339 for (i = 0; i < recog_data.n_operands; i++)
3340 *recog_data.operand_loc[i] = substed_operand[i];
3341 for (i = 0; i < recog_data.n_dups; i++)
3342 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3344 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3345 re-recognize the insn. We do this in case we had a simple addition
3346 but now can do this as a load-address. This saves an insn in this
3348 If re-recognition fails, the old insn code number will still be used,
3349 and some register operands may have changed into PLUS expressions.
3350 These will be handled by find_reloads by loading them into a register
3355 /* If we aren't replacing things permanently and we changed something,
3356 make another copy to ensure that all the RTL is new. Otherwise
3357 things can go wrong if find_reload swaps commutative operands
3358 and one is inside RTL that has been copied while the other is not. */
3359 new_body = old_body;
3362 new_body = copy_insn (old_body);
3363 if (REG_NOTES (insn))
3364 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3366 PATTERN (insn) = new_body;
3368 /* If we had a move insn but now we don't, rerecognize it. This will
3369 cause spurious re-recognition if the old move had a PARALLEL since
3370 the new one still will, but we can't call single_set without
3371 having put NEW_BODY into the insn and the re-recognition won't
3372 hurt in this rare case. */
3373 /* ??? Why this huge if statement - why don't we just rerecognize the
3377 && ((REG_P (SET_SRC (old_set))
3378 && (GET_CODE (new_body) != SET
3379 || !REG_P (SET_SRC (new_body))))
3380 /* If this was a load from or store to memory, compare
3381 the MEM in recog_data.operand to the one in the insn.
3382 If they are not equal, then rerecognize the insn. */
3384 && ((MEM_P (SET_SRC (old_set))
3385 && SET_SRC (old_set) != recog_data.operand[1])
3386 || (MEM_P (SET_DEST (old_set))
3387 && SET_DEST (old_set) != recog_data.operand[0])))
3388 /* If this was an add insn before, rerecognize. */
3389 || GET_CODE (SET_SRC (old_set)) == PLUS))
3391 int new_icode = recog (PATTERN (insn), insn, 0);
3393 INSN_CODE (insn) = new_icode;
3397 /* Restore the old body. If there were any changes to it, we made a copy
3398 of it while the changes were still in place, so we'll correctly return
3399 a modified insn below. */
3402 /* Restore the old body. */
3403 for (i = 0; i < recog_data.n_operands; i++)
3404 *recog_data.operand_loc[i] = orig_operand[i];
3405 for (i = 0; i < recog_data.n_dups; i++)
3406 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3409 /* Update all elimination pairs to reflect the status after the current
3410 insn. The changes we make were determined by the earlier call to
3411 elimination_effects.
3413 We also detect cases where register elimination cannot be done,
3414 namely, if a register would be both changed and referenced outside a MEM
3415 in the resulting insn since such an insn is often undefined and, even if
3416 not, we cannot know what meaning will be given to it. Note that it is
3417 valid to have a register used in an address in an insn that changes it
3418 (presumably with a pre- or post-increment or decrement).
3420 If anything changes, return nonzero. */
3422 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3424 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3425 ep->can_eliminate = 0;
3427 ep->ref_outside_mem = 0;
3429 if (ep->previous_offset != ep->offset)
3434 /* If we changed something, perform elimination in REG_NOTES. This is
3435 needed even when REPLACE is zero because a REG_DEAD note might refer
3436 to a register that we eliminate and could cause a different number
3437 of spill registers to be needed in the final reload pass than in
3439 if (val && REG_NOTES (insn) != 0)
3441 = eliminate_regs_1 (REG_NOTES (insn), 0, REG_NOTES (insn), true);
3446 /* Loop through all elimination pairs.
3447 Recalculate the number not at initial offset.
3449 Compute the maximum offset (minimum offset if the stack does not
3450 grow downward) for each elimination pair. */
3453 update_eliminable_offsets (void)
3455 struct elim_table *ep;
3457 num_not_at_initial_offset = 0;
3458 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3460 ep->previous_offset = ep->offset;
3461 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3462 num_not_at_initial_offset++;
3466 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3467 replacement we currently believe is valid, mark it as not eliminable if X
3468 modifies DEST in any way other than by adding a constant integer to it.
3470 If DEST is the frame pointer, we do nothing because we assume that
3471 all assignments to the hard frame pointer are nonlocal gotos and are being
3472 done at a time when they are valid and do not disturb anything else.
3473 Some machines want to eliminate a fake argument pointer with either the
3474 frame or stack pointer. Assignments to the hard frame pointer must not
3475 prevent this elimination.
3477 Called via note_stores from reload before starting its passes to scan
3478 the insns of the function. */
3481 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3485 /* A SUBREG of a hard register here is just changing its mode. We should
3486 not see a SUBREG of an eliminable hard register, but check just in
3488 if (GET_CODE (dest) == SUBREG)
3489 dest = SUBREG_REG (dest);
3491 if (dest == hard_frame_pointer_rtx)
3494 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3495 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3496 && (GET_CODE (x) != SET
3497 || GET_CODE (SET_SRC (x)) != PLUS
3498 || XEXP (SET_SRC (x), 0) != dest
3499 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3501 reg_eliminate[i].can_eliminate_previous
3502 = reg_eliminate[i].can_eliminate = 0;
3507 /* Verify that the initial elimination offsets did not change since the
3508 last call to set_initial_elim_offsets. This is used to catch cases
3509 where something illegal happened during reload_as_needed that could
3510 cause incorrect code to be generated if we did not check for it. */
3513 verify_initial_elim_offsets (void)
3517 if (!num_eliminable)
3520 #ifdef ELIMINABLE_REGS
3522 struct elim_table *ep;
3524 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3526 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3527 if (t != ep->initial_offset)
3532 INITIAL_FRAME_POINTER_OFFSET (t);
3533 if (t != reg_eliminate[0].initial_offset)
3540 /* Reset all offsets on eliminable registers to their initial values. */
3543 set_initial_elim_offsets (void)
3545 struct elim_table *ep = reg_eliminate;
3547 #ifdef ELIMINABLE_REGS
3548 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3550 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3551 ep->previous_offset = ep->offset = ep->initial_offset;
3554 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3555 ep->previous_offset = ep->offset = ep->initial_offset;
3558 num_not_at_initial_offset = 0;
3561 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3564 set_initial_eh_label_offset (rtx label)
3566 set_label_offsets (label, NULL_RTX, 1);
3569 /* Initialize the known label offsets.
3570 Set a known offset for each forced label to be at the initial offset
3571 of each elimination. We do this because we assume that all
3572 computed jumps occur from a location where each elimination is
3573 at its initial offset.
3574 For all other labels, show that we don't know the offsets. */
3577 set_initial_label_offsets (void)
3580 memset (offsets_known_at, 0, num_labels);
3582 for (x = forced_labels; x; x = XEXP (x, 1))
3584 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3586 for_each_eh_label (set_initial_eh_label_offset);
3589 /* Set all elimination offsets to the known values for the code label given
3593 set_offsets_for_label (rtx insn)
3596 int label_nr = CODE_LABEL_NUMBER (insn);
3597 struct elim_table *ep;
3599 num_not_at_initial_offset = 0;
3600 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3602 ep->offset = ep->previous_offset
3603 = offsets_at[label_nr - first_label_num][i];
3604 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3605 num_not_at_initial_offset++;
3609 /* See if anything that happened changes which eliminations are valid.
3610 For example, on the SPARC, whether or not the frame pointer can
3611 be eliminated can depend on what registers have been used. We need
3612 not check some conditions again (such as flag_omit_frame_pointer)
3613 since they can't have changed. */
3616 update_eliminables (HARD_REG_SET *pset)
3618 int previous_frame_pointer_needed = frame_pointer_needed;
3619 struct elim_table *ep;
3621 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3622 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3623 #ifdef ELIMINABLE_REGS
3624 || ! CAN_ELIMINATE (ep->from, ep->to)
3627 ep->can_eliminate = 0;
3629 /* Look for the case where we have discovered that we can't replace
3630 register A with register B and that means that we will now be
3631 trying to replace register A with register C. This means we can
3632 no longer replace register C with register B and we need to disable
3633 such an elimination, if it exists. This occurs often with A == ap,
3634 B == sp, and C == fp. */
3636 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3638 struct elim_table *op;
3641 if (! ep->can_eliminate && ep->can_eliminate_previous)
3643 /* Find the current elimination for ep->from, if there is a
3645 for (op = reg_eliminate;
3646 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3647 if (op->from == ep->from && op->can_eliminate)
3653 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3655 for (op = reg_eliminate;
3656 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3657 if (op->from == new_to && op->to == ep->to)
3658 op->can_eliminate = 0;
3662 /* See if any registers that we thought we could eliminate the previous
3663 time are no longer eliminable. If so, something has changed and we
3664 must spill the register. Also, recompute the number of eliminable
3665 registers and see if the frame pointer is needed; it is if there is
3666 no elimination of the frame pointer that we can perform. */
3668 frame_pointer_needed = 1;
3669 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3671 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3672 && ep->to != HARD_FRAME_POINTER_REGNUM)
3673 frame_pointer_needed = 0;
3675 if (! ep->can_eliminate && ep->can_eliminate_previous)
3677 ep->can_eliminate_previous = 0;
3678 SET_HARD_REG_BIT (*pset, ep->from);
3683 /* If we didn't need a frame pointer last time, but we do now, spill
3684 the hard frame pointer. */
3685 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3686 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3689 /* Return true if X is used as the target register of an elimination. */
3692 elimination_target_reg_p (rtx x)
3694 struct elim_table *ep;
3696 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3697 if (ep->to_rtx == x && ep->can_eliminate)
3703 /* Initialize the table of registers to eliminate. */
3706 init_elim_table (void)
3708 struct elim_table *ep;
3709 #ifdef ELIMINABLE_REGS
3710 const struct elim_table_1 *ep1;
3714 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3716 /* Does this function require a frame pointer? */
3718 frame_pointer_needed = (! flag_omit_frame_pointer
3719 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3720 and restore sp for alloca. So we can't eliminate
3721 the frame pointer in that case. At some point,
3722 we should improve this by emitting the
3723 sp-adjusting insns for this case. */
3724 || (cfun->calls_alloca
3725 && EXIT_IGNORE_STACK)
3726 || crtl->accesses_prior_frames
3727 || FRAME_POINTER_REQUIRED);
3731 #ifdef ELIMINABLE_REGS
3732 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3733 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3735 ep->from = ep1->from;
3737 ep->can_eliminate = ep->can_eliminate_previous
3738 = (CAN_ELIMINATE (ep->from, ep->to)
3739 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3742 reg_eliminate[0].from = reg_eliminate_1[0].from;
3743 reg_eliminate[0].to = reg_eliminate_1[0].to;
3744 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3745 = ! frame_pointer_needed;
3748 /* Count the number of eliminable registers and build the FROM and TO
3749 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3750 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3751 We depend on this. */
3752 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3754 num_eliminable += ep->can_eliminate;
3755 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3756 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3760 /* Kick all pseudos out of hard register REGNO.
3762 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3763 because we found we can't eliminate some register. In the case, no pseudos
3764 are allowed to be in the register, even if they are only in a block that
3765 doesn't require spill registers, unlike the case when we are spilling this
3766 hard reg to produce another spill register.
3768 Return nonzero if any pseudos needed to be kicked out. */
3771 spill_hard_reg (unsigned int regno, int cant_eliminate)
3777 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3778 df_set_regs_ever_live (regno, true);
3781 /* Spill every pseudo reg that was allocated to this reg
3782 or to something that overlaps this reg. */
3784 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3785 if (reg_renumber[i] >= 0
3786 && (unsigned int) reg_renumber[i] <= regno
3787 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
3788 SET_REGNO_REG_SET (&spilled_pseudos, i);
3791 /* After find_reload_regs has been run for all insn that need reloads,
3792 and/or spill_hard_regs was called, this function is used to actually
3793 spill pseudo registers and try to reallocate them. It also sets up the
3794 spill_regs array for use by choose_reload_regs. */
3797 finish_spills (int global)
3799 struct insn_chain *chain;
3800 int something_changed = 0;
3802 reg_set_iterator rsi;
3804 /* Build the spill_regs array for the function. */
3805 /* If there are some registers still to eliminate and one of the spill regs
3806 wasn't ever used before, additional stack space may have to be
3807 allocated to store this register. Thus, we may have changed the offset
3808 between the stack and frame pointers, so mark that something has changed.
3810 One might think that we need only set VAL to 1 if this is a call-used
3811 register. However, the set of registers that must be saved by the
3812 prologue is not identical to the call-used set. For example, the
3813 register used by the call insn for the return PC is a call-used register,
3814 but must be saved by the prologue. */
3817 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3818 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3820 spill_reg_order[i] = n_spills;
3821 spill_regs[n_spills++] = i;
3822 if (num_eliminable && ! df_regs_ever_live_p (i))
3823 something_changed = 1;
3824 df_set_regs_ever_live (i, true);
3827 spill_reg_order[i] = -1;
3829 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3831 /* Record the current hard register the pseudo is allocated to in
3832 pseudo_previous_regs so we avoid reallocating it to the same
3833 hard reg in a later pass. */
3834 gcc_assert (reg_renumber[i] >= 0);
3836 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3837 /* Mark it as no longer having a hard register home. */
3838 reg_renumber[i] = -1;
3839 /* We will need to scan everything again. */
3840 something_changed = 1;
3843 /* Retry global register allocation if possible. */
3846 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3847 /* For every insn that needs reloads, set the registers used as spill
3848 regs in pseudo_forbidden_regs for every pseudo live across the
3850 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3852 EXECUTE_IF_SET_IN_REG_SET
3853 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3855 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3856 chain->used_spill_regs);
3858 EXECUTE_IF_SET_IN_REG_SET
3859 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3861 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3862 chain->used_spill_regs);
3866 /* Retry allocating the spilled pseudos. For each reg, merge the
3867 various reg sets that indicate which hard regs can't be used,
3868 and call retry_global_alloc.
3869 We change spill_pseudos here to only contain pseudos that did not
3870 get a new hard register. */
3871 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3872 if (reg_old_renumber[i] != reg_renumber[i])
3874 HARD_REG_SET forbidden;
3875 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3876 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3877 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3878 retry_global_alloc (i, forbidden);
3879 if (reg_renumber[i] >= 0)
3880 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3884 /* Fix up the register information in the insn chain.
3885 This involves deleting those of the spilled pseudos which did not get
3886 a new hard register home from the live_{before,after} sets. */
3887 for (chain = reload_insn_chain; chain; chain = chain->next)
3889 HARD_REG_SET used_by_pseudos;
3890 HARD_REG_SET used_by_pseudos2;
3892 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3893 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3895 /* Mark any unallocated hard regs as available for spills. That
3896 makes inheritance work somewhat better. */
3897 if (chain->need_reload)
3899 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3900 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3901 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3903 /* Save the old value for the sanity test below. */
3904 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3906 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3907 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3908 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3909 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3911 /* Make sure we only enlarge the set. */
3912 gcc_assert (hard_reg_set_subset_p (used_by_pseudos2,
3913 chain->used_spill_regs));
3917 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3918 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3920 int regno = reg_renumber[i];
3921 if (reg_old_renumber[i] == regno)
3924 alter_reg (i, reg_old_renumber[i]);
3925 reg_old_renumber[i] = regno;
3929 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3931 fprintf (dump_file, " Register %d now in %d.\n\n",
3932 i, reg_renumber[i]);
3936 return something_changed;
3939 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3942 scan_paradoxical_subregs (rtx x)
3946 enum rtx_code code = GET_CODE (x);
3957 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3965 if (REG_P (SUBREG_REG (x))
3966 && (GET_MODE_SIZE (GET_MODE (x))
3967 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
3969 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3970 = GET_MODE_SIZE (GET_MODE (x));
3971 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
3979 fmt = GET_RTX_FORMAT (code);
3980 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3983 scan_paradoxical_subregs (XEXP (x, i));
3984 else if (fmt[i] == 'E')
3987 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3988 scan_paradoxical_subregs (XVECEXP (x, i, j));
3993 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
3994 examine all of the reload insns between PREV and NEXT exclusive, and
3995 annotate all that may trap. */
3998 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
4000 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4001 unsigned int trap_count;
4007 if (may_trap_p (PATTERN (insn)))
4011 remove_note (insn, note);
4015 for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i))
4016 if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i)))
4020 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (note, 0), REG_NOTES (i));
4024 /* Reload pseudo-registers into hard regs around each insn as needed.
4025 Additional register load insns are output before the insn that needs it
4026 and perhaps store insns after insns that modify the reloaded pseudo reg.
4028 reg_last_reload_reg and reg_reloaded_contents keep track of
4029 which registers are already available in reload registers.
4030 We update these for the reloads that we perform,
4031 as the insns are scanned. */
4034 reload_as_needed (int live_known)
4036 struct insn_chain *chain;
4037 #if defined (AUTO_INC_DEC)
4042 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4043 memset (spill_reg_store, 0, sizeof spill_reg_store);
4044 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4045 INIT_REG_SET (®_has_output_reload);
4046 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4047 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4049 set_initial_elim_offsets ();
4051 for (chain = reload_insn_chain; chain; chain = chain->next)
4054 rtx insn = chain->insn;
4055 rtx old_next = NEXT_INSN (insn);
4057 /* If we pass a label, copy the offsets from the label information
4058 into the current offsets of each elimination. */
4060 set_offsets_for_label (insn);
4062 else if (INSN_P (insn))
4064 regset_head regs_to_forget;
4065 INIT_REG_SET (®s_to_forget);
4066 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4068 /* If this is a USE and CLOBBER of a MEM, ensure that any
4069 references to eliminable registers have been removed. */
4071 if ((GET_CODE (PATTERN (insn)) == USE
4072 || GET_CODE (PATTERN (insn)) == CLOBBER)
4073 && MEM_P (XEXP (PATTERN (insn), 0)))
4074 XEXP (XEXP (PATTERN (insn), 0), 0)
4075 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4076 GET_MODE (XEXP (PATTERN (insn), 0)),
4079 /* If we need to do register elimination processing, do so.
4080 This might delete the insn, in which case we are done. */
4081 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4083 eliminate_regs_in_insn (insn, 1);
4086 update_eliminable_offsets ();
4087 CLEAR_REG_SET (®s_to_forget);
4092 /* If need_elim is nonzero but need_reload is zero, one might think
4093 that we could simply set n_reloads to 0. However, find_reloads
4094 could have done some manipulation of the insn (such as swapping
4095 commutative operands), and these manipulations are lost during
4096 the first pass for every insn that needs register elimination.
4097 So the actions of find_reloads must be redone here. */
4099 if (! chain->need_elim && ! chain->need_reload
4100 && ! chain->need_operand_change)
4102 /* First find the pseudo regs that must be reloaded for this insn.
4103 This info is returned in the tables reload_... (see reload.h).
4104 Also modify the body of INSN by substituting RELOAD
4105 rtx's for those pseudo regs. */
4108 CLEAR_REG_SET (®_has_output_reload);
4109 CLEAR_HARD_REG_SET (reg_is_output_reload);
4111 find_reloads (insn, 1, spill_indirect_levels, live_known,
4117 rtx next = NEXT_INSN (insn);
4120 prev = PREV_INSN (insn);
4122 /* Now compute which reload regs to reload them into. Perhaps
4123 reusing reload regs from previous insns, or else output
4124 load insns to reload them. Maybe output store insns too.
4125 Record the choices of reload reg in reload_reg_rtx. */
4126 choose_reload_regs (chain);
4128 /* Merge any reloads that we didn't combine for fear of
4129 increasing the number of spill registers needed but now
4130 discover can be safely merged. */
4131 if (SMALL_REGISTER_CLASSES)
4132 merge_assigned_reloads (insn);
4134 /* Generate the insns to reload operands into or out of
4135 their reload regs. */
4136 emit_reload_insns (chain);
4138 /* Substitute the chosen reload regs from reload_reg_rtx
4139 into the insn's body (or perhaps into the bodies of other
4140 load and store insn that we just made for reloading
4141 and that we moved the structure into). */
4142 subst_reloads (insn);
4144 /* Adjust the exception region notes for loads and stores. */
4145 if (flag_non_call_exceptions && !CALL_P (insn))
4146 fixup_eh_region_note (insn, prev, next);
4148 /* If this was an ASM, make sure that all the reload insns
4149 we have generated are valid. If not, give an error
4151 if (asm_noperands (PATTERN (insn)) >= 0)
4152 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4153 if (p != insn && INSN_P (p)
4154 && GET_CODE (PATTERN (p)) != USE
4155 && (recog_memoized (p) < 0
4156 || (extract_insn (p), ! constrain_operands (1))))
4158 error_for_asm (insn,
4159 "%<asm%> operand requires "
4160 "impossible reload");
4165 if (num_eliminable && chain->need_elim)
4166 update_eliminable_offsets ();
4168 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4169 is no longer validly lying around to save a future reload.
4170 Note that this does not detect pseudos that were reloaded
4171 for this insn in order to be stored in
4172 (obeying register constraints). That is correct; such reload
4173 registers ARE still valid. */
4174 forget_marked_reloads (®s_to_forget);
4175 CLEAR_REG_SET (®s_to_forget);
4177 /* There may have been CLOBBER insns placed after INSN. So scan
4178 between INSN and NEXT and use them to forget old reloads. */
4179 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4180 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4181 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4184 /* Likewise for regs altered by auto-increment in this insn.
4185 REG_INC notes have been changed by reloading:
4186 find_reloads_address_1 records substitutions for them,
4187 which have been performed by subst_reloads above. */
4188 for (i = n_reloads - 1; i >= 0; i--)
4190 rtx in_reg = rld[i].in_reg;
4193 enum rtx_code code = GET_CODE (in_reg);
4194 /* PRE_INC / PRE_DEC will have the reload register ending up
4195 with the same value as the stack slot, but that doesn't
4196 hold true for POST_INC / POST_DEC. Either we have to
4197 convert the memory access to a true POST_INC / POST_DEC,
4198 or we can't use the reload register for inheritance. */
4199 if ((code == POST_INC || code == POST_DEC)
4200 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4201 REGNO (rld[i].reg_rtx))
4202 /* Make sure it is the inc/dec pseudo, and not
4203 some other (e.g. output operand) pseudo. */
4204 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4205 == REGNO (XEXP (in_reg, 0))))
4208 rtx reload_reg = rld[i].reg_rtx;
4209 enum machine_mode mode = GET_MODE (reload_reg);
4213 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4215 /* We really want to ignore REG_INC notes here, so
4216 use PATTERN (p) as argument to reg_set_p . */
4217 if (reg_set_p (reload_reg, PATTERN (p)))
4219 n = count_occurrences (PATTERN (p), reload_reg, 0);
4224 n = validate_replace_rtx (reload_reg,
4225 gen_rtx_fmt_e (code,
4230 /* We must also verify that the constraints
4231 are met after the replacement. */
4234 n = constrain_operands (1);
4238 /* If the constraints were not met, then
4239 undo the replacement. */
4242 validate_replace_rtx (gen_rtx_fmt_e (code,
4255 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4257 /* Mark this as having an output reload so that the
4258 REG_INC processing code below won't invalidate
4259 the reload for inheritance. */
4260 SET_HARD_REG_BIT (reg_is_output_reload,
4261 REGNO (reload_reg));
4262 SET_REGNO_REG_SET (®_has_output_reload,
4263 REGNO (XEXP (in_reg, 0)));
4266 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4269 else if ((code == PRE_INC || code == PRE_DEC)
4270 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4271 REGNO (rld[i].reg_rtx))
4272 /* Make sure it is the inc/dec pseudo, and not
4273 some other (e.g. output operand) pseudo. */
4274 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4275 == REGNO (XEXP (in_reg, 0))))
4277 SET_HARD_REG_BIT (reg_is_output_reload,
4278 REGNO (rld[i].reg_rtx));
4279 SET_REGNO_REG_SET (®_has_output_reload,
4280 REGNO (XEXP (in_reg, 0)));
4284 /* If a pseudo that got a hard register is auto-incremented,
4285 we must purge records of copying it into pseudos without
4287 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4288 if (REG_NOTE_KIND (x) == REG_INC)
4290 /* See if this pseudo reg was reloaded in this insn.
4291 If so, its last-reload info is still valid
4292 because it is based on this insn's reload. */
4293 for (i = 0; i < n_reloads; i++)
4294 if (rld[i].out == XEXP (x, 0))
4298 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4302 /* A reload reg's contents are unknown after a label. */
4304 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4306 /* Don't assume a reload reg is still good after a call insn
4307 if it is a call-used reg, or if it contains a value that will
4308 be partially clobbered by the call. */
4309 else if (CALL_P (insn))
4311 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4312 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4317 free (reg_last_reload_reg);
4318 CLEAR_REG_SET (®_has_output_reload);
4321 /* Discard all record of any value reloaded from X,
4322 or reloaded in X from someplace else;
4323 unless X is an output reload reg of the current insn.
4325 X may be a hard reg (the reload reg)
4326 or it may be a pseudo reg that was reloaded from.
4328 When DATA is non-NULL just mark the registers in regset
4329 to be forgotten later. */
4332 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4337 regset regs = (regset) data;
4339 /* note_stores does give us subregs of hard regs,
4340 subreg_regno_offset requires a hard reg. */
4341 while (GET_CODE (x) == SUBREG)
4343 /* We ignore the subreg offset when calculating the regno,
4344 because we are using the entire underlying hard register
4354 if (regno >= FIRST_PSEUDO_REGISTER)
4360 nr = hard_regno_nregs[regno][GET_MODE (x)];
4361 /* Storing into a spilled-reg invalidates its contents.
4362 This can happen if a block-local pseudo is allocated to that reg
4363 and it wasn't spilled because this block's total need is 0.
4364 Then some insn might have an optional reload and use this reg. */
4366 for (i = 0; i < nr; i++)
4367 /* But don't do this if the reg actually serves as an output
4368 reload reg in the current instruction. */
4370 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4372 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4373 spill_reg_store[regno + i] = 0;
4379 SET_REGNO_REG_SET (regs, regno + nr);
4382 /* Since value of X has changed,
4383 forget any value previously copied from it. */
4386 /* But don't forget a copy if this is the output reload
4387 that establishes the copy's validity. */
4389 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4390 reg_last_reload_reg[regno + nr] = 0;
4394 /* Forget the reloads marked in regset by previous function. */
4396 forget_marked_reloads (regset regs)
4399 reg_set_iterator rsi;
4400 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4402 if (reg < FIRST_PSEUDO_REGISTER
4403 /* But don't do this if the reg actually serves as an output
4404 reload reg in the current instruction. */
4406 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4408 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4409 spill_reg_store[reg] = 0;
4412 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4413 reg_last_reload_reg[reg] = 0;
4417 /* The following HARD_REG_SETs indicate when each hard register is
4418 used for a reload of various parts of the current insn. */
4420 /* If reg is unavailable for all reloads. */
4421 static HARD_REG_SET reload_reg_unavailable;
4422 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4423 static HARD_REG_SET reload_reg_used;
4424 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4425 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4426 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4427 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4428 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4429 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4430 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4431 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4432 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4433 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4434 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4435 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4436 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4437 static HARD_REG_SET reload_reg_used_in_op_addr;
4438 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4439 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4440 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4441 static HARD_REG_SET reload_reg_used_in_insn;
4442 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4443 static HARD_REG_SET reload_reg_used_in_other_addr;
4445 /* If reg is in use as a reload reg for any sort of reload. */
4446 static HARD_REG_SET reload_reg_used_at_all;
4448 /* If reg is use as an inherited reload. We just mark the first register
4450 static HARD_REG_SET reload_reg_used_for_inherit;
4452 /* Records which hard regs are used in any way, either as explicit use or
4453 by being allocated to a pseudo during any point of the current insn. */
4454 static HARD_REG_SET reg_used_in_insn;
4456 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4457 TYPE. MODE is used to indicate how many consecutive regs are
4461 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4462 enum machine_mode mode)
4464 unsigned int nregs = hard_regno_nregs[regno][mode];
4467 for (i = regno; i < nregs + regno; i++)
4472 SET_HARD_REG_BIT (reload_reg_used, i);
4475 case RELOAD_FOR_INPUT_ADDRESS:
4476 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4479 case RELOAD_FOR_INPADDR_ADDRESS:
4480 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4483 case RELOAD_FOR_OUTPUT_ADDRESS:
4484 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4487 case RELOAD_FOR_OUTADDR_ADDRESS:
4488 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4491 case RELOAD_FOR_OPERAND_ADDRESS:
4492 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4495 case RELOAD_FOR_OPADDR_ADDR:
4496 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4499 case RELOAD_FOR_OTHER_ADDRESS:
4500 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4503 case RELOAD_FOR_INPUT:
4504 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4507 case RELOAD_FOR_OUTPUT:
4508 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4511 case RELOAD_FOR_INSN:
4512 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4516 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4520 /* Similarly, but show REGNO is no longer in use for a reload. */
4523 clear_reload_reg_in_use (unsigned int regno, int opnum,
4524 enum reload_type type, enum machine_mode mode)
4526 unsigned int nregs = hard_regno_nregs[regno][mode];
4527 unsigned int start_regno, end_regno, r;
4529 /* A complication is that for some reload types, inheritance might
4530 allow multiple reloads of the same types to share a reload register.
4531 We set check_opnum if we have to check only reloads with the same
4532 operand number, and check_any if we have to check all reloads. */
4533 int check_opnum = 0;
4535 HARD_REG_SET *used_in_set;
4540 used_in_set = &reload_reg_used;
4543 case RELOAD_FOR_INPUT_ADDRESS:
4544 used_in_set = &reload_reg_used_in_input_addr[opnum];
4547 case RELOAD_FOR_INPADDR_ADDRESS:
4549 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4552 case RELOAD_FOR_OUTPUT_ADDRESS:
4553 used_in_set = &reload_reg_used_in_output_addr[opnum];
4556 case RELOAD_FOR_OUTADDR_ADDRESS:
4558 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4561 case RELOAD_FOR_OPERAND_ADDRESS:
4562 used_in_set = &reload_reg_used_in_op_addr;
4565 case RELOAD_FOR_OPADDR_ADDR:
4567 used_in_set = &reload_reg_used_in_op_addr_reload;
4570 case RELOAD_FOR_OTHER_ADDRESS:
4571 used_in_set = &reload_reg_used_in_other_addr;
4575 case RELOAD_FOR_INPUT:
4576 used_in_set = &reload_reg_used_in_input[opnum];
4579 case RELOAD_FOR_OUTPUT:
4580 used_in_set = &reload_reg_used_in_output[opnum];
4583 case RELOAD_FOR_INSN:
4584 used_in_set = &reload_reg_used_in_insn;
4589 /* We resolve conflicts with remaining reloads of the same type by
4590 excluding the intervals of reload registers by them from the
4591 interval of freed reload registers. Since we only keep track of
4592 one set of interval bounds, we might have to exclude somewhat
4593 more than what would be necessary if we used a HARD_REG_SET here.
4594 But this should only happen very infrequently, so there should
4595 be no reason to worry about it. */
4597 start_regno = regno;
4598 end_regno = regno + nregs;
4599 if (check_opnum || check_any)
4601 for (i = n_reloads - 1; i >= 0; i--)
4603 if (rld[i].when_needed == type
4604 && (check_any || rld[i].opnum == opnum)
4607 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4608 unsigned int conflict_end
4609 = end_hard_regno (rld[i].mode, conflict_start);
4611 /* If there is an overlap with the first to-be-freed register,
4612 adjust the interval start. */
4613 if (conflict_start <= start_regno && conflict_end > start_regno)
4614 start_regno = conflict_end;
4615 /* Otherwise, if there is a conflict with one of the other
4616 to-be-freed registers, adjust the interval end. */
4617 if (conflict_start > start_regno && conflict_start < end_regno)
4618 end_regno = conflict_start;
4623 for (r = start_regno; r < end_regno; r++)
4624 CLEAR_HARD_REG_BIT (*used_in_set, r);
4627 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4628 specified by OPNUM and TYPE. */
4631 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4635 /* In use for a RELOAD_OTHER means it's not available for anything. */
4636 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4637 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4643 /* In use for anything means we can't use it for RELOAD_OTHER. */
4644 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4645 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4646 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4647 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4650 for (i = 0; i < reload_n_operands; i++)
4651 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4652 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4653 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4654 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4655 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4656 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4661 case RELOAD_FOR_INPUT:
4662 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4663 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4666 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4669 /* If it is used for some other input, can't use it. */
4670 for (i = 0; i < reload_n_operands; i++)
4671 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4674 /* If it is used in a later operand's address, can't use it. */
4675 for (i = opnum + 1; i < reload_n_operands; i++)
4676 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4677 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4682 case RELOAD_FOR_INPUT_ADDRESS:
4683 /* Can't use a register if it is used for an input address for this
4684 operand or used as an input in an earlier one. */
4685 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4686 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4689 for (i = 0; i < opnum; i++)
4690 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4695 case RELOAD_FOR_INPADDR_ADDRESS:
4696 /* Can't use a register if it is used for an input address
4697 for this operand or used as an input in an earlier
4699 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4702 for (i = 0; i < opnum; i++)
4703 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4708 case RELOAD_FOR_OUTPUT_ADDRESS:
4709 /* Can't use a register if it is used for an output address for this
4710 operand or used as an output in this or a later operand. Note
4711 that multiple output operands are emitted in reverse order, so
4712 the conflicting ones are those with lower indices. */
4713 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4716 for (i = 0; i <= opnum; i++)
4717 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4722 case RELOAD_FOR_OUTADDR_ADDRESS:
4723 /* Can't use a register if it is used for an output address
4724 for this operand or used as an output in this or a
4725 later operand. Note that multiple output operands are
4726 emitted in reverse order, so the conflicting ones are
4727 those with lower indices. */
4728 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4731 for (i = 0; i <= opnum; i++)
4732 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4737 case RELOAD_FOR_OPERAND_ADDRESS:
4738 for (i = 0; i < reload_n_operands; i++)
4739 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4742 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4743 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4745 case RELOAD_FOR_OPADDR_ADDR:
4746 for (i = 0; i < reload_n_operands; i++)
4747 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4750 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4752 case RELOAD_FOR_OUTPUT:
4753 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4754 outputs, or an operand address for this or an earlier output.
4755 Note that multiple output operands are emitted in reverse order,
4756 so the conflicting ones are those with higher indices. */
4757 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4760 for (i = 0; i < reload_n_operands; i++)
4761 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4764 for (i = opnum; i < reload_n_operands; i++)
4765 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4766 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4771 case RELOAD_FOR_INSN:
4772 for (i = 0; i < reload_n_operands; i++)
4773 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4774 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4777 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4778 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4780 case RELOAD_FOR_OTHER_ADDRESS:
4781 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4788 /* Return 1 if the value in reload reg REGNO, as used by a reload
4789 needed for the part of the insn specified by OPNUM and TYPE,
4790 is still available in REGNO at the end of the insn.
4792 We can assume that the reload reg was already tested for availability
4793 at the time it is needed, and we should not check this again,
4794 in case the reg has already been marked in use. */
4797 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4804 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4805 its value must reach the end. */
4808 /* If this use is for part of the insn,
4809 its value reaches if no subsequent part uses the same register.
4810 Just like the above function, don't try to do this with lots
4813 case RELOAD_FOR_OTHER_ADDRESS:
4814 /* Here we check for everything else, since these don't conflict
4815 with anything else and everything comes later. */
4817 for (i = 0; i < reload_n_operands; i++)
4818 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4819 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4820 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4821 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4822 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4823 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4826 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4827 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4828 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4829 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4831 case RELOAD_FOR_INPUT_ADDRESS:
4832 case RELOAD_FOR_INPADDR_ADDRESS:
4833 /* Similar, except that we check only for this and subsequent inputs
4834 and the address of only subsequent inputs and we do not need
4835 to check for RELOAD_OTHER objects since they are known not to
4838 for (i = opnum; i < reload_n_operands; i++)
4839 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4842 for (i = opnum + 1; i < reload_n_operands; i++)
4843 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4844 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4847 for (i = 0; i < reload_n_operands; i++)
4848 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4849 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4850 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4853 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4856 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4857 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4858 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4860 case RELOAD_FOR_INPUT:
4861 /* Similar to input address, except we start at the next operand for
4862 both input and input address and we do not check for
4863 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4866 for (i = opnum + 1; i < reload_n_operands; i++)
4867 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4868 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4869 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4872 /* ... fall through ... */
4874 case RELOAD_FOR_OPERAND_ADDRESS:
4875 /* Check outputs and their addresses. */
4877 for (i = 0; i < reload_n_operands; i++)
4878 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4879 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4880 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4883 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4885 case RELOAD_FOR_OPADDR_ADDR:
4886 for (i = 0; i < reload_n_operands; i++)
4887 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4888 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4889 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4892 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4893 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4894 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4896 case RELOAD_FOR_INSN:
4897 /* These conflict with other outputs with RELOAD_OTHER. So
4898 we need only check for output addresses. */
4900 opnum = reload_n_operands;
4902 /* ... fall through ... */
4904 case RELOAD_FOR_OUTPUT:
4905 case RELOAD_FOR_OUTPUT_ADDRESS:
4906 case RELOAD_FOR_OUTADDR_ADDRESS:
4907 /* We already know these can't conflict with a later output. So the
4908 only thing to check are later output addresses.
4909 Note that multiple output operands are emitted in reverse order,
4910 so the conflicting ones are those with lower indices. */
4911 for (i = 0; i < opnum; i++)
4912 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4913 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4923 /* Like reload_reg_reaches_end_p, but check that the condition holds for
4924 every register in the range [REGNO, REGNO + NREGS). */
4927 reload_regs_reach_end_p (unsigned int regno, int nregs,
4928 int opnum, enum reload_type type)
4932 for (i = 0; i < nregs; i++)
4933 if (!reload_reg_reaches_end_p (regno + i, opnum, type))
4939 /* Returns whether R1 and R2 are uniquely chained: the value of one
4940 is used by the other, and that value is not used by any other
4941 reload for this insn. This is used to partially undo the decision
4942 made in find_reloads when in the case of multiple
4943 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
4944 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
4945 reloads. This code tries to avoid the conflict created by that
4946 change. It might be cleaner to explicitly keep track of which
4947 RELOAD_FOR_OPADDR_ADDR reload is associated with which
4948 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
4949 this after the fact. */
4951 reloads_unique_chain_p (int r1, int r2)
4955 /* We only check input reloads. */
4956 if (! rld[r1].in || ! rld[r2].in)
4959 /* Avoid anything with output reloads. */
4960 if (rld[r1].out || rld[r2].out)
4963 /* "chained" means one reload is a component of the other reload,
4964 not the same as the other reload. */
4965 if (rld[r1].opnum != rld[r2].opnum
4966 || rtx_equal_p (rld[r1].in, rld[r2].in)
4967 || rld[r1].optional || rld[r2].optional
4968 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
4969 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
4972 for (i = 0; i < n_reloads; i ++)
4973 /* Look for input reloads that aren't our two */
4974 if (i != r1 && i != r2 && rld[i].in)
4976 /* If our reload is mentioned at all, it isn't a simple chain. */
4977 if (reg_mentioned_p (rld[r1].in, rld[i].in))
4983 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4986 This function uses the same algorithm as reload_reg_free_p above. */
4989 reloads_conflict (int r1, int r2)
4991 enum reload_type r1_type = rld[r1].when_needed;
4992 enum reload_type r2_type = rld[r2].when_needed;
4993 int r1_opnum = rld[r1].opnum;
4994 int r2_opnum = rld[r2].opnum;
4996 /* RELOAD_OTHER conflicts with everything. */
4997 if (r2_type == RELOAD_OTHER)
5000 /* Otherwise, check conflicts differently for each type. */
5004 case RELOAD_FOR_INPUT:
5005 return (r2_type == RELOAD_FOR_INSN
5006 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5007 || r2_type == RELOAD_FOR_OPADDR_ADDR
5008 || r2_type == RELOAD_FOR_INPUT
5009 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5010 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5011 && r2_opnum > r1_opnum));
5013 case RELOAD_FOR_INPUT_ADDRESS:
5014 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5015 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5017 case RELOAD_FOR_INPADDR_ADDRESS:
5018 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5019 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5021 case RELOAD_FOR_OUTPUT_ADDRESS:
5022 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5023 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5025 case RELOAD_FOR_OUTADDR_ADDRESS:
5026 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5027 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5029 case RELOAD_FOR_OPERAND_ADDRESS:
5030 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5031 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5032 && !reloads_unique_chain_p (r1, r2)));
5034 case RELOAD_FOR_OPADDR_ADDR:
5035 return (r2_type == RELOAD_FOR_INPUT
5036 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5038 case RELOAD_FOR_OUTPUT:
5039 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5040 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5041 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5042 && r2_opnum >= r1_opnum));
5044 case RELOAD_FOR_INSN:
5045 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5046 || r2_type == RELOAD_FOR_INSN
5047 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5049 case RELOAD_FOR_OTHER_ADDRESS:
5050 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5060 /* Indexed by reload number, 1 if incoming value
5061 inherited from previous insns. */
5062 static char reload_inherited[MAX_RELOADS];
5064 /* For an inherited reload, this is the insn the reload was inherited from,
5065 if we know it. Otherwise, this is 0. */
5066 static rtx reload_inheritance_insn[MAX_RELOADS];
5068 /* If nonzero, this is a place to get the value of the reload,
5069 rather than using reload_in. */
5070 static rtx reload_override_in[MAX_RELOADS];
5072 /* For each reload, the hard register number of the register used,
5073 or -1 if we did not need a register for this reload. */
5074 static int reload_spill_index[MAX_RELOADS];
5076 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5077 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5079 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5080 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5082 /* Subroutine of free_for_value_p, used to check a single register.
5083 START_REGNO is the starting regno of the full reload register
5084 (possibly comprising multiple hard registers) that we are considering. */
5087 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5088 enum reload_type type, rtx value, rtx out,
5089 int reloadnum, int ignore_address_reloads)
5092 /* Set if we see an input reload that must not share its reload register
5093 with any new earlyclobber, but might otherwise share the reload
5094 register with an output or input-output reload. */
5095 int check_earlyclobber = 0;
5099 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5102 if (out == const0_rtx)
5108 /* We use some pseudo 'time' value to check if the lifetimes of the
5109 new register use would overlap with the one of a previous reload
5110 that is not read-only or uses a different value.
5111 The 'time' used doesn't have to be linear in any shape or form, just
5113 Some reload types use different 'buckets' for each operand.
5114 So there are MAX_RECOG_OPERANDS different time values for each
5116 We compute TIME1 as the time when the register for the prospective
5117 new reload ceases to be live, and TIME2 for each existing
5118 reload as the time when that the reload register of that reload
5120 Where there is little to be gained by exact lifetime calculations,
5121 we just make conservative assumptions, i.e. a longer lifetime;
5122 this is done in the 'default:' cases. */
5125 case RELOAD_FOR_OTHER_ADDRESS:
5126 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5127 time1 = copy ? 0 : 1;
5130 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5132 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5133 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5134 respectively, to the time values for these, we get distinct time
5135 values. To get distinct time values for each operand, we have to
5136 multiply opnum by at least three. We round that up to four because
5137 multiply by four is often cheaper. */
5138 case RELOAD_FOR_INPADDR_ADDRESS:
5139 time1 = opnum * 4 + 2;
5141 case RELOAD_FOR_INPUT_ADDRESS:
5142 time1 = opnum * 4 + 3;
5144 case RELOAD_FOR_INPUT:
5145 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5146 executes (inclusive). */
5147 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5149 case RELOAD_FOR_OPADDR_ADDR:
5151 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5152 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5154 case RELOAD_FOR_OPERAND_ADDRESS:
5155 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5157 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5159 case RELOAD_FOR_OUTADDR_ADDRESS:
5160 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5162 case RELOAD_FOR_OUTPUT_ADDRESS:
5163 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5166 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5169 for (i = 0; i < n_reloads; i++)
5171 rtx reg = rld[i].reg_rtx;
5172 if (reg && REG_P (reg)
5173 && ((unsigned) regno - true_regnum (reg)
5174 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5177 rtx other_input = rld[i].in;
5179 /* If the other reload loads the same input value, that
5180 will not cause a conflict only if it's loading it into
5181 the same register. */
5182 if (true_regnum (reg) != start_regno)
5183 other_input = NULL_RTX;
5184 if (! other_input || ! rtx_equal_p (other_input, value)
5185 || rld[i].out || out)
5188 switch (rld[i].when_needed)
5190 case RELOAD_FOR_OTHER_ADDRESS:
5193 case RELOAD_FOR_INPADDR_ADDRESS:
5194 /* find_reloads makes sure that a
5195 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5196 by at most one - the first -
5197 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5198 address reload is inherited, the address address reload
5199 goes away, so we can ignore this conflict. */
5200 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5201 && ignore_address_reloads
5202 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5203 Then the address address is still needed to store
5204 back the new address. */
5205 && ! rld[reloadnum].out)
5207 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5208 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5210 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5211 && ignore_address_reloads
5212 /* Unless we are reloading an auto_inc expression. */
5213 && ! rld[reloadnum].out)
5215 time2 = rld[i].opnum * 4 + 2;
5217 case RELOAD_FOR_INPUT_ADDRESS:
5218 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5219 && ignore_address_reloads
5220 && ! rld[reloadnum].out)
5222 time2 = rld[i].opnum * 4 + 3;
5224 case RELOAD_FOR_INPUT:
5225 time2 = rld[i].opnum * 4 + 4;
5226 check_earlyclobber = 1;
5228 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5229 == MAX_RECOG_OPERAND * 4 */
5230 case RELOAD_FOR_OPADDR_ADDR:
5231 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5232 && ignore_address_reloads
5233 && ! rld[reloadnum].out)
5235 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5237 case RELOAD_FOR_OPERAND_ADDRESS:
5238 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5239 check_earlyclobber = 1;
5241 case RELOAD_FOR_INSN:
5242 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5244 case RELOAD_FOR_OUTPUT:
5245 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5246 instruction is executed. */
5247 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5249 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5250 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5252 case RELOAD_FOR_OUTADDR_ADDRESS:
5253 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5254 && ignore_address_reloads
5255 && ! rld[reloadnum].out)
5257 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5259 case RELOAD_FOR_OUTPUT_ADDRESS:
5260 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5263 /* If there is no conflict in the input part, handle this
5264 like an output reload. */
5265 if (! rld[i].in || rtx_equal_p (other_input, value))
5267 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5268 /* Earlyclobbered outputs must conflict with inputs. */
5269 if (earlyclobber_operand_p (rld[i].out))
5270 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5275 /* RELOAD_OTHER might be live beyond instruction execution,
5276 but this is not obvious when we set time2 = 1. So check
5277 here if there might be a problem with the new reload
5278 clobbering the register used by the RELOAD_OTHER. */
5286 && (! rld[i].in || rld[i].out
5287 || ! rtx_equal_p (other_input, value)))
5288 || (out && rld[reloadnum].out_reg
5289 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5295 /* Earlyclobbered outputs must conflict with inputs. */
5296 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5302 /* Return 1 if the value in reload reg REGNO, as used by a reload
5303 needed for the part of the insn specified by OPNUM and TYPE,
5304 may be used to load VALUE into it.
5306 MODE is the mode in which the register is used, this is needed to
5307 determine how many hard regs to test.
5309 Other read-only reloads with the same value do not conflict
5310 unless OUT is nonzero and these other reloads have to live while
5311 output reloads live.
5312 If OUT is CONST0_RTX, this is a special case: it means that the
5313 test should not be for using register REGNO as reload register, but
5314 for copying from register REGNO into the reload register.
5316 RELOADNUM is the number of the reload we want to load this value for;
5317 a reload does not conflict with itself.
5319 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5320 reloads that load an address for the very reload we are considering.
5322 The caller has to make sure that there is no conflict with the return
5326 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5327 enum reload_type type, rtx value, rtx out, int reloadnum,
5328 int ignore_address_reloads)
5330 int nregs = hard_regno_nregs[regno][mode];
5332 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5333 value, out, reloadnum,
5334 ignore_address_reloads))
5339 /* Return nonzero if the rtx X is invariant over the current function. */
5340 /* ??? Actually, the places where we use this expect exactly what is
5341 tested here, and not everything that is function invariant. In
5342 particular, the frame pointer and arg pointer are special cased;
5343 pic_offset_table_rtx is not, and we must not spill these things to
5347 function_invariant_p (const_rtx x)
5351 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5353 if (GET_CODE (x) == PLUS
5354 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5355 && CONSTANT_P (XEXP (x, 1)))
5360 /* Determine whether the reload reg X overlaps any rtx'es used for
5361 overriding inheritance. Return nonzero if so. */
5364 conflicts_with_override (rtx x)
5367 for (i = 0; i < n_reloads; i++)
5368 if (reload_override_in[i]
5369 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5374 /* Give an error message saying we failed to find a reload for INSN,
5375 and clear out reload R. */
5377 failed_reload (rtx insn, int r)
5379 if (asm_noperands (PATTERN (insn)) < 0)
5380 /* It's the compiler's fault. */
5381 fatal_insn ("could not find a spill register", insn);
5383 /* It's the user's fault; the operand's mode and constraint
5384 don't match. Disable this reload so we don't crash in final. */
5385 error_for_asm (insn,
5386 "%<asm%> operand constraint incompatible with operand size");
5390 rld[r].optional = 1;
5391 rld[r].secondary_p = 1;
5394 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5395 for reload R. If it's valid, get an rtx for it. Return nonzero if
5398 set_reload_reg (int i, int r)
5401 rtx reg = spill_reg_rtx[i];
5403 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5404 spill_reg_rtx[i] = reg
5405 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5407 regno = true_regnum (reg);
5409 /* Detect when the reload reg can't hold the reload mode.
5410 This used to be one `if', but Sequent compiler can't handle that. */
5411 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5413 enum machine_mode test_mode = VOIDmode;
5415 test_mode = GET_MODE (rld[r].in);
5416 /* If rld[r].in has VOIDmode, it means we will load it
5417 in whatever mode the reload reg has: to wit, rld[r].mode.
5418 We have already tested that for validity. */
5419 /* Aside from that, we need to test that the expressions
5420 to reload from or into have modes which are valid for this
5421 reload register. Otherwise the reload insns would be invalid. */
5422 if (! (rld[r].in != 0 && test_mode != VOIDmode
5423 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5424 if (! (rld[r].out != 0
5425 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5427 /* The reg is OK. */
5430 /* Mark as in use for this insn the reload regs we use
5432 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5433 rld[r].when_needed, rld[r].mode);
5435 rld[r].reg_rtx = reg;
5436 reload_spill_index[r] = spill_regs[i];
5443 /* Find a spill register to use as a reload register for reload R.
5444 LAST_RELOAD is nonzero if this is the last reload for the insn being
5447 Set rld[R].reg_rtx to the register allocated.
5449 We return 1 if successful, or 0 if we couldn't find a spill reg and
5450 we didn't change anything. */
5453 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5458 /* If we put this reload ahead, thinking it is a group,
5459 then insist on finding a group. Otherwise we can grab a
5460 reg that some other reload needs.
5461 (That can happen when we have a 68000 DATA_OR_FP_REG
5462 which is a group of data regs or one fp reg.)
5463 We need not be so restrictive if there are no more reloads
5466 ??? Really it would be nicer to have smarter handling
5467 for that kind of reg class, where a problem like this is normal.
5468 Perhaps those classes should be avoided for reloading
5469 by use of more alternatives. */
5471 int force_group = rld[r].nregs > 1 && ! last_reload;
5473 /* If we want a single register and haven't yet found one,
5474 take any reg in the right class and not in use.
5475 If we want a consecutive group, here is where we look for it.
5477 We use two passes so we can first look for reload regs to
5478 reuse, which are already in use for other reloads in this insn,
5479 and only then use additional registers.
5480 I think that maximizing reuse is needed to make sure we don't
5481 run out of reload regs. Suppose we have three reloads, and
5482 reloads A and B can share regs. These need two regs.
5483 Suppose A and B are given different regs.
5484 That leaves none for C. */
5485 for (pass = 0; pass < 2; pass++)
5487 /* I is the index in spill_regs.
5488 We advance it round-robin between insns to use all spill regs
5489 equally, so that inherited reloads have a chance
5490 of leapfrogging each other. */
5494 for (count = 0; count < n_spills; count++)
5496 int class = (int) rld[r].class;
5502 regnum = spill_regs[i];
5504 if ((reload_reg_free_p (regnum, rld[r].opnum,
5507 /* We check reload_reg_used to make sure we
5508 don't clobber the return register. */
5509 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5510 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5511 rld[r].when_needed, rld[r].in,
5513 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5514 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5515 /* Look first for regs to share, then for unshared. But
5516 don't share regs used for inherited reloads; they are
5517 the ones we want to preserve. */
5519 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5521 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5524 int nr = hard_regno_nregs[regnum][rld[r].mode];
5525 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5526 (on 68000) got us two FP regs. If NR is 1,
5527 we would reject both of them. */
5530 /* If we need only one reg, we have already won. */
5533 /* But reject a single reg if we demand a group. */
5538 /* Otherwise check that as many consecutive regs as we need
5539 are available here. */
5542 int regno = regnum + nr - 1;
5543 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5544 && spill_reg_order[regno] >= 0
5545 && reload_reg_free_p (regno, rld[r].opnum,
5546 rld[r].when_needed)))
5555 /* If we found something on pass 1, omit pass 2. */
5556 if (count < n_spills)
5560 /* We should have found a spill register by now. */
5561 if (count >= n_spills)
5564 /* I is the index in SPILL_REG_RTX of the reload register we are to
5565 allocate. Get an rtx for it and find its register number. */
5567 return set_reload_reg (i, r);
5570 /* Initialize all the tables needed to allocate reload registers.
5571 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5572 is the array we use to restore the reg_rtx field for every reload. */
5575 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5579 for (i = 0; i < n_reloads; i++)
5580 rld[i].reg_rtx = save_reload_reg_rtx[i];
5582 memset (reload_inherited, 0, MAX_RELOADS);
5583 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5584 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5586 CLEAR_HARD_REG_SET (reload_reg_used);
5587 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5588 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5589 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5590 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5591 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5593 CLEAR_HARD_REG_SET (reg_used_in_insn);
5596 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5597 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5598 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5599 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5600 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5601 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5604 for (i = 0; i < reload_n_operands; i++)
5606 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5607 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5608 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5609 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5610 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5611 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5614 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5616 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5618 for (i = 0; i < n_reloads; i++)
5619 /* If we have already decided to use a certain register,
5620 don't use it in another way. */
5622 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5623 rld[i].when_needed, rld[i].mode);
5626 /* Assign hard reg targets for the pseudo-registers we must reload
5627 into hard regs for this insn.
5628 Also output the instructions to copy them in and out of the hard regs.
5630 For machines with register classes, we are responsible for
5631 finding a reload reg in the proper class. */
5634 choose_reload_regs (struct insn_chain *chain)
5636 rtx insn = chain->insn;
5638 unsigned int max_group_size = 1;
5639 enum reg_class group_class = NO_REGS;
5640 int pass, win, inheritance;
5642 rtx save_reload_reg_rtx[MAX_RELOADS];
5644 /* In order to be certain of getting the registers we need,
5645 we must sort the reloads into order of increasing register class.
5646 Then our grabbing of reload registers will parallel the process
5647 that provided the reload registers.
5649 Also note whether any of the reloads wants a consecutive group of regs.
5650 If so, record the maximum size of the group desired and what
5651 register class contains all the groups needed by this insn. */
5653 for (j = 0; j < n_reloads; j++)
5655 reload_order[j] = j;
5656 if (rld[j].reg_rtx != NULL_RTX)
5658 gcc_assert (REG_P (rld[j].reg_rtx)
5659 && HARD_REGISTER_P (rld[j].reg_rtx));
5660 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
5663 reload_spill_index[j] = -1;
5665 if (rld[j].nregs > 1)
5667 max_group_size = MAX (rld[j].nregs, max_group_size);
5669 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5672 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5676 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5678 /* If -O, try first with inheritance, then turning it off.
5679 If not -O, don't do inheritance.
5680 Using inheritance when not optimizing leads to paradoxes
5681 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5682 because one side of the comparison might be inherited. */
5684 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5686 choose_reload_regs_init (chain, save_reload_reg_rtx);
5688 /* Process the reloads in order of preference just found.
5689 Beyond this point, subregs can be found in reload_reg_rtx.
5691 This used to look for an existing reloaded home for all of the
5692 reloads, and only then perform any new reloads. But that could lose
5693 if the reloads were done out of reg-class order because a later
5694 reload with a looser constraint might have an old home in a register
5695 needed by an earlier reload with a tighter constraint.
5697 To solve this, we make two passes over the reloads, in the order
5698 described above. In the first pass we try to inherit a reload
5699 from a previous insn. If there is a later reload that needs a
5700 class that is a proper subset of the class being processed, we must
5701 also allocate a spill register during the first pass.
5703 Then make a second pass over the reloads to allocate any reloads
5704 that haven't been given registers yet. */
5706 for (j = 0; j < n_reloads; j++)
5708 int r = reload_order[j];
5709 rtx search_equiv = NULL_RTX;
5711 /* Ignore reloads that got marked inoperative. */
5712 if (rld[r].out == 0 && rld[r].in == 0
5713 && ! rld[r].secondary_p)
5716 /* If find_reloads chose to use reload_in or reload_out as a reload
5717 register, we don't need to chose one. Otherwise, try even if it
5718 found one since we might save an insn if we find the value lying
5720 Try also when reload_in is a pseudo without a hard reg. */
5721 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5722 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5723 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5724 && !MEM_P (rld[r].in)
5725 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5728 #if 0 /* No longer needed for correct operation.
5729 It might give better code, or might not; worth an experiment? */
5730 /* If this is an optional reload, we can't inherit from earlier insns
5731 until we are sure that any non-optional reloads have been allocated.
5732 The following code takes advantage of the fact that optional reloads
5733 are at the end of reload_order. */
5734 if (rld[r].optional != 0)
5735 for (i = 0; i < j; i++)
5736 if ((rld[reload_order[i]].out != 0
5737 || rld[reload_order[i]].in != 0
5738 || rld[reload_order[i]].secondary_p)
5739 && ! rld[reload_order[i]].optional
5740 && rld[reload_order[i]].reg_rtx == 0)
5741 allocate_reload_reg (chain, reload_order[i], 0);
5744 /* First see if this pseudo is already available as reloaded
5745 for a previous insn. We cannot try to inherit for reloads
5746 that are smaller than the maximum number of registers needed
5747 for groups unless the register we would allocate cannot be used
5750 We could check here to see if this is a secondary reload for
5751 an object that is already in a register of the desired class.
5752 This would avoid the need for the secondary reload register.
5753 But this is complex because we can't easily determine what
5754 objects might want to be loaded via this reload. So let a
5755 register be allocated here. In `emit_reload_insns' we suppress
5756 one of the loads in the case described above. */
5762 enum machine_mode mode = VOIDmode;
5766 else if (REG_P (rld[r].in))
5768 regno = REGNO (rld[r].in);
5769 mode = GET_MODE (rld[r].in);
5771 else if (REG_P (rld[r].in_reg))
5773 regno = REGNO (rld[r].in_reg);
5774 mode = GET_MODE (rld[r].in_reg);
5776 else if (GET_CODE (rld[r].in_reg) == SUBREG
5777 && REG_P (SUBREG_REG (rld[r].in_reg)))
5779 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5780 if (regno < FIRST_PSEUDO_REGISTER)
5781 regno = subreg_regno (rld[r].in_reg);
5783 byte = SUBREG_BYTE (rld[r].in_reg);
5784 mode = GET_MODE (rld[r].in_reg);
5787 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
5788 && REG_P (XEXP (rld[r].in_reg, 0)))
5790 regno = REGNO (XEXP (rld[r].in_reg, 0));
5791 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5792 rld[r].out = rld[r].in;
5796 /* This won't work, since REGNO can be a pseudo reg number.
5797 Also, it takes much more hair to keep track of all the things
5798 that can invalidate an inherited reload of part of a pseudoreg. */
5799 else if (GET_CODE (rld[r].in) == SUBREG
5800 && REG_P (SUBREG_REG (rld[r].in)))
5801 regno = subreg_regno (rld[r].in);
5805 && reg_last_reload_reg[regno] != 0
5806 #ifdef CANNOT_CHANGE_MODE_CLASS
5807 /* Verify that the register it's in can be used in
5809 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
5810 GET_MODE (reg_last_reload_reg[regno]),
5815 enum reg_class class = rld[r].class, last_class;
5816 rtx last_reg = reg_last_reload_reg[regno];
5817 enum machine_mode need_mode;
5819 i = REGNO (last_reg);
5820 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5821 last_class = REGNO_REG_CLASS (i);
5827 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
5828 + byte * BITS_PER_UNIT,
5829 GET_MODE_CLASS (mode));
5831 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5832 >= GET_MODE_SIZE (need_mode))
5833 && reg_reloaded_contents[i] == regno
5834 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5835 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5836 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5837 /* Even if we can't use this register as a reload
5838 register, we might use it for reload_override_in,
5839 if copying it to the desired class is cheap
5841 || ((REGISTER_MOVE_COST (mode, last_class, class)
5842 < MEMORY_MOVE_COST (mode, class, 1))
5843 && (secondary_reload_class (1, class, mode,
5846 #ifdef SECONDARY_MEMORY_NEEDED
5847 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5852 && (rld[r].nregs == max_group_size
5853 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5855 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5856 rld[r].when_needed, rld[r].in,
5859 /* If a group is needed, verify that all the subsequent
5860 registers still have their values intact. */
5861 int nr = hard_regno_nregs[i][rld[r].mode];
5864 for (k = 1; k < nr; k++)
5865 if (reg_reloaded_contents[i + k] != regno
5866 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5874 last_reg = (GET_MODE (last_reg) == mode
5875 ? last_reg : gen_rtx_REG (mode, i));
5878 for (k = 0; k < nr; k++)
5879 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5882 /* We found a register that contains the
5883 value we need. If this register is the
5884 same as an `earlyclobber' operand of the
5885 current insn, just mark it as a place to
5886 reload from since we can't use it as the
5887 reload register itself. */
5889 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5890 if (reg_overlap_mentioned_for_reload_p
5891 (reg_last_reload_reg[regno],
5892 reload_earlyclobbers[i1]))
5895 if (i1 != n_earlyclobbers
5896 || ! (free_for_value_p (i, rld[r].mode,
5898 rld[r].when_needed, rld[r].in,
5900 /* Don't use it if we'd clobber a pseudo reg. */
5901 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5903 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5904 /* Don't clobber the frame pointer. */
5905 || (i == HARD_FRAME_POINTER_REGNUM
5906 && frame_pointer_needed
5908 /* Don't really use the inherited spill reg
5909 if we need it wider than we've got it. */
5910 || (GET_MODE_SIZE (rld[r].mode)
5911 > GET_MODE_SIZE (mode))
5914 /* If find_reloads chose reload_out as reload
5915 register, stay with it - that leaves the
5916 inherited register for subsequent reloads. */
5917 || (rld[r].out && rld[r].reg_rtx
5918 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5920 if (! rld[r].optional)
5922 reload_override_in[r] = last_reg;
5923 reload_inheritance_insn[r]
5924 = reg_reloaded_insn[i];
5930 /* We can use this as a reload reg. */
5931 /* Mark the register as in use for this part of
5933 mark_reload_reg_in_use (i,
5937 rld[r].reg_rtx = last_reg;
5938 reload_inherited[r] = 1;
5939 reload_inheritance_insn[r]
5940 = reg_reloaded_insn[i];
5941 reload_spill_index[r] = i;
5942 for (k = 0; k < nr; k++)
5943 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5951 /* Here's another way to see if the value is already lying around. */
5954 && ! reload_inherited[r]
5956 && (CONSTANT_P (rld[r].in)
5957 || GET_CODE (rld[r].in) == PLUS
5958 || REG_P (rld[r].in)
5959 || MEM_P (rld[r].in))
5960 && (rld[r].nregs == max_group_size
5961 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5962 search_equiv = rld[r].in;
5963 /* If this is an output reload from a simple move insn, look
5964 if an equivalence for the input is available. */
5965 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5967 rtx set = single_set (insn);
5970 && rtx_equal_p (rld[r].out, SET_DEST (set))
5971 && CONSTANT_P (SET_SRC (set)))
5972 search_equiv = SET_SRC (set);
5978 = find_equiv_reg (search_equiv, insn, rld[r].class,
5979 -1, NULL, 0, rld[r].mode);
5985 regno = REGNO (equiv);
5988 /* This must be a SUBREG of a hard register.
5989 Make a new REG since this might be used in an
5990 address and not all machines support SUBREGs
5992 gcc_assert (GET_CODE (equiv) == SUBREG);
5993 regno = subreg_regno (equiv);
5994 equiv = gen_rtx_REG (rld[r].mode, regno);
5995 /* If we choose EQUIV as the reload register, but the
5996 loop below decides to cancel the inheritance, we'll
5997 end up reloading EQUIV in rld[r].mode, not the mode
5998 it had originally. That isn't safe when EQUIV isn't
5999 available as a spill register since its value might
6000 still be live at this point. */
6001 for (i = regno; i < regno + (int) rld[r].nregs; i++)
6002 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6007 /* If we found a spill reg, reject it unless it is free
6008 and of the desired class. */
6012 int bad_for_class = 0;
6013 int max_regno = regno + rld[r].nregs;
6015 for (i = regno; i < max_regno; i++)
6017 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6019 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
6024 && ! free_for_value_p (regno, rld[r].mode,
6025 rld[r].opnum, rld[r].when_needed,
6026 rld[r].in, rld[r].out, r, 1))
6031 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6034 /* We found a register that contains the value we need.
6035 If this register is the same as an `earlyclobber' operand
6036 of the current insn, just mark it as a place to reload from
6037 since we can't use it as the reload register itself. */
6040 for (i = 0; i < n_earlyclobbers; i++)
6041 if (reg_overlap_mentioned_for_reload_p (equiv,
6042 reload_earlyclobbers[i]))
6044 if (! rld[r].optional)
6045 reload_override_in[r] = equiv;
6050 /* If the equiv register we have found is explicitly clobbered
6051 in the current insn, it depends on the reload type if we
6052 can use it, use it for reload_override_in, or not at all.
6053 In particular, we then can't use EQUIV for a
6054 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6058 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6059 switch (rld[r].when_needed)
6061 case RELOAD_FOR_OTHER_ADDRESS:
6062 case RELOAD_FOR_INPADDR_ADDRESS:
6063 case RELOAD_FOR_INPUT_ADDRESS:
6064 case RELOAD_FOR_OPADDR_ADDR:
6067 case RELOAD_FOR_INPUT:
6068 case RELOAD_FOR_OPERAND_ADDRESS:
6069 if (! rld[r].optional)
6070 reload_override_in[r] = equiv;
6076 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6077 switch (rld[r].when_needed)
6079 case RELOAD_FOR_OTHER_ADDRESS:
6080 case RELOAD_FOR_INPADDR_ADDRESS:
6081 case RELOAD_FOR_INPUT_ADDRESS:
6082 case RELOAD_FOR_OPADDR_ADDR:
6083 case RELOAD_FOR_OPERAND_ADDRESS:
6084 case RELOAD_FOR_INPUT:
6087 if (! rld[r].optional)
6088 reload_override_in[r] = equiv;
6096 /* If we found an equivalent reg, say no code need be generated
6097 to load it, and use it as our reload reg. */
6099 && (regno != HARD_FRAME_POINTER_REGNUM
6100 || !frame_pointer_needed))
6102 int nr = hard_regno_nregs[regno][rld[r].mode];
6104 rld[r].reg_rtx = equiv;
6105 reload_inherited[r] = 1;
6107 /* If reg_reloaded_valid is not set for this register,
6108 there might be a stale spill_reg_store lying around.
6109 We must clear it, since otherwise emit_reload_insns
6110 might delete the store. */
6111 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6112 spill_reg_store[regno] = NULL_RTX;
6113 /* If any of the hard registers in EQUIV are spill
6114 registers, mark them as in use for this insn. */
6115 for (k = 0; k < nr; k++)
6117 i = spill_reg_order[regno + k];
6120 mark_reload_reg_in_use (regno, rld[r].opnum,
6123 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6130 /* If we found a register to use already, or if this is an optional
6131 reload, we are done. */
6132 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6136 /* No longer needed for correct operation. Might or might
6137 not give better code on the average. Want to experiment? */
6139 /* See if there is a later reload that has a class different from our
6140 class that intersects our class or that requires less register
6141 than our reload. If so, we must allocate a register to this
6142 reload now, since that reload might inherit a previous reload
6143 and take the only available register in our class. Don't do this
6144 for optional reloads since they will force all previous reloads
6145 to be allocated. Also don't do this for reloads that have been
6148 for (i = j + 1; i < n_reloads; i++)
6150 int s = reload_order[i];
6152 if ((rld[s].in == 0 && rld[s].out == 0
6153 && ! rld[s].secondary_p)
6157 if ((rld[s].class != rld[r].class
6158 && reg_classes_intersect_p (rld[r].class,
6160 || rld[s].nregs < rld[r].nregs)
6167 allocate_reload_reg (chain, r, j == n_reloads - 1);
6171 /* Now allocate reload registers for anything non-optional that
6172 didn't get one yet. */
6173 for (j = 0; j < n_reloads; j++)
6175 int r = reload_order[j];
6177 /* Ignore reloads that got marked inoperative. */
6178 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6181 /* Skip reloads that already have a register allocated or are
6183 if (rld[r].reg_rtx != 0 || rld[r].optional)
6186 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6190 /* If that loop got all the way, we have won. */
6197 /* Loop around and try without any inheritance. */
6202 /* First undo everything done by the failed attempt
6203 to allocate with inheritance. */
6204 choose_reload_regs_init (chain, save_reload_reg_rtx);
6206 /* Some sanity tests to verify that the reloads found in the first
6207 pass are identical to the ones we have now. */
6208 gcc_assert (chain->n_reloads == n_reloads);
6210 for (i = 0; i < n_reloads; i++)
6212 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6214 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6215 for (j = 0; j < n_spills; j++)
6216 if (spill_regs[j] == chain->rld[i].regno)
6217 if (! set_reload_reg (j, i))
6218 failed_reload (chain->insn, i);
6222 /* If we thought we could inherit a reload, because it seemed that
6223 nothing else wanted the same reload register earlier in the insn,
6224 verify that assumption, now that all reloads have been assigned.
6225 Likewise for reloads where reload_override_in has been set. */
6227 /* If doing expensive optimizations, do one preliminary pass that doesn't
6228 cancel any inheritance, but removes reloads that have been needed only
6229 for reloads that we know can be inherited. */
6230 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6232 for (j = 0; j < n_reloads; j++)
6234 int r = reload_order[j];
6236 if (reload_inherited[r] && rld[r].reg_rtx)
6237 check_reg = rld[r].reg_rtx;
6238 else if (reload_override_in[r]
6239 && (REG_P (reload_override_in[r])
6240 || GET_CODE (reload_override_in[r]) == SUBREG))
6241 check_reg = reload_override_in[r];
6244 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6245 rld[r].opnum, rld[r].when_needed, rld[r].in,
6246 (reload_inherited[r]
6247 ? rld[r].out : const0_rtx),
6252 reload_inherited[r] = 0;
6253 reload_override_in[r] = 0;
6255 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6256 reload_override_in, then we do not need its related
6257 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6258 likewise for other reload types.
6259 We handle this by removing a reload when its only replacement
6260 is mentioned in reload_in of the reload we are going to inherit.
6261 A special case are auto_inc expressions; even if the input is
6262 inherited, we still need the address for the output. We can
6263 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6264 If we succeeded removing some reload and we are doing a preliminary
6265 pass just to remove such reloads, make another pass, since the
6266 removal of one reload might allow us to inherit another one. */
6268 && rld[r].out != rld[r].in
6269 && remove_address_replacements (rld[r].in) && pass)
6274 /* Now that reload_override_in is known valid,
6275 actually override reload_in. */
6276 for (j = 0; j < n_reloads; j++)
6277 if (reload_override_in[j])
6278 rld[j].in = reload_override_in[j];
6280 /* If this reload won't be done because it has been canceled or is
6281 optional and not inherited, clear reload_reg_rtx so other
6282 routines (such as subst_reloads) don't get confused. */
6283 for (j = 0; j < n_reloads; j++)
6284 if (rld[j].reg_rtx != 0
6285 && ((rld[j].optional && ! reload_inherited[j])
6286 || (rld[j].in == 0 && rld[j].out == 0
6287 && ! rld[j].secondary_p)))
6289 int regno = true_regnum (rld[j].reg_rtx);
6291 if (spill_reg_order[regno] >= 0)
6292 clear_reload_reg_in_use (regno, rld[j].opnum,
6293 rld[j].when_needed, rld[j].mode);
6295 reload_spill_index[j] = -1;
6298 /* Record which pseudos and which spill regs have output reloads. */
6299 for (j = 0; j < n_reloads; j++)
6301 int r = reload_order[j];
6303 i = reload_spill_index[r];
6305 /* I is nonneg if this reload uses a register.
6306 If rld[r].reg_rtx is 0, this is an optional reload
6307 that we opted to ignore. */
6308 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6309 && rld[r].reg_rtx != 0)
6311 int nregno = REGNO (rld[r].out_reg);
6314 if (nregno < FIRST_PSEUDO_REGISTER)
6315 nr = hard_regno_nregs[nregno][rld[r].mode];
6318 SET_REGNO_REG_SET (®_has_output_reload,
6323 nr = hard_regno_nregs[i][rld[r].mode];
6325 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6328 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6329 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6330 || rld[r].when_needed == RELOAD_FOR_INSN);
6335 /* Deallocate the reload register for reload R. This is called from
6336 remove_address_replacements. */
6339 deallocate_reload_reg (int r)
6343 if (! rld[r].reg_rtx)
6345 regno = true_regnum (rld[r].reg_rtx);
6347 if (spill_reg_order[regno] >= 0)
6348 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6350 reload_spill_index[r] = -1;
6353 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6354 reloads of the same item for fear that we might not have enough reload
6355 registers. However, normally they will get the same reload register
6356 and hence actually need not be loaded twice.
6358 Here we check for the most common case of this phenomenon: when we have
6359 a number of reloads for the same object, each of which were allocated
6360 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6361 reload, and is not modified in the insn itself. If we find such,
6362 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6363 This will not increase the number of spill registers needed and will
6364 prevent redundant code. */
6367 merge_assigned_reloads (rtx insn)
6371 /* Scan all the reloads looking for ones that only load values and
6372 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6373 assigned and not modified by INSN. */
6375 for (i = 0; i < n_reloads; i++)
6377 int conflicting_input = 0;
6378 int max_input_address_opnum = -1;
6379 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6381 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6382 || rld[i].out != 0 || rld[i].reg_rtx == 0
6383 || reg_set_p (rld[i].reg_rtx, insn))
6386 /* Look at all other reloads. Ensure that the only use of this
6387 reload_reg_rtx is in a reload that just loads the same value
6388 as we do. Note that any secondary reloads must be of the identical
6389 class since the values, modes, and result registers are the
6390 same, so we need not do anything with any secondary reloads. */
6392 for (j = 0; j < n_reloads; j++)
6394 if (i == j || rld[j].reg_rtx == 0
6395 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6399 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6400 && rld[j].opnum > max_input_address_opnum)
6401 max_input_address_opnum = rld[j].opnum;
6403 /* If the reload regs aren't exactly the same (e.g, different modes)
6404 or if the values are different, we can't merge this reload.
6405 But if it is an input reload, we might still merge
6406 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6408 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6409 || rld[j].out != 0 || rld[j].in == 0
6410 || ! rtx_equal_p (rld[i].in, rld[j].in))
6412 if (rld[j].when_needed != RELOAD_FOR_INPUT
6413 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6414 || rld[i].opnum > rld[j].opnum)
6415 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6417 conflicting_input = 1;
6418 if (min_conflicting_input_opnum > rld[j].opnum)
6419 min_conflicting_input_opnum = rld[j].opnum;
6423 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6424 we, in fact, found any matching reloads. */
6427 && max_input_address_opnum <= min_conflicting_input_opnum)
6429 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6431 for (j = 0; j < n_reloads; j++)
6432 if (i != j && rld[j].reg_rtx != 0
6433 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6434 && (! conflicting_input
6435 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6436 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6438 rld[i].when_needed = RELOAD_OTHER;
6440 reload_spill_index[j] = -1;
6441 transfer_replacements (i, j);
6444 /* If this is now RELOAD_OTHER, look for any reloads that
6445 load parts of this operand and set them to
6446 RELOAD_FOR_OTHER_ADDRESS if they were for inputs,
6447 RELOAD_OTHER for outputs. Note that this test is
6448 equivalent to looking for reloads for this operand
6451 We must take special care with RELOAD_FOR_OUTPUT_ADDRESS;
6452 it may share registers with a RELOAD_FOR_INPUT, so we can
6453 not change it to RELOAD_FOR_OTHER_ADDRESS. We should
6454 never need to, since we do not modify RELOAD_FOR_OUTPUT.
6456 It is possible that the RELOAD_FOR_OPERAND_ADDRESS
6457 instruction is assigned the same register as the earlier
6458 RELOAD_FOR_OTHER_ADDRESS instruction. Merging these two
6459 instructions will cause the RELOAD_FOR_OTHER_ADDRESS
6460 instruction to be deleted later on. */
6462 if (rld[i].when_needed == RELOAD_OTHER)
6463 for (j = 0; j < n_reloads; j++)
6465 && rld[j].when_needed != RELOAD_OTHER
6466 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6467 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6468 && rld[j].when_needed != RELOAD_FOR_OPERAND_ADDRESS
6469 && (! conflicting_input
6470 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6471 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6472 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6478 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6479 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6480 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6482 /* Check to see if we accidentally converted two
6483 reloads that use the same reload register with
6484 different inputs to the same type. If so, the
6485 resulting code won't work. */
6487 for (k = 0; k < j; k++)
6488 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6489 || rld[k].when_needed != rld[j].when_needed
6490 || !rtx_equal_p (rld[k].reg_rtx,
6492 || rtx_equal_p (rld[k].in,
6499 /* These arrays are filled by emit_reload_insns and its subroutines. */
6500 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6501 static rtx other_input_address_reload_insns = 0;
6502 static rtx other_input_reload_insns = 0;
6503 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6504 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6505 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6506 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6507 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6508 static rtx operand_reload_insns = 0;
6509 static rtx other_operand_reload_insns = 0;
6510 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6512 /* Values to be put in spill_reg_store are put here first. */
6513 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6514 static HARD_REG_SET reg_reloaded_died;
6516 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6517 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6518 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6519 adjusted register, and return true. Otherwise, return false. */
6521 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6522 enum reg_class new_class,
6523 enum machine_mode new_mode)
6528 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6530 unsigned regno = REGNO (reg);
6532 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6534 if (GET_MODE (reg) != new_mode)
6536 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6538 if (hard_regno_nregs[regno][new_mode]
6539 > hard_regno_nregs[regno][GET_MODE (reg)])
6541 reg = reload_adjust_reg_for_mode (reg, new_mode);
6549 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6550 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6551 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6552 adjusted register, and return true. Otherwise, return false. */
6554 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6555 enum insn_code icode)
6558 enum reg_class new_class = scratch_reload_class (icode);
6559 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6561 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6562 new_class, new_mode);
6565 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6566 has the number J. OLD contains the value to be used as input. */
6569 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6572 rtx insn = chain->insn;
6574 rtx oldequiv_reg = 0;
6577 enum machine_mode mode;
6580 /* delete_output_reload is only invoked properly if old contains
6581 the original pseudo register. Since this is replaced with a
6582 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6583 find the pseudo in RELOAD_IN_REG. */
6584 if (reload_override_in[j]
6585 && REG_P (rl->in_reg))
6592 else if (REG_P (oldequiv))
6593 oldequiv_reg = oldequiv;
6594 else if (GET_CODE (oldequiv) == SUBREG)
6595 oldequiv_reg = SUBREG_REG (oldequiv);
6597 reloadreg = reload_reg_rtx_for_input[j];
6598 mode = GET_MODE (reloadreg);
6600 /* If we are reloading from a register that was recently stored in
6601 with an output-reload, see if we can prove there was
6602 actually no need to store the old value in it. */
6604 if (optimize && REG_P (oldequiv)
6605 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6606 && spill_reg_store[REGNO (oldequiv)]
6608 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6609 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6611 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6613 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
6616 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6617 oldequiv = SUBREG_REG (oldequiv);
6618 if (GET_MODE (oldequiv) != VOIDmode
6619 && mode != GET_MODE (oldequiv))
6620 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6622 /* Switch to the right place to emit the reload insns. */
6623 switch (rl->when_needed)
6626 where = &other_input_reload_insns;
6628 case RELOAD_FOR_INPUT:
6629 where = &input_reload_insns[rl->opnum];
6631 case RELOAD_FOR_INPUT_ADDRESS:
6632 where = &input_address_reload_insns[rl->opnum];
6634 case RELOAD_FOR_INPADDR_ADDRESS:
6635 where = &inpaddr_address_reload_insns[rl->opnum];
6637 case RELOAD_FOR_OUTPUT_ADDRESS:
6638 where = &output_address_reload_insns[rl->opnum];
6640 case RELOAD_FOR_OUTADDR_ADDRESS:
6641 where = &outaddr_address_reload_insns[rl->opnum];
6643 case RELOAD_FOR_OPERAND_ADDRESS:
6644 where = &operand_reload_insns;
6646 case RELOAD_FOR_OPADDR_ADDR:
6647 where = &other_operand_reload_insns;
6649 case RELOAD_FOR_OTHER_ADDRESS:
6650 where = &other_input_address_reload_insns;
6656 push_to_sequence (*where);
6658 /* Auto-increment addresses must be reloaded in a special way. */
6659 if (rl->out && ! rl->out_reg)
6661 /* We are not going to bother supporting the case where a
6662 incremented register can't be copied directly from
6663 OLDEQUIV since this seems highly unlikely. */
6664 gcc_assert (rl->secondary_in_reload < 0);
6666 if (reload_inherited[j])
6667 oldequiv = reloadreg;
6669 old = XEXP (rl->in_reg, 0);
6671 if (optimize && REG_P (oldequiv)
6672 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6673 && spill_reg_store[REGNO (oldequiv)]
6675 && (dead_or_set_p (insn,
6676 spill_reg_stored_to[REGNO (oldequiv)])
6677 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6679 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6681 /* Prevent normal processing of this reload. */
6683 /* Output a special code sequence for this case. */
6684 new_spill_reg_store[REGNO (reloadreg)]
6685 = inc_for_reload (reloadreg, oldequiv, rl->out,
6689 /* If we are reloading a pseudo-register that was set by the previous
6690 insn, see if we can get rid of that pseudo-register entirely
6691 by redirecting the previous insn into our reload register. */
6693 else if (optimize && REG_P (old)
6694 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6695 && dead_or_set_p (insn, old)
6696 /* This is unsafe if some other reload
6697 uses the same reg first. */
6698 && ! conflicts_with_override (reloadreg)
6699 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6700 rl->when_needed, old, rl->out, j, 0))
6702 rtx temp = PREV_INSN (insn);
6703 while (temp && NOTE_P (temp))
6704 temp = PREV_INSN (temp);
6706 && NONJUMP_INSN_P (temp)
6707 && GET_CODE (PATTERN (temp)) == SET
6708 && SET_DEST (PATTERN (temp)) == old
6709 /* Make sure we can access insn_operand_constraint. */
6710 && asm_noperands (PATTERN (temp)) < 0
6711 /* This is unsafe if operand occurs more than once in current
6712 insn. Perhaps some occurrences aren't reloaded. */
6713 && count_occurrences (PATTERN (insn), old, 0) == 1)
6715 rtx old = SET_DEST (PATTERN (temp));
6716 /* Store into the reload register instead of the pseudo. */
6717 SET_DEST (PATTERN (temp)) = reloadreg;
6719 /* Verify that resulting insn is valid. */
6720 extract_insn (temp);
6721 if (constrain_operands (1))
6723 /* If the previous insn is an output reload, the source is
6724 a reload register, and its spill_reg_store entry will
6725 contain the previous destination. This is now
6727 if (REG_P (SET_SRC (PATTERN (temp)))
6728 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6730 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6731 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6734 /* If these are the only uses of the pseudo reg,
6735 pretend for GDB it lives in the reload reg we used. */
6736 if (REG_N_DEATHS (REGNO (old)) == 1
6737 && REG_N_SETS (REGNO (old)) == 1)
6739 reg_renumber[REGNO (old)] = REGNO (reloadreg);
6740 alter_reg (REGNO (old), -1);
6746 SET_DEST (PATTERN (temp)) = old;
6751 /* We can't do that, so output an insn to load RELOADREG. */
6753 /* If we have a secondary reload, pick up the secondary register
6754 and icode, if any. If OLDEQUIV and OLD are different or
6755 if this is an in-out reload, recompute whether or not we
6756 still need a secondary register and what the icode should
6757 be. If we still need a secondary register and the class or
6758 icode is different, go back to reloading from OLD if using
6759 OLDEQUIV means that we got the wrong type of register. We
6760 cannot have different class or icode due to an in-out reload
6761 because we don't make such reloads when both the input and
6762 output need secondary reload registers. */
6764 if (! special && rl->secondary_in_reload >= 0)
6766 rtx second_reload_reg = 0;
6767 rtx third_reload_reg = 0;
6768 int secondary_reload = rl->secondary_in_reload;
6769 rtx real_oldequiv = oldequiv;
6772 enum insn_code icode;
6773 enum insn_code tertiary_icode = CODE_FOR_nothing;
6775 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6776 and similarly for OLD.
6777 See comments in get_secondary_reload in reload.c. */
6778 /* If it is a pseudo that cannot be replaced with its
6779 equivalent MEM, we must fall back to reload_in, which
6780 will have all the necessary substitutions registered.
6781 Likewise for a pseudo that can't be replaced with its
6782 equivalent constant.
6784 Take extra care for subregs of such pseudos. Note that
6785 we cannot use reg_equiv_mem in this case because it is
6786 not in the right mode. */
6789 if (GET_CODE (tmp) == SUBREG)
6790 tmp = SUBREG_REG (tmp);
6792 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6793 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6794 || reg_equiv_constant[REGNO (tmp)] != 0))
6796 if (! reg_equiv_mem[REGNO (tmp)]
6797 || num_not_at_initial_offset
6798 || GET_CODE (oldequiv) == SUBREG)
6799 real_oldequiv = rl->in;
6801 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6805 if (GET_CODE (tmp) == SUBREG)
6806 tmp = SUBREG_REG (tmp);
6808 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6809 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6810 || reg_equiv_constant[REGNO (tmp)] != 0))
6812 if (! reg_equiv_mem[REGNO (tmp)]
6813 || num_not_at_initial_offset
6814 || GET_CODE (old) == SUBREG)
6817 real_old = reg_equiv_mem[REGNO (tmp)];
6820 second_reload_reg = rld[secondary_reload].reg_rtx;
6821 if (rld[secondary_reload].secondary_in_reload >= 0)
6823 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
6825 third_reload_reg = rld[tertiary_reload].reg_rtx;
6826 tertiary_icode = rld[secondary_reload].secondary_in_icode;
6827 /* We'd have to add more code for quartary reloads. */
6828 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
6830 icode = rl->secondary_in_icode;
6832 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6833 || (rl->in != 0 && rl->out != 0))
6835 secondary_reload_info sri, sri2;
6836 enum reg_class new_class, new_t_class;
6838 sri.icode = CODE_FOR_nothing;
6839 sri.prev_sri = NULL;
6840 new_class = targetm.secondary_reload (1, real_oldequiv, rl->class,
6843 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
6844 second_reload_reg = 0;
6845 else if (new_class == NO_REGS)
6847 if (reload_adjust_reg_for_icode (&second_reload_reg,
6848 third_reload_reg, sri.icode))
6849 icode = sri.icode, third_reload_reg = 0;
6851 oldequiv = old, real_oldequiv = real_old;
6853 else if (sri.icode != CODE_FOR_nothing)
6854 /* We currently lack a way to express this in reloads. */
6858 sri2.icode = CODE_FOR_nothing;
6859 sri2.prev_sri = &sri;
6860 new_t_class = targetm.secondary_reload (1, real_oldequiv,
6861 new_class, mode, &sri);
6862 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
6864 if (reload_adjust_reg_for_temp (&second_reload_reg,
6867 third_reload_reg = 0, tertiary_icode = sri2.icode;
6869 oldequiv = old, real_oldequiv = real_old;
6871 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
6873 rtx intermediate = second_reload_reg;
6875 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6877 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
6880 second_reload_reg = intermediate;
6881 tertiary_icode = sri2.icode;
6884 oldequiv = old, real_oldequiv = real_old;
6886 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
6888 rtx intermediate = second_reload_reg;
6890 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6892 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
6895 second_reload_reg = intermediate;
6896 tertiary_icode = sri2.icode;
6899 oldequiv = old, real_oldequiv = real_old;
6902 /* This could be handled more intelligently too. */
6903 oldequiv = old, real_oldequiv = real_old;
6907 /* If we still need a secondary reload register, check
6908 to see if it is being used as a scratch or intermediate
6909 register and generate code appropriately. If we need
6910 a scratch register, use REAL_OLDEQUIV since the form of
6911 the insn may depend on the actual address if it is
6914 if (second_reload_reg)
6916 if (icode != CODE_FOR_nothing)
6918 /* We'd have to add extra code to handle this case. */
6919 gcc_assert (!third_reload_reg);
6921 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6922 second_reload_reg));
6927 /* See if we need a scratch register to load the
6928 intermediate register (a tertiary reload). */
6929 if (tertiary_icode != CODE_FOR_nothing)
6931 emit_insn ((GEN_FCN (tertiary_icode)
6932 (second_reload_reg, real_oldequiv,
6933 third_reload_reg)));
6935 else if (third_reload_reg)
6937 gen_reload (third_reload_reg, real_oldequiv,
6940 gen_reload (second_reload_reg, third_reload_reg,
6945 gen_reload (second_reload_reg, real_oldequiv,
6949 oldequiv = second_reload_reg;
6954 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6956 rtx real_oldequiv = oldequiv;
6958 if ((REG_P (oldequiv)
6959 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6960 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6961 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6962 || (GET_CODE (oldequiv) == SUBREG
6963 && REG_P (SUBREG_REG (oldequiv))
6964 && (REGNO (SUBREG_REG (oldequiv))
6965 >= FIRST_PSEUDO_REGISTER)
6966 && ((reg_equiv_memory_loc
6967 [REGNO (SUBREG_REG (oldequiv))] != 0)
6968 || (reg_equiv_constant
6969 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6970 || (CONSTANT_P (oldequiv)
6971 && (PREFERRED_RELOAD_CLASS (oldequiv,
6972 REGNO_REG_CLASS (REGNO (reloadreg)))
6974 real_oldequiv = rl->in;
6975 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6979 if (flag_non_call_exceptions)
6980 copy_eh_notes (insn, get_insns ());
6982 /* End this sequence. */
6983 *where = get_insns ();
6986 /* Update reload_override_in so that delete_address_reloads_1
6987 can see the actual register usage. */
6989 reload_override_in[j] = oldequiv;
6992 /* Generate insns to for the output reload RL, which is for the insn described
6993 by CHAIN and has the number J. */
6995 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6999 rtx insn = chain->insn;
7002 enum machine_mode mode;
7006 if (rl->when_needed == RELOAD_OTHER)
7009 push_to_sequence (output_reload_insns[rl->opnum]);
7011 rl_reg_rtx = reload_reg_rtx_for_output[j];
7012 mode = GET_MODE (rl_reg_rtx);
7014 reloadreg = rl_reg_rtx;
7016 /* If we need two reload regs, set RELOADREG to the intermediate
7017 one, since it will be stored into OLD. We might need a secondary
7018 register only for an input reload, so check again here. */
7020 if (rl->secondary_out_reload >= 0)
7023 int secondary_reload = rl->secondary_out_reload;
7024 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7026 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7027 && reg_equiv_mem[REGNO (old)] != 0)
7028 real_old = reg_equiv_mem[REGNO (old)];
7030 if (secondary_reload_class (0, rl->class, mode, real_old) != NO_REGS)
7032 rtx second_reloadreg = reloadreg;
7033 reloadreg = rld[secondary_reload].reg_rtx;
7035 /* See if RELOADREG is to be used as a scratch register
7036 or as an intermediate register. */
7037 if (rl->secondary_out_icode != CODE_FOR_nothing)
7039 /* We'd have to add extra code to handle this case. */
7040 gcc_assert (tertiary_reload < 0);
7042 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7043 (real_old, second_reloadreg, reloadreg)));
7048 /* See if we need both a scratch and intermediate reload
7051 enum insn_code tertiary_icode
7052 = rld[secondary_reload].secondary_out_icode;
7054 /* We'd have to add more code for quartary reloads. */
7055 gcc_assert (tertiary_reload < 0
7056 || rld[tertiary_reload].secondary_out_reload < 0);
7058 if (GET_MODE (reloadreg) != mode)
7059 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7061 if (tertiary_icode != CODE_FOR_nothing)
7063 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7066 /* Copy primary reload reg to secondary reload reg.
7067 (Note that these have been swapped above, then
7068 secondary reload reg to OLD using our insn.) */
7070 /* If REAL_OLD is a paradoxical SUBREG, remove it
7071 and try to put the opposite SUBREG on
7073 if (GET_CODE (real_old) == SUBREG
7074 && (GET_MODE_SIZE (GET_MODE (real_old))
7075 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7076 && 0 != (tem = gen_lowpart_common
7077 (GET_MODE (SUBREG_REG (real_old)),
7079 real_old = SUBREG_REG (real_old), reloadreg = tem;
7081 gen_reload (reloadreg, second_reloadreg,
7082 rl->opnum, rl->when_needed);
7083 emit_insn ((GEN_FCN (tertiary_icode)
7084 (real_old, reloadreg, third_reloadreg)));
7090 /* Copy between the reload regs here and then to
7093 gen_reload (reloadreg, second_reloadreg,
7094 rl->opnum, rl->when_needed);
7095 if (tertiary_reload >= 0)
7097 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7099 gen_reload (third_reloadreg, reloadreg,
7100 rl->opnum, rl->when_needed);
7101 reloadreg = third_reloadreg;
7108 /* Output the last reload insn. */
7113 /* Don't output the last reload if OLD is not the dest of
7114 INSN and is in the src and is clobbered by INSN. */
7115 if (! flag_expensive_optimizations
7117 || !(set = single_set (insn))
7118 || rtx_equal_p (old, SET_DEST (set))
7119 || !reg_mentioned_p (old, SET_SRC (set))
7120 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7121 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7122 gen_reload (old, reloadreg, rl->opnum,
7126 /* Look at all insns we emitted, just to be safe. */
7127 for (p = get_insns (); p; p = NEXT_INSN (p))
7130 rtx pat = PATTERN (p);
7132 /* If this output reload doesn't come from a spill reg,
7133 clear any memory of reloaded copies of the pseudo reg.
7134 If this output reload comes from a spill reg,
7135 reg_has_output_reload will make this do nothing. */
7136 note_stores (pat, forget_old_reloads_1, NULL);
7138 if (reg_mentioned_p (rl_reg_rtx, pat))
7140 rtx set = single_set (insn);
7141 if (reload_spill_index[j] < 0
7143 && SET_SRC (set) == rl_reg_rtx)
7145 int src = REGNO (SET_SRC (set));
7147 reload_spill_index[j] = src;
7148 SET_HARD_REG_BIT (reg_is_output_reload, src);
7149 if (find_regno_note (insn, REG_DEAD, src))
7150 SET_HARD_REG_BIT (reg_reloaded_died, src);
7152 if (HARD_REGISTER_P (rl_reg_rtx))
7154 int s = rl->secondary_out_reload;
7155 set = single_set (p);
7156 /* If this reload copies only to the secondary reload
7157 register, the secondary reload does the actual
7159 if (s >= 0 && set == NULL_RTX)
7160 /* We can't tell what function the secondary reload
7161 has and where the actual store to the pseudo is
7162 made; leave new_spill_reg_store alone. */
7165 && SET_SRC (set) == rl_reg_rtx
7166 && SET_DEST (set) == rld[s].reg_rtx)
7168 /* Usually the next instruction will be the
7169 secondary reload insn; if we can confirm
7170 that it is, setting new_spill_reg_store to
7171 that insn will allow an extra optimization. */
7172 rtx s_reg = rld[s].reg_rtx;
7173 rtx next = NEXT_INSN (p);
7174 rld[s].out = rl->out;
7175 rld[s].out_reg = rl->out_reg;
7176 set = single_set (next);
7177 if (set && SET_SRC (set) == s_reg
7178 && ! new_spill_reg_store[REGNO (s_reg)])
7180 SET_HARD_REG_BIT (reg_is_output_reload,
7182 new_spill_reg_store[REGNO (s_reg)] = next;
7186 new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7191 if (rl->when_needed == RELOAD_OTHER)
7193 emit_insn (other_output_reload_insns[rl->opnum]);
7194 other_output_reload_insns[rl->opnum] = get_insns ();
7197 output_reload_insns[rl->opnum] = get_insns ();
7199 if (flag_non_call_exceptions)
7200 copy_eh_notes (insn, get_insns ());
7205 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7206 and has the number J. */
7208 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7210 rtx insn = chain->insn;
7211 rtx old = (rl->in && MEM_P (rl->in)
7212 ? rl->in_reg : rl->in);
7213 rtx reg_rtx = rl->reg_rtx;
7217 enum machine_mode mode;
7219 /* Determine the mode to reload in.
7220 This is very tricky because we have three to choose from.
7221 There is the mode the insn operand wants (rl->inmode).
7222 There is the mode of the reload register RELOADREG.
7223 There is the intrinsic mode of the operand, which we could find
7224 by stripping some SUBREGs.
7225 It turns out that RELOADREG's mode is irrelevant:
7226 we can change that arbitrarily.
7228 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7229 then the reload reg may not support QImode moves, so use SImode.
7230 If foo is in memory due to spilling a pseudo reg, this is safe,
7231 because the QImode value is in the least significant part of a
7232 slot big enough for a SImode. If foo is some other sort of
7233 memory reference, then it is impossible to reload this case,
7234 so previous passes had better make sure this never happens.
7236 Then consider a one-word union which has SImode and one of its
7237 members is a float, being fetched as (SUBREG:SF union:SI).
7238 We must fetch that as SFmode because we could be loading into
7239 a float-only register. In this case OLD's mode is correct.
7241 Consider an immediate integer: it has VOIDmode. Here we need
7242 to get a mode from something else.
7244 In some cases, there is a fourth mode, the operand's
7245 containing mode. If the insn specifies a containing mode for
7246 this operand, it overrides all others.
7248 I am not sure whether the algorithm here is always right,
7249 but it does the right things in those cases. */
7251 mode = GET_MODE (old);
7252 if (mode == VOIDmode)
7255 /* We cannot use gen_lowpart_common since it can do the wrong thing
7256 when REG_RTX has a multi-word mode. Note that REG_RTX must
7257 always be a REG here. */
7258 if (GET_MODE (reg_rtx) != mode)
7259 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7261 reload_reg_rtx_for_input[j] = reg_rtx;
7264 /* AUTO_INC reloads need to be handled even if inherited. We got an
7265 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7266 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7267 && ! rtx_equal_p (reg_rtx, old)
7269 emit_input_reload_insns (chain, rld + j, old, j);
7271 /* When inheriting a wider reload, we have a MEM in rl->in,
7272 e.g. inheriting a SImode output reload for
7273 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7274 if (optimize && reload_inherited[j] && rl->in
7276 && MEM_P (rl->in_reg)
7277 && reload_spill_index[j] >= 0
7278 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7279 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7281 /* If we are reloading a register that was recently stored in with an
7282 output-reload, see if we can prove there was
7283 actually no need to store the old value in it. */
7286 && (reload_inherited[j] || reload_override_in[j])
7289 && spill_reg_store[REGNO (reg_rtx)] != 0
7291 /* There doesn't seem to be any reason to restrict this to pseudos
7292 and doing so loses in the case where we are copying from a
7293 register of the wrong class. */
7294 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7296 /* The insn might have already some references to stackslots
7297 replaced by MEMs, while reload_out_reg still names the
7299 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7300 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7301 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7304 /* Do output reloading for reload RL, which is for the insn described by
7305 CHAIN and has the number J.
7306 ??? At some point we need to support handling output reloads of
7307 JUMP_INSNs or insns that set cc0. */
7309 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7312 rtx insn = chain->insn;
7313 /* If this is an output reload that stores something that is
7314 not loaded in this same reload, see if we can eliminate a previous
7316 rtx pseudo = rl->out_reg;
7317 rtx reg_rtx = rl->reg_rtx;
7319 if (rl->out && reg_rtx)
7321 enum machine_mode mode;
7323 /* Determine the mode to reload in.
7324 See comments above (for input reloading). */
7325 mode = GET_MODE (rl->out);
7326 if (mode == VOIDmode)
7328 /* VOIDmode should never happen for an output. */
7329 if (asm_noperands (PATTERN (insn)) < 0)
7330 /* It's the compiler's fault. */
7331 fatal_insn ("VOIDmode on an output", insn);
7332 error_for_asm (insn, "output operand is constant in %<asm%>");
7333 /* Prevent crash--use something we know is valid. */
7335 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7337 if (GET_MODE (reg_rtx) != mode)
7338 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7340 reload_reg_rtx_for_output[j] = reg_rtx;
7345 && ! rtx_equal_p (rl->in_reg, pseudo)
7346 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7347 && reg_last_reload_reg[REGNO (pseudo)])
7349 int pseudo_no = REGNO (pseudo);
7350 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7352 /* We don't need to test full validity of last_regno for
7353 inherit here; we only want to know if the store actually
7354 matches the pseudo. */
7355 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7356 && reg_reloaded_contents[last_regno] == pseudo_no
7357 && spill_reg_store[last_regno]
7358 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7359 delete_output_reload (insn, j, last_regno, reg_rtx);
7365 || rtx_equal_p (old, reg_rtx))
7368 /* An output operand that dies right away does need a reload,
7369 but need not be copied from it. Show the new location in the
7371 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7372 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7374 XEXP (note, 0) = reg_rtx;
7377 /* Likewise for a SUBREG of an operand that dies. */
7378 else if (GET_CODE (old) == SUBREG
7379 && REG_P (SUBREG_REG (old))
7380 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7383 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
7386 else if (GET_CODE (old) == SCRATCH)
7387 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7388 but we don't want to make an output reload. */
7391 /* If is a JUMP_INSN, we can't support output reloads yet. */
7392 gcc_assert (NONJUMP_INSN_P (insn));
7394 emit_output_reload_insns (chain, rld + j, j);
7397 /* A reload copies values of MODE from register SRC to register DEST.
7398 Return true if it can be treated for inheritance purposes like a
7399 group of reloads, each one reloading a single hard register. The
7400 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7401 occupy the same number of hard registers. */
7404 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
7405 int src ATTRIBUTE_UNUSED,
7406 enum machine_mode mode ATTRIBUTE_UNUSED)
7408 #ifdef CANNOT_CHANGE_MODE_CLASS
7409 return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
7410 && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
7416 /* Output insns to reload values in and out of the chosen reload regs. */
7419 emit_reload_insns (struct insn_chain *chain)
7421 rtx insn = chain->insn;
7425 CLEAR_HARD_REG_SET (reg_reloaded_died);
7427 for (j = 0; j < reload_n_operands; j++)
7428 input_reload_insns[j] = input_address_reload_insns[j]
7429 = inpaddr_address_reload_insns[j]
7430 = output_reload_insns[j] = output_address_reload_insns[j]
7431 = outaddr_address_reload_insns[j]
7432 = other_output_reload_insns[j] = 0;
7433 other_input_address_reload_insns = 0;
7434 other_input_reload_insns = 0;
7435 operand_reload_insns = 0;
7436 other_operand_reload_insns = 0;
7438 /* Dump reloads into the dump file. */
7441 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7442 debug_reload_to_stream (dump_file);
7445 /* Now output the instructions to copy the data into and out of the
7446 reload registers. Do these in the order that the reloads were reported,
7447 since reloads of base and index registers precede reloads of operands
7448 and the operands may need the base and index registers reloaded. */
7450 for (j = 0; j < n_reloads; j++)
7452 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
7456 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
7457 new_spill_reg_store[i] = 0;
7460 do_input_reload (chain, rld + j, j);
7461 do_output_reload (chain, rld + j, j);
7464 /* Now write all the insns we made for reloads in the order expected by
7465 the allocation functions. Prior to the insn being reloaded, we write
7466 the following reloads:
7468 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7470 RELOAD_OTHER reloads.
7472 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7473 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7474 RELOAD_FOR_INPUT reload for the operand.
7476 RELOAD_FOR_OPADDR_ADDRS reloads.
7478 RELOAD_FOR_OPERAND_ADDRESS reloads.
7480 After the insn being reloaded, we write the following:
7482 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7483 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7484 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7485 reloads for the operand. The RELOAD_OTHER output reloads are
7486 output in descending order by reload number. */
7488 emit_insn_before (other_input_address_reload_insns, insn);
7489 emit_insn_before (other_input_reload_insns, insn);
7491 for (j = 0; j < reload_n_operands; j++)
7493 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7494 emit_insn_before (input_address_reload_insns[j], insn);
7495 emit_insn_before (input_reload_insns[j], insn);
7498 emit_insn_before (other_operand_reload_insns, insn);
7499 emit_insn_before (operand_reload_insns, insn);
7501 for (j = 0; j < reload_n_operands; j++)
7503 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7504 x = emit_insn_after (output_address_reload_insns[j], x);
7505 x = emit_insn_after (output_reload_insns[j], x);
7506 emit_insn_after (other_output_reload_insns[j], x);
7509 /* For all the spill regs newly reloaded in this instruction,
7510 record what they were reloaded from, so subsequent instructions
7511 can inherit the reloads.
7513 Update spill_reg_store for the reloads of this insn.
7514 Copy the elements that were updated in the loop above. */
7516 for (j = 0; j < n_reloads; j++)
7518 int r = reload_order[j];
7519 int i = reload_spill_index[r];
7521 /* If this is a non-inherited input reload from a pseudo, we must
7522 clear any memory of a previous store to the same pseudo. Only do
7523 something if there will not be an output reload for the pseudo
7525 if (rld[r].in_reg != 0
7526 && ! (reload_inherited[r] || reload_override_in[r]))
7528 rtx reg = rld[r].in_reg;
7530 if (GET_CODE (reg) == SUBREG)
7531 reg = SUBREG_REG (reg);
7534 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7535 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
7537 int nregno = REGNO (reg);
7539 if (reg_last_reload_reg[nregno])
7541 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7543 if (reg_reloaded_contents[last_regno] == nregno)
7544 spill_reg_store[last_regno] = 0;
7549 /* I is nonneg if this reload used a register.
7550 If rld[r].reg_rtx is 0, this is an optional reload
7551 that we opted to ignore. */
7553 if (i >= 0 && rld[r].reg_rtx != 0)
7555 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7558 /* For a multi register reload, we need to check if all or part
7559 of the value lives to the end. */
7560 for (k = 0; k < nr; k++)
7561 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7562 rld[r].when_needed))
7563 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7565 /* Maybe the spill reg contains a copy of reload_out. */
7567 && (REG_P (rld[r].out)
7571 || REG_P (rld[r].out_reg)))
7574 enum machine_mode mode;
7577 reg = reload_reg_rtx_for_output[r];
7578 mode = GET_MODE (reg);
7579 regno = REGNO (reg);
7580 nregs = hard_regno_nregs[regno][mode];
7581 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
7582 rld[r].when_needed))
7584 rtx out = (REG_P (rld[r].out)
7588 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7589 int out_regno = REGNO (out);
7590 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
7591 : hard_regno_nregs[out_regno][mode]);
7594 spill_reg_store[regno] = new_spill_reg_store[regno];
7595 spill_reg_stored_to[regno] = out;
7596 reg_last_reload_reg[out_regno] = reg;
7598 piecemeal = (HARD_REGISTER_NUM_P (out_regno)
7599 && nregs == out_nregs
7600 && inherit_piecemeal_p (out_regno, regno, mode));
7602 /* If OUT_REGNO is a hard register, it may occupy more than
7603 one register. If it does, say what is in the
7604 rest of the registers assuming that both registers
7605 agree on how many words the object takes. If not,
7606 invalidate the subsequent registers. */
7608 if (HARD_REGISTER_NUM_P (out_regno))
7609 for (k = 1; k < out_nregs; k++)
7610 reg_last_reload_reg[out_regno + k]
7611 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
7613 /* Now do the inverse operation. */
7614 for (k = 0; k < nregs; k++)
7616 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
7617 reg_reloaded_contents[regno + k]
7618 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
7621 reg_reloaded_insn[regno + k] = insn;
7622 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
7623 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
7624 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7627 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7632 /* Maybe the spill reg contains a copy of reload_in. Only do
7633 something if there will not be an output reload for
7634 the register being reloaded. */
7635 else if (rld[r].out_reg == 0
7637 && ((REG_P (rld[r].in)
7638 && !HARD_REGISTER_P (rld[r].in)
7639 && !REGNO_REG_SET_P (®_has_output_reload,
7641 || (REG_P (rld[r].in_reg)
7642 && !REGNO_REG_SET_P (®_has_output_reload,
7643 REGNO (rld[r].in_reg))))
7644 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
7647 enum machine_mode mode;
7650 reg = reload_reg_rtx_for_input[r];
7651 mode = GET_MODE (reg);
7652 regno = REGNO (reg);
7653 nregs = hard_regno_nregs[regno][mode];
7654 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
7655 rld[r].when_needed))
7662 if (REG_P (rld[r].in)
7663 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7665 else if (REG_P (rld[r].in_reg))
7668 in = XEXP (rld[r].in_reg, 0);
7669 in_regno = REGNO (in);
7671 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
7672 : hard_regno_nregs[in_regno][mode]);
7674 reg_last_reload_reg[in_regno] = reg;
7676 piecemeal = (HARD_REGISTER_NUM_P (in_regno)
7677 && nregs == in_nregs
7678 && inherit_piecemeal_p (regno, in_regno, mode));
7680 if (HARD_REGISTER_NUM_P (in_regno))
7681 for (k = 1; k < in_nregs; k++)
7682 reg_last_reload_reg[in_regno + k]
7683 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
7685 /* Unless we inherited this reload, show we haven't
7686 recently done a store.
7687 Previous stores of inherited auto_inc expressions
7688 also have to be discarded. */
7689 if (! reload_inherited[r]
7690 || (rld[r].out && ! rld[r].out_reg))
7691 spill_reg_store[regno] = 0;
7693 for (k = 0; k < nregs; k++)
7695 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
7696 reg_reloaded_contents[regno + k]
7697 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
7700 reg_reloaded_insn[regno + k] = insn;
7701 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
7702 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
7703 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7706 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7713 /* The following if-statement was #if 0'd in 1.34 (or before...).
7714 It's reenabled in 1.35 because supposedly nothing else
7715 deals with this problem. */
7717 /* If a register gets output-reloaded from a non-spill register,
7718 that invalidates any previous reloaded copy of it.
7719 But forget_old_reloads_1 won't get to see it, because
7720 it thinks only about the original insn. So invalidate it here.
7721 Also do the same thing for RELOAD_OTHER constraints where the
7722 output is discarded. */
7724 && ((rld[r].out != 0
7725 && (REG_P (rld[r].out)
7726 || (MEM_P (rld[r].out)
7727 && REG_P (rld[r].out_reg))))
7728 || (rld[r].out == 0 && rld[r].out_reg
7729 && REG_P (rld[r].out_reg))))
7731 rtx out = ((rld[r].out && REG_P (rld[r].out))
7732 ? rld[r].out : rld[r].out_reg);
7733 int out_regno = REGNO (out);
7734 enum machine_mode mode = GET_MODE (out);
7736 /* REG_RTX is now set or clobbered by the main instruction.
7737 As the comment above explains, forget_old_reloads_1 only
7738 sees the original instruction, and there is no guarantee
7739 that the original instruction also clobbered REG_RTX.
7740 For example, if find_reloads sees that the input side of
7741 a matched operand pair dies in this instruction, it may
7742 use the input register as the reload register.
7744 Calling forget_old_reloads_1 is a waste of effort if
7745 REG_RTX is also the output register.
7747 If we know that REG_RTX holds the value of a pseudo
7748 register, the code after the call will record that fact. */
7749 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
7750 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
7752 if (!HARD_REGISTER_NUM_P (out_regno))
7754 rtx src_reg, store_insn = NULL_RTX;
7756 reg_last_reload_reg[out_regno] = 0;
7758 /* If we can find a hard register that is stored, record
7759 the storing insn so that we may delete this insn with
7760 delete_output_reload. */
7761 src_reg = reload_reg_rtx_for_output[r];
7763 /* If this is an optional reload, try to find the source reg
7764 from an input reload. */
7767 rtx set = single_set (insn);
7768 if (set && SET_DEST (set) == rld[r].out)
7772 src_reg = SET_SRC (set);
7774 for (k = 0; k < n_reloads; k++)
7776 if (rld[k].in == src_reg)
7778 src_reg = reload_reg_rtx_for_input[k];
7785 store_insn = new_spill_reg_store[REGNO (src_reg)];
7786 if (src_reg && REG_P (src_reg)
7787 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7789 int src_regno, src_nregs, k;
7792 gcc_assert (GET_MODE (src_reg) == mode);
7793 src_regno = REGNO (src_reg);
7794 src_nregs = hard_regno_nregs[src_regno][mode];
7795 /* The place where to find a death note varies with
7796 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7797 necessarily checked exactly in the code that moves
7798 notes, so just check both locations. */
7799 note = find_regno_note (insn, REG_DEAD, src_regno);
7800 if (! note && store_insn)
7801 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7802 for (k = 0; k < src_nregs; k++)
7804 spill_reg_store[src_regno + k] = store_insn;
7805 spill_reg_stored_to[src_regno + k] = out;
7806 reg_reloaded_contents[src_regno + k] = out_regno;
7807 reg_reloaded_insn[src_regno + k] = store_insn;
7808 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
7809 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
7810 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
7812 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7815 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7817 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
7819 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7821 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7823 reg_last_reload_reg[out_regno] = src_reg;
7824 /* We have to set reg_has_output_reload here, or else
7825 forget_old_reloads_1 will clear reg_last_reload_reg
7827 SET_REGNO_REG_SET (®_has_output_reload,
7833 int k, out_nregs = hard_regno_nregs[out_regno][mode];
7835 for (k = 0; k < out_nregs; k++)
7836 reg_last_reload_reg[out_regno + k] = 0;
7840 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7843 /* Go through the motions to emit INSN and test if it is strictly valid.
7844 Return the emitted insn if valid, else return NULL. */
7847 emit_insn_if_valid_for_reload (rtx insn)
7849 rtx last = get_last_insn ();
7852 insn = emit_insn (insn);
7853 code = recog_memoized (insn);
7857 extract_insn (insn);
7858 /* We want constrain operands to treat this insn strictly in its
7859 validity determination, i.e., the way it would after reload has
7861 if (constrain_operands (1))
7865 delete_insns_since (last);
7869 /* Emit code to perform a reload from IN (which may be a reload register) to
7870 OUT (which may also be a reload register). IN or OUT is from operand
7871 OPNUM with reload type TYPE.
7873 Returns first insn emitted. */
7876 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7878 rtx last = get_last_insn ();
7881 /* If IN is a paradoxical SUBREG, remove it and try to put the
7882 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7883 if (GET_CODE (in) == SUBREG
7884 && (GET_MODE_SIZE (GET_MODE (in))
7885 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7886 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7887 in = SUBREG_REG (in), out = tem;
7888 else if (GET_CODE (out) == SUBREG
7889 && (GET_MODE_SIZE (GET_MODE (out))
7890 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7891 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7892 out = SUBREG_REG (out), in = tem;
7894 /* How to do this reload can get quite tricky. Normally, we are being
7895 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7896 register that didn't get a hard register. In that case we can just
7897 call emit_move_insn.
7899 We can also be asked to reload a PLUS that adds a register or a MEM to
7900 another register, constant or MEM. This can occur during frame pointer
7901 elimination and while reloading addresses. This case is handled by
7902 trying to emit a single insn to perform the add. If it is not valid,
7903 we use a two insn sequence.
7905 Or we can be asked to reload an unary operand that was a fragment of
7906 an addressing mode, into a register. If it isn't recognized as-is,
7907 we try making the unop operand and the reload-register the same:
7908 (set reg:X (unop:X expr:Y))
7909 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
7911 Finally, we could be called to handle an 'o' constraint by putting
7912 an address into a register. In that case, we first try to do this
7913 with a named pattern of "reload_load_address". If no such pattern
7914 exists, we just emit a SET insn and hope for the best (it will normally
7915 be valid on machines that use 'o').
7917 This entire process is made complex because reload will never
7918 process the insns we generate here and so we must ensure that
7919 they will fit their constraints and also by the fact that parts of
7920 IN might be being reloaded separately and replaced with spill registers.
7921 Because of this, we are, in some sense, just guessing the right approach
7922 here. The one listed above seems to work.
7924 ??? At some point, this whole thing needs to be rethought. */
7926 if (GET_CODE (in) == PLUS
7927 && (REG_P (XEXP (in, 0))
7928 || GET_CODE (XEXP (in, 0)) == SUBREG
7929 || MEM_P (XEXP (in, 0)))
7930 && (REG_P (XEXP (in, 1))
7931 || GET_CODE (XEXP (in, 1)) == SUBREG
7932 || CONSTANT_P (XEXP (in, 1))
7933 || MEM_P (XEXP (in, 1))))
7935 /* We need to compute the sum of a register or a MEM and another
7936 register, constant, or MEM, and put it into the reload
7937 register. The best possible way of doing this is if the machine
7938 has a three-operand ADD insn that accepts the required operands.
7940 The simplest approach is to try to generate such an insn and see if it
7941 is recognized and matches its constraints. If so, it can be used.
7943 It might be better not to actually emit the insn unless it is valid,
7944 but we need to pass the insn as an operand to `recog' and
7945 `extract_insn' and it is simpler to emit and then delete the insn if
7946 not valid than to dummy things up. */
7948 rtx op0, op1, tem, insn;
7951 op0 = find_replacement (&XEXP (in, 0));
7952 op1 = find_replacement (&XEXP (in, 1));
7954 /* Since constraint checking is strict, commutativity won't be
7955 checked, so we need to do that here to avoid spurious failure
7956 if the add instruction is two-address and the second operand
7957 of the add is the same as the reload reg, which is frequently
7958 the case. If the insn would be A = B + A, rearrange it so
7959 it will be A = A + B as constrain_operands expects. */
7961 if (REG_P (XEXP (in, 1))
7962 && REGNO (out) == REGNO (XEXP (in, 1)))
7963 tem = op0, op0 = op1, op1 = tem;
7965 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7966 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7968 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7972 /* If that failed, we must use a conservative two-insn sequence.
7974 Use a move to copy one operand into the reload register. Prefer
7975 to reload a constant, MEM or pseudo since the move patterns can
7976 handle an arbitrary operand. If OP1 is not a constant, MEM or
7977 pseudo and OP1 is not a valid operand for an add instruction, then
7980 After reloading one of the operands into the reload register, add
7981 the reload register to the output register.
7983 If there is another way to do this for a specific machine, a
7984 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7987 code = (int) optab_handler (add_optab, GET_MODE (out))->insn_code;
7989 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7991 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7992 || (code != CODE_FOR_nothing
7993 && ! ((*insn_data[code].operand[2].predicate)
7994 (op1, insn_data[code].operand[2].mode))))
7995 tem = op0, op0 = op1, op1 = tem;
7997 gen_reload (out, op0, opnum, type);
7999 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8000 This fixes a problem on the 32K where the stack pointer cannot
8001 be used as an operand of an add insn. */
8003 if (rtx_equal_p (op0, op1))
8006 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8009 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8010 set_unique_reg_note (insn, REG_EQUIV, in);
8014 /* If that failed, copy the address register to the reload register.
8015 Then add the constant to the reload register. */
8017 gcc_assert (!reg_overlap_mentioned_p (out, op0));
8018 gen_reload (out, op1, opnum, type);
8019 insn = emit_insn (gen_add2_insn (out, op0));
8020 set_unique_reg_note (insn, REG_EQUIV, in);
8023 #ifdef SECONDARY_MEMORY_NEEDED
8024 /* If we need a memory location to do the move, do it that way. */
8025 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
8026 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
8027 && (REG_P (out) || GET_CODE (out) == SUBREG)
8028 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
8029 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
8030 REGNO_REG_CLASS (reg_or_subregno (out)),
8033 /* Get the memory to use and rewrite both registers to its mode. */
8034 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8036 if (GET_MODE (loc) != GET_MODE (out))
8037 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
8039 if (GET_MODE (loc) != GET_MODE (in))
8040 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
8042 gen_reload (loc, in, opnum, type);
8043 gen_reload (out, loc, opnum, type);
8046 else if (REG_P (out) && UNARY_P (in))
8053 op1 = find_replacement (&XEXP (in, 0));
8054 if (op1 != XEXP (in, 0))
8055 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8057 /* First, try a plain SET. */
8058 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8062 /* If that failed, move the inner operand to the reload
8063 register, and try the same unop with the inner expression
8064 replaced with the reload register. */
8066 if (GET_MODE (op1) != GET_MODE (out))
8067 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8071 gen_reload (out_moded, op1, opnum, type);
8074 = gen_rtx_SET (VOIDmode, out,
8075 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8077 insn = emit_insn_if_valid_for_reload (insn);
8080 set_unique_reg_note (insn, REG_EQUIV, in);
8084 fatal_insn ("Failure trying to reload:", set);
8086 /* If IN is a simple operand, use gen_move_insn. */
8087 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8089 tem = emit_insn (gen_move_insn (out, in));
8090 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8091 mark_jump_label (in, tem, 0);
8094 #ifdef HAVE_reload_load_address
8095 else if (HAVE_reload_load_address)
8096 emit_insn (gen_reload_load_address (out, in));
8099 /* Otherwise, just write (set OUT IN) and hope for the best. */
8101 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8103 /* Return the first insn emitted.
8104 We can not just return get_last_insn, because there may have
8105 been multiple instructions emitted. Also note that gen_move_insn may
8106 emit more than one insn itself, so we can not assume that there is one
8107 insn emitted per emit_insn_before call. */
8109 return last ? NEXT_INSN (last) : get_insns ();
8112 /* Delete a previously made output-reload whose result we now believe
8113 is not needed. First we double-check.
8115 INSN is the insn now being processed.
8116 LAST_RELOAD_REG is the hard register number for which we want to delete
8117 the last output reload.
8118 J is the reload-number that originally used REG. The caller has made
8119 certain that reload J doesn't use REG any longer for input.
8120 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8123 delete_output_reload (rtx insn, int j, int last_reload_reg, rtx new_reload_reg)
8125 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8126 rtx reg = spill_reg_stored_to[last_reload_reg];
8129 int n_inherited = 0;
8133 /* It is possible that this reload has been only used to set another reload
8134 we eliminated earlier and thus deleted this instruction too. */
8135 if (INSN_DELETED_P (output_reload_insn))
8138 /* Get the raw pseudo-register referred to. */
8140 while (GET_CODE (reg) == SUBREG)
8141 reg = SUBREG_REG (reg);
8142 substed = reg_equiv_memory_loc[REGNO (reg)];
8144 /* This is unsafe if the operand occurs more often in the current
8145 insn than it is inherited. */
8146 for (k = n_reloads - 1; k >= 0; k--)
8148 rtx reg2 = rld[k].in;
8151 if (MEM_P (reg2) || reload_override_in[k])
8152 reg2 = rld[k].in_reg;
8154 if (rld[k].out && ! rld[k].out_reg)
8155 reg2 = XEXP (rld[k].in_reg, 0);
8157 while (GET_CODE (reg2) == SUBREG)
8158 reg2 = SUBREG_REG (reg2);
8159 if (rtx_equal_p (reg2, reg))
8161 if (reload_inherited[k] || reload_override_in[k] || k == j)
8167 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8168 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8169 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8172 n_occurrences += count_occurrences (PATTERN (insn),
8173 eliminate_regs (substed, 0,
8175 for (i1 = reg_equiv_alt_mem_list [REGNO (reg)]; i1; i1 = XEXP (i1, 1))
8177 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8178 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8180 if (n_occurrences > n_inherited)
8183 /* If the pseudo-reg we are reloading is no longer referenced
8184 anywhere between the store into it and here,
8185 and we're within the same basic block, then the value can only
8186 pass through the reload reg and end up here.
8187 Otherwise, give up--return. */
8188 for (i1 = NEXT_INSN (output_reload_insn);
8189 i1 != insn; i1 = NEXT_INSN (i1))
8191 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8193 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8194 && reg_mentioned_p (reg, PATTERN (i1)))
8196 /* If this is USE in front of INSN, we only have to check that
8197 there are no more references than accounted for by inheritance. */
8198 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8200 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8201 i1 = NEXT_INSN (i1);
8203 if (n_occurrences <= n_inherited && i1 == insn)
8209 /* We will be deleting the insn. Remove the spill reg information. */
8210 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8212 spill_reg_store[last_reload_reg + k] = 0;
8213 spill_reg_stored_to[last_reload_reg + k] = 0;
8216 /* The caller has already checked that REG dies or is set in INSN.
8217 It has also checked that we are optimizing, and thus some
8218 inaccuracies in the debugging information are acceptable.
8219 So we could just delete output_reload_insn. But in some cases
8220 we can improve the debugging information without sacrificing
8221 optimization - maybe even improving the code: See if the pseudo
8222 reg has been completely replaced with reload regs. If so, delete
8223 the store insn and forget we had a stack slot for the pseudo. */
8224 if (rld[j].out != rld[j].in
8225 && REG_N_DEATHS (REGNO (reg)) == 1
8226 && REG_N_SETS (REGNO (reg)) == 1
8227 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8228 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8232 /* We know that it was used only between here and the beginning of
8233 the current basic block. (We also know that the last use before
8234 INSN was the output reload we are thinking of deleting, but never
8235 mind that.) Search that range; see if any ref remains. */
8236 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8238 rtx set = single_set (i2);
8240 /* Uses which just store in the pseudo don't count,
8241 since if they are the only uses, they are dead. */
8242 if (set != 0 && SET_DEST (set) == reg)
8247 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8248 && reg_mentioned_p (reg, PATTERN (i2)))
8250 /* Some other ref remains; just delete the output reload we
8252 delete_address_reloads (output_reload_insn, insn);
8253 delete_insn (output_reload_insn);
8258 /* Delete the now-dead stores into this pseudo. Note that this
8259 loop also takes care of deleting output_reload_insn. */
8260 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8262 rtx set = single_set (i2);
8264 if (set != 0 && SET_DEST (set) == reg)
8266 delete_address_reloads (i2, insn);
8274 /* For the debugging info, say the pseudo lives in this reload reg. */
8275 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8276 alter_reg (REGNO (reg), -1);
8280 delete_address_reloads (output_reload_insn, insn);
8281 delete_insn (output_reload_insn);
8285 /* We are going to delete DEAD_INSN. Recursively delete loads of
8286 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8287 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8289 delete_address_reloads (rtx dead_insn, rtx current_insn)
8291 rtx set = single_set (dead_insn);
8292 rtx set2, dst, prev, next;
8295 rtx dst = SET_DEST (set);
8297 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8299 /* If we deleted the store from a reloaded post_{in,de}c expression,
8300 we can delete the matching adds. */
8301 prev = PREV_INSN (dead_insn);
8302 next = NEXT_INSN (dead_insn);
8303 if (! prev || ! next)
8305 set = single_set (next);
8306 set2 = single_set (prev);
8308 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8309 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8310 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8312 dst = SET_DEST (set);
8313 if (! rtx_equal_p (dst, SET_DEST (set2))
8314 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8315 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8316 || (INTVAL (XEXP (SET_SRC (set), 1))
8317 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8319 delete_related_insns (prev);
8320 delete_related_insns (next);
8323 /* Subfunction of delete_address_reloads: process registers found in X. */
8325 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8327 rtx prev, set, dst, i2;
8329 enum rtx_code code = GET_CODE (x);
8333 const char *fmt = GET_RTX_FORMAT (code);
8334 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8337 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8338 else if (fmt[i] == 'E')
8340 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8341 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8348 if (spill_reg_order[REGNO (x)] < 0)
8351 /* Scan backwards for the insn that sets x. This might be a way back due
8353 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8355 code = GET_CODE (prev);
8356 if (code == CODE_LABEL || code == JUMP_INSN)
8360 if (reg_set_p (x, PATTERN (prev)))
8362 if (reg_referenced_p (x, PATTERN (prev)))
8365 if (! prev || INSN_UID (prev) < reload_first_uid)
8367 /* Check that PREV only sets the reload register. */
8368 set = single_set (prev);
8371 dst = SET_DEST (set);
8373 || ! rtx_equal_p (dst, x))
8375 if (! reg_set_p (dst, PATTERN (dead_insn)))
8377 /* Check if DST was used in a later insn -
8378 it might have been inherited. */
8379 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8385 if (reg_referenced_p (dst, PATTERN (i2)))
8387 /* If there is a reference to the register in the current insn,
8388 it might be loaded in a non-inherited reload. If no other
8389 reload uses it, that means the register is set before
8391 if (i2 == current_insn)
8393 for (j = n_reloads - 1; j >= 0; j--)
8394 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8395 || reload_override_in[j] == dst)
8397 for (j = n_reloads - 1; j >= 0; j--)
8398 if (rld[j].in && rld[j].reg_rtx == dst)
8407 /* If DST is still live at CURRENT_INSN, check if it is used for
8408 any reload. Note that even if CURRENT_INSN sets DST, we still
8409 have to check the reloads. */
8410 if (i2 == current_insn)
8412 for (j = n_reloads - 1; j >= 0; j--)
8413 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8414 || reload_override_in[j] == dst)
8416 /* ??? We can't finish the loop here, because dst might be
8417 allocated to a pseudo in this block if no reload in this
8418 block needs any of the classes containing DST - see
8419 spill_hard_reg. There is no easy way to tell this, so we
8420 have to scan till the end of the basic block. */
8422 if (reg_set_p (dst, PATTERN (i2)))
8426 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8427 reg_reloaded_contents[REGNO (dst)] = -1;
8431 /* Output reload-insns to reload VALUE into RELOADREG.
8432 VALUE is an autoincrement or autodecrement RTX whose operand
8433 is a register or memory location;
8434 so reloading involves incrementing that location.
8435 IN is either identical to VALUE, or some cheaper place to reload from.
8437 INC_AMOUNT is the number to increment or decrement by (always positive).
8438 This cannot be deduced from VALUE.
8440 Return the instruction that stores into RELOADREG. */
8443 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8445 /* REG or MEM to be copied and incremented. */
8446 rtx incloc = find_replacement (&XEXP (value, 0));
8447 /* Nonzero if increment after copying. */
8448 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8449 || GET_CODE (value) == POST_MODIFY);
8455 rtx real_in = in == value ? incloc : in;
8457 /* No hard register is equivalent to this register after
8458 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8459 we could inc/dec that register as well (maybe even using it for
8460 the source), but I'm not sure it's worth worrying about. */
8462 reg_last_reload_reg[REGNO (incloc)] = 0;
8464 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8466 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8467 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
8471 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8472 inc_amount = -inc_amount;
8474 inc = GEN_INT (inc_amount);
8477 /* If this is post-increment, first copy the location to the reload reg. */
8478 if (post && real_in != reloadreg)
8479 emit_insn (gen_move_insn (reloadreg, real_in));
8483 /* See if we can directly increment INCLOC. Use a method similar to
8484 that in gen_reload. */
8486 last = get_last_insn ();
8487 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8488 gen_rtx_PLUS (GET_MODE (incloc),
8491 code = recog_memoized (add_insn);
8494 extract_insn (add_insn);
8495 if (constrain_operands (1))
8497 /* If this is a pre-increment and we have incremented the value
8498 where it lives, copy the incremented value to RELOADREG to
8499 be used as an address. */
8502 emit_insn (gen_move_insn (reloadreg, incloc));
8507 delete_insns_since (last);
8510 /* If couldn't do the increment directly, must increment in RELOADREG.
8511 The way we do this depends on whether this is pre- or post-increment.
8512 For pre-increment, copy INCLOC to the reload register, increment it
8513 there, then save back. */
8517 if (in != reloadreg)
8518 emit_insn (gen_move_insn (reloadreg, real_in));
8519 emit_insn (gen_add2_insn (reloadreg, inc));
8520 store = emit_insn (gen_move_insn (incloc, reloadreg));
8525 Because this might be a jump insn or a compare, and because RELOADREG
8526 may not be available after the insn in an input reload, we must do
8527 the incrementation before the insn being reloaded for.
8529 We have already copied IN to RELOADREG. Increment the copy in
8530 RELOADREG, save that back, then decrement RELOADREG so it has
8531 the original value. */
8533 emit_insn (gen_add2_insn (reloadreg, inc));
8534 store = emit_insn (gen_move_insn (incloc, reloadreg));
8535 if (GET_CODE (inc) == CONST_INT)
8536 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
8538 emit_insn (gen_sub2_insn (reloadreg, inc));
8546 add_auto_inc_notes (rtx insn, rtx x)
8548 enum rtx_code code = GET_CODE (x);
8552 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8555 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8559 /* Scan all the operand sub-expressions. */
8560 fmt = GET_RTX_FORMAT (code);
8561 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8564 add_auto_inc_notes (insn, XEXP (x, i));
8565 else if (fmt[i] == 'E')
8566 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8567 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8572 /* Copy EH notes from an insn to its reloads. */
8574 copy_eh_notes (rtx insn, rtx x)
8576 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8579 for (; x != 0; x = NEXT_INSN (x))
8581 if (may_trap_p (PATTERN (x)))
8583 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8589 /* This is used by reload pass, that does emit some instructions after
8590 abnormal calls moving basic block end, but in fact it wants to emit
8591 them on the edge. Looks for abnormal call edges, find backward the
8592 proper call and fix the damage.
8594 Similar handle instructions throwing exceptions internally. */
8596 fixup_abnormal_edges (void)
8598 bool inserted = false;
8606 /* Look for cases we are interested in - calls or instructions causing
8608 FOR_EACH_EDGE (e, ei, bb->succs)
8610 if (e->flags & EDGE_ABNORMAL_CALL)
8612 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8613 == (EDGE_ABNORMAL | EDGE_EH))
8616 if (e && !CALL_P (BB_END (bb))
8617 && !can_throw_internal (BB_END (bb)))
8621 /* Get past the new insns generated. Allow notes, as the insns
8622 may be already deleted. */
8624 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8625 && !can_throw_internal (insn)
8626 && insn != BB_HEAD (bb))
8627 insn = PREV_INSN (insn);
8629 if (CALL_P (insn) || can_throw_internal (insn))
8633 stop = NEXT_INSN (BB_END (bb));
8635 insn = NEXT_INSN (insn);
8637 FOR_EACH_EDGE (e, ei, bb->succs)
8638 if (e->flags & EDGE_FALLTHRU)
8641 while (insn && insn != stop)
8643 next = NEXT_INSN (insn);
8648 /* Sometimes there's still the return value USE.
8649 If it's placed after a trapping call (i.e. that
8650 call is the last insn anyway), we have no fallthru
8651 edge. Simply delete this use and don't try to insert
8652 on the non-existent edge. */
8653 if (GET_CODE (PATTERN (insn)) != USE)
8655 /* We're not deleting it, we're moving it. */
8656 INSN_DELETED_P (insn) = 0;
8657 PREV_INSN (insn) = NULL_RTX;
8658 NEXT_INSN (insn) = NULL_RTX;
8660 insert_insn_on_edge (insn, e);
8664 else if (!BARRIER_P (insn))
8665 set_block_for_insn (insn, NULL);
8670 /* It may be that we don't find any such trapping insn. In this
8671 case we discovered quite late that the insn that had been
8672 marked as can_throw_internal in fact couldn't trap at all.
8673 So we should in fact delete the EH edges out of the block. */
8675 purge_dead_edges (bb);
8679 /* We've possibly turned single trapping insn into multiple ones. */
8680 if (flag_non_call_exceptions)
8683 blocks = sbitmap_alloc (last_basic_block);
8684 sbitmap_ones (blocks);
8685 find_many_sub_basic_blocks (blocks);
8686 sbitmap_free (blocks);
8690 commit_edge_insertions ();
8692 #ifdef ENABLE_CHECKING
8693 /* Verify that we didn't turn one trapping insn into many, and that
8694 we found and corrected all of the problems wrt fixups on the
8696 verify_flow_info ();
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