1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "rtl-error.h"
32 #include "insn-config.h"
38 #include "addresses.h"
39 #include "basic-block.h"
50 /* This file contains the reload pass of the compiler, which is
51 run after register allocation has been done. It checks that
52 each insn is valid (operands required to be in registers really
53 are in registers of the proper class) and fixes up invalid ones
54 by copying values temporarily into registers for the insns
57 The results of register allocation are described by the vector
58 reg_renumber; the insns still contain pseudo regs, but reg_renumber
59 can be used to find which hard reg, if any, a pseudo reg is in.
61 The technique we always use is to free up a few hard regs that are
62 called ``reload regs'', and for each place where a pseudo reg
63 must be in a hard reg, copy it temporarily into one of the reload regs.
65 Reload regs are allocated locally for every instruction that needs
66 reloads. When there are pseudos which are allocated to a register that
67 has been chosen as a reload reg, such pseudos must be ``spilled''.
68 This means that they go to other hard regs, or to stack slots if no other
69 available hard regs can be found. Spilling can invalidate more
70 insns, requiring additional need for reloads, so we must keep checking
71 until the process stabilizes.
73 For machines with different classes of registers, we must keep track
74 of the register class needed for each reload, and make sure that
75 we allocate enough reload registers of each class.
77 The file reload.c contains the code that checks one insn for
78 validity and reports the reloads that it needs. This file
79 is in charge of scanning the entire rtl code, accumulating the
80 reload needs, spilling, assigning reload registers to use for
81 fixing up each insn, and generating the new insns to copy values
82 into the reload registers. */
84 struct target_reload default_target_reload;
86 struct target_reload *this_target_reload = &default_target_reload;
89 #define spill_indirect_levels \
90 (this_target_reload->x_spill_indirect_levels)
92 /* During reload_as_needed, element N contains a REG rtx for the hard reg
93 into which reg N has been reloaded (perhaps for a previous insn). */
94 static rtx *reg_last_reload_reg;
96 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
97 for an output reload that stores into reg N. */
98 static regset_head reg_has_output_reload;
100 /* Indicates which hard regs are reload-registers for an output reload
101 in the current insn. */
102 static HARD_REG_SET reg_is_output_reload;
104 /* Element N is the constant value to which pseudo reg N is equivalent,
105 or zero if pseudo reg N is not equivalent to a constant.
106 find_reloads looks at this in order to replace pseudo reg N
107 with the constant it stands for. */
108 rtx *reg_equiv_constant;
110 /* Element N is an invariant value to which pseudo reg N is equivalent.
111 eliminate_regs_in_insn uses this to replace pseudos in particular
113 rtx *reg_equiv_invariant;
115 /* Element N is a memory location to which pseudo reg N is equivalent,
116 prior to any register elimination (such as frame pointer to stack
117 pointer). Depending on whether or not it is a valid address, this value
118 is transferred to either reg_equiv_address or reg_equiv_mem. */
119 rtx *reg_equiv_memory_loc;
121 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
122 collector can keep track of what is inside. */
123 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
125 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
126 This is used when the address is not valid as a memory address
127 (because its displacement is too big for the machine.) */
128 rtx *reg_equiv_address;
130 /* Element N is the memory slot to which pseudo reg N is equivalent,
131 or zero if pseudo reg N is not equivalent to a memory slot. */
134 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
135 alternate representations of the location of pseudo reg N. */
136 rtx *reg_equiv_alt_mem_list;
138 /* Widest width in which each pseudo reg is referred to (via subreg). */
139 static unsigned int *reg_max_ref_width;
141 /* Element N is the list of insns that initialized reg N from its equivalent
142 constant or memory slot. */
144 int reg_equiv_init_size;
146 /* Vector to remember old contents of reg_renumber before spilling. */
147 static short *reg_old_renumber;
149 /* During reload_as_needed, element N contains the last pseudo regno reloaded
150 into hard register N. If that pseudo reg occupied more than one register,
151 reg_reloaded_contents points to that pseudo for each spill register in
152 use; all of these must remain set for an inheritance to occur. */
153 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
155 /* During reload_as_needed, element N contains the insn for which
156 hard register N was last used. Its contents are significant only
157 when reg_reloaded_valid is set for this register. */
158 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
160 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
161 static HARD_REG_SET reg_reloaded_valid;
162 /* Indicate if the register was dead at the end of the reload.
163 This is only valid if reg_reloaded_contents is set and valid. */
164 static HARD_REG_SET reg_reloaded_dead;
166 /* Indicate whether the register's current value is one that is not
167 safe to retain across a call, even for registers that are normally
168 call-saved. This is only meaningful for members of reg_reloaded_valid. */
169 static HARD_REG_SET reg_reloaded_call_part_clobbered;
171 /* Number of spill-regs so far; number of valid elements of spill_regs. */
174 /* In parallel with spill_regs, contains REG rtx's for those regs.
175 Holds the last rtx used for any given reg, or 0 if it has never
176 been used for spilling yet. This rtx is reused, provided it has
178 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
180 /* In parallel with spill_regs, contains nonzero for a spill reg
181 that was stored after the last time it was used.
182 The precise value is the insn generated to do the store. */
183 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
185 /* This is the register that was stored with spill_reg_store. This is a
186 copy of reload_out / reload_out_reg when the value was stored; if
187 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
188 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
190 /* This table is the inverse mapping of spill_regs:
191 indexed by hard reg number,
192 it contains the position of that reg in spill_regs,
193 or -1 for something that is not in spill_regs.
195 ?!? This is no longer accurate. */
196 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
198 /* This reg set indicates registers that can't be used as spill registers for
199 the currently processed insn. These are the hard registers which are live
200 during the insn, but not allocated to pseudos, as well as fixed
202 static HARD_REG_SET bad_spill_regs;
204 /* These are the hard registers that can't be used as spill register for any
205 insn. This includes registers used for user variables and registers that
206 we can't eliminate. A register that appears in this set also can't be used
207 to retry register allocation. */
208 static HARD_REG_SET bad_spill_regs_global;
210 /* Describes order of use of registers for reloading
211 of spilled pseudo-registers. `n_spills' is the number of
212 elements that are actually valid; new ones are added at the end.
214 Both spill_regs and spill_reg_order are used on two occasions:
215 once during find_reload_regs, where they keep track of the spill registers
216 for a single insn, but also during reload_as_needed where they show all
217 the registers ever used by reload. For the latter case, the information
218 is calculated during finish_spills. */
219 static short spill_regs[FIRST_PSEUDO_REGISTER];
221 /* This vector of reg sets indicates, for each pseudo, which hard registers
222 may not be used for retrying global allocation because the register was
223 formerly spilled from one of them. If we allowed reallocating a pseudo to
224 a register that it was already allocated to, reload might not
226 static HARD_REG_SET *pseudo_previous_regs;
228 /* This vector of reg sets indicates, for each pseudo, which hard
229 registers may not be used for retrying global allocation because they
230 are used as spill registers during one of the insns in which the
232 static HARD_REG_SET *pseudo_forbidden_regs;
234 /* All hard regs that have been used as spill registers for any insn are
235 marked in this set. */
236 static HARD_REG_SET used_spill_regs;
238 /* Index of last register assigned as a spill register. We allocate in
239 a round-robin fashion. */
240 static int last_spill_reg;
242 /* Record the stack slot for each spilled hard register. */
243 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
245 /* Width allocated so far for that stack slot. */
246 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
248 /* Record which pseudos needed to be spilled. */
249 static regset_head spilled_pseudos;
251 /* Record which pseudos changed their allocation in finish_spills. */
252 static regset_head changed_allocation_pseudos;
254 /* Used for communication between order_regs_for_reload and count_pseudo.
255 Used to avoid counting one pseudo twice. */
256 static regset_head pseudos_counted;
258 /* First uid used by insns created by reload in this function.
259 Used in find_equiv_reg. */
260 int reload_first_uid;
262 /* Flag set by local-alloc or global-alloc if anything is live in
263 a call-clobbered reg across calls. */
264 int caller_save_needed;
266 /* Set to 1 while reload_as_needed is operating.
267 Required by some machines to handle any generated moves differently. */
268 int reload_in_progress = 0;
270 /* This obstack is used for allocation of rtl during register elimination.
271 The allocated storage can be freed once find_reloads has processed the
273 static struct obstack reload_obstack;
275 /* Points to the beginning of the reload_obstack. All insn_chain structures
276 are allocated first. */
277 static char *reload_startobj;
279 /* The point after all insn_chain structures. Used to quickly deallocate
280 memory allocated in copy_reloads during calculate_needs_all_insns. */
281 static char *reload_firstobj;
283 /* This points before all local rtl generated by register elimination.
284 Used to quickly free all memory after processing one insn. */
285 static char *reload_insn_firstobj;
287 /* List of insn_chain instructions, one for every insn that reload needs to
289 struct insn_chain *reload_insn_chain;
291 /* List of all insns needing reloads. */
292 static struct insn_chain *insns_need_reload;
294 /* This structure is used to record information about register eliminations.
295 Each array entry describes one possible way of eliminating a register
296 in favor of another. If there is more than one way of eliminating a
297 particular register, the most preferred should be specified first. */
301 int from; /* Register number to be eliminated. */
302 int to; /* Register number used as replacement. */
303 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
304 int can_eliminate; /* Nonzero if this elimination can be done. */
305 int can_eliminate_previous; /* Value returned by TARGET_CAN_ELIMINATE
306 target hook in previous scan over insns
308 HOST_WIDE_INT offset; /* Current offset between the two regs. */
309 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
310 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
311 rtx from_rtx; /* REG rtx for the register to be eliminated.
312 We cannot simply compare the number since
313 we might then spuriously replace a hard
314 register corresponding to a pseudo
315 assigned to the reg to be eliminated. */
316 rtx to_rtx; /* REG rtx for the replacement. */
319 static struct elim_table *reg_eliminate = 0;
321 /* This is an intermediate structure to initialize the table. It has
322 exactly the members provided by ELIMINABLE_REGS. */
323 static const struct elim_table_1
327 } reg_eliminate_1[] =
329 /* If a set of eliminable registers was specified, define the table from it.
330 Otherwise, default to the normal case of the frame pointer being
331 replaced by the stack pointer. */
333 #ifdef ELIMINABLE_REGS
336 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
339 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
341 /* Record the number of pending eliminations that have an offset not equal
342 to their initial offset. If nonzero, we use a new copy of each
343 replacement result in any insns encountered. */
344 int num_not_at_initial_offset;
346 /* Count the number of registers that we may be able to eliminate. */
347 static int num_eliminable;
348 /* And the number of registers that are equivalent to a constant that
349 can be eliminated to frame_pointer / arg_pointer + constant. */
350 static int num_eliminable_invariants;
352 /* For each label, we record the offset of each elimination. If we reach
353 a label by more than one path and an offset differs, we cannot do the
354 elimination. This information is indexed by the difference of the
355 number of the label and the first label number. We can't offset the
356 pointer itself as this can cause problems on machines with segmented
357 memory. The first table is an array of flags that records whether we
358 have yet encountered a label and the second table is an array of arrays,
359 one entry in the latter array for each elimination. */
361 static int first_label_num;
362 static char *offsets_known_at;
363 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
365 /* Stack of addresses where an rtx has been changed. We can undo the
366 changes by popping items off the stack and restoring the original
367 value at each location.
369 We use this simplistic undo capability rather than copy_rtx as copy_rtx
370 will not make a deep copy of a normally sharable rtx, such as
371 (const (plus (symbol_ref) (const_int))). If such an expression appears
372 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
373 rtx expression would be changed. See PR 42431. */
377 DEF_VEC_ALLOC_P(rtx_p,heap);
378 static VEC(rtx_p,heap) *substitute_stack;
380 /* Number of labels in the current function. */
382 static int num_labels;
384 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
385 static void maybe_fix_stack_asms (void);
386 static void copy_reloads (struct insn_chain *);
387 static void calculate_needs_all_insns (int);
388 static int find_reg (struct insn_chain *, int);
389 static void find_reload_regs (struct insn_chain *);
390 static void select_reload_regs (void);
391 static void delete_caller_save_insns (void);
393 static void spill_failure (rtx, enum reg_class);
394 static void count_spilled_pseudo (int, int, int);
395 static void delete_dead_insn (rtx);
396 static void alter_reg (int, int, bool);
397 static void set_label_offsets (rtx, rtx, int);
398 static void check_eliminable_occurrences (rtx);
399 static void elimination_effects (rtx, enum machine_mode);
400 static rtx eliminate_regs_1 (rtx, enum machine_mode, rtx, bool, bool);
401 static int eliminate_regs_in_insn (rtx, int);
402 static void update_eliminable_offsets (void);
403 static void mark_not_eliminable (rtx, const_rtx, void *);
404 static void set_initial_elim_offsets (void);
405 static bool verify_initial_elim_offsets (void);
406 static void set_initial_label_offsets (void);
407 static void set_offsets_for_label (rtx);
408 static void init_eliminable_invariants (rtx, bool);
409 static void init_elim_table (void);
410 static void free_reg_equiv (void);
411 static void update_eliminables (HARD_REG_SET *);
412 static void elimination_costs_in_insn (rtx);
413 static void spill_hard_reg (unsigned int, int);
414 static int finish_spills (int);
415 static void scan_paradoxical_subregs (rtx);
416 static void count_pseudo (int);
417 static void order_regs_for_reload (struct insn_chain *);
418 static void reload_as_needed (int);
419 static void forget_old_reloads_1 (rtx, const_rtx, void *);
420 static void forget_marked_reloads (regset);
421 static int reload_reg_class_lower (const void *, const void *);
422 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
424 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
426 static int reload_reg_free_p (unsigned int, int, enum reload_type);
427 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
429 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
431 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
432 static int allocate_reload_reg (struct insn_chain *, int, int);
433 static int conflicts_with_override (rtx);
434 static void failed_reload (rtx, int);
435 static int set_reload_reg (int, int);
436 static void choose_reload_regs_init (struct insn_chain *, rtx *);
437 static void choose_reload_regs (struct insn_chain *);
438 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
440 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
442 static void do_input_reload (struct insn_chain *, struct reload *, int);
443 static void do_output_reload (struct insn_chain *, struct reload *, int);
444 static void emit_reload_insns (struct insn_chain *);
445 static void delete_output_reload (rtx, int, int, rtx);
446 static void delete_address_reloads (rtx, rtx);
447 static void delete_address_reloads_1 (rtx, rtx, rtx);
448 static rtx inc_for_reload (rtx, rtx, rtx, int);
450 static void add_auto_inc_notes (rtx, rtx);
452 static void substitute (rtx *, const_rtx, rtx);
453 static bool gen_reload_chain_without_interm_reg_p (int, int);
454 static int reloads_conflict (int, int);
455 static rtx gen_reload (rtx, rtx, int, enum reload_type);
456 static rtx emit_insn_if_valid_for_reload (rtx);
458 /* Initialize the reload pass. This is called at the beginning of compilation
459 and may be called again if the target is reinitialized. */
466 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
467 Set spill_indirect_levels to the number of levels such addressing is
468 permitted, zero if it is not permitted at all. */
471 = gen_rtx_MEM (Pmode,
474 LAST_VIRTUAL_REGISTER + 1),
476 spill_indirect_levels = 0;
478 while (memory_address_p (QImode, tem))
480 spill_indirect_levels++;
481 tem = gen_rtx_MEM (Pmode, tem);
484 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
486 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
487 indirect_symref_ok = memory_address_p (QImode, tem);
489 /* See if reg+reg is a valid (and offsettable) address. */
491 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
493 tem = gen_rtx_PLUS (Pmode,
494 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
495 gen_rtx_REG (Pmode, i));
497 /* This way, we make sure that reg+reg is an offsettable address. */
498 tem = plus_constant (tem, 4);
500 if (memory_address_p (QImode, tem))
502 double_reg_address_ok = 1;
507 /* Initialize obstack for our rtl allocation. */
508 gcc_obstack_init (&reload_obstack);
509 reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
511 INIT_REG_SET (&spilled_pseudos);
512 INIT_REG_SET (&changed_allocation_pseudos);
513 INIT_REG_SET (&pseudos_counted);
516 /* List of insn chains that are currently unused. */
517 static struct insn_chain *unused_insn_chains = 0;
519 /* Allocate an empty insn_chain structure. */
521 new_insn_chain (void)
523 struct insn_chain *c;
525 if (unused_insn_chains == 0)
527 c = XOBNEW (&reload_obstack, struct insn_chain);
528 INIT_REG_SET (&c->live_throughout);
529 INIT_REG_SET (&c->dead_or_set);
533 c = unused_insn_chains;
534 unused_insn_chains = c->next;
536 c->is_caller_save_insn = 0;
537 c->need_operand_change = 0;
543 /* Small utility function to set all regs in hard reg set TO which are
544 allocated to pseudos in regset FROM. */
547 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
550 reg_set_iterator rsi;
552 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
554 int r = reg_renumber[regno];
558 /* reload_combine uses the information from DF_LIVE_IN,
559 which might still contain registers that have not
560 actually been allocated since they have an
562 gcc_assert (ira_conflicts_p || reload_completed);
565 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
569 /* Replace all pseudos found in LOC with their corresponding
573 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
586 unsigned int regno = REGNO (x);
588 if (regno < FIRST_PSEUDO_REGISTER)
591 x = eliminate_regs (x, mem_mode, usage);
595 replace_pseudos_in (loc, mem_mode, usage);
599 if (reg_equiv_constant[regno])
600 *loc = reg_equiv_constant[regno];
601 else if (reg_equiv_mem[regno])
602 *loc = reg_equiv_mem[regno];
603 else if (reg_equiv_address[regno])
604 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
607 gcc_assert (!REG_P (regno_reg_rtx[regno])
608 || REGNO (regno_reg_rtx[regno]) != regno);
609 *loc = regno_reg_rtx[regno];
614 else if (code == MEM)
616 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
620 /* Process each of our operands recursively. */
621 fmt = GET_RTX_FORMAT (code);
622 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
624 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
625 else if (*fmt == 'E')
626 for (j = 0; j < XVECLEN (x, i); j++)
627 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
630 /* Determine if the current function has an exception receiver block
631 that reaches the exit block via non-exceptional edges */
634 has_nonexceptional_receiver (void)
638 basic_block *tos, *worklist, bb;
640 /* If we're not optimizing, then just err on the safe side. */
644 /* First determine which blocks can reach exit via normal paths. */
645 tos = worklist = XNEWVEC (basic_block, n_basic_blocks + 1);
648 bb->flags &= ~BB_REACHABLE;
650 /* Place the exit block on our worklist. */
651 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
652 *tos++ = EXIT_BLOCK_PTR;
654 /* Iterate: find everything reachable from what we've already seen. */
655 while (tos != worklist)
659 FOR_EACH_EDGE (e, ei, bb->preds)
660 if (!(e->flags & EDGE_ABNORMAL))
662 basic_block src = e->src;
664 if (!(src->flags & BB_REACHABLE))
666 src->flags |= BB_REACHABLE;
673 /* Now see if there's a reachable block with an exceptional incoming
676 if (bb->flags & BB_REACHABLE)
677 FOR_EACH_EDGE (e, ei, bb->preds)
678 if (e->flags & EDGE_ABNORMAL)
681 /* No exceptional block reached exit unexceptionally. */
686 /* Global variables used by reload and its subroutines. */
688 /* The current basic block while in calculate_elim_costs_all_insns. */
689 static basic_block elim_bb;
691 /* Set during calculate_needs if an insn needs register elimination. */
692 static int something_needs_elimination;
693 /* Set during calculate_needs if an insn needs an operand changed. */
694 static int something_needs_operands_changed;
695 /* Set by alter_regs if we spilled a register to the stack. */
696 static bool something_was_spilled;
698 /* Nonzero means we couldn't get enough spill regs. */
701 /* Temporary array of pseudo-register number. */
702 static int *temp_pseudo_reg_arr;
704 /* Main entry point for the reload pass.
706 FIRST is the first insn of the function being compiled.
708 GLOBAL nonzero means we were called from global_alloc
709 and should attempt to reallocate any pseudoregs that we
710 displace from hard regs we will use for reloads.
711 If GLOBAL is zero, we do not have enough information to do that,
712 so any pseudo reg that is spilled must go to the stack.
714 Return value is nonzero if reload failed
715 and we must not do any more for this function. */
718 reload (rtx first, int global)
722 struct elim_table *ep;
725 /* Make sure even insns with volatile mem refs are recognizable. */
730 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
732 /* Make sure that the last insn in the chain
733 is not something that needs reloading. */
734 emit_note (NOTE_INSN_DELETED);
736 /* Enable find_equiv_reg to distinguish insns made by reload. */
737 reload_first_uid = get_max_uid ();
739 #ifdef SECONDARY_MEMORY_NEEDED
740 /* Initialize the secondary memory table. */
741 clear_secondary_mem ();
744 /* We don't have a stack slot for any spill reg yet. */
745 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
746 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
748 /* Initialize the save area information for caller-save, in case some
752 /* Compute which hard registers are now in use
753 as homes for pseudo registers.
754 This is done here rather than (eg) in global_alloc
755 because this point is reached even if not optimizing. */
756 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
759 /* A function that has a nonlocal label that can reach the exit
760 block via non-exceptional paths must save all call-saved
762 if (cfun->has_nonlocal_label
763 && has_nonexceptional_receiver ())
764 crtl->saves_all_registers = 1;
766 if (crtl->saves_all_registers)
767 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
768 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
769 df_set_regs_ever_live (i, true);
771 reg_old_renumber = XCNEWVEC (short, max_regno);
772 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
773 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
774 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
776 CLEAR_HARD_REG_SET (bad_spill_regs_global);
778 init_eliminable_invariants (first, true);
781 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
782 stack slots to the pseudos that lack hard regs or equivalents.
783 Do not touch virtual registers. */
785 temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
786 for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
787 temp_pseudo_reg_arr[n++] = i;
790 /* Ask IRA to order pseudo-registers for better stack slot
792 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width);
794 for (i = 0; i < n; i++)
795 alter_reg (temp_pseudo_reg_arr[i], -1, false);
797 /* If we have some registers we think can be eliminated, scan all insns to
798 see if there is an insn that sets one of these registers to something
799 other than itself plus a constant. If so, the register cannot be
800 eliminated. Doing this scan here eliminates an extra pass through the
801 main reload loop in the most common case where register elimination
803 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
805 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
807 maybe_fix_stack_asms ();
809 insns_need_reload = 0;
810 something_needs_elimination = 0;
812 /* Initialize to -1, which means take the first spill register. */
815 /* Spill any hard regs that we know we can't eliminate. */
816 CLEAR_HARD_REG_SET (used_spill_regs);
817 /* There can be multiple ways to eliminate a register;
818 they should be listed adjacently.
819 Elimination for any register fails only if all possible ways fail. */
820 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
823 int can_eliminate = 0;
826 can_eliminate |= ep->can_eliminate;
829 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
831 spill_hard_reg (from, 1);
834 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
835 if (frame_pointer_needed)
836 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
838 finish_spills (global);
840 /* From now on, we may need to generate moves differently. We may also
841 allow modifications of insns which cause them to not be recognized.
842 Any such modifications will be cleaned up during reload itself. */
843 reload_in_progress = 1;
845 /* This loop scans the entire function each go-round
846 and repeats until one repetition spills no additional hard regs. */
849 int something_changed;
851 HOST_WIDE_INT starting_frame_size;
853 starting_frame_size = get_frame_size ();
854 something_was_spilled = false;
856 set_initial_elim_offsets ();
857 set_initial_label_offsets ();
859 /* For each pseudo register that has an equivalent location defined,
860 try to eliminate any eliminable registers (such as the frame pointer)
861 assuming initial offsets for the replacement register, which
864 If the resulting location is directly addressable, substitute
865 the MEM we just got directly for the old REG.
867 If it is not addressable but is a constant or the sum of a hard reg
868 and constant, it is probably not addressable because the constant is
869 out of range, in that case record the address; we will generate
870 hairy code to compute the address in a register each time it is
871 needed. Similarly if it is a hard register, but one that is not
872 valid as an address register.
874 If the location is not addressable, but does not have one of the
875 above forms, assign a stack slot. We have to do this to avoid the
876 potential of producing lots of reloads if, e.g., a location involves
877 a pseudo that didn't get a hard register and has an equivalent memory
878 location that also involves a pseudo that didn't get a hard register.
880 Perhaps at some point we will improve reload_when_needed handling
881 so this problem goes away. But that's very hairy. */
883 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
884 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
886 rtx x = eliminate_regs (reg_equiv_memory_loc[i], VOIDmode,
889 if (strict_memory_address_addr_space_p
890 (GET_MODE (regno_reg_rtx[i]), XEXP (x, 0),
892 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
893 else if (CONSTANT_P (XEXP (x, 0))
894 || (REG_P (XEXP (x, 0))
895 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
896 || (GET_CODE (XEXP (x, 0)) == PLUS
897 && REG_P (XEXP (XEXP (x, 0), 0))
898 && (REGNO (XEXP (XEXP (x, 0), 0))
899 < FIRST_PSEUDO_REGISTER)
900 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
901 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
904 /* Make a new stack slot. Then indicate that something
905 changed so we go back and recompute offsets for
906 eliminable registers because the allocation of memory
907 below might change some offset. reg_equiv_{mem,address}
908 will be set up for this pseudo on the next pass around
910 reg_equiv_memory_loc[i] = 0;
911 reg_equiv_init[i] = 0;
912 alter_reg (i, -1, true);
916 if (caller_save_needed)
919 /* If we allocated another stack slot, redo elimination bookkeeping. */
920 if (something_was_spilled || starting_frame_size != get_frame_size ())
922 if (starting_frame_size && crtl->stack_alignment_needed)
924 /* If we have a stack frame, we must align it now. The
925 stack size may be a part of the offset computation for
926 register elimination. So if this changes the stack size,
927 then repeat the elimination bookkeeping. We don't
928 realign when there is no stack, as that will cause a
929 stack frame when none is needed should
930 STARTING_FRAME_OFFSET not be already aligned to
932 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
933 if (starting_frame_size != get_frame_size ())
937 if (caller_save_needed)
939 save_call_clobbered_regs ();
940 /* That might have allocated new insn_chain structures. */
941 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
944 calculate_needs_all_insns (global);
946 if (! ira_conflicts_p)
947 /* Don't do it for IRA. We need this info because we don't
948 change live_throughout and dead_or_set for chains when IRA
950 CLEAR_REG_SET (&spilled_pseudos);
954 something_changed = 0;
956 /* If we allocated any new memory locations, make another pass
957 since it might have changed elimination offsets. */
958 if (something_was_spilled || starting_frame_size != get_frame_size ())
959 something_changed = 1;
961 /* Even if the frame size remained the same, we might still have
962 changed elimination offsets, e.g. if find_reloads called
963 force_const_mem requiring the back end to allocate a constant
964 pool base register that needs to be saved on the stack. */
965 else if (!verify_initial_elim_offsets ())
966 something_changed = 1;
969 HARD_REG_SET to_spill;
970 CLEAR_HARD_REG_SET (to_spill);
971 update_eliminables (&to_spill);
972 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
974 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
975 if (TEST_HARD_REG_BIT (to_spill, i))
977 spill_hard_reg (i, 1);
980 /* Regardless of the state of spills, if we previously had
981 a register that we thought we could eliminate, but now can
982 not eliminate, we must run another pass.
984 Consider pseudos which have an entry in reg_equiv_* which
985 reference an eliminable register. We must make another pass
986 to update reg_equiv_* so that we do not substitute in the
987 old value from when we thought the elimination could be
989 something_changed = 1;
993 select_reload_regs ();
997 if (insns_need_reload != 0 || did_spill)
998 something_changed |= finish_spills (global);
1000 if (! something_changed)
1003 if (caller_save_needed)
1004 delete_caller_save_insns ();
1006 obstack_free (&reload_obstack, reload_firstobj);
1009 /* If global-alloc was run, notify it of any register eliminations we have
1012 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1013 if (ep->can_eliminate)
1014 mark_elimination (ep->from, ep->to);
1016 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1017 If that insn didn't set the register (i.e., it copied the register to
1018 memory), just delete that insn instead of the equivalencing insn plus
1019 anything now dead. If we call delete_dead_insn on that insn, we may
1020 delete the insn that actually sets the register if the register dies
1021 there and that is incorrect. */
1023 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1025 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1028 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1030 rtx equiv_insn = XEXP (list, 0);
1032 /* If we already deleted the insn or if it may trap, we can't
1033 delete it. The latter case shouldn't happen, but can
1034 if an insn has a variable address, gets a REG_EH_REGION
1035 note added to it, and then gets converted into a load
1036 from a constant address. */
1037 if (NOTE_P (equiv_insn)
1038 || can_throw_internal (equiv_insn))
1040 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1041 delete_dead_insn (equiv_insn);
1043 SET_INSN_DELETED (equiv_insn);
1048 /* Use the reload registers where necessary
1049 by generating move instructions to move the must-be-register
1050 values into or out of the reload registers. */
1052 if (insns_need_reload != 0 || something_needs_elimination
1053 || something_needs_operands_changed)
1055 HOST_WIDE_INT old_frame_size = get_frame_size ();
1057 reload_as_needed (global);
1059 gcc_assert (old_frame_size == get_frame_size ());
1061 gcc_assert (verify_initial_elim_offsets ());
1064 /* If we were able to eliminate the frame pointer, show that it is no
1065 longer live at the start of any basic block. If it ls live by
1066 virtue of being in a pseudo, that pseudo will be marked live
1067 and hence the frame pointer will be known to be live via that
1070 if (! frame_pointer_needed)
1072 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1074 /* Come here (with failure set nonzero) if we can't get enough spill
1078 CLEAR_REG_SET (&changed_allocation_pseudos);
1079 CLEAR_REG_SET (&spilled_pseudos);
1080 reload_in_progress = 0;
1082 /* Now eliminate all pseudo regs by modifying them into
1083 their equivalent memory references.
1084 The REG-rtx's for the pseudos are modified in place,
1085 so all insns that used to refer to them now refer to memory.
1087 For a reg that has a reg_equiv_address, all those insns
1088 were changed by reloading so that no insns refer to it any longer;
1089 but the DECL_RTL of a variable decl may refer to it,
1090 and if so this causes the debugging info to mention the variable. */
1092 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1096 if (reg_equiv_mem[i])
1097 addr = XEXP (reg_equiv_mem[i], 0);
1099 if (reg_equiv_address[i])
1100 addr = reg_equiv_address[i];
1104 if (reg_renumber[i] < 0)
1106 rtx reg = regno_reg_rtx[i];
1108 REG_USERVAR_P (reg) = 0;
1109 PUT_CODE (reg, MEM);
1110 XEXP (reg, 0) = addr;
1111 if (reg_equiv_memory_loc[i])
1112 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1115 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1116 MEM_ATTRS (reg) = 0;
1118 MEM_NOTRAP_P (reg) = 1;
1120 else if (reg_equiv_mem[i])
1121 XEXP (reg_equiv_mem[i], 0) = addr;
1124 /* We don't want complex addressing modes in debug insns
1125 if simpler ones will do, so delegitimize equivalences
1127 if (MAY_HAVE_DEBUG_INSNS && reg_renumber[i] < 0)
1129 rtx reg = regno_reg_rtx[i];
1133 if (reg_equiv_constant[i])
1134 equiv = reg_equiv_constant[i];
1135 else if (reg_equiv_invariant[i])
1136 equiv = reg_equiv_invariant[i];
1137 else if (reg && MEM_P (reg))
1138 equiv = targetm.delegitimize_address (reg);
1139 else if (reg && REG_P (reg) && (int)REGNO (reg) != i)
1145 for (use = DF_REG_USE_CHAIN (i); use; use = next)
1147 insn = DF_REF_INSN (use);
1149 /* Make sure the next ref is for a different instruction,
1150 so that we're not affected by the rescan. */
1151 next = DF_REF_NEXT_REG (use);
1152 while (next && DF_REF_INSN (next) == insn)
1153 next = DF_REF_NEXT_REG (next);
1155 if (DEBUG_INSN_P (insn))
1159 INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
1160 df_insn_rescan_debug_internal (insn);
1163 INSN_VAR_LOCATION_LOC (insn)
1164 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn),
1171 /* We must set reload_completed now since the cleanup_subreg_operands call
1172 below will re-recognize each insn and reload may have generated insns
1173 which are only valid during and after reload. */
1174 reload_completed = 1;
1176 /* Make a pass over all the insns and delete all USEs which we inserted
1177 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1178 notes. Delete all CLOBBER insns, except those that refer to the return
1179 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1180 from misarranging variable-array code, and simplify (subreg (reg))
1181 operands. Strip and regenerate REG_INC notes that may have been moved
1184 for (insn = first; insn; insn = NEXT_INSN (insn))
1190 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1191 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1193 if ((GET_CODE (PATTERN (insn)) == USE
1194 /* We mark with QImode USEs introduced by reload itself. */
1195 && (GET_MODE (insn) == QImode
1196 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1197 || (GET_CODE (PATTERN (insn)) == CLOBBER
1198 && (!MEM_P (XEXP (PATTERN (insn), 0))
1199 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1200 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1201 && XEXP (XEXP (PATTERN (insn), 0), 0)
1202 != stack_pointer_rtx))
1203 && (!REG_P (XEXP (PATTERN (insn), 0))
1204 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1210 /* Some CLOBBERs may survive until here and still reference unassigned
1211 pseudos with const equivalent, which may in turn cause ICE in later
1212 passes if the reference remains in place. */
1213 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1214 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1215 VOIDmode, PATTERN (insn));
1217 /* Discard obvious no-ops, even without -O. This optimization
1218 is fast and doesn't interfere with debugging. */
1219 if (NONJUMP_INSN_P (insn)
1220 && GET_CODE (PATTERN (insn)) == SET
1221 && REG_P (SET_SRC (PATTERN (insn)))
1222 && REG_P (SET_DEST (PATTERN (insn)))
1223 && (REGNO (SET_SRC (PATTERN (insn)))
1224 == REGNO (SET_DEST (PATTERN (insn)))))
1230 pnote = ®_NOTES (insn);
1233 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1234 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1235 || REG_NOTE_KIND (*pnote) == REG_INC)
1236 *pnote = XEXP (*pnote, 1);
1238 pnote = &XEXP (*pnote, 1);
1242 add_auto_inc_notes (insn, PATTERN (insn));
1245 /* Simplify (subreg (reg)) if it appears as an operand. */
1246 cleanup_subreg_operands (insn);
1248 /* Clean up invalid ASMs so that they don't confuse later passes.
1250 if (asm_noperands (PATTERN (insn)) >= 0)
1252 extract_insn (insn);
1253 if (!constrain_operands (1))
1255 error_for_asm (insn,
1256 "%<asm%> operand has impossible constraints");
1263 /* If we are doing generic stack checking, give a warning if this
1264 function's frame size is larger than we expect. */
1265 if (flag_stack_check == GENERIC_STACK_CHECK)
1267 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1268 static int verbose_warned = 0;
1270 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1271 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1272 size += UNITS_PER_WORD;
1274 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1276 warning (0, "frame size too large for reliable stack checking");
1277 if (! verbose_warned)
1279 warning (0, "try reducing the number of local variables");
1285 free (temp_pseudo_reg_arr);
1287 /* Indicate that we no longer have known memory locations or constants. */
1290 free (reg_max_ref_width);
1291 free (reg_old_renumber);
1292 free (pseudo_previous_regs);
1293 free (pseudo_forbidden_regs);
1295 CLEAR_HARD_REG_SET (used_spill_regs);
1296 for (i = 0; i < n_spills; i++)
1297 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1299 /* Free all the insn_chain structures at once. */
1300 obstack_free (&reload_obstack, reload_startobj);
1301 unused_insn_chains = 0;
1302 fixup_abnormal_edges ();
1304 /* Replacing pseudos with their memory equivalents might have
1305 created shared rtx. Subsequent passes would get confused
1306 by this, so unshare everything here. */
1307 unshare_all_rtl_again (first);
1309 #ifdef STACK_BOUNDARY
1310 /* init_emit has set the alignment of the hard frame pointer
1311 to STACK_BOUNDARY. It is very likely no longer valid if
1312 the hard frame pointer was used for register allocation. */
1313 if (!frame_pointer_needed)
1314 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1317 VEC_free (rtx_p, heap, substitute_stack);
1322 /* Yet another special case. Unfortunately, reg-stack forces people to
1323 write incorrect clobbers in asm statements. These clobbers must not
1324 cause the register to appear in bad_spill_regs, otherwise we'll call
1325 fatal_insn later. We clear the corresponding regnos in the live
1326 register sets to avoid this.
1327 The whole thing is rather sick, I'm afraid. */
1330 maybe_fix_stack_asms (void)
1333 const char *constraints[MAX_RECOG_OPERANDS];
1334 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1335 struct insn_chain *chain;
1337 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1340 HARD_REG_SET clobbered, allowed;
1343 if (! INSN_P (chain->insn)
1344 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1346 pat = PATTERN (chain->insn);
1347 if (GET_CODE (pat) != PARALLEL)
1350 CLEAR_HARD_REG_SET (clobbered);
1351 CLEAR_HARD_REG_SET (allowed);
1353 /* First, make a mask of all stack regs that are clobbered. */
1354 for (i = 0; i < XVECLEN (pat, 0); i++)
1356 rtx t = XVECEXP (pat, 0, i);
1357 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1358 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1361 /* Get the operand values and constraints out of the insn. */
1362 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1363 constraints, operand_mode, NULL);
1365 /* For every operand, see what registers are allowed. */
1366 for (i = 0; i < noperands; i++)
1368 const char *p = constraints[i];
1369 /* For every alternative, we compute the class of registers allowed
1370 for reloading in CLS, and merge its contents into the reg set
1372 int cls = (int) NO_REGS;
1378 if (c == '\0' || c == ',' || c == '#')
1380 /* End of one alternative - mark the regs in the current
1381 class, and reset the class. */
1382 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1388 } while (c != '\0' && c != ',');
1396 case '=': case '+': case '*': case '%': case '?': case '!':
1397 case '0': case '1': case '2': case '3': case '4': case '<':
1398 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1399 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1400 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1401 case TARGET_MEM_CONSTRAINT:
1405 cls = (int) reg_class_subunion[cls]
1406 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1411 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1415 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1416 cls = (int) reg_class_subunion[cls]
1417 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1419 cls = (int) reg_class_subunion[cls]
1420 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1422 p += CONSTRAINT_LEN (c, p);
1425 /* Those of the registers which are clobbered, but allowed by the
1426 constraints, must be usable as reload registers. So clear them
1427 out of the life information. */
1428 AND_HARD_REG_SET (allowed, clobbered);
1429 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1430 if (TEST_HARD_REG_BIT (allowed, i))
1432 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1433 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1440 /* Copy the global variables n_reloads and rld into the corresponding elts
1443 copy_reloads (struct insn_chain *chain)
1445 chain->n_reloads = n_reloads;
1446 chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1447 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1448 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1451 /* Walk the chain of insns, and determine for each whether it needs reloads
1452 and/or eliminations. Build the corresponding insns_need_reload list, and
1453 set something_needs_elimination as appropriate. */
1455 calculate_needs_all_insns (int global)
1457 struct insn_chain **pprev_reload = &insns_need_reload;
1458 struct insn_chain *chain, *next = 0;
1460 something_needs_elimination = 0;
1462 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1463 for (chain = reload_insn_chain; chain != 0; chain = next)
1465 rtx insn = chain->insn;
1469 /* Clear out the shortcuts. */
1470 chain->n_reloads = 0;
1471 chain->need_elim = 0;
1472 chain->need_reload = 0;
1473 chain->need_operand_change = 0;
1475 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1476 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1477 what effects this has on the known offsets at labels. */
1479 if (LABEL_P (insn) || JUMP_P (insn)
1480 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1481 set_label_offsets (insn, insn, 0);
1485 rtx old_body = PATTERN (insn);
1486 int old_code = INSN_CODE (insn);
1487 rtx old_notes = REG_NOTES (insn);
1488 int did_elimination = 0;
1489 int operands_changed = 0;
1490 rtx set = single_set (insn);
1492 /* Skip insns that only set an equivalence. */
1493 if (set && REG_P (SET_DEST (set))
1494 && reg_renumber[REGNO (SET_DEST (set))] < 0
1495 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1496 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1497 && reg_equiv_init[REGNO (SET_DEST (set))])
1500 /* If needed, eliminate any eliminable registers. */
1501 if (num_eliminable || num_eliminable_invariants)
1502 did_elimination = eliminate_regs_in_insn (insn, 0);
1504 /* Analyze the instruction. */
1505 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1506 global, spill_reg_order);
1508 /* If a no-op set needs more than one reload, this is likely
1509 to be something that needs input address reloads. We
1510 can't get rid of this cleanly later, and it is of no use
1511 anyway, so discard it now.
1512 We only do this when expensive_optimizations is enabled,
1513 since this complements reload inheritance / output
1514 reload deletion, and it can make debugging harder. */
1515 if (flag_expensive_optimizations && n_reloads > 1)
1517 rtx set = single_set (insn);
1520 ((SET_SRC (set) == SET_DEST (set)
1521 && REG_P (SET_SRC (set))
1522 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1523 || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1524 && reg_renumber[REGNO (SET_SRC (set))] < 0
1525 && reg_renumber[REGNO (SET_DEST (set))] < 0
1526 && reg_equiv_memory_loc[REGNO (SET_SRC (set))] != NULL
1527 && reg_equiv_memory_loc[REGNO (SET_DEST (set))] != NULL
1528 && rtx_equal_p (reg_equiv_memory_loc
1529 [REGNO (SET_SRC (set))],
1530 reg_equiv_memory_loc
1531 [REGNO (SET_DEST (set))]))))
1533 if (ira_conflicts_p)
1534 /* Inform IRA about the insn deletion. */
1535 ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1536 REGNO (SET_SRC (set)));
1538 /* Delete it from the reload chain. */
1540 chain->prev->next = next;
1542 reload_insn_chain = next;
1544 next->prev = chain->prev;
1545 chain->next = unused_insn_chains;
1546 unused_insn_chains = chain;
1551 update_eliminable_offsets ();
1553 /* Remember for later shortcuts which insns had any reloads or
1554 register eliminations. */
1555 chain->need_elim = did_elimination;
1556 chain->need_reload = n_reloads > 0;
1557 chain->need_operand_change = operands_changed;
1559 /* Discard any register replacements done. */
1560 if (did_elimination)
1562 obstack_free (&reload_obstack, reload_insn_firstobj);
1563 PATTERN (insn) = old_body;
1564 INSN_CODE (insn) = old_code;
1565 REG_NOTES (insn) = old_notes;
1566 something_needs_elimination = 1;
1569 something_needs_operands_changed |= operands_changed;
1573 copy_reloads (chain);
1574 *pprev_reload = chain;
1575 pprev_reload = &chain->next_need_reload;
1582 /* This function is called from the register allocator to set up estimates
1583 for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1584 an invariant. The structure is similar to calculate_needs_all_insns. */
1587 calculate_elim_costs_all_insns (void)
1589 int *reg_equiv_init_cost;
1593 reg_equiv_init_cost = XCNEWVEC (int, max_regno);
1595 init_eliminable_invariants (get_insns (), false);
1597 set_initial_elim_offsets ();
1598 set_initial_label_offsets ();
1605 FOR_BB_INSNS (bb, insn)
1607 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1608 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1609 what effects this has on the known offsets at labels. */
1611 if (LABEL_P (insn) || JUMP_P (insn)
1612 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1613 set_label_offsets (insn, insn, 0);
1617 rtx set = single_set (insn);
1619 /* Skip insns that only set an equivalence. */
1620 if (set && REG_P (SET_DEST (set))
1621 && reg_renumber[REGNO (SET_DEST (set))] < 0
1622 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1623 || (reg_equiv_invariant[REGNO (SET_DEST (set))])))
1625 unsigned regno = REGNO (SET_DEST (set));
1626 rtx init = reg_equiv_init[regno];
1629 rtx t = eliminate_regs_1 (SET_SRC (set), VOIDmode, insn,
1631 int cost = rtx_cost (t, SET,
1632 optimize_bb_for_speed_p (bb));
1633 int freq = REG_FREQ_FROM_BB (bb);
1635 reg_equiv_init_cost[regno] = cost * freq;
1639 /* If needed, eliminate any eliminable registers. */
1640 if (num_eliminable || num_eliminable_invariants)
1641 elimination_costs_in_insn (insn);
1644 update_eliminable_offsets ();
1648 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1650 if (reg_equiv_invariant[i])
1652 if (reg_equiv_init[i])
1654 int cost = reg_equiv_init_cost[i];
1657 "Reg %d has equivalence, initial gains %d\n", i, cost);
1659 ira_adjust_equiv_reg_cost (i, cost);
1665 "Reg %d had equivalence, but can't be eliminated\n",
1667 ira_adjust_equiv_reg_cost (i, 0);
1673 free (reg_equiv_init_cost);
1676 /* Comparison function for qsort to decide which of two reloads
1677 should be handled first. *P1 and *P2 are the reload numbers. */
1680 reload_reg_class_lower (const void *r1p, const void *r2p)
1682 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1685 /* Consider required reloads before optional ones. */
1686 t = rld[r1].optional - rld[r2].optional;
1690 /* Count all solitary classes before non-solitary ones. */
1691 t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1692 - (reg_class_size[(int) rld[r1].rclass] == 1));
1696 /* Aside from solitaires, consider all multi-reg groups first. */
1697 t = rld[r2].nregs - rld[r1].nregs;
1701 /* Consider reloads in order of increasing reg-class number. */
1702 t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1706 /* If reloads are equally urgent, sort by reload number,
1707 so that the results of qsort leave nothing to chance. */
1711 /* The cost of spilling each hard reg. */
1712 static int spill_cost[FIRST_PSEUDO_REGISTER];
1714 /* When spilling multiple hard registers, we use SPILL_COST for the first
1715 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1716 only the first hard reg for a multi-reg pseudo. */
1717 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1719 /* Map of hard regno to pseudo regno currently occupying the hard
1721 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1723 /* Update the spill cost arrays, considering that pseudo REG is live. */
1726 count_pseudo (int reg)
1728 int freq = REG_FREQ (reg);
1729 int r = reg_renumber[reg];
1732 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1733 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1734 /* Ignore spilled pseudo-registers which can be here only if IRA
1736 || (ira_conflicts_p && r < 0))
1739 SET_REGNO_REG_SET (&pseudos_counted, reg);
1741 gcc_assert (r >= 0);
1743 spill_add_cost[r] += freq;
1744 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1747 hard_regno_to_pseudo_regno[r + nregs] = reg;
1748 spill_cost[r + nregs] += freq;
1752 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1753 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1756 order_regs_for_reload (struct insn_chain *chain)
1759 HARD_REG_SET used_by_pseudos;
1760 HARD_REG_SET used_by_pseudos2;
1761 reg_set_iterator rsi;
1763 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1765 memset (spill_cost, 0, sizeof spill_cost);
1766 memset (spill_add_cost, 0, sizeof spill_add_cost);
1767 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1768 hard_regno_to_pseudo_regno[i] = -1;
1770 /* Count number of uses of each hard reg by pseudo regs allocated to it
1771 and then order them by decreasing use. First exclude hard registers
1772 that are live in or across this insn. */
1774 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1775 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1776 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1777 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1779 /* Now find out which pseudos are allocated to it, and update
1781 CLEAR_REG_SET (&pseudos_counted);
1783 EXECUTE_IF_SET_IN_REG_SET
1784 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1788 EXECUTE_IF_SET_IN_REG_SET
1789 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1793 CLEAR_REG_SET (&pseudos_counted);
1796 /* Vector of reload-numbers showing the order in which the reloads should
1798 static short reload_order[MAX_RELOADS];
1800 /* This is used to keep track of the spill regs used in one insn. */
1801 static HARD_REG_SET used_spill_regs_local;
1803 /* We decided to spill hard register SPILLED, which has a size of
1804 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1805 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1806 update SPILL_COST/SPILL_ADD_COST. */
1809 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1811 int freq = REG_FREQ (reg);
1812 int r = reg_renumber[reg];
1813 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1815 /* Ignore spilled pseudo-registers which can be here only if IRA is
1817 if ((ira_conflicts_p && r < 0)
1818 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1819 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1822 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1824 spill_add_cost[r] -= freq;
1827 hard_regno_to_pseudo_regno[r + nregs] = -1;
1828 spill_cost[r + nregs] -= freq;
1832 /* Find reload register to use for reload number ORDER. */
1835 find_reg (struct insn_chain *chain, int order)
1837 int rnum = reload_order[order];
1838 struct reload *rl = rld + rnum;
1839 int best_cost = INT_MAX;
1841 unsigned int i, j, n;
1843 HARD_REG_SET not_usable;
1844 HARD_REG_SET used_by_other_reload;
1845 reg_set_iterator rsi;
1846 static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1847 static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1849 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1850 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1851 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
1853 CLEAR_HARD_REG_SET (used_by_other_reload);
1854 for (k = 0; k < order; k++)
1856 int other = reload_order[k];
1858 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1859 for (j = 0; j < rld[other].nregs; j++)
1860 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1863 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1865 #ifdef REG_ALLOC_ORDER
1866 unsigned int regno = reg_alloc_order[i];
1868 unsigned int regno = i;
1871 if (! TEST_HARD_REG_BIT (not_usable, regno)
1872 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1873 && HARD_REGNO_MODE_OK (regno, rl->mode))
1875 int this_cost = spill_cost[regno];
1877 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1879 for (j = 1; j < this_nregs; j++)
1881 this_cost += spill_add_cost[regno + j];
1882 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1883 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1889 if (ira_conflicts_p)
1891 /* Ask IRA to find a better pseudo-register for
1893 for (n = j = 0; j < this_nregs; j++)
1895 int r = hard_regno_to_pseudo_regno[regno + j];
1899 if (n == 0 || regno_pseudo_regs[n - 1] != r)
1900 regno_pseudo_regs[n++] = r;
1902 regno_pseudo_regs[n++] = -1;
1904 || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1905 best_regno_pseudo_regs,
1912 best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1913 if (regno_pseudo_regs[j] < 0)
1920 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1922 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1924 if (this_cost < best_cost
1925 /* Among registers with equal cost, prefer caller-saved ones, or
1926 use REG_ALLOC_ORDER if it is defined. */
1927 || (this_cost == best_cost
1928 #ifdef REG_ALLOC_ORDER
1929 && (inv_reg_alloc_order[regno]
1930 < inv_reg_alloc_order[best_reg])
1932 && call_used_regs[regno]
1933 && ! call_used_regs[best_reg]
1938 best_cost = this_cost;
1946 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1948 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1949 rl->regno = best_reg;
1951 EXECUTE_IF_SET_IN_REG_SET
1952 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1954 count_spilled_pseudo (best_reg, rl->nregs, j);
1957 EXECUTE_IF_SET_IN_REG_SET
1958 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1960 count_spilled_pseudo (best_reg, rl->nregs, j);
1963 for (i = 0; i < rl->nregs; i++)
1965 gcc_assert (spill_cost[best_reg + i] == 0);
1966 gcc_assert (spill_add_cost[best_reg + i] == 0);
1967 gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
1968 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1973 /* Find more reload regs to satisfy the remaining need of an insn, which
1975 Do it by ascending class number, since otherwise a reg
1976 might be spilled for a big class and might fail to count
1977 for a smaller class even though it belongs to that class. */
1980 find_reload_regs (struct insn_chain *chain)
1984 /* In order to be certain of getting the registers we need,
1985 we must sort the reloads into order of increasing register class.
1986 Then our grabbing of reload registers will parallel the process
1987 that provided the reload registers. */
1988 for (i = 0; i < chain->n_reloads; i++)
1990 /* Show whether this reload already has a hard reg. */
1991 if (chain->rld[i].reg_rtx)
1993 int regno = REGNO (chain->rld[i].reg_rtx);
1994 chain->rld[i].regno = regno;
1996 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1999 chain->rld[i].regno = -1;
2000 reload_order[i] = i;
2003 n_reloads = chain->n_reloads;
2004 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
2006 CLEAR_HARD_REG_SET (used_spill_regs_local);
2009 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
2011 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
2013 /* Compute the order of preference for hard registers to spill. */
2015 order_regs_for_reload (chain);
2017 for (i = 0; i < n_reloads; i++)
2019 int r = reload_order[i];
2021 /* Ignore reloads that got marked inoperative. */
2022 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
2023 && ! rld[r].optional
2024 && rld[r].regno == -1)
2025 if (! find_reg (chain, i))
2028 fprintf (dump_file, "reload failure for reload %d\n", r);
2029 spill_failure (chain->insn, rld[r].rclass);
2035 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
2036 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
2038 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2042 select_reload_regs (void)
2044 struct insn_chain *chain;
2046 /* Try to satisfy the needs for each insn. */
2047 for (chain = insns_need_reload; chain != 0;
2048 chain = chain->next_need_reload)
2049 find_reload_regs (chain);
2052 /* Delete all insns that were inserted by emit_caller_save_insns during
2055 delete_caller_save_insns (void)
2057 struct insn_chain *c = reload_insn_chain;
2061 while (c != 0 && c->is_caller_save_insn)
2063 struct insn_chain *next = c->next;
2066 if (c == reload_insn_chain)
2067 reload_insn_chain = next;
2071 next->prev = c->prev;
2073 c->prev->next = next;
2074 c->next = unused_insn_chains;
2075 unused_insn_chains = c;
2083 /* Handle the failure to find a register to spill.
2084 INSN should be one of the insns which needed this particular spill reg. */
2087 spill_failure (rtx insn, enum reg_class rclass)
2089 if (asm_noperands (PATTERN (insn)) >= 0)
2090 error_for_asm (insn, "can't find a register in class %qs while "
2091 "reloading %<asm%>",
2092 reg_class_names[rclass]);
2095 error ("unable to find a register to spill in class %qs",
2096 reg_class_names[rclass]);
2100 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2101 debug_reload_to_stream (dump_file);
2103 fatal_insn ("this is the insn:", insn);
2107 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2108 data that is dead in INSN. */
2111 delete_dead_insn (rtx insn)
2113 rtx prev = prev_real_insn (insn);
2116 /* If the previous insn sets a register that dies in our insn, delete it
2118 if (prev && GET_CODE (PATTERN (prev)) == SET
2119 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2120 && reg_mentioned_p (prev_dest, PATTERN (insn))
2121 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2122 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2123 delete_dead_insn (prev);
2125 SET_INSN_DELETED (insn);
2128 /* Modify the home of pseudo-reg I.
2129 The new home is present in reg_renumber[I].
2131 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2132 or it may be -1, meaning there is none or it is not relevant.
2133 This is used so that all pseudos spilled from a given hard reg
2134 can share one stack slot. */
2137 alter_reg (int i, int from_reg, bool dont_share_p)
2139 /* When outputting an inline function, this can happen
2140 for a reg that isn't actually used. */
2141 if (regno_reg_rtx[i] == 0)
2144 /* If the reg got changed to a MEM at rtl-generation time,
2146 if (!REG_P (regno_reg_rtx[i]))
2149 /* Modify the reg-rtx to contain the new hard reg
2150 number or else to contain its pseudo reg number. */
2151 SET_REGNO (regno_reg_rtx[i],
2152 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2154 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2155 allocate a stack slot for it. */
2157 if (reg_renumber[i] < 0
2158 && REG_N_REFS (i) > 0
2159 && reg_equiv_constant[i] == 0
2160 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
2161 && reg_equiv_memory_loc[i] == 0)
2164 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2165 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2166 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2167 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2168 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2171 something_was_spilled = true;
2173 if (ira_conflicts_p)
2175 /* Mark the spill for IRA. */
2176 SET_REGNO_REG_SET (&spilled_pseudos, i);
2178 x = ira_reuse_stack_slot (i, inherent_size, total_size);
2184 /* Each pseudo reg has an inherent size which comes from its own mode,
2185 and a total size which provides room for paradoxical subregs
2186 which refer to the pseudo reg in wider modes.
2188 We can use a slot already allocated if it provides both
2189 enough inherent space and enough total space.
2190 Otherwise, we allocate a new slot, making sure that it has no less
2191 inherent space, and no less total space, then the previous slot. */
2192 else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
2196 /* No known place to spill from => no slot to reuse. */
2197 x = assign_stack_local (mode, total_size,
2198 min_align > inherent_align
2199 || total_size > inherent_size ? -1 : 0);
2203 /* Cancel the big-endian correction done in assign_stack_local.
2204 Get the address of the beginning of the slot. This is so we
2205 can do a big-endian correction unconditionally below. */
2206 if (BYTES_BIG_ENDIAN)
2208 adjust = inherent_size - total_size;
2211 = adjust_address_nv (x, mode_for_size (total_size
2217 if (! dont_share_p && ira_conflicts_p)
2218 /* Inform IRA about allocation a new stack slot. */
2219 ira_mark_new_stack_slot (stack_slot, i, total_size);
2222 /* Reuse a stack slot if possible. */
2223 else if (spill_stack_slot[from_reg] != 0
2224 && spill_stack_slot_width[from_reg] >= total_size
2225 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2227 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2228 x = spill_stack_slot[from_reg];
2230 /* Allocate a bigger slot. */
2233 /* Compute maximum size needed, both for inherent size
2234 and for total size. */
2237 if (spill_stack_slot[from_reg])
2239 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2241 mode = GET_MODE (spill_stack_slot[from_reg]);
2242 if (spill_stack_slot_width[from_reg] > total_size)
2243 total_size = spill_stack_slot_width[from_reg];
2244 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2245 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2248 /* Make a slot with that size. */
2249 x = assign_stack_local (mode, total_size,
2250 min_align > inherent_align
2251 || total_size > inherent_size ? -1 : 0);
2254 /* Cancel the big-endian correction done in assign_stack_local.
2255 Get the address of the beginning of the slot. This is so we
2256 can do a big-endian correction unconditionally below. */
2257 if (BYTES_BIG_ENDIAN)
2259 adjust = GET_MODE_SIZE (mode) - total_size;
2262 = adjust_address_nv (x, mode_for_size (total_size
2268 spill_stack_slot[from_reg] = stack_slot;
2269 spill_stack_slot_width[from_reg] = total_size;
2272 /* On a big endian machine, the "address" of the slot
2273 is the address of the low part that fits its inherent mode. */
2274 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2275 adjust += (total_size - inherent_size);
2277 /* If we have any adjustment to make, or if the stack slot is the
2278 wrong mode, make a new stack slot. */
2279 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2281 /* Set all of the memory attributes as appropriate for a spill. */
2282 set_mem_attrs_for_spill (x);
2284 /* Save the stack slot for later. */
2285 reg_equiv_memory_loc[i] = x;
2289 /* Mark the slots in regs_ever_live for the hard regs used by
2290 pseudo-reg number REGNO, accessed in MODE. */
2293 mark_home_live_1 (int regno, enum machine_mode mode)
2297 i = reg_renumber[regno];
2300 lim = end_hard_regno (mode, i);
2302 df_set_regs_ever_live(i++, true);
2305 /* Mark the slots in regs_ever_live for the hard regs
2306 used by pseudo-reg number REGNO. */
2309 mark_home_live (int regno)
2311 if (reg_renumber[regno] >= 0)
2312 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2315 /* This function handles the tracking of elimination offsets around branches.
2317 X is a piece of RTL being scanned.
2319 INSN is the insn that it came from, if any.
2321 INITIAL_P is nonzero if we are to set the offset to be the initial
2322 offset and zero if we are setting the offset of the label to be the
2326 set_label_offsets (rtx x, rtx insn, int initial_p)
2328 enum rtx_code code = GET_CODE (x);
2331 struct elim_table *p;
2336 if (LABEL_REF_NONLOCAL_P (x))
2341 /* ... fall through ... */
2344 /* If we know nothing about this label, set the desired offsets. Note
2345 that this sets the offset at a label to be the offset before a label
2346 if we don't know anything about the label. This is not correct for
2347 the label after a BARRIER, but is the best guess we can make. If
2348 we guessed wrong, we will suppress an elimination that might have
2349 been possible had we been able to guess correctly. */
2351 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2353 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2354 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2355 = (initial_p ? reg_eliminate[i].initial_offset
2356 : reg_eliminate[i].offset);
2357 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2360 /* Otherwise, if this is the definition of a label and it is
2361 preceded by a BARRIER, set our offsets to the known offset of
2365 && (tem = prev_nonnote_insn (insn)) != 0
2367 set_offsets_for_label (insn);
2369 /* If neither of the above cases is true, compare each offset
2370 with those previously recorded and suppress any eliminations
2371 where the offsets disagree. */
2373 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2374 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2375 != (initial_p ? reg_eliminate[i].initial_offset
2376 : reg_eliminate[i].offset))
2377 reg_eliminate[i].can_eliminate = 0;
2382 set_label_offsets (PATTERN (insn), insn, initial_p);
2384 /* ... fall through ... */
2388 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2389 to indirectly and hence must have all eliminations at their
2391 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2392 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2393 set_label_offsets (XEXP (tem, 0), insn, 1);
2399 /* Each of the labels in the parallel or address vector must be
2400 at their initial offsets. We want the first field for PARALLEL
2401 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2403 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2404 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2409 /* We only care about setting PC. If the source is not RETURN,
2410 IF_THEN_ELSE, or a label, disable any eliminations not at
2411 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2412 isn't one of those possibilities. For branches to a label,
2413 call ourselves recursively.
2415 Note that this can disable elimination unnecessarily when we have
2416 a non-local goto since it will look like a non-constant jump to
2417 someplace in the current function. This isn't a significant
2418 problem since such jumps will normally be when all elimination
2419 pairs are back to their initial offsets. */
2421 if (SET_DEST (x) != pc_rtx)
2424 switch (GET_CODE (SET_SRC (x)))
2431 set_label_offsets (SET_SRC (x), insn, initial_p);
2435 tem = XEXP (SET_SRC (x), 1);
2436 if (GET_CODE (tem) == LABEL_REF)
2437 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2438 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2441 tem = XEXP (SET_SRC (x), 2);
2442 if (GET_CODE (tem) == LABEL_REF)
2443 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2444 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2452 /* If we reach here, all eliminations must be at their initial
2453 offset because we are doing a jump to a variable address. */
2454 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2455 if (p->offset != p->initial_offset)
2456 p->can_eliminate = 0;
2464 /* Called through for_each_rtx, this function examines every reg that occurs
2465 in PX and adjusts the costs for its elimination which are gathered by IRA.
2466 DATA is the insn in which PX occurs. We do not recurse into MEM
2470 note_reg_elim_costly (rtx *px, void *data)
2472 rtx insn = (rtx)data;
2479 && REGNO (x) >= FIRST_PSEUDO_REGISTER
2480 && reg_equiv_init[REGNO (x)]
2481 && reg_equiv_invariant[REGNO (x)])
2483 rtx t = reg_equiv_invariant[REGNO (x)];
2484 rtx new_rtx = eliminate_regs_1 (t, Pmode, insn, true, true);
2485 int cost = rtx_cost (new_rtx, SET, optimize_bb_for_speed_p (elim_bb));
2486 int freq = REG_FREQ_FROM_BB (elim_bb);
2489 ira_adjust_equiv_reg_cost (REGNO (x), -cost * freq);
2494 /* Scan X and replace any eliminable registers (such as fp) with a
2495 replacement (such as sp), plus an offset.
2497 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2498 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2499 MEM, we are allowed to replace a sum of a register and the constant zero
2500 with the register, which we cannot do outside a MEM. In addition, we need
2501 to record the fact that a register is referenced outside a MEM.
2503 If INSN is an insn, it is the insn containing X. If we replace a REG
2504 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2505 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2506 the REG is being modified.
2508 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2509 That's used when we eliminate in expressions stored in notes.
2510 This means, do not set ref_outside_mem even if the reference
2513 If FOR_COSTS is true, we are being called before reload in order to
2514 estimate the costs of keeping registers with an equivalence unallocated.
2516 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2517 replacements done assuming all offsets are at their initial values. If
2518 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2519 encounter, return the actual location so that find_reloads will do
2520 the proper thing. */
2523 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2524 bool may_use_invariant, bool for_costs)
2526 enum rtx_code code = GET_CODE (x);
2527 struct elim_table *ep;
2534 if (! current_function_decl)
2557 /* First handle the case where we encounter a bare register that
2558 is eliminable. Replace it with a PLUS. */
2559 if (regno < FIRST_PSEUDO_REGISTER)
2561 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2563 if (ep->from_rtx == x && ep->can_eliminate)
2564 return plus_constant (ep->to_rtx, ep->previous_offset);
2567 else if (reg_renumber && reg_renumber[regno] < 0
2568 && reg_equiv_invariant && reg_equiv_invariant[regno])
2570 if (may_use_invariant || (insn && DEBUG_INSN_P (insn)))
2571 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2572 mem_mode, insn, true, for_costs);
2573 /* There exists at least one use of REGNO that cannot be
2574 eliminated. Prevent the defining insn from being deleted. */
2575 reg_equiv_init[regno] = NULL_RTX;
2577 alter_reg (regno, -1, true);
2581 /* You might think handling MINUS in a manner similar to PLUS is a
2582 good idea. It is not. It has been tried multiple times and every
2583 time the change has had to have been reverted.
2585 Other parts of reload know a PLUS is special (gen_reload for example)
2586 and require special code to handle code a reloaded PLUS operand.
2588 Also consider backends where the flags register is clobbered by a
2589 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2590 lea instruction comes to mind). If we try to reload a MINUS, we
2591 may kill the flags register that was holding a useful value.
2593 So, please before trying to handle MINUS, consider reload as a
2594 whole instead of this little section as well as the backend issues. */
2596 /* If this is the sum of an eliminable register and a constant, rework
2598 if (REG_P (XEXP (x, 0))
2599 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2600 && CONSTANT_P (XEXP (x, 1)))
2602 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2604 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2606 /* The only time we want to replace a PLUS with a REG (this
2607 occurs when the constant operand of the PLUS is the negative
2608 of the offset) is when we are inside a MEM. We won't want
2609 to do so at other times because that would change the
2610 structure of the insn in a way that reload can't handle.
2611 We special-case the commonest situation in
2612 eliminate_regs_in_insn, so just replace a PLUS with a
2613 PLUS here, unless inside a MEM. */
2614 if (mem_mode != 0 && CONST_INT_P (XEXP (x, 1))
2615 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2618 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2619 plus_constant (XEXP (x, 1),
2620 ep->previous_offset));
2623 /* If the register is not eliminable, we are done since the other
2624 operand is a constant. */
2628 /* If this is part of an address, we want to bring any constant to the
2629 outermost PLUS. We will do this by doing register replacement in
2630 our operands and seeing if a constant shows up in one of them.
2632 Note that there is no risk of modifying the structure of the insn,
2633 since we only get called for its operands, thus we are either
2634 modifying the address inside a MEM, or something like an address
2635 operand of a load-address insn. */
2638 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2640 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2643 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2645 /* If one side is a PLUS and the other side is a pseudo that
2646 didn't get a hard register but has a reg_equiv_constant,
2647 we must replace the constant here since it may no longer
2648 be in the position of any operand. */
2649 if (GET_CODE (new0) == PLUS && REG_P (new1)
2650 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2651 && reg_renumber[REGNO (new1)] < 0
2652 && reg_equiv_constant != 0
2653 && reg_equiv_constant[REGNO (new1)] != 0)
2654 new1 = reg_equiv_constant[REGNO (new1)];
2655 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2656 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2657 && reg_renumber[REGNO (new0)] < 0
2658 && reg_equiv_constant[REGNO (new0)] != 0)
2659 new0 = reg_equiv_constant[REGNO (new0)];
2661 new_rtx = form_sum (GET_MODE (x), new0, new1);
2663 /* As above, if we are not inside a MEM we do not want to
2664 turn a PLUS into something else. We might try to do so here
2665 for an addition of 0 if we aren't optimizing. */
2666 if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2667 return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2675 /* If this is the product of an eliminable register and a
2676 constant, apply the distribute law and move the constant out
2677 so that we have (plus (mult ..) ..). This is needed in order
2678 to keep load-address insns valid. This case is pathological.
2679 We ignore the possibility of overflow here. */
2680 if (REG_P (XEXP (x, 0))
2681 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2682 && CONST_INT_P (XEXP (x, 1)))
2683 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2685 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2688 /* Refs inside notes or in DEBUG_INSNs don't count for
2690 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2691 || GET_CODE (insn) == INSN_LIST
2692 || DEBUG_INSN_P (insn))))
2693 ep->ref_outside_mem = 1;
2696 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2697 ep->previous_offset * INTVAL (XEXP (x, 1)));
2700 /* ... fall through ... */
2704 /* See comments before PLUS about handling MINUS. */
2706 case DIV: case UDIV:
2707 case MOD: case UMOD:
2708 case AND: case IOR: case XOR:
2709 case ROTATERT: case ROTATE:
2710 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2712 case GE: case GT: case GEU: case GTU:
2713 case LE: case LT: case LEU: case LTU:
2715 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2717 rtx new1 = XEXP (x, 1)
2718 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false,
2721 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2722 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2727 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2730 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2732 if (new_rtx != XEXP (x, 0))
2734 /* If this is a REG_DEAD note, it is not valid anymore.
2735 Using the eliminated version could result in creating a
2736 REG_DEAD note for the stack or frame pointer. */
2737 if (REG_NOTE_KIND (x) == REG_DEAD)
2739 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2743 x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2747 /* ... fall through ... */
2750 /* Now do eliminations in the rest of the chain. If this was
2751 an EXPR_LIST, this might result in allocating more memory than is
2752 strictly needed, but it simplifies the code. */
2755 new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2757 if (new_rtx != XEXP (x, 1))
2759 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2767 /* We do not support elimination of a register that is modified.
2768 elimination_effects has already make sure that this does not
2774 /* We do not support elimination of a register that is modified.
2775 elimination_effects has already make sure that this does not
2776 happen. The only remaining case we need to consider here is
2777 that the increment value may be an eliminable register. */
2778 if (GET_CODE (XEXP (x, 1)) == PLUS
2779 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2781 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2782 insn, true, for_costs);
2784 if (new_rtx != XEXP (XEXP (x, 1), 1))
2785 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2786 gen_rtx_PLUS (GET_MODE (x),
2787 XEXP (x, 0), new_rtx));
2791 case STRICT_LOW_PART:
2793 case SIGN_EXTEND: case ZERO_EXTEND:
2794 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2795 case FLOAT: case FIX:
2796 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2805 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2807 if (new_rtx != XEXP (x, 0))
2808 return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2812 /* Similar to above processing, but preserve SUBREG_BYTE.
2813 Convert (subreg (mem)) to (mem) if not paradoxical.
2814 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2815 pseudo didn't get a hard reg, we must replace this with the
2816 eliminated version of the memory location because push_reload
2817 may do the replacement in certain circumstances. */
2818 if (REG_P (SUBREG_REG (x))
2819 && (GET_MODE_SIZE (GET_MODE (x))
2820 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2821 && reg_equiv_memory_loc != 0
2822 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2824 new_rtx = SUBREG_REG (x);
2827 new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false,
2830 if (new_rtx != SUBREG_REG (x))
2832 int x_size = GET_MODE_SIZE (GET_MODE (x));
2833 int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2836 && ((x_size < new_size
2837 #ifdef WORD_REGISTER_OPERATIONS
2838 /* On these machines, combine can create rtl of the form
2839 (set (subreg:m1 (reg:m2 R) 0) ...)
2840 where m1 < m2, and expects something interesting to
2841 happen to the entire word. Moreover, it will use the
2842 (reg:m2 R) later, expecting all bits to be preserved.
2843 So if the number of words is the same, preserve the
2844 subreg so that push_reload can see it. */
2845 && ! ((x_size - 1) / UNITS_PER_WORD
2846 == (new_size -1 ) / UNITS_PER_WORD)
2849 || x_size == new_size)
2851 return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2853 return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2859 /* Our only special processing is to pass the mode of the MEM to our
2860 recursive call and copy the flags. While we are here, handle this
2861 case more efficiently. */
2863 new_rtx = eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), insn, true,
2866 && memory_address_p (GET_MODE (x), XEXP (x, 0))
2867 && !memory_address_p (GET_MODE (x), new_rtx))
2868 for_each_rtx (&XEXP (x, 0), note_reg_elim_costly, insn);
2870 return replace_equiv_address_nv (x, new_rtx);
2873 /* Handle insn_list USE that a call to a pure function may generate. */
2874 new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false,
2876 if (new_rtx != XEXP (x, 0))
2877 return gen_rtx_USE (GET_MODE (x), new_rtx);
2881 gcc_assert (insn && DEBUG_INSN_P (insn));
2892 /* Process each of our operands recursively. If any have changed, make a
2894 fmt = GET_RTX_FORMAT (code);
2895 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2899 new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false,
2901 if (new_rtx != XEXP (x, i) && ! copied)
2903 x = shallow_copy_rtx (x);
2906 XEXP (x, i) = new_rtx;
2908 else if (*fmt == 'E')
2911 for (j = 0; j < XVECLEN (x, i); j++)
2913 new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false,
2915 if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2917 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2921 x = shallow_copy_rtx (x);
2924 XVEC (x, i) = new_v;
2927 XVECEXP (x, i, j) = new_rtx;
2936 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2938 return eliminate_regs_1 (x, mem_mode, insn, false, false);
2941 /* Scan rtx X for modifications of elimination target registers. Update
2942 the table of eliminables to reflect the changed state. MEM_MODE is
2943 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2946 elimination_effects (rtx x, enum machine_mode mem_mode)
2948 enum rtx_code code = GET_CODE (x);
2949 struct elim_table *ep;
2974 /* First handle the case where we encounter a bare register that
2975 is eliminable. Replace it with a PLUS. */
2976 if (regno < FIRST_PSEUDO_REGISTER)
2978 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2980 if (ep->from_rtx == x && ep->can_eliminate)
2983 ep->ref_outside_mem = 1;
2988 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2989 && reg_equiv_constant[regno]
2990 && ! function_invariant_p (reg_equiv_constant[regno]))
2991 elimination_effects (reg_equiv_constant[regno], mem_mode);
3000 /* If we modify the source of an elimination rule, disable it. */
3001 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3002 if (ep->from_rtx == XEXP (x, 0))
3003 ep->can_eliminate = 0;
3005 /* If we modify the target of an elimination rule by adding a constant,
3006 update its offset. If we modify the target in any other way, we'll
3007 have to disable the rule as well. */
3008 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3009 if (ep->to_rtx == XEXP (x, 0))
3011 int size = GET_MODE_SIZE (mem_mode);
3013 /* If more bytes than MEM_MODE are pushed, account for them. */
3014 #ifdef PUSH_ROUNDING
3015 if (ep->to_rtx == stack_pointer_rtx)
3016 size = PUSH_ROUNDING (size);
3018 if (code == PRE_DEC || code == POST_DEC)
3020 else if (code == PRE_INC || code == POST_INC)
3022 else if (code == PRE_MODIFY || code == POST_MODIFY)
3024 if (GET_CODE (XEXP (x, 1)) == PLUS
3025 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
3026 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
3027 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
3029 ep->can_eliminate = 0;
3033 /* These two aren't unary operators. */
3034 if (code == POST_MODIFY || code == PRE_MODIFY)
3037 /* Fall through to generic unary operation case. */
3038 case STRICT_LOW_PART:
3040 case SIGN_EXTEND: case ZERO_EXTEND:
3041 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3042 case FLOAT: case FIX:
3043 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3052 elimination_effects (XEXP (x, 0), mem_mode);
3056 if (REG_P (SUBREG_REG (x))
3057 && (GET_MODE_SIZE (GET_MODE (x))
3058 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3059 && reg_equiv_memory_loc != 0
3060 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
3063 elimination_effects (SUBREG_REG (x), mem_mode);
3067 /* If using a register that is the source of an eliminate we still
3068 think can be performed, note it cannot be performed since we don't
3069 know how this register is used. */
3070 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3071 if (ep->from_rtx == XEXP (x, 0))
3072 ep->can_eliminate = 0;
3074 elimination_effects (XEXP (x, 0), mem_mode);
3078 /* If clobbering a register that is the replacement register for an
3079 elimination we still think can be performed, note that it cannot
3080 be performed. Otherwise, we need not be concerned about it. */
3081 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3082 if (ep->to_rtx == XEXP (x, 0))
3083 ep->can_eliminate = 0;
3085 elimination_effects (XEXP (x, 0), mem_mode);
3089 /* Check for setting a register that we know about. */
3090 if (REG_P (SET_DEST (x)))
3092 /* See if this is setting the replacement register for an
3095 If DEST is the hard frame pointer, we do nothing because we
3096 assume that all assignments to the frame pointer are for
3097 non-local gotos and are being done at a time when they are valid
3098 and do not disturb anything else. Some machines want to
3099 eliminate a fake argument pointer (or even a fake frame pointer)
3100 with either the real frame or the stack pointer. Assignments to
3101 the hard frame pointer must not prevent this elimination. */
3103 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3105 if (ep->to_rtx == SET_DEST (x)
3106 && SET_DEST (x) != hard_frame_pointer_rtx)
3108 /* If it is being incremented, adjust the offset. Otherwise,
3109 this elimination can't be done. */
3110 rtx src = SET_SRC (x);
3112 if (GET_CODE (src) == PLUS
3113 && XEXP (src, 0) == SET_DEST (x)
3114 && CONST_INT_P (XEXP (src, 1)))
3115 ep->offset -= INTVAL (XEXP (src, 1));
3117 ep->can_eliminate = 0;
3121 elimination_effects (SET_DEST (x), VOIDmode);
3122 elimination_effects (SET_SRC (x), VOIDmode);
3126 /* Our only special processing is to pass the mode of the MEM to our
3128 elimination_effects (XEXP (x, 0), GET_MODE (x));
3135 fmt = GET_RTX_FORMAT (code);
3136 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3139 elimination_effects (XEXP (x, i), mem_mode);
3140 else if (*fmt == 'E')
3141 for (j = 0; j < XVECLEN (x, i); j++)
3142 elimination_effects (XVECEXP (x, i, j), mem_mode);
3146 /* Descend through rtx X and verify that no references to eliminable registers
3147 remain. If any do remain, mark the involved register as not
3151 check_eliminable_occurrences (rtx x)
3160 code = GET_CODE (x);
3162 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3164 struct elim_table *ep;
3166 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3167 if (ep->from_rtx == x)
3168 ep->can_eliminate = 0;
3172 fmt = GET_RTX_FORMAT (code);
3173 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3176 check_eliminable_occurrences (XEXP (x, i));
3177 else if (*fmt == 'E')
3180 for (j = 0; j < XVECLEN (x, i); j++)
3181 check_eliminable_occurrences (XVECEXP (x, i, j));
3186 /* Scan INSN and eliminate all eliminable registers in it.
3188 If REPLACE is nonzero, do the replacement destructively. Also
3189 delete the insn as dead it if it is setting an eliminable register.
3191 If REPLACE is zero, do all our allocations in reload_obstack.
3193 If no eliminations were done and this insn doesn't require any elimination
3194 processing (these are not identical conditions: it might be updating sp,
3195 but not referencing fp; this needs to be seen during reload_as_needed so
3196 that the offset between fp and sp can be taken into consideration), zero
3197 is returned. Otherwise, 1 is returned. */
3200 eliminate_regs_in_insn (rtx insn, int replace)
3202 int icode = recog_memoized (insn);
3203 rtx old_body = PATTERN (insn);
3204 int insn_is_asm = asm_noperands (old_body) >= 0;
3205 rtx old_set = single_set (insn);
3209 rtx substed_operand[MAX_RECOG_OPERANDS];
3210 rtx orig_operand[MAX_RECOG_OPERANDS];
3211 struct elim_table *ep;
3212 rtx plus_src, plus_cst_src;
3214 if (! insn_is_asm && icode < 0)
3216 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3217 || GET_CODE (PATTERN (insn)) == CLOBBER
3218 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3219 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3220 || GET_CODE (PATTERN (insn)) == ASM_INPUT
3221 || DEBUG_INSN_P (insn));
3222 if (DEBUG_INSN_P (insn))
3223 INSN_VAR_LOCATION_LOC (insn)
3224 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn), VOIDmode, insn);
3228 if (old_set != 0 && REG_P (SET_DEST (old_set))
3229 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3231 /* Check for setting an eliminable register. */
3232 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3233 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3235 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
3236 /* If this is setting the frame pointer register to the
3237 hardware frame pointer register and this is an elimination
3238 that will be done (tested above), this insn is really
3239 adjusting the frame pointer downward to compensate for
3240 the adjustment done before a nonlocal goto. */
3241 if (ep->from == FRAME_POINTER_REGNUM
3242 && ep->to == HARD_FRAME_POINTER_REGNUM)
3244 rtx base = SET_SRC (old_set);
3245 rtx base_insn = insn;
3246 HOST_WIDE_INT offset = 0;
3248 while (base != ep->to_rtx)
3250 rtx prev_insn, prev_set;
3252 if (GET_CODE (base) == PLUS
3253 && CONST_INT_P (XEXP (base, 1)))
3255 offset += INTVAL (XEXP (base, 1));
3256 base = XEXP (base, 0);
3258 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3259 && (prev_set = single_set (prev_insn)) != 0
3260 && rtx_equal_p (SET_DEST (prev_set), base))
3262 base = SET_SRC (prev_set);
3263 base_insn = prev_insn;
3269 if (base == ep->to_rtx)
3272 = plus_constant (ep->to_rtx, offset - ep->offset);
3274 new_body = old_body;
3277 new_body = copy_insn (old_body);
3278 if (REG_NOTES (insn))
3279 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3281 PATTERN (insn) = new_body;
3282 old_set = single_set (insn);
3284 /* First see if this insn remains valid when we
3285 make the change. If not, keep the INSN_CODE
3286 the same and let reload fit it up. */
3287 validate_change (insn, &SET_SRC (old_set), src, 1);
3288 validate_change (insn, &SET_DEST (old_set),
3290 if (! apply_change_group ())
3292 SET_SRC (old_set) = src;
3293 SET_DEST (old_set) = ep->to_rtx;
3302 /* In this case this insn isn't serving a useful purpose. We
3303 will delete it in reload_as_needed once we know that this
3304 elimination is, in fact, being done.
3306 If REPLACE isn't set, we can't delete this insn, but needn't
3307 process it since it won't be used unless something changes. */
3310 delete_dead_insn (insn);
3318 /* We allow one special case which happens to work on all machines we
3319 currently support: a single set with the source or a REG_EQUAL
3320 note being a PLUS of an eliminable register and a constant. */
3321 plus_src = plus_cst_src = 0;
3322 if (old_set && REG_P (SET_DEST (old_set)))
3324 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3325 plus_src = SET_SRC (old_set);
3326 /* First see if the source is of the form (plus (...) CST). */
3328 && CONST_INT_P (XEXP (plus_src, 1)))
3329 plus_cst_src = plus_src;
3330 else if (REG_P (SET_SRC (old_set))
3333 /* Otherwise, see if we have a REG_EQUAL note of the form
3334 (plus (...) CST). */
3336 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3338 if ((REG_NOTE_KIND (links) == REG_EQUAL
3339 || REG_NOTE_KIND (links) == REG_EQUIV)
3340 && GET_CODE (XEXP (links, 0)) == PLUS
3341 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3343 plus_cst_src = XEXP (links, 0);
3349 /* Check that the first operand of the PLUS is a hard reg or
3350 the lowpart subreg of one. */
3353 rtx reg = XEXP (plus_cst_src, 0);
3354 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3355 reg = SUBREG_REG (reg);
3357 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3363 rtx reg = XEXP (plus_cst_src, 0);
3364 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3366 if (GET_CODE (reg) == SUBREG)
3367 reg = SUBREG_REG (reg);
3369 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3370 if (ep->from_rtx == reg && ep->can_eliminate)
3372 rtx to_rtx = ep->to_rtx;
3373 offset += ep->offset;
3374 offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
3376 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3377 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3379 /* If we have a nonzero offset, and the source is already
3380 a simple REG, the following transformation would
3381 increase the cost of the insn by replacing a simple REG
3382 with (plus (reg sp) CST). So try only when we already
3383 had a PLUS before. */
3384 if (offset == 0 || plus_src)
3386 rtx new_src = plus_constant (to_rtx, offset);
3388 new_body = old_body;
3391 new_body = copy_insn (old_body);
3392 if (REG_NOTES (insn))
3393 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3395 PATTERN (insn) = new_body;
3396 old_set = single_set (insn);
3398 /* First see if this insn remains valid when we make the
3399 change. If not, try to replace the whole pattern with
3400 a simple set (this may help if the original insn was a
3401 PARALLEL that was only recognized as single_set due to
3402 REG_UNUSED notes). If this isn't valid either, keep
3403 the INSN_CODE the same and let reload fix it up. */
3404 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3406 rtx new_pat = gen_rtx_SET (VOIDmode,
3407 SET_DEST (old_set), new_src);
3409 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3410 SET_SRC (old_set) = new_src;
3417 /* This can't have an effect on elimination offsets, so skip right
3423 /* Determine the effects of this insn on elimination offsets. */
3424 elimination_effects (old_body, VOIDmode);
3426 /* Eliminate all eliminable registers occurring in operands that
3427 can be handled by reload. */
3428 extract_insn (insn);
3429 for (i = 0; i < recog_data.n_operands; i++)
3431 orig_operand[i] = recog_data.operand[i];
3432 substed_operand[i] = recog_data.operand[i];
3434 /* For an asm statement, every operand is eliminable. */
3435 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3437 bool is_set_src, in_plus;
3439 /* Check for setting a register that we know about. */
3440 if (recog_data.operand_type[i] != OP_IN
3441 && REG_P (orig_operand[i]))
3443 /* If we are assigning to a register that can be eliminated, it
3444 must be as part of a PARALLEL, since the code above handles
3445 single SETs. We must indicate that we can no longer
3446 eliminate this reg. */
3447 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3449 if (ep->from_rtx == orig_operand[i])
3450 ep->can_eliminate = 0;
3453 /* Companion to the above plus substitution, we can allow
3454 invariants as the source of a plain move. */
3457 && recog_data.operand_loc[i] == &SET_SRC (old_set))
3461 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3462 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3466 = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3467 replace ? insn : NULL_RTX,
3468 is_set_src || in_plus, false);
3469 if (substed_operand[i] != orig_operand[i])
3471 /* Terminate the search in check_eliminable_occurrences at
3473 *recog_data.operand_loc[i] = 0;
3475 /* If an output operand changed from a REG to a MEM and INSN is an
3476 insn, write a CLOBBER insn. */
3477 if (recog_data.operand_type[i] != OP_IN
3478 && REG_P (orig_operand[i])
3479 && MEM_P (substed_operand[i])
3481 emit_insn_after (gen_clobber (orig_operand[i]), insn);
3485 for (i = 0; i < recog_data.n_dups; i++)
3486 *recog_data.dup_loc[i]
3487 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3489 /* If any eliminable remain, they aren't eliminable anymore. */
3490 check_eliminable_occurrences (old_body);
3492 /* Substitute the operands; the new values are in the substed_operand
3494 for (i = 0; i < recog_data.n_operands; i++)
3495 *recog_data.operand_loc[i] = substed_operand[i];
3496 for (i = 0; i < recog_data.n_dups; i++)
3497 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3499 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3500 re-recognize the insn. We do this in case we had a simple addition
3501 but now can do this as a load-address. This saves an insn in this
3503 If re-recognition fails, the old insn code number will still be used,
3504 and some register operands may have changed into PLUS expressions.
3505 These will be handled by find_reloads by loading them into a register
3510 /* If we aren't replacing things permanently and we changed something,
3511 make another copy to ensure that all the RTL is new. Otherwise
3512 things can go wrong if find_reload swaps commutative operands
3513 and one is inside RTL that has been copied while the other is not. */
3514 new_body = old_body;
3517 new_body = copy_insn (old_body);
3518 if (REG_NOTES (insn))
3519 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3521 PATTERN (insn) = new_body;
3523 /* If we had a move insn but now we don't, rerecognize it. This will
3524 cause spurious re-recognition if the old move had a PARALLEL since
3525 the new one still will, but we can't call single_set without
3526 having put NEW_BODY into the insn and the re-recognition won't
3527 hurt in this rare case. */
3528 /* ??? Why this huge if statement - why don't we just rerecognize the
3532 && ((REG_P (SET_SRC (old_set))
3533 && (GET_CODE (new_body) != SET
3534 || !REG_P (SET_SRC (new_body))))
3535 /* If this was a load from or store to memory, compare
3536 the MEM in recog_data.operand to the one in the insn.
3537 If they are not equal, then rerecognize the insn. */
3539 && ((MEM_P (SET_SRC (old_set))
3540 && SET_SRC (old_set) != recog_data.operand[1])
3541 || (MEM_P (SET_DEST (old_set))
3542 && SET_DEST (old_set) != recog_data.operand[0])))
3543 /* If this was an add insn before, rerecognize. */
3544 || GET_CODE (SET_SRC (old_set)) == PLUS))
3546 int new_icode = recog (PATTERN (insn), insn, 0);
3548 INSN_CODE (insn) = new_icode;
3552 /* Restore the old body. If there were any changes to it, we made a copy
3553 of it while the changes were still in place, so we'll correctly return
3554 a modified insn below. */
3557 /* Restore the old body. */
3558 for (i = 0; i < recog_data.n_operands; i++)
3559 /* Restoring a top-level match_parallel would clobber the new_body
3560 we installed in the insn. */
3561 if (recog_data.operand_loc[i] != &PATTERN (insn))
3562 *recog_data.operand_loc[i] = orig_operand[i];
3563 for (i = 0; i < recog_data.n_dups; i++)
3564 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3567 /* Update all elimination pairs to reflect the status after the current
3568 insn. The changes we make were determined by the earlier call to
3569 elimination_effects.
3571 We also detect cases where register elimination cannot be done,
3572 namely, if a register would be both changed and referenced outside a MEM
3573 in the resulting insn since such an insn is often undefined and, even if
3574 not, we cannot know what meaning will be given to it. Note that it is
3575 valid to have a register used in an address in an insn that changes it
3576 (presumably with a pre- or post-increment or decrement).
3578 If anything changes, return nonzero. */
3580 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3582 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3583 ep->can_eliminate = 0;
3585 ep->ref_outside_mem = 0;
3587 if (ep->previous_offset != ep->offset)
3592 /* If we changed something, perform elimination in REG_NOTES. This is
3593 needed even when REPLACE is zero because a REG_DEAD note might refer
3594 to a register that we eliminate and could cause a different number
3595 of spill registers to be needed in the final reload pass than in
3597 if (val && REG_NOTES (insn) != 0)
3599 = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true,
3605 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3606 register allocator. INSN is the instruction we need to examine, we perform
3607 eliminations in its operands and record cases where eliminating a reg with
3608 an invariant equivalence would add extra cost. */
3611 elimination_costs_in_insn (rtx insn)
3613 int icode = recog_memoized (insn);
3614 rtx old_body = PATTERN (insn);
3615 int insn_is_asm = asm_noperands (old_body) >= 0;
3616 rtx old_set = single_set (insn);
3618 rtx orig_operand[MAX_RECOG_OPERANDS];
3619 rtx orig_dup[MAX_RECOG_OPERANDS];
3620 struct elim_table *ep;
3621 rtx plus_src, plus_cst_src;
3624 if (! insn_is_asm && icode < 0)
3626 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3627 || GET_CODE (PATTERN (insn)) == CLOBBER
3628 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3629 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3630 || GET_CODE (PATTERN (insn)) == ASM_INPUT
3631 || DEBUG_INSN_P (insn));
3635 if (old_set != 0 && REG_P (SET_DEST (old_set))
3636 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3638 /* Check for setting an eliminable register. */
3639 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3640 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3644 /* We allow one special case which happens to work on all machines we
3645 currently support: a single set with the source or a REG_EQUAL
3646 note being a PLUS of an eliminable register and a constant. */
3647 plus_src = plus_cst_src = 0;
3649 if (old_set && REG_P (SET_DEST (old_set)))
3652 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3653 plus_src = SET_SRC (old_set);
3654 /* First see if the source is of the form (plus (...) CST). */
3656 && CONST_INT_P (XEXP (plus_src, 1)))
3657 plus_cst_src = plus_src;
3658 else if (REG_P (SET_SRC (old_set))
3661 /* Otherwise, see if we have a REG_EQUAL note of the form
3662 (plus (...) CST). */
3664 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3666 if ((REG_NOTE_KIND (links) == REG_EQUAL
3667 || REG_NOTE_KIND (links) == REG_EQUIV)
3668 && GET_CODE (XEXP (links, 0)) == PLUS
3669 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3671 plus_cst_src = XEXP (links, 0);
3678 /* Determine the effects of this insn on elimination offsets. */
3679 elimination_effects (old_body, VOIDmode);
3681 /* Eliminate all eliminable registers occurring in operands that
3682 can be handled by reload. */
3683 extract_insn (insn);
3684 for (i = 0; i < recog_data.n_dups; i++)
3685 orig_dup[i] = *recog_data.dup_loc[i];
3687 for (i = 0; i < recog_data.n_operands; i++)
3689 orig_operand[i] = recog_data.operand[i];
3691 /* For an asm statement, every operand is eliminable. */
3692 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3694 bool is_set_src, in_plus;
3696 /* Check for setting a register that we know about. */
3697 if (recog_data.operand_type[i] != OP_IN
3698 && REG_P (orig_operand[i]))
3700 /* If we are assigning to a register that can be eliminated, it
3701 must be as part of a PARALLEL, since the code above handles
3702 single SETs. We must indicate that we can no longer
3703 eliminate this reg. */
3704 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3706 if (ep->from_rtx == orig_operand[i])
3707 ep->can_eliminate = 0;
3710 /* Companion to the above plus substitution, we can allow
3711 invariants as the source of a plain move. */
3713 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3715 if (is_set_src && !sets_reg_p)
3716 note_reg_elim_costly (&SET_SRC (old_set), insn);
3718 if (plus_src && sets_reg_p
3719 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3720 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3723 eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3725 is_set_src || in_plus, true);
3726 /* Terminate the search in check_eliminable_occurrences at
3728 *recog_data.operand_loc[i] = 0;
3732 for (i = 0; i < recog_data.n_dups; i++)
3733 *recog_data.dup_loc[i]
3734 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3736 /* If any eliminable remain, they aren't eliminable anymore. */
3737 check_eliminable_occurrences (old_body);
3739 /* Restore the old body. */
3740 for (i = 0; i < recog_data.n_operands; i++)
3741 *recog_data.operand_loc[i] = orig_operand[i];
3742 for (i = 0; i < recog_data.n_dups; i++)
3743 *recog_data.dup_loc[i] = orig_dup[i];
3745 /* Update all elimination pairs to reflect the status after the current
3746 insn. The changes we make were determined by the earlier call to
3747 elimination_effects. */
3749 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3751 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3752 ep->can_eliminate = 0;
3754 ep->ref_outside_mem = 0;
3760 /* Loop through all elimination pairs.
3761 Recalculate the number not at initial offset.
3763 Compute the maximum offset (minimum offset if the stack does not
3764 grow downward) for each elimination pair. */
3767 update_eliminable_offsets (void)
3769 struct elim_table *ep;
3771 num_not_at_initial_offset = 0;
3772 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3774 ep->previous_offset = ep->offset;
3775 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3776 num_not_at_initial_offset++;
3780 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3781 replacement we currently believe is valid, mark it as not eliminable if X
3782 modifies DEST in any way other than by adding a constant integer to it.
3784 If DEST is the frame pointer, we do nothing because we assume that
3785 all assignments to the hard frame pointer are nonlocal gotos and are being
3786 done at a time when they are valid and do not disturb anything else.
3787 Some machines want to eliminate a fake argument pointer with either the
3788 frame or stack pointer. Assignments to the hard frame pointer must not
3789 prevent this elimination.
3791 Called via note_stores from reload before starting its passes to scan
3792 the insns of the function. */
3795 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3799 /* A SUBREG of a hard register here is just changing its mode. We should
3800 not see a SUBREG of an eliminable hard register, but check just in
3802 if (GET_CODE (dest) == SUBREG)
3803 dest = SUBREG_REG (dest);
3805 if (dest == hard_frame_pointer_rtx)
3808 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3809 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3810 && (GET_CODE (x) != SET
3811 || GET_CODE (SET_SRC (x)) != PLUS
3812 || XEXP (SET_SRC (x), 0) != dest
3813 || !CONST_INT_P (XEXP (SET_SRC (x), 1))))
3815 reg_eliminate[i].can_eliminate_previous
3816 = reg_eliminate[i].can_eliminate = 0;
3821 /* Verify that the initial elimination offsets did not change since the
3822 last call to set_initial_elim_offsets. This is used to catch cases
3823 where something illegal happened during reload_as_needed that could
3824 cause incorrect code to be generated if we did not check for it. */
3827 verify_initial_elim_offsets (void)
3831 if (!num_eliminable)
3834 #ifdef ELIMINABLE_REGS
3836 struct elim_table *ep;
3838 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3840 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3841 if (t != ep->initial_offset)
3846 INITIAL_FRAME_POINTER_OFFSET (t);
3847 if (t != reg_eliminate[0].initial_offset)
3854 /* Reset all offsets on eliminable registers to their initial values. */
3857 set_initial_elim_offsets (void)
3859 struct elim_table *ep = reg_eliminate;
3861 #ifdef ELIMINABLE_REGS
3862 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3864 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3865 ep->previous_offset = ep->offset = ep->initial_offset;
3868 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3869 ep->previous_offset = ep->offset = ep->initial_offset;
3872 num_not_at_initial_offset = 0;
3875 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3878 set_initial_eh_label_offset (rtx label)
3880 set_label_offsets (label, NULL_RTX, 1);
3883 /* Initialize the known label offsets.
3884 Set a known offset for each forced label to be at the initial offset
3885 of each elimination. We do this because we assume that all
3886 computed jumps occur from a location where each elimination is
3887 at its initial offset.
3888 For all other labels, show that we don't know the offsets. */
3891 set_initial_label_offsets (void)
3894 memset (offsets_known_at, 0, num_labels);
3896 for (x = forced_labels; x; x = XEXP (x, 1))
3898 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3900 for_each_eh_label (set_initial_eh_label_offset);
3903 /* Set all elimination offsets to the known values for the code label given
3907 set_offsets_for_label (rtx insn)
3910 int label_nr = CODE_LABEL_NUMBER (insn);
3911 struct elim_table *ep;
3913 num_not_at_initial_offset = 0;
3914 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3916 ep->offset = ep->previous_offset
3917 = offsets_at[label_nr - first_label_num][i];
3918 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3919 num_not_at_initial_offset++;
3923 /* See if anything that happened changes which eliminations are valid.
3924 For example, on the SPARC, whether or not the frame pointer can
3925 be eliminated can depend on what registers have been used. We need
3926 not check some conditions again (such as flag_omit_frame_pointer)
3927 since they can't have changed. */
3930 update_eliminables (HARD_REG_SET *pset)
3932 int previous_frame_pointer_needed = frame_pointer_needed;
3933 struct elim_table *ep;
3935 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3936 if ((ep->from == HARD_FRAME_POINTER_REGNUM
3937 && targetm.frame_pointer_required ())
3938 #ifdef ELIMINABLE_REGS
3939 || ! targetm.can_eliminate (ep->from, ep->to)
3942 ep->can_eliminate = 0;
3944 /* Look for the case where we have discovered that we can't replace
3945 register A with register B and that means that we will now be
3946 trying to replace register A with register C. This means we can
3947 no longer replace register C with register B and we need to disable
3948 such an elimination, if it exists. This occurs often with A == ap,
3949 B == sp, and C == fp. */
3951 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3953 struct elim_table *op;
3956 if (! ep->can_eliminate && ep->can_eliminate_previous)
3958 /* Find the current elimination for ep->from, if there is a
3960 for (op = reg_eliminate;
3961 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3962 if (op->from == ep->from && op->can_eliminate)
3968 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3970 for (op = reg_eliminate;
3971 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3972 if (op->from == new_to && op->to == ep->to)
3973 op->can_eliminate = 0;
3977 /* See if any registers that we thought we could eliminate the previous
3978 time are no longer eliminable. If so, something has changed and we
3979 must spill the register. Also, recompute the number of eliminable
3980 registers and see if the frame pointer is needed; it is if there is
3981 no elimination of the frame pointer that we can perform. */
3983 frame_pointer_needed = 1;
3984 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3986 if (ep->can_eliminate
3987 && ep->from == FRAME_POINTER_REGNUM
3988 && ep->to != HARD_FRAME_POINTER_REGNUM
3989 && (! SUPPORTS_STACK_ALIGNMENT
3990 || ! crtl->stack_realign_needed))
3991 frame_pointer_needed = 0;
3993 if (! ep->can_eliminate && ep->can_eliminate_previous)
3995 ep->can_eliminate_previous = 0;
3996 SET_HARD_REG_BIT (*pset, ep->from);
4001 /* If we didn't need a frame pointer last time, but we do now, spill
4002 the hard frame pointer. */
4003 if (frame_pointer_needed && ! previous_frame_pointer_needed)
4004 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
4007 /* Return true if X is used as the target register of an elimination. */
4010 elimination_target_reg_p (rtx x)
4012 struct elim_table *ep;
4014 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4015 if (ep->to_rtx == x && ep->can_eliminate)
4021 /* Initialize the table of registers to eliminate.
4022 Pre-condition: global flag frame_pointer_needed has been set before
4023 calling this function. */
4026 init_elim_table (void)
4028 struct elim_table *ep;
4029 #ifdef ELIMINABLE_REGS
4030 const struct elim_table_1 *ep1;
4034 reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
4038 #ifdef ELIMINABLE_REGS
4039 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
4040 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
4042 ep->from = ep1->from;
4044 ep->can_eliminate = ep->can_eliminate_previous
4045 = (targetm.can_eliminate (ep->from, ep->to)
4046 && ! (ep->to == STACK_POINTER_REGNUM
4047 && frame_pointer_needed
4048 && (! SUPPORTS_STACK_ALIGNMENT
4049 || ! stack_realign_fp)));
4052 reg_eliminate[0].from = reg_eliminate_1[0].from;
4053 reg_eliminate[0].to = reg_eliminate_1[0].to;
4054 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
4055 = ! frame_pointer_needed;
4058 /* Count the number of eliminable registers and build the FROM and TO
4059 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
4060 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
4061 We depend on this. */
4062 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4064 num_eliminable += ep->can_eliminate;
4065 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
4066 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
4070 /* Find all the pseudo registers that didn't get hard regs
4071 but do have known equivalent constants or memory slots.
4072 These include parameters (known equivalent to parameter slots)
4073 and cse'd or loop-moved constant memory addresses.
4075 Record constant equivalents in reg_equiv_constant
4076 so they will be substituted by find_reloads.
4077 Record memory equivalents in reg_mem_equiv so they can
4078 be substituted eventually by altering the REG-rtx's. */
4081 init_eliminable_invariants (rtx first, bool do_subregs)
4086 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
4087 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
4088 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
4089 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
4090 reg_equiv_address = XCNEWVEC (rtx, max_regno);
4092 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
4094 reg_max_ref_width = NULL;
4096 num_eliminable_invariants = 0;
4098 first_label_num = get_first_label_num ();
4099 num_labels = max_label_num () - first_label_num;
4101 /* Allocate the tables used to store offset information at labels. */
4102 offsets_known_at = XNEWVEC (char, num_labels);
4103 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
4105 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4106 to. If DO_SUBREGS is true, also find all paradoxical subregs and
4107 find largest such for each pseudo. FIRST is the head of the insn
4110 for (insn = first; insn; insn = NEXT_INSN (insn))
4112 rtx set = single_set (insn);
4114 /* We may introduce USEs that we want to remove at the end, so
4115 we'll mark them with QImode. Make sure there are no
4116 previously-marked insns left by say regmove. */
4117 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
4118 && GET_MODE (insn) != VOIDmode)
4119 PUT_MODE (insn, VOIDmode);
4121 if (do_subregs && NONDEBUG_INSN_P (insn))
4122 scan_paradoxical_subregs (PATTERN (insn));
4124 if (set != 0 && REG_P (SET_DEST (set)))
4126 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
4132 i = REGNO (SET_DEST (set));
4135 if (i <= LAST_VIRTUAL_REGISTER)
4138 /* If flag_pic and we have constant, verify it's legitimate. */
4140 || !flag_pic || LEGITIMATE_PIC_OPERAND_P (x))
4142 /* It can happen that a REG_EQUIV note contains a MEM
4143 that is not a legitimate memory operand. As later
4144 stages of reload assume that all addresses found
4145 in the reg_equiv_* arrays were originally legitimate,
4146 we ignore such REG_EQUIV notes. */
4147 if (memory_operand (x, VOIDmode))
4149 /* Always unshare the equivalence, so we can
4150 substitute into this insn without touching the
4152 reg_equiv_memory_loc[i] = copy_rtx (x);
4154 else if (function_invariant_p (x))
4156 if (GET_CODE (x) == PLUS)
4158 /* This is PLUS of frame pointer and a constant,
4159 and might be shared. Unshare it. */
4160 reg_equiv_invariant[i] = copy_rtx (x);
4161 num_eliminable_invariants++;
4163 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4165 reg_equiv_invariant[i] = x;
4166 num_eliminable_invariants++;
4168 else if (LEGITIMATE_CONSTANT_P (x))
4169 reg_equiv_constant[i] = x;
4172 reg_equiv_memory_loc[i]
4173 = force_const_mem (GET_MODE (SET_DEST (set)), x);
4174 if (! reg_equiv_memory_loc[i])
4175 reg_equiv_init[i] = NULL_RTX;
4180 reg_equiv_init[i] = NULL_RTX;
4185 reg_equiv_init[i] = NULL_RTX;
4190 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4191 if (reg_equiv_init[i])
4193 fprintf (dump_file, "init_insns for %u: ", i);
4194 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
4195 fprintf (dump_file, "\n");
4199 /* Indicate that we no longer have known memory locations or constants.
4200 Free all data involved in tracking these. */
4203 free_reg_equiv (void)
4207 if (reg_equiv_constant)
4208 free (reg_equiv_constant);
4209 if (reg_equiv_invariant)
4210 free (reg_equiv_invariant);
4211 reg_equiv_constant = 0;
4212 reg_equiv_invariant = 0;
4213 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
4214 reg_equiv_memory_loc = 0;
4216 if (offsets_known_at)
4217 free (offsets_known_at);
4221 offsets_known_at = 0;
4223 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4224 if (reg_equiv_alt_mem_list[i])
4225 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
4226 free (reg_equiv_alt_mem_list);
4228 free (reg_equiv_mem);
4229 free (reg_equiv_address);
4232 /* Kick all pseudos out of hard register REGNO.
4234 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4235 because we found we can't eliminate some register. In the case, no pseudos
4236 are allowed to be in the register, even if they are only in a block that
4237 doesn't require spill registers, unlike the case when we are spilling this
4238 hard reg to produce another spill register.
4240 Return nonzero if any pseudos needed to be kicked out. */
4243 spill_hard_reg (unsigned int regno, int cant_eliminate)
4249 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
4250 df_set_regs_ever_live (regno, true);
4253 /* Spill every pseudo reg that was allocated to this reg
4254 or to something that overlaps this reg. */
4256 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4257 if (reg_renumber[i] >= 0
4258 && (unsigned int) reg_renumber[i] <= regno
4259 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
4260 SET_REGNO_REG_SET (&spilled_pseudos, i);
4263 /* After find_reload_regs has been run for all insn that need reloads,
4264 and/or spill_hard_regs was called, this function is used to actually
4265 spill pseudo registers and try to reallocate them. It also sets up the
4266 spill_regs array for use by choose_reload_regs. */
4269 finish_spills (int global)
4271 struct insn_chain *chain;
4272 int something_changed = 0;
4274 reg_set_iterator rsi;
4276 /* Build the spill_regs array for the function. */
4277 /* If there are some registers still to eliminate and one of the spill regs
4278 wasn't ever used before, additional stack space may have to be
4279 allocated to store this register. Thus, we may have changed the offset
4280 between the stack and frame pointers, so mark that something has changed.
4282 One might think that we need only set VAL to 1 if this is a call-used
4283 register. However, the set of registers that must be saved by the
4284 prologue is not identical to the call-used set. For example, the
4285 register used by the call insn for the return PC is a call-used register,
4286 but must be saved by the prologue. */
4289 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4290 if (TEST_HARD_REG_BIT (used_spill_regs, i))
4292 spill_reg_order[i] = n_spills;
4293 spill_regs[n_spills++] = i;
4294 if (num_eliminable && ! df_regs_ever_live_p (i))
4295 something_changed = 1;
4296 df_set_regs_ever_live (i, true);
4299 spill_reg_order[i] = -1;
4301 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
4302 if (! ira_conflicts_p || reg_renumber[i] >= 0)
4304 /* Record the current hard register the pseudo is allocated to
4305 in pseudo_previous_regs so we avoid reallocating it to the
4306 same hard reg in a later pass. */
4307 gcc_assert (reg_renumber[i] >= 0);
4309 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
4310 /* Mark it as no longer having a hard register home. */
4311 reg_renumber[i] = -1;
4312 if (ira_conflicts_p)
4313 /* Inform IRA about the change. */
4314 ira_mark_allocation_change (i);
4315 /* We will need to scan everything again. */
4316 something_changed = 1;
4319 /* Retry global register allocation if possible. */
4320 if (global && ira_conflicts_p)
4324 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
4325 /* For every insn that needs reloads, set the registers used as spill
4326 regs in pseudo_forbidden_regs for every pseudo live across the
4328 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
4330 EXECUTE_IF_SET_IN_REG_SET
4331 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
4333 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4334 chain->used_spill_regs);
4336 EXECUTE_IF_SET_IN_REG_SET
4337 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
4339 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4340 chain->used_spill_regs);
4344 /* Retry allocating the pseudos spilled in IRA and the
4345 reload. For each reg, merge the various reg sets that
4346 indicate which hard regs can't be used, and call
4347 ira_reassign_pseudos. */
4348 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
4349 if (reg_old_renumber[i] != reg_renumber[i])
4351 if (reg_renumber[i] < 0)
4352 temp_pseudo_reg_arr[n++] = i;
4354 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4356 if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
4357 bad_spill_regs_global,
4358 pseudo_forbidden_regs, pseudo_previous_regs,
4360 something_changed = 1;
4362 /* Fix up the register information in the insn chain.
4363 This involves deleting those of the spilled pseudos which did not get
4364 a new hard register home from the live_{before,after} sets. */
4365 for (chain = reload_insn_chain; chain; chain = chain->next)
4367 HARD_REG_SET used_by_pseudos;
4368 HARD_REG_SET used_by_pseudos2;
4370 if (! ira_conflicts_p)
4372 /* Don't do it for IRA because IRA and the reload still can
4373 assign hard registers to the spilled pseudos on next
4374 reload iterations. */
4375 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
4376 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
4378 /* Mark any unallocated hard regs as available for spills. That
4379 makes inheritance work somewhat better. */
4380 if (chain->need_reload)
4382 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
4383 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
4384 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
4386 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
4387 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
4388 /* Value of chain->used_spill_regs from previous iteration
4389 may be not included in the value calculated here because
4390 of possible removing caller-saves insns (see function
4391 delete_caller_save_insns. */
4392 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
4393 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4397 CLEAR_REG_SET (&changed_allocation_pseudos);
4398 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4399 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4401 int regno = reg_renumber[i];
4402 if (reg_old_renumber[i] == regno)
4405 SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4407 alter_reg (i, reg_old_renumber[i], false);
4408 reg_old_renumber[i] = regno;
4412 fprintf (dump_file, " Register %d now on stack.\n\n", i);
4414 fprintf (dump_file, " Register %d now in %d.\n\n",
4415 i, reg_renumber[i]);
4419 return something_changed;
4422 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4425 scan_paradoxical_subregs (rtx x)
4429 enum rtx_code code = GET_CODE (x);
4440 case CONST_VECTOR: /* shouldn't happen, but just in case. */
4448 if (REG_P (SUBREG_REG (x))
4449 && (GET_MODE_SIZE (GET_MODE (x))
4450 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
4452 reg_max_ref_width[REGNO (SUBREG_REG (x))]
4453 = GET_MODE_SIZE (GET_MODE (x));
4454 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
4462 fmt = GET_RTX_FORMAT (code);
4463 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4466 scan_paradoxical_subregs (XEXP (x, i));
4467 else if (fmt[i] == 'E')
4470 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4471 scan_paradoxical_subregs (XVECEXP (x, i, j));
4476 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4477 examine all of the reload insns between PREV and NEXT exclusive, and
4478 annotate all that may trap. */
4481 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
4483 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4486 if (!insn_could_throw_p (insn))
4487 remove_note (insn, note);
4488 copy_reg_eh_region_note_forward (note, NEXT_INSN (prev), next);
4491 /* Reload pseudo-registers into hard regs around each insn as needed.
4492 Additional register load insns are output before the insn that needs it
4493 and perhaps store insns after insns that modify the reloaded pseudo reg.
4495 reg_last_reload_reg and reg_reloaded_contents keep track of
4496 which registers are already available in reload registers.
4497 We update these for the reloads that we perform,
4498 as the insns are scanned. */
4501 reload_as_needed (int live_known)
4503 struct insn_chain *chain;
4504 #if defined (AUTO_INC_DEC)
4509 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4510 memset (spill_reg_store, 0, sizeof spill_reg_store);
4511 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4512 INIT_REG_SET (®_has_output_reload);
4513 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4514 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4516 set_initial_elim_offsets ();
4518 for (chain = reload_insn_chain; chain; chain = chain->next)
4521 rtx insn = chain->insn;
4522 rtx old_next = NEXT_INSN (insn);
4524 rtx old_prev = PREV_INSN (insn);
4527 /* If we pass a label, copy the offsets from the label information
4528 into the current offsets of each elimination. */
4530 set_offsets_for_label (insn);
4532 else if (INSN_P (insn))
4534 regset_head regs_to_forget;
4535 INIT_REG_SET (®s_to_forget);
4536 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4538 /* If this is a USE and CLOBBER of a MEM, ensure that any
4539 references to eliminable registers have been removed. */
4541 if ((GET_CODE (PATTERN (insn)) == USE
4542 || GET_CODE (PATTERN (insn)) == CLOBBER)
4543 && MEM_P (XEXP (PATTERN (insn), 0)))
4544 XEXP (XEXP (PATTERN (insn), 0), 0)
4545 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4546 GET_MODE (XEXP (PATTERN (insn), 0)),
4549 /* If we need to do register elimination processing, do so.
4550 This might delete the insn, in which case we are done. */
4551 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4553 eliminate_regs_in_insn (insn, 1);
4556 update_eliminable_offsets ();
4557 CLEAR_REG_SET (®s_to_forget);
4562 /* If need_elim is nonzero but need_reload is zero, one might think
4563 that we could simply set n_reloads to 0. However, find_reloads
4564 could have done some manipulation of the insn (such as swapping
4565 commutative operands), and these manipulations are lost during
4566 the first pass for every insn that needs register elimination.
4567 So the actions of find_reloads must be redone here. */
4569 if (! chain->need_elim && ! chain->need_reload
4570 && ! chain->need_operand_change)
4572 /* First find the pseudo regs that must be reloaded for this insn.
4573 This info is returned in the tables reload_... (see reload.h).
4574 Also modify the body of INSN by substituting RELOAD
4575 rtx's for those pseudo regs. */
4578 CLEAR_REG_SET (®_has_output_reload);
4579 CLEAR_HARD_REG_SET (reg_is_output_reload);
4581 find_reloads (insn, 1, spill_indirect_levels, live_known,
4587 rtx next = NEXT_INSN (insn);
4590 prev = PREV_INSN (insn);
4592 /* Now compute which reload regs to reload them into. Perhaps
4593 reusing reload regs from previous insns, or else output
4594 load insns to reload them. Maybe output store insns too.
4595 Record the choices of reload reg in reload_reg_rtx. */
4596 choose_reload_regs (chain);
4598 /* Generate the insns to reload operands into or out of
4599 their reload regs. */
4600 emit_reload_insns (chain);
4602 /* Substitute the chosen reload regs from reload_reg_rtx
4603 into the insn's body (or perhaps into the bodies of other
4604 load and store insn that we just made for reloading
4605 and that we moved the structure into). */
4606 subst_reloads (insn);
4608 /* Adjust the exception region notes for loads and stores. */
4609 if (cfun->can_throw_non_call_exceptions && !CALL_P (insn))
4610 fixup_eh_region_note (insn, prev, next);
4612 /* If this was an ASM, make sure that all the reload insns
4613 we have generated are valid. If not, give an error
4615 if (asm_noperands (PATTERN (insn)) >= 0)
4616 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4617 if (p != insn && INSN_P (p)
4618 && GET_CODE (PATTERN (p)) != USE
4619 && (recog_memoized (p) < 0
4620 || (extract_insn (p), ! constrain_operands (1))))
4622 error_for_asm (insn,
4623 "%<asm%> operand requires "
4624 "impossible reload");
4629 if (num_eliminable && chain->need_elim)
4630 update_eliminable_offsets ();
4632 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4633 is no longer validly lying around to save a future reload.
4634 Note that this does not detect pseudos that were reloaded
4635 for this insn in order to be stored in
4636 (obeying register constraints). That is correct; such reload
4637 registers ARE still valid. */
4638 forget_marked_reloads (®s_to_forget);
4639 CLEAR_REG_SET (®s_to_forget);
4641 /* There may have been CLOBBER insns placed after INSN. So scan
4642 between INSN and NEXT and use them to forget old reloads. */
4643 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4644 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4645 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4648 /* Likewise for regs altered by auto-increment in this insn.
4649 REG_INC notes have been changed by reloading:
4650 find_reloads_address_1 records substitutions for them,
4651 which have been performed by subst_reloads above. */
4652 for (i = n_reloads - 1; i >= 0; i--)
4654 rtx in_reg = rld[i].in_reg;
4657 enum rtx_code code = GET_CODE (in_reg);
4658 /* PRE_INC / PRE_DEC will have the reload register ending up
4659 with the same value as the stack slot, but that doesn't
4660 hold true for POST_INC / POST_DEC. Either we have to
4661 convert the memory access to a true POST_INC / POST_DEC,
4662 or we can't use the reload register for inheritance. */
4663 if ((code == POST_INC || code == POST_DEC)
4664 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4665 REGNO (rld[i].reg_rtx))
4666 /* Make sure it is the inc/dec pseudo, and not
4667 some other (e.g. output operand) pseudo. */
4668 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4669 == REGNO (XEXP (in_reg, 0))))
4672 rtx reload_reg = rld[i].reg_rtx;
4673 enum machine_mode mode = GET_MODE (reload_reg);
4677 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4679 /* We really want to ignore REG_INC notes here, so
4680 use PATTERN (p) as argument to reg_set_p . */
4681 if (reg_set_p (reload_reg, PATTERN (p)))
4683 n = count_occurrences (PATTERN (p), reload_reg, 0);
4689 = gen_rtx_fmt_e (code, mode, reload_reg);
4691 validate_replace_rtx_group (reload_reg,
4693 n = verify_changes (0);
4695 /* We must also verify that the constraints
4696 are met after the replacement. Make sure
4697 extract_insn is only called for an insn
4698 where the replacements were found to be
4703 n = constrain_operands (1);
4706 /* If the constraints were not met, then
4707 undo the replacement, else confirm it. */
4711 confirm_change_group ();
4717 add_reg_note (p, REG_INC, reload_reg);
4718 /* Mark this as having an output reload so that the
4719 REG_INC processing code below won't invalidate
4720 the reload for inheritance. */
4721 SET_HARD_REG_BIT (reg_is_output_reload,
4722 REGNO (reload_reg));
4723 SET_REGNO_REG_SET (®_has_output_reload,
4724 REGNO (XEXP (in_reg, 0)));
4727 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4730 else if ((code == PRE_INC || code == PRE_DEC)
4731 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4732 REGNO (rld[i].reg_rtx))
4733 /* Make sure it is the inc/dec pseudo, and not
4734 some other (e.g. output operand) pseudo. */
4735 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4736 == REGNO (XEXP (in_reg, 0))))
4738 SET_HARD_REG_BIT (reg_is_output_reload,
4739 REGNO (rld[i].reg_rtx));
4740 SET_REGNO_REG_SET (®_has_output_reload,
4741 REGNO (XEXP (in_reg, 0)));
4743 else if (code == PRE_INC || code == PRE_DEC
4744 || code == POST_INC || code == POST_DEC)
4746 int in_regno = REGNO (XEXP (in_reg, 0));
4748 if (reg_last_reload_reg[in_regno] != NULL_RTX)
4751 bool forget_p = true;
4753 in_hard_regno = REGNO (reg_last_reload_reg[in_regno]);
4754 if (TEST_HARD_REG_BIT (reg_reloaded_valid,
4757 for (x = old_prev ? NEXT_INSN (old_prev) : insn;
4760 if (x == reg_reloaded_insn[in_hard_regno])
4766 /* If for some reasons, we didn't set up
4767 reg_last_reload_reg in this insn,
4768 invalidate inheritance from previous
4769 insns for the incremented/decremented
4770 register. Such registers will be not in
4771 reg_has_output_reload. Invalidate it
4772 also if the corresponding element in
4773 reg_reloaded_insn is also
4776 forget_old_reloads_1 (XEXP (in_reg, 0),
4782 /* If a pseudo that got a hard register is auto-incremented,
4783 we must purge records of copying it into pseudos without
4785 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4786 if (REG_NOTE_KIND (x) == REG_INC)
4788 /* See if this pseudo reg was reloaded in this insn.
4789 If so, its last-reload info is still valid
4790 because it is based on this insn's reload. */
4791 for (i = 0; i < n_reloads; i++)
4792 if (rld[i].out == XEXP (x, 0))
4796 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4800 /* A reload reg's contents are unknown after a label. */
4802 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4804 /* Don't assume a reload reg is still good after a call insn
4805 if it is a call-used reg, or if it contains a value that will
4806 be partially clobbered by the call. */
4807 else if (CALL_P (insn))
4809 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4810 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4815 free (reg_last_reload_reg);
4816 CLEAR_REG_SET (®_has_output_reload);
4819 /* Discard all record of any value reloaded from X,
4820 or reloaded in X from someplace else;
4821 unless X is an output reload reg of the current insn.
4823 X may be a hard reg (the reload reg)
4824 or it may be a pseudo reg that was reloaded from.
4826 When DATA is non-NULL just mark the registers in regset
4827 to be forgotten later. */
4830 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4835 regset regs = (regset) data;
4837 /* note_stores does give us subregs of hard regs,
4838 subreg_regno_offset requires a hard reg. */
4839 while (GET_CODE (x) == SUBREG)
4841 /* We ignore the subreg offset when calculating the regno,
4842 because we are using the entire underlying hard register
4852 if (regno >= FIRST_PSEUDO_REGISTER)
4858 nr = hard_regno_nregs[regno][GET_MODE (x)];
4859 /* Storing into a spilled-reg invalidates its contents.
4860 This can happen if a block-local pseudo is allocated to that reg
4861 and it wasn't spilled because this block's total need is 0.
4862 Then some insn might have an optional reload and use this reg. */
4864 for (i = 0; i < nr; i++)
4865 /* But don't do this if the reg actually serves as an output
4866 reload reg in the current instruction. */
4868 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4870 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4871 spill_reg_store[regno + i] = 0;
4877 SET_REGNO_REG_SET (regs, regno + nr);
4880 /* Since value of X has changed,
4881 forget any value previously copied from it. */
4884 /* But don't forget a copy if this is the output reload
4885 that establishes the copy's validity. */
4887 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4888 reg_last_reload_reg[regno + nr] = 0;
4892 /* Forget the reloads marked in regset by previous function. */
4894 forget_marked_reloads (regset regs)
4897 reg_set_iterator rsi;
4898 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4900 if (reg < FIRST_PSEUDO_REGISTER
4901 /* But don't do this if the reg actually serves as an output
4902 reload reg in the current instruction. */
4904 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4906 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4907 spill_reg_store[reg] = 0;
4910 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4911 reg_last_reload_reg[reg] = 0;
4915 /* The following HARD_REG_SETs indicate when each hard register is
4916 used for a reload of various parts of the current insn. */
4918 /* If reg is unavailable for all reloads. */
4919 static HARD_REG_SET reload_reg_unavailable;
4920 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4921 static HARD_REG_SET reload_reg_used;
4922 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4923 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4924 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4925 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4926 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4927 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4928 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4929 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4930 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4931 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4932 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4933 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4934 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4935 static HARD_REG_SET reload_reg_used_in_op_addr;
4936 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4937 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4938 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4939 static HARD_REG_SET reload_reg_used_in_insn;
4940 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4941 static HARD_REG_SET reload_reg_used_in_other_addr;
4943 /* If reg is in use as a reload reg for any sort of reload. */
4944 static HARD_REG_SET reload_reg_used_at_all;
4946 /* If reg is use as an inherited reload. We just mark the first register
4948 static HARD_REG_SET reload_reg_used_for_inherit;
4950 /* Records which hard regs are used in any way, either as explicit use or
4951 by being allocated to a pseudo during any point of the current insn. */
4952 static HARD_REG_SET reg_used_in_insn;
4954 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4955 TYPE. MODE is used to indicate how many consecutive regs are
4959 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4960 enum machine_mode mode)
4962 unsigned int nregs = hard_regno_nregs[regno][mode];
4965 for (i = regno; i < nregs + regno; i++)
4970 SET_HARD_REG_BIT (reload_reg_used, i);
4973 case RELOAD_FOR_INPUT_ADDRESS:
4974 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4977 case RELOAD_FOR_INPADDR_ADDRESS:
4978 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4981 case RELOAD_FOR_OUTPUT_ADDRESS:
4982 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4985 case RELOAD_FOR_OUTADDR_ADDRESS:
4986 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4989 case RELOAD_FOR_OPERAND_ADDRESS:
4990 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4993 case RELOAD_FOR_OPADDR_ADDR:
4994 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4997 case RELOAD_FOR_OTHER_ADDRESS:
4998 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
5001 case RELOAD_FOR_INPUT:
5002 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
5005 case RELOAD_FOR_OUTPUT:
5006 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
5009 case RELOAD_FOR_INSN:
5010 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
5014 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
5018 /* Similarly, but show REGNO is no longer in use for a reload. */
5021 clear_reload_reg_in_use (unsigned int regno, int opnum,
5022 enum reload_type type, enum machine_mode mode)
5024 unsigned int nregs = hard_regno_nregs[regno][mode];
5025 unsigned int start_regno, end_regno, r;
5027 /* A complication is that for some reload types, inheritance might
5028 allow multiple reloads of the same types to share a reload register.
5029 We set check_opnum if we have to check only reloads with the same
5030 operand number, and check_any if we have to check all reloads. */
5031 int check_opnum = 0;
5033 HARD_REG_SET *used_in_set;
5038 used_in_set = &reload_reg_used;
5041 case RELOAD_FOR_INPUT_ADDRESS:
5042 used_in_set = &reload_reg_used_in_input_addr[opnum];
5045 case RELOAD_FOR_INPADDR_ADDRESS:
5047 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
5050 case RELOAD_FOR_OUTPUT_ADDRESS:
5051 used_in_set = &reload_reg_used_in_output_addr[opnum];
5054 case RELOAD_FOR_OUTADDR_ADDRESS:
5056 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
5059 case RELOAD_FOR_OPERAND_ADDRESS:
5060 used_in_set = &reload_reg_used_in_op_addr;
5063 case RELOAD_FOR_OPADDR_ADDR:
5065 used_in_set = &reload_reg_used_in_op_addr_reload;
5068 case RELOAD_FOR_OTHER_ADDRESS:
5069 used_in_set = &reload_reg_used_in_other_addr;
5073 case RELOAD_FOR_INPUT:
5074 used_in_set = &reload_reg_used_in_input[opnum];
5077 case RELOAD_FOR_OUTPUT:
5078 used_in_set = &reload_reg_used_in_output[opnum];
5081 case RELOAD_FOR_INSN:
5082 used_in_set = &reload_reg_used_in_insn;
5087 /* We resolve conflicts with remaining reloads of the same type by
5088 excluding the intervals of reload registers by them from the
5089 interval of freed reload registers. Since we only keep track of
5090 one set of interval bounds, we might have to exclude somewhat
5091 more than what would be necessary if we used a HARD_REG_SET here.
5092 But this should only happen very infrequently, so there should
5093 be no reason to worry about it. */
5095 start_regno = regno;
5096 end_regno = regno + nregs;
5097 if (check_opnum || check_any)
5099 for (i = n_reloads - 1; i >= 0; i--)
5101 if (rld[i].when_needed == type
5102 && (check_any || rld[i].opnum == opnum)
5105 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
5106 unsigned int conflict_end
5107 = end_hard_regno (rld[i].mode, conflict_start);
5109 /* If there is an overlap with the first to-be-freed register,
5110 adjust the interval start. */
5111 if (conflict_start <= start_regno && conflict_end > start_regno)
5112 start_regno = conflict_end;
5113 /* Otherwise, if there is a conflict with one of the other
5114 to-be-freed registers, adjust the interval end. */
5115 if (conflict_start > start_regno && conflict_start < end_regno)
5116 end_regno = conflict_start;
5121 for (r = start_regno; r < end_regno; r++)
5122 CLEAR_HARD_REG_BIT (*used_in_set, r);
5125 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5126 specified by OPNUM and TYPE. */
5129 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
5133 /* In use for a RELOAD_OTHER means it's not available for anything. */
5134 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
5135 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5141 /* In use for anything means we can't use it for RELOAD_OTHER. */
5142 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
5143 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5144 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5145 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5148 for (i = 0; i < reload_n_operands; i++)
5149 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5150 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5151 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5152 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5153 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5154 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5159 case RELOAD_FOR_INPUT:
5160 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5161 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
5164 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5167 /* If it is used for some other input, can't use it. */
5168 for (i = 0; i < reload_n_operands; i++)
5169 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5172 /* If it is used in a later operand's address, can't use it. */
5173 for (i = opnum + 1; i < reload_n_operands; i++)
5174 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5175 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5180 case RELOAD_FOR_INPUT_ADDRESS:
5181 /* Can't use a register if it is used for an input address for this
5182 operand or used as an input in an earlier one. */
5183 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
5184 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5187 for (i = 0; i < opnum; i++)
5188 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5193 case RELOAD_FOR_INPADDR_ADDRESS:
5194 /* Can't use a register if it is used for an input address
5195 for this operand or used as an input in an earlier
5197 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5200 for (i = 0; i < opnum; i++)
5201 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5206 case RELOAD_FOR_OUTPUT_ADDRESS:
5207 /* Can't use a register if it is used for an output address for this
5208 operand or used as an output in this or a later operand. Note
5209 that multiple output operands are emitted in reverse order, so
5210 the conflicting ones are those with lower indices. */
5211 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
5214 for (i = 0; i <= opnum; i++)
5215 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5220 case RELOAD_FOR_OUTADDR_ADDRESS:
5221 /* Can't use a register if it is used for an output address
5222 for this operand or used as an output in this or a
5223 later operand. Note that multiple output operands are
5224 emitted in reverse order, so the conflicting ones are
5225 those with lower indices. */
5226 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5229 for (i = 0; i <= opnum; i++)
5230 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5235 case RELOAD_FOR_OPERAND_ADDRESS:
5236 for (i = 0; i < reload_n_operands; i++)
5237 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5240 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5241 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5243 case RELOAD_FOR_OPADDR_ADDR:
5244 for (i = 0; i < reload_n_operands; i++)
5245 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5248 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
5250 case RELOAD_FOR_OUTPUT:
5251 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5252 outputs, or an operand address for this or an earlier output.
5253 Note that multiple output operands are emitted in reverse order,
5254 so the conflicting ones are those with higher indices. */
5255 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5258 for (i = 0; i < reload_n_operands; i++)
5259 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5262 for (i = opnum; i < reload_n_operands; i++)
5263 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5264 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5269 case RELOAD_FOR_INSN:
5270 for (i = 0; i < reload_n_operands; i++)
5271 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5272 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5275 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5276 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5278 case RELOAD_FOR_OTHER_ADDRESS:
5279 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
5286 /* Return 1 if the value in reload reg REGNO, as used by a reload
5287 needed for the part of the insn specified by OPNUM and TYPE,
5288 is still available in REGNO at the end of the insn.
5290 We can assume that the reload reg was already tested for availability
5291 at the time it is needed, and we should not check this again,
5292 in case the reg has already been marked in use. */
5295 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
5302 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5303 its value must reach the end. */
5306 /* If this use is for part of the insn,
5307 its value reaches if no subsequent part uses the same register.
5308 Just like the above function, don't try to do this with lots
5311 case RELOAD_FOR_OTHER_ADDRESS:
5312 /* Here we check for everything else, since these don't conflict
5313 with anything else and everything comes later. */
5315 for (i = 0; i < reload_n_operands; i++)
5316 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5317 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5318 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
5319 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5320 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5321 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5324 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5325 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5326 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5327 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
5329 case RELOAD_FOR_INPUT_ADDRESS:
5330 case RELOAD_FOR_INPADDR_ADDRESS:
5331 /* Similar, except that we check only for this and subsequent inputs
5332 and the address of only subsequent inputs and we do not need
5333 to check for RELOAD_OTHER objects since they are known not to
5336 for (i = opnum; i < reload_n_operands; i++)
5337 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5340 for (i = opnum + 1; i < reload_n_operands; i++)
5341 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5342 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5345 for (i = 0; i < reload_n_operands; i++)
5346 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5347 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5348 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5351 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5354 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5355 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5356 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5358 case RELOAD_FOR_INPUT:
5359 /* Similar to input address, except we start at the next operand for
5360 both input and input address and we do not check for
5361 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5364 for (i = opnum + 1; i < reload_n_operands; i++)
5365 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5366 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5367 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5370 /* ... fall through ... */
5372 case RELOAD_FOR_OPERAND_ADDRESS:
5373 /* Check outputs and their addresses. */
5375 for (i = 0; i < reload_n_operands; i++)
5376 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5377 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5378 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5381 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5383 case RELOAD_FOR_OPADDR_ADDR:
5384 for (i = 0; i < reload_n_operands; i++)
5385 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5386 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5387 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5390 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5391 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5392 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5394 case RELOAD_FOR_INSN:
5395 /* These conflict with other outputs with RELOAD_OTHER. So
5396 we need only check for output addresses. */
5398 opnum = reload_n_operands;
5400 /* ... fall through ... */
5402 case RELOAD_FOR_OUTPUT:
5403 case RELOAD_FOR_OUTPUT_ADDRESS:
5404 case RELOAD_FOR_OUTADDR_ADDRESS:
5405 /* We already know these can't conflict with a later output. So the
5406 only thing to check are later output addresses.
5407 Note that multiple output operands are emitted in reverse order,
5408 so the conflicting ones are those with lower indices. */
5409 for (i = 0; i < opnum; i++)
5410 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5411 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5421 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5422 every register in the range [REGNO, REGNO + NREGS). */
5425 reload_regs_reach_end_p (unsigned int regno, int nregs,
5426 int opnum, enum reload_type type)
5430 for (i = 0; i < nregs; i++)
5431 if (!reload_reg_reaches_end_p (regno + i, opnum, type))
5437 /* Returns whether R1 and R2 are uniquely chained: the value of one
5438 is used by the other, and that value is not used by any other
5439 reload for this insn. This is used to partially undo the decision
5440 made in find_reloads when in the case of multiple
5441 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5442 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5443 reloads. This code tries to avoid the conflict created by that
5444 change. It might be cleaner to explicitly keep track of which
5445 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5446 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5447 this after the fact. */
5449 reloads_unique_chain_p (int r1, int r2)
5453 /* We only check input reloads. */
5454 if (! rld[r1].in || ! rld[r2].in)
5457 /* Avoid anything with output reloads. */
5458 if (rld[r1].out || rld[r2].out)
5461 /* "chained" means one reload is a component of the other reload,
5462 not the same as the other reload. */
5463 if (rld[r1].opnum != rld[r2].opnum
5464 || rtx_equal_p (rld[r1].in, rld[r2].in)
5465 || rld[r1].optional || rld[r2].optional
5466 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5467 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5470 for (i = 0; i < n_reloads; i ++)
5471 /* Look for input reloads that aren't our two */
5472 if (i != r1 && i != r2 && rld[i].in)
5474 /* If our reload is mentioned at all, it isn't a simple chain. */
5475 if (reg_mentioned_p (rld[r1].in, rld[i].in))
5481 /* The recursive function change all occurrences of WHAT in *WHERE
5484 substitute (rtx *where, const_rtx what, rtx repl)
5493 if (*where == what || rtx_equal_p (*where, what))
5495 /* Record the location of the changed rtx. */
5496 VEC_safe_push (rtx_p, heap, substitute_stack, where);
5501 code = GET_CODE (*where);
5502 fmt = GET_RTX_FORMAT (code);
5503 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5509 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5510 substitute (&XVECEXP (*where, i, j), what, repl);
5512 else if (fmt[i] == 'e')
5513 substitute (&XEXP (*where, i), what, repl);
5517 /* The function returns TRUE if chain of reload R1 and R2 (in any
5518 order) can be evaluated without usage of intermediate register for
5519 the reload containing another reload. It is important to see
5520 gen_reload to understand what the function is trying to do. As an
5521 example, let us have reload chain
5524 r1: <something> + const
5526 and reload R2 got reload reg HR. The function returns true if
5527 there is a correct insn HR = HR + <something>. Otherwise,
5528 gen_reload will use intermediate register (and this is the reload
5529 reg for R1) to reload <something>.
5531 We need this function to find a conflict for chain reloads. In our
5532 example, if HR = HR + <something> is incorrect insn, then we cannot
5533 use HR as a reload register for R2. If we do use it then we get a
5542 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5544 /* Assume other cases in gen_reload are not possible for
5545 chain reloads or do need an intermediate hard registers. */
5548 rtx out, in, tem, insn;
5549 rtx last = get_last_insn ();
5551 /* Make r2 a component of r1. */
5552 if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5558 gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5559 regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5560 gcc_assert (regno >= 0);
5561 out = gen_rtx_REG (rld[r1].mode, regno);
5563 substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5565 /* If IN is a paradoxical SUBREG, remove it and try to put the
5566 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5567 if (GET_CODE (in) == SUBREG
5568 && (GET_MODE_SIZE (GET_MODE (in))
5569 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
5570 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
5571 in = SUBREG_REG (in), out = tem;
5573 if (GET_CODE (in) == PLUS
5574 && (REG_P (XEXP (in, 0))
5575 || GET_CODE (XEXP (in, 0)) == SUBREG
5576 || MEM_P (XEXP (in, 0)))
5577 && (REG_P (XEXP (in, 1))
5578 || GET_CODE (XEXP (in, 1)) == SUBREG
5579 || CONSTANT_P (XEXP (in, 1))
5580 || MEM_P (XEXP (in, 1))))
5582 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
5583 code = recog_memoized (insn);
5588 extract_insn (insn);
5589 /* We want constrain operands to treat this insn strictly in
5590 its validity determination, i.e., the way it would after
5591 reload has completed. */
5592 result = constrain_operands (1);
5595 delete_insns_since (last);
5598 /* Restore the original value at each changed address within R1. */
5599 while (!VEC_empty (rtx_p, substitute_stack))
5601 rtx *where = VEC_pop (rtx_p, substitute_stack);
5602 *where = rld[r2].in;
5608 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5611 This function uses the same algorithm as reload_reg_free_p above. */
5614 reloads_conflict (int r1, int r2)
5616 enum reload_type r1_type = rld[r1].when_needed;
5617 enum reload_type r2_type = rld[r2].when_needed;
5618 int r1_opnum = rld[r1].opnum;
5619 int r2_opnum = rld[r2].opnum;
5621 /* RELOAD_OTHER conflicts with everything. */
5622 if (r2_type == RELOAD_OTHER)
5625 /* Otherwise, check conflicts differently for each type. */
5629 case RELOAD_FOR_INPUT:
5630 return (r2_type == RELOAD_FOR_INSN
5631 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5632 || r2_type == RELOAD_FOR_OPADDR_ADDR
5633 || r2_type == RELOAD_FOR_INPUT
5634 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5635 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5636 && r2_opnum > r1_opnum));
5638 case RELOAD_FOR_INPUT_ADDRESS:
5639 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5640 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5642 case RELOAD_FOR_INPADDR_ADDRESS:
5643 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5644 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5646 case RELOAD_FOR_OUTPUT_ADDRESS:
5647 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5648 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5650 case RELOAD_FOR_OUTADDR_ADDRESS:
5651 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5652 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5654 case RELOAD_FOR_OPERAND_ADDRESS:
5655 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5656 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5657 && (!reloads_unique_chain_p (r1, r2)
5658 || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5660 case RELOAD_FOR_OPADDR_ADDR:
5661 return (r2_type == RELOAD_FOR_INPUT
5662 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5664 case RELOAD_FOR_OUTPUT:
5665 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5666 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5667 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5668 && r2_opnum >= r1_opnum));
5670 case RELOAD_FOR_INSN:
5671 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5672 || r2_type == RELOAD_FOR_INSN
5673 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5675 case RELOAD_FOR_OTHER_ADDRESS:
5676 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5686 /* Indexed by reload number, 1 if incoming value
5687 inherited from previous insns. */
5688 static char reload_inherited[MAX_RELOADS];
5690 /* For an inherited reload, this is the insn the reload was inherited from,
5691 if we know it. Otherwise, this is 0. */
5692 static rtx reload_inheritance_insn[MAX_RELOADS];
5694 /* If nonzero, this is a place to get the value of the reload,
5695 rather than using reload_in. */
5696 static rtx reload_override_in[MAX_RELOADS];
5698 /* For each reload, the hard register number of the register used,
5699 or -1 if we did not need a register for this reload. */
5700 static int reload_spill_index[MAX_RELOADS];
5702 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5703 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5705 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5706 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5708 /* Subroutine of free_for_value_p, used to check a single register.
5709 START_REGNO is the starting regno of the full reload register
5710 (possibly comprising multiple hard registers) that we are considering. */
5713 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5714 enum reload_type type, rtx value, rtx out,
5715 int reloadnum, int ignore_address_reloads)
5718 /* Set if we see an input reload that must not share its reload register
5719 with any new earlyclobber, but might otherwise share the reload
5720 register with an output or input-output reload. */
5721 int check_earlyclobber = 0;
5725 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5728 if (out == const0_rtx)
5734 /* We use some pseudo 'time' value to check if the lifetimes of the
5735 new register use would overlap with the one of a previous reload
5736 that is not read-only or uses a different value.
5737 The 'time' used doesn't have to be linear in any shape or form, just
5739 Some reload types use different 'buckets' for each operand.
5740 So there are MAX_RECOG_OPERANDS different time values for each
5742 We compute TIME1 as the time when the register for the prospective
5743 new reload ceases to be live, and TIME2 for each existing
5744 reload as the time when that the reload register of that reload
5746 Where there is little to be gained by exact lifetime calculations,
5747 we just make conservative assumptions, i.e. a longer lifetime;
5748 this is done in the 'default:' cases. */
5751 case RELOAD_FOR_OTHER_ADDRESS:
5752 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5753 time1 = copy ? 0 : 1;
5756 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5758 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5759 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5760 respectively, to the time values for these, we get distinct time
5761 values. To get distinct time values for each operand, we have to
5762 multiply opnum by at least three. We round that up to four because
5763 multiply by four is often cheaper. */
5764 case RELOAD_FOR_INPADDR_ADDRESS:
5765 time1 = opnum * 4 + 2;
5767 case RELOAD_FOR_INPUT_ADDRESS:
5768 time1 = opnum * 4 + 3;
5770 case RELOAD_FOR_INPUT:
5771 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5772 executes (inclusive). */
5773 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5775 case RELOAD_FOR_OPADDR_ADDR:
5777 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5778 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5780 case RELOAD_FOR_OPERAND_ADDRESS:
5781 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5783 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5785 case RELOAD_FOR_OUTADDR_ADDRESS:
5786 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5788 case RELOAD_FOR_OUTPUT_ADDRESS:
5789 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5792 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5795 for (i = 0; i < n_reloads; i++)
5797 rtx reg = rld[i].reg_rtx;
5798 if (reg && REG_P (reg)
5799 && ((unsigned) regno - true_regnum (reg)
5800 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5803 rtx other_input = rld[i].in;
5805 /* If the other reload loads the same input value, that
5806 will not cause a conflict only if it's loading it into
5807 the same register. */
5808 if (true_regnum (reg) != start_regno)
5809 other_input = NULL_RTX;
5810 if (! other_input || ! rtx_equal_p (other_input, value)
5811 || rld[i].out || out)
5814 switch (rld[i].when_needed)
5816 case RELOAD_FOR_OTHER_ADDRESS:
5819 case RELOAD_FOR_INPADDR_ADDRESS:
5820 /* find_reloads makes sure that a
5821 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5822 by at most one - the first -
5823 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5824 address reload is inherited, the address address reload
5825 goes away, so we can ignore this conflict. */
5826 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5827 && ignore_address_reloads
5828 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5829 Then the address address is still needed to store
5830 back the new address. */
5831 && ! rld[reloadnum].out)
5833 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5834 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5836 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5837 && ignore_address_reloads
5838 /* Unless we are reloading an auto_inc expression. */
5839 && ! rld[reloadnum].out)
5841 time2 = rld[i].opnum * 4 + 2;
5843 case RELOAD_FOR_INPUT_ADDRESS:
5844 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5845 && ignore_address_reloads
5846 && ! rld[reloadnum].out)
5848 time2 = rld[i].opnum * 4 + 3;
5850 case RELOAD_FOR_INPUT:
5851 time2 = rld[i].opnum * 4 + 4;
5852 check_earlyclobber = 1;
5854 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5855 == MAX_RECOG_OPERAND * 4 */
5856 case RELOAD_FOR_OPADDR_ADDR:
5857 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5858 && ignore_address_reloads
5859 && ! rld[reloadnum].out)
5861 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5863 case RELOAD_FOR_OPERAND_ADDRESS:
5864 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5865 check_earlyclobber = 1;
5867 case RELOAD_FOR_INSN:
5868 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5870 case RELOAD_FOR_OUTPUT:
5871 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5872 instruction is executed. */
5873 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5875 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5876 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5878 case RELOAD_FOR_OUTADDR_ADDRESS:
5879 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5880 && ignore_address_reloads
5881 && ! rld[reloadnum].out)
5883 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5885 case RELOAD_FOR_OUTPUT_ADDRESS:
5886 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5889 /* If there is no conflict in the input part, handle this
5890 like an output reload. */
5891 if (! rld[i].in || rtx_equal_p (other_input, value))
5893 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5894 /* Earlyclobbered outputs must conflict with inputs. */
5895 if (earlyclobber_operand_p (rld[i].out))
5896 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5901 /* RELOAD_OTHER might be live beyond instruction execution,
5902 but this is not obvious when we set time2 = 1. So check
5903 here if there might be a problem with the new reload
5904 clobbering the register used by the RELOAD_OTHER. */
5912 && (! rld[i].in || rld[i].out
5913 || ! rtx_equal_p (other_input, value)))
5914 || (out && rld[reloadnum].out_reg
5915 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5921 /* Earlyclobbered outputs must conflict with inputs. */
5922 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5928 /* Return 1 if the value in reload reg REGNO, as used by a reload
5929 needed for the part of the insn specified by OPNUM and TYPE,
5930 may be used to load VALUE into it.
5932 MODE is the mode in which the register is used, this is needed to
5933 determine how many hard regs to test.
5935 Other read-only reloads with the same value do not conflict
5936 unless OUT is nonzero and these other reloads have to live while
5937 output reloads live.
5938 If OUT is CONST0_RTX, this is a special case: it means that the
5939 test should not be for using register REGNO as reload register, but
5940 for copying from register REGNO into the reload register.
5942 RELOADNUM is the number of the reload we want to load this value for;
5943 a reload does not conflict with itself.
5945 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5946 reloads that load an address for the very reload we are considering.
5948 The caller has to make sure that there is no conflict with the return
5952 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5953 enum reload_type type, rtx value, rtx out, int reloadnum,
5954 int ignore_address_reloads)
5956 int nregs = hard_regno_nregs[regno][mode];
5958 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5959 value, out, reloadnum,
5960 ignore_address_reloads))
5965 /* Return nonzero if the rtx X is invariant over the current function. */
5966 /* ??? Actually, the places where we use this expect exactly what is
5967 tested here, and not everything that is function invariant. In
5968 particular, the frame pointer and arg pointer are special cased;
5969 pic_offset_table_rtx is not, and we must not spill these things to
5973 function_invariant_p (const_rtx x)
5977 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5979 if (GET_CODE (x) == PLUS
5980 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5981 && GET_CODE (XEXP (x, 1)) == CONST_INT)
5986 /* Determine whether the reload reg X overlaps any rtx'es used for
5987 overriding inheritance. Return nonzero if so. */
5990 conflicts_with_override (rtx x)
5993 for (i = 0; i < n_reloads; i++)
5994 if (reload_override_in[i]
5995 && reg_overlap_mentioned_p (x, reload_override_in[i]))
6000 /* Give an error message saying we failed to find a reload for INSN,
6001 and clear out reload R. */
6003 failed_reload (rtx insn, int r)
6005 if (asm_noperands (PATTERN (insn)) < 0)
6006 /* It's the compiler's fault. */
6007 fatal_insn ("could not find a spill register", insn);
6009 /* It's the user's fault; the operand's mode and constraint
6010 don't match. Disable this reload so we don't crash in final. */
6011 error_for_asm (insn,
6012 "%<asm%> operand constraint incompatible with operand size");
6016 rld[r].optional = 1;
6017 rld[r].secondary_p = 1;
6020 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6021 for reload R. If it's valid, get an rtx for it. Return nonzero if
6024 set_reload_reg (int i, int r)
6027 rtx reg = spill_reg_rtx[i];
6029 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
6030 spill_reg_rtx[i] = reg
6031 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
6033 regno = true_regnum (reg);
6035 /* Detect when the reload reg can't hold the reload mode.
6036 This used to be one `if', but Sequent compiler can't handle that. */
6037 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
6039 enum machine_mode test_mode = VOIDmode;
6041 test_mode = GET_MODE (rld[r].in);
6042 /* If rld[r].in has VOIDmode, it means we will load it
6043 in whatever mode the reload reg has: to wit, rld[r].mode.
6044 We have already tested that for validity. */
6045 /* Aside from that, we need to test that the expressions
6046 to reload from or into have modes which are valid for this
6047 reload register. Otherwise the reload insns would be invalid. */
6048 if (! (rld[r].in != 0 && test_mode != VOIDmode
6049 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
6050 if (! (rld[r].out != 0
6051 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
6053 /* The reg is OK. */
6056 /* Mark as in use for this insn the reload regs we use
6058 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
6059 rld[r].when_needed, rld[r].mode);
6061 rld[r].reg_rtx = reg;
6062 reload_spill_index[r] = spill_regs[i];
6069 /* Find a spill register to use as a reload register for reload R.
6070 LAST_RELOAD is nonzero if this is the last reload for the insn being
6073 Set rld[R].reg_rtx to the register allocated.
6075 We return 1 if successful, or 0 if we couldn't find a spill reg and
6076 we didn't change anything. */
6079 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
6084 /* If we put this reload ahead, thinking it is a group,
6085 then insist on finding a group. Otherwise we can grab a
6086 reg that some other reload needs.
6087 (That can happen when we have a 68000 DATA_OR_FP_REG
6088 which is a group of data regs or one fp reg.)
6089 We need not be so restrictive if there are no more reloads
6092 ??? Really it would be nicer to have smarter handling
6093 for that kind of reg class, where a problem like this is normal.
6094 Perhaps those classes should be avoided for reloading
6095 by use of more alternatives. */
6097 int force_group = rld[r].nregs > 1 && ! last_reload;
6099 /* If we want a single register and haven't yet found one,
6100 take any reg in the right class and not in use.
6101 If we want a consecutive group, here is where we look for it.
6103 We use three passes so we can first look for reload regs to
6104 reuse, which are already in use for other reloads in this insn,
6105 and only then use additional registers which are not "bad", then
6106 finally any register.
6108 I think that maximizing reuse is needed to make sure we don't
6109 run out of reload regs. Suppose we have three reloads, and
6110 reloads A and B can share regs. These need two regs.
6111 Suppose A and B are given different regs.
6112 That leaves none for C. */
6113 for (pass = 0; pass < 3; pass++)
6115 /* I is the index in spill_regs.
6116 We advance it round-robin between insns to use all spill regs
6117 equally, so that inherited reloads have a chance
6118 of leapfrogging each other. */
6122 for (count = 0; count < n_spills; count++)
6124 int rclass = (int) rld[r].rclass;
6130 regnum = spill_regs[i];
6132 if ((reload_reg_free_p (regnum, rld[r].opnum,
6135 /* We check reload_reg_used to make sure we
6136 don't clobber the return register. */
6137 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
6138 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
6139 rld[r].when_needed, rld[r].in,
6141 && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
6142 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
6143 /* Look first for regs to share, then for unshared. But
6144 don't share regs used for inherited reloads; they are
6145 the ones we want to preserve. */
6147 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
6149 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
6152 int nr = hard_regno_nregs[regnum][rld[r].mode];
6154 /* During the second pass we want to avoid reload registers
6155 which are "bad" for this reload. */
6157 && ira_bad_reload_regno (regnum, rld[r].in, rld[r].out))
6160 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6161 (on 68000) got us two FP regs. If NR is 1,
6162 we would reject both of them. */
6165 /* If we need only one reg, we have already won. */
6168 /* But reject a single reg if we demand a group. */
6173 /* Otherwise check that as many consecutive regs as we need
6174 are available here. */
6177 int regno = regnum + nr - 1;
6178 if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
6179 && spill_reg_order[regno] >= 0
6180 && reload_reg_free_p (regno, rld[r].opnum,
6181 rld[r].when_needed)))
6190 /* If we found something on the current pass, omit later passes. */
6191 if (count < n_spills)
6195 /* We should have found a spill register by now. */
6196 if (count >= n_spills)
6199 /* I is the index in SPILL_REG_RTX of the reload register we are to
6200 allocate. Get an rtx for it and find its register number. */
6202 return set_reload_reg (i, r);
6205 /* Initialize all the tables needed to allocate reload registers.
6206 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6207 is the array we use to restore the reg_rtx field for every reload. */
6210 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
6214 for (i = 0; i < n_reloads; i++)
6215 rld[i].reg_rtx = save_reload_reg_rtx[i];
6217 memset (reload_inherited, 0, MAX_RELOADS);
6218 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
6219 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
6221 CLEAR_HARD_REG_SET (reload_reg_used);
6222 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
6223 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
6224 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
6225 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
6226 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
6228 CLEAR_HARD_REG_SET (reg_used_in_insn);
6231 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
6232 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6233 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
6234 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6235 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
6236 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
6239 for (i = 0; i < reload_n_operands; i++)
6241 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
6242 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
6243 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
6244 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
6245 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
6246 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
6249 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
6251 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
6253 for (i = 0; i < n_reloads; i++)
6254 /* If we have already decided to use a certain register,
6255 don't use it in another way. */
6257 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
6258 rld[i].when_needed, rld[i].mode);
6261 /* Assign hard reg targets for the pseudo-registers we must reload
6262 into hard regs for this insn.
6263 Also output the instructions to copy them in and out of the hard regs.
6265 For machines with register classes, we are responsible for
6266 finding a reload reg in the proper class. */
6269 choose_reload_regs (struct insn_chain *chain)
6271 rtx insn = chain->insn;
6273 unsigned int max_group_size = 1;
6274 enum reg_class group_class = NO_REGS;
6275 int pass, win, inheritance;
6277 rtx save_reload_reg_rtx[MAX_RELOADS];
6279 /* In order to be certain of getting the registers we need,
6280 we must sort the reloads into order of increasing register class.
6281 Then our grabbing of reload registers will parallel the process
6282 that provided the reload registers.
6284 Also note whether any of the reloads wants a consecutive group of regs.
6285 If so, record the maximum size of the group desired and what
6286 register class contains all the groups needed by this insn. */
6288 for (j = 0; j < n_reloads; j++)
6290 reload_order[j] = j;
6291 if (rld[j].reg_rtx != NULL_RTX)
6293 gcc_assert (REG_P (rld[j].reg_rtx)
6294 && HARD_REGISTER_P (rld[j].reg_rtx));
6295 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
6298 reload_spill_index[j] = -1;
6300 if (rld[j].nregs > 1)
6302 max_group_size = MAX (rld[j].nregs, max_group_size);
6304 = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
6307 save_reload_reg_rtx[j] = rld[j].reg_rtx;
6311 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
6313 /* If -O, try first with inheritance, then turning it off.
6314 If not -O, don't do inheritance.
6315 Using inheritance when not optimizing leads to paradoxes
6316 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6317 because one side of the comparison might be inherited. */
6319 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
6321 choose_reload_regs_init (chain, save_reload_reg_rtx);
6323 /* Process the reloads in order of preference just found.
6324 Beyond this point, subregs can be found in reload_reg_rtx.
6326 This used to look for an existing reloaded home for all of the
6327 reloads, and only then perform any new reloads. But that could lose
6328 if the reloads were done out of reg-class order because a later
6329 reload with a looser constraint might have an old home in a register
6330 needed by an earlier reload with a tighter constraint.
6332 To solve this, we make two passes over the reloads, in the order
6333 described above. In the first pass we try to inherit a reload
6334 from a previous insn. If there is a later reload that needs a
6335 class that is a proper subset of the class being processed, we must
6336 also allocate a spill register during the first pass.
6338 Then make a second pass over the reloads to allocate any reloads
6339 that haven't been given registers yet. */
6341 for (j = 0; j < n_reloads; j++)
6343 int r = reload_order[j];
6344 rtx search_equiv = NULL_RTX;
6346 /* Ignore reloads that got marked inoperative. */
6347 if (rld[r].out == 0 && rld[r].in == 0
6348 && ! rld[r].secondary_p)
6351 /* If find_reloads chose to use reload_in or reload_out as a reload
6352 register, we don't need to chose one. Otherwise, try even if it
6353 found one since we might save an insn if we find the value lying
6355 Try also when reload_in is a pseudo without a hard reg. */
6356 if (rld[r].in != 0 && rld[r].reg_rtx != 0
6357 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
6358 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
6359 && !MEM_P (rld[r].in)
6360 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
6363 #if 0 /* No longer needed for correct operation.
6364 It might give better code, or might not; worth an experiment? */
6365 /* If this is an optional reload, we can't inherit from earlier insns
6366 until we are sure that any non-optional reloads have been allocated.
6367 The following code takes advantage of the fact that optional reloads
6368 are at the end of reload_order. */
6369 if (rld[r].optional != 0)
6370 for (i = 0; i < j; i++)
6371 if ((rld[reload_order[i]].out != 0
6372 || rld[reload_order[i]].in != 0
6373 || rld[reload_order[i]].secondary_p)
6374 && ! rld[reload_order[i]].optional
6375 && rld[reload_order[i]].reg_rtx == 0)
6376 allocate_reload_reg (chain, reload_order[i], 0);
6379 /* First see if this pseudo is already available as reloaded
6380 for a previous insn. We cannot try to inherit for reloads
6381 that are smaller than the maximum number of registers needed
6382 for groups unless the register we would allocate cannot be used
6385 We could check here to see if this is a secondary reload for
6386 an object that is already in a register of the desired class.
6387 This would avoid the need for the secondary reload register.
6388 But this is complex because we can't easily determine what
6389 objects might want to be loaded via this reload. So let a
6390 register be allocated here. In `emit_reload_insns' we suppress
6391 one of the loads in the case described above. */
6397 enum machine_mode mode = VOIDmode;
6401 else if (REG_P (rld[r].in))
6403 regno = REGNO (rld[r].in);
6404 mode = GET_MODE (rld[r].in);
6406 else if (REG_P (rld[r].in_reg))
6408 regno = REGNO (rld[r].in_reg);
6409 mode = GET_MODE (rld[r].in_reg);
6411 else if (GET_CODE (rld[r].in_reg) == SUBREG
6412 && REG_P (SUBREG_REG (rld[r].in_reg)))
6414 regno = REGNO (SUBREG_REG (rld[r].in_reg));
6415 if (regno < FIRST_PSEUDO_REGISTER)
6416 regno = subreg_regno (rld[r].in_reg);
6418 byte = SUBREG_BYTE (rld[r].in_reg);
6419 mode = GET_MODE (rld[r].in_reg);
6422 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6423 && REG_P (XEXP (rld[r].in_reg, 0)))
6425 regno = REGNO (XEXP (rld[r].in_reg, 0));
6426 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6427 rld[r].out = rld[r].in;
6431 /* This won't work, since REGNO can be a pseudo reg number.
6432 Also, it takes much more hair to keep track of all the things
6433 that can invalidate an inherited reload of part of a pseudoreg. */
6434 else if (GET_CODE (rld[r].in) == SUBREG
6435 && REG_P (SUBREG_REG (rld[r].in)))
6436 regno = subreg_regno (rld[r].in);
6440 && reg_last_reload_reg[regno] != 0
6441 #ifdef CANNOT_CHANGE_MODE_CLASS
6442 /* Verify that the register it's in can be used in
6444 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
6445 GET_MODE (reg_last_reload_reg[regno]),
6450 enum reg_class rclass = rld[r].rclass, last_class;
6451 rtx last_reg = reg_last_reload_reg[regno];
6452 enum machine_mode need_mode;
6454 i = REGNO (last_reg);
6455 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6456 last_class = REGNO_REG_CLASS (i);
6462 = smallest_mode_for_size
6463 (GET_MODE_BITSIZE (mode) + byte * BITS_PER_UNIT,
6464 GET_MODE_CLASS (mode) == MODE_PARTIAL_INT
6465 ? MODE_INT : GET_MODE_CLASS (mode));
6467 if ((GET_MODE_SIZE (GET_MODE (last_reg))
6468 >= GET_MODE_SIZE (need_mode))
6469 && reg_reloaded_contents[i] == regno
6470 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6471 && HARD_REGNO_MODE_OK (i, rld[r].mode)
6472 && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6473 /* Even if we can't use this register as a reload
6474 register, we might use it for reload_override_in,
6475 if copying it to the desired class is cheap
6477 || ((register_move_cost (mode, last_class, rclass)
6478 < memory_move_cost (mode, rclass, true))
6479 && (secondary_reload_class (1, rclass, mode,
6482 #ifdef SECONDARY_MEMORY_NEEDED
6483 && ! SECONDARY_MEMORY_NEEDED (last_class, rclass,
6488 && (rld[r].nregs == max_group_size
6489 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6491 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6492 rld[r].when_needed, rld[r].in,
6495 /* If a group is needed, verify that all the subsequent
6496 registers still have their values intact. */
6497 int nr = hard_regno_nregs[i][rld[r].mode];
6500 for (k = 1; k < nr; k++)
6501 if (reg_reloaded_contents[i + k] != regno
6502 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6510 last_reg = (GET_MODE (last_reg) == mode
6511 ? last_reg : gen_rtx_REG (mode, i));
6514 for (k = 0; k < nr; k++)
6515 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6518 /* We found a register that contains the
6519 value we need. If this register is the
6520 same as an `earlyclobber' operand of the
6521 current insn, just mark it as a place to
6522 reload from since we can't use it as the
6523 reload register itself. */
6525 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6526 if (reg_overlap_mentioned_for_reload_p
6527 (reg_last_reload_reg[regno],
6528 reload_earlyclobbers[i1]))
6531 if (i1 != n_earlyclobbers
6532 || ! (free_for_value_p (i, rld[r].mode,
6534 rld[r].when_needed, rld[r].in,
6536 /* Don't use it if we'd clobber a pseudo reg. */
6537 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6539 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6540 /* Don't clobber the frame pointer. */
6541 || (i == HARD_FRAME_POINTER_REGNUM
6542 && frame_pointer_needed
6544 /* Don't really use the inherited spill reg
6545 if we need it wider than we've got it. */
6546 || (GET_MODE_SIZE (rld[r].mode)
6547 > GET_MODE_SIZE (mode))
6550 /* If find_reloads chose reload_out as reload
6551 register, stay with it - that leaves the
6552 inherited register for subsequent reloads. */
6553 || (rld[r].out && rld[r].reg_rtx
6554 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6556 if (! rld[r].optional)
6558 reload_override_in[r] = last_reg;
6559 reload_inheritance_insn[r]
6560 = reg_reloaded_insn[i];
6566 /* We can use this as a reload reg. */
6567 /* Mark the register as in use for this part of
6569 mark_reload_reg_in_use (i,
6573 rld[r].reg_rtx = last_reg;
6574 reload_inherited[r] = 1;
6575 reload_inheritance_insn[r]
6576 = reg_reloaded_insn[i];
6577 reload_spill_index[r] = i;
6578 for (k = 0; k < nr; k++)
6579 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6587 /* Here's another way to see if the value is already lying around. */
6590 && ! reload_inherited[r]
6592 && (CONSTANT_P (rld[r].in)
6593 || GET_CODE (rld[r].in) == PLUS
6594 || REG_P (rld[r].in)
6595 || MEM_P (rld[r].in))
6596 && (rld[r].nregs == max_group_size
6597 || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6598 search_equiv = rld[r].in;
6599 /* If this is an output reload from a simple move insn, look
6600 if an equivalence for the input is available. */
6601 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
6603 rtx set = single_set (insn);
6606 && rtx_equal_p (rld[r].out, SET_DEST (set))
6607 && CONSTANT_P (SET_SRC (set)))
6608 search_equiv = SET_SRC (set);
6614 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6615 -1, NULL, 0, rld[r].mode);
6621 regno = REGNO (equiv);
6624 /* This must be a SUBREG of a hard register.
6625 Make a new REG since this might be used in an
6626 address and not all machines support SUBREGs
6628 gcc_assert (GET_CODE (equiv) == SUBREG);
6629 regno = subreg_regno (equiv);
6630 equiv = gen_rtx_REG (rld[r].mode, regno);
6631 /* If we choose EQUIV as the reload register, but the
6632 loop below decides to cancel the inheritance, we'll
6633 end up reloading EQUIV in rld[r].mode, not the mode
6634 it had originally. That isn't safe when EQUIV isn't
6635 available as a spill register since its value might
6636 still be live at this point. */
6637 for (i = regno; i < regno + (int) rld[r].nregs; i++)
6638 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6643 /* If we found a spill reg, reject it unless it is free
6644 and of the desired class. */
6648 int bad_for_class = 0;
6649 int max_regno = regno + rld[r].nregs;
6651 for (i = regno; i < max_regno; i++)
6653 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6655 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6660 && ! free_for_value_p (regno, rld[r].mode,
6661 rld[r].opnum, rld[r].when_needed,
6662 rld[r].in, rld[r].out, r, 1))
6667 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6670 /* We found a register that contains the value we need.
6671 If this register is the same as an `earlyclobber' operand
6672 of the current insn, just mark it as a place to reload from
6673 since we can't use it as the reload register itself. */
6676 for (i = 0; i < n_earlyclobbers; i++)
6677 if (reg_overlap_mentioned_for_reload_p (equiv,
6678 reload_earlyclobbers[i]))
6680 if (! rld[r].optional)
6681 reload_override_in[r] = equiv;
6686 /* If the equiv register we have found is explicitly clobbered
6687 in the current insn, it depends on the reload type if we
6688 can use it, use it for reload_override_in, or not at all.
6689 In particular, we then can't use EQUIV for a
6690 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6694 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6695 switch (rld[r].when_needed)
6697 case RELOAD_FOR_OTHER_ADDRESS:
6698 case RELOAD_FOR_INPADDR_ADDRESS:
6699 case RELOAD_FOR_INPUT_ADDRESS:
6700 case RELOAD_FOR_OPADDR_ADDR:
6703 case RELOAD_FOR_INPUT:
6704 case RELOAD_FOR_OPERAND_ADDRESS:
6705 if (! rld[r].optional)
6706 reload_override_in[r] = equiv;
6712 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6713 switch (rld[r].when_needed)
6715 case RELOAD_FOR_OTHER_ADDRESS:
6716 case RELOAD_FOR_INPADDR_ADDRESS:
6717 case RELOAD_FOR_INPUT_ADDRESS:
6718 case RELOAD_FOR_OPADDR_ADDR:
6719 case RELOAD_FOR_OPERAND_ADDRESS:
6720 case RELOAD_FOR_INPUT:
6723 if (! rld[r].optional)
6724 reload_override_in[r] = equiv;
6732 /* If we found an equivalent reg, say no code need be generated
6733 to load it, and use it as our reload reg. */
6735 && (regno != HARD_FRAME_POINTER_REGNUM
6736 || !frame_pointer_needed))
6738 int nr = hard_regno_nregs[regno][rld[r].mode];
6740 rld[r].reg_rtx = equiv;
6741 reload_spill_index[r] = regno;
6742 reload_inherited[r] = 1;
6744 /* If reg_reloaded_valid is not set for this register,
6745 there might be a stale spill_reg_store lying around.
6746 We must clear it, since otherwise emit_reload_insns
6747 might delete the store. */
6748 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6749 spill_reg_store[regno] = NULL_RTX;
6750 /* If any of the hard registers in EQUIV are spill
6751 registers, mark them as in use for this insn. */
6752 for (k = 0; k < nr; k++)
6754 i = spill_reg_order[regno + k];
6757 mark_reload_reg_in_use (regno, rld[r].opnum,
6760 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6767 /* If we found a register to use already, or if this is an optional
6768 reload, we are done. */
6769 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6773 /* No longer needed for correct operation. Might or might
6774 not give better code on the average. Want to experiment? */
6776 /* See if there is a later reload that has a class different from our
6777 class that intersects our class or that requires less register
6778 than our reload. If so, we must allocate a register to this
6779 reload now, since that reload might inherit a previous reload
6780 and take the only available register in our class. Don't do this
6781 for optional reloads since they will force all previous reloads
6782 to be allocated. Also don't do this for reloads that have been
6785 for (i = j + 1; i < n_reloads; i++)
6787 int s = reload_order[i];
6789 if ((rld[s].in == 0 && rld[s].out == 0
6790 && ! rld[s].secondary_p)
6794 if ((rld[s].rclass != rld[r].rclass
6795 && reg_classes_intersect_p (rld[r].rclass,
6797 || rld[s].nregs < rld[r].nregs)
6804 allocate_reload_reg (chain, r, j == n_reloads - 1);
6808 /* Now allocate reload registers for anything non-optional that
6809 didn't get one yet. */
6810 for (j = 0; j < n_reloads; j++)
6812 int r = reload_order[j];
6814 /* Ignore reloads that got marked inoperative. */
6815 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6818 /* Skip reloads that already have a register allocated or are
6820 if (rld[r].reg_rtx != 0 || rld[r].optional)
6823 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6827 /* If that loop got all the way, we have won. */
6834 /* Loop around and try without any inheritance. */
6839 /* First undo everything done by the failed attempt
6840 to allocate with inheritance. */
6841 choose_reload_regs_init (chain, save_reload_reg_rtx);
6843 /* Some sanity tests to verify that the reloads found in the first
6844 pass are identical to the ones we have now. */
6845 gcc_assert (chain->n_reloads == n_reloads);
6847 for (i = 0; i < n_reloads; i++)
6849 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6851 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6852 for (j = 0; j < n_spills; j++)
6853 if (spill_regs[j] == chain->rld[i].regno)
6854 if (! set_reload_reg (j, i))
6855 failed_reload (chain->insn, i);
6859 /* If we thought we could inherit a reload, because it seemed that
6860 nothing else wanted the same reload register earlier in the insn,
6861 verify that assumption, now that all reloads have been assigned.
6862 Likewise for reloads where reload_override_in has been set. */
6864 /* If doing expensive optimizations, do one preliminary pass that doesn't
6865 cancel any inheritance, but removes reloads that have been needed only
6866 for reloads that we know can be inherited. */
6867 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6869 for (j = 0; j < n_reloads; j++)
6871 int r = reload_order[j];
6873 if (reload_inherited[r] && rld[r].reg_rtx)
6874 check_reg = rld[r].reg_rtx;
6875 else if (reload_override_in[r]
6876 && (REG_P (reload_override_in[r])
6877 || GET_CODE (reload_override_in[r]) == SUBREG))
6878 check_reg = reload_override_in[r];
6881 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6882 rld[r].opnum, rld[r].when_needed, rld[r].in,
6883 (reload_inherited[r]
6884 ? rld[r].out : const0_rtx),
6889 reload_inherited[r] = 0;
6890 reload_override_in[r] = 0;
6892 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6893 reload_override_in, then we do not need its related
6894 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6895 likewise for other reload types.
6896 We handle this by removing a reload when its only replacement
6897 is mentioned in reload_in of the reload we are going to inherit.
6898 A special case are auto_inc expressions; even if the input is
6899 inherited, we still need the address for the output. We can
6900 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6901 If we succeeded removing some reload and we are doing a preliminary
6902 pass just to remove such reloads, make another pass, since the
6903 removal of one reload might allow us to inherit another one. */
6905 && rld[r].out != rld[r].in
6906 && remove_address_replacements (rld[r].in) && pass)
6911 /* Now that reload_override_in is known valid,
6912 actually override reload_in. */
6913 for (j = 0; j < n_reloads; j++)
6914 if (reload_override_in[j])
6915 rld[j].in = reload_override_in[j];
6917 /* If this reload won't be done because it has been canceled or is
6918 optional and not inherited, clear reload_reg_rtx so other
6919 routines (such as subst_reloads) don't get confused. */
6920 for (j = 0; j < n_reloads; j++)
6921 if (rld[j].reg_rtx != 0
6922 && ((rld[j].optional && ! reload_inherited[j])
6923 || (rld[j].in == 0 && rld[j].out == 0
6924 && ! rld[j].secondary_p)))
6926 int regno = true_regnum (rld[j].reg_rtx);
6928 if (spill_reg_order[regno] >= 0)
6929 clear_reload_reg_in_use (regno, rld[j].opnum,
6930 rld[j].when_needed, rld[j].mode);
6932 reload_spill_index[j] = -1;
6935 /* Record which pseudos and which spill regs have output reloads. */
6936 for (j = 0; j < n_reloads; j++)
6938 int r = reload_order[j];
6940 i = reload_spill_index[r];
6942 /* I is nonneg if this reload uses a register.
6943 If rld[r].reg_rtx is 0, this is an optional reload
6944 that we opted to ignore. */
6945 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6946 && rld[r].reg_rtx != 0)
6948 int nregno = REGNO (rld[r].out_reg);
6951 if (nregno < FIRST_PSEUDO_REGISTER)
6952 nr = hard_regno_nregs[nregno][rld[r].mode];
6955 SET_REGNO_REG_SET (®_has_output_reload,
6960 nr = hard_regno_nregs[i][rld[r].mode];
6962 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6965 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6966 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6967 || rld[r].when_needed == RELOAD_FOR_INSN);
6972 /* Deallocate the reload register for reload R. This is called from
6973 remove_address_replacements. */
6976 deallocate_reload_reg (int r)
6980 if (! rld[r].reg_rtx)
6982 regno = true_regnum (rld[r].reg_rtx);
6984 if (spill_reg_order[regno] >= 0)
6985 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6987 reload_spill_index[r] = -1;
6990 /* These arrays are filled by emit_reload_insns and its subroutines. */
6991 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6992 static rtx other_input_address_reload_insns = 0;
6993 static rtx other_input_reload_insns = 0;
6994 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6995 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6996 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6997 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6998 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6999 static rtx operand_reload_insns = 0;
7000 static rtx other_operand_reload_insns = 0;
7001 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
7003 /* Values to be put in spill_reg_store are put here first. */
7004 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
7005 static HARD_REG_SET reg_reloaded_died;
7007 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7008 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
7009 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
7010 adjusted register, and return true. Otherwise, return false. */
7012 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
7013 enum reg_class new_class,
7014 enum machine_mode new_mode)
7019 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
7021 unsigned regno = REGNO (reg);
7023 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
7025 if (GET_MODE (reg) != new_mode)
7027 if (!HARD_REGNO_MODE_OK (regno, new_mode))
7029 if (hard_regno_nregs[regno][new_mode]
7030 > hard_regno_nregs[regno][GET_MODE (reg)])
7032 reg = reload_adjust_reg_for_mode (reg, new_mode);
7040 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7041 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7042 nonzero, if that is suitable. On success, change *RELOAD_REG to the
7043 adjusted register, and return true. Otherwise, return false. */
7045 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
7046 enum insn_code icode)
7049 enum reg_class new_class = scratch_reload_class (icode);
7050 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
7052 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
7053 new_class, new_mode);
7056 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7057 has the number J. OLD contains the value to be used as input. */
7060 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
7063 rtx insn = chain->insn;
7065 rtx oldequiv_reg = 0;
7068 enum machine_mode mode;
7071 /* delete_output_reload is only invoked properly if old contains
7072 the original pseudo register. Since this is replaced with a
7073 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7074 find the pseudo in RELOAD_IN_REG. */
7075 if (reload_override_in[j]
7076 && REG_P (rl->in_reg))
7083 else if (REG_P (oldequiv))
7084 oldequiv_reg = oldequiv;
7085 else if (GET_CODE (oldequiv) == SUBREG)
7086 oldequiv_reg = SUBREG_REG (oldequiv);
7088 reloadreg = reload_reg_rtx_for_input[j];
7089 mode = GET_MODE (reloadreg);
7091 /* If we are reloading from a register that was recently stored in
7092 with an output-reload, see if we can prove there was
7093 actually no need to store the old value in it. */
7095 if (optimize && REG_P (oldequiv)
7096 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
7097 && spill_reg_store[REGNO (oldequiv)]
7099 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
7100 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
7102 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
7104 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7107 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
7108 oldequiv = SUBREG_REG (oldequiv);
7109 if (GET_MODE (oldequiv) != VOIDmode
7110 && mode != GET_MODE (oldequiv))
7111 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
7113 /* Switch to the right place to emit the reload insns. */
7114 switch (rl->when_needed)
7117 where = &other_input_reload_insns;
7119 case RELOAD_FOR_INPUT:
7120 where = &input_reload_insns[rl->opnum];
7122 case RELOAD_FOR_INPUT_ADDRESS:
7123 where = &input_address_reload_insns[rl->opnum];
7125 case RELOAD_FOR_INPADDR_ADDRESS:
7126 where = &inpaddr_address_reload_insns[rl->opnum];
7128 case RELOAD_FOR_OUTPUT_ADDRESS:
7129 where = &output_address_reload_insns[rl->opnum];
7131 case RELOAD_FOR_OUTADDR_ADDRESS:
7132 where = &outaddr_address_reload_insns[rl->opnum];
7134 case RELOAD_FOR_OPERAND_ADDRESS:
7135 where = &operand_reload_insns;
7137 case RELOAD_FOR_OPADDR_ADDR:
7138 where = &other_operand_reload_insns;
7140 case RELOAD_FOR_OTHER_ADDRESS:
7141 where = &other_input_address_reload_insns;
7147 push_to_sequence (*where);
7149 /* Auto-increment addresses must be reloaded in a special way. */
7150 if (rl->out && ! rl->out_reg)
7152 /* We are not going to bother supporting the case where a
7153 incremented register can't be copied directly from
7154 OLDEQUIV since this seems highly unlikely. */
7155 gcc_assert (rl->secondary_in_reload < 0);
7157 if (reload_inherited[j])
7158 oldequiv = reloadreg;
7160 old = XEXP (rl->in_reg, 0);
7162 if (optimize && REG_P (oldequiv)
7163 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
7164 && spill_reg_store[REGNO (oldequiv)]
7166 && (dead_or_set_p (insn,
7167 spill_reg_stored_to[REGNO (oldequiv)])
7168 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
7170 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
7172 /* Prevent normal processing of this reload. */
7174 /* Output a special code sequence for this case. */
7175 new_spill_reg_store[REGNO (reloadreg)]
7176 = inc_for_reload (reloadreg, oldequiv, rl->out,
7180 /* If we are reloading a pseudo-register that was set by the previous
7181 insn, see if we can get rid of that pseudo-register entirely
7182 by redirecting the previous insn into our reload register. */
7184 else if (optimize && REG_P (old)
7185 && REGNO (old) >= FIRST_PSEUDO_REGISTER
7186 && dead_or_set_p (insn, old)
7187 /* This is unsafe if some other reload
7188 uses the same reg first. */
7189 && ! conflicts_with_override (reloadreg)
7190 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
7191 rl->when_needed, old, rl->out, j, 0))
7193 rtx temp = PREV_INSN (insn);
7194 while (temp && (NOTE_P (temp) || DEBUG_INSN_P (temp)))
7195 temp = PREV_INSN (temp);
7197 && NONJUMP_INSN_P (temp)
7198 && GET_CODE (PATTERN (temp)) == SET
7199 && SET_DEST (PATTERN (temp)) == old
7200 /* Make sure we can access insn_operand_constraint. */
7201 && asm_noperands (PATTERN (temp)) < 0
7202 /* This is unsafe if operand occurs more than once in current
7203 insn. Perhaps some occurrences aren't reloaded. */
7204 && count_occurrences (PATTERN (insn), old, 0) == 1)
7206 rtx old = SET_DEST (PATTERN (temp));
7207 /* Store into the reload register instead of the pseudo. */
7208 SET_DEST (PATTERN (temp)) = reloadreg;
7210 /* Verify that resulting insn is valid. */
7211 extract_insn (temp);
7212 if (constrain_operands (1))
7214 /* If the previous insn is an output reload, the source is
7215 a reload register, and its spill_reg_store entry will
7216 contain the previous destination. This is now
7218 if (REG_P (SET_SRC (PATTERN (temp)))
7219 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
7221 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7222 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7225 /* If these are the only uses of the pseudo reg,
7226 pretend for GDB it lives in the reload reg we used. */
7227 if (REG_N_DEATHS (REGNO (old)) == 1
7228 && REG_N_SETS (REGNO (old)) == 1)
7230 reg_renumber[REGNO (old)] = REGNO (reloadreg);
7231 if (ira_conflicts_p)
7232 /* Inform IRA about the change. */
7233 ira_mark_allocation_change (REGNO (old));
7234 alter_reg (REGNO (old), -1, false);
7238 /* Adjust any debug insns between temp and insn. */
7239 while ((temp = NEXT_INSN (temp)) != insn)
7240 if (DEBUG_INSN_P (temp))
7241 replace_rtx (PATTERN (temp), old, reloadreg);
7243 gcc_assert (NOTE_P (temp));
7247 SET_DEST (PATTERN (temp)) = old;
7252 /* We can't do that, so output an insn to load RELOADREG. */
7254 /* If we have a secondary reload, pick up the secondary register
7255 and icode, if any. If OLDEQUIV and OLD are different or
7256 if this is an in-out reload, recompute whether or not we
7257 still need a secondary register and what the icode should
7258 be. If we still need a secondary register and the class or
7259 icode is different, go back to reloading from OLD if using
7260 OLDEQUIV means that we got the wrong type of register. We
7261 cannot have different class or icode due to an in-out reload
7262 because we don't make such reloads when both the input and
7263 output need secondary reload registers. */
7265 if (! special && rl->secondary_in_reload >= 0)
7267 rtx second_reload_reg = 0;
7268 rtx third_reload_reg = 0;
7269 int secondary_reload = rl->secondary_in_reload;
7270 rtx real_oldequiv = oldequiv;
7273 enum insn_code icode;
7274 enum insn_code tertiary_icode = CODE_FOR_nothing;
7276 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7277 and similarly for OLD.
7278 See comments in get_secondary_reload in reload.c. */
7279 /* If it is a pseudo that cannot be replaced with its
7280 equivalent MEM, we must fall back to reload_in, which
7281 will have all the necessary substitutions registered.
7282 Likewise for a pseudo that can't be replaced with its
7283 equivalent constant.
7285 Take extra care for subregs of such pseudos. Note that
7286 we cannot use reg_equiv_mem in this case because it is
7287 not in the right mode. */
7290 if (GET_CODE (tmp) == SUBREG)
7291 tmp = SUBREG_REG (tmp);
7293 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7294 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
7295 || reg_equiv_constant[REGNO (tmp)] != 0))
7297 if (! reg_equiv_mem[REGNO (tmp)]
7298 || num_not_at_initial_offset
7299 || GET_CODE (oldequiv) == SUBREG)
7300 real_oldequiv = rl->in;
7302 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
7306 if (GET_CODE (tmp) == SUBREG)
7307 tmp = SUBREG_REG (tmp);
7309 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7310 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
7311 || reg_equiv_constant[REGNO (tmp)] != 0))
7313 if (! reg_equiv_mem[REGNO (tmp)]
7314 || num_not_at_initial_offset
7315 || GET_CODE (old) == SUBREG)
7318 real_old = reg_equiv_mem[REGNO (tmp)];
7321 second_reload_reg = rld[secondary_reload].reg_rtx;
7322 if (rld[secondary_reload].secondary_in_reload >= 0)
7324 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7326 third_reload_reg = rld[tertiary_reload].reg_rtx;
7327 tertiary_icode = rld[secondary_reload].secondary_in_icode;
7328 /* We'd have to add more code for quartary reloads. */
7329 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7331 icode = rl->secondary_in_icode;
7333 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7334 || (rl->in != 0 && rl->out != 0))
7336 secondary_reload_info sri, sri2;
7337 enum reg_class new_class, new_t_class;
7339 sri.icode = CODE_FOR_nothing;
7340 sri.prev_sri = NULL;
7342 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7346 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7347 second_reload_reg = 0;
7348 else if (new_class == NO_REGS)
7350 if (reload_adjust_reg_for_icode (&second_reload_reg,
7352 (enum insn_code) sri.icode))
7354 icode = (enum insn_code) sri.icode;
7355 third_reload_reg = 0;
7360 real_oldequiv = real_old;
7363 else if (sri.icode != CODE_FOR_nothing)
7364 /* We currently lack a way to express this in reloads. */
7368 sri2.icode = CODE_FOR_nothing;
7369 sri2.prev_sri = &sri;
7371 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7374 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7376 if (reload_adjust_reg_for_temp (&second_reload_reg,
7380 third_reload_reg = 0;
7381 tertiary_icode = (enum insn_code) sri2.icode;
7386 real_oldequiv = real_old;
7389 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7391 rtx intermediate = second_reload_reg;
7393 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7395 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7399 second_reload_reg = intermediate;
7400 tertiary_icode = (enum insn_code) sri2.icode;
7405 real_oldequiv = real_old;
7408 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7410 rtx intermediate = second_reload_reg;
7412 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7414 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7417 second_reload_reg = intermediate;
7418 tertiary_icode = (enum insn_code) sri2.icode;
7423 real_oldequiv = real_old;
7428 /* This could be handled more intelligently too. */
7430 real_oldequiv = real_old;
7435 /* If we still need a secondary reload register, check
7436 to see if it is being used as a scratch or intermediate
7437 register and generate code appropriately. If we need
7438 a scratch register, use REAL_OLDEQUIV since the form of
7439 the insn may depend on the actual address if it is
7442 if (second_reload_reg)
7444 if (icode != CODE_FOR_nothing)
7446 /* We'd have to add extra code to handle this case. */
7447 gcc_assert (!third_reload_reg);
7449 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7450 second_reload_reg));
7455 /* See if we need a scratch register to load the
7456 intermediate register (a tertiary reload). */
7457 if (tertiary_icode != CODE_FOR_nothing)
7459 emit_insn ((GEN_FCN (tertiary_icode)
7460 (second_reload_reg, real_oldequiv,
7461 third_reload_reg)));
7463 else if (third_reload_reg)
7465 gen_reload (third_reload_reg, real_oldequiv,
7468 gen_reload (second_reload_reg, third_reload_reg,
7473 gen_reload (second_reload_reg, real_oldequiv,
7477 oldequiv = second_reload_reg;
7482 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7484 rtx real_oldequiv = oldequiv;
7486 if ((REG_P (oldequiv)
7487 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7488 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
7489 || reg_equiv_constant[REGNO (oldequiv)] != 0))
7490 || (GET_CODE (oldequiv) == SUBREG
7491 && REG_P (SUBREG_REG (oldequiv))
7492 && (REGNO (SUBREG_REG (oldequiv))
7493 >= FIRST_PSEUDO_REGISTER)
7494 && ((reg_equiv_memory_loc
7495 [REGNO (SUBREG_REG (oldequiv))] != 0)
7496 || (reg_equiv_constant
7497 [REGNO (SUBREG_REG (oldequiv))] != 0)))
7498 || (CONSTANT_P (oldequiv)
7499 && (PREFERRED_RELOAD_CLASS (oldequiv,
7500 REGNO_REG_CLASS (REGNO (reloadreg)))
7502 real_oldequiv = rl->in;
7503 gen_reload (reloadreg, real_oldequiv, rl->opnum,
7507 if (cfun->can_throw_non_call_exceptions)
7508 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7510 /* End this sequence. */
7511 *where = get_insns ();
7514 /* Update reload_override_in so that delete_address_reloads_1
7515 can see the actual register usage. */
7517 reload_override_in[j] = oldequiv;
7520 /* Generate insns to for the output reload RL, which is for the insn described
7521 by CHAIN and has the number J. */
7523 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7527 rtx insn = chain->insn;
7530 enum machine_mode mode;
7534 if (rl->when_needed == RELOAD_OTHER)
7537 push_to_sequence (output_reload_insns[rl->opnum]);
7539 rl_reg_rtx = reload_reg_rtx_for_output[j];
7540 mode = GET_MODE (rl_reg_rtx);
7542 reloadreg = rl_reg_rtx;
7544 /* If we need two reload regs, set RELOADREG to the intermediate
7545 one, since it will be stored into OLD. We might need a secondary
7546 register only for an input reload, so check again here. */
7548 if (rl->secondary_out_reload >= 0)
7551 int secondary_reload = rl->secondary_out_reload;
7552 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7554 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7555 && reg_equiv_mem[REGNO (old)] != 0)
7556 real_old = reg_equiv_mem[REGNO (old)];
7558 if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7560 rtx second_reloadreg = reloadreg;
7561 reloadreg = rld[secondary_reload].reg_rtx;
7563 /* See if RELOADREG is to be used as a scratch register
7564 or as an intermediate register. */
7565 if (rl->secondary_out_icode != CODE_FOR_nothing)
7567 /* We'd have to add extra code to handle this case. */
7568 gcc_assert (tertiary_reload < 0);
7570 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7571 (real_old, second_reloadreg, reloadreg)));
7576 /* See if we need both a scratch and intermediate reload
7579 enum insn_code tertiary_icode
7580 = rld[secondary_reload].secondary_out_icode;
7582 /* We'd have to add more code for quartary reloads. */
7583 gcc_assert (tertiary_reload < 0
7584 || rld[tertiary_reload].secondary_out_reload < 0);
7586 if (GET_MODE (reloadreg) != mode)
7587 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7589 if (tertiary_icode != CODE_FOR_nothing)
7591 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7594 /* Copy primary reload reg to secondary reload reg.
7595 (Note that these have been swapped above, then
7596 secondary reload reg to OLD using our insn.) */
7598 /* If REAL_OLD is a paradoxical SUBREG, remove it
7599 and try to put the opposite SUBREG on
7601 if (GET_CODE (real_old) == SUBREG
7602 && (GET_MODE_SIZE (GET_MODE (real_old))
7603 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7604 && 0 != (tem = gen_lowpart_common
7605 (GET_MODE (SUBREG_REG (real_old)),
7607 real_old = SUBREG_REG (real_old), reloadreg = tem;
7609 gen_reload (reloadreg, second_reloadreg,
7610 rl->opnum, rl->when_needed);
7611 emit_insn ((GEN_FCN (tertiary_icode)
7612 (real_old, reloadreg, third_reloadreg)));
7618 /* Copy between the reload regs here and then to
7621 gen_reload (reloadreg, second_reloadreg,
7622 rl->opnum, rl->when_needed);
7623 if (tertiary_reload >= 0)
7625 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7627 gen_reload (third_reloadreg, reloadreg,
7628 rl->opnum, rl->when_needed);
7629 reloadreg = third_reloadreg;
7636 /* Output the last reload insn. */
7641 /* Don't output the last reload if OLD is not the dest of
7642 INSN and is in the src and is clobbered by INSN. */
7643 if (! flag_expensive_optimizations
7645 || !(set = single_set (insn))
7646 || rtx_equal_p (old, SET_DEST (set))
7647 || !reg_mentioned_p (old, SET_SRC (set))
7648 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7649 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7650 gen_reload (old, reloadreg, rl->opnum,
7654 /* Look at all insns we emitted, just to be safe. */
7655 for (p = get_insns (); p; p = NEXT_INSN (p))
7658 rtx pat = PATTERN (p);
7660 /* If this output reload doesn't come from a spill reg,
7661 clear any memory of reloaded copies of the pseudo reg.
7662 If this output reload comes from a spill reg,
7663 reg_has_output_reload will make this do nothing. */
7664 note_stores (pat, forget_old_reloads_1, NULL);
7666 if (reg_mentioned_p (rl_reg_rtx, pat))
7668 rtx set = single_set (insn);
7669 if (reload_spill_index[j] < 0
7671 && SET_SRC (set) == rl_reg_rtx)
7673 int src = REGNO (SET_SRC (set));
7675 reload_spill_index[j] = src;
7676 SET_HARD_REG_BIT (reg_is_output_reload, src);
7677 if (find_regno_note (insn, REG_DEAD, src))
7678 SET_HARD_REG_BIT (reg_reloaded_died, src);
7680 if (HARD_REGISTER_P (rl_reg_rtx))
7682 int s = rl->secondary_out_reload;
7683 set = single_set (p);
7684 /* If this reload copies only to the secondary reload
7685 register, the secondary reload does the actual
7687 if (s >= 0 && set == NULL_RTX)
7688 /* We can't tell what function the secondary reload
7689 has and where the actual store to the pseudo is
7690 made; leave new_spill_reg_store alone. */
7693 && SET_SRC (set) == rl_reg_rtx
7694 && SET_DEST (set) == rld[s].reg_rtx)
7696 /* Usually the next instruction will be the
7697 secondary reload insn; if we can confirm
7698 that it is, setting new_spill_reg_store to
7699 that insn will allow an extra optimization. */
7700 rtx s_reg = rld[s].reg_rtx;
7701 rtx next = NEXT_INSN (p);
7702 rld[s].out = rl->out;
7703 rld[s].out_reg = rl->out_reg;
7704 set = single_set (next);
7705 if (set && SET_SRC (set) == s_reg
7706 && ! new_spill_reg_store[REGNO (s_reg)])
7708 SET_HARD_REG_BIT (reg_is_output_reload,
7710 new_spill_reg_store[REGNO (s_reg)] = next;
7714 new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7719 if (rl->when_needed == RELOAD_OTHER)
7721 emit_insn (other_output_reload_insns[rl->opnum]);
7722 other_output_reload_insns[rl->opnum] = get_insns ();
7725 output_reload_insns[rl->opnum] = get_insns ();
7727 if (cfun->can_throw_non_call_exceptions)
7728 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7733 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7734 and has the number J. */
7736 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7738 rtx insn = chain->insn;
7739 rtx old = (rl->in && MEM_P (rl->in)
7740 ? rl->in_reg : rl->in);
7741 rtx reg_rtx = rl->reg_rtx;
7745 enum machine_mode mode;
7747 /* Determine the mode to reload in.
7748 This is very tricky because we have three to choose from.
7749 There is the mode the insn operand wants (rl->inmode).
7750 There is the mode of the reload register RELOADREG.
7751 There is the intrinsic mode of the operand, which we could find
7752 by stripping some SUBREGs.
7753 It turns out that RELOADREG's mode is irrelevant:
7754 we can change that arbitrarily.
7756 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7757 then the reload reg may not support QImode moves, so use SImode.
7758 If foo is in memory due to spilling a pseudo reg, this is safe,
7759 because the QImode value is in the least significant part of a
7760 slot big enough for a SImode. If foo is some other sort of
7761 memory reference, then it is impossible to reload this case,
7762 so previous passes had better make sure this never happens.
7764 Then consider a one-word union which has SImode and one of its
7765 members is a float, being fetched as (SUBREG:SF union:SI).
7766 We must fetch that as SFmode because we could be loading into
7767 a float-only register. In this case OLD's mode is correct.
7769 Consider an immediate integer: it has VOIDmode. Here we need
7770 to get a mode from something else.
7772 In some cases, there is a fourth mode, the operand's
7773 containing mode. If the insn specifies a containing mode for
7774 this operand, it overrides all others.
7776 I am not sure whether the algorithm here is always right,
7777 but it does the right things in those cases. */
7779 mode = GET_MODE (old);
7780 if (mode == VOIDmode)
7783 /* We cannot use gen_lowpart_common since it can do the wrong thing
7784 when REG_RTX has a multi-word mode. Note that REG_RTX must
7785 always be a REG here. */
7786 if (GET_MODE (reg_rtx) != mode)
7787 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7789 reload_reg_rtx_for_input[j] = reg_rtx;
7792 /* AUTO_INC reloads need to be handled even if inherited. We got an
7793 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7794 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7795 && ! rtx_equal_p (reg_rtx, old)
7797 emit_input_reload_insns (chain, rld + j, old, j);
7799 /* When inheriting a wider reload, we have a MEM in rl->in,
7800 e.g. inheriting a SImode output reload for
7801 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7802 if (optimize && reload_inherited[j] && rl->in
7804 && MEM_P (rl->in_reg)
7805 && reload_spill_index[j] >= 0
7806 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7807 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7809 /* If we are reloading a register that was recently stored in with an
7810 output-reload, see if we can prove there was
7811 actually no need to store the old value in it. */
7814 && (reload_inherited[j] || reload_override_in[j])
7817 && spill_reg_store[REGNO (reg_rtx)] != 0
7819 /* There doesn't seem to be any reason to restrict this to pseudos
7820 and doing so loses in the case where we are copying from a
7821 register of the wrong class. */
7822 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7824 /* The insn might have already some references to stackslots
7825 replaced by MEMs, while reload_out_reg still names the
7827 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7828 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7829 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7832 /* Do output reloading for reload RL, which is for the insn described by
7833 CHAIN and has the number J.
7834 ??? At some point we need to support handling output reloads of
7835 JUMP_INSNs or insns that set cc0. */
7837 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7840 rtx insn = chain->insn;
7841 /* If this is an output reload that stores something that is
7842 not loaded in this same reload, see if we can eliminate a previous
7844 rtx pseudo = rl->out_reg;
7845 rtx reg_rtx = rl->reg_rtx;
7847 if (rl->out && reg_rtx)
7849 enum machine_mode mode;
7851 /* Determine the mode to reload in.
7852 See comments above (for input reloading). */
7853 mode = GET_MODE (rl->out);
7854 if (mode == VOIDmode)
7856 /* VOIDmode should never happen for an output. */
7857 if (asm_noperands (PATTERN (insn)) < 0)
7858 /* It's the compiler's fault. */
7859 fatal_insn ("VOIDmode on an output", insn);
7860 error_for_asm (insn, "output operand is constant in %<asm%>");
7861 /* Prevent crash--use something we know is valid. */
7863 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7865 if (GET_MODE (reg_rtx) != mode)
7866 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7868 reload_reg_rtx_for_output[j] = reg_rtx;
7873 && ! rtx_equal_p (rl->in_reg, pseudo)
7874 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7875 && reg_last_reload_reg[REGNO (pseudo)])
7877 int pseudo_no = REGNO (pseudo);
7878 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7880 /* We don't need to test full validity of last_regno for
7881 inherit here; we only want to know if the store actually
7882 matches the pseudo. */
7883 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7884 && reg_reloaded_contents[last_regno] == pseudo_no
7885 && spill_reg_store[last_regno]
7886 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7887 delete_output_reload (insn, j, last_regno, reg_rtx);
7893 || rtx_equal_p (old, reg_rtx))
7896 /* An output operand that dies right away does need a reload,
7897 but need not be copied from it. Show the new location in the
7899 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7900 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7902 XEXP (note, 0) = reg_rtx;
7905 /* Likewise for a SUBREG of an operand that dies. */
7906 else if (GET_CODE (old) == SUBREG
7907 && REG_P (SUBREG_REG (old))
7908 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7911 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
7914 else if (GET_CODE (old) == SCRATCH)
7915 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7916 but we don't want to make an output reload. */
7919 /* If is a JUMP_INSN, we can't support output reloads yet. */
7920 gcc_assert (NONJUMP_INSN_P (insn));
7922 emit_output_reload_insns (chain, rld + j, j);
7925 /* A reload copies values of MODE from register SRC to register DEST.
7926 Return true if it can be treated for inheritance purposes like a
7927 group of reloads, each one reloading a single hard register. The
7928 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7929 occupy the same number of hard registers. */
7932 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
7933 int src ATTRIBUTE_UNUSED,
7934 enum machine_mode mode ATTRIBUTE_UNUSED)
7936 #ifdef CANNOT_CHANGE_MODE_CLASS
7937 return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
7938 && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
7944 /* Output insns to reload values in and out of the chosen reload regs. */
7947 emit_reload_insns (struct insn_chain *chain)
7949 rtx insn = chain->insn;
7953 CLEAR_HARD_REG_SET (reg_reloaded_died);
7955 for (j = 0; j < reload_n_operands; j++)
7956 input_reload_insns[j] = input_address_reload_insns[j]
7957 = inpaddr_address_reload_insns[j]
7958 = output_reload_insns[j] = output_address_reload_insns[j]
7959 = outaddr_address_reload_insns[j]
7960 = other_output_reload_insns[j] = 0;
7961 other_input_address_reload_insns = 0;
7962 other_input_reload_insns = 0;
7963 operand_reload_insns = 0;
7964 other_operand_reload_insns = 0;
7966 /* Dump reloads into the dump file. */
7969 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7970 debug_reload_to_stream (dump_file);
7973 /* Now output the instructions to copy the data into and out of the
7974 reload registers. Do these in the order that the reloads were reported,
7975 since reloads of base and index registers precede reloads of operands
7976 and the operands may need the base and index registers reloaded. */
7978 for (j = 0; j < n_reloads; j++)
7980 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
7984 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
7985 new_spill_reg_store[i] = 0;
7988 do_input_reload (chain, rld + j, j);
7989 do_output_reload (chain, rld + j, j);
7992 /* Now write all the insns we made for reloads in the order expected by
7993 the allocation functions. Prior to the insn being reloaded, we write
7994 the following reloads:
7996 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7998 RELOAD_OTHER reloads.
8000 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8001 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8002 RELOAD_FOR_INPUT reload for the operand.
8004 RELOAD_FOR_OPADDR_ADDRS reloads.
8006 RELOAD_FOR_OPERAND_ADDRESS reloads.
8008 After the insn being reloaded, we write the following:
8010 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8011 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8012 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8013 reloads for the operand. The RELOAD_OTHER output reloads are
8014 output in descending order by reload number. */
8016 emit_insn_before (other_input_address_reload_insns, insn);
8017 emit_insn_before (other_input_reload_insns, insn);
8019 for (j = 0; j < reload_n_operands; j++)
8021 emit_insn_before (inpaddr_address_reload_insns[j], insn);
8022 emit_insn_before (input_address_reload_insns[j], insn);
8023 emit_insn_before (input_reload_insns[j], insn);
8026 emit_insn_before (other_operand_reload_insns, insn);
8027 emit_insn_before (operand_reload_insns, insn);
8029 for (j = 0; j < reload_n_operands; j++)
8031 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
8032 x = emit_insn_after (output_address_reload_insns[j], x);
8033 x = emit_insn_after (output_reload_insns[j], x);
8034 emit_insn_after (other_output_reload_insns[j], x);
8037 /* For all the spill regs newly reloaded in this instruction,
8038 record what they were reloaded from, so subsequent instructions
8039 can inherit the reloads.
8041 Update spill_reg_store for the reloads of this insn.
8042 Copy the elements that were updated in the loop above. */
8044 for (j = 0; j < n_reloads; j++)
8046 int r = reload_order[j];
8047 int i = reload_spill_index[r];
8049 /* If this is a non-inherited input reload from a pseudo, we must
8050 clear any memory of a previous store to the same pseudo. Only do
8051 something if there will not be an output reload for the pseudo
8053 if (rld[r].in_reg != 0
8054 && ! (reload_inherited[r] || reload_override_in[r]))
8056 rtx reg = rld[r].in_reg;
8058 if (GET_CODE (reg) == SUBREG)
8059 reg = SUBREG_REG (reg);
8062 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
8063 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
8065 int nregno = REGNO (reg);
8067 if (reg_last_reload_reg[nregno])
8069 int last_regno = REGNO (reg_last_reload_reg[nregno]);
8071 if (reg_reloaded_contents[last_regno] == nregno)
8072 spill_reg_store[last_regno] = 0;
8077 /* I is nonneg if this reload used a register.
8078 If rld[r].reg_rtx is 0, this is an optional reload
8079 that we opted to ignore. */
8081 if (i >= 0 && rld[r].reg_rtx != 0)
8083 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
8086 /* For a multi register reload, we need to check if all or part
8087 of the value lives to the end. */
8088 for (k = 0; k < nr; k++)
8089 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
8090 rld[r].when_needed))
8091 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
8093 /* Maybe the spill reg contains a copy of reload_out. */
8095 && (REG_P (rld[r].out)
8099 || REG_P (rld[r].out_reg)))
8102 enum machine_mode mode;
8105 reg = reload_reg_rtx_for_output[r];
8106 mode = GET_MODE (reg);
8107 regno = REGNO (reg);
8108 nregs = hard_regno_nregs[regno][mode];
8109 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
8110 rld[r].when_needed))
8112 rtx out = (REG_P (rld[r].out)
8116 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
8117 int out_regno = REGNO (out);
8118 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
8119 : hard_regno_nregs[out_regno][mode]);
8122 spill_reg_store[regno] = new_spill_reg_store[regno];
8123 spill_reg_stored_to[regno] = out;
8124 reg_last_reload_reg[out_regno] = reg;
8126 piecemeal = (HARD_REGISTER_NUM_P (out_regno)
8127 && nregs == out_nregs
8128 && inherit_piecemeal_p (out_regno, regno, mode));
8130 /* If OUT_REGNO is a hard register, it may occupy more than
8131 one register. If it does, say what is in the
8132 rest of the registers assuming that both registers
8133 agree on how many words the object takes. If not,
8134 invalidate the subsequent registers. */
8136 if (HARD_REGISTER_NUM_P (out_regno))
8137 for (k = 1; k < out_nregs; k++)
8138 reg_last_reload_reg[out_regno + k]
8139 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8141 /* Now do the inverse operation. */
8142 for (k = 0; k < nregs; k++)
8144 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8145 reg_reloaded_contents[regno + k]
8146 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
8149 reg_reloaded_insn[regno + k] = insn;
8150 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8151 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8152 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8155 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8160 /* Maybe the spill reg contains a copy of reload_in. Only do
8161 something if there will not be an output reload for
8162 the register being reloaded. */
8163 else if (rld[r].out_reg == 0
8165 && ((REG_P (rld[r].in)
8166 && !HARD_REGISTER_P (rld[r].in)
8167 && !REGNO_REG_SET_P (®_has_output_reload,
8169 || (REG_P (rld[r].in_reg)
8170 && !REGNO_REG_SET_P (®_has_output_reload,
8171 REGNO (rld[r].in_reg))))
8172 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
8175 enum machine_mode mode;
8178 reg = reload_reg_rtx_for_input[r];
8179 mode = GET_MODE (reg);
8180 regno = REGNO (reg);
8181 nregs = hard_regno_nregs[regno][mode];
8182 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
8183 rld[r].when_needed))
8190 if (REG_P (rld[r].in)
8191 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
8193 else if (REG_P (rld[r].in_reg))
8196 in = XEXP (rld[r].in_reg, 0);
8197 in_regno = REGNO (in);
8199 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
8200 : hard_regno_nregs[in_regno][mode]);
8202 reg_last_reload_reg[in_regno] = reg;
8204 piecemeal = (HARD_REGISTER_NUM_P (in_regno)
8205 && nregs == in_nregs
8206 && inherit_piecemeal_p (regno, in_regno, mode));
8208 if (HARD_REGISTER_NUM_P (in_regno))
8209 for (k = 1; k < in_nregs; k++)
8210 reg_last_reload_reg[in_regno + k]
8211 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8213 /* Unless we inherited this reload, show we haven't
8214 recently done a store.
8215 Previous stores of inherited auto_inc expressions
8216 also have to be discarded. */
8217 if (! reload_inherited[r]
8218 || (rld[r].out && ! rld[r].out_reg))
8219 spill_reg_store[regno] = 0;
8221 for (k = 0; k < nregs; k++)
8223 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8224 reg_reloaded_contents[regno + k]
8225 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
8228 reg_reloaded_insn[regno + k] = insn;
8229 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8230 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8231 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8234 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8241 /* The following if-statement was #if 0'd in 1.34 (or before...).
8242 It's reenabled in 1.35 because supposedly nothing else
8243 deals with this problem. */
8245 /* If a register gets output-reloaded from a non-spill register,
8246 that invalidates any previous reloaded copy of it.
8247 But forget_old_reloads_1 won't get to see it, because
8248 it thinks only about the original insn. So invalidate it here.
8249 Also do the same thing for RELOAD_OTHER constraints where the
8250 output is discarded. */
8252 && ((rld[r].out != 0
8253 && (REG_P (rld[r].out)
8254 || (MEM_P (rld[r].out)
8255 && REG_P (rld[r].out_reg))))
8256 || (rld[r].out == 0 && rld[r].out_reg
8257 && REG_P (rld[r].out_reg))))
8259 rtx out = ((rld[r].out && REG_P (rld[r].out))
8260 ? rld[r].out : rld[r].out_reg);
8261 int out_regno = REGNO (out);
8262 enum machine_mode mode = GET_MODE (out);
8264 /* REG_RTX is now set or clobbered by the main instruction.
8265 As the comment above explains, forget_old_reloads_1 only
8266 sees the original instruction, and there is no guarantee
8267 that the original instruction also clobbered REG_RTX.
8268 For example, if find_reloads sees that the input side of
8269 a matched operand pair dies in this instruction, it may
8270 use the input register as the reload register.
8272 Calling forget_old_reloads_1 is a waste of effort if
8273 REG_RTX is also the output register.
8275 If we know that REG_RTX holds the value of a pseudo
8276 register, the code after the call will record that fact. */
8277 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8278 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8280 if (!HARD_REGISTER_NUM_P (out_regno))
8282 rtx src_reg, store_insn = NULL_RTX;
8284 reg_last_reload_reg[out_regno] = 0;
8286 /* If we can find a hard register that is stored, record
8287 the storing insn so that we may delete this insn with
8288 delete_output_reload. */
8289 src_reg = reload_reg_rtx_for_output[r];
8291 /* If this is an optional reload, try to find the source reg
8292 from an input reload. */
8295 rtx set = single_set (insn);
8296 if (set && SET_DEST (set) == rld[r].out)
8300 src_reg = SET_SRC (set);
8302 for (k = 0; k < n_reloads; k++)
8304 if (rld[k].in == src_reg)
8306 src_reg = reload_reg_rtx_for_input[k];
8313 store_insn = new_spill_reg_store[REGNO (src_reg)];
8314 if (src_reg && REG_P (src_reg)
8315 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8317 int src_regno, src_nregs, k;
8320 gcc_assert (GET_MODE (src_reg) == mode);
8321 src_regno = REGNO (src_reg);
8322 src_nregs = hard_regno_nregs[src_regno][mode];
8323 /* The place where to find a death note varies with
8324 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8325 necessarily checked exactly in the code that moves
8326 notes, so just check both locations. */
8327 note = find_regno_note (insn, REG_DEAD, src_regno);
8328 if (! note && store_insn)
8329 note = find_regno_note (store_insn, REG_DEAD, src_regno);
8330 for (k = 0; k < src_nregs; k++)
8332 spill_reg_store[src_regno + k] = store_insn;
8333 spill_reg_stored_to[src_regno + k] = out;
8334 reg_reloaded_contents[src_regno + k] = out_regno;
8335 reg_reloaded_insn[src_regno + k] = store_insn;
8336 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8337 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8338 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
8340 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8343 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8345 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8347 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8349 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8351 reg_last_reload_reg[out_regno] = src_reg;
8352 /* We have to set reg_has_output_reload here, or else
8353 forget_old_reloads_1 will clear reg_last_reload_reg
8355 SET_REGNO_REG_SET (®_has_output_reload,
8361 int k, out_nregs = hard_regno_nregs[out_regno][mode];
8363 for (k = 0; k < out_nregs; k++)
8364 reg_last_reload_reg[out_regno + k] = 0;
8368 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
8371 /* Go through the motions to emit INSN and test if it is strictly valid.
8372 Return the emitted insn if valid, else return NULL. */
8375 emit_insn_if_valid_for_reload (rtx insn)
8377 rtx last = get_last_insn ();
8380 insn = emit_insn (insn);
8381 code = recog_memoized (insn);
8385 extract_insn (insn);
8386 /* We want constrain operands to treat this insn strictly in its
8387 validity determination, i.e., the way it would after reload has
8389 if (constrain_operands (1))
8393 delete_insns_since (last);
8397 /* Emit code to perform a reload from IN (which may be a reload register) to
8398 OUT (which may also be a reload register). IN or OUT is from operand
8399 OPNUM with reload type TYPE.
8401 Returns first insn emitted. */
8404 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8406 rtx last = get_last_insn ();
8409 /* If IN is a paradoxical SUBREG, remove it and try to put the
8410 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8411 if (GET_CODE (in) == SUBREG
8412 && (GET_MODE_SIZE (GET_MODE (in))
8413 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
8414 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
8415 in = SUBREG_REG (in), out = tem;
8416 else if (GET_CODE (out) == SUBREG
8417 && (GET_MODE_SIZE (GET_MODE (out))
8418 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
8419 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
8420 out = SUBREG_REG (out), in = tem;
8422 /* How to do this reload can get quite tricky. Normally, we are being
8423 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8424 register that didn't get a hard register. In that case we can just
8425 call emit_move_insn.
8427 We can also be asked to reload a PLUS that adds a register or a MEM to
8428 another register, constant or MEM. This can occur during frame pointer
8429 elimination and while reloading addresses. This case is handled by
8430 trying to emit a single insn to perform the add. If it is not valid,
8431 we use a two insn sequence.
8433 Or we can be asked to reload an unary operand that was a fragment of
8434 an addressing mode, into a register. If it isn't recognized as-is,
8435 we try making the unop operand and the reload-register the same:
8436 (set reg:X (unop:X expr:Y))
8437 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8439 Finally, we could be called to handle an 'o' constraint by putting
8440 an address into a register. In that case, we first try to do this
8441 with a named pattern of "reload_load_address". If no such pattern
8442 exists, we just emit a SET insn and hope for the best (it will normally
8443 be valid on machines that use 'o').
8445 This entire process is made complex because reload will never
8446 process the insns we generate here and so we must ensure that
8447 they will fit their constraints and also by the fact that parts of
8448 IN might be being reloaded separately and replaced with spill registers.
8449 Because of this, we are, in some sense, just guessing the right approach
8450 here. The one listed above seems to work.
8452 ??? At some point, this whole thing needs to be rethought. */
8454 if (GET_CODE (in) == PLUS
8455 && (REG_P (XEXP (in, 0))
8456 || GET_CODE (XEXP (in, 0)) == SUBREG
8457 || MEM_P (XEXP (in, 0)))
8458 && (REG_P (XEXP (in, 1))
8459 || GET_CODE (XEXP (in, 1)) == SUBREG
8460 || CONSTANT_P (XEXP (in, 1))
8461 || MEM_P (XEXP (in, 1))))
8463 /* We need to compute the sum of a register or a MEM and another
8464 register, constant, or MEM, and put it into the reload
8465 register. The best possible way of doing this is if the machine
8466 has a three-operand ADD insn that accepts the required operands.
8468 The simplest approach is to try to generate such an insn and see if it
8469 is recognized and matches its constraints. If so, it can be used.
8471 It might be better not to actually emit the insn unless it is valid,
8472 but we need to pass the insn as an operand to `recog' and
8473 `extract_insn' and it is simpler to emit and then delete the insn if
8474 not valid than to dummy things up. */
8476 rtx op0, op1, tem, insn;
8479 op0 = find_replacement (&XEXP (in, 0));
8480 op1 = find_replacement (&XEXP (in, 1));
8482 /* Since constraint checking is strict, commutativity won't be
8483 checked, so we need to do that here to avoid spurious failure
8484 if the add instruction is two-address and the second operand
8485 of the add is the same as the reload reg, which is frequently
8486 the case. If the insn would be A = B + A, rearrange it so
8487 it will be A = A + B as constrain_operands expects. */
8489 if (REG_P (XEXP (in, 1))
8490 && REGNO (out) == REGNO (XEXP (in, 1)))
8491 tem = op0, op0 = op1, op1 = tem;
8493 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8494 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8496 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8500 /* If that failed, we must use a conservative two-insn sequence.
8502 Use a move to copy one operand into the reload register. Prefer
8503 to reload a constant, MEM or pseudo since the move patterns can
8504 handle an arbitrary operand. If OP1 is not a constant, MEM or
8505 pseudo and OP1 is not a valid operand for an add instruction, then
8508 After reloading one of the operands into the reload register, add
8509 the reload register to the output register.
8511 If there is another way to do this for a specific machine, a
8512 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8515 code = (int) optab_handler (add_optab, GET_MODE (out));
8517 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8519 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8520 || (code != CODE_FOR_nothing
8521 && ! ((*insn_data[code].operand[2].predicate)
8522 (op1, insn_data[code].operand[2].mode))))
8523 tem = op0, op0 = op1, op1 = tem;
8525 gen_reload (out, op0, opnum, type);
8527 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8528 This fixes a problem on the 32K where the stack pointer cannot
8529 be used as an operand of an add insn. */
8531 if (rtx_equal_p (op0, op1))
8534 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8537 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8538 set_unique_reg_note (insn, REG_EQUIV, in);
8542 /* If that failed, copy the address register to the reload register.
8543 Then add the constant to the reload register. */
8545 gcc_assert (!reg_overlap_mentioned_p (out, op0));
8546 gen_reload (out, op1, opnum, type);
8547 insn = emit_insn (gen_add2_insn (out, op0));
8548 set_unique_reg_note (insn, REG_EQUIV, in);
8551 #ifdef SECONDARY_MEMORY_NEEDED
8552 /* If we need a memory location to do the move, do it that way. */
8553 else if ((REG_P (in)
8554 || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))))
8555 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
8557 || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out))))
8558 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
8559 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
8560 REGNO_REG_CLASS (reg_or_subregno (out)),
8563 /* Get the memory to use and rewrite both registers to its mode. */
8564 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8566 if (GET_MODE (loc) != GET_MODE (out))
8567 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
8569 if (GET_MODE (loc) != GET_MODE (in))
8570 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
8572 gen_reload (loc, in, opnum, type);
8573 gen_reload (out, loc, opnum, type);
8576 else if (REG_P (out) && UNARY_P (in))
8583 op1 = find_replacement (&XEXP (in, 0));
8584 if (op1 != XEXP (in, 0))
8585 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8587 /* First, try a plain SET. */
8588 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8592 /* If that failed, move the inner operand to the reload
8593 register, and try the same unop with the inner expression
8594 replaced with the reload register. */
8596 if (GET_MODE (op1) != GET_MODE (out))
8597 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8601 gen_reload (out_moded, op1, opnum, type);
8604 = gen_rtx_SET (VOIDmode, out,
8605 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8607 insn = emit_insn_if_valid_for_reload (insn);
8610 set_unique_reg_note (insn, REG_EQUIV, in);
8614 fatal_insn ("Failure trying to reload:", set);
8616 /* If IN is a simple operand, use gen_move_insn. */
8617 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8619 tem = emit_insn (gen_move_insn (out, in));
8620 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8621 mark_jump_label (in, tem, 0);
8624 #ifdef HAVE_reload_load_address
8625 else if (HAVE_reload_load_address)
8626 emit_insn (gen_reload_load_address (out, in));
8629 /* Otherwise, just write (set OUT IN) and hope for the best. */
8631 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8633 /* Return the first insn emitted.
8634 We can not just return get_last_insn, because there may have
8635 been multiple instructions emitted. Also note that gen_move_insn may
8636 emit more than one insn itself, so we can not assume that there is one
8637 insn emitted per emit_insn_before call. */
8639 return last ? NEXT_INSN (last) : get_insns ();
8642 /* Delete a previously made output-reload whose result we now believe
8643 is not needed. First we double-check.
8645 INSN is the insn now being processed.
8646 LAST_RELOAD_REG is the hard register number for which we want to delete
8647 the last output reload.
8648 J is the reload-number that originally used REG. The caller has made
8649 certain that reload J doesn't use REG any longer for input.
8650 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8653 delete_output_reload (rtx insn, int j, int last_reload_reg, rtx new_reload_reg)
8655 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8656 rtx reg = spill_reg_stored_to[last_reload_reg];
8659 int n_inherited = 0;
8665 /* It is possible that this reload has been only used to set another reload
8666 we eliminated earlier and thus deleted this instruction too. */
8667 if (INSN_DELETED_P (output_reload_insn))
8670 /* Get the raw pseudo-register referred to. */
8672 while (GET_CODE (reg) == SUBREG)
8673 reg = SUBREG_REG (reg);
8674 substed = reg_equiv_memory_loc[REGNO (reg)];
8676 /* This is unsafe if the operand occurs more often in the current
8677 insn than it is inherited. */
8678 for (k = n_reloads - 1; k >= 0; k--)
8680 rtx reg2 = rld[k].in;
8683 if (MEM_P (reg2) || reload_override_in[k])
8684 reg2 = rld[k].in_reg;
8686 if (rld[k].out && ! rld[k].out_reg)
8687 reg2 = XEXP (rld[k].in_reg, 0);
8689 while (GET_CODE (reg2) == SUBREG)
8690 reg2 = SUBREG_REG (reg2);
8691 if (rtx_equal_p (reg2, reg))
8693 if (reload_inherited[k] || reload_override_in[k] || k == j)
8699 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8700 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8701 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8704 n_occurrences += count_occurrences (PATTERN (insn),
8705 eliminate_regs (substed, VOIDmode,
8707 for (i1 = reg_equiv_alt_mem_list[REGNO (reg)]; i1; i1 = XEXP (i1, 1))
8709 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8710 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8712 if (n_occurrences > n_inherited)
8715 regno = REGNO (reg);
8716 if (regno >= FIRST_PSEUDO_REGISTER)
8719 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
8721 /* If the pseudo-reg we are reloading is no longer referenced
8722 anywhere between the store into it and here,
8723 and we're within the same basic block, then the value can only
8724 pass through the reload reg and end up here.
8725 Otherwise, give up--return. */
8726 for (i1 = NEXT_INSN (output_reload_insn);
8727 i1 != insn; i1 = NEXT_INSN (i1))
8729 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8731 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8732 && refers_to_regno_p (regno, regno + nregs, PATTERN (i1), NULL))
8734 /* If this is USE in front of INSN, we only have to check that
8735 there are no more references than accounted for by inheritance. */
8736 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8738 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8739 i1 = NEXT_INSN (i1);
8741 if (n_occurrences <= n_inherited && i1 == insn)
8747 /* We will be deleting the insn. Remove the spill reg information. */
8748 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8750 spill_reg_store[last_reload_reg + k] = 0;
8751 spill_reg_stored_to[last_reload_reg + k] = 0;
8754 /* The caller has already checked that REG dies or is set in INSN.
8755 It has also checked that we are optimizing, and thus some
8756 inaccuracies in the debugging information are acceptable.
8757 So we could just delete output_reload_insn. But in some cases
8758 we can improve the debugging information without sacrificing
8759 optimization - maybe even improving the code: See if the pseudo
8760 reg has been completely replaced with reload regs. If so, delete
8761 the store insn and forget we had a stack slot for the pseudo. */
8762 if (rld[j].out != rld[j].in
8763 && REG_N_DEATHS (REGNO (reg)) == 1
8764 && REG_N_SETS (REGNO (reg)) == 1
8765 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8766 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8770 /* We know that it was used only between here and the beginning of
8771 the current basic block. (We also know that the last use before
8772 INSN was the output reload we are thinking of deleting, but never
8773 mind that.) Search that range; see if any ref remains. */
8774 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8776 rtx set = single_set (i2);
8778 /* Uses which just store in the pseudo don't count,
8779 since if they are the only uses, they are dead. */
8780 if (set != 0 && SET_DEST (set) == reg)
8785 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8786 && reg_mentioned_p (reg, PATTERN (i2)))
8788 /* Some other ref remains; just delete the output reload we
8790 delete_address_reloads (output_reload_insn, insn);
8791 delete_insn (output_reload_insn);
8796 /* Delete the now-dead stores into this pseudo. Note that this
8797 loop also takes care of deleting output_reload_insn. */
8798 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8800 rtx set = single_set (i2);
8802 if (set != 0 && SET_DEST (set) == reg)
8804 delete_address_reloads (i2, insn);
8812 /* For the debugging info, say the pseudo lives in this reload reg. */
8813 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8814 if (ira_conflicts_p)
8815 /* Inform IRA about the change. */
8816 ira_mark_allocation_change (REGNO (reg));
8817 alter_reg (REGNO (reg), -1, false);
8821 delete_address_reloads (output_reload_insn, insn);
8822 delete_insn (output_reload_insn);
8826 /* We are going to delete DEAD_INSN. Recursively delete loads of
8827 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8828 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8830 delete_address_reloads (rtx dead_insn, rtx current_insn)
8832 rtx set = single_set (dead_insn);
8833 rtx set2, dst, prev, next;
8836 rtx dst = SET_DEST (set);
8838 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8840 /* If we deleted the store from a reloaded post_{in,de}c expression,
8841 we can delete the matching adds. */
8842 prev = PREV_INSN (dead_insn);
8843 next = NEXT_INSN (dead_insn);
8844 if (! prev || ! next)
8846 set = single_set (next);
8847 set2 = single_set (prev);
8849 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8850 || !CONST_INT_P (XEXP (SET_SRC (set), 1))
8851 || !CONST_INT_P (XEXP (SET_SRC (set2), 1)))
8853 dst = SET_DEST (set);
8854 if (! rtx_equal_p (dst, SET_DEST (set2))
8855 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8856 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8857 || (INTVAL (XEXP (SET_SRC (set), 1))
8858 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8860 delete_related_insns (prev);
8861 delete_related_insns (next);
8864 /* Subfunction of delete_address_reloads: process registers found in X. */
8866 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8868 rtx prev, set, dst, i2;
8870 enum rtx_code code = GET_CODE (x);
8874 const char *fmt = GET_RTX_FORMAT (code);
8875 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8878 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8879 else if (fmt[i] == 'E')
8881 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8882 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8889 if (spill_reg_order[REGNO (x)] < 0)
8892 /* Scan backwards for the insn that sets x. This might be a way back due
8894 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8896 code = GET_CODE (prev);
8897 if (code == CODE_LABEL || code == JUMP_INSN)
8901 if (reg_set_p (x, PATTERN (prev)))
8903 if (reg_referenced_p (x, PATTERN (prev)))
8906 if (! prev || INSN_UID (prev) < reload_first_uid)
8908 /* Check that PREV only sets the reload register. */
8909 set = single_set (prev);
8912 dst = SET_DEST (set);
8914 || ! rtx_equal_p (dst, x))
8916 if (! reg_set_p (dst, PATTERN (dead_insn)))
8918 /* Check if DST was used in a later insn -
8919 it might have been inherited. */
8920 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8926 if (reg_referenced_p (dst, PATTERN (i2)))
8928 /* If there is a reference to the register in the current insn,
8929 it might be loaded in a non-inherited reload. If no other
8930 reload uses it, that means the register is set before
8932 if (i2 == current_insn)
8934 for (j = n_reloads - 1; j >= 0; j--)
8935 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8936 || reload_override_in[j] == dst)
8938 for (j = n_reloads - 1; j >= 0; j--)
8939 if (rld[j].in && rld[j].reg_rtx == dst)
8948 /* If DST is still live at CURRENT_INSN, check if it is used for
8949 any reload. Note that even if CURRENT_INSN sets DST, we still
8950 have to check the reloads. */
8951 if (i2 == current_insn)
8953 for (j = n_reloads - 1; j >= 0; j--)
8954 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8955 || reload_override_in[j] == dst)
8957 /* ??? We can't finish the loop here, because dst might be
8958 allocated to a pseudo in this block if no reload in this
8959 block needs any of the classes containing DST - see
8960 spill_hard_reg. There is no easy way to tell this, so we
8961 have to scan till the end of the basic block. */
8963 if (reg_set_p (dst, PATTERN (i2)))
8967 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8968 reg_reloaded_contents[REGNO (dst)] = -1;
8972 /* Output reload-insns to reload VALUE into RELOADREG.
8973 VALUE is an autoincrement or autodecrement RTX whose operand
8974 is a register or memory location;
8975 so reloading involves incrementing that location.
8976 IN is either identical to VALUE, or some cheaper place to reload from.
8978 INC_AMOUNT is the number to increment or decrement by (always positive).
8979 This cannot be deduced from VALUE.
8981 Return the instruction that stores into RELOADREG. */
8984 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8986 /* REG or MEM to be copied and incremented. */
8987 rtx incloc = find_replacement (&XEXP (value, 0));
8988 /* Nonzero if increment after copying. */
8989 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8990 || GET_CODE (value) == POST_MODIFY);
8996 rtx real_in = in == value ? incloc : in;
8998 /* No hard register is equivalent to this register after
8999 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
9000 we could inc/dec that register as well (maybe even using it for
9001 the source), but I'm not sure it's worth worrying about. */
9003 reg_last_reload_reg[REGNO (incloc)] = 0;
9005 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
9007 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
9008 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
9012 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
9013 inc_amount = -inc_amount;
9015 inc = GEN_INT (inc_amount);
9018 /* If this is post-increment, first copy the location to the reload reg. */
9019 if (post && real_in != reloadreg)
9020 emit_insn (gen_move_insn (reloadreg, real_in));
9024 /* See if we can directly increment INCLOC. Use a method similar to
9025 that in gen_reload. */
9027 last = get_last_insn ();
9028 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
9029 gen_rtx_PLUS (GET_MODE (incloc),
9032 code = recog_memoized (add_insn);
9035 extract_insn (add_insn);
9036 if (constrain_operands (1))
9038 /* If this is a pre-increment and we have incremented the value
9039 where it lives, copy the incremented value to RELOADREG to
9040 be used as an address. */
9043 emit_insn (gen_move_insn (reloadreg, incloc));
9048 delete_insns_since (last);
9051 /* If couldn't do the increment directly, must increment in RELOADREG.
9052 The way we do this depends on whether this is pre- or post-increment.
9053 For pre-increment, copy INCLOC to the reload register, increment it
9054 there, then save back. */
9058 if (in != reloadreg)
9059 emit_insn (gen_move_insn (reloadreg, real_in));
9060 emit_insn (gen_add2_insn (reloadreg, inc));
9061 store = emit_insn (gen_move_insn (incloc, reloadreg));
9066 Because this might be a jump insn or a compare, and because RELOADREG
9067 may not be available after the insn in an input reload, we must do
9068 the incrementation before the insn being reloaded for.
9070 We have already copied IN to RELOADREG. Increment the copy in
9071 RELOADREG, save that back, then decrement RELOADREG so it has
9072 the original value. */
9074 emit_insn (gen_add2_insn (reloadreg, inc));
9075 store = emit_insn (gen_move_insn (incloc, reloadreg));
9076 if (CONST_INT_P (inc))
9077 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
9079 emit_insn (gen_sub2_insn (reloadreg, inc));
9087 add_auto_inc_notes (rtx insn, rtx x)
9089 enum rtx_code code = GET_CODE (x);
9093 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9095 add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
9099 /* Scan all the operand sub-expressions. */
9100 fmt = GET_RTX_FORMAT (code);
9101 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9104 add_auto_inc_notes (insn, XEXP (x, i));
9105 else if (fmt[i] == 'E')
9106 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9107 add_auto_inc_notes (insn, XVECEXP (x, i, j));
9112 /* This is used by reload pass, that does emit some instructions after
9113 abnormal calls moving basic block end, but in fact it wants to emit
9114 them on the edge. Looks for abnormal call edges, find backward the
9115 proper call and fix the damage.
9117 Similar handle instructions throwing exceptions internally. */
9119 fixup_abnormal_edges (void)
9121 bool inserted = false;
9129 /* Look for cases we are interested in - calls or instructions causing
9131 FOR_EACH_EDGE (e, ei, bb->succs)
9133 if (e->flags & EDGE_ABNORMAL_CALL)
9135 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
9136 == (EDGE_ABNORMAL | EDGE_EH))
9139 if (e && !CALL_P (BB_END (bb))
9140 && !can_throw_internal (BB_END (bb)))
9144 /* Get past the new insns generated. Allow notes, as the insns
9145 may be already deleted. */
9147 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
9148 && !can_throw_internal (insn)
9149 && insn != BB_HEAD (bb))
9150 insn = PREV_INSN (insn);
9152 if (CALL_P (insn) || can_throw_internal (insn))
9156 stop = NEXT_INSN (BB_END (bb));
9158 insn = NEXT_INSN (insn);
9160 FOR_EACH_EDGE (e, ei, bb->succs)
9161 if (e->flags & EDGE_FALLTHRU)
9164 while (insn && insn != stop)
9166 next = NEXT_INSN (insn);
9171 /* Sometimes there's still the return value USE.
9172 If it's placed after a trapping call (i.e. that
9173 call is the last insn anyway), we have no fallthru
9174 edge. Simply delete this use and don't try to insert
9175 on the non-existent edge. */
9176 if (GET_CODE (PATTERN (insn)) != USE)
9178 /* We're not deleting it, we're moving it. */
9179 INSN_DELETED_P (insn) = 0;
9180 PREV_INSN (insn) = NULL_RTX;
9181 NEXT_INSN (insn) = NULL_RTX;
9183 insert_insn_on_edge (insn, e);
9187 else if (!BARRIER_P (insn))
9188 set_block_for_insn (insn, NULL);
9193 /* It may be that we don't find any such trapping insn. In this
9194 case we discovered quite late that the insn that had been
9195 marked as can_throw_internal in fact couldn't trap at all.
9196 So we should in fact delete the EH edges out of the block. */
9198 purge_dead_edges (bb);
9202 /* We've possibly turned single trapping insn into multiple ones. */
9203 if (cfun->can_throw_non_call_exceptions)
9206 blocks = sbitmap_alloc (last_basic_block);
9207 sbitmap_ones (blocks);
9208 find_many_sub_basic_blocks (blocks);
9209 sbitmap_free (blocks);
9213 commit_edge_insertions ();
9215 #ifdef ENABLE_CHECKING
9216 /* Verify that we didn't turn one trapping insn into many, and that
9217 we found and corrected all of the problems wrt fixups on the
9219 verify_flow_info ();
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