1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996
3 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 /* This file contains two passes of the compiler: reg_scan and reg_class.
24 It also defines some tables of information about the hardware registers
25 and a function init_reg_sets to initialize the tables. */
31 #include "hard-reg-set.h"
33 #include "basic-block.h"
36 #include "insn-config.h"
44 #ifndef REGISTER_MOVE_COST
45 #define REGISTER_MOVE_COST(x, y) 2
48 static void init_reg_sets_1 PARAMS ((void));
49 static void init_reg_modes PARAMS ((void));
51 /* If we have auto-increment or auto-decrement and we can have secondary
52 reloads, we are not allowed to use classes requiring secondary
53 reloads for pseudos auto-incremented since reload can't handle it. */
56 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
57 #define FORBIDDEN_INC_DEC_CLASSES
61 /* Register tables used by many passes. */
63 /* Indexed by hard register number, contains 1 for registers
64 that are fixed use (stack pointer, pc, frame pointer, etc.).
65 These are the registers that cannot be used to allocate
66 a pseudo reg for general use. */
68 char fixed_regs[FIRST_PSEUDO_REGISTER];
70 /* Same info as a HARD_REG_SET. */
72 HARD_REG_SET fixed_reg_set;
74 /* Data for initializing the above. */
76 static char initial_fixed_regs[] = FIXED_REGISTERS;
78 /* Indexed by hard register number, contains 1 for registers
79 that are fixed use or are clobbered by function calls.
80 These are the registers that cannot be used to allocate
81 a pseudo reg whose life crosses calls unless we are able
82 to save/restore them across the calls. */
84 char call_used_regs[FIRST_PSEUDO_REGISTER];
86 /* Same info as a HARD_REG_SET. */
88 HARD_REG_SET call_used_reg_set;
90 /* HARD_REG_SET of registers we want to avoid caller saving. */
91 HARD_REG_SET losing_caller_save_reg_set;
93 /* Data for initializing the above. */
95 static char initial_call_used_regs[] = CALL_USED_REGISTERS;
97 /* Indexed by hard register number, contains 1 for registers that are
98 fixed use or call used registers that cannot hold quantities across
99 calls even if we are willing to save and restore them. call fixed
100 registers are a subset of call used registers. */
102 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
104 /* The same info as a HARD_REG_SET. */
106 HARD_REG_SET call_fixed_reg_set;
108 /* Number of non-fixed registers. */
110 int n_non_fixed_regs;
112 /* Indexed by hard register number, contains 1 for registers
113 that are being used for global register decls.
114 These must be exempt from ordinary flow analysis
115 and are also considered fixed. */
117 char global_regs[FIRST_PSEUDO_REGISTER];
119 /* Table of register numbers in the order in which to try to use them. */
120 #ifdef REG_ALLOC_ORDER
121 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
123 /* The inverse of reg_alloc_order. */
124 int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER];
127 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
129 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
131 /* The same information, but as an array of unsigned ints. We copy from
132 these unsigned ints to the table above. We do this so the tm.h files
133 do not have to be aware of the wordsize for machines with <= 64 regs. */
136 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
138 static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
139 = REG_CLASS_CONTENTS;
141 /* For each reg class, number of regs it contains. */
143 unsigned int reg_class_size[N_REG_CLASSES];
145 /* For each reg class, table listing all the containing classes. */
147 enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
149 /* For each reg class, table listing all the classes contained in it. */
151 enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
153 /* For each pair of reg classes,
154 a largest reg class contained in their union. */
156 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
158 /* For each pair of reg classes,
159 the smallest reg class containing their union. */
161 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
163 /* Array containing all of the register names. Unless
164 DEBUG_REGISTER_NAMES is defined, use the copy in print-rtl.c. */
166 #ifdef DEBUG_REGISTER_NAMES
167 const char * reg_names[] = REGISTER_NAMES;
170 /* For each hard register, the widest mode object that it can contain.
171 This will be a MODE_INT mode if the register can hold integers. Otherwise
172 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
175 enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER];
177 /* Maximum cost of moving from a register in one class to a register in
178 another class. Based on REGISTER_MOVE_COST. */
180 static int move_cost[N_REG_CLASSES][N_REG_CLASSES];
182 /* Similar, but here we don't have to move if the first index is a subset
183 of the second so in that case the cost is zero. */
185 static int may_move_in_cost[N_REG_CLASSES][N_REG_CLASSES];
187 /* Similar, but here we don't have to move if the first index is a superset
188 of the second so in that case the cost is zero. */
190 static int may_move_out_cost[N_REG_CLASSES][N_REG_CLASSES];
192 #ifdef FORBIDDEN_INC_DEC_CLASSES
194 /* These are the classes that regs which are auto-incremented or decremented
197 static int forbidden_inc_dec_class[N_REG_CLASSES];
199 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
202 static char *in_inc_dec;
204 #endif /* FORBIDDEN_INC_DEC_CLASSES */
206 #ifdef CLASS_CANNOT_CHANGE_SIZE
208 /* These are the classes containing only registers that can be used in
209 a SUBREG expression that changes the size of the register. */
211 static int class_can_change_size[N_REG_CLASSES];
213 /* Registers, including pseudos, which change size. */
215 static regset reg_changes_size;
217 #endif /* CLASS_CANNOT_CHANGE_SIZE */
219 #ifdef HAVE_SECONDARY_RELOADS
221 /* Sample MEM values for use by memory_move_secondary_cost. */
223 static rtx top_of_stack[MAX_MACHINE_MODE];
225 #endif /* HAVE_SECONDARY_RELOADS */
227 /* Linked list of reg_info structures allocated for reg_n_info array.
228 Grouping all of the allocated structures together in one lump
229 means only one call to bzero to clear them, rather than n smaller
231 struct reg_info_data {
232 struct reg_info_data *next; /* next set of reg_info structures */
233 size_t min_index; /* minimum index # */
234 size_t max_index; /* maximum index # */
235 char used_p; /* non-zero if this has been used previously */
236 reg_info data[1]; /* beginning of the reg_info data */
239 static struct reg_info_data *reg_info_head;
241 /* No more global register variables may be declared; true once
242 regclass has been initialized. */
244 static int no_global_reg_vars = 0;
247 /* Function called only once to initialize the above data on reg usage.
248 Once this is done, various switches may override. */
255 /* First copy the register information from the initial int form into
258 for (i = 0; i < N_REG_CLASSES; i++)
260 CLEAR_HARD_REG_SET (reg_class_contents[i]);
262 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
263 if (int_reg_class_contents[i][j / HOST_BITS_PER_INT]
264 & ((unsigned) 1 << (j % HOST_BITS_PER_INT)))
265 SET_HARD_REG_BIT (reg_class_contents[i], j);
268 bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs);
269 bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs);
270 bzero (global_regs, sizeof global_regs);
272 /* Do any additional initialization regsets may need */
273 INIT_ONCE_REG_SET ();
275 #ifdef REG_ALLOC_ORDER
276 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
277 inv_reg_alloc_order[reg_alloc_order[i]] = i;
281 /* After switches have been processed, which perhaps alter
282 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
287 register unsigned int i, j;
289 /* This macro allows the fixed or call-used registers
290 and the register classes to depend on target flags. */
292 #ifdef CONDITIONAL_REGISTER_USAGE
293 CONDITIONAL_REGISTER_USAGE;
296 /* Compute number of hard regs in each class. */
298 bzero ((char *) reg_class_size, sizeof reg_class_size);
299 for (i = 0; i < N_REG_CLASSES; i++)
300 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
301 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
304 /* Initialize the table of subunions.
305 reg_class_subunion[I][J] gets the largest-numbered reg-class
306 that is contained in the union of classes I and J. */
308 for (i = 0; i < N_REG_CLASSES; i++)
310 for (j = 0; j < N_REG_CLASSES; j++)
313 register /* Declare it register if it's a scalar. */
318 COPY_HARD_REG_SET (c, reg_class_contents[i]);
319 IOR_HARD_REG_SET (c, reg_class_contents[j]);
320 for (k = 0; k < N_REG_CLASSES; k++)
322 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
327 /* keep the largest subclass */ /* SPEE 900308 */
328 GO_IF_HARD_REG_SUBSET (reg_class_contents[k],
329 reg_class_contents[(int) reg_class_subunion[i][j]],
331 reg_class_subunion[i][j] = (enum reg_class) k;
338 /* Initialize the table of superunions.
339 reg_class_superunion[I][J] gets the smallest-numbered reg-class
340 containing the union of classes I and J. */
342 for (i = 0; i < N_REG_CLASSES; i++)
344 for (j = 0; j < N_REG_CLASSES; j++)
347 register /* Declare it register if it's a scalar. */
352 COPY_HARD_REG_SET (c, reg_class_contents[i]);
353 IOR_HARD_REG_SET (c, reg_class_contents[j]);
354 for (k = 0; k < N_REG_CLASSES; k++)
355 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass);
358 reg_class_superunion[i][j] = (enum reg_class) k;
362 /* Initialize the tables of subclasses and superclasses of each reg class.
363 First clear the whole table, then add the elements as they are found. */
365 for (i = 0; i < N_REG_CLASSES; i++)
367 for (j = 0; j < N_REG_CLASSES; j++)
369 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
370 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
374 for (i = 0; i < N_REG_CLASSES; i++)
376 if (i == (int) NO_REGS)
379 for (j = i + 1; j < N_REG_CLASSES; j++)
383 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
387 /* Reg class I is a subclass of J.
388 Add J to the table of superclasses of I. */
389 p = ®_class_superclasses[i][0];
390 while (*p != LIM_REG_CLASSES) p++;
391 *p = (enum reg_class) j;
392 /* Add I to the table of superclasses of J. */
393 p = ®_class_subclasses[j][0];
394 while (*p != LIM_REG_CLASSES) p++;
395 *p = (enum reg_class) i;
399 /* Initialize "constant" tables. */
401 CLEAR_HARD_REG_SET (fixed_reg_set);
402 CLEAR_HARD_REG_SET (call_used_reg_set);
403 CLEAR_HARD_REG_SET (call_fixed_reg_set);
405 bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs);
407 n_non_fixed_regs = 0;
409 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
412 SET_HARD_REG_BIT (fixed_reg_set, i);
416 if (call_used_regs[i])
417 SET_HARD_REG_BIT (call_used_reg_set, i);
418 if (call_fixed_regs[i])
419 SET_HARD_REG_BIT (call_fixed_reg_set, i);
420 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i)))
421 SET_HARD_REG_BIT (losing_caller_save_reg_set, i);
424 /* Initialize the move cost table. Find every subset of each class
425 and take the maximum cost of moving any subset to any other. */
427 for (i = 0; i < N_REG_CLASSES; i++)
428 for (j = 0; j < N_REG_CLASSES; j++)
430 int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j);
431 enum reg_class *p1, *p2;
433 for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++)
435 cost = MAX (cost, REGISTER_MOVE_COST (i, *p2));
437 for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++)
440 cost = MAX (cost, REGISTER_MOVE_COST (*p1, j));
442 for (p2 = ®_class_subclasses[j][0];
443 *p2 != LIM_REG_CLASSES; p2++)
445 cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2));
448 move_cost[i][j] = cost;
450 if (reg_class_subset_p (i, j))
451 may_move_in_cost[i][j] = 0;
453 may_move_in_cost[i][j] = cost;
455 if (reg_class_subset_p (j, i))
456 may_move_out_cost[i][j] = 0;
458 may_move_out_cost[i][j] = cost;
461 #ifdef CLASS_CANNOT_CHANGE_SIZE
464 COMPL_HARD_REG_SET (c, reg_class_contents[CLASS_CANNOT_CHANGE_SIZE]);
466 for (i = 0; i < N_REG_CLASSES; i++)
468 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], c, ok_class);
469 class_can_change_size [i] = 0;
472 class_can_change_size [i] = 1;
475 #endif /* CLASS_CANNOT_CHANGE_SIZE */
478 /* Compute the table of register modes.
479 These values are used to record death information for individual registers
480 (as opposed to a multi-register mode). */
487 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
489 reg_raw_mode[i] = choose_hard_reg_mode (i, 1);
491 /* If we couldn't find a valid mode, just use the previous mode.
492 ??? One situation in which we need to do this is on the mips where
493 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
494 to use DF mode for the even registers and VOIDmode for the odd
495 (for the cpu models where the odd ones are inaccessible). */
496 if (reg_raw_mode[i] == VOIDmode)
497 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1];
501 /* Finish initializing the register sets and
502 initialize the register modes. */
507 /* This finishes what was started by init_reg_sets, but couldn't be done
508 until after register usage was specified. */
513 #ifdef HAVE_SECONDARY_RELOADS
515 /* Make some fake stack-frame MEM references for use in
516 memory_move_secondary_cost. */
518 for (i = 0; i < MAX_MACHINE_MODE; i++)
519 top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx);
520 ggc_add_rtx_root (top_of_stack, MAX_MACHINE_MODE);
525 #ifdef HAVE_SECONDARY_RELOADS
527 /* Compute extra cost of moving registers to/from memory due to reloads.
528 Only needed if secondary reloads are required for memory moves. */
531 memory_move_secondary_cost (mode, class, in)
532 enum machine_mode mode;
533 enum reg_class class;
536 enum reg_class altclass;
537 int partial_cost = 0;
538 /* We need a memory reference to feed to SECONDARY... macros. */
539 /* mem may be unused even if the SECONDARY_ macros are defined. */
540 rtx mem ATTRIBUTE_UNUSED = top_of_stack[(int) mode];
545 #ifdef SECONDARY_INPUT_RELOAD_CLASS
546 altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem);
553 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
554 altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem);
560 if (altclass == NO_REGS)
564 partial_cost = REGISTER_MOVE_COST (altclass, class);
566 partial_cost = REGISTER_MOVE_COST (class, altclass);
568 if (class == altclass)
569 /* This isn't simply a copy-to-temporary situation. Can't guess
570 what it is, so MEMORY_MOVE_COST really ought not to be calling
573 I'm tempted to put in an abort here, but returning this will
574 probably only give poor estimates, which is what we would've
575 had before this code anyways. */
578 /* Check if the secondary reload register will also need a
580 return memory_move_secondary_cost (mode, altclass, in) + partial_cost;
584 /* Return a machine mode that is legitimate for hard reg REGNO and large
585 enough to save nregs. If we can't find one, return VOIDmode. */
588 choose_hard_reg_mode (regno, nregs)
589 unsigned int regno ATTRIBUTE_UNUSED;
592 enum machine_mode found_mode = VOIDmode, mode;
594 /* We first look for the largest integer mode that can be validly
595 held in REGNO. If none, we look for the largest floating-point mode.
596 If we still didn't find a valid mode, try CCmode. */
598 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
600 mode = GET_MODE_WIDER_MODE (mode))
601 if (HARD_REGNO_NREGS (regno, mode) == nregs
602 && HARD_REGNO_MODE_OK (regno, mode))
605 if (found_mode != VOIDmode)
608 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
610 mode = GET_MODE_WIDER_MODE (mode))
611 if (HARD_REGNO_NREGS (regno, mode) == nregs
612 && HARD_REGNO_MODE_OK (regno, mode))
615 if (found_mode != VOIDmode)
618 if (HARD_REGNO_NREGS (regno, CCmode) == nregs
619 && HARD_REGNO_MODE_OK (regno, CCmode))
622 /* We can't find a mode valid for this register. */
626 /* Specify the usage characteristics of the register named NAME.
627 It should be a fixed register if FIXED and a
628 call-used register if CALL_USED. */
631 fix_register (name, fixed, call_used)
633 int fixed, call_used;
637 /* Decode the name and update the primary form of
638 the register info. */
640 if ((i = decode_reg_name (name)) >= 0)
642 if ((i == STACK_POINTER_REGNUM
643 #ifdef HARD_FRAME_POINTER_REGNUM
644 || i == HARD_FRAME_POINTER_REGNUM
646 || i == FRAME_POINTER_REGNUM
649 && (fixed == 0 || call_used == 0))
651 static const char * const what_option[2][2] = {
652 { "call-saved", "call-used" },
653 { "no-such-option", "fixed" }};
655 error ("can't use '%s' as a %s register", name,
656 what_option[fixed][call_used]);
660 fixed_regs[i] = fixed;
661 call_used_regs[i] = call_used;
666 warning ("unknown register name: %s", name);
670 /* Mark register number I as global. */
676 if (fixed_regs[i] == 0 && no_global_reg_vars)
677 error ("global register variable follows a function definition");
681 warning ("register used for two global register variables");
685 if (call_used_regs[i] && ! fixed_regs[i])
686 warning ("call-clobbered register used for global register variable");
690 /* If already fixed, nothing else to do. */
694 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
697 SET_HARD_REG_BIT (fixed_reg_set, i);
698 SET_HARD_REG_BIT (call_used_reg_set, i);
699 SET_HARD_REG_BIT (call_fixed_reg_set, i);
702 /* Now the data and code for the `regclass' pass, which happens
703 just before local-alloc. */
705 /* The `costs' struct records the cost of using a hard register of each class
706 and of using memory for each pseudo. We use this data to set up
707 register class preferences. */
711 int cost[N_REG_CLASSES];
715 /* Structure used to record preferrences of given pseudo. */
718 /* (enum reg_class) prefclass is the preferred class. */
721 /* altclass is a register class that we should use for allocating
722 pseudo if no register in the preferred class is available.
723 If no register in this class is available, memory is preferred.
725 It might appear to be more general to have a bitmask of classes here,
726 but since it is recommended that there be a class corresponding to the
727 union of most major pair of classes, that generality is not required. */
731 /* Record the cost of each class for each pseudo. */
733 static struct costs *costs;
735 /* Initialized once, and used to initialize cost values for each insn. */
737 static struct costs init_cost;
739 /* Record preferrences of each pseudo.
740 This is available after `regclass' is run. */
742 static struct reg_pref *reg_pref;
744 /* Allocated buffers for reg_pref. */
746 static struct reg_pref *reg_pref_buffer;
748 /* Account for the fact that insns within a loop are executed very commonly,
749 but don't keep doing this as loops go too deep. */
751 static int loop_cost;
753 static rtx scan_one_insn PARAMS ((rtx, int));
754 static void record_operand_costs PARAMS ((rtx, struct costs *, struct reg_pref *));
755 static void dump_regclass PARAMS ((FILE *));
756 static void record_reg_classes PARAMS ((int, int, rtx *, enum machine_mode *,
758 struct costs *, struct reg_pref *));
759 static int copy_cost PARAMS ((rtx, enum machine_mode,
760 enum reg_class, int));
761 static void record_address_regs PARAMS ((rtx, enum reg_class, int));
762 #ifdef FORBIDDEN_INC_DEC_CLASSES
763 static int auto_inc_dec_reg_p PARAMS ((rtx, enum machine_mode));
765 static void reg_scan_mark_refs PARAMS ((rtx, rtx, int, unsigned int));
767 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
768 This function is sometimes called before the info has been computed.
769 When that happens, just return GENERAL_REGS, which is innocuous. */
772 reg_preferred_class (regno)
777 return (enum reg_class) reg_pref[regno].prefclass;
781 reg_alternate_class (regno)
787 return (enum reg_class) reg_pref[regno].altclass;
790 /* Initialize some global data for this pass. */
797 init_cost.mem_cost = 10000;
798 for (i = 0; i < N_REG_CLASSES; i++)
799 init_cost.cost[i] = 10000;
801 /* This prevents dump_flow_info from losing if called
802 before regclass is run. */
805 /* No more global register variables may be declared. */
806 no_global_reg_vars = 1;
809 /* Dump register costs. */
814 static const char *const reg_class_names[] = REG_CLASS_NAMES;
816 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
818 enum reg_class class;
821 fprintf (dump, " Register %i costs:", i);
822 for (class = 0; class < N_REG_CLASSES; class++)
823 fprintf (dump, " %s:%i", reg_class_names[(int) class],
824 costs[i].cost[class]);
825 fprintf (dump, " MEM:%i\n", costs[i].mem_cost);
831 /* Calculate the costs of insn operands. */
834 record_operand_costs (insn, op_costs, reg_pref)
836 struct costs *op_costs;
837 struct reg_pref *reg_pref;
839 const char *constraints[MAX_RECOG_OPERANDS];
840 enum machine_mode modes[MAX_RECOG_OPERANDS];
843 for (i = 0; i < recog_data.n_operands; i++)
845 constraints[i] = recog_data.constraints[i];
846 modes[i] = recog_data.operand_mode[i];
849 /* If we get here, we are set up to record the costs of all the
850 operands for this insn. Start by initializing the costs.
851 Then handle any address registers. Finally record the desired
852 classes for any pseudos, doing it twice if some pair of
853 operands are commutative. */
855 for (i = 0; i < recog_data.n_operands; i++)
857 op_costs[i] = init_cost;
859 if (GET_CODE (recog_data.operand[i]) == SUBREG)
861 rtx inner = SUBREG_REG (recog_data.operand[i]);
862 if (GET_MODE_SIZE (modes[i]) != GET_MODE_SIZE (GET_MODE (inner))
863 && GET_CODE (inner) == REG)
864 SET_REGNO_REG_SET (reg_changes_size, REGNO (inner));
865 recog_data.operand[i] = inner;
868 if (GET_CODE (recog_data.operand[i]) == MEM)
869 record_address_regs (XEXP (recog_data.operand[i], 0),
870 BASE_REG_CLASS, loop_cost * 2);
871 else if (constraints[i][0] == 'p')
872 record_address_regs (recog_data.operand[i],
873 BASE_REG_CLASS, loop_cost * 2);
876 /* Check for commutative in a separate loop so everything will
877 have been initialized. We must do this even if one operand
878 is a constant--see addsi3 in m68k.md. */
880 for (i = 0; i < (int) recog_data.n_operands - 1; i++)
881 if (constraints[i][0] == '%')
883 const char *xconstraints[MAX_RECOG_OPERANDS];
886 /* Handle commutative operands by swapping the constraints.
887 We assume the modes are the same. */
889 for (j = 0; j < recog_data.n_operands; j++)
890 xconstraints[j] = constraints[j];
892 xconstraints[i] = constraints[i+1];
893 xconstraints[i+1] = constraints[i];
894 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
895 recog_data.operand, modes,
896 xconstraints, insn, op_costs, reg_pref);
899 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
900 recog_data.operand, modes,
901 constraints, insn, op_costs, reg_pref);
904 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
905 time it would save code to put a certain register in a certain class.
906 PASS, when nonzero, inhibits some optimizations which need only be done
908 Return the last insn processed, so that the scan can be continued from
912 scan_one_insn (insn, pass)
916 enum rtx_code code = GET_CODE (insn);
917 enum rtx_code pat_code;
920 struct costs op_costs[MAX_RECOG_OPERANDS];
922 if (GET_RTX_CLASS (code) != 'i')
925 pat_code = GET_CODE (PATTERN (insn));
927 || pat_code == CLOBBER
928 || pat_code == ASM_INPUT
929 || pat_code == ADDR_VEC
930 || pat_code == ADDR_DIFF_VEC)
933 set = single_set (insn);
936 /* If this insn loads a parameter from its stack slot, then
937 it represents a savings, rather than a cost, if the
938 parameter is stored in memory. Record this fact. */
940 if (set != 0 && GET_CODE (SET_DEST (set)) == REG
941 && GET_CODE (SET_SRC (set)) == MEM
942 && (note = find_reg_note (insn, REG_EQUIV,
944 && GET_CODE (XEXP (note, 0)) == MEM)
946 costs[REGNO (SET_DEST (set))].mem_cost
947 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)),
950 record_address_regs (XEXP (SET_SRC (set), 0),
951 BASE_REG_CLASS, loop_cost * 2);
955 /* Improve handling of two-address insns such as
956 (set X (ashift CONST Y)) where CONST must be made to
957 match X. Change it into two insns: (set X CONST)
958 (set X (ashift X Y)). If we left this for reloading, it
959 would probably get three insns because X and Y might go
960 in the same place. This prevents X and Y from receiving
963 We can only do this if the modes of operands 0 and 1
964 (which might not be the same) are tieable and we only need
965 do this during our first pass. */
967 if (pass == 0 && optimize
968 && recog_data.n_operands >= 3
969 && recog_data.constraints[1][0] == '0'
970 && recog_data.constraints[1][1] == 0
971 && CONSTANT_P (recog_data.operand[1])
972 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1])
973 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2])
974 && GET_CODE (recog_data.operand[0]) == REG
975 && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]),
976 recog_data.operand_mode[1]))
978 rtx previnsn = prev_real_insn (insn);
980 = gen_lowpart (recog_data.operand_mode[1],
981 recog_data.operand[0]);
983 = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn);
985 /* If this insn was the start of a basic block,
986 include the new insn in that block.
987 We need not check for code_label here;
988 while a basic block can start with a code_label,
989 INSN could not be at the beginning of that block. */
990 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
993 for (b = 0; b < n_basic_blocks; b++)
994 if (insn == BLOCK_HEAD (b))
995 BLOCK_HEAD (b) = newinsn;
998 /* This makes one more setting of new insns's dest. */
999 REG_N_SETS (REGNO (recog_data.operand[0]))++;
1001 *recog_data.operand_loc[1] = recog_data.operand[0];
1002 for (i = recog_data.n_dups - 1; i >= 0; i--)
1003 if (recog_data.dup_num[i] == 1)
1004 *recog_data.dup_loc[i] = recog_data.operand[0];
1006 return PREV_INSN (newinsn);
1009 record_operand_costs (insn, op_costs, reg_pref);
1011 /* Now add the cost for each operand to the total costs for
1014 for (i = 0; i < recog_data.n_operands; i++)
1015 if (GET_CODE (recog_data.operand[i]) == REG
1016 && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER)
1018 int regno = REGNO (recog_data.operand[i]);
1019 struct costs *p = &costs[regno], *q = &op_costs[i];
1021 p->mem_cost += q->mem_cost * loop_cost;
1022 for (j = 0; j < N_REG_CLASSES; j++)
1023 p->cost[j] += q->cost[j] * loop_cost;
1029 /* This is a pass of the compiler that scans all instructions
1030 and calculates the preferred class for each pseudo-register.
1031 This information can be accessed later by calling `reg_preferred_class'.
1032 This pass comes just before local register allocation. */
1035 regclass (f, nregs, dump)
1046 costs = (struct costs *) xmalloc (nregs * sizeof (struct costs));
1048 #ifdef CLASS_CANNOT_CHANGE_SIZE
1049 reg_changes_size = BITMAP_XMALLOC();
1052 #ifdef FORBIDDEN_INC_DEC_CLASSES
1054 in_inc_dec = (char *) xmalloc (nregs);
1056 /* Initialize information about which register classes can be used for
1057 pseudos that are auto-incremented or auto-decremented. It would
1058 seem better to put this in init_reg_sets, but we need to be able
1059 to allocate rtx, which we can't do that early. */
1061 for (i = 0; i < N_REG_CLASSES; i++)
1063 rtx r = gen_rtx_REG (VOIDmode, 0);
1064 enum machine_mode m;
1067 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
1068 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
1072 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE;
1073 m = (enum machine_mode) ((int) m + 1))
1074 if (HARD_REGNO_MODE_OK (j, m))
1078 /* If a register is not directly suitable for an
1079 auto-increment or decrement addressing mode and
1080 requires secondary reloads, disallow its class from
1081 being used in such addresses. */
1084 #ifdef SECONDARY_RELOAD_CLASS
1085 || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1088 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1089 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1092 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1093 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1098 && ! auto_inc_dec_reg_p (r, m))
1099 forbidden_inc_dec_class[i] = 1;
1103 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1105 /* Normally we scan the insns once and determine the best class to use for
1106 each register. However, if -fexpensive_optimizations are on, we do so
1107 twice, the second time using the tentative best classes to guide the
1110 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
1115 fprintf (dump, "\n\nPass %i\n\n",pass);
1116 /* Zero out our accumulation of the cost of each class for each reg. */
1118 bzero ((char *) costs, nregs * sizeof (struct costs));
1120 #ifdef FORBIDDEN_INC_DEC_CLASSES
1121 bzero (in_inc_dec, nregs);
1124 /* Scan the instructions and record each time it would
1125 save code to put a certain register in a certain class. */
1130 for (insn = f; insn; insn = NEXT_INSN (insn))
1131 insn = scan_one_insn (insn, pass);
1134 for (index = 0; index < n_basic_blocks; index++)
1136 basic_block bb = BASIC_BLOCK (index);
1138 /* Show that an insn inside a loop is likely to be executed three
1139 times more than insns outside a loop. This is much more
1140 aggressive than the assumptions made elsewhere and is being
1141 tried as an experiment. */
1145 loop_cost = 1 << (2 * MIN (bb->loop_depth, 5));
1146 for (insn = bb->head; ; insn = NEXT_INSN (insn))
1148 insn = scan_one_insn (insn, pass);
1149 if (insn == bb->end)
1154 /* Now for each register look at how desirable each class is
1155 and find which class is preferred. Store that in
1156 `prefclass'. Record in `altclass' the largest register
1157 class any of whose registers is better than memory. */
1160 reg_pref = reg_pref_buffer;
1164 dump_regclass (dump);
1165 fprintf (dump,"\n");
1167 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
1169 register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
1170 enum reg_class best = ALL_REGS, alt = NO_REGS;
1171 /* This is an enum reg_class, but we call it an int
1172 to save lots of casts. */
1174 register struct costs *p = &costs[i];
1176 /* In non-optimizing compilation REG_N_REFS is not initialized
1178 if (optimize && !REG_N_REFS (i))
1181 for (class = (int) ALL_REGS - 1; class > 0; class--)
1183 /* Ignore classes that are too small for this operand or
1184 invalid for a operand that was auto-incremented. */
1185 if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i))
1186 > reg_class_size[class]
1187 #ifdef FORBIDDEN_INC_DEC_CLASSES
1188 || (in_inc_dec[i] && forbidden_inc_dec_class[class])
1190 #ifdef CLASS_CANNOT_CHANGE_SIZE
1191 || (REGNO_REG_SET_P (reg_changes_size, i)
1192 && ! class_can_change_size [class])
1196 else if (p->cost[class] < best_cost)
1198 best_cost = p->cost[class];
1199 best = (enum reg_class) class;
1201 else if (p->cost[class] == best_cost)
1202 best = reg_class_subunion[(int)best][class];
1205 /* Record the alternate register class; i.e., a class for which
1206 every register in it is better than using memory. If adding a
1207 class would make a smaller class (i.e., no union of just those
1208 classes exists), skip that class. The major unions of classes
1209 should be provided as a register class. Don't do this if we
1210 will be doing it again later. */
1212 if ((pass == 1 || dump) || ! flag_expensive_optimizations)
1213 for (class = 0; class < N_REG_CLASSES; class++)
1214 if (p->cost[class] < p->mem_cost
1215 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]]
1216 > reg_class_size[(int) alt])
1217 #ifdef FORBIDDEN_INC_DEC_CLASSES
1218 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class])
1220 #ifdef CLASS_CANNOT_CHANGE_SIZE
1221 && ! (REGNO_REG_SET_P (reg_changes_size, i)
1222 && ! class_can_change_size [class])
1225 alt = reg_class_subunion[(int) alt][class];
1227 /* If we don't add any classes, nothing to try. */
1232 && (reg_pref[i].prefclass != (int) best
1233 || reg_pref[i].altclass != (int) alt))
1235 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1236 fprintf (dump, " Register %i", i);
1237 if (alt == ALL_REGS || best == ALL_REGS)
1238 fprintf (dump, " pref %s\n", reg_class_names[(int) best]);
1239 else if (alt == NO_REGS)
1240 fprintf (dump, " pref %s or none\n", reg_class_names[(int) best]);
1242 fprintf (dump, " pref %s, else %s\n",
1243 reg_class_names[(int) best],
1244 reg_class_names[(int) alt]);
1247 /* We cast to (int) because (char) hits bugs in some compilers. */
1248 reg_pref[i].prefclass = (int) best;
1249 reg_pref[i].altclass = (int) alt;
1253 #ifdef FORBIDDEN_INC_DEC_CLASSES
1256 #ifdef CLASS_CANNOT_CHANGE_SIZE
1257 BITMAP_XFREE (reg_changes_size);
1262 /* Record the cost of using memory or registers of various classes for
1263 the operands in INSN.
1265 N_ALTS is the number of alternatives.
1267 N_OPS is the number of operands.
1269 OPS is an array of the operands.
1271 MODES are the modes of the operands, in case any are VOIDmode.
1273 CONSTRAINTS are the constraints to use for the operands. This array
1274 is modified by this procedure.
1276 This procedure works alternative by alternative. For each alternative
1277 we assume that we will be able to allocate all pseudos to their ideal
1278 register class and calculate the cost of using that alternative. Then
1279 we compute for each operand that is a pseudo-register, the cost of
1280 having the pseudo allocated to each register class and using it in that
1281 alternative. To this cost is added the cost of the alternative.
1283 The cost of each class for this insn is its lowest cost among all the
1287 record_reg_classes (n_alts, n_ops, ops, modes,
1288 constraints, insn, op_costs, reg_pref)
1292 enum machine_mode *modes;
1293 const char **constraints;
1295 struct costs *op_costs;
1296 struct reg_pref *reg_pref;
1302 /* Process each alternative, each time minimizing an operand's cost with
1303 the cost for each operand in that alternative. */
1305 for (alt = 0; alt < n_alts; alt++)
1307 struct costs this_op_costs[MAX_RECOG_OPERANDS];
1310 enum reg_class classes[MAX_RECOG_OPERANDS];
1311 int allows_mem[MAX_RECOG_OPERANDS];
1314 for (i = 0; i < n_ops; i++)
1316 const char *p = constraints[i];
1318 enum machine_mode mode = modes[i];
1319 int allows_addr = 0;
1323 /* Initially show we know nothing about the register class. */
1324 classes[i] = NO_REGS;
1327 /* If this operand has no constraints at all, we can conclude
1328 nothing about it since anything is valid. */
1332 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1333 bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]);
1338 /* If this alternative is only relevant when this operand
1339 matches a previous operand, we do different things depending
1340 on whether this operand is a pseudo-reg or not. We must process
1341 any modifiers for the operand before we can make this test. */
1343 while (*p == '%' || *p == '=' || *p == '+' || *p == '&')
1346 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
1348 /* Copy class and whether memory is allowed from the matching
1349 alternative. Then perform any needed cost computations
1350 and/or adjustments. */
1352 classes[i] = classes[j];
1353 allows_mem[i] = allows_mem[j];
1355 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER)
1357 /* If this matches the other operand, we have no added
1359 if (rtx_equal_p (ops[j], op))
1362 /* If we can put the other operand into a register, add to
1363 the cost of this alternative the cost to copy this
1364 operand to the register used for the other operand. */
1366 else if (classes[j] != NO_REGS)
1367 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1;
1369 else if (GET_CODE (ops[j]) != REG
1370 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
1372 /* This op is a pseudo but the one it matches is not. */
1374 /* If we can't put the other operand into a register, this
1375 alternative can't be used. */
1377 if (classes[j] == NO_REGS)
1380 /* Otherwise, add to the cost of this alternative the cost
1381 to copy the other operand to the register used for this
1385 alt_cost += copy_cost (ops[j], mode, classes[j], 1);
1389 /* The costs of this operand are not the same as the other
1390 operand since move costs are not symmetric. Moreover,
1391 if we cannot tie them, this alternative needs to do a
1392 copy, which is one instruction. */
1394 struct costs *pp = &this_op_costs[i];
1396 for (class = 0; class < N_REG_CLASSES; class++)
1398 = ((recog_data.operand_type[i] != OP_OUT
1399 ? may_move_in_cost[class][(int) classes[i]]
1401 + (recog_data.operand_type[i] != OP_IN
1402 ? may_move_out_cost[(int) classes[i]][class]
1405 /* If the alternative actually allows memory, make things
1406 a bit cheaper since we won't need an extra insn to
1410 = ((recog_data.operand_type[i] != OP_IN
1411 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1413 + (recog_data.operand_type[i] != OP_OUT
1414 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1415 : 0) - allows_mem[i]);
1417 /* If we have assigned a class to this register in our
1418 first pass, add a cost to this alternative corresponding
1419 to what we would add if this register were not in the
1420 appropriate class. */
1424 += (may_move_in_cost[(unsigned char) reg_pref[REGNO (op)].prefclass]
1425 [(int) classes[i]]);
1427 if (REGNO (ops[i]) != REGNO (ops[j])
1428 && ! find_reg_note (insn, REG_DEAD, op))
1431 /* This is in place of ordinary cost computation
1432 for this operand, so skip to the end of the
1433 alternative (should be just one character). */
1434 while (*p && *p++ != ',')
1442 /* Scan all the constraint letters. See if the operand matches
1443 any of the constraints. Collect the valid register classes
1444 and see if this operand accepts memory. */
1446 while (*p && (c = *p++) != ',')
1450 /* Ignore the next letter for this pass. */
1456 case '!': case '#': case '&':
1457 case '0': case '1': case '2': case '3': case '4':
1458 case '5': case '6': case '7': case '8': case '9':
1463 win = address_operand (op, GET_MODE (op));
1464 /* We know this operand is an address, so we want it to be
1465 allocated to a register that can be the base of an
1466 address, ie BASE_REG_CLASS. */
1468 = reg_class_subunion[(int) classes[i]]
1469 [(int) BASE_REG_CLASS];
1472 case 'm': case 'o': case 'V':
1473 /* It doesn't seem worth distinguishing between offsettable
1474 and non-offsettable addresses here. */
1476 if (GET_CODE (op) == MEM)
1481 if (GET_CODE (op) == MEM
1482 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1483 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1488 if (GET_CODE (op) == MEM
1489 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1490 || GET_CODE (XEXP (op, 0)) == POST_INC))
1495 #ifndef REAL_ARITHMETIC
1496 /* Match any floating double constant, but only if
1497 we can examine the bits of it reliably. */
1498 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1499 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1500 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1503 if (GET_CODE (op) == CONST_DOUBLE)
1508 if (GET_CODE (op) == CONST_DOUBLE)
1514 if (GET_CODE (op) == CONST_DOUBLE
1515 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
1520 if (GET_CODE (op) == CONST_INT
1521 || (GET_CODE (op) == CONST_DOUBLE
1522 && GET_MODE (op) == VOIDmode))
1526 #ifdef LEGITIMATE_PIC_OPERAND_P
1527 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1534 if (GET_CODE (op) == CONST_INT
1535 || (GET_CODE (op) == CONST_DOUBLE
1536 && GET_MODE (op) == VOIDmode))
1548 if (GET_CODE (op) == CONST_INT
1549 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
1557 #ifdef EXTRA_CONSTRAINT
1563 if (EXTRA_CONSTRAINT (op, c))
1569 if (GET_CODE (op) == MEM
1571 #ifdef LEGITIMATE_PIC_OPERAND_P
1572 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1579 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1584 = reg_class_subunion[(int) classes[i]]
1585 [(int) REG_CLASS_FROM_LETTER (c)];
1590 /* How we account for this operand now depends on whether it is a
1591 pseudo register or not. If it is, we first check if any
1592 register classes are valid. If not, we ignore this alternative,
1593 since we want to assume that all pseudos get allocated for
1594 register preferencing. If some register class is valid, compute
1595 the costs of moving the pseudo into that class. */
1597 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1599 if (classes[i] == NO_REGS)
1601 /* We must always fail if the operand is a REG, but
1602 we did not find a suitable class.
1604 Otherwise we may perform an uninitialized read
1605 from this_op_costs after the `continue' statement
1611 struct costs *pp = &this_op_costs[i];
1613 for (class = 0; class < N_REG_CLASSES; class++)
1615 = ((recog_data.operand_type[i] != OP_OUT
1616 ? may_move_in_cost[class][(int) classes[i]]
1618 + (recog_data.operand_type[i] != OP_IN
1619 ? may_move_out_cost[(int) classes[i]][class]
1622 /* If the alternative actually allows memory, make things
1623 a bit cheaper since we won't need an extra insn to
1627 = ((recog_data.operand_type[i] != OP_IN
1628 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1630 + (recog_data.operand_type[i] != OP_OUT
1631 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1632 : 0) - allows_mem[i]);
1634 /* If we have assigned a class to this register in our
1635 first pass, add a cost to this alternative corresponding
1636 to what we would add if this register were not in the
1637 appropriate class. */
1641 += (may_move_in_cost[(unsigned char) reg_pref[REGNO (op)].prefclass]
1642 [(int) classes[i]]);
1646 /* Otherwise, if this alternative wins, either because we
1647 have already determined that or if we have a hard register of
1648 the proper class, there is no cost for this alternative. */
1651 || (GET_CODE (op) == REG
1652 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op))))
1655 /* If registers are valid, the cost of this alternative includes
1656 copying the object to and/or from a register. */
1658 else if (classes[i] != NO_REGS)
1660 if (recog_data.operand_type[i] != OP_OUT)
1661 alt_cost += copy_cost (op, mode, classes[i], 1);
1663 if (recog_data.operand_type[i] != OP_IN)
1664 alt_cost += copy_cost (op, mode, classes[i], 0);
1667 /* The only other way this alternative can be used is if this is a
1668 constant that could be placed into memory. */
1670 else if (CONSTANT_P (op) && (allows_addr || allows_mem[i]))
1671 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1);
1679 /* Finally, update the costs with the information we've calculated
1680 about this alternative. */
1682 for (i = 0; i < n_ops; i++)
1683 if (GET_CODE (ops[i]) == REG
1684 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1686 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1687 int scale = 1 + (recog_data.operand_type[i] == OP_INOUT);
1689 pp->mem_cost = MIN (pp->mem_cost,
1690 (qq->mem_cost + alt_cost) * scale);
1692 for (class = 0; class < N_REG_CLASSES; class++)
1693 pp->cost[class] = MIN (pp->cost[class],
1694 (qq->cost[class] + alt_cost) * scale);
1698 /* If this insn is a single set copying operand 1 to operand 0
1699 and one operand is a pseudo with the other a hard reg or a pseudo
1700 that prefers a register that is in its own register class then
1701 we may want to adjust the cost of that register class to -1.
1703 Avoid the adjustment if the source does not die to avoid stressing of
1704 register allocator by preferrencing two coliding registers into single
1707 Also avoid the adjustment if a copy between registers of the class
1708 is expensive (ten times the cost of a default copy is considered
1709 arbitrarily expensive). This avoids losing when the preferred class
1710 is very expensive as the source of a copy instruction. */
1712 if ((set = single_set (insn)) != 0
1713 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set)
1714 && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG
1715 && find_regno_note (insn, REG_DEAD, REGNO (ops[1])))
1716 for (i = 0; i <= 1; i++)
1717 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1719 unsigned int regno = REGNO (ops[!i]);
1720 enum machine_mode mode = GET_MODE (ops[!i]);
1724 if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0)
1726 enum reg_class pref = reg_pref[regno].prefclass;
1728 if ((reg_class_size[(unsigned char) pref]
1729 == CLASS_MAX_NREGS (pref, mode))
1730 && REGISTER_MOVE_COST (pref, pref) < 10 * 2)
1731 op_costs[i].cost[(unsigned char) pref] = -1;
1733 else if (regno < FIRST_PSEUDO_REGISTER)
1734 for (class = 0; class < N_REG_CLASSES; class++)
1735 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1736 && reg_class_size[class] == CLASS_MAX_NREGS (class, mode))
1738 if (reg_class_size[class] == 1)
1739 op_costs[i].cost[class] = -1;
1742 for (nr = 0; nr < HARD_REGNO_NREGS (regno, mode); nr++)
1744 if (! TEST_HARD_REG_BIT (reg_class_contents[class],
1749 if (nr == HARD_REGNO_NREGS (regno,mode))
1750 op_costs[i].cost[class] = -1;
1756 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1757 TO_P is zero) a register of class CLASS in mode MODE.
1759 X must not be a pseudo. */
1762 copy_cost (x, mode, class, to_p)
1764 enum machine_mode mode ATTRIBUTE_UNUSED;
1765 enum reg_class class;
1766 int to_p ATTRIBUTE_UNUSED;
1768 #ifdef HAVE_SECONDARY_RELOADS
1769 enum reg_class secondary_class = NO_REGS;
1772 /* If X is a SCRATCH, there is actually nothing to move since we are
1773 assuming optimal allocation. */
1775 if (GET_CODE (x) == SCRATCH)
1778 /* Get the class we will actually use for a reload. */
1779 class = PREFERRED_RELOAD_CLASS (x, class);
1781 #ifdef HAVE_SECONDARY_RELOADS
1782 /* If we need a secondary reload (we assume here that we are using
1783 the secondary reload as an intermediate, not a scratch register), the
1784 cost is that to load the input into the intermediate register, then
1785 to copy them. We use a special value of TO_P to avoid recursion. */
1787 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1789 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x);
1792 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1794 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x);
1797 if (secondary_class != NO_REGS)
1798 return (move_cost[(int) secondary_class][(int) class]
1799 + copy_cost (x, mode, secondary_class, 2));
1800 #endif /* HAVE_SECONDARY_RELOADS */
1802 /* For memory, use the memory move cost, for (hard) registers, use the
1803 cost to move between the register classes, and use 2 for everything
1804 else (constants). */
1806 if (GET_CODE (x) == MEM || class == NO_REGS)
1807 return MEMORY_MOVE_COST (mode, class, to_p);
1809 else if (GET_CODE (x) == REG)
1810 return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class];
1813 /* If this is a constant, we may eventually want to call rtx_cost here. */
1817 /* Record the pseudo registers we must reload into hard registers
1818 in a subexpression of a memory address, X.
1820 CLASS is the class that the register needs to be in and is either
1821 BASE_REG_CLASS or INDEX_REG_CLASS.
1823 SCALE is twice the amount to multiply the cost by (it is twice so we
1824 can represent half-cost adjustments). */
1827 record_address_regs (x, class, scale)
1829 enum reg_class class;
1832 register enum rtx_code code = GET_CODE (x);
1845 /* When we have an address that is a sum,
1846 we must determine whether registers are "base" or "index" regs.
1847 If there is a sum of two registers, we must choose one to be
1848 the "base". Luckily, we can use the REGNO_POINTER_FLAG
1849 to make a good choice most of the time. We only need to do this
1850 on machines that can have two registers in an address and where
1851 the base and index register classes are different.
1853 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1854 that seems bogus since it should only be set when we are sure
1855 the register is being used as a pointer. */
1858 rtx arg0 = XEXP (x, 0);
1859 rtx arg1 = XEXP (x, 1);
1860 register enum rtx_code code0 = GET_CODE (arg0);
1861 register enum rtx_code code1 = GET_CODE (arg1);
1863 /* Look inside subregs. */
1864 if (code0 == SUBREG)
1865 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1866 if (code1 == SUBREG)
1867 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1869 /* If this machine only allows one register per address, it must
1870 be in the first operand. */
1872 if (MAX_REGS_PER_ADDRESS == 1)
1873 record_address_regs (arg0, class, scale);
1875 /* If index and base registers are the same on this machine, just
1876 record registers in any non-constant operands. We assume here,
1877 as well as in the tests below, that all addresses are in
1880 else if (INDEX_REG_CLASS == BASE_REG_CLASS)
1882 record_address_regs (arg0, class, scale);
1883 if (! CONSTANT_P (arg1))
1884 record_address_regs (arg1, class, scale);
1887 /* If the second operand is a constant integer, it doesn't change
1888 what class the first operand must be. */
1890 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
1891 record_address_regs (arg0, class, scale);
1893 /* If the second operand is a symbolic constant, the first operand
1894 must be an index register. */
1896 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
1897 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1899 /* If both operands are registers but one is already a hard register
1900 of index or base class, give the other the class that the hard
1903 #ifdef REG_OK_FOR_BASE_P
1904 else if (code0 == REG && code1 == REG
1905 && REGNO (arg0) < FIRST_PSEUDO_REGISTER
1906 && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0)))
1907 record_address_regs (arg1,
1908 REG_OK_FOR_BASE_P (arg0)
1909 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1911 else if (code0 == REG && code1 == REG
1912 && REGNO (arg1) < FIRST_PSEUDO_REGISTER
1913 && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1)))
1914 record_address_regs (arg0,
1915 REG_OK_FOR_BASE_P (arg1)
1916 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1920 /* If one operand is known to be a pointer, it must be the base
1921 with the other operand the index. Likewise if the other operand
1924 else if ((code0 == REG && REGNO_POINTER_FLAG (REGNO (arg0)))
1927 record_address_regs (arg0, BASE_REG_CLASS, scale);
1928 record_address_regs (arg1, INDEX_REG_CLASS, scale);
1930 else if ((code1 == REG && REGNO_POINTER_FLAG (REGNO (arg1)))
1933 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1934 record_address_regs (arg1, BASE_REG_CLASS, scale);
1937 /* Otherwise, count equal chances that each might be a base
1938 or index register. This case should be rare. */
1942 record_address_regs (arg0, BASE_REG_CLASS, scale / 2);
1943 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2);
1944 record_address_regs (arg1, BASE_REG_CLASS, scale / 2);
1945 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2);
1954 /* Double the importance of a pseudo register that is incremented
1955 or decremented, since it would take two extra insns
1956 if it ends up in the wrong place. If the operand is a pseudo,
1957 show it is being used in an INC_DEC context. */
1959 #ifdef FORBIDDEN_INC_DEC_CLASSES
1960 if (GET_CODE (XEXP (x, 0)) == REG
1961 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
1962 in_inc_dec[REGNO (XEXP (x, 0))] = 1;
1965 record_address_regs (XEXP (x, 0), class, 2 * scale);
1970 register struct costs *pp = &costs[REGNO (x)];
1973 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2;
1975 for (i = 0; i < N_REG_CLASSES; i++)
1976 pp->cost[i] += (may_move_in_cost[i][(int) class] * scale) / 2;
1982 register const char *fmt = GET_RTX_FORMAT (code);
1984 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1986 record_address_regs (XEXP (x, i), class, scale);
1991 #ifdef FORBIDDEN_INC_DEC_CLASSES
1993 /* Return 1 if REG is valid as an auto-increment memory reference
1994 to an object of MODE. */
1997 auto_inc_dec_reg_p (reg, mode)
1999 enum machine_mode mode;
2001 if (HAVE_POST_INCREMENT
2002 && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg)))
2005 if (HAVE_POST_DECREMENT
2006 && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg)))
2009 if (HAVE_PRE_INCREMENT
2010 && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg)))
2013 if (HAVE_PRE_DECREMENT
2014 && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg)))
2021 static short *renumber;
2022 static size_t regno_allocated;
2023 static unsigned int reg_n_max;
2025 /* Allocate enough space to hold NUM_REGS registers for the tables used for
2026 reg_scan and flow_analysis that are indexed by the register number. If
2027 NEW_P is non zero, initialize all of the registers, otherwise only
2028 initialize the new registers allocated. The same table is kept from
2029 function to function, only reallocating it when we need more room. If
2030 RENUMBER_P is non zero, allocate the reg_renumber array also. */
2033 allocate_reg_info (num_regs, new_p, renumber_p)
2039 size_t size_renumber;
2040 size_t min = (new_p) ? 0 : reg_n_max;
2041 struct reg_info_data *reg_data;
2043 if (num_regs > regno_allocated)
2045 size_t old_allocated = regno_allocated;
2047 regno_allocated = num_regs + (num_regs / 20); /* add some slop space */
2048 size_renumber = regno_allocated * sizeof (short);
2052 VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info");
2053 renumber = (short *) xmalloc (size_renumber);
2054 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated
2055 * sizeof (struct reg_pref));
2060 VARRAY_GROW (reg_n_info, regno_allocated);
2062 if (new_p) /* if we're zapping everything, no need to realloc */
2064 free ((char *)renumber);
2065 free ((char *)reg_pref);
2066 renumber = (short *) xmalloc (size_renumber);
2067 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated
2068 * sizeof (struct reg_pref));
2073 renumber = (short *) xrealloc ((char *)renumber, size_renumber);
2074 reg_pref_buffer = (struct reg_pref *) xrealloc ((char *)reg_pref_buffer,
2076 * sizeof (struct reg_pref));
2080 size_info = (regno_allocated - old_allocated) * sizeof (reg_info)
2081 + sizeof (struct reg_info_data) - sizeof (reg_info);
2082 reg_data = (struct reg_info_data *) xcalloc (size_info, 1);
2083 reg_data->min_index = old_allocated;
2084 reg_data->max_index = regno_allocated - 1;
2085 reg_data->next = reg_info_head;
2086 reg_info_head = reg_data;
2089 reg_n_max = num_regs;
2092 /* Loop through each of the segments allocated for the actual
2093 reg_info pages, and set up the pointers, zero the pages, etc. */
2094 for (reg_data = reg_info_head;
2095 reg_data && reg_data->max_index >= min;
2096 reg_data = reg_data->next)
2098 size_t min_index = reg_data->min_index;
2099 size_t max_index = reg_data->max_index;
2100 size_t max = MIN (max_index, num_regs);
2101 size_t local_min = min - min_index;
2104 if (reg_data->min_index > num_regs)
2107 if (min < min_index)
2109 if (!reg_data->used_p) /* page just allocated with calloc */
2110 reg_data->used_p = 1; /* no need to zero */
2112 bzero ((char *) ®_data->data[local_min],
2113 sizeof (reg_info) * (max - min_index - local_min + 1));
2115 for (i = min_index+local_min; i <= max; i++)
2117 VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index];
2118 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN;
2120 reg_pref_buffer[i].prefclass = (char) NO_REGS;
2121 reg_pref_buffer[i].altclass = (char) NO_REGS;
2126 /* If {pref,alt}class have already been allocated, update the pointers to
2127 the newly realloced ones. */
2129 reg_pref = reg_pref_buffer;
2132 reg_renumber = renumber;
2134 /* Tell the regset code about the new number of registers */
2135 MAX_REGNO_REG_SET (num_regs, new_p, renumber_p);
2138 /* Free up the space allocated by allocate_reg_info. */
2144 struct reg_info_data *reg_data;
2145 struct reg_info_data *reg_next;
2147 VARRAY_FREE (reg_n_info);
2148 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
2150 reg_next = reg_data->next;
2151 free ((char *)reg_data);
2154 free (reg_pref_buffer);
2155 reg_pref_buffer = (struct reg_pref *)0;
2156 reg_info_head = (struct reg_info_data *)0;
2157 renumber = (short *)0;
2159 regno_allocated = 0;
2163 /* This is the `regscan' pass of the compiler, run just before cse
2164 and again just before loop.
2166 It finds the first and last use of each pseudo-register
2167 and records them in the vectors regno_first_uid, regno_last_uid
2168 and counts the number of sets in the vector reg_n_sets.
2170 REPEAT is nonzero the second time this is called. */
2172 /* Maximum number of parallel sets and clobbers in any insn in this fn.
2173 Always at least 3, since the combiner could put that many together
2174 and we want this to remain correct for all the remaining passes. */
2179 reg_scan (f, nregs, repeat)
2182 int repeat ATTRIBUTE_UNUSED;
2186 allocate_reg_info (nregs, TRUE, FALSE);
2189 for (insn = f; insn; insn = NEXT_INSN (insn))
2190 if (GET_CODE (insn) == INSN
2191 || GET_CODE (insn) == CALL_INSN
2192 || GET_CODE (insn) == JUMP_INSN)
2194 if (GET_CODE (PATTERN (insn)) == PARALLEL
2195 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2196 max_parallel = XVECLEN (PATTERN (insn), 0);
2197 reg_scan_mark_refs (PATTERN (insn), insn, 0, 0);
2199 if (REG_NOTES (insn))
2200 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0);
2204 /* Update 'regscan' information by looking at the insns
2205 from FIRST to LAST. Some new REGs have been created,
2206 and any REG with number greater than OLD_MAX_REGNO is
2207 such a REG. We only update information for those. */
2210 reg_scan_update (first, last, old_max_regno)
2213 unsigned int old_max_regno;
2217 allocate_reg_info (max_reg_num (), FALSE, FALSE);
2219 for (insn = first; insn != last; insn = NEXT_INSN (insn))
2220 if (GET_CODE (insn) == INSN
2221 || GET_CODE (insn) == CALL_INSN
2222 || GET_CODE (insn) == JUMP_INSN)
2224 if (GET_CODE (PATTERN (insn)) == PARALLEL
2225 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2226 max_parallel = XVECLEN (PATTERN (insn), 0);
2227 reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno);
2229 if (REG_NOTES (insn))
2230 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno);
2234 /* X is the expression to scan. INSN is the insn it appears in.
2235 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2236 We should only record information for REGs with numbers
2237 greater than or equal to MIN_REGNO. */
2240 reg_scan_mark_refs (x, insn, note_flag, min_regno)
2244 unsigned int min_regno;
2246 register enum rtx_code code;
2250 code = GET_CODE (x);
2266 unsigned int regno = REGNO (x);
2268 if (regno >= min_regno)
2270 REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn);
2272 REGNO_LAST_UID (regno) = INSN_UID (insn);
2273 if (REGNO_FIRST_UID (regno) == 0)
2274 REGNO_FIRST_UID (regno) = INSN_UID (insn);
2281 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno);
2283 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2288 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2292 /* Count a set of the destination if it is a register. */
2293 for (dest = SET_DEST (x);
2294 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
2295 || GET_CODE (dest) == ZERO_EXTEND;
2296 dest = XEXP (dest, 0))
2299 if (GET_CODE (dest) == REG
2300 && REGNO (dest) >= min_regno)
2301 REG_N_SETS (REGNO (dest))++;
2303 /* If this is setting a pseudo from another pseudo or the sum of a
2304 pseudo and a constant integer and the other pseudo is known to be
2305 a pointer, set the destination to be a pointer as well.
2307 Likewise if it is setting the destination from an address or from a
2308 value equivalent to an address or to the sum of an address and
2311 But don't do any of this if the pseudo corresponds to a user
2312 variable since it should have already been set as a pointer based
2315 if (GET_CODE (SET_DEST (x)) == REG
2316 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER
2317 && REGNO (SET_DEST (x)) >= min_regno
2318 /* If the destination pseudo is set more than once, then other
2319 sets might not be to a pointer value (consider access to a
2320 union in two threads of control in the presense of global
2321 optimizations). So only set REGNO_POINTER_FLAG on the destination
2322 pseudo if this is the only set of that pseudo. */
2323 && REG_N_SETS (REGNO (SET_DEST (x))) == 1
2324 && ! REG_USERVAR_P (SET_DEST (x))
2325 && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x)))
2326 && ((GET_CODE (SET_SRC (x)) == REG
2327 && REGNO_POINTER_FLAG (REGNO (SET_SRC (x))))
2328 || ((GET_CODE (SET_SRC (x)) == PLUS
2329 || GET_CODE (SET_SRC (x)) == LO_SUM)
2330 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2331 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2332 && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x), 0))))
2333 || GET_CODE (SET_SRC (x)) == CONST
2334 || GET_CODE (SET_SRC (x)) == SYMBOL_REF
2335 || GET_CODE (SET_SRC (x)) == LABEL_REF
2336 || (GET_CODE (SET_SRC (x)) == HIGH
2337 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
2338 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
2339 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
2340 || ((GET_CODE (SET_SRC (x)) == PLUS
2341 || GET_CODE (SET_SRC (x)) == LO_SUM)
2342 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
2343 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
2344 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
2345 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
2346 && (GET_CODE (XEXP (note, 0)) == CONST
2347 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
2348 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
2349 REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) = 1;
2351 /* ... fall through ... */
2355 register const char *fmt = GET_RTX_FORMAT (code);
2357 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2360 reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno);
2361 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
2364 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2365 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno);
2372 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2376 reg_class_subset_p (c1, c2)
2377 register enum reg_class c1;
2378 register enum reg_class c2;
2380 if (c1 == c2) return 1;
2385 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1],
2386 reg_class_contents[(int)c2],
2391 /* Return nonzero if there is a register that is in both C1 and C2. */
2394 reg_classes_intersect_p (c1, c2)
2395 register enum reg_class c1;
2396 register enum reg_class c2;
2403 if (c1 == c2) return 1;
2405 if (c1 == ALL_REGS || c2 == ALL_REGS)
2408 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
2409 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
2411 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose);
2418 /* Release any memory allocated by register sets. */
2421 regset_release_memory ()
2423 bitmap_release_memory ();