1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 88, 91-98, 1999, 2000 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This file contains two passes of the compiler: reg_scan and reg_class.
23 It also defines some tables of information about the hardware registers
24 and a function init_reg_sets to initialize the tables. */
30 #include "hard-reg-set.h"
32 #include "basic-block.h"
35 #include "insn-config.h"
43 #ifndef REGISTER_MOVE_COST
44 #define REGISTER_MOVE_COST(x, y) 2
47 static void init_reg_sets_1 PROTO((void));
48 static void init_reg_modes PROTO((void));
50 /* If we have auto-increment or auto-decrement and we can have secondary
51 reloads, we are not allowed to use classes requiring secondary
52 reloads for pseudos auto-incremented since reload can't handle it. */
55 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
56 #define FORBIDDEN_INC_DEC_CLASSES
60 /* Register tables used by many passes. */
62 /* Indexed by hard register number, contains 1 for registers
63 that are fixed use (stack pointer, pc, frame pointer, etc.).
64 These are the registers that cannot be used to allocate
65 a pseudo reg for general use. */
67 char fixed_regs[FIRST_PSEUDO_REGISTER];
69 /* Same info as a HARD_REG_SET. */
71 HARD_REG_SET fixed_reg_set;
73 /* Data for initializing the above. */
75 static char initial_fixed_regs[] = FIXED_REGISTERS;
77 /* Indexed by hard register number, contains 1 for registers
78 that are fixed use or are clobbered by function calls.
79 These are the registers that cannot be used to allocate
80 a pseudo reg whose life crosses calls unless we are able
81 to save/restore them across the calls. */
83 char call_used_regs[FIRST_PSEUDO_REGISTER];
85 /* Same info as a HARD_REG_SET. */
87 HARD_REG_SET call_used_reg_set;
89 /* HARD_REG_SET of registers we want to avoid caller saving. */
90 HARD_REG_SET losing_caller_save_reg_set;
92 /* Data for initializing the above. */
94 static char initial_call_used_regs[] = CALL_USED_REGISTERS;
96 /* Indexed by hard register number, contains 1 for registers that are
97 fixed use or call used registers that cannot hold quantities across
98 calls even if we are willing to save and restore them. call fixed
99 registers are a subset of call used registers. */
101 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
103 /* The same info as a HARD_REG_SET. */
105 HARD_REG_SET call_fixed_reg_set;
107 /* Number of non-fixed registers. */
109 int n_non_fixed_regs;
111 /* Indexed by hard register number, contains 1 for registers
112 that are being used for global register decls.
113 These must be exempt from ordinary flow analysis
114 and are also considered fixed. */
116 char global_regs[FIRST_PSEUDO_REGISTER];
118 /* Table of register numbers in the order in which to try to use them. */
119 #ifdef REG_ALLOC_ORDER
120 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
122 /* The inverse of reg_alloc_order. */
123 int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER];
126 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
128 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
130 /* The same information, but as an array of unsigned ints. We copy from
131 these unsigned ints to the table above. We do this so the tm.h files
132 do not have to be aware of the wordsize for machines with <= 64 regs. */
135 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
137 static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
138 = REG_CLASS_CONTENTS;
140 /* For each reg class, number of regs it contains. */
142 int reg_class_size[N_REG_CLASSES];
144 /* For each reg class, table listing all the containing classes. */
146 enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
148 /* For each reg class, table listing all the classes contained in it. */
150 enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
152 /* For each pair of reg classes,
153 a largest reg class contained in their union. */
155 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
157 /* For each pair of reg classes,
158 the smallest reg class containing their union. */
160 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
162 /* Array containing all of the register names */
164 const char *reg_names[] = REGISTER_NAMES;
166 /* For each hard register, the widest mode object that it can contain.
167 This will be a MODE_INT mode if the register can hold integers. Otherwise
168 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
171 enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER];
173 /* Maximum cost of moving from a register in one class to a register in
174 another class. Based on REGISTER_MOVE_COST. */
176 static int move_cost[N_REG_CLASSES][N_REG_CLASSES];
178 /* Similar, but here we don't have to move if the first index is a subset
179 of the second so in that case the cost is zero. */
181 static int may_move_in_cost[N_REG_CLASSES][N_REG_CLASSES];
183 /* Similar, but here we don't have to move if the first index is a superset
184 of the second so in that case the cost is zero. */
186 static int may_move_out_cost[N_REG_CLASSES][N_REG_CLASSES];
188 #ifdef FORBIDDEN_INC_DEC_CLASSES
190 /* These are the classes that regs which are auto-incremented or decremented
193 static int forbidden_inc_dec_class[N_REG_CLASSES];
195 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
198 static char *in_inc_dec;
200 #endif /* FORBIDDEN_INC_DEC_CLASSES */
202 #ifdef HAVE_SECONDARY_RELOADS
204 /* Sample MEM values for use by memory_move_secondary_cost. */
206 static rtx top_of_stack[MAX_MACHINE_MODE];
208 #endif /* HAVE_SECONDARY_RELOADS */
210 /* Linked list of reg_info structures allocated for reg_n_info array.
211 Grouping all of the allocated structures together in one lump
212 means only one call to bzero to clear them, rather than n smaller
214 struct reg_info_data {
215 struct reg_info_data *next; /* next set of reg_info structures */
216 size_t min_index; /* minimum index # */
217 size_t max_index; /* maximum index # */
218 char used_p; /* non-zero if this has been used previously */
219 reg_info data[1]; /* beginning of the reg_info data */
222 static struct reg_info_data *reg_info_head;
224 /* No more global register variables may be declared; true once
225 regclass has been initialized. */
227 static int no_global_reg_vars = 0;
230 /* Function called only once to initialize the above data on reg usage.
231 Once this is done, various switches may override. */
238 /* First copy the register information from the initial int form into
241 for (i = 0; i < N_REG_CLASSES; i++)
243 CLEAR_HARD_REG_SET (reg_class_contents[i]);
245 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
246 if (int_reg_class_contents[i][j / HOST_BITS_PER_INT]
247 & ((unsigned) 1 << (j % HOST_BITS_PER_INT)))
248 SET_HARD_REG_BIT (reg_class_contents[i], j);
251 bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs);
252 bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs);
253 bzero (global_regs, sizeof global_regs);
255 /* Do any additional initialization regsets may need */
256 INIT_ONCE_REG_SET ();
258 #ifdef REG_ALLOC_ORDER
259 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
260 inv_reg_alloc_order[reg_alloc_order[i]] = i;
264 /* After switches have been processed, which perhaps alter
265 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
270 register unsigned int i, j;
272 /* This macro allows the fixed or call-used registers
273 and the register classes to depend on target flags. */
275 #ifdef CONDITIONAL_REGISTER_USAGE
276 CONDITIONAL_REGISTER_USAGE;
279 /* Compute number of hard regs in each class. */
281 bzero ((char *) reg_class_size, sizeof reg_class_size);
282 for (i = 0; i < N_REG_CLASSES; i++)
283 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
284 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
287 /* Initialize the table of subunions.
288 reg_class_subunion[I][J] gets the largest-numbered reg-class
289 that is contained in the union of classes I and J. */
291 for (i = 0; i < N_REG_CLASSES; i++)
293 for (j = 0; j < N_REG_CLASSES; j++)
296 register /* Declare it register if it's a scalar. */
301 COPY_HARD_REG_SET (c, reg_class_contents[i]);
302 IOR_HARD_REG_SET (c, reg_class_contents[j]);
303 for (k = 0; k < N_REG_CLASSES; k++)
305 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
310 /* keep the largest subclass */ /* SPEE 900308 */
311 GO_IF_HARD_REG_SUBSET (reg_class_contents[k],
312 reg_class_contents[(int) reg_class_subunion[i][j]],
314 reg_class_subunion[i][j] = (enum reg_class) k;
321 /* Initialize the table of superunions.
322 reg_class_superunion[I][J] gets the smallest-numbered reg-class
323 containing the union of classes I and J. */
325 for (i = 0; i < N_REG_CLASSES; i++)
327 for (j = 0; j < N_REG_CLASSES; j++)
330 register /* Declare it register if it's a scalar. */
335 COPY_HARD_REG_SET (c, reg_class_contents[i]);
336 IOR_HARD_REG_SET (c, reg_class_contents[j]);
337 for (k = 0; k < N_REG_CLASSES; k++)
338 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass);
341 reg_class_superunion[i][j] = (enum reg_class) k;
345 /* Initialize the tables of subclasses and superclasses of each reg class.
346 First clear the whole table, then add the elements as they are found. */
348 for (i = 0; i < N_REG_CLASSES; i++)
350 for (j = 0; j < N_REG_CLASSES; j++)
352 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
353 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
357 for (i = 0; i < N_REG_CLASSES; i++)
359 if (i == (int) NO_REGS)
362 for (j = i + 1; j < N_REG_CLASSES; j++)
366 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
370 /* Reg class I is a subclass of J.
371 Add J to the table of superclasses of I. */
372 p = ®_class_superclasses[i][0];
373 while (*p != LIM_REG_CLASSES) p++;
374 *p = (enum reg_class) j;
375 /* Add I to the table of superclasses of J. */
376 p = ®_class_subclasses[j][0];
377 while (*p != LIM_REG_CLASSES) p++;
378 *p = (enum reg_class) i;
382 /* Initialize "constant" tables. */
384 CLEAR_HARD_REG_SET (fixed_reg_set);
385 CLEAR_HARD_REG_SET (call_used_reg_set);
386 CLEAR_HARD_REG_SET (call_fixed_reg_set);
388 bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs);
390 n_non_fixed_regs = 0;
392 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
395 SET_HARD_REG_BIT (fixed_reg_set, i);
399 if (call_used_regs[i])
400 SET_HARD_REG_BIT (call_used_reg_set, i);
401 if (call_fixed_regs[i])
402 SET_HARD_REG_BIT (call_fixed_reg_set, i);
403 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i)))
404 SET_HARD_REG_BIT (losing_caller_save_reg_set, i);
407 /* Initialize the move cost table. Find every subset of each class
408 and take the maximum cost of moving any subset to any other. */
410 for (i = 0; i < N_REG_CLASSES; i++)
411 for (j = 0; j < N_REG_CLASSES; j++)
413 int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j);
414 enum reg_class *p1, *p2;
416 for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++)
418 cost = MAX (cost, REGISTER_MOVE_COST (i, *p2));
420 for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++)
423 cost = MAX (cost, REGISTER_MOVE_COST (*p1, j));
425 for (p2 = ®_class_subclasses[j][0];
426 *p2 != LIM_REG_CLASSES; p2++)
428 cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2));
431 move_cost[i][j] = cost;
433 if (reg_class_subset_p (i, j))
434 may_move_in_cost[i][j] = 0;
436 may_move_in_cost[i][j] = cost;
438 if (reg_class_subset_p (j, i))
439 may_move_out_cost[i][j] = 0;
441 may_move_out_cost[i][j] = cost;
445 /* Compute the table of register modes.
446 These values are used to record death information for individual registers
447 (as opposed to a multi-register mode). */
454 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
456 reg_raw_mode[i] = choose_hard_reg_mode (i, 1);
458 /* If we couldn't find a valid mode, just use the previous mode.
459 ??? One situation in which we need to do this is on the mips where
460 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
461 to use DF mode for the even registers and VOIDmode for the odd
462 (for the cpu models where the odd ones are inaccessible). */
463 if (reg_raw_mode[i] == VOIDmode)
464 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1];
468 /* Finish initializing the register sets and
469 initialize the register modes. */
474 /* This finishes what was started by init_reg_sets, but couldn't be done
475 until after register usage was specified. */
480 #ifdef HAVE_SECONDARY_RELOADS
482 /* Make some fake stack-frame MEM references for use in
483 memory_move_secondary_cost. */
485 for (i = 0; i < MAX_MACHINE_MODE; i++)
486 top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx);
487 ggc_add_rtx_root (top_of_stack, MAX_MACHINE_MODE);
492 #ifdef HAVE_SECONDARY_RELOADS
494 /* Compute extra cost of moving registers to/from memory due to reloads.
495 Only needed if secondary reloads are required for memory moves. */
498 memory_move_secondary_cost (mode, class, in)
499 enum machine_mode mode;
500 enum reg_class class;
503 enum reg_class altclass;
504 int partial_cost = 0;
505 /* We need a memory reference to feed to SECONDARY... macros. */
506 /* mem may be unused even if the SECONDARY_ macros are defined. */
507 rtx mem ATTRIBUTE_UNUSED = top_of_stack[(int) mode];
512 #ifdef SECONDARY_INPUT_RELOAD_CLASS
513 altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem);
520 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
521 altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem);
527 if (altclass == NO_REGS)
531 partial_cost = REGISTER_MOVE_COST (altclass, class);
533 partial_cost = REGISTER_MOVE_COST (class, altclass);
535 if (class == altclass)
536 /* This isn't simply a copy-to-temporary situation. Can't guess
537 what it is, so MEMORY_MOVE_COST really ought not to be calling
540 I'm tempted to put in an abort here, but returning this will
541 probably only give poor estimates, which is what we would've
542 had before this code anyways. */
545 /* Check if the secondary reload register will also need a
547 return memory_move_secondary_cost (mode, altclass, in) + partial_cost;
551 /* Return a machine mode that is legitimate for hard reg REGNO and large
552 enough to save nregs. If we can't find one, return VOIDmode. */
555 choose_hard_reg_mode (regno, nregs)
559 enum machine_mode found_mode = VOIDmode, mode;
561 /* We first look for the largest integer mode that can be validly
562 held in REGNO. If none, we look for the largest floating-point mode.
563 If we still didn't find a valid mode, try CCmode. */
565 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
567 mode = GET_MODE_WIDER_MODE (mode))
568 if (HARD_REGNO_NREGS (regno, mode) == nregs
569 && HARD_REGNO_MODE_OK (regno, mode))
572 if (found_mode != VOIDmode)
575 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
577 mode = GET_MODE_WIDER_MODE (mode))
578 if (HARD_REGNO_NREGS (regno, mode) == nregs
579 && HARD_REGNO_MODE_OK (regno, mode))
582 if (found_mode != VOIDmode)
585 if (HARD_REGNO_NREGS (regno, CCmode) == nregs
586 && HARD_REGNO_MODE_OK (regno, CCmode))
589 /* We can't find a mode valid for this register. */
593 /* Specify the usage characteristics of the register named NAME.
594 It should be a fixed register if FIXED and a
595 call-used register if CALL_USED. */
598 fix_register (name, fixed, call_used)
600 int fixed, call_used;
604 /* Decode the name and update the primary form of
605 the register info. */
607 if ((i = decode_reg_name (name)) >= 0)
609 if ((i == STACK_POINTER_REGNUM
610 #ifdef HARD_FRAME_POINTER_REGNUM
611 || i == HARD_FRAME_POINTER_REGNUM
613 || i == FRAME_POINTER_REGNUM
616 && (fixed == 0 || call_used == 0))
618 static const char * const what_option[2][2] = {
619 { "call-saved", "call-used" },
620 { "no-such-option", "fixed" }};
622 error ("can't use '%s' as a %s register", name,
623 what_option[fixed][call_used]);
627 fixed_regs[i] = fixed;
628 call_used_regs[i] = call_used;
633 warning ("unknown register name: %s", name);
637 /* Mark register number I as global. */
643 if (fixed_regs[i] == 0 && no_global_reg_vars)
644 error ("global register variable follows a function definition");
648 warning ("register used for two global register variables");
652 if (call_used_regs[i] && ! fixed_regs[i])
653 warning ("call-clobbered register used for global register variable");
657 /* If already fixed, nothing else to do. */
661 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
664 SET_HARD_REG_BIT (fixed_reg_set, i);
665 SET_HARD_REG_BIT (call_used_reg_set, i);
666 SET_HARD_REG_BIT (call_fixed_reg_set, i);
669 /* Now the data and code for the `regclass' pass, which happens
670 just before local-alloc. */
672 /* The `costs' struct records the cost of using a hard register of each class
673 and of using memory for each pseudo. We use this data to set up
674 register class preferences. */
678 int cost[N_REG_CLASSES];
682 /* Structure used to record preferrences of given pseudo. */
685 /* (enum reg_class) prefclass is the preferred class. */
688 /* altclass is a register class that we should use for allocating
689 pseudo if no register in the preferred class is available.
690 If no register in this class is available, memory is preferred.
692 It might appear to be more general to have a bitmask of classes here,
693 but since it is recommended that there be a class corresponding to the
694 union of most major pair of classes, that generality is not required. */
698 /* Record the cost of each class for each pseudo. */
700 static struct costs *costs;
702 /* Initialized once, and used to initialize cost values for each insn. */
704 static struct costs init_cost;
706 /* Record preferrences of each pseudo.
707 This is available after `regclass' is run. */
709 static struct reg_pref *reg_pref;
711 /* Allocated buffers for reg_pref. */
713 static struct reg_pref *reg_pref_buffer;
715 /* Account for the fact that insns within a loop are executed very commonly,
716 but don't keep doing this as loops go too deep. */
718 static int loop_cost;
720 static rtx scan_one_insn PROTO((rtx, int));
721 static void record_operand_costs PROTO((rtx, struct costs *, struct reg_pref *));
722 static void dump_regclass PROTO((FILE *));
723 static void record_reg_classes PROTO((int, int, rtx *, enum machine_mode *,
724 char *, const char **, rtx,
725 struct costs *, struct reg_pref *));
726 static int copy_cost PROTO((rtx, enum machine_mode,
727 enum reg_class, int));
728 static void record_address_regs PROTO((rtx, enum reg_class, int));
729 #ifdef FORBIDDEN_INC_DEC_CLASSES
730 static int auto_inc_dec_reg_p PROTO((rtx, enum machine_mode));
732 static void reg_scan_mark_refs PROTO((rtx, rtx, int, int));
734 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
735 This function is sometimes called before the info has been computed.
736 When that happens, just return GENERAL_REGS, which is innocuous. */
739 reg_preferred_class (regno)
744 return (enum reg_class) reg_pref[regno].prefclass;
748 reg_alternate_class (regno)
754 return (enum reg_class) reg_pref[regno].altclass;
757 /* Initialize some global data for this pass. */
764 init_cost.mem_cost = 10000;
765 for (i = 0; i < N_REG_CLASSES; i++)
766 init_cost.cost[i] = 10000;
768 /* This prevents dump_flow_info from losing if called
769 before regclass is run. */
772 /* No more global register variables may be declared. */
773 no_global_reg_vars = 1;
776 /* Dump register costs. */
781 static const char *const reg_class_names[] = REG_CLASS_NAMES;
783 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
785 enum reg_class class;
788 fprintf (dump, " Register %i costs:", i);
789 for (class = 0; class < N_REG_CLASSES; class++)
790 fprintf (dump, " %s:%i", reg_class_names[(int) class],
791 costs[i].cost[class]);
792 fprintf (dump, " MEM:%i\n", costs[i].mem_cost);
798 /* Calculate the costs of insn operands. */
801 record_operand_costs (insn, op_costs, reg_pref)
803 struct costs *op_costs;
804 struct reg_pref *reg_pref;
806 const char *constraints[MAX_RECOG_OPERANDS];
807 enum machine_mode modes[MAX_RECOG_OPERANDS];
808 char subreg_changes_size[MAX_RECOG_OPERANDS];
811 for (i = 0; i < recog_data.n_operands; i++)
813 constraints[i] = recog_data.constraints[i];
814 modes[i] = recog_data.operand_mode[i];
816 memset (subreg_changes_size, 0, sizeof (subreg_changes_size));
818 /* If we get here, we are set up to record the costs of all the
819 operands for this insn. Start by initializing the costs.
820 Then handle any address registers. Finally record the desired
821 classes for any pseudos, doing it twice if some pair of
822 operands are commutative. */
824 for (i = 0; i < recog_data.n_operands; i++)
826 op_costs[i] = init_cost;
828 if (GET_CODE (recog_data.operand[i]) == SUBREG)
830 rtx inner = SUBREG_REG (recog_data.operand[i]);
831 if (GET_MODE_SIZE (modes[i]) != GET_MODE_SIZE (GET_MODE (inner)))
832 subreg_changes_size[i] = 1;
833 recog_data.operand[i] = inner;
836 if (GET_CODE (recog_data.operand[i]) == MEM)
837 record_address_regs (XEXP (recog_data.operand[i], 0),
838 BASE_REG_CLASS, loop_cost * 2);
839 else if (constraints[i][0] == 'p')
840 record_address_regs (recog_data.operand[i],
841 BASE_REG_CLASS, loop_cost * 2);
844 /* Check for commutative in a separate loop so everything will
845 have been initialized. We must do this even if one operand
846 is a constant--see addsi3 in m68k.md. */
848 for (i = 0; i < (int) recog_data.n_operands - 1; i++)
849 if (constraints[i][0] == '%')
851 const char *xconstraints[MAX_RECOG_OPERANDS];
854 /* Handle commutative operands by swapping the constraints.
855 We assume the modes are the same. */
857 for (j = 0; j < recog_data.n_operands; j++)
858 xconstraints[j] = constraints[j];
860 xconstraints[i] = constraints[i+1];
861 xconstraints[i+1] = constraints[i];
862 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
863 recog_data.operand, modes, subreg_changes_size,
864 xconstraints, insn, op_costs, reg_pref);
867 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
868 recog_data.operand, modes, subreg_changes_size,
869 constraints, insn, op_costs, reg_pref);
872 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
873 time it would save code to put a certain register in a certain class.
874 PASS, when nonzero, inhibits some optimizations which need only be done
876 Return the last insn processed, so that the scan can be continued from
880 scan_one_insn (insn, pass)
884 enum rtx_code code = GET_CODE (insn);
885 enum rtx_code pat_code;
888 struct costs op_costs[MAX_RECOG_OPERANDS];
890 if (GET_RTX_CLASS (code) != 'i')
893 pat_code = GET_CODE (PATTERN (insn));
895 || pat_code == CLOBBER
896 || pat_code == ASM_INPUT
897 || pat_code == ADDR_VEC
898 || pat_code == ADDR_DIFF_VEC)
901 set = single_set (insn);
904 /* If this insn loads a parameter from its stack slot, then
905 it represents a savings, rather than a cost, if the
906 parameter is stored in memory. Record this fact. */
908 if (set != 0 && GET_CODE (SET_DEST (set)) == REG
909 && GET_CODE (SET_SRC (set)) == MEM
910 && (note = find_reg_note (insn, REG_EQUIV,
912 && GET_CODE (XEXP (note, 0)) == MEM)
914 costs[REGNO (SET_DEST (set))].mem_cost
915 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)),
918 record_address_regs (XEXP (SET_SRC (set), 0),
919 BASE_REG_CLASS, loop_cost * 2);
923 /* Improve handling of two-address insns such as
924 (set X (ashift CONST Y)) where CONST must be made to
925 match X. Change it into two insns: (set X CONST)
926 (set X (ashift X Y)). If we left this for reloading, it
927 would probably get three insns because X and Y might go
928 in the same place. This prevents X and Y from receiving
931 We can only do this if the modes of operands 0 and 1
932 (which might not be the same) are tieable and we only need
933 do this during our first pass. */
935 if (pass == 0 && optimize
936 && recog_data.n_operands >= 3
937 && recog_data.constraints[1][0] == '0'
938 && recog_data.constraints[1][1] == 0
939 && CONSTANT_P (recog_data.operand[1])
940 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1])
941 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2])
942 && GET_CODE (recog_data.operand[0]) == REG
943 && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]),
944 recog_data.operand_mode[1]))
946 rtx previnsn = prev_real_insn (insn);
948 = gen_lowpart (recog_data.operand_mode[1],
949 recog_data.operand[0]);
951 = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn);
953 /* If this insn was the start of a basic block,
954 include the new insn in that block.
955 We need not check for code_label here;
956 while a basic block can start with a code_label,
957 INSN could not be at the beginning of that block. */
958 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
961 for (b = 0; b < n_basic_blocks; b++)
962 if (insn == BLOCK_HEAD (b))
963 BLOCK_HEAD (b) = newinsn;
966 /* This makes one more setting of new insns's dest. */
967 REG_N_SETS (REGNO (recog_data.operand[0]))++;
969 *recog_data.operand_loc[1] = recog_data.operand[0];
970 for (i = recog_data.n_dups - 1; i >= 0; i--)
971 if (recog_data.dup_num[i] == 1)
972 *recog_data.dup_loc[i] = recog_data.operand[0];
974 return PREV_INSN (newinsn);
977 record_operand_costs (insn, op_costs, reg_pref);
979 /* Now add the cost for each operand to the total costs for
982 for (i = 0; i < recog_data.n_operands; i++)
983 if (GET_CODE (recog_data.operand[i]) == REG
984 && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER)
986 int regno = REGNO (recog_data.operand[i]);
987 struct costs *p = &costs[regno], *q = &op_costs[i];
989 p->mem_cost += q->mem_cost * loop_cost;
990 for (j = 0; j < N_REG_CLASSES; j++)
991 p->cost[j] += q->cost[j] * loop_cost;
997 /* This is a pass of the compiler that scans all instructions
998 and calculates the preferred class for each pseudo-register.
999 This information can be accessed later by calling `reg_preferred_class'.
1000 This pass comes just before local register allocation. */
1003 regclass (f, nregs, dump)
1014 costs = (struct costs *) xmalloc (nregs * sizeof (struct costs));
1016 #ifdef FORBIDDEN_INC_DEC_CLASSES
1018 in_inc_dec = (char *) xmalloc (nregs);
1020 /* Initialize information about which register classes can be used for
1021 pseudos that are auto-incremented or auto-decremented. It would
1022 seem better to put this in init_reg_sets, but we need to be able
1023 to allocate rtx, which we can't do that early. */
1025 for (i = 0; i < N_REG_CLASSES; i++)
1027 rtx r = gen_rtx_REG (VOIDmode, 0);
1028 enum machine_mode m;
1031 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
1032 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
1036 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE;
1037 m = (enum machine_mode) ((int) m + 1))
1038 if (HARD_REGNO_MODE_OK (j, m))
1042 /* If a register is not directly suitable for an
1043 auto-increment or decrement addressing mode and
1044 requires secondary reloads, disallow its class from
1045 being used in such addresses. */
1048 #ifdef SECONDARY_RELOAD_CLASS
1049 || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1052 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1053 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1056 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1057 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1062 && ! auto_inc_dec_reg_p (r, m))
1063 forbidden_inc_dec_class[i] = 1;
1067 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1069 /* Normally we scan the insns once and determine the best class to use for
1070 each register. However, if -fexpensive_optimizations are on, we do so
1071 twice, the second time using the tentative best classes to guide the
1074 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
1079 fprintf (dump, "\n\nPass %i\n\n",pass);
1080 /* Zero out our accumulation of the cost of each class for each reg. */
1082 bzero ((char *) costs, nregs * sizeof (struct costs));
1084 #ifdef FORBIDDEN_INC_DEC_CLASSES
1085 bzero (in_inc_dec, nregs);
1088 /* Scan the instructions and record each time it would
1089 save code to put a certain register in a certain class. */
1094 for (insn = f; insn; insn = NEXT_INSN (insn))
1095 insn = scan_one_insn (insn, pass);
1098 for (index = 0; index < n_basic_blocks; index++)
1100 basic_block bb = BASIC_BLOCK (index);
1102 /* Show that an insn inside a loop is likely to be executed three
1103 times more than insns outside a loop. This is much more aggressive
1104 than the assumptions made elsewhere and is being tried as an
1109 loop_cost = 1 << (2 * MIN (bb->loop_depth - 1, 5));
1110 for (insn = bb->head; ; insn = NEXT_INSN (insn))
1112 insn = scan_one_insn (insn, pass);
1113 if (insn == bb->end)
1118 /* Now for each register look at how desirable each class is
1119 and find which class is preferred. Store that in
1120 `prefclass'. Record in `altclass' the largest register
1121 class any of whose registers is better than memory. */
1124 reg_pref = reg_pref_buffer;
1128 dump_regclass (dump);
1129 fprintf (dump,"\n");
1131 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
1133 register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
1134 enum reg_class best = ALL_REGS, alt = NO_REGS;
1135 /* This is an enum reg_class, but we call it an int
1136 to save lots of casts. */
1138 register struct costs *p = &costs[i];
1140 if (!REG_N_REFS (i))
1143 for (class = (int) ALL_REGS - 1; class > 0; class--)
1145 /* Ignore classes that are too small for this operand or
1146 invalid for a operand that was auto-incremented. */
1147 if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i))
1148 > reg_class_size[class]
1149 #ifdef FORBIDDEN_INC_DEC_CLASSES
1150 || (in_inc_dec[i] && forbidden_inc_dec_class[class])
1154 else if (p->cost[class] < best_cost)
1156 best_cost = p->cost[class];
1157 best = (enum reg_class) class;
1159 else if (p->cost[class] == best_cost)
1160 best = reg_class_subunion[(int)best][class];
1163 /* Record the alternate register class; i.e., a class for which
1164 every register in it is better than using memory. If adding a
1165 class would make a smaller class (i.e., no union of just those
1166 classes exists), skip that class. The major unions of classes
1167 should be provided as a register class. Don't do this if we
1168 will be doing it again later. */
1170 if ((pass == 1 || dump) || ! flag_expensive_optimizations)
1171 for (class = 0; class < N_REG_CLASSES; class++)
1172 if (p->cost[class] < p->mem_cost
1173 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]]
1174 > reg_class_size[(int) alt])
1175 #ifdef FORBIDDEN_INC_DEC_CLASSES
1176 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class])
1179 alt = reg_class_subunion[(int) alt][class];
1181 /* If we don't add any classes, nothing to try. */
1186 && (reg_pref[i].prefclass != (int) best
1187 || reg_pref[i].altclass != (int) alt))
1189 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1190 fprintf (dump, " Register %i", i);
1191 if (alt == ALL_REGS || best == ALL_REGS)
1192 fprintf (dump, " pref %s\n", reg_class_names[(int) best]);
1193 else if (alt == NO_REGS)
1194 fprintf (dump, " pref %s or none\n", reg_class_names[(int) best]);
1196 fprintf (dump, " pref %s, else %s\n",
1197 reg_class_names[(int) best],
1198 reg_class_names[(int) alt]);
1201 /* We cast to (int) because (char) hits bugs in some compilers. */
1202 reg_pref[i].prefclass = (int) best;
1203 reg_pref[i].altclass = (int) alt;
1207 #ifdef FORBIDDEN_INC_DEC_CLASSES
1213 /* Record the cost of using memory or registers of various classes for
1214 the operands in INSN.
1216 N_ALTS is the number of alternatives.
1218 N_OPS is the number of operands.
1220 OPS is an array of the operands.
1222 MODES are the modes of the operands, in case any are VOIDmode.
1224 CONSTRAINTS are the constraints to use for the operands. This array
1225 is modified by this procedure.
1227 This procedure works alternative by alternative. For each alternative
1228 we assume that we will be able to allocate all pseudos to their ideal
1229 register class and calculate the cost of using that alternative. Then
1230 we compute for each operand that is a pseudo-register, the cost of
1231 having the pseudo allocated to each register class and using it in that
1232 alternative. To this cost is added the cost of the alternative.
1234 The cost of each class for this insn is its lowest cost among all the
1238 record_reg_classes (n_alts, n_ops, ops, modes, subreg_changes_size,
1239 constraints, insn, op_costs, reg_pref)
1243 enum machine_mode *modes;
1244 char *subreg_changes_size ATTRIBUTE_UNUSED;
1245 const char **constraints;
1247 struct costs *op_costs;
1248 struct reg_pref *reg_pref;
1254 /* Process each alternative, each time minimizing an operand's cost with
1255 the cost for each operand in that alternative. */
1257 for (alt = 0; alt < n_alts; alt++)
1259 struct costs this_op_costs[MAX_RECOG_OPERANDS];
1262 enum reg_class classes[MAX_RECOG_OPERANDS];
1263 int allows_mem[MAX_RECOG_OPERANDS];
1266 for (i = 0; i < n_ops; i++)
1268 const char *p = constraints[i];
1270 enum machine_mode mode = modes[i];
1271 int allows_addr = 0;
1275 /* Initially show we know nothing about the register class. */
1276 classes[i] = NO_REGS;
1279 /* If this operand has no constraints at all, we can conclude
1280 nothing about it since anything is valid. */
1284 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1285 bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]);
1290 /* If this alternative is only relevant when this operand
1291 matches a previous operand, we do different things depending
1292 on whether this operand is a pseudo-reg or not. We must process
1293 any modifiers for the operand before we can make this test. */
1295 while (*p == '%' || *p == '=' || *p == '+' || *p == '&')
1298 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
1300 /* Copy class and whether memory is allowed from the matching
1301 alternative. Then perform any needed cost computations
1302 and/or adjustments. */
1304 classes[i] = classes[j];
1305 allows_mem[i] = allows_mem[j];
1307 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER)
1309 /* If this matches the other operand, we have no added
1311 if (rtx_equal_p (ops[j], op))
1314 /* If we can put the other operand into a register, add to
1315 the cost of this alternative the cost to copy this
1316 operand to the register used for the other operand. */
1318 else if (classes[j] != NO_REGS)
1319 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1;
1321 else if (GET_CODE (ops[j]) != REG
1322 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
1324 /* This op is a pseudo but the one it matches is not. */
1326 /* If we can't put the other operand into a register, this
1327 alternative can't be used. */
1329 if (classes[j] == NO_REGS)
1332 /* Otherwise, add to the cost of this alternative the cost
1333 to copy the other operand to the register used for this
1337 alt_cost += copy_cost (ops[j], mode, classes[j], 1);
1341 /* The costs of this operand are not the same as the other
1342 operand since move costs are not symmetric. Moreover,
1343 if we cannot tie them, this alternative needs to do a
1344 copy, which is one instruction. */
1346 struct costs *pp = &this_op_costs[i];
1348 for (class = 0; class < N_REG_CLASSES; class++)
1350 = ((recog_data.operand_type[i] != OP_OUT
1351 ? may_move_in_cost[class][(int) classes[i]]
1353 + (recog_data.operand_type[i] != OP_IN
1354 ? may_move_out_cost[(int) classes[i]][class]
1357 /* If the alternative actually allows memory, make things
1358 a bit cheaper since we won't need an extra insn to
1362 = ((recog_data.operand_type[i] != OP_IN
1363 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1365 + (recog_data.operand_type[i] != OP_OUT
1366 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1367 : 0) - allows_mem[i]);
1369 /* If we have assigned a class to this register in our
1370 first pass, add a cost to this alternative corresponding
1371 to what we would add if this register were not in the
1372 appropriate class. */
1376 += (may_move_in_cost[(unsigned char) reg_pref[REGNO (op)].prefclass]
1377 [(int) classes[i]]);
1379 if (REGNO (ops[i]) != REGNO (ops[j])
1380 && ! find_reg_note (insn, REG_DEAD, op))
1383 /* This is in place of ordinary cost computation
1384 for this operand, so skip to the end of the
1385 alternative (should be just one character). */
1386 while (*p && *p++ != ',')
1394 /* Scan all the constraint letters. See if the operand matches
1395 any of the constraints. Collect the valid register classes
1396 and see if this operand accepts memory. */
1398 while (*p && (c = *p++) != ',')
1402 /* Ignore the next letter for this pass. */
1408 case '!': case '#': case '&':
1409 case '0': case '1': case '2': case '3': case '4':
1410 case '5': case '6': case '7': case '8': case '9':
1415 win = address_operand (op, GET_MODE (op));
1416 /* We know this operand is an address, so we want it to be
1417 allocated to a register that can be the base of an
1418 address, ie BASE_REG_CLASS. */
1420 = reg_class_subunion[(int) classes[i]]
1421 [(int) BASE_REG_CLASS];
1424 case 'm': case 'o': case 'V':
1425 /* It doesn't seem worth distinguishing between offsettable
1426 and non-offsettable addresses here. */
1428 if (GET_CODE (op) == MEM)
1433 if (GET_CODE (op) == MEM
1434 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1435 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1440 if (GET_CODE (op) == MEM
1441 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1442 || GET_CODE (XEXP (op, 0)) == POST_INC))
1447 #ifndef REAL_ARITHMETIC
1448 /* Match any floating double constant, but only if
1449 we can examine the bits of it reliably. */
1450 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1451 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1452 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1455 if (GET_CODE (op) == CONST_DOUBLE)
1460 if (GET_CODE (op) == CONST_DOUBLE)
1466 if (GET_CODE (op) == CONST_DOUBLE
1467 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
1472 if (GET_CODE (op) == CONST_INT
1473 || (GET_CODE (op) == CONST_DOUBLE
1474 && GET_MODE (op) == VOIDmode))
1478 #ifdef LEGITIMATE_PIC_OPERAND_P
1479 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1486 if (GET_CODE (op) == CONST_INT
1487 || (GET_CODE (op) == CONST_DOUBLE
1488 && GET_MODE (op) == VOIDmode))
1500 if (GET_CODE (op) == CONST_INT
1501 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
1509 #ifdef EXTRA_CONSTRAINT
1515 if (EXTRA_CONSTRAINT (op, c))
1521 if (GET_CODE (op) == MEM
1523 #ifdef LEGITIMATE_PIC_OPERAND_P
1524 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1531 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1536 = reg_class_subunion[(int) classes[i]]
1537 [(int) REG_CLASS_FROM_LETTER (c)];
1542 #ifdef CLASS_CANNOT_CHANGE_SIZE
1543 /* If we noted a subreg earlier, and the selected class is a
1544 subclass of CLASS_CANNOT_CHANGE_SIZE, zap it. */
1545 if (subreg_changes_size[i]
1546 && (reg_class_subunion[(int) CLASS_CANNOT_CHANGE_SIZE]
1548 == CLASS_CANNOT_CHANGE_SIZE))
1549 classes[i] = NO_REGS;
1552 /* How we account for this operand now depends on whether it is a
1553 pseudo register or not. If it is, we first check if any
1554 register classes are valid. If not, we ignore this alternative,
1555 since we want to assume that all pseudos get allocated for
1556 register preferencing. If some register class is valid, compute
1557 the costs of moving the pseudo into that class. */
1559 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1561 if (classes[i] == NO_REGS)
1563 /* We must always fail if the operand is a REG, but
1564 we did not find a suitable class.
1566 Otherwise we may perform an uninitialized read
1567 from this_op_costs after the `continue' statement
1573 struct costs *pp = &this_op_costs[i];
1575 for (class = 0; class < N_REG_CLASSES; class++)
1577 = ((recog_data.operand_type[i] != OP_OUT
1578 ? may_move_in_cost[class][(int) classes[i]]
1580 + (recog_data.operand_type[i] != OP_IN
1581 ? may_move_out_cost[(int) classes[i]][class]
1584 /* If the alternative actually allows memory, make things
1585 a bit cheaper since we won't need an extra insn to
1589 = ((recog_data.operand_type[i] != OP_IN
1590 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1592 + (recog_data.operand_type[i] != OP_OUT
1593 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1594 : 0) - allows_mem[i]);
1596 /* If we have assigned a class to this register in our
1597 first pass, add a cost to this alternative corresponding
1598 to what we would add if this register were not in the
1599 appropriate class. */
1603 += (may_move_in_cost[(unsigned char) reg_pref[REGNO (op)].prefclass]
1604 [(int) classes[i]]);
1608 /* Otherwise, if this alternative wins, either because we
1609 have already determined that or if we have a hard register of
1610 the proper class, there is no cost for this alternative. */
1613 || (GET_CODE (op) == REG
1614 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op))))
1617 /* If registers are valid, the cost of this alternative includes
1618 copying the object to and/or from a register. */
1620 else if (classes[i] != NO_REGS)
1622 if (recog_data.operand_type[i] != OP_OUT)
1623 alt_cost += copy_cost (op, mode, classes[i], 1);
1625 if (recog_data.operand_type[i] != OP_IN)
1626 alt_cost += copy_cost (op, mode, classes[i], 0);
1629 /* The only other way this alternative can be used is if this is a
1630 constant that could be placed into memory. */
1632 else if (CONSTANT_P (op) && (allows_addr || allows_mem[i]))
1633 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1);
1641 /* Finally, update the costs with the information we've calculated
1642 about this alternative. */
1644 for (i = 0; i < n_ops; i++)
1645 if (GET_CODE (ops[i]) == REG
1646 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1648 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1649 int scale = 1 + (recog_data.operand_type[i] == OP_INOUT);
1651 pp->mem_cost = MIN (pp->mem_cost,
1652 (qq->mem_cost + alt_cost) * scale);
1654 for (class = 0; class < N_REG_CLASSES; class++)
1655 pp->cost[class] = MIN (pp->cost[class],
1656 (qq->cost[class] + alt_cost) * scale);
1660 /* If this insn is a single set copying operand 1 to operand 0
1661 and one operand is a pseudo with the other a hard reg or a pseudo
1662 that prefers a register that is in its own register class then
1663 we may want to adjust the cost of that register class to -1.
1665 Avoid the adjustment if the source does not die to avoid stressing of
1666 register allocator by preferrencing two coliding registers into single
1669 Also avoid the adjustment if a copy between registers of the class
1670 is expensive (ten times the cost of a default copy is considered
1671 arbitrarily expensive). This avoids losing when the preferred class
1672 is very expensive as the source of a copy instruction. */
1674 if ((set = single_set (insn)) != 0
1675 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set)
1676 && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG
1677 && find_regno_note (insn, REG_DEAD, REGNO (ops[1])))
1678 for (i = 0; i <= 1; i++)
1679 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1681 int regno = REGNO (ops[!i]);
1682 enum machine_mode mode = GET_MODE (ops[!i]);
1686 if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0)
1688 enum reg_class pref = reg_pref[regno].prefclass;
1690 if ((reg_class_size[(unsigned char) pref]
1691 == CLASS_MAX_NREGS (pref, mode))
1692 && REGISTER_MOVE_COST (pref, pref) < 10 * 2)
1693 op_costs[i].cost[(unsigned char) pref] = -1;
1695 else if (regno < FIRST_PSEUDO_REGISTER)
1696 for (class = 0; class < N_REG_CLASSES; class++)
1697 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1698 && reg_class_size[class] == CLASS_MAX_NREGS (class, mode))
1700 if (reg_class_size[class] == 1)
1701 op_costs[i].cost[class] = -1;
1704 for (nr = 0; nr < HARD_REGNO_NREGS(regno, mode); nr++)
1706 if (!TEST_HARD_REG_BIT (reg_class_contents[class], regno + nr))
1710 if (nr == HARD_REGNO_NREGS(regno,mode))
1711 op_costs[i].cost[class] = -1;
1717 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1718 TO_P is zero) a register of class CLASS in mode MODE.
1720 X must not be a pseudo. */
1723 copy_cost (x, mode, class, to_p)
1725 enum machine_mode mode;
1726 enum reg_class class;
1729 #ifdef HAVE_SECONDARY_RELOADS
1730 enum reg_class secondary_class = NO_REGS;
1733 /* If X is a SCRATCH, there is actually nothing to move since we are
1734 assuming optimal allocation. */
1736 if (GET_CODE (x) == SCRATCH)
1739 /* Get the class we will actually use for a reload. */
1740 class = PREFERRED_RELOAD_CLASS (x, class);
1742 #ifdef HAVE_SECONDARY_RELOADS
1743 /* If we need a secondary reload (we assume here that we are using
1744 the secondary reload as an intermediate, not a scratch register), the
1745 cost is that to load the input into the intermediate register, then
1746 to copy them. We use a special value of TO_P to avoid recursion. */
1748 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1750 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x);
1753 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1755 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x);
1758 if (secondary_class != NO_REGS)
1759 return (move_cost[(int) secondary_class][(int) class]
1760 + copy_cost (x, mode, secondary_class, 2));
1761 #endif /* HAVE_SECONDARY_RELOADS */
1763 /* For memory, use the memory move cost, for (hard) registers, use the
1764 cost to move between the register classes, and use 2 for everything
1765 else (constants). */
1767 if (GET_CODE (x) == MEM || class == NO_REGS)
1768 return MEMORY_MOVE_COST (mode, class, to_p);
1770 else if (GET_CODE (x) == REG)
1771 return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class];
1774 /* If this is a constant, we may eventually want to call rtx_cost here. */
1778 /* Record the pseudo registers we must reload into hard registers
1779 in a subexpression of a memory address, X.
1781 CLASS is the class that the register needs to be in and is either
1782 BASE_REG_CLASS or INDEX_REG_CLASS.
1784 SCALE is twice the amount to multiply the cost by (it is twice so we
1785 can represent half-cost adjustments). */
1788 record_address_regs (x, class, scale)
1790 enum reg_class class;
1793 register enum rtx_code code = GET_CODE (x);
1806 /* When we have an address that is a sum,
1807 we must determine whether registers are "base" or "index" regs.
1808 If there is a sum of two registers, we must choose one to be
1809 the "base". Luckily, we can use the REGNO_POINTER_FLAG
1810 to make a good choice most of the time. We only need to do this
1811 on machines that can have two registers in an address and where
1812 the base and index register classes are different.
1814 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1815 that seems bogus since it should only be set when we are sure
1816 the register is being used as a pointer. */
1819 rtx arg0 = XEXP (x, 0);
1820 rtx arg1 = XEXP (x, 1);
1821 register enum rtx_code code0 = GET_CODE (arg0);
1822 register enum rtx_code code1 = GET_CODE (arg1);
1824 /* Look inside subregs. */
1825 if (code0 == SUBREG)
1826 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1827 if (code1 == SUBREG)
1828 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1830 /* If this machine only allows one register per address, it must
1831 be in the first operand. */
1833 if (MAX_REGS_PER_ADDRESS == 1)
1834 record_address_regs (arg0, class, scale);
1836 /* If index and base registers are the same on this machine, just
1837 record registers in any non-constant operands. We assume here,
1838 as well as in the tests below, that all addresses are in
1841 else if (INDEX_REG_CLASS == BASE_REG_CLASS)
1843 record_address_regs (arg0, class, scale);
1844 if (! CONSTANT_P (arg1))
1845 record_address_regs (arg1, class, scale);
1848 /* If the second operand is a constant integer, it doesn't change
1849 what class the first operand must be. */
1851 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
1852 record_address_regs (arg0, class, scale);
1854 /* If the second operand is a symbolic constant, the first operand
1855 must be an index register. */
1857 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
1858 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1860 /* If both operands are registers but one is already a hard register
1861 of index or base class, give the other the class that the hard
1864 #ifdef REG_OK_FOR_BASE_P
1865 else if (code0 == REG && code1 == REG
1866 && REGNO (arg0) < FIRST_PSEUDO_REGISTER
1867 && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0)))
1868 record_address_regs (arg1,
1869 REG_OK_FOR_BASE_P (arg0)
1870 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1872 else if (code0 == REG && code1 == REG
1873 && REGNO (arg1) < FIRST_PSEUDO_REGISTER
1874 && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1)))
1875 record_address_regs (arg0,
1876 REG_OK_FOR_BASE_P (arg1)
1877 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1881 /* If one operand is known to be a pointer, it must be the base
1882 with the other operand the index. Likewise if the other operand
1885 else if ((code0 == REG && REGNO_POINTER_FLAG (REGNO (arg0)))
1888 record_address_regs (arg0, BASE_REG_CLASS, scale);
1889 record_address_regs (arg1, INDEX_REG_CLASS, scale);
1891 else if ((code1 == REG && REGNO_POINTER_FLAG (REGNO (arg1)))
1894 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1895 record_address_regs (arg1, BASE_REG_CLASS, scale);
1898 /* Otherwise, count equal chances that each might be a base
1899 or index register. This case should be rare. */
1903 record_address_regs (arg0, BASE_REG_CLASS, scale / 2);
1904 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2);
1905 record_address_regs (arg1, BASE_REG_CLASS, scale / 2);
1906 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2);
1915 /* Double the importance of a pseudo register that is incremented
1916 or decremented, since it would take two extra insns
1917 if it ends up in the wrong place. If the operand is a pseudo,
1918 show it is being used in an INC_DEC context. */
1920 #ifdef FORBIDDEN_INC_DEC_CLASSES
1921 if (GET_CODE (XEXP (x, 0)) == REG
1922 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
1923 in_inc_dec[REGNO (XEXP (x, 0))] = 1;
1926 record_address_regs (XEXP (x, 0), class, 2 * scale);
1931 register struct costs *pp = &costs[REGNO (x)];
1934 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2;
1936 for (i = 0; i < N_REG_CLASSES; i++)
1937 pp->cost[i] += (may_move_in_cost[i][(int) class] * scale) / 2;
1943 register const char *fmt = GET_RTX_FORMAT (code);
1945 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1947 record_address_regs (XEXP (x, i), class, scale);
1952 #ifdef FORBIDDEN_INC_DEC_CLASSES
1954 /* Return 1 if REG is valid as an auto-increment memory reference
1955 to an object of MODE. */
1958 auto_inc_dec_reg_p (reg, mode)
1960 enum machine_mode mode;
1962 if (HAVE_POST_INCREMENT
1963 && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg)))
1966 if (HAVE_POST_DECREMENT
1967 && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg)))
1970 if (HAVE_PRE_INCREMENT
1971 && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg)))
1974 if (HAVE_PRE_DECREMENT
1975 && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg)))
1982 static short *renumber = (short *)0;
1983 static size_t regno_allocated = 0;
1985 /* Allocate enough space to hold NUM_REGS registers for the tables used for
1986 reg_scan and flow_analysis that are indexed by the register number. If
1987 NEW_P is non zero, initialize all of the registers, otherwise only
1988 initialize the new registers allocated. The same table is kept from
1989 function to function, only reallocating it when we need more room. If
1990 RENUMBER_P is non zero, allocate the reg_renumber array also. */
1993 allocate_reg_info (num_regs, new_p, renumber_p)
1999 size_t size_renumber;
2000 size_t min = (new_p) ? 0 : reg_n_max;
2001 struct reg_info_data *reg_data;
2002 struct reg_info_data *reg_next;
2004 if (num_regs > regno_allocated)
2006 size_t old_allocated = regno_allocated;
2008 regno_allocated = num_regs + (num_regs / 20); /* add some slop space */
2009 size_renumber = regno_allocated * sizeof (short);
2013 VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info");
2014 renumber = (short *) xmalloc (size_renumber);
2015 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated
2016 * sizeof (struct reg_pref));
2021 VARRAY_GROW (reg_n_info, regno_allocated);
2023 if (new_p) /* if we're zapping everything, no need to realloc */
2025 free ((char *)renumber);
2026 free ((char *)reg_pref);
2027 renumber = (short *) xmalloc (size_renumber);
2028 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated
2029 * sizeof (struct reg_pref));
2034 renumber = (short *) xrealloc ((char *)renumber, size_renumber);
2035 reg_pref_buffer = (struct reg_pref *) xrealloc ((char *)reg_pref_buffer,
2037 * sizeof (struct reg_pref));
2041 size_info = (regno_allocated - old_allocated) * sizeof (reg_info)
2042 + sizeof (struct reg_info_data) - sizeof (reg_info);
2043 reg_data = (struct reg_info_data *) xcalloc (size_info, 1);
2044 reg_data->min_index = old_allocated;
2045 reg_data->max_index = regno_allocated - 1;
2046 reg_data->next = reg_info_head;
2047 reg_info_head = reg_data;
2050 reg_n_max = num_regs;
2053 /* Loop through each of the segments allocated for the actual
2054 reg_info pages, and set up the pointers, zero the pages, etc. */
2055 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
2057 size_t min_index = reg_data->min_index;
2058 size_t max_index = reg_data->max_index;
2060 reg_next = reg_data->next;
2061 if (min <= max_index)
2063 size_t max = max_index;
2064 size_t local_min = min - min_index;
2067 if (min < min_index)
2069 if (!reg_data->used_p) /* page just allocated with calloc */
2070 reg_data->used_p = 1; /* no need to zero */
2072 bzero ((char *) ®_data->data[local_min],
2073 sizeof (reg_info) * (max - min_index - local_min + 1));
2075 for (i = min_index+local_min; i <= max; i++)
2077 VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index];
2078 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN;
2080 reg_pref_buffer[i].prefclass = (char) NO_REGS;
2081 reg_pref_buffer[i].altclass = (char) NO_REGS;
2087 /* If {pref,alt}class have already been allocated, update the pointers to
2088 the newly realloced ones. */
2090 reg_pref = reg_pref_buffer;
2093 reg_renumber = renumber;
2095 /* Tell the regset code about the new number of registers */
2096 MAX_REGNO_REG_SET (num_regs, new_p, renumber_p);
2099 /* Free up the space allocated by allocate_reg_info. */
2105 struct reg_info_data *reg_data;
2106 struct reg_info_data *reg_next;
2108 VARRAY_FREE (reg_n_info);
2109 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
2111 reg_next = reg_data->next;
2112 free ((char *)reg_data);
2115 free (reg_pref_buffer);
2116 reg_pref_buffer = (struct reg_pref *)0;
2117 reg_info_head = (struct reg_info_data *)0;
2118 renumber = (short *)0;
2120 regno_allocated = 0;
2124 /* This is the `regscan' pass of the compiler, run just before cse
2125 and again just before loop.
2127 It finds the first and last use of each pseudo-register
2128 and records them in the vectors regno_first_uid, regno_last_uid
2129 and counts the number of sets in the vector reg_n_sets.
2131 REPEAT is nonzero the second time this is called. */
2133 /* Maximum number of parallel sets and clobbers in any insn in this fn.
2134 Always at least 3, since the combiner could put that many together
2135 and we want this to remain correct for all the remaining passes. */
2140 reg_scan (f, nregs, repeat)
2143 int repeat ATTRIBUTE_UNUSED;
2147 allocate_reg_info (nregs, TRUE, FALSE);
2150 for (insn = f; insn; insn = NEXT_INSN (insn))
2151 if (GET_CODE (insn) == INSN
2152 || GET_CODE (insn) == CALL_INSN
2153 || GET_CODE (insn) == JUMP_INSN)
2155 if (GET_CODE (PATTERN (insn)) == PARALLEL
2156 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2157 max_parallel = XVECLEN (PATTERN (insn), 0);
2158 reg_scan_mark_refs (PATTERN (insn), insn, 0, 0);
2160 if (REG_NOTES (insn))
2161 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0);
2165 /* Update 'regscan' information by looking at the insns
2166 from FIRST to LAST. Some new REGs have been created,
2167 and any REG with number greater than OLD_MAX_REGNO is
2168 such a REG. We only update information for those. */
2171 reg_scan_update(first, last, old_max_regno)
2178 allocate_reg_info (max_reg_num (), FALSE, FALSE);
2180 for (insn = first; insn != last; insn = NEXT_INSN (insn))
2181 if (GET_CODE (insn) == INSN
2182 || GET_CODE (insn) == CALL_INSN
2183 || GET_CODE (insn) == JUMP_INSN)
2185 if (GET_CODE (PATTERN (insn)) == PARALLEL
2186 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2187 max_parallel = XVECLEN (PATTERN (insn), 0);
2188 reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno);
2190 if (REG_NOTES (insn))
2191 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno);
2195 /* X is the expression to scan. INSN is the insn it appears in.
2196 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2197 We should only record information for REGs with numbers
2198 greater than or equal to MIN_REGNO. */
2201 reg_scan_mark_refs (x, insn, note_flag, min_regno)
2207 register enum rtx_code code;
2211 code = GET_CODE (x);
2227 register int regno = REGNO (x);
2229 if (regno >= min_regno)
2231 REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn);
2233 REGNO_LAST_UID (regno) = INSN_UID (insn);
2234 if (REGNO_FIRST_UID (regno) == 0)
2235 REGNO_FIRST_UID (regno) = INSN_UID (insn);
2242 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno);
2244 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2249 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2253 /* Count a set of the destination if it is a register. */
2254 for (dest = SET_DEST (x);
2255 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
2256 || GET_CODE (dest) == ZERO_EXTEND;
2257 dest = XEXP (dest, 0))
2260 if (GET_CODE (dest) == REG
2261 && REGNO (dest) >= min_regno)
2262 REG_N_SETS (REGNO (dest))++;
2264 /* If this is setting a pseudo from another pseudo or the sum of a
2265 pseudo and a constant integer and the other pseudo is known to be
2266 a pointer, set the destination to be a pointer as well.
2268 Likewise if it is setting the destination from an address or from a
2269 value equivalent to an address or to the sum of an address and
2272 But don't do any of this if the pseudo corresponds to a user
2273 variable since it should have already been set as a pointer based
2276 if (GET_CODE (SET_DEST (x)) == REG
2277 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER
2278 && REGNO (SET_DEST (x)) >= min_regno
2279 /* If the destination pseudo is set more than once, then other
2280 sets might not be to a pointer value (consider access to a
2281 union in two threads of control in the presense of global
2282 optimizations). So only set REGNO_POINTER_FLAG on the destination
2283 pseudo if this is the only set of that pseudo. */
2284 && REG_N_SETS (REGNO (SET_DEST (x))) == 1
2285 && ! REG_USERVAR_P (SET_DEST (x))
2286 && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x)))
2287 && ((GET_CODE (SET_SRC (x)) == REG
2288 && REGNO_POINTER_FLAG (REGNO (SET_SRC (x))))
2289 || ((GET_CODE (SET_SRC (x)) == PLUS
2290 || GET_CODE (SET_SRC (x)) == LO_SUM)
2291 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2292 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2293 && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x), 0))))
2294 || GET_CODE (SET_SRC (x)) == CONST
2295 || GET_CODE (SET_SRC (x)) == SYMBOL_REF
2296 || GET_CODE (SET_SRC (x)) == LABEL_REF
2297 || (GET_CODE (SET_SRC (x)) == HIGH
2298 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
2299 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
2300 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
2301 || ((GET_CODE (SET_SRC (x)) == PLUS
2302 || GET_CODE (SET_SRC (x)) == LO_SUM)
2303 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
2304 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
2305 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
2306 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
2307 && (GET_CODE (XEXP (note, 0)) == CONST
2308 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
2309 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
2310 REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) = 1;
2312 /* ... fall through ... */
2316 register const char *fmt = GET_RTX_FORMAT (code);
2318 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2321 reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno);
2322 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
2325 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2326 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno);
2333 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2337 reg_class_subset_p (c1, c2)
2338 register enum reg_class c1;
2339 register enum reg_class c2;
2341 if (c1 == c2) return 1;
2346 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1],
2347 reg_class_contents[(int)c2],
2352 /* Return nonzero if there is a register that is in both C1 and C2. */
2355 reg_classes_intersect_p (c1, c2)
2356 register enum reg_class c1;
2357 register enum reg_class c2;
2364 if (c1 == c2) return 1;
2366 if (c1 == ALL_REGS || c2 == ALL_REGS)
2369 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
2370 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
2372 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose);
2379 /* Release any memory allocated by register sets. */
2382 regset_release_memory ()
2384 bitmap_release_memory ();