1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996
3 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
23 /* This file contains two passes of the compiler: reg_scan and reg_class.
24 It also defines some tables of information about the hardware registers
25 and a function init_reg_sets to initialize the tables. */
29 #include "coretypes.h"
31 #include "hard-reg-set.h"
36 #include "basic-block.h"
38 #include "addresses.h"
40 #include "insn-config.h"
50 #include "tree-pass.h"
53 /* Maximum register number used in this function, plus one. */
57 static void init_reg_sets_1 (void);
58 static void init_reg_autoinc (void);
60 /* If we have auto-increment or auto-decrement and we can have secondary
61 reloads, we are not allowed to use classes requiring secondary
62 reloads for pseudos auto-incremented since reload can't handle it. */
63 /* We leave it to target hooks to decide if we have secondary reloads, so
64 assume that we might have them. */
65 #if defined(AUTO_INC_DEC) /* */
66 #define FORBIDDEN_INC_DEC_CLASSES
69 /* Register tables used by many passes. */
71 /* Indexed by hard register number, contains 1 for registers
72 that are fixed use (stack pointer, pc, frame pointer, etc.).
73 These are the registers that cannot be used to allocate
74 a pseudo reg for general use. */
76 char fixed_regs[FIRST_PSEUDO_REGISTER];
78 /* Same info as a HARD_REG_SET. */
80 HARD_REG_SET fixed_reg_set;
82 /* Data for initializing the above. */
84 static const char initial_fixed_regs[] = FIXED_REGISTERS;
86 /* Indexed by hard register number, contains 1 for registers
87 that are fixed use or are clobbered by function calls.
88 These are the registers that cannot be used to allocate
89 a pseudo reg whose life crosses calls unless we are able
90 to save/restore them across the calls. */
92 char call_used_regs[FIRST_PSEUDO_REGISTER];
94 /* Same info as a HARD_REG_SET. */
96 HARD_REG_SET call_used_reg_set;
98 /* HARD_REG_SET of registers we want to avoid caller saving. */
99 HARD_REG_SET losing_caller_save_reg_set;
101 /* Data for initializing the above. */
103 static const char initial_call_used_regs[] = CALL_USED_REGISTERS;
105 /* This is much like call_used_regs, except it doesn't have to
106 be a superset of FIXED_REGISTERS. This vector indicates
107 what is really call clobbered, and is used when defining
108 regs_invalidated_by_call. */
110 #ifdef CALL_REALLY_USED_REGISTERS
111 char call_really_used_regs[] = CALL_REALLY_USED_REGISTERS;
114 #ifdef CALL_REALLY_USED_REGISTERS
115 #define CALL_REALLY_USED_REGNO_P(X) call_really_used_regs[X]
117 #define CALL_REALLY_USED_REGNO_P(X) call_used_regs[X]
121 /* Indexed by hard register number, contains 1 for registers that are
122 fixed use or call used registers that cannot hold quantities across
123 calls even if we are willing to save and restore them. call fixed
124 registers are a subset of call used registers. */
126 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
128 /* The same info as a HARD_REG_SET. */
130 HARD_REG_SET call_fixed_reg_set;
132 /* Indexed by hard register number, contains 1 for registers
133 that are being used for global register decls.
134 These must be exempt from ordinary flow analysis
135 and are also considered fixed. */
137 char global_regs[FIRST_PSEUDO_REGISTER];
139 /* Contains 1 for registers that are set or clobbered by calls. */
140 /* ??? Ideally, this would be just call_used_regs plus global_regs, but
141 for someone's bright idea to have call_used_regs strictly include
142 fixed_regs. Which leaves us guessing as to the set of fixed_regs
143 that are actually preserved. We know for sure that those associated
144 with the local stack frame are safe, but scant others. */
146 HARD_REG_SET regs_invalidated_by_call;
148 /* Table of register numbers in the order in which to try to use them. */
149 #ifdef REG_ALLOC_ORDER
150 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
152 /* The inverse of reg_alloc_order. */
153 int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER];
156 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
158 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
160 /* The same information, but as an array of unsigned ints. We copy from
161 these unsigned ints to the table above. We do this so the tm.h files
162 do not have to be aware of the wordsize for machines with <= 64 regs.
163 Note that we hard-code 32 here, not HOST_BITS_PER_INT. */
166 ((FIRST_PSEUDO_REGISTER + (32 - 1)) / 32)
168 static const unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
169 = REG_CLASS_CONTENTS;
171 /* For each reg class, number of regs it contains. */
173 unsigned int reg_class_size[N_REG_CLASSES];
175 /* For each reg class, table listing all the containing classes. */
177 static enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
179 /* For each reg class, table listing all the classes contained in it. */
181 static enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
183 /* For each pair of reg classes,
184 a largest reg class contained in their union. */
186 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
188 /* For each pair of reg classes,
189 the smallest reg class containing their union. */
191 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
193 /* Array containing all of the register names. */
195 const char * reg_names[] = REGISTER_NAMES;
197 /* Array containing all of the register class names. */
199 const char * reg_class_names[] = REG_CLASS_NAMES;
201 /* For each hard register, the widest mode object that it can contain.
202 This will be a MODE_INT mode if the register can hold integers. Otherwise
203 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
206 enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER];
208 /* 1 if there is a register of given mode. */
210 bool have_regs_of_mode [MAX_MACHINE_MODE];
212 /* 1 if class does contain register of given mode. */
214 static char contains_reg_of_mode [N_REG_CLASSES] [MAX_MACHINE_MODE];
216 typedef unsigned short move_table[N_REG_CLASSES];
218 /* Maximum cost of moving from a register in one class to a register in
219 another class. Based on REGISTER_MOVE_COST. */
221 static move_table *move_cost[MAX_MACHINE_MODE];
223 /* Similar, but here we don't have to move if the first index is a subset
224 of the second so in that case the cost is zero. */
226 static move_table *may_move_in_cost[MAX_MACHINE_MODE];
228 /* Similar, but here we don't have to move if the first index is a superset
229 of the second so in that case the cost is zero. */
231 static move_table *may_move_out_cost[MAX_MACHINE_MODE];
233 #ifdef FORBIDDEN_INC_DEC_CLASSES
235 /* These are the classes that regs which are auto-incremented or decremented
238 static int forbidden_inc_dec_class[N_REG_CLASSES];
240 /* Indexed by n, is nonzero if (REG n) is used in an auto-inc or auto-dec
243 static char *in_inc_dec;
245 #endif /* FORBIDDEN_INC_DEC_CLASSES */
247 /* Sample MEM values for use by memory_move_secondary_cost. */
249 static GTY(()) rtx top_of_stack[MAX_MACHINE_MODE];
251 /* No more global register variables may be declared; true once
252 regclass has been initialized. */
254 static int no_global_reg_vars = 0;
256 /* Specify number of hard registers given machine mode occupy. */
257 unsigned char hard_regno_nregs[FIRST_PSEUDO_REGISTER][MAX_MACHINE_MODE];
259 /* Given a register bitmap, turn on the bits in a HARD_REG_SET that
260 correspond to the hard registers, if any, set in that map. This
261 could be done far more efficiently by having all sorts of special-cases
262 with moving single words, but probably isn't worth the trouble. */
265 reg_set_to_hard_reg_set (HARD_REG_SET *to, const_bitmap from)
270 EXECUTE_IF_SET_IN_BITMAP (from, 0, i, bi)
272 if (i >= FIRST_PSEUDO_REGISTER)
274 SET_HARD_REG_BIT (*to, i);
279 /* Function called only once to initialize the above data on reg usage.
280 Once this is done, various switches may override. */
287 /* First copy the register information from the initial int form into
290 for (i = 0; i < N_REG_CLASSES; i++)
292 CLEAR_HARD_REG_SET (reg_class_contents[i]);
294 /* Note that we hard-code 32 here, not HOST_BITS_PER_INT. */
295 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
296 if (int_reg_class_contents[i][j / 32]
297 & ((unsigned) 1 << (j % 32)))
298 SET_HARD_REG_BIT (reg_class_contents[i], j);
301 /* Sanity check: make sure the target macros FIXED_REGISTERS and
302 CALL_USED_REGISTERS had the right number of initializers. */
303 gcc_assert (sizeof fixed_regs == sizeof initial_fixed_regs);
304 gcc_assert (sizeof call_used_regs == sizeof initial_call_used_regs);
306 memcpy (fixed_regs, initial_fixed_regs, sizeof fixed_regs);
307 memcpy (call_used_regs, initial_call_used_regs, sizeof call_used_regs);
308 memset (global_regs, 0, sizeof global_regs);
310 #ifdef REG_ALLOC_ORDER
311 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
312 inv_reg_alloc_order[reg_alloc_order[i]] = i;
316 /* Initialize may_move_cost and friends for mode M. */
319 init_move_cost (enum machine_mode m)
321 static unsigned short last_move_cost[N_REG_CLASSES][N_REG_CLASSES];
322 static int last_mode = -1;
323 bool all_match = true;
326 gcc_assert (have_regs_of_mode[m]);
327 for (i = 0; i < N_REG_CLASSES; i++)
328 if (contains_reg_of_mode[i][m])
329 for (j = 0; j < N_REG_CLASSES; j++)
332 if (!contains_reg_of_mode[j][m])
336 cost = REGISTER_MOVE_COST (m, i, j);
337 gcc_assert (cost < 65535);
339 all_match &= (last_move_cost[i][j] == cost);
340 last_move_cost[i][j] = cost;
342 if (all_match && last_mode != -1)
344 move_cost[m] = move_cost[last_mode];
345 may_move_in_cost[m] = may_move_in_cost[last_mode];
346 may_move_out_cost[m] = may_move_out_cost[last_mode];
350 move_cost[m] = (move_table *)xmalloc (sizeof (move_table)
352 may_move_in_cost[m] = (move_table *)xmalloc (sizeof (move_table)
354 may_move_out_cost[m] = (move_table *)xmalloc (sizeof (move_table)
356 for (i = 0; i < N_REG_CLASSES; i++)
357 if (contains_reg_of_mode[i][m])
358 for (j = 0; j < N_REG_CLASSES; j++)
361 enum reg_class *p1, *p2;
363 if (last_move_cost[i][j] == 65535)
365 move_cost[m][i][j] = 65535;
366 may_move_in_cost[m][i][j] = 65535;
367 may_move_out_cost[m][i][j] = 65535;
371 cost = last_move_cost[i][j];
373 for (p2 = ®_class_subclasses[j][0];
374 *p2 != LIM_REG_CLASSES; p2++)
375 if (*p2 != i && contains_reg_of_mode[*p2][m])
376 cost = MAX (cost, move_cost[m][i][*p2]);
378 for (p1 = ®_class_subclasses[i][0];
379 *p1 != LIM_REG_CLASSES; p1++)
380 if (*p1 != j && contains_reg_of_mode[*p1][m])
381 cost = MAX (cost, move_cost[m][*p1][j]);
383 gcc_assert (cost <= 65535);
384 move_cost[m][i][j] = cost;
386 if (reg_class_subset_p (i, j))
387 may_move_in_cost[m][i][j] = 0;
389 may_move_in_cost[m][i][j] = cost;
391 if (reg_class_subset_p (j, i))
392 may_move_out_cost[m][i][j] = 0;
394 may_move_out_cost[m][i][j] = cost;
398 for (j = 0; j < N_REG_CLASSES; j++)
400 move_cost[m][i][j] = 65535;
401 may_move_in_cost[m][i][j] = 65535;
402 may_move_out_cost[m][i][j] = 65535;
406 /* After switches have been processed, which perhaps alter
407 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
410 init_reg_sets_1 (void)
413 unsigned int /* enum machine_mode */ m;
415 /* This macro allows the fixed or call-used registers
416 and the register classes to depend on target flags. */
418 #ifdef CONDITIONAL_REGISTER_USAGE
419 CONDITIONAL_REGISTER_USAGE;
422 /* Compute number of hard regs in each class. */
424 memset (reg_class_size, 0, sizeof reg_class_size);
425 for (i = 0; i < N_REG_CLASSES; i++)
426 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
427 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
430 /* Initialize the table of subunions.
431 reg_class_subunion[I][J] gets the largest-numbered reg-class
432 that is contained in the union of classes I and J. */
434 for (i = 0; i < N_REG_CLASSES; i++)
436 for (j = 0; j < N_REG_CLASSES; j++)
441 COPY_HARD_REG_SET (c, reg_class_contents[i]);
442 IOR_HARD_REG_SET (c, reg_class_contents[j]);
443 for (k = 0; k < N_REG_CLASSES; k++)
444 if (hard_reg_set_subset_p (reg_class_contents[k], c)
445 && !hard_reg_set_subset_p (reg_class_contents[k],
447 [(int) reg_class_subunion[i][j]]))
448 reg_class_subunion[i][j] = (enum reg_class) k;
452 /* Initialize the table of superunions.
453 reg_class_superunion[I][J] gets the smallest-numbered reg-class
454 containing the union of classes I and J. */
456 for (i = 0; i < N_REG_CLASSES; i++)
458 for (j = 0; j < N_REG_CLASSES; j++)
463 COPY_HARD_REG_SET (c, reg_class_contents[i]);
464 IOR_HARD_REG_SET (c, reg_class_contents[j]);
465 for (k = 0; k < N_REG_CLASSES; k++)
466 if (hard_reg_set_subset_p (c, reg_class_contents[k]))
469 reg_class_superunion[i][j] = (enum reg_class) k;
473 /* Initialize the tables of subclasses and superclasses of each reg class.
474 First clear the whole table, then add the elements as they are found. */
476 for (i = 0; i < N_REG_CLASSES; i++)
478 for (j = 0; j < N_REG_CLASSES; j++)
480 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
481 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
485 for (i = 0; i < N_REG_CLASSES; i++)
487 if (i == (int) NO_REGS)
490 for (j = i + 1; j < N_REG_CLASSES; j++)
491 if (hard_reg_set_subset_p (reg_class_contents[i],
492 reg_class_contents[j]))
494 /* Reg class I is a subclass of J.
495 Add J to the table of superclasses of I. */
498 p = ®_class_superclasses[i][0];
499 while (*p != LIM_REG_CLASSES) p++;
500 *p = (enum reg_class) j;
501 /* Add I to the table of superclasses of J. */
502 p = ®_class_subclasses[j][0];
503 while (*p != LIM_REG_CLASSES) p++;
504 *p = (enum reg_class) i;
508 /* Initialize "constant" tables. */
510 CLEAR_HARD_REG_SET (fixed_reg_set);
511 CLEAR_HARD_REG_SET (call_used_reg_set);
512 CLEAR_HARD_REG_SET (call_fixed_reg_set);
513 CLEAR_HARD_REG_SET (regs_invalidated_by_call);
515 memcpy (call_fixed_regs, fixed_regs, sizeof call_fixed_regs);
517 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
519 /* call_used_regs must include fixed_regs. */
520 gcc_assert (!fixed_regs[i] || call_used_regs[i]);
521 #ifdef CALL_REALLY_USED_REGISTERS
522 /* call_used_regs must include call_really_used_regs. */
523 gcc_assert (!call_really_used_regs[i] || call_used_regs[i]);
527 SET_HARD_REG_BIT (fixed_reg_set, i);
529 if (call_used_regs[i])
530 SET_HARD_REG_BIT (call_used_reg_set, i);
531 if (call_fixed_regs[i])
532 SET_HARD_REG_BIT (call_fixed_reg_set, i);
533 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i)))
534 SET_HARD_REG_BIT (losing_caller_save_reg_set, i);
536 /* There are a couple of fixed registers that we know are safe to
537 exclude from being clobbered by calls:
539 The frame pointer is always preserved across calls. The arg pointer
540 is if it is fixed. The stack pointer usually is, unless
541 RETURN_POPS_ARGS, in which case an explicit CLOBBER will be present.
542 If we are generating PIC code, the PIC offset table register is
543 preserved across calls, though the target can override that. */
545 if (i == STACK_POINTER_REGNUM)
547 else if (global_regs[i])
548 SET_HARD_REG_BIT (regs_invalidated_by_call, i);
549 else if (i == FRAME_POINTER_REGNUM)
551 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
552 else if (i == HARD_FRAME_POINTER_REGNUM)
555 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
556 else if (i == ARG_POINTER_REGNUM && fixed_regs[i])
559 #ifndef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
560 else if (i == (unsigned) PIC_OFFSET_TABLE_REGNUM && fixed_regs[i])
563 else if (CALL_REALLY_USED_REGNO_P (i))
564 SET_HARD_REG_BIT (regs_invalidated_by_call, i);
567 memset (have_regs_of_mode, 0, sizeof (have_regs_of_mode));
568 memset (contains_reg_of_mode, 0, sizeof (contains_reg_of_mode));
569 for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++)
571 HARD_REG_SET ok_regs;
572 CLEAR_HARD_REG_SET (ok_regs);
573 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
574 if (!fixed_regs [j] && HARD_REGNO_MODE_OK (j, m))
575 SET_HARD_REG_BIT (ok_regs, j);
577 for (i = 0; i < N_REG_CLASSES; i++)
578 if ((unsigned) CLASS_MAX_NREGS (i, m) <= reg_class_size[i]
579 && hard_reg_set_intersect_p (ok_regs, reg_class_contents[i]))
581 contains_reg_of_mode [i][m] = 1;
582 have_regs_of_mode [m] = 1;
587 /* Compute the table of register modes.
588 These values are used to record death information for individual registers
589 (as opposed to a multi-register mode). */
592 init_reg_modes_once (void)
596 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
597 for (j = 0; j < MAX_MACHINE_MODE; j++)
598 hard_regno_nregs[i][j] = HARD_REGNO_NREGS(i, (enum machine_mode)j);
600 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
602 reg_raw_mode[i] = choose_hard_reg_mode (i, 1, false);
604 /* If we couldn't find a valid mode, just use the previous mode.
605 ??? One situation in which we need to do this is on the mips where
606 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
607 to use DF mode for the even registers and VOIDmode for the odd
608 (for the cpu models where the odd ones are inaccessible). */
609 if (reg_raw_mode[i] == VOIDmode)
610 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1];
614 /* Finish initializing the register sets and
615 initialize the register modes. */
620 /* This finishes what was started by init_reg_sets, but couldn't be done
621 until after register usage was specified. */
627 /* Initialize some fake stack-frame MEM references for use in
628 memory_move_secondary_cost. */
631 init_fake_stack_mems (void)
636 for (i = 0; i < MAX_MACHINE_MODE; i++)
637 top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx);
642 /* Compute extra cost of moving registers to/from memory due to reloads.
643 Only needed if secondary reloads are required for memory moves. */
646 memory_move_secondary_cost (enum machine_mode mode, enum reg_class class, int in)
648 enum reg_class altclass;
649 int partial_cost = 0;
650 /* We need a memory reference to feed to SECONDARY... macros. */
651 /* mem may be unused even if the SECONDARY_ macros are defined. */
652 rtx mem ATTRIBUTE_UNUSED = top_of_stack[(int) mode];
655 altclass = secondary_reload_class (in ? 1 : 0, class, mode, mem);
657 if (altclass == NO_REGS)
661 partial_cost = REGISTER_MOVE_COST (mode, altclass, class);
663 partial_cost = REGISTER_MOVE_COST (mode, class, altclass);
665 if (class == altclass)
666 /* This isn't simply a copy-to-temporary situation. Can't guess
667 what it is, so MEMORY_MOVE_COST really ought not to be calling
670 I'm tempted to put in an assert here, but returning this will
671 probably only give poor estimates, which is what we would've
672 had before this code anyways. */
675 /* Check if the secondary reload register will also need a
677 return memory_move_secondary_cost (mode, altclass, in) + partial_cost;
680 /* Return a machine mode that is legitimate for hard reg REGNO and large
681 enough to save nregs. If we can't find one, return VOIDmode.
682 If CALL_SAVED is true, only consider modes that are call saved. */
685 choose_hard_reg_mode (unsigned int regno ATTRIBUTE_UNUSED,
686 unsigned int nregs, bool call_saved)
688 unsigned int /* enum machine_mode */ m;
689 enum machine_mode found_mode = VOIDmode, mode;
691 /* We first look for the largest integer mode that can be validly
692 held in REGNO. If none, we look for the largest floating-point mode.
693 If we still didn't find a valid mode, try CCmode. */
695 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
697 mode = GET_MODE_WIDER_MODE (mode))
698 if ((unsigned) hard_regno_nregs[regno][mode] == nregs
699 && HARD_REGNO_MODE_OK (regno, mode)
700 && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
703 if (found_mode != VOIDmode)
706 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
708 mode = GET_MODE_WIDER_MODE (mode))
709 if ((unsigned) hard_regno_nregs[regno][mode] == nregs
710 && HARD_REGNO_MODE_OK (regno, mode)
711 && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
714 if (found_mode != VOIDmode)
717 for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT);
719 mode = GET_MODE_WIDER_MODE (mode))
720 if ((unsigned) hard_regno_nregs[regno][mode] == nregs
721 && HARD_REGNO_MODE_OK (regno, mode)
722 && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
725 if (found_mode != VOIDmode)
728 for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT);
730 mode = GET_MODE_WIDER_MODE (mode))
731 if ((unsigned) hard_regno_nregs[regno][mode] == nregs
732 && HARD_REGNO_MODE_OK (regno, mode)
733 && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
736 if (found_mode != VOIDmode)
739 /* Iterate over all of the CCmodes. */
740 for (m = (unsigned int) CCmode; m < (unsigned int) NUM_MACHINE_MODES; ++m)
742 mode = (enum machine_mode) m;
743 if ((unsigned) hard_regno_nregs[regno][mode] == nregs
744 && HARD_REGNO_MODE_OK (regno, mode)
745 && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
749 /* We can't find a mode valid for this register. */
753 /* Specify the usage characteristics of the register named NAME.
754 It should be a fixed register if FIXED and a
755 call-used register if CALL_USED. */
758 fix_register (const char *name, int fixed, int call_used)
762 /* Decode the name and update the primary form of
763 the register info. */
765 if ((i = decode_reg_name (name)) >= 0)
767 if ((i == STACK_POINTER_REGNUM
768 #ifdef HARD_FRAME_POINTER_REGNUM
769 || i == HARD_FRAME_POINTER_REGNUM
771 || i == FRAME_POINTER_REGNUM
774 && (fixed == 0 || call_used == 0))
776 static const char * const what_option[2][2] = {
777 { "call-saved", "call-used" },
778 { "no-such-option", "fixed" }};
780 error ("can't use '%s' as a %s register", name,
781 what_option[fixed][call_used]);
785 fixed_regs[i] = fixed;
786 call_used_regs[i] = call_used;
787 #ifdef CALL_REALLY_USED_REGISTERS
789 call_really_used_regs[i] = call_used;
795 warning (0, "unknown register name: %s", name);
799 /* Mark register number I as global. */
802 globalize_reg (int i)
804 if (fixed_regs[i] == 0 && no_global_reg_vars)
805 error ("global register variable follows a function definition");
809 warning (0, "register used for two global register variables");
813 if (call_used_regs[i] && ! fixed_regs[i])
814 warning (0, "call-clobbered register used for global register variable");
818 /* If we're globalizing the frame pointer, we need to set the
819 appropriate regs_invalidated_by_call bit, even if it's already
820 set in fixed_regs. */
821 if (i != STACK_POINTER_REGNUM)
822 SET_HARD_REG_BIT (regs_invalidated_by_call, i);
824 /* If already fixed, nothing else to do. */
828 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
829 #ifdef CALL_REALLY_USED_REGISTERS
830 call_really_used_regs[i] = 1;
833 SET_HARD_REG_BIT (fixed_reg_set, i);
834 SET_HARD_REG_BIT (call_used_reg_set, i);
835 SET_HARD_REG_BIT (call_fixed_reg_set, i);
838 /* Now the data and code for the `regclass' pass, which happens
839 just before local-alloc. */
841 /* The `costs' struct records the cost of using a hard register of each class
842 and of using memory for each pseudo. We use this data to set up
843 register class preferences. */
847 int cost[N_REG_CLASSES];
851 /* Structure used to record preferences of given pseudo. */
854 /* (enum reg_class) prefclass is the preferred class. May be
855 NO_REGS if no class is better than memory. */
858 /* altclass is a register class that we should use for allocating
859 pseudo if no register in the preferred class is available.
860 If no register in this class is available, memory is preferred.
862 It might appear to be more general to have a bitmask of classes here,
863 but since it is recommended that there be a class corresponding to the
864 union of most major pair of classes, that generality is not required. */
868 /* Record the cost of each class for each pseudo. */
870 static struct costs *costs;
872 /* Initialized once, and used to initialize cost values for each insn. */
874 static struct costs init_cost;
876 /* Record preferences of each pseudo.
877 This is available after `regclass' is run. */
879 static struct reg_pref *reg_pref;
881 /* Frequency of executions of current insn. */
883 static int frequency;
885 static rtx scan_one_insn (rtx, int);
886 static void record_operand_costs (rtx, struct costs *, struct reg_pref *);
887 static void dump_regclass (FILE *);
888 static void record_reg_classes (int, int, rtx *, enum machine_mode *,
889 const char **, rtx, struct costs *,
891 static int copy_cost (rtx, enum machine_mode, enum reg_class, int,
892 secondary_reload_info *);
893 static void record_address_regs (enum machine_mode, rtx, int, enum rtx_code,
895 #ifdef FORBIDDEN_INC_DEC_CLASSES
896 static int auto_inc_dec_reg_p (rtx, enum machine_mode);
898 static void reg_scan_mark_refs (rtx, rtx);
900 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudo registers. */
903 ok_for_index_p_nonstrict (rtx reg)
905 unsigned regno = REGNO (reg);
906 return regno >= FIRST_PSEUDO_REGISTER || REGNO_OK_FOR_INDEX_P (regno);
909 /* A version of regno_ok_for_base_p for use during regclass, when all pseudos
910 should count as OK. Arguments as for regno_ok_for_base_p. */
913 ok_for_base_p_nonstrict (rtx reg, enum machine_mode mode,
914 enum rtx_code outer_code, enum rtx_code index_code)
916 unsigned regno = REGNO (reg);
917 if (regno >= FIRST_PSEUDO_REGISTER)
920 return ok_for_base_p_1 (regno, mode, outer_code, index_code);
923 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
924 This function is sometimes called before the info has been computed.
925 When that happens, just return GENERAL_REGS, which is innocuous. */
928 reg_preferred_class (int regno)
932 return (enum reg_class) reg_pref[regno].prefclass;
936 reg_alternate_class (int regno)
941 return (enum reg_class) reg_pref[regno].altclass;
944 /* Initialize some global data for this pass. */
952 df_compute_regs_ever_live (true);
954 init_cost.mem_cost = 10000;
955 for (i = 0; i < N_REG_CLASSES; i++)
956 init_cost.cost[i] = 10000;
958 /* This prevents dump_flow_info from losing if called
959 before regclass is run. */
962 /* No more global register variables may be declared. */
963 no_global_reg_vars = 1;
967 struct tree_opt_pass pass_regclass_init =
969 "regclass", /* name */
971 regclass_init, /* execute */
974 0, /* static_pass_number */
976 0, /* properties_required */
977 0, /* properties_provided */
978 0, /* properties_destroyed */
979 0, /* todo_flags_start */
980 0, /* todo_flags_finish */
986 /* Dump register costs. */
988 dump_regclass (FILE *dump)
991 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
993 int /* enum reg_class */ class;
996 fprintf (dump, " Register %i costs:", i);
997 for (class = 0; class < (int) N_REG_CLASSES; class++)
998 if (contains_reg_of_mode [(enum reg_class) class][PSEUDO_REGNO_MODE (i)]
999 #ifdef FORBIDDEN_INC_DEC_CLASSES
1001 || !forbidden_inc_dec_class[(enum reg_class) class])
1003 #ifdef CANNOT_CHANGE_MODE_CLASS
1004 && ! invalid_mode_change_p (i, (enum reg_class) class,
1005 PSEUDO_REGNO_MODE (i))
1008 fprintf (dump, " %s:%i", reg_class_names[class],
1009 costs[i].cost[(enum reg_class) class]);
1010 fprintf (dump, " MEM:%i\n", costs[i].mem_cost);
1016 /* Calculate the costs of insn operands. */
1019 record_operand_costs (rtx insn, struct costs *op_costs,
1020 struct reg_pref *reg_pref)
1022 const char *constraints[MAX_RECOG_OPERANDS];
1023 enum machine_mode modes[MAX_RECOG_OPERANDS];
1026 for (i = 0; i < recog_data.n_operands; i++)
1028 constraints[i] = recog_data.constraints[i];
1029 modes[i] = recog_data.operand_mode[i];
1032 /* If we get here, we are set up to record the costs of all the
1033 operands for this insn. Start by initializing the costs.
1034 Then handle any address registers. Finally record the desired
1035 classes for any pseudos, doing it twice if some pair of
1036 operands are commutative. */
1038 for (i = 0; i < recog_data.n_operands; i++)
1040 op_costs[i] = init_cost;
1042 if (GET_CODE (recog_data.operand[i]) == SUBREG)
1043 recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]);
1045 if (MEM_P (recog_data.operand[i]))
1046 record_address_regs (GET_MODE (recog_data.operand[i]),
1047 XEXP (recog_data.operand[i], 0),
1048 0, MEM, SCRATCH, frequency * 2);
1049 else if (constraints[i][0] == 'p'
1050 || EXTRA_ADDRESS_CONSTRAINT (constraints[i][0], constraints[i]))
1051 record_address_regs (VOIDmode, recog_data.operand[i], 0, ADDRESS,
1052 SCRATCH, frequency * 2);
1055 /* Check for commutative in a separate loop so everything will
1056 have been initialized. We must do this even if one operand
1057 is a constant--see addsi3 in m68k.md. */
1059 for (i = 0; i < (int) recog_data.n_operands - 1; i++)
1060 if (constraints[i][0] == '%')
1062 const char *xconstraints[MAX_RECOG_OPERANDS];
1065 /* Handle commutative operands by swapping the constraints.
1066 We assume the modes are the same. */
1068 for (j = 0; j < recog_data.n_operands; j++)
1069 xconstraints[j] = constraints[j];
1071 xconstraints[i] = constraints[i+1];
1072 xconstraints[i+1] = constraints[i];
1073 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
1074 recog_data.operand, modes,
1075 xconstraints, insn, op_costs, reg_pref);
1078 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
1079 recog_data.operand, modes,
1080 constraints, insn, op_costs, reg_pref);
1083 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
1084 time it would save code to put a certain register in a certain class.
1085 PASS, when nonzero, inhibits some optimizations which need only be done
1087 Return the last insn processed, so that the scan can be continued from
1091 scan_one_insn (rtx insn, int pass ATTRIBUTE_UNUSED)
1093 enum rtx_code pat_code;
1096 struct costs op_costs[MAX_RECOG_OPERANDS];
1101 pat_code = GET_CODE (PATTERN (insn));
1103 || pat_code == CLOBBER
1104 || pat_code == ASM_INPUT
1105 || pat_code == ADDR_VEC
1106 || pat_code == ADDR_DIFF_VEC)
1109 set = single_set (insn);
1110 extract_insn (insn);
1112 /* If this insn loads a parameter from its stack slot, then
1113 it represents a savings, rather than a cost, if the
1114 parameter is stored in memory. Record this fact. */
1116 if (set != 0 && REG_P (SET_DEST (set))
1117 && MEM_P (SET_SRC (set))
1118 && (note = find_reg_note (insn, REG_EQUIV,
1120 && MEM_P (XEXP (note, 0)))
1122 costs[REGNO (SET_DEST (set))].mem_cost
1123 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)),
1126 record_address_regs (GET_MODE (SET_SRC (set)), XEXP (SET_SRC (set), 0),
1127 0, MEM, SCRATCH, frequency * 2);
1131 record_operand_costs (insn, op_costs, reg_pref);
1133 /* Now add the cost for each operand to the total costs for
1136 for (i = 0; i < recog_data.n_operands; i++)
1137 if (REG_P (recog_data.operand[i])
1138 && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER)
1140 int regno = REGNO (recog_data.operand[i]);
1141 struct costs *p = &costs[regno], *q = &op_costs[i];
1143 p->mem_cost += q->mem_cost * frequency;
1144 for (j = 0; j < N_REG_CLASSES; j++)
1145 p->cost[j] += q->cost[j] * frequency;
1151 /* Initialize information about which register classes can be used for
1152 pseudos that are auto-incremented or auto-decremented. */
1155 init_reg_autoinc (void)
1157 #ifdef FORBIDDEN_INC_DEC_CLASSES
1160 for (i = 0; i < N_REG_CLASSES; i++)
1162 rtx r = gen_rtx_raw_REG (VOIDmode, 0);
1163 enum machine_mode m;
1166 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
1167 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
1171 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE;
1172 m = (enum machine_mode) ((int) m + 1))
1173 if (HARD_REGNO_MODE_OK (j, m))
1175 /* ??? There are two assumptions here; that the base class does not
1176 depend on the exact outer code (POST_INC vs. PRE_INC etc.), and
1177 that it does not depend on the machine mode of the memory
1179 enum reg_class base_class
1180 = base_reg_class (VOIDmode, POST_INC, SCRATCH);
1184 /* If a register is not directly suitable for an
1185 auto-increment or decrement addressing mode and
1186 requires secondary reloads, disallow its class from
1187 being used in such addresses. */
1189 if ((secondary_reload_class (1, base_class, m, r)
1190 || secondary_reload_class (1, base_class, m, r))
1191 && ! auto_inc_dec_reg_p (r, m))
1192 forbidden_inc_dec_class[i] = 1;
1196 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1199 /* This is a pass of the compiler that scans all instructions
1200 and calculates the preferred class for each pseudo-register.
1201 This information can be accessed later by calling `reg_preferred_class'.
1202 This pass comes just before local register allocation. */
1205 regclass (rtx f, int nregs)
1210 max_regno = max_reg_num ();
1214 reg_renumber = xmalloc (max_regno * sizeof (short));
1215 reg_pref = XCNEWVEC (struct reg_pref, max_regno);
1216 memset (reg_renumber, -1, max_regno * sizeof (short));
1218 costs = XNEWVEC (struct costs, nregs);
1220 #ifdef FORBIDDEN_INC_DEC_CLASSES
1222 in_inc_dec = XNEWVEC (char, nregs);
1224 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1226 /* Normally we scan the insns once and determine the best class to use for
1227 each register. However, if -fexpensive_optimizations are on, we do so
1228 twice, the second time using the tentative best classes to guide the
1231 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
1236 fprintf (dump_file, "\n\nPass %i\n\n",pass);
1237 /* Zero out our accumulation of the cost of each class for each reg. */
1239 memset (costs, 0, nregs * sizeof (struct costs));
1241 #ifdef FORBIDDEN_INC_DEC_CLASSES
1242 memset (in_inc_dec, 0, nregs);
1245 /* Scan the instructions and record each time it would
1246 save code to put a certain register in a certain class. */
1250 frequency = REG_FREQ_MAX;
1251 for (insn = f; insn; insn = NEXT_INSN (insn))
1252 insn = scan_one_insn (insn, pass);
1257 /* Show that an insn inside a loop is likely to be executed three
1258 times more than insns outside a loop. This is much more
1259 aggressive than the assumptions made elsewhere and is being
1260 tried as an experiment. */
1261 frequency = REG_FREQ_FROM_BB (bb);
1262 for (insn = BB_HEAD (bb); ; insn = NEXT_INSN (insn))
1264 insn = scan_one_insn (insn, pass);
1265 if (insn == BB_END (bb))
1270 /* Now for each register look at how desirable each class is
1271 and find which class is preferred. Store that in
1272 `prefclass'. Record in `altclass' the largest register
1273 class any of whose registers is better than memory. */
1277 dump_regclass (dump_file);
1278 fprintf (dump_file,"\n");
1280 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
1282 int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
1283 enum reg_class best = ALL_REGS, alt = NO_REGS;
1284 /* This is an enum reg_class, but we call it an int
1285 to save lots of casts. */
1287 struct costs *p = &costs[i];
1289 if (regno_reg_rtx[i] == NULL)
1292 /* In non-optimizing compilation REG_N_REFS is not initialized
1294 if (optimize && !REG_N_REFS (i) && !REG_N_SETS (i))
1297 for (class = (int) ALL_REGS - 1; class > 0; class--)
1299 /* Ignore classes that are too small for this operand or
1300 invalid for an operand that was auto-incremented. */
1301 if (!contains_reg_of_mode [class][PSEUDO_REGNO_MODE (i)]
1302 #ifdef FORBIDDEN_INC_DEC_CLASSES
1303 || (in_inc_dec[i] && forbidden_inc_dec_class[class])
1305 #ifdef CANNOT_CHANGE_MODE_CLASS
1306 || invalid_mode_change_p (i, (enum reg_class) class,
1307 PSEUDO_REGNO_MODE (i))
1311 else if (p->cost[class] < best_cost)
1313 best_cost = p->cost[class];
1314 best = (enum reg_class) class;
1316 else if (p->cost[class] == best_cost)
1317 best = reg_class_subunion[(int) best][class];
1320 /* If no register class is better than memory, use memory. */
1321 if (p->mem_cost < best_cost)
1324 /* Record the alternate register class; i.e., a class for which
1325 every register in it is better than using memory. If adding a
1326 class would make a smaller class (i.e., no union of just those
1327 classes exists), skip that class. The major unions of classes
1328 should be provided as a register class. Don't do this if we
1329 will be doing it again later. */
1331 if ((pass == 1 || dump_file) || ! flag_expensive_optimizations)
1332 for (class = 0; class < N_REG_CLASSES; class++)
1333 if (p->cost[class] < p->mem_cost
1334 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]]
1335 > reg_class_size[(int) alt])
1336 #ifdef FORBIDDEN_INC_DEC_CLASSES
1337 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class])
1339 #ifdef CANNOT_CHANGE_MODE_CLASS
1340 && ! invalid_mode_change_p (i, (enum reg_class) class,
1341 PSEUDO_REGNO_MODE (i))
1344 alt = reg_class_subunion[(int) alt][class];
1346 /* If we don't add any classes, nothing to try. */
1351 && (reg_pref[i].prefclass != (int) best
1352 || reg_pref[i].altclass != (int) alt))
1354 fprintf (dump_file, " Register %i", i);
1355 if (alt == ALL_REGS || best == ALL_REGS)
1356 fprintf (dump_file, " pref %s\n", reg_class_names[(int) best]);
1357 else if (alt == NO_REGS)
1358 fprintf (dump_file, " pref %s or none\n", reg_class_names[(int) best]);
1360 fprintf (dump_file, " pref %s, else %s\n",
1361 reg_class_names[(int) best],
1362 reg_class_names[(int) alt]);
1365 /* We cast to (int) because (char) hits bugs in some compilers. */
1366 reg_pref[i].prefclass = (int) best;
1367 reg_pref[i].altclass = (int) alt;
1371 #ifdef FORBIDDEN_INC_DEC_CLASSES
1377 /* Record the cost of using memory or registers of various classes for
1378 the operands in INSN.
1380 N_ALTS is the number of alternatives.
1382 N_OPS is the number of operands.
1384 OPS is an array of the operands.
1386 MODES are the modes of the operands, in case any are VOIDmode.
1388 CONSTRAINTS are the constraints to use for the operands. This array
1389 is modified by this procedure.
1391 This procedure works alternative by alternative. For each alternative
1392 we assume that we will be able to allocate all pseudos to their ideal
1393 register class and calculate the cost of using that alternative. Then
1394 we compute for each operand that is a pseudo-register, the cost of
1395 having the pseudo allocated to each register class and using it in that
1396 alternative. To this cost is added the cost of the alternative.
1398 The cost of each class for this insn is its lowest cost among all the
1402 record_reg_classes (int n_alts, int n_ops, rtx *ops,
1403 enum machine_mode *modes, const char **constraints,
1404 rtx insn, struct costs *op_costs,
1405 struct reg_pref *reg_pref)
1411 /* Process each alternative, each time minimizing an operand's cost with
1412 the cost for each operand in that alternative. */
1414 for (alt = 0; alt < n_alts; alt++)
1416 struct costs this_op_costs[MAX_RECOG_OPERANDS];
1419 enum reg_class classes[MAX_RECOG_OPERANDS];
1420 int allows_mem[MAX_RECOG_OPERANDS];
1423 for (i = 0; i < n_ops; i++)
1425 const char *p = constraints[i];
1427 enum machine_mode mode = modes[i];
1428 int allows_addr = 0;
1432 /* Initially show we know nothing about the register class. */
1433 classes[i] = NO_REGS;
1436 /* If this operand has no constraints at all, we can conclude
1437 nothing about it since anything is valid. */
1441 if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1442 memset (&this_op_costs[i], 0, sizeof this_op_costs[i]);
1447 /* If this alternative is only relevant when this operand
1448 matches a previous operand, we do different things depending
1449 on whether this operand is a pseudo-reg or not. We must process
1450 any modifiers for the operand before we can make this test. */
1452 while (*p == '%' || *p == '=' || *p == '+' || *p == '&')
1455 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
1457 /* Copy class and whether memory is allowed from the matching
1458 alternative. Then perform any needed cost computations
1459 and/or adjustments. */
1461 classes[i] = classes[j];
1462 allows_mem[i] = allows_mem[j];
1464 if (!REG_P (op) || REGNO (op) < FIRST_PSEUDO_REGISTER)
1466 /* If this matches the other operand, we have no added
1468 if (rtx_equal_p (ops[j], op))
1471 /* If we can put the other operand into a register, add to
1472 the cost of this alternative the cost to copy this
1473 operand to the register used for the other operand. */
1475 else if (classes[j] != NO_REGS)
1477 alt_cost += copy_cost (op, mode, classes[j], 1, NULL);
1481 else if (!REG_P (ops[j])
1482 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
1484 /* This op is a pseudo but the one it matches is not. */
1486 /* If we can't put the other operand into a register, this
1487 alternative can't be used. */
1489 if (classes[j] == NO_REGS)
1492 /* Otherwise, add to the cost of this alternative the cost
1493 to copy the other operand to the register used for this
1497 alt_cost += copy_cost (ops[j], mode, classes[j], 1, NULL);
1501 /* The costs of this operand are not the same as the other
1502 operand since move costs are not symmetric. Moreover,
1503 if we cannot tie them, this alternative needs to do a
1504 copy, which is one instruction. */
1506 struct costs *pp = &this_op_costs[i];
1507 move_table *intable = NULL;
1508 move_table *outtable = NULL;
1509 int op_class = (int) classes[i];
1511 if (!move_cost[mode])
1512 init_move_cost (mode);
1513 intable = may_move_in_cost[mode];
1514 outtable = may_move_out_cost[mode];
1516 /* The loop is performance critical, so unswitch it manually.
1518 switch (recog_data.operand_type[i])
1521 for (class = 0; class < N_REG_CLASSES; class++)
1522 pp->cost[class] = (intable[class][op_class]
1523 + outtable[op_class][class]);
1526 for (class = 0; class < N_REG_CLASSES; class++)
1527 pp->cost[class] = intable[class][op_class];
1530 for (class = 0; class < N_REG_CLASSES; class++)
1531 pp->cost[class] = outtable[op_class][class];
1535 /* If the alternative actually allows memory, make things
1536 a bit cheaper since we won't need an extra insn to
1540 = ((recog_data.operand_type[i] != OP_IN
1541 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1543 + (recog_data.operand_type[i] != OP_OUT
1544 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1545 : 0) - allows_mem[i]);
1547 /* If we have assigned a class to this register in our
1548 first pass, add a cost to this alternative corresponding
1549 to what we would add if this register were not in the
1550 appropriate class. */
1552 if (reg_pref && reg_pref[REGNO (op)].prefclass != NO_REGS)
1554 += (may_move_in_cost[mode]
1555 [(unsigned char) reg_pref[REGNO (op)].prefclass]
1556 [(int) classes[i]]);
1558 if (REGNO (ops[i]) != REGNO (ops[j])
1559 && ! find_reg_note (insn, REG_DEAD, op))
1562 /* This is in place of ordinary cost computation
1563 for this operand, so skip to the end of the
1564 alternative (should be just one character). */
1565 while (*p && *p++ != ',')
1573 /* Scan all the constraint letters. See if the operand matches
1574 any of the constraints. Collect the valid register classes
1575 and see if this operand accepts memory. */
1584 /* Ignore the next letter for this pass. */
1590 case '!': case '#': case '&':
1591 case '0': case '1': case '2': case '3': case '4':
1592 case '5': case '6': case '7': case '8': case '9':
1597 win = address_operand (op, GET_MODE (op));
1598 /* We know this operand is an address, so we want it to be
1599 allocated to a register that can be the base of an
1600 address, i.e. BASE_REG_CLASS. */
1602 = reg_class_subunion[(int) classes[i]]
1603 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1606 case 'm': case 'o': case 'V':
1607 /* It doesn't seem worth distinguishing between offsettable
1608 and non-offsettable addresses here. */
1616 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1617 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1623 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1624 || GET_CODE (XEXP (op, 0)) == POST_INC))
1630 if (GET_CODE (op) == CONST_DOUBLE
1631 || (GET_CODE (op) == CONST_VECTOR
1632 && (GET_MODE_CLASS (GET_MODE (op))
1633 == MODE_VECTOR_FLOAT)))
1639 if (GET_CODE (op) == CONST_DOUBLE
1640 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, c, p))
1645 if (GET_CODE (op) == CONST_INT
1646 || (GET_CODE (op) == CONST_DOUBLE
1647 && GET_MODE (op) == VOIDmode))
1651 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)))
1656 if (GET_CODE (op) == CONST_INT
1657 || (GET_CODE (op) == CONST_DOUBLE
1658 && GET_MODE (op) == VOIDmode))
1670 if (GET_CODE (op) == CONST_INT
1671 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), c, p))
1682 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))))
1687 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1691 if (REG_CLASS_FROM_CONSTRAINT (c, p) != NO_REGS)
1693 = reg_class_subunion[(int) classes[i]]
1694 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1695 #ifdef EXTRA_CONSTRAINT_STR
1696 else if (EXTRA_CONSTRAINT_STR (op, c, p))
1699 if (EXTRA_MEMORY_CONSTRAINT (c, p))
1701 /* Every MEM can be reloaded to fit. */
1706 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1708 /* Every address can be reloaded to fit. */
1710 if (address_operand (op, GET_MODE (op)))
1712 /* We know this operand is an address, so we want it to
1713 be allocated to a register that can be the base of an
1714 address, i.e. BASE_REG_CLASS. */
1716 = reg_class_subunion[(int) classes[i]]
1717 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1722 p += CONSTRAINT_LEN (c, p);
1729 /* How we account for this operand now depends on whether it is a
1730 pseudo register or not. If it is, we first check if any
1731 register classes are valid. If not, we ignore this alternative,
1732 since we want to assume that all pseudos get allocated for
1733 register preferencing. If some register class is valid, compute
1734 the costs of moving the pseudo into that class. */
1736 if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1738 if (classes[i] == NO_REGS)
1740 /* We must always fail if the operand is a REG, but
1741 we did not find a suitable class.
1743 Otherwise we may perform an uninitialized read
1744 from this_op_costs after the `continue' statement
1750 struct costs *pp = &this_op_costs[i];
1751 move_table *intable = NULL;
1752 move_table *outtable = NULL;
1753 int op_class = (int) classes[i];
1755 if (!move_cost[mode])
1756 init_move_cost (mode);
1757 intable = may_move_in_cost[mode];
1758 outtable = may_move_out_cost[mode];
1760 /* The loop is performance critical, so unswitch it manually.
1762 switch (recog_data.operand_type[i])
1765 for (class = 0; class < N_REG_CLASSES; class++)
1766 pp->cost[class] = (intable[class][op_class]
1767 + outtable[op_class][class]);
1770 for (class = 0; class < N_REG_CLASSES; class++)
1771 pp->cost[class] = intable[class][op_class];
1774 for (class = 0; class < N_REG_CLASSES; class++)
1775 pp->cost[class] = outtable[op_class][class];
1779 /* If the alternative actually allows memory, make things
1780 a bit cheaper since we won't need an extra insn to
1784 = ((recog_data.operand_type[i] != OP_IN
1785 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1787 + (recog_data.operand_type[i] != OP_OUT
1788 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1789 : 0) - allows_mem[i]);
1791 /* If we have assigned a class to this register in our
1792 first pass, add a cost to this alternative corresponding
1793 to what we would add if this register were not in the
1794 appropriate class. */
1796 if (reg_pref && reg_pref[REGNO (op)].prefclass != NO_REGS)
1798 += (may_move_in_cost[mode]
1799 [(unsigned char) reg_pref[REGNO (op)].prefclass]
1800 [(int) classes[i]]);
1804 /* Otherwise, if this alternative wins, either because we
1805 have already determined that or if we have a hard register of
1806 the proper class, there is no cost for this alternative. */
1810 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op))))
1813 /* If registers are valid, the cost of this alternative includes
1814 copying the object to and/or from a register. */
1816 else if (classes[i] != NO_REGS)
1818 if (recog_data.operand_type[i] != OP_OUT)
1819 alt_cost += copy_cost (op, mode, classes[i], 1, NULL);
1821 if (recog_data.operand_type[i] != OP_IN)
1822 alt_cost += copy_cost (op, mode, classes[i], 0, NULL);
1825 /* The only other way this alternative can be used is if this is a
1826 constant that could be placed into memory. */
1828 else if (CONSTANT_P (op) && (allows_addr || allows_mem[i]))
1829 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1);
1837 /* Finally, update the costs with the information we've calculated
1838 about this alternative. */
1840 for (i = 0; i < n_ops; i++)
1842 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1844 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1845 int scale = 1 + (recog_data.operand_type[i] == OP_INOUT);
1847 pp->mem_cost = MIN (pp->mem_cost,
1848 (qq->mem_cost + alt_cost) * scale);
1850 for (class = 0; class < N_REG_CLASSES; class++)
1851 pp->cost[class] = MIN (pp->cost[class],
1852 (qq->cost[class] + alt_cost) * scale);
1856 /* If this insn is a single set copying operand 1 to operand 0
1857 and one operand is a pseudo with the other a hard reg or a pseudo
1858 that prefers a register that is in its own register class then
1859 we may want to adjust the cost of that register class to -1.
1861 Avoid the adjustment if the source does not die to avoid stressing of
1862 register allocator by preferrencing two colliding registers into single
1865 Also avoid the adjustment if a copy between registers of the class
1866 is expensive (ten times the cost of a default copy is considered
1867 arbitrarily expensive). This avoids losing when the preferred class
1868 is very expensive as the source of a copy instruction. */
1870 if ((set = single_set (insn)) != 0
1871 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set)
1872 && REG_P (ops[0]) && REG_P (ops[1])
1873 && find_regno_note (insn, REG_DEAD, REGNO (ops[1])))
1874 for (i = 0; i <= 1; i++)
1875 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1877 unsigned int regno = REGNO (ops[!i]);
1878 enum machine_mode mode = GET_MODE (ops[!i]);
1881 if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0
1882 && reg_pref[regno].prefclass != NO_REGS)
1884 enum reg_class pref = reg_pref[regno].prefclass;
1886 if ((reg_class_size[(unsigned char) pref]
1887 == (unsigned) CLASS_MAX_NREGS (pref, mode))
1888 && REGISTER_MOVE_COST (mode, pref, pref) < 10 * 2)
1889 op_costs[i].cost[(unsigned char) pref] = -1;
1891 else if (regno < FIRST_PSEUDO_REGISTER)
1892 for (class = 0; class < N_REG_CLASSES; class++)
1893 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1894 && reg_class_size[class] == (unsigned) CLASS_MAX_NREGS (class, mode))
1896 if (reg_class_size[class] == 1)
1897 op_costs[i].cost[class] = -1;
1898 else if (in_hard_reg_set_p (reg_class_contents[class],
1900 op_costs[i].cost[class] = -1;
1905 /* Compute the cost of loading X into (if TO_P is nonzero) or from (if
1906 TO_P is zero) a register of class CLASS in mode MODE.
1908 X must not be a pseudo. */
1911 copy_cost (rtx x, enum machine_mode mode, enum reg_class class, int to_p,
1912 secondary_reload_info *prev_sri)
1914 enum reg_class secondary_class = NO_REGS;
1915 secondary_reload_info sri;
1917 /* If X is a SCRATCH, there is actually nothing to move since we are
1918 assuming optimal allocation. */
1920 if (GET_CODE (x) == SCRATCH)
1923 /* Get the class we will actually use for a reload. */
1924 class = PREFERRED_RELOAD_CLASS (x, class);
1926 /* If we need a secondary reload for an intermediate, the
1927 cost is that to load the input into the intermediate register, then
1930 sri.prev_sri = prev_sri;
1932 secondary_class = targetm.secondary_reload (to_p, x, class, mode, &sri);
1934 if (!move_cost[mode])
1935 init_move_cost (mode);
1937 if (secondary_class != NO_REGS)
1938 return (move_cost[mode][(int) secondary_class][(int) class]
1940 + copy_cost (x, mode, secondary_class, to_p, &sri));
1942 /* For memory, use the memory move cost, for (hard) registers, use the
1943 cost to move between the register classes, and use 2 for everything
1944 else (constants). */
1946 if (MEM_P (x) || class == NO_REGS)
1947 return sri.extra_cost + MEMORY_MOVE_COST (mode, class, to_p);
1950 return (sri.extra_cost
1951 + move_cost[mode][(int) REGNO_REG_CLASS (REGNO (x))][(int) class]);
1954 /* If this is a constant, we may eventually want to call rtx_cost here. */
1955 return sri.extra_cost + COSTS_N_INSNS (1);
1958 /* Record the pseudo registers we must reload into hard registers
1959 in a subexpression of a memory address, X.
1961 If CONTEXT is 0, we are looking at the base part of an address, otherwise we
1962 are looking at the index part.
1964 MODE is the mode of the memory reference; OUTER_CODE and INDEX_CODE
1965 give the context that the rtx appears in. These three arguments are
1966 passed down to base_reg_class.
1968 SCALE is twice the amount to multiply the cost by (it is twice so we
1969 can represent half-cost adjustments). */
1972 record_address_regs (enum machine_mode mode, rtx x, int context,
1973 enum rtx_code outer_code, enum rtx_code index_code,
1976 enum rtx_code code = GET_CODE (x);
1977 enum reg_class class;
1980 class = INDEX_REG_CLASS;
1982 class = base_reg_class (mode, outer_code, index_code);
1995 /* When we have an address that is a sum,
1996 we must determine whether registers are "base" or "index" regs.
1997 If there is a sum of two registers, we must choose one to be
1998 the "base". Luckily, we can use the REG_POINTER to make a good
1999 choice most of the time. We only need to do this on machines
2000 that can have two registers in an address and where the base
2001 and index register classes are different.
2003 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
2004 that seems bogus since it should only be set when we are sure
2005 the register is being used as a pointer. */
2008 rtx arg0 = XEXP (x, 0);
2009 rtx arg1 = XEXP (x, 1);
2010 enum rtx_code code0 = GET_CODE (arg0);
2011 enum rtx_code code1 = GET_CODE (arg1);
2013 /* Look inside subregs. */
2014 if (code0 == SUBREG)
2015 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
2016 if (code1 == SUBREG)
2017 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
2019 /* If this machine only allows one register per address, it must
2020 be in the first operand. */
2022 if (MAX_REGS_PER_ADDRESS == 1)
2023 record_address_regs (mode, arg0, 0, PLUS, code1, scale);
2025 /* If index and base registers are the same on this machine, just
2026 record registers in any non-constant operands. We assume here,
2027 as well as in the tests below, that all addresses are in
2030 else if (INDEX_REG_CLASS == base_reg_class (VOIDmode, PLUS, SCRATCH))
2032 record_address_regs (mode, arg0, context, PLUS, code1, scale);
2033 if (! CONSTANT_P (arg1))
2034 record_address_regs (mode, arg1, context, PLUS, code0, scale);
2037 /* If the second operand is a constant integer, it doesn't change
2038 what class the first operand must be. */
2040 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
2041 record_address_regs (mode, arg0, context, PLUS, code1, scale);
2043 /* If the second operand is a symbolic constant, the first operand
2044 must be an index register. */
2046 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
2047 record_address_regs (mode, arg0, 1, PLUS, code1, scale);
2049 /* If both operands are registers but one is already a hard register
2050 of index or reg-base class, give the other the class that the
2051 hard register is not. */
2053 else if (code0 == REG && code1 == REG
2054 && REGNO (arg0) < FIRST_PSEUDO_REGISTER
2055 && (ok_for_base_p_nonstrict (arg0, mode, PLUS, REG)
2056 || ok_for_index_p_nonstrict (arg0)))
2057 record_address_regs (mode, arg1,
2058 ok_for_base_p_nonstrict (arg0, mode, PLUS, REG)
2061 else if (code0 == REG && code1 == REG
2062 && REGNO (arg1) < FIRST_PSEUDO_REGISTER
2063 && (ok_for_base_p_nonstrict (arg1, mode, PLUS, REG)
2064 || ok_for_index_p_nonstrict (arg1)))
2065 record_address_regs (mode, arg0,
2066 ok_for_base_p_nonstrict (arg1, mode, PLUS, REG)
2070 /* If one operand is known to be a pointer, it must be the base
2071 with the other operand the index. Likewise if the other operand
2074 else if ((code0 == REG && REG_POINTER (arg0))
2077 record_address_regs (mode, arg0, 0, PLUS, code1, scale);
2078 record_address_regs (mode, arg1, 1, PLUS, code0, scale);
2080 else if ((code1 == REG && REG_POINTER (arg1))
2083 record_address_regs (mode, arg0, 1, PLUS, code1, scale);
2084 record_address_regs (mode, arg1, 0, PLUS, code0, scale);
2087 /* Otherwise, count equal chances that each might be a base
2088 or index register. This case should be rare. */
2092 record_address_regs (mode, arg0, 0, PLUS, code1, scale / 2);
2093 record_address_regs (mode, arg0, 1, PLUS, code1, scale / 2);
2094 record_address_regs (mode, arg1, 0, PLUS, code0, scale / 2);
2095 record_address_regs (mode, arg1, 1, PLUS, code0, scale / 2);
2100 /* Double the importance of a pseudo register that is incremented
2101 or decremented, since it would take two extra insns
2102 if it ends up in the wrong place. */
2105 record_address_regs (mode, XEXP (x, 0), 0, code,
2106 GET_CODE (XEXP (XEXP (x, 1), 1)), 2 * scale);
2107 if (REG_P (XEXP (XEXP (x, 1), 1)))
2108 record_address_regs (mode, XEXP (XEXP (x, 1), 1), 1, code, REG,
2116 /* Double the importance of a pseudo register that is incremented
2117 or decremented, since it would take two extra insns
2118 if it ends up in the wrong place. If the operand is a pseudo,
2119 show it is being used in an INC_DEC context. */
2121 #ifdef FORBIDDEN_INC_DEC_CLASSES
2122 if (REG_P (XEXP (x, 0))
2123 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
2124 in_inc_dec[REGNO (XEXP (x, 0))] = 1;
2127 record_address_regs (mode, XEXP (x, 0), 0, code, SCRATCH, 2 * scale);
2132 struct costs *pp = &costs[REGNO (x)];
2135 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2;
2137 if (!move_cost[Pmode])
2138 init_move_cost (Pmode);
2139 for (i = 0; i < N_REG_CLASSES; i++)
2140 pp->cost[i] += (may_move_in_cost[Pmode][i][(int) class] * scale) / 2;
2146 const char *fmt = GET_RTX_FORMAT (code);
2148 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2150 record_address_regs (mode, XEXP (x, i), context, code, SCRATCH,
2156 #ifdef FORBIDDEN_INC_DEC_CLASSES
2158 /* Return 1 if REG is valid as an auto-increment memory reference
2159 to an object of MODE. */
2162 auto_inc_dec_reg_p (rtx reg, enum machine_mode mode)
2164 if (HAVE_POST_INCREMENT
2165 && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg)))
2168 if (HAVE_POST_DECREMENT
2169 && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg)))
2172 if (HAVE_PRE_INCREMENT
2173 && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg)))
2176 if (HAVE_PRE_DECREMENT
2177 && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg)))
2184 /* Free up the space allocated by allocate_reg_info. */
2186 free_reg_info (void)
2196 free (reg_renumber);
2197 reg_renumber = NULL;
2202 /* This is the `regscan' pass of the compiler, run just before cse and
2203 again just before loop. It finds the first and last use of each
2207 reg_scan (rtx f, unsigned int nregs ATTRIBUTE_UNUSED)
2211 timevar_push (TV_REG_SCAN);
2213 for (insn = f; insn; insn = NEXT_INSN (insn))
2216 reg_scan_mark_refs (PATTERN (insn), insn);
2217 if (REG_NOTES (insn))
2218 reg_scan_mark_refs (REG_NOTES (insn), insn);
2221 timevar_pop (TV_REG_SCAN);
2225 /* X is the expression to scan. INSN is the insn it appears in.
2226 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2227 We should only record information for REGs with numbers
2228 greater than or equal to MIN_REGNO. */
2230 extern struct tree_opt_pass *current_pass;
2233 reg_scan_mark_refs (rtx x, rtx insn)
2241 code = GET_CODE (x);
2260 reg_scan_mark_refs (XEXP (x, 0), insn);
2262 reg_scan_mark_refs (XEXP (x, 1), insn);
2267 reg_scan_mark_refs (XEXP (x, 1), insn);
2271 if (MEM_P (XEXP (x, 0)))
2272 reg_scan_mark_refs (XEXP (XEXP (x, 0), 0), insn);
2276 /* Count a set of the destination if it is a register. */
2277 for (dest = SET_DEST (x);
2278 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
2279 || GET_CODE (dest) == ZERO_EXTEND;
2280 dest = XEXP (dest, 0))
2283 /* If this is setting a pseudo from another pseudo or the sum of a
2284 pseudo and a constant integer and the other pseudo is known to be
2285 a pointer, set the destination to be a pointer as well.
2287 Likewise if it is setting the destination from an address or from a
2288 value equivalent to an address or to the sum of an address and
2291 But don't do any of this if the pseudo corresponds to a user
2292 variable since it should have already been set as a pointer based
2295 if (REG_P (SET_DEST (x))
2296 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER
2297 /* If the destination pseudo is set more than once, then other
2298 sets might not be to a pointer value (consider access to a
2299 union in two threads of control in the presence of global
2300 optimizations). So only set REG_POINTER on the destination
2301 pseudo if this is the only set of that pseudo. */
2302 && DF_REG_DEF_COUNT (REGNO (SET_DEST (x))) == 1
2303 && ! REG_USERVAR_P (SET_DEST (x))
2304 && ! REG_POINTER (SET_DEST (x))
2305 && ((REG_P (SET_SRC (x))
2306 && REG_POINTER (SET_SRC (x)))
2307 || ((GET_CODE (SET_SRC (x)) == PLUS
2308 || GET_CODE (SET_SRC (x)) == LO_SUM)
2309 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2310 && REG_P (XEXP (SET_SRC (x), 0))
2311 && REG_POINTER (XEXP (SET_SRC (x), 0)))
2312 || GET_CODE (SET_SRC (x)) == CONST
2313 || GET_CODE (SET_SRC (x)) == SYMBOL_REF
2314 || GET_CODE (SET_SRC (x)) == LABEL_REF
2315 || (GET_CODE (SET_SRC (x)) == HIGH
2316 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
2317 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
2318 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
2319 || ((GET_CODE (SET_SRC (x)) == PLUS
2320 || GET_CODE (SET_SRC (x)) == LO_SUM)
2321 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
2322 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
2323 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
2324 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
2325 && (GET_CODE (XEXP (note, 0)) == CONST
2326 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
2327 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
2328 REG_POINTER (SET_DEST (x)) = 1;
2330 /* If this is setting a register from a register or from a simple
2331 conversion of a register, propagate REG_EXPR. */
2332 if (REG_P (dest) && !REG_ATTRS (dest))
2334 rtx src = SET_SRC (x);
2336 while (GET_CODE (src) == SIGN_EXTEND
2337 || GET_CODE (src) == ZERO_EXTEND
2338 || GET_CODE (src) == TRUNCATE
2339 || (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)))
2340 src = XEXP (src, 0);
2343 REG_ATTRS (dest) = REG_ATTRS (src);
2345 set_reg_attrs_from_mem (dest, src);
2348 /* ... fall through ... */
2352 const char *fmt = GET_RTX_FORMAT (code);
2354 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2357 reg_scan_mark_refs (XEXP (x, i), insn);
2358 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
2361 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2362 reg_scan_mark_refs (XVECEXP (x, i, j), insn);
2369 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2373 reg_class_subset_p (enum reg_class c1, enum reg_class c2)
2377 || hard_reg_set_subset_p (reg_class_contents[(int) c1],
2378 reg_class_contents[(int) c2]));
2381 /* Return nonzero if there is a register that is in both C1 and C2. */
2384 reg_classes_intersect_p (enum reg_class c1, enum reg_class c2)
2389 || hard_reg_set_intersect_p (reg_class_contents[(int) c1],
2390 reg_class_contents[(int) c2]));
2393 #ifdef CANNOT_CHANGE_MODE_CLASS
2395 struct subregs_of_mode_node
2398 unsigned char modes[MAX_MACHINE_MODE];
2401 static htab_t subregs_of_mode;
2404 som_hash (const void *x)
2406 const struct subregs_of_mode_node *a = x;
2411 som_eq (const void *x, const void *y)
2413 const struct subregs_of_mode_node *a = x;
2414 const struct subregs_of_mode_node *b = y;
2415 return a->block == b->block;
2420 record_subregs_of_mode (rtx subreg)
2422 struct subregs_of_mode_node dummy, *node;
2423 enum machine_mode mode;
2427 if (!REG_P (SUBREG_REG (subreg)))
2430 regno = REGNO (SUBREG_REG (subreg));
2431 mode = GET_MODE (subreg);
2433 if (regno < FIRST_PSEUDO_REGISTER)
2436 dummy.block = regno & -8;
2437 slot = htab_find_slot_with_hash (subregs_of_mode, &dummy,
2438 dummy.block, INSERT);
2442 node = XCNEW (struct subregs_of_mode_node);
2443 node->block = regno & -8;
2447 node->modes[mode] |= 1 << (regno & 7);
2451 /* Call record_subregs_of_mode for all the subregs in X. */
2454 find_subregs_of_mode (rtx x)
2456 enum rtx_code code = GET_CODE (x);
2457 const char * const fmt = GET_RTX_FORMAT (code);
2461 record_subregs_of_mode (x);
2463 /* Time for some deep diving. */
2464 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2467 find_subregs_of_mode (XEXP (x, i));
2468 else if (fmt[i] == 'E')
2471 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2472 find_subregs_of_mode (XVECEXP (x, i, j));
2478 init_subregs_of_mode (void)
2483 if (subregs_of_mode)
2484 htab_empty (subregs_of_mode);
2486 subregs_of_mode = htab_create (100, som_hash, som_eq, free);
2489 FOR_BB_INSNS (bb, insn)
2491 find_subregs_of_mode (PATTERN (insn));
2497 /* Set bits in *USED which correspond to registers which can't change
2498 their mode from FROM to any mode in which REGNO was encountered. */
2501 cannot_change_mode_set_regs (HARD_REG_SET *used, enum machine_mode from,
2504 struct subregs_of_mode_node dummy, *node;
2505 enum machine_mode to;
2509 gcc_assert (subregs_of_mode);
2510 dummy.block = regno & -8;
2511 node = htab_find_with_hash (subregs_of_mode, &dummy, dummy.block);
2515 mask = 1 << (regno & 7);
2516 for (to = VOIDmode; to < NUM_MACHINE_MODES; to++)
2517 if (node->modes[to] & mask)
2518 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2519 if (!TEST_HARD_REG_BIT (*used, i)
2520 && REG_CANNOT_CHANGE_MODE_P (i, from, to))
2521 SET_HARD_REG_BIT (*used, i);
2524 /* Return 1 if REGNO has had an invalid mode change in CLASS from FROM
2528 invalid_mode_change_p (unsigned int regno,
2529 enum reg_class class ATTRIBUTE_UNUSED,
2530 enum machine_mode from)
2532 struct subregs_of_mode_node dummy, *node;
2533 enum machine_mode to;
2536 gcc_assert (subregs_of_mode);
2537 dummy.block = regno & -8;
2538 node = htab_find_with_hash (subregs_of_mode, &dummy, dummy.block);
2542 mask = 1 << (regno & 7);
2543 for (to = VOIDmode; to < NUM_MACHINE_MODES; to++)
2544 if (node->modes[to] & mask)
2545 if (CANNOT_CHANGE_MODE_CLASS (from, to, class))
2552 finish_subregs_of_mode (void)
2554 htab_delete (subregs_of_mode);
2555 subregs_of_mode = 0;
2560 init_subregs_of_mode (void)
2565 finish_subregs_of_mode (void)
2570 #endif /* CANNOT_CHANGE_MODE_CLASS */
2573 gate_subregs_of_mode_init (void)
2575 #ifdef CANNOT_CHANGE_MODE_CLASS
2582 struct tree_opt_pass pass_subregs_of_mode_init =
2584 "subregs_of_mode_init", /* name */
2585 gate_subregs_of_mode_init, /* gate */
2586 init_subregs_of_mode, /* execute */
2589 0, /* static_pass_number */
2591 0, /* properties_required */
2592 0, /* properties_provided */
2593 0, /* properties_destroyed */
2594 0, /* todo_flags_start */
2595 0, /* todo_flags_finish */
2599 struct tree_opt_pass pass_subregs_of_mode_finish =
2601 "subregs_of_mode_finish", /* name */
2602 gate_subregs_of_mode_init, /* gate */
2603 finish_subregs_of_mode, /* execute */
2606 0, /* static_pass_number */
2608 0, /* properties_required */
2609 0, /* properties_provided */
2610 0, /* properties_destroyed */
2611 0, /* todo_flags_start */
2612 0, /* todo_flags_finish */
2618 #include "gt-regclass.h"