1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996
3 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 /* This file contains two passes of the compiler: reg_scan and reg_class.
24 It also defines some tables of information about the hardware registers
25 and a function init_reg_sets to initialize the tables. */
29 #include "hard-reg-set.h"
34 #include "basic-block.h"
37 #include "insn-config.h"
45 #ifndef REGISTER_MOVE_COST
46 #define REGISTER_MOVE_COST(m, x, y) 2
49 static void init_reg_sets_1 PARAMS ((void));
50 static void init_reg_modes PARAMS ((void));
52 /* If we have auto-increment or auto-decrement and we can have secondary
53 reloads, we are not allowed to use classes requiring secondary
54 reloads for pseudos auto-incremented since reload can't handle it. */
57 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
58 #define FORBIDDEN_INC_DEC_CLASSES
62 /* Register tables used by many passes. */
64 /* Indexed by hard register number, contains 1 for registers
65 that are fixed use (stack pointer, pc, frame pointer, etc.).
66 These are the registers that cannot be used to allocate
67 a pseudo reg for general use. */
69 char fixed_regs[FIRST_PSEUDO_REGISTER];
71 /* Same info as a HARD_REG_SET. */
73 HARD_REG_SET fixed_reg_set;
75 /* Data for initializing the above. */
77 static const char initial_fixed_regs[] = FIXED_REGISTERS;
79 /* Indexed by hard register number, contains 1 for registers
80 that are fixed use or are clobbered by function calls.
81 These are the registers that cannot be used to allocate
82 a pseudo reg whose life crosses calls unless we are able
83 to save/restore them across the calls. */
85 char call_used_regs[FIRST_PSEUDO_REGISTER];
87 /* Same info as a HARD_REG_SET. */
89 HARD_REG_SET call_used_reg_set;
91 /* HARD_REG_SET of registers we want to avoid caller saving. */
92 HARD_REG_SET losing_caller_save_reg_set;
94 /* Data for initializing the above. */
96 static const char initial_call_used_regs[] = CALL_USED_REGISTERS;
98 /* This is much like call_used_regs, except it doesn't have to
99 be a superset of FIXED_REGISTERS. This vector indicates
100 what is really call clobbered, and is used when defining
101 regs_invalidated_by_call. */
103 #ifdef CALL_REALLY_USED_REGISTERS
104 char call_really_used_regs[] = CALL_REALLY_USED_REGISTERS;
107 /* Indexed by hard register number, contains 1 for registers that are
108 fixed use or call used registers that cannot hold quantities across
109 calls even if we are willing to save and restore them. call fixed
110 registers are a subset of call used registers. */
112 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
114 /* The same info as a HARD_REG_SET. */
116 HARD_REG_SET call_fixed_reg_set;
118 /* Number of non-fixed registers. */
120 int n_non_fixed_regs;
122 /* Indexed by hard register number, contains 1 for registers
123 that are being used for global register decls.
124 These must be exempt from ordinary flow analysis
125 and are also considered fixed. */
127 char global_regs[FIRST_PSEUDO_REGISTER];
129 /* Contains 1 for registers that are set or clobbered by calls. */
130 /* ??? Ideally, this would be just call_used_regs plus global_regs, but
131 for someone's bright idea to have call_used_regs strictly include
132 fixed_regs. Which leaves us guessing as to the set of fixed_regs
133 that are actually preserved. We know for sure that those associated
134 with the local stack frame are safe, but scant others. */
136 HARD_REG_SET regs_invalidated_by_call;
138 /* Table of register numbers in the order in which to try to use them. */
139 #ifdef REG_ALLOC_ORDER
140 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
142 /* The inverse of reg_alloc_order. */
143 int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER];
146 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
148 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
150 /* The same information, but as an array of unsigned ints. We copy from
151 these unsigned ints to the table above. We do this so the tm.h files
152 do not have to be aware of the wordsize for machines with <= 64 regs.
153 Note that we hard-code 32 here, not HOST_BITS_PER_INT. */
156 ((FIRST_PSEUDO_REGISTER + (32 - 1)) / 32)
158 static const unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
159 = REG_CLASS_CONTENTS;
161 /* For each reg class, number of regs it contains. */
163 unsigned int reg_class_size[N_REG_CLASSES];
165 /* For each reg class, table listing all the containing classes. */
167 enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
169 /* For each reg class, table listing all the classes contained in it. */
171 enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
173 /* For each pair of reg classes,
174 a largest reg class contained in their union. */
176 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
178 /* For each pair of reg classes,
179 the smallest reg class containing their union. */
181 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
183 /* Array containing all of the register names. Unless
184 DEBUG_REGISTER_NAMES is defined, use the copy in print-rtl.c. */
186 #ifdef DEBUG_REGISTER_NAMES
187 const char * reg_names[] = REGISTER_NAMES;
190 /* For each hard register, the widest mode object that it can contain.
191 This will be a MODE_INT mode if the register can hold integers. Otherwise
192 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
195 enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER];
197 /* 1 if class does contain register of given mode. */
199 static char contains_reg_of_mode [N_REG_CLASSES] [MAX_MACHINE_MODE];
201 /* Maximum cost of moving from a register in one class to a register in
202 another class. Based on REGISTER_MOVE_COST. */
204 static int move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES];
206 /* Similar, but here we don't have to move if the first index is a subset
207 of the second so in that case the cost is zero. */
209 static int may_move_in_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES];
211 /* Similar, but here we don't have to move if the first index is a superset
212 of the second so in that case the cost is zero. */
214 static int may_move_out_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES];
216 #ifdef FORBIDDEN_INC_DEC_CLASSES
218 /* These are the classes that regs which are auto-incremented or decremented
221 static int forbidden_inc_dec_class[N_REG_CLASSES];
223 /* Indexed by n, is nonzero if (REG n) is used in an auto-inc or auto-dec
226 static char *in_inc_dec;
228 #endif /* FORBIDDEN_INC_DEC_CLASSES */
230 #ifdef CANNOT_CHANGE_MODE_CLASS
231 /* All registers that have been subreged. Indexed by mode, where each
232 entry is a regset of registers. */
233 regset_head subregs_of_mode [NUM_MACHINE_MODES];
236 /* Sample MEM values for use by memory_move_secondary_cost. */
238 static GTY(()) rtx top_of_stack[MAX_MACHINE_MODE];
240 /* Linked list of reg_info structures allocated for reg_n_info array.
241 Grouping all of the allocated structures together in one lump
242 means only one call to bzero to clear them, rather than n smaller
244 struct reg_info_data {
245 struct reg_info_data *next; /* next set of reg_info structures */
246 size_t min_index; /* minimum index # */
247 size_t max_index; /* maximum index # */
248 char used_p; /* nonzero if this has been used previously */
249 reg_info data[1]; /* beginning of the reg_info data */
252 static struct reg_info_data *reg_info_head;
254 /* No more global register variables may be declared; true once
255 regclass has been initialized. */
257 static int no_global_reg_vars = 0;
260 /* Function called only once to initialize the above data on reg usage.
261 Once this is done, various switches may override. */
268 /* First copy the register information from the initial int form into
271 for (i = 0; i < N_REG_CLASSES; i++)
273 CLEAR_HARD_REG_SET (reg_class_contents[i]);
275 /* Note that we hard-code 32 here, not HOST_BITS_PER_INT. */
276 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
277 if (int_reg_class_contents[i][j / 32]
278 & ((unsigned) 1 << (j % 32)))
279 SET_HARD_REG_BIT (reg_class_contents[i], j);
282 memcpy (fixed_regs, initial_fixed_regs, sizeof fixed_regs);
283 memcpy (call_used_regs, initial_call_used_regs, sizeof call_used_regs);
284 memset (global_regs, 0, sizeof global_regs);
286 /* Do any additional initialization regsets may need. */
287 INIT_ONCE_REG_SET ();
289 #ifdef REG_ALLOC_ORDER
290 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
291 inv_reg_alloc_order[reg_alloc_order[i]] = i;
295 /* After switches have been processed, which perhaps alter
296 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
302 unsigned int /* enum machine_mode */ m;
303 char allocatable_regs_of_mode [MAX_MACHINE_MODE];
305 /* This macro allows the fixed or call-used registers
306 and the register classes to depend on target flags. */
308 #ifdef CONDITIONAL_REGISTER_USAGE
309 CONDITIONAL_REGISTER_USAGE;
312 /* Compute number of hard regs in each class. */
314 memset ((char *) reg_class_size, 0, sizeof reg_class_size);
315 for (i = 0; i < N_REG_CLASSES; i++)
316 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
317 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
320 /* Initialize the table of subunions.
321 reg_class_subunion[I][J] gets the largest-numbered reg-class
322 that is contained in the union of classes I and J. */
324 for (i = 0; i < N_REG_CLASSES; i++)
326 for (j = 0; j < N_REG_CLASSES; j++)
329 register /* Declare it register if it's a scalar. */
334 COPY_HARD_REG_SET (c, reg_class_contents[i]);
335 IOR_HARD_REG_SET (c, reg_class_contents[j]);
336 for (k = 0; k < N_REG_CLASSES; k++)
338 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
343 /* keep the largest subclass */ /* SPEE 900308 */
344 GO_IF_HARD_REG_SUBSET (reg_class_contents[k],
345 reg_class_contents[(int) reg_class_subunion[i][j]],
347 reg_class_subunion[i][j] = (enum reg_class) k;
354 /* Initialize the table of superunions.
355 reg_class_superunion[I][J] gets the smallest-numbered reg-class
356 containing the union of classes I and J. */
358 for (i = 0; i < N_REG_CLASSES; i++)
360 for (j = 0; j < N_REG_CLASSES; j++)
363 register /* Declare it register if it's a scalar. */
368 COPY_HARD_REG_SET (c, reg_class_contents[i]);
369 IOR_HARD_REG_SET (c, reg_class_contents[j]);
370 for (k = 0; k < N_REG_CLASSES; k++)
371 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass);
374 reg_class_superunion[i][j] = (enum reg_class) k;
378 /* Initialize the tables of subclasses and superclasses of each reg class.
379 First clear the whole table, then add the elements as they are found. */
381 for (i = 0; i < N_REG_CLASSES; i++)
383 for (j = 0; j < N_REG_CLASSES; j++)
385 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
386 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
390 for (i = 0; i < N_REG_CLASSES; i++)
392 if (i == (int) NO_REGS)
395 for (j = i + 1; j < N_REG_CLASSES; j++)
399 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
403 /* Reg class I is a subclass of J.
404 Add J to the table of superclasses of I. */
405 p = ®_class_superclasses[i][0];
406 while (*p != LIM_REG_CLASSES) p++;
407 *p = (enum reg_class) j;
408 /* Add I to the table of superclasses of J. */
409 p = ®_class_subclasses[j][0];
410 while (*p != LIM_REG_CLASSES) p++;
411 *p = (enum reg_class) i;
415 /* Initialize "constant" tables. */
417 CLEAR_HARD_REG_SET (fixed_reg_set);
418 CLEAR_HARD_REG_SET (call_used_reg_set);
419 CLEAR_HARD_REG_SET (call_fixed_reg_set);
420 CLEAR_HARD_REG_SET (regs_invalidated_by_call);
422 memcpy (call_fixed_regs, fixed_regs, sizeof call_fixed_regs);
424 n_non_fixed_regs = 0;
426 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
429 SET_HARD_REG_BIT (fixed_reg_set, i);
433 if (call_used_regs[i])
434 SET_HARD_REG_BIT (call_used_reg_set, i);
435 if (call_fixed_regs[i])
436 SET_HARD_REG_BIT (call_fixed_reg_set, i);
437 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i)))
438 SET_HARD_REG_BIT (losing_caller_save_reg_set, i);
440 /* There are a couple of fixed registers that we know are safe to
441 exclude from being clobbered by calls:
443 The frame pointer is always preserved across calls. The arg pointer
444 is if it is fixed. The stack pointer usually is, unless
445 RETURN_POPS_ARGS, in which case an explicit CLOBBER will be present.
446 If we are generating PIC code, the PIC offset table register is
447 preserved across calls, though the target can override that. */
449 if (i == STACK_POINTER_REGNUM || i == FRAME_POINTER_REGNUM)
451 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
452 else if (i == HARD_FRAME_POINTER_REGNUM)
455 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
456 else if (i == ARG_POINTER_REGNUM && fixed_regs[i])
459 #ifndef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
460 else if (i == PIC_OFFSET_TABLE_REGNUM && fixed_regs[i])
464 #ifdef CALL_REALLY_USED_REGISTERS
465 || call_really_used_regs[i]
470 SET_HARD_REG_BIT (regs_invalidated_by_call, i);
473 memset (contains_reg_of_mode, 0, sizeof (contains_reg_of_mode));
474 memset (allocatable_regs_of_mode, 0, sizeof (allocatable_regs_of_mode));
475 for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++)
476 for (i = 0; i < N_REG_CLASSES; i++)
477 if ((unsigned) CLASS_MAX_NREGS (i, m) <= reg_class_size[i])
478 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
479 if (!fixed_regs [j] && TEST_HARD_REG_BIT (reg_class_contents[i], j)
480 && HARD_REGNO_MODE_OK (j, m))
482 contains_reg_of_mode [i][m] = 1;
483 allocatable_regs_of_mode [m] = 1;
487 /* Initialize the move cost table. Find every subset of each class
488 and take the maximum cost of moving any subset to any other. */
490 for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++)
491 if (allocatable_regs_of_mode [m])
493 for (i = 0; i < N_REG_CLASSES; i++)
494 if (contains_reg_of_mode [i][m])
495 for (j = 0; j < N_REG_CLASSES; j++)
498 enum reg_class *p1, *p2;
500 if (!contains_reg_of_mode [j][m])
502 move_cost[m][i][j] = 65536;
503 may_move_in_cost[m][i][j] = 65536;
504 may_move_out_cost[m][i][j] = 65536;
508 cost = REGISTER_MOVE_COST (m, i, j);
510 for (p2 = ®_class_subclasses[j][0];
511 *p2 != LIM_REG_CLASSES;
513 if (*p2 != i && contains_reg_of_mode [*p2][m])
514 cost = MAX (cost, move_cost [m][i][*p2]);
516 for (p1 = ®_class_subclasses[i][0];
517 *p1 != LIM_REG_CLASSES;
519 if (*p1 != j && contains_reg_of_mode [*p1][m])
520 cost = MAX (cost, move_cost [m][*p1][j]);
522 move_cost[m][i][j] = cost;
524 if (reg_class_subset_p (i, j))
525 may_move_in_cost[m][i][j] = 0;
527 may_move_in_cost[m][i][j] = cost;
529 if (reg_class_subset_p (j, i))
530 may_move_out_cost[m][i][j] = 0;
532 may_move_out_cost[m][i][j] = cost;
536 for (j = 0; j < N_REG_CLASSES; j++)
538 move_cost[m][i][j] = 65536;
539 may_move_in_cost[m][i][j] = 65536;
540 may_move_out_cost[m][i][j] = 65536;
545 /* Compute the table of register modes.
546 These values are used to record death information for individual registers
547 (as opposed to a multi-register mode). */
554 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
556 reg_raw_mode[i] = choose_hard_reg_mode (i, 1);
558 /* If we couldn't find a valid mode, just use the previous mode.
559 ??? One situation in which we need to do this is on the mips where
560 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
561 to use DF mode for the even registers and VOIDmode for the odd
562 (for the cpu models where the odd ones are inaccessible). */
563 if (reg_raw_mode[i] == VOIDmode)
564 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1];
568 /* Finish initializing the register sets and
569 initialize the register modes. */
574 /* This finishes what was started by init_reg_sets, but couldn't be done
575 until after register usage was specified. */
581 /* Initialize some fake stack-frame MEM references for use in
582 memory_move_secondary_cost. */
585 init_fake_stack_mems ()
587 #ifdef HAVE_SECONDARY_RELOADS
591 for (i = 0; i < MAX_MACHINE_MODE; i++)
592 top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx);
597 #ifdef HAVE_SECONDARY_RELOADS
599 /* Compute extra cost of moving registers to/from memory due to reloads.
600 Only needed if secondary reloads are required for memory moves. */
603 memory_move_secondary_cost (mode, class, in)
604 enum machine_mode mode;
605 enum reg_class class;
608 enum reg_class altclass;
609 int partial_cost = 0;
610 /* We need a memory reference to feed to SECONDARY... macros. */
611 /* mem may be unused even if the SECONDARY_ macros are defined. */
612 rtx mem ATTRIBUTE_UNUSED = top_of_stack[(int) mode];
617 #ifdef SECONDARY_INPUT_RELOAD_CLASS
618 altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem);
625 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
626 altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem);
632 if (altclass == NO_REGS)
636 partial_cost = REGISTER_MOVE_COST (mode, altclass, class);
638 partial_cost = REGISTER_MOVE_COST (mode, class, altclass);
640 if (class == altclass)
641 /* This isn't simply a copy-to-temporary situation. Can't guess
642 what it is, so MEMORY_MOVE_COST really ought not to be calling
645 I'm tempted to put in an abort here, but returning this will
646 probably only give poor estimates, which is what we would've
647 had before this code anyways. */
650 /* Check if the secondary reload register will also need a
652 return memory_move_secondary_cost (mode, altclass, in) + partial_cost;
656 /* Return a machine mode that is legitimate for hard reg REGNO and large
657 enough to save nregs. If we can't find one, return VOIDmode. */
660 choose_hard_reg_mode (regno, nregs)
661 unsigned int regno ATTRIBUTE_UNUSED;
664 unsigned int /* enum machine_mode */ m;
665 enum machine_mode found_mode = VOIDmode, mode;
667 /* We first look for the largest integer mode that can be validly
668 held in REGNO. If none, we look for the largest floating-point mode.
669 If we still didn't find a valid mode, try CCmode. */
671 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
673 mode = GET_MODE_WIDER_MODE (mode))
674 if ((unsigned) HARD_REGNO_NREGS (regno, mode) == nregs
675 && HARD_REGNO_MODE_OK (regno, mode))
678 if (found_mode != VOIDmode)
681 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
683 mode = GET_MODE_WIDER_MODE (mode))
684 if ((unsigned) HARD_REGNO_NREGS (regno, mode) == nregs
685 && HARD_REGNO_MODE_OK (regno, mode))
688 if (found_mode != VOIDmode)
691 for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT);
693 mode = GET_MODE_WIDER_MODE (mode))
694 if ((unsigned) HARD_REGNO_NREGS (regno, mode) == nregs
695 && HARD_REGNO_MODE_OK (regno, mode))
698 if (found_mode != VOIDmode)
701 for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT);
703 mode = GET_MODE_WIDER_MODE (mode))
704 if ((unsigned) HARD_REGNO_NREGS (regno, mode) == nregs
705 && HARD_REGNO_MODE_OK (regno, mode))
708 if (found_mode != VOIDmode)
711 /* Iterate over all of the CCmodes. */
712 for (m = (unsigned int) CCmode; m < (unsigned int) NUM_MACHINE_MODES; ++m)
714 mode = (enum machine_mode) m;
715 if ((unsigned) HARD_REGNO_NREGS (regno, mode) == nregs
716 && HARD_REGNO_MODE_OK (regno, mode))
720 /* We can't find a mode valid for this register. */
724 /* Specify the usage characteristics of the register named NAME.
725 It should be a fixed register if FIXED and a
726 call-used register if CALL_USED. */
729 fix_register (name, fixed, call_used)
731 int fixed, call_used;
735 /* Decode the name and update the primary form of
736 the register info. */
738 if ((i = decode_reg_name (name)) >= 0)
740 if ((i == STACK_POINTER_REGNUM
741 #ifdef HARD_FRAME_POINTER_REGNUM
742 || i == HARD_FRAME_POINTER_REGNUM
744 || i == FRAME_POINTER_REGNUM
747 && (fixed == 0 || call_used == 0))
749 static const char * const what_option[2][2] = {
750 { "call-saved", "call-used" },
751 { "no-such-option", "fixed" }};
753 error ("can't use '%s' as a %s register", name,
754 what_option[fixed][call_used]);
758 fixed_regs[i] = fixed;
759 call_used_regs[i] = call_used;
760 #ifdef CALL_REALLY_USED_REGISTERS
762 call_really_used_regs[i] = call_used;
768 warning ("unknown register name: %s", name);
772 /* Mark register number I as global. */
778 if (fixed_regs[i] == 0 && no_global_reg_vars)
779 error ("global register variable follows a function definition");
783 warning ("register used for two global register variables");
787 if (call_used_regs[i] && ! fixed_regs[i])
788 warning ("call-clobbered register used for global register variable");
792 /* If already fixed, nothing else to do. */
796 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
799 SET_HARD_REG_BIT (fixed_reg_set, i);
800 SET_HARD_REG_BIT (call_used_reg_set, i);
801 SET_HARD_REG_BIT (call_fixed_reg_set, i);
802 SET_HARD_REG_BIT (regs_invalidated_by_call, i);
805 /* Now the data and code for the `regclass' pass, which happens
806 just before local-alloc. */
808 /* The `costs' struct records the cost of using a hard register of each class
809 and of using memory for each pseudo. We use this data to set up
810 register class preferences. */
814 int cost[N_REG_CLASSES];
818 /* Structure used to record preferrences of given pseudo. */
821 /* (enum reg_class) prefclass is the preferred class. */
824 /* altclass is a register class that we should use for allocating
825 pseudo if no register in the preferred class is available.
826 If no register in this class is available, memory is preferred.
828 It might appear to be more general to have a bitmask of classes here,
829 but since it is recommended that there be a class corresponding to the
830 union of most major pair of classes, that generality is not required. */
834 /* Record the cost of each class for each pseudo. */
836 static struct costs *costs;
838 /* Initialized once, and used to initialize cost values for each insn. */
840 static struct costs init_cost;
842 /* Record preferrences of each pseudo.
843 This is available after `regclass' is run. */
845 static struct reg_pref *reg_pref;
847 /* Allocated buffers for reg_pref. */
849 static struct reg_pref *reg_pref_buffer;
851 /* Frequency of executions of current insn. */
853 static int frequency;
855 static rtx scan_one_insn PARAMS ((rtx, int));
856 static void record_operand_costs PARAMS ((rtx, struct costs *, struct reg_pref *));
857 static void dump_regclass PARAMS ((FILE *));
858 static void record_reg_classes PARAMS ((int, int, rtx *, enum machine_mode *,
860 struct costs *, struct reg_pref *));
861 static int copy_cost PARAMS ((rtx, enum machine_mode,
862 enum reg_class, int));
863 static void record_address_regs PARAMS ((rtx, enum reg_class, int));
864 #ifdef FORBIDDEN_INC_DEC_CLASSES
865 static int auto_inc_dec_reg_p PARAMS ((rtx, enum machine_mode));
867 static void reg_scan_mark_refs PARAMS ((rtx, rtx, int, unsigned int));
869 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
870 This function is sometimes called before the info has been computed.
871 When that happens, just return GENERAL_REGS, which is innocuous. */
874 reg_preferred_class (regno)
879 return (enum reg_class) reg_pref[regno].prefclass;
883 reg_alternate_class (regno)
889 return (enum reg_class) reg_pref[regno].altclass;
892 /* Initialize some global data for this pass. */
899 init_cost.mem_cost = 10000;
900 for (i = 0; i < N_REG_CLASSES; i++)
901 init_cost.cost[i] = 10000;
903 /* This prevents dump_flow_info from losing if called
904 before regclass is run. */
907 /* No more global register variables may be declared. */
908 no_global_reg_vars = 1;
911 /* Dump register costs. */
916 static const char *const reg_class_names[] = REG_CLASS_NAMES;
918 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
920 int /* enum reg_class */ class;
923 fprintf (dump, " Register %i costs:", i);
924 for (class = 0; class < (int) N_REG_CLASSES; class++)
925 if (contains_reg_of_mode [(enum reg_class) class][PSEUDO_REGNO_MODE (i)]
926 #ifdef FORBIDDEN_INC_DEC_CLASSES
928 || !forbidden_inc_dec_class[(enum reg_class) class])
930 #ifdef CANNOT_CHANGE_MODE_CLASS
931 && ! invalid_mode_change_p (i, (enum reg_class) class,
932 PSEUDO_REGNO_MODE (i))
935 fprintf (dump, " %s:%i", reg_class_names[class],
936 costs[i].cost[(enum reg_class) class]);
937 fprintf (dump, " MEM:%i\n", costs[i].mem_cost);
943 /* Calculate the costs of insn operands. */
946 record_operand_costs (insn, op_costs, reg_pref)
948 struct costs *op_costs;
949 struct reg_pref *reg_pref;
951 const char *constraints[MAX_RECOG_OPERANDS];
952 enum machine_mode modes[MAX_RECOG_OPERANDS];
955 for (i = 0; i < recog_data.n_operands; i++)
957 constraints[i] = recog_data.constraints[i];
958 modes[i] = recog_data.operand_mode[i];
961 /* If we get here, we are set up to record the costs of all the
962 operands for this insn. Start by initializing the costs.
963 Then handle any address registers. Finally record the desired
964 classes for any pseudos, doing it twice if some pair of
965 operands are commutative. */
967 for (i = 0; i < recog_data.n_operands; i++)
969 op_costs[i] = init_cost;
971 if (GET_CODE (recog_data.operand[i]) == SUBREG)
972 recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]);
974 if (GET_CODE (recog_data.operand[i]) == MEM)
975 record_address_regs (XEXP (recog_data.operand[i], 0),
976 MODE_BASE_REG_CLASS (modes[i]), frequency * 2);
977 else if (constraints[i][0] == 'p'
978 || EXTRA_ADDRESS_CONSTRAINT (constraints[i][0]))
979 record_address_regs (recog_data.operand[i],
980 MODE_BASE_REG_CLASS (modes[i]), frequency * 2);
983 /* Check for commutative in a separate loop so everything will
984 have been initialized. We must do this even if one operand
985 is a constant--see addsi3 in m68k.md. */
987 for (i = 0; i < (int) recog_data.n_operands - 1; i++)
988 if (constraints[i][0] == '%')
990 const char *xconstraints[MAX_RECOG_OPERANDS];
993 /* Handle commutative operands by swapping the constraints.
994 We assume the modes are the same. */
996 for (j = 0; j < recog_data.n_operands; j++)
997 xconstraints[j] = constraints[j];
999 xconstraints[i] = constraints[i+1];
1000 xconstraints[i+1] = constraints[i];
1001 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
1002 recog_data.operand, modes,
1003 xconstraints, insn, op_costs, reg_pref);
1006 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
1007 recog_data.operand, modes,
1008 constraints, insn, op_costs, reg_pref);
1011 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
1012 time it would save code to put a certain register in a certain class.
1013 PASS, when nonzero, inhibits some optimizations which need only be done
1015 Return the last insn processed, so that the scan can be continued from
1019 scan_one_insn (insn, pass)
1023 enum rtx_code code = GET_CODE (insn);
1024 enum rtx_code pat_code;
1027 struct costs op_costs[MAX_RECOG_OPERANDS];
1029 if (GET_RTX_CLASS (code) != 'i')
1032 pat_code = GET_CODE (PATTERN (insn));
1034 || pat_code == CLOBBER
1035 || pat_code == ASM_INPUT
1036 || pat_code == ADDR_VEC
1037 || pat_code == ADDR_DIFF_VEC)
1040 set = single_set (insn);
1041 extract_insn (insn);
1043 /* If this insn loads a parameter from its stack slot, then
1044 it represents a savings, rather than a cost, if the
1045 parameter is stored in memory. Record this fact. */
1047 if (set != 0 && GET_CODE (SET_DEST (set)) == REG
1048 && GET_CODE (SET_SRC (set)) == MEM
1049 && (note = find_reg_note (insn, REG_EQUIV,
1051 && GET_CODE (XEXP (note, 0)) == MEM)
1053 costs[REGNO (SET_DEST (set))].mem_cost
1054 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)),
1057 record_address_regs (XEXP (SET_SRC (set), 0),
1058 MODE_BASE_REG_CLASS (VOIDmode), frequency * 2);
1062 /* Improve handling of two-address insns such as
1063 (set X (ashift CONST Y)) where CONST must be made to
1064 match X. Change it into two insns: (set X CONST)
1065 (set X (ashift X Y)). If we left this for reloading, it
1066 would probably get three insns because X and Y might go
1067 in the same place. This prevents X and Y from receiving
1070 We can only do this if the modes of operands 0 and 1
1071 (which might not be the same) are tieable and we only need
1072 do this during our first pass. */
1074 if (pass == 0 && optimize
1075 && recog_data.n_operands >= 3
1076 && recog_data.constraints[1][0] == '0'
1077 && recog_data.constraints[1][1] == 0
1078 && CONSTANT_P (recog_data.operand[1])
1079 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1])
1080 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2])
1081 && GET_CODE (recog_data.operand[0]) == REG
1082 && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]),
1083 recog_data.operand_mode[1]))
1085 rtx previnsn = prev_real_insn (insn);
1087 = gen_lowpart (recog_data.operand_mode[1],
1088 recog_data.operand[0]);
1090 = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn);
1092 /* If this insn was the start of a basic block,
1093 include the new insn in that block.
1094 We need not check for code_label here;
1095 while a basic block can start with a code_label,
1096 INSN could not be at the beginning of that block. */
1097 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
1101 if (insn == b->head)
1105 /* This makes one more setting of new insns's dest. */
1106 REG_N_SETS (REGNO (recog_data.operand[0]))++;
1107 REG_N_REFS (REGNO (recog_data.operand[0]))++;
1108 REG_FREQ (REGNO (recog_data.operand[0])) += frequency;
1110 *recog_data.operand_loc[1] = recog_data.operand[0];
1111 REG_N_REFS (REGNO (recog_data.operand[0]))++;
1112 REG_FREQ (REGNO (recog_data.operand[0])) += frequency;
1113 for (i = recog_data.n_dups - 1; i >= 0; i--)
1114 if (recog_data.dup_num[i] == 1)
1116 *recog_data.dup_loc[i] = recog_data.operand[0];
1117 REG_N_REFS (REGNO (recog_data.operand[0]))++;
1118 REG_FREQ (REGNO (recog_data.operand[0])) += frequency;
1121 return PREV_INSN (newinsn);
1124 record_operand_costs (insn, op_costs, reg_pref);
1126 /* Now add the cost for each operand to the total costs for
1129 for (i = 0; i < recog_data.n_operands; i++)
1130 if (GET_CODE (recog_data.operand[i]) == REG
1131 && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER)
1133 int regno = REGNO (recog_data.operand[i]);
1134 struct costs *p = &costs[regno], *q = &op_costs[i];
1136 p->mem_cost += q->mem_cost * frequency;
1137 for (j = 0; j < N_REG_CLASSES; j++)
1138 p->cost[j] += q->cost[j] * frequency;
1144 /* This is a pass of the compiler that scans all instructions
1145 and calculates the preferred class for each pseudo-register.
1146 This information can be accessed later by calling `reg_preferred_class'.
1147 This pass comes just before local register allocation. */
1150 regclass (f, nregs, dump)
1161 costs = (struct costs *) xmalloc (nregs * sizeof (struct costs));
1163 #ifdef FORBIDDEN_INC_DEC_CLASSES
1165 in_inc_dec = (char *) xmalloc (nregs);
1167 /* Initialize information about which register classes can be used for
1168 pseudos that are auto-incremented or auto-decremented. It would
1169 seem better to put this in init_reg_sets, but we need to be able
1170 to allocate rtx, which we can't do that early. */
1172 for (i = 0; i < N_REG_CLASSES; i++)
1174 rtx r = gen_rtx_REG (VOIDmode, 0);
1175 enum machine_mode m;
1178 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
1179 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
1183 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE;
1184 m = (enum machine_mode) ((int) m + 1))
1185 if (HARD_REGNO_MODE_OK (j, m))
1189 /* If a register is not directly suitable for an
1190 auto-increment or decrement addressing mode and
1191 requires secondary reloads, disallow its class from
1192 being used in such addresses. */
1195 #ifdef SECONDARY_RELOAD_CLASS
1196 || (SECONDARY_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r)
1199 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1200 || (SECONDARY_INPUT_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r)
1203 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1204 || (SECONDARY_OUTPUT_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r)
1209 && ! auto_inc_dec_reg_p (r, m))
1210 forbidden_inc_dec_class[i] = 1;
1214 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1216 /* Normally we scan the insns once and determine the best class to use for
1217 each register. However, if -fexpensive_optimizations are on, we do so
1218 twice, the second time using the tentative best classes to guide the
1221 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
1226 fprintf (dump, "\n\nPass %i\n\n",pass);
1227 /* Zero out our accumulation of the cost of each class for each reg. */
1229 memset ((char *) costs, 0, nregs * sizeof (struct costs));
1231 #ifdef FORBIDDEN_INC_DEC_CLASSES
1232 memset (in_inc_dec, 0, nregs);
1235 /* Scan the instructions and record each time it would
1236 save code to put a certain register in a certain class. */
1240 frequency = REG_FREQ_MAX;
1241 for (insn = f; insn; insn = NEXT_INSN (insn))
1242 insn = scan_one_insn (insn, pass);
1247 /* Show that an insn inside a loop is likely to be executed three
1248 times more than insns outside a loop. This is much more
1249 aggressive than the assumptions made elsewhere and is being
1250 tried as an experiment. */
1251 frequency = REG_FREQ_FROM_BB (bb);
1252 for (insn = bb->head; ; insn = NEXT_INSN (insn))
1254 insn = scan_one_insn (insn, pass);
1255 if (insn == bb->end)
1260 /* Now for each register look at how desirable each class is
1261 and find which class is preferred. Store that in
1262 `prefclass'. Record in `altclass' the largest register
1263 class any of whose registers is better than memory. */
1266 reg_pref = reg_pref_buffer;
1270 dump_regclass (dump);
1271 fprintf (dump,"\n");
1273 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
1275 int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
1276 enum reg_class best = ALL_REGS, alt = NO_REGS;
1277 /* This is an enum reg_class, but we call it an int
1278 to save lots of casts. */
1280 struct costs *p = &costs[i];
1282 /* In non-optimizing compilation REG_N_REFS is not initialized
1284 if (optimize && !REG_N_REFS (i) && !REG_N_SETS (i))
1287 for (class = (int) ALL_REGS - 1; class > 0; class--)
1289 /* Ignore classes that are too small for this operand or
1290 invalid for an operand that was auto-incremented. */
1291 if (!contains_reg_of_mode [class][PSEUDO_REGNO_MODE (i)]
1292 #ifdef FORBIDDEN_INC_DEC_CLASSES
1293 || (in_inc_dec[i] && forbidden_inc_dec_class[class])
1295 #ifdef CANNOT_CHANGE_MODE_CLASS
1296 || invalid_mode_change_p (i, (enum reg_class) class,
1297 PSEUDO_REGNO_MODE (i))
1301 else if (p->cost[class] < best_cost)
1303 best_cost = p->cost[class];
1304 best = (enum reg_class) class;
1306 else if (p->cost[class] == best_cost)
1307 best = reg_class_subunion[(int) best][class];
1310 /* Record the alternate register class; i.e., a class for which
1311 every register in it is better than using memory. If adding a
1312 class would make a smaller class (i.e., no union of just those
1313 classes exists), skip that class. The major unions of classes
1314 should be provided as a register class. Don't do this if we
1315 will be doing it again later. */
1317 if ((pass == 1 || dump) || ! flag_expensive_optimizations)
1318 for (class = 0; class < N_REG_CLASSES; class++)
1319 if (p->cost[class] < p->mem_cost
1320 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]]
1321 > reg_class_size[(int) alt])
1322 #ifdef FORBIDDEN_INC_DEC_CLASSES
1323 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class])
1325 #ifdef CANNOT_CHANGE_MODE_CLASS
1326 && ! invalid_mode_change_p (i, (enum reg_class) class,
1327 PSEUDO_REGNO_MODE (i))
1330 alt = reg_class_subunion[(int) alt][class];
1332 /* If we don't add any classes, nothing to try. */
1337 && (reg_pref[i].prefclass != (int) best
1338 || reg_pref[i].altclass != (int) alt))
1340 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1341 fprintf (dump, " Register %i", i);
1342 if (alt == ALL_REGS || best == ALL_REGS)
1343 fprintf (dump, " pref %s\n", reg_class_names[(int) best]);
1344 else if (alt == NO_REGS)
1345 fprintf (dump, " pref %s or none\n", reg_class_names[(int) best]);
1347 fprintf (dump, " pref %s, else %s\n",
1348 reg_class_names[(int) best],
1349 reg_class_names[(int) alt]);
1352 /* We cast to (int) because (char) hits bugs in some compilers. */
1353 reg_pref[i].prefclass = (int) best;
1354 reg_pref[i].altclass = (int) alt;
1358 #ifdef FORBIDDEN_INC_DEC_CLASSES
1364 /* Record the cost of using memory or registers of various classes for
1365 the operands in INSN.
1367 N_ALTS is the number of alternatives.
1369 N_OPS is the number of operands.
1371 OPS is an array of the operands.
1373 MODES are the modes of the operands, in case any are VOIDmode.
1375 CONSTRAINTS are the constraints to use for the operands. This array
1376 is modified by this procedure.
1378 This procedure works alternative by alternative. For each alternative
1379 we assume that we will be able to allocate all pseudos to their ideal
1380 register class and calculate the cost of using that alternative. Then
1381 we compute for each operand that is a pseudo-register, the cost of
1382 having the pseudo allocated to each register class and using it in that
1383 alternative. To this cost is added the cost of the alternative.
1385 The cost of each class for this insn is its lowest cost among all the
1389 record_reg_classes (n_alts, n_ops, ops, modes,
1390 constraints, insn, op_costs, reg_pref)
1394 enum machine_mode *modes;
1395 const char **constraints;
1397 struct costs *op_costs;
1398 struct reg_pref *reg_pref;
1404 /* Process each alternative, each time minimizing an operand's cost with
1405 the cost for each operand in that alternative. */
1407 for (alt = 0; alt < n_alts; alt++)
1409 struct costs this_op_costs[MAX_RECOG_OPERANDS];
1412 enum reg_class classes[MAX_RECOG_OPERANDS];
1413 int allows_mem[MAX_RECOG_OPERANDS];
1416 for (i = 0; i < n_ops; i++)
1418 const char *p = constraints[i];
1420 enum machine_mode mode = modes[i];
1421 int allows_addr = 0;
1425 /* Initially show we know nothing about the register class. */
1426 classes[i] = NO_REGS;
1429 /* If this operand has no constraints at all, we can conclude
1430 nothing about it since anything is valid. */
1434 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1435 memset ((char *) &this_op_costs[i], 0, sizeof this_op_costs[i]);
1440 /* If this alternative is only relevant when this operand
1441 matches a previous operand, we do different things depending
1442 on whether this operand is a pseudo-reg or not. We must process
1443 any modifiers for the operand before we can make this test. */
1445 while (*p == '%' || *p == '=' || *p == '+' || *p == '&')
1448 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
1450 /* Copy class and whether memory is allowed from the matching
1451 alternative. Then perform any needed cost computations
1452 and/or adjustments. */
1454 classes[i] = classes[j];
1455 allows_mem[i] = allows_mem[j];
1457 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER)
1459 /* If this matches the other operand, we have no added
1461 if (rtx_equal_p (ops[j], op))
1464 /* If we can put the other operand into a register, add to
1465 the cost of this alternative the cost to copy this
1466 operand to the register used for the other operand. */
1468 else if (classes[j] != NO_REGS)
1469 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1;
1471 else if (GET_CODE (ops[j]) != REG
1472 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
1474 /* This op is a pseudo but the one it matches is not. */
1476 /* If we can't put the other operand into a register, this
1477 alternative can't be used. */
1479 if (classes[j] == NO_REGS)
1482 /* Otherwise, add to the cost of this alternative the cost
1483 to copy the other operand to the register used for this
1487 alt_cost += copy_cost (ops[j], mode, classes[j], 1);
1491 /* The costs of this operand are not the same as the other
1492 operand since move costs are not symmetric. Moreover,
1493 if we cannot tie them, this alternative needs to do a
1494 copy, which is one instruction. */
1496 struct costs *pp = &this_op_costs[i];
1498 for (class = 0; class < N_REG_CLASSES; class++)
1500 = ((recog_data.operand_type[i] != OP_OUT
1501 ? may_move_in_cost[mode][class][(int) classes[i]]
1503 + (recog_data.operand_type[i] != OP_IN
1504 ? may_move_out_cost[mode][(int) classes[i]][class]
1507 /* If the alternative actually allows memory, make things
1508 a bit cheaper since we won't need an extra insn to
1512 = ((recog_data.operand_type[i] != OP_IN
1513 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1515 + (recog_data.operand_type[i] != OP_OUT
1516 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1517 : 0) - allows_mem[i]);
1519 /* If we have assigned a class to this register in our
1520 first pass, add a cost to this alternative corresponding
1521 to what we would add if this register were not in the
1522 appropriate class. */
1526 += (may_move_in_cost[mode]
1527 [(unsigned char) reg_pref[REGNO (op)].prefclass]
1528 [(int) classes[i]]);
1530 if (REGNO (ops[i]) != REGNO (ops[j])
1531 && ! find_reg_note (insn, REG_DEAD, op))
1534 /* This is in place of ordinary cost computation
1535 for this operand, so skip to the end of the
1536 alternative (should be just one character). */
1537 while (*p && *p++ != ',')
1545 /* Scan all the constraint letters. See if the operand matches
1546 any of the constraints. Collect the valid register classes
1547 and see if this operand accepts memory. */
1549 while (*p && (c = *p++) != ',')
1553 /* Ignore the next letter for this pass. */
1559 case '!': case '#': case '&':
1560 case '0': case '1': case '2': case '3': case '4':
1561 case '5': case '6': case '7': case '8': case '9':
1566 win = address_operand (op, GET_MODE (op));
1567 /* We know this operand is an address, so we want it to be
1568 allocated to a register that can be the base of an
1569 address, ie BASE_REG_CLASS. */
1571 = reg_class_subunion[(int) classes[i]]
1572 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1575 case 'm': case 'o': case 'V':
1576 /* It doesn't seem worth distinguishing between offsettable
1577 and non-offsettable addresses here. */
1579 if (GET_CODE (op) == MEM)
1584 if (GET_CODE (op) == MEM
1585 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1586 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1591 if (GET_CODE (op) == MEM
1592 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1593 || GET_CODE (XEXP (op, 0)) == POST_INC))
1599 if (GET_CODE (op) == CONST_DOUBLE
1600 || (GET_CODE (op) == CONST_VECTOR
1601 && (GET_MODE_CLASS (GET_MODE (op))
1602 == MODE_VECTOR_FLOAT)))
1608 if (GET_CODE (op) == CONST_DOUBLE
1609 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
1614 if (GET_CODE (op) == CONST_INT
1615 || (GET_CODE (op) == CONST_DOUBLE
1616 && GET_MODE (op) == VOIDmode))
1620 #ifdef LEGITIMATE_PIC_OPERAND_P
1621 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1628 if (GET_CODE (op) == CONST_INT
1629 || (GET_CODE (op) == CONST_DOUBLE
1630 && GET_MODE (op) == VOIDmode))
1642 if (GET_CODE (op) == CONST_INT
1643 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
1652 if (GET_CODE (op) == MEM
1654 #ifdef LEGITIMATE_PIC_OPERAND_P
1655 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1662 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1666 if (REG_CLASS_FROM_LETTER (c) != NO_REGS)
1668 = reg_class_subunion[(int) classes[i]]
1669 [(int) REG_CLASS_FROM_LETTER (c)];
1670 #ifdef EXTRA_CONSTRAINT
1671 else if (EXTRA_CONSTRAINT (op, c))
1674 if (EXTRA_MEMORY_CONSTRAINT (c))
1676 /* Every MEM can be reloaded to fit. */
1678 if (GET_CODE (op) == MEM)
1681 if (EXTRA_ADDRESS_CONSTRAINT (op))
1683 /* Every address can be reloaded to fit. */
1685 if (address_operand (op, GET_MODE (op)))
1687 /* We know this operand is an address, so we want it to be
1688 allocated to a register that can be the base of an
1689 address, ie BASE_REG_CLASS. */
1691 = reg_class_subunion[(int) classes[i]]
1692 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1700 /* How we account for this operand now depends on whether it is a
1701 pseudo register or not. If it is, we first check if any
1702 register classes are valid. If not, we ignore this alternative,
1703 since we want to assume that all pseudos get allocated for
1704 register preferencing. If some register class is valid, compute
1705 the costs of moving the pseudo into that class. */
1707 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1709 if (classes[i] == NO_REGS)
1711 /* We must always fail if the operand is a REG, but
1712 we did not find a suitable class.
1714 Otherwise we may perform an uninitialized read
1715 from this_op_costs after the `continue' statement
1721 struct costs *pp = &this_op_costs[i];
1723 for (class = 0; class < N_REG_CLASSES; class++)
1725 = ((recog_data.operand_type[i] != OP_OUT
1726 ? may_move_in_cost[mode][class][(int) classes[i]]
1728 + (recog_data.operand_type[i] != OP_IN
1729 ? may_move_out_cost[mode][(int) classes[i]][class]
1732 /* If the alternative actually allows memory, make things
1733 a bit cheaper since we won't need an extra insn to
1737 = ((recog_data.operand_type[i] != OP_IN
1738 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1740 + (recog_data.operand_type[i] != OP_OUT
1741 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1742 : 0) - allows_mem[i]);
1744 /* If we have assigned a class to this register in our
1745 first pass, add a cost to this alternative corresponding
1746 to what we would add if this register were not in the
1747 appropriate class. */
1751 += (may_move_in_cost[mode]
1752 [(unsigned char) reg_pref[REGNO (op)].prefclass]
1753 [(int) classes[i]]);
1757 /* Otherwise, if this alternative wins, either because we
1758 have already determined that or if we have a hard register of
1759 the proper class, there is no cost for this alternative. */
1762 || (GET_CODE (op) == REG
1763 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op))))
1766 /* If registers are valid, the cost of this alternative includes
1767 copying the object to and/or from a register. */
1769 else if (classes[i] != NO_REGS)
1771 if (recog_data.operand_type[i] != OP_OUT)
1772 alt_cost += copy_cost (op, mode, classes[i], 1);
1774 if (recog_data.operand_type[i] != OP_IN)
1775 alt_cost += copy_cost (op, mode, classes[i], 0);
1778 /* The only other way this alternative can be used is if this is a
1779 constant that could be placed into memory. */
1781 else if (CONSTANT_P (op) && (allows_addr || allows_mem[i]))
1782 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1);
1790 /* Finally, update the costs with the information we've calculated
1791 about this alternative. */
1793 for (i = 0; i < n_ops; i++)
1794 if (GET_CODE (ops[i]) == REG
1795 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1797 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1798 int scale = 1 + (recog_data.operand_type[i] == OP_INOUT);
1800 pp->mem_cost = MIN (pp->mem_cost,
1801 (qq->mem_cost + alt_cost) * scale);
1803 for (class = 0; class < N_REG_CLASSES; class++)
1804 pp->cost[class] = MIN (pp->cost[class],
1805 (qq->cost[class] + alt_cost) * scale);
1809 /* If this insn is a single set copying operand 1 to operand 0
1810 and one operand is a pseudo with the other a hard reg or a pseudo
1811 that prefers a register that is in its own register class then
1812 we may want to adjust the cost of that register class to -1.
1814 Avoid the adjustment if the source does not die to avoid stressing of
1815 register allocator by preferrencing two coliding registers into single
1818 Also avoid the adjustment if a copy between registers of the class
1819 is expensive (ten times the cost of a default copy is considered
1820 arbitrarily expensive). This avoids losing when the preferred class
1821 is very expensive as the source of a copy instruction. */
1823 if ((set = single_set (insn)) != 0
1824 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set)
1825 && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG
1826 && find_regno_note (insn, REG_DEAD, REGNO (ops[1])))
1827 for (i = 0; i <= 1; i++)
1828 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1830 unsigned int regno = REGNO (ops[!i]);
1831 enum machine_mode mode = GET_MODE (ops[!i]);
1835 if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0)
1837 enum reg_class pref = reg_pref[regno].prefclass;
1839 if ((reg_class_size[(unsigned char) pref]
1840 == (unsigned) CLASS_MAX_NREGS (pref, mode))
1841 && REGISTER_MOVE_COST (mode, pref, pref) < 10 * 2)
1842 op_costs[i].cost[(unsigned char) pref] = -1;
1844 else if (regno < FIRST_PSEUDO_REGISTER)
1845 for (class = 0; class < N_REG_CLASSES; class++)
1846 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1847 && reg_class_size[class] == (unsigned) CLASS_MAX_NREGS (class, mode))
1849 if (reg_class_size[class] == 1)
1850 op_costs[i].cost[class] = -1;
1853 for (nr = 0; nr < (unsigned) HARD_REGNO_NREGS (regno, mode); nr++)
1855 if (! TEST_HARD_REG_BIT (reg_class_contents[class],
1860 if (nr == (unsigned) HARD_REGNO_NREGS (regno,mode))
1861 op_costs[i].cost[class] = -1;
1867 /* Compute the cost of loading X into (if TO_P is nonzero) or from (if
1868 TO_P is zero) a register of class CLASS in mode MODE.
1870 X must not be a pseudo. */
1873 copy_cost (x, mode, class, to_p)
1875 enum machine_mode mode ATTRIBUTE_UNUSED;
1876 enum reg_class class;
1877 int to_p ATTRIBUTE_UNUSED;
1879 #ifdef HAVE_SECONDARY_RELOADS
1880 enum reg_class secondary_class = NO_REGS;
1883 /* If X is a SCRATCH, there is actually nothing to move since we are
1884 assuming optimal allocation. */
1886 if (GET_CODE (x) == SCRATCH)
1889 /* Get the class we will actually use for a reload. */
1890 class = PREFERRED_RELOAD_CLASS (x, class);
1892 #ifdef HAVE_SECONDARY_RELOADS
1893 /* If we need a secondary reload (we assume here that we are using
1894 the secondary reload as an intermediate, not a scratch register), the
1895 cost is that to load the input into the intermediate register, then
1896 to copy them. We use a special value of TO_P to avoid recursion. */
1898 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1900 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x);
1903 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1905 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x);
1908 if (secondary_class != NO_REGS)
1909 return (move_cost[mode][(int) secondary_class][(int) class]
1910 + copy_cost (x, mode, secondary_class, 2));
1911 #endif /* HAVE_SECONDARY_RELOADS */
1913 /* For memory, use the memory move cost, for (hard) registers, use the
1914 cost to move between the register classes, and use 2 for everything
1915 else (constants). */
1917 if (GET_CODE (x) == MEM || class == NO_REGS)
1918 return MEMORY_MOVE_COST (mode, class, to_p);
1920 else if (GET_CODE (x) == REG)
1921 return move_cost[mode][(int) REGNO_REG_CLASS (REGNO (x))][(int) class];
1924 /* If this is a constant, we may eventually want to call rtx_cost here. */
1925 return COSTS_N_INSNS (1);
1928 /* Record the pseudo registers we must reload into hard registers
1929 in a subexpression of a memory address, X.
1931 CLASS is the class that the register needs to be in and is either
1932 BASE_REG_CLASS or INDEX_REG_CLASS.
1934 SCALE is twice the amount to multiply the cost by (it is twice so we
1935 can represent half-cost adjustments). */
1938 record_address_regs (x, class, scale)
1940 enum reg_class class;
1943 enum rtx_code code = GET_CODE (x);
1956 /* When we have an address that is a sum,
1957 we must determine whether registers are "base" or "index" regs.
1958 If there is a sum of two registers, we must choose one to be
1959 the "base". Luckily, we can use the REG_POINTER to make a good
1960 choice most of the time. We only need to do this on machines
1961 that can have two registers in an address and where the base
1962 and index register classes are different.
1964 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1965 that seems bogus since it should only be set when we are sure
1966 the register is being used as a pointer. */
1969 rtx arg0 = XEXP (x, 0);
1970 rtx arg1 = XEXP (x, 1);
1971 enum rtx_code code0 = GET_CODE (arg0);
1972 enum rtx_code code1 = GET_CODE (arg1);
1974 /* Look inside subregs. */
1975 if (code0 == SUBREG)
1976 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1977 if (code1 == SUBREG)
1978 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1980 /* If this machine only allows one register per address, it must
1981 be in the first operand. */
1983 if (MAX_REGS_PER_ADDRESS == 1)
1984 record_address_regs (arg0, class, scale);
1986 /* If index and base registers are the same on this machine, just
1987 record registers in any non-constant operands. We assume here,
1988 as well as in the tests below, that all addresses are in
1991 else if (INDEX_REG_CLASS == MODE_BASE_REG_CLASS (VOIDmode))
1993 record_address_regs (arg0, class, scale);
1994 if (! CONSTANT_P (arg1))
1995 record_address_regs (arg1, class, scale);
1998 /* If the second operand is a constant integer, it doesn't change
1999 what class the first operand must be. */
2001 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
2002 record_address_regs (arg0, class, scale);
2004 /* If the second operand is a symbolic constant, the first operand
2005 must be an index register. */
2007 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
2008 record_address_regs (arg0, INDEX_REG_CLASS, scale);
2010 /* If both operands are registers but one is already a hard register
2011 of index or base class, give the other the class that the hard
2014 #ifdef REG_OK_FOR_BASE_P
2015 else if (code0 == REG && code1 == REG
2016 && REGNO (arg0) < FIRST_PSEUDO_REGISTER
2017 && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0)))
2018 record_address_regs (arg1,
2019 REG_OK_FOR_BASE_P (arg0)
2020 ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (VOIDmode),
2022 else if (code0 == REG && code1 == REG
2023 && REGNO (arg1) < FIRST_PSEUDO_REGISTER
2024 && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1)))
2025 record_address_regs (arg0,
2026 REG_OK_FOR_BASE_P (arg1)
2027 ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (VOIDmode),
2031 /* If one operand is known to be a pointer, it must be the base
2032 with the other operand the index. Likewise if the other operand
2035 else if ((code0 == REG && REG_POINTER (arg0))
2038 record_address_regs (arg0, MODE_BASE_REG_CLASS (VOIDmode), scale);
2039 record_address_regs (arg1, INDEX_REG_CLASS, scale);
2041 else if ((code1 == REG && REG_POINTER (arg1))
2044 record_address_regs (arg0, INDEX_REG_CLASS, scale);
2045 record_address_regs (arg1, MODE_BASE_REG_CLASS (VOIDmode), scale);
2048 /* Otherwise, count equal chances that each might be a base
2049 or index register. This case should be rare. */
2053 record_address_regs (arg0, MODE_BASE_REG_CLASS (VOIDmode),
2055 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2);
2056 record_address_regs (arg1, MODE_BASE_REG_CLASS (VOIDmode),
2058 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2);
2063 /* Double the importance of a pseudo register that is incremented
2064 or decremented, since it would take two extra insns
2065 if it ends up in the wrong place. */
2068 record_address_regs (XEXP (x, 0), MODE_BASE_REG_CLASS (VOIDmode),
2070 if (REG_P (XEXP (XEXP (x, 1), 1)))
2071 record_address_regs (XEXP (XEXP (x, 1), 1),
2072 INDEX_REG_CLASS, 2 * scale);
2079 /* Double the importance of a pseudo register that is incremented
2080 or decremented, since it would take two extra insns
2081 if it ends up in the wrong place. If the operand is a pseudo,
2082 show it is being used in an INC_DEC context. */
2084 #ifdef FORBIDDEN_INC_DEC_CLASSES
2085 if (GET_CODE (XEXP (x, 0)) == REG
2086 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
2087 in_inc_dec[REGNO (XEXP (x, 0))] = 1;
2090 record_address_regs (XEXP (x, 0), class, 2 * scale);
2095 struct costs *pp = &costs[REGNO (x)];
2098 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2;
2100 for (i = 0; i < N_REG_CLASSES; i++)
2101 pp->cost[i] += (may_move_in_cost[Pmode][i][(int) class] * scale) / 2;
2107 const char *fmt = GET_RTX_FORMAT (code);
2109 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2111 record_address_regs (XEXP (x, i), class, scale);
2116 #ifdef FORBIDDEN_INC_DEC_CLASSES
2118 /* Return 1 if REG is valid as an auto-increment memory reference
2119 to an object of MODE. */
2122 auto_inc_dec_reg_p (reg, mode)
2124 enum machine_mode mode;
2126 if (HAVE_POST_INCREMENT
2127 && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg)))
2130 if (HAVE_POST_DECREMENT
2131 && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg)))
2134 if (HAVE_PRE_INCREMENT
2135 && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg)))
2138 if (HAVE_PRE_DECREMENT
2139 && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg)))
2146 static short *renumber;
2147 static size_t regno_allocated;
2148 static unsigned int reg_n_max;
2150 /* Allocate enough space to hold NUM_REGS registers for the tables used for
2151 reg_scan and flow_analysis that are indexed by the register number. If
2152 NEW_P is nonzero, initialize all of the registers, otherwise only
2153 initialize the new registers allocated. The same table is kept from
2154 function to function, only reallocating it when we need more room. If
2155 RENUMBER_P is nonzero, allocate the reg_renumber array also. */
2158 allocate_reg_info (num_regs, new_p, renumber_p)
2164 size_t size_renumber;
2165 size_t min = (new_p) ? 0 : reg_n_max;
2166 struct reg_info_data *reg_data;
2168 if (num_regs > regno_allocated)
2170 size_t old_allocated = regno_allocated;
2172 regno_allocated = num_regs + (num_regs / 20); /* add some slop space */
2173 size_renumber = regno_allocated * sizeof (short);
2177 VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info");
2178 renumber = (short *) xmalloc (size_renumber);
2179 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated
2180 * sizeof (struct reg_pref));
2185 VARRAY_GROW (reg_n_info, regno_allocated);
2187 if (new_p) /* if we're zapping everything, no need to realloc */
2189 free ((char *) renumber);
2190 free ((char *) reg_pref);
2191 renumber = (short *) xmalloc (size_renumber);
2192 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated
2193 * sizeof (struct reg_pref));
2198 renumber = (short *) xrealloc ((char *) renumber, size_renumber);
2199 reg_pref_buffer = (struct reg_pref *) xrealloc ((char *) reg_pref_buffer,
2201 * sizeof (struct reg_pref));
2205 size_info = (regno_allocated - old_allocated) * sizeof (reg_info)
2206 + sizeof (struct reg_info_data) - sizeof (reg_info);
2207 reg_data = (struct reg_info_data *) xcalloc (size_info, 1);
2208 reg_data->min_index = old_allocated;
2209 reg_data->max_index = regno_allocated - 1;
2210 reg_data->next = reg_info_head;
2211 reg_info_head = reg_data;
2214 reg_n_max = num_regs;
2217 /* Loop through each of the segments allocated for the actual
2218 reg_info pages, and set up the pointers, zero the pages, etc. */
2219 for (reg_data = reg_info_head;
2220 reg_data && reg_data->max_index >= min;
2221 reg_data = reg_data->next)
2223 size_t min_index = reg_data->min_index;
2224 size_t max_index = reg_data->max_index;
2225 size_t max = MIN (max_index, num_regs);
2226 size_t local_min = min - min_index;
2229 if (reg_data->min_index > num_regs)
2232 if (min < min_index)
2234 if (!reg_data->used_p) /* page just allocated with calloc */
2235 reg_data->used_p = 1; /* no need to zero */
2237 memset ((char *) ®_data->data[local_min], 0,
2238 sizeof (reg_info) * (max - min_index - local_min + 1));
2240 for (i = min_index+local_min; i <= max; i++)
2242 VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index];
2243 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN;
2245 reg_pref_buffer[i].prefclass = (char) NO_REGS;
2246 reg_pref_buffer[i].altclass = (char) NO_REGS;
2251 /* If {pref,alt}class have already been allocated, update the pointers to
2252 the newly realloced ones. */
2254 reg_pref = reg_pref_buffer;
2257 reg_renumber = renumber;
2259 /* Tell the regset code about the new number of registers. */
2260 MAX_REGNO_REG_SET (num_regs, new_p, renumber_p);
2263 /* Free up the space allocated by allocate_reg_info. */
2269 struct reg_info_data *reg_data;
2270 struct reg_info_data *reg_next;
2272 VARRAY_FREE (reg_n_info);
2273 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
2275 reg_next = reg_data->next;
2276 free ((char *) reg_data);
2279 free (reg_pref_buffer);
2280 reg_pref_buffer = (struct reg_pref *) 0;
2281 reg_info_head = (struct reg_info_data *) 0;
2282 renumber = (short *) 0;
2284 regno_allocated = 0;
2288 /* This is the `regscan' pass of the compiler, run just before cse
2289 and again just before loop.
2291 It finds the first and last use of each pseudo-register
2292 and records them in the vectors regno_first_uid, regno_last_uid
2293 and counts the number of sets in the vector reg_n_sets.
2295 REPEAT is nonzero the second time this is called. */
2297 /* Maximum number of parallel sets and clobbers in any insn in this fn.
2298 Always at least 3, since the combiner could put that many together
2299 and we want this to remain correct for all the remaining passes.
2300 This corresponds to the maximum number of times note_stores will call
2301 a function for any insn. */
2305 /* Used as a temporary to record the largest number of registers in
2306 PARALLEL in a SET_DEST. This is added to max_parallel. */
2308 static int max_set_parallel;
2311 reg_scan (f, nregs, repeat)
2314 int repeat ATTRIBUTE_UNUSED;
2318 allocate_reg_info (nregs, TRUE, FALSE);
2320 max_set_parallel = 0;
2322 for (insn = f; insn; insn = NEXT_INSN (insn))
2323 if (GET_CODE (insn) == INSN
2324 || GET_CODE (insn) == CALL_INSN
2325 || GET_CODE (insn) == JUMP_INSN)
2327 if (GET_CODE (PATTERN (insn)) == PARALLEL
2328 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2329 max_parallel = XVECLEN (PATTERN (insn), 0);
2330 reg_scan_mark_refs (PATTERN (insn), insn, 0, 0);
2332 if (REG_NOTES (insn))
2333 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0);
2336 max_parallel += max_set_parallel;
2339 /* Update 'regscan' information by looking at the insns
2340 from FIRST to LAST. Some new REGs have been created,
2341 and any REG with number greater than OLD_MAX_REGNO is
2342 such a REG. We only update information for those. */
2345 reg_scan_update (first, last, old_max_regno)
2348 unsigned int old_max_regno;
2352 allocate_reg_info (max_reg_num (), FALSE, FALSE);
2354 for (insn = first; insn != last; insn = NEXT_INSN (insn))
2355 if (GET_CODE (insn) == INSN
2356 || GET_CODE (insn) == CALL_INSN
2357 || GET_CODE (insn) == JUMP_INSN)
2359 if (GET_CODE (PATTERN (insn)) == PARALLEL
2360 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2361 max_parallel = XVECLEN (PATTERN (insn), 0);
2362 reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno);
2364 if (REG_NOTES (insn))
2365 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno);
2369 /* X is the expression to scan. INSN is the insn it appears in.
2370 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2371 We should only record information for REGs with numbers
2372 greater than or equal to MIN_REGNO. */
2375 reg_scan_mark_refs (x, insn, note_flag, min_regno)
2379 unsigned int min_regno;
2387 code = GET_CODE (x);
2404 unsigned int regno = REGNO (x);
2406 if (regno >= min_regno)
2408 REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn);
2410 REGNO_LAST_UID (regno) = INSN_UID (insn);
2411 if (REGNO_FIRST_UID (regno) == 0)
2412 REGNO_FIRST_UID (regno) = INSN_UID (insn);
2413 /* If we are called by reg_scan_update() (indicated by min_regno
2414 being set), we also need to update the reference count. */
2416 REG_N_REFS (regno)++;
2423 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno);
2425 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2430 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2435 rtx reg = XEXP (x, 0);
2437 && REGNO (reg) >= min_regno)
2439 REG_N_SETS (REGNO (reg))++;
2440 REG_N_REFS (REGNO (reg))++;
2446 /* Count a set of the destination if it is a register. */
2447 for (dest = SET_DEST (x);
2448 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
2449 || GET_CODE (dest) == ZERO_EXTEND;
2450 dest = XEXP (dest, 0))
2453 /* For a PARALLEL, record the number of things (less the usual one for a
2454 SET) that are set. */
2455 if (GET_CODE (dest) == PARALLEL)
2456 max_set_parallel = MAX (max_set_parallel, XVECLEN (dest, 0) - 1);
2458 if (GET_CODE (dest) == REG
2459 && REGNO (dest) >= min_regno)
2461 REG_N_SETS (REGNO (dest))++;
2462 REG_N_REFS (REGNO (dest))++;
2465 /* If this is setting a pseudo from another pseudo or the sum of a
2466 pseudo and a constant integer and the other pseudo is known to be
2467 a pointer, set the destination to be a pointer as well.
2469 Likewise if it is setting the destination from an address or from a
2470 value equivalent to an address or to the sum of an address and
2473 But don't do any of this if the pseudo corresponds to a user
2474 variable since it should have already been set as a pointer based
2477 if (GET_CODE (SET_DEST (x)) == REG
2478 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER
2479 && REGNO (SET_DEST (x)) >= min_regno
2480 /* If the destination pseudo is set more than once, then other
2481 sets might not be to a pointer value (consider access to a
2482 union in two threads of control in the presense of global
2483 optimizations). So only set REG_POINTER on the destination
2484 pseudo if this is the only set of that pseudo. */
2485 && REG_N_SETS (REGNO (SET_DEST (x))) == 1
2486 && ! REG_USERVAR_P (SET_DEST (x))
2487 && ! REG_POINTER (SET_DEST (x))
2488 && ((GET_CODE (SET_SRC (x)) == REG
2489 && REG_POINTER (SET_SRC (x)))
2490 || ((GET_CODE (SET_SRC (x)) == PLUS
2491 || GET_CODE (SET_SRC (x)) == LO_SUM)
2492 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2493 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2494 && REG_POINTER (XEXP (SET_SRC (x), 0)))
2495 || GET_CODE (SET_SRC (x)) == CONST
2496 || GET_CODE (SET_SRC (x)) == SYMBOL_REF
2497 || GET_CODE (SET_SRC (x)) == LABEL_REF
2498 || (GET_CODE (SET_SRC (x)) == HIGH
2499 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
2500 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
2501 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
2502 || ((GET_CODE (SET_SRC (x)) == PLUS
2503 || GET_CODE (SET_SRC (x)) == LO_SUM)
2504 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
2505 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
2506 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
2507 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
2508 && (GET_CODE (XEXP (note, 0)) == CONST
2509 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
2510 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
2511 REG_POINTER (SET_DEST (x)) = 1;
2513 /* If this is setting a register from a register or from a simple
2514 conversion of a register, propagate REG_DECL. */
2515 if (GET_CODE (dest) == REG)
2517 rtx src = SET_SRC (x);
2519 while (GET_CODE (src) == SIGN_EXTEND
2520 || GET_CODE (src) == ZERO_EXTEND
2521 || GET_CODE (src) == TRUNCATE
2522 || (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)))
2523 src = XEXP (src, 0);
2525 if (GET_CODE (src) == REG && REGNO_DECL (REGNO (src)) == 0)
2526 REGNO_DECL (REGNO (src)) = REGNO_DECL (REGNO (dest));
2527 else if (GET_CODE (src) == REG && REGNO_DECL (REGNO (dest)) == 0)
2528 REGNO_DECL (REGNO (dest)) = REGNO_DECL (REGNO (src));
2531 /* ... fall through ... */
2535 const char *fmt = GET_RTX_FORMAT (code);
2537 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2540 reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno);
2541 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
2544 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2545 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno);
2552 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2556 reg_class_subset_p (c1, c2)
2560 if (c1 == c2) return 1;
2565 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) c1],
2566 reg_class_contents[(int) c2],
2571 /* Return nonzero if there is a register that is in both C1 and C2. */
2574 reg_classes_intersect_p (c1, c2)
2583 if (c1 == c2) return 1;
2585 if (c1 == ALL_REGS || c2 == ALL_REGS)
2588 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
2589 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
2591 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose);
2598 /* Release any memory allocated by register sets. */
2601 regset_release_memory ()
2603 bitmap_release_memory ();
2606 #ifdef CANNOT_CHANGE_MODE_CLASS
2607 /* Set bits in *USED which correspond to registers which can't change
2608 their mode from FROM to any mode in which REGNO was encountered. */
2611 cannot_change_mode_set_regs (used, from, regno)
2613 enum machine_mode from;
2616 enum machine_mode to;
2617 enum reg_class class;
2619 for (to = VOIDmode; to < MAX_MACHINE_MODE; ++to)
2620 if (REGNO_REG_SET_P (&subregs_of_mode[to], regno))
2622 class = CANNOT_CHANGE_MODE_CLASS (from, to);
2623 if (class != NO_REGS)
2624 IOR_HARD_REG_SET (*used, reg_class_contents [(int) class]);
2628 /* Return 1 if REGNO has had an invalid mode change in CLASS from FROM
2632 invalid_mode_change_p (regno, class, from_mode)
2634 enum reg_class class;
2635 enum machine_mode from_mode;
2637 enum machine_mode to_mode;
2639 for (to_mode = 0; to_mode < NUM_MACHINE_MODES; ++to_mode)
2640 if (REGNO_REG_SET_P (&subregs_of_mode[(int) to_mode], regno)
2641 && reg_classes_intersect_p
2642 (class, CANNOT_CHANGE_MODE_CLASS (from_mode, to_mode)))
2646 #endif /* CANNOT_CHANGE_MODE_CLASS */
2648 #include "gt-regclass.h"