1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "insn-config.h"
30 #include "insn-attr.h"
31 #include "hard-reg-set.h"
34 #include "addresses.h"
40 #include "basic-block.h"
45 #include "tree-pass.h"
48 #ifndef STACK_PUSH_CODE
49 #ifdef STACK_GROWS_DOWNWARD
50 #define STACK_PUSH_CODE PRE_DEC
52 #define STACK_PUSH_CODE PRE_INC
56 #ifndef STACK_POP_CODE
57 #ifdef STACK_GROWS_DOWNWARD
58 #define STACK_POP_CODE POST_INC
60 #define STACK_POP_CODE POST_DEC
64 #ifndef HAVE_ATTR_enabled
66 get_attr_enabled (rtx insn ATTRIBUTE_UNUSED)
72 static void validate_replace_rtx_1 (rtx *, rtx, rtx, rtx, bool);
73 static void validate_replace_src_1 (rtx *, void *);
74 static rtx split_insn (rtx);
76 /* Nonzero means allow operands to be volatile.
77 This should be 0 if you are generating rtl, such as if you are calling
78 the functions in optabs.c and expmed.c (most of the time).
79 This should be 1 if all valid insns need to be recognized,
80 such as in reginfo.c and final.c and reload.c.
82 init_recog and init_recog_no_volatile are responsible for setting this. */
86 struct recog_data recog_data;
88 /* Contains a vector of operand_alternative structures for every operand.
89 Set up by preprocess_constraints. */
90 struct operand_alternative recog_op_alt[MAX_RECOG_OPERANDS][MAX_RECOG_ALTERNATIVES];
92 /* On return from `constrain_operands', indicate which alternative
95 int which_alternative;
97 /* Nonzero after end of reload pass.
98 Set to 1 or 0 by toplev.c.
99 Controls the significance of (SUBREG (MEM)). */
101 int reload_completed;
103 /* Nonzero after thread_prologue_and_epilogue_insns has run. */
104 int epilogue_completed;
106 /* Initialize data used by the function `recog'.
107 This must be called once in the compilation of a function
108 before any insn recognition may be done in the function. */
111 init_recog_no_volatile (void)
123 /* Check that X is an insn-body for an `asm' with operands
124 and that the operands mentioned in it are legitimate. */
127 check_asm_operands (rtx x)
131 const char **constraints;
134 /* Post-reload, be more strict with things. */
135 if (reload_completed)
137 /* ??? Doh! We've not got the wrapping insn. Cook one up. */
138 extract_insn (make_insn_raw (x));
139 constrain_operands (1);
140 return which_alternative >= 0;
143 noperands = asm_noperands (x);
149 operands = XALLOCAVEC (rtx, noperands);
150 constraints = XALLOCAVEC (const char *, noperands);
152 decode_asm_operands (x, operands, NULL, constraints, NULL, NULL);
154 for (i = 0; i < noperands; i++)
156 const char *c = constraints[i];
159 if (! asm_operand_ok (operands[i], c, constraints))
166 /* Static data for the next two routines. */
168 typedef struct change_t
177 static change_t *changes;
178 static int changes_allocated;
180 static int num_changes = 0;
182 /* Validate a proposed change to OBJECT. LOC is the location in the rtl
183 at which NEW_RTX will be placed. If OBJECT is zero, no validation is done,
184 the change is simply made.
186 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
187 will be called with the address and mode as parameters. If OBJECT is
188 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
191 IN_GROUP is nonzero if this is part of a group of changes that must be
192 performed as a group. In that case, the changes will be stored. The
193 function `apply_change_group' will validate and apply the changes.
195 If IN_GROUP is zero, this is a single change. Try to recognize the insn
196 or validate the memory reference with the change applied. If the result
197 is not valid for the machine, suppress the change and return zero.
198 Otherwise, perform the change and return 1. */
201 validate_change_1 (rtx object, rtx *loc, rtx new_rtx, bool in_group, bool unshare)
205 if (old == new_rtx || rtx_equal_p (old, new_rtx))
208 gcc_assert (in_group != 0 || num_changes == 0);
212 /* Save the information describing this change. */
213 if (num_changes >= changes_allocated)
215 if (changes_allocated == 0)
216 /* This value allows for repeated substitutions inside complex
217 indexed addresses, or changes in up to 5 insns. */
218 changes_allocated = MAX_RECOG_OPERANDS * 5;
220 changes_allocated *= 2;
222 changes = XRESIZEVEC (change_t, changes, changes_allocated);
225 changes[num_changes].object = object;
226 changes[num_changes].loc = loc;
227 changes[num_changes].old = old;
228 changes[num_changes].unshare = unshare;
230 if (object && !MEM_P (object))
232 /* Set INSN_CODE to force rerecognition of insn. Save old code in
234 changes[num_changes].old_code = INSN_CODE (object);
235 INSN_CODE (object) = -1;
240 /* If we are making a group of changes, return 1. Otherwise, validate the
241 change group we made. */
246 return apply_change_group ();
249 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
253 validate_change (rtx object, rtx *loc, rtx new_rtx, bool in_group)
255 return validate_change_1 (object, loc, new_rtx, in_group, false);
258 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
262 validate_unshare_change (rtx object, rtx *loc, rtx new_rtx, bool in_group)
264 return validate_change_1 (object, loc, new_rtx, in_group, true);
268 /* Keep X canonicalized if some changes have made it non-canonical; only
269 modifies the operands of X, not (for example) its code. Simplifications
270 are not the job of this routine.
272 Return true if anything was changed. */
274 canonicalize_change_group (rtx insn, rtx x)
276 if (COMMUTATIVE_P (x)
277 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
279 /* Oops, the caller has made X no longer canonical.
280 Let's redo the changes in the correct order. */
281 rtx tem = XEXP (x, 0);
282 validate_change (insn, &XEXP (x, 0), XEXP (x, 1), 1);
283 validate_change (insn, &XEXP (x, 1), tem, 1);
291 /* This subroutine of apply_change_group verifies whether the changes to INSN
292 were valid; i.e. whether INSN can still be recognized. */
295 insn_invalid_p (rtx insn)
297 rtx pat = PATTERN (insn);
298 int num_clobbers = 0;
299 /* If we are before reload and the pattern is a SET, see if we can add
301 int icode = recog (pat, insn,
302 (GET_CODE (pat) == SET
303 && ! reload_completed && ! reload_in_progress)
304 ? &num_clobbers : 0);
305 int is_asm = icode < 0 && asm_noperands (PATTERN (insn)) >= 0;
308 /* If this is an asm and the operand aren't legal, then fail. Likewise if
309 this is not an asm and the insn wasn't recognized. */
310 if ((is_asm && ! check_asm_operands (PATTERN (insn)))
311 || (!is_asm && icode < 0))
314 /* If we have to add CLOBBERs, fail if we have to add ones that reference
315 hard registers since our callers can't know if they are live or not.
316 Otherwise, add them. */
317 if (num_clobbers > 0)
321 if (added_clobbers_hard_reg_p (icode))
324 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_clobbers + 1));
325 XVECEXP (newpat, 0, 0) = pat;
326 add_clobbers (newpat, icode);
327 PATTERN (insn) = pat = newpat;
330 /* After reload, verify that all constraints are satisfied. */
331 if (reload_completed)
335 if (! constrain_operands (1))
339 INSN_CODE (insn) = icode;
343 /* Return number of changes made and not validated yet. */
345 num_changes_pending (void)
350 /* Tentatively apply the changes numbered NUM and up.
351 Return 1 if all changes are valid, zero otherwise. */
354 verify_changes (int num)
357 rtx last_validated = NULL_RTX;
359 /* The changes have been applied and all INSN_CODEs have been reset to force
362 The changes are valid if we aren't given an object, or if we are
363 given a MEM and it still is a valid address, or if this is in insn
364 and it is recognized. In the latter case, if reload has completed,
365 we also require that the operands meet the constraints for
368 for (i = num; i < num_changes; i++)
370 rtx object = changes[i].object;
372 /* If there is no object to test or if it is the same as the one we
373 already tested, ignore it. */
374 if (object == 0 || object == last_validated)
379 if (! memory_address_addr_space_p (GET_MODE (object),
381 MEM_ADDR_SPACE (object)))
384 else if (REG_P (changes[i].old)
385 && asm_noperands (PATTERN (object)) > 0
386 && REG_EXPR (changes[i].old) != NULL_TREE
387 && DECL_ASSEMBLER_NAME_SET_P (REG_EXPR (changes[i].old))
388 && DECL_REGISTER (REG_EXPR (changes[i].old)))
390 /* Don't allow changes of hard register operands to inline
391 assemblies if they have been defined as register asm ("x"). */
394 else if (DEBUG_INSN_P (object))
396 else if (insn_invalid_p (object))
398 rtx pat = PATTERN (object);
400 /* Perhaps we couldn't recognize the insn because there were
401 extra CLOBBERs at the end. If so, try to re-recognize
402 without the last CLOBBER (later iterations will cause each of
403 them to be eliminated, in turn). But don't do this if we
404 have an ASM_OPERAND. */
405 if (GET_CODE (pat) == PARALLEL
406 && GET_CODE (XVECEXP (pat, 0, XVECLEN (pat, 0) - 1)) == CLOBBER
407 && asm_noperands (PATTERN (object)) < 0)
411 if (XVECLEN (pat, 0) == 2)
412 newpat = XVECEXP (pat, 0, 0);
418 = gen_rtx_PARALLEL (VOIDmode,
419 rtvec_alloc (XVECLEN (pat, 0) - 1));
420 for (j = 0; j < XVECLEN (newpat, 0); j++)
421 XVECEXP (newpat, 0, j) = XVECEXP (pat, 0, j);
424 /* Add a new change to this group to replace the pattern
425 with this new pattern. Then consider this change
426 as having succeeded. The change we added will
427 cause the entire call to fail if things remain invalid.
429 Note that this can lose if a later change than the one
430 we are processing specified &XVECEXP (PATTERN (object), 0, X)
431 but this shouldn't occur. */
433 validate_change (object, &PATTERN (object), newpat, 1);
436 else if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER
437 || GET_CODE (pat) == VAR_LOCATION)
438 /* If this insn is a CLOBBER or USE, it is always valid, but is
444 last_validated = object;
447 return (i == num_changes);
450 /* A group of changes has previously been issued with validate_change
451 and verified with verify_changes. Call df_insn_rescan for each of
452 the insn changed and clear num_changes. */
455 confirm_change_group (void)
458 rtx last_object = NULL;
460 for (i = 0; i < num_changes; i++)
462 rtx object = changes[i].object;
464 if (changes[i].unshare)
465 *changes[i].loc = copy_rtx (*changes[i].loc);
467 /* Avoid unnecessary rescanning when multiple changes to same instruction
471 if (object != last_object && last_object && INSN_P (last_object))
472 df_insn_rescan (last_object);
473 last_object = object;
477 if (last_object && INSN_P (last_object))
478 df_insn_rescan (last_object);
482 /* Apply a group of changes previously issued with `validate_change'.
483 If all changes are valid, call confirm_change_group and return 1,
484 otherwise, call cancel_changes and return 0. */
487 apply_change_group (void)
489 if (verify_changes (0))
491 confirm_change_group ();
502 /* Return the number of changes so far in the current group. */
505 num_validated_changes (void)
510 /* Retract the changes numbered NUM and up. */
513 cancel_changes (int num)
517 /* Back out all the changes. Do this in the opposite order in which
519 for (i = num_changes - 1; i >= num; i--)
521 *changes[i].loc = changes[i].old;
522 if (changes[i].object && !MEM_P (changes[i].object))
523 INSN_CODE (changes[i].object) = changes[i].old_code;
528 /* A subroutine of validate_replace_rtx_1 that tries to simplify the resulting
532 simplify_while_replacing (rtx *loc, rtx to, rtx object,
533 enum machine_mode op0_mode)
536 enum rtx_code code = GET_CODE (x);
539 if (SWAPPABLE_OPERANDS_P (x)
540 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
542 validate_unshare_change (object, loc,
543 gen_rtx_fmt_ee (COMMUTATIVE_ARITH_P (x) ? code
544 : swap_condition (code),
545 GET_MODE (x), XEXP (x, 1),
554 /* If we have a PLUS whose second operand is now a CONST_INT, use
555 simplify_gen_binary to try to simplify it.
556 ??? We may want later to remove this, once simplification is
557 separated from this function. */
558 if (CONST_INT_P (XEXP (x, 1)) && XEXP (x, 1) == to)
559 validate_change (object, loc,
561 (PLUS, GET_MODE (x), XEXP (x, 0), XEXP (x, 1)), 1);
564 if (CONST_INT_P (XEXP (x, 1))
565 || GET_CODE (XEXP (x, 1)) == CONST_DOUBLE)
566 validate_change (object, loc,
568 (PLUS, GET_MODE (x), XEXP (x, 0),
569 simplify_gen_unary (NEG,
570 GET_MODE (x), XEXP (x, 1),
575 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
577 new_rtx = simplify_gen_unary (code, GET_MODE (x), XEXP (x, 0),
579 /* If any of the above failed, substitute in something that
580 we know won't be recognized. */
582 new_rtx = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
583 validate_change (object, loc, new_rtx, 1);
587 /* All subregs possible to simplify should be simplified. */
588 new_rtx = simplify_subreg (GET_MODE (x), SUBREG_REG (x), op0_mode,
591 /* Subregs of VOIDmode operands are incorrect. */
592 if (!new_rtx && GET_MODE (SUBREG_REG (x)) == VOIDmode)
593 new_rtx = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
595 validate_change (object, loc, new_rtx, 1);
599 /* If we are replacing a register with memory, try to change the memory
600 to be the mode required for memory in extract operations (this isn't
601 likely to be an insertion operation; if it was, nothing bad will
602 happen, we might just fail in some cases). */
604 if (MEM_P (XEXP (x, 0))
605 && CONST_INT_P (XEXP (x, 1))
606 && CONST_INT_P (XEXP (x, 2))
607 && !mode_dependent_address_p (XEXP (XEXP (x, 0), 0))
608 && !MEM_VOLATILE_P (XEXP (x, 0)))
610 enum machine_mode wanted_mode = VOIDmode;
611 enum machine_mode is_mode = GET_MODE (XEXP (x, 0));
612 int pos = INTVAL (XEXP (x, 2));
614 if (GET_CODE (x) == ZERO_EXTRACT)
616 enum machine_mode new_mode
617 = mode_for_extraction (EP_extzv, 1);
618 if (new_mode != MAX_MACHINE_MODE)
619 wanted_mode = new_mode;
621 else if (GET_CODE (x) == SIGN_EXTRACT)
623 enum machine_mode new_mode
624 = mode_for_extraction (EP_extv, 1);
625 if (new_mode != MAX_MACHINE_MODE)
626 wanted_mode = new_mode;
629 /* If we have a narrower mode, we can do something. */
630 if (wanted_mode != VOIDmode
631 && GET_MODE_SIZE (wanted_mode) < GET_MODE_SIZE (is_mode))
633 int offset = pos / BITS_PER_UNIT;
636 /* If the bytes and bits are counted differently, we
637 must adjust the offset. */
638 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN)
640 (GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (wanted_mode) -
643 pos %= GET_MODE_BITSIZE (wanted_mode);
645 newmem = adjust_address_nv (XEXP (x, 0), wanted_mode, offset);
647 validate_change (object, &XEXP (x, 2), GEN_INT (pos), 1);
648 validate_change (object, &XEXP (x, 0), newmem, 1);
659 /* Replace every occurrence of FROM in X with TO. Mark each change with
660 validate_change passing OBJECT. */
663 validate_replace_rtx_1 (rtx *loc, rtx from, rtx to, rtx object,
670 enum machine_mode op0_mode = VOIDmode;
671 int prev_changes = num_changes;
677 fmt = GET_RTX_FORMAT (code);
679 op0_mode = GET_MODE (XEXP (x, 0));
681 /* X matches FROM if it is the same rtx or they are both referring to the
682 same register in the same mode. Avoid calling rtx_equal_p unless the
683 operands look similar. */
686 || (REG_P (x) && REG_P (from)
687 && GET_MODE (x) == GET_MODE (from)
688 && REGNO (x) == REGNO (from))
689 || (GET_CODE (x) == GET_CODE (from) && GET_MODE (x) == GET_MODE (from)
690 && rtx_equal_p (x, from)))
692 validate_unshare_change (object, loc, to, 1);
696 /* Call ourself recursively to perform the replacements.
697 We must not replace inside already replaced expression, otherwise we
698 get infinite recursion for replacements like (reg X)->(subreg (reg X))
699 done by regmove, so we must special case shared ASM_OPERANDS. */
701 if (GET_CODE (x) == PARALLEL)
703 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
705 if (j && GET_CODE (XVECEXP (x, 0, j)) == SET
706 && GET_CODE (SET_SRC (XVECEXP (x, 0, j))) == ASM_OPERANDS)
708 /* Verify that operands are really shared. */
709 gcc_assert (ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (x, 0, 0)))
710 == ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP
712 validate_replace_rtx_1 (&SET_DEST (XVECEXP (x, 0, j)),
713 from, to, object, simplify);
716 validate_replace_rtx_1 (&XVECEXP (x, 0, j), from, to, object,
721 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
724 validate_replace_rtx_1 (&XEXP (x, i), from, to, object, simplify);
725 else if (fmt[i] == 'E')
726 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
727 validate_replace_rtx_1 (&XVECEXP (x, i, j), from, to, object,
731 /* If we didn't substitute, there is nothing more to do. */
732 if (num_changes == prev_changes)
735 /* Allow substituted expression to have different mode. This is used by
736 regmove to change mode of pseudo register. */
737 if (fmt[0] == 'e' && GET_MODE (XEXP (x, 0)) != VOIDmode)
738 op0_mode = GET_MODE (XEXP (x, 0));
740 /* Do changes needed to keep rtx consistent. Don't do any other
741 simplifications, as it is not our job. */
743 simplify_while_replacing (loc, to, object, op0_mode);
746 /* Try replacing every occurrence of FROM in subexpression LOC of INSN
747 with TO. After all changes have been made, validate by seeing
748 if INSN is still valid. */
751 validate_replace_rtx_subexp (rtx from, rtx to, rtx insn, rtx *loc)
753 validate_replace_rtx_1 (loc, from, to, insn, true);
754 return apply_change_group ();
757 /* Try replacing every occurrence of FROM in INSN with TO. After all
758 changes have been made, validate by seeing if INSN is still valid. */
761 validate_replace_rtx (rtx from, rtx to, rtx insn)
763 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn, true);
764 return apply_change_group ();
767 /* Try replacing every occurrence of FROM in WHERE with TO. Assume that WHERE
768 is a part of INSN. After all changes have been made, validate by seeing if
770 validate_replace_rtx (from, to, insn) is equivalent to
771 validate_replace_rtx_part (from, to, &PATTERN (insn), insn). */
774 validate_replace_rtx_part (rtx from, rtx to, rtx *where, rtx insn)
776 validate_replace_rtx_1 (where, from, to, insn, true);
777 return apply_change_group ();
780 /* Same as above, but do not simplify rtx afterwards. */
782 validate_replace_rtx_part_nosimplify (rtx from, rtx to, rtx *where,
785 validate_replace_rtx_1 (where, from, to, insn, false);
786 return apply_change_group ();
790 /* Try replacing every occurrence of FROM in INSN with TO. */
793 validate_replace_rtx_group (rtx from, rtx to, rtx insn)
795 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn, true);
798 /* Function called by note_uses to replace used subexpressions. */
799 struct validate_replace_src_data
801 rtx from; /* Old RTX */
802 rtx to; /* New RTX */
803 rtx insn; /* Insn in which substitution is occurring. */
807 validate_replace_src_1 (rtx *x, void *data)
809 struct validate_replace_src_data *d
810 = (struct validate_replace_src_data *) data;
812 validate_replace_rtx_1 (x, d->from, d->to, d->insn, true);
815 /* Try replacing every occurrence of FROM in INSN with TO, avoiding
819 validate_replace_src_group (rtx from, rtx to, rtx insn)
821 struct validate_replace_src_data d;
826 note_uses (&PATTERN (insn), validate_replace_src_1, &d);
829 /* Try simplify INSN.
830 Invoke simplify_rtx () on every SET_SRC and SET_DEST inside the INSN's
831 pattern and return true if something was simplified. */
834 validate_simplify_insn (rtx insn)
840 pat = PATTERN (insn);
842 if (GET_CODE (pat) == SET)
844 newpat = simplify_rtx (SET_SRC (pat));
845 if (newpat && !rtx_equal_p (SET_SRC (pat), newpat))
846 validate_change (insn, &SET_SRC (pat), newpat, 1);
847 newpat = simplify_rtx (SET_DEST (pat));
848 if (newpat && !rtx_equal_p (SET_DEST (pat), newpat))
849 validate_change (insn, &SET_DEST (pat), newpat, 1);
851 else if (GET_CODE (pat) == PARALLEL)
852 for (i = 0; i < XVECLEN (pat, 0); i++)
854 rtx s = XVECEXP (pat, 0, i);
856 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
858 newpat = simplify_rtx (SET_SRC (s));
859 if (newpat && !rtx_equal_p (SET_SRC (s), newpat))
860 validate_change (insn, &SET_SRC (s), newpat, 1);
861 newpat = simplify_rtx (SET_DEST (s));
862 if (newpat && !rtx_equal_p (SET_DEST (s), newpat))
863 validate_change (insn, &SET_DEST (s), newpat, 1);
866 return ((num_changes_pending () > 0) && (apply_change_group () > 0));
870 /* Return 1 if the insn using CC0 set by INSN does not contain
871 any ordered tests applied to the condition codes.
872 EQ and NE tests do not count. */
875 next_insn_tests_no_inequality (rtx insn)
877 rtx next = next_cc0_user (insn);
879 /* If there is no next insn, we have to take the conservative choice. */
883 return (INSN_P (next)
884 && ! inequality_comparisons_p (PATTERN (next)));
888 /* Return 1 if OP is a valid general operand for machine mode MODE.
889 This is either a register reference, a memory reference,
890 or a constant. In the case of a memory reference, the address
891 is checked for general validity for the target machine.
893 Register and memory references must have mode MODE in order to be valid,
894 but some constants have no machine mode and are valid for any mode.
896 If MODE is VOIDmode, OP is checked for validity for whatever mode
899 The main use of this function is as a predicate in match_operand
900 expressions in the machine description.
902 For an explanation of this function's behavior for registers of
903 class NO_REGS, see the comment for `register_operand'. */
906 general_operand (rtx op, enum machine_mode mode)
908 enum rtx_code code = GET_CODE (op);
910 if (mode == VOIDmode)
911 mode = GET_MODE (op);
913 /* Don't accept CONST_INT or anything similar
914 if the caller wants something floating. */
915 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
916 && GET_MODE_CLASS (mode) != MODE_INT
917 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
922 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op))
926 return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode
928 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
929 && LEGITIMATE_CONSTANT_P (op));
931 /* Except for certain constants with VOIDmode, already checked for,
932 OP's mode must match MODE if MODE specifies a mode. */
934 if (GET_MODE (op) != mode)
939 rtx sub = SUBREG_REG (op);
941 #ifdef INSN_SCHEDULING
942 /* On machines that have insn scheduling, we want all memory
943 reference to be explicit, so outlaw paradoxical SUBREGs.
944 However, we must allow them after reload so that they can
945 get cleaned up by cleanup_subreg_operands. */
946 if (!reload_completed && MEM_P (sub)
947 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (sub)))
950 /* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory
951 may result in incorrect reference. We should simplify all valid
952 subregs of MEM anyway. But allow this after reload because we
953 might be called from cleanup_subreg_operands.
955 ??? This is a kludge. */
956 if (!reload_completed && SUBREG_BYTE (op) != 0
960 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
961 create such rtl, and we must reject it. */
962 if (SCALAR_FLOAT_MODE_P (GET_MODE (op))
963 && GET_MODE_SIZE (GET_MODE (op)) > GET_MODE_SIZE (GET_MODE (sub)))
967 code = GET_CODE (op);
971 /* A register whose class is NO_REGS is not a general operand. */
972 return (REGNO (op) >= FIRST_PSEUDO_REGISTER
973 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS);
977 rtx y = XEXP (op, 0);
979 if (! volatile_ok && MEM_VOLATILE_P (op))
982 /* Use the mem's mode, since it will be reloaded thus. */
983 if (memory_address_addr_space_p (GET_MODE (op), y, MEM_ADDR_SPACE (op)))
990 /* Return 1 if OP is a valid memory address for a memory reference
993 The main use of this function is as a predicate in match_operand
994 expressions in the machine description. */
997 address_operand (rtx op, enum machine_mode mode)
999 return memory_address_p (mode, op);
1002 /* Return 1 if OP is a register reference of mode MODE.
1003 If MODE is VOIDmode, accept a register in any mode.
1005 The main use of this function is as a predicate in match_operand
1006 expressions in the machine description.
1008 As a special exception, registers whose class is NO_REGS are
1009 not accepted by `register_operand'. The reason for this change
1010 is to allow the representation of special architecture artifacts
1011 (such as a condition code register) without extending the rtl
1012 definitions. Since registers of class NO_REGS cannot be used
1013 as registers in any case where register classes are examined,
1014 it is most consistent to keep this function from accepting them. */
1017 register_operand (rtx op, enum machine_mode mode)
1019 if (GET_MODE (op) != mode && mode != VOIDmode)
1022 if (GET_CODE (op) == SUBREG)
1024 rtx sub = SUBREG_REG (op);
1026 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1027 because it is guaranteed to be reloaded into one.
1028 Just make sure the MEM is valid in itself.
1029 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1030 but currently it does result from (SUBREG (REG)...) where the
1031 reg went on the stack.) */
1032 if (! reload_completed && MEM_P (sub))
1033 return general_operand (op, mode);
1035 #ifdef CANNOT_CHANGE_MODE_CLASS
1037 && REGNO (sub) < FIRST_PSEUDO_REGISTER
1038 && REG_CANNOT_CHANGE_MODE_P (REGNO (sub), GET_MODE (sub), mode)
1039 && GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_INT
1040 && GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_FLOAT)
1044 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
1045 create such rtl, and we must reject it. */
1046 if (SCALAR_FLOAT_MODE_P (GET_MODE (op))
1047 && GET_MODE_SIZE (GET_MODE (op)) > GET_MODE_SIZE (GET_MODE (sub)))
1053 /* We don't consider registers whose class is NO_REGS
1054 to be a register operand. */
1056 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1057 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
1060 /* Return 1 for a register in Pmode; ignore the tested mode. */
1063 pmode_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1065 return register_operand (op, Pmode);
1068 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
1069 or a hard register. */
1072 scratch_operand (rtx op, enum machine_mode mode)
1074 if (GET_MODE (op) != mode && mode != VOIDmode)
1077 return (GET_CODE (op) == SCRATCH
1079 && REGNO (op) < FIRST_PSEUDO_REGISTER));
1082 /* Return 1 if OP is a valid immediate operand for mode MODE.
1084 The main use of this function is as a predicate in match_operand
1085 expressions in the machine description. */
1088 immediate_operand (rtx op, enum machine_mode mode)
1090 /* Don't accept CONST_INT or anything similar
1091 if the caller wants something floating. */
1092 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1093 && GET_MODE_CLASS (mode) != MODE_INT
1094 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1097 if (CONST_INT_P (op)
1099 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op))
1102 return (CONSTANT_P (op)
1103 && (GET_MODE (op) == mode || mode == VOIDmode
1104 || GET_MODE (op) == VOIDmode)
1105 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1106 && LEGITIMATE_CONSTANT_P (op));
1109 /* Returns 1 if OP is an operand that is a CONST_INT. */
1112 const_int_operand (rtx op, enum machine_mode mode)
1114 if (!CONST_INT_P (op))
1117 if (mode != VOIDmode
1118 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op))
1124 /* Returns 1 if OP is an operand that is a constant integer or constant
1125 floating-point number. */
1128 const_double_operand (rtx op, enum machine_mode mode)
1130 /* Don't accept CONST_INT or anything similar
1131 if the caller wants something floating. */
1132 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1133 && GET_MODE_CLASS (mode) != MODE_INT
1134 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1137 return ((GET_CODE (op) == CONST_DOUBLE || CONST_INT_P (op))
1138 && (mode == VOIDmode || GET_MODE (op) == mode
1139 || GET_MODE (op) == VOIDmode));
1142 /* Return 1 if OP is a general operand that is not an immediate operand. */
1145 nonimmediate_operand (rtx op, enum machine_mode mode)
1147 return (general_operand (op, mode) && ! CONSTANT_P (op));
1150 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
1153 nonmemory_operand (rtx op, enum machine_mode mode)
1155 if (CONSTANT_P (op))
1157 /* Don't accept CONST_INT or anything similar
1158 if the caller wants something floating. */
1159 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1160 && GET_MODE_CLASS (mode) != MODE_INT
1161 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1164 if (CONST_INT_P (op)
1166 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op))
1169 return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode
1170 || mode == VOIDmode)
1171 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1172 && LEGITIMATE_CONSTANT_P (op));
1175 if (GET_MODE (op) != mode && mode != VOIDmode)
1178 if (GET_CODE (op) == SUBREG)
1180 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1181 because it is guaranteed to be reloaded into one.
1182 Just make sure the MEM is valid in itself.
1183 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1184 but currently it does result from (SUBREG (REG)...) where the
1185 reg went on the stack.) */
1186 if (! reload_completed && MEM_P (SUBREG_REG (op)))
1187 return general_operand (op, mode);
1188 op = SUBREG_REG (op);
1191 /* We don't consider registers whose class is NO_REGS
1192 to be a register operand. */
1194 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1195 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
1198 /* Return 1 if OP is a valid operand that stands for pushing a
1199 value of mode MODE onto the stack.
1201 The main use of this function is as a predicate in match_operand
1202 expressions in the machine description. */
1205 push_operand (rtx op, enum machine_mode mode)
1207 unsigned int rounded_size = GET_MODE_SIZE (mode);
1209 #ifdef PUSH_ROUNDING
1210 rounded_size = PUSH_ROUNDING (rounded_size);
1216 if (mode != VOIDmode && GET_MODE (op) != mode)
1221 if (rounded_size == GET_MODE_SIZE (mode))
1223 if (GET_CODE (op) != STACK_PUSH_CODE)
1228 if (GET_CODE (op) != PRE_MODIFY
1229 || GET_CODE (XEXP (op, 1)) != PLUS
1230 || XEXP (XEXP (op, 1), 0) != XEXP (op, 0)
1231 || !CONST_INT_P (XEXP (XEXP (op, 1), 1))
1232 #ifdef STACK_GROWS_DOWNWARD
1233 || INTVAL (XEXP (XEXP (op, 1), 1)) != - (int) rounded_size
1235 || INTVAL (XEXP (XEXP (op, 1), 1)) != (int) rounded_size
1241 return XEXP (op, 0) == stack_pointer_rtx;
1244 /* Return 1 if OP is a valid operand that stands for popping a
1245 value of mode MODE off the stack.
1247 The main use of this function is as a predicate in match_operand
1248 expressions in the machine description. */
1251 pop_operand (rtx op, enum machine_mode mode)
1256 if (mode != VOIDmode && GET_MODE (op) != mode)
1261 if (GET_CODE (op) != STACK_POP_CODE)
1264 return XEXP (op, 0) == stack_pointer_rtx;
1267 /* Return 1 if ADDR is a valid memory address
1268 for mode MODE in address space AS. */
1271 memory_address_addr_space_p (enum machine_mode mode ATTRIBUTE_UNUSED,
1272 rtx addr, addr_space_t as)
1274 #ifdef GO_IF_LEGITIMATE_ADDRESS
1275 gcc_assert (ADDR_SPACE_GENERIC_P (as));
1276 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
1282 return targetm.addr_space.legitimate_address_p (mode, addr, 0, as);
1286 /* Return 1 if OP is a valid memory reference with mode MODE,
1287 including a valid address.
1289 The main use of this function is as a predicate in match_operand
1290 expressions in the machine description. */
1293 memory_operand (rtx op, enum machine_mode mode)
1297 if (! reload_completed)
1298 /* Note that no SUBREG is a memory operand before end of reload pass,
1299 because (SUBREG (MEM...)) forces reloading into a register. */
1300 return MEM_P (op) && general_operand (op, mode);
1302 if (mode != VOIDmode && GET_MODE (op) != mode)
1306 if (GET_CODE (inner) == SUBREG)
1307 inner = SUBREG_REG (inner);
1309 return (MEM_P (inner) && general_operand (op, mode));
1312 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1313 that is, a memory reference whose address is a general_operand. */
1316 indirect_operand (rtx op, enum machine_mode mode)
1318 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1319 if (! reload_completed
1320 && GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))
1322 int offset = SUBREG_BYTE (op);
1323 rtx inner = SUBREG_REG (op);
1325 if (mode != VOIDmode && GET_MODE (op) != mode)
1328 /* The only way that we can have a general_operand as the resulting
1329 address is if OFFSET is zero and the address already is an operand
1330 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1333 return ((offset == 0 && general_operand (XEXP (inner, 0), Pmode))
1334 || (GET_CODE (XEXP (inner, 0)) == PLUS
1335 && CONST_INT_P (XEXP (XEXP (inner, 0), 1))
1336 && INTVAL (XEXP (XEXP (inner, 0), 1)) == -offset
1337 && general_operand (XEXP (XEXP (inner, 0), 0), Pmode)));
1341 && memory_operand (op, mode)
1342 && general_operand (XEXP (op, 0), Pmode));
1345 /* Return 1 if this is an ordered comparison operator (not including
1346 ORDERED and UNORDERED). */
1349 ordered_comparison_operator (rtx op, enum machine_mode mode)
1351 if (mode != VOIDmode && GET_MODE (op) != mode)
1353 switch (GET_CODE (op))
1371 /* Return 1 if this is a comparison operator. This allows the use of
1372 MATCH_OPERATOR to recognize all the branch insns. */
1375 comparison_operator (rtx op, enum machine_mode mode)
1377 return ((mode == VOIDmode || GET_MODE (op) == mode)
1378 && COMPARISON_P (op));
1381 /* If BODY is an insn body that uses ASM_OPERANDS, return it. */
1384 extract_asm_operands (rtx body)
1387 switch (GET_CODE (body))
1393 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1394 tmp = SET_SRC (body);
1395 if (GET_CODE (tmp) == ASM_OPERANDS)
1400 tmp = XVECEXP (body, 0, 0);
1401 if (GET_CODE (tmp) == ASM_OPERANDS)
1403 if (GET_CODE (tmp) == SET)
1405 tmp = SET_SRC (tmp);
1406 if (GET_CODE (tmp) == ASM_OPERANDS)
1417 /* If BODY is an insn body that uses ASM_OPERANDS,
1418 return the number of operands (both input and output) in the insn.
1419 Otherwise return -1. */
1422 asm_noperands (const_rtx body)
1424 rtx asm_op = extract_asm_operands (CONST_CAST_RTX (body));
1430 if (GET_CODE (body) == SET)
1432 else if (GET_CODE (body) == PARALLEL)
1435 if (GET_CODE (XVECEXP (body, 0, 0)) == SET)
1437 /* Multiple output operands, or 1 output plus some clobbers:
1439 [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1440 /* Count backwards through CLOBBERs to determine number of SETs. */
1441 for (i = XVECLEN (body, 0); i > 0; i--)
1443 if (GET_CODE (XVECEXP (body, 0, i - 1)) == SET)
1445 if (GET_CODE (XVECEXP (body, 0, i - 1)) != CLOBBER)
1449 /* N_SETS is now number of output operands. */
1452 /* Verify that all the SETs we have
1453 came from a single original asm_operands insn
1454 (so that invalid combinations are blocked). */
1455 for (i = 0; i < n_sets; i++)
1457 rtx elt = XVECEXP (body, 0, i);
1458 if (GET_CODE (elt) != SET)
1460 if (GET_CODE (SET_SRC (elt)) != ASM_OPERANDS)
1462 /* If these ASM_OPERANDS rtx's came from different original insns
1463 then they aren't allowed together. */
1464 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt))
1465 != ASM_OPERANDS_INPUT_VEC (asm_op))
1471 /* 0 outputs, but some clobbers:
1472 body is [(asm_operands ...) (clobber (reg ...))...]. */
1473 /* Make sure all the other parallel things really are clobbers. */
1474 for (i = XVECLEN (body, 0) - 1; i > 0; i--)
1475 if (GET_CODE (XVECEXP (body, 0, i)) != CLOBBER)
1480 return (ASM_OPERANDS_INPUT_LENGTH (asm_op)
1481 + ASM_OPERANDS_LABEL_LENGTH (asm_op) + n_sets);
1484 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1485 copy its operands (both input and output) into the vector OPERANDS,
1486 the locations of the operands within the insn into the vector OPERAND_LOCS,
1487 and the constraints for the operands into CONSTRAINTS.
1488 Write the modes of the operands into MODES.
1489 Return the assembler-template.
1491 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1492 we don't store that info. */
1495 decode_asm_operands (rtx body, rtx *operands, rtx **operand_locs,
1496 const char **constraints, enum machine_mode *modes,
1499 int noperands, nbase = 0, n, i;
1502 switch (GET_CODE (body))
1505 /* Zero output asm: BODY is (asm_operands ...). */
1510 /* Single output asm: BODY is (set OUTPUT (asm_operands ...)). */
1511 asmop = SET_SRC (body);
1513 /* The output is in the SET.
1514 Its constraint is in the ASM_OPERANDS itself. */
1516 operands[0] = SET_DEST (body);
1518 operand_locs[0] = &SET_DEST (body);
1520 constraints[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop);
1522 modes[0] = GET_MODE (SET_DEST (body));
1528 int nparallel = XVECLEN (body, 0); /* Includes CLOBBERs. */
1530 asmop = XVECEXP (body, 0, 0);
1531 if (GET_CODE (asmop) == SET)
1533 asmop = SET_SRC (asmop);
1535 /* At least one output, plus some CLOBBERs. The outputs are in
1536 the SETs. Their constraints are in the ASM_OPERANDS itself. */
1537 for (i = 0; i < nparallel; i++)
1539 if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER)
1540 break; /* Past last SET */
1542 operands[i] = SET_DEST (XVECEXP (body, 0, i));
1544 operand_locs[i] = &SET_DEST (XVECEXP (body, 0, i));
1546 constraints[i] = XSTR (SET_SRC (XVECEXP (body, 0, i)), 1);
1548 modes[i] = GET_MODE (SET_DEST (XVECEXP (body, 0, i)));
1559 noperands = (ASM_OPERANDS_INPUT_LENGTH (asmop)
1560 + ASM_OPERANDS_LABEL_LENGTH (asmop) + nbase);
1562 n = ASM_OPERANDS_INPUT_LENGTH (asmop);
1563 for (i = 0; i < n; i++)
1566 operand_locs[nbase + i] = &ASM_OPERANDS_INPUT (asmop, i);
1568 operands[nbase + i] = ASM_OPERANDS_INPUT (asmop, i);
1570 constraints[nbase + i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i);
1572 modes[nbase + i] = ASM_OPERANDS_INPUT_MODE (asmop, i);
1576 n = ASM_OPERANDS_LABEL_LENGTH (asmop);
1577 for (i = 0; i < n; i++)
1580 operand_locs[nbase + i] = &ASM_OPERANDS_LABEL (asmop, i);
1582 operands[nbase + i] = ASM_OPERANDS_LABEL (asmop, i);
1584 constraints[nbase + i] = "";
1586 modes[nbase + i] = Pmode;
1590 *loc = ASM_OPERANDS_SOURCE_LOCATION (asmop);
1592 return ASM_OPERANDS_TEMPLATE (asmop);
1595 /* Check if an asm_operand matches its constraints.
1596 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
1599 asm_operand_ok (rtx op, const char *constraint, const char **constraints)
1603 /* Use constrain_operands after reload. */
1604 gcc_assert (!reload_completed);
1606 /* Empty constraint string is the same as "X,...,X", i.e. X for as
1607 many alternatives as required to match the other operands. */
1608 if (*constraint == '\0')
1613 char c = *constraint;
1630 case '0': case '1': case '2': case '3': case '4':
1631 case '5': case '6': case '7': case '8': case '9':
1632 /* If caller provided constraints pointer, look up
1633 the maching constraint. Otherwise, our caller should have
1634 given us the proper matching constraint, but we can't
1635 actually fail the check if they didn't. Indicate that
1636 results are inconclusive. */
1640 unsigned long match;
1642 match = strtoul (constraint, &end, 10);
1644 result = asm_operand_ok (op, constraints[match], NULL);
1645 constraint = (const char *) end;
1651 while (ISDIGIT (*constraint));
1658 if (address_operand (op, VOIDmode))
1662 case TARGET_MEM_CONSTRAINT:
1663 case 'V': /* non-offsettable */
1664 if (memory_operand (op, VOIDmode))
1668 case 'o': /* offsettable */
1669 if (offsettable_nonstrict_memref_p (op))
1674 /* ??? Before auto-inc-dec, auto inc/dec insns are not supposed to exist,
1675 excepting those that expand_call created. Further, on some
1676 machines which do not have generalized auto inc/dec, an inc/dec
1677 is not a memory_operand.
1679 Match any memory and hope things are resolved after reload. */
1683 || GET_CODE (XEXP (op, 0)) == PRE_DEC
1684 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1691 || GET_CODE (XEXP (op, 0)) == PRE_INC
1692 || GET_CODE (XEXP (op, 0)) == POST_INC))
1698 if (GET_CODE (op) == CONST_DOUBLE
1699 || (GET_CODE (op) == CONST_VECTOR
1700 && GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_FLOAT))
1705 if (GET_CODE (op) == CONST_DOUBLE
1706 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, 'G', constraint))
1710 if (GET_CODE (op) == CONST_DOUBLE
1711 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, 'H', constraint))
1716 if (CONST_INT_P (op)
1717 || (GET_CODE (op) == CONST_DOUBLE
1718 && GET_MODE (op) == VOIDmode))
1723 if (CONSTANT_P (op) && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)))
1728 if (CONST_INT_P (op)
1729 || (GET_CODE (op) == CONST_DOUBLE
1730 && GET_MODE (op) == VOIDmode))
1735 if (CONST_INT_P (op)
1736 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'I', constraint))
1740 if (CONST_INT_P (op)
1741 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'J', constraint))
1745 if (CONST_INT_P (op)
1746 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'K', constraint))
1750 if (CONST_INT_P (op)
1751 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'L', constraint))
1755 if (CONST_INT_P (op)
1756 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'M', constraint))
1760 if (CONST_INT_P (op)
1761 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'N', constraint))
1765 if (CONST_INT_P (op)
1766 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'O', constraint))
1770 if (CONST_INT_P (op)
1771 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'P', constraint))
1780 if (general_operand (op, VOIDmode))
1785 /* For all other letters, we first check for a register class,
1786 otherwise it is an EXTRA_CONSTRAINT. */
1787 if (REG_CLASS_FROM_CONSTRAINT (c, constraint) != NO_REGS)
1790 if (GET_MODE (op) == BLKmode)
1792 if (register_operand (op, VOIDmode))
1795 #ifdef EXTRA_CONSTRAINT_STR
1796 else if (EXTRA_MEMORY_CONSTRAINT (c, constraint))
1797 /* Every memory operand can be reloaded to fit. */
1798 result = result || memory_operand (op, VOIDmode);
1799 else if (EXTRA_ADDRESS_CONSTRAINT (c, constraint))
1800 /* Every address operand can be reloaded to fit. */
1801 result = result || address_operand (op, VOIDmode);
1802 else if (EXTRA_CONSTRAINT_STR (op, c, constraint))
1807 len = CONSTRAINT_LEN (c, constraint);
1810 while (--len && *constraint);
1818 /* Given an rtx *P, if it is a sum containing an integer constant term,
1819 return the location (type rtx *) of the pointer to that constant term.
1820 Otherwise, return a null pointer. */
1823 find_constant_term_loc (rtx *p)
1826 enum rtx_code code = GET_CODE (*p);
1828 /* If *P IS such a constant term, P is its location. */
1830 if (code == CONST_INT || code == SYMBOL_REF || code == LABEL_REF
1834 /* Otherwise, if not a sum, it has no constant term. */
1836 if (GET_CODE (*p) != PLUS)
1839 /* If one of the summands is constant, return its location. */
1841 if (XEXP (*p, 0) && CONSTANT_P (XEXP (*p, 0))
1842 && XEXP (*p, 1) && CONSTANT_P (XEXP (*p, 1)))
1845 /* Otherwise, check each summand for containing a constant term. */
1847 if (XEXP (*p, 0) != 0)
1849 tem = find_constant_term_loc (&XEXP (*p, 0));
1854 if (XEXP (*p, 1) != 0)
1856 tem = find_constant_term_loc (&XEXP (*p, 1));
1864 /* Return 1 if OP is a memory reference
1865 whose address contains no side effects
1866 and remains valid after the addition
1867 of a positive integer less than the
1868 size of the object being referenced.
1870 We assume that the original address is valid and do not check it.
1872 This uses strict_memory_address_p as a subroutine, so
1873 don't use it before reload. */
1876 offsettable_memref_p (rtx op)
1878 return ((MEM_P (op))
1879 && offsettable_address_addr_space_p (1, GET_MODE (op), XEXP (op, 0),
1880 MEM_ADDR_SPACE (op)));
1883 /* Similar, but don't require a strictly valid mem ref:
1884 consider pseudo-regs valid as index or base regs. */
1887 offsettable_nonstrict_memref_p (rtx op)
1889 return ((MEM_P (op))
1890 && offsettable_address_addr_space_p (0, GET_MODE (op), XEXP (op, 0),
1891 MEM_ADDR_SPACE (op)));
1894 /* Return 1 if Y is a memory address which contains no side effects
1895 and would remain valid for address space AS after the addition of
1896 a positive integer less than the size of that mode.
1898 We assume that the original address is valid and do not check it.
1899 We do check that it is valid for narrower modes.
1901 If STRICTP is nonzero, we require a strictly valid address,
1902 for the sake of use in reload.c. */
1905 offsettable_address_addr_space_p (int strictp, enum machine_mode mode, rtx y,
1908 enum rtx_code ycode = GET_CODE (y);
1912 int (*addressp) (enum machine_mode, rtx, addr_space_t) =
1913 (strictp ? strict_memory_address_addr_space_p
1914 : memory_address_addr_space_p);
1915 unsigned int mode_sz = GET_MODE_SIZE (mode);
1917 if (CONSTANT_ADDRESS_P (y))
1920 /* Adjusting an offsettable address involves changing to a narrower mode.
1921 Make sure that's OK. */
1923 if (mode_dependent_address_p (y))
1926 /* ??? How much offset does an offsettable BLKmode reference need?
1927 Clearly that depends on the situation in which it's being used.
1928 However, the current situation in which we test 0xffffffff is
1929 less than ideal. Caveat user. */
1931 mode_sz = BIGGEST_ALIGNMENT / BITS_PER_UNIT;
1933 /* If the expression contains a constant term,
1934 see if it remains valid when max possible offset is added. */
1936 if ((ycode == PLUS) && (y2 = find_constant_term_loc (&y1)))
1941 *y2 = plus_constant (*y2, mode_sz - 1);
1942 /* Use QImode because an odd displacement may be automatically invalid
1943 for any wider mode. But it should be valid for a single byte. */
1944 good = (*addressp) (QImode, y, as);
1946 /* In any case, restore old contents of memory. */
1951 if (GET_RTX_CLASS (ycode) == RTX_AUTOINC)
1954 /* The offset added here is chosen as the maximum offset that
1955 any instruction could need to add when operating on something
1956 of the specified mode. We assume that if Y and Y+c are
1957 valid addresses then so is Y+d for all 0<d<c. adjust_address will
1958 go inside a LO_SUM here, so we do so as well. */
1959 if (GET_CODE (y) == LO_SUM
1961 && mode_sz <= GET_MODE_ALIGNMENT (mode) / BITS_PER_UNIT)
1962 z = gen_rtx_LO_SUM (GET_MODE (y), XEXP (y, 0),
1963 plus_constant (XEXP (y, 1), mode_sz - 1));
1965 z = plus_constant (y, mode_sz - 1);
1967 /* Use QImode because an odd displacement may be automatically invalid
1968 for any wider mode. But it should be valid for a single byte. */
1969 return (*addressp) (QImode, z, as);
1972 /* Return 1 if ADDR is an address-expression whose effect depends
1973 on the mode of the memory reference it is used in.
1975 Autoincrement addressing is a typical example of mode-dependence
1976 because the amount of the increment depends on the mode. */
1979 mode_dependent_address_p (rtx addr)
1981 /* Auto-increment addressing with anything other than post_modify
1982 or pre_modify always introduces a mode dependency. Catch such
1983 cases now instead of deferring to the target. */
1984 if (GET_CODE (addr) == PRE_INC
1985 || GET_CODE (addr) == POST_INC
1986 || GET_CODE (addr) == PRE_DEC
1987 || GET_CODE (addr) == POST_DEC)
1990 GO_IF_MODE_DEPENDENT_ADDRESS (addr, win);
1992 /* Label `win' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */
1993 win: ATTRIBUTE_UNUSED_LABEL
1997 /* Like extract_insn, but save insn extracted and don't extract again, when
1998 called again for the same insn expecting that recog_data still contain the
1999 valid information. This is used primary by gen_attr infrastructure that
2000 often does extract insn again and again. */
2002 extract_insn_cached (rtx insn)
2004 if (recog_data.insn == insn && INSN_CODE (insn) >= 0)
2006 extract_insn (insn);
2007 recog_data.insn = insn;
2010 /* Do cached extract_insn, constrain_operands and complain about failures.
2011 Used by insn_attrtab. */
2013 extract_constrain_insn_cached (rtx insn)
2015 extract_insn_cached (insn);
2016 if (which_alternative == -1
2017 && !constrain_operands (reload_completed))
2018 fatal_insn_not_found (insn);
2021 /* Do cached constrain_operands and complain about failures. */
2023 constrain_operands_cached (int strict)
2025 if (which_alternative == -1)
2026 return constrain_operands (strict);
2031 /* Analyze INSN and fill in recog_data. */
2034 extract_insn (rtx insn)
2039 rtx body = PATTERN (insn);
2041 recog_data.n_operands = 0;
2042 recog_data.n_alternatives = 0;
2043 recog_data.n_dups = 0;
2045 switch (GET_CODE (body))
2056 if (GET_CODE (SET_SRC (body)) == ASM_OPERANDS)
2061 if ((GET_CODE (XVECEXP (body, 0, 0)) == SET
2062 && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS)
2063 || GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS)
2069 recog_data.n_operands = noperands = asm_noperands (body);
2072 /* This insn is an `asm' with operands. */
2074 /* expand_asm_operands makes sure there aren't too many operands. */
2075 gcc_assert (noperands <= MAX_RECOG_OPERANDS);
2077 /* Now get the operand values and constraints out of the insn. */
2078 decode_asm_operands (body, recog_data.operand,
2079 recog_data.operand_loc,
2080 recog_data.constraints,
2081 recog_data.operand_mode, NULL);
2084 const char *p = recog_data.constraints[0];
2085 recog_data.n_alternatives = 1;
2087 recog_data.n_alternatives += (*p++ == ',');
2091 fatal_insn_not_found (insn);
2095 /* Ordinary insn: recognize it, get the operands via insn_extract
2096 and get the constraints. */
2098 icode = recog_memoized (insn);
2100 fatal_insn_not_found (insn);
2102 recog_data.n_operands = noperands = insn_data[icode].n_operands;
2103 recog_data.n_alternatives = insn_data[icode].n_alternatives;
2104 recog_data.n_dups = insn_data[icode].n_dups;
2106 insn_extract (insn);
2108 for (i = 0; i < noperands; i++)
2110 recog_data.constraints[i] = insn_data[icode].operand[i].constraint;
2111 recog_data.operand_mode[i] = insn_data[icode].operand[i].mode;
2112 /* VOIDmode match_operands gets mode from their real operand. */
2113 if (recog_data.operand_mode[i] == VOIDmode)
2114 recog_data.operand_mode[i] = GET_MODE (recog_data.operand[i]);
2117 for (i = 0; i < noperands; i++)
2118 recog_data.operand_type[i]
2119 = (recog_data.constraints[i][0] == '=' ? OP_OUT
2120 : recog_data.constraints[i][0] == '+' ? OP_INOUT
2123 gcc_assert (recog_data.n_alternatives <= MAX_RECOG_ALTERNATIVES);
2125 if (INSN_CODE (insn) < 0)
2126 for (i = 0; i < recog_data.n_alternatives; i++)
2127 recog_data.alternative_enabled_p[i] = true;
2130 recog_data.insn = insn;
2131 for (i = 0; i < recog_data.n_alternatives; i++)
2133 which_alternative = i;
2134 recog_data.alternative_enabled_p[i] = get_attr_enabled (insn);
2138 recog_data.insn = NULL;
2139 which_alternative = -1;
2142 /* After calling extract_insn, you can use this function to extract some
2143 information from the constraint strings into a more usable form.
2144 The collected data is stored in recog_op_alt. */
2146 preprocess_constraints (void)
2150 for (i = 0; i < recog_data.n_operands; i++)
2151 memset (recog_op_alt[i], 0, (recog_data.n_alternatives
2152 * sizeof (struct operand_alternative)));
2154 for (i = 0; i < recog_data.n_operands; i++)
2157 struct operand_alternative *op_alt;
2158 const char *p = recog_data.constraints[i];
2160 op_alt = recog_op_alt[i];
2162 for (j = 0; j < recog_data.n_alternatives; j++)
2164 op_alt[j].cl = NO_REGS;
2165 op_alt[j].constraint = p;
2166 op_alt[j].matches = -1;
2167 op_alt[j].matched = -1;
2169 if (!recog_data.alternative_enabled_p[j])
2171 p = skip_alternative (p);
2175 if (*p == '\0' || *p == ',')
2177 op_alt[j].anything_ok = 1;
2187 while (c != ',' && c != '\0');
2188 if (c == ',' || c == '\0')
2196 case '=': case '+': case '*': case '%':
2197 case 'E': case 'F': case 'G': case 'H':
2198 case 's': case 'i': case 'n':
2199 case 'I': case 'J': case 'K': case 'L':
2200 case 'M': case 'N': case 'O': case 'P':
2201 /* These don't say anything we care about. */
2205 op_alt[j].reject += 6;
2208 op_alt[j].reject += 600;
2211 op_alt[j].earlyclobber = 1;
2214 case '0': case '1': case '2': case '3': case '4':
2215 case '5': case '6': case '7': case '8': case '9':
2218 op_alt[j].matches = strtoul (p, &end, 10);
2219 recog_op_alt[op_alt[j].matches][j].matched = i;
2224 case TARGET_MEM_CONSTRAINT:
2225 op_alt[j].memory_ok = 1;
2228 op_alt[j].decmem_ok = 1;
2231 op_alt[j].incmem_ok = 1;
2234 op_alt[j].nonoffmem_ok = 1;
2237 op_alt[j].offmem_ok = 1;
2240 op_alt[j].anything_ok = 1;
2244 op_alt[j].is_address = 1;
2245 op_alt[j].cl = reg_class_subunion[(int) op_alt[j].cl]
2246 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
2252 reg_class_subunion[(int) op_alt[j].cl][(int) GENERAL_REGS];
2256 if (EXTRA_MEMORY_CONSTRAINT (c, p))
2258 op_alt[j].memory_ok = 1;
2261 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
2263 op_alt[j].is_address = 1;
2265 = (reg_class_subunion
2266 [(int) op_alt[j].cl]
2267 [(int) base_reg_class (VOIDmode, ADDRESS,
2273 = (reg_class_subunion
2274 [(int) op_alt[j].cl]
2275 [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c, p)]);
2278 p += CONSTRAINT_LEN (c, p);
2284 /* Check the operands of an insn against the insn's operand constraints
2285 and return 1 if they are valid.
2286 The information about the insn's operands, constraints, operand modes
2287 etc. is obtained from the global variables set up by extract_insn.
2289 WHICH_ALTERNATIVE is set to a number which indicates which
2290 alternative of constraints was matched: 0 for the first alternative,
2291 1 for the next, etc.
2293 In addition, when two operands are required to match
2294 and it happens that the output operand is (reg) while the
2295 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
2296 make the output operand look like the input.
2297 This is because the output operand is the one the template will print.
2299 This is used in final, just before printing the assembler code and by
2300 the routines that determine an insn's attribute.
2302 If STRICT is a positive nonzero value, it means that we have been
2303 called after reload has been completed. In that case, we must
2304 do all checks strictly. If it is zero, it means that we have been called
2305 before reload has completed. In that case, we first try to see if we can
2306 find an alternative that matches strictly. If not, we try again, this
2307 time assuming that reload will fix up the insn. This provides a "best
2308 guess" for the alternative and is used to compute attributes of insns prior
2309 to reload. A negative value of STRICT is used for this internal call. */
2317 constrain_operands (int strict)
2319 const char *constraints[MAX_RECOG_OPERANDS];
2320 int matching_operands[MAX_RECOG_OPERANDS];
2321 int earlyclobber[MAX_RECOG_OPERANDS];
2324 struct funny_match funny_match[MAX_RECOG_OPERANDS];
2325 int funny_match_index;
2327 which_alternative = 0;
2328 if (recog_data.n_operands == 0 || recog_data.n_alternatives == 0)
2331 for (c = 0; c < recog_data.n_operands; c++)
2333 constraints[c] = recog_data.constraints[c];
2334 matching_operands[c] = -1;
2339 int seen_earlyclobber_at = -1;
2342 funny_match_index = 0;
2344 if (!recog_data.alternative_enabled_p[which_alternative])
2348 for (i = 0; i < recog_data.n_operands; i++)
2349 constraints[i] = skip_alternative (constraints[i]);
2351 which_alternative++;
2355 for (opno = 0; opno < recog_data.n_operands; opno++)
2357 rtx op = recog_data.operand[opno];
2358 enum machine_mode mode = GET_MODE (op);
2359 const char *p = constraints[opno];
2365 earlyclobber[opno] = 0;
2367 /* A unary operator may be accepted by the predicate, but it
2368 is irrelevant for matching constraints. */
2372 if (GET_CODE (op) == SUBREG)
2374 if (REG_P (SUBREG_REG (op))
2375 && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER)
2376 offset = subreg_regno_offset (REGNO (SUBREG_REG (op)),
2377 GET_MODE (SUBREG_REG (op)),
2380 op = SUBREG_REG (op);
2383 /* An empty constraint or empty alternative
2384 allows anything which matched the pattern. */
2385 if (*p == 0 || *p == ',')
2389 switch (c = *p, len = CONSTRAINT_LEN (c, p), c)
2398 case '?': case '!': case '*': case '%':
2403 /* Ignore rest of this alternative as far as
2404 constraint checking is concerned. */
2407 while (*p && *p != ',');
2412 earlyclobber[opno] = 1;
2413 if (seen_earlyclobber_at < 0)
2414 seen_earlyclobber_at = opno;
2417 case '0': case '1': case '2': case '3': case '4':
2418 case '5': case '6': case '7': case '8': case '9':
2420 /* This operand must be the same as a previous one.
2421 This kind of constraint is used for instructions such
2422 as add when they take only two operands.
2424 Note that the lower-numbered operand is passed first.
2426 If we are not testing strictly, assume that this
2427 constraint will be satisfied. */
2432 match = strtoul (p, &end, 10);
2439 rtx op1 = recog_data.operand[match];
2440 rtx op2 = recog_data.operand[opno];
2442 /* A unary operator may be accepted by the predicate,
2443 but it is irrelevant for matching constraints. */
2445 op1 = XEXP (op1, 0);
2447 op2 = XEXP (op2, 0);
2449 val = operands_match_p (op1, op2);
2452 matching_operands[opno] = match;
2453 matching_operands[match] = opno;
2458 /* If output is *x and input is *--x, arrange later
2459 to change the output to *--x as well, since the
2460 output op is the one that will be printed. */
2461 if (val == 2 && strict > 0)
2463 funny_match[funny_match_index].this_op = opno;
2464 funny_match[funny_match_index++].other = match;
2471 /* p is used for address_operands. When we are called by
2472 gen_reload, no one will have checked that the address is
2473 strictly valid, i.e., that all pseudos requiring hard regs
2474 have gotten them. */
2476 || (strict_memory_address_p (recog_data.operand_mode[opno],
2481 /* No need to check general_operand again;
2482 it was done in insn-recog.c. Well, except that reload
2483 doesn't check the validity of its replacements, but
2484 that should only matter when there's a bug. */
2486 /* Anything goes unless it is a REG and really has a hard reg
2487 but the hard reg is not in the class GENERAL_REGS. */
2491 || GENERAL_REGS == ALL_REGS
2492 || (reload_in_progress
2493 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2494 || reg_fits_class_p (op, GENERAL_REGS, offset, mode))
2497 else if (strict < 0 || general_operand (op, mode))
2502 /* This is used for a MATCH_SCRATCH in the cases when
2503 we don't actually need anything. So anything goes
2508 case TARGET_MEM_CONSTRAINT:
2509 /* Memory operands must be valid, to the extent
2510 required by STRICT. */
2514 && !strict_memory_address_addr_space_p
2515 (GET_MODE (op), XEXP (op, 0),
2516 MEM_ADDR_SPACE (op)))
2519 && !memory_address_addr_space_p
2520 (GET_MODE (op), XEXP (op, 0),
2521 MEM_ADDR_SPACE (op)))
2525 /* Before reload, accept what reload can turn into mem. */
2526 else if (strict < 0 && CONSTANT_P (op))
2528 /* During reload, accept a pseudo */
2529 else if (reload_in_progress && REG_P (op)
2530 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2536 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
2537 || GET_CODE (XEXP (op, 0)) == POST_DEC))
2543 && (GET_CODE (XEXP (op, 0)) == PRE_INC
2544 || GET_CODE (XEXP (op, 0)) == POST_INC))
2550 if (GET_CODE (op) == CONST_DOUBLE
2551 || (GET_CODE (op) == CONST_VECTOR
2552 && GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_FLOAT))
2558 if (GET_CODE (op) == CONST_DOUBLE
2559 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, c, p))
2564 if (CONST_INT_P (op)
2565 || (GET_CODE (op) == CONST_DOUBLE
2566 && GET_MODE (op) == VOIDmode))
2569 if (CONSTANT_P (op))
2574 if (CONST_INT_P (op)
2575 || (GET_CODE (op) == CONST_DOUBLE
2576 && GET_MODE (op) == VOIDmode))
2588 if (CONST_INT_P (op)
2589 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), c, p))
2595 && ((strict > 0 && ! offsettable_memref_p (op))
2597 && !(CONSTANT_P (op) || MEM_P (op)))
2598 || (reload_in_progress
2600 && REGNO (op) >= FIRST_PSEUDO_REGISTER))))
2605 if ((strict > 0 && offsettable_memref_p (op))
2606 || (strict == 0 && offsettable_nonstrict_memref_p (op))
2607 /* Before reload, accept what reload can handle. */
2609 && (CONSTANT_P (op) || MEM_P (op)))
2610 /* During reload, accept a pseudo */
2611 || (reload_in_progress && REG_P (op)
2612 && REGNO (op) >= FIRST_PSEUDO_REGISTER))
2621 ? GENERAL_REGS : REG_CLASS_FROM_CONSTRAINT (c, p));
2627 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2628 || (strict == 0 && GET_CODE (op) == SCRATCH)
2630 && reg_fits_class_p (op, cl, offset, mode)))
2633 #ifdef EXTRA_CONSTRAINT_STR
2634 else if (EXTRA_CONSTRAINT_STR (op, c, p))
2637 else if (EXTRA_MEMORY_CONSTRAINT (c, p)
2638 /* Every memory operand can be reloaded to fit. */
2639 && ((strict < 0 && MEM_P (op))
2640 /* Before reload, accept what reload can turn
2642 || (strict < 0 && CONSTANT_P (op))
2643 /* During reload, accept a pseudo */
2644 || (reload_in_progress && REG_P (op)
2645 && REGNO (op) >= FIRST_PSEUDO_REGISTER)))
2647 else if (EXTRA_ADDRESS_CONSTRAINT (c, p)
2648 /* Every address operand can be reloaded to fit. */
2655 while (p += len, c);
2657 constraints[opno] = p;
2658 /* If this operand did not win somehow,
2659 this alternative loses. */
2663 /* This alternative won; the operands are ok.
2664 Change whichever operands this alternative says to change. */
2669 /* See if any earlyclobber operand conflicts with some other
2672 if (strict > 0 && seen_earlyclobber_at >= 0)
2673 for (eopno = seen_earlyclobber_at;
2674 eopno < recog_data.n_operands;
2676 /* Ignore earlyclobber operands now in memory,
2677 because we would often report failure when we have
2678 two memory operands, one of which was formerly a REG. */
2679 if (earlyclobber[eopno]
2680 && REG_P (recog_data.operand[eopno]))
2681 for (opno = 0; opno < recog_data.n_operands; opno++)
2682 if ((MEM_P (recog_data.operand[opno])
2683 || recog_data.operand_type[opno] != OP_OUT)
2685 /* Ignore things like match_operator operands. */
2686 && *recog_data.constraints[opno] != 0
2687 && ! (matching_operands[opno] == eopno
2688 && operands_match_p (recog_data.operand[opno],
2689 recog_data.operand[eopno]))
2690 && ! safe_from_earlyclobber (recog_data.operand[opno],
2691 recog_data.operand[eopno]))
2696 while (--funny_match_index >= 0)
2698 recog_data.operand[funny_match[funny_match_index].other]
2699 = recog_data.operand[funny_match[funny_match_index].this_op];
2706 which_alternative++;
2708 while (which_alternative < recog_data.n_alternatives);
2710 which_alternative = -1;
2711 /* If we are about to reject this, but we are not to test strictly,
2712 try a very loose test. Only return failure if it fails also. */
2714 return constrain_operands (-1);
2719 /* Return 1 iff OPERAND (assumed to be a REG rtx)
2720 is a hard reg in class CLASS when its regno is offset by OFFSET
2721 and changed to mode MODE.
2722 If REG occupies multiple hard regs, all of them must be in CLASS. */
2725 reg_fits_class_p (rtx operand, enum reg_class cl, int offset,
2726 enum machine_mode mode)
2728 int regno = REGNO (operand);
2733 return (regno < FIRST_PSEUDO_REGISTER
2734 && in_hard_reg_set_p (reg_class_contents[(int) cl],
2735 mode, regno + offset));
2738 /* Split single instruction. Helper function for split_all_insns and
2739 split_all_insns_noflow. Return last insn in the sequence if successful,
2740 or NULL if unsuccessful. */
2743 split_insn (rtx insn)
2745 /* Split insns here to get max fine-grain parallelism. */
2746 rtx first = PREV_INSN (insn);
2747 rtx last = try_split (PATTERN (insn), insn, 1);
2748 rtx insn_set, last_set, note;
2753 /* If the original instruction was a single set that was known to be
2754 equivalent to a constant, see if we can say the same about the last
2755 instruction in the split sequence. The two instructions must set
2756 the same destination. */
2757 insn_set = single_set (insn);
2760 last_set = single_set (last);
2761 if (last_set && rtx_equal_p (SET_DEST (last_set), SET_DEST (insn_set)))
2763 note = find_reg_equal_equiv_note (insn);
2764 if (note && CONSTANT_P (XEXP (note, 0)))
2765 set_unique_reg_note (last, REG_EQUAL, XEXP (note, 0));
2766 else if (CONSTANT_P (SET_SRC (insn_set)))
2767 set_unique_reg_note (last, REG_EQUAL, SET_SRC (insn_set));
2771 /* try_split returns the NOTE that INSN became. */
2772 SET_INSN_DELETED (insn);
2774 /* ??? Coddle to md files that generate subregs in post-reload
2775 splitters instead of computing the proper hard register. */
2776 if (reload_completed && first != last)
2778 first = NEXT_INSN (first);
2782 cleanup_subreg_operands (first);
2785 first = NEXT_INSN (first);
2792 /* Split all insns in the function. If UPD_LIFE, update life info after. */
2795 split_all_insns (void)
2801 blocks = sbitmap_alloc (last_basic_block);
2802 sbitmap_zero (blocks);
2805 FOR_EACH_BB_REVERSE (bb)
2808 bool finish = false;
2810 rtl_profile_for_bb (bb);
2811 for (insn = BB_HEAD (bb); !finish ; insn = next)
2813 /* Can't use `next_real_insn' because that might go across
2814 CODE_LABELS and short-out basic blocks. */
2815 next = NEXT_INSN (insn);
2816 finish = (insn == BB_END (bb));
2819 rtx set = single_set (insn);
2821 /* Don't split no-op move insns. These should silently
2822 disappear later in final. Splitting such insns would
2823 break the code that handles LIBCALL blocks. */
2824 if (set && set_noop_p (set))
2826 /* Nops get in the way while scheduling, so delete them
2827 now if register allocation has already been done. It
2828 is too risky to try to do this before register
2829 allocation, and there are unlikely to be very many
2830 nops then anyways. */
2831 if (reload_completed)
2832 delete_insn_and_edges (insn);
2836 rtx last = split_insn (insn);
2839 /* The split sequence may include barrier, but the
2840 BB boundary we are interested in will be set to
2843 while (BARRIER_P (last))
2844 last = PREV_INSN (last);
2845 SET_BIT (blocks, bb->index);
2853 default_rtl_profile ();
2855 find_many_sub_basic_blocks (blocks);
2857 #ifdef ENABLE_CHECKING
2858 verify_flow_info ();
2861 sbitmap_free (blocks);
2864 /* Same as split_all_insns, but do not expect CFG to be available.
2865 Used by machine dependent reorg passes. */
2868 split_all_insns_noflow (void)
2872 for (insn = get_insns (); insn; insn = next)
2874 next = NEXT_INSN (insn);
2877 /* Don't split no-op move insns. These should silently
2878 disappear later in final. Splitting such insns would
2879 break the code that handles LIBCALL blocks. */
2880 rtx set = single_set (insn);
2881 if (set && set_noop_p (set))
2883 /* Nops get in the way while scheduling, so delete them
2884 now if register allocation has already been done. It
2885 is too risky to try to do this before register
2886 allocation, and there are unlikely to be very many
2889 ??? Should we use delete_insn when the CFG isn't valid? */
2890 if (reload_completed)
2891 delete_insn_and_edges (insn);
2900 #ifdef HAVE_peephole2
2901 struct peep2_insn_data
2907 static struct peep2_insn_data peep2_insn_data[MAX_INSNS_PER_PEEP2 + 1];
2908 static int peep2_current;
2909 /* The number of instructions available to match a peep2. */
2910 int peep2_current_count;
2912 /* A non-insn marker indicating the last insn of the block.
2913 The live_before regset for this element is correct, indicating
2914 DF_LIVE_OUT for the block. */
2915 #define PEEP2_EOB pc_rtx
2917 /* Return the Nth non-note insn after `current', or return NULL_RTX if it
2918 does not exist. Used by the recognizer to find the next insn to match
2919 in a multi-insn pattern. */
2922 peep2_next_insn (int n)
2924 gcc_assert (n <= peep2_current_count);
2927 if (n >= MAX_INSNS_PER_PEEP2 + 1)
2928 n -= MAX_INSNS_PER_PEEP2 + 1;
2930 return peep2_insn_data[n].insn;
2933 /* Return true if REGNO is dead before the Nth non-note insn
2937 peep2_regno_dead_p (int ofs, int regno)
2939 gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1);
2941 ofs += peep2_current;
2942 if (ofs >= MAX_INSNS_PER_PEEP2 + 1)
2943 ofs -= MAX_INSNS_PER_PEEP2 + 1;
2945 gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX);
2947 return ! REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno);
2950 /* Similarly for a REG. */
2953 peep2_reg_dead_p (int ofs, rtx reg)
2957 gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1);
2959 ofs += peep2_current;
2960 if (ofs >= MAX_INSNS_PER_PEEP2 + 1)
2961 ofs -= MAX_INSNS_PER_PEEP2 + 1;
2963 gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX);
2965 regno = REGNO (reg);
2966 n = hard_regno_nregs[regno][GET_MODE (reg)];
2968 if (REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno + n))
2973 /* Try to find a hard register of mode MODE, matching the register class in
2974 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
2975 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
2976 in which case the only condition is that the register must be available
2977 before CURRENT_INSN.
2978 Registers that already have bits set in REG_SET will not be considered.
2980 If an appropriate register is available, it will be returned and the
2981 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
2985 peep2_find_free_register (int from, int to, const char *class_str,
2986 enum machine_mode mode, HARD_REG_SET *reg_set)
2988 static int search_ofs;
2993 gcc_assert (from < MAX_INSNS_PER_PEEP2 + 1);
2994 gcc_assert (to < MAX_INSNS_PER_PEEP2 + 1);
2996 from += peep2_current;
2997 if (from >= MAX_INSNS_PER_PEEP2 + 1)
2998 from -= MAX_INSNS_PER_PEEP2 + 1;
2999 to += peep2_current;
3000 if (to >= MAX_INSNS_PER_PEEP2 + 1)
3001 to -= MAX_INSNS_PER_PEEP2 + 1;
3003 gcc_assert (peep2_insn_data[from].insn != NULL_RTX);
3004 REG_SET_TO_HARD_REG_SET (live, peep2_insn_data[from].live_before);
3008 HARD_REG_SET this_live;
3010 if (++from >= MAX_INSNS_PER_PEEP2 + 1)
3012 gcc_assert (peep2_insn_data[from].insn != NULL_RTX);
3013 REG_SET_TO_HARD_REG_SET (this_live, peep2_insn_data[from].live_before);
3014 IOR_HARD_REG_SET (live, this_live);
3017 cl = (class_str[0] == 'r' ? GENERAL_REGS
3018 : REG_CLASS_FROM_CONSTRAINT (class_str[0], class_str));
3020 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3022 int raw_regno, regno, success, j;
3024 /* Distribute the free registers as much as possible. */
3025 raw_regno = search_ofs + i;
3026 if (raw_regno >= FIRST_PSEUDO_REGISTER)
3027 raw_regno -= FIRST_PSEUDO_REGISTER;
3028 #ifdef REG_ALLOC_ORDER
3029 regno = reg_alloc_order[raw_regno];
3034 /* Don't allocate fixed registers. */
3035 if (fixed_regs[regno])
3037 /* Don't allocate global registers. */
3038 if (global_regs[regno])
3040 /* Make sure the register is of the right class. */
3041 if (! TEST_HARD_REG_BIT (reg_class_contents[cl], regno))
3043 /* And can support the mode we need. */
3044 if (! HARD_REGNO_MODE_OK (regno, mode))
3046 /* And that we don't create an extra save/restore. */
3047 if (! call_used_regs[regno] && ! df_regs_ever_live_p (regno))
3049 if (! targetm.hard_regno_scratch_ok (regno))
3052 /* And we don't clobber traceback for noreturn functions. */
3053 if ((regno == FRAME_POINTER_REGNUM || regno == HARD_FRAME_POINTER_REGNUM)
3054 && (! reload_completed || frame_pointer_needed))
3058 for (j = hard_regno_nregs[regno][mode] - 1; j >= 0; j--)
3060 if (TEST_HARD_REG_BIT (*reg_set, regno + j)
3061 || TEST_HARD_REG_BIT (live, regno + j))
3069 add_to_hard_reg_set (reg_set, mode, regno);
3071 /* Start the next search with the next register. */
3072 if (++raw_regno >= FIRST_PSEUDO_REGISTER)
3074 search_ofs = raw_regno;
3076 return gen_rtx_REG (mode, regno);
3084 /* Forget all currently tracked instructions, only remember current
3088 peep2_reinit_state (regset live)
3092 /* Indicate that all slots except the last holds invalid data. */
3093 for (i = 0; i < MAX_INSNS_PER_PEEP2; ++i)
3094 peep2_insn_data[i].insn = NULL_RTX;
3095 peep2_current_count = 0;
3097 /* Indicate that the last slot contains live_after data. */
3098 peep2_insn_data[MAX_INSNS_PER_PEEP2].insn = PEEP2_EOB;
3099 peep2_current = MAX_INSNS_PER_PEEP2;
3101 COPY_REG_SET (peep2_insn_data[MAX_INSNS_PER_PEEP2].live_before, live);
3104 /* Perform the peephole2 optimization pass. */
3107 peephole2_optimize (void)
3113 bool do_cleanup_cfg = false;
3114 bool do_rebuild_jump_labels = false;
3116 df_set_flags (DF_LR_RUN_DCE);
3119 /* Initialize the regsets we're going to use. */
3120 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
3121 peep2_insn_data[i].live_before = BITMAP_ALLOC (®_obstack);
3122 live = BITMAP_ALLOC (®_obstack);
3124 FOR_EACH_BB_REVERSE (bb)
3126 rtl_profile_for_bb (bb);
3128 /* Start up propagation. */
3129 bitmap_copy (live, DF_LR_OUT (bb));
3130 df_simulate_initialize_backwards (bb, live);
3131 peep2_reinit_state (live);
3133 for (insn = BB_END (bb); ; insn = prev)
3135 prev = PREV_INSN (insn);
3136 if (NONDEBUG_INSN_P (insn))
3138 rtx attempt, before_try, x;
3141 bool was_call = false;
3143 /* Record this insn. */
3144 if (--peep2_current < 0)
3145 peep2_current = MAX_INSNS_PER_PEEP2;
3146 if (peep2_current_count < MAX_INSNS_PER_PEEP2
3147 && peep2_insn_data[peep2_current].insn == NULL_RTX)
3148 peep2_current_count++;
3149 peep2_insn_data[peep2_current].insn = insn;
3150 df_simulate_one_insn_backwards (bb, insn, live);
3151 COPY_REG_SET (peep2_insn_data[peep2_current].live_before, live);
3153 if (RTX_FRAME_RELATED_P (insn))
3155 /* If an insn has RTX_FRAME_RELATED_P set, peephole
3156 substitution would lose the
3157 REG_FRAME_RELATED_EXPR that is attached. */
3158 peep2_reinit_state (live);
3162 /* Match the peephole. */
3163 attempt = peephole2_insns (PATTERN (insn), insn, &match_len);
3165 if (attempt != NULL)
3167 /* If we are splitting a CALL_INSN, look for the CALL_INSN
3168 in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other
3169 cfg-related call notes. */
3170 for (i = 0; i <= match_len; ++i)
3173 rtx old_insn, new_insn, note;
3175 j = i + peep2_current;
3176 if (j >= MAX_INSNS_PER_PEEP2 + 1)
3177 j -= MAX_INSNS_PER_PEEP2 + 1;
3178 old_insn = peep2_insn_data[j].insn;
3179 if (!CALL_P (old_insn))
3184 while (new_insn != NULL_RTX)
3186 if (CALL_P (new_insn))
3188 new_insn = NEXT_INSN (new_insn);
3191 gcc_assert (new_insn != NULL_RTX);
3193 CALL_INSN_FUNCTION_USAGE (new_insn)
3194 = CALL_INSN_FUNCTION_USAGE (old_insn);
3196 for (note = REG_NOTES (old_insn);
3198 note = XEXP (note, 1))
3199 switch (REG_NOTE_KIND (note))
3203 add_reg_note (new_insn, REG_NOTE_KIND (note),
3207 /* Discard all other reg notes. */
3211 /* Croak if there is another call in the sequence. */
3212 while (++i <= match_len)
3214 j = i + peep2_current;
3215 if (j >= MAX_INSNS_PER_PEEP2 + 1)
3216 j -= MAX_INSNS_PER_PEEP2 + 1;
3217 old_insn = peep2_insn_data[j].insn;
3218 gcc_assert (!CALL_P (old_insn));
3223 i = match_len + peep2_current;
3224 if (i >= MAX_INSNS_PER_PEEP2 + 1)
3225 i -= MAX_INSNS_PER_PEEP2 + 1;
3227 note = find_reg_note (peep2_insn_data[i].insn,
3228 REG_EH_REGION, NULL_RTX);
3230 /* Replace the old sequence with the new. */
3231 attempt = emit_insn_after_setloc (attempt,
3232 peep2_insn_data[i].insn,
3233 INSN_LOCATOR (peep2_insn_data[i].insn));
3234 before_try = PREV_INSN (insn);
3235 delete_insn_chain (insn, peep2_insn_data[i].insn, false);
3237 /* Re-insert the EH_REGION notes. */
3238 if (note || (was_call && nonlocal_goto_handler_labels))
3243 FOR_EACH_EDGE (eh_edge, ei, bb->succs)
3244 if (eh_edge->flags & (EDGE_EH | EDGE_ABNORMAL_CALL))
3248 copy_reg_eh_region_note_backward (note, attempt,
3252 for (x = attempt ; x != before_try ; x = PREV_INSN (x))
3253 if (x != BB_END (bb)
3254 && (can_throw_internal (x)
3255 || can_nonlocal_goto (x)))
3260 nfte = split_block (bb, x);
3261 flags = (eh_edge->flags
3262 & (EDGE_EH | EDGE_ABNORMAL));
3264 flags |= EDGE_ABNORMAL_CALL;
3265 nehe = make_edge (nfte->src, eh_edge->dest,
3268 nehe->probability = eh_edge->probability;
3270 = REG_BR_PROB_BASE - nehe->probability;
3272 do_cleanup_cfg |= purge_dead_edges (nfte->dest);
3277 /* Converting possibly trapping insn to non-trapping is
3278 possible. Zap dummy outgoing edges. */
3279 do_cleanup_cfg |= purge_dead_edges (bb);
3282 if (targetm.have_conditional_execution ())
3284 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
3285 peep2_insn_data[i].insn = NULL_RTX;
3286 peep2_insn_data[peep2_current].insn = PEEP2_EOB;
3287 peep2_current_count = 0;
3291 /* Back up lifetime information past the end of the
3292 newly created sequence. */
3293 if (++i >= MAX_INSNS_PER_PEEP2 + 1)
3295 bitmap_copy (live, peep2_insn_data[i].live_before);
3297 /* Update life information for the new sequence. */
3304 i = MAX_INSNS_PER_PEEP2;
3305 if (peep2_current_count < MAX_INSNS_PER_PEEP2
3306 && peep2_insn_data[i].insn == NULL_RTX)
3307 peep2_current_count++;
3308 peep2_insn_data[i].insn = x;
3310 df_simulate_one_insn_backwards (bb, x, live);
3311 bitmap_copy (peep2_insn_data[i].live_before,
3321 /* If we generated a jump instruction, it won't have
3322 JUMP_LABEL set. Recompute after we're done. */
3323 for (x = attempt; x != before_try; x = PREV_INSN (x))
3326 do_rebuild_jump_labels = true;
3332 if (insn == BB_HEAD (bb))
3337 default_rtl_profile ();
3338 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
3339 BITMAP_FREE (peep2_insn_data[i].live_before);
3341 if (do_rebuild_jump_labels)
3342 rebuild_jump_labels (get_insns ());
3344 #endif /* HAVE_peephole2 */
3346 /* Common predicates for use with define_bypass. */
3348 /* True if the dependency between OUT_INSN and IN_INSN is on the store
3349 data not the address operand(s) of the store. IN_INSN and OUT_INSN
3350 must be either a single_set or a PARALLEL with SETs inside. */
3353 store_data_bypass_p (rtx out_insn, rtx in_insn)
3355 rtx out_set, in_set;
3356 rtx out_pat, in_pat;
3357 rtx out_exp, in_exp;
3360 in_set = single_set (in_insn);
3363 if (!MEM_P (SET_DEST (in_set)))
3366 out_set = single_set (out_insn);
3369 if (reg_mentioned_p (SET_DEST (out_set), SET_DEST (in_set)))
3374 out_pat = PATTERN (out_insn);
3376 if (GET_CODE (out_pat) != PARALLEL)
3379 for (i = 0; i < XVECLEN (out_pat, 0); i++)
3381 out_exp = XVECEXP (out_pat, 0, i);
3383 if (GET_CODE (out_exp) == CLOBBER)
3386 gcc_assert (GET_CODE (out_exp) == SET);
3388 if (reg_mentioned_p (SET_DEST (out_exp), SET_DEST (in_set)))
3395 in_pat = PATTERN (in_insn);
3396 gcc_assert (GET_CODE (in_pat) == PARALLEL);
3398 for (i = 0; i < XVECLEN (in_pat, 0); i++)
3400 in_exp = XVECEXP (in_pat, 0, i);
3402 if (GET_CODE (in_exp) == CLOBBER)
3405 gcc_assert (GET_CODE (in_exp) == SET);
3407 if (!MEM_P (SET_DEST (in_exp)))
3410 out_set = single_set (out_insn);
3413 if (reg_mentioned_p (SET_DEST (out_set), SET_DEST (in_exp)))
3418 out_pat = PATTERN (out_insn);
3419 gcc_assert (GET_CODE (out_pat) == PARALLEL);
3421 for (j = 0; j < XVECLEN (out_pat, 0); j++)
3423 out_exp = XVECEXP (out_pat, 0, j);
3425 if (GET_CODE (out_exp) == CLOBBER)
3428 gcc_assert (GET_CODE (out_exp) == SET);
3430 if (reg_mentioned_p (SET_DEST (out_exp), SET_DEST (in_exp)))
3440 /* True if the dependency between OUT_INSN and IN_INSN is in the IF_THEN_ELSE
3441 condition, and not the THEN or ELSE branch. OUT_INSN may be either a single
3442 or multiple set; IN_INSN should be single_set for truth, but for convenience
3443 of insn categorization may be any JUMP or CALL insn. */
3446 if_test_bypass_p (rtx out_insn, rtx in_insn)
3448 rtx out_set, in_set;
3450 in_set = single_set (in_insn);
3453 gcc_assert (JUMP_P (in_insn) || CALL_P (in_insn));
3457 if (GET_CODE (SET_SRC (in_set)) != IF_THEN_ELSE)
3459 in_set = SET_SRC (in_set);
3461 out_set = single_set (out_insn);
3464 if (reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 1))
3465 || reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 2)))
3473 out_pat = PATTERN (out_insn);
3474 gcc_assert (GET_CODE (out_pat) == PARALLEL);
3476 for (i = 0; i < XVECLEN (out_pat, 0); i++)
3478 rtx exp = XVECEXP (out_pat, 0, i);
3480 if (GET_CODE (exp) == CLOBBER)
3483 gcc_assert (GET_CODE (exp) == SET);
3485 if (reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 1))
3486 || reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 2)))
3495 gate_handle_peephole2 (void)
3497 return (optimize > 0 && flag_peephole2);
3501 rest_of_handle_peephole2 (void)
3503 #ifdef HAVE_peephole2
3504 peephole2_optimize ();
3509 struct rtl_opt_pass pass_peephole2 =
3513 "peephole2", /* name */
3514 gate_handle_peephole2, /* gate */
3515 rest_of_handle_peephole2, /* execute */
3518 0, /* static_pass_number */
3519 TV_PEEPHOLE2, /* tv_id */
3520 0, /* properties_required */
3521 0, /* properties_provided */
3522 0, /* properties_destroyed */
3523 0, /* todo_flags_start */
3524 TODO_df_finish | TODO_verify_rtl_sharing |
3525 TODO_dump_func /* todo_flags_finish */
3530 rest_of_handle_split_all_insns (void)
3536 struct rtl_opt_pass pass_split_all_insns =
3540 "split1", /* name */
3542 rest_of_handle_split_all_insns, /* execute */
3545 0, /* static_pass_number */
3546 TV_NONE, /* tv_id */
3547 0, /* properties_required */
3548 0, /* properties_provided */
3549 0, /* properties_destroyed */
3550 0, /* todo_flags_start */
3551 TODO_dump_func /* todo_flags_finish */
3556 rest_of_handle_split_after_reload (void)
3558 /* If optimizing, then go ahead and split insns now. */
3566 struct rtl_opt_pass pass_split_after_reload =
3570 "split2", /* name */
3572 rest_of_handle_split_after_reload, /* execute */
3575 0, /* static_pass_number */
3576 TV_NONE, /* tv_id */
3577 0, /* properties_required */
3578 0, /* properties_provided */
3579 0, /* properties_destroyed */
3580 0, /* todo_flags_start */
3581 TODO_dump_func /* todo_flags_finish */
3586 gate_handle_split_before_regstack (void)
3588 #if defined (HAVE_ATTR_length) && defined (STACK_REGS)
3589 /* If flow2 creates new instructions which need splitting
3590 and scheduling after reload is not done, they might not be
3591 split until final which doesn't allow splitting
3592 if HAVE_ATTR_length. */
3593 # ifdef INSN_SCHEDULING
3594 return (optimize && !flag_schedule_insns_after_reload);
3604 rest_of_handle_split_before_regstack (void)
3610 struct rtl_opt_pass pass_split_before_regstack =
3614 "split3", /* name */
3615 gate_handle_split_before_regstack, /* gate */
3616 rest_of_handle_split_before_regstack, /* execute */
3619 0, /* static_pass_number */
3620 TV_NONE, /* tv_id */
3621 0, /* properties_required */
3622 0, /* properties_provided */
3623 0, /* properties_destroyed */
3624 0, /* todo_flags_start */
3625 TODO_dump_func /* todo_flags_finish */
3630 gate_handle_split_before_sched2 (void)
3632 #ifdef INSN_SCHEDULING
3633 return optimize > 0 && flag_schedule_insns_after_reload;
3640 rest_of_handle_split_before_sched2 (void)
3642 #ifdef INSN_SCHEDULING
3648 struct rtl_opt_pass pass_split_before_sched2 =
3652 "split4", /* name */
3653 gate_handle_split_before_sched2, /* gate */
3654 rest_of_handle_split_before_sched2, /* execute */
3657 0, /* static_pass_number */
3658 TV_NONE, /* tv_id */
3659 0, /* properties_required */
3660 0, /* properties_provided */
3661 0, /* properties_destroyed */
3662 0, /* todo_flags_start */
3664 TODO_dump_func /* todo_flags_finish */
3668 /* The placement of the splitting that we do for shorten_branches
3669 depends on whether regstack is used by the target or not. */
3671 gate_do_final_split (void)
3673 #if defined (HAVE_ATTR_length) && !defined (STACK_REGS)
3680 struct rtl_opt_pass pass_split_for_shorten_branches =
3684 "split5", /* name */
3685 gate_do_final_split, /* gate */
3686 split_all_insns_noflow, /* execute */
3689 0, /* static_pass_number */
3690 TV_NONE, /* tv_id */
3691 0, /* properties_required */
3692 0, /* properties_provided */
3693 0, /* properties_destroyed */
3694 0, /* todo_flags_start */
3695 TODO_dump_func | TODO_verify_rtl_sharing /* todo_flags_finish */