1 /* Swing Modulo Scheduling implementation.
2 Copyright (C) 2004, 2005, 2006, 2007
3 Free Software Foundation, Inc.
4 Contributed by Ayal Zaks and Mustafa Hagog <zaks,mustafa@il.ibm.com>
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
30 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "insn-attr.h"
39 #include "sched-int.h"
41 #include "cfglayout.h"
49 #include "tree-pass.h"
51 #ifdef INSN_SCHEDULING
53 /* This file contains the implementation of the Swing Modulo Scheduler,
54 described in the following references:
55 [1] J. Llosa, A. Gonzalez, E. Ayguade, M. Valero., and J. Eckhardt.
56 Lifetime--sensitive modulo scheduling in a production environment.
57 IEEE Trans. on Comps., 50(3), March 2001
58 [2] J. Llosa, A. Gonzalez, E. Ayguade, and M. Valero.
59 Swing Modulo Scheduling: A Lifetime Sensitive Approach.
60 PACT '96 , pages 80-87, October 1996 (Boston - Massachusetts - USA).
62 The basic structure is:
63 1. Build a data-dependence graph (DDG) for each loop.
64 2. Use the DDG to order the insns of a loop (not in topological order
65 necessarily, but rather) trying to place each insn after all its
66 predecessors _or_ after all its successors.
67 3. Compute MII: a lower bound on the number of cycles to schedule the loop.
68 4. Use the ordering to perform list-scheduling of the loop:
69 1. Set II = MII. We will try to schedule the loop within II cycles.
70 2. Try to schedule the insns one by one according to the ordering.
71 For each insn compute an interval of cycles by considering already-
72 scheduled preds and succs (and associated latencies); try to place
73 the insn in the cycles of this window checking for potential
74 resource conflicts (using the DFA interface).
75 Note: this is different from the cycle-scheduling of schedule_insns;
76 here the insns are not scheduled monotonically top-down (nor bottom-
78 3. If failed in scheduling all insns - bump II++ and try again, unless
79 II reaches an upper bound MaxII, in which case report failure.
80 5. If we succeeded in scheduling the loop within II cycles, we now
81 generate prolog and epilog, decrease the counter of the loop, and
82 perform modulo variable expansion for live ranges that span more than
83 II cycles (i.e. use register copies to prevent a def from overwriting
84 itself before reaching the use).
88 /* This page defines partial-schedule structures and functions for
91 typedef struct partial_schedule *partial_schedule_ptr;
92 typedef struct ps_insn *ps_insn_ptr;
94 /* The minimum (absolute) cycle that a node of ps was scheduled in. */
95 #define PS_MIN_CYCLE(ps) (((partial_schedule_ptr)(ps))->min_cycle)
97 /* The maximum (absolute) cycle that a node of ps was scheduled in. */
98 #define PS_MAX_CYCLE(ps) (((partial_schedule_ptr)(ps))->max_cycle)
100 /* Perform signed modulo, always returning a non-negative value. */
101 #define SMODULO(x,y) ((x) % (y) < 0 ? ((x) % (y) + (y)) : (x) % (y))
103 /* The number of different iterations the nodes in ps span, assuming
104 the stage boundaries are placed efficiently. */
105 #define PS_STAGE_COUNT(ps) ((PS_MAX_CYCLE (ps) - PS_MIN_CYCLE (ps) \
106 + 1 + (ps)->ii - 1) / (ps)->ii)
108 /* A single instruction in the partial schedule. */
111 /* The corresponding DDG_NODE. */
114 /* The (absolute) cycle in which the PS instruction is scheduled.
115 Same as SCHED_TIME (node). */
118 /* The next/prev PS_INSN in the same row. */
119 ps_insn_ptr next_in_row,
122 /* The number of nodes in the same row that come after this node. */
126 /* Holds the partial schedule as an array of II rows. Each entry of the
127 array points to a linked list of PS_INSNs, which represents the
128 instructions that are scheduled for that row. */
129 struct partial_schedule
131 int ii; /* Number of rows in the partial schedule. */
132 int history; /* Threshold for conflict checking using DFA. */
134 /* rows[i] points to linked list of insns scheduled in row i (0<=i<ii). */
137 /* The earliest absolute cycle of an insn in the partial schedule. */
140 /* The latest absolute cycle of an insn in the partial schedule. */
143 ddg_ptr g; /* The DDG of the insns in the partial schedule. */
146 /* We use this to record all the register replacements we do in
147 the kernel so we can undo SMS if it is not profitable. */
148 struct undo_replace_buff_elem
153 struct undo_replace_buff_elem *next;
158 static partial_schedule_ptr create_partial_schedule (int ii, ddg_ptr, int history);
159 static void free_partial_schedule (partial_schedule_ptr);
160 static void reset_partial_schedule (partial_schedule_ptr, int new_ii);
161 void print_partial_schedule (partial_schedule_ptr, FILE *);
162 static int kernel_number_of_cycles (rtx first_insn, rtx last_insn);
163 static ps_insn_ptr ps_add_node_check_conflicts (partial_schedule_ptr,
164 ddg_node_ptr node, int cycle,
165 sbitmap must_precede,
166 sbitmap must_follow);
167 static void rotate_partial_schedule (partial_schedule_ptr, int);
168 void set_row_column_for_ps (partial_schedule_ptr);
169 static bool ps_unschedule_node (partial_schedule_ptr, ddg_node_ptr );
172 /* This page defines constants and structures for the modulo scheduling
175 /* As in haifa-sched.c: */
176 /* issue_rate is the number of insns that can be scheduled in the same
177 machine cycle. It can be defined in the config/mach/mach.h file,
178 otherwise we set it to 1. */
180 static int issue_rate;
182 static int sms_order_nodes (ddg_ptr, int, int * result);
183 static void set_node_sched_params (ddg_ptr);
184 static partial_schedule_ptr sms_schedule_by_order (ddg_ptr, int, int, int *);
185 static void permute_partial_schedule (partial_schedule_ptr ps, rtx last);
186 static void generate_prolog_epilog (partial_schedule_ptr ,struct loop * loop, rtx);
187 static void duplicate_insns_of_cycles (partial_schedule_ptr ps,
188 int from_stage, int to_stage,
191 #define SCHED_ASAP(x) (((node_sched_params_ptr)(x)->aux.info)->asap)
192 #define SCHED_TIME(x) (((node_sched_params_ptr)(x)->aux.info)->time)
193 #define SCHED_FIRST_REG_MOVE(x) \
194 (((node_sched_params_ptr)(x)->aux.info)->first_reg_move)
195 #define SCHED_NREG_MOVES(x) \
196 (((node_sched_params_ptr)(x)->aux.info)->nreg_moves)
197 #define SCHED_ROW(x) (((node_sched_params_ptr)(x)->aux.info)->row)
198 #define SCHED_STAGE(x) (((node_sched_params_ptr)(x)->aux.info)->stage)
199 #define SCHED_COLUMN(x) (((node_sched_params_ptr)(x)->aux.info)->column)
201 /* The scheduling parameters held for each node. */
202 typedef struct node_sched_params
204 int asap; /* A lower-bound on the absolute scheduling cycle. */
205 int time; /* The absolute scheduling cycle (time >= asap). */
207 /* The following field (first_reg_move) is a pointer to the first
208 register-move instruction added to handle the modulo-variable-expansion
209 of the register defined by this node. This register-move copies the
210 original register defined by the node. */
213 /* The number of register-move instructions added, immediately preceding
217 int row; /* Holds time % ii. */
218 int stage; /* Holds time / ii. */
220 /* The column of a node inside the ps. If nodes u, v are on the same row,
221 u will precede v if column (u) < column (v). */
223 } *node_sched_params_ptr;
226 /* The following three functions are copied from the current scheduler
227 code in order to use sched_analyze() for computing the dependencies.
228 They are used when initializing the sched_info structure. */
230 sms_print_insn (rtx insn, int aligned ATTRIBUTE_UNUSED)
234 sprintf (tmp, "i%4d", INSN_UID (insn));
239 compute_jump_reg_dependencies (rtx insn ATTRIBUTE_UNUSED,
240 regset cond_exec ATTRIBUTE_UNUSED,
241 regset used ATTRIBUTE_UNUSED,
242 regset set ATTRIBUTE_UNUSED)
246 static struct sched_info sms_sched_info =
255 compute_jump_reg_dependencies,
260 NULL, NULL, NULL, NULL, NULL,
265 /* Return the register decremented and tested in INSN,
266 or zero if it is not a decrement-and-branch insn. */
269 doloop_register_get (rtx insn ATTRIBUTE_UNUSED)
271 #ifdef HAVE_doloop_end
272 rtx pattern, reg, condition;
277 pattern = PATTERN (insn);
278 condition = doloop_condition_get (pattern);
282 if (REG_P (XEXP (condition, 0)))
283 reg = XEXP (condition, 0);
284 else if (GET_CODE (XEXP (condition, 0)) == PLUS
285 && REG_P (XEXP (XEXP (condition, 0), 0)))
286 reg = XEXP (XEXP (condition, 0), 0);
296 /* Check if COUNT_REG is set to a constant in the PRE_HEADER block, so
297 that the number of iterations is a compile-time constant. If so,
298 return the rtx that sets COUNT_REG to a constant, and set COUNT to
299 this constant. Otherwise return 0. */
301 const_iteration_count (rtx count_reg, basic_block pre_header,
302 HOST_WIDEST_INT * count)
310 get_ebb_head_tail (pre_header, pre_header, &head, &tail);
312 for (insn = tail; insn != PREV_INSN (head); insn = PREV_INSN (insn))
313 if (INSN_P (insn) && single_set (insn) &&
314 rtx_equal_p (count_reg, SET_DEST (single_set (insn))))
316 rtx pat = single_set (insn);
318 if (GET_CODE (SET_SRC (pat)) == CONST_INT)
320 *count = INTVAL (SET_SRC (pat));
330 /* A very simple resource-based lower bound on the initiation interval.
331 ??? Improve the accuracy of this bound by considering the
332 utilization of various units. */
336 return (g->num_nodes / issue_rate);
340 /* Points to the array that contains the sched data for each node. */
341 static node_sched_params_ptr node_sched_params;
343 /* Allocate sched_params for each node and initialize it. Assumes that
344 the aux field of each node contain the asap bound (computed earlier),
345 and copies it into the sched_params field. */
347 set_node_sched_params (ddg_ptr g)
351 /* Allocate for each node in the DDG a place to hold the "sched_data". */
352 /* Initialize ASAP/ALAP/HIGHT to zero. */
353 node_sched_params = (node_sched_params_ptr)
354 xcalloc (g->num_nodes,
355 sizeof (struct node_sched_params));
357 /* Set the pointer of the general data of the node to point to the
358 appropriate sched_params structure. */
359 for (i = 0; i < g->num_nodes; i++)
361 /* Watch out for aliasing problems? */
362 node_sched_params[i].asap = g->nodes[i].aux.count;
363 g->nodes[i].aux.info = &node_sched_params[i];
368 print_node_sched_params (FILE * file, int num_nodes)
374 for (i = 0; i < num_nodes; i++)
376 node_sched_params_ptr nsp = &node_sched_params[i];
377 rtx reg_move = nsp->first_reg_move;
380 fprintf (file, "Node %d:\n", i);
381 fprintf (file, " asap = %d:\n", nsp->asap);
382 fprintf (file, " time = %d:\n", nsp->time);
383 fprintf (file, " nreg_moves = %d:\n", nsp->nreg_moves);
384 for (j = 0; j < nsp->nreg_moves; j++)
386 fprintf (file, " reg_move = ");
387 print_rtl_single (file, reg_move);
388 reg_move = PREV_INSN (reg_move);
393 /* Calculate an upper bound for II. SMS should not schedule the loop if it
394 requires more cycles than this bound. Currently set to the sum of the
395 longest latency edge for each node. Reset based on experiments. */
397 calculate_maxii (ddg_ptr g)
402 for (i = 0; i < g->num_nodes; i++)
404 ddg_node_ptr u = &g->nodes[i];
406 int max_edge_latency = 0;
408 for (e = u->out; e; e = e->next_out)
409 max_edge_latency = MAX (max_edge_latency, e->latency);
411 maxii += max_edge_latency;
417 Breaking intra-loop register anti-dependences:
418 Each intra-loop register anti-dependence implies a cross-iteration true
419 dependence of distance 1. Therefore, we can remove such false dependencies
420 and figure out if the partial schedule broke them by checking if (for a
421 true-dependence of distance 1): SCHED_TIME (def) < SCHED_TIME (use) and
422 if so generate a register move. The number of such moves is equal to:
423 SCHED_TIME (use) - SCHED_TIME (def) { 0 broken
424 nreg_moves = ----------------------------------- + 1 - { dependence.
427 static struct undo_replace_buff_elem *
428 generate_reg_moves (partial_schedule_ptr ps, bool rescan)
433 struct undo_replace_buff_elem *reg_move_replaces = NULL;
435 for (i = 0; i < g->num_nodes; i++)
437 ddg_node_ptr u = &g->nodes[i];
439 int nreg_moves = 0, i_reg_move;
440 sbitmap *uses_of_defs;
442 rtx prev_reg, old_reg;
444 /* Compute the number of reg_moves needed for u, by looking at life
445 ranges started at u (excluding self-loops). */
446 for (e = u->out; e; e = e->next_out)
447 if (e->type == TRUE_DEP && e->dest != e->src)
449 int nreg_moves4e = (SCHED_TIME (e->dest) - SCHED_TIME (e->src)) / ii;
451 if (e->distance == 1)
452 nreg_moves4e = (SCHED_TIME (e->dest) - SCHED_TIME (e->src) + ii) / ii;
454 /* If dest precedes src in the schedule of the kernel, then dest
455 will read before src writes and we can save one reg_copy. */
456 if (SCHED_ROW (e->dest) == SCHED_ROW (e->src)
457 && SCHED_COLUMN (e->dest) < SCHED_COLUMN (e->src))
460 nreg_moves = MAX (nreg_moves, nreg_moves4e);
466 /* Every use of the register defined by node may require a different
467 copy of this register, depending on the time the use is scheduled.
468 Set a bitmap vector, telling which nodes use each copy of this
470 uses_of_defs = sbitmap_vector_alloc (nreg_moves, g->num_nodes);
471 sbitmap_vector_zero (uses_of_defs, nreg_moves);
472 for (e = u->out; e; e = e->next_out)
473 if (e->type == TRUE_DEP && e->dest != e->src)
475 int dest_copy = (SCHED_TIME (e->dest) - SCHED_TIME (e->src)) / ii;
477 if (e->distance == 1)
478 dest_copy = (SCHED_TIME (e->dest) - SCHED_TIME (e->src) + ii) / ii;
480 if (SCHED_ROW (e->dest) == SCHED_ROW (e->src)
481 && SCHED_COLUMN (e->dest) < SCHED_COLUMN (e->src))
485 SET_BIT (uses_of_defs[dest_copy - 1], e->dest->cuid);
488 /* Now generate the reg_moves, attaching relevant uses to them. */
489 SCHED_NREG_MOVES (u) = nreg_moves;
490 old_reg = prev_reg = copy_rtx (SET_DEST (single_set (u->insn)));
491 last_reg_move = u->insn;
493 for (i_reg_move = 0; i_reg_move < nreg_moves; i_reg_move++)
495 unsigned int i_use = 0;
496 rtx new_reg = gen_reg_rtx (GET_MODE (prev_reg));
497 rtx reg_move = gen_move_insn (new_reg, prev_reg);
498 sbitmap_iterator sbi;
500 add_insn_before (reg_move, last_reg_move, NULL);
501 last_reg_move = reg_move;
503 if (!SCHED_FIRST_REG_MOVE (u))
504 SCHED_FIRST_REG_MOVE (u) = reg_move;
506 EXECUTE_IF_SET_IN_SBITMAP (uses_of_defs[i_reg_move], 0, i_use, sbi)
508 struct undo_replace_buff_elem *rep;
510 rep = (struct undo_replace_buff_elem *)
511 xcalloc (1, sizeof (struct undo_replace_buff_elem));
512 rep->insn = g->nodes[i_use].insn;
513 rep->orig_reg = old_reg;
514 rep->new_reg = new_reg;
516 if (! reg_move_replaces)
517 reg_move_replaces = rep;
520 rep->next = reg_move_replaces;
521 reg_move_replaces = rep;
524 replace_rtx (g->nodes[i_use].insn, old_reg, new_reg);
526 df_insn_rescan (g->nodes[i_use].insn);
531 sbitmap_vector_free (uses_of_defs);
533 return reg_move_replaces;
536 /* We call this when we want to undo the SMS schedule for a given loop.
537 One of the things that we do is to delete the register moves generated
538 for the sake of SMS; this function deletes the register move instructions
539 recorded in the undo buffer. */
541 undo_generate_reg_moves (partial_schedule_ptr ps,
542 struct undo_replace_buff_elem *reg_move_replaces)
546 for (i = 0; i < ps->g->num_nodes; i++)
548 ddg_node_ptr u = &ps->g->nodes[i];
550 rtx crr = SCHED_FIRST_REG_MOVE (u);
552 for (j = 0; j < SCHED_NREG_MOVES (u); j++)
554 prev = PREV_INSN (crr);
558 SCHED_FIRST_REG_MOVE (u) = NULL_RTX;
561 while (reg_move_replaces)
563 struct undo_replace_buff_elem *rep = reg_move_replaces;
565 reg_move_replaces = reg_move_replaces->next;
566 replace_rtx (rep->insn, rep->new_reg, rep->orig_reg);
570 /* Free memory allocated for the undo buffer. */
572 free_undo_replace_buff (struct undo_replace_buff_elem *reg_move_replaces)
575 while (reg_move_replaces)
577 struct undo_replace_buff_elem *rep = reg_move_replaces;
579 reg_move_replaces = reg_move_replaces->next;
584 /* Bump the SCHED_TIMEs of all nodes to start from zero. Set the values
585 of SCHED_ROW and SCHED_STAGE. */
587 normalize_sched_times (partial_schedule_ptr ps)
591 int amount = PS_MIN_CYCLE (ps);
594 /* Don't include the closing branch assuming that it is the last node. */
595 for (i = 0; i < g->num_nodes - 1; i++)
597 ddg_node_ptr u = &g->nodes[i];
598 int normalized_time = SCHED_TIME (u) - amount;
600 gcc_assert (normalized_time >= 0);
602 SCHED_TIME (u) = normalized_time;
603 SCHED_ROW (u) = normalized_time % ii;
604 SCHED_STAGE (u) = normalized_time / ii;
608 /* Set SCHED_COLUMN of each node according to its position in PS. */
610 set_columns_for_ps (partial_schedule_ptr ps)
614 for (row = 0; row < ps->ii; row++)
616 ps_insn_ptr cur_insn = ps->rows[row];
619 for (; cur_insn; cur_insn = cur_insn->next_in_row)
620 SCHED_COLUMN (cur_insn->node) = column++;
624 /* Permute the insns according to their order in PS, from row 0 to
625 row ii-1, and position them right before LAST. This schedules
626 the insns of the loop kernel. */
628 permute_partial_schedule (partial_schedule_ptr ps, rtx last)
634 for (row = 0; row < ii ; row++)
635 for (ps_ij = ps->rows[row]; ps_ij; ps_ij = ps_ij->next_in_row)
636 if (PREV_INSN (last) != ps_ij->node->insn)
637 reorder_insns_nobb (ps_ij->node->first_note, ps_ij->node->insn,
641 /* As part of undoing SMS we return to the original ordering of the
642 instructions inside the loop kernel. Given the partial schedule PS, this
643 function returns the ordering of the instruction according to their CUID
644 in the DDG (PS->G), which is the original order of the instruction before
647 undo_permute_partial_schedule (partial_schedule_ptr ps, rtx last)
651 for (i = 0 ; i < ps->g->num_nodes; i++)
652 if (last == ps->g->nodes[i].insn
653 || last == ps->g->nodes[i].first_note)
655 else if (PREV_INSN (last) != ps->g->nodes[i].insn)
656 reorder_insns_nobb (ps->g->nodes[i].first_note, ps->g->nodes[i].insn,
660 /* Used to generate the prologue & epilogue. Duplicate the subset of
661 nodes whose stages are between FROM_STAGE and TO_STAGE (inclusive
662 of both), together with a prefix/suffix of their reg_moves. */
664 duplicate_insns_of_cycles (partial_schedule_ptr ps, int from_stage,
665 int to_stage, int for_prolog)
670 for (row = 0; row < ps->ii; row++)
671 for (ps_ij = ps->rows[row]; ps_ij; ps_ij = ps_ij->next_in_row)
673 ddg_node_ptr u_node = ps_ij->node;
675 rtx reg_move = NULL_RTX;
679 /* SCHED_STAGE (u_node) >= from_stage == 0. Generate increasing
680 number of reg_moves starting with the second occurrence of
681 u_node, which is generated if its SCHED_STAGE <= to_stage. */
682 i_reg_moves = to_stage - SCHED_STAGE (u_node) + 1;
683 i_reg_moves = MAX (i_reg_moves, 0);
684 i_reg_moves = MIN (i_reg_moves, SCHED_NREG_MOVES (u_node));
686 /* The reg_moves start from the *first* reg_move backwards. */
689 reg_move = SCHED_FIRST_REG_MOVE (u_node);
690 for (j = 1; j < i_reg_moves; j++)
691 reg_move = PREV_INSN (reg_move);
694 else /* It's for the epilog. */
696 /* SCHED_STAGE (u_node) <= to_stage. Generate all reg_moves,
697 starting to decrease one stage after u_node no longer occurs;
698 that is, generate all reg_moves until
699 SCHED_STAGE (u_node) == from_stage - 1. */
700 i_reg_moves = SCHED_NREG_MOVES (u_node)
701 - (from_stage - SCHED_STAGE (u_node) - 1);
702 i_reg_moves = MAX (i_reg_moves, 0);
703 i_reg_moves = MIN (i_reg_moves, SCHED_NREG_MOVES (u_node));
705 /* The reg_moves start from the *last* reg_move forwards. */
708 reg_move = SCHED_FIRST_REG_MOVE (u_node);
709 for (j = 1; j < SCHED_NREG_MOVES (u_node); j++)
710 reg_move = PREV_INSN (reg_move);
714 for (j = 0; j < i_reg_moves; j++, reg_move = NEXT_INSN (reg_move))
715 emit_insn (copy_rtx (PATTERN (reg_move)));
716 if (SCHED_STAGE (u_node) >= from_stage
717 && SCHED_STAGE (u_node) <= to_stage)
718 duplicate_insn_chain (u_node->first_note, u_node->insn);
723 /* Generate the instructions (including reg_moves) for prolog & epilog. */
725 generate_prolog_epilog (partial_schedule_ptr ps, struct loop * loop, rtx count_reg)
728 int last_stage = PS_STAGE_COUNT (ps) - 1;
731 /* Generate the prolog, inserting its insns on the loop-entry edge. */
735 /* Generate a subtract instruction at the beginning of the prolog to
736 adjust the loop count by STAGE_COUNT. */
737 emit_insn (gen_sub2_insn (count_reg, GEN_INT (last_stage)));
739 for (i = 0; i < last_stage; i++)
740 duplicate_insns_of_cycles (ps, 0, i, 1);
742 /* Put the prolog on the entry edge. */
743 e = loop_preheader_edge (loop);
744 split_edge_and_insert (e, get_insns ());
748 /* Generate the epilog, inserting its insns on the loop-exit edge. */
751 for (i = 0; i < last_stage; i++)
752 duplicate_insns_of_cycles (ps, i + 1, last_stage, 0);
754 /* Put the epilogue on the exit edge. */
755 gcc_assert (single_exit (loop));
756 e = single_exit (loop);
757 split_edge_and_insert (e, get_insns ());
761 /* Return true if all the BBs of the loop are empty except the
764 loop_single_full_bb_p (struct loop *loop)
767 basic_block *bbs = get_loop_body (loop);
769 for (i = 0; i < loop->num_nodes ; i++)
772 bool empty_bb = true;
774 if (bbs[i] == loop->header)
777 /* Make sure that basic blocks other than the header
778 have only notes labels or jumps. */
779 get_ebb_head_tail (bbs[i], bbs[i], &head, &tail);
780 for (; head != NEXT_INSN (tail); head = NEXT_INSN (head))
782 if (NOTE_P (head) || LABEL_P (head)
783 || (INSN_P (head) && JUMP_P (head)))
799 /* A simple loop from SMS point of view; it is a loop that is composed of
800 either a single basic block or two BBs - a header and a latch. */
801 #define SIMPLE_SMS_LOOP_P(loop) ((loop->num_nodes < 3 ) \
802 && (EDGE_COUNT (loop->latch->preds) == 1) \
803 && (EDGE_COUNT (loop->latch->succs) == 1))
805 /* Return true if the loop is in its canonical form and false if not.
806 i.e. SIMPLE_SMS_LOOP_P and have one preheader block, and single exit. */
808 loop_canon_p (struct loop *loop)
811 if (loop->inner || !loop_outer (loop))
814 if (!single_exit (loop))
818 rtx insn = BB_END (loop->header);
820 fprintf (dump_file, "SMS loop many exits ");
821 fprintf (dump_file, " %s %d (file, line)\n",
822 insn_file (insn), insn_line (insn));
827 if (! SIMPLE_SMS_LOOP_P (loop) && ! loop_single_full_bb_p (loop))
831 rtx insn = BB_END (loop->header);
833 fprintf (dump_file, "SMS loop many BBs. ");
834 fprintf (dump_file, " %s %d (file, line)\n",
835 insn_file (insn), insn_line (insn));
843 /* If there are more than one entry for the loop,
844 make it one by splitting the first entry edge and
845 redirecting the others to the new BB. */
847 canon_loop (struct loop *loop)
852 /* Avoid annoying special cases of edges going to exit
854 FOR_EACH_EDGE (e, i, EXIT_BLOCK_PTR->preds)
855 if ((e->flags & EDGE_FALLTHRU) && (EDGE_COUNT (e->src->succs) > 1))
858 if (loop->latch == loop->header
859 || EDGE_COUNT (loop->latch->succs) > 1)
861 FOR_EACH_EDGE (e, i, loop->header->preds)
862 if (e->src == loop->latch)
868 /* Probability in % that the sms-ed loop rolls enough so that optimized
869 version may be entered. Just a guess. */
870 #define PROB_SMS_ENOUGH_ITERATIONS 80
872 /* Main entry point, perform SMS scheduling on the loops of the function
873 that consist of single basic blocks. */
877 static int passes = 0;
883 partial_schedule_ptr ps;
884 basic_block bb = NULL;
886 basic_block condition_bb = NULL;
888 gcov_type trip_count = 0;
890 loop_optimizer_init (LOOPS_HAVE_PREHEADERS
891 | LOOPS_HAVE_RECORDED_EXITS);
892 if (number_of_loops () <= 1)
894 loop_optimizer_finalize ();
895 return; /* There are no loops to schedule. */
898 /* Initialize issue_rate. */
899 if (targetm.sched.issue_rate)
901 int temp = reload_completed;
903 reload_completed = 1;
904 issue_rate = targetm.sched.issue_rate ();
905 reload_completed = temp;
910 /* Initialize the scheduler. */
911 current_sched_info = &sms_sched_info;
913 /* Init Data Flow analysis, to be used in interloop dep calculation. */
914 df_set_flags (DF_LR_RUN_DCE);
915 df_rd_add_problem ();
916 df_note_add_problem ();
917 df_chain_add_problem (DF_DU_CHAIN);
919 regstat_compute_calls_crossed ();
922 /* Allocate memory to hold the DDG array one entry for each loop.
923 We use loop->num as index into this array. */
924 g_arr = XCNEWVEC (ddg_ptr, number_of_loops ());
926 /* Build DDGs for all the relevant loops and hold them in G_ARR
927 indexed by the loop index. */
928 FOR_EACH_LOOP (li, loop, 0)
934 if ((passes++ > MAX_SMS_LOOP_NUMBER) && (MAX_SMS_LOOP_NUMBER != -1))
937 fprintf (dump_file, "SMS reached MAX_PASSES... \n");
942 if (! loop_canon_p (loop))
945 if (! loop_single_full_bb_p (loop))
950 get_ebb_head_tail (bb, bb, &head, &tail);
951 latch_edge = loop_latch_edge (loop);
952 gcc_assert (single_exit (loop));
953 if (single_exit (loop)->count)
954 trip_count = latch_edge->count / single_exit (loop)->count;
956 /* Perfrom SMS only on loops that their average count is above threshold. */
958 if ( latch_edge->count
959 && (latch_edge->count < single_exit (loop)->count * SMS_LOOP_AVERAGE_COUNT_THRESHOLD))
963 fprintf (dump_file, " %s %d (file, line)\n",
964 insn_file (tail), insn_line (tail));
965 fprintf (dump_file, "SMS single-bb-loop\n");
966 if (profile_info && flag_branch_probabilities)
968 fprintf (dump_file, "SMS loop-count ");
969 fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC,
970 (HOST_WIDEST_INT) bb->count);
971 fprintf (dump_file, "\n");
972 fprintf (dump_file, "SMS trip-count ");
973 fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC,
974 (HOST_WIDEST_INT) trip_count);
975 fprintf (dump_file, "\n");
976 fprintf (dump_file, "SMS profile-sum-max ");
977 fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC,
978 (HOST_WIDEST_INT) profile_info->sum_max);
979 fprintf (dump_file, "\n");
985 /* Make sure this is a doloop. */
986 if ( !(count_reg = doloop_register_get (tail)))
989 /* Don't handle BBs with calls or barriers, or !single_set insns,
990 or auto-increment insns (to avoid creating invalid reg-moves
991 for the auto-increment insns).
992 ??? Should handle auto-increment insns. */
993 for (insn = head; insn != NEXT_INSN (tail); insn = NEXT_INSN (insn))
996 || (INSN_P (insn) && !JUMP_P (insn)
997 && !single_set (insn) && GET_CODE (PATTERN (insn)) != USE)
998 || (FIND_REG_INC_NOTE (insn, NULL_RTX) != 0))
1001 if (insn != NEXT_INSN (tail))
1006 fprintf (dump_file, "SMS loop-with-call\n");
1007 else if (BARRIER_P (insn))
1008 fprintf (dump_file, "SMS loop-with-barrier\n");
1009 else if (FIND_REG_INC_NOTE (insn, NULL_RTX) != 0)
1010 fprintf (dump_file, "SMS reg inc\n");
1012 fprintf (dump_file, "SMS loop-with-not-single-set\n");
1013 print_rtl_single (dump_file, insn);
1019 if (! (g = create_ddg (bb, 0)))
1022 fprintf (dump_file, "SMS doloop\n");
1026 g_arr[loop->num] = g;
1029 /* We don't want to perform SMS on new loops - created by versioning. */
1030 FOR_EACH_LOOP (li, loop, 0)
1033 rtx count_reg, count_init;
1035 unsigned stage_count = 0;
1036 HOST_WIDEST_INT loop_count = 0;
1038 if (! (g = g_arr[loop->num]))
1042 print_ddg (dump_file, g);
1044 get_ebb_head_tail (loop->header, loop->header, &head, &tail);
1046 latch_edge = loop_latch_edge (loop);
1047 gcc_assert (single_exit (loop));
1048 if (single_exit (loop)->count)
1049 trip_count = latch_edge->count / single_exit (loop)->count;
1053 fprintf (dump_file, " %s %d (file, line)\n",
1054 insn_file (tail), insn_line (tail));
1055 fprintf (dump_file, "SMS single-bb-loop\n");
1056 if (profile_info && flag_branch_probabilities)
1058 fprintf (dump_file, "SMS loop-count ");
1059 fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC,
1060 (HOST_WIDEST_INT) bb->count);
1061 fprintf (dump_file, "\n");
1062 fprintf (dump_file, "SMS profile-sum-max ");
1063 fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC,
1064 (HOST_WIDEST_INT) profile_info->sum_max);
1065 fprintf (dump_file, "\n");
1067 fprintf (dump_file, "SMS doloop\n");
1068 fprintf (dump_file, "SMS built-ddg %d\n", g->num_nodes);
1069 fprintf (dump_file, "SMS num-loads %d\n", g->num_loads);
1070 fprintf (dump_file, "SMS num-stores %d\n", g->num_stores);
1074 /* In case of th loop have doloop register it gets special
1076 count_init = NULL_RTX;
1077 if ((count_reg = doloop_register_get (tail)))
1079 basic_block pre_header;
1081 pre_header = loop_preheader_edge (loop)->src;
1082 count_init = const_iteration_count (count_reg, pre_header,
1085 gcc_assert (count_reg);
1087 if (dump_file && count_init)
1089 fprintf (dump_file, "SMS const-doloop ");
1090 fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC,
1092 fprintf (dump_file, "\n");
1095 node_order = XNEWVEC (int, g->num_nodes);
1097 mii = 1; /* Need to pass some estimate of mii. */
1098 rec_mii = sms_order_nodes (g, mii, node_order);
1099 mii = MAX (res_MII (g), rec_mii);
1100 maxii = (calculate_maxii (g) * SMS_MAX_II_FACTOR) / 100;
1103 fprintf (dump_file, "SMS iis %d %d %d (rec_mii, mii, maxii)\n",
1104 rec_mii, mii, maxii);
1106 /* After sms_order_nodes and before sms_schedule_by_order, to copy over
1108 set_node_sched_params (g);
1110 ps = sms_schedule_by_order (g, mii, maxii, node_order);
1113 stage_count = PS_STAGE_COUNT (ps);
1115 /* Stage count of 1 means that there is no interleaving between
1116 iterations, let the scheduling passes do the job. */
1118 || (count_init && (loop_count <= stage_count))
1119 || (flag_branch_probabilities && (trip_count <= stage_count)))
1123 fprintf (dump_file, "SMS failed... \n");
1124 fprintf (dump_file, "SMS sched-failed (stage-count=%d, loop-count=", stage_count);
1125 fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC, loop_count);
1126 fprintf (dump_file, ", trip-count=");
1127 fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC, trip_count);
1128 fprintf (dump_file, ")\n");
1134 int orig_cycles = kernel_number_of_cycles (BB_HEAD (g->bb), BB_END (g->bb));
1136 struct undo_replace_buff_elem *reg_move_replaces;
1141 "SMS succeeded %d %d (with ii, sc)\n", ps->ii,
1143 print_partial_schedule (ps, dump_file);
1145 "SMS Branch (%d) will later be scheduled at cycle %d.\n",
1146 g->closing_branch->cuid, PS_MIN_CYCLE (ps) - 1);
1149 /* Set the stage boundaries. If the DDG is built with closing_branch_deps,
1150 the closing_branch was scheduled and should appear in the last (ii-1)
1151 row. Otherwise, we are free to schedule the branch, and we let nodes
1152 that were scheduled at the first PS_MIN_CYCLE cycle appear in the first
1153 row; this should reduce stage_count to minimum. */
1154 normalize_sched_times (ps);
1155 rotate_partial_schedule (ps, PS_MIN_CYCLE (ps));
1156 set_columns_for_ps (ps);
1158 /* Generate the kernel just to be able to measure its cycles. */
1159 permute_partial_schedule (ps, g->closing_branch->first_note);
1160 reg_move_replaces = generate_reg_moves (ps, false);
1162 /* Get the number of cycles the new kernel expect to execute in. */
1163 new_cycles = kernel_number_of_cycles (BB_HEAD (g->bb), BB_END (g->bb));
1165 /* Get back to the original loop so we can do loop versioning. */
1166 undo_permute_partial_schedule (ps, g->closing_branch->first_note);
1167 if (reg_move_replaces)
1168 undo_generate_reg_moves (ps, reg_move_replaces);
1170 if ( new_cycles >= orig_cycles)
1172 /* SMS is not profitable so undo the permutation and reg move generation
1173 and return the kernel to its original state. */
1175 fprintf (dump_file, "Undoing SMS because it is not profitable.\n");
1182 /* case the BCT count is not known , Do loop-versioning */
1183 if (count_reg && ! count_init)
1185 rtx comp_rtx = gen_rtx_fmt_ee (GT, VOIDmode, count_reg,
1186 GEN_INT(stage_count));
1187 unsigned prob = (PROB_SMS_ENOUGH_ITERATIONS
1188 * REG_BR_PROB_BASE) / 100;
1190 loop_version (loop, comp_rtx, &condition_bb,
1191 prob, prob, REG_BR_PROB_BASE - prob,
1195 /* Set new iteration count of loop kernel. */
1196 if (count_reg && count_init)
1197 SET_SRC (single_set (count_init)) = GEN_INT (loop_count
1200 /* Now apply the scheduled kernel to the RTL of the loop. */
1201 permute_partial_schedule (ps, g->closing_branch->first_note);
1203 /* Mark this loop as software pipelined so the later
1204 scheduling passes doesn't touch it. */
1205 if (! flag_resched_modulo_sched)
1206 g->bb->flags |= BB_DISABLE_SCHEDULE;
1207 /* The life-info is not valid any more. */
1208 df_set_bb_dirty (g->bb);
1210 reg_move_replaces = generate_reg_moves (ps, true);
1212 print_node_sched_params (dump_file, g->num_nodes);
1213 /* Generate prolog and epilog. */
1214 if (count_reg && !count_init)
1215 generate_prolog_epilog (ps, loop, count_reg);
1217 generate_prolog_epilog (ps, loop, NULL_RTX);
1219 free_undo_replace_buff (reg_move_replaces);
1222 free_partial_schedule (ps);
1223 free (node_sched_params);
1228 regstat_free_calls_crossed ();
1231 /* Release scheduler data, needed until now because of DFA. */
1233 loop_optimizer_finalize ();
1236 /* The SMS scheduling algorithm itself
1237 -----------------------------------
1238 Input: 'O' an ordered list of insns of a loop.
1239 Output: A scheduling of the loop - kernel, prolog, and epilogue.
1241 'Q' is the empty Set
1242 'PS' is the partial schedule; it holds the currently scheduled nodes with
1244 'PSP' previously scheduled predecessors.
1245 'PSS' previously scheduled successors.
1246 't(u)' the cycle where u is scheduled.
1247 'l(u)' is the latency of u.
1248 'd(v,u)' is the dependence distance from v to u.
1249 'ASAP(u)' the earliest time at which u could be scheduled as computed in
1250 the node ordering phase.
1251 'check_hardware_resources_conflicts(u, PS, c)'
1252 run a trace around cycle/slot through DFA model
1253 to check resource conflicts involving instruction u
1254 at cycle c given the partial schedule PS.
1255 'add_to_partial_schedule_at_time(u, PS, c)'
1256 Add the node/instruction u to the partial schedule
1258 'calculate_register_pressure(PS)'
1259 Given a schedule of instructions, calculate the register
1260 pressure it implies. One implementation could be the
1261 maximum number of overlapping live ranges.
1262 'maxRP' The maximum allowed register pressure, it is usually derived from the number
1263 registers available in the hardware.
1267 3. for each node u in O in pre-computed order
1268 4. if (PSP(u) != Q && PSS(u) == Q) then
1269 5. Early_start(u) = max ( t(v) + l(v) - d(v,u)*II ) over all every v in PSP(u).
1270 6. start = Early_start; end = Early_start + II - 1; step = 1
1271 11. else if (PSP(u) == Q && PSS(u) != Q) then
1272 12. Late_start(u) = min ( t(v) - l(v) + d(v,u)*II ) over all every v in PSS(u).
1273 13. start = Late_start; end = Late_start - II + 1; step = -1
1274 14. else if (PSP(u) != Q && PSS(u) != Q) then
1275 15. Early_start(u) = max ( t(v) + l(v) - d(v,u)*II ) over all every v in PSP(u).
1276 16. Late_start(u) = min ( t(v) - l(v) + d(v,u)*II ) over all every v in PSS(u).
1277 17. start = Early_start;
1278 18. end = min(Early_start + II - 1 , Late_start);
1280 20. else "if (PSP(u) == Q && PSS(u) == Q)"
1281 21. start = ASAP(u); end = start + II - 1; step = 1
1285 24. for (c = start ; c != end ; c += step)
1286 25. if check_hardware_resources_conflicts(u, PS, c) then
1287 26. add_to_partial_schedule_at_time(u, PS, c)
1292 31. if (success == false) then
1294 33. if (II > maxII) then
1295 34. finish - failed to schedule
1300 39. if (calculate_register_pressure(PS) > maxRP) then
1303 42. compute epilogue & prologue
1304 43. finish - succeeded to schedule
1307 /* A limit on the number of cycles that resource conflicts can span. ??? Should
1308 be provided by DFA, and be dependent on the type of insn scheduled. Currently
1309 set to 0 to save compile time. */
1310 #define DFA_HISTORY SMS_DFA_HISTORY
1312 /* Given the partial schedule PS, this function calculates and returns the
1313 cycles in which we can schedule the node with the given index I.
1314 NOTE: Here we do the backtracking in SMS, in some special cases. We have
1315 noticed that there are several cases in which we fail to SMS the loop
1316 because the sched window of a node is empty due to tight data-deps. In
1317 such cases we want to unschedule some of the predecessors/successors
1318 until we get non-empty scheduling window. It returns -1 if the
1319 scheduling window is empty and zero otherwise. */
1322 get_sched_window (partial_schedule_ptr ps, int *nodes_order, int i,
1323 sbitmap sched_nodes, int ii, int *start_p, int *step_p, int *end_p)
1325 int start, step, end;
1327 int u = nodes_order [i];
1328 ddg_node_ptr u_node = &ps->g->nodes[u];
1329 sbitmap psp = sbitmap_alloc (ps->g->num_nodes);
1330 sbitmap pss = sbitmap_alloc (ps->g->num_nodes);
1331 sbitmap u_node_preds = NODE_PREDECESSORS (u_node);
1332 sbitmap u_node_succs = NODE_SUCCESSORS (u_node);
1336 /* 1. compute sched window for u (start, end, step). */
1339 psp_not_empty = sbitmap_a_and_b_cg (psp, u_node_preds, sched_nodes);
1340 pss_not_empty = sbitmap_a_and_b_cg (pss, u_node_succs, sched_nodes);
1342 if (psp_not_empty && !pss_not_empty)
1344 int early_start = INT_MIN;
1347 for (e = u_node->in; e != 0; e = e->next_in)
1349 ddg_node_ptr v_node = e->src;
1350 if (TEST_BIT (sched_nodes, v_node->cuid))
1352 int node_st = SCHED_TIME (v_node)
1353 + e->latency - (e->distance * ii);
1355 early_start = MAX (early_start, node_st);
1357 if (e->data_type == MEM_DEP)
1358 end = MIN (end, SCHED_TIME (v_node) + ii - 1);
1361 start = early_start;
1362 end = MIN (end, early_start + ii);
1366 else if (!psp_not_empty && pss_not_empty)
1368 int late_start = INT_MAX;
1371 for (e = u_node->out; e != 0; e = e->next_out)
1373 ddg_node_ptr v_node = e->dest;
1374 if (TEST_BIT (sched_nodes, v_node->cuid))
1376 late_start = MIN (late_start,
1377 SCHED_TIME (v_node) - e->latency
1378 + (e->distance * ii));
1379 if (e->data_type == MEM_DEP)
1380 end = MAX (end, SCHED_TIME (v_node) - ii + 1);
1384 end = MAX (end, late_start - ii);
1388 else if (psp_not_empty && pss_not_empty)
1390 int early_start = INT_MIN;
1391 int late_start = INT_MAX;
1395 for (e = u_node->in; e != 0; e = e->next_in)
1397 ddg_node_ptr v_node = e->src;
1399 if (TEST_BIT (sched_nodes, v_node->cuid))
1401 early_start = MAX (early_start,
1402 SCHED_TIME (v_node) + e->latency
1403 - (e->distance * ii));
1404 if (e->data_type == MEM_DEP)
1405 end = MIN (end, SCHED_TIME (v_node) + ii - 1);
1408 for (e = u_node->out; e != 0; e = e->next_out)
1410 ddg_node_ptr v_node = e->dest;
1412 if (TEST_BIT (sched_nodes, v_node->cuid))
1414 late_start = MIN (late_start,
1415 SCHED_TIME (v_node) - e->latency
1416 + (e->distance * ii));
1417 if (e->data_type == MEM_DEP)
1418 start = MAX (start, SCHED_TIME (v_node) - ii + 1);
1421 start = MAX (start, early_start);
1422 end = MIN (end, MIN (early_start + ii, late_start + 1));
1425 else /* psp is empty && pss is empty. */
1427 start = SCHED_ASAP (u_node);
1438 if ((start >= end && step == 1) || (start <= end && step == -1))
1444 /* This function implements the scheduling algorithm for SMS according to the
1446 static partial_schedule_ptr
1447 sms_schedule_by_order (ddg_ptr g, int mii, int maxii, int *nodes_order)
1451 int try_again_with_larger_ii = true;
1452 int num_nodes = g->num_nodes;
1454 int start, end, step; /* Place together into one struct? */
1455 sbitmap sched_nodes = sbitmap_alloc (num_nodes);
1456 sbitmap must_precede = sbitmap_alloc (num_nodes);
1457 sbitmap must_follow = sbitmap_alloc (num_nodes);
1458 sbitmap tobe_scheduled = sbitmap_alloc (num_nodes);
1460 partial_schedule_ptr ps = create_partial_schedule (ii, g, DFA_HISTORY);
1462 sbitmap_ones (tobe_scheduled);
1463 sbitmap_zero (sched_nodes);
1465 while ((! sbitmap_equal (tobe_scheduled, sched_nodes)
1466 || try_again_with_larger_ii ) && ii < maxii)
1469 bool unscheduled_nodes = false;
1472 fprintf (dump_file, "Starting with ii=%d\n", ii);
1473 if (try_again_with_larger_ii)
1475 try_again_with_larger_ii = false;
1476 sbitmap_zero (sched_nodes);
1479 for (i = 0; i < num_nodes; i++)
1481 int u = nodes_order[i];
1482 ddg_node_ptr u_node = &ps->g->nodes[u];
1483 rtx insn = u_node->insn;
1487 RESET_BIT (tobe_scheduled, u);
1491 if (JUMP_P (insn)) /* Closing branch handled later. */
1493 RESET_BIT (tobe_scheduled, u);
1497 if (TEST_BIT (sched_nodes, u))
1500 /* Try to get non-empty scheduling window. */
1502 while (get_sched_window (ps, nodes_order, i, sched_nodes, ii, &start, &step, &end) < 0
1505 unscheduled_nodes = true;
1506 if (TEST_BIT (NODE_PREDECESSORS (u_node), nodes_order[j - 1])
1507 || TEST_BIT (NODE_SUCCESSORS (u_node), nodes_order[j - 1]))
1509 ps_unschedule_node (ps, &ps->g->nodes[nodes_order[j - 1]]);
1510 RESET_BIT (sched_nodes, nodes_order [j - 1]);
1516 /* ??? Try backtracking instead of immediately ii++? */
1518 try_again_with_larger_ii = true;
1519 reset_partial_schedule (ps, ii);
1522 /* 2. Try scheduling u in window. */
1525 "Trying to schedule node %d in (%d .. %d) step %d\n",
1526 u, start, end, step);
1528 /* use must_follow & must_precede bitmaps to determine order
1529 of nodes within the cycle. */
1530 sbitmap_zero (must_precede);
1531 sbitmap_zero (must_follow);
1532 for (e = u_node->in; e != 0; e = e->next_in)
1533 if (TEST_BIT (sched_nodes, e->src->cuid)
1534 && e->latency == (ii * e->distance)
1535 && start == SCHED_TIME (e->src))
1536 SET_BIT (must_precede, e->src->cuid);
1538 for (e = u_node->out; e != 0; e = e->next_out)
1539 if (TEST_BIT (sched_nodes, e->dest->cuid)
1540 && e->latency == (ii * e->distance)
1541 && end == SCHED_TIME (e->dest))
1542 SET_BIT (must_follow, e->dest->cuid);
1545 if ((step > 0 && start < end) || (step < 0 && start > end))
1546 for (c = start; c != end; c += step)
1550 psi = ps_add_node_check_conflicts (ps, u_node, c,
1556 SCHED_TIME (u_node) = c;
1557 SET_BIT (sched_nodes, u);
1560 fprintf (dump_file, "Schedule in %d\n", c);
1566 /* ??? Try backtracking instead of immediately ii++? */
1568 try_again_with_larger_ii = true;
1569 reset_partial_schedule (ps, ii);
1572 if (unscheduled_nodes)
1575 /* ??? If (success), check register pressure estimates. */
1576 } /* Continue with next node. */
1577 } /* While try_again_with_larger_ii. */
1579 sbitmap_free (sched_nodes);
1580 sbitmap_free (must_precede);
1581 sbitmap_free (must_follow);
1582 sbitmap_free (tobe_scheduled);
1586 free_partial_schedule (ps);
1593 /* This page implements the algorithm for ordering the nodes of a DDG
1594 for modulo scheduling, activated through the
1595 "int sms_order_nodes (ddg_ptr, int mii, int * result)" API. */
1597 #define ORDER_PARAMS(x) ((struct node_order_params *) (x)->aux.info)
1598 #define ASAP(x) (ORDER_PARAMS ((x))->asap)
1599 #define ALAP(x) (ORDER_PARAMS ((x))->alap)
1600 #define HEIGHT(x) (ORDER_PARAMS ((x))->height)
1601 #define MOB(x) (ALAP ((x)) - ASAP ((x)))
1602 #define DEPTH(x) (ASAP ((x)))
1604 typedef struct node_order_params * nopa;
1606 static void order_nodes_of_sccs (ddg_all_sccs_ptr, int * result);
1607 static int order_nodes_in_scc (ddg_ptr, sbitmap, sbitmap, int*, int);
1608 static nopa calculate_order_params (ddg_ptr, int mii);
1609 static int find_max_asap (ddg_ptr, sbitmap);
1610 static int find_max_hv_min_mob (ddg_ptr, sbitmap);
1611 static int find_max_dv_min_mob (ddg_ptr, sbitmap);
1613 enum sms_direction {BOTTOMUP, TOPDOWN};
1615 struct node_order_params
1622 /* Check if NODE_ORDER contains a permutation of 0 .. NUM_NODES-1. */
1624 check_nodes_order (int *node_order, int num_nodes)
1627 sbitmap tmp = sbitmap_alloc (num_nodes);
1631 for (i = 0; i < num_nodes; i++)
1633 int u = node_order[i];
1635 gcc_assert (u < num_nodes && u >= 0 && !TEST_BIT (tmp, u));
1643 /* Order the nodes of G for scheduling and pass the result in
1644 NODE_ORDER. Also set aux.count of each node to ASAP.
1645 Return the recMII for the given DDG. */
1647 sms_order_nodes (ddg_ptr g, int mii, int * node_order)
1651 ddg_all_sccs_ptr sccs = create_ddg_all_sccs (g);
1653 nopa nops = calculate_order_params (g, mii);
1656 print_sccs (dump_file, sccs, g);
1658 order_nodes_of_sccs (sccs, node_order);
1660 if (sccs->num_sccs > 0)
1661 /* First SCC has the largest recurrence_length. */
1662 rec_mii = sccs->sccs[0]->recurrence_length;
1664 /* Save ASAP before destroying node_order_params. */
1665 for (i = 0; i < g->num_nodes; i++)
1667 ddg_node_ptr v = &g->nodes[i];
1668 v->aux.count = ASAP (v);
1672 free_ddg_all_sccs (sccs);
1673 check_nodes_order (node_order, g->num_nodes);
1679 order_nodes_of_sccs (ddg_all_sccs_ptr all_sccs, int * node_order)
1682 ddg_ptr g = all_sccs->ddg;
1683 int num_nodes = g->num_nodes;
1684 sbitmap prev_sccs = sbitmap_alloc (num_nodes);
1685 sbitmap on_path = sbitmap_alloc (num_nodes);
1686 sbitmap tmp = sbitmap_alloc (num_nodes);
1687 sbitmap ones = sbitmap_alloc (num_nodes);
1689 sbitmap_zero (prev_sccs);
1690 sbitmap_ones (ones);
1692 /* Perfrom the node ordering starting from the SCC with the highest recMII.
1693 For each SCC order the nodes according to their ASAP/ALAP/HEIGHT etc. */
1694 for (i = 0; i < all_sccs->num_sccs; i++)
1696 ddg_scc_ptr scc = all_sccs->sccs[i];
1698 /* Add nodes on paths from previous SCCs to the current SCC. */
1699 find_nodes_on_paths (on_path, g, prev_sccs, scc->nodes);
1700 sbitmap_a_or_b (tmp, scc->nodes, on_path);
1702 /* Add nodes on paths from the current SCC to previous SCCs. */
1703 find_nodes_on_paths (on_path, g, scc->nodes, prev_sccs);
1704 sbitmap_a_or_b (tmp, tmp, on_path);
1706 /* Remove nodes of previous SCCs from current extended SCC. */
1707 sbitmap_difference (tmp, tmp, prev_sccs);
1709 pos = order_nodes_in_scc (g, prev_sccs, tmp, node_order, pos);
1710 /* Above call to order_nodes_in_scc updated prev_sccs |= tmp. */
1713 /* Handle the remaining nodes that do not belong to any scc. Each call
1714 to order_nodes_in_scc handles a single connected component. */
1715 while (pos < g->num_nodes)
1717 sbitmap_difference (tmp, ones, prev_sccs);
1718 pos = order_nodes_in_scc (g, prev_sccs, tmp, node_order, pos);
1720 sbitmap_free (prev_sccs);
1721 sbitmap_free (on_path);
1723 sbitmap_free (ones);
1726 /* MII is needed if we consider backarcs (that do not close recursive cycles). */
1727 static struct node_order_params *
1728 calculate_order_params (ddg_ptr g, int mii ATTRIBUTE_UNUSED)
1732 int num_nodes = g->num_nodes;
1734 /* Allocate a place to hold ordering params for each node in the DDG. */
1735 nopa node_order_params_arr;
1737 /* Initialize of ASAP/ALAP/HEIGHT to zero. */
1738 node_order_params_arr = (nopa) xcalloc (num_nodes,
1739 sizeof (struct node_order_params));
1741 /* Set the aux pointer of each node to point to its order_params structure. */
1742 for (u = 0; u < num_nodes; u++)
1743 g->nodes[u].aux.info = &node_order_params_arr[u];
1745 /* Disregarding a backarc from each recursive cycle to obtain a DAG,
1746 calculate ASAP, ALAP, mobility, distance, and height for each node
1747 in the dependence (direct acyclic) graph. */
1749 /* We assume that the nodes in the array are in topological order. */
1752 for (u = 0; u < num_nodes; u++)
1754 ddg_node_ptr u_node = &g->nodes[u];
1757 for (e = u_node->in; e; e = e->next_in)
1758 if (e->distance == 0)
1759 ASAP (u_node) = MAX (ASAP (u_node),
1760 ASAP (e->src) + e->latency);
1761 max_asap = MAX (max_asap, ASAP (u_node));
1764 for (u = num_nodes - 1; u > -1; u--)
1766 ddg_node_ptr u_node = &g->nodes[u];
1768 ALAP (u_node) = max_asap;
1769 HEIGHT (u_node) = 0;
1770 for (e = u_node->out; e; e = e->next_out)
1771 if (e->distance == 0)
1773 ALAP (u_node) = MIN (ALAP (u_node),
1774 ALAP (e->dest) - e->latency);
1775 HEIGHT (u_node) = MAX (HEIGHT (u_node),
1776 HEIGHT (e->dest) + e->latency);
1780 return node_order_params_arr;
1784 find_max_asap (ddg_ptr g, sbitmap nodes)
1789 sbitmap_iterator sbi;
1791 EXECUTE_IF_SET_IN_SBITMAP (nodes, 0, u, sbi)
1793 ddg_node_ptr u_node = &g->nodes[u];
1795 if (max_asap < ASAP (u_node))
1797 max_asap = ASAP (u_node);
1805 find_max_hv_min_mob (ddg_ptr g, sbitmap nodes)
1809 int min_mob = INT_MAX;
1811 sbitmap_iterator sbi;
1813 EXECUTE_IF_SET_IN_SBITMAP (nodes, 0, u, sbi)
1815 ddg_node_ptr u_node = &g->nodes[u];
1817 if (max_hv < HEIGHT (u_node))
1819 max_hv = HEIGHT (u_node);
1820 min_mob = MOB (u_node);
1823 else if ((max_hv == HEIGHT (u_node))
1824 && (min_mob > MOB (u_node)))
1826 min_mob = MOB (u_node);
1834 find_max_dv_min_mob (ddg_ptr g, sbitmap nodes)
1838 int min_mob = INT_MAX;
1840 sbitmap_iterator sbi;
1842 EXECUTE_IF_SET_IN_SBITMAP (nodes, 0, u, sbi)
1844 ddg_node_ptr u_node = &g->nodes[u];
1846 if (max_dv < DEPTH (u_node))
1848 max_dv = DEPTH (u_node);
1849 min_mob = MOB (u_node);
1852 else if ((max_dv == DEPTH (u_node))
1853 && (min_mob > MOB (u_node)))
1855 min_mob = MOB (u_node);
1862 /* Places the nodes of SCC into the NODE_ORDER array starting
1863 at position POS, according to the SMS ordering algorithm.
1864 NODES_ORDERED (in&out parameter) holds the bitset of all nodes in
1865 the NODE_ORDER array, starting from position zero. */
1867 order_nodes_in_scc (ddg_ptr g, sbitmap nodes_ordered, sbitmap scc,
1868 int * node_order, int pos)
1870 enum sms_direction dir;
1871 int num_nodes = g->num_nodes;
1872 sbitmap workset = sbitmap_alloc (num_nodes);
1873 sbitmap tmp = sbitmap_alloc (num_nodes);
1874 sbitmap zero_bitmap = sbitmap_alloc (num_nodes);
1875 sbitmap predecessors = sbitmap_alloc (num_nodes);
1876 sbitmap successors = sbitmap_alloc (num_nodes);
1878 sbitmap_zero (predecessors);
1879 find_predecessors (predecessors, g, nodes_ordered);
1881 sbitmap_zero (successors);
1882 find_successors (successors, g, nodes_ordered);
1885 if (sbitmap_a_and_b_cg (tmp, predecessors, scc))
1887 sbitmap_copy (workset, tmp);
1890 else if (sbitmap_a_and_b_cg (tmp, successors, scc))
1892 sbitmap_copy (workset, tmp);
1899 sbitmap_zero (workset);
1900 if ((u = find_max_asap (g, scc)) >= 0)
1901 SET_BIT (workset, u);
1905 sbitmap_zero (zero_bitmap);
1906 while (!sbitmap_equal (workset, zero_bitmap))
1909 ddg_node_ptr v_node;
1910 sbitmap v_node_preds;
1911 sbitmap v_node_succs;
1915 while (!sbitmap_equal (workset, zero_bitmap))
1917 v = find_max_hv_min_mob (g, workset);
1918 v_node = &g->nodes[v];
1919 node_order[pos++] = v;
1920 v_node_succs = NODE_SUCCESSORS (v_node);
1921 sbitmap_a_and_b (tmp, v_node_succs, scc);
1923 /* Don't consider the already ordered successors again. */
1924 sbitmap_difference (tmp, tmp, nodes_ordered);
1925 sbitmap_a_or_b (workset, workset, tmp);
1926 RESET_BIT (workset, v);
1927 SET_BIT (nodes_ordered, v);
1930 sbitmap_zero (predecessors);
1931 find_predecessors (predecessors, g, nodes_ordered);
1932 sbitmap_a_and_b (workset, predecessors, scc);
1936 while (!sbitmap_equal (workset, zero_bitmap))
1938 v = find_max_dv_min_mob (g, workset);
1939 v_node = &g->nodes[v];
1940 node_order[pos++] = v;
1941 v_node_preds = NODE_PREDECESSORS (v_node);
1942 sbitmap_a_and_b (tmp, v_node_preds, scc);
1944 /* Don't consider the already ordered predecessors again. */
1945 sbitmap_difference (tmp, tmp, nodes_ordered);
1946 sbitmap_a_or_b (workset, workset, tmp);
1947 RESET_BIT (workset, v);
1948 SET_BIT (nodes_ordered, v);
1951 sbitmap_zero (successors);
1952 find_successors (successors, g, nodes_ordered);
1953 sbitmap_a_and_b (workset, successors, scc);
1957 sbitmap_free (workset);
1958 sbitmap_free (zero_bitmap);
1959 sbitmap_free (predecessors);
1960 sbitmap_free (successors);
1965 /* This page contains functions for manipulating partial-schedules during
1966 modulo scheduling. */
1968 /* Create a partial schedule and allocate a memory to hold II rows. */
1970 static partial_schedule_ptr
1971 create_partial_schedule (int ii, ddg_ptr g, int history)
1973 partial_schedule_ptr ps = XNEW (struct partial_schedule);
1974 ps->rows = (ps_insn_ptr *) xcalloc (ii, sizeof (ps_insn_ptr));
1976 ps->history = history;
1977 ps->min_cycle = INT_MAX;
1978 ps->max_cycle = INT_MIN;
1984 /* Free the PS_INSNs in rows array of the given partial schedule.
1985 ??? Consider caching the PS_INSN's. */
1987 free_ps_insns (partial_schedule_ptr ps)
1991 for (i = 0; i < ps->ii; i++)
1995 ps_insn_ptr ps_insn = ps->rows[i]->next_in_row;
1998 ps->rows[i] = ps_insn;
2004 /* Free all the memory allocated to the partial schedule. */
2007 free_partial_schedule (partial_schedule_ptr ps)
2016 /* Clear the rows array with its PS_INSNs, and create a new one with
2020 reset_partial_schedule (partial_schedule_ptr ps, int new_ii)
2025 if (new_ii == ps->ii)
2027 ps->rows = (ps_insn_ptr *) xrealloc (ps->rows, new_ii
2028 * sizeof (ps_insn_ptr));
2029 memset (ps->rows, 0, new_ii * sizeof (ps_insn_ptr));
2031 ps->min_cycle = INT_MAX;
2032 ps->max_cycle = INT_MIN;
2035 /* Prints the partial schedule as an ii rows array, for each rows
2036 print the ids of the insns in it. */
2038 print_partial_schedule (partial_schedule_ptr ps, FILE *dump)
2042 for (i = 0; i < ps->ii; i++)
2044 ps_insn_ptr ps_i = ps->rows[i];
2046 fprintf (dump, "\n[CYCLE %d ]: ", i);
2049 fprintf (dump, "%d, ",
2050 INSN_UID (ps_i->node->insn));
2051 ps_i = ps_i->next_in_row;
2056 /* Creates an object of PS_INSN and initializes it to the given parameters. */
2058 create_ps_insn (ddg_node_ptr node, int rest_count, int cycle)
2060 ps_insn_ptr ps_i = XNEW (struct ps_insn);
2063 ps_i->next_in_row = NULL;
2064 ps_i->prev_in_row = NULL;
2065 ps_i->row_rest_count = rest_count;
2066 ps_i->cycle = cycle;
2072 /* Removes the given PS_INSN from the partial schedule. Returns false if the
2073 node is not found in the partial schedule, else returns true. */
2075 remove_node_from_ps (partial_schedule_ptr ps, ps_insn_ptr ps_i)
2082 row = SMODULO (ps_i->cycle, ps->ii);
2083 if (! ps_i->prev_in_row)
2085 if (ps_i != ps->rows[row])
2088 ps->rows[row] = ps_i->next_in_row;
2090 ps->rows[row]->prev_in_row = NULL;
2094 ps_i->prev_in_row->next_in_row = ps_i->next_in_row;
2095 if (ps_i->next_in_row)
2096 ps_i->next_in_row->prev_in_row = ps_i->prev_in_row;
2102 /* Unlike what literature describes for modulo scheduling (which focuses
2103 on VLIW machines) the order of the instructions inside a cycle is
2104 important. Given the bitmaps MUST_FOLLOW and MUST_PRECEDE we know
2105 where the current instruction should go relative to the already
2106 scheduled instructions in the given cycle. Go over these
2107 instructions and find the first possible column to put it in. */
2109 ps_insn_find_column (partial_schedule_ptr ps, ps_insn_ptr ps_i,
2110 sbitmap must_precede, sbitmap must_follow)
2112 ps_insn_ptr next_ps_i;
2113 ps_insn_ptr first_must_follow = NULL;
2114 ps_insn_ptr last_must_precede = NULL;
2120 row = SMODULO (ps_i->cycle, ps->ii);
2122 /* Find the first must follow and the last must precede
2123 and insert the node immediately after the must precede
2124 but make sure that it there is no must follow after it. */
2125 for (next_ps_i = ps->rows[row];
2127 next_ps_i = next_ps_i->next_in_row)
2129 if (TEST_BIT (must_follow, next_ps_i->node->cuid)
2130 && ! first_must_follow)
2131 first_must_follow = next_ps_i;
2132 if (TEST_BIT (must_precede, next_ps_i->node->cuid))
2134 /* If we have already met a node that must follow, then
2135 there is no possible column. */
2136 if (first_must_follow)
2139 last_must_precede = next_ps_i;
2143 /* Now insert the node after INSERT_AFTER_PSI. */
2145 if (! last_must_precede)
2147 ps_i->next_in_row = ps->rows[row];
2148 ps_i->prev_in_row = NULL;
2149 if (ps_i->next_in_row)
2150 ps_i->next_in_row->prev_in_row = ps_i;
2151 ps->rows[row] = ps_i;
2155 ps_i->next_in_row = last_must_precede->next_in_row;
2156 last_must_precede->next_in_row = ps_i;
2157 ps_i->prev_in_row = last_must_precede;
2158 if (ps_i->next_in_row)
2159 ps_i->next_in_row->prev_in_row = ps_i;
2165 /* Advances the PS_INSN one column in its current row; returns false
2166 in failure and true in success. Bit N is set in MUST_FOLLOW if
2167 the node with cuid N must be come after the node pointed to by
2168 PS_I when scheduled in the same cycle. */
2170 ps_insn_advance_column (partial_schedule_ptr ps, ps_insn_ptr ps_i,
2171 sbitmap must_follow)
2173 ps_insn_ptr prev, next;
2175 ddg_node_ptr next_node;
2180 row = SMODULO (ps_i->cycle, ps->ii);
2182 if (! ps_i->next_in_row)
2185 next_node = ps_i->next_in_row->node;
2187 /* Check if next_in_row is dependent on ps_i, both having same sched
2188 times (typically ANTI_DEP). If so, ps_i cannot skip over it. */
2189 if (TEST_BIT (must_follow, next_node->cuid))
2192 /* Advance PS_I over its next_in_row in the doubly linked list. */
2193 prev = ps_i->prev_in_row;
2194 next = ps_i->next_in_row;
2196 if (ps_i == ps->rows[row])
2197 ps->rows[row] = next;
2199 ps_i->next_in_row = next->next_in_row;
2201 if (next->next_in_row)
2202 next->next_in_row->prev_in_row = ps_i;
2204 next->next_in_row = ps_i;
2205 ps_i->prev_in_row = next;
2207 next->prev_in_row = prev;
2209 prev->next_in_row = next;
2214 /* Inserts a DDG_NODE to the given partial schedule at the given cycle.
2215 Returns 0 if this is not possible and a PS_INSN otherwise. Bit N is
2216 set in MUST_PRECEDE/MUST_FOLLOW if the node with cuid N must be come
2217 before/after (respectively) the node pointed to by PS_I when scheduled
2218 in the same cycle. */
2220 add_node_to_ps (partial_schedule_ptr ps, ddg_node_ptr node, int cycle,
2221 sbitmap must_precede, sbitmap must_follow)
2225 int row = SMODULO (cycle, ps->ii);
2228 && ps->rows[row]->row_rest_count >= issue_rate)
2232 rest_count += ps->rows[row]->row_rest_count;
2234 ps_i = create_ps_insn (node, rest_count, cycle);
2236 /* Finds and inserts PS_I according to MUST_FOLLOW and
2238 if (! ps_insn_find_column (ps, ps_i, must_precede, must_follow))
2247 /* Advance time one cycle. Assumes DFA is being used. */
2249 advance_one_cycle (void)
2251 if (targetm.sched.dfa_pre_cycle_insn)
2252 state_transition (curr_state,
2253 targetm.sched.dfa_pre_cycle_insn ());
2255 state_transition (curr_state, NULL);
2257 if (targetm.sched.dfa_post_cycle_insn)
2258 state_transition (curr_state,
2259 targetm.sched.dfa_post_cycle_insn ());
2262 /* Given the kernel of a loop (from FIRST_INSN to LAST_INSN), finds
2263 the number of cycles according to DFA that the kernel fits in,
2264 we use this to check if we done well with SMS after we add
2265 register moves. In some cases register moves overhead makes
2266 it even worse than the original loop. We want SMS to be performed
2267 when it gives less cycles after register moves are added. */
2269 kernel_number_of_cycles (rtx first_insn, rtx last_insn)
2273 int can_issue_more = issue_rate;
2275 state_reset (curr_state);
2277 for (insn = first_insn;
2278 insn != NULL_RTX && insn != last_insn;
2279 insn = NEXT_INSN (insn))
2281 if (! INSN_P (insn) || GET_CODE (PATTERN (insn)) == USE)
2284 /* Check if there is room for the current insn. */
2285 if (!can_issue_more || state_dead_lock_p (curr_state))
2288 advance_one_cycle ();
2289 can_issue_more = issue_rate;
2292 /* Update the DFA state and return with failure if the DFA found
2293 recource conflicts. */
2294 if (state_transition (curr_state, insn) >= 0)
2297 advance_one_cycle ();
2298 can_issue_more = issue_rate;
2301 if (targetm.sched.variable_issue)
2303 targetm.sched.variable_issue (sched_dump, sched_verbose,
2304 insn, can_issue_more);
2305 /* A naked CLOBBER or USE generates no instruction, so don't
2306 let them consume issue slots. */
2307 else if (GET_CODE (PATTERN (insn)) != USE
2308 && GET_CODE (PATTERN (insn)) != CLOBBER)
2314 /* Checks if PS has resource conflicts according to DFA, starting from
2315 FROM cycle to TO cycle; returns true if there are conflicts and false
2316 if there are no conflicts. Assumes DFA is being used. */
2318 ps_has_conflicts (partial_schedule_ptr ps, int from, int to)
2322 state_reset (curr_state);
2324 for (cycle = from; cycle <= to; cycle++)
2326 ps_insn_ptr crr_insn;
2327 /* Holds the remaining issue slots in the current row. */
2328 int can_issue_more = issue_rate;
2330 /* Walk through the DFA for the current row. */
2331 for (crr_insn = ps->rows[SMODULO (cycle, ps->ii)];
2333 crr_insn = crr_insn->next_in_row)
2335 rtx insn = crr_insn->node->insn;
2340 /* Check if there is room for the current insn. */
2341 if (!can_issue_more || state_dead_lock_p (curr_state))
2344 /* Update the DFA state and return with failure if the DFA found
2345 recource conflicts. */
2346 if (state_transition (curr_state, insn) >= 0)
2349 if (targetm.sched.variable_issue)
2351 targetm.sched.variable_issue (sched_dump, sched_verbose,
2352 insn, can_issue_more);
2353 /* A naked CLOBBER or USE generates no instruction, so don't
2354 let them consume issue slots. */
2355 else if (GET_CODE (PATTERN (insn)) != USE
2356 && GET_CODE (PATTERN (insn)) != CLOBBER)
2360 /* Advance the DFA to the next cycle. */
2361 advance_one_cycle ();
2366 /* Checks if the given node causes resource conflicts when added to PS at
2367 cycle C. If not the node is added to PS and returned; otherwise zero
2368 is returned. Bit N is set in MUST_PRECEDE/MUST_FOLLOW if the node with
2369 cuid N must be come before/after (respectively) the node pointed to by
2370 PS_I when scheduled in the same cycle. */
2372 ps_add_node_check_conflicts (partial_schedule_ptr ps, ddg_node_ptr n,
2373 int c, sbitmap must_precede,
2374 sbitmap must_follow)
2376 int has_conflicts = 0;
2379 /* First add the node to the PS, if this succeeds check for
2380 conflicts, trying different issue slots in the same row. */
2381 if (! (ps_i = add_node_to_ps (ps, n, c, must_precede, must_follow)))
2382 return NULL; /* Failed to insert the node at the given cycle. */
2384 has_conflicts = ps_has_conflicts (ps, c, c)
2386 && ps_has_conflicts (ps,
2390 /* Try different issue slots to find one that the given node can be
2391 scheduled in without conflicts. */
2392 while (has_conflicts)
2394 if (! ps_insn_advance_column (ps, ps_i, must_follow))
2396 has_conflicts = ps_has_conflicts (ps, c, c)
2398 && ps_has_conflicts (ps,
2405 remove_node_from_ps (ps, ps_i);
2409 ps->min_cycle = MIN (ps->min_cycle, c);
2410 ps->max_cycle = MAX (ps->max_cycle, c);
2414 /* Rotate the rows of PS such that insns scheduled at time
2415 START_CYCLE will appear in row 0. Updates max/min_cycles. */
2417 rotate_partial_schedule (partial_schedule_ptr ps, int start_cycle)
2419 int i, row, backward_rotates;
2420 int last_row = ps->ii - 1;
2422 if (start_cycle == 0)
2425 backward_rotates = SMODULO (start_cycle, ps->ii);
2427 /* Revisit later and optimize this into a single loop. */
2428 for (i = 0; i < backward_rotates; i++)
2430 ps_insn_ptr first_row = ps->rows[0];
2432 for (row = 0; row < last_row; row++)
2433 ps->rows[row] = ps->rows[row+1];
2435 ps->rows[last_row] = first_row;
2438 ps->max_cycle -= start_cycle;
2439 ps->min_cycle -= start_cycle;
2442 /* Remove the node N from the partial schedule PS; because we restart the DFA
2443 each time we want to check for resource conflicts; this is equivalent to
2444 unscheduling the node N. */
2446 ps_unschedule_node (partial_schedule_ptr ps, ddg_node_ptr n)
2449 int row = SMODULO (SCHED_TIME (n), ps->ii);
2451 if (row < 0 || row > ps->ii)
2454 for (ps_i = ps->rows[row];
2455 ps_i && ps_i->node != n;
2456 ps_i = ps_i->next_in_row);
2460 return remove_node_from_ps (ps, ps_i);
2462 #endif /* INSN_SCHEDULING */
2465 gate_handle_sms (void)
2467 return (optimize > 0 && flag_modulo_sched);
2471 /* Run instruction scheduler. */
2472 /* Perform SMS module scheduling. */
2474 rest_of_handle_sms (void)
2476 #ifdef INSN_SCHEDULING
2479 /* Collect loop information to be used in SMS. */
2480 cfg_layout_initialize (0);
2483 /* Update the life information, because we add pseudos. */
2484 max_regno = max_reg_num ();
2486 /* Finalize layout changes. */
2488 if (bb->next_bb != EXIT_BLOCK_PTR)
2489 bb->aux = bb->next_bb;
2490 free_dominance_info (CDI_DOMINATORS);
2491 cfg_layout_finalize ();
2492 #endif /* INSN_SCHEDULING */
2496 struct tree_opt_pass pass_sms =
2499 gate_handle_sms, /* gate */
2500 rest_of_handle_sms, /* execute */
2503 0, /* static_pass_number */
2505 0, /* properties_required */
2506 0, /* properties_provided */
2507 0, /* properties_destroyed */
2508 TODO_dump_func, /* todo_flags_start */
2511 TODO_ggc_collect, /* todo_flags_finish */