2 Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007
3 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
27 #include "hard-reg-set.h"
30 #include "insn-config.h"
32 #include "basic-block.h"
36 #include "tree-pass.h"
40 /* We want target macros for the mode switching code to be able to refer
41 to instruction attribute values. */
42 #include "insn-attr.h"
44 #ifdef OPTIMIZE_MODE_SWITCHING
46 /* The algorithm for setting the modes consists of scanning the insn list
47 and finding all the insns which require a specific mode. Each insn gets
48 a unique struct seginfo element. These structures are inserted into a list
49 for each basic block. For each entity, there is an array of bb_info over
50 the flow graph basic blocks (local var 'bb_info'), and contains a list
51 of all insns within that basic block, in the order they are encountered.
53 For each entity, any basic block WITHOUT any insns requiring a specific
54 mode are given a single entry, without a mode. (Each basic block
55 in the flow graph must have at least one entry in the segment table.)
57 The LCM algorithm is then run over the flow graph to determine where to
58 place the sets to the highest-priority value in respect of first the first
59 insn in any one block. Any adjustments required to the transparency
60 vectors are made, then the next iteration starts for the next-lower
61 priority mode, till for each entity all modes are exhausted.
63 More details are located in the code for optimize_mode_switching(). */
65 /* This structure contains the information for each insn which requires
66 either single or double mode to be set.
67 MODE is the mode this insn must be executed in.
68 INSN_PTR is the insn to be executed (may be the note that marks the
69 beginning of a basic block).
70 BBNUM is the flow graph basic block this insn occurs in.
71 NEXT is the next insn in the same basic block. */
78 HARD_REG_SET regs_live;
83 struct seginfo *seginfo;
87 /* These bitmaps are used for the LCM algorithm. */
89 static sbitmap *antic;
90 static sbitmap *transp;
93 static struct seginfo * new_seginfo (int, rtx, int, HARD_REG_SET);
94 static void add_seginfo (struct bb_info *, struct seginfo *);
95 static void reg_dies (rtx, HARD_REG_SET *);
96 static void reg_becomes_live (rtx, rtx, void *);
97 static void make_preds_opaque (basic_block, int);
100 /* This function will allocate a new BBINFO structure, initialized
101 with the MODE, INSN, and basic block BB parameters. */
103 static struct seginfo *
104 new_seginfo (int mode, rtx insn, int bb, HARD_REG_SET regs_live)
107 ptr = XNEW (struct seginfo);
109 ptr->insn_ptr = insn;
112 COPY_HARD_REG_SET (ptr->regs_live, regs_live);
116 /* Add a seginfo element to the end of a list.
117 HEAD is a pointer to the list beginning.
118 INFO is the structure to be linked in. */
121 add_seginfo (struct bb_info *head, struct seginfo *info)
125 if (head->seginfo == NULL)
126 head->seginfo = info;
130 while (ptr->next != NULL)
136 /* Make all predecessors of basic block B opaque, recursively, till we hit
137 some that are already non-transparent, or an edge where aux is set; that
138 denotes that a mode set is to be done on that edge.
139 J is the bit number in the bitmaps that corresponds to the entity that
140 we are currently handling mode-switching for. */
143 make_preds_opaque (basic_block b, int j)
148 FOR_EACH_EDGE (e, ei, b->preds)
150 basic_block pb = e->src;
152 if (e->aux || ! TEST_BIT (transp[pb->index], j))
155 RESET_BIT (transp[pb->index], j);
156 make_preds_opaque (pb, j);
160 /* Record in LIVE that register REG died. */
163 reg_dies (rtx reg, HARD_REG_SET *live)
171 if (regno < FIRST_PSEUDO_REGISTER)
172 remove_from_hard_reg_set (live, GET_MODE (reg), regno);
175 /* Record in LIVE that register REG became live.
176 This is called via note_stores. */
179 reg_becomes_live (rtx reg, rtx setter ATTRIBUTE_UNUSED, void *live)
183 if (GET_CODE (reg) == SUBREG)
184 reg = SUBREG_REG (reg);
190 if (regno < FIRST_PSEUDO_REGISTER)
191 add_to_hard_reg_set ((HARD_REG_SET *) live, GET_MODE (reg), regno);
194 /* Make sure if MODE_ENTRY is defined the MODE_EXIT is defined
196 #if defined (MODE_ENTRY) != defined (MODE_EXIT)
197 #error "Both MODE_ENTRY and MODE_EXIT must be defined"
200 #if defined (MODE_ENTRY) && defined (MODE_EXIT)
201 /* Split the fallthrough edge to the exit block, so that we can note
202 that there NORMAL_MODE is required. Return the new block if it's
203 inserted before the exit block. Otherwise return null. */
206 create_pre_exit (int n_entities, int *entity_map, const int *num_modes)
210 basic_block pre_exit;
212 /* The only non-call predecessor at this stage is a block with a
213 fallthrough edge; there can be at most one, but there could be
214 none at all, e.g. when exit is called. */
216 FOR_EACH_EDGE (eg, ei, EXIT_BLOCK_PTR->preds)
217 if (eg->flags & EDGE_FALLTHRU)
219 basic_block src_bb = eg->src;
220 rtx last_insn, ret_reg;
222 gcc_assert (!pre_exit);
223 /* If this function returns a value at the end, we have to
224 insert the final mode switch before the return value copy
225 to its hard register. */
226 if (EDGE_COUNT (EXIT_BLOCK_PTR->preds) == 1
227 && NONJUMP_INSN_P ((last_insn = BB_END (src_bb)))
228 && GET_CODE (PATTERN (last_insn)) == USE
229 && GET_CODE ((ret_reg = XEXP (PATTERN (last_insn), 0))) == REG)
231 int ret_start = REGNO (ret_reg);
232 int nregs = hard_regno_nregs[ret_start][GET_MODE (ret_reg)];
233 int ret_end = ret_start + nregs;
235 int maybe_builtin_apply = 0;
236 int forced_late_switch = 0;
237 rtx before_return_copy;
241 rtx return_copy = PREV_INSN (last_insn);
242 rtx return_copy_pat, copy_reg;
243 int copy_start, copy_num;
246 if (INSN_P (return_copy))
248 return_copy_pat = PATTERN (return_copy);
249 switch (GET_CODE (return_copy_pat))
252 /* Skip __builtin_apply pattern. */
253 if (GET_CODE (XEXP (return_copy_pat, 0)) == REG
254 && (FUNCTION_VALUE_REGNO_P
255 (REGNO (XEXP (return_copy_pat, 0)))))
257 maybe_builtin_apply = 1;
258 last_insn = return_copy;
264 /* Skip barrier insns. */
265 if (!MEM_VOLATILE_P (return_copy_pat))
271 case UNSPEC_VOLATILE:
272 last_insn = return_copy;
279 /* If the return register is not (in its entirety)
280 likely spilled, the return copy might be
281 partially or completely optimized away. */
282 return_copy_pat = single_set (return_copy);
283 if (!return_copy_pat)
285 return_copy_pat = PATTERN (return_copy);
286 if (GET_CODE (return_copy_pat) != CLOBBER)
290 /* This might be (clobber (reg [<result>]))
291 when not optimizing. Then check if
292 the previous insn is the clobber for
293 the return register. */
294 copy_reg = SET_DEST (return_copy_pat);
295 if (GET_CODE (copy_reg) == REG
296 && !HARD_REGISTER_NUM_P (REGNO (copy_reg)))
298 if (INSN_P (PREV_INSN (return_copy)))
300 return_copy = PREV_INSN (return_copy);
301 return_copy_pat = PATTERN (return_copy);
302 if (GET_CODE (return_copy_pat) != CLOBBER)
308 copy_reg = SET_DEST (return_copy_pat);
309 if (GET_CODE (copy_reg) == REG)
310 copy_start = REGNO (copy_reg);
311 else if (GET_CODE (copy_reg) == SUBREG
312 && GET_CODE (SUBREG_REG (copy_reg)) == REG)
313 copy_start = REGNO (SUBREG_REG (copy_reg));
316 if (copy_start >= FIRST_PSEUDO_REGISTER)
319 = hard_regno_nregs[copy_start][GET_MODE (copy_reg)];
321 /* If the return register is not likely spilled, - as is
322 the case for floating point on SH4 - then it might
323 be set by an arithmetic operation that needs a
324 different mode than the exit block. */
325 for (j = n_entities - 1; j >= 0; j--)
327 int e = entity_map[j];
328 int mode = MODE_NEEDED (e, return_copy);
330 if (mode != num_modes[e] && mode != MODE_EXIT (e))
335 /* For the SH4, floating point loads depend on fpscr,
336 thus we might need to put the final mode switch
337 after the return value copy. That is still OK,
338 because a floating point return value does not
339 conflict with address reloads. */
340 if (copy_start >= ret_start
341 && copy_start + copy_num <= ret_end
342 && OBJECT_P (SET_SRC (return_copy_pat)))
343 forced_late_switch = 1;
347 if (copy_start >= ret_start
348 && copy_start + copy_num <= ret_end)
350 else if (!maybe_builtin_apply
351 || !FUNCTION_VALUE_REGNO_P (copy_start))
353 last_insn = return_copy;
355 /* ??? Exception handling can lead to the return value
356 copy being already separated from the return value use,
358 Similarly, conditionally returning without a value,
359 and conditionally using builtin_return can lead to an
361 if (return_copy == BB_HEAD (src_bb))
366 last_insn = return_copy;
370 /* If we didn't see a full return value copy, verify that there
371 is a plausible reason for this. If some, but not all of the
372 return register is likely spilled, we can expect that there
373 is a copy for the likely spilled part. */
375 || forced_late_switch
377 || !(CLASS_LIKELY_SPILLED_P
378 (REGNO_REG_CLASS (ret_start)))
380 != hard_regno_nregs[ret_start][GET_MODE (ret_reg)])
381 /* For multi-hard-register floating point
382 values, sometimes the likely-spilled part
383 is ordinarily copied first, then the other
384 part is set with an arithmetic operation.
385 This doesn't actually cause reload
386 failures, so let it pass. */
387 || (GET_MODE_CLASS (GET_MODE (ret_reg)) != MODE_INT
390 if (INSN_P (last_insn))
393 = emit_note_before (NOTE_INSN_DELETED, last_insn);
394 /* Instructions preceding LAST_INSN in the same block might
395 require a different mode than MODE_EXIT, so if we might
396 have such instructions, keep them in a separate block
398 if (last_insn != BB_HEAD (src_bb))
399 src_bb = split_block (src_bb,
400 PREV_INSN (before_return_copy))->dest;
403 before_return_copy = last_insn;
404 pre_exit = split_block (src_bb, before_return_copy)->src;
408 pre_exit = split_edge (eg);
416 /* Find all insns that need a particular mode setting, and insert the
417 necessary mode switches. Return true if we did work. */
420 optimize_mode_switching (void)
427 struct edge_list *edge_list;
428 static const int num_modes[] = NUM_MODES_FOR_MODE_SWITCHING;
429 #define N_ENTITIES ARRAY_SIZE (num_modes)
430 int entity_map[N_ENTITIES];
431 struct bb_info *bb_info[N_ENTITIES];
434 int max_num_modes = 0;
436 basic_block post_entry ATTRIBUTE_UNUSED, pre_exit ATTRIBUTE_UNUSED;
438 for (e = N_ENTITIES - 1, n_entities = 0; e >= 0; e--)
439 if (OPTIMIZE_MODE_SWITCHING (e))
441 int entry_exit_extra = 0;
443 /* Create the list of segments within each basic block.
444 If NORMAL_MODE is defined, allow for two extra
445 blocks split from the entry and exit block. */
446 #if defined (MODE_ENTRY) && defined (MODE_EXIT)
447 entry_exit_extra = 3;
450 = XCNEWVEC (struct bb_info, last_basic_block + entry_exit_extra);
451 entity_map[n_entities++] = e;
452 if (num_modes[e] > max_num_modes)
453 max_num_modes = num_modes[e];
459 #if defined (MODE_ENTRY) && defined (MODE_EXIT)
460 /* Split the edge from the entry block, so that we can note that
461 there NORMAL_MODE is supplied. */
462 post_entry = split_edge (single_succ_edge (ENTRY_BLOCK_PTR));
463 pre_exit = create_pre_exit (n_entities, entity_map, num_modes);
468 /* Create the bitmap vectors. */
470 antic = sbitmap_vector_alloc (last_basic_block, n_entities);
471 transp = sbitmap_vector_alloc (last_basic_block, n_entities);
472 comp = sbitmap_vector_alloc (last_basic_block, n_entities);
474 sbitmap_vector_ones (transp, last_basic_block);
476 for (j = n_entities - 1; j >= 0; j--)
478 int e = entity_map[j];
479 int no_mode = num_modes[e];
480 struct bb_info *info = bb_info[j];
482 /* Determine what the first use (if any) need for a mode of entity E is.
483 This will be the mode that is anticipatable for this block.
484 Also compute the initial transparency settings. */
488 int last_mode = no_mode;
489 HARD_REG_SET live_now;
491 REG_SET_TO_HARD_REG_SET (live_now, df_get_live_in (bb));
493 /* Pretend the mode is clobbered across abnormal edges. */
497 FOR_EACH_EDGE (e, ei, bb->preds)
498 if (e->flags & EDGE_COMPLEX)
502 ptr = new_seginfo (no_mode, BB_HEAD (bb), bb->index, live_now);
503 add_seginfo (info + bb->index, ptr);
504 RESET_BIT (transp[bb->index], j);
508 for (insn = BB_HEAD (bb);
509 insn != NULL && insn != NEXT_INSN (BB_END (bb));
510 insn = NEXT_INSN (insn))
514 int mode = MODE_NEEDED (e, insn);
517 if (mode != no_mode && mode != last_mode)
520 ptr = new_seginfo (mode, insn, bb->index, live_now);
521 add_seginfo (info + bb->index, ptr);
522 RESET_BIT (transp[bb->index], j);
525 last_mode = MODE_AFTER (last_mode, insn);
527 /* Update LIVE_NOW. */
528 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
529 if (REG_NOTE_KIND (link) == REG_DEAD)
530 reg_dies (XEXP (link, 0), &live_now);
532 note_stores (PATTERN (insn), reg_becomes_live, &live_now);
533 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
534 if (REG_NOTE_KIND (link) == REG_UNUSED)
535 reg_dies (XEXP (link, 0), &live_now);
539 info[bb->index].computing = last_mode;
540 /* Check for blocks without ANY mode requirements. */
541 if (last_mode == no_mode)
543 ptr = new_seginfo (no_mode, BB_END (bb), bb->index, live_now);
544 add_seginfo (info + bb->index, ptr);
547 #if defined (MODE_ENTRY) && defined (MODE_EXIT)
549 int mode = MODE_ENTRY (e);
555 /* By always making this nontransparent, we save
556 an extra check in make_preds_opaque. We also
557 need this to avoid confusing pre_edge_lcm when
558 antic is cleared but transp and comp are set. */
559 RESET_BIT (transp[bb->index], j);
561 /* Insert a fake computing definition of MODE into entry
562 blocks which compute no mode. This represents the mode on
564 info[bb->index].computing = mode;
567 info[pre_exit->index].seginfo->mode = MODE_EXIT (e);
570 #endif /* NORMAL_MODE */
573 kill = sbitmap_vector_alloc (last_basic_block, n_entities);
574 for (i = 0; i < max_num_modes; i++)
576 int current_mode[N_ENTITIES];
580 /* Set the anticipatable and computing arrays. */
581 sbitmap_vector_zero (antic, last_basic_block);
582 sbitmap_vector_zero (comp, last_basic_block);
583 for (j = n_entities - 1; j >= 0; j--)
585 int m = current_mode[j] = MODE_PRIORITY_TO_MODE (entity_map[j], i);
586 struct bb_info *info = bb_info[j];
590 if (info[bb->index].seginfo->mode == m)
591 SET_BIT (antic[bb->index], j);
593 if (info[bb->index].computing == m)
594 SET_BIT (comp[bb->index], j);
598 /* Calculate the optimal locations for the
599 placement mode switches to modes with priority I. */
602 sbitmap_not (kill[bb->index], transp[bb->index]);
603 edge_list = pre_edge_lcm (n_entities, transp, comp, antic,
604 kill, &insert, &delete);
606 for (j = n_entities - 1; j >= 0; j--)
608 /* Insert all mode sets that have been inserted by lcm. */
609 int no_mode = num_modes[entity_map[j]];
611 /* Wherever we have moved a mode setting upwards in the flow graph,
612 the blocks between the new setting site and the now redundant
613 computation ceases to be transparent for any lower-priority
614 mode of the same entity. First set the aux field of each
615 insertion site edge non-transparent, then propagate the new
616 non-transparency from the redundant computation upwards till
617 we hit an insertion site or an already non-transparent block. */
618 for (e = NUM_EDGES (edge_list) - 1; e >= 0; e--)
620 edge eg = INDEX_EDGE (edge_list, e);
623 HARD_REG_SET live_at_edge;
628 if (! TEST_BIT (insert[e], j))
633 mode = current_mode[j];
636 REG_SET_TO_HARD_REG_SET (live_at_edge, df_get_live_out (src_bb));
639 EMIT_MODE_SET (entity_map[j], mode, live_at_edge);
640 mode_set = get_insns ();
643 /* Do not bother to insert empty sequence. */
644 if (mode_set == NULL_RTX)
647 /* We should not get an abnormal edge here. */
648 gcc_assert (! (eg->flags & EDGE_ABNORMAL));
651 insert_insn_on_edge (mode_set, eg);
654 FOR_EACH_BB_REVERSE (bb)
655 if (TEST_BIT (delete[bb->index], j))
657 make_preds_opaque (bb, j);
658 /* Cancel the 'deleted' mode set. */
659 bb_info[j][bb->index].seginfo->mode = no_mode;
663 sbitmap_vector_free (delete);
664 sbitmap_vector_free (insert);
665 clear_aux_for_edges ();
666 free_edge_list (edge_list);
669 /* Now output the remaining mode sets in all the segments. */
670 for (j = n_entities - 1; j >= 0; j--)
672 int no_mode = num_modes[entity_map[j]];
674 FOR_EACH_BB_REVERSE (bb)
676 struct seginfo *ptr, *next;
677 for (ptr = bb_info[j][bb->index].seginfo; ptr; ptr = next)
680 if (ptr->mode != no_mode)
685 EMIT_MODE_SET (entity_map[j], ptr->mode, ptr->regs_live);
686 mode_set = get_insns ();
689 /* Insert MODE_SET only if it is nonempty. */
690 if (mode_set != NULL_RTX)
693 if (NOTE_INSN_BASIC_BLOCK_P (ptr->insn_ptr))
694 emit_insn_after (mode_set, ptr->insn_ptr);
696 emit_insn_before (mode_set, ptr->insn_ptr);
707 /* Finished. Free up all the things we've allocated. */
708 sbitmap_vector_free (kill);
709 sbitmap_vector_free (antic);
710 sbitmap_vector_free (transp);
711 sbitmap_vector_free (comp);
714 commit_edge_insertions ();
716 #if defined (MODE_ENTRY) && defined (MODE_EXIT)
717 cleanup_cfg (CLEANUP_NO_INSN_DEL);
719 if (!need_commit && !emited)
726 #endif /* OPTIMIZE_MODE_SWITCHING */
729 gate_mode_switching (void)
731 #ifdef OPTIMIZE_MODE_SWITCHING
739 rest_of_handle_mode_switching (void)
741 #ifdef OPTIMIZE_MODE_SWITCHING
742 optimize_mode_switching ();
743 #endif /* OPTIMIZE_MODE_SWITCHING */
748 struct tree_opt_pass pass_mode_switching =
750 "mode-sw", /* name */
751 gate_mode_switching, /* gate */
752 rest_of_handle_mode_switching, /* execute */
755 0, /* static_pass_number */
756 TV_MODE_SWITCH, /* tv_id */
757 0, /* properties_required */
758 0, /* properties_provided */
759 0, /* properties_destroyed */
760 0, /* todo_flags_start */
762 TODO_dump_func, /* todo_flags_finish */