1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 88, 91, 93, 94, 95, 1996 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Allocation of hard register numbers to pseudo registers is done in
23 two passes. In this pass we consider only regs that are born and
24 die once within one basic block. We do this one basic block at a
25 time. Then the next pass allocates the registers that remain.
26 Two passes are used because this pass uses methods that work only
27 on linear code, but that do a better job than the general methods
28 used in global_alloc, and more quickly too.
30 The assignments made are recorded in the vector reg_renumber
31 whose space is allocated here. The rtl code itself is not altered.
33 We assign each instruction in the basic block a number
34 which is its order from the beginning of the block.
35 Then we can represent the lifetime of a pseudo register with
36 a pair of numbers, and check for conflicts easily.
37 We can record the availability of hard registers with a
38 HARD_REG_SET for each instruction. The HARD_REG_SET
39 contains 0 or 1 for each hard reg.
41 To avoid register shuffling, we tie registers together when one
42 dies by being copied into another, or dies in an instruction that
43 does arithmetic to produce another. The tied registers are
44 allocated as one. Registers with different reg class preferences
45 can never be tied unless the class preferred by one is a subclass
46 of the one preferred by the other.
48 Tying is represented with "quantity numbers".
49 A non-tied register is given a new quantity number.
50 Tied registers have the same quantity number.
52 We have provision to exempt registers, even when they are contained
53 within the block, that can be tied to others that are not contained in it.
54 This is so that global_alloc could process them both and tie them then.
55 But this is currently disabled since tying in global_alloc is not
58 /* Pseudos allocated here cannot be reallocated by global.c if the hard
59 register is used as a spill register. So we don't allocate such pseudos
60 here if their preferred class is likely to be used by spills. */
66 #include "basic-block.h"
68 #include "hard-reg-set.h"
69 #include "insn-config.h"
73 /* Next quantity number available for allocation. */
77 /* In all the following vectors indexed by quantity number. */
79 /* Element Q is the hard reg number chosen for quantity Q,
80 or -1 if none was found. */
82 static short *qty_phys_reg;
84 /* We maintain two hard register sets that indicate suggested hard registers
85 for each quantity. The first, qty_phys_copy_sugg, contains hard registers
86 that are tied to the quantity by a simple copy. The second contains all
87 hard registers that are tied to the quantity via an arithmetic operation.
89 The former register set is given priority for allocation. This tends to
90 eliminate copy insns. */
92 /* Element Q is a set of hard registers that are suggested for quantity Q by
95 static HARD_REG_SET *qty_phys_copy_sugg;
97 /* Element Q is a set of hard registers that are suggested for quantity Q by
100 static HARD_REG_SET *qty_phys_sugg;
102 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
104 static short *qty_phys_num_copy_sugg;
106 /* Element Q is the number of suggested registers in qty_phys_sugg. */
108 static short *qty_phys_num_sugg;
110 /* Element Q is the number of refs to quantity Q. */
112 static int *qty_n_refs;
114 /* Element Q is a reg class contained in (smaller than) the
115 preferred classes of all the pseudo regs that are tied in quantity Q.
116 This is the preferred class for allocating that quantity. */
118 static enum reg_class *qty_min_class;
120 /* Insn number (counting from head of basic block)
121 where quantity Q was born. -1 if birth has not been recorded. */
123 static int *qty_birth;
125 /* Insn number (counting from head of basic block)
126 where quantity Q died. Due to the way tying is done,
127 and the fact that we consider in this pass only regs that die but once,
128 a quantity can die only once. Each quantity's life span
129 is a set of consecutive insns. -1 if death has not been recorded. */
131 static int *qty_death;
133 /* Number of words needed to hold the data in quantity Q.
134 This depends on its machine mode. It is used for these purposes:
135 1. It is used in computing the relative importances of qtys,
136 which determines the order in which we look for regs for them.
137 2. It is used in rules that prevent tying several registers of
138 different sizes in a way that is geometrically impossible
139 (see combine_regs). */
141 static int *qty_size;
143 /* This holds the mode of the registers that are tied to qty Q,
144 or VOIDmode if registers with differing modes are tied together. */
146 static enum machine_mode *qty_mode;
148 /* Number of times a reg tied to qty Q lives across a CALL_INSN. */
150 static int *qty_n_calls_crossed;
152 /* Register class within which we allocate qty Q if we can't get
153 its preferred class. */
155 static enum reg_class *qty_alternate_class;
157 /* Element Q is the SCRATCH expression for which this quantity is being
158 allocated or 0 if this quantity is allocating registers. */
160 static rtx *qty_scratch_rtx;
162 /* Element Q is nonzero if this quantity has been used in a SUBREG
163 that changes its size. */
165 static char *qty_changes_size;
167 /* Element Q is the register number of one pseudo register whose
168 reg_qty value is Q, or -1 is this quantity is for a SCRATCH. This
169 register should be the head of the chain maintained in reg_next_in_qty. */
171 static int *qty_first_reg;
173 /* If (REG N) has been assigned a quantity number, is a register number
174 of another register assigned the same quantity number, or -1 for the
175 end of the chain. qty_first_reg point to the head of this chain. */
177 static int *reg_next_in_qty;
179 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
181 of -1 if this register cannot be allocated by local-alloc,
182 or -2 if not known yet.
184 Note that if we see a use or death of pseudo register N with
185 reg_qty[N] == -2, register N must be local to the current block. If
186 it were used in more than one block, we would have reg_qty[N] == -1.
187 This relies on the fact that if reg_basic_block[N] is >= 0, register N
188 will not appear in any other block. We save a considerable number of
189 tests by exploiting this.
191 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
196 /* The offset (in words) of register N within its quantity.
197 This can be nonzero if register N is SImode, and has been tied
198 to a subreg of a DImode register. */
200 static char *reg_offset;
202 /* Vector of substitutions of register numbers,
203 used to map pseudo regs into hardware regs.
204 This is set up as a result of register allocation.
205 Element N is the hard reg assigned to pseudo reg N,
206 or is -1 if no hard reg was assigned.
207 If N is a hard reg number, element N is N. */
211 /* Set of hard registers live at the current point in the scan
212 of the instructions in a basic block. */
214 static HARD_REG_SET regs_live;
216 /* Each set of hard registers indicates registers live at a particular
217 point in the basic block. For N even, regs_live_at[N] says which
218 hard registers are needed *after* insn N/2 (i.e., they may not
219 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
221 If an object is to conflict with the inputs of insn J but not the
222 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
223 if it is to conflict with the outputs of insn J but not the inputs of
224 insn J + 1, it is said to die at index J*2 + 1. */
226 static HARD_REG_SET *regs_live_at;
230 int scratch_list_length;
231 static int scratch_index;
233 /* Communicate local vars `insn_number' and `insn'
234 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
235 static int this_insn_number;
236 static rtx this_insn;
238 /* Used to communicate changes made by update_equiv_regs to
239 memref_referenced_p. reg_equiv_replacement is set for any REG_EQUIV note
240 found or created, so that we can keep track of what memory accesses might
241 be created later, e.g. by reload. */
243 static rtx *reg_equiv_replacement;
245 static void alloc_qty PROTO((int, enum machine_mode, int, int));
246 static void alloc_qty_for_scratch PROTO((rtx, int, rtx, int, int));
247 static void validate_equiv_mem_from_store PROTO((rtx, rtx));
248 static int validate_equiv_mem PROTO((rtx, rtx, rtx));
249 static int memref_referenced_p PROTO((rtx, rtx));
250 static int memref_used_between_p PROTO((rtx, rtx, rtx));
251 static void optimize_reg_copy_1 PROTO((rtx, rtx, rtx));
252 static void optimize_reg_copy_2 PROTO((rtx, rtx, rtx));
253 static void update_equiv_regs PROTO((void));
254 static void block_alloc PROTO((int));
255 static int qty_sugg_compare PROTO((int, int));
256 static int qty_sugg_compare_1 PROTO((const GENERIC_PTR, const GENERIC_PTR));
257 static int qty_compare PROTO((int, int));
258 static int qty_compare_1 PROTO((const GENERIC_PTR, const GENERIC_PTR));
259 static int combine_regs PROTO((rtx, rtx, int, int, rtx, int));
260 static int reg_meets_class_p PROTO((int, enum reg_class));
261 static int reg_classes_overlap_p PROTO((enum reg_class, enum reg_class,
263 static void update_qty_class PROTO((int, int));
264 static void reg_is_set PROTO((rtx, rtx));
265 static void reg_is_born PROTO((rtx, int));
266 static void wipe_dead_reg PROTO((rtx, int));
267 static int find_free_reg PROTO((enum reg_class, enum machine_mode,
268 int, int, int, int, int));
269 static void mark_life PROTO((int, enum machine_mode, int));
270 static void post_mark_life PROTO((int, enum machine_mode, int, int, int));
271 static int no_conflict_p PROTO((rtx, rtx, rtx));
272 static int requires_inout PROTO((char *));
274 /* Allocate a new quantity (new within current basic block)
275 for register number REGNO which is born at index BIRTH
276 within the block. MODE and SIZE are info on reg REGNO. */
279 alloc_qty (regno, mode, size, birth)
281 enum machine_mode mode;
284 register int qty = next_qty++;
286 reg_qty[regno] = qty;
287 reg_offset[regno] = 0;
288 reg_next_in_qty[regno] = -1;
290 qty_first_reg[qty] = regno;
291 qty_size[qty] = size;
292 qty_mode[qty] = mode;
293 qty_birth[qty] = birth;
294 qty_n_calls_crossed[qty] = reg_n_calls_crossed[regno];
295 qty_min_class[qty] = reg_preferred_class (regno);
296 qty_alternate_class[qty] = reg_alternate_class (regno);
297 qty_n_refs[qty] = reg_n_refs[regno];
298 qty_changes_size[qty] = reg_changes_size[regno];
301 /* Similar to `alloc_qty', but allocates a quantity for a SCRATCH rtx
302 used as operand N in INSN. We assume here that the SCRATCH is used in
306 alloc_qty_for_scratch (scratch, n, insn, insn_code_num, insn_number)
310 int insn_code_num, insn_number;
313 enum reg_class class;
317 #ifdef REGISTER_CONSTRAINTS
318 /* If we haven't yet computed which alternative will be used, do so now.
319 Then set P to the constraints for that alternative. */
320 if (which_alternative == -1)
321 if (! constrain_operands (insn_code_num, 0))
324 for (p = insn_operand_constraint[insn_code_num][n], i = 0;
325 *p && i < which_alternative; p++)
329 /* Compute the class required for this SCRATCH. If we don't need a
330 register, the class will remain NO_REGS. If we guessed the alternative
331 number incorrectly, reload will fix things up for us. */
334 while ((c = *p++) != '\0' && c != ',')
337 case '=': case '+': case '?':
338 case '#': case '&': case '!':
340 case '0': case '1': case '2': case '3': case '4':
341 case 'm': case '<': case '>': case 'V': case 'o':
342 case 'E': case 'F': case 'G': case 'H':
343 case 's': case 'i': case 'n':
344 case 'I': case 'J': case 'K': case 'L':
345 case 'M': case 'N': case 'O': case 'P':
346 #ifdef EXTRA_CONSTRAINT
347 case 'Q': case 'R': case 'S': case 'T': case 'U':
350 /* These don't say anything we care about. */
354 /* We don't need to allocate this SCRATCH. */
358 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
363 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER (c)];
367 if (class == NO_REGS)
370 #else /* REGISTER_CONSTRAINTS */
372 class = GENERAL_REGS;
378 qty_first_reg[qty] = -1;
379 qty_scratch_rtx[qty] = scratch;
380 qty_size[qty] = GET_MODE_SIZE (GET_MODE (scratch));
381 qty_mode[qty] = GET_MODE (scratch);
382 qty_birth[qty] = 2 * insn_number - 1;
383 qty_death[qty] = 2 * insn_number + 1;
384 qty_n_calls_crossed[qty] = 0;
385 qty_min_class[qty] = class;
386 qty_alternate_class[qty] = NO_REGS;
388 qty_changes_size[qty] = 0;
391 /* Main entry point of this file. */
399 /* Leaf functions and non-leaf functions have different needs.
400 If defined, let the machine say what kind of ordering we
402 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
403 ORDER_REGS_FOR_LOCAL_ALLOC;
406 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
408 update_equiv_regs ();
410 /* This sets the maximum number of quantities we can have. Quantity
411 numbers start at zero and we can have one for each pseudo plus the
412 number of SCRATCHes in the largest block, in the worst case. */
413 max_qty = (max_regno - FIRST_PSEUDO_REGISTER) + max_scratch;
415 /* Allocate vectors of temporary data.
416 See the declarations of these variables, above,
417 for what they mean. */
419 /* There can be up to MAX_SCRATCH * N_BASIC_BLOCKS SCRATCHes to allocate.
420 Instead of allocating this much memory from now until the end of
421 reload, only allocate space for MAX_QTY SCRATCHes. If there are more
422 reload will allocate them. */
424 scratch_list_length = max_qty;
425 scratch_list = (rtx *) xmalloc (scratch_list_length * sizeof (rtx));
426 bzero ((char *) scratch_list, scratch_list_length * sizeof (rtx));
427 scratch_block = (int *) xmalloc (scratch_list_length * sizeof (int));
428 bzero ((char *) scratch_block, scratch_list_length * sizeof (int));
431 qty_phys_reg = (short *) alloca (max_qty * sizeof (short));
433 = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
434 qty_phys_num_copy_sugg = (short *) alloca (max_qty * sizeof (short));
435 qty_phys_sugg = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
436 qty_phys_num_sugg = (short *) alloca (max_qty * sizeof (short));
437 qty_birth = (int *) alloca (max_qty * sizeof (int));
438 qty_death = (int *) alloca (max_qty * sizeof (int));
439 qty_scratch_rtx = (rtx *) alloca (max_qty * sizeof (rtx));
440 qty_first_reg = (int *) alloca (max_qty * sizeof (int));
441 qty_size = (int *) alloca (max_qty * sizeof (int));
443 = (enum machine_mode *) alloca (max_qty * sizeof (enum machine_mode));
444 qty_n_calls_crossed = (int *) alloca (max_qty * sizeof (int));
446 = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
448 = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
449 qty_n_refs = (int *) alloca (max_qty * sizeof (int));
450 qty_changes_size = (char *) alloca (max_qty * sizeof (char));
452 reg_qty = (int *) alloca (max_regno * sizeof (int));
453 reg_offset = (char *) alloca (max_regno * sizeof (char));
454 reg_next_in_qty = (int *) alloca (max_regno * sizeof (int));
456 reg_renumber = (short *) oballoc (max_regno * sizeof (short));
457 for (i = 0; i < max_regno; i++)
458 reg_renumber[i] = -1;
460 /* Determine which pseudo-registers can be allocated by local-alloc.
461 In general, these are the registers used only in a single block and
462 which only die once. However, if a register's preferred class has only
463 a few entries, don't allocate this register here unless it is preferred
464 or nothing since retry_global_alloc won't be able to move it to
465 GENERAL_REGS if a reload register of this class is needed.
467 We need not be concerned with which block actually uses the register
468 since we will never see it outside that block. */
470 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
472 if (reg_basic_block[i] >= 0 && reg_n_deaths[i] == 1
473 && (reg_alternate_class (i) == NO_REGS
474 || ! CLASS_LIKELY_SPILLED_P (reg_preferred_class (i))))
480 /* Force loop below to initialize entire quantity array. */
483 /* Allocate each block's local registers, block by block. */
485 for (b = 0; b < n_basic_blocks; b++)
487 /* NEXT_QTY indicates which elements of the `qty_...'
488 vectors might need to be initialized because they were used
489 for the previous block; it is set to the entire array before
490 block 0. Initialize those, with explicit loop if there are few,
491 else with bzero and bcopy. Do not initialize vectors that are
492 explicit set by `alloc_qty'. */
496 for (i = 0; i < next_qty; i++)
498 qty_scratch_rtx[i] = 0;
499 CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]);
500 qty_phys_num_copy_sugg[i] = 0;
501 CLEAR_HARD_REG_SET (qty_phys_sugg[i]);
502 qty_phys_num_sugg[i] = 0;
507 #define CLEAR(vector) \
508 bzero ((char *) (vector), (sizeof (*(vector))) * next_qty);
510 CLEAR (qty_scratch_rtx);
511 CLEAR (qty_phys_copy_sugg);
512 CLEAR (qty_phys_num_copy_sugg);
513 CLEAR (qty_phys_sugg);
514 CLEAR (qty_phys_num_sugg);
526 /* Depth of loops we are in while in update_equiv_regs. */
527 static int loop_depth;
529 /* Used for communication between the following two functions: contains
530 a MEM that we wish to ensure remains unchanged. */
531 static rtx equiv_mem;
533 /* Set nonzero if EQUIV_MEM is modified. */
534 static int equiv_mem_modified;
536 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
537 Called via note_stores. */
540 validate_equiv_mem_from_store (dest, set)
544 if ((GET_CODE (dest) == REG
545 && reg_overlap_mentioned_p (dest, equiv_mem))
546 || (GET_CODE (dest) == MEM
547 && true_dependence (dest, equiv_mem)))
548 equiv_mem_modified = 1;
551 /* Verify that no store between START and the death of REG invalidates
552 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
553 by storing into an overlapping memory location, or with a non-const
556 Return 1 if MEMREF remains valid. */
559 validate_equiv_mem (start, reg, memref)
568 equiv_mem_modified = 0;
570 /* If the memory reference has side effects or is volatile, it isn't a
571 valid equivalence. */
572 if (side_effects_p (memref))
575 for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn))
577 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
580 if (find_reg_note (insn, REG_DEAD, reg))
583 if (GET_CODE (insn) == CALL_INSN && ! RTX_UNCHANGING_P (memref)
584 && ! CONST_CALL_P (insn))
587 note_stores (PATTERN (insn), validate_equiv_mem_from_store);
589 /* If a register mentioned in MEMREF is modified via an
590 auto-increment, we lose the equivalence. Do the same if one
591 dies; although we could extend the life, it doesn't seem worth
594 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
595 if ((REG_NOTE_KIND (note) == REG_INC
596 || REG_NOTE_KIND (note) == REG_DEAD)
597 && GET_CODE (XEXP (note, 0)) == REG
598 && reg_overlap_mentioned_p (XEXP (note, 0), memref))
605 /* TRUE if X references a memory location that would be affected by a store
609 memref_referenced_p (memref, x)
615 enum rtx_code code = GET_CODE (x);
631 return (reg_equiv_replacement[REGNO (x)]
632 && memref_referenced_p (memref,
633 reg_equiv_replacement[REGNO (x)]));
636 if (true_dependence (memref, x))
641 /* If we are setting a MEM, it doesn't count (its address does), but any
642 other SET_DEST that has a MEM in it is referencing the MEM. */
643 if (GET_CODE (SET_DEST (x)) == MEM)
645 if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0)))
648 else if (memref_referenced_p (memref, SET_DEST (x)))
651 return memref_referenced_p (memref, SET_SRC (x));
654 fmt = GET_RTX_FORMAT (code);
655 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
659 if (memref_referenced_p (memref, XEXP (x, i)))
663 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
664 if (memref_referenced_p (memref, XVECEXP (x, i, j)))
672 /* TRUE if some insn in the range (START, END] references a memory location
673 that would be affected by a store to MEMREF. */
676 memref_used_between_p (memref, start, end)
683 for (insn = NEXT_INSN (start); insn != NEXT_INSN (end);
684 insn = NEXT_INSN (insn))
685 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
686 && memref_referenced_p (memref, PATTERN (insn)))
692 /* INSN is a copy from SRC to DEST, both registers, and SRC does not die
695 Search forward to see if SRC dies before either it or DEST is modified,
696 but don't scan past the end of a basic block. If so, we can replace SRC
697 with DEST and let SRC die in INSN.
699 This will reduce the number of registers live in that range and may enable
700 DEST to be tied to SRC, thus often saving one register in addition to a
701 register-register copy. */
704 optimize_reg_copy_1 (insn, dest, src)
712 int sregno = REGNO (src);
713 int dregno = REGNO (dest);
716 #ifdef SMALL_REGISTER_CLASSES
717 /* We don't want to mess with hard regs if register classes are small. */
718 || (SMALL_REGISTER_CLASSES
719 && (sregno < FIRST_PSEUDO_REGISTER
720 || dregno < FIRST_PSEUDO_REGISTER))
722 /* We don't see all updates to SP if they are in an auto-inc memory
723 reference, so we must disallow this optimization on them. */
724 || sregno == STACK_POINTER_REGNUM || dregno == STACK_POINTER_REGNUM)
727 for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p))
729 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN
730 || (GET_CODE (p) == NOTE
731 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
732 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
735 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
738 if (reg_set_p (src, p) || reg_set_p (dest, p)
739 /* Don't change a USE of a register. */
740 || (GET_CODE (PATTERN (p)) == USE
741 && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0))))
744 /* See if all of SRC dies in P. This test is slightly more
745 conservative than it needs to be. */
746 if ((note = find_regno_note (p, REG_DEAD, sregno)) != 0
747 && GET_MODE (XEXP (note, 0)) == GET_MODE (src))
755 /* We can do the optimization. Scan forward from INSN again,
756 replacing regs as we go. Set FAILED if a replacement can't
757 be done. In that case, we can't move the death note for SRC.
758 This should be rare. */
760 /* Set to stop at next insn. */
761 for (q = next_real_insn (insn);
762 q != next_real_insn (p);
763 q = next_real_insn (q))
765 if (reg_overlap_mentioned_p (src, PATTERN (q)))
767 /* If SRC is a hard register, we might miss some
768 overlapping registers with validate_replace_rtx,
769 so we would have to undo it. We can't if DEST is
770 present in the insn, so fail in that combination
772 if (sregno < FIRST_PSEUDO_REGISTER
773 && reg_mentioned_p (dest, PATTERN (q)))
776 /* Replace all uses and make sure that the register
777 isn't still present. */
778 else if (validate_replace_rtx (src, dest, q)
779 && (sregno >= FIRST_PSEUDO_REGISTER
780 || ! reg_overlap_mentioned_p (src,
783 /* We assume that a register is used exactly once per
784 insn in the updates below. If this is not correct,
785 no great harm is done. */
786 if (sregno >= FIRST_PSEUDO_REGISTER)
787 reg_n_refs[sregno] -= loop_depth;
788 if (dregno >= FIRST_PSEUDO_REGISTER)
789 reg_n_refs[dregno] += loop_depth;
793 validate_replace_rtx (dest, src, q);
798 /* Count the insns and CALL_INSNs passed. If we passed the
799 death note of DEST, show increased live length. */
804 /* If the insn in which SRC dies is a CALL_INSN, don't count it
805 as a call that has been crossed. Otherwise, count it. */
806 if (q != p && GET_CODE (q) == CALL_INSN)
813 /* If DEST dies here, remove the death note and save it for
814 later. Make sure ALL of DEST dies here; again, this is
815 overly conservative. */
817 && (dest_death = find_regno_note (q, REG_DEAD, dregno)) != 0
818 && GET_MODE (XEXP (dest_death, 0)) == GET_MODE (dest))
819 remove_note (q, dest_death);
824 if (sregno >= FIRST_PSEUDO_REGISTER)
826 if (reg_live_length[sregno] >= 0)
828 reg_live_length[sregno] -= length;
829 /* reg_live_length is only an approximation after
830 combine if sched is not run, so make sure that we
831 still have a reasonable value. */
832 if (reg_live_length[sregno] < 2)
833 reg_live_length[sregno] = 2;
836 reg_n_calls_crossed[sregno] -= n_calls;
839 if (dregno >= FIRST_PSEUDO_REGISTER)
841 if (reg_live_length[dregno] >= 0)
842 reg_live_length[dregno] += d_length;
844 reg_n_calls_crossed[dregno] += d_n_calls;
847 /* Move death note of SRC from P to INSN. */
848 remove_note (p, note);
849 XEXP (note, 1) = REG_NOTES (insn);
850 REG_NOTES (insn) = note;
853 /* Put death note of DEST on P if we saw it die. */
856 XEXP (dest_death, 1) = REG_NOTES (p);
857 REG_NOTES (p) = dest_death;
863 /* If SRC is a hard register which is set or killed in some other
864 way, we can't do this optimization. */
865 else if (sregno < FIRST_PSEUDO_REGISTER
866 && dead_or_set_p (p, src))
871 /* INSN is a copy of SRC to DEST, in which SRC dies. See if we now have
872 a sequence of insns that modify DEST followed by an insn that sets
873 SRC to DEST in which DEST dies, with no prior modification of DEST.
874 (There is no need to check if the insns in between actually modify
875 DEST. We should not have cases where DEST is not modified, but
876 the optimization is safe if no such modification is detected.)
877 In that case, we can replace all uses of DEST, starting with INSN and
878 ending with the set of SRC to DEST, with SRC. We do not do this
879 optimization if a CALL_INSN is crossed unless SRC already crosses a
880 call or if DEST dies before the copy back to SRC.
882 It is assumed that DEST and SRC are pseudos; it is too complicated to do
883 this for hard registers since the substitutions we may make might fail. */
886 optimize_reg_copy_2 (insn, dest, src)
893 int sregno = REGNO (src);
894 int dregno = REGNO (dest);
896 for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p))
898 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN
899 || (GET_CODE (p) == NOTE
900 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
901 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
904 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
907 set = single_set (p);
908 if (set && SET_SRC (set) == dest && SET_DEST (set) == src
909 && find_reg_note (p, REG_DEAD, dest))
911 /* We can do the optimization. Scan forward from INSN again,
912 replacing regs as we go. */
914 /* Set to stop at next insn. */
915 for (q = insn; q != NEXT_INSN (p); q = NEXT_INSN (q))
916 if (GET_RTX_CLASS (GET_CODE (q)) == 'i')
918 if (reg_mentioned_p (dest, PATTERN (q)))
920 PATTERN (q) = replace_rtx (PATTERN (q), dest, src);
922 /* We assume that a register is used exactly once per
923 insn in the updates below. If this is not correct,
924 no great harm is done. */
925 reg_n_refs[dregno] -= loop_depth;
926 reg_n_refs[sregno] += loop_depth;
930 if (GET_CODE (q) == CALL_INSN)
932 reg_n_calls_crossed[dregno]--;
933 reg_n_calls_crossed[sregno]++;
937 remove_note (p, find_reg_note (p, REG_DEAD, dest));
938 reg_n_deaths[dregno]--;
939 remove_note (insn, find_reg_note (insn, REG_DEAD, src));
940 reg_n_deaths[sregno]--;
944 if (reg_set_p (src, p)
945 || find_reg_note (p, REG_DEAD, dest)
946 || (GET_CODE (p) == CALL_INSN && reg_n_calls_crossed[sregno] == 0))
951 /* Find registers that are equivalent to a single value throughout the
952 compilation (either because they can be referenced in memory or are set once
953 from a single constant). Lower their priority for a register.
955 If such a register is only referenced once, try substituting its value
956 into the using insn. If it succeeds, we can eliminate the register
962 rtx *reg_equiv_init_insn = (rtx *) alloca (max_regno * sizeof (rtx *));
963 /* Set when an attempt should be made to replace a register with the
964 associated reg_equiv_replacement entry at the end of this function. */
965 char *reg_equiv_replace
966 = (char *) alloca (max_regno * sizeof *reg_equiv_replace);
969 reg_equiv_replacement = (rtx *) alloca (max_regno * sizeof (rtx *));
971 bzero ((char *) reg_equiv_init_insn, max_regno * sizeof (rtx *));
972 bzero ((char *) reg_equiv_replacement, max_regno * sizeof (rtx *));
973 bzero ((char *) reg_equiv_replace, max_regno * sizeof *reg_equiv_replace);
975 init_alias_analysis ();
979 /* Scan the insns and find which registers have equivalences. Do this
980 in a separate scan of the insns because (due to -fcse-follow-jumps)
981 a register can be set below its use. */
982 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
985 rtx set = single_set (insn);
989 if (GET_CODE (insn) == NOTE)
991 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
993 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
997 /* If this insn contains more (or less) than a single SET, ignore it. */
1001 dest = SET_DEST (set);
1002 src = SET_SRC (set);
1004 /* If this sets a MEM to the contents of a REG that is only used
1005 in a single basic block, see if the register is always equivalent
1006 to that memory location and if moving the store from INSN to the
1007 insn that set REG is safe. If so, put a REG_EQUIV note on the
1008 initializing insn. */
1010 if (GET_CODE (dest) == MEM && GET_CODE (SET_SRC (set)) == REG
1011 && (regno = REGNO (SET_SRC (set))) >= FIRST_PSEUDO_REGISTER
1012 && reg_basic_block[regno] >= 0
1013 && reg_equiv_init_insn[regno] != 0
1014 && validate_equiv_mem (reg_equiv_init_insn[regno], SET_SRC (set),
1016 && ! memref_used_between_p (SET_DEST (set),
1017 reg_equiv_init_insn[regno], insn))
1018 REG_NOTES (reg_equiv_init_insn[regno])
1019 = gen_rtx (EXPR_LIST, REG_EQUIV, dest,
1020 REG_NOTES (reg_equiv_init_insn[regno]));
1022 /* If this is a register-register copy where SRC is not dead, see if we
1024 if (flag_expensive_optimizations && GET_CODE (dest) == REG
1025 && GET_CODE (SET_SRC (set)) == REG
1026 && ! find_reg_note (insn, REG_DEAD, SET_SRC (set)))
1027 optimize_reg_copy_1 (insn, dest, SET_SRC (set));
1029 /* Similarly for a pseudo-pseudo copy when SRC is dead. */
1030 else if (flag_expensive_optimizations && GET_CODE (dest) == REG
1031 && REGNO (dest) >= FIRST_PSEUDO_REGISTER
1032 && GET_CODE (SET_SRC (set)) == REG
1033 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER
1034 && find_reg_note (insn, REG_DEAD, SET_SRC (set)))
1035 optimize_reg_copy_2 (insn, dest, SET_SRC (set));
1037 /* Otherwise, we only handle the case of a pseudo register being set
1038 once and only if neither the source nor the destination are
1039 in a register class that's likely to be spilled. */
1040 if (GET_CODE (dest) != REG
1041 || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER
1042 || reg_n_sets[regno] != 1
1043 || CLASS_LIKELY_SPILLED_P (reg_preferred_class (REGNO (dest)))
1044 || (GET_CODE (src) == REG
1045 && REGNO (src) >= FIRST_PSEUDO_REGISTER
1046 && CLASS_LIKELY_SPILLED_P (reg_preferred_class (REGNO (src)))))
1049 note = find_reg_note (insn, REG_EQUAL, NULL_RTX);
1051 /* Record this insn as initializing this register. */
1052 reg_equiv_init_insn[regno] = insn;
1054 /* If this register is known to be equal to a constant, record that
1055 it is always equivalent to the constant. */
1056 if (note && CONSTANT_P (XEXP (note, 0)))
1057 PUT_MODE (note, (enum machine_mode) REG_EQUIV);
1059 /* If this insn introduces a "constant" register, decrease the priority
1060 of that register. Record this insn if the register is only used once
1061 more and the equivalence value is the same as our source.
1063 The latter condition is checked for two reasons: First, it is an
1064 indication that it may be more efficient to actually emit the insn
1065 as written (if no registers are available, reload will substitute
1066 the equivalence). Secondly, it avoids problems with any registers
1067 dying in this insn whose death notes would be missed.
1069 If we don't have a REG_EQUIV note, see if this insn is loading
1070 a register used only in one basic block from a MEM. If so, and the
1071 MEM remains unchanged for the life of the register, add a REG_EQUIV
1074 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
1076 if (note == 0 && reg_basic_block[regno] >= 0
1077 && GET_CODE (SET_SRC (set)) == MEM
1078 && validate_equiv_mem (insn, dest, SET_SRC (set)))
1079 REG_NOTES (insn) = note = gen_rtx (EXPR_LIST, REG_EQUIV, SET_SRC (set),
1084 int regno = REGNO (dest);
1086 reg_equiv_replacement[regno] = XEXP (note, 0);
1088 /* Don't mess with things live during setjmp. */
1089 if (reg_live_length[regno] >= 0)
1091 /* Note that the statement below does not affect the priority
1093 reg_live_length[regno] *= 2;
1096 /* If the register is referenced exactly twice, meaning it is
1097 set once and used once, indicate that the reference may be
1098 replaced by the equivalence we computed above. If the
1099 register is only used in one basic block, this can't succeed
1100 or combine would have done it.
1102 It would be nice to use "loop_depth * 2" in the compare
1103 below. Unfortunately, LOOP_DEPTH need not be constant within
1104 a basic block so this would be too complicated.
1106 This case normally occurs when a parameter is read from
1107 memory and then used exactly once, not in a loop. */
1109 if (reg_n_refs[regno] == 2
1110 && reg_basic_block[regno] < 0
1111 && rtx_equal_p (XEXP (note, 0), SET_SRC (set)))
1112 reg_equiv_replace[regno] = 1;
1117 /* Now scan all regs killed in an insn to see if any of them are registers
1118 only used that once. If so, see if we can replace the reference with
1119 the equivalent from. If we can, delete the initializing reference
1120 and this register will go away. */
1121 for (insn = next_active_insn (get_insns ());
1123 insn = next_active_insn (insn))
1127 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1128 if (REG_NOTE_KIND (link) == REG_DEAD
1129 /* Make sure this insn still refers to the register. */
1130 && reg_mentioned_p (XEXP (link, 0), PATTERN (insn)))
1132 int regno = REGNO (XEXP (link, 0));
1134 if (reg_equiv_replace[regno]
1135 && validate_replace_rtx (regno_reg_rtx[regno],
1136 reg_equiv_replacement[regno], insn))
1138 rtx equiv_insn = reg_equiv_init_insn[regno];
1140 remove_death (regno, insn);
1141 reg_n_refs[regno] = 0;
1142 PUT_CODE (equiv_insn, NOTE);
1143 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1144 NOTE_SOURCE_FILE (equiv_insn) = 0;
1150 /* Allocate hard regs to the pseudo regs used only within block number B.
1151 Only the pseudos that die but once can be handled. */
1160 int insn_number = 0;
1162 int max_uid = get_max_uid ();
1164 int no_conflict_combined_regno = -1;
1165 /* Counter to prevent allocating more SCRATCHes than can be stored
1167 int scratches_allocated = scratch_index;
1169 /* Count the instructions in the basic block. */
1171 insn = basic_block_end[b];
1174 if (GET_CODE (insn) != NOTE)
1175 if (++insn_count > max_uid)
1177 if (insn == basic_block_head[b])
1179 insn = PREV_INSN (insn);
1182 /* +2 to leave room for a post_mark_life at the last insn and for
1183 the birth of a CLOBBER in the first insn. */
1184 regs_live_at = (HARD_REG_SET *) alloca ((2 * insn_count + 2)
1185 * sizeof (HARD_REG_SET));
1186 bzero ((char *) regs_live_at, (2 * insn_count + 2) * sizeof (HARD_REG_SET));
1188 /* Initialize table of hardware registers currently live. */
1191 regs_live = *basic_block_live_at_start[b];
1193 COPY_HARD_REG_SET (regs_live, basic_block_live_at_start[b]);
1196 /* This loop scans the instructions of the basic block
1197 and assigns quantities to registers.
1198 It computes which registers to tie. */
1200 insn = basic_block_head[b];
1203 register rtx body = PATTERN (insn);
1205 if (GET_CODE (insn) != NOTE)
1208 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1210 register rtx link, set;
1211 register int win = 0;
1212 register rtx r0, r1;
1213 int combined_regno = -1;
1215 int insn_code_number = recog_memoized (insn);
1217 this_insn_number = insn_number;
1220 if (insn_code_number >= 0)
1221 insn_extract (insn);
1222 which_alternative = -1;
1224 /* Is this insn suitable for tying two registers?
1225 If so, try doing that.
1226 Suitable insns are those with at least two operands and where
1227 operand 0 is an output that is a register that is not
1230 We can tie operand 0 with some operand that dies in this insn.
1231 First look for operands that are required to be in the same
1232 register as operand 0. If we find such, only try tying that
1233 operand or one that can be put into that operand if the
1234 operation is commutative. If we don't find an operand
1235 that is required to be in the same register as operand 0,
1236 we can tie with any operand.
1238 Subregs in place of regs are also ok.
1240 If tying is done, WIN is set nonzero. */
1242 if (insn_code_number >= 0
1243 #ifdef REGISTER_CONSTRAINTS
1244 && insn_n_operands[insn_code_number] > 1
1245 && insn_operand_constraint[insn_code_number][0][0] == '='
1246 && insn_operand_constraint[insn_code_number][0][1] != '&'
1248 && GET_CODE (PATTERN (insn)) == SET
1249 && rtx_equal_p (SET_DEST (PATTERN (insn)), recog_operand[0])
1253 #ifdef REGISTER_CONSTRAINTS
1254 /* If non-negative, is an operand that must match operand 0. */
1255 int must_match_0 = -1;
1256 /* Counts number of alternatives that require a match with
1258 int n_matching_alts = 0;
1260 for (i = 1; i < insn_n_operands[insn_code_number]; i++)
1262 char *p = insn_operand_constraint[insn_code_number][i];
1263 int this_match = (requires_inout (p));
1265 n_matching_alts += this_match;
1266 if (this_match == insn_n_alternatives[insn_code_number])
1271 r0 = recog_operand[0];
1272 for (i = 1; i < insn_n_operands[insn_code_number]; i++)
1274 #ifdef REGISTER_CONSTRAINTS
1275 /* Skip this operand if we found an operand that
1276 must match operand 0 and this operand isn't it
1277 and can't be made to be it by commutativity. */
1279 if (must_match_0 >= 0 && i != must_match_0
1280 && ! (i == must_match_0 + 1
1281 && insn_operand_constraint[insn_code_number][i-1][0] == '%')
1282 && ! (i == must_match_0 - 1
1283 && insn_operand_constraint[insn_code_number][i][0] == '%'))
1286 /* Likewise if each alternative has some operand that
1287 must match operand zero. In that case, skip any
1288 operand that doesn't list operand 0 since we know that
1289 the operand always conflicts with operand 0. We
1290 ignore commutatity in this case to keep things simple. */
1291 if (n_matching_alts == insn_n_alternatives[insn_code_number]
1292 && (0 == requires_inout
1293 (insn_operand_constraint[insn_code_number][i])))
1297 r1 = recog_operand[i];
1299 /* If the operand is an address, find a register in it.
1300 There may be more than one register, but we only try one
1303 #ifdef REGISTER_CONSTRAINTS
1304 insn_operand_constraint[insn_code_number][i][0] == 'p'
1306 insn_operand_address_p[insn_code_number][i]
1309 while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT)
1312 if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG)
1314 /* We have two priorities for hard register preferences.
1315 If we have a move insn or an insn whose first input
1316 can only be in the same register as the output, give
1317 priority to an equivalence found from that insn. */
1319 = ((SET_DEST (body) == r0 && SET_SRC (body) == r1)
1320 #ifdef REGISTER_CONSTRAINTS
1321 || (r1 == recog_operand[i] && must_match_0 >= 0)
1325 if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1326 win = combine_regs (r1, r0, may_save_copy,
1327 insn_number, insn, 0);
1334 /* Recognize an insn sequence with an ultimate result
1335 which can safely overlap one of the inputs.
1336 The sequence begins with a CLOBBER of its result,
1337 and ends with an insn that copies the result to itself
1338 and has a REG_EQUAL note for an equivalent formula.
1339 That note indicates what the inputs are.
1340 The result and the input can overlap if each insn in
1341 the sequence either doesn't mention the input
1342 or has a REG_NO_CONFLICT note to inhibit the conflict.
1344 We do the combining test at the CLOBBER so that the
1345 destination register won't have had a quantity number
1346 assigned, since that would prevent combining. */
1348 if (GET_CODE (PATTERN (insn)) == CLOBBER
1349 && (r0 = XEXP (PATTERN (insn), 0),
1350 GET_CODE (r0) == REG)
1351 && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0
1352 && XEXP (link, 0) != 0
1353 && GET_CODE (XEXP (link, 0)) == INSN
1354 && (set = single_set (XEXP (link, 0))) != 0
1355 && SET_DEST (set) == r0 && SET_SRC (set) == r0
1356 && (note = find_reg_note (XEXP (link, 0), REG_EQUAL,
1359 if (r1 = XEXP (note, 0), GET_CODE (r1) == REG
1360 /* Check that we have such a sequence. */
1361 && no_conflict_p (insn, r0, r1))
1362 win = combine_regs (r1, r0, 1, insn_number, insn, 1);
1363 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e'
1364 && (r1 = XEXP (XEXP (note, 0), 0),
1365 GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1366 && no_conflict_p (insn, r0, r1))
1367 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1369 /* Here we care if the operation to be computed is
1371 else if ((GET_CODE (XEXP (note, 0)) == EQ
1372 || GET_CODE (XEXP (note, 0)) == NE
1373 || GET_RTX_CLASS (GET_CODE (XEXP (note, 0))) == 'c')
1374 && (r1 = XEXP (XEXP (note, 0), 1),
1375 (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG))
1376 && no_conflict_p (insn, r0, r1))
1377 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1379 /* If we did combine something, show the register number
1380 in question so that we know to ignore its death. */
1382 no_conflict_combined_regno = REGNO (r1);
1385 /* If registers were just tied, set COMBINED_REGNO
1386 to the number of the register used in this insn
1387 that was tied to the register set in this insn.
1388 This register's qty should not be "killed". */
1392 while (GET_CODE (r1) == SUBREG)
1393 r1 = SUBREG_REG (r1);
1394 combined_regno = REGNO (r1);
1397 /* Mark the death of everything that dies in this instruction,
1398 except for anything that was just combined. */
1400 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1401 if (REG_NOTE_KIND (link) == REG_DEAD
1402 && GET_CODE (XEXP (link, 0)) == REG
1403 && combined_regno != REGNO (XEXP (link, 0))
1404 && (no_conflict_combined_regno != REGNO (XEXP (link, 0))
1405 || ! find_reg_note (insn, REG_NO_CONFLICT, XEXP (link, 0))))
1406 wipe_dead_reg (XEXP (link, 0), 0);
1408 /* Allocate qty numbers for all registers local to this block
1409 that are born (set) in this instruction.
1410 A pseudo that already has a qty is not changed. */
1412 note_stores (PATTERN (insn), reg_is_set);
1414 /* If anything is set in this insn and then unused, mark it as dying
1415 after this insn, so it will conflict with our outputs. This
1416 can't match with something that combined, and it doesn't matter
1417 if it did. Do this after the calls to reg_is_set since these
1418 die after, not during, the current insn. */
1420 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1421 if (REG_NOTE_KIND (link) == REG_UNUSED
1422 && GET_CODE (XEXP (link, 0)) == REG)
1423 wipe_dead_reg (XEXP (link, 0), 1);
1425 /* Allocate quantities for any SCRATCH operands of this insn. */
1427 if (insn_code_number >= 0)
1428 for (i = 0; i < insn_n_operands[insn_code_number]; i++)
1429 if (GET_CODE (recog_operand[i]) == SCRATCH
1430 && scratches_allocated++ < scratch_list_length)
1431 alloc_qty_for_scratch (recog_operand[i], i, insn,
1432 insn_code_number, insn_number);
1434 /* If this is an insn that has a REG_RETVAL note pointing at a
1435 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1436 block, so clear any register number that combined within it. */
1437 if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0
1438 && GET_CODE (XEXP (note, 0)) == INSN
1439 && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER)
1440 no_conflict_combined_regno = -1;
1443 /* Set the registers live after INSN_NUMBER. Note that we never
1444 record the registers live before the block's first insn, since no
1445 pseudos we care about are live before that insn. */
1447 IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live);
1448 IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live);
1450 if (insn == basic_block_end[b])
1453 insn = NEXT_INSN (insn);
1456 /* Now every register that is local to this basic block
1457 should have been given a quantity, or else -1 meaning ignore it.
1458 Every quantity should have a known birth and death.
1460 Order the qtys so we assign them registers in order of the
1461 number of suggested registers they need so we allocate those with
1462 the most restrictive needs first. */
1464 qty_order = (int *) alloca (next_qty * sizeof (int));
1465 for (i = 0; i < next_qty; i++)
1468 #define EXCHANGE(I1, I2) \
1469 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1474 /* Make qty_order[2] be the one to allocate last. */
1475 if (qty_sugg_compare (0, 1) > 0)
1477 if (qty_sugg_compare (1, 2) > 0)
1480 /* ... Fall through ... */
1482 /* Put the best one to allocate in qty_order[0]. */
1483 if (qty_sugg_compare (0, 1) > 0)
1486 /* ... Fall through ... */
1490 /* Nothing to do here. */
1494 qsort (qty_order, next_qty, sizeof (int), qty_sugg_compare_1);
1497 /* Try to put each quantity in a suggested physical register, if it has one.
1498 This may cause registers to be allocated that otherwise wouldn't be, but
1499 this seems acceptable in local allocation (unlike global allocation). */
1500 for (i = 0; i < next_qty; i++)
1503 if (qty_phys_num_sugg[q] != 0 || qty_phys_num_copy_sugg[q] != 0)
1504 qty_phys_reg[q] = find_free_reg (qty_min_class[q], qty_mode[q], q,
1505 0, 1, qty_birth[q], qty_death[q]);
1507 qty_phys_reg[q] = -1;
1510 /* Order the qtys so we assign them registers in order of
1511 decreasing length of life. Normally call qsort, but if we
1512 have only a very small number of quantities, sort them ourselves. */
1514 for (i = 0; i < next_qty; i++)
1517 #define EXCHANGE(I1, I2) \
1518 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1523 /* Make qty_order[2] be the one to allocate last. */
1524 if (qty_compare (0, 1) > 0)
1526 if (qty_compare (1, 2) > 0)
1529 /* ... Fall through ... */
1531 /* Put the best one to allocate in qty_order[0]. */
1532 if (qty_compare (0, 1) > 0)
1535 /* ... Fall through ... */
1539 /* Nothing to do here. */
1543 qsort (qty_order, next_qty, sizeof (int), qty_compare_1);
1546 /* Now for each qty that is not a hardware register,
1547 look for a hardware register to put it in.
1548 First try the register class that is cheapest for this qty,
1549 if there is more than one class. */
1551 for (i = 0; i < next_qty; i++)
1554 if (qty_phys_reg[q] < 0)
1556 if (N_REG_CLASSES > 1)
1558 qty_phys_reg[q] = find_free_reg (qty_min_class[q],
1559 qty_mode[q], q, 0, 0,
1560 qty_birth[q], qty_death[q]);
1561 if (qty_phys_reg[q] >= 0)
1565 if (qty_alternate_class[q] != NO_REGS)
1566 qty_phys_reg[q] = find_free_reg (qty_alternate_class[q],
1567 qty_mode[q], q, 0, 0,
1568 qty_birth[q], qty_death[q]);
1572 /* Now propagate the register assignments
1573 to the pseudo regs belonging to the qtys. */
1575 for (q = 0; q < next_qty; q++)
1576 if (qty_phys_reg[q] >= 0)
1578 for (i = qty_first_reg[q]; i >= 0; i = reg_next_in_qty[i])
1579 reg_renumber[i] = qty_phys_reg[q] + reg_offset[i];
1580 if (qty_scratch_rtx[q])
1582 if (GET_CODE (qty_scratch_rtx[q]) == REG)
1584 PUT_CODE (qty_scratch_rtx[q], REG);
1585 REGNO (qty_scratch_rtx[q]) = qty_phys_reg[q];
1587 scratch_block[scratch_index] = b;
1588 scratch_list[scratch_index++] = qty_scratch_rtx[q];
1590 /* Must clear the USED field, because it will have been set by
1591 copy_rtx_if_shared, but the leaf_register code expects that
1592 it is zero in all REG rtx. copy_rtx_if_shared does not set the
1593 used bit for REGs, but does for SCRATCHes. */
1594 qty_scratch_rtx[q]->used = 0;
1599 /* Compare two quantities' priority for getting real registers.
1600 We give shorter-lived quantities higher priority.
1601 Quantities with more references are also preferred, as are quantities that
1602 require multiple registers. This is the identical prioritization as
1603 done by global-alloc.
1605 We used to give preference to registers with *longer* lives, but using
1606 the same algorithm in both local- and global-alloc can speed up execution
1607 of some programs by as much as a factor of three! */
1609 /* Note that the quotient will never be bigger than
1610 the value of floor_log2 times the maximum number of
1611 times a register can occur in one insn (surely less than 100).
1612 Multiplying this by 10000 can't overflow.
1613 QTY_CMP_PRI is also used by qty_sugg_compare. */
1615 #define QTY_CMP_PRI(q) \
1616 ((int) (((double) (floor_log2 (qty_n_refs[q]) * qty_n_refs[q] * qty_size[q]) \
1617 / (qty_death[q] - qty_birth[q])) * 10000))
1620 qty_compare (q1, q2)
1623 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1627 qty_compare_1 (q1p, q2p)
1628 const GENERIC_PTR q1p;
1629 const GENERIC_PTR q2p;
1631 register int q1 = *(int *)q1p, q2 = *(int *)q2p;
1632 register int tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1637 /* If qtys are equally good, sort by qty number,
1638 so that the results of qsort leave nothing to chance. */
1642 /* Compare two quantities' priority for getting real registers. This version
1643 is called for quantities that have suggested hard registers. First priority
1644 goes to quantities that have copy preferences, then to those that have
1645 normal preferences. Within those groups, quantities with the lower
1646 number of preferences have the highest priority. Of those, we use the same
1647 algorithm as above. */
1649 #define QTY_CMP_SUGG(q) \
1650 (qty_phys_num_copy_sugg[q] \
1651 ? qty_phys_num_copy_sugg[q] \
1652 : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER)
1655 qty_sugg_compare (q1, q2)
1658 register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1663 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1667 qty_sugg_compare_1 (q1p, q2p)
1668 const GENERIC_PTR q1p;
1669 const GENERIC_PTR q2p;
1671 register int q1 = *(int *)q1p, q2 = *(int *)q2p;
1672 register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1677 tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1681 /* If qtys are equally good, sort by qty number,
1682 so that the results of qsort leave nothing to chance. */
1689 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1690 Returns 1 if have done so, or 0 if cannot.
1692 Combining registers means marking them as having the same quantity
1693 and adjusting the offsets within the quantity if either of
1696 We don't actually combine a hard reg with a pseudo; instead
1697 we just record the hard reg as the suggestion for the pseudo's quantity.
1698 If we really combined them, we could lose if the pseudo lives
1699 across an insn that clobbers the hard reg (eg, movstr).
1701 ALREADY_DEAD is non-zero if USEDREG is known to be dead even though
1702 there is no REG_DEAD note on INSN. This occurs during the processing
1703 of REG_NO_CONFLICT blocks.
1705 MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
1706 SETREG or if the input and output must share a register.
1707 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1709 There are elaborate checks for the validity of combining. */
1713 combine_regs (usedreg, setreg, may_save_copy, insn_number, insn, already_dead)
1714 rtx usedreg, setreg;
1720 register int ureg, sreg;
1721 register int offset = 0;
1725 /* Determine the numbers and sizes of registers being used. If a subreg
1726 is present that does not change the entire register, don't consider
1727 this a copy insn. */
1729 while (GET_CODE (usedreg) == SUBREG)
1731 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg))) > UNITS_PER_WORD)
1733 offset += SUBREG_WORD (usedreg);
1734 usedreg = SUBREG_REG (usedreg);
1736 if (GET_CODE (usedreg) != REG)
1738 ureg = REGNO (usedreg);
1739 usize = REG_SIZE (usedreg);
1741 while (GET_CODE (setreg) == SUBREG)
1743 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg))) > UNITS_PER_WORD)
1745 offset -= SUBREG_WORD (setreg);
1746 setreg = SUBREG_REG (setreg);
1748 if (GET_CODE (setreg) != REG)
1750 sreg = REGNO (setreg);
1751 ssize = REG_SIZE (setreg);
1753 /* If UREG is a pseudo-register that hasn't already been assigned a
1754 quantity number, it means that it is not local to this block or dies
1755 more than once. In either event, we can't do anything with it. */
1756 if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0)
1757 /* Do not combine registers unless one fits within the other. */
1758 || (offset > 0 && usize + offset > ssize)
1759 || (offset < 0 && usize + offset < ssize)
1760 /* Do not combine with a smaller already-assigned object
1761 if that smaller object is already combined with something bigger. */
1762 || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER
1763 && usize < qty_size[reg_qty[ureg]])
1764 /* Can't combine if SREG is not a register we can allocate. */
1765 || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1)
1766 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1767 These have already been taken care of. This probably wouldn't
1768 combine anyway, but don't take any chances. */
1769 || (ureg >= FIRST_PSEUDO_REGISTER
1770 && find_reg_note (insn, REG_NO_CONFLICT, usedreg))
1771 /* Don't tie something to itself. In most cases it would make no
1772 difference, but it would screw up if the reg being tied to itself
1773 also dies in this insn. */
1775 /* Don't try to connect two different hardware registers. */
1776 || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER)
1777 /* Don't connect two different machine modes if they have different
1778 implications as to which registers may be used. */
1779 || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg)))
1782 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1783 qty_phys_sugg for the pseudo instead of tying them.
1785 Return "failure" so that the lifespan of UREG is terminated here;
1786 that way the two lifespans will be disjoint and nothing will prevent
1787 the pseudo reg from being given this hard reg. */
1789 if (ureg < FIRST_PSEUDO_REGISTER)
1791 /* Allocate a quantity number so we have a place to put our
1793 if (reg_qty[sreg] == -2)
1794 reg_is_born (setreg, 2 * insn_number);
1796 if (reg_qty[sreg] >= 0)
1799 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg))
1801 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg);
1802 qty_phys_num_copy_sugg[reg_qty[sreg]]++;
1804 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg))
1806 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg);
1807 qty_phys_num_sugg[reg_qty[sreg]]++;
1813 /* Similarly for SREG a hard register and UREG a pseudo register. */
1815 if (sreg < FIRST_PSEUDO_REGISTER)
1818 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg))
1820 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg);
1821 qty_phys_num_copy_sugg[reg_qty[ureg]]++;
1823 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg))
1825 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg);
1826 qty_phys_num_sugg[reg_qty[ureg]]++;
1831 /* At this point we know that SREG and UREG are both pseudos.
1832 Do nothing if SREG already has a quantity or is a register that we
1834 if (reg_qty[sreg] >= -1
1835 /* If we are not going to let any regs live across calls,
1836 don't tie a call-crossing reg to a non-call-crossing reg. */
1837 || (current_function_has_nonlocal_label
1838 && ((reg_n_calls_crossed[ureg] > 0)
1839 != (reg_n_calls_crossed[sreg] > 0))))
1842 /* We don't already know about SREG, so tie it to UREG
1843 if this is the last use of UREG, provided the classes they want
1846 if ((already_dead || find_regno_note (insn, REG_DEAD, ureg))
1847 && reg_meets_class_p (sreg, qty_min_class[reg_qty[ureg]]))
1849 /* Add SREG to UREG's quantity. */
1850 sqty = reg_qty[ureg];
1851 reg_qty[sreg] = sqty;
1852 reg_offset[sreg] = reg_offset[ureg] + offset;
1853 reg_next_in_qty[sreg] = qty_first_reg[sqty];
1854 qty_first_reg[sqty] = sreg;
1856 /* If SREG's reg class is smaller, set qty_min_class[SQTY]. */
1857 update_qty_class (sqty, sreg);
1859 /* Update info about quantity SQTY. */
1860 qty_n_calls_crossed[sqty] += reg_n_calls_crossed[sreg];
1861 qty_n_refs[sqty] += reg_n_refs[sreg];
1866 for (i = qty_first_reg[sqty]; i >= 0; i = reg_next_in_qty[i])
1867 reg_offset[i] -= offset;
1869 qty_size[sqty] = ssize;
1870 qty_mode[sqty] = GET_MODE (setreg);
1879 /* Return 1 if the preferred class of REG allows it to be tied
1880 to a quantity or register whose class is CLASS.
1881 True if REG's reg class either contains or is contained in CLASS. */
1884 reg_meets_class_p (reg, class)
1886 enum reg_class class;
1888 register enum reg_class rclass = reg_preferred_class (reg);
1889 return (reg_class_subset_p (rclass, class)
1890 || reg_class_subset_p (class, rclass));
1893 /* Return 1 if the two specified classes have registers in common.
1894 If CALL_SAVED, then consider only call-saved registers. */
1897 reg_classes_overlap_p (c1, c2, call_saved)
1898 register enum reg_class c1;
1899 register enum reg_class c2;
1905 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
1906 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
1908 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1909 if (TEST_HARD_REG_BIT (c, i)
1910 && (! call_saved || ! call_used_regs[i]))
1916 /* Update the class of QTY assuming that REG is being tied to it. */
1919 update_qty_class (qty, reg)
1923 enum reg_class rclass = reg_preferred_class (reg);
1924 if (reg_class_subset_p (rclass, qty_min_class[qty]))
1925 qty_min_class[qty] = rclass;
1927 rclass = reg_alternate_class (reg);
1928 if (reg_class_subset_p (rclass, qty_alternate_class[qty]))
1929 qty_alternate_class[qty] = rclass;
1931 if (reg_changes_size[reg])
1932 qty_changes_size[qty] = 1;
1935 /* Handle something which alters the value of an rtx REG.
1937 REG is whatever is set or clobbered. SETTER is the rtx that
1938 is modifying the register.
1940 If it is not really a register, we do nothing.
1941 The file-global variables `this_insn' and `this_insn_number'
1942 carry info from `block_alloc'. */
1945 reg_is_set (reg, setter)
1949 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
1950 a hard register. These may actually not exist any more. */
1952 if (GET_CODE (reg) != SUBREG
1953 && GET_CODE (reg) != REG)
1956 /* Mark this register as being born. If it is used in a CLOBBER, mark
1957 it as being born halfway between the previous insn and this insn so that
1958 it conflicts with our inputs but not the outputs of the previous insn. */
1960 reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER));
1963 /* Handle beginning of the life of register REG.
1964 BIRTH is the index at which this is happening. */
1967 reg_is_born (reg, birth)
1973 if (GET_CODE (reg) == SUBREG)
1974 regno = REGNO (SUBREG_REG (reg)) + SUBREG_WORD (reg);
1976 regno = REGNO (reg);
1978 if (regno < FIRST_PSEUDO_REGISTER)
1980 mark_life (regno, GET_MODE (reg), 1);
1982 /* If the register was to have been born earlier that the present
1983 insn, mark it as live where it is actually born. */
1984 if (birth < 2 * this_insn_number)
1985 post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number);
1989 if (reg_qty[regno] == -2)
1990 alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth);
1992 /* If this register has a quantity number, show that it isn't dead. */
1993 if (reg_qty[regno] >= 0)
1994 qty_death[reg_qty[regno]] = -1;
1998 /* Record the death of REG in the current insn. If OUTPUT_P is non-zero,
1999 REG is an output that is dying (i.e., it is never used), otherwise it
2000 is an input (the normal case).
2001 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
2004 wipe_dead_reg (reg, output_p)
2008 register int regno = REGNO (reg);
2010 /* If this insn has multiple results,
2011 and the dead reg is used in one of the results,
2012 extend its life to after this insn,
2013 so it won't get allocated together with any other result of this insn. */
2014 if (GET_CODE (PATTERN (this_insn)) == PARALLEL
2015 && !single_set (this_insn))
2018 for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--)
2020 rtx set = XVECEXP (PATTERN (this_insn), 0, i);
2021 if (GET_CODE (set) == SET
2022 && GET_CODE (SET_DEST (set)) != REG
2023 && !rtx_equal_p (reg, SET_DEST (set))
2024 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2029 /* If this register is used in an auto-increment address, then extend its
2030 life to after this insn, so that it won't get allocated together with
2031 the result of this insn. */
2032 if (! output_p && find_regno_note (this_insn, REG_INC, regno))
2035 if (regno < FIRST_PSEUDO_REGISTER)
2037 mark_life (regno, GET_MODE (reg), 0);
2039 /* If a hard register is dying as an output, mark it as in use at
2040 the beginning of this insn (the above statement would cause this
2043 post_mark_life (regno, GET_MODE (reg), 1,
2044 2 * this_insn_number, 2 * this_insn_number+ 1);
2047 else if (reg_qty[regno] >= 0)
2048 qty_death[reg_qty[regno]] = 2 * this_insn_number + output_p;
2051 /* Find a block of SIZE words of hard regs in reg_class CLASS
2052 that can hold something of machine-mode MODE
2053 (but actually we test only the first of the block for holding MODE)
2054 and still free between insn BORN_INDEX and insn DEAD_INDEX,
2055 and return the number of the first of them.
2056 Return -1 if such a block cannot be found.
2057 If QTY crosses calls, insist on a register preserved by calls,
2058 unless ACCEPT_CALL_CLOBBERED is nonzero.
2060 If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
2061 register is available. If not, return -1. */
2064 find_free_reg (class, mode, qty, accept_call_clobbered, just_try_suggested,
2065 born_index, dead_index)
2066 enum reg_class class;
2067 enum machine_mode mode;
2069 int accept_call_clobbered;
2070 int just_try_suggested;
2071 int born_index, dead_index;
2073 register int i, ins;
2075 register /* Declare it register if it's a scalar. */
2077 HARD_REG_SET used, first_used;
2078 #ifdef ELIMINABLE_REGS
2079 static struct {int from, to; } eliminables[] = ELIMINABLE_REGS;
2082 /* Validate our parameters. */
2083 if (born_index < 0 || born_index > dead_index)
2086 /* Don't let a pseudo live in a reg across a function call
2087 if we might get a nonlocal goto. */
2088 if (current_function_has_nonlocal_label
2089 && qty_n_calls_crossed[qty] > 0)
2092 if (accept_call_clobbered)
2093 COPY_HARD_REG_SET (used, call_fixed_reg_set);
2094 else if (qty_n_calls_crossed[qty] == 0)
2095 COPY_HARD_REG_SET (used, fixed_reg_set);
2097 COPY_HARD_REG_SET (used, call_used_reg_set);
2099 if (accept_call_clobbered)
2100 IOR_HARD_REG_SET (used, losing_caller_save_reg_set);
2102 for (ins = born_index; ins < dead_index; ins++)
2103 IOR_HARD_REG_SET (used, regs_live_at[ins]);
2105 IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]);
2107 /* Don't use the frame pointer reg in local-alloc even if
2108 we may omit the frame pointer, because if we do that and then we
2109 need a frame pointer, reload won't know how to move the pseudo
2110 to another hard reg. It can move only regs made by global-alloc.
2112 This is true of any register that can be eliminated. */
2113 #ifdef ELIMINABLE_REGS
2114 for (i = 0; i < sizeof eliminables / sizeof eliminables[0]; i++)
2115 SET_HARD_REG_BIT (used, eliminables[i].from);
2116 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
2117 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
2118 that it might be eliminated into. */
2119 SET_HARD_REG_BIT (used, HARD_FRAME_POINTER_REGNUM);
2122 SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM);
2125 #ifdef CLASS_CANNOT_CHANGE_SIZE
2126 if (qty_changes_size[qty])
2127 IOR_HARD_REG_SET (used,
2128 reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE]);
2131 /* Normally, the registers that can be used for the first register in
2132 a multi-register quantity are the same as those that can be used for
2133 subsequent registers. However, if just trying suggested registers,
2134 restrict our consideration to them. If there are copy-suggested
2135 register, try them. Otherwise, try the arithmetic-suggested
2137 COPY_HARD_REG_SET (first_used, used);
2139 if (just_try_suggested)
2141 if (qty_phys_num_copy_sugg[qty] != 0)
2142 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qty]);
2144 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qty]);
2147 /* If all registers are excluded, we can't do anything. */
2148 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail);
2150 /* If at least one would be suitable, test each hard reg. */
2152 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2154 #ifdef REG_ALLOC_ORDER
2155 int regno = reg_alloc_order[i];
2159 if (! TEST_HARD_REG_BIT (first_used, regno)
2160 && HARD_REGNO_MODE_OK (regno, mode))
2163 register int size1 = HARD_REGNO_NREGS (regno, mode);
2164 for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++);
2167 /* Mark that this register is in use between its birth and death
2169 post_mark_life (regno, mode, 1, born_index, dead_index);
2172 #ifndef REG_ALLOC_ORDER
2173 i += j; /* Skip starting points we know will lose */
2180 /* If we are just trying suggested register, we have just tried copy-
2181 suggested registers, and there are arithmetic-suggested registers,
2184 /* If it would be profitable to allocate a call-clobbered register
2185 and save and restore it around calls, do that. */
2186 if (just_try_suggested && qty_phys_num_copy_sugg[qty] != 0
2187 && qty_phys_num_sugg[qty] != 0)
2189 /* Don't try the copy-suggested regs again. */
2190 qty_phys_num_copy_sugg[qty] = 0;
2191 return find_free_reg (class, mode, qty, accept_call_clobbered, 1,
2192 born_index, dead_index);
2195 /* We need not check to see if the current function has nonlocal
2196 labels because we don't put any pseudos that are live over calls in
2197 registers in that case. */
2199 if (! accept_call_clobbered
2200 && flag_caller_saves
2201 && ! just_try_suggested
2202 && qty_n_calls_crossed[qty] != 0
2203 && CALLER_SAVE_PROFITABLE (qty_n_refs[qty], qty_n_calls_crossed[qty]))
2205 i = find_free_reg (class, mode, qty, 1, 0, born_index, dead_index);
2207 caller_save_needed = 1;
2213 /* Mark that REGNO with machine-mode MODE is live starting from the current
2214 insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE
2218 mark_life (regno, mode, life)
2220 enum machine_mode mode;
2223 register int j = HARD_REGNO_NREGS (regno, mode);
2226 SET_HARD_REG_BIT (regs_live, regno + j);
2229 CLEAR_HARD_REG_BIT (regs_live, regno + j);
2232 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2233 is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2234 to insn number DEATH (exclusive). */
2237 post_mark_life (regno, mode, life, birth, death)
2239 enum machine_mode mode;
2240 int life, birth, death;
2242 register int j = HARD_REGNO_NREGS (regno, mode);
2244 register /* Declare it register if it's a scalar. */
2246 HARD_REG_SET this_reg;
2248 CLEAR_HARD_REG_SET (this_reg);
2250 SET_HARD_REG_BIT (this_reg, regno + j);
2253 while (birth < death)
2255 IOR_HARD_REG_SET (regs_live_at[birth], this_reg);
2259 while (birth < death)
2261 AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg);
2266 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2267 is the register being clobbered, and R1 is a register being used in
2268 the equivalent expression.
2270 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2271 in which it is used, return 1.
2273 Otherwise, return 0. */
2276 no_conflict_p (insn, r0, r1)
2280 rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
2283 /* If R1 is a hard register, return 0 since we handle this case
2284 when we scan the insns that actually use it. */
2287 || (GET_CODE (r1) == REG && REGNO (r1) < FIRST_PSEUDO_REGISTER)
2288 || (GET_CODE (r1) == SUBREG && GET_CODE (SUBREG_REG (r1)) == REG
2289 && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER))
2292 last = XEXP (note, 0);
2294 for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p))
2295 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
2297 if (find_reg_note (p, REG_DEAD, r1))
2300 if (reg_mentioned_p (r1, PATTERN (p))
2301 && ! find_reg_note (p, REG_NO_CONFLICT, r1))
2308 #ifdef REGISTER_CONSTRAINTS
2310 /* Return the number of alternatives for which the constraint string P
2311 indicates that the operand must be equal to operand 0 and that no register
2320 int reg_allowed = 0;
2321 int num_matching_alts = 0;
2326 case '=': case '+': case '?':
2327 case '#': case '&': case '!':
2329 case '1': case '2': case '3': case '4':
2330 case 'm': case '<': case '>': case 'V': case 'o':
2331 case 'E': case 'F': case 'G': case 'H':
2332 case 's': case 'i': case 'n':
2333 case 'I': case 'J': case 'K': case 'L':
2334 case 'M': case 'N': case 'O': case 'P':
2335 #ifdef EXTRA_CONSTRAINT
2336 case 'Q': case 'R': case 'S': case 'T': case 'U':
2339 /* These don't say anything we care about. */
2343 if (found_zero && ! reg_allowed)
2344 num_matching_alts++;
2346 found_zero = reg_allowed = 0;
2360 if (found_zero && ! reg_allowed)
2361 num_matching_alts++;
2363 return num_matching_alts;
2365 #endif /* REGISTER_CONSTRAINTS */
2368 dump_local_alloc (file)
2372 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2373 if (reg_renumber[i] != -1)
2374 fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]);