1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 88, 91, 93-6, 1997 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Allocation of hard register numbers to pseudo registers is done in
23 two passes. In this pass we consider only regs that are born and
24 die once within one basic block. We do this one basic block at a
25 time. Then the next pass allocates the registers that remain.
26 Two passes are used because this pass uses methods that work only
27 on linear code, but that do a better job than the general methods
28 used in global_alloc, and more quickly too.
30 The assignments made are recorded in the vector reg_renumber
31 whose space is allocated here. The rtl code itself is not altered.
33 We assign each instruction in the basic block a number
34 which is its order from the beginning of the block.
35 Then we can represent the lifetime of a pseudo register with
36 a pair of numbers, and check for conflicts easily.
37 We can record the availability of hard registers with a
38 HARD_REG_SET for each instruction. The HARD_REG_SET
39 contains 0 or 1 for each hard reg.
41 To avoid register shuffling, we tie registers together when one
42 dies by being copied into another, or dies in an instruction that
43 does arithmetic to produce another. The tied registers are
44 allocated as one. Registers with different reg class preferences
45 can never be tied unless the class preferred by one is a subclass
46 of the one preferred by the other.
48 Tying is represented with "quantity numbers".
49 A non-tied register is given a new quantity number.
50 Tied registers have the same quantity number.
52 We have provision to exempt registers, even when they are contained
53 within the block, that can be tied to others that are not contained in it.
54 This is so that global_alloc could process them both and tie them then.
55 But this is currently disabled since tying in global_alloc is not
58 /* Pseudos allocated here cannot be reallocated by global.c if the hard
59 register is used as a spill register. So we don't allocate such pseudos
60 here if their preferred class is likely to be used by spills. */
66 #include "basic-block.h"
68 #include "hard-reg-set.h"
69 #include "insn-config.h"
73 /* Next quantity number available for allocation. */
77 /* In all the following vectors indexed by quantity number. */
79 /* Element Q is the hard reg number chosen for quantity Q,
80 or -1 if none was found. */
82 static short *qty_phys_reg;
84 /* We maintain two hard register sets that indicate suggested hard registers
85 for each quantity. The first, qty_phys_copy_sugg, contains hard registers
86 that are tied to the quantity by a simple copy. The second contains all
87 hard registers that are tied to the quantity via an arithmetic operation.
89 The former register set is given priority for allocation. This tends to
90 eliminate copy insns. */
92 /* Element Q is a set of hard registers that are suggested for quantity Q by
95 static HARD_REG_SET *qty_phys_copy_sugg;
97 /* Element Q is a set of hard registers that are suggested for quantity Q by
100 static HARD_REG_SET *qty_phys_sugg;
102 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
104 static short *qty_phys_num_copy_sugg;
106 /* Element Q is the number of suggested registers in qty_phys_sugg. */
108 static short *qty_phys_num_sugg;
110 /* Element Q is the number of refs to quantity Q. */
112 static int *qty_n_refs;
114 /* Element Q is a reg class contained in (smaller than) the
115 preferred classes of all the pseudo regs that are tied in quantity Q.
116 This is the preferred class for allocating that quantity. */
118 static enum reg_class *qty_min_class;
120 /* Insn number (counting from head of basic block)
121 where quantity Q was born. -1 if birth has not been recorded. */
123 static int *qty_birth;
125 /* Insn number (counting from head of basic block)
126 where quantity Q died. Due to the way tying is done,
127 and the fact that we consider in this pass only regs that die but once,
128 a quantity can die only once. Each quantity's life span
129 is a set of consecutive insns. -1 if death has not been recorded. */
131 static int *qty_death;
133 /* Number of words needed to hold the data in quantity Q.
134 This depends on its machine mode. It is used for these purposes:
135 1. It is used in computing the relative importances of qtys,
136 which determines the order in which we look for regs for them.
137 2. It is used in rules that prevent tying several registers of
138 different sizes in a way that is geometrically impossible
139 (see combine_regs). */
141 static int *qty_size;
143 /* This holds the mode of the registers that are tied to qty Q,
144 or VOIDmode if registers with differing modes are tied together. */
146 static enum machine_mode *qty_mode;
148 /* Number of times a reg tied to qty Q lives across a CALL_INSN. */
150 static int *qty_n_calls_crossed;
152 /* Register class within which we allocate qty Q if we can't get
153 its preferred class. */
155 static enum reg_class *qty_alternate_class;
157 /* Element Q is the SCRATCH expression for which this quantity is being
158 allocated or 0 if this quantity is allocating registers. */
160 static rtx *qty_scratch_rtx;
162 /* Element Q is nonzero if this quantity has been used in a SUBREG
163 that changes its size. */
165 static char *qty_changes_size;
167 /* Element Q is the register number of one pseudo register whose
168 reg_qty value is Q, or -1 is this quantity is for a SCRATCH. This
169 register should be the head of the chain maintained in reg_next_in_qty. */
171 static int *qty_first_reg;
173 /* If (REG N) has been assigned a quantity number, is a register number
174 of another register assigned the same quantity number, or -1 for the
175 end of the chain. qty_first_reg point to the head of this chain. */
177 static int *reg_next_in_qty;
179 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
181 of -1 if this register cannot be allocated by local-alloc,
182 or -2 if not known yet.
184 Note that if we see a use or death of pseudo register N with
185 reg_qty[N] == -2, register N must be local to the current block. If
186 it were used in more than one block, we would have reg_qty[N] == -1.
187 This relies on the fact that if reg_basic_block[N] is >= 0, register N
188 will not appear in any other block. We save a considerable number of
189 tests by exploiting this.
191 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
196 /* The offset (in words) of register N within its quantity.
197 This can be nonzero if register N is SImode, and has been tied
198 to a subreg of a DImode register. */
200 static char *reg_offset;
202 /* Vector of substitutions of register numbers,
203 used to map pseudo regs into hardware regs.
204 This is set up as a result of register allocation.
205 Element N is the hard reg assigned to pseudo reg N,
206 or is -1 if no hard reg was assigned.
207 If N is a hard reg number, element N is N. */
211 /* Set of hard registers live at the current point in the scan
212 of the instructions in a basic block. */
214 static HARD_REG_SET regs_live;
216 /* Each set of hard registers indicates registers live at a particular
217 point in the basic block. For N even, regs_live_at[N] says which
218 hard registers are needed *after* insn N/2 (i.e., they may not
219 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
221 If an object is to conflict with the inputs of insn J but not the
222 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
223 if it is to conflict with the outputs of insn J but not the inputs of
224 insn J + 1, it is said to die at index J*2 + 1. */
226 static HARD_REG_SET *regs_live_at;
230 int scratch_list_length;
231 static int scratch_index;
233 /* Communicate local vars `insn_number' and `insn'
234 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
235 static int this_insn_number;
236 static rtx this_insn;
238 /* Used to communicate changes made by update_equiv_regs to
239 memref_referenced_p. reg_equiv_replacement is set for any REG_EQUIV note
240 found or created, so that we can keep track of what memory accesses might
241 be created later, e.g. by reload. */
243 static rtx *reg_equiv_replacement;
245 static void alloc_qty PROTO((int, enum machine_mode, int, int));
246 static void alloc_qty_for_scratch PROTO((rtx, int, rtx, int, int));
247 static void validate_equiv_mem_from_store PROTO((rtx, rtx));
248 static int validate_equiv_mem PROTO((rtx, rtx, rtx));
249 static int memref_referenced_p PROTO((rtx, rtx));
250 static int memref_used_between_p PROTO((rtx, rtx, rtx));
251 static void optimize_reg_copy_1 PROTO((rtx, rtx, rtx));
252 static void optimize_reg_copy_2 PROTO((rtx, rtx, rtx));
253 static void update_equiv_regs PROTO((void));
254 static void block_alloc PROTO((int));
255 static int qty_sugg_compare PROTO((int, int));
256 static int qty_sugg_compare_1 PROTO((const GENERIC_PTR, const GENERIC_PTR));
257 static int qty_compare PROTO((int, int));
258 static int qty_compare_1 PROTO((const GENERIC_PTR, const GENERIC_PTR));
259 static int combine_regs PROTO((rtx, rtx, int, int, rtx, int));
260 static int reg_meets_class_p PROTO((int, enum reg_class));
261 static int reg_classes_overlap_p PROTO((enum reg_class, enum reg_class,
263 static void update_qty_class PROTO((int, int));
264 static void reg_is_set PROTO((rtx, rtx));
265 static void reg_is_born PROTO((rtx, int));
266 static void wipe_dead_reg PROTO((rtx, int));
267 static int find_free_reg PROTO((enum reg_class, enum machine_mode,
268 int, int, int, int, int));
269 static void mark_life PROTO((int, enum machine_mode, int));
270 static void post_mark_life PROTO((int, enum machine_mode, int, int, int));
271 static int no_conflict_p PROTO((rtx, rtx, rtx));
272 static int requires_inout PROTO((char *));
274 /* Allocate a new quantity (new within current basic block)
275 for register number REGNO which is born at index BIRTH
276 within the block. MODE and SIZE are info on reg REGNO. */
279 alloc_qty (regno, mode, size, birth)
281 enum machine_mode mode;
284 register int qty = next_qty++;
286 reg_qty[regno] = qty;
287 reg_offset[regno] = 0;
288 reg_next_in_qty[regno] = -1;
290 qty_first_reg[qty] = regno;
291 qty_size[qty] = size;
292 qty_mode[qty] = mode;
293 qty_birth[qty] = birth;
294 qty_n_calls_crossed[qty] = reg_n_calls_crossed[regno];
295 qty_min_class[qty] = reg_preferred_class (regno);
296 qty_alternate_class[qty] = reg_alternate_class (regno);
297 qty_n_refs[qty] = reg_n_refs[regno];
298 qty_changes_size[qty] = reg_changes_size[regno];
301 /* Similar to `alloc_qty', but allocates a quantity for a SCRATCH rtx
302 used as operand N in INSN. We assume here that the SCRATCH is used in
306 alloc_qty_for_scratch (scratch, n, insn, insn_code_num, insn_number)
310 int insn_code_num, insn_number;
313 enum reg_class class;
317 #ifdef REGISTER_CONSTRAINTS
318 /* If we haven't yet computed which alternative will be used, do so now.
319 Then set P to the constraints for that alternative. */
320 if (which_alternative == -1)
321 if (! constrain_operands (insn_code_num, 0))
324 for (p = insn_operand_constraint[insn_code_num][n], i = 0;
325 *p && i < which_alternative; p++)
329 /* Compute the class required for this SCRATCH. If we don't need a
330 register, the class will remain NO_REGS. If we guessed the alternative
331 number incorrectly, reload will fix things up for us. */
334 while ((c = *p++) != '\0' && c != ',')
337 case '=': case '+': case '?':
338 case '#': case '&': case '!':
340 case '0': case '1': case '2': case '3': case '4':
341 case 'm': case '<': case '>': case 'V': case 'o':
342 case 'E': case 'F': case 'G': case 'H':
343 case 's': case 'i': case 'n':
344 case 'I': case 'J': case 'K': case 'L':
345 case 'M': case 'N': case 'O': case 'P':
346 #ifdef EXTRA_CONSTRAINT
347 case 'Q': case 'R': case 'S': case 'T': case 'U':
350 /* These don't say anything we care about. */
354 /* We don't need to allocate this SCRATCH. */
358 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
363 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER (c)];
367 if (class == NO_REGS)
370 #else /* REGISTER_CONSTRAINTS */
372 class = GENERAL_REGS;
378 qty_first_reg[qty] = -1;
379 qty_scratch_rtx[qty] = scratch;
380 qty_size[qty] = GET_MODE_SIZE (GET_MODE (scratch));
381 qty_mode[qty] = GET_MODE (scratch);
382 qty_birth[qty] = 2 * insn_number - 1;
383 qty_death[qty] = 2 * insn_number + 1;
384 qty_n_calls_crossed[qty] = 0;
385 qty_min_class[qty] = class;
386 qty_alternate_class[qty] = NO_REGS;
388 qty_changes_size[qty] = 0;
391 /* Main entry point of this file. */
399 /* Leaf functions and non-leaf functions have different needs.
400 If defined, let the machine say what kind of ordering we
402 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
403 ORDER_REGS_FOR_LOCAL_ALLOC;
406 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
408 update_equiv_regs ();
410 /* This sets the maximum number of quantities we can have. Quantity
411 numbers start at zero and we can have one for each pseudo plus the
412 number of SCRATCHes in the largest block, in the worst case. */
413 max_qty = (max_regno - FIRST_PSEUDO_REGISTER) + max_scratch;
415 /* Allocate vectors of temporary data.
416 See the declarations of these variables, above,
417 for what they mean. */
419 /* There can be up to MAX_SCRATCH * N_BASIC_BLOCKS SCRATCHes to allocate.
420 Instead of allocating this much memory from now until the end of
421 reload, only allocate space for MAX_QTY SCRATCHes. If there are more
422 reload will allocate them. */
424 scratch_list_length = max_qty;
425 scratch_list = (rtx *) xmalloc (scratch_list_length * sizeof (rtx));
426 bzero ((char *) scratch_list, scratch_list_length * sizeof (rtx));
427 scratch_block = (int *) xmalloc (scratch_list_length * sizeof (int));
428 bzero ((char *) scratch_block, scratch_list_length * sizeof (int));
431 qty_phys_reg = (short *) alloca (max_qty * sizeof (short));
433 = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
434 qty_phys_num_copy_sugg = (short *) alloca (max_qty * sizeof (short));
435 qty_phys_sugg = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
436 qty_phys_num_sugg = (short *) alloca (max_qty * sizeof (short));
437 qty_birth = (int *) alloca (max_qty * sizeof (int));
438 qty_death = (int *) alloca (max_qty * sizeof (int));
439 qty_scratch_rtx = (rtx *) alloca (max_qty * sizeof (rtx));
440 qty_first_reg = (int *) alloca (max_qty * sizeof (int));
441 qty_size = (int *) alloca (max_qty * sizeof (int));
443 = (enum machine_mode *) alloca (max_qty * sizeof (enum machine_mode));
444 qty_n_calls_crossed = (int *) alloca (max_qty * sizeof (int));
446 = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
448 = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
449 qty_n_refs = (int *) alloca (max_qty * sizeof (int));
450 qty_changes_size = (char *) alloca (max_qty * sizeof (char));
452 reg_qty = (int *) alloca (max_regno * sizeof (int));
453 reg_offset = (char *) alloca (max_regno * sizeof (char));
454 reg_next_in_qty = (int *) alloca (max_regno * sizeof (int));
456 reg_renumber = (short *) oballoc (max_regno * sizeof (short));
457 for (i = 0; i < max_regno; i++)
458 reg_renumber[i] = -1;
460 /* Determine which pseudo-registers can be allocated by local-alloc.
461 In general, these are the registers used only in a single block and
462 which only die once. However, if a register's preferred class has only
463 a few entries, don't allocate this register here unless it is preferred
464 or nothing since retry_global_alloc won't be able to move it to
465 GENERAL_REGS if a reload register of this class is needed.
467 We need not be concerned with which block actually uses the register
468 since we will never see it outside that block. */
470 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
472 if (reg_basic_block[i] >= 0 && reg_n_deaths[i] == 1
473 && (reg_alternate_class (i) == NO_REGS
474 || ! CLASS_LIKELY_SPILLED_P (reg_preferred_class (i))))
480 /* Force loop below to initialize entire quantity array. */
483 /* Allocate each block's local registers, block by block. */
485 for (b = 0; b < n_basic_blocks; b++)
487 /* NEXT_QTY indicates which elements of the `qty_...'
488 vectors might need to be initialized because they were used
489 for the previous block; it is set to the entire array before
490 block 0. Initialize those, with explicit loop if there are few,
491 else with bzero and bcopy. Do not initialize vectors that are
492 explicit set by `alloc_qty'. */
496 for (i = 0; i < next_qty; i++)
498 qty_scratch_rtx[i] = 0;
499 CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]);
500 qty_phys_num_copy_sugg[i] = 0;
501 CLEAR_HARD_REG_SET (qty_phys_sugg[i]);
502 qty_phys_num_sugg[i] = 0;
507 #define CLEAR(vector) \
508 bzero ((char *) (vector), (sizeof (*(vector))) * next_qty);
510 CLEAR (qty_scratch_rtx);
511 CLEAR (qty_phys_copy_sugg);
512 CLEAR (qty_phys_num_copy_sugg);
513 CLEAR (qty_phys_sugg);
514 CLEAR (qty_phys_num_sugg);
526 /* Depth of loops we are in while in update_equiv_regs. */
527 static int loop_depth;
529 /* Used for communication between the following two functions: contains
530 a MEM that we wish to ensure remains unchanged. */
531 static rtx equiv_mem;
533 /* Set nonzero if EQUIV_MEM is modified. */
534 static int equiv_mem_modified;
536 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
537 Called via note_stores. */
540 validate_equiv_mem_from_store (dest, set)
544 if ((GET_CODE (dest) == REG
545 && reg_overlap_mentioned_p (dest, equiv_mem))
546 || (GET_CODE (dest) == MEM
547 && true_dependence (dest, equiv_mem)))
548 equiv_mem_modified = 1;
551 /* Verify that no store between START and the death of REG invalidates
552 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
553 by storing into an overlapping memory location, or with a non-const
556 Return 1 if MEMREF remains valid. */
559 validate_equiv_mem (start, reg, memref)
568 equiv_mem_modified = 0;
570 /* If the memory reference has side effects or is volatile, it isn't a
571 valid equivalence. */
572 if (side_effects_p (memref))
575 for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn))
577 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
580 if (find_reg_note (insn, REG_DEAD, reg))
583 if (GET_CODE (insn) == CALL_INSN && ! RTX_UNCHANGING_P (memref)
584 && ! CONST_CALL_P (insn))
587 note_stores (PATTERN (insn), validate_equiv_mem_from_store);
589 /* If a register mentioned in MEMREF is modified via an
590 auto-increment, we lose the equivalence. Do the same if one
591 dies; although we could extend the life, it doesn't seem worth
594 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
595 if ((REG_NOTE_KIND (note) == REG_INC
596 || REG_NOTE_KIND (note) == REG_DEAD)
597 && GET_CODE (XEXP (note, 0)) == REG
598 && reg_overlap_mentioned_p (XEXP (note, 0), memref))
605 /* TRUE if X references a memory location that would be affected by a store
609 memref_referenced_p (memref, x)
615 enum rtx_code code = GET_CODE (x);
631 return (reg_equiv_replacement[REGNO (x)]
632 && memref_referenced_p (memref,
633 reg_equiv_replacement[REGNO (x)]));
636 if (true_dependence (memref, x))
641 /* If we are setting a MEM, it doesn't count (its address does), but any
642 other SET_DEST that has a MEM in it is referencing the MEM. */
643 if (GET_CODE (SET_DEST (x)) == MEM)
645 if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0)))
648 else if (memref_referenced_p (memref, SET_DEST (x)))
651 return memref_referenced_p (memref, SET_SRC (x));
654 fmt = GET_RTX_FORMAT (code);
655 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
659 if (memref_referenced_p (memref, XEXP (x, i)))
663 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
664 if (memref_referenced_p (memref, XVECEXP (x, i, j)))
672 /* TRUE if some insn in the range (START, END] references a memory location
673 that would be affected by a store to MEMREF. */
676 memref_used_between_p (memref, start, end)
683 for (insn = NEXT_INSN (start); insn != NEXT_INSN (end);
684 insn = NEXT_INSN (insn))
685 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
686 && memref_referenced_p (memref, PATTERN (insn)))
692 /* INSN is a copy from SRC to DEST, both registers, and SRC does not die
695 Search forward to see if SRC dies before either it or DEST is modified,
696 but don't scan past the end of a basic block. If so, we can replace SRC
697 with DEST and let SRC die in INSN.
699 This will reduce the number of registers live in that range and may enable
700 DEST to be tied to SRC, thus often saving one register in addition to a
701 register-register copy. */
704 optimize_reg_copy_1 (insn, dest, src)
712 int sregno = REGNO (src);
713 int dregno = REGNO (dest);
716 #ifdef SMALL_REGISTER_CLASSES
717 /* We don't want to mess with hard regs if register classes are small. */
718 || (SMALL_REGISTER_CLASSES
719 && (sregno < FIRST_PSEUDO_REGISTER
720 || dregno < FIRST_PSEUDO_REGISTER))
722 /* We don't see all updates to SP if they are in an auto-inc memory
723 reference, so we must disallow this optimization on them. */
724 || sregno == STACK_POINTER_REGNUM || dregno == STACK_POINTER_REGNUM)
727 for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p))
729 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN
730 || (GET_CODE (p) == NOTE
731 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
732 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
735 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
738 if (reg_set_p (src, p) || reg_set_p (dest, p)
739 /* Don't change a USE of a register. */
740 || (GET_CODE (PATTERN (p)) == USE
741 && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0))))
744 /* See if all of SRC dies in P. This test is slightly more
745 conservative than it needs to be. */
746 if ((note = find_regno_note (p, REG_DEAD, sregno)) != 0
747 && GET_MODE (XEXP (note, 0)) == GET_MODE (src))
755 /* We can do the optimization. Scan forward from INSN again,
756 replacing regs as we go. Set FAILED if a replacement can't
757 be done. In that case, we can't move the death note for SRC.
758 This should be rare. */
760 /* Set to stop at next insn. */
761 for (q = next_real_insn (insn);
762 q != next_real_insn (p);
763 q = next_real_insn (q))
765 if (reg_overlap_mentioned_p (src, PATTERN (q)))
767 /* If SRC is a hard register, we might miss some
768 overlapping registers with validate_replace_rtx,
769 so we would have to undo it. We can't if DEST is
770 present in the insn, so fail in that combination
772 if (sregno < FIRST_PSEUDO_REGISTER
773 && reg_mentioned_p (dest, PATTERN (q)))
776 /* Replace all uses and make sure that the register
777 isn't still present. */
778 else if (validate_replace_rtx (src, dest, q)
779 && (sregno >= FIRST_PSEUDO_REGISTER
780 || ! reg_overlap_mentioned_p (src,
783 /* We assume that a register is used exactly once per
784 insn in the updates below. If this is not correct,
785 no great harm is done. */
786 if (sregno >= FIRST_PSEUDO_REGISTER)
787 reg_n_refs[sregno] -= loop_depth;
788 if (dregno >= FIRST_PSEUDO_REGISTER)
789 reg_n_refs[dregno] += loop_depth;
793 validate_replace_rtx (dest, src, q);
798 /* Count the insns and CALL_INSNs passed. If we passed the
799 death note of DEST, show increased live length. */
804 /* If the insn in which SRC dies is a CALL_INSN, don't count it
805 as a call that has been crossed. Otherwise, count it. */
806 if (q != p && GET_CODE (q) == CALL_INSN)
813 /* If DEST dies here, remove the death note and save it for
814 later. Make sure ALL of DEST dies here; again, this is
815 overly conservative. */
817 && (dest_death = find_regno_note (q, REG_DEAD, dregno)) != 0
818 && GET_MODE (XEXP (dest_death, 0)) == GET_MODE (dest))
819 remove_note (q, dest_death);
824 if (sregno >= FIRST_PSEUDO_REGISTER)
826 if (reg_live_length[sregno] >= 0)
828 reg_live_length[sregno] -= length;
829 /* reg_live_length is only an approximation after
830 combine if sched is not run, so make sure that we
831 still have a reasonable value. */
832 if (reg_live_length[sregno] < 2)
833 reg_live_length[sregno] = 2;
836 reg_n_calls_crossed[sregno] -= n_calls;
839 if (dregno >= FIRST_PSEUDO_REGISTER)
841 if (reg_live_length[dregno] >= 0)
842 reg_live_length[dregno] += d_length;
844 reg_n_calls_crossed[dregno] += d_n_calls;
847 /* Move death note of SRC from P to INSN. */
848 remove_note (p, note);
849 XEXP (note, 1) = REG_NOTES (insn);
850 REG_NOTES (insn) = note;
853 /* Put death note of DEST on P if we saw it die. */
856 XEXP (dest_death, 1) = REG_NOTES (p);
857 REG_NOTES (p) = dest_death;
863 /* If SRC is a hard register which is set or killed in some other
864 way, we can't do this optimization. */
865 else if (sregno < FIRST_PSEUDO_REGISTER
866 && dead_or_set_p (p, src))
871 /* INSN is a copy of SRC to DEST, in which SRC dies. See if we now have
872 a sequence of insns that modify DEST followed by an insn that sets
873 SRC to DEST in which DEST dies, with no prior modification of DEST.
874 (There is no need to check if the insns in between actually modify
875 DEST. We should not have cases where DEST is not modified, but
876 the optimization is safe if no such modification is detected.)
877 In that case, we can replace all uses of DEST, starting with INSN and
878 ending with the set of SRC to DEST, with SRC. We do not do this
879 optimization if a CALL_INSN is crossed unless SRC already crosses a
880 call or if DEST dies before the copy back to SRC.
882 It is assumed that DEST and SRC are pseudos; it is too complicated to do
883 this for hard registers since the substitutions we may make might fail. */
886 optimize_reg_copy_2 (insn, dest, src)
893 int sregno = REGNO (src);
894 int dregno = REGNO (dest);
896 for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p))
898 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN
899 || (GET_CODE (p) == NOTE
900 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
901 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
904 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
907 set = single_set (p);
908 if (set && SET_SRC (set) == dest && SET_DEST (set) == src
909 && find_reg_note (p, REG_DEAD, dest))
911 /* We can do the optimization. Scan forward from INSN again,
912 replacing regs as we go. */
914 /* Set to stop at next insn. */
915 for (q = insn; q != NEXT_INSN (p); q = NEXT_INSN (q))
916 if (GET_RTX_CLASS (GET_CODE (q)) == 'i')
918 if (reg_mentioned_p (dest, PATTERN (q)))
920 PATTERN (q) = replace_rtx (PATTERN (q), dest, src);
922 /* We assume that a register is used exactly once per
923 insn in the updates below. If this is not correct,
924 no great harm is done. */
925 reg_n_refs[dregno] -= loop_depth;
926 reg_n_refs[sregno] += loop_depth;
930 if (GET_CODE (q) == CALL_INSN)
932 reg_n_calls_crossed[dregno]--;
933 reg_n_calls_crossed[sregno]++;
937 remove_note (p, find_reg_note (p, REG_DEAD, dest));
938 reg_n_deaths[dregno]--;
939 remove_note (insn, find_reg_note (insn, REG_DEAD, src));
940 reg_n_deaths[sregno]--;
944 if (reg_set_p (src, p)
945 || find_reg_note (p, REG_DEAD, dest)
946 || (GET_CODE (p) == CALL_INSN && reg_n_calls_crossed[sregno] == 0))
951 /* Find registers that are equivalent to a single value throughout the
952 compilation (either because they can be referenced in memory or are set once
953 from a single constant). Lower their priority for a register.
955 If such a register is only referenced once, try substituting its value
956 into the using insn. If it succeeds, we can eliminate the register
962 rtx *reg_equiv_init_insn = (rtx *) alloca (max_regno * sizeof (rtx *));
963 /* Set when an attempt should be made to replace a register with the
964 associated reg_equiv_replacement entry at the end of this function. */
965 char *reg_equiv_replace
966 = (char *) alloca (max_regno * sizeof *reg_equiv_replace);
970 reg_equiv_replacement = (rtx *) alloca (max_regno * sizeof (rtx *));
972 bzero ((char *) reg_equiv_init_insn, max_regno * sizeof (rtx *));
973 bzero ((char *) reg_equiv_replacement, max_regno * sizeof (rtx *));
974 bzero ((char *) reg_equiv_replace, max_regno * sizeof *reg_equiv_replace);
976 init_alias_analysis ();
980 /* Scan the insns and find which registers have equivalences. Do this
981 in a separate scan of the insns because (due to -fcse-follow-jumps)
982 a register can be set below its use. */
983 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
986 rtx set = single_set (insn);
990 if (GET_CODE (insn) == NOTE)
992 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
994 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
998 /* If this insn contains more (or less) than a single SET, ignore it. */
1002 dest = SET_DEST (set);
1003 src = SET_SRC (set);
1005 /* If this sets a MEM to the contents of a REG that is only used
1006 in a single basic block, see if the register is always equivalent
1007 to that memory location and if moving the store from INSN to the
1008 insn that set REG is safe. If so, put a REG_EQUIV note on the
1009 initializing insn. */
1011 if (GET_CODE (dest) == MEM && GET_CODE (SET_SRC (set)) == REG
1012 && (regno = REGNO (SET_SRC (set))) >= FIRST_PSEUDO_REGISTER
1013 && reg_basic_block[regno] >= 0
1014 && reg_equiv_init_insn[regno] != 0
1015 && validate_equiv_mem (reg_equiv_init_insn[regno], SET_SRC (set),
1017 && ! memref_used_between_p (SET_DEST (set),
1018 reg_equiv_init_insn[regno], insn))
1019 REG_NOTES (reg_equiv_init_insn[regno])
1020 = gen_rtx (EXPR_LIST, REG_EQUIV, dest,
1021 REG_NOTES (reg_equiv_init_insn[regno]));
1023 /* If this is a register-register copy where SRC is not dead, see if we
1025 if (flag_expensive_optimizations && GET_CODE (dest) == REG
1026 && GET_CODE (SET_SRC (set)) == REG
1027 && ! find_reg_note (insn, REG_DEAD, SET_SRC (set)))
1028 optimize_reg_copy_1 (insn, dest, SET_SRC (set));
1030 /* Similarly for a pseudo-pseudo copy when SRC is dead. */
1031 else if (flag_expensive_optimizations && GET_CODE (dest) == REG
1032 && REGNO (dest) >= FIRST_PSEUDO_REGISTER
1033 && GET_CODE (SET_SRC (set)) == REG
1034 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER
1035 && find_reg_note (insn, REG_DEAD, SET_SRC (set)))
1036 optimize_reg_copy_2 (insn, dest, SET_SRC (set));
1038 /* Otherwise, we only handle the case of a pseudo register being set
1039 once and only if neither the source nor the destination are
1040 in a register class that's likely to be spilled. */
1041 if (GET_CODE (dest) != REG
1042 || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER
1043 || reg_n_sets[regno] != 1
1044 || CLASS_LIKELY_SPILLED_P (reg_preferred_class (REGNO (dest)))
1045 || (GET_CODE (src) == REG
1046 && REGNO (src) >= FIRST_PSEUDO_REGISTER
1047 && CLASS_LIKELY_SPILLED_P (reg_preferred_class (REGNO (src)))))
1050 note = find_reg_note (insn, REG_EQUAL, NULL_RTX);
1052 /* Record this insn as initializing this register. */
1053 reg_equiv_init_insn[regno] = insn;
1055 /* If this register is known to be equal to a constant, record that
1056 it is always equivalent to the constant. */
1057 if (note && CONSTANT_P (XEXP (note, 0)))
1058 PUT_MODE (note, (enum machine_mode) REG_EQUIV);
1060 /* If this insn introduces a "constant" register, decrease the priority
1061 of that register. Record this insn if the register is only used once
1062 more and the equivalence value is the same as our source.
1064 The latter condition is checked for two reasons: First, it is an
1065 indication that it may be more efficient to actually emit the insn
1066 as written (if no registers are available, reload will substitute
1067 the equivalence). Secondly, it avoids problems with any registers
1068 dying in this insn whose death notes would be missed.
1070 If we don't have a REG_EQUIV note, see if this insn is loading
1071 a register used only in one basic block from a MEM. If so, and the
1072 MEM remains unchanged for the life of the register, add a REG_EQUIV
1075 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
1077 if (note == 0 && reg_basic_block[regno] >= 0
1078 && GET_CODE (SET_SRC (set)) == MEM
1079 && validate_equiv_mem (insn, dest, SET_SRC (set)))
1080 REG_NOTES (insn) = note = gen_rtx (EXPR_LIST, REG_EQUIV, SET_SRC (set),
1085 int regno = REGNO (dest);
1087 reg_equiv_replacement[regno] = XEXP (note, 0);
1089 /* Don't mess with things live during setjmp. */
1090 if (reg_live_length[regno] >= 0)
1092 /* Note that the statement below does not affect the priority
1094 reg_live_length[regno] *= 2;
1097 /* If the register is referenced exactly twice, meaning it is
1098 set once and used once, indicate that the reference may be
1099 replaced by the equivalence we computed above. If the
1100 register is only used in one basic block, this can't succeed
1101 or combine would have done it.
1103 It would be nice to use "loop_depth * 2" in the compare
1104 below. Unfortunately, LOOP_DEPTH need not be constant within
1105 a basic block so this would be too complicated.
1107 This case normally occurs when a parameter is read from
1108 memory and then used exactly once, not in a loop. */
1110 if (reg_n_refs[regno] == 2
1111 && reg_basic_block[regno] < 0
1112 && rtx_equal_p (XEXP (note, 0), SET_SRC (set)))
1113 reg_equiv_replace[regno] = 1;
1118 /* Now scan all regs killed in an insn to see if any of them are
1119 registers only used that once. If so, see if we can replace the
1120 reference with the equivalent from. If we can, delete the
1121 initializing reference and this register will go away. If we
1122 can't replace the reference, and the instruction is not in a
1123 loop, then move the register initialization just before the use,
1124 so that they are in the same basic block. */
1127 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1131 /* Keep track of which basic block we are in. */
1132 if (block + 1 < n_basic_blocks
1133 && basic_block_head[block + 1] == insn)
1136 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
1138 if (GET_CODE (insn) == NOTE)
1140 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
1142 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
1153 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1155 if (REG_NOTE_KIND (link) == REG_DEAD
1156 /* Make sure this insn still refers to the register. */
1157 && reg_mentioned_p (XEXP (link, 0), PATTERN (insn)))
1159 int regno = REGNO (XEXP (link, 0));
1162 if (! reg_equiv_replace[regno])
1165 equiv_insn = reg_equiv_init_insn[regno];
1167 if (validate_replace_rtx (regno_reg_rtx[regno],
1168 reg_equiv_replacement[regno], insn))
1170 remove_death (regno, insn);
1171 reg_n_refs[regno] = 0;
1172 PUT_CODE (equiv_insn, NOTE);
1173 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1174 NOTE_SOURCE_FILE (equiv_insn) = 0;
1176 /* If we aren't in a loop, and there are no calls in
1177 INSN or in the initialization of the register, then
1178 move the initialization of the register to just
1179 before INSN. Update the flow information. */
1181 && GET_CODE (equiv_insn) == INSN
1182 && GET_CODE (insn) == INSN
1183 && reg_basic_block[regno] < 0)
1186 REGSET_ELT_TYPE bit;
1188 emit_insn_before (copy_rtx (PATTERN (equiv_insn)), insn);
1189 REG_NOTES (PREV_INSN (insn)) = REG_NOTES (equiv_insn);
1191 PUT_CODE (equiv_insn, NOTE);
1192 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1193 NOTE_SOURCE_FILE (equiv_insn) = 0;
1194 REG_NOTES (equiv_insn) = 0;
1197 reg_basic_block[regno] = 0;
1199 reg_basic_block[regno] = block;
1200 reg_n_calls_crossed[regno] = 0;
1201 reg_live_length[regno] = 2;
1203 if (block >= 0 && insn == basic_block_head[block])
1204 basic_block_head[block] = PREV_INSN (insn);
1206 offset = regno / REGSET_ELT_BITS;
1207 bit = ((REGSET_ELT_TYPE) 1
1208 << (regno % REGSET_ELT_BITS));
1209 for (l = 0; l < n_basic_blocks; l++)
1210 basic_block_live_at_start[l][offset] &= ~ bit;
1217 /* Allocate hard regs to the pseudo regs used only within block number B.
1218 Only the pseudos that die but once can be handled. */
1227 int insn_number = 0;
1229 int max_uid = get_max_uid ();
1231 int no_conflict_combined_regno = -1;
1232 /* Counter to prevent allocating more SCRATCHes than can be stored
1234 int scratches_allocated = scratch_index;
1236 /* Count the instructions in the basic block. */
1238 insn = basic_block_end[b];
1241 if (GET_CODE (insn) != NOTE)
1242 if (++insn_count > max_uid)
1244 if (insn == basic_block_head[b])
1246 insn = PREV_INSN (insn);
1249 /* +2 to leave room for a post_mark_life at the last insn and for
1250 the birth of a CLOBBER in the first insn. */
1251 regs_live_at = (HARD_REG_SET *) alloca ((2 * insn_count + 2)
1252 * sizeof (HARD_REG_SET));
1253 bzero ((char *) regs_live_at, (2 * insn_count + 2) * sizeof (HARD_REG_SET));
1255 /* Initialize table of hardware registers currently live. */
1258 regs_live = *basic_block_live_at_start[b];
1260 COPY_HARD_REG_SET (regs_live, basic_block_live_at_start[b]);
1263 /* This loop scans the instructions of the basic block
1264 and assigns quantities to registers.
1265 It computes which registers to tie. */
1267 insn = basic_block_head[b];
1270 register rtx body = PATTERN (insn);
1272 if (GET_CODE (insn) != NOTE)
1275 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1277 register rtx link, set;
1278 register int win = 0;
1279 register rtx r0, r1;
1280 int combined_regno = -1;
1282 int insn_code_number = recog_memoized (insn);
1284 this_insn_number = insn_number;
1287 if (insn_code_number >= 0)
1288 insn_extract (insn);
1289 which_alternative = -1;
1291 /* Is this insn suitable for tying two registers?
1292 If so, try doing that.
1293 Suitable insns are those with at least two operands and where
1294 operand 0 is an output that is a register that is not
1297 We can tie operand 0 with some operand that dies in this insn.
1298 First look for operands that are required to be in the same
1299 register as operand 0. If we find such, only try tying that
1300 operand or one that can be put into that operand if the
1301 operation is commutative. If we don't find an operand
1302 that is required to be in the same register as operand 0,
1303 we can tie with any operand.
1305 Subregs in place of regs are also ok.
1307 If tying is done, WIN is set nonzero. */
1309 if (insn_code_number >= 0
1310 #ifdef REGISTER_CONSTRAINTS
1311 && insn_n_operands[insn_code_number] > 1
1312 && insn_operand_constraint[insn_code_number][0][0] == '='
1313 && insn_operand_constraint[insn_code_number][0][1] != '&'
1315 && GET_CODE (PATTERN (insn)) == SET
1316 && rtx_equal_p (SET_DEST (PATTERN (insn)), recog_operand[0])
1320 #ifdef REGISTER_CONSTRAINTS
1321 /* If non-negative, is an operand that must match operand 0. */
1322 int must_match_0 = -1;
1323 /* Counts number of alternatives that require a match with
1325 int n_matching_alts = 0;
1327 for (i = 1; i < insn_n_operands[insn_code_number]; i++)
1329 char *p = insn_operand_constraint[insn_code_number][i];
1330 int this_match = (requires_inout (p));
1332 n_matching_alts += this_match;
1333 if (this_match == insn_n_alternatives[insn_code_number])
1338 r0 = recog_operand[0];
1339 for (i = 1; i < insn_n_operands[insn_code_number]; i++)
1341 #ifdef REGISTER_CONSTRAINTS
1342 /* Skip this operand if we found an operand that
1343 must match operand 0 and this operand isn't it
1344 and can't be made to be it by commutativity. */
1346 if (must_match_0 >= 0 && i != must_match_0
1347 && ! (i == must_match_0 + 1
1348 && insn_operand_constraint[insn_code_number][i-1][0] == '%')
1349 && ! (i == must_match_0 - 1
1350 && insn_operand_constraint[insn_code_number][i][0] == '%'))
1353 /* Likewise if each alternative has some operand that
1354 must match operand zero. In that case, skip any
1355 operand that doesn't list operand 0 since we know that
1356 the operand always conflicts with operand 0. We
1357 ignore commutatity in this case to keep things simple. */
1358 if (n_matching_alts == insn_n_alternatives[insn_code_number]
1359 && (0 == requires_inout
1360 (insn_operand_constraint[insn_code_number][i])))
1364 r1 = recog_operand[i];
1366 /* If the operand is an address, find a register in it.
1367 There may be more than one register, but we only try one
1370 #ifdef REGISTER_CONSTRAINTS
1371 insn_operand_constraint[insn_code_number][i][0] == 'p'
1373 insn_operand_address_p[insn_code_number][i]
1376 while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT)
1379 if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG)
1381 /* We have two priorities for hard register preferences.
1382 If we have a move insn or an insn whose first input
1383 can only be in the same register as the output, give
1384 priority to an equivalence found from that insn. */
1386 = ((SET_DEST (body) == r0 && SET_SRC (body) == r1)
1387 #ifdef REGISTER_CONSTRAINTS
1388 || (r1 == recog_operand[i] && must_match_0 >= 0)
1392 if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1393 win = combine_regs (r1, r0, may_save_copy,
1394 insn_number, insn, 0);
1401 /* Recognize an insn sequence with an ultimate result
1402 which can safely overlap one of the inputs.
1403 The sequence begins with a CLOBBER of its result,
1404 and ends with an insn that copies the result to itself
1405 and has a REG_EQUAL note for an equivalent formula.
1406 That note indicates what the inputs are.
1407 The result and the input can overlap if each insn in
1408 the sequence either doesn't mention the input
1409 or has a REG_NO_CONFLICT note to inhibit the conflict.
1411 We do the combining test at the CLOBBER so that the
1412 destination register won't have had a quantity number
1413 assigned, since that would prevent combining. */
1415 if (GET_CODE (PATTERN (insn)) == CLOBBER
1416 && (r0 = XEXP (PATTERN (insn), 0),
1417 GET_CODE (r0) == REG)
1418 && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0
1419 && XEXP (link, 0) != 0
1420 && GET_CODE (XEXP (link, 0)) == INSN
1421 && (set = single_set (XEXP (link, 0))) != 0
1422 && SET_DEST (set) == r0 && SET_SRC (set) == r0
1423 && (note = find_reg_note (XEXP (link, 0), REG_EQUAL,
1426 if (r1 = XEXP (note, 0), GET_CODE (r1) == REG
1427 /* Check that we have such a sequence. */
1428 && no_conflict_p (insn, r0, r1))
1429 win = combine_regs (r1, r0, 1, insn_number, insn, 1);
1430 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e'
1431 && (r1 = XEXP (XEXP (note, 0), 0),
1432 GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1433 && no_conflict_p (insn, r0, r1))
1434 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1436 /* Here we care if the operation to be computed is
1438 else if ((GET_CODE (XEXP (note, 0)) == EQ
1439 || GET_CODE (XEXP (note, 0)) == NE
1440 || GET_RTX_CLASS (GET_CODE (XEXP (note, 0))) == 'c')
1441 && (r1 = XEXP (XEXP (note, 0), 1),
1442 (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG))
1443 && no_conflict_p (insn, r0, r1))
1444 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1446 /* If we did combine something, show the register number
1447 in question so that we know to ignore its death. */
1449 no_conflict_combined_regno = REGNO (r1);
1452 /* If registers were just tied, set COMBINED_REGNO
1453 to the number of the register used in this insn
1454 that was tied to the register set in this insn.
1455 This register's qty should not be "killed". */
1459 while (GET_CODE (r1) == SUBREG)
1460 r1 = SUBREG_REG (r1);
1461 combined_regno = REGNO (r1);
1464 /* Mark the death of everything that dies in this instruction,
1465 except for anything that was just combined. */
1467 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1468 if (REG_NOTE_KIND (link) == REG_DEAD
1469 && GET_CODE (XEXP (link, 0)) == REG
1470 && combined_regno != REGNO (XEXP (link, 0))
1471 && (no_conflict_combined_regno != REGNO (XEXP (link, 0))
1472 || ! find_reg_note (insn, REG_NO_CONFLICT, XEXP (link, 0))))
1473 wipe_dead_reg (XEXP (link, 0), 0);
1475 /* Allocate qty numbers for all registers local to this block
1476 that are born (set) in this instruction.
1477 A pseudo that already has a qty is not changed. */
1479 note_stores (PATTERN (insn), reg_is_set);
1481 /* If anything is set in this insn and then unused, mark it as dying
1482 after this insn, so it will conflict with our outputs. This
1483 can't match with something that combined, and it doesn't matter
1484 if it did. Do this after the calls to reg_is_set since these
1485 die after, not during, the current insn. */
1487 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1488 if (REG_NOTE_KIND (link) == REG_UNUSED
1489 && GET_CODE (XEXP (link, 0)) == REG)
1490 wipe_dead_reg (XEXP (link, 0), 1);
1492 /* Allocate quantities for any SCRATCH operands of this insn. */
1494 if (insn_code_number >= 0)
1495 for (i = 0; i < insn_n_operands[insn_code_number]; i++)
1496 if (GET_CODE (recog_operand[i]) == SCRATCH
1497 && scratches_allocated++ < scratch_list_length)
1498 alloc_qty_for_scratch (recog_operand[i], i, insn,
1499 insn_code_number, insn_number);
1501 /* If this is an insn that has a REG_RETVAL note pointing at a
1502 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1503 block, so clear any register number that combined within it. */
1504 if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0
1505 && GET_CODE (XEXP (note, 0)) == INSN
1506 && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER)
1507 no_conflict_combined_regno = -1;
1510 /* Set the registers live after INSN_NUMBER. Note that we never
1511 record the registers live before the block's first insn, since no
1512 pseudos we care about are live before that insn. */
1514 IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live);
1515 IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live);
1517 if (insn == basic_block_end[b])
1520 insn = NEXT_INSN (insn);
1523 /* Now every register that is local to this basic block
1524 should have been given a quantity, or else -1 meaning ignore it.
1525 Every quantity should have a known birth and death.
1527 Order the qtys so we assign them registers in order of the
1528 number of suggested registers they need so we allocate those with
1529 the most restrictive needs first. */
1531 qty_order = (int *) alloca (next_qty * sizeof (int));
1532 for (i = 0; i < next_qty; i++)
1535 #define EXCHANGE(I1, I2) \
1536 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1541 /* Make qty_order[2] be the one to allocate last. */
1542 if (qty_sugg_compare (0, 1) > 0)
1544 if (qty_sugg_compare (1, 2) > 0)
1547 /* ... Fall through ... */
1549 /* Put the best one to allocate in qty_order[0]. */
1550 if (qty_sugg_compare (0, 1) > 0)
1553 /* ... Fall through ... */
1557 /* Nothing to do here. */
1561 qsort (qty_order, next_qty, sizeof (int), qty_sugg_compare_1);
1564 /* Try to put each quantity in a suggested physical register, if it has one.
1565 This may cause registers to be allocated that otherwise wouldn't be, but
1566 this seems acceptable in local allocation (unlike global allocation). */
1567 for (i = 0; i < next_qty; i++)
1570 if (qty_phys_num_sugg[q] != 0 || qty_phys_num_copy_sugg[q] != 0)
1571 qty_phys_reg[q] = find_free_reg (qty_min_class[q], qty_mode[q], q,
1572 0, 1, qty_birth[q], qty_death[q]);
1574 qty_phys_reg[q] = -1;
1577 /* Order the qtys so we assign them registers in order of
1578 decreasing length of life. Normally call qsort, but if we
1579 have only a very small number of quantities, sort them ourselves. */
1581 for (i = 0; i < next_qty; i++)
1584 #define EXCHANGE(I1, I2) \
1585 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1590 /* Make qty_order[2] be the one to allocate last. */
1591 if (qty_compare (0, 1) > 0)
1593 if (qty_compare (1, 2) > 0)
1596 /* ... Fall through ... */
1598 /* Put the best one to allocate in qty_order[0]. */
1599 if (qty_compare (0, 1) > 0)
1602 /* ... Fall through ... */
1606 /* Nothing to do here. */
1610 qsort (qty_order, next_qty, sizeof (int), qty_compare_1);
1613 /* Now for each qty that is not a hardware register,
1614 look for a hardware register to put it in.
1615 First try the register class that is cheapest for this qty,
1616 if there is more than one class. */
1618 for (i = 0; i < next_qty; i++)
1621 if (qty_phys_reg[q] < 0)
1623 if (N_REG_CLASSES > 1)
1625 qty_phys_reg[q] = find_free_reg (qty_min_class[q],
1626 qty_mode[q], q, 0, 0,
1627 qty_birth[q], qty_death[q]);
1628 if (qty_phys_reg[q] >= 0)
1632 if (qty_alternate_class[q] != NO_REGS)
1633 qty_phys_reg[q] = find_free_reg (qty_alternate_class[q],
1634 qty_mode[q], q, 0, 0,
1635 qty_birth[q], qty_death[q]);
1639 /* Now propagate the register assignments
1640 to the pseudo regs belonging to the qtys. */
1642 for (q = 0; q < next_qty; q++)
1643 if (qty_phys_reg[q] >= 0)
1645 for (i = qty_first_reg[q]; i >= 0; i = reg_next_in_qty[i])
1646 reg_renumber[i] = qty_phys_reg[q] + reg_offset[i];
1647 if (qty_scratch_rtx[q])
1649 if (GET_CODE (qty_scratch_rtx[q]) == REG)
1651 PUT_CODE (qty_scratch_rtx[q], REG);
1652 REGNO (qty_scratch_rtx[q]) = qty_phys_reg[q];
1654 scratch_block[scratch_index] = b;
1655 scratch_list[scratch_index++] = qty_scratch_rtx[q];
1657 /* Must clear the USED field, because it will have been set by
1658 copy_rtx_if_shared, but the leaf_register code expects that
1659 it is zero in all REG rtx. copy_rtx_if_shared does not set the
1660 used bit for REGs, but does for SCRATCHes. */
1661 qty_scratch_rtx[q]->used = 0;
1666 /* Compare two quantities' priority for getting real registers.
1667 We give shorter-lived quantities higher priority.
1668 Quantities with more references are also preferred, as are quantities that
1669 require multiple registers. This is the identical prioritization as
1670 done by global-alloc.
1672 We used to give preference to registers with *longer* lives, but using
1673 the same algorithm in both local- and global-alloc can speed up execution
1674 of some programs by as much as a factor of three! */
1676 /* Note that the quotient will never be bigger than
1677 the value of floor_log2 times the maximum number of
1678 times a register can occur in one insn (surely less than 100).
1679 Multiplying this by 10000 can't overflow.
1680 QTY_CMP_PRI is also used by qty_sugg_compare. */
1682 #define QTY_CMP_PRI(q) \
1683 ((int) (((double) (floor_log2 (qty_n_refs[q]) * qty_n_refs[q] * qty_size[q]) \
1684 / (qty_death[q] - qty_birth[q])) * 10000))
1687 qty_compare (q1, q2)
1690 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1694 qty_compare_1 (q1p, q2p)
1695 const GENERIC_PTR q1p;
1696 const GENERIC_PTR q2p;
1698 register int q1 = *(int *)q1p, q2 = *(int *)q2p;
1699 register int tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1704 /* If qtys are equally good, sort by qty number,
1705 so that the results of qsort leave nothing to chance. */
1709 /* Compare two quantities' priority for getting real registers. This version
1710 is called for quantities that have suggested hard registers. First priority
1711 goes to quantities that have copy preferences, then to those that have
1712 normal preferences. Within those groups, quantities with the lower
1713 number of preferences have the highest priority. Of those, we use the same
1714 algorithm as above. */
1716 #define QTY_CMP_SUGG(q) \
1717 (qty_phys_num_copy_sugg[q] \
1718 ? qty_phys_num_copy_sugg[q] \
1719 : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER)
1722 qty_sugg_compare (q1, q2)
1725 register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1730 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1734 qty_sugg_compare_1 (q1p, q2p)
1735 const GENERIC_PTR q1p;
1736 const GENERIC_PTR q2p;
1738 register int q1 = *(int *)q1p, q2 = *(int *)q2p;
1739 register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1744 tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1748 /* If qtys are equally good, sort by qty number,
1749 so that the results of qsort leave nothing to chance. */
1756 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1757 Returns 1 if have done so, or 0 if cannot.
1759 Combining registers means marking them as having the same quantity
1760 and adjusting the offsets within the quantity if either of
1763 We don't actually combine a hard reg with a pseudo; instead
1764 we just record the hard reg as the suggestion for the pseudo's quantity.
1765 If we really combined them, we could lose if the pseudo lives
1766 across an insn that clobbers the hard reg (eg, movstr).
1768 ALREADY_DEAD is non-zero if USEDREG is known to be dead even though
1769 there is no REG_DEAD note on INSN. This occurs during the processing
1770 of REG_NO_CONFLICT blocks.
1772 MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
1773 SETREG or if the input and output must share a register.
1774 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1776 There are elaborate checks for the validity of combining. */
1780 combine_regs (usedreg, setreg, may_save_copy, insn_number, insn, already_dead)
1781 rtx usedreg, setreg;
1787 register int ureg, sreg;
1788 register int offset = 0;
1792 /* Determine the numbers and sizes of registers being used. If a subreg
1793 is present that does not change the entire register, don't consider
1794 this a copy insn. */
1796 while (GET_CODE (usedreg) == SUBREG)
1798 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg))) > UNITS_PER_WORD)
1800 offset += SUBREG_WORD (usedreg);
1801 usedreg = SUBREG_REG (usedreg);
1803 if (GET_CODE (usedreg) != REG)
1805 ureg = REGNO (usedreg);
1806 usize = REG_SIZE (usedreg);
1808 while (GET_CODE (setreg) == SUBREG)
1810 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg))) > UNITS_PER_WORD)
1812 offset -= SUBREG_WORD (setreg);
1813 setreg = SUBREG_REG (setreg);
1815 if (GET_CODE (setreg) != REG)
1817 sreg = REGNO (setreg);
1818 ssize = REG_SIZE (setreg);
1820 /* If UREG is a pseudo-register that hasn't already been assigned a
1821 quantity number, it means that it is not local to this block or dies
1822 more than once. In either event, we can't do anything with it. */
1823 if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0)
1824 /* Do not combine registers unless one fits within the other. */
1825 || (offset > 0 && usize + offset > ssize)
1826 || (offset < 0 && usize + offset < ssize)
1827 /* Do not combine with a smaller already-assigned object
1828 if that smaller object is already combined with something bigger. */
1829 || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER
1830 && usize < qty_size[reg_qty[ureg]])
1831 /* Can't combine if SREG is not a register we can allocate. */
1832 || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1)
1833 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1834 These have already been taken care of. This probably wouldn't
1835 combine anyway, but don't take any chances. */
1836 || (ureg >= FIRST_PSEUDO_REGISTER
1837 && find_reg_note (insn, REG_NO_CONFLICT, usedreg))
1838 /* Don't tie something to itself. In most cases it would make no
1839 difference, but it would screw up if the reg being tied to itself
1840 also dies in this insn. */
1842 /* Don't try to connect two different hardware registers. */
1843 || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER)
1844 /* Don't connect two different machine modes if they have different
1845 implications as to which registers may be used. */
1846 || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg)))
1849 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1850 qty_phys_sugg for the pseudo instead of tying them.
1852 Return "failure" so that the lifespan of UREG is terminated here;
1853 that way the two lifespans will be disjoint and nothing will prevent
1854 the pseudo reg from being given this hard reg. */
1856 if (ureg < FIRST_PSEUDO_REGISTER)
1858 /* Allocate a quantity number so we have a place to put our
1860 if (reg_qty[sreg] == -2)
1861 reg_is_born (setreg, 2 * insn_number);
1863 if (reg_qty[sreg] >= 0)
1866 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg))
1868 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg);
1869 qty_phys_num_copy_sugg[reg_qty[sreg]]++;
1871 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg))
1873 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg);
1874 qty_phys_num_sugg[reg_qty[sreg]]++;
1880 /* Similarly for SREG a hard register and UREG a pseudo register. */
1882 if (sreg < FIRST_PSEUDO_REGISTER)
1885 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg))
1887 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg);
1888 qty_phys_num_copy_sugg[reg_qty[ureg]]++;
1890 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg))
1892 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg);
1893 qty_phys_num_sugg[reg_qty[ureg]]++;
1898 /* At this point we know that SREG and UREG are both pseudos.
1899 Do nothing if SREG already has a quantity or is a register that we
1901 if (reg_qty[sreg] >= -1
1902 /* If we are not going to let any regs live across calls,
1903 don't tie a call-crossing reg to a non-call-crossing reg. */
1904 || (current_function_has_nonlocal_label
1905 && ((reg_n_calls_crossed[ureg] > 0)
1906 != (reg_n_calls_crossed[sreg] > 0))))
1909 /* We don't already know about SREG, so tie it to UREG
1910 if this is the last use of UREG, provided the classes they want
1913 if ((already_dead || find_regno_note (insn, REG_DEAD, ureg))
1914 && reg_meets_class_p (sreg, qty_min_class[reg_qty[ureg]]))
1916 /* Add SREG to UREG's quantity. */
1917 sqty = reg_qty[ureg];
1918 reg_qty[sreg] = sqty;
1919 reg_offset[sreg] = reg_offset[ureg] + offset;
1920 reg_next_in_qty[sreg] = qty_first_reg[sqty];
1921 qty_first_reg[sqty] = sreg;
1923 /* If SREG's reg class is smaller, set qty_min_class[SQTY]. */
1924 update_qty_class (sqty, sreg);
1926 /* Update info about quantity SQTY. */
1927 qty_n_calls_crossed[sqty] += reg_n_calls_crossed[sreg];
1928 qty_n_refs[sqty] += reg_n_refs[sreg];
1933 for (i = qty_first_reg[sqty]; i >= 0; i = reg_next_in_qty[i])
1934 reg_offset[i] -= offset;
1936 qty_size[sqty] = ssize;
1937 qty_mode[sqty] = GET_MODE (setreg);
1946 /* Return 1 if the preferred class of REG allows it to be tied
1947 to a quantity or register whose class is CLASS.
1948 True if REG's reg class either contains or is contained in CLASS. */
1951 reg_meets_class_p (reg, class)
1953 enum reg_class class;
1955 register enum reg_class rclass = reg_preferred_class (reg);
1956 return (reg_class_subset_p (rclass, class)
1957 || reg_class_subset_p (class, rclass));
1960 /* Return 1 if the two specified classes have registers in common.
1961 If CALL_SAVED, then consider only call-saved registers. */
1964 reg_classes_overlap_p (c1, c2, call_saved)
1965 register enum reg_class c1;
1966 register enum reg_class c2;
1972 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
1973 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
1975 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1976 if (TEST_HARD_REG_BIT (c, i)
1977 && (! call_saved || ! call_used_regs[i]))
1983 /* Update the class of QTY assuming that REG is being tied to it. */
1986 update_qty_class (qty, reg)
1990 enum reg_class rclass = reg_preferred_class (reg);
1991 if (reg_class_subset_p (rclass, qty_min_class[qty]))
1992 qty_min_class[qty] = rclass;
1994 rclass = reg_alternate_class (reg);
1995 if (reg_class_subset_p (rclass, qty_alternate_class[qty]))
1996 qty_alternate_class[qty] = rclass;
1998 if (reg_changes_size[reg])
1999 qty_changes_size[qty] = 1;
2002 /* Handle something which alters the value of an rtx REG.
2004 REG is whatever is set or clobbered. SETTER is the rtx that
2005 is modifying the register.
2007 If it is not really a register, we do nothing.
2008 The file-global variables `this_insn' and `this_insn_number'
2009 carry info from `block_alloc'. */
2012 reg_is_set (reg, setter)
2016 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
2017 a hard register. These may actually not exist any more. */
2019 if (GET_CODE (reg) != SUBREG
2020 && GET_CODE (reg) != REG)
2023 /* Mark this register as being born. If it is used in a CLOBBER, mark
2024 it as being born halfway between the previous insn and this insn so that
2025 it conflicts with our inputs but not the outputs of the previous insn. */
2027 reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER));
2030 /* Handle beginning of the life of register REG.
2031 BIRTH is the index at which this is happening. */
2034 reg_is_born (reg, birth)
2040 if (GET_CODE (reg) == SUBREG)
2041 regno = REGNO (SUBREG_REG (reg)) + SUBREG_WORD (reg);
2043 regno = REGNO (reg);
2045 if (regno < FIRST_PSEUDO_REGISTER)
2047 mark_life (regno, GET_MODE (reg), 1);
2049 /* If the register was to have been born earlier that the present
2050 insn, mark it as live where it is actually born. */
2051 if (birth < 2 * this_insn_number)
2052 post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number);
2056 if (reg_qty[regno] == -2)
2057 alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth);
2059 /* If this register has a quantity number, show that it isn't dead. */
2060 if (reg_qty[regno] >= 0)
2061 qty_death[reg_qty[regno]] = -1;
2065 /* Record the death of REG in the current insn. If OUTPUT_P is non-zero,
2066 REG is an output that is dying (i.e., it is never used), otherwise it
2067 is an input (the normal case).
2068 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
2071 wipe_dead_reg (reg, output_p)
2075 register int regno = REGNO (reg);
2077 /* If this insn has multiple results,
2078 and the dead reg is used in one of the results,
2079 extend its life to after this insn,
2080 so it won't get allocated together with any other result of this insn. */
2081 if (GET_CODE (PATTERN (this_insn)) == PARALLEL
2082 && !single_set (this_insn))
2085 for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--)
2087 rtx set = XVECEXP (PATTERN (this_insn), 0, i);
2088 if (GET_CODE (set) == SET
2089 && GET_CODE (SET_DEST (set)) != REG
2090 && !rtx_equal_p (reg, SET_DEST (set))
2091 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2096 /* If this register is used in an auto-increment address, then extend its
2097 life to after this insn, so that it won't get allocated together with
2098 the result of this insn. */
2099 if (! output_p && find_regno_note (this_insn, REG_INC, regno))
2102 if (regno < FIRST_PSEUDO_REGISTER)
2104 mark_life (regno, GET_MODE (reg), 0);
2106 /* If a hard register is dying as an output, mark it as in use at
2107 the beginning of this insn (the above statement would cause this
2110 post_mark_life (regno, GET_MODE (reg), 1,
2111 2 * this_insn_number, 2 * this_insn_number+ 1);
2114 else if (reg_qty[regno] >= 0)
2115 qty_death[reg_qty[regno]] = 2 * this_insn_number + output_p;
2118 /* Find a block of SIZE words of hard regs in reg_class CLASS
2119 that can hold something of machine-mode MODE
2120 (but actually we test only the first of the block for holding MODE)
2121 and still free between insn BORN_INDEX and insn DEAD_INDEX,
2122 and return the number of the first of them.
2123 Return -1 if such a block cannot be found.
2124 If QTY crosses calls, insist on a register preserved by calls,
2125 unless ACCEPT_CALL_CLOBBERED is nonzero.
2127 If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
2128 register is available. If not, return -1. */
2131 find_free_reg (class, mode, qty, accept_call_clobbered, just_try_suggested,
2132 born_index, dead_index)
2133 enum reg_class class;
2134 enum machine_mode mode;
2136 int accept_call_clobbered;
2137 int just_try_suggested;
2138 int born_index, dead_index;
2140 register int i, ins;
2142 register /* Declare it register if it's a scalar. */
2144 HARD_REG_SET used, first_used;
2145 #ifdef ELIMINABLE_REGS
2146 static struct {int from, to; } eliminables[] = ELIMINABLE_REGS;
2149 /* Validate our parameters. */
2150 if (born_index < 0 || born_index > dead_index)
2153 /* Don't let a pseudo live in a reg across a function call
2154 if we might get a nonlocal goto. */
2155 if (current_function_has_nonlocal_label
2156 && qty_n_calls_crossed[qty] > 0)
2159 if (accept_call_clobbered)
2160 COPY_HARD_REG_SET (used, call_fixed_reg_set);
2161 else if (qty_n_calls_crossed[qty] == 0)
2162 COPY_HARD_REG_SET (used, fixed_reg_set);
2164 COPY_HARD_REG_SET (used, call_used_reg_set);
2166 if (accept_call_clobbered)
2167 IOR_HARD_REG_SET (used, losing_caller_save_reg_set);
2169 for (ins = born_index; ins < dead_index; ins++)
2170 IOR_HARD_REG_SET (used, regs_live_at[ins]);
2172 IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]);
2174 /* Don't use the frame pointer reg in local-alloc even if
2175 we may omit the frame pointer, because if we do that and then we
2176 need a frame pointer, reload won't know how to move the pseudo
2177 to another hard reg. It can move only regs made by global-alloc.
2179 This is true of any register that can be eliminated. */
2180 #ifdef ELIMINABLE_REGS
2181 for (i = 0; i < sizeof eliminables / sizeof eliminables[0]; i++)
2182 SET_HARD_REG_BIT (used, eliminables[i].from);
2183 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
2184 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
2185 that it might be eliminated into. */
2186 SET_HARD_REG_BIT (used, HARD_FRAME_POINTER_REGNUM);
2189 SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM);
2192 #ifdef CLASS_CANNOT_CHANGE_SIZE
2193 if (qty_changes_size[qty])
2194 IOR_HARD_REG_SET (used,
2195 reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE]);
2198 /* Normally, the registers that can be used for the first register in
2199 a multi-register quantity are the same as those that can be used for
2200 subsequent registers. However, if just trying suggested registers,
2201 restrict our consideration to them. If there are copy-suggested
2202 register, try them. Otherwise, try the arithmetic-suggested
2204 COPY_HARD_REG_SET (first_used, used);
2206 if (just_try_suggested)
2208 if (qty_phys_num_copy_sugg[qty] != 0)
2209 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qty]);
2211 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qty]);
2214 /* If all registers are excluded, we can't do anything. */
2215 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail);
2217 /* If at least one would be suitable, test each hard reg. */
2219 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2221 #ifdef REG_ALLOC_ORDER
2222 int regno = reg_alloc_order[i];
2226 if (! TEST_HARD_REG_BIT (first_used, regno)
2227 && HARD_REGNO_MODE_OK (regno, mode))
2230 register int size1 = HARD_REGNO_NREGS (regno, mode);
2231 for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++);
2234 /* Mark that this register is in use between its birth and death
2236 post_mark_life (regno, mode, 1, born_index, dead_index);
2239 #ifndef REG_ALLOC_ORDER
2240 i += j; /* Skip starting points we know will lose */
2247 /* If we are just trying suggested register, we have just tried copy-
2248 suggested registers, and there are arithmetic-suggested registers,
2251 /* If it would be profitable to allocate a call-clobbered register
2252 and save and restore it around calls, do that. */
2253 if (just_try_suggested && qty_phys_num_copy_sugg[qty] != 0
2254 && qty_phys_num_sugg[qty] != 0)
2256 /* Don't try the copy-suggested regs again. */
2257 qty_phys_num_copy_sugg[qty] = 0;
2258 return find_free_reg (class, mode, qty, accept_call_clobbered, 1,
2259 born_index, dead_index);
2262 /* We need not check to see if the current function has nonlocal
2263 labels because we don't put any pseudos that are live over calls in
2264 registers in that case. */
2266 if (! accept_call_clobbered
2267 && flag_caller_saves
2268 && ! just_try_suggested
2269 && qty_n_calls_crossed[qty] != 0
2270 && CALLER_SAVE_PROFITABLE (qty_n_refs[qty], qty_n_calls_crossed[qty]))
2272 i = find_free_reg (class, mode, qty, 1, 0, born_index, dead_index);
2274 caller_save_needed = 1;
2280 /* Mark that REGNO with machine-mode MODE is live starting from the current
2281 insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE
2285 mark_life (regno, mode, life)
2287 enum machine_mode mode;
2290 register int j = HARD_REGNO_NREGS (regno, mode);
2293 SET_HARD_REG_BIT (regs_live, regno + j);
2296 CLEAR_HARD_REG_BIT (regs_live, regno + j);
2299 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2300 is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2301 to insn number DEATH (exclusive). */
2304 post_mark_life (regno, mode, life, birth, death)
2306 enum machine_mode mode;
2307 int life, birth, death;
2309 register int j = HARD_REGNO_NREGS (regno, mode);
2311 register /* Declare it register if it's a scalar. */
2313 HARD_REG_SET this_reg;
2315 CLEAR_HARD_REG_SET (this_reg);
2317 SET_HARD_REG_BIT (this_reg, regno + j);
2320 while (birth < death)
2322 IOR_HARD_REG_SET (regs_live_at[birth], this_reg);
2326 while (birth < death)
2328 AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg);
2333 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2334 is the register being clobbered, and R1 is a register being used in
2335 the equivalent expression.
2337 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2338 in which it is used, return 1.
2340 Otherwise, return 0. */
2343 no_conflict_p (insn, r0, r1)
2347 rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
2350 /* If R1 is a hard register, return 0 since we handle this case
2351 when we scan the insns that actually use it. */
2354 || (GET_CODE (r1) == REG && REGNO (r1) < FIRST_PSEUDO_REGISTER)
2355 || (GET_CODE (r1) == SUBREG && GET_CODE (SUBREG_REG (r1)) == REG
2356 && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER))
2359 last = XEXP (note, 0);
2361 for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p))
2362 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
2364 if (find_reg_note (p, REG_DEAD, r1))
2367 /* There must be a REG_NO_CONFLICT note on every insn, otherwise
2368 some earlier optimization pass has inserted instructions into
2369 the sequence, and it is not safe to perform this optimization.
2370 Note that emit_no_conflict_block always ensures that this is
2371 true when these sequences are created. */
2372 if (! find_reg_note (p, REG_NO_CONFLICT, r1))
2379 #ifdef REGISTER_CONSTRAINTS
2381 /* Return the number of alternatives for which the constraint string P
2382 indicates that the operand must be equal to operand 0 and that no register
2391 int reg_allowed = 0;
2392 int num_matching_alts = 0;
2397 case '=': case '+': case '?':
2398 case '#': case '&': case '!':
2400 case '1': case '2': case '3': case '4':
2401 case 'm': case '<': case '>': case 'V': case 'o':
2402 case 'E': case 'F': case 'G': case 'H':
2403 case 's': case 'i': case 'n':
2404 case 'I': case 'J': case 'K': case 'L':
2405 case 'M': case 'N': case 'O': case 'P':
2406 #ifdef EXTRA_CONSTRAINT
2407 case 'Q': case 'R': case 'S': case 'T': case 'U':
2410 /* These don't say anything we care about. */
2414 if (found_zero && ! reg_allowed)
2415 num_matching_alts++;
2417 found_zero = reg_allowed = 0;
2431 if (found_zero && ! reg_allowed)
2432 num_matching_alts++;
2434 return num_matching_alts;
2436 #endif /* REGISTER_CONSTRAINTS */
2439 dump_local_alloc (file)
2443 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2444 if (reg_renumber[i] != -1)
2445 fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]);
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