1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 1988, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
23 /* Allocation of hard register numbers to pseudo registers is done in
24 two passes. In this pass we consider only regs that are born and
25 die once within one basic block. We do this one basic block at a
26 time. Then the next pass allocates the registers that remain.
27 Two passes are used because this pass uses methods that work only
28 on linear code, but that do a better job than the general methods
29 used in global_alloc, and more quickly too.
31 The assignments made are recorded in the vector reg_renumber
32 whose space is allocated here. The rtl code itself is not altered.
34 We assign each instruction in the basic block a number
35 which is its order from the beginning of the block.
36 Then we can represent the lifetime of a pseudo register with
37 a pair of numbers, and check for conflicts easily.
38 We can record the availability of hard registers with a
39 HARD_REG_SET for each instruction. The HARD_REG_SET
40 contains 0 or 1 for each hard reg.
42 To avoid register shuffling, we tie registers together when one
43 dies by being copied into another, or dies in an instruction that
44 does arithmetic to produce another. The tied registers are
45 allocated as one. Registers with different reg class preferences
46 can never be tied unless the class preferred by one is a subclass
47 of the one preferred by the other.
49 Tying is represented with "quantity numbers".
50 A non-tied register is given a new quantity number.
51 Tied registers have the same quantity number.
53 We have provision to exempt registers, even when they are contained
54 within the block, that can be tied to others that are not contained in it.
55 This is so that global_alloc could process them both and tie them then.
56 But this is currently disabled since tying in global_alloc is not
59 /* Pseudos allocated here can be reallocated by global.c if the hard register
60 is used as a spill register. Currently we don't allocate such pseudos
61 here if their preferred class is likely to be used by spills. */
65 #include "coretypes.h"
67 #include "hard-reg-set.h"
73 #include "insn-config.h"
74 #include "insn-attr.h"
79 #include "integrate.h"
83 #include "tree-pass.h"
88 /* Next quantity number available for allocation. */
92 /* Information we maintain about each quantity. */
95 /* The number of refs to quantity Q. */
99 /* The frequency of uses of quantity Q. */
103 /* Insn number (counting from head of basic block)
104 where quantity Q was born. -1 if birth has not been recorded. */
108 /* Insn number (counting from head of basic block)
109 where given quantity died. Due to the way tying is done,
110 and the fact that we consider in this pass only regs that die but once,
111 a quantity can die only once. Each quantity's life span
112 is a set of consecutive insns. -1 if death has not been recorded. */
116 /* Number of words needed to hold the data in given quantity.
117 This depends on its machine mode. It is used for these purposes:
118 1. It is used in computing the relative importance of qtys,
119 which determines the order in which we look for regs for them.
120 2. It is used in rules that prevent tying several registers of
121 different sizes in a way that is geometrically impossible
122 (see combine_regs). */
126 /* Number of times a reg tied to given qty lives across a CALL_INSN. */
130 /* Number of times a reg tied to given qty lives across a CALL_INSN
133 int n_throwing_calls_crossed;
135 /* The register number of one pseudo register whose reg_qty value is Q.
136 This register should be the head of the chain
137 maintained in reg_next_in_qty. */
141 /* Reg class contained in (smaller than) the preferred classes of all
142 the pseudo regs that are tied in given quantity.
143 This is the preferred class for allocating that quantity. */
145 enum reg_class min_class;
147 /* Register class within which we allocate given qty if we can't get
148 its preferred class. */
150 enum reg_class alternate_class;
152 /* This holds the mode of the registers that are tied to given qty,
153 or VOIDmode if registers with differing modes are tied together. */
155 enum machine_mode mode;
157 /* the hard reg number chosen for given quantity,
158 or -1 if none was found. */
163 static struct qty *qty;
165 /* These fields are kept separately to speedup their clearing. */
167 /* We maintain two hard register sets that indicate suggested hard registers
168 for each quantity. The first, phys_copy_sugg, contains hard registers
169 that are tied to the quantity by a simple copy. The second contains all
170 hard registers that are tied to the quantity via an arithmetic operation.
172 The former register set is given priority for allocation. This tends to
173 eliminate copy insns. */
175 /* Element Q is a set of hard registers that are suggested for quantity Q by
178 static HARD_REG_SET *qty_phys_copy_sugg;
180 /* Element Q is a set of hard registers that are suggested for quantity Q by
183 static HARD_REG_SET *qty_phys_sugg;
185 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
187 static short *qty_phys_num_copy_sugg;
189 /* Element Q is the number of suggested registers in qty_phys_sugg. */
191 static short *qty_phys_num_sugg;
193 /* If (REG N) has been assigned a quantity number, is a register number
194 of another register assigned the same quantity number, or -1 for the
195 end of the chain. qty->first_reg point to the head of this chain. */
197 static int *reg_next_in_qty;
199 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
201 of -1 if this register cannot be allocated by local-alloc,
202 or -2 if not known yet.
204 Note that if we see a use or death of pseudo register N with
205 reg_qty[N] == -2, register N must be local to the current block. If
206 it were used in more than one block, we would have reg_qty[N] == -1.
207 This relies on the fact that if reg_basic_block[N] is >= 0, register N
208 will not appear in any other block. We save a considerable number of
209 tests by exploiting this.
211 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
216 /* The offset (in words) of register N within its quantity.
217 This can be nonzero if register N is SImode, and has been tied
218 to a subreg of a DImode register. */
220 static char *reg_offset;
222 /* Vector of substitutions of register numbers,
223 used to map pseudo regs into hardware regs.
224 This is set up as a result of register allocation.
225 Element N is the hard reg assigned to pseudo reg N,
226 or is -1 if no hard reg was assigned.
227 If N is a hard reg number, element N is N. */
231 /* Set of hard registers live at the current point in the scan
232 of the instructions in a basic block. */
234 static HARD_REG_SET regs_live;
236 /* Each set of hard registers indicates registers live at a particular
237 point in the basic block. For N even, regs_live_at[N] says which
238 hard registers are needed *after* insn N/2 (i.e., they may not
239 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
241 If an object is to conflict with the inputs of insn J but not the
242 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
243 if it is to conflict with the outputs of insn J but not the inputs of
244 insn J + 1, it is said to die at index J*2 + 1. */
246 static HARD_REG_SET *regs_live_at;
248 /* Communicate local vars `insn_number' and `insn'
249 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
250 static int this_insn_number;
251 static rtx this_insn;
255 /* Set when an attempt should be made to replace a register
256 with the associated src_p entry. */
260 /* Set when a REG_EQUIV note is found or created. Use to
261 keep track of what memory accesses might be created later,
268 /* Loop depth is used to recognize equivalences which appear
269 to be present within the same loop (or in an inner loop). */
273 /* The list of each instruction which initializes this register. */
277 /* Nonzero if this had a preexisting REG_EQUIV note. */
279 int is_arg_equivalence;
282 /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence
283 structure for that register. */
285 static struct equivalence *reg_equiv;
287 /* Nonzero if we recorded an equivalence for a LABEL_REF. */
288 static int recorded_label_ref;
290 static void alloc_qty (int, enum machine_mode, int, int);
291 static void validate_equiv_mem_from_store (rtx, rtx, void *);
292 static int validate_equiv_mem (rtx, rtx, rtx);
293 static int equiv_init_varies_p (rtx);
294 static int equiv_init_movable_p (rtx, int);
295 static int contains_replace_regs (rtx);
296 static int memref_referenced_p (rtx, rtx);
297 static int memref_used_between_p (rtx, rtx, rtx);
298 static void update_equiv_regs (void);
299 static void no_equiv (rtx, rtx, void *);
300 static void block_alloc (int);
301 static int qty_sugg_compare (int, int);
302 static int qty_sugg_compare_1 (const void *, const void *);
303 static int qty_compare (int, int);
304 static int qty_compare_1 (const void *, const void *);
305 static int combine_regs (rtx, rtx, int, int, rtx, int);
306 static int reg_meets_class_p (int, enum reg_class);
307 static void update_qty_class (int, int);
308 static void reg_is_set (rtx, rtx, void *);
309 static void reg_is_born (rtx, int);
310 static void wipe_dead_reg (rtx, int);
311 static int find_free_reg (enum reg_class, enum machine_mode, int, int, int,
313 static void mark_life (int, enum machine_mode, int);
314 static void post_mark_life (int, enum machine_mode, int, int, int);
315 static int no_conflict_p (rtx, rtx, rtx);
316 static int requires_inout (const char *);
318 /* Allocate a new quantity (new within current basic block)
319 for register number REGNO which is born at index BIRTH
320 within the block. MODE and SIZE are info on reg REGNO. */
323 alloc_qty (int regno, enum machine_mode mode, int size, int birth)
325 int qtyno = next_qty++;
327 reg_qty[regno] = qtyno;
328 reg_offset[regno] = 0;
329 reg_next_in_qty[regno] = -1;
331 qty[qtyno].first_reg = regno;
332 qty[qtyno].size = size;
333 qty[qtyno].mode = mode;
334 qty[qtyno].birth = birth;
335 qty[qtyno].n_calls_crossed = REG_N_CALLS_CROSSED (regno);
336 qty[qtyno].n_throwing_calls_crossed = REG_N_THROWING_CALLS_CROSSED (regno);
337 qty[qtyno].min_class = reg_preferred_class (regno);
338 qty[qtyno].alternate_class = reg_alternate_class (regno);
339 qty[qtyno].n_refs = REG_N_REFS (regno);
340 qty[qtyno].freq = REG_FREQ (regno);
343 /* Main entry point of this file. */
352 /* We need to keep track of whether or not we recorded a LABEL_REF so
353 that we know if the jump optimizer needs to be rerun. */
354 recorded_label_ref = 0;
356 /* Leaf functions and non-leaf functions have different needs.
357 If defined, let the machine say what kind of ordering we
359 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
360 ORDER_REGS_FOR_LOCAL_ALLOC;
363 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
365 update_equiv_regs ();
367 /* This sets the maximum number of quantities we can have. Quantity
368 numbers start at zero and we can have one for each pseudo. */
369 max_qty = (max_regno - FIRST_PSEUDO_REGISTER);
371 /* Allocate vectors of temporary data.
372 See the declarations of these variables, above,
373 for what they mean. */
375 qty = XNEWVEC (struct qty, max_qty);
376 qty_phys_copy_sugg = XNEWVEC (HARD_REG_SET, max_qty);
377 qty_phys_num_copy_sugg = XNEWVEC (short, max_qty);
378 qty_phys_sugg = XNEWVEC (HARD_REG_SET, max_qty);
379 qty_phys_num_sugg = XNEWVEC (short, max_qty);
381 reg_qty = XNEWVEC (int, max_regno);
382 reg_offset = XNEWVEC (char, max_regno);
383 reg_next_in_qty = XNEWVEC (int, max_regno);
385 /* Determine which pseudo-registers can be allocated by local-alloc.
386 In general, these are the registers used only in a single block and
389 We need not be concerned with which block actually uses the register
390 since we will never see it outside that block. */
392 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
394 if (REG_BASIC_BLOCK (i) >= NUM_FIXED_BLOCKS && REG_N_DEATHS (i) == 1)
400 /* Force loop below to initialize entire quantity array. */
403 /* Allocate each block's local registers, block by block. */
407 /* NEXT_QTY indicates which elements of the `qty_...'
408 vectors might need to be initialized because they were used
409 for the previous block; it is set to the entire array before
410 block 0. Initialize those, with explicit loop if there are few,
411 else with bzero and bcopy. Do not initialize vectors that are
412 explicit set by `alloc_qty'. */
416 for (i = 0; i < next_qty; i++)
418 CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]);
419 qty_phys_num_copy_sugg[i] = 0;
420 CLEAR_HARD_REG_SET (qty_phys_sugg[i]);
421 qty_phys_num_sugg[i] = 0;
426 #define CLEAR(vector) \
427 memset ((vector), 0, (sizeof (*(vector))) * next_qty);
429 CLEAR (qty_phys_copy_sugg);
430 CLEAR (qty_phys_num_copy_sugg);
431 CLEAR (qty_phys_sugg);
432 CLEAR (qty_phys_num_sugg);
437 block_alloc (b->index);
441 free (qty_phys_copy_sugg);
442 free (qty_phys_num_copy_sugg);
443 free (qty_phys_sugg);
444 free (qty_phys_num_sugg);
448 free (reg_next_in_qty);
450 return recorded_label_ref;
453 /* Used for communication between the following two functions: contains
454 a MEM that we wish to ensure remains unchanged. */
455 static rtx equiv_mem;
457 /* Set nonzero if EQUIV_MEM is modified. */
458 static int equiv_mem_modified;
460 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
461 Called via note_stores. */
464 validate_equiv_mem_from_store (rtx dest, rtx set ATTRIBUTE_UNUSED,
465 void *data ATTRIBUTE_UNUSED)
468 && reg_overlap_mentioned_p (dest, equiv_mem))
470 && true_dependence (dest, VOIDmode, equiv_mem, rtx_varies_p)))
471 equiv_mem_modified = 1;
474 /* Verify that no store between START and the death of REG invalidates
475 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
476 by storing into an overlapping memory location, or with a non-const
479 Return 1 if MEMREF remains valid. */
482 validate_equiv_mem (rtx start, rtx reg, rtx memref)
488 equiv_mem_modified = 0;
490 /* If the memory reference has side effects or is volatile, it isn't a
491 valid equivalence. */
492 if (side_effects_p (memref))
495 for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn))
500 if (find_reg_note (insn, REG_DEAD, reg))
503 if (CALL_P (insn) && ! MEM_READONLY_P (memref)
504 && ! CONST_OR_PURE_CALL_P (insn))
507 note_stores (PATTERN (insn), validate_equiv_mem_from_store, NULL);
509 /* If a register mentioned in MEMREF is modified via an
510 auto-increment, we lose the equivalence. Do the same if one
511 dies; although we could extend the life, it doesn't seem worth
514 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
515 if ((REG_NOTE_KIND (note) == REG_INC
516 || REG_NOTE_KIND (note) == REG_DEAD)
517 && REG_P (XEXP (note, 0))
518 && reg_overlap_mentioned_p (XEXP (note, 0), memref))
525 /* Returns zero if X is known to be invariant. */
528 equiv_init_varies_p (rtx x)
530 RTX_CODE code = GET_CODE (x);
537 return !MEM_READONLY_P (x) || equiv_init_varies_p (XEXP (x, 0));
548 return reg_equiv[REGNO (x)].replace == 0 && rtx_varies_p (x, 0);
551 if (MEM_VOLATILE_P (x))
560 fmt = GET_RTX_FORMAT (code);
561 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
564 if (equiv_init_varies_p (XEXP (x, i)))
567 else if (fmt[i] == 'E')
570 for (j = 0; j < XVECLEN (x, i); j++)
571 if (equiv_init_varies_p (XVECEXP (x, i, j)))
578 /* Returns nonzero if X (used to initialize register REGNO) is movable.
579 X is only movable if the registers it uses have equivalent initializations
580 which appear to be within the same loop (or in an inner loop) and movable
581 or if they are not candidates for local_alloc and don't vary. */
584 equiv_init_movable_p (rtx x, int regno)
588 enum rtx_code code = GET_CODE (x);
593 return equiv_init_movable_p (SET_SRC (x), regno);
608 return (reg_equiv[REGNO (x)].loop_depth >= reg_equiv[regno].loop_depth
609 && reg_equiv[REGNO (x)].replace)
610 || (REG_BASIC_BLOCK (REGNO (x)) < NUM_FIXED_BLOCKS && ! rtx_varies_p (x, 0));
612 case UNSPEC_VOLATILE:
616 if (MEM_VOLATILE_P (x))
625 fmt = GET_RTX_FORMAT (code);
626 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
630 if (! equiv_init_movable_p (XEXP (x, i), regno))
634 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
635 if (! equiv_init_movable_p (XVECEXP (x, i, j), regno))
643 /* TRUE if X uses any registers for which reg_equiv[REGNO].replace is true. */
646 contains_replace_regs (rtx x)
650 enum rtx_code code = GET_CODE (x);
666 return reg_equiv[REGNO (x)].replace;
672 fmt = GET_RTX_FORMAT (code);
673 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
677 if (contains_replace_regs (XEXP (x, i)))
681 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
682 if (contains_replace_regs (XVECEXP (x, i, j)))
690 /* TRUE if X references a memory location that would be affected by a store
694 memref_referenced_p (rtx memref, rtx x)
698 enum rtx_code code = GET_CODE (x);
715 return (reg_equiv[REGNO (x)].replacement
716 && memref_referenced_p (memref,
717 reg_equiv[REGNO (x)].replacement));
720 if (true_dependence (memref, VOIDmode, x, rtx_varies_p))
725 /* If we are setting a MEM, it doesn't count (its address does), but any
726 other SET_DEST that has a MEM in it is referencing the MEM. */
727 if (MEM_P (SET_DEST (x)))
729 if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0)))
732 else if (memref_referenced_p (memref, SET_DEST (x)))
735 return memref_referenced_p (memref, SET_SRC (x));
741 fmt = GET_RTX_FORMAT (code);
742 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
746 if (memref_referenced_p (memref, XEXP (x, i)))
750 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
751 if (memref_referenced_p (memref, XVECEXP (x, i, j)))
759 /* TRUE if some insn in the range (START, END] references a memory location
760 that would be affected by a store to MEMREF. */
763 memref_used_between_p (rtx memref, rtx start, rtx end)
767 for (insn = NEXT_INSN (start); insn != NEXT_INSN (end);
768 insn = NEXT_INSN (insn))
773 if (memref_referenced_p (memref, PATTERN (insn)))
776 /* Nonconst functions may access memory. */
778 && (! CONST_OR_PURE_CALL_P (insn)
779 || pure_call_p (insn)))
786 /* Find registers that are equivalent to a single value throughout the
787 compilation (either because they can be referenced in memory or are set once
788 from a single constant). Lower their priority for a register.
790 If such a register is only referenced once, try substituting its value
791 into the using insn. If it succeeds, we can eliminate the register
794 Initialize the REG_EQUIV_INIT array of initializing insns. */
797 update_equiv_regs (void)
804 reg_equiv = XCNEWVEC (struct equivalence, max_regno);
805 reg_equiv_init = ggc_alloc_cleared (max_regno * sizeof (rtx));
806 reg_equiv_init_size = max_regno;
808 init_alias_analysis ();
810 /* Scan the insns and find which registers have equivalences. Do this
811 in a separate scan of the insns because (due to -fcse-follow-jumps)
812 a register can be set below its use. */
815 loop_depth = bb->loop_depth;
817 for (insn = BB_HEAD (bb);
818 insn != NEXT_INSN (BB_END (bb));
819 insn = NEXT_INSN (insn))
829 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
830 if (REG_NOTE_KIND (note) == REG_INC)
831 no_equiv (XEXP (note, 0), note, NULL);
833 set = single_set (insn);
835 /* If this insn contains more (or less) than a single SET,
836 only mark all destinations as having no known equivalence. */
839 note_stores (PATTERN (insn), no_equiv, NULL);
842 else if (GET_CODE (PATTERN (insn)) == PARALLEL)
846 for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--)
848 rtx part = XVECEXP (PATTERN (insn), 0, i);
850 note_stores (part, no_equiv, NULL);
854 dest = SET_DEST (set);
857 /* See if this is setting up the equivalence between an argument
858 register and its stack slot. */
859 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
862 gcc_assert (REG_P (dest));
863 regno = REGNO (dest);
865 /* Note that we don't want to clear reg_equiv_init even if there
866 are multiple sets of this register. */
867 reg_equiv[regno].is_arg_equivalence = 1;
869 /* Record for reload that this is an equivalencing insn. */
870 if (rtx_equal_p (src, XEXP (note, 0)))
871 reg_equiv_init[regno]
872 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[regno]);
874 /* Continue normally in case this is a candidate for
881 /* We only handle the case of a pseudo register being set
882 once, or always to the same value. */
883 /* ??? The mn10200 port breaks if we add equivalences for
884 values that need an ADDRESS_REGS register and set them equivalent
885 to a MEM of a pseudo. The actual problem is in the over-conservative
886 handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in
887 calculate_needs, but we traditionally work around this problem
888 here by rejecting equivalences when the destination is in a register
889 that's likely spilled. This is fragile, of course, since the
890 preferred class of a pseudo depends on all instructions that set
894 || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER
895 || reg_equiv[regno].init_insns == const0_rtx
896 || (CLASS_LIKELY_SPILLED_P (reg_preferred_class (regno))
897 && MEM_P (src) && ! reg_equiv[regno].is_arg_equivalence))
899 /* This might be setting a SUBREG of a pseudo, a pseudo that is
900 also set somewhere else to a constant. */
901 note_stores (set, no_equiv, NULL);
905 note = find_reg_note (insn, REG_EQUAL, NULL_RTX);
907 /* cse sometimes generates function invariants, but doesn't put a
908 REG_EQUAL note on the insn. Since this note would be redundant,
909 there's no point creating it earlier than here. */
910 if (! note && ! rtx_varies_p (src, 0))
911 note = set_unique_reg_note (insn, REG_EQUAL, copy_rtx (src));
913 /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST
914 since it represents a function call */
915 if (note && GET_CODE (XEXP (note, 0)) == EXPR_LIST)
918 if (DF_REG_DEF_COUNT (regno) != 1
920 || rtx_varies_p (XEXP (note, 0), 0)
921 || (reg_equiv[regno].replacement
922 && ! rtx_equal_p (XEXP (note, 0),
923 reg_equiv[regno].replacement))))
925 no_equiv (dest, set, NULL);
928 /* Record this insn as initializing this register. */
929 reg_equiv[regno].init_insns
930 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv[regno].init_insns);
932 /* If this register is known to be equal to a constant, record that
933 it is always equivalent to the constant. */
934 if (DF_REG_DEF_COUNT (regno) == 1
935 && note && ! rtx_varies_p (XEXP (note, 0), 0))
937 rtx note_value = XEXP (note, 0);
938 remove_note (insn, note);
939 set_unique_reg_note (insn, REG_EQUIV, note_value);
942 /* If this insn introduces a "constant" register, decrease the priority
943 of that register. Record this insn if the register is only used once
944 more and the equivalence value is the same as our source.
946 The latter condition is checked for two reasons: First, it is an
947 indication that it may be more efficient to actually emit the insn
948 as written (if no registers are available, reload will substitute
949 the equivalence). Secondly, it avoids problems with any registers
950 dying in this insn whose death notes would be missed.
952 If we don't have a REG_EQUIV note, see if this insn is loading
953 a register used only in one basic block from a MEM. If so, and the
954 MEM remains unchanged for the life of the register, add a REG_EQUIV
957 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
959 if (note == 0 && REG_BASIC_BLOCK (regno) >= NUM_FIXED_BLOCKS
960 && MEM_P (SET_SRC (set))
961 && validate_equiv_mem (insn, dest, SET_SRC (set)))
962 note = set_unique_reg_note (insn, REG_EQUIV, copy_rtx (SET_SRC (set)));
966 int regno = REGNO (dest);
967 rtx x = XEXP (note, 0);
969 /* If we haven't done so, record for reload that this is an
970 equivalencing insn. */
971 if (!reg_equiv[regno].is_arg_equivalence)
972 reg_equiv_init[regno]
973 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[regno]);
975 /* Record whether or not we created a REG_EQUIV note for a LABEL_REF.
976 We might end up substituting the LABEL_REF for uses of the
977 pseudo here or later. That kind of transformation may turn an
978 indirect jump into a direct jump, in which case we must rerun the
979 jump optimizer to ensure that the JUMP_LABEL fields are valid. */
980 if (GET_CODE (x) == LABEL_REF
981 || (GET_CODE (x) == CONST
982 && GET_CODE (XEXP (x, 0)) == PLUS
983 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF)))
984 recorded_label_ref = 1;
986 reg_equiv[regno].replacement = x;
987 reg_equiv[regno].src_p = &SET_SRC (set);
988 reg_equiv[regno].loop_depth = loop_depth;
990 /* Don't mess with things live during setjmp. */
991 if (REG_LIVE_LENGTH (regno) >= 0 && optimize)
993 /* Note that the statement below does not affect the priority
995 REG_LIVE_LENGTH (regno) *= 2;
997 /* If the register is referenced exactly twice, meaning it is
998 set once and used once, indicate that the reference may be
999 replaced by the equivalence we computed above. Do this
1000 even if the register is only used in one block so that
1001 dependencies can be handled where the last register is
1002 used in a different block (i.e. HIGH / LO_SUM sequences)
1003 and to reduce the number of registers alive across
1006 if (REG_N_REFS (regno) == 2
1007 && (rtx_equal_p (x, src)
1008 || ! equiv_init_varies_p (src))
1009 && NONJUMP_INSN_P (insn)
1010 && equiv_init_movable_p (PATTERN (insn), regno))
1011 reg_equiv[regno].replace = 1;
1020 /* A second pass, to gather additional equivalences with memory. This needs
1021 to be done after we know which registers we are going to replace. */
1023 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1028 if (! INSN_P (insn))
1031 set = single_set (insn);
1035 dest = SET_DEST (set);
1036 src = SET_SRC (set);
1038 /* If this sets a MEM to the contents of a REG that is only used
1039 in a single basic block, see if the register is always equivalent
1040 to that memory location and if moving the store from INSN to the
1041 insn that set REG is safe. If so, put a REG_EQUIV note on the
1044 Don't add a REG_EQUIV note if the insn already has one. The existing
1045 REG_EQUIV is likely more useful than the one we are adding.
1047 If one of the regs in the address has reg_equiv[REGNO].replace set,
1048 then we can't add this REG_EQUIV note. The reg_equiv[REGNO].replace
1049 optimization may move the set of this register immediately before
1050 insn, which puts it after reg_equiv[REGNO].init_insns, and hence
1051 the mention in the REG_EQUIV note would be to an uninitialized
1054 if (MEM_P (dest) && REG_P (src)
1055 && (regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER
1056 && REG_BASIC_BLOCK (regno) >= NUM_FIXED_BLOCKS
1057 && DF_REG_DEF_COUNT (regno) == 1
1058 && reg_equiv[regno].init_insns != 0
1059 && reg_equiv[regno].init_insns != const0_rtx
1060 && ! find_reg_note (XEXP (reg_equiv[regno].init_insns, 0),
1061 REG_EQUIV, NULL_RTX)
1062 && ! contains_replace_regs (XEXP (dest, 0)))
1064 rtx init_insn = XEXP (reg_equiv[regno].init_insns, 0);
1065 if (validate_equiv_mem (init_insn, src, dest)
1066 && ! memref_used_between_p (dest, init_insn, insn)
1067 /* Attaching a REG_EQUIV note will fail if INIT_INSN has
1069 && set_unique_reg_note (init_insn, REG_EQUIV, copy_rtx (dest)))
1071 /* This insn makes the equivalence, not the one initializing
1073 reg_equiv_init[regno]
1074 = gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX);
1075 df_notes_rescan (init_insn);
1080 cleared_regs = BITMAP_ALLOC (NULL);
1081 /* Now scan all regs killed in an insn to see if any of them are
1082 registers only used that once. If so, see if we can replace the
1083 reference with the equivalent form. If we can, delete the
1084 initializing reference and this register will go away. If we
1085 can't replace the reference, and the initializing reference is
1086 within the same loop (or in an inner loop), then move the register
1087 initialization just before the use, so that they are in the same
1089 FOR_EACH_BB_REVERSE (bb)
1091 loop_depth = bb->loop_depth;
1092 for (insn = BB_END (bb);
1093 insn != PREV_INSN (BB_HEAD (bb));
1094 insn = PREV_INSN (insn))
1098 if (! INSN_P (insn))
1101 /* Don't substitute into a non-local goto, this confuses CFG. */
1103 && find_reg_note (insn, REG_NON_LOCAL_GOTO, NULL_RTX))
1106 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1108 if (REG_NOTE_KIND (link) == REG_DEAD
1109 /* Make sure this insn still refers to the register. */
1110 && reg_mentioned_p (XEXP (link, 0), PATTERN (insn)))
1112 int regno = REGNO (XEXP (link, 0));
1115 if (! reg_equiv[regno].replace
1116 || reg_equiv[regno].loop_depth < loop_depth)
1119 /* reg_equiv[REGNO].replace gets set only when
1120 REG_N_REFS[REGNO] is 2, i.e. the register is set
1121 once and used once. (If it were only set, but not used,
1122 flow would have deleted the setting insns.) Hence
1123 there can only be one insn in reg_equiv[REGNO].init_insns. */
1124 gcc_assert (reg_equiv[regno].init_insns
1125 && !XEXP (reg_equiv[regno].init_insns, 1));
1126 equiv_insn = XEXP (reg_equiv[regno].init_insns, 0);
1128 /* We may not move instructions that can throw, since
1129 that changes basic block boundaries and we are not
1130 prepared to adjust the CFG to match. */
1131 if (can_throw_internal (equiv_insn))
1134 if (asm_noperands (PATTERN (equiv_insn)) < 0
1135 && validate_replace_rtx (regno_reg_rtx[regno],
1136 *(reg_equiv[regno].src_p), insn))
1142 /* Find the last note. */
1143 for (last_link = link; XEXP (last_link, 1);
1144 last_link = XEXP (last_link, 1))
1147 /* Append the REG_DEAD notes from equiv_insn. */
1148 equiv_link = REG_NOTES (equiv_insn);
1152 equiv_link = XEXP (equiv_link, 1);
1153 if (REG_NOTE_KIND (note) == REG_DEAD)
1155 remove_note (equiv_insn, note);
1156 XEXP (last_link, 1) = note;
1157 XEXP (note, 1) = NULL_RTX;
1162 remove_death (regno, insn);
1163 SET_REG_N_REFS (regno, 0);
1164 REG_FREQ (regno) = 0;
1165 delete_insn (equiv_insn);
1167 reg_equiv[regno].init_insns
1168 = XEXP (reg_equiv[regno].init_insns, 1);
1170 reg_equiv_init[regno] = NULL_RTX;
1171 bitmap_set_bit (cleared_regs, regno);
1173 /* Move the initialization of the register to just before
1174 INSN. Update the flow information. */
1175 else if (PREV_INSN (insn) != equiv_insn)
1179 new_insn = emit_insn_before (PATTERN (equiv_insn), insn);
1180 REG_NOTES (new_insn) = REG_NOTES (equiv_insn);
1181 REG_NOTES (equiv_insn) = 0;
1183 /* Make sure this insn is recognized before
1184 reload begins, otherwise
1185 eliminate_regs_in_insn will die. */
1186 INSN_CODE (new_insn) = INSN_CODE (equiv_insn);
1188 delete_insn (equiv_insn);
1190 XEXP (reg_equiv[regno].init_insns, 0) = new_insn;
1192 REG_BASIC_BLOCK (regno) = bb->index;
1193 REG_N_CALLS_CROSSED (regno) = 0;
1194 REG_N_THROWING_CALLS_CROSSED (regno) = 0;
1195 REG_LIVE_LENGTH (regno) = 2;
1197 if (insn == BB_HEAD (bb))
1198 BB_HEAD (bb) = PREV_INSN (insn);
1200 reg_equiv_init[regno]
1201 = gen_rtx_INSN_LIST (VOIDmode, new_insn, NULL_RTX);
1202 bitmap_set_bit (cleared_regs, regno);
1209 if (!bitmap_empty_p (cleared_regs))
1212 bitmap_and_compl_into (DF_RA_LIVE_IN (bb), cleared_regs);
1213 if (DF_RA_LIVE_TOP (bb))
1214 bitmap_and_compl_into (DF_RA_LIVE_TOP (bb), cleared_regs);
1215 bitmap_and_compl_into (DF_RA_LIVE_OUT (bb), cleared_regs);
1216 bitmap_and_compl_into (DF_LR_IN (bb), cleared_regs);
1218 bitmap_and_compl_into (DF_LR_TOP (bb), cleared_regs);
1219 bitmap_and_compl_into (DF_LR_OUT (bb), cleared_regs);
1222 BITMAP_FREE (cleared_regs);
1227 end_alias_analysis ();
1231 /* Mark REG as having no known equivalence.
1232 Some instructions might have been processed before and furnished
1233 with REG_EQUIV notes for this register; these notes will have to be
1235 STORE is the piece of RTL that does the non-constant / conflicting
1236 assignment - a SET, CLOBBER or REG_INC note. It is currently not used,
1237 but needs to be there because this function is called from note_stores. */
1239 no_equiv (rtx reg, rtx store ATTRIBUTE_UNUSED, void *data ATTRIBUTE_UNUSED)
1246 regno = REGNO (reg);
1247 list = reg_equiv[regno].init_insns;
1248 if (list == const0_rtx)
1250 reg_equiv[regno].init_insns = const0_rtx;
1251 reg_equiv[regno].replacement = NULL_RTX;
1252 /* This doesn't matter for equivalences made for argument registers, we
1253 should keep their initialization insns. */
1254 if (reg_equiv[regno].is_arg_equivalence)
1256 reg_equiv_init[regno] = NULL_RTX;
1257 for (; list; list = XEXP (list, 1))
1259 rtx insn = XEXP (list, 0);
1260 remove_note (insn, find_reg_note (insn, REG_EQUIV, NULL_RTX));
1264 /* Allocate hard regs to the pseudo regs used only within block number B.
1265 Only the pseudos that die but once can be handled. */
1273 int insn_number = 0;
1275 int max_uid = get_max_uid ();
1277 int no_conflict_combined_regno = -1;
1279 /* Count the instructions in the basic block. */
1281 insn = BB_END (BASIC_BLOCK (b));
1287 gcc_assert (insn_count <= max_uid);
1289 if (insn == BB_HEAD (BASIC_BLOCK (b)))
1291 insn = PREV_INSN (insn);
1294 /* +2 to leave room for a post_mark_life at the last insn and for
1295 the birth of a CLOBBER in the first insn. */
1296 regs_live_at = XCNEWVEC (HARD_REG_SET, 2 * insn_count + 2);
1298 /* Initialize table of hardware registers currently live. */
1300 REG_SET_TO_HARD_REG_SET (regs_live, DF_LR_TOP (BASIC_BLOCK (b)));
1302 /* This loop scans the instructions of the basic block
1303 and assigns quantities to registers.
1304 It computes which registers to tie. */
1306 insn = BB_HEAD (BASIC_BLOCK (b));
1316 rtx r0, r1 = NULL_RTX;
1317 int combined_regno = -1;
1320 this_insn_number = insn_number;
1323 extract_insn (insn);
1324 which_alternative = -1;
1326 /* Is this insn suitable for tying two registers?
1327 If so, try doing that.
1328 Suitable insns are those with at least two operands and where
1329 operand 0 is an output that is a register that is not
1332 We can tie operand 0 with some operand that dies in this insn.
1333 First look for operands that are required to be in the same
1334 register as operand 0. If we find such, only try tying that
1335 operand or one that can be put into that operand if the
1336 operation is commutative. If we don't find an operand
1337 that is required to be in the same register as operand 0,
1338 we can tie with any operand.
1340 Subregs in place of regs are also ok.
1342 If tying is done, WIN is set nonzero. */
1345 && recog_data.n_operands > 1
1346 && recog_data.constraints[0][0] == '='
1347 && recog_data.constraints[0][1] != '&')
1349 /* If non-negative, is an operand that must match operand 0. */
1350 int must_match_0 = -1;
1351 /* Counts number of alternatives that require a match with
1353 int n_matching_alts = 0;
1355 for (i = 1; i < recog_data.n_operands; i++)
1357 const char *p = recog_data.constraints[i];
1358 int this_match = requires_inout (p);
1360 n_matching_alts += this_match;
1361 if (this_match == recog_data.n_alternatives)
1365 r0 = recog_data.operand[0];
1366 for (i = 1; i < recog_data.n_operands; i++)
1368 /* Skip this operand if we found an operand that
1369 must match operand 0 and this operand isn't it
1370 and can't be made to be it by commutativity. */
1372 if (must_match_0 >= 0 && i != must_match_0
1373 && ! (i == must_match_0 + 1
1374 && recog_data.constraints[i-1][0] == '%')
1375 && ! (i == must_match_0 - 1
1376 && recog_data.constraints[i][0] == '%'))
1379 /* Likewise if each alternative has some operand that
1380 must match operand zero. In that case, skip any
1381 operand that doesn't list operand 0 since we know that
1382 the operand always conflicts with operand 0. We
1383 ignore commutativity in this case to keep things simple. */
1384 if (n_matching_alts == recog_data.n_alternatives
1385 && 0 == requires_inout (recog_data.constraints[i]))
1388 r1 = recog_data.operand[i];
1390 /* If the operand is an address, find a register in it.
1391 There may be more than one register, but we only try one
1393 if (recog_data.constraints[i][0] == 'p'
1394 || EXTRA_ADDRESS_CONSTRAINT (recog_data.constraints[i][0],
1395 recog_data.constraints[i]))
1396 while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT)
1399 /* Avoid making a call-saved register unnecessarily
1401 hard_reg = get_hard_reg_initial_reg (cfun, r1);
1402 if (hard_reg != NULL_RTX)
1404 if (REG_P (hard_reg)
1405 && REGNO (hard_reg) < FIRST_PSEUDO_REGISTER
1406 && !call_used_regs[REGNO (hard_reg)])
1410 if (REG_P (r0) || GET_CODE (r0) == SUBREG)
1412 /* We have two priorities for hard register preferences.
1413 If we have a move insn or an insn whose first input
1414 can only be in the same register as the output, give
1415 priority to an equivalence found from that insn. */
1417 = (r1 == recog_data.operand[i] && must_match_0 >= 0);
1419 if (REG_P (r1) || GET_CODE (r1) == SUBREG)
1420 win = combine_regs (r1, r0, may_save_copy,
1421 insn_number, insn, 0);
1428 /* Recognize an insn sequence with an ultimate result
1429 which can safely overlap one of the inputs.
1430 The sequence begins with a CLOBBER of its result,
1431 and ends with an insn that copies the result to itself
1432 and has a REG_EQUAL note for an equivalent formula.
1433 That note indicates what the inputs are.
1434 The result and the input can overlap if each insn in
1435 the sequence either doesn't mention the input
1436 or has a REG_NO_CONFLICT note to inhibit the conflict.
1438 We do the combining test at the CLOBBER so that the
1439 destination register won't have had a quantity number
1440 assigned, since that would prevent combining. */
1443 && GET_CODE (PATTERN (insn)) == CLOBBER
1444 && (r0 = XEXP (PATTERN (insn), 0),
1446 && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0
1447 && XEXP (link, 0) != 0
1448 && NONJUMP_INSN_P (XEXP (link, 0))
1449 && (set = single_set (XEXP (link, 0))) != 0
1450 && SET_DEST (set) == r0 && SET_SRC (set) == r0
1451 && (note = find_reg_note (XEXP (link, 0), REG_EQUAL,
1454 if (r1 = XEXP (note, 0), REG_P (r1)
1455 /* Check that we have such a sequence. */
1456 && no_conflict_p (insn, r0, r1))
1457 win = combine_regs (r1, r0, 1, insn_number, insn, 1);
1458 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e'
1459 && (r1 = XEXP (XEXP (note, 0), 0),
1460 REG_P (r1) || GET_CODE (r1) == SUBREG)
1461 && no_conflict_p (insn, r0, r1))
1462 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1464 /* Here we care if the operation to be computed is
1466 else if (COMMUTATIVE_P (XEXP (note, 0))
1467 && (r1 = XEXP (XEXP (note, 0), 1),
1468 (REG_P (r1) || GET_CODE (r1) == SUBREG))
1469 && no_conflict_p (insn, r0, r1))
1470 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1472 /* If we did combine something, show the register number
1473 in question so that we know to ignore its death. */
1475 no_conflict_combined_regno = REGNO (r1);
1478 /* If registers were just tied, set COMBINED_REGNO
1479 to the number of the register used in this insn
1480 that was tied to the register set in this insn.
1481 This register's qty should not be "killed". */
1485 while (GET_CODE (r1) == SUBREG)
1486 r1 = SUBREG_REG (r1);
1487 combined_regno = REGNO (r1);
1490 /* Mark the death of everything that dies in this instruction,
1491 except for anything that was just combined. */
1493 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1494 if (REG_NOTE_KIND (link) == REG_DEAD
1495 && REG_P (XEXP (link, 0))
1496 && combined_regno != (int) REGNO (XEXP (link, 0))
1497 && (no_conflict_combined_regno != (int) REGNO (XEXP (link, 0))
1498 || ! find_reg_note (insn, REG_NO_CONFLICT,
1500 wipe_dead_reg (XEXP (link, 0), 0);
1502 /* Allocate qty numbers for all registers local to this block
1503 that are born (set) in this instruction.
1504 A pseudo that already has a qty is not changed. */
1506 note_stores (PATTERN (insn), reg_is_set, NULL);
1508 /* If anything is set in this insn and then unused, mark it as dying
1509 after this insn, so it will conflict with our outputs. This
1510 can't match with something that combined, and it doesn't matter
1511 if it did. Do this after the calls to reg_is_set since these
1512 die after, not during, the current insn. */
1514 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1515 if (REG_NOTE_KIND (link) == REG_UNUSED
1516 && REG_P (XEXP (link, 0)))
1517 wipe_dead_reg (XEXP (link, 0), 1);
1519 /* If this is an insn that has a REG_RETVAL note pointing at a
1520 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1521 block, so clear any register number that combined within it. */
1522 if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0
1523 && NONJUMP_INSN_P (XEXP (note, 0))
1524 && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER)
1525 no_conflict_combined_regno = -1;
1528 /* Set the registers live after INSN_NUMBER. Note that we never
1529 record the registers live before the block's first insn, since no
1530 pseudos we care about are live before that insn. */
1532 IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live);
1533 IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live);
1535 if (insn == BB_END (BASIC_BLOCK (b)))
1538 insn = NEXT_INSN (insn);
1541 /* Now every register that is local to this basic block
1542 should have been given a quantity, or else -1 meaning ignore it.
1543 Every quantity should have a known birth and death.
1545 Order the qtys so we assign them registers in order of the
1546 number of suggested registers they need so we allocate those with
1547 the most restrictive needs first. */
1549 qty_order = XNEWVEC (int, next_qty);
1550 for (i = 0; i < next_qty; i++)
1553 #define EXCHANGE(I1, I2) \
1554 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1559 /* Make qty_order[2] be the one to allocate last. */
1560 if (qty_sugg_compare (0, 1) > 0)
1562 if (qty_sugg_compare (1, 2) > 0)
1565 /* ... Fall through ... */
1567 /* Put the best one to allocate in qty_order[0]. */
1568 if (qty_sugg_compare (0, 1) > 0)
1571 /* ... Fall through ... */
1575 /* Nothing to do here. */
1579 qsort (qty_order, next_qty, sizeof (int), qty_sugg_compare_1);
1582 /* Try to put each quantity in a suggested physical register, if it has one.
1583 This may cause registers to be allocated that otherwise wouldn't be, but
1584 this seems acceptable in local allocation (unlike global allocation). */
1585 for (i = 0; i < next_qty; i++)
1588 if (qty_phys_num_sugg[q] != 0 || qty_phys_num_copy_sugg[q] != 0)
1589 qty[q].phys_reg = find_free_reg (qty[q].min_class, qty[q].mode, q,
1590 0, 1, qty[q].birth, qty[q].death);
1592 qty[q].phys_reg = -1;
1595 /* Order the qtys so we assign them registers in order of
1596 decreasing length of life. Normally call qsort, but if we
1597 have only a very small number of quantities, sort them ourselves. */
1599 for (i = 0; i < next_qty; i++)
1602 #define EXCHANGE(I1, I2) \
1603 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1608 /* Make qty_order[2] be the one to allocate last. */
1609 if (qty_compare (0, 1) > 0)
1611 if (qty_compare (1, 2) > 0)
1614 /* ... Fall through ... */
1616 /* Put the best one to allocate in qty_order[0]. */
1617 if (qty_compare (0, 1) > 0)
1620 /* ... Fall through ... */
1624 /* Nothing to do here. */
1628 qsort (qty_order, next_qty, sizeof (int), qty_compare_1);
1631 /* Now for each qty that is not a hardware register,
1632 look for a hardware register to put it in.
1633 First try the register class that is cheapest for this qty,
1634 if there is more than one class. */
1636 for (i = 0; i < next_qty; i++)
1639 if (qty[q].phys_reg < 0)
1641 #ifdef INSN_SCHEDULING
1642 /* These values represent the adjusted lifetime of a qty so
1643 that it conflicts with qtys which appear near the start/end
1644 of this qty's lifetime.
1646 The purpose behind extending the lifetime of this qty is to
1647 discourage the register allocator from creating false
1650 The adjustment value is chosen to indicate that this qty
1651 conflicts with all the qtys in the instructions immediately
1652 before and after the lifetime of this qty.
1654 Experiments have shown that higher values tend to hurt
1655 overall code performance.
1657 If allocation using the extended lifetime fails we will try
1658 again with the qty's unadjusted lifetime. */
1659 int fake_birth = MAX (0, qty[q].birth - 2 + qty[q].birth % 2);
1660 int fake_death = MIN (insn_number * 2 + 1,
1661 qty[q].death + 2 - qty[q].death % 2);
1664 if (N_REG_CLASSES > 1)
1666 #ifdef INSN_SCHEDULING
1667 /* We try to avoid using hard registers allocated to qtys which
1668 are born immediately after this qty or die immediately before
1671 This optimization is only appropriate when we will run
1672 a scheduling pass after reload and we are not optimizing
1674 if (flag_schedule_insns_after_reload && dbg_cnt (local_alloc_for_sched)
1676 && !SMALL_REGISTER_CLASSES)
1678 qty[q].phys_reg = find_free_reg (qty[q].min_class,
1679 qty[q].mode, q, 0, 0,
1680 fake_birth, fake_death);
1681 if (qty[q].phys_reg >= 0)
1685 qty[q].phys_reg = find_free_reg (qty[q].min_class,
1686 qty[q].mode, q, 0, 0,
1687 qty[q].birth, qty[q].death);
1688 if (qty[q].phys_reg >= 0)
1692 #ifdef INSN_SCHEDULING
1693 /* Similarly, avoid false dependencies. */
1694 if (flag_schedule_insns_after_reload && dbg_cnt (local_alloc_for_sched)
1696 && !SMALL_REGISTER_CLASSES
1697 && qty[q].alternate_class != NO_REGS)
1698 qty[q].phys_reg = find_free_reg (qty[q].alternate_class,
1699 qty[q].mode, q, 0, 0,
1700 fake_birth, fake_death);
1702 if (qty[q].alternate_class != NO_REGS)
1703 qty[q].phys_reg = find_free_reg (qty[q].alternate_class,
1704 qty[q].mode, q, 0, 0,
1705 qty[q].birth, qty[q].death);
1709 /* Now propagate the register assignments
1710 to the pseudo regs belonging to the qtys. */
1712 for (q = 0; q < next_qty; q++)
1713 if (qty[q].phys_reg >= 0)
1715 for (i = qty[q].first_reg; i >= 0; i = reg_next_in_qty[i])
1716 reg_renumber[i] = qty[q].phys_reg + reg_offset[i];
1720 free (regs_live_at);
1724 /* Compare two quantities' priority for getting real registers.
1725 We give shorter-lived quantities higher priority.
1726 Quantities with more references are also preferred, as are quantities that
1727 require multiple registers. This is the identical prioritization as
1728 done by global-alloc.
1730 We used to give preference to registers with *longer* lives, but using
1731 the same algorithm in both local- and global-alloc can speed up execution
1732 of some programs by as much as a factor of three! */
1734 /* Note that the quotient will never be bigger than
1735 the value of floor_log2 times the maximum number of
1736 times a register can occur in one insn (surely less than 100)
1737 weighted by frequency (max REG_FREQ_MAX).
1738 Multiplying this by 10000/REG_FREQ_MAX can't overflow.
1739 QTY_CMP_PRI is also used by qty_sugg_compare. */
1741 #define QTY_CMP_PRI(q) \
1742 ((int) (((double) (floor_log2 (qty[q].n_refs) * qty[q].freq * qty[q].size) \
1743 / (qty[q].death - qty[q].birth)) * (10000 / REG_FREQ_MAX)))
1746 qty_compare (int q1, int q2)
1748 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1752 qty_compare_1 (const void *q1p, const void *q2p)
1754 int q1 = *(const int *) q1p, q2 = *(const int *) q2p;
1755 int tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1760 /* If qtys are equally good, sort by qty number,
1761 so that the results of qsort leave nothing to chance. */
1765 /* Compare two quantities' priority for getting real registers. This version
1766 is called for quantities that have suggested hard registers. First priority
1767 goes to quantities that have copy preferences, then to those that have
1768 normal preferences. Within those groups, quantities with the lower
1769 number of preferences have the highest priority. Of those, we use the same
1770 algorithm as above. */
1772 #define QTY_CMP_SUGG(q) \
1773 (qty_phys_num_copy_sugg[q] \
1774 ? qty_phys_num_copy_sugg[q] \
1775 : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER)
1778 qty_sugg_compare (int q1, int q2)
1780 int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1785 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1789 qty_sugg_compare_1 (const void *q1p, const void *q2p)
1791 int q1 = *(const int *) q1p, q2 = *(const int *) q2p;
1792 int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1797 tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1801 /* If qtys are equally good, sort by qty number,
1802 so that the results of qsort leave nothing to chance. */
1809 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1810 Returns 1 if have done so, or 0 if cannot.
1812 Combining registers means marking them as having the same quantity
1813 and adjusting the offsets within the quantity if either of
1816 We don't actually combine a hard reg with a pseudo; instead
1817 we just record the hard reg as the suggestion for the pseudo's quantity.
1818 If we really combined them, we could lose if the pseudo lives
1819 across an insn that clobbers the hard reg (eg, movmem).
1821 ALREADY_DEAD is nonzero if USEDREG is known to be dead even though
1822 there is no REG_DEAD note on INSN. This occurs during the processing
1823 of REG_NO_CONFLICT blocks.
1825 MAY_SAVE_COPY is nonzero if this insn is simply copying USEDREG to
1826 SETREG or if the input and output must share a register.
1827 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1829 There are elaborate checks for the validity of combining. */
1832 combine_regs (rtx usedreg, rtx setreg, int may_save_copy, int insn_number,
1833 rtx insn, int already_dead)
1840 /* Determine the numbers and sizes of registers being used. If a subreg
1841 is present that does not change the entire register, don't consider
1842 this a copy insn. */
1844 while (GET_CODE (usedreg) == SUBREG)
1846 rtx subreg = SUBREG_REG (usedreg);
1850 if (GET_MODE_SIZE (GET_MODE (subreg)) > UNITS_PER_WORD)
1853 if (REGNO (subreg) < FIRST_PSEUDO_REGISTER)
1854 offset += subreg_regno_offset (REGNO (subreg),
1856 SUBREG_BYTE (usedreg),
1857 GET_MODE (usedreg));
1859 offset += (SUBREG_BYTE (usedreg)
1860 / REGMODE_NATURAL_SIZE (GET_MODE (usedreg)));
1866 if (!REG_P (usedreg))
1869 ureg = REGNO (usedreg);
1870 if (ureg < FIRST_PSEUDO_REGISTER)
1871 usize = hard_regno_nregs[ureg][GET_MODE (usedreg)];
1873 usize = ((GET_MODE_SIZE (GET_MODE (usedreg))
1874 + (REGMODE_NATURAL_SIZE (GET_MODE (usedreg)) - 1))
1875 / REGMODE_NATURAL_SIZE (GET_MODE (usedreg)));
1877 while (GET_CODE (setreg) == SUBREG)
1879 rtx subreg = SUBREG_REG (setreg);
1883 if (GET_MODE_SIZE (GET_MODE (subreg)) > UNITS_PER_WORD)
1886 if (REGNO (subreg) < FIRST_PSEUDO_REGISTER)
1887 offset -= subreg_regno_offset (REGNO (subreg),
1889 SUBREG_BYTE (setreg),
1892 offset -= (SUBREG_BYTE (setreg)
1893 / REGMODE_NATURAL_SIZE (GET_MODE (setreg)));
1899 if (!REG_P (setreg))
1902 sreg = REGNO (setreg);
1903 if (sreg < FIRST_PSEUDO_REGISTER)
1904 ssize = hard_regno_nregs[sreg][GET_MODE (setreg)];
1906 ssize = ((GET_MODE_SIZE (GET_MODE (setreg))
1907 + (REGMODE_NATURAL_SIZE (GET_MODE (setreg)) - 1))
1908 / REGMODE_NATURAL_SIZE (GET_MODE (setreg)));
1910 /* If UREG is a pseudo-register that hasn't already been assigned a
1911 quantity number, it means that it is not local to this block or dies
1912 more than once. In either event, we can't do anything with it. */
1913 if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0)
1914 /* Do not combine registers unless one fits within the other. */
1915 || (offset > 0 && usize + offset > ssize)
1916 || (offset < 0 && usize + offset < ssize)
1917 /* Do not combine with a smaller already-assigned object
1918 if that smaller object is already combined with something bigger. */
1919 || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER
1920 && usize < qty[reg_qty[ureg]].size)
1921 /* Can't combine if SREG is not a register we can allocate. */
1922 || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1)
1923 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1924 These have already been taken care of. This probably wouldn't
1925 combine anyway, but don't take any chances. */
1926 || (ureg >= FIRST_PSEUDO_REGISTER
1927 && find_reg_note (insn, REG_NO_CONFLICT, usedreg))
1928 /* Don't tie something to itself. In most cases it would make no
1929 difference, but it would screw up if the reg being tied to itself
1930 also dies in this insn. */
1932 /* Don't try to connect two different hardware registers. */
1933 || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER)
1934 /* Don't connect two different machine modes if they have different
1935 implications as to which registers may be used. */
1936 || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg)))
1939 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1940 qty_phys_sugg for the pseudo instead of tying them.
1942 Return "failure" so that the lifespan of UREG is terminated here;
1943 that way the two lifespans will be disjoint and nothing will prevent
1944 the pseudo reg from being given this hard reg. */
1946 if (ureg < FIRST_PSEUDO_REGISTER)
1948 /* Allocate a quantity number so we have a place to put our
1950 if (reg_qty[sreg] == -2)
1951 reg_is_born (setreg, 2 * insn_number);
1953 if (reg_qty[sreg] >= 0)
1956 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg))
1958 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg);
1959 qty_phys_num_copy_sugg[reg_qty[sreg]]++;
1961 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg))
1963 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg);
1964 qty_phys_num_sugg[reg_qty[sreg]]++;
1970 /* Similarly for SREG a hard register and UREG a pseudo register. */
1972 if (sreg < FIRST_PSEUDO_REGISTER)
1975 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg))
1977 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg);
1978 qty_phys_num_copy_sugg[reg_qty[ureg]]++;
1980 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg))
1982 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg);
1983 qty_phys_num_sugg[reg_qty[ureg]]++;
1988 /* At this point we know that SREG and UREG are both pseudos.
1989 Do nothing if SREG already has a quantity or is a register that we
1991 if (reg_qty[sreg] >= -1
1992 /* If we are not going to let any regs live across calls,
1993 don't tie a call-crossing reg to a non-call-crossing reg. */
1994 || (current_function_has_nonlocal_label
1995 && ((REG_N_CALLS_CROSSED (ureg) > 0)
1996 != (REG_N_CALLS_CROSSED (sreg) > 0))))
1999 /* We don't already know about SREG, so tie it to UREG
2000 if this is the last use of UREG, provided the classes they want
2003 if ((already_dead || find_regno_note (insn, REG_DEAD, ureg))
2004 && reg_meets_class_p (sreg, qty[reg_qty[ureg]].min_class))
2006 /* Add SREG to UREG's quantity. */
2007 sqty = reg_qty[ureg];
2008 reg_qty[sreg] = sqty;
2009 reg_offset[sreg] = reg_offset[ureg] + offset;
2010 reg_next_in_qty[sreg] = qty[sqty].first_reg;
2011 qty[sqty].first_reg = sreg;
2013 /* If SREG's reg class is smaller, set qty[SQTY].min_class. */
2014 update_qty_class (sqty, sreg);
2016 /* Update info about quantity SQTY. */
2017 qty[sqty].n_calls_crossed += REG_N_CALLS_CROSSED (sreg);
2018 qty[sqty].n_throwing_calls_crossed
2019 += REG_N_THROWING_CALLS_CROSSED (sreg);
2020 qty[sqty].n_refs += REG_N_REFS (sreg);
2021 qty[sqty].freq += REG_FREQ (sreg);
2026 for (i = qty[sqty].first_reg; i >= 0; i = reg_next_in_qty[i])
2027 reg_offset[i] -= offset;
2029 qty[sqty].size = ssize;
2030 qty[sqty].mode = GET_MODE (setreg);
2039 /* Return 1 if the preferred class of REG allows it to be tied
2040 to a quantity or register whose class is CLASS.
2041 True if REG's reg class either contains or is contained in CLASS. */
2044 reg_meets_class_p (int reg, enum reg_class class)
2046 enum reg_class rclass = reg_preferred_class (reg);
2047 return (reg_class_subset_p (rclass, class)
2048 || reg_class_subset_p (class, rclass));
2051 /* Update the class of QTYNO assuming that REG is being tied to it. */
2054 update_qty_class (int qtyno, int reg)
2056 enum reg_class rclass = reg_preferred_class (reg);
2057 if (reg_class_subset_p (rclass, qty[qtyno].min_class))
2058 qty[qtyno].min_class = rclass;
2060 rclass = reg_alternate_class (reg);
2061 if (reg_class_subset_p (rclass, qty[qtyno].alternate_class))
2062 qty[qtyno].alternate_class = rclass;
2065 /* Handle something which alters the value of an rtx REG.
2067 REG is whatever is set or clobbered. SETTER is the rtx that
2068 is modifying the register.
2070 If it is not really a register, we do nothing.
2071 The file-global variables `this_insn' and `this_insn_number'
2072 carry info from `block_alloc'. */
2075 reg_is_set (rtx reg, rtx setter, void *data ATTRIBUTE_UNUSED)
2077 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
2078 a hard register. These may actually not exist any more. */
2080 if (GET_CODE (reg) != SUBREG
2084 /* Mark this register as being born. If it is used in a CLOBBER, mark
2085 it as being born halfway between the previous insn and this insn so that
2086 it conflicts with our inputs but not the outputs of the previous insn. */
2088 reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER));
2091 /* Handle beginning of the life of register REG.
2092 BIRTH is the index at which this is happening. */
2095 reg_is_born (rtx reg, int birth)
2099 if (GET_CODE (reg) == SUBREG)
2101 regno = REGNO (SUBREG_REG (reg));
2102 if (regno < FIRST_PSEUDO_REGISTER)
2103 regno = subreg_regno (reg);
2106 regno = REGNO (reg);
2108 if (regno < FIRST_PSEUDO_REGISTER)
2110 mark_life (regno, GET_MODE (reg), 1);
2112 /* If the register was to have been born earlier that the present
2113 insn, mark it as live where it is actually born. */
2114 if (birth < 2 * this_insn_number)
2115 post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number);
2119 if (reg_qty[regno] == -2)
2120 alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth);
2122 /* If this register has a quantity number, show that it isn't dead. */
2123 if (reg_qty[regno] >= 0)
2124 qty[reg_qty[regno]].death = -1;
2128 /* Record the death of REG in the current insn. If OUTPUT_P is nonzero,
2129 REG is an output that is dying (i.e., it is never used), otherwise it
2130 is an input (the normal case).
2131 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
2134 wipe_dead_reg (rtx reg, int output_p)
2136 int regno = REGNO (reg);
2138 /* If this insn has multiple results,
2139 and the dead reg is used in one of the results,
2140 extend its life to after this insn,
2141 so it won't get allocated together with any other result of this insn.
2143 It is unsafe to use !single_set here since it will ignore an unused
2144 output. Just because an output is unused does not mean the compiler
2145 can assume the side effect will not occur. Consider if REG appears
2146 in the address of an output and we reload the output. If we allocate
2147 REG to the same hard register as an unused output we could set the hard
2148 register before the output reload insn. */
2149 if (GET_CODE (PATTERN (this_insn)) == PARALLEL
2150 && multiple_sets (this_insn))
2153 for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--)
2155 rtx set = XVECEXP (PATTERN (this_insn), 0, i);
2156 if (GET_CODE (set) == SET
2157 && !REG_P (SET_DEST (set))
2158 && !rtx_equal_p (reg, SET_DEST (set))
2159 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2164 /* If this register is used in an auto-increment address, then extend its
2165 life to after this insn, so that it won't get allocated together with
2166 the result of this insn. */
2167 if (! output_p && find_regno_note (this_insn, REG_INC, regno))
2170 if (regno < FIRST_PSEUDO_REGISTER)
2172 mark_life (regno, GET_MODE (reg), 0);
2174 /* If a hard register is dying as an output, mark it as in use at
2175 the beginning of this insn (the above statement would cause this
2178 post_mark_life (regno, GET_MODE (reg), 1,
2179 2 * this_insn_number, 2 * this_insn_number + 1);
2182 else if (reg_qty[regno] >= 0)
2183 qty[reg_qty[regno]].death = 2 * this_insn_number + output_p;
2186 /* Find a block of SIZE words of hard regs in reg_class CLASS
2187 that can hold something of machine-mode MODE
2188 (but actually we test only the first of the block for holding MODE)
2189 and still free between insn BORN_INDEX and insn DEAD_INDEX,
2190 and return the number of the first of them.
2191 Return -1 if such a block cannot be found.
2192 If QTYNO crosses calls, insist on a register preserved by calls,
2193 unless ACCEPT_CALL_CLOBBERED is nonzero.
2195 If JUST_TRY_SUGGESTED is nonzero, only try to see if the suggested
2196 register is available. If not, return -1. */
2199 find_free_reg (enum reg_class class, enum machine_mode mode, int qtyno,
2200 int accept_call_clobbered, int just_try_suggested,
2201 int born_index, int dead_index)
2204 HARD_REG_SET first_used, used;
2205 #ifdef ELIMINABLE_REGS
2206 static const struct {const int from, to; } eliminables[] = ELIMINABLE_REGS;
2209 /* Validate our parameters. */
2210 gcc_assert (born_index >= 0 && born_index <= dead_index);
2212 /* Don't let a pseudo live in a reg across a function call
2213 if we might get a nonlocal goto. */
2214 if (current_function_has_nonlocal_label
2215 && qty[qtyno].n_calls_crossed > 0)
2218 if (accept_call_clobbered)
2219 COPY_HARD_REG_SET (used, call_fixed_reg_set);
2220 else if (qty[qtyno].n_calls_crossed == 0)
2221 COPY_HARD_REG_SET (used, fixed_reg_set);
2223 COPY_HARD_REG_SET (used, call_used_reg_set);
2225 if (accept_call_clobbered)
2226 IOR_HARD_REG_SET (used, losing_caller_save_reg_set);
2228 for (ins = born_index; ins < dead_index; ins++)
2229 IOR_HARD_REG_SET (used, regs_live_at[ins]);
2231 IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]);
2233 /* Don't use the frame pointer reg in local-alloc even if
2234 we may omit the frame pointer, because if we do that and then we
2235 need a frame pointer, reload won't know how to move the pseudo
2236 to another hard reg. It can move only regs made by global-alloc.
2238 This is true of any register that can be eliminated. */
2239 #ifdef ELIMINABLE_REGS
2240 for (i = 0; i < (int) ARRAY_SIZE (eliminables); i++)
2241 SET_HARD_REG_BIT (used, eliminables[i].from);
2242 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
2243 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
2244 that it might be eliminated into. */
2245 SET_HARD_REG_BIT (used, HARD_FRAME_POINTER_REGNUM);
2248 SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM);
2251 #ifdef CANNOT_CHANGE_MODE_CLASS
2252 cannot_change_mode_set_regs (&used, mode, qty[qtyno].first_reg);
2255 /* Normally, the registers that can be used for the first register in
2256 a multi-register quantity are the same as those that can be used for
2257 subsequent registers. However, if just trying suggested registers,
2258 restrict our consideration to them. If there are copy-suggested
2259 register, try them. Otherwise, try the arithmetic-suggested
2261 COPY_HARD_REG_SET (first_used, used);
2263 if (just_try_suggested)
2265 if (qty_phys_num_copy_sugg[qtyno] != 0)
2266 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qtyno]);
2268 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qtyno]);
2271 /* If at least one would be suitable, test each hard reg. */
2272 if (!hard_reg_set_subset_p (reg_class_contents[(int) ALL_REGS], first_used))
2273 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2275 #ifdef REG_ALLOC_ORDER
2276 int regno = reg_alloc_order[i];
2280 if (!TEST_HARD_REG_BIT (first_used, regno)
2281 && HARD_REGNO_MODE_OK (regno, mode)
2282 && (qty[qtyno].n_calls_crossed == 0
2283 || accept_call_clobbered
2284 || !HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
2287 int size1 = hard_regno_nregs[regno][mode];
2289 while (j < size1 && !TEST_HARD_REG_BIT (used, regno + j))
2293 /* Mark that this register is in use between its birth
2295 post_mark_life (regno, mode, 1, born_index, dead_index);
2298 #ifndef REG_ALLOC_ORDER
2299 /* Skip starting points we know will lose. */
2305 /* If we are just trying suggested register, we have just tried copy-
2306 suggested registers, and there are arithmetic-suggested registers,
2309 /* If it would be profitable to allocate a call-clobbered register
2310 and save and restore it around calls, do that. */
2311 if (just_try_suggested && qty_phys_num_copy_sugg[qtyno] != 0
2312 && qty_phys_num_sugg[qtyno] != 0)
2314 /* Don't try the copy-suggested regs again. */
2315 qty_phys_num_copy_sugg[qtyno] = 0;
2316 return find_free_reg (class, mode, qtyno, accept_call_clobbered, 1,
2317 born_index, dead_index);
2320 /* We need not check to see if the current function has nonlocal
2321 labels because we don't put any pseudos that are live over calls in
2322 registers in that case. Avoid putting pseudos crossing calls that
2323 might throw into call used registers. */
2325 if (! accept_call_clobbered
2326 && flag_caller_saves
2327 && ! just_try_suggested
2328 && qty[qtyno].n_calls_crossed != 0
2329 && qty[qtyno].n_throwing_calls_crossed == 0
2330 && CALLER_SAVE_PROFITABLE (qty[qtyno].n_refs,
2331 qty[qtyno].n_calls_crossed))
2333 i = find_free_reg (class, mode, qtyno, 1, 0, born_index, dead_index);
2335 caller_save_needed = 1;
2341 /* Mark that REGNO with machine-mode MODE is live starting from the current
2342 insn (if LIFE is nonzero) or dead starting at the current insn (if LIFE
2346 mark_life (int regno, enum machine_mode mode, int life)
2349 add_to_hard_reg_set (®s_live, mode, regno);
2351 remove_from_hard_reg_set (®s_live, mode, regno);
2354 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2355 is nonzero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2356 to insn number DEATH (exclusive). */
2359 post_mark_life (int regno, enum machine_mode mode, int life, int birth,
2362 HARD_REG_SET this_reg;
2364 CLEAR_HARD_REG_SET (this_reg);
2365 add_to_hard_reg_set (&this_reg, mode, regno);
2368 while (birth < death)
2370 IOR_HARD_REG_SET (regs_live_at[birth], this_reg);
2374 while (birth < death)
2376 AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg);
2381 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2382 is the register being clobbered, and R1 is a register being used in
2383 the equivalent expression.
2385 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2386 in which it is used, return 1.
2388 Otherwise, return 0. */
2391 no_conflict_p (rtx insn, rtx r0 ATTRIBUTE_UNUSED, rtx r1)
2394 rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
2397 /* If R1 is a hard register, return 0 since we handle this case
2398 when we scan the insns that actually use it. */
2401 || (REG_P (r1) && REGNO (r1) < FIRST_PSEUDO_REGISTER)
2402 || (GET_CODE (r1) == SUBREG && REG_P (SUBREG_REG (r1))
2403 && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER))
2406 last = XEXP (note, 0);
2408 for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p))
2411 if (find_reg_note (p, REG_DEAD, r1))
2414 /* There must be a REG_NO_CONFLICT note on every insn, otherwise
2415 some earlier optimization pass has inserted instructions into
2416 the sequence, and it is not safe to perform this optimization.
2417 Note that emit_no_conflict_block always ensures that this is
2418 true when these sequences are created. */
2419 if (! find_reg_note (p, REG_NO_CONFLICT, r1))
2426 /* Return the number of alternatives for which the constraint string P
2427 indicates that the operand must be equal to operand 0 and that no register
2431 requires_inout (const char *p)
2435 int reg_allowed = 0;
2436 int num_matching_alts = 0;
2439 for ( ; (c = *p); p += len)
2441 len = CONSTRAINT_LEN (c, p);
2444 case '=': case '+': case '?':
2445 case '#': case '&': case '!':
2447 case 'm': case '<': case '>': case 'V': case 'o':
2448 case 'E': case 'F': case 'G': case 'H':
2449 case 's': case 'i': case 'n':
2450 case 'I': case 'J': case 'K': case 'L':
2451 case 'M': case 'N': case 'O': case 'P':
2453 /* These don't say anything we care about. */
2457 if (found_zero && ! reg_allowed)
2458 num_matching_alts++;
2460 found_zero = reg_allowed = 0;
2467 case '1': case '2': case '3': case '4': case '5':
2468 case '6': case '7': case '8': case '9':
2469 /* Skip the balance of the matching constraint. */
2472 while (ISDIGIT (*p));
2477 if (REG_CLASS_FROM_CONSTRAINT (c, p) == NO_REGS
2478 && !EXTRA_ADDRESS_CONSTRAINT (c, p))
2488 if (found_zero && ! reg_allowed)
2489 num_matching_alts++;
2491 return num_matching_alts;
2495 dump_local_alloc (FILE *file)
2498 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2499 if (reg_renumber[i] != -1)
2500 fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]);
2503 /* Run old register allocator. Return TRUE if we must exit
2504 rest_of_compilation upon return. */
2506 rest_of_handle_local_alloc (void)
2509 int max_regno = max_reg_num ();
2511 df_note_add_problem ();
2514 df_remove_problem (df_live);
2515 /* Create a new version of df that has the special version of UR if
2516 we are doing optimization. */
2518 df_urec_add_problem ();
2520 regstat_init_n_sets_and_refs ();
2521 regstat_compute_ri ();
2523 /* There is just too much going on in the register allocators to
2524 keep things up to date. At the end we have to rescan anyway
2525 because things change when the reload_completed flag is set.
2526 So we just turn off scanning and we will rescan by hand. */
2527 df_set_flags (DF_NO_INSN_RESCAN);
2530 /* If we are not optimizing, then this is the only place before
2531 register allocation where dataflow is done. And that is needed
2532 to generate these warnings. */
2534 generate_setjmp_warnings ();
2536 /* Determine if the current function is a leaf before running reload
2537 since this can impact optimizations done by the prologue and
2538 epilogue thus changing register elimination offsets. */
2539 current_function_is_leaf = leaf_function_p ();
2541 /* And the reg_equiv_memory_loc array. */
2542 VEC_safe_grow (rtx, gc, reg_equiv_memory_loc_vec, max_regno);
2543 memset (VEC_address (rtx, reg_equiv_memory_loc_vec), 0,
2544 sizeof (rtx) * max_regno);
2545 reg_equiv_memory_loc = VEC_address (rtx, reg_equiv_memory_loc_vec);
2547 allocate_initial_values (reg_equiv_memory_loc);
2549 regclass (get_insns (), max_regno);
2550 rebuild_notes = local_alloc ();
2552 /* Local allocation may have turned an indirect jump into a direct
2553 jump. If so, we must rebuild the JUMP_LABEL fields of jumping
2557 timevar_push (TV_JUMP);
2559 rebuild_jump_labels (get_insns ());
2560 purge_all_dead_edges ();
2561 timevar_pop (TV_JUMP);
2564 if (dump_file && (dump_flags & TDF_DETAILS))
2566 timevar_push (TV_DUMP);
2567 dump_flow_info (dump_file, dump_flags);
2568 dump_local_alloc (dump_file);
2569 timevar_pop (TV_DUMP);
2574 struct tree_opt_pass pass_local_alloc =
2578 rest_of_handle_local_alloc, /* execute */
2581 0, /* static_pass_number */
2582 TV_LOCAL_ALLOC, /* tv_id */
2583 0, /* properties_required */
2584 0, /* properties_provided */
2585 0, /* properties_destroyed */
2586 0, /* todo_flags_start */
2588 TODO_ggc_collect, /* todo_flags_finish */