1 /* IRA processing allocno lives to build allocno live ranges.
2 Copyright (C) 2006, 2007, 2008
3 Free Software Foundation, Inc.
4 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
31 #include "hard-reg-set.h"
32 #include "basic-block.h"
33 #include "insn-config.h"
38 #include "sparseset.h"
41 /* The code in this file is similar to one in global but the code
42 works on the allocno basis and creates live ranges instead of
43 pseudo-register conflicts. */
45 /* Program points are enumerated by numbers from range
46 0..IRA_MAX_POINT-1. There are approximately two times more program
47 points than insns. Program points are places in the program where
48 liveness info can be changed. In most general case (there are more
49 complicated cases too) some program points correspond to places
50 where input operand dies and other ones correspond to places where
51 output operands are born. */
54 /* Arrays of size IRA_MAX_POINT mapping a program point to the allocno
55 live ranges with given start/finish point. */
56 allocno_live_range_t *ira_start_point_ranges, *ira_finish_point_ranges;
58 /* Number of the current program point. */
59 static int curr_point;
61 /* Point where register pressure excess started or -1 if there is no
62 register pressure excess. Excess pressure for a register class at
63 some point means that there are more allocnos of given register
64 class living at the point than number of hard-registers of the
65 class available for the allocation. It is defined only for cover
67 static int high_pressure_start_point[N_REG_CLASSES];
69 /* Allocnos live at current point in the scan. */
70 static sparseset allocnos_live;
72 /* Set of hard regs (except eliminable ones) currently live. */
73 static HARD_REG_SET hard_regs_live;
75 /* The loop tree node corresponding to the current basic block. */
76 static ira_loop_tree_node_t curr_bb_node;
78 /* The number of the last processed call. */
79 static int last_call_num;
80 /* The number of last call at which given allocno was saved. */
81 static int *allocno_saved_at_call;
83 /* The function processing birth of register REGNO. It updates living
84 hard regs and conflict hard regs for living allocnos or starts a
85 new live range for the allocno corresponding to REGNO if it is
88 make_regno_born (int regno)
92 allocno_live_range_t p;
94 if (regno < FIRST_PSEUDO_REGISTER)
96 SET_HARD_REG_BIT (hard_regs_live, regno);
97 EXECUTE_IF_SET_IN_SPARSESET (allocnos_live, i)
99 SET_HARD_REG_BIT (ALLOCNO_CONFLICT_HARD_REGS (ira_allocnos[i]),
101 SET_HARD_REG_BIT (ALLOCNO_TOTAL_CONFLICT_HARD_REGS (ira_allocnos[i]),
106 a = ira_curr_regno_allocno_map[regno];
109 if ((p = ALLOCNO_LIVE_RANGES (a)) == NULL
110 || (p->finish != curr_point && p->finish + 1 != curr_point))
111 ALLOCNO_LIVE_RANGES (a)
112 = ira_create_allocno_live_range (a, curr_point, -1,
113 ALLOCNO_LIVE_RANGES (a));
116 /* Update ALLOCNO_EXCESS_PRESSURE_POINTS_NUM for allocno A. */
118 update_allocno_pressure_excess_length (ira_allocno_t a)
121 enum reg_class cover_class, cl;
122 allocno_live_range_t p;
124 cover_class = ALLOCNO_COVER_CLASS (a);
126 (cl = ira_reg_class_super_classes[cover_class][i]) != LIM_REG_CLASSES;
129 if (high_pressure_start_point[cl] < 0)
131 p = ALLOCNO_LIVE_RANGES (a);
132 ira_assert (p != NULL);
133 start = (high_pressure_start_point[cl] > p->start
134 ? high_pressure_start_point[cl] : p->start);
135 ALLOCNO_EXCESS_PRESSURE_POINTS_NUM (a) += curr_point - start + 1;
139 /* Process the death of register REGNO. This updates hard_regs_live
140 or finishes the current live range for the allocno corresponding to
143 make_regno_dead (int regno)
146 allocno_live_range_t p;
148 if (regno < FIRST_PSEUDO_REGISTER)
150 CLEAR_HARD_REG_BIT (hard_regs_live, regno);
153 a = ira_curr_regno_allocno_map[regno];
156 p = ALLOCNO_LIVE_RANGES (a);
157 ira_assert (p != NULL);
158 p->finish = curr_point;
159 update_allocno_pressure_excess_length (a);
162 /* The current register pressures for each cover class for the current
164 static int curr_reg_pressure[N_REG_CLASSES];
166 /* Mark allocno A as currently living and update current register
167 pressure, maximal register pressure for the current BB, start point
168 of the register pressure excess, and conflicting hard registers of
171 set_allocno_live (ira_allocno_t a)
174 enum reg_class cover_class, cl;
176 /* Invalidate because it is referenced. */
177 allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
178 if (sparseset_bit_p (allocnos_live, ALLOCNO_NUM (a)))
180 sparseset_set_bit (allocnos_live, ALLOCNO_NUM (a));
181 IOR_HARD_REG_SET (ALLOCNO_CONFLICT_HARD_REGS (a), hard_regs_live);
182 IOR_HARD_REG_SET (ALLOCNO_TOTAL_CONFLICT_HARD_REGS (a), hard_regs_live);
183 cover_class = ALLOCNO_COVER_CLASS (a);
185 (cl = ira_reg_class_super_classes[cover_class][i]) != LIM_REG_CLASSES;
188 curr_reg_pressure[cl] += ira_reg_class_nregs[cl][ALLOCNO_MODE (a)];
189 if (high_pressure_start_point[cl] < 0
190 && (curr_reg_pressure[cl] > ira_available_class_regs[cl]))
191 high_pressure_start_point[cl] = curr_point;
192 if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl])
193 curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl];
197 /* Mark allocno A as currently not living and update current register
198 pressure, start point of the register pressure excess, and register
199 pressure excess length for living allocnos. */
201 clear_allocno_live (ira_allocno_t a)
205 enum reg_class cover_class, cl;
208 /* Invalidate because it is referenced. */
209 allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
210 if (sparseset_bit_p (allocnos_live, ALLOCNO_NUM (a)))
212 cover_class = ALLOCNO_COVER_CLASS (a);
215 (cl = ira_reg_class_super_classes[cover_class][i])
219 curr_reg_pressure[cl] -= ira_reg_class_nregs[cl][ALLOCNO_MODE (a)];
220 ira_assert (curr_reg_pressure[cl] >= 0);
221 if (high_pressure_start_point[cl] >= 0
222 && curr_reg_pressure[cl] <= ira_available_class_regs[cl])
227 EXECUTE_IF_SET_IN_SPARSESET (allocnos_live, j)
228 update_allocno_pressure_excess_length (ira_allocnos[j]);
230 (cl = ira_reg_class_super_classes[cover_class][i])
233 if (high_pressure_start_point[cl] >= 0
234 && curr_reg_pressure[cl] <= ira_available_class_regs[cl])
235 high_pressure_start_point[cl] = -1;
239 sparseset_clear_bit (allocnos_live, ALLOCNO_NUM (a));
242 /* Mark the register REG as live. Store a 1 in hard_regs_live or
243 allocnos_live for this register or the corresponding allocno,
244 record how many consecutive hardware registers it actually
247 mark_reg_live (rtx reg)
251 gcc_assert (REG_P (reg));
254 if (regno >= FIRST_PSEUDO_REGISTER)
256 ira_allocno_t a = ira_curr_regno_allocno_map[regno];
260 if (sparseset_bit_p (allocnos_live, ALLOCNO_NUM (a)))
262 /* Invalidate because it is referenced. */
263 allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
266 set_allocno_live (a);
268 make_regno_born (regno);
270 else if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno))
272 int last = regno + hard_regno_nregs[regno][GET_MODE (reg)];
273 enum reg_class cover_class, cl;
277 if (! TEST_HARD_REG_BIT (hard_regs_live, regno)
278 && ! TEST_HARD_REG_BIT (eliminable_regset, regno))
280 cover_class = ira_hard_regno_cover_class[regno];
282 (cl = ira_reg_class_super_classes[cover_class][i])
286 curr_reg_pressure[cl]++;
287 if (high_pressure_start_point[cl] < 0
288 && (curr_reg_pressure[cl]
289 > ira_available_class_regs[cl]))
290 high_pressure_start_point[cl] = curr_point;
292 make_regno_born (regno);
294 (cl = ira_reg_class_super_classes[cover_class][i])
298 if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl])
299 curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl];
307 /* Mark the register referenced by use or def REF as live. */
309 mark_ref_live (df_ref ref)
313 reg = DF_REF_REG (ref);
314 if (GET_CODE (reg) == SUBREG)
315 reg = SUBREG_REG (reg);
319 /* Mark the register REG as dead. Store a 0 in hard_regs_live or
320 allocnos_live for the register. */
322 mark_reg_dead (rtx reg)
326 gcc_assert (REG_P (reg));
329 if (regno >= FIRST_PSEUDO_REGISTER)
331 ira_allocno_t a = ira_curr_regno_allocno_map[regno];
335 if (! sparseset_bit_p (allocnos_live, ALLOCNO_NUM (a)))
337 /* Invalidate because it is referenced. */
338 allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
341 clear_allocno_live (a);
343 make_regno_dead (regno);
345 else if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno))
349 int last = regno + hard_regno_nregs[regno][GET_MODE (reg)];
350 enum reg_class cover_class, cl;
355 if (TEST_HARD_REG_BIT (hard_regs_live, regno))
358 cover_class = ira_hard_regno_cover_class[regno];
360 (cl = ira_reg_class_super_classes[cover_class][i])
364 curr_reg_pressure[cl]--;
365 if (high_pressure_start_point[cl] >= 0
366 && curr_reg_pressure[cl] <= ira_available_class_regs[cl])
368 ira_assert (curr_reg_pressure[cl] >= 0);
372 EXECUTE_IF_SET_IN_SPARSESET (allocnos_live, j)
373 update_allocno_pressure_excess_length (ira_allocnos[j]);
375 (cl = ira_reg_class_super_classes[cover_class][i])
378 if (high_pressure_start_point[cl] >= 0
379 && (curr_reg_pressure[cl]
380 <= ira_available_class_regs[cl]))
381 high_pressure_start_point[cl] = -1;
383 make_regno_dead (regno);
390 /* Mark the register referenced by definition DEF as dead, if the
391 definition is a total one. */
393 mark_ref_dead (df_ref def)
397 if (DF_REF_FLAGS_IS_SET (def, DF_REF_PARTIAL)
398 || DF_REF_FLAGS_IS_SET (def, DF_REF_CONDITIONAL))
401 reg = DF_REF_REG (def);
402 if (GET_CODE (reg) == SUBREG)
403 reg = SUBREG_REG (reg);
407 /* Make pseudo REG conflicting with pseudo DREG, if the 1st pseudo
408 class is intersected with class CL. Advance the current program
409 point before making the conflict if ADVANCE_P. Return TRUE if we
410 will need to advance the current program point. */
412 make_pseudo_conflict (rtx reg, enum reg_class cl, rtx dreg, bool advance_p)
416 if (GET_CODE (reg) == SUBREG)
417 reg = SUBREG_REG (reg);
419 if (! REG_P (reg) || REGNO (reg) < FIRST_PSEUDO_REGISTER)
422 a = ira_curr_regno_allocno_map[REGNO (reg)];
423 if (! reg_classes_intersect_p (cl, ALLOCNO_COVER_CLASS (a)))
430 mark_reg_live (dreg);
432 mark_reg_dead (dreg);
437 /* Check and make if necessary conflicts for pseudo DREG of class
438 DEF_CL of the current insn with input operand USE of class USE_CL.
439 Advance the current program point before making the conflict if
440 ADVANCE_P. Return TRUE if we will need to advance the current
443 check_and_make_def_use_conflict (rtx dreg, enum reg_class def_cl,
444 int use, enum reg_class use_cl,
447 if (! reg_classes_intersect_p (def_cl, use_cl))
450 advance_p = make_pseudo_conflict (recog_data.operand[use],
451 use_cl, dreg, advance_p);
452 /* Reload may end up swapping commutative operands, so you
453 have to take both orderings into account. The
454 constraints for the two operands can be completely
455 different. (Indeed, if the constraints for the two
456 operands are the same for all alternatives, there's no
457 point marking them as commutative.) */
458 if (use < recog_data.n_operands + 1
459 && recog_data.constraints[use][0] == '%')
461 = make_pseudo_conflict (recog_data.operand[use + 1],
462 use_cl, dreg, advance_p);
464 && recog_data.constraints[use - 1][0] == '%')
466 = make_pseudo_conflict (recog_data.operand[use - 1],
467 use_cl, dreg, advance_p);
471 /* Check and make if necessary conflicts for definition DEF of class
472 DEF_CL of the current insn with input operands. Process only
473 constraints of alternative ALT. */
475 check_and_make_def_conflict (int alt, int def, enum reg_class def_cl)
479 enum reg_class use_cl, acl;
481 rtx dreg = recog_data.operand[def];
483 if (def_cl == NO_REGS)
486 if (GET_CODE (dreg) == SUBREG)
487 dreg = SUBREG_REG (dreg);
489 if (! REG_P (dreg) || REGNO (dreg) < FIRST_PSEUDO_REGISTER)
492 a = ira_curr_regno_allocno_map[REGNO (dreg)];
493 acl = ALLOCNO_COVER_CLASS (a);
494 if (! reg_classes_intersect_p (acl, def_cl))
499 for (use = 0; use < recog_data.n_operands; use++)
501 if (use == def || recog_data.operand_type[use] == OP_OUT)
504 if (recog_op_alt[use][alt].anything_ok)
507 use_cl = recog_op_alt[use][alt].cl;
509 advance_p = check_and_make_def_use_conflict (dreg, def_cl, use,
512 if ((use_match = recog_op_alt[use][alt].matches) >= 0)
514 if (use_match == def)
517 if (recog_op_alt[use_match][alt].anything_ok)
520 use_cl = recog_op_alt[use_match][alt].cl;
521 advance_p = check_and_make_def_use_conflict (dreg, def_cl, use,
527 /* Make conflicts of early clobber pseudo registers of the current
528 insn with its inputs. Avoid introducing unnecessary conflicts by
529 checking classes of the constraints and pseudos because otherwise
530 significant code degradation is possible for some targets. */
532 make_early_clobber_and_input_conflicts (void)
536 enum reg_class def_cl;
538 for (alt = 0; alt < recog_data.n_alternatives; alt++)
539 for (def = 0; def < recog_data.n_operands; def++)
542 if (recog_op_alt[def][alt].earlyclobber)
544 if (recog_op_alt[def][alt].anything_ok)
547 def_cl = recog_op_alt[def][alt].cl;
548 check_and_make_def_conflict (alt, def, def_cl);
550 if ((def_match = recog_op_alt[def][alt].matches) >= 0
551 && (recog_op_alt[def_match][alt].earlyclobber
552 || recog_op_alt[def][alt].earlyclobber))
554 if (recog_op_alt[def_match][alt].anything_ok)
557 def_cl = recog_op_alt[def_match][alt].cl;
558 check_and_make_def_conflict (alt, def, def_cl);
563 /* Mark early clobber hard registers of the current INSN as live (if
564 LIVE_P) or dead. Return true if there are such registers. */
566 mark_hard_reg_early_clobbers (rtx insn, bool live_p)
571 for (def_rec = DF_INSN_DEFS (insn); *def_rec; def_rec++)
572 if (DF_REF_FLAGS_IS_SET (*def_rec, DF_REF_MUST_CLOBBER))
574 rtx dreg = DF_REF_REG (*def_rec);
576 if (GET_CODE (dreg) == SUBREG)
577 dreg = SUBREG_REG (dreg);
578 if (! REG_P (dreg) || REGNO (dreg) >= FIRST_PSEUDO_REGISTER)
581 /* Hard register clobbers are believed to be early clobber
582 because there is no way to say that non-operand hard
583 register clobbers are not early ones. */
585 mark_ref_live (*def_rec);
587 mark_ref_dead (*def_rec);
594 /* Checks that CONSTRAINTS permits to use only one hard register. If
595 it is so, the function returns the class of the hard register.
596 Otherwise it returns NO_REGS. */
597 static enum reg_class
598 single_reg_class (const char *constraints, rtx op, rtx equiv_const)
601 enum reg_class cl, next_cl;
605 for (ignore_p = false;
607 constraints += CONSTRAINT_LEN (c, constraints))
627 || (equiv_const != NULL_RTX && CONSTANT_P (equiv_const)))
632 if (GET_CODE (op) == CONST_INT
633 || (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == VOIDmode)
634 || (equiv_const != NULL_RTX
635 && (GET_CODE (equiv_const) == CONST_INT
636 || (GET_CODE (equiv_const) == CONST_DOUBLE
637 && GET_MODE (equiv_const) == VOIDmode))))
642 if ((CONSTANT_P (op) && GET_CODE (op) != CONST_INT
643 && (GET_CODE (op) != CONST_DOUBLE || GET_MODE (op) != VOIDmode))
644 || (equiv_const != NULL_RTX
645 && CONSTANT_P (equiv_const)
646 && GET_CODE (equiv_const) != CONST_INT
647 && (GET_CODE (equiv_const) != CONST_DOUBLE
648 || GET_MODE (equiv_const) != VOIDmode)))
660 if ((GET_CODE (op) == CONST_INT
661 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), c, constraints))
662 || (equiv_const != NULL_RTX
663 && GET_CODE (equiv_const) == CONST_INT
664 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (equiv_const),
671 if (GET_CODE (op) == CONST_DOUBLE
672 || (GET_CODE (op) == CONST_VECTOR
673 && GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_FLOAT)
674 || (equiv_const != NULL_RTX
675 && (GET_CODE (equiv_const) == CONST_DOUBLE
676 || (GET_CODE (equiv_const) == CONST_VECTOR
677 && (GET_MODE_CLASS (GET_MODE (equiv_const))
678 == MODE_VECTOR_FLOAT)))))
684 if ((GET_CODE (op) == CONST_DOUBLE
685 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, c, constraints))
686 || (equiv_const != NULL_RTX
687 && GET_CODE (equiv_const) == CONST_DOUBLE
688 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (equiv_const,
691 /* ??? what about memory */
693 case 'a': case 'b': case 'c': case 'd': case 'e': case 'f':
694 case 'h': case 'j': case 'k': case 'l':
695 case 'q': case 't': case 'u':
696 case 'v': case 'w': case 'x': case 'y': case 'z':
697 case 'A': case 'B': case 'C': case 'D':
698 case 'Q': case 'R': case 'S': case 'T': case 'U':
699 case 'W': case 'Y': case 'Z':
702 : REG_CLASS_FROM_CONSTRAINT (c, constraints));
703 if ((cl != NO_REGS && next_cl != cl)
704 || ira_available_class_regs[next_cl] > 1)
709 case '0': case '1': case '2': case '3': case '4':
710 case '5': case '6': case '7': case '8': case '9':
712 = single_reg_class (recog_data.constraints[c - '0'],
713 recog_data.operand[c - '0'], NULL_RTX);
714 if ((cl != NO_REGS && next_cl != cl) || next_cl == NO_REGS
715 || ira_available_class_regs[next_cl] > 1)
726 /* The function checks that operand OP_NUM of the current insn can use
727 only one hard register. If it is so, the function returns the
728 class of the hard register. Otherwise it returns NO_REGS. */
729 static enum reg_class
730 single_reg_operand_class (int op_num)
732 if (op_num < 0 || recog_data.n_alternatives == 0)
734 return single_reg_class (recog_data.constraints[op_num],
735 recog_data.operand[op_num], NULL_RTX);
738 /* Processes input operands, if IN_P, or output operands otherwise of
739 the current insn with FREQ to find allocno which can use only one
740 hard register and makes other currently living allocnos conflicting
741 with the hard register. */
743 process_single_reg_class_operands (bool in_p, int freq)
747 enum reg_class cl, cover_class;
749 ira_allocno_t operand_a, a;
751 for (i = 0; i < recog_data.n_operands; i++)
753 operand = recog_data.operand[i];
754 if (in_p && recog_data.operand_type[i] != OP_IN
755 && recog_data.operand_type[i] != OP_INOUT)
757 if (! in_p && recog_data.operand_type[i] != OP_OUT
758 && recog_data.operand_type[i] != OP_INOUT)
760 cl = single_reg_operand_class (i);
766 if (GET_CODE (operand) == SUBREG)
767 operand = SUBREG_REG (operand);
770 && (regno = REGNO (operand)) >= FIRST_PSEUDO_REGISTER)
772 enum machine_mode mode;
773 enum reg_class cover_class;
775 operand_a = ira_curr_regno_allocno_map[regno];
776 mode = ALLOCNO_MODE (operand_a);
777 cover_class = ALLOCNO_COVER_CLASS (operand_a);
778 if (ira_class_subset_p[cl][cover_class]
779 && ira_class_hard_regs_num[cl] != 0
780 && (ira_class_hard_reg_index[cover_class]
781 [ira_class_hard_regs[cl][0]]) >= 0
782 && reg_class_size[cl] <= (unsigned) CLASS_MAX_NREGS (cl, mode))
786 ? ira_register_move_cost[mode][cover_class][cl]
787 : ira_register_move_cost[mode][cl][cover_class]);
788 ira_allocate_and_set_costs
789 (&ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a), cover_class, 0);
790 ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a)
791 [ira_class_hard_reg_index
792 [cover_class][ira_class_hard_regs[cl][0]]]
797 EXECUTE_IF_SET_IN_SPARSESET (allocnos_live, px)
799 a = ira_allocnos[px];
800 cover_class = ALLOCNO_COVER_CLASS (a);
803 /* We could increase costs of A instead of making it
804 conflicting with the hard register. But it works worse
805 because it will be spilled in reload in anyway. */
806 IOR_HARD_REG_SET (ALLOCNO_CONFLICT_HARD_REGS (a),
807 reg_class_contents[cl]);
808 IOR_HARD_REG_SET (ALLOCNO_TOTAL_CONFLICT_HARD_REGS (a),
809 reg_class_contents[cl]);
815 /* Process insns of the basic block given by its LOOP_TREE_NODE to
816 update allocno live ranges, allocno hard register conflicts,
817 intersected calls, and register pressure info for allocnos for the
818 basic block for and regions containing the basic block. */
820 process_bb_node_lives (ira_loop_tree_node_t loop_tree_node)
831 bb = loop_tree_node->bb;
834 for (i = 0; i < ira_reg_class_cover_size; i++)
836 curr_reg_pressure[ira_reg_class_cover[i]] = 0;
837 high_pressure_start_point[ira_reg_class_cover[i]] = -1;
839 curr_bb_node = loop_tree_node;
840 reg_live_out = DF_LR_OUT (bb);
841 sparseset_clear (allocnos_live);
842 REG_SET_TO_HARD_REG_SET (hard_regs_live, reg_live_out);
843 AND_COMPL_HARD_REG_SET (hard_regs_live, eliminable_regset);
844 AND_COMPL_HARD_REG_SET (hard_regs_live, ira_no_alloc_regs);
845 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
846 if (TEST_HARD_REG_BIT (hard_regs_live, i))
848 enum reg_class cover_class, cl;
850 cover_class = ira_class_translate[REGNO_REG_CLASS (i)];
852 (cl = ira_reg_class_super_classes[cover_class][j])
856 curr_reg_pressure[cl]++;
857 if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl])
858 curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl];
859 ira_assert (curr_reg_pressure[cl]
860 <= ira_available_class_regs[cl]);
863 EXECUTE_IF_SET_IN_BITMAP (reg_live_out, FIRST_PSEUDO_REGISTER, j, bi)
865 ira_allocno_t a = ira_curr_regno_allocno_map[j];
869 ira_assert (! sparseset_bit_p (allocnos_live, ALLOCNO_NUM (a)));
870 set_allocno_live (a);
874 freq = REG_FREQ_FROM_BB (bb);
878 /* Invalidate all allocno_saved_at_call entries. */
881 /* Scan the code of this basic block, noting which allocnos and
882 hard regs are born or die.
884 Note that this loop treats uninitialized values as live until
885 the beginning of the block. For example, if an instruction
886 uses (reg:DI foo), and only (subreg:SI (reg:DI foo) 0) is ever
887 set, FOO will remain live until the beginning of the block.
888 Likewise if FOO is not set at all. This is unnecessarily
889 pessimistic, but it probably doesn't matter much in practice. */
890 FOR_BB_INSNS_REVERSE (bb, insn)
892 df_ref *def_rec, *use_rec;
898 if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL)
899 fprintf (ira_dump_file, " Insn %u(l%d): point = %d\n",
900 INSN_UID (insn), loop_tree_node->parent->loop->num,
903 /* Mark each defined value as live. We need to do this for
904 unused values because they still conflict with quantities
905 that are live at the time of the definition.
907 Ignore DF_REF_MAY_CLOBBERs on a call instruction. Such
908 references represent the effect of the called function
909 on a call-clobbered register. Marking the register as
910 live would stop us from allocating it to a call-crossing
912 call_p = CALL_P (insn);
913 for (def_rec = DF_INSN_DEFS (insn); *def_rec; def_rec++)
914 if (!call_p || !DF_REF_FLAGS_IS_SET (*def_rec, DF_REF_MAY_CLOBBER))
915 mark_ref_live (*def_rec);
917 /* If INSN has multiple outputs, then any value used in one
918 of the outputs conflicts with the other outputs. Model this
919 by making the used value live during the output phase.
921 It is unsafe to use !single_set here since it will ignore
922 an unused output. Just because an output is unused does
923 not mean the compiler can assume the side effect will not
924 occur. Consider if ALLOCNO appears in the address of an
925 output and we reload the output. If we allocate ALLOCNO
926 to the same hard register as an unused output we could
927 set the hard register before the output reload insn. */
928 if (GET_CODE (PATTERN (insn)) == PARALLEL && multiple_sets (insn))
929 for (use_rec = DF_INSN_USES (insn); *use_rec; use_rec++)
934 reg = DF_REF_REG (*use_rec);
935 for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--)
939 set = XVECEXP (PATTERN (insn), 0, i);
940 if (GET_CODE (set) == SET
941 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
943 /* After the previous loop, this is a no-op if
944 REG is contained within SET_DEST (SET). */
945 mark_ref_live (*use_rec);
952 preprocess_constraints ();
953 process_single_reg_class_operands (false, freq);
955 /* See which defined values die here. */
956 for (def_rec = DF_INSN_DEFS (insn); *def_rec; def_rec++)
957 if (!call_p || !DF_REF_FLAGS_IS_SET (*def_rec, DF_REF_MAY_CLOBBER))
958 mark_ref_dead (*def_rec);
963 /* The current set of live allocnos are live across the call. */
964 EXECUTE_IF_SET_IN_SPARSESET (allocnos_live, i)
966 ira_allocno_t a = ira_allocnos[i];
968 if (allocno_saved_at_call[i] != last_call_num)
969 /* Here we are mimicking caller-save.c behaviour
970 which does not save hard register at a call if
971 it was saved on previous call in the same basic
972 block and the hard register was not mentioned
973 between the two calls. */
974 ALLOCNO_CALL_FREQ (a) += freq;
975 /* Mark it as saved at the next call. */
976 allocno_saved_at_call[i] = last_call_num + 1;
977 ALLOCNO_CALLS_CROSSED_NUM (a)++;
978 /* Don't allocate allocnos that cross setjmps or any
979 call, if this function receives a nonlocal
981 if (cfun->has_nonlocal_label
982 || find_reg_note (insn, REG_SETJMP,
983 NULL_RTX) != NULL_RTX)
985 SET_HARD_REG_SET (ALLOCNO_CONFLICT_HARD_REGS (a));
986 SET_HARD_REG_SET (ALLOCNO_TOTAL_CONFLICT_HARD_REGS (a));
991 make_early_clobber_and_input_conflicts ();
995 /* Mark each used value as live. */
996 for (use_rec = DF_INSN_USES (insn); *use_rec; use_rec++)
997 mark_ref_live (*use_rec);
999 process_single_reg_class_operands (true, freq);
1001 set_p = mark_hard_reg_early_clobbers (insn, true);
1005 mark_hard_reg_early_clobbers (insn, false);
1007 /* Mark each hard reg as live again. For example, a
1008 hard register can be in clobber and in an insn
1010 for (use_rec = DF_INSN_USES (insn); *use_rec; use_rec++)
1012 rtx ureg = DF_REF_REG (*use_rec);
1014 if (GET_CODE (ureg) == SUBREG)
1015 ureg = SUBREG_REG (ureg);
1016 if (! REG_P (ureg) || REGNO (ureg) >= FIRST_PSEUDO_REGISTER)
1019 mark_ref_live (*use_rec);
1026 #ifdef EH_RETURN_DATA_REGNO
1027 if (bb_has_eh_pred (bb))
1030 unsigned int regno = EH_RETURN_DATA_REGNO (j);
1031 if (regno == INVALID_REGNUM)
1033 make_regno_born (regno);
1037 /* Allocnos can't go in stack regs at the start of a basic block
1038 that is reached by an abnormal edge. Likewise for call
1039 clobbered regs, because caller-save, fixup_abnormal_edges and
1040 possibly the table driven EH machinery are not quite ready to
1041 handle such allocnos live across such edges. */
1042 if (bb_has_abnormal_pred (bb))
1045 EXECUTE_IF_SET_IN_SPARSESET (allocnos_live, px)
1047 ALLOCNO_NO_STACK_REG_P (ira_allocnos[px]) = true;
1048 ALLOCNO_TOTAL_NO_STACK_REG_P (ira_allocnos[px]) = true;
1050 for (px = FIRST_STACK_REG; px <= LAST_STACK_REG; px++)
1051 make_regno_born (px);
1053 /* No need to record conflicts for call clobbered regs if we
1054 have nonlocal labels around, as we don't ever try to
1055 allocate such regs in this case. */
1056 if (!cfun->has_nonlocal_label)
1057 for (px = 0; px < FIRST_PSEUDO_REGISTER; px++)
1058 if (call_used_regs[px])
1059 make_regno_born (px);
1062 EXECUTE_IF_SET_IN_SPARSESET (allocnos_live, i)
1064 make_regno_dead (ALLOCNO_REGNO (ira_allocnos[i]));
1070 /* Propagate register pressure to upper loop tree nodes: */
1071 if (loop_tree_node != ira_loop_tree_root)
1072 for (i = 0; i < ira_reg_class_cover_size; i++)
1074 enum reg_class cover_class;
1076 cover_class = ira_reg_class_cover[i];
1077 if (loop_tree_node->reg_pressure[cover_class]
1078 > loop_tree_node->parent->reg_pressure[cover_class])
1079 loop_tree_node->parent->reg_pressure[cover_class]
1080 = loop_tree_node->reg_pressure[cover_class];
1084 /* Create and set up IRA_START_POINT_RANGES and
1085 IRA_FINISH_POINT_RANGES. */
1087 create_start_finish_chains (void)
1090 ira_allocno_iterator ai;
1091 allocno_live_range_t r;
1093 ira_start_point_ranges
1094 = (allocno_live_range_t *) ira_allocate (ira_max_point
1095 * sizeof (allocno_live_range_t));
1096 memset (ira_start_point_ranges, 0,
1097 ira_max_point * sizeof (allocno_live_range_t));
1098 ira_finish_point_ranges
1099 = (allocno_live_range_t *) ira_allocate (ira_max_point
1100 * sizeof (allocno_live_range_t));
1101 memset (ira_finish_point_ranges, 0,
1102 ira_max_point * sizeof (allocno_live_range_t));
1103 FOR_EACH_ALLOCNO (a, ai)
1105 for (r = ALLOCNO_LIVE_RANGES (a); r != NULL; r = r->next)
1107 r->start_next = ira_start_point_ranges[r->start];
1108 ira_start_point_ranges[r->start] = r;
1109 r->finish_next = ira_finish_point_ranges[r->finish];
1110 ira_finish_point_ranges[r->finish] = r;
1115 /* Rebuild IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES after
1116 new live ranges and program points were added as a result if new
1119 ira_rebuild_start_finish_chains (void)
1121 ira_free (ira_finish_point_ranges);
1122 ira_free (ira_start_point_ranges);
1123 create_start_finish_chains ();
1126 /* Compress allocno live ranges by removing program points where
1129 remove_some_program_points_and_update_live_ranges (void)
1135 ira_allocno_iterator ai;
1136 allocno_live_range_t r;
1137 bitmap born_or_died;
1140 born_or_died = ira_allocate_bitmap ();
1141 FOR_EACH_ALLOCNO (a, ai)
1143 for (r = ALLOCNO_LIVE_RANGES (a); r != NULL; r = r->next)
1145 ira_assert (r->start <= r->finish);
1146 bitmap_set_bit (born_or_died, r->start);
1147 bitmap_set_bit (born_or_died, r->finish);
1150 map = (int *) ira_allocate (sizeof (int) * ira_max_point);
1152 EXECUTE_IF_SET_IN_BITMAP(born_or_died, 0, i, bi)
1156 ira_free_bitmap (born_or_died);
1157 if (internal_flag_ira_verbose > 1 && ira_dump_file != NULL)
1158 fprintf (ira_dump_file, "Compressing live ranges: from %d to %d - %d%%\n",
1159 ira_max_point, n, 100 * n / ira_max_point);
1161 FOR_EACH_ALLOCNO (a, ai)
1163 for (r = ALLOCNO_LIVE_RANGES (a); r != NULL; r = r->next)
1165 r->start = map[r->start];
1166 r->finish = map[r->finish];
1172 /* Print live ranges R to file F. */
1174 ira_print_live_range_list (FILE *f, allocno_live_range_t r)
1176 for (; r != NULL; r = r->next)
1177 fprintf (f, " [%d..%d]", r->start, r->finish);
1181 /* Print live ranges R to stderr. */
1183 ira_debug_live_range_list (allocno_live_range_t r)
1185 ira_print_live_range_list (stderr, r);
1188 /* Print live ranges of allocno A to file F. */
1190 print_allocno_live_ranges (FILE *f, ira_allocno_t a)
1192 fprintf (f, " a%d(r%d):", ALLOCNO_NUM (a), ALLOCNO_REGNO (a));
1193 ira_print_live_range_list (f, ALLOCNO_LIVE_RANGES (a));
1196 /* Print live ranges of allocno A to stderr. */
1198 ira_debug_allocno_live_ranges (ira_allocno_t a)
1200 print_allocno_live_ranges (stderr, a);
1203 /* Print live ranges of all allocnos to file F. */
1205 print_live_ranges (FILE *f)
1208 ira_allocno_iterator ai;
1210 FOR_EACH_ALLOCNO (a, ai)
1211 print_allocno_live_ranges (f, a);
1214 /* Print live ranges of all allocnos to stderr. */
1216 ira_debug_live_ranges (void)
1218 print_live_ranges (stderr);
1221 /* The main entry function creates live ranges, set up
1222 CONFLICT_HARD_REGS and TOTAL_CONFLICT_HARD_REGS for allocnos, and
1223 calculate register pressure info. */
1225 ira_create_allocno_live_ranges (void)
1227 allocnos_live = sparseset_alloc (ira_allocnos_num);
1230 allocno_saved_at_call
1231 = (int *) ira_allocate (ira_allocnos_num * sizeof (int));
1232 memset (allocno_saved_at_call, 0, ira_allocnos_num * sizeof (int));
1233 ira_traverse_loop_tree (true, ira_loop_tree_root, NULL,
1234 process_bb_node_lives);
1235 ira_max_point = curr_point;
1236 create_start_finish_chains ();
1237 if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL)
1238 print_live_ranges (ira_dump_file);
1240 ira_free (allocno_saved_at_call);
1241 sparseset_free (allocnos_live);
1244 /* Compress allocno live ranges. */
1246 ira_compress_allocno_live_ranges (void)
1248 remove_some_program_points_and_update_live_ranges ();
1249 ira_rebuild_start_finish_chains ();
1250 if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL)
1252 fprintf (ira_dump_file, "Ranges after the compression:\n");
1253 print_live_ranges (ira_dump_file);
1257 /* Free arrays IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES. */
1259 ira_finish_allocno_live_ranges (void)
1261 ira_free (ira_finish_point_ranges);
1262 ira_free (ira_start_point_ranges);