1 /* Medium-level subroutines: convert bit-field store and extract
2 and shifts, multiplies and divides to rtl instructions.
3 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
4 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
26 #include "coretypes.h"
33 #include "insn-config.h"
38 #include "langhooks.h"
40 static void store_fixed_bit_field (rtx, unsigned HOST_WIDE_INT,
41 unsigned HOST_WIDE_INT,
42 unsigned HOST_WIDE_INT, rtx);
43 static void store_split_bit_field (rtx, unsigned HOST_WIDE_INT,
44 unsigned HOST_WIDE_INT, rtx);
45 static rtx extract_fixed_bit_field (enum machine_mode, rtx,
46 unsigned HOST_WIDE_INT,
47 unsigned HOST_WIDE_INT,
48 unsigned HOST_WIDE_INT, rtx, int);
49 static rtx mask_rtx (enum machine_mode, int, int, int);
50 static rtx lshift_value (enum machine_mode, rtx, int, int);
51 static rtx extract_split_bit_field (rtx, unsigned HOST_WIDE_INT,
52 unsigned HOST_WIDE_INT, int);
53 static void do_cmp_and_jump (rtx, rtx, enum rtx_code, enum machine_mode, rtx);
54 static rtx expand_smod_pow2 (enum machine_mode, rtx, HOST_WIDE_INT);
56 /* Nonzero means divides or modulus operations are relatively cheap for
57 powers of two, so don't use branches; emit the operation instead.
58 Usually, this will mean that the MD file will emit non-branch
61 static int sdiv_pow2_cheap[NUM_MACHINE_MODES];
62 static int smod_pow2_cheap[NUM_MACHINE_MODES];
64 #ifndef SLOW_UNALIGNED_ACCESS
65 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) STRICT_ALIGNMENT
68 /* For compilers that support multiple targets with different word sizes,
69 MAX_BITS_PER_WORD contains the biggest value of BITS_PER_WORD. An example
70 is the H8/300(H) compiler. */
72 #ifndef MAX_BITS_PER_WORD
73 #define MAX_BITS_PER_WORD BITS_PER_WORD
76 /* Reduce conditional compilation elsewhere. */
79 #define CODE_FOR_insv CODE_FOR_nothing
80 #define gen_insv(a,b,c,d) NULL_RTX
84 #define CODE_FOR_extv CODE_FOR_nothing
85 #define gen_extv(a,b,c,d) NULL_RTX
89 #define CODE_FOR_extzv CODE_FOR_nothing
90 #define gen_extzv(a,b,c,d) NULL_RTX
93 /* Cost of various pieces of RTL. Note that some of these are indexed by
94 shift count and some by mode. */
96 static int add_cost[NUM_MACHINE_MODES];
97 static int neg_cost[NUM_MACHINE_MODES];
98 static int shift_cost[NUM_MACHINE_MODES][MAX_BITS_PER_WORD];
99 static int shiftadd_cost[NUM_MACHINE_MODES][MAX_BITS_PER_WORD];
100 static int shiftsub_cost[NUM_MACHINE_MODES][MAX_BITS_PER_WORD];
101 static int mul_cost[NUM_MACHINE_MODES];
102 static int div_cost[NUM_MACHINE_MODES];
103 static int mul_widen_cost[NUM_MACHINE_MODES];
104 static int mul_highpart_cost[NUM_MACHINE_MODES];
109 rtx reg, shift_insn, shiftadd_insn, shiftsub_insn;
110 rtx shift_pat, shiftadd_pat, shiftsub_pat;
111 rtx pow2[MAX_BITS_PER_WORD];
112 rtx cint[MAX_BITS_PER_WORD];
115 enum machine_mode mode, wider_mode;
119 zero_cost = rtx_cost (const0_rtx, 0);
123 for (m = 1; m < MAX_BITS_PER_WORD; m++)
125 pow2[m] = GEN_INT ((HOST_WIDE_INT) 1 << m);
126 cint[m] = GEN_INT (m);
129 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
131 mode = GET_MODE_WIDER_MODE (mode))
133 reg = gen_rtx_REG (mode, 10000);
134 add_cost[mode] = rtx_cost (gen_rtx_PLUS (mode, reg, reg), SET);
135 neg_cost[mode] = rtx_cost (gen_rtx_NEG (mode, reg), SET);
136 div_cost[mode] = rtx_cost (gen_rtx_UDIV (mode, reg, reg), SET);
137 mul_cost[mode] = rtx_cost (gen_rtx_MULT (mode, reg, reg), SET);
139 sdiv_pow2_cheap[mode]
140 = (rtx_cost (gen_rtx_DIV (mode, reg, GEN_INT (32)), SET)
141 <= 2 * add_cost[mode]);
142 smod_pow2_cheap[mode]
143 = (rtx_cost (gen_rtx_MOD (mode, reg, GEN_INT (32)), SET)
144 <= 2 * add_cost[mode]);
146 wider_mode = GET_MODE_WIDER_MODE (mode);
147 if (wider_mode != VOIDmode)
149 mul_widen_cost[wider_mode]
150 = rtx_cost (gen_rtx_MULT (wider_mode,
151 gen_rtx_ZERO_EXTEND (wider_mode, reg),
152 gen_rtx_ZERO_EXTEND (wider_mode, reg)),
154 mul_highpart_cost[mode]
155 = rtx_cost (gen_rtx_TRUNCATE
157 gen_rtx_LSHIFTRT (wider_mode,
158 gen_rtx_MULT (wider_mode,
163 GEN_INT (GET_MODE_BITSIZE (mode)))),
167 shift_insn = emit_insn (gen_rtx_SET (VOIDmode, reg,
168 gen_rtx_ASHIFT (mode, reg,
172 = emit_insn (gen_rtx_SET (VOIDmode, reg,
180 = emit_insn (gen_rtx_SET (VOIDmode, reg,
187 shift_pat = PATTERN (shift_insn);
188 shiftadd_pat = PATTERN (shiftadd_insn);
189 shiftsub_pat = PATTERN (shiftsub_insn);
191 shift_cost[mode][0] = 0;
192 shiftadd_cost[mode][0] = shiftsub_cost[mode][0] = add_cost[mode];
194 n = MIN (MAX_BITS_PER_WORD, GET_MODE_BITSIZE (mode));
195 for (m = 1; m < n; m++)
197 shift_cost[mode][m] = 32000;
198 XEXP (SET_SRC (shift_pat), 1) = cint[m];
199 if (recog (shift_pat, shift_insn, &dummy) >= 0)
200 shift_cost[mode][m] = rtx_cost (SET_SRC (shift_pat), SET);
202 shiftadd_cost[mode][m] = 32000;
203 XEXP (XEXP (SET_SRC (shiftadd_pat), 0), 1) = pow2[m];
204 if (recog (shiftadd_pat, shiftadd_insn, &dummy) >= 0)
205 shiftadd_cost[mode][m] = rtx_cost (SET_SRC (shiftadd_pat), SET);
207 shiftsub_cost[mode][m] = 32000;
208 XEXP (XEXP (SET_SRC (shiftsub_pat), 0), 1) = pow2[m];
209 if (recog (shiftsub_pat, shiftsub_insn, &dummy) >= 0)
210 shiftsub_cost[mode][m] = rtx_cost (SET_SRC (shiftsub_pat), SET);
217 /* Return an rtx representing minus the value of X.
218 MODE is the intended mode of the result,
219 useful if X is a CONST_INT. */
222 negate_rtx (enum machine_mode mode, rtx x)
224 rtx result = simplify_unary_operation (NEG, mode, x, mode);
227 result = expand_unop (mode, neg_optab, x, NULL_RTX, 0);
232 /* Report on the availability of insv/extv/extzv and the desired mode
233 of each of their operands. Returns MAX_MACHINE_MODE if HAVE_foo
234 is false; else the mode of the specified operand. If OPNO is -1,
235 all the caller cares about is whether the insn is available. */
237 mode_for_extraction (enum extraction_pattern pattern, int opno)
239 const struct insn_data *data;
246 data = &insn_data[CODE_FOR_insv];
249 return MAX_MACHINE_MODE;
254 data = &insn_data[CODE_FOR_extv];
257 return MAX_MACHINE_MODE;
262 data = &insn_data[CODE_FOR_extzv];
265 return MAX_MACHINE_MODE;
274 /* Everyone who uses this function used to follow it with
275 if (result == VOIDmode) result = word_mode; */
276 if (data->operand[opno].mode == VOIDmode)
278 return data->operand[opno].mode;
282 /* Generate code to store value from rtx VALUE
283 into a bit-field within structure STR_RTX
284 containing BITSIZE bits starting at bit BITNUM.
285 FIELDMODE is the machine-mode of the FIELD_DECL node for this field.
286 ALIGN is the alignment that STR_RTX is known to have.
287 TOTAL_SIZE is the size of the structure in bytes, or -1 if varying. */
289 /* ??? Note that there are two different ideas here for how
290 to determine the size to count bits within, for a register.
291 One is BITS_PER_WORD, and the other is the size of operand 3
294 If operand 3 of the insv pattern is VOIDmode, then we will use BITS_PER_WORD
295 else, we use the mode of operand 3. */
298 store_bit_field (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
299 unsigned HOST_WIDE_INT bitnum, enum machine_mode fieldmode,
300 rtx value, HOST_WIDE_INT total_size)
303 = (MEM_P (str_rtx)) ? BITS_PER_UNIT : BITS_PER_WORD;
304 unsigned HOST_WIDE_INT offset = bitnum / unit;
305 unsigned HOST_WIDE_INT bitpos = bitnum % unit;
309 enum machine_mode op_mode = mode_for_extraction (EP_insv, 3);
311 /* Discount the part of the structure before the desired byte.
312 We need to know how many bytes are safe to reference after it. */
314 total_size -= (bitpos / BIGGEST_ALIGNMENT
315 * (BIGGEST_ALIGNMENT / BITS_PER_UNIT));
317 while (GET_CODE (op0) == SUBREG)
319 /* The following line once was done only if WORDS_BIG_ENDIAN,
320 but I think that is a mistake. WORDS_BIG_ENDIAN is
321 meaningful at a much higher level; when structures are copied
322 between memory and regs, the higher-numbered regs
323 always get higher addresses. */
324 offset += (SUBREG_BYTE (op0) / UNITS_PER_WORD);
325 /* We used to adjust BITPOS here, but now we do the whole adjustment
326 right after the loop. */
327 op0 = SUBREG_REG (op0);
330 value = protect_from_queue (value, 0);
332 /* Use vec_extract patterns for extracting parts of vectors whenever
334 if (VECTOR_MODE_P (GET_MODE (op0))
336 && (vec_set_optab->handlers[GET_MODE (op0)].insn_code
338 && fieldmode == GET_MODE_INNER (GET_MODE (op0))
339 && bitsize == GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0)))
340 && !(bitnum % GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0)))))
342 enum machine_mode outermode = GET_MODE (op0);
343 enum machine_mode innermode = GET_MODE_INNER (outermode);
344 int icode = (int) vec_set_optab->handlers[outermode].insn_code;
345 int pos = bitnum / GET_MODE_BITSIZE (innermode);
346 rtx rtxpos = GEN_INT (pos);
350 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
351 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
352 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
356 if (! (*insn_data[icode].operand[1].predicate) (src, mode1))
357 src = copy_to_mode_reg (mode1, src);
359 if (! (*insn_data[icode].operand[2].predicate) (rtxpos, mode2))
360 rtxpos = copy_to_mode_reg (mode1, rtxpos);
362 /* We could handle this, but we should always be called with a pseudo
363 for our targets and all insns should take them as outputs. */
364 if (! (*insn_data[icode].operand[0].predicate) (dest, mode0)
365 || ! (*insn_data[icode].operand[1].predicate) (src, mode1)
366 || ! (*insn_data[icode].operand[2].predicate) (rtxpos, mode2))
368 pat = GEN_FCN (icode) (dest, src, rtxpos);
381 int old_generating_concat_p = generating_concat_p;
382 generating_concat_p = 0;
383 value = force_not_mem (value);
384 generating_concat_p = old_generating_concat_p;
387 /* If the target is a register, overwriting the entire object, or storing
388 a full-word or multi-word field can be done with just a SUBREG.
390 If the target is memory, storing any naturally aligned field can be
391 done with a simple store. For targets that support fast unaligned
392 memory, any naturally sized, unit aligned field can be done directly. */
394 byte_offset = (bitnum % BITS_PER_WORD) / BITS_PER_UNIT
395 + (offset * UNITS_PER_WORD);
398 && bitsize == GET_MODE_BITSIZE (fieldmode)
400 ? ((GET_MODE_SIZE (fieldmode) >= UNITS_PER_WORD
401 || GET_MODE_SIZE (GET_MODE (op0)) == GET_MODE_SIZE (fieldmode))
402 && byte_offset % GET_MODE_SIZE (fieldmode) == 0)
403 : (! SLOW_UNALIGNED_ACCESS (fieldmode, MEM_ALIGN (op0))
404 || (offset * BITS_PER_UNIT % bitsize == 0
405 && MEM_ALIGN (op0) % GET_MODE_BITSIZE (fieldmode) == 0))))
407 if (GET_MODE (op0) != fieldmode)
409 if (GET_CODE (op0) == SUBREG)
411 if (GET_MODE (SUBREG_REG (op0)) == fieldmode
412 || GET_MODE_CLASS (fieldmode) == MODE_INT
413 || GET_MODE_CLASS (fieldmode) == MODE_PARTIAL_INT)
414 op0 = SUBREG_REG (op0);
416 /* Else we've got some float mode source being extracted into
417 a different float mode destination -- this combination of
418 subregs results in Severe Tire Damage. */
422 op0 = gen_rtx_SUBREG (fieldmode, op0, byte_offset);
424 op0 = adjust_address (op0, fieldmode, offset);
426 emit_move_insn (op0, value);
430 /* Make sure we are playing with integral modes. Pun with subregs
431 if we aren't. This must come after the entire register case above,
432 since that case is valid for any mode. The following cases are only
433 valid for integral modes. */
435 enum machine_mode imode = int_mode_for_mode (GET_MODE (op0));
436 if (imode != GET_MODE (op0))
439 op0 = adjust_address (op0, imode, 0);
440 else if (imode != BLKmode)
441 op0 = gen_lowpart (imode, op0);
447 /* We may be accessing data outside the field, which means
448 we can alias adjacent data. */
451 op0 = shallow_copy_rtx (op0);
452 set_mem_alias_set (op0, 0);
453 set_mem_expr (op0, 0);
456 /* If OP0 is a register, BITPOS must count within a word.
457 But as we have it, it counts within whatever size OP0 now has.
458 On a bigendian machine, these are not the same, so convert. */
461 && unit > GET_MODE_BITSIZE (GET_MODE (op0)))
462 bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0));
464 /* Storing an lsb-aligned field in a register
465 can be done with a movestrict instruction. */
468 && (BYTES_BIG_ENDIAN ? bitpos + bitsize == unit : bitpos == 0)
469 && bitsize == GET_MODE_BITSIZE (fieldmode)
470 && (movstrict_optab->handlers[fieldmode].insn_code
471 != CODE_FOR_nothing))
473 int icode = movstrict_optab->handlers[fieldmode].insn_code;
475 /* Get appropriate low part of the value being stored. */
476 if (GET_CODE (value) == CONST_INT || REG_P (value))
477 value = gen_lowpart (fieldmode, value);
478 else if (!(GET_CODE (value) == SYMBOL_REF
479 || GET_CODE (value) == LABEL_REF
480 || GET_CODE (value) == CONST))
481 value = convert_to_mode (fieldmode, value, 0);
483 if (! (*insn_data[icode].operand[1].predicate) (value, fieldmode))
484 value = copy_to_mode_reg (fieldmode, value);
486 if (GET_CODE (op0) == SUBREG)
488 if (GET_MODE (SUBREG_REG (op0)) == fieldmode
489 || GET_MODE_CLASS (fieldmode) == MODE_INT
490 || GET_MODE_CLASS (fieldmode) == MODE_PARTIAL_INT)
491 op0 = SUBREG_REG (op0);
493 /* Else we've got some float mode source being extracted into
494 a different float mode destination -- this combination of
495 subregs results in Severe Tire Damage. */
499 emit_insn (GEN_FCN (icode)
500 (gen_rtx_SUBREG (fieldmode, op0,
501 (bitnum % BITS_PER_WORD) / BITS_PER_UNIT
502 + (offset * UNITS_PER_WORD)),
508 /* Handle fields bigger than a word. */
510 if (bitsize > BITS_PER_WORD)
512 /* Here we transfer the words of the field
513 in the order least significant first.
514 This is because the most significant word is the one which may
516 However, only do that if the value is not BLKmode. */
518 unsigned int backwards = WORDS_BIG_ENDIAN && fieldmode != BLKmode;
519 unsigned int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD;
522 /* This is the mode we must force value to, so that there will be enough
523 subwords to extract. Note that fieldmode will often (always?) be
524 VOIDmode, because that is what store_field uses to indicate that this
525 is a bit field, but passing VOIDmode to operand_subword_force will
526 result in an abort. */
527 fieldmode = GET_MODE (value);
528 if (fieldmode == VOIDmode)
529 fieldmode = smallest_mode_for_size (nwords * BITS_PER_WORD, MODE_INT);
531 for (i = 0; i < nwords; i++)
533 /* If I is 0, use the low-order word in both field and target;
534 if I is 1, use the next to lowest word; and so on. */
535 unsigned int wordnum = (backwards ? nwords - i - 1 : i);
536 unsigned int bit_offset = (backwards
537 ? MAX ((int) bitsize - ((int) i + 1)
540 : (int) i * BITS_PER_WORD);
542 store_bit_field (op0, MIN (BITS_PER_WORD,
543 bitsize - i * BITS_PER_WORD),
544 bitnum + bit_offset, word_mode,
545 operand_subword_force (value, wordnum, fieldmode),
551 /* From here on we can assume that the field to be stored in is
552 a full-word (whatever type that is), since it is shorter than a word. */
554 /* OFFSET is the number of words or bytes (UNIT says which)
555 from STR_RTX to the first word or byte containing part of the field. */
560 || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD)
564 /* Since this is a destination (lvalue), we can't copy it to a
565 pseudo. We can trivially remove a SUBREG that does not
566 change the size of the operand. Such a SUBREG may have been
567 added above. Otherwise, abort. */
568 if (GET_CODE (op0) == SUBREG
569 && (GET_MODE_SIZE (GET_MODE (op0))
570 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0)))))
571 op0 = SUBREG_REG (op0);
575 op0 = gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD, MODE_INT, 0),
576 op0, (offset * UNITS_PER_WORD));
581 op0 = protect_from_queue (op0, 1);
583 /* If VALUE is a floating-point mode, access it as an integer of the
584 corresponding size. This can occur on a machine with 64 bit registers
585 that uses SFmode for float. This can also occur for unaligned float
587 if (GET_MODE_CLASS (GET_MODE (value)) != MODE_INT
588 && GET_MODE_CLASS (GET_MODE (value)) != MODE_PARTIAL_INT)
589 value = gen_lowpart ((GET_MODE (value) == VOIDmode
590 ? word_mode : int_mode_for_mode (GET_MODE (value))),
593 /* Now OFFSET is nonzero only if OP0 is memory
594 and is therefore always measured in bytes. */
597 && GET_MODE (value) != BLKmode
598 && !(bitsize == 1 && GET_CODE (value) == CONST_INT)
599 /* Ensure insv's size is wide enough for this field. */
600 && (GET_MODE_BITSIZE (op_mode) >= bitsize)
601 && ! ((REG_P (op0) || GET_CODE (op0) == SUBREG)
602 && (bitsize + bitpos > GET_MODE_BITSIZE (op_mode))))
604 int xbitpos = bitpos;
607 rtx last = get_last_insn ();
609 enum machine_mode maxmode = mode_for_extraction (EP_insv, 3);
610 int save_volatile_ok = volatile_ok;
614 /* If this machine's insv can only insert into a register, copy OP0
615 into a register and save it back later. */
616 /* This used to check flag_force_mem, but that was a serious
617 de-optimization now that flag_force_mem is enabled by -O2. */
619 && ! ((*insn_data[(int) CODE_FOR_insv].operand[0].predicate)
623 enum machine_mode bestmode;
625 /* Get the mode to use for inserting into this field. If OP0 is
626 BLKmode, get the smallest mode consistent with the alignment. If
627 OP0 is a non-BLKmode object that is no wider than MAXMODE, use its
628 mode. Otherwise, use the smallest mode containing the field. */
630 if (GET_MODE (op0) == BLKmode
631 || GET_MODE_SIZE (GET_MODE (op0)) > GET_MODE_SIZE (maxmode))
633 = get_best_mode (bitsize, bitnum, MEM_ALIGN (op0), maxmode,
634 MEM_VOLATILE_P (op0));
636 bestmode = GET_MODE (op0);
638 if (bestmode == VOIDmode
639 || (SLOW_UNALIGNED_ACCESS (bestmode, MEM_ALIGN (op0))
640 && GET_MODE_BITSIZE (bestmode) > MEM_ALIGN (op0)))
643 /* Adjust address to point to the containing unit of that mode.
644 Compute offset as multiple of this unit, counting in bytes. */
645 unit = GET_MODE_BITSIZE (bestmode);
646 offset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
647 bitpos = bitnum % unit;
648 op0 = adjust_address (op0, bestmode, offset);
650 /* Fetch that unit, store the bitfield in it, then store
652 tempreg = copy_to_reg (op0);
653 store_bit_field (tempreg, bitsize, bitpos, fieldmode, value,
655 emit_move_insn (op0, tempreg);
658 volatile_ok = save_volatile_ok;
660 /* Add OFFSET into OP0's address. */
662 xop0 = adjust_address (xop0, byte_mode, offset);
664 /* If xop0 is a register, we need it in MAXMODE
665 to make it acceptable to the format of insv. */
666 if (GET_CODE (xop0) == SUBREG)
667 /* We can't just change the mode, because this might clobber op0,
668 and we will need the original value of op0 if insv fails. */
669 xop0 = gen_rtx_SUBREG (maxmode, SUBREG_REG (xop0), SUBREG_BYTE (xop0));
670 if (REG_P (xop0) && GET_MODE (xop0) != maxmode)
671 xop0 = gen_rtx_SUBREG (maxmode, xop0, 0);
673 /* On big-endian machines, we count bits from the most significant.
674 If the bit field insn does not, we must invert. */
676 if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
677 xbitpos = unit - bitsize - xbitpos;
679 /* We have been counting XBITPOS within UNIT.
680 Count instead within the size of the register. */
681 if (BITS_BIG_ENDIAN && !MEM_P (xop0))
682 xbitpos += GET_MODE_BITSIZE (maxmode) - unit;
684 unit = GET_MODE_BITSIZE (maxmode);
686 /* Convert VALUE to maxmode (which insv insn wants) in VALUE1. */
688 if (GET_MODE (value) != maxmode)
690 if (GET_MODE_BITSIZE (GET_MODE (value)) >= bitsize)
692 /* Optimization: Don't bother really extending VALUE
693 if it has all the bits we will actually use. However,
694 if we must narrow it, be sure we do it correctly. */
696 if (GET_MODE_SIZE (GET_MODE (value)) < GET_MODE_SIZE (maxmode))
700 tmp = simplify_subreg (maxmode, value1, GET_MODE (value), 0);
702 tmp = simplify_gen_subreg (maxmode,
703 force_reg (GET_MODE (value),
705 GET_MODE (value), 0);
709 value1 = gen_lowpart (maxmode, value1);
711 else if (GET_CODE (value) == CONST_INT)
712 value1 = gen_int_mode (INTVAL (value), maxmode);
713 else if (!CONSTANT_P (value))
714 /* Parse phase is supposed to make VALUE's data type
715 match that of the component reference, which is a type
716 at least as wide as the field; so VALUE should have
717 a mode that corresponds to that type. */
721 /* If this machine's insv insists on a register,
722 get VALUE1 into a register. */
723 if (! ((*insn_data[(int) CODE_FOR_insv].operand[3].predicate)
725 value1 = force_reg (maxmode, value1);
727 pat = gen_insv (xop0, GEN_INT (bitsize), GEN_INT (xbitpos), value1);
732 delete_insns_since (last);
733 store_fixed_bit_field (op0, offset, bitsize, bitpos, value);
738 /* Insv is not available; store using shifts and boolean ops. */
739 store_fixed_bit_field (op0, offset, bitsize, bitpos, value);
743 /* Use shifts and boolean operations to store VALUE
744 into a bit field of width BITSIZE
745 in a memory location specified by OP0 except offset by OFFSET bytes.
746 (OFFSET must be 0 if OP0 is a register.)
747 The field starts at position BITPOS within the byte.
748 (If OP0 is a register, it may be a full word or a narrower mode,
749 but BITPOS still counts within a full word,
750 which is significant on bigendian machines.)
752 Note that protect_from_queue has already been done on OP0 and VALUE. */
755 store_fixed_bit_field (rtx op0, unsigned HOST_WIDE_INT offset,
756 unsigned HOST_WIDE_INT bitsize,
757 unsigned HOST_WIDE_INT bitpos, rtx value)
759 enum machine_mode mode;
760 unsigned int total_bits = BITS_PER_WORD;
765 /* There is a case not handled here:
766 a structure with a known alignment of just a halfword
767 and a field split across two aligned halfwords within the structure.
768 Or likewise a structure with a known alignment of just a byte
769 and a field split across two bytes.
770 Such cases are not supposed to be able to occur. */
772 if (REG_P (op0) || GET_CODE (op0) == SUBREG)
776 /* Special treatment for a bit field split across two registers. */
777 if (bitsize + bitpos > BITS_PER_WORD)
779 store_split_bit_field (op0, bitsize, bitpos, value);
785 /* Get the proper mode to use for this field. We want a mode that
786 includes the entire field. If such a mode would be larger than
787 a word, we won't be doing the extraction the normal way.
788 We don't want a mode bigger than the destination. */
790 mode = GET_MODE (op0);
791 if (GET_MODE_BITSIZE (mode) == 0
792 || GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (word_mode))
794 mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT,
795 MEM_ALIGN (op0), mode, MEM_VOLATILE_P (op0));
797 if (mode == VOIDmode)
799 /* The only way this should occur is if the field spans word
801 store_split_bit_field (op0, bitsize, bitpos + offset * BITS_PER_UNIT,
806 total_bits = GET_MODE_BITSIZE (mode);
808 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
809 be in the range 0 to total_bits-1, and put any excess bytes in
811 if (bitpos >= total_bits)
813 offset += (bitpos / total_bits) * (total_bits / BITS_PER_UNIT);
814 bitpos -= ((bitpos / total_bits) * (total_bits / BITS_PER_UNIT)
818 /* Get ref to an aligned byte, halfword, or word containing the field.
819 Adjust BITPOS to be position within a word,
820 and OFFSET to be the offset of that word.
821 Then alter OP0 to refer to that word. */
822 bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT;
823 offset -= (offset % (total_bits / BITS_PER_UNIT));
824 op0 = adjust_address (op0, mode, offset);
827 mode = GET_MODE (op0);
829 /* Now MODE is either some integral mode for a MEM as OP0,
830 or is a full-word for a REG as OP0. TOTAL_BITS corresponds.
831 The bit field is contained entirely within OP0.
832 BITPOS is the starting bit number within OP0.
833 (OP0's mode may actually be narrower than MODE.) */
835 if (BYTES_BIG_ENDIAN)
836 /* BITPOS is the distance between our msb
837 and that of the containing datum.
838 Convert it to the distance from the lsb. */
839 bitpos = total_bits - bitsize - bitpos;
841 /* Now BITPOS is always the distance between our lsb
844 /* Shift VALUE left by BITPOS bits. If VALUE is not constant,
845 we must first convert its mode to MODE. */
847 if (GET_CODE (value) == CONST_INT)
849 HOST_WIDE_INT v = INTVAL (value);
851 if (bitsize < HOST_BITS_PER_WIDE_INT)
852 v &= ((HOST_WIDE_INT) 1 << bitsize) - 1;
856 else if ((bitsize < HOST_BITS_PER_WIDE_INT
857 && v == ((HOST_WIDE_INT) 1 << bitsize) - 1)
858 || (bitsize == HOST_BITS_PER_WIDE_INT && v == -1))
861 value = lshift_value (mode, value, bitpos, bitsize);
865 int must_and = (GET_MODE_BITSIZE (GET_MODE (value)) != bitsize
866 && bitpos + bitsize != GET_MODE_BITSIZE (mode));
868 if (GET_MODE (value) != mode)
870 if ((REG_P (value) || GET_CODE (value) == SUBREG)
871 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (value)))
872 value = gen_lowpart (mode, value);
874 value = convert_to_mode (mode, value, 1);
878 value = expand_binop (mode, and_optab, value,
879 mask_rtx (mode, 0, bitsize, 0),
880 NULL_RTX, 1, OPTAB_LIB_WIDEN);
882 value = expand_shift (LSHIFT_EXPR, mode, value,
883 build_int_2 (bitpos, 0), NULL_RTX, 1);
886 /* Now clear the chosen bits in OP0,
887 except that if VALUE is -1 we need not bother. */
889 subtarget = (REG_P (op0) || ! flag_force_mem) ? op0 : 0;
893 temp = expand_binop (mode, and_optab, op0,
894 mask_rtx (mode, bitpos, bitsize, 1),
895 subtarget, 1, OPTAB_LIB_WIDEN);
901 /* Now logical-or VALUE into OP0, unless it is zero. */
904 temp = expand_binop (mode, ior_optab, temp, value,
905 subtarget, 1, OPTAB_LIB_WIDEN);
907 emit_move_insn (op0, temp);
910 /* Store a bit field that is split across multiple accessible memory objects.
912 OP0 is the REG, SUBREG or MEM rtx for the first of the objects.
913 BITSIZE is the field width; BITPOS the position of its first bit
915 VALUE is the value to store.
917 This does not yet handle fields wider than BITS_PER_WORD. */
920 store_split_bit_field (rtx op0, unsigned HOST_WIDE_INT bitsize,
921 unsigned HOST_WIDE_INT bitpos, rtx value)
924 unsigned int bitsdone = 0;
926 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
928 if (REG_P (op0) || GET_CODE (op0) == SUBREG)
929 unit = BITS_PER_WORD;
931 unit = MIN (MEM_ALIGN (op0), BITS_PER_WORD);
933 /* If VALUE is a constant other than a CONST_INT, get it into a register in
934 WORD_MODE. If we can do this using gen_lowpart_common, do so. Note
935 that VALUE might be a floating-point constant. */
936 if (CONSTANT_P (value) && GET_CODE (value) != CONST_INT)
938 rtx word = gen_lowpart_common (word_mode, value);
940 if (word && (value != word))
943 value = gen_lowpart_common (word_mode,
944 force_reg (GET_MODE (value) != VOIDmode
946 : word_mode, value));
948 else if (GET_CODE (value) == ADDRESSOF)
949 value = copy_to_reg (value);
951 while (bitsdone < bitsize)
953 unsigned HOST_WIDE_INT thissize;
955 unsigned HOST_WIDE_INT thispos;
956 unsigned HOST_WIDE_INT offset;
958 offset = (bitpos + bitsdone) / unit;
959 thispos = (bitpos + bitsdone) % unit;
961 /* THISSIZE must not overrun a word boundary. Otherwise,
962 store_fixed_bit_field will call us again, and we will mutually
964 thissize = MIN (bitsize - bitsdone, BITS_PER_WORD);
965 thissize = MIN (thissize, unit - thispos);
967 if (BYTES_BIG_ENDIAN)
971 /* We must do an endian conversion exactly the same way as it is
972 done in extract_bit_field, so that the two calls to
973 extract_fixed_bit_field will have comparable arguments. */
974 if (!MEM_P (value) || GET_MODE (value) == BLKmode)
975 total_bits = BITS_PER_WORD;
977 total_bits = GET_MODE_BITSIZE (GET_MODE (value));
979 /* Fetch successively less significant portions. */
980 if (GET_CODE (value) == CONST_INT)
981 part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value))
982 >> (bitsize - bitsdone - thissize))
983 & (((HOST_WIDE_INT) 1 << thissize) - 1));
985 /* The args are chosen so that the last part includes the
986 lsb. Give extract_bit_field the value it needs (with
987 endianness compensation) to fetch the piece we want. */
988 part = extract_fixed_bit_field (word_mode, value, 0, thissize,
989 total_bits - bitsize + bitsdone,
994 /* Fetch successively more significant portions. */
995 if (GET_CODE (value) == CONST_INT)
996 part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value))
998 & (((HOST_WIDE_INT) 1 << thissize) - 1));
1000 part = extract_fixed_bit_field (word_mode, value, 0, thissize,
1001 bitsdone, NULL_RTX, 1);
1004 /* If OP0 is a register, then handle OFFSET here.
1006 When handling multiword bitfields, extract_bit_field may pass
1007 down a word_mode SUBREG of a larger REG for a bitfield that actually
1008 crosses a word boundary. Thus, for a SUBREG, we must find
1009 the current word starting from the base register. */
1010 if (GET_CODE (op0) == SUBREG)
1012 int word_offset = (SUBREG_BYTE (op0) / UNITS_PER_WORD) + offset;
1013 word = operand_subword_force (SUBREG_REG (op0), word_offset,
1014 GET_MODE (SUBREG_REG (op0)));
1017 else if (REG_P (op0))
1019 word = operand_subword_force (op0, offset, GET_MODE (op0));
1025 /* OFFSET is in UNITs, and UNIT is in bits.
1026 store_fixed_bit_field wants offset in bytes. */
1027 store_fixed_bit_field (word, offset * unit / BITS_PER_UNIT, thissize,
1029 bitsdone += thissize;
1033 /* Generate code to extract a byte-field from STR_RTX
1034 containing BITSIZE bits, starting at BITNUM,
1035 and put it in TARGET if possible (if TARGET is nonzero).
1036 Regardless of TARGET, we return the rtx for where the value is placed.
1039 STR_RTX is the structure containing the byte (a REG or MEM).
1040 UNSIGNEDP is nonzero if this is an unsigned bit field.
1041 MODE is the natural mode of the field value once extracted.
1042 TMODE is the mode the caller would like the value to have;
1043 but the value may be returned with type MODE instead.
1045 TOTAL_SIZE is the size in bytes of the containing structure,
1048 If a TARGET is specified and we can store in it at no extra cost,
1049 we do so, and return TARGET.
1050 Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
1051 if they are equally easy. */
1054 extract_bit_field (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
1055 unsigned HOST_WIDE_INT bitnum, int unsignedp, rtx target,
1056 enum machine_mode mode, enum machine_mode tmode,
1057 HOST_WIDE_INT total_size)
1060 = (MEM_P (str_rtx)) ? BITS_PER_UNIT : BITS_PER_WORD;
1061 unsigned HOST_WIDE_INT offset = bitnum / unit;
1062 unsigned HOST_WIDE_INT bitpos = bitnum % unit;
1064 rtx spec_target = target;
1065 rtx spec_target_subreg = 0;
1066 enum machine_mode int_mode;
1067 enum machine_mode extv_mode = mode_for_extraction (EP_extv, 0);
1068 enum machine_mode extzv_mode = mode_for_extraction (EP_extzv, 0);
1069 enum machine_mode mode1;
1072 /* Discount the part of the structure before the desired byte.
1073 We need to know how many bytes are safe to reference after it. */
1074 if (total_size >= 0)
1075 total_size -= (bitpos / BIGGEST_ALIGNMENT
1076 * (BIGGEST_ALIGNMENT / BITS_PER_UNIT));
1078 if (tmode == VOIDmode)
1081 while (GET_CODE (op0) == SUBREG)
1083 bitpos += SUBREG_BYTE (op0) * BITS_PER_UNIT;
1086 offset += (bitpos / unit);
1089 op0 = SUBREG_REG (op0);
1093 && mode == GET_MODE (op0)
1095 && bitsize == GET_MODE_BITSIZE (GET_MODE (op0)))
1097 /* We're trying to extract a full register from itself. */
1101 /* Use vec_extract patterns for extracting parts of vectors whenever
1103 if (VECTOR_MODE_P (GET_MODE (op0))
1105 && (vec_extract_optab->handlers[GET_MODE (op0)].insn_code
1106 != CODE_FOR_nothing)
1107 && ((bitsize + bitnum) / GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0)))
1108 == bitsize / GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0)))))
1110 enum machine_mode outermode = GET_MODE (op0);
1111 enum machine_mode innermode = GET_MODE_INNER (outermode);
1112 int icode = (int) vec_extract_optab->handlers[outermode].insn_code;
1113 int pos = bitnum / GET_MODE_BITSIZE (innermode);
1114 rtx rtxpos = GEN_INT (pos);
1116 rtx dest = NULL, pat, seq;
1117 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
1118 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
1119 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
1121 if (innermode == tmode || innermode == mode)
1125 dest = gen_reg_rtx (innermode);
1129 if (! (*insn_data[icode].operand[0].predicate) (dest, mode0))
1130 dest = copy_to_mode_reg (mode0, dest);
1132 if (! (*insn_data[icode].operand[1].predicate) (src, mode1))
1133 src = copy_to_mode_reg (mode1, src);
1135 if (! (*insn_data[icode].operand[2].predicate) (rtxpos, mode2))
1136 rtxpos = copy_to_mode_reg (mode1, rtxpos);
1138 /* We could handle this, but we should always be called with a pseudo
1139 for our targets and all insns should take them as outputs. */
1140 if (! (*insn_data[icode].operand[0].predicate) (dest, mode0)
1141 || ! (*insn_data[icode].operand[1].predicate) (src, mode1)
1142 || ! (*insn_data[icode].operand[2].predicate) (rtxpos, mode2))
1145 pat = GEN_FCN (icode) (dest, src, rtxpos);
1156 /* Make sure we are playing with integral modes. Pun with subregs
1159 enum machine_mode imode = int_mode_for_mode (GET_MODE (op0));
1160 if (imode != GET_MODE (op0))
1163 op0 = adjust_address (op0, imode, 0);
1164 else if (imode != BLKmode)
1165 op0 = gen_lowpart (imode, op0);
1171 /* We may be accessing data outside the field, which means
1172 we can alias adjacent data. */
1175 op0 = shallow_copy_rtx (op0);
1176 set_mem_alias_set (op0, 0);
1177 set_mem_expr (op0, 0);
1180 /* Extraction of a full-word or multi-word value from a structure
1181 in a register or aligned memory can be done with just a SUBREG.
1182 A subword value in the least significant part of a register
1183 can also be extracted with a SUBREG. For this, we need the
1184 byte offset of the value in op0. */
1186 byte_offset = bitpos / BITS_PER_UNIT + offset * UNITS_PER_WORD;
1188 /* If OP0 is a register, BITPOS must count within a word.
1189 But as we have it, it counts within whatever size OP0 now has.
1190 On a bigendian machine, these are not the same, so convert. */
1191 if (BYTES_BIG_ENDIAN
1193 && unit > GET_MODE_BITSIZE (GET_MODE (op0)))
1194 bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0));
1196 /* ??? We currently assume TARGET is at least as big as BITSIZE.
1197 If that's wrong, the solution is to test for it and set TARGET to 0
1200 /* Only scalar integer modes can be converted via subregs. There is an
1201 additional problem for FP modes here in that they can have a precision
1202 which is different from the size. mode_for_size uses precision, but
1203 we want a mode based on the size, so we must avoid calling it for FP
1205 mode1 = (SCALAR_INT_MODE_P (tmode)
1206 ? mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0)
1209 if (((bitsize >= BITS_PER_WORD && bitsize == GET_MODE_BITSIZE (mode)
1210 && bitpos % BITS_PER_WORD == 0)
1211 || (mode1 != BLKmode
1212 /* ??? The big endian test here is wrong. This is correct
1213 if the value is in a register, and if mode_for_size is not
1214 the same mode as op0. This causes us to get unnecessarily
1215 inefficient code from the Thumb port when -mbig-endian. */
1216 && (BYTES_BIG_ENDIAN
1217 ? bitpos + bitsize == BITS_PER_WORD
1220 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
1221 GET_MODE_BITSIZE (GET_MODE (op0)))
1222 && GET_MODE_SIZE (mode1) != 0
1223 && byte_offset % GET_MODE_SIZE (mode1) == 0)
1225 && (! SLOW_UNALIGNED_ACCESS (mode, MEM_ALIGN (op0))
1226 || (offset * BITS_PER_UNIT % bitsize == 0
1227 && MEM_ALIGN (op0) % bitsize == 0)))))
1229 if (mode1 != GET_MODE (op0))
1231 if (GET_CODE (op0) == SUBREG)
1233 if (GET_MODE (SUBREG_REG (op0)) == mode1
1234 || GET_MODE_CLASS (mode1) == MODE_INT
1235 || GET_MODE_CLASS (mode1) == MODE_PARTIAL_INT)
1236 op0 = SUBREG_REG (op0);
1238 /* Else we've got some float mode source being extracted into
1239 a different float mode destination -- this combination of
1240 subregs results in Severe Tire Damage. */
1241 goto no_subreg_mode_swap;
1244 op0 = gen_rtx_SUBREG (mode1, op0, byte_offset);
1246 op0 = adjust_address (op0, mode1, offset);
1249 return convert_to_mode (tmode, op0, unsignedp);
1252 no_subreg_mode_swap:
1254 /* Handle fields bigger than a word. */
1256 if (bitsize > BITS_PER_WORD)
1258 /* Here we transfer the words of the field
1259 in the order least significant first.
1260 This is because the most significant word is the one which may
1261 be less than full. */
1263 unsigned int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD;
1266 if (target == 0 || !REG_P (target))
1267 target = gen_reg_rtx (mode);
1269 /* Indicate for flow that the entire target reg is being set. */
1270 emit_insn (gen_rtx_CLOBBER (VOIDmode, target));
1272 for (i = 0; i < nwords; i++)
1274 /* If I is 0, use the low-order word in both field and target;
1275 if I is 1, use the next to lowest word; and so on. */
1276 /* Word number in TARGET to use. */
1277 unsigned int wordnum
1279 ? GET_MODE_SIZE (GET_MODE (target)) / UNITS_PER_WORD - i - 1
1281 /* Offset from start of field in OP0. */
1282 unsigned int bit_offset = (WORDS_BIG_ENDIAN
1283 ? MAX (0, ((int) bitsize - ((int) i + 1)
1284 * (int) BITS_PER_WORD))
1285 : (int) i * BITS_PER_WORD);
1286 rtx target_part = operand_subword (target, wordnum, 1, VOIDmode);
1288 = extract_bit_field (op0, MIN (BITS_PER_WORD,
1289 bitsize - i * BITS_PER_WORD),
1290 bitnum + bit_offset, 1, target_part, mode,
1291 word_mode, total_size);
1293 if (target_part == 0)
1296 if (result_part != target_part)
1297 emit_move_insn (target_part, result_part);
1302 /* Unless we've filled TARGET, the upper regs in a multi-reg value
1303 need to be zero'd out. */
1304 if (GET_MODE_SIZE (GET_MODE (target)) > nwords * UNITS_PER_WORD)
1306 unsigned int i, total_words;
1308 total_words = GET_MODE_SIZE (GET_MODE (target)) / UNITS_PER_WORD;
1309 for (i = nwords; i < total_words; i++)
1311 (operand_subword (target,
1312 WORDS_BIG_ENDIAN ? total_words - i - 1 : i,
1319 /* Signed bit field: sign-extend with two arithmetic shifts. */
1320 target = expand_shift (LSHIFT_EXPR, mode, target,
1321 build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0),
1323 return expand_shift (RSHIFT_EXPR, mode, target,
1324 build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0),
1328 /* From here on we know the desired field is smaller than a word. */
1330 /* Check if there is a correspondingly-sized integer field, so we can
1331 safely extract it as one size of integer, if necessary; then
1332 truncate or extend to the size that is wanted; then use SUBREGs or
1333 convert_to_mode to get one of the modes we really wanted. */
1335 int_mode = int_mode_for_mode (tmode);
1336 if (int_mode == BLKmode)
1337 int_mode = int_mode_for_mode (mode);
1338 if (int_mode == BLKmode)
1339 abort (); /* Should probably push op0 out to memory and then
1342 /* OFFSET is the number of words or bytes (UNIT says which)
1343 from STR_RTX to the first word or byte containing part of the field. */
1348 || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD)
1351 op0 = copy_to_reg (op0);
1352 op0 = gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD, MODE_INT, 0),
1353 op0, (offset * UNITS_PER_WORD));
1358 op0 = protect_from_queue (str_rtx, 1);
1360 /* Now OFFSET is nonzero only for memory operands. */
1365 && (GET_MODE_BITSIZE (extzv_mode) >= bitsize)
1366 && ! ((REG_P (op0) || GET_CODE (op0) == SUBREG)
1367 && (bitsize + bitpos > GET_MODE_BITSIZE (extzv_mode))))
1369 unsigned HOST_WIDE_INT xbitpos = bitpos, xoffset = offset;
1370 rtx bitsize_rtx, bitpos_rtx;
1371 rtx last = get_last_insn ();
1373 rtx xtarget = target;
1374 rtx xspec_target = spec_target;
1375 rtx xspec_target_subreg = spec_target_subreg;
1377 enum machine_mode maxmode = mode_for_extraction (EP_extzv, 0);
1381 int save_volatile_ok = volatile_ok;
1384 /* Is the memory operand acceptable? */
1385 if (! ((*insn_data[(int) CODE_FOR_extzv].operand[1].predicate)
1386 (xop0, GET_MODE (xop0))))
1388 /* No, load into a reg and extract from there. */
1389 enum machine_mode bestmode;
1391 /* Get the mode to use for inserting into this field. If
1392 OP0 is BLKmode, get the smallest mode consistent with the
1393 alignment. If OP0 is a non-BLKmode object that is no
1394 wider than MAXMODE, use its mode. Otherwise, use the
1395 smallest mode containing the field. */
1397 if (GET_MODE (xop0) == BLKmode
1398 || (GET_MODE_SIZE (GET_MODE (op0))
1399 > GET_MODE_SIZE (maxmode)))
1400 bestmode = get_best_mode (bitsize, bitnum,
1401 MEM_ALIGN (xop0), maxmode,
1402 MEM_VOLATILE_P (xop0));
1404 bestmode = GET_MODE (xop0);
1406 if (bestmode == VOIDmode
1407 || (SLOW_UNALIGNED_ACCESS (bestmode, MEM_ALIGN (xop0))
1408 && GET_MODE_BITSIZE (bestmode) > MEM_ALIGN (xop0)))
1411 /* Compute offset as multiple of this unit,
1412 counting in bytes. */
1413 unit = GET_MODE_BITSIZE (bestmode);
1414 xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
1415 xbitpos = bitnum % unit;
1416 xop0 = adjust_address (xop0, bestmode, xoffset);
1418 /* Fetch it to a register in that size. */
1419 xop0 = force_reg (bestmode, xop0);
1421 /* XBITPOS counts within UNIT, which is what is expected. */
1424 /* Get ref to first byte containing part of the field. */
1425 xop0 = adjust_address (xop0, byte_mode, xoffset);
1427 volatile_ok = save_volatile_ok;
1430 /* If op0 is a register, we need it in MAXMODE (which is usually
1431 SImode). to make it acceptable to the format of extzv. */
1432 if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode)
1434 if (REG_P (xop0) && GET_MODE (xop0) != maxmode)
1435 xop0 = gen_rtx_SUBREG (maxmode, xop0, 0);
1437 /* On big-endian machines, we count bits from the most significant.
1438 If the bit field insn does not, we must invert. */
1439 if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
1440 xbitpos = unit - bitsize - xbitpos;
1442 /* Now convert from counting within UNIT to counting in MAXMODE. */
1443 if (BITS_BIG_ENDIAN && !MEM_P (xop0))
1444 xbitpos += GET_MODE_BITSIZE (maxmode) - unit;
1446 unit = GET_MODE_BITSIZE (maxmode);
1449 || (flag_force_mem && MEM_P (xtarget)))
1450 xtarget = xspec_target = gen_reg_rtx (tmode);
1452 if (GET_MODE (xtarget) != maxmode)
1454 if (REG_P (xtarget))
1456 int wider = (GET_MODE_SIZE (maxmode)
1457 > GET_MODE_SIZE (GET_MODE (xtarget)));
1458 xtarget = gen_lowpart (maxmode, xtarget);
1460 xspec_target_subreg = xtarget;
1463 xtarget = gen_reg_rtx (maxmode);
1466 /* If this machine's extzv insists on a register target,
1467 make sure we have one. */
1468 if (! ((*insn_data[(int) CODE_FOR_extzv].operand[0].predicate)
1469 (xtarget, maxmode)))
1470 xtarget = gen_reg_rtx (maxmode);
1472 bitsize_rtx = GEN_INT (bitsize);
1473 bitpos_rtx = GEN_INT (xbitpos);
1475 pat = gen_extzv (protect_from_queue (xtarget, 1),
1476 xop0, bitsize_rtx, bitpos_rtx);
1481 spec_target = xspec_target;
1482 spec_target_subreg = xspec_target_subreg;
1486 delete_insns_since (last);
1487 target = extract_fixed_bit_field (int_mode, op0, offset, bitsize,
1493 target = extract_fixed_bit_field (int_mode, op0, offset, bitsize,
1499 && (GET_MODE_BITSIZE (extv_mode) >= bitsize)
1500 && ! ((REG_P (op0) || GET_CODE (op0) == SUBREG)
1501 && (bitsize + bitpos > GET_MODE_BITSIZE (extv_mode))))
1503 int xbitpos = bitpos, xoffset = offset;
1504 rtx bitsize_rtx, bitpos_rtx;
1505 rtx last = get_last_insn ();
1506 rtx xop0 = op0, xtarget = target;
1507 rtx xspec_target = spec_target;
1508 rtx xspec_target_subreg = spec_target_subreg;
1510 enum machine_mode maxmode = mode_for_extraction (EP_extv, 0);
1514 /* Is the memory operand acceptable? */
1515 if (! ((*insn_data[(int) CODE_FOR_extv].operand[1].predicate)
1516 (xop0, GET_MODE (xop0))))
1518 /* No, load into a reg and extract from there. */
1519 enum machine_mode bestmode;
1521 /* Get the mode to use for inserting into this field. If
1522 OP0 is BLKmode, get the smallest mode consistent with the
1523 alignment. If OP0 is a non-BLKmode object that is no
1524 wider than MAXMODE, use its mode. Otherwise, use the
1525 smallest mode containing the field. */
1527 if (GET_MODE (xop0) == BLKmode
1528 || (GET_MODE_SIZE (GET_MODE (op0))
1529 > GET_MODE_SIZE (maxmode)))
1530 bestmode = get_best_mode (bitsize, bitnum,
1531 MEM_ALIGN (xop0), maxmode,
1532 MEM_VOLATILE_P (xop0));
1534 bestmode = GET_MODE (xop0);
1536 if (bestmode == VOIDmode
1537 || (SLOW_UNALIGNED_ACCESS (bestmode, MEM_ALIGN (xop0))
1538 && GET_MODE_BITSIZE (bestmode) > MEM_ALIGN (xop0)))
1541 /* Compute offset as multiple of this unit,
1542 counting in bytes. */
1543 unit = GET_MODE_BITSIZE (bestmode);
1544 xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
1545 xbitpos = bitnum % unit;
1546 xop0 = adjust_address (xop0, bestmode, xoffset);
1548 /* Fetch it to a register in that size. */
1549 xop0 = force_reg (bestmode, xop0);
1551 /* XBITPOS counts within UNIT, which is what is expected. */
1554 /* Get ref to first byte containing part of the field. */
1555 xop0 = adjust_address (xop0, byte_mode, xoffset);
1558 /* If op0 is a register, we need it in MAXMODE (which is usually
1559 SImode) to make it acceptable to the format of extv. */
1560 if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode)
1562 if (REG_P (xop0) && GET_MODE (xop0) != maxmode)
1563 xop0 = gen_rtx_SUBREG (maxmode, xop0, 0);
1565 /* On big-endian machines, we count bits from the most significant.
1566 If the bit field insn does not, we must invert. */
1567 if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
1568 xbitpos = unit - bitsize - xbitpos;
1570 /* XBITPOS counts within a size of UNIT.
1571 Adjust to count within a size of MAXMODE. */
1572 if (BITS_BIG_ENDIAN && !MEM_P (xop0))
1573 xbitpos += (GET_MODE_BITSIZE (maxmode) - unit);
1575 unit = GET_MODE_BITSIZE (maxmode);
1578 || (flag_force_mem && MEM_P (xtarget)))
1579 xtarget = xspec_target = gen_reg_rtx (tmode);
1581 if (GET_MODE (xtarget) != maxmode)
1583 if (REG_P (xtarget))
1585 int wider = (GET_MODE_SIZE (maxmode)
1586 > GET_MODE_SIZE (GET_MODE (xtarget)));
1587 xtarget = gen_lowpart (maxmode, xtarget);
1589 xspec_target_subreg = xtarget;
1592 xtarget = gen_reg_rtx (maxmode);
1595 /* If this machine's extv insists on a register target,
1596 make sure we have one. */
1597 if (! ((*insn_data[(int) CODE_FOR_extv].operand[0].predicate)
1598 (xtarget, maxmode)))
1599 xtarget = gen_reg_rtx (maxmode);
1601 bitsize_rtx = GEN_INT (bitsize);
1602 bitpos_rtx = GEN_INT (xbitpos);
1604 pat = gen_extv (protect_from_queue (xtarget, 1),
1605 xop0, bitsize_rtx, bitpos_rtx);
1610 spec_target = xspec_target;
1611 spec_target_subreg = xspec_target_subreg;
1615 delete_insns_since (last);
1616 target = extract_fixed_bit_field (int_mode, op0, offset, bitsize,
1622 target = extract_fixed_bit_field (int_mode, op0, offset, bitsize,
1625 if (target == spec_target)
1627 if (target == spec_target_subreg)
1629 if (GET_MODE (target) != tmode && GET_MODE (target) != mode)
1631 /* If the target mode is floating-point, first convert to the
1632 integer mode of that size and then access it as a floating-point
1633 value via a SUBREG. */
1634 if (GET_MODE_CLASS (tmode) != MODE_INT
1635 && GET_MODE_CLASS (tmode) != MODE_PARTIAL_INT)
1637 target = convert_to_mode (mode_for_size (GET_MODE_BITSIZE (tmode),
1640 return gen_lowpart (tmode, target);
1643 return convert_to_mode (tmode, target, unsignedp);
1648 /* Extract a bit field using shifts and boolean operations
1649 Returns an rtx to represent the value.
1650 OP0 addresses a register (word) or memory (byte).
1651 BITPOS says which bit within the word or byte the bit field starts in.
1652 OFFSET says how many bytes farther the bit field starts;
1653 it is 0 if OP0 is a register.
1654 BITSIZE says how many bits long the bit field is.
1655 (If OP0 is a register, it may be narrower than a full word,
1656 but BITPOS still counts within a full word,
1657 which is significant on bigendian machines.)
1659 UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
1660 If TARGET is nonzero, attempts to store the value there
1661 and return TARGET, but this is not guaranteed.
1662 If TARGET is not used, create a pseudo-reg of mode TMODE for the value. */
1665 extract_fixed_bit_field (enum machine_mode tmode, rtx op0,
1666 unsigned HOST_WIDE_INT offset,
1667 unsigned HOST_WIDE_INT bitsize,
1668 unsigned HOST_WIDE_INT bitpos, rtx target,
1671 unsigned int total_bits = BITS_PER_WORD;
1672 enum machine_mode mode;
1674 if (GET_CODE (op0) == SUBREG || REG_P (op0))
1676 /* Special treatment for a bit field split across two registers. */
1677 if (bitsize + bitpos > BITS_PER_WORD)
1678 return extract_split_bit_field (op0, bitsize, bitpos, unsignedp);
1682 /* Get the proper mode to use for this field. We want a mode that
1683 includes the entire field. If such a mode would be larger than
1684 a word, we won't be doing the extraction the normal way. */
1686 mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT,
1687 MEM_ALIGN (op0), word_mode, MEM_VOLATILE_P (op0));
1689 if (mode == VOIDmode)
1690 /* The only way this should occur is if the field spans word
1692 return extract_split_bit_field (op0, bitsize,
1693 bitpos + offset * BITS_PER_UNIT,
1696 total_bits = GET_MODE_BITSIZE (mode);
1698 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
1699 be in the range 0 to total_bits-1, and put any excess bytes in
1701 if (bitpos >= total_bits)
1703 offset += (bitpos / total_bits) * (total_bits / BITS_PER_UNIT);
1704 bitpos -= ((bitpos / total_bits) * (total_bits / BITS_PER_UNIT)
1708 /* Get ref to an aligned byte, halfword, or word containing the field.
1709 Adjust BITPOS to be position within a word,
1710 and OFFSET to be the offset of that word.
1711 Then alter OP0 to refer to that word. */
1712 bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT;
1713 offset -= (offset % (total_bits / BITS_PER_UNIT));
1714 op0 = adjust_address (op0, mode, offset);
1717 mode = GET_MODE (op0);
1719 if (BYTES_BIG_ENDIAN)
1720 /* BITPOS is the distance between our msb and that of OP0.
1721 Convert it to the distance from the lsb. */
1722 bitpos = total_bits - bitsize - bitpos;
1724 /* Now BITPOS is always the distance between the field's lsb and that of OP0.
1725 We have reduced the big-endian case to the little-endian case. */
1731 /* If the field does not already start at the lsb,
1732 shift it so it does. */
1733 tree amount = build_int_2 (bitpos, 0);
1734 /* Maybe propagate the target for the shift. */
1735 /* But not if we will return it--could confuse integrate.c. */
1736 rtx subtarget = (target != 0 && REG_P (target) ? target : 0);
1737 if (tmode != mode) subtarget = 0;
1738 op0 = expand_shift (RSHIFT_EXPR, mode, op0, amount, subtarget, 1);
1740 /* Convert the value to the desired mode. */
1742 op0 = convert_to_mode (tmode, op0, 1);
1744 /* Unless the msb of the field used to be the msb when we shifted,
1745 mask out the upper bits. */
1747 if (GET_MODE_BITSIZE (mode) != bitpos + bitsize)
1748 return expand_binop (GET_MODE (op0), and_optab, op0,
1749 mask_rtx (GET_MODE (op0), 0, bitsize, 0),
1750 target, 1, OPTAB_LIB_WIDEN);
1754 /* To extract a signed bit-field, first shift its msb to the msb of the word,
1755 then arithmetic-shift its lsb to the lsb of the word. */
1756 op0 = force_reg (mode, op0);
1760 /* Find the narrowest integer mode that contains the field. */
1762 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode;
1763 mode = GET_MODE_WIDER_MODE (mode))
1764 if (GET_MODE_BITSIZE (mode) >= bitsize + bitpos)
1766 op0 = convert_to_mode (mode, op0, 0);
1770 if (GET_MODE_BITSIZE (mode) != (bitsize + bitpos))
1773 = build_int_2 (GET_MODE_BITSIZE (mode) - (bitsize + bitpos), 0);
1774 /* Maybe propagate the target for the shift. */
1775 rtx subtarget = (target != 0 && REG_P (target) ? target : 0);
1776 op0 = expand_shift (LSHIFT_EXPR, mode, op0, amount, subtarget, 1);
1779 return expand_shift (RSHIFT_EXPR, mode, op0,
1780 build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0),
1784 /* Return a constant integer (CONST_INT or CONST_DOUBLE) mask value
1785 of mode MODE with BITSIZE ones followed by BITPOS zeros, or the
1786 complement of that if COMPLEMENT. The mask is truncated if
1787 necessary to the width of mode MODE. The mask is zero-extended if
1788 BITSIZE+BITPOS is too small for MODE. */
1791 mask_rtx (enum machine_mode mode, int bitpos, int bitsize, int complement)
1793 HOST_WIDE_INT masklow, maskhigh;
1797 else if (bitpos < HOST_BITS_PER_WIDE_INT)
1798 masklow = (HOST_WIDE_INT) -1 << bitpos;
1802 if (bitpos + bitsize < HOST_BITS_PER_WIDE_INT)
1803 masklow &= ((unsigned HOST_WIDE_INT) -1
1804 >> (HOST_BITS_PER_WIDE_INT - bitpos - bitsize));
1806 if (bitpos <= HOST_BITS_PER_WIDE_INT)
1809 maskhigh = (HOST_WIDE_INT) -1 << (bitpos - HOST_BITS_PER_WIDE_INT);
1813 else if (bitpos + bitsize > HOST_BITS_PER_WIDE_INT)
1814 maskhigh &= ((unsigned HOST_WIDE_INT) -1
1815 >> (2 * HOST_BITS_PER_WIDE_INT - bitpos - bitsize));
1821 maskhigh = ~maskhigh;
1825 return immed_double_const (masklow, maskhigh, mode);
1828 /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
1829 VALUE truncated to BITSIZE bits and then shifted left BITPOS bits. */
1832 lshift_value (enum machine_mode mode, rtx value, int bitpos, int bitsize)
1834 unsigned HOST_WIDE_INT v = INTVAL (value);
1835 HOST_WIDE_INT low, high;
1837 if (bitsize < HOST_BITS_PER_WIDE_INT)
1838 v &= ~((HOST_WIDE_INT) -1 << bitsize);
1840 if (bitpos < HOST_BITS_PER_WIDE_INT)
1843 high = (bitpos > 0 ? (v >> (HOST_BITS_PER_WIDE_INT - bitpos)) : 0);
1848 high = v << (bitpos - HOST_BITS_PER_WIDE_INT);
1851 return immed_double_const (low, high, mode);
1854 /* Extract a bit field that is split across two words
1855 and return an RTX for the result.
1857 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
1858 BITSIZE is the field width; BITPOS, position of its first bit, in the word.
1859 UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend. */
1862 extract_split_bit_field (rtx op0, unsigned HOST_WIDE_INT bitsize,
1863 unsigned HOST_WIDE_INT bitpos, int unsignedp)
1866 unsigned int bitsdone = 0;
1867 rtx result = NULL_RTX;
1870 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1872 if (REG_P (op0) || GET_CODE (op0) == SUBREG)
1873 unit = BITS_PER_WORD;
1875 unit = MIN (MEM_ALIGN (op0), BITS_PER_WORD);
1877 while (bitsdone < bitsize)
1879 unsigned HOST_WIDE_INT thissize;
1881 unsigned HOST_WIDE_INT thispos;
1882 unsigned HOST_WIDE_INT offset;
1884 offset = (bitpos + bitsdone) / unit;
1885 thispos = (bitpos + bitsdone) % unit;
1887 /* THISSIZE must not overrun a word boundary. Otherwise,
1888 extract_fixed_bit_field will call us again, and we will mutually
1890 thissize = MIN (bitsize - bitsdone, BITS_PER_WORD);
1891 thissize = MIN (thissize, unit - thispos);
1893 /* If OP0 is a register, then handle OFFSET here.
1895 When handling multiword bitfields, extract_bit_field may pass
1896 down a word_mode SUBREG of a larger REG for a bitfield that actually
1897 crosses a word boundary. Thus, for a SUBREG, we must find
1898 the current word starting from the base register. */
1899 if (GET_CODE (op0) == SUBREG)
1901 int word_offset = (SUBREG_BYTE (op0) / UNITS_PER_WORD) + offset;
1902 word = operand_subword_force (SUBREG_REG (op0), word_offset,
1903 GET_MODE (SUBREG_REG (op0)));
1906 else if (REG_P (op0))
1908 word = operand_subword_force (op0, offset, GET_MODE (op0));
1914 /* Extract the parts in bit-counting order,
1915 whose meaning is determined by BYTES_PER_UNIT.
1916 OFFSET is in UNITs, and UNIT is in bits.
1917 extract_fixed_bit_field wants offset in bytes. */
1918 part = extract_fixed_bit_field (word_mode, word,
1919 offset * unit / BITS_PER_UNIT,
1920 thissize, thispos, 0, 1);
1921 bitsdone += thissize;
1923 /* Shift this part into place for the result. */
1924 if (BYTES_BIG_ENDIAN)
1926 if (bitsize != bitsdone)
1927 part = expand_shift (LSHIFT_EXPR, word_mode, part,
1928 build_int_2 (bitsize - bitsdone, 0), 0, 1);
1932 if (bitsdone != thissize)
1933 part = expand_shift (LSHIFT_EXPR, word_mode, part,
1934 build_int_2 (bitsdone - thissize, 0), 0, 1);
1940 /* Combine the parts with bitwise or. This works
1941 because we extracted each part as an unsigned bit field. */
1942 result = expand_binop (word_mode, ior_optab, part, result, NULL_RTX, 1,
1948 /* Unsigned bit field: we are done. */
1951 /* Signed bit field: sign-extend with two arithmetic shifts. */
1952 result = expand_shift (LSHIFT_EXPR, word_mode, result,
1953 build_int_2 (BITS_PER_WORD - bitsize, 0),
1955 return expand_shift (RSHIFT_EXPR, word_mode, result,
1956 build_int_2 (BITS_PER_WORD - bitsize, 0), NULL_RTX, 0);
1959 /* Add INC into TARGET. */
1962 expand_inc (rtx target, rtx inc)
1964 rtx value = expand_binop (GET_MODE (target), add_optab,
1966 target, 0, OPTAB_LIB_WIDEN);
1967 if (value != target)
1968 emit_move_insn (target, value);
1971 /* Subtract DEC from TARGET. */
1974 expand_dec (rtx target, rtx dec)
1976 rtx value = expand_binop (GET_MODE (target), sub_optab,
1978 target, 0, OPTAB_LIB_WIDEN);
1979 if (value != target)
1980 emit_move_insn (target, value);
1983 /* Output a shift instruction for expression code CODE,
1984 with SHIFTED being the rtx for the value to shift,
1985 and AMOUNT the tree for the amount to shift by.
1986 Store the result in the rtx TARGET, if that is convenient.
1987 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
1988 Return the rtx for where the value is. */
1991 expand_shift (enum tree_code code, enum machine_mode mode, rtx shifted,
1992 tree amount, rtx target, int unsignedp)
1995 int left = (code == LSHIFT_EXPR || code == LROTATE_EXPR);
1996 int rotate = (code == LROTATE_EXPR || code == RROTATE_EXPR);
1999 /* Previously detected shift-counts computed by NEGATE_EXPR
2000 and shifted in the other direction; but that does not work
2003 op1 = expand_expr (amount, NULL_RTX, VOIDmode, 0);
2005 if (SHIFT_COUNT_TRUNCATED)
2007 if (GET_CODE (op1) == CONST_INT
2008 && ((unsigned HOST_WIDE_INT) INTVAL (op1) >=
2009 (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode)))
2010 op1 = GEN_INT ((unsigned HOST_WIDE_INT) INTVAL (op1)
2011 % GET_MODE_BITSIZE (mode));
2012 else if (GET_CODE (op1) == SUBREG
2013 && subreg_lowpart_p (op1))
2014 op1 = SUBREG_REG (op1);
2017 if (op1 == const0_rtx)
2020 /* Check whether its cheaper to implement a left shift by a constant
2021 bit count by a sequence of additions. */
2022 if (code == LSHIFT_EXPR
2023 && GET_CODE (op1) == CONST_INT
2025 && INTVAL (op1) < GET_MODE_BITSIZE (mode)
2026 && shift_cost[mode][INTVAL (op1)] > INTVAL (op1) * add_cost[mode])
2029 for (i = 0; i < INTVAL (op1); i++)
2031 temp = force_reg (mode, shifted);
2032 shifted = expand_binop (mode, add_optab, temp, temp, NULL_RTX,
2033 unsignedp, OPTAB_LIB_WIDEN);
2038 for (try = 0; temp == 0 && try < 3; try++)
2040 enum optab_methods methods;
2043 methods = OPTAB_DIRECT;
2045 methods = OPTAB_WIDEN;
2047 methods = OPTAB_LIB_WIDEN;
2051 /* Widening does not work for rotation. */
2052 if (methods == OPTAB_WIDEN)
2054 else if (methods == OPTAB_LIB_WIDEN)
2056 /* If we have been unable to open-code this by a rotation,
2057 do it as the IOR of two shifts. I.e., to rotate A
2058 by N bits, compute (A << N) | ((unsigned) A >> (C - N))
2059 where C is the bitsize of A.
2061 It is theoretically possible that the target machine might
2062 not be able to perform either shift and hence we would
2063 be making two libcalls rather than just the one for the
2064 shift (similarly if IOR could not be done). We will allow
2065 this extremely unlikely lossage to avoid complicating the
2068 rtx subtarget = target == shifted ? 0 : target;
2070 tree type = TREE_TYPE (amount);
2071 tree new_amount = make_tree (type, op1);
2073 = fold (build (MINUS_EXPR, type,
2075 build_int_2 (GET_MODE_BITSIZE (mode),
2079 shifted = force_reg (mode, shifted);
2081 temp = expand_shift (left ? LSHIFT_EXPR : RSHIFT_EXPR,
2082 mode, shifted, new_amount, subtarget, 1);
2083 temp1 = expand_shift (left ? RSHIFT_EXPR : LSHIFT_EXPR,
2084 mode, shifted, other_amount, 0, 1);
2085 return expand_binop (mode, ior_optab, temp, temp1, target,
2086 unsignedp, methods);
2089 temp = expand_binop (mode,
2090 left ? rotl_optab : rotr_optab,
2091 shifted, op1, target, unsignedp, methods);
2093 /* If we don't have the rotate, but we are rotating by a constant
2094 that is in range, try a rotate in the opposite direction. */
2096 if (temp == 0 && GET_CODE (op1) == CONST_INT
2098 && (unsigned int) INTVAL (op1) < GET_MODE_BITSIZE (mode))
2099 temp = expand_binop (mode,
2100 left ? rotr_optab : rotl_optab,
2102 GEN_INT (GET_MODE_BITSIZE (mode)
2104 target, unsignedp, methods);
2107 temp = expand_binop (mode,
2108 left ? ashl_optab : lshr_optab,
2109 shifted, op1, target, unsignedp, methods);
2111 /* Do arithmetic shifts.
2112 Also, if we are going to widen the operand, we can just as well
2113 use an arithmetic right-shift instead of a logical one. */
2114 if (temp == 0 && ! rotate
2115 && (! unsignedp || (! left && methods == OPTAB_WIDEN)))
2117 enum optab_methods methods1 = methods;
2119 /* If trying to widen a log shift to an arithmetic shift,
2120 don't accept an arithmetic shift of the same size. */
2122 methods1 = OPTAB_MUST_WIDEN;
2124 /* Arithmetic shift */
2126 temp = expand_binop (mode,
2127 left ? ashl_optab : ashr_optab,
2128 shifted, op1, target, unsignedp, methods1);
2131 /* We used to try extzv here for logical right shifts, but that was
2132 only useful for one machine, the VAX, and caused poor code
2133 generation there for lshrdi3, so the code was deleted and a
2134 define_expand for lshrsi3 was added to vax.md. */
2142 enum alg_code { alg_zero, alg_m, alg_shift,
2143 alg_add_t_m2, alg_sub_t_m2,
2144 alg_add_factor, alg_sub_factor,
2145 alg_add_t2_m, alg_sub_t2_m,
2146 alg_add, alg_subtract, alg_factor, alg_shiftop };
2148 /* This structure records a sequence of operations.
2149 `ops' is the number of operations recorded.
2150 `cost' is their total cost.
2151 The operations are stored in `op' and the corresponding
2152 logarithms of the integer coefficients in `log'.
2154 These are the operations:
2155 alg_zero total := 0;
2156 alg_m total := multiplicand;
2157 alg_shift total := total * coeff
2158 alg_add_t_m2 total := total + multiplicand * coeff;
2159 alg_sub_t_m2 total := total - multiplicand * coeff;
2160 alg_add_factor total := total * coeff + total;
2161 alg_sub_factor total := total * coeff - total;
2162 alg_add_t2_m total := total * coeff + multiplicand;
2163 alg_sub_t2_m total := total * coeff - multiplicand;
2165 The first operand must be either alg_zero or alg_m. */
2171 /* The size of the OP and LOG fields are not directly related to the
2172 word size, but the worst-case algorithms will be if we have few
2173 consecutive ones or zeros, i.e., a multiplicand like 10101010101...
2174 In that case we will generate shift-by-2, add, shift-by-2, add,...,
2175 in total wordsize operations. */
2176 enum alg_code op[MAX_BITS_PER_WORD];
2177 char log[MAX_BITS_PER_WORD];
2180 /* Indicates the type of fixup needed after a constant multiplication.
2181 BASIC_VARIANT means no fixup is needed, NEGATE_VARIANT means that
2182 the result should be negated, and ADD_VARIANT means that the
2183 multiplicand should be added to the result. */
2184 enum mult_variant {basic_variant, negate_variant, add_variant};
2186 static void synth_mult (struct algorithm *, unsigned HOST_WIDE_INT,
2187 int, enum machine_mode mode);
2188 static bool choose_mult_variant (enum machine_mode, HOST_WIDE_INT,
2189 struct algorithm *, enum mult_variant *, int);
2190 static rtx expand_mult_const (enum machine_mode, rtx, HOST_WIDE_INT, rtx,
2191 const struct algorithm *, enum mult_variant);
2192 static unsigned HOST_WIDE_INT choose_multiplier (unsigned HOST_WIDE_INT, int,
2193 int, unsigned HOST_WIDE_INT *,
2195 static unsigned HOST_WIDE_INT invert_mod2n (unsigned HOST_WIDE_INT, int);
2196 static rtx extract_high_half (enum machine_mode, rtx);
2197 static rtx expand_mult_highpart_optab (enum machine_mode, rtx, rtx, rtx,
2199 /* Compute and return the best algorithm for multiplying by T.
2200 The algorithm must cost less than cost_limit
2201 If retval.cost >= COST_LIMIT, no algorithm was found and all
2202 other field of the returned struct are undefined.
2203 MODE is the machine mode of the multiplication. */
2206 synth_mult (struct algorithm *alg_out, unsigned HOST_WIDE_INT t,
2207 int cost_limit, enum machine_mode mode)
2210 struct algorithm *alg_in, *best_alg;
2212 unsigned HOST_WIDE_INT q;
2213 int maxm = MIN (BITS_PER_WORD, GET_MODE_BITSIZE (mode));
2215 /* Indicate that no algorithm is yet found. If no algorithm
2216 is found, this value will be returned and indicate failure. */
2217 alg_out->cost = cost_limit;
2219 if (cost_limit <= 0)
2222 /* Restrict the bits of "t" to the multiplication's mode. */
2223 t &= GET_MODE_MASK (mode);
2225 /* t == 1 can be done in zero cost. */
2230 alg_out->op[0] = alg_m;
2234 /* t == 0 sometimes has a cost. If it does and it exceeds our limit,
2238 if (zero_cost >= cost_limit)
2243 alg_out->cost = zero_cost;
2244 alg_out->op[0] = alg_zero;
2249 /* We'll be needing a couple extra algorithm structures now. */
2251 alg_in = alloca (sizeof (struct algorithm));
2252 best_alg = alloca (sizeof (struct algorithm));
2254 /* If we have a group of zero bits at the low-order part of T, try
2255 multiplying by the remaining bits and then doing a shift. */
2259 m = floor_log2 (t & -t); /* m = number of low zero bits */
2263 /* The function expand_shift will choose between a shift and
2264 a sequence of additions, so the observed cost is given as
2265 MIN (m * add_cost[mode], shift_cost[mode][m]). */
2266 cost = m * add_cost[mode];
2267 if (shift_cost[mode][m] < cost)
2268 cost = shift_cost[mode][m];
2269 synth_mult (alg_in, q, cost_limit - cost, mode);
2271 cost += alg_in->cost;
2272 if (cost < cost_limit)
2274 struct algorithm *x;
2275 x = alg_in, alg_in = best_alg, best_alg = x;
2276 best_alg->log[best_alg->ops] = m;
2277 best_alg->op[best_alg->ops] = alg_shift;
2283 /* If we have an odd number, add or subtract one. */
2286 unsigned HOST_WIDE_INT w;
2288 for (w = 1; (w & t) != 0; w <<= 1)
2290 /* If T was -1, then W will be zero after the loop. This is another
2291 case where T ends with ...111. Handling this with (T + 1) and
2292 subtract 1 produces slightly better code and results in algorithm
2293 selection much faster than treating it like the ...0111 case
2297 /* Reject the case where t is 3.
2298 Thus we prefer addition in that case. */
2301 /* T ends with ...111. Multiply by (T + 1) and subtract 1. */
2303 cost = add_cost[mode];
2304 synth_mult (alg_in, t + 1, cost_limit - cost, mode);
2306 cost += alg_in->cost;
2307 if (cost < cost_limit)
2309 struct algorithm *x;
2310 x = alg_in, alg_in = best_alg, best_alg = x;
2311 best_alg->log[best_alg->ops] = 0;
2312 best_alg->op[best_alg->ops] = alg_sub_t_m2;
2318 /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */
2320 cost = add_cost[mode];
2321 synth_mult (alg_in, t - 1, cost_limit - cost, mode);
2323 cost += alg_in->cost;
2324 if (cost < cost_limit)
2326 struct algorithm *x;
2327 x = alg_in, alg_in = best_alg, best_alg = x;
2328 best_alg->log[best_alg->ops] = 0;
2329 best_alg->op[best_alg->ops] = alg_add_t_m2;
2335 /* Look for factors of t of the form
2336 t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)).
2337 If we find such a factor, we can multiply by t using an algorithm that
2338 multiplies by q, shift the result by m and add/subtract it to itself.
2340 We search for large factors first and loop down, even if large factors
2341 are less probable than small; if we find a large factor we will find a
2342 good sequence quickly, and therefore be able to prune (by decreasing
2343 COST_LIMIT) the search. */
2345 for (m = floor_log2 (t - 1); m >= 2; m--)
2347 unsigned HOST_WIDE_INT d;
2349 d = ((unsigned HOST_WIDE_INT) 1 << m) + 1;
2350 if (t % d == 0 && t > d && m < maxm)
2352 cost = add_cost[mode] + shift_cost[mode][m];
2353 if (shiftadd_cost[mode][m] < cost)
2354 cost = shiftadd_cost[mode][m];
2355 synth_mult (alg_in, t / d, cost_limit - cost, mode);
2357 cost += alg_in->cost;
2358 if (cost < cost_limit)
2360 struct algorithm *x;
2361 x = alg_in, alg_in = best_alg, best_alg = x;
2362 best_alg->log[best_alg->ops] = m;
2363 best_alg->op[best_alg->ops] = alg_add_factor;
2366 /* Other factors will have been taken care of in the recursion. */
2370 d = ((unsigned HOST_WIDE_INT) 1 << m) - 1;
2371 if (t % d == 0 && t > d && m < maxm)
2373 cost = add_cost[mode] + shift_cost[mode][m];
2374 if (shiftsub_cost[mode][m] < cost)
2375 cost = shiftsub_cost[mode][m];
2376 synth_mult (alg_in, t / d, cost_limit - cost, mode);
2378 cost += alg_in->cost;
2379 if (cost < cost_limit)
2381 struct algorithm *x;
2382 x = alg_in, alg_in = best_alg, best_alg = x;
2383 best_alg->log[best_alg->ops] = m;
2384 best_alg->op[best_alg->ops] = alg_sub_factor;
2391 /* Try shift-and-add (load effective address) instructions,
2392 i.e. do a*3, a*5, a*9. */
2398 if (m >= 0 && m < maxm)
2400 cost = shiftadd_cost[mode][m];
2401 synth_mult (alg_in, (t - 1) >> m, cost_limit - cost, mode);
2403 cost += alg_in->cost;
2404 if (cost < cost_limit)
2406 struct algorithm *x;
2407 x = alg_in, alg_in = best_alg, best_alg = x;
2408 best_alg->log[best_alg->ops] = m;
2409 best_alg->op[best_alg->ops] = alg_add_t2_m;
2417 if (m >= 0 && m < maxm)
2419 cost = shiftsub_cost[mode][m];
2420 synth_mult (alg_in, (t + 1) >> m, cost_limit - cost, mode);
2422 cost += alg_in->cost;
2423 if (cost < cost_limit)
2425 struct algorithm *x;
2426 x = alg_in, alg_in = best_alg, best_alg = x;
2427 best_alg->log[best_alg->ops] = m;
2428 best_alg->op[best_alg->ops] = alg_sub_t2_m;
2434 /* If cost_limit has not decreased since we stored it in alg_out->cost,
2435 we have not found any algorithm. */
2436 if (cost_limit == alg_out->cost)
2439 /* If we are getting a too long sequence for `struct algorithm'
2440 to record, make this search fail. */
2441 if (best_alg->ops == MAX_BITS_PER_WORD)
2444 /* Copy the algorithm from temporary space to the space at alg_out.
2445 We avoid using structure assignment because the majority of
2446 best_alg is normally undefined, and this is a critical function. */
2447 alg_out->ops = best_alg->ops + 1;
2448 alg_out->cost = cost_limit;
2449 memcpy (alg_out->op, best_alg->op,
2450 alg_out->ops * sizeof *alg_out->op);
2451 memcpy (alg_out->log, best_alg->log,
2452 alg_out->ops * sizeof *alg_out->log);
2455 /* Find the cheapest way of multiplying a value of mode MODE by VAL.
2456 Try three variations:
2458 - a shift/add sequence based on VAL itself
2459 - a shift/add sequence based on -VAL, followed by a negation
2460 - a shift/add sequence based on VAL - 1, followed by an addition.
2462 Return true if the cheapest of these cost less than MULT_COST,
2463 describing the algorithm in *ALG and final fixup in *VARIANT. */
2466 choose_mult_variant (enum machine_mode mode, HOST_WIDE_INT val,
2467 struct algorithm *alg, enum mult_variant *variant,
2470 struct algorithm alg2;
2472 *variant = basic_variant;
2473 synth_mult (alg, val, mult_cost, mode);
2475 /* This works only if the inverted value actually fits in an
2477 if (HOST_BITS_PER_INT >= GET_MODE_BITSIZE (mode))
2479 synth_mult (&alg2, -val, MIN (alg->cost, mult_cost) - neg_cost[mode],
2481 alg2.cost += neg_cost[mode];
2482 if (alg2.cost < alg->cost)
2483 *alg = alg2, *variant = negate_variant;
2486 /* This proves very useful for division-by-constant. */
2487 synth_mult (&alg2, val - 1, MIN (alg->cost, mult_cost) - add_cost[mode],
2489 alg2.cost += add_cost[mode];
2490 if (alg2.cost < alg->cost)
2491 *alg = alg2, *variant = add_variant;
2493 return alg->cost < mult_cost;
2496 /* A subroutine of expand_mult, used for constant multiplications.
2497 Multiply OP0 by VAL in mode MODE, storing the result in TARGET if
2498 convenient. Use the shift/add sequence described by ALG and apply
2499 the final fixup specified by VARIANT. */
2502 expand_mult_const (enum machine_mode mode, rtx op0, HOST_WIDE_INT val,
2503 rtx target, const struct algorithm *alg,
2504 enum mult_variant variant)
2506 HOST_WIDE_INT val_so_far;
2507 rtx insn, accum, tem;
2509 enum machine_mode nmode;
2511 /* op0 must be register to make mult_cost match the precomputed
2512 shiftadd_cost array. */
2513 op0 = protect_from_queue (op0, 0);
2515 /* Avoid referencing memory over and over.
2516 For speed, but also for correctness when mem is volatile. */
2518 op0 = force_reg (mode, op0);
2520 /* ACCUM starts out either as OP0 or as a zero, depending on
2521 the first operation. */
2523 if (alg->op[0] == alg_zero)
2525 accum = copy_to_mode_reg (mode, const0_rtx);
2528 else if (alg->op[0] == alg_m)
2530 accum = copy_to_mode_reg (mode, op0);
2536 for (opno = 1; opno < alg->ops; opno++)
2538 int log = alg->log[opno];
2539 int preserve = preserve_subexpressions_p ();
2540 rtx shift_subtarget = preserve ? 0 : accum;
2542 = (opno == alg->ops - 1 && target != 0 && variant != add_variant
2545 rtx accum_target = preserve ? 0 : accum;
2547 switch (alg->op[opno])
2550 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2551 build_int_2 (log, 0), NULL_RTX, 0);
2556 tem = expand_shift (LSHIFT_EXPR, mode, op0,
2557 build_int_2 (log, 0), NULL_RTX, 0);
2558 accum = force_operand (gen_rtx_PLUS (mode, accum, tem),
2559 add_target ? add_target : accum_target);
2560 val_so_far += (HOST_WIDE_INT) 1 << log;
2564 tem = expand_shift (LSHIFT_EXPR, mode, op0,
2565 build_int_2 (log, 0), NULL_RTX, 0);
2566 accum = force_operand (gen_rtx_MINUS (mode, accum, tem),
2567 add_target ? add_target : accum_target);
2568 val_so_far -= (HOST_WIDE_INT) 1 << log;
2572 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2573 build_int_2 (log, 0), shift_subtarget,
2575 accum = force_operand (gen_rtx_PLUS (mode, accum, op0),
2576 add_target ? add_target : accum_target);
2577 val_so_far = (val_so_far << log) + 1;
2581 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2582 build_int_2 (log, 0), shift_subtarget, 0);
2583 accum = force_operand (gen_rtx_MINUS (mode, accum, op0),
2584 add_target ? add_target : accum_target);
2585 val_so_far = (val_so_far << log) - 1;
2588 case alg_add_factor:
2589 tem = expand_shift (LSHIFT_EXPR, mode, accum,
2590 build_int_2 (log, 0), NULL_RTX, 0);
2591 accum = force_operand (gen_rtx_PLUS (mode, accum, tem),
2592 add_target ? add_target : accum_target);
2593 val_so_far += val_so_far << log;
2596 case alg_sub_factor:
2597 tem = expand_shift (LSHIFT_EXPR, mode, accum,
2598 build_int_2 (log, 0), NULL_RTX, 0);
2599 accum = force_operand (gen_rtx_MINUS (mode, tem, accum),
2600 (add_target ? add_target
2601 : preserve ? 0 : tem));
2602 val_so_far = (val_so_far << log) - val_so_far;
2609 /* Write a REG_EQUAL note on the last insn so that we can cse
2610 multiplication sequences. Note that if ACCUM is a SUBREG,
2611 we've set the inner register and must properly indicate
2614 tem = op0, nmode = mode;
2615 if (GET_CODE (accum) == SUBREG)
2617 nmode = GET_MODE (SUBREG_REG (accum));
2618 tem = gen_lowpart (nmode, op0);
2621 insn = get_last_insn ();
2622 set_unique_reg_note (insn, REG_EQUAL,
2623 gen_rtx_MULT (nmode, tem, GEN_INT (val_so_far)));
2626 if (variant == negate_variant)
2628 val_so_far = -val_so_far;
2629 accum = expand_unop (mode, neg_optab, accum, target, 0);
2631 else if (variant == add_variant)
2633 val_so_far = val_so_far + 1;
2634 accum = force_operand (gen_rtx_PLUS (mode, accum, op0), target);
2637 /* Compare only the bits of val and val_so_far that are significant
2638 in the result mode, to avoid sign-/zero-extension confusion. */
2639 val &= GET_MODE_MASK (mode);
2640 val_so_far &= GET_MODE_MASK (mode);
2641 if (val != val_so_far)
2647 /* Perform a multiplication and return an rtx for the result.
2648 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
2649 TARGET is a suggestion for where to store the result (an rtx).
2651 We check specially for a constant integer as OP1.
2652 If you want this check for OP0 as well, then before calling
2653 you should swap the two operands if OP0 would be constant. */
2656 expand_mult (enum machine_mode mode, rtx op0, rtx op1, rtx target,
2659 rtx const_op1 = op1;
2660 enum mult_variant variant;
2661 struct algorithm algorithm;
2663 /* synth_mult does an `unsigned int' multiply. As long as the mode is
2664 less than or equal in size to `unsigned int' this doesn't matter.
2665 If the mode is larger than `unsigned int', then synth_mult works only
2666 if the constant value exactly fits in an `unsigned int' without any
2667 truncation. This means that multiplying by negative values does
2668 not work; results are off by 2^32 on a 32 bit machine. */
2670 /* If we are multiplying in DImode, it may still be a win
2671 to try to work with shifts and adds. */
2672 if (GET_CODE (op1) == CONST_DOUBLE
2673 && GET_MODE_CLASS (GET_MODE (op1)) == MODE_INT
2674 && HOST_BITS_PER_INT >= BITS_PER_WORD
2675 && CONST_DOUBLE_HIGH (op1) == 0)
2676 const_op1 = GEN_INT (CONST_DOUBLE_LOW (op1));
2677 else if (HOST_BITS_PER_INT < GET_MODE_BITSIZE (mode)
2678 && GET_CODE (op1) == CONST_INT
2679 && INTVAL (op1) < 0)
2682 /* We used to test optimize here, on the grounds that it's better to
2683 produce a smaller program when -O is not used.
2684 But this causes such a terrible slowdown sometimes
2685 that it seems better to use synth_mult always. */
2687 if (const_op1 && GET_CODE (const_op1) == CONST_INT
2688 && (unsignedp || !flag_trapv))
2690 int mult_cost = rtx_cost (gen_rtx_MULT (mode, op0, op1), SET);
2692 if (choose_mult_variant (mode, INTVAL (const_op1), &algorithm, &variant,
2694 return expand_mult_const (mode, op0, INTVAL (const_op1), target,
2695 &algorithm, variant);
2698 if (GET_CODE (op0) == CONST_DOUBLE)
2705 /* Expand x*2.0 as x+x. */
2706 if (GET_CODE (op1) == CONST_DOUBLE
2707 && GET_MODE_CLASS (mode) == MODE_FLOAT)
2710 REAL_VALUE_FROM_CONST_DOUBLE (d, op1);
2712 if (REAL_VALUES_EQUAL (d, dconst2))
2714 op0 = force_reg (GET_MODE (op0), op0);
2715 return expand_binop (mode, add_optab, op0, op0,
2716 target, unsignedp, OPTAB_LIB_WIDEN);
2720 /* This used to use umul_optab if unsigned, but for non-widening multiply
2721 there is no difference between signed and unsigned. */
2722 op0 = expand_binop (mode,
2724 && flag_trapv && (GET_MODE_CLASS(mode) == MODE_INT)
2725 ? smulv_optab : smul_optab,
2726 op0, op1, target, unsignedp, OPTAB_LIB_WIDEN);
2732 /* Return the smallest n such that 2**n >= X. */
2735 ceil_log2 (unsigned HOST_WIDE_INT x)
2737 return floor_log2 (x - 1) + 1;
2740 /* Choose a minimal N + 1 bit approximation to 1/D that can be used to
2741 replace division by D, and put the least significant N bits of the result
2742 in *MULTIPLIER_PTR and return the most significant bit.
2744 The width of operations is N (should be <= HOST_BITS_PER_WIDE_INT), the
2745 needed precision is in PRECISION (should be <= N).
2747 PRECISION should be as small as possible so this function can choose
2748 multiplier more freely.
2750 The rounded-up logarithm of D is placed in *lgup_ptr. A shift count that
2751 is to be used for a final right shift is placed in *POST_SHIFT_PTR.
2753 Using this function, x/D will be equal to (x * m) >> (*POST_SHIFT_PTR),
2754 where m is the full HOST_BITS_PER_WIDE_INT + 1 bit multiplier. */
2757 unsigned HOST_WIDE_INT
2758 choose_multiplier (unsigned HOST_WIDE_INT d, int n, int precision,
2759 unsigned HOST_WIDE_INT *multiplier_ptr,
2760 int *post_shift_ptr, int *lgup_ptr)
2762 HOST_WIDE_INT mhigh_hi, mlow_hi;
2763 unsigned HOST_WIDE_INT mhigh_lo, mlow_lo;
2764 int lgup, post_shift;
2766 unsigned HOST_WIDE_INT nl, dummy1;
2767 HOST_WIDE_INT nh, dummy2;
2769 /* lgup = ceil(log2(divisor)); */
2770 lgup = ceil_log2 (d);
2776 pow2 = n + lgup - precision;
2778 if (pow == 2 * HOST_BITS_PER_WIDE_INT)
2780 /* We could handle this with some effort, but this case is much better
2781 handled directly with a scc insn, so rely on caller using that. */
2785 /* mlow = 2^(N + lgup)/d */
2786 if (pow >= HOST_BITS_PER_WIDE_INT)
2788 nh = (HOST_WIDE_INT) 1 << (pow - HOST_BITS_PER_WIDE_INT);
2794 nl = (unsigned HOST_WIDE_INT) 1 << pow;
2796 div_and_round_double (TRUNC_DIV_EXPR, 1, nl, nh, d, (HOST_WIDE_INT) 0,
2797 &mlow_lo, &mlow_hi, &dummy1, &dummy2);
2799 /* mhigh = (2^(N + lgup) + 2^N + lgup - precision)/d */
2800 if (pow2 >= HOST_BITS_PER_WIDE_INT)
2801 nh |= (HOST_WIDE_INT) 1 << (pow2 - HOST_BITS_PER_WIDE_INT);
2803 nl |= (unsigned HOST_WIDE_INT) 1 << pow2;
2804 div_and_round_double (TRUNC_DIV_EXPR, 1, nl, nh, d, (HOST_WIDE_INT) 0,
2805 &mhigh_lo, &mhigh_hi, &dummy1, &dummy2);
2807 if (mhigh_hi && nh - d >= d)
2809 if (mhigh_hi > 1 || mlow_hi > 1)
2811 /* Assert that mlow < mhigh. */
2812 if (! (mlow_hi < mhigh_hi || (mlow_hi == mhigh_hi && mlow_lo < mhigh_lo)))
2815 /* If precision == N, then mlow, mhigh exceed 2^N
2816 (but they do not exceed 2^(N+1)). */
2818 /* Reduce to lowest terms. */
2819 for (post_shift = lgup; post_shift > 0; post_shift--)
2821 unsigned HOST_WIDE_INT ml_lo = (mlow_hi << (HOST_BITS_PER_WIDE_INT - 1)) | (mlow_lo >> 1);
2822 unsigned HOST_WIDE_INT mh_lo = (mhigh_hi << (HOST_BITS_PER_WIDE_INT - 1)) | (mhigh_lo >> 1);
2832 *post_shift_ptr = post_shift;
2834 if (n < HOST_BITS_PER_WIDE_INT)
2836 unsigned HOST_WIDE_INT mask = ((unsigned HOST_WIDE_INT) 1 << n) - 1;
2837 *multiplier_ptr = mhigh_lo & mask;
2838 return mhigh_lo >= mask;
2842 *multiplier_ptr = mhigh_lo;
2847 /* Compute the inverse of X mod 2**n, i.e., find Y such that X * Y is
2848 congruent to 1 (mod 2**N). */
2850 static unsigned HOST_WIDE_INT
2851 invert_mod2n (unsigned HOST_WIDE_INT x, int n)
2853 /* Solve x*y == 1 (mod 2^n), where x is odd. Return y. */
2855 /* The algorithm notes that the choice y = x satisfies
2856 x*y == 1 mod 2^3, since x is assumed odd.
2857 Each iteration doubles the number of bits of significance in y. */
2859 unsigned HOST_WIDE_INT mask;
2860 unsigned HOST_WIDE_INT y = x;
2863 mask = (n == HOST_BITS_PER_WIDE_INT
2864 ? ~(unsigned HOST_WIDE_INT) 0
2865 : ((unsigned HOST_WIDE_INT) 1 << n) - 1);
2869 y = y * (2 - x*y) & mask; /* Modulo 2^N */
2875 /* Emit code to adjust ADJ_OPERAND after multiplication of wrong signedness
2876 flavor of OP0 and OP1. ADJ_OPERAND is already the high half of the
2877 product OP0 x OP1. If UNSIGNEDP is nonzero, adjust the signed product
2878 to become unsigned, if UNSIGNEDP is zero, adjust the unsigned product to
2881 The result is put in TARGET if that is convenient.
2883 MODE is the mode of operation. */
2886 expand_mult_highpart_adjust (enum machine_mode mode, rtx adj_operand, rtx op0,
2887 rtx op1, rtx target, int unsignedp)
2890 enum rtx_code adj_code = unsignedp ? PLUS : MINUS;
2892 tem = expand_shift (RSHIFT_EXPR, mode, op0,
2893 build_int_2 (GET_MODE_BITSIZE (mode) - 1, 0),
2895 tem = expand_and (mode, tem, op1, NULL_RTX);
2897 = force_operand (gen_rtx_fmt_ee (adj_code, mode, adj_operand, tem),
2900 tem = expand_shift (RSHIFT_EXPR, mode, op1,
2901 build_int_2 (GET_MODE_BITSIZE (mode) - 1, 0),
2903 tem = expand_and (mode, tem, op0, NULL_RTX);
2904 target = force_operand (gen_rtx_fmt_ee (adj_code, mode, adj_operand, tem),
2910 /* Subroutine of expand_mult_highpart. Return the MODE high part of OP. */
2913 extract_high_half (enum machine_mode mode, rtx op)
2915 enum machine_mode wider_mode;
2917 if (mode == word_mode)
2918 return gen_highpart (mode, op);
2920 wider_mode = GET_MODE_WIDER_MODE (mode);
2921 op = expand_shift (RSHIFT_EXPR, wider_mode, op,
2922 build_int_2 (GET_MODE_BITSIZE (mode), 0), 0, 1);
2923 return convert_modes (mode, wider_mode, op, 0);
2926 /* Like expand_mult_highpart, but only consider using a multiplication
2927 optab. OP1 is an rtx for the constant operand. */
2930 expand_mult_highpart_optab (enum machine_mode mode, rtx op0, rtx op1,
2931 rtx target, int unsignedp, int max_cost)
2933 rtx narrow_op1 = gen_int_mode (INTVAL (op1), mode);
2934 enum machine_mode wider_mode;
2939 wider_mode = GET_MODE_WIDER_MODE (mode);
2940 size = GET_MODE_BITSIZE (mode);
2942 /* Firstly, try using a multiplication insn that only generates the needed
2943 high part of the product, and in the sign flavor of unsignedp. */
2944 if (mul_highpart_cost[mode] < max_cost)
2946 moptab = unsignedp ? umul_highpart_optab : smul_highpart_optab;
2947 tem = expand_binop (mode, moptab, op0, narrow_op1, target,
2948 unsignedp, OPTAB_DIRECT);
2953 /* Secondly, same as above, but use sign flavor opposite of unsignedp.
2954 Need to adjust the result after the multiplication. */
2955 if (size - 1 < BITS_PER_WORD
2956 && (mul_highpart_cost[mode] + 2 * shift_cost[mode][size-1]
2957 + 4 * add_cost[mode] < max_cost))
2959 moptab = unsignedp ? smul_highpart_optab : umul_highpart_optab;
2960 tem = expand_binop (mode, moptab, op0, narrow_op1, target,
2961 unsignedp, OPTAB_DIRECT);
2963 /* We used the wrong signedness. Adjust the result. */
2964 return expand_mult_highpart_adjust (mode, tem, op0, narrow_op1,
2968 /* Try widening multiplication. */
2969 moptab = unsignedp ? umul_widen_optab : smul_widen_optab;
2970 if (moptab->handlers[wider_mode].insn_code != CODE_FOR_nothing
2971 && mul_widen_cost[wider_mode] < max_cost)
2973 tem = expand_binop (wider_mode, moptab, op0, narrow_op1, 0,
2974 unsignedp, OPTAB_WIDEN);
2976 return extract_high_half (mode, tem);
2979 /* Try widening the mode and perform a non-widening multiplication. */
2980 moptab = smul_optab;
2981 if (smul_optab->handlers[wider_mode].insn_code != CODE_FOR_nothing
2982 && size - 1 < BITS_PER_WORD
2983 && mul_cost[wider_mode] + shift_cost[mode][size-1] < max_cost)
2985 tem = expand_binop (wider_mode, moptab, op0, op1, 0,
2986 unsignedp, OPTAB_WIDEN);
2988 return extract_high_half (mode, tem);
2991 /* Try widening multiplication of opposite signedness, and adjust. */
2992 moptab = unsignedp ? smul_widen_optab : umul_widen_optab;
2993 if (moptab->handlers[wider_mode].insn_code != CODE_FOR_nothing
2994 && size - 1 < BITS_PER_WORD
2995 && (mul_widen_cost[wider_mode] + 2 * shift_cost[mode][size-1]
2996 + 4 * add_cost[mode] < max_cost))
2998 tem = expand_binop (wider_mode, moptab, op0, narrow_op1,
2999 NULL_RTX, ! unsignedp, OPTAB_WIDEN);
3002 tem = extract_high_half (mode, tem);
3003 /* We used the wrong signedness. Adjust the result. */
3004 return expand_mult_highpart_adjust (mode, tem, op0, narrow_op1,
3012 /* Emit code to multiply OP0 and CNST1, putting the high half of the result
3013 in TARGET if that is convenient, and return where the result is. If the
3014 operation can not be performed, 0 is returned.
3016 MODE is the mode of operation and result.
3018 UNSIGNEDP nonzero means unsigned multiply.
3020 MAX_COST is the total allowed cost for the expanded RTL. */
3023 expand_mult_highpart (enum machine_mode mode, rtx op0,
3024 unsigned HOST_WIDE_INT cnst1, rtx target,
3025 int unsignedp, int max_cost)
3027 enum machine_mode wider_mode = GET_MODE_WIDER_MODE (mode);
3029 bool sign_adjust = false;
3030 enum mult_variant variant;
3031 struct algorithm alg;
3034 /* We can't support modes wider than HOST_BITS_PER_INT. */
3035 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
3038 op1 = gen_int_mode (cnst1, wider_mode);
3039 cnst1 &= GET_MODE_MASK (mode);
3041 /* We can't optimize modes wider than BITS_PER_WORD.
3042 ??? We might be able to perform double-word arithmetic if
3043 mode == word_mode, however all the cost calculations in
3044 synth_mult etc. assume single-word operations. */
3045 if (GET_MODE_BITSIZE (wider_mode) > BITS_PER_WORD)
3046 return expand_mult_highpart_optab (mode, op0, op1, target,
3047 unsignedp, max_cost);
3049 extra_cost = shift_cost[mode][GET_MODE_BITSIZE (mode) - 1];
3051 /* Check whether we try to multiply by a negative constant. */
3052 if (!unsignedp && ((cnst1 >> (GET_MODE_BITSIZE (mode) - 1)) & 1))
3055 extra_cost += add_cost[mode];
3058 /* See whether shift/add multiplication is cheap enough. */
3059 if (choose_mult_variant (wider_mode, cnst1, &alg, &variant,
3060 max_cost - extra_cost))
3062 /* See whether the specialized multiplication optabs are
3063 cheaper than the shift/add version. */
3064 tem = expand_mult_highpart_optab (mode, op0, op1, target,
3065 unsignedp, alg.cost + extra_cost);
3069 tem = convert_to_mode (wider_mode, op0, unsignedp);
3070 tem = expand_mult_const (wider_mode, tem, cnst1, 0, &alg, variant);
3071 tem = extract_high_half (mode, tem);
3073 /* Adjust result for signedness. */
3075 tem = force_operand (gen_rtx_MINUS (mode, tem, op0), tem);
3079 return expand_mult_highpart_optab (mode, op0, op1, target,
3080 unsignedp, max_cost);
3084 /* Expand signed modulus of OP0 by a power of two D in mode MODE. */
3087 expand_smod_pow2 (enum machine_mode mode, rtx op0, HOST_WIDE_INT d)
3089 unsigned HOST_WIDE_INT mask;
3090 rtx result, temp, shift, label;
3093 logd = floor_log2 (d);
3094 result = gen_reg_rtx (mode);
3096 /* Avoid conditional branches when they're expensive. */
3097 if (BRANCH_COST >= 2
3100 rtx signmask = emit_store_flag (result, LT, op0, const0_rtx,
3104 signmask = force_reg (mode, signmask);
3105 mask = ((HOST_WIDE_INT) 1 << logd) - 1;
3106 shift = GEN_INT (GET_MODE_BITSIZE (mode) - logd);
3108 /* Use the rtx_cost of a LSHIFTRT instruction to determine
3109 which instruction sequence to use. If logical right shifts
3110 are expensive the use 2 XORs, 2 SUBs and an AND, otherwise
3111 use a LSHIFTRT, 1 ADD, 1 SUB and an AND. */
3113 temp = gen_rtx_LSHIFTRT (mode, result, shift);
3114 if (lshr_optab->handlers[mode].insn_code == CODE_FOR_nothing
3115 || rtx_cost (temp, SET) > COSTS_N_INSNS (2))
3117 temp = expand_binop (mode, xor_optab, op0, signmask,
3118 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3119 temp = expand_binop (mode, sub_optab, temp, signmask,
3120 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3121 temp = expand_binop (mode, and_optab, temp, GEN_INT (mask),
3122 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3123 temp = expand_binop (mode, xor_optab, temp, signmask,
3124 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3125 temp = expand_binop (mode, sub_optab, temp, signmask,
3126 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3130 signmask = expand_binop (mode, lshr_optab, signmask, shift,
3131 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3132 signmask = force_reg (mode, signmask);
3134 temp = expand_binop (mode, add_optab, op0, signmask,
3135 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3136 temp = expand_binop (mode, and_optab, temp, GEN_INT (mask),
3137 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3138 temp = expand_binop (mode, sub_optab, temp, signmask,
3139 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3145 /* Mask contains the mode's signbit and the significant bits of the
3146 modulus. By including the signbit in the operation, many targets
3147 can avoid an explicit compare operation in the following comparison
3150 mask = (HOST_WIDE_INT) -1 << (GET_MODE_BITSIZE (mode) - 1)
3151 | (((HOST_WIDE_INT) 1 << logd) - 1);
3153 temp = expand_binop (mode, and_optab, op0, GEN_INT (mask), result,
3154 1, OPTAB_LIB_WIDEN);
3156 emit_move_insn (result, temp);
3158 label = gen_label_rtx ();
3159 do_cmp_and_jump (result, const0_rtx, GE, mode, label);
3161 temp = expand_binop (mode, sub_optab, result, const1_rtx, result,
3162 0, OPTAB_LIB_WIDEN);
3163 mask = (HOST_WIDE_INT) -1 << logd;
3164 temp = expand_binop (mode, ior_optab, temp, GEN_INT (mask), result,
3165 1, OPTAB_LIB_WIDEN);
3166 temp = expand_binop (mode, add_optab, temp, const1_rtx, result,
3167 0, OPTAB_LIB_WIDEN);
3169 emit_move_insn (result, temp);
3174 /* Emit the code to divide OP0 by OP1, putting the result in TARGET
3175 if that is convenient, and returning where the result is.
3176 You may request either the quotient or the remainder as the result;
3177 specify REM_FLAG nonzero to get the remainder.
3179 CODE is the expression code for which kind of division this is;
3180 it controls how rounding is done. MODE is the machine mode to use.
3181 UNSIGNEDP nonzero means do unsigned division. */
3183 /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
3184 and then correct it by or'ing in missing high bits
3185 if result of ANDI is nonzero.
3186 For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
3187 This could optimize to a bfexts instruction.
3188 But C doesn't use these operations, so their optimizations are
3190 /* ??? For modulo, we don't actually need the highpart of the first product,
3191 the low part will do nicely. And for small divisors, the second multiply
3192 can also be a low-part only multiply or even be completely left out.
3193 E.g. to calculate the remainder of a division by 3 with a 32 bit
3194 multiply, multiply with 0x55555556 and extract the upper two bits;
3195 the result is exact for inputs up to 0x1fffffff.
3196 The input range can be reduced by using cross-sum rules.
3197 For odd divisors >= 3, the following table gives right shift counts
3198 so that if a number is shifted by an integer multiple of the given
3199 amount, the remainder stays the same:
3200 2, 4, 3, 6, 10, 12, 4, 8, 18, 6, 11, 20, 18, 0, 5, 10, 12, 0, 12, 20,
3201 14, 12, 23, 21, 8, 0, 20, 18, 0, 0, 6, 12, 0, 22, 0, 18, 20, 30, 0, 0,
3202 0, 8, 0, 11, 12, 10, 36, 0, 30, 0, 0, 12, 0, 0, 0, 0, 44, 12, 24, 0,
3203 20, 0, 7, 14, 0, 18, 36, 0, 0, 46, 60, 0, 42, 0, 15, 24, 20, 0, 0, 33,
3204 0, 20, 0, 0, 18, 0, 60, 0, 0, 0, 0, 0, 40, 18, 0, 0, 12
3206 Cross-sum rules for even numbers can be derived by leaving as many bits
3207 to the right alone as the divisor has zeros to the right.
3208 E.g. if x is an unsigned 32 bit number:
3209 (x mod 12) == (((x & 1023) + ((x >> 8) & ~3)) * 0x15555558 >> 2 * 3) >> 28
3212 #define EXACT_POWER_OF_2_OR_ZERO_P(x) (((x) & ((x) - 1)) == 0)
3215 expand_divmod (int rem_flag, enum tree_code code, enum machine_mode mode,
3216 rtx op0, rtx op1, rtx target, int unsignedp)
3218 enum machine_mode compute_mode;
3220 rtx quotient = 0, remainder = 0;
3224 optab optab1, optab2;
3225 int op1_is_constant, op1_is_pow2 = 0;
3226 int max_cost, extra_cost;
3227 static HOST_WIDE_INT last_div_const = 0;
3228 static HOST_WIDE_INT ext_op1;
3230 op1_is_constant = GET_CODE (op1) == CONST_INT;
3231 if (op1_is_constant)
3233 ext_op1 = INTVAL (op1);
3235 ext_op1 &= GET_MODE_MASK (mode);
3236 op1_is_pow2 = ((EXACT_POWER_OF_2_OR_ZERO_P (ext_op1)
3237 || (! unsignedp && EXACT_POWER_OF_2_OR_ZERO_P (-ext_op1))));
3241 This is the structure of expand_divmod:
3243 First comes code to fix up the operands so we can perform the operations
3244 correctly and efficiently.
3246 Second comes a switch statement with code specific for each rounding mode.
3247 For some special operands this code emits all RTL for the desired
3248 operation, for other cases, it generates only a quotient and stores it in
3249 QUOTIENT. The case for trunc division/remainder might leave quotient = 0,
3250 to indicate that it has not done anything.
3252 Last comes code that finishes the operation. If QUOTIENT is set and
3253 REM_FLAG is set, the remainder is computed as OP0 - QUOTIENT * OP1. If
3254 QUOTIENT is not set, it is computed using trunc rounding.
3256 We try to generate special code for division and remainder when OP1 is a
3257 constant. If |OP1| = 2**n we can use shifts and some other fast
3258 operations. For other values of OP1, we compute a carefully selected
3259 fixed-point approximation m = 1/OP1, and generate code that multiplies OP0
3262 In all cases but EXACT_DIV_EXPR, this multiplication requires the upper
3263 half of the product. Different strategies for generating the product are
3264 implemented in expand_mult_highpart.
3266 If what we actually want is the remainder, we generate that by another
3267 by-constant multiplication and a subtraction. */
3269 /* We shouldn't be called with OP1 == const1_rtx, but some of the
3270 code below will malfunction if we are, so check here and handle
3271 the special case if so. */
3272 if (op1 == const1_rtx)
3273 return rem_flag ? const0_rtx : op0;
3275 /* When dividing by -1, we could get an overflow.
3276 negv_optab can handle overflows. */
3277 if (! unsignedp && op1 == constm1_rtx)
3281 return expand_unop (mode, flag_trapv && GET_MODE_CLASS(mode) == MODE_INT
3282 ? negv_optab : neg_optab, op0, target, 0);
3286 /* Don't use the function value register as a target
3287 since we have to read it as well as write it,
3288 and function-inlining gets confused by this. */
3289 && ((REG_P (target) && REG_FUNCTION_VALUE_P (target))
3290 /* Don't clobber an operand while doing a multi-step calculation. */
3291 || ((rem_flag || op1_is_constant)
3292 && (reg_mentioned_p (target, op0)
3293 || (MEM_P (op0) && MEM_P (target))))
3294 || reg_mentioned_p (target, op1)
3295 || (MEM_P (op1) && MEM_P (target))))
3298 /* Get the mode in which to perform this computation. Normally it will
3299 be MODE, but sometimes we can't do the desired operation in MODE.
3300 If so, pick a wider mode in which we can do the operation. Convert
3301 to that mode at the start to avoid repeated conversions.
3303 First see what operations we need. These depend on the expression
3304 we are evaluating. (We assume that divxx3 insns exist under the
3305 same conditions that modxx3 insns and that these insns don't normally
3306 fail. If these assumptions are not correct, we may generate less
3307 efficient code in some cases.)
3309 Then see if we find a mode in which we can open-code that operation
3310 (either a division, modulus, or shift). Finally, check for the smallest
3311 mode for which we can do the operation with a library call. */
3313 /* We might want to refine this now that we have division-by-constant
3314 optimization. Since expand_mult_highpart tries so many variants, it is
3315 not straightforward to generalize this. Maybe we should make an array
3316 of possible modes in init_expmed? Save this for GCC 2.7. */
3318 optab1 = ((op1_is_pow2 && op1 != const0_rtx)
3319 ? (unsignedp ? lshr_optab : ashr_optab)
3320 : (unsignedp ? udiv_optab : sdiv_optab));
3321 optab2 = ((op1_is_pow2 && op1 != const0_rtx)
3323 : (unsignedp ? udivmod_optab : sdivmod_optab));
3325 for (compute_mode = mode; compute_mode != VOIDmode;
3326 compute_mode = GET_MODE_WIDER_MODE (compute_mode))
3327 if (optab1->handlers[compute_mode].insn_code != CODE_FOR_nothing
3328 || optab2->handlers[compute_mode].insn_code != CODE_FOR_nothing)
3331 if (compute_mode == VOIDmode)
3332 for (compute_mode = mode; compute_mode != VOIDmode;
3333 compute_mode = GET_MODE_WIDER_MODE (compute_mode))
3334 if (optab1->handlers[compute_mode].libfunc
3335 || optab2->handlers[compute_mode].libfunc)
3338 /* If we still couldn't find a mode, use MODE, but we'll probably abort
3340 if (compute_mode == VOIDmode)
3341 compute_mode = mode;
3343 if (target && GET_MODE (target) == compute_mode)
3346 tquotient = gen_reg_rtx (compute_mode);
3348 size = GET_MODE_BITSIZE (compute_mode);
3350 /* It should be possible to restrict the precision to GET_MODE_BITSIZE
3351 (mode), and thereby get better code when OP1 is a constant. Do that
3352 later. It will require going over all usages of SIZE below. */
3353 size = GET_MODE_BITSIZE (mode);
3356 /* Only deduct something for a REM if the last divide done was
3357 for a different constant. Then set the constant of the last
3359 max_cost = div_cost[compute_mode]
3360 - (rem_flag && ! (last_div_const != 0 && op1_is_constant
3361 && INTVAL (op1) == last_div_const)
3362 ? mul_cost[compute_mode] + add_cost[compute_mode]
3365 last_div_const = ! rem_flag && op1_is_constant ? INTVAL (op1) : 0;
3367 /* Now convert to the best mode to use. */
3368 if (compute_mode != mode)
3370 op0 = convert_modes (compute_mode, mode, op0, unsignedp);
3371 op1 = convert_modes (compute_mode, mode, op1, unsignedp);
3373 /* convert_modes may have placed op1 into a register, so we
3374 must recompute the following. */
3375 op1_is_constant = GET_CODE (op1) == CONST_INT;
3376 op1_is_pow2 = (op1_is_constant
3377 && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1))
3379 && EXACT_POWER_OF_2_OR_ZERO_P (-INTVAL (op1)))))) ;
3382 /* If one of the operands is a volatile MEM, copy it into a register. */
3384 if (MEM_P (op0) && MEM_VOLATILE_P (op0))
3385 op0 = force_reg (compute_mode, op0);
3386 if (MEM_P (op1) && MEM_VOLATILE_P (op1))
3387 op1 = force_reg (compute_mode, op1);
3389 /* If we need the remainder or if OP1 is constant, we need to
3390 put OP0 in a register in case it has any queued subexpressions. */
3391 if (rem_flag || op1_is_constant)
3392 op0 = force_reg (compute_mode, op0);
3394 last = get_last_insn ();
3396 /* Promote floor rounding to trunc rounding for unsigned operations. */
3399 if (code == FLOOR_DIV_EXPR)
3400 code = TRUNC_DIV_EXPR;
3401 if (code == FLOOR_MOD_EXPR)
3402 code = TRUNC_MOD_EXPR;
3403 if (code == EXACT_DIV_EXPR && op1_is_pow2)
3404 code = TRUNC_DIV_EXPR;
3407 if (op1 != const0_rtx)
3410 case TRUNC_MOD_EXPR:
3411 case TRUNC_DIV_EXPR:
3412 if (op1_is_constant)
3416 unsigned HOST_WIDE_INT mh, ml;
3417 int pre_shift, post_shift;
3419 unsigned HOST_WIDE_INT d = (INTVAL (op1)
3420 & GET_MODE_MASK (compute_mode));
3422 if (EXACT_POWER_OF_2_OR_ZERO_P (d))
3424 pre_shift = floor_log2 (d);
3428 = expand_binop (compute_mode, and_optab, op0,
3429 GEN_INT (((HOST_WIDE_INT) 1 << pre_shift) - 1),
3433 return gen_lowpart (mode, remainder);
3435 quotient = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3436 build_int_2 (pre_shift, 0),
3439 else if (size <= HOST_BITS_PER_WIDE_INT)
3441 if (d >= ((unsigned HOST_WIDE_INT) 1 << (size - 1)))
3443 /* Most significant bit of divisor is set; emit an scc
3445 quotient = emit_store_flag (tquotient, GEU, op0, op1,
3446 compute_mode, 1, 1);
3452 /* Find a suitable multiplier and right shift count
3453 instead of multiplying with D. */
3455 mh = choose_multiplier (d, size, size,
3456 &ml, &post_shift, &dummy);
3458 /* If the suggested multiplier is more than SIZE bits,
3459 we can do better for even divisors, using an
3460 initial right shift. */
3461 if (mh != 0 && (d & 1) == 0)
3463 pre_shift = floor_log2 (d & -d);
3464 mh = choose_multiplier (d >> pre_shift, size,
3466 &ml, &post_shift, &dummy);
3477 if (post_shift - 1 >= BITS_PER_WORD)
3481 = (shift_cost[compute_mode][post_shift - 1]
3482 + shift_cost[compute_mode][1]
3483 + 2 * add_cost[compute_mode]);
3484 t1 = expand_mult_highpart (compute_mode, op0, ml,
3486 max_cost - extra_cost);
3489 t2 = force_operand (gen_rtx_MINUS (compute_mode,
3492 t3 = expand_shift (RSHIFT_EXPR, compute_mode, t2,
3493 build_int_2 (1, 0), NULL_RTX,1);
3494 t4 = force_operand (gen_rtx_PLUS (compute_mode,
3498 = expand_shift (RSHIFT_EXPR, compute_mode, t4,
3499 build_int_2 (post_shift - 1, 0),
3506 if (pre_shift >= BITS_PER_WORD
3507 || post_shift >= BITS_PER_WORD)
3510 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3511 build_int_2 (pre_shift, 0),
3514 = (shift_cost[compute_mode][pre_shift]
3515 + shift_cost[compute_mode][post_shift]);
3516 t2 = expand_mult_highpart (compute_mode, t1, ml,
3518 max_cost - extra_cost);
3522 = expand_shift (RSHIFT_EXPR, compute_mode, t2,
3523 build_int_2 (post_shift, 0),
3528 else /* Too wide mode to use tricky code */
3531 insn = get_last_insn ();
3533 && (set = single_set (insn)) != 0
3534 && SET_DEST (set) == quotient)
3535 set_unique_reg_note (insn,
3537 gen_rtx_UDIV (compute_mode, op0, op1));
3539 else /* TRUNC_DIV, signed */
3541 unsigned HOST_WIDE_INT ml;
3542 int lgup, post_shift;
3543 HOST_WIDE_INT d = INTVAL (op1);
3544 unsigned HOST_WIDE_INT abs_d = d >= 0 ? d : -d;
3546 /* n rem d = n rem -d */
3547 if (rem_flag && d < 0)
3550 op1 = gen_int_mode (abs_d, compute_mode);
3556 quotient = expand_unop (compute_mode, neg_optab, op0,
3558 else if (abs_d == (unsigned HOST_WIDE_INT) 1 << (size - 1))
3560 /* This case is not handled correctly below. */
3561 quotient = emit_store_flag (tquotient, EQ, op0, op1,
3562 compute_mode, 1, 1);
3566 else if (EXACT_POWER_OF_2_OR_ZERO_P (d)
3567 && (rem_flag ? smod_pow2_cheap[compute_mode]
3568 : sdiv_pow2_cheap[compute_mode])
3569 /* We assume that cheap metric is true if the
3570 optab has an expander for this mode. */
3571 && (((rem_flag ? smod_optab : sdiv_optab)
3572 ->handlers[compute_mode].insn_code
3573 != CODE_FOR_nothing)
3574 || (sdivmod_optab->handlers[compute_mode]
3575 .insn_code != CODE_FOR_nothing)))
3577 else if (EXACT_POWER_OF_2_OR_ZERO_P (abs_d))
3581 remainder = expand_smod_pow2 (compute_mode, op0, d);
3583 return gen_lowpart (mode, remainder);
3585 lgup = floor_log2 (abs_d);
3586 if (BRANCH_COST < 1 || (abs_d != 2 && BRANCH_COST < 3))
3588 rtx label = gen_label_rtx ();
3591 t1 = copy_to_mode_reg (compute_mode, op0);
3592 do_cmp_and_jump (t1, const0_rtx, GE,
3593 compute_mode, label);
3594 expand_inc (t1, gen_int_mode (abs_d - 1,
3597 quotient = expand_shift (RSHIFT_EXPR, compute_mode, t1,
3598 build_int_2 (lgup, 0),
3604 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3605 build_int_2 (size - 1, 0),
3607 t2 = expand_shift (RSHIFT_EXPR, compute_mode, t1,
3608 build_int_2 (size - lgup, 0),
3610 t3 = force_operand (gen_rtx_PLUS (compute_mode,
3613 quotient = expand_shift (RSHIFT_EXPR, compute_mode, t3,
3614 build_int_2 (lgup, 0),
3618 /* We have computed OP0 / abs(OP1). If OP1 is negative,
3619 negate the quotient. */
3622 insn = get_last_insn ();
3624 && (set = single_set (insn)) != 0
3625 && SET_DEST (set) == quotient
3626 && abs_d < ((unsigned HOST_WIDE_INT) 1
3627 << (HOST_BITS_PER_WIDE_INT - 1)))
3628 set_unique_reg_note (insn,
3630 gen_rtx_DIV (compute_mode,
3637 quotient = expand_unop (compute_mode, neg_optab,
3638 quotient, quotient, 0);
3641 else if (size <= HOST_BITS_PER_WIDE_INT)
3643 choose_multiplier (abs_d, size, size - 1,
3644 &ml, &post_shift, &lgup);
3645 if (ml < (unsigned HOST_WIDE_INT) 1 << (size - 1))
3649 if (post_shift >= BITS_PER_WORD
3650 || size - 1 >= BITS_PER_WORD)
3653 extra_cost = (shift_cost[compute_mode][post_shift]
3654 + shift_cost[compute_mode][size - 1]
3655 + add_cost[compute_mode]);
3656 t1 = expand_mult_highpart (compute_mode, op0, ml,
3658 max_cost - extra_cost);
3661 t2 = expand_shift (RSHIFT_EXPR, compute_mode, t1,
3662 build_int_2 (post_shift, 0), NULL_RTX, 0);
3663 t3 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3664 build_int_2 (size - 1, 0), NULL_RTX, 0);
3667 = force_operand (gen_rtx_MINUS (compute_mode,
3672 = force_operand (gen_rtx_MINUS (compute_mode,
3680 if (post_shift >= BITS_PER_WORD
3681 || size - 1 >= BITS_PER_WORD)
3684 ml |= (~(unsigned HOST_WIDE_INT) 0) << (size - 1);
3685 extra_cost = (shift_cost[compute_mode][post_shift]
3686 + shift_cost[compute_mode][size - 1]
3687 + 2 * add_cost[compute_mode]);
3688 t1 = expand_mult_highpart (compute_mode, op0, ml,
3690 max_cost - extra_cost);
3693 t2 = force_operand (gen_rtx_PLUS (compute_mode,
3696 t3 = expand_shift (RSHIFT_EXPR, compute_mode, t2,
3697 build_int_2 (post_shift, 0),
3699 t4 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3700 build_int_2 (size - 1, 0),
3704 = force_operand (gen_rtx_MINUS (compute_mode,
3709 = force_operand (gen_rtx_MINUS (compute_mode,
3714 else /* Too wide mode to use tricky code */
3717 insn = get_last_insn ();
3719 && (set = single_set (insn)) != 0
3720 && SET_DEST (set) == quotient)
3721 set_unique_reg_note (insn,
3723 gen_rtx_DIV (compute_mode, op0, op1));
3728 delete_insns_since (last);
3731 case FLOOR_DIV_EXPR:
3732 case FLOOR_MOD_EXPR:
3733 /* We will come here only for signed operations. */
3734 if (op1_is_constant && HOST_BITS_PER_WIDE_INT >= size)
3736 unsigned HOST_WIDE_INT mh, ml;
3737 int pre_shift, lgup, post_shift;
3738 HOST_WIDE_INT d = INTVAL (op1);
3742 /* We could just as easily deal with negative constants here,
3743 but it does not seem worth the trouble for GCC 2.6. */
3744 if (EXACT_POWER_OF_2_OR_ZERO_P (d))
3746 pre_shift = floor_log2 (d);
3749 remainder = expand_binop (compute_mode, and_optab, op0,
3750 GEN_INT (((HOST_WIDE_INT) 1 << pre_shift) - 1),
3751 remainder, 0, OPTAB_LIB_WIDEN);
3753 return gen_lowpart (mode, remainder);
3755 quotient = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3756 build_int_2 (pre_shift, 0),
3763 mh = choose_multiplier (d, size, size - 1,
3764 &ml, &post_shift, &lgup);
3768 if (post_shift < BITS_PER_WORD
3769 && size - 1 < BITS_PER_WORD)
3771 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3772 build_int_2 (size - 1, 0),
3774 t2 = expand_binop (compute_mode, xor_optab, op0, t1,
3775 NULL_RTX, 0, OPTAB_WIDEN);
3776 extra_cost = (shift_cost[compute_mode][post_shift]
3777 + shift_cost[compute_mode][size - 1]
3778 + 2 * add_cost[compute_mode]);
3779 t3 = expand_mult_highpart (compute_mode, t2, ml,
3781 max_cost - extra_cost);
3784 t4 = expand_shift (RSHIFT_EXPR, compute_mode, t3,
3785 build_int_2 (post_shift, 0),
3787 quotient = expand_binop (compute_mode, xor_optab,
3788 t4, t1, tquotient, 0,
3796 rtx nsign, t1, t2, t3, t4;
3797 t1 = force_operand (gen_rtx_PLUS (compute_mode,
3798 op0, constm1_rtx), NULL_RTX);
3799 t2 = expand_binop (compute_mode, ior_optab, op0, t1, NULL_RTX,
3801 nsign = expand_shift (RSHIFT_EXPR, compute_mode, t2,
3802 build_int_2 (size - 1, 0), NULL_RTX, 0);
3803 t3 = force_operand (gen_rtx_MINUS (compute_mode, t1, nsign),
3805 t4 = expand_divmod (0, TRUNC_DIV_EXPR, compute_mode, t3, op1,
3810 t5 = expand_unop (compute_mode, one_cmpl_optab, nsign,
3812 quotient = force_operand (gen_rtx_PLUS (compute_mode,
3821 delete_insns_since (last);
3823 /* Try using an instruction that produces both the quotient and
3824 remainder, using truncation. We can easily compensate the quotient
3825 or remainder to get floor rounding, once we have the remainder.
3826 Notice that we compute also the final remainder value here,
3827 and return the result right away. */
3828 if (target == 0 || GET_MODE (target) != compute_mode)
3829 target = gen_reg_rtx (compute_mode);
3834 = REG_P (target) ? target : gen_reg_rtx (compute_mode);
3835 quotient = gen_reg_rtx (compute_mode);
3840 = REG_P (target) ? target : gen_reg_rtx (compute_mode);
3841 remainder = gen_reg_rtx (compute_mode);
3844 if (expand_twoval_binop (sdivmod_optab, op0, op1,
3845 quotient, remainder, 0))
3847 /* This could be computed with a branch-less sequence.
3848 Save that for later. */
3850 rtx label = gen_label_rtx ();
3851 do_cmp_and_jump (remainder, const0_rtx, EQ, compute_mode, label);
3852 tem = expand_binop (compute_mode, xor_optab, op0, op1,
3853 NULL_RTX, 0, OPTAB_WIDEN);
3854 do_cmp_and_jump (tem, const0_rtx, GE, compute_mode, label);
3855 expand_dec (quotient, const1_rtx);
3856 expand_inc (remainder, op1);
3858 return gen_lowpart (mode, rem_flag ? remainder : quotient);
3861 /* No luck with division elimination or divmod. Have to do it
3862 by conditionally adjusting op0 *and* the result. */
3864 rtx label1, label2, label3, label4, label5;
3868 quotient = gen_reg_rtx (compute_mode);
3869 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
3870 label1 = gen_label_rtx ();
3871 label2 = gen_label_rtx ();
3872 label3 = gen_label_rtx ();
3873 label4 = gen_label_rtx ();
3874 label5 = gen_label_rtx ();
3875 do_cmp_and_jump (op1, const0_rtx, LT, compute_mode, label2);
3876 do_cmp_and_jump (adjusted_op0, const0_rtx, LT, compute_mode, label1);
3877 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3878 quotient, 0, OPTAB_LIB_WIDEN);
3879 if (tem != quotient)
3880 emit_move_insn (quotient, tem);
3881 emit_jump_insn (gen_jump (label5));
3883 emit_label (label1);
3884 expand_inc (adjusted_op0, const1_rtx);
3885 emit_jump_insn (gen_jump (label4));
3887 emit_label (label2);
3888 do_cmp_and_jump (adjusted_op0, const0_rtx, GT, compute_mode, label3);
3889 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3890 quotient, 0, OPTAB_LIB_WIDEN);
3891 if (tem != quotient)
3892 emit_move_insn (quotient, tem);
3893 emit_jump_insn (gen_jump (label5));
3895 emit_label (label3);
3896 expand_dec (adjusted_op0, const1_rtx);
3897 emit_label (label4);
3898 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3899 quotient, 0, OPTAB_LIB_WIDEN);
3900 if (tem != quotient)
3901 emit_move_insn (quotient, tem);
3902 expand_dec (quotient, const1_rtx);
3903 emit_label (label5);
3911 if (op1_is_constant && EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1)))
3914 unsigned HOST_WIDE_INT d = INTVAL (op1);
3915 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3916 build_int_2 (floor_log2 (d), 0),
3918 t2 = expand_binop (compute_mode, and_optab, op0,
3920 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3921 t3 = gen_reg_rtx (compute_mode);
3922 t3 = emit_store_flag (t3, NE, t2, const0_rtx,
3923 compute_mode, 1, 1);
3927 lab = gen_label_rtx ();
3928 do_cmp_and_jump (t2, const0_rtx, EQ, compute_mode, lab);
3929 expand_inc (t1, const1_rtx);
3934 quotient = force_operand (gen_rtx_PLUS (compute_mode,
3940 /* Try using an instruction that produces both the quotient and
3941 remainder, using truncation. We can easily compensate the
3942 quotient or remainder to get ceiling rounding, once we have the
3943 remainder. Notice that we compute also the final remainder
3944 value here, and return the result right away. */
3945 if (target == 0 || GET_MODE (target) != compute_mode)
3946 target = gen_reg_rtx (compute_mode);
3950 remainder = (REG_P (target)
3951 ? target : gen_reg_rtx (compute_mode));
3952 quotient = gen_reg_rtx (compute_mode);
3956 quotient = (REG_P (target)
3957 ? target : gen_reg_rtx (compute_mode));
3958 remainder = gen_reg_rtx (compute_mode);
3961 if (expand_twoval_binop (udivmod_optab, op0, op1, quotient,
3964 /* This could be computed with a branch-less sequence.
3965 Save that for later. */
3966 rtx label = gen_label_rtx ();
3967 do_cmp_and_jump (remainder, const0_rtx, EQ,
3968 compute_mode, label);
3969 expand_inc (quotient, const1_rtx);
3970 expand_dec (remainder, op1);
3972 return gen_lowpart (mode, rem_flag ? remainder : quotient);
3975 /* No luck with division elimination or divmod. Have to do it
3976 by conditionally adjusting op0 *and* the result. */
3979 rtx adjusted_op0, tem;
3981 quotient = gen_reg_rtx (compute_mode);
3982 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
3983 label1 = gen_label_rtx ();
3984 label2 = gen_label_rtx ();
3985 do_cmp_and_jump (adjusted_op0, const0_rtx, NE,
3986 compute_mode, label1);
3987 emit_move_insn (quotient, const0_rtx);
3988 emit_jump_insn (gen_jump (label2));
3990 emit_label (label1);
3991 expand_dec (adjusted_op0, const1_rtx);
3992 tem = expand_binop (compute_mode, udiv_optab, adjusted_op0, op1,
3993 quotient, 1, OPTAB_LIB_WIDEN);
3994 if (tem != quotient)
3995 emit_move_insn (quotient, tem);
3996 expand_inc (quotient, const1_rtx);
3997 emit_label (label2);
4002 if (op1_is_constant && EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1))
4003 && INTVAL (op1) >= 0)
4005 /* This is extremely similar to the code for the unsigned case
4006 above. For 2.7 we should merge these variants, but for
4007 2.6.1 I don't want to touch the code for unsigned since that
4008 get used in C. The signed case will only be used by other
4012 unsigned HOST_WIDE_INT d = INTVAL (op1);
4013 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
4014 build_int_2 (floor_log2 (d), 0),
4016 t2 = expand_binop (compute_mode, and_optab, op0,
4018 NULL_RTX, 1, OPTAB_LIB_WIDEN);
4019 t3 = gen_reg_rtx (compute_mode);
4020 t3 = emit_store_flag (t3, NE, t2, const0_rtx,
4021 compute_mode, 1, 1);
4025 lab = gen_label_rtx ();
4026 do_cmp_and_jump (t2, const0_rtx, EQ, compute_mode, lab);
4027 expand_inc (t1, const1_rtx);
4032 quotient = force_operand (gen_rtx_PLUS (compute_mode,
4038 /* Try using an instruction that produces both the quotient and
4039 remainder, using truncation. We can easily compensate the
4040 quotient or remainder to get ceiling rounding, once we have the
4041 remainder. Notice that we compute also the final remainder
4042 value here, and return the result right away. */
4043 if (target == 0 || GET_MODE (target) != compute_mode)
4044 target = gen_reg_rtx (compute_mode);
4047 remainder= (REG_P (target)
4048 ? target : gen_reg_rtx (compute_mode));
4049 quotient = gen_reg_rtx (compute_mode);
4053 quotient = (REG_P (target)
4054 ? target : gen_reg_rtx (compute_mode));
4055 remainder = gen_reg_rtx (compute_mode);
4058 if (expand_twoval_binop (sdivmod_optab, op0, op1, quotient,
4061 /* This could be computed with a branch-less sequence.
4062 Save that for later. */
4064 rtx label = gen_label_rtx ();
4065 do_cmp_and_jump (remainder, const0_rtx, EQ,
4066 compute_mode, label);
4067 tem = expand_binop (compute_mode, xor_optab, op0, op1,
4068 NULL_RTX, 0, OPTAB_WIDEN);
4069 do_cmp_and_jump (tem, const0_rtx, LT, compute_mode, label);
4070 expand_inc (quotient, const1_rtx);
4071 expand_dec (remainder, op1);
4073 return gen_lowpart (mode, rem_flag ? remainder : quotient);
4076 /* No luck with division elimination or divmod. Have to do it
4077 by conditionally adjusting op0 *and* the result. */
4079 rtx label1, label2, label3, label4, label5;
4083 quotient = gen_reg_rtx (compute_mode);
4084 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
4085 label1 = gen_label_rtx ();
4086 label2 = gen_label_rtx ();
4087 label3 = gen_label_rtx ();
4088 label4 = gen_label_rtx ();
4089 label5 = gen_label_rtx ();
4090 do_cmp_and_jump (op1, const0_rtx, LT, compute_mode, label2);
4091 do_cmp_and_jump (adjusted_op0, const0_rtx, GT,
4092 compute_mode, label1);
4093 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
4094 quotient, 0, OPTAB_LIB_WIDEN);
4095 if (tem != quotient)
4096 emit_move_insn (quotient, tem);
4097 emit_jump_insn (gen_jump (label5));
4099 emit_label (label1);
4100 expand_dec (adjusted_op0, const1_rtx);
4101 emit_jump_insn (gen_jump (label4));
4103 emit_label (label2);
4104 do_cmp_and_jump (adjusted_op0, const0_rtx, LT,
4105 compute_mode, label3);
4106 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
4107 quotient, 0, OPTAB_LIB_WIDEN);
4108 if (tem != quotient)
4109 emit_move_insn (quotient, tem);
4110 emit_jump_insn (gen_jump (label5));
4112 emit_label (label3);
4113 expand_inc (adjusted_op0, const1_rtx);
4114 emit_label (label4);
4115 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
4116 quotient, 0, OPTAB_LIB_WIDEN);
4117 if (tem != quotient)
4118 emit_move_insn (quotient, tem);
4119 expand_inc (quotient, const1_rtx);
4120 emit_label (label5);
4125 case EXACT_DIV_EXPR:
4126 if (op1_is_constant && HOST_BITS_PER_WIDE_INT >= size)
4128 HOST_WIDE_INT d = INTVAL (op1);
4129 unsigned HOST_WIDE_INT ml;
4133 pre_shift = floor_log2 (d & -d);
4134 ml = invert_mod2n (d >> pre_shift, size);
4135 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
4136 build_int_2 (pre_shift, 0), NULL_RTX, unsignedp);
4137 quotient = expand_mult (compute_mode, t1,
4138 gen_int_mode (ml, compute_mode),
4141 insn = get_last_insn ();
4142 set_unique_reg_note (insn,
4144 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
4150 case ROUND_DIV_EXPR:
4151 case ROUND_MOD_EXPR:
4156 label = gen_label_rtx ();
4157 quotient = gen_reg_rtx (compute_mode);
4158 remainder = gen_reg_rtx (compute_mode);
4159 if (expand_twoval_binop (udivmod_optab, op0, op1, quotient, remainder, 1) == 0)
4162 quotient = expand_binop (compute_mode, udiv_optab, op0, op1,
4163 quotient, 1, OPTAB_LIB_WIDEN);
4164 tem = expand_mult (compute_mode, quotient, op1, NULL_RTX, 1);
4165 remainder = expand_binop (compute_mode, sub_optab, op0, tem,
4166 remainder, 1, OPTAB_LIB_WIDEN);
4168 tem = plus_constant (op1, -1);
4169 tem = expand_shift (RSHIFT_EXPR, compute_mode, tem,
4170 build_int_2 (1, 0), NULL_RTX, 1);
4171 do_cmp_and_jump (remainder, tem, LEU, compute_mode, label);
4172 expand_inc (quotient, const1_rtx);
4173 expand_dec (remainder, op1);
4178 rtx abs_rem, abs_op1, tem, mask;
4180 label = gen_label_rtx ();
4181 quotient = gen_reg_rtx (compute_mode);
4182 remainder = gen_reg_rtx (compute_mode);
4183 if (expand_twoval_binop (sdivmod_optab, op0, op1, quotient, remainder, 0) == 0)
4186 quotient = expand_binop (compute_mode, sdiv_optab, op0, op1,
4187 quotient, 0, OPTAB_LIB_WIDEN);
4188 tem = expand_mult (compute_mode, quotient, op1, NULL_RTX, 0);
4189 remainder = expand_binop (compute_mode, sub_optab, op0, tem,
4190 remainder, 0, OPTAB_LIB_WIDEN);
4192 abs_rem = expand_abs (compute_mode, remainder, NULL_RTX, 1, 0);
4193 abs_op1 = expand_abs (compute_mode, op1, NULL_RTX, 1, 0);
4194 tem = expand_shift (LSHIFT_EXPR, compute_mode, abs_rem,
4195 build_int_2 (1, 0), NULL_RTX, 1);
4196 do_cmp_and_jump (tem, abs_op1, LTU, compute_mode, label);
4197 tem = expand_binop (compute_mode, xor_optab, op0, op1,
4198 NULL_RTX, 0, OPTAB_WIDEN);
4199 mask = expand_shift (RSHIFT_EXPR, compute_mode, tem,
4200 build_int_2 (size - 1, 0), NULL_RTX, 0);
4201 tem = expand_binop (compute_mode, xor_optab, mask, const1_rtx,
4202 NULL_RTX, 0, OPTAB_WIDEN);
4203 tem = expand_binop (compute_mode, sub_optab, tem, mask,
4204 NULL_RTX, 0, OPTAB_WIDEN);
4205 expand_inc (quotient, tem);
4206 tem = expand_binop (compute_mode, xor_optab, mask, op1,
4207 NULL_RTX, 0, OPTAB_WIDEN);
4208 tem = expand_binop (compute_mode, sub_optab, tem, mask,
4209 NULL_RTX, 0, OPTAB_WIDEN);
4210 expand_dec (remainder, tem);
4213 return gen_lowpart (mode, rem_flag ? remainder : quotient);
4221 if (target && GET_MODE (target) != compute_mode)
4226 /* Try to produce the remainder without producing the quotient.
4227 If we seem to have a divmod pattern that does not require widening,
4228 don't try widening here. We should really have a WIDEN argument
4229 to expand_twoval_binop, since what we'd really like to do here is
4230 1) try a mod insn in compute_mode
4231 2) try a divmod insn in compute_mode
4232 3) try a div insn in compute_mode and multiply-subtract to get
4234 4) try the same things with widening allowed. */
4236 = sign_expand_binop (compute_mode, umod_optab, smod_optab,
4239 ((optab2->handlers[compute_mode].insn_code
4240 != CODE_FOR_nothing)
4241 ? OPTAB_DIRECT : OPTAB_WIDEN));
4244 /* No luck there. Can we do remainder and divide at once
4245 without a library call? */
4246 remainder = gen_reg_rtx (compute_mode);
4247 if (! expand_twoval_binop ((unsignedp
4251 NULL_RTX, remainder, unsignedp))
4256 return gen_lowpart (mode, remainder);
4259 /* Produce the quotient. Try a quotient insn, but not a library call.
4260 If we have a divmod in this mode, use it in preference to widening
4261 the div (for this test we assume it will not fail). Note that optab2
4262 is set to the one of the two optabs that the call below will use. */
4264 = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab,
4265 op0, op1, rem_flag ? NULL_RTX : target,
4267 ((optab2->handlers[compute_mode].insn_code
4268 != CODE_FOR_nothing)
4269 ? OPTAB_DIRECT : OPTAB_WIDEN));
4273 /* No luck there. Try a quotient-and-remainder insn,
4274 keeping the quotient alone. */
4275 quotient = gen_reg_rtx (compute_mode);
4276 if (! expand_twoval_binop (unsignedp ? udivmod_optab : sdivmod_optab,
4278 quotient, NULL_RTX, unsignedp))
4282 /* Still no luck. If we are not computing the remainder,
4283 use a library call for the quotient. */
4284 quotient = sign_expand_binop (compute_mode,
4285 udiv_optab, sdiv_optab,
4287 unsignedp, OPTAB_LIB_WIDEN);
4294 if (target && GET_MODE (target) != compute_mode)
4298 /* No divide instruction either. Use library for remainder. */
4299 remainder = sign_expand_binop (compute_mode, umod_optab, smod_optab,
4301 unsignedp, OPTAB_LIB_WIDEN);
4304 /* We divided. Now finish doing X - Y * (X / Y). */
4305 remainder = expand_mult (compute_mode, quotient, op1,
4306 NULL_RTX, unsignedp);
4307 remainder = expand_binop (compute_mode, sub_optab, op0,
4308 remainder, target, unsignedp,
4313 return gen_lowpart (mode, rem_flag ? remainder : quotient);
4316 /* Return a tree node with data type TYPE, describing the value of X.
4317 Usually this is an RTL_EXPR, if there is no obvious better choice.
4318 X may be an expression, however we only support those expressions
4319 generated by loop.c. */
4322 make_tree (tree type, rtx x)
4326 switch (GET_CODE (x))
4329 t = build_int_2 (INTVAL (x),
4330 (TYPE_UNSIGNED (type)
4331 && (GET_MODE_BITSIZE (TYPE_MODE (type))
4332 < HOST_BITS_PER_WIDE_INT))
4333 || INTVAL (x) >= 0 ? 0 : -1);
4334 TREE_TYPE (t) = type;
4338 if (GET_MODE (x) == VOIDmode)
4340 t = build_int_2 (CONST_DOUBLE_LOW (x), CONST_DOUBLE_HIGH (x));
4341 TREE_TYPE (t) = type;
4347 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
4348 t = build_real (type, d);
4359 units = CONST_VECTOR_NUNITS (x);
4361 /* Build a tree with vector elements. */
4362 for (i = units - 1; i >= 0; --i)
4364 elt = CONST_VECTOR_ELT (x, i);
4365 t = tree_cons (NULL_TREE, make_tree (type, elt), t);
4368 return build_vector (type, t);
4372 return fold (build (PLUS_EXPR, type, make_tree (type, XEXP (x, 0)),
4373 make_tree (type, XEXP (x, 1))));
4376 return fold (build (MINUS_EXPR, type, make_tree (type, XEXP (x, 0)),
4377 make_tree (type, XEXP (x, 1))));
4380 return fold (build1 (NEGATE_EXPR, type, make_tree (type, XEXP (x, 0))));
4383 return fold (build (MULT_EXPR, type, make_tree (type, XEXP (x, 0)),
4384 make_tree (type, XEXP (x, 1))));
4387 return fold (build (LSHIFT_EXPR, type, make_tree (type, XEXP (x, 0)),
4388 make_tree (type, XEXP (x, 1))));
4391 t = lang_hooks.types.unsigned_type (type);
4392 return fold (convert (type,
4393 build (RSHIFT_EXPR, t,
4394 make_tree (t, XEXP (x, 0)),
4395 make_tree (type, XEXP (x, 1)))));
4398 t = lang_hooks.types.signed_type (type);
4399 return fold (convert (type,
4400 build (RSHIFT_EXPR, t,
4401 make_tree (t, XEXP (x, 0)),
4402 make_tree (type, XEXP (x, 1)))));
4405 if (TREE_CODE (type) != REAL_TYPE)
4406 t = lang_hooks.types.signed_type (type);
4410 return fold (convert (type,
4411 build (TRUNC_DIV_EXPR, t,
4412 make_tree (t, XEXP (x, 0)),
4413 make_tree (t, XEXP (x, 1)))));
4415 t = lang_hooks.types.unsigned_type (type);
4416 return fold (convert (type,
4417 build (TRUNC_DIV_EXPR, t,
4418 make_tree (t, XEXP (x, 0)),
4419 make_tree (t, XEXP (x, 1)))));
4423 t = lang_hooks.types.type_for_mode (GET_MODE (XEXP (x, 0)),
4424 GET_CODE (x) == ZERO_EXTEND);
4425 return fold (convert (type, make_tree (t, XEXP (x, 0))));
4428 t = make_node (RTL_EXPR);
4429 TREE_TYPE (t) = type;
4431 /* If TYPE is a POINTER_TYPE, X might be Pmode with TYPE_MODE being
4432 ptr_mode. So convert. */
4433 if (POINTER_TYPE_P (type))
4434 x = convert_memory_address (TYPE_MODE (type), x);
4436 RTL_EXPR_RTL (t) = x;
4437 /* There are no insns to be output
4438 when this rtl_expr is used. */
4439 RTL_EXPR_SEQUENCE (t) = 0;
4444 /* Check whether the multiplication X * MULT + ADD overflows.
4445 X, MULT and ADD must be CONST_*.
4446 MODE is the machine mode for the computation.
4447 X and MULT must have mode MODE. ADD may have a different mode.
4448 So can X (defaults to same as MODE).
4449 UNSIGNEDP is nonzero to do unsigned multiplication. */
4452 const_mult_add_overflow_p (rtx x, rtx mult, rtx add, enum machine_mode mode, int unsignedp)
4454 tree type, mult_type, add_type, result;
4456 type = lang_hooks.types.type_for_mode (mode, unsignedp);
4458 /* In order to get a proper overflow indication from an unsigned
4459 type, we have to pretend that it's a sizetype. */
4463 mult_type = copy_node (type);
4464 TYPE_IS_SIZETYPE (mult_type) = 1;
4467 add_type = (GET_MODE (add) == VOIDmode ? mult_type
4468 : lang_hooks.types.type_for_mode (GET_MODE (add), unsignedp));
4470 result = fold (build (PLUS_EXPR, mult_type,
4471 fold (build (MULT_EXPR, mult_type,
4472 make_tree (mult_type, x),
4473 make_tree (mult_type, mult))),
4474 make_tree (add_type, add)));
4476 return TREE_CONSTANT_OVERFLOW (result);
4479 /* Return an rtx representing the value of X * MULT + ADD.
4480 TARGET is a suggestion for where to store the result (an rtx).
4481 MODE is the machine mode for the computation.
4482 X and MULT must have mode MODE. ADD may have a different mode.
4483 So can X (defaults to same as MODE).
4484 UNSIGNEDP is nonzero to do unsigned multiplication.
4485 This may emit insns. */
4488 expand_mult_add (rtx x, rtx target, rtx mult, rtx add, enum machine_mode mode,
4491 tree type = lang_hooks.types.type_for_mode (mode, unsignedp);
4492 tree add_type = (GET_MODE (add) == VOIDmode
4493 ? type: lang_hooks.types.type_for_mode (GET_MODE (add),
4495 tree result = fold (build (PLUS_EXPR, type,
4496 fold (build (MULT_EXPR, type,
4497 make_tree (type, x),
4498 make_tree (type, mult))),
4499 make_tree (add_type, add)));
4501 return expand_expr (result, target, VOIDmode, 0);
4504 /* Compute the logical-and of OP0 and OP1, storing it in TARGET
4505 and returning TARGET.
4507 If TARGET is 0, a pseudo-register or constant is returned. */
4510 expand_and (enum machine_mode mode, rtx op0, rtx op1, rtx target)
4514 if (GET_MODE (op0) == VOIDmode && GET_MODE (op1) == VOIDmode)
4515 tem = simplify_binary_operation (AND, mode, op0, op1);
4517 tem = expand_binop (mode, and_optab, op0, op1, target, 0, OPTAB_LIB_WIDEN);
4521 else if (tem != target)
4522 emit_move_insn (target, tem);
4526 /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
4527 and storing in TARGET. Normally return TARGET.
4528 Return 0 if that cannot be done.
4530 MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
4531 it is VOIDmode, they cannot both be CONST_INT.
4533 UNSIGNEDP is for the case where we have to widen the operands
4534 to perform the operation. It says to use zero-extension.
4536 NORMALIZEP is 1 if we should convert the result to be either zero
4537 or one. Normalize is -1 if we should convert the result to be
4538 either zero or -1. If NORMALIZEP is zero, the result will be left
4539 "raw" out of the scc insn. */
4542 emit_store_flag (rtx target, enum rtx_code code, rtx op0, rtx op1,
4543 enum machine_mode mode, int unsignedp, int normalizep)
4546 enum insn_code icode;
4547 enum machine_mode compare_mode;
4548 enum machine_mode target_mode = GET_MODE (target);
4550 rtx last = get_last_insn ();
4551 rtx pattern, comparison;
4553 /* ??? Ok to do this and then fail? */
4554 op0 = protect_from_queue (op0, 0);
4555 op1 = protect_from_queue (op1, 0);
4558 code = unsigned_condition (code);
4560 /* If one operand is constant, make it the second one. Only do this
4561 if the other operand is not constant as well. */
4563 if (swap_commutative_operands_p (op0, op1))
4568 code = swap_condition (code);
4571 if (mode == VOIDmode)
4572 mode = GET_MODE (op0);
4574 /* For some comparisons with 1 and -1, we can convert this to
4575 comparisons with zero. This will often produce more opportunities for
4576 store-flag insns. */
4581 if (op1 == const1_rtx)
4582 op1 = const0_rtx, code = LE;
4585 if (op1 == constm1_rtx)
4586 op1 = const0_rtx, code = LT;
4589 if (op1 == const1_rtx)
4590 op1 = const0_rtx, code = GT;
4593 if (op1 == constm1_rtx)
4594 op1 = const0_rtx, code = GE;
4597 if (op1 == const1_rtx)
4598 op1 = const0_rtx, code = NE;
4601 if (op1 == const1_rtx)
4602 op1 = const0_rtx, code = EQ;
4608 /* If we are comparing a double-word integer with zero, we can convert
4609 the comparison into one involving a single word. */
4610 if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD * 2
4611 && GET_MODE_CLASS (mode) == MODE_INT
4612 && op1 == const0_rtx
4613 && (!MEM_P (op0) || ! MEM_VOLATILE_P (op0)))
4615 if (code == EQ || code == NE)
4617 rtx op00, op01, op0both;
4619 /* Do a logical OR of the two words and compare the result. */
4620 op00 = simplify_gen_subreg (word_mode, op0, mode, 0);
4621 op01 = simplify_gen_subreg (word_mode, op0, mode, UNITS_PER_WORD);
4622 op0both = expand_binop (word_mode, ior_optab, op00, op01,
4623 NULL_RTX, unsignedp, OPTAB_DIRECT);
4625 return emit_store_flag (target, code, op0both, op1, word_mode,
4626 unsignedp, normalizep);
4628 else if (code == LT || code == GE)
4632 /* If testing the sign bit, can just test on high word. */
4633 op0h = simplify_gen_subreg (word_mode, op0, mode,
4634 subreg_highpart_offset (word_mode, mode));
4635 return emit_store_flag (target, code, op0h, op1, word_mode,
4636 unsignedp, normalizep);
4640 /* From now on, we won't change CODE, so set ICODE now. */
4641 icode = setcc_gen_code[(int) code];
4643 /* If this is A < 0 or A >= 0, we can do this by taking the ones
4644 complement of A (for GE) and shifting the sign bit to the low bit. */
4645 if (op1 == const0_rtx && (code == LT || code == GE)
4646 && GET_MODE_CLASS (mode) == MODE_INT
4647 && (normalizep || STORE_FLAG_VALUE == 1
4648 || (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4649 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4650 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)))))
4654 /* If the result is to be wider than OP0, it is best to convert it
4655 first. If it is to be narrower, it is *incorrect* to convert it
4657 if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (mode))
4659 op0 = protect_from_queue (op0, 0);
4660 op0 = convert_modes (target_mode, mode, op0, 0);
4664 if (target_mode != mode)
4668 op0 = expand_unop (mode, one_cmpl_optab, op0,
4669 ((STORE_FLAG_VALUE == 1 || normalizep)
4670 ? 0 : subtarget), 0);
4672 if (STORE_FLAG_VALUE == 1 || normalizep)
4673 /* If we are supposed to produce a 0/1 value, we want to do
4674 a logical shift from the sign bit to the low-order bit; for
4675 a -1/0 value, we do an arithmetic shift. */
4676 op0 = expand_shift (RSHIFT_EXPR, mode, op0,
4677 size_int (GET_MODE_BITSIZE (mode) - 1),
4678 subtarget, normalizep != -1);
4680 if (mode != target_mode)
4681 op0 = convert_modes (target_mode, mode, op0, 0);
4686 if (icode != CODE_FOR_nothing)
4688 insn_operand_predicate_fn pred;
4690 /* We think we may be able to do this with a scc insn. Emit the
4691 comparison and then the scc insn.
4693 compare_from_rtx may call emit_queue, which would be deleted below
4694 if the scc insn fails. So call it ourselves before setting LAST.
4695 Likewise for do_pending_stack_adjust. */
4698 do_pending_stack_adjust ();
4699 last = get_last_insn ();
4702 = compare_from_rtx (op0, op1, code, unsignedp, mode, NULL_RTX);
4703 if (CONSTANT_P (comparison))
4705 if (GET_CODE (comparison) == CONST_INT)
4707 if (comparison == const0_rtx)
4710 #ifdef FLOAT_STORE_FLAG_VALUE
4711 else if (GET_CODE (comparison) == CONST_DOUBLE)
4713 if (comparison == CONST0_RTX (GET_MODE (comparison)))
4719 if (normalizep == 1)
4721 if (normalizep == -1)
4723 return const_true_rtx;
4726 /* The code of COMPARISON may not match CODE if compare_from_rtx
4727 decided to swap its operands and reverse the original code.
4729 We know that compare_from_rtx returns either a CONST_INT or
4730 a new comparison code, so it is safe to just extract the
4731 code from COMPARISON. */
4732 code = GET_CODE (comparison);
4734 /* Get a reference to the target in the proper mode for this insn. */
4735 compare_mode = insn_data[(int) icode].operand[0].mode;
4737 pred = insn_data[(int) icode].operand[0].predicate;
4738 if (preserve_subexpressions_p ()
4739 || ! (*pred) (subtarget, compare_mode))
4740 subtarget = gen_reg_rtx (compare_mode);
4742 pattern = GEN_FCN (icode) (subtarget);
4745 emit_insn (pattern);
4747 /* If we are converting to a wider mode, first convert to
4748 TARGET_MODE, then normalize. This produces better combining
4749 opportunities on machines that have a SIGN_EXTRACT when we are
4750 testing a single bit. This mostly benefits the 68k.
4752 If STORE_FLAG_VALUE does not have the sign bit set when
4753 interpreted in COMPARE_MODE, we can do this conversion as
4754 unsigned, which is usually more efficient. */
4755 if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (compare_mode))
4757 convert_move (target, subtarget,
4758 (GET_MODE_BITSIZE (compare_mode)
4759 <= HOST_BITS_PER_WIDE_INT)
4760 && 0 == (STORE_FLAG_VALUE
4761 & ((HOST_WIDE_INT) 1
4762 << (GET_MODE_BITSIZE (compare_mode) -1))));
4764 compare_mode = target_mode;
4769 /* If we want to keep subexpressions around, don't reuse our
4772 if (preserve_subexpressions_p ())
4775 /* Now normalize to the proper value in COMPARE_MODE. Sometimes
4776 we don't have to do anything. */
4777 if (normalizep == 0 || normalizep == STORE_FLAG_VALUE)
4779 /* STORE_FLAG_VALUE might be the most negative number, so write
4780 the comparison this way to avoid a compiler-time warning. */
4781 else if (- normalizep == STORE_FLAG_VALUE)
4782 op0 = expand_unop (compare_mode, neg_optab, op0, subtarget, 0);
4784 /* We don't want to use STORE_FLAG_VALUE < 0 below since this
4785 makes it hard to use a value of just the sign bit due to
4786 ANSI integer constant typing rules. */
4787 else if (GET_MODE_BITSIZE (compare_mode) <= HOST_BITS_PER_WIDE_INT
4788 && (STORE_FLAG_VALUE
4789 & ((HOST_WIDE_INT) 1
4790 << (GET_MODE_BITSIZE (compare_mode) - 1))))
4791 op0 = expand_shift (RSHIFT_EXPR, compare_mode, op0,
4792 size_int (GET_MODE_BITSIZE (compare_mode) - 1),
4793 subtarget, normalizep == 1);
4794 else if (STORE_FLAG_VALUE & 1)
4796 op0 = expand_and (compare_mode, op0, const1_rtx, subtarget);
4797 if (normalizep == -1)
4798 op0 = expand_unop (compare_mode, neg_optab, op0, op0, 0);
4803 /* If we were converting to a smaller mode, do the
4805 if (target_mode != compare_mode)
4807 convert_move (target, op0, 0);
4815 delete_insns_since (last);
4817 /* If expensive optimizations, use different pseudo registers for each
4818 insn, instead of reusing the same pseudo. This leads to better CSE,
4819 but slows down the compiler, since there are more pseudos */
4820 subtarget = (!flag_expensive_optimizations
4821 && (target_mode == mode)) ? target : NULL_RTX;
4823 /* If we reached here, we can't do this with a scc insn. However, there
4824 are some comparisons that can be done directly. For example, if
4825 this is an equality comparison of integers, we can try to exclusive-or
4826 (or subtract) the two operands and use a recursive call to try the
4827 comparison with zero. Don't do any of these cases if branches are
4831 && GET_MODE_CLASS (mode) == MODE_INT && (code == EQ || code == NE)
4832 && op1 != const0_rtx)
4834 tem = expand_binop (mode, xor_optab, op0, op1, subtarget, 1,
4838 tem = expand_binop (mode, sub_optab, op0, op1, subtarget, 1,
4841 tem = emit_store_flag (target, code, tem, const0_rtx,
4842 mode, unsignedp, normalizep);
4844 delete_insns_since (last);
4848 /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
4849 the constant zero. Reject all other comparisons at this point. Only
4850 do LE and GT if branches are expensive since they are expensive on
4851 2-operand machines. */
4853 if (BRANCH_COST == 0
4854 || GET_MODE_CLASS (mode) != MODE_INT || op1 != const0_rtx
4855 || (code != EQ && code != NE
4856 && (BRANCH_COST <= 1 || (code != LE && code != GT))))
4859 /* See what we need to return. We can only return a 1, -1, or the
4862 if (normalizep == 0)
4864 if (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4865 normalizep = STORE_FLAG_VALUE;
4867 else if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4868 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4869 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)))
4875 /* Try to put the result of the comparison in the sign bit. Assume we can't
4876 do the necessary operation below. */
4880 /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
4881 the sign bit set. */
4885 /* This is destructive, so SUBTARGET can't be OP0. */
4886 if (rtx_equal_p (subtarget, op0))
4889 tem = expand_binop (mode, sub_optab, op0, const1_rtx, subtarget, 0,
4892 tem = expand_binop (mode, ior_optab, op0, tem, subtarget, 0,
4896 /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
4897 number of bits in the mode of OP0, minus one. */
4901 if (rtx_equal_p (subtarget, op0))
4904 tem = expand_shift (RSHIFT_EXPR, mode, op0,
4905 size_int (GET_MODE_BITSIZE (mode) - 1),
4907 tem = expand_binop (mode, sub_optab, tem, op0, subtarget, 0,
4911 if (code == EQ || code == NE)
4913 /* For EQ or NE, one way to do the comparison is to apply an operation
4914 that converts the operand into a positive number if it is nonzero
4915 or zero if it was originally zero. Then, for EQ, we subtract 1 and
4916 for NE we negate. This puts the result in the sign bit. Then we
4917 normalize with a shift, if needed.
4919 Two operations that can do the above actions are ABS and FFS, so try
4920 them. If that doesn't work, and MODE is smaller than a full word,
4921 we can use zero-extension to the wider mode (an unsigned conversion)
4922 as the operation. */
4924 /* Note that ABS doesn't yield a positive number for INT_MIN, but
4925 that is compensated by the subsequent overflow when subtracting
4928 if (abs_optab->handlers[mode].insn_code != CODE_FOR_nothing)
4929 tem = expand_unop (mode, abs_optab, op0, subtarget, 1);
4930 else if (ffs_optab->handlers[mode].insn_code != CODE_FOR_nothing)
4931 tem = expand_unop (mode, ffs_optab, op0, subtarget, 1);
4932 else if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
4934 op0 = protect_from_queue (op0, 0);
4935 tem = convert_modes (word_mode, mode, op0, 1);
4942 tem = expand_binop (mode, sub_optab, tem, const1_rtx, subtarget,
4945 tem = expand_unop (mode, neg_optab, tem, subtarget, 0);
4948 /* If we couldn't do it that way, for NE we can "or" the two's complement
4949 of the value with itself. For EQ, we take the one's complement of
4950 that "or", which is an extra insn, so we only handle EQ if branches
4953 if (tem == 0 && (code == NE || BRANCH_COST > 1))
4955 if (rtx_equal_p (subtarget, op0))
4958 tem = expand_unop (mode, neg_optab, op0, subtarget, 0);
4959 tem = expand_binop (mode, ior_optab, tem, op0, subtarget, 0,
4962 if (tem && code == EQ)
4963 tem = expand_unop (mode, one_cmpl_optab, tem, subtarget, 0);
4967 if (tem && normalizep)
4968 tem = expand_shift (RSHIFT_EXPR, mode, tem,
4969 size_int (GET_MODE_BITSIZE (mode) - 1),
4970 subtarget, normalizep == 1);
4974 if (GET_MODE (tem) != target_mode)
4976 convert_move (target, tem, 0);
4979 else if (!subtarget)
4981 emit_move_insn (target, tem);
4986 delete_insns_since (last);
4991 /* Like emit_store_flag, but always succeeds. */
4994 emit_store_flag_force (rtx target, enum rtx_code code, rtx op0, rtx op1,
4995 enum machine_mode mode, int unsignedp, int normalizep)
4999 /* First see if emit_store_flag can do the job. */
5000 tem = emit_store_flag (target, code, op0, op1, mode, unsignedp, normalizep);
5004 if (normalizep == 0)
5007 /* If this failed, we have to do this with set/compare/jump/set code. */
5010 || reg_mentioned_p (target, op0) || reg_mentioned_p (target, op1))
5011 target = gen_reg_rtx (GET_MODE (target));
5013 emit_move_insn (target, const1_rtx);
5014 label = gen_label_rtx ();
5015 do_compare_rtx_and_jump (op0, op1, code, unsignedp, mode, NULL_RTX,
5018 emit_move_insn (target, const0_rtx);
5024 /* Perform possibly multi-word comparison and conditional jump to LABEL
5025 if ARG1 OP ARG2 true where ARG1 and ARG2 are of mode MODE
5027 The algorithm is based on the code in expr.c:do_jump.
5029 Note that this does not perform a general comparison. Only variants
5030 generated within expmed.c are correctly handled, others abort (but could
5031 be handled if needed). */
5034 do_cmp_and_jump (rtx arg1, rtx arg2, enum rtx_code op, enum machine_mode mode,
5037 /* If this mode is an integer too wide to compare properly,
5038 compare word by word. Rely on cse to optimize constant cases. */
5040 if (GET_MODE_CLASS (mode) == MODE_INT
5041 && ! can_compare_p (op, mode, ccp_jump))
5043 rtx label2 = gen_label_rtx ();
5048 do_jump_by_parts_greater_rtx (mode, 1, arg2, arg1, label2, label);
5052 do_jump_by_parts_greater_rtx (mode, 1, arg1, arg2, label, label2);
5056 do_jump_by_parts_greater_rtx (mode, 0, arg2, arg1, label2, label);
5060 do_jump_by_parts_greater_rtx (mode, 0, arg1, arg2, label2, label);
5064 do_jump_by_parts_greater_rtx (mode, 0, arg2, arg1, label, label2);
5067 /* do_jump_by_parts_equality_rtx compares with zero. Luckily
5068 that's the only equality operations we do */
5070 if (arg2 != const0_rtx || mode != GET_MODE(arg1))
5072 do_jump_by_parts_equality_rtx (arg1, label2, label);
5076 if (arg2 != const0_rtx || mode != GET_MODE(arg1))
5078 do_jump_by_parts_equality_rtx (arg1, label, label2);
5085 emit_label (label2);
5088 emit_cmp_and_jump_insns (arg1, arg2, op, NULL_RTX, mode, 0, label);