1 @c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 1999, 2000, 2001,
2 @c 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
3 @c This is part of the GCC manual.
4 @c For copying conditions, see the file gcc.texi.
8 @chapter Machine Descriptions
9 @cindex machine descriptions
11 A machine description has two parts: a file of instruction patterns
12 (@file{.md} file) and a C header file of macro definitions.
14 The @file{.md} file for a target machine contains a pattern for each
15 instruction that the target machine supports (or at least each instruction
16 that is worth telling the compiler about). It may also contain comments.
17 A semicolon causes the rest of the line to be a comment, unless the semicolon
18 is inside a quoted string.
20 See the next chapter for information on the C header file.
23 * Overview:: How the machine description is used.
24 * Patterns:: How to write instruction patterns.
25 * Example:: An explained example of a @code{define_insn} pattern.
26 * RTL Template:: The RTL template defines what insns match a pattern.
27 * Output Template:: The output template says how to make assembler code
29 * Output Statement:: For more generality, write C code to output
31 * Predicates:: Controlling what kinds of operands can be used
33 * Constraints:: Fine-tuning operand selection.
34 * Standard Names:: Names mark patterns to use for code generation.
35 * Pattern Ordering:: When the order of patterns makes a difference.
36 * Dependent Patterns:: Having one pattern may make you need another.
37 * Jump Patterns:: Special considerations for patterns for jump insns.
38 * Looping Patterns:: How to define patterns for special looping insns.
39 * Insn Canonicalizations::Canonicalization of Instructions
40 * Expander Definitions::Generating a sequence of several RTL insns
41 for a standard operation.
42 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
43 * Including Patterns:: Including Patterns in Machine Descriptions.
44 * Peephole Definitions::Defining machine-specific peephole optimizations.
45 * Insn Attributes:: Specifying the value of attributes for generated insns.
46 * Conditional Execution::Generating @code{define_insn} patterns for
48 * Constant Definitions::Defining symbolic constants that can be used in the
50 * Macros:: Using macros to generate patterns from a template.
54 @section Overview of How the Machine Description is Used
56 There are three main conversions that happen in the compiler:
61 The front end reads the source code and builds a parse tree.
64 The parse tree is used to generate an RTL insn list based on named
68 The insn list is matched against the RTL templates to produce assembler
73 For the generate pass, only the names of the insns matter, from either a
74 named @code{define_insn} or a @code{define_expand}. The compiler will
75 choose the pattern with the right name and apply the operands according
76 to the documentation later in this chapter, without regard for the RTL
77 template or operand constraints. Note that the names the compiler looks
78 for are hard-coded in the compiler---it will ignore unnamed patterns and
79 patterns with names it doesn't know about, but if you don't provide a
80 named pattern it needs, it will abort.
82 If a @code{define_insn} is used, the template given is inserted into the
83 insn list. If a @code{define_expand} is used, one of three things
84 happens, based on the condition logic. The condition logic may manually
85 create new insns for the insn list, say via @code{emit_insn()}, and
86 invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
87 compiler to use an alternate way of performing that task. If it invokes
88 neither @code{DONE} nor @code{FAIL}, the template given in the pattern
89 is inserted, as if the @code{define_expand} were a @code{define_insn}.
91 Once the insn list is generated, various optimization passes convert,
92 replace, and rearrange the insns in the insn list. This is where the
93 @code{define_split} and @code{define_peephole} patterns get used, for
96 Finally, the insn list's RTL is matched up with the RTL templates in the
97 @code{define_insn} patterns, and those patterns are used to emit the
98 final assembly code. For this purpose, each named @code{define_insn}
99 acts like it's unnamed, since the names are ignored.
102 @section Everything about Instruction Patterns
104 @cindex instruction patterns
107 Each instruction pattern contains an incomplete RTL expression, with pieces
108 to be filled in later, operand constraints that restrict how the pieces can
109 be filled in, and an output pattern or C code to generate the assembler
110 output, all wrapped up in a @code{define_insn} expression.
112 A @code{define_insn} is an RTL expression containing four or five operands:
116 An optional name. The presence of a name indicate that this instruction
117 pattern can perform a certain standard job for the RTL-generation
118 pass of the compiler. This pass knows certain names and will use
119 the instruction patterns with those names, if the names are defined
120 in the machine description.
122 The absence of a name is indicated by writing an empty string
123 where the name should go. Nameless instruction patterns are never
124 used for generating RTL code, but they may permit several simpler insns
125 to be combined later on.
127 Names that are not thus known and used in RTL-generation have no
128 effect; they are equivalent to no name at all.
130 For the purpose of debugging the compiler, you may also specify a
131 name beginning with the @samp{*} character. Such a name is used only
132 for identifying the instruction in RTL dumps; it is entirely equivalent
133 to having a nameless pattern for all other purposes.
136 The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete
137 RTL expressions which show what the instruction should look like. It is
138 incomplete because it may contain @code{match_operand},
139 @code{match_operator}, and @code{match_dup} expressions that stand for
140 operands of the instruction.
142 If the vector has only one element, that element is the template for the
143 instruction pattern. If the vector has multiple elements, then the
144 instruction pattern is a @code{parallel} expression containing the
148 @cindex pattern conditions
149 @cindex conditions, in patterns
150 A condition. This is a string which contains a C expression that is
151 the final test to decide whether an insn body matches this pattern.
153 @cindex named patterns and conditions
154 For a named pattern, the condition (if present) may not depend on
155 the data in the insn being matched, but only the target-machine-type
156 flags. The compiler needs to test these conditions during
157 initialization in order to learn exactly which named instructions are
158 available in a particular run.
161 For nameless patterns, the condition is applied only when matching an
162 individual insn, and only after the insn has matched the pattern's
163 recognition template. The insn's operands may be found in the vector
164 @code{operands}. For an insn where the condition has once matched, it
165 can't be used to control register allocation, for example by excluding
166 certain hard registers or hard register combinations.
169 The @dfn{output template}: a string that says how to output matching
170 insns as assembler code. @samp{%} in this string specifies where
171 to substitute the value of an operand. @xref{Output Template}.
173 When simple substitution isn't general enough, you can specify a piece
174 of C code to compute the output. @xref{Output Statement}.
177 Optionally, a vector containing the values of attributes for insns matching
178 this pattern. @xref{Insn Attributes}.
182 @section Example of @code{define_insn}
183 @cindex @code{define_insn} example
185 Here is an actual example of an instruction pattern, for the 68000/68020.
190 (match_operand:SI 0 "general_operand" "rm"))]
194 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
196 return \"cmpl #0,%0\";
201 This can also be written using braced strings:
206 (match_operand:SI 0 "general_operand" "rm"))]
209 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
215 This is an instruction that sets the condition codes based on the value of
216 a general operand. It has no condition, so any insn whose RTL description
217 has the form shown may be handled according to this pattern. The name
218 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation
219 pass that, when it is necessary to test such a value, an insn to do so
220 can be constructed using this pattern.
222 The output control string is a piece of C code which chooses which
223 output template to return based on the kind of operand and the specific
224 type of CPU for which code is being generated.
226 @samp{"rm"} is an operand constraint. Its meaning is explained below.
229 @section RTL Template
230 @cindex RTL insn template
231 @cindex generating insns
232 @cindex insns, generating
233 @cindex recognizing insns
234 @cindex insns, recognizing
236 The RTL template is used to define which insns match the particular pattern
237 and how to find their operands. For named patterns, the RTL template also
238 says how to construct an insn from specified operands.
240 Construction involves substituting specified operands into a copy of the
241 template. Matching involves determining the values that serve as the
242 operands in the insn being matched. Both of these activities are
243 controlled by special expression types that direct matching and
244 substitution of the operands.
247 @findex match_operand
248 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
249 This expression is a placeholder for operand number @var{n} of
250 the insn. When constructing an insn, operand number @var{n}
251 will be substituted at this point. When matching an insn, whatever
252 appears at this position in the insn will be taken as operand
253 number @var{n}; but it must satisfy @var{predicate} or this instruction
254 pattern will not match at all.
256 Operand numbers must be chosen consecutively counting from zero in
257 each instruction pattern. There may be only one @code{match_operand}
258 expression in the pattern for each operand number. Usually operands
259 are numbered in the order of appearance in @code{match_operand}
260 expressions. In the case of a @code{define_expand}, any operand numbers
261 used only in @code{match_dup} expressions have higher values than all
262 other operand numbers.
264 @var{predicate} is a string that is the name of a function that
265 accepts two arguments, an expression and a machine mode.
266 @xref{Predicates}. During matching, the function will be called with
267 the putative operand as the expression and @var{m} as the mode
268 argument (if @var{m} is not specified, @code{VOIDmode} will be used,
269 which normally causes @var{predicate} to accept any mode). If it
270 returns zero, this instruction pattern fails to match.
271 @var{predicate} may be an empty string; then it means no test is to be
272 done on the operand, so anything which occurs in this position is
275 Most of the time, @var{predicate} will reject modes other than @var{m}---but
276 not always. For example, the predicate @code{address_operand} uses
277 @var{m} as the mode of memory ref that the address should be valid for.
278 Many predicates accept @code{const_int} nodes even though their mode is
281 @var{constraint} controls reloading and the choice of the best register
282 class to use for a value, as explained later (@pxref{Constraints}).
283 If the constraint would be an empty string, it can be omitted.
285 People are often unclear on the difference between the constraint and the
286 predicate. The predicate helps decide whether a given insn matches the
287 pattern. The constraint plays no role in this decision; instead, it
288 controls various decisions in the case of an insn which does match.
290 @findex match_scratch
291 @item (match_scratch:@var{m} @var{n} @var{constraint})
292 This expression is also a placeholder for operand number @var{n}
293 and indicates that operand must be a @code{scratch} or @code{reg}
296 When matching patterns, this is equivalent to
299 (match_operand:@var{m} @var{n} "scratch_operand" @var{pred})
302 but, when generating RTL, it produces a (@code{scratch}:@var{m})
305 If the last few expressions in a @code{parallel} are @code{clobber}
306 expressions whose operands are either a hard register or
307 @code{match_scratch}, the combiner can add or delete them when
308 necessary. @xref{Side Effects}.
311 @item (match_dup @var{n})
312 This expression is also a placeholder for operand number @var{n}.
313 It is used when the operand needs to appear more than once in the
316 In construction, @code{match_dup} acts just like @code{match_operand}:
317 the operand is substituted into the insn being constructed. But in
318 matching, @code{match_dup} behaves differently. It assumes that operand
319 number @var{n} has already been determined by a @code{match_operand}
320 appearing earlier in the recognition template, and it matches only an
321 identical-looking expression.
323 Note that @code{match_dup} should not be used to tell the compiler that
324 a particular register is being used for two operands (example:
325 @code{add} that adds one register to another; the second register is
326 both an input operand and the output operand). Use a matching
327 constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
328 operand is used in two places in the template, such as an instruction
329 that computes both a quotient and a remainder, where the opcode takes
330 two input operands but the RTL template has to refer to each of those
331 twice; once for the quotient pattern and once for the remainder pattern.
333 @findex match_operator
334 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
335 This pattern is a kind of placeholder for a variable RTL expression
338 When constructing an insn, it stands for an RTL expression whose
339 expression code is taken from that of operand @var{n}, and whose
340 operands are constructed from the patterns @var{operands}.
342 When matching an expression, it matches an expression if the function
343 @var{predicate} returns nonzero on that expression @emph{and} the
344 patterns @var{operands} match the operands of the expression.
346 Suppose that the function @code{commutative_operator} is defined as
347 follows, to match any expression whose operator is one of the
348 commutative arithmetic operators of RTL and whose mode is @var{mode}:
352 commutative_integer_operator (x, mode)
354 enum machine_mode mode;
356 enum rtx_code code = GET_CODE (x);
357 if (GET_MODE (x) != mode)
359 return (GET_RTX_CLASS (code) == RTX_COMM_ARITH
360 || code == EQ || code == NE);
364 Then the following pattern will match any RTL expression consisting
365 of a commutative operator applied to two general operands:
368 (match_operator:SI 3 "commutative_operator"
369 [(match_operand:SI 1 "general_operand" "g")
370 (match_operand:SI 2 "general_operand" "g")])
373 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
374 because the expressions to be matched all contain two operands.
376 When this pattern does match, the two operands of the commutative
377 operator are recorded as operands 1 and 2 of the insn. (This is done
378 by the two instances of @code{match_operand}.) Operand 3 of the insn
379 will be the entire commutative expression: use @code{GET_CODE
380 (operands[3])} to see which commutative operator was used.
382 The machine mode @var{m} of @code{match_operator} works like that of
383 @code{match_operand}: it is passed as the second argument to the
384 predicate function, and that function is solely responsible for
385 deciding whether the expression to be matched ``has'' that mode.
387 When constructing an insn, argument 3 of the gen-function will specify
388 the operation (i.e.@: the expression code) for the expression to be
389 made. It should be an RTL expression, whose expression code is copied
390 into a new expression whose operands are arguments 1 and 2 of the
391 gen-function. The subexpressions of argument 3 are not used;
392 only its expression code matters.
394 When @code{match_operator} is used in a pattern for matching an insn,
395 it usually best if the operand number of the @code{match_operator}
396 is higher than that of the actual operands of the insn. This improves
397 register allocation because the register allocator often looks at
398 operands 1 and 2 of insns to see if it can do register tying.
400 There is no way to specify constraints in @code{match_operator}. The
401 operand of the insn which corresponds to the @code{match_operator}
402 never has any constraints because it is never reloaded as a whole.
403 However, if parts of its @var{operands} are matched by
404 @code{match_operand} patterns, those parts may have constraints of
408 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
409 Like @code{match_dup}, except that it applies to operators instead of
410 operands. When constructing an insn, operand number @var{n} will be
411 substituted at this point. But in matching, @code{match_op_dup} behaves
412 differently. It assumes that operand number @var{n} has already been
413 determined by a @code{match_operator} appearing earlier in the
414 recognition template, and it matches only an identical-looking
417 @findex match_parallel
418 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
419 This pattern is a placeholder for an insn that consists of a
420 @code{parallel} expression with a variable number of elements. This
421 expression should only appear at the top level of an insn pattern.
423 When constructing an insn, operand number @var{n} will be substituted at
424 this point. When matching an insn, it matches if the body of the insn
425 is a @code{parallel} expression with at least as many elements as the
426 vector of @var{subpat} expressions in the @code{match_parallel}, if each
427 @var{subpat} matches the corresponding element of the @code{parallel},
428 @emph{and} the function @var{predicate} returns nonzero on the
429 @code{parallel} that is the body of the insn. It is the responsibility
430 of the predicate to validate elements of the @code{parallel} beyond
431 those listed in the @code{match_parallel}.
433 A typical use of @code{match_parallel} is to match load and store
434 multiple expressions, which can contain a variable number of elements
435 in a @code{parallel}. For example,
439 [(match_parallel 0 "load_multiple_operation"
440 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
441 (match_operand:SI 2 "memory_operand" "m"))
443 (clobber (reg:SI 179))])]
448 This example comes from @file{a29k.md}. The function
449 @code{load_multiple_operation} is defined in @file{a29k.c} and checks
450 that subsequent elements in the @code{parallel} are the same as the
451 @code{set} in the pattern, except that they are referencing subsequent
452 registers and memory locations.
454 An insn that matches this pattern might look like:
458 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
460 (clobber (reg:SI 179))
462 (mem:SI (plus:SI (reg:SI 100)
465 (mem:SI (plus:SI (reg:SI 100)
469 @findex match_par_dup
470 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
471 Like @code{match_op_dup}, but for @code{match_parallel} instead of
472 @code{match_operator}.
476 @node Output Template
477 @section Output Templates and Operand Substitution
478 @cindex output templates
479 @cindex operand substitution
481 @cindex @samp{%} in template
483 The @dfn{output template} is a string which specifies how to output the
484 assembler code for an instruction pattern. Most of the template is a
485 fixed string which is output literally. The character @samp{%} is used
486 to specify where to substitute an operand; it can also be used to
487 identify places where different variants of the assembler require
490 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
491 operand @var{n} at that point in the string.
493 @samp{%} followed by a letter and a digit says to output an operand in an
494 alternate fashion. Four letters have standard, built-in meanings described
495 below. The machine description macro @code{PRINT_OPERAND} can define
496 additional letters with nonstandard meanings.
498 @samp{%c@var{digit}} can be used to substitute an operand that is a
499 constant value without the syntax that normally indicates an immediate
502 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
503 the constant is negated before printing.
505 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
506 memory reference, with the actual operand treated as the address. This may
507 be useful when outputting a ``load address'' instruction, because often the
508 assembler syntax for such an instruction requires you to write the operand
509 as if it were a memory reference.
511 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
514 @samp{%=} outputs a number which is unique to each instruction in the
515 entire compilation. This is useful for making local labels to be
516 referred to more than once in a single template that generates multiple
517 assembler instructions.
519 @samp{%} followed by a punctuation character specifies a substitution that
520 does not use an operand. Only one case is standard: @samp{%%} outputs a
521 @samp{%} into the assembler code. Other nonstandard cases can be
522 defined in the @code{PRINT_OPERAND} macro. You must also define
523 which punctuation characters are valid with the
524 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
528 The template may generate multiple assembler instructions. Write the text
529 for the instructions, with @samp{\;} between them.
531 @cindex matching operands
532 When the RTL contains two operands which are required by constraint to match
533 each other, the output template must refer only to the lower-numbered operand.
534 Matching operands are not always identical, and the rest of the compiler
535 arranges to put the proper RTL expression for printing into the lower-numbered
538 One use of nonstandard letters or punctuation following @samp{%} is to
539 distinguish between different assembler languages for the same machine; for
540 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
541 requires periods in most opcode names, while MIT syntax does not. For
542 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
543 syntax. The same file of patterns is used for both kinds of output syntax,
544 but the character sequence @samp{%.} is used in each place where Motorola
545 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
546 defines the sequence to output a period; the macro for MIT syntax defines
549 @cindex @code{#} in template
550 As a special case, a template consisting of the single character @code{#}
551 instructs the compiler to first split the insn, and then output the
552 resulting instructions separately. This helps eliminate redundancy in the
553 output templates. If you have a @code{define_insn} that needs to emit
554 multiple assembler instructions, and there is an matching @code{define_split}
555 already defined, then you can simply use @code{#} as the output template
556 instead of writing an output template that emits the multiple assembler
559 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
560 of the form @samp{@{option0|option1|option2@}} in the templates. These
561 describe multiple variants of assembler language syntax.
562 @xref{Instruction Output}.
564 @node Output Statement
565 @section C Statements for Assembler Output
566 @cindex output statements
567 @cindex C statements for assembler output
568 @cindex generating assembler output
570 Often a single fixed template string cannot produce correct and efficient
571 assembler code for all the cases that are recognized by a single
572 instruction pattern. For example, the opcodes may depend on the kinds of
573 operands; or some unfortunate combinations of operands may require extra
574 machine instructions.
576 If the output control string starts with a @samp{@@}, then it is actually
577 a series of templates, each on a separate line. (Blank lines and
578 leading spaces and tabs are ignored.) The templates correspond to the
579 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
580 if a target machine has a two-address add instruction @samp{addr} to add
581 into a register and another @samp{addm} to add a register to memory, you
582 might write this pattern:
585 (define_insn "addsi3"
586 [(set (match_operand:SI 0 "general_operand" "=r,m")
587 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
588 (match_operand:SI 2 "general_operand" "g,r")))]
595 @cindex @code{*} in template
596 @cindex asterisk in template
597 If the output control string starts with a @samp{*}, then it is not an
598 output template but rather a piece of C program that should compute a
599 template. It should execute a @code{return} statement to return the
600 template-string you want. Most such templates use C string literals, which
601 require doublequote characters to delimit them. To include these
602 doublequote characters in the string, prefix each one with @samp{\}.
604 If the output control string is written as a brace block instead of a
605 double-quoted string, it is automatically assumed to be C code. In that
606 case, it is not necessary to put in a leading asterisk, or to escape the
607 doublequotes surrounding C string literals.
609 The operands may be found in the array @code{operands}, whose C data type
612 It is very common to select different ways of generating assembler code
613 based on whether an immediate operand is within a certain range. Be
614 careful when doing this, because the result of @code{INTVAL} is an
615 integer on the host machine. If the host machine has more bits in an
616 @code{int} than the target machine has in the mode in which the constant
617 will be used, then some of the bits you get from @code{INTVAL} will be
618 superfluous. For proper results, you must carefully disregard the
619 values of those bits.
621 @findex output_asm_insn
622 It is possible to output an assembler instruction and then go on to output
623 or compute more of them, using the subroutine @code{output_asm_insn}. This
624 receives two arguments: a template-string and a vector of operands. The
625 vector may be @code{operands}, or it may be another array of @code{rtx}
626 that you declare locally and initialize yourself.
628 @findex which_alternative
629 When an insn pattern has multiple alternatives in its constraints, often
630 the appearance of the assembler code is determined mostly by which alternative
631 was matched. When this is so, the C code can test the variable
632 @code{which_alternative}, which is the ordinal number of the alternative
633 that was actually satisfied (0 for the first, 1 for the second alternative,
636 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
637 for registers and @samp{clrmem} for memory locations. Here is how
638 a pattern could use @code{which_alternative} to choose between them:
642 [(set (match_operand:SI 0 "general_operand" "=r,m")
646 return (which_alternative == 0
647 ? "clrreg %0" : "clrmem %0");
651 The example above, where the assembler code to generate was
652 @emph{solely} determined by the alternative, could also have been specified
653 as follows, having the output control string start with a @samp{@@}:
658 [(set (match_operand:SI 0 "general_operand" "=r,m")
670 @cindex operand predicates
671 @cindex operator predicates
673 A predicate determines whether a @code{match_operand} or
674 @code{match_operator} expression matches, and therefore whether the
675 surrounding instruction pattern will be used for that combination of
676 operands. GCC has a number of machine-independent predicates, and you
677 can define machine-specific predicates as needed. By convention,
678 predicates used with @code{match_operand} have names that end in
679 @samp{_operand}, and those used with @code{match_operator} have names
680 that end in @samp{_operator}.
682 All predicates are Boolean functions (in the mathematical sense) of
683 two arguments: the RTL expression that is being considered at that
684 position in the instruction pattern, and the machine mode that the
685 @code{match_operand} or @code{match_operator} specifies. In this
686 section, the first argument is called @var{op} and the second argument
687 @var{mode}. Predicates can be called from C as ordinary two-argument
688 functions; this can be useful in output templates or other
689 machine-specific code.
691 Operand predicates can allow operands that are not actually acceptable
692 to the hardware, as long as the constraints give reload the ability to
693 fix them up (@pxref{Constraints}). However, GCC will usually generate
694 better code if the predicates specify the requirements of the machine
695 instructions as closely as possible. Reload cannot fix up operands
696 that must be constants (``immediate operands''); you must use a
697 predicate that allows only constants, or else enforce the requirement
698 in the extra condition.
700 @cindex predicates and machine modes
701 @cindex normal predicates
702 @cindex special predicates
703 Most predicates handle their @var{mode} argument in a uniform manner.
704 If @var{mode} is @code{VOIDmode} (unspecified), then @var{op} can have
705 any mode. If @var{mode} is anything else, then @var{op} must have the
706 same mode, unless @var{op} is a @code{CONST_INT} or integer
707 @code{CONST_DOUBLE}. These RTL expressions always have
708 @code{VOIDmode}, so it would be counterproductive to check that their
709 mode matches. Instead, predicates that accept @code{CONST_INT} and/or
710 integer @code{CONST_DOUBLE} check that the value stored in the
711 constant will fit in the requested mode.
713 Predicates with this behavior are called @dfn{normal}.
714 @command{genrecog} can optimize the instruction recognizer based on
715 knowledge of how normal predicates treat modes. It can also diagnose
716 certain kinds of common errors in the use of normal predicates; for
717 instance, it is almost always an error to use a normal predicate
718 without specifying a mode.
720 Predicates that do something different with their @var{mode} argument
721 are called @dfn{special}. The generic predicates
722 @code{address_operand} and @code{pmode_register_operand} are special
723 predicates. @command{genrecog} does not do any optimizations or
724 diagnosis when special predicates are used.
727 * Machine-Independent Predicates:: Predicates available to all back ends.
728 * Defining Predicates:: How to write machine-specific predicate
732 @node Machine-Independent Predicates
733 @subsection Machine-Independent Predicates
734 @cindex machine-independent predicates
735 @cindex generic predicates
737 These are the generic predicates available to all back ends. They are
738 defined in @file{recog.c}. The first category of predicates allow
739 only constant, or @dfn{immediate}, operands.
741 @defun immediate_operand
742 This predicate allows any sort of constant that fits in @var{mode}.
743 It is an appropriate choice for instructions that take operands that
747 @defun const_int_operand
748 This predicate allows any @code{CONST_INT} expression that fits in
749 @var{mode}. It is an appropriate choice for an immediate operand that
750 does not allow a symbol or label.
753 @defun const_double_operand
754 This predicate accepts any @code{CONST_DOUBLE} expression that has
755 exactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also
756 accept @code{CONST_INT}. It is intended for immediate floating point
761 The second category of predicates allow only some kind of machine
764 @defun register_operand
765 This predicate allows any @code{REG} or @code{SUBREG} expression that
766 is valid for @var{mode}. It is often suitable for arithmetic
767 instruction operands on a RISC machine.
770 @defun pmode_register_operand
771 This is a slight variant on @code{register_operand} which works around
772 a limitation in the machine-description reader.
775 (match_operand @var{n} "pmode_register_operand" @var{constraint})
782 (match_operand:P @var{n} "register_operand" @var{constraint})
786 would mean, if the machine-description reader accepted @samp{:P}
787 mode suffixes. Unfortunately, it cannot, because @code{Pmode} is an
788 alias for some other mode, and might vary with machine-specific
789 options. @xref{Misc}.
792 @defun scratch_operand
793 This predicate allows hard registers and @code{SCRATCH} expressions,
794 but not pseudo-registers. It is used internally by @code{match_scratch};
795 it should not be used directly.
799 The third category of predicates allow only some kind of memory reference.
801 @defun memory_operand
802 This predicate allows any valid reference to a quantity of mode
803 @var{mode} in memory, as determined by the weak form of
804 @code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}).
807 @defun address_operand
808 This predicate is a little unusual; it allows any operand that is a
809 valid expression for the @emph{address} of a quantity of mode
810 @var{mode}, again determined by the weak form of
811 @code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if
812 @samp{@w{(mem:@var{mode} (@var{exp}))}} is acceptable to
813 @code{memory_operand}, then @var{exp} is acceptable to
814 @code{address_operand}. Note that @var{exp} does not necessarily have
818 @defun indirect_operand
819 This is a stricter form of @code{memory_operand} which allows only
820 memory references with a @code{general_operand} as the address
821 expression. New uses of this predicate are discouraged, because
822 @code{general_operand} is very permissive, so it's hard to tell what
823 an @code{indirect_operand} does or does not allow. If a target has
824 different requirements for memory operands for different instructions,
825 it is better to define target-specific predicates which enforce the
826 hardware's requirements explicitly.
830 This predicate allows a memory reference suitable for pushing a value
831 onto the stack. This will be a @code{MEM} which refers to
832 @code{stack_pointer_rtx}, with a side-effect in its address expression
833 (@pxref{Incdec}); which one is determined by the
834 @code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}).
838 This predicate allows a memory reference suitable for popping a value
839 off the stack. Again, this will be a @code{MEM} referring to
840 @code{stack_pointer_rtx}, with a side-effect in its address
841 expression. However, this time @code{STACK_POP_CODE} is expected.
845 The fourth category of predicates allow some combination of the above
848 @defun nonmemory_operand
849 This predicate allows any immediate or register operand valid for @var{mode}.
852 @defun nonimmediate_operand
853 This predicate allows any register or memory operand valid for @var{mode}.
856 @defun general_operand
857 This predicate allows any immediate, register, or memory operand
858 valid for @var{mode}.
862 Finally, there is one generic operator predicate.
864 @defun comparison_operator
865 This predicate matches any expression which performs an arithmetic
866 comparison in @var{mode}; that is, @code{COMPARISON_P} is true for the
870 @node Defining Predicates
871 @subsection Defining Machine-Specific Predicates
872 @cindex defining predicates
873 @findex define_predicate
874 @findex define_special_predicate
876 Many machines have requirements for their operands that cannot be
877 expressed precisely using the generic predicates. You can define
878 additional predicates using @code{define_predicate} and
879 @code{define_special_predicate} expressions. These expressions have
884 The name of the predicate, as it will be referred to in
885 @code{match_operand} or @code{match_operator} expressions.
888 An RTL expression which evaluates to true if the predicate allows the
889 operand @var{op}, false if it does not. This expression can only use
890 the following RTL codes:
894 When written inside a predicate expression, a @code{MATCH_OPERAND}
895 expression evaluates to true if the predicate it names would allow
896 @var{op}. The operand number and constraint are ignored. Due to
897 limitations in @command{genrecog}, you can only refer to generic
898 predicates and predicates that have already been defined.
901 This expression has one operand, a string constant containing a
902 comma-separated list of RTX code names (in lower case). It evaluates
903 to true if @var{op} has any of the listed codes.
906 This expression has one operand, a string constant containing a C
907 expression. The predicate's arguments, @var{op} and @var{mode}, are
908 available with those names in the C expression. The @code{MATCH_TEST}
909 evaluates to true if the C expression evaluates to a nonzero value.
910 @code{MATCH_TEST} expressions must not have side effects.
916 The basic @samp{MATCH_} expressions can be combined using these
917 logical operators, which have the semantics of the C operators
918 @samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively.
922 An optional block of C code, which should execute
923 @samp{@w{return true}} if the predicate is found to match and
924 @samp{@w{return false}} if it does not. It must not have any side
925 effects. The predicate arguments, @var{op} and @var{mode}, are
926 available with those names.
928 If a code block is present in a predicate definition, then the RTL
929 expression must evaluate to true @emph{and} the code block must
930 execute @samp{@w{return true}} for the predicate to allow the operand.
931 The RTL expression is evaluated first; do not re-check anything in the
932 code block that was checked in the RTL expression.
935 The program @command{genrecog} scans @code{define_predicate} and
936 @code{define_special_predicate} expressions to determine which RTX
937 codes are possibly allowed. You should always make this explicit in
938 the RTL predicate expression, using @code{MATCH_OPERAND} and
941 Here is an example of a simple predicate definition, from the IA64
946 ;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.}
947 (define_predicate "small_addr_symbolic_operand"
948 (and (match_code "symbol_ref")
949 (match_test "SYMBOL_REF_SMALL_ADDR_P (op)")))
954 And here is another, showing the use of the C block.
958 ;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.}
959 (define_predicate "gr_register_operand"
960 (match_operand 0 "register_operand")
963 if (GET_CODE (op) == SUBREG)
964 op = SUBREG_REG (op);
967 return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno));
972 Predicates written with @code{define_predicate} automatically include
973 a test that @var{mode} is @code{VOIDmode}, or @var{op} has the same
974 mode as @var{mode}, or @var{op} is a @code{CONST_INT} or
975 @code{CONST_DOUBLE}. They do @emph{not} check specifically for
976 integer @code{CONST_DOUBLE}, nor do they test that the value of either
977 kind of constant fits in the requested mode. This is because
978 target-specific predicates that take constants usually have to do more
979 stringent value checks anyway. If you need the exact same treatment
980 of @code{CONST_INT} or @code{CONST_DOUBLE} that the generic predicates
981 provide, use a @code{MATCH_OPERAND} subexpression to call
982 @code{const_int_operand}, @code{const_double_operand}, or
983 @code{immediate_operand}.
985 Predicates written with @code{define_special_predicate} do not get any
986 automatic mode checks, and are treated as having special mode handling
987 by @command{genrecog}.
989 The program @command{genpreds} is responsible for generating code to
990 test predicates. It also writes a header file containing function
991 declarations for all machine-specific predicates. It is not necessary
992 to declare these predicates in @file{@var{cpu}-protos.h}.
995 @c Most of this node appears by itself (in a different place) even
996 @c when the INTERNALS flag is clear. Passages that require the internals
997 @c manual's context are conditionalized to appear only in the internals manual.
1000 @section Operand Constraints
1001 @cindex operand constraints
1004 Each @code{match_operand} in an instruction pattern can specify
1005 constraints for the operands allowed. The constraints allow you to
1006 fine-tune matching within the set of operands allowed by the
1012 @section Constraints for @code{asm} Operands
1013 @cindex operand constraints, @code{asm}
1014 @cindex constraints, @code{asm}
1015 @cindex @code{asm} constraints
1017 Here are specific details on what constraint letters you can use with
1018 @code{asm} operands.
1020 Constraints can say whether
1021 an operand may be in a register, and which kinds of register; whether the
1022 operand can be a memory reference, and which kinds of address; whether the
1023 operand may be an immediate constant, and which possible values it may
1024 have. Constraints can also require two operands to match.
1028 * Simple Constraints:: Basic use of constraints.
1029 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1030 * Class Preferences:: Constraints guide which hard register to put things in.
1031 * Modifiers:: More precise control over effects of constraints.
1032 * Machine Constraints:: Existing constraints for some particular machines.
1038 * Simple Constraints:: Basic use of constraints.
1039 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1040 * Modifiers:: More precise control over effects of constraints.
1041 * Machine Constraints:: Special constraints for some particular machines.
1045 @node Simple Constraints
1046 @subsection Simple Constraints
1047 @cindex simple constraints
1049 The simplest kind of constraint is a string full of letters, each of
1050 which describes one kind of operand that is permitted. Here are
1051 the letters that are allowed:
1055 Whitespace characters are ignored and can be inserted at any position
1056 except the first. This enables each alternative for different operands to
1057 be visually aligned in the machine description even if they have different
1058 number of constraints and modifiers.
1060 @cindex @samp{m} in constraint
1061 @cindex memory references in constraints
1063 A memory operand is allowed, with any kind of address that the machine
1064 supports in general.
1066 @cindex offsettable address
1067 @cindex @samp{o} in constraint
1069 A memory operand is allowed, but only if the address is
1070 @dfn{offsettable}. This means that adding a small integer (actually,
1071 the width in bytes of the operand, as determined by its machine mode)
1072 may be added to the address and the result is also a valid memory
1075 @cindex autoincrement/decrement addressing
1076 For example, an address which is constant is offsettable; so is an
1077 address that is the sum of a register and a constant (as long as a
1078 slightly larger constant is also within the range of address-offsets
1079 supported by the machine); but an autoincrement or autodecrement
1080 address is not offsettable. More complicated indirect/indexed
1081 addresses may or may not be offsettable depending on the other
1082 addressing modes that the machine supports.
1084 Note that in an output operand which can be matched by another
1085 operand, the constraint letter @samp{o} is valid only when accompanied
1086 by both @samp{<} (if the target machine has predecrement addressing)
1087 and @samp{>} (if the target machine has preincrement addressing).
1089 @cindex @samp{V} in constraint
1091 A memory operand that is not offsettable. In other words, anything that
1092 would fit the @samp{m} constraint but not the @samp{o} constraint.
1094 @cindex @samp{<} in constraint
1096 A memory operand with autodecrement addressing (either predecrement or
1097 postdecrement) is allowed.
1099 @cindex @samp{>} in constraint
1101 A memory operand with autoincrement addressing (either preincrement or
1102 postincrement) is allowed.
1104 @cindex @samp{r} in constraint
1105 @cindex registers in constraints
1107 A register operand is allowed provided that it is in a general
1110 @cindex constants in constraints
1111 @cindex @samp{i} in constraint
1113 An immediate integer operand (one with constant value) is allowed.
1114 This includes symbolic constants whose values will be known only at
1115 assembly time or later.
1117 @cindex @samp{n} in constraint
1119 An immediate integer operand with a known numeric value is allowed.
1120 Many systems cannot support assembly-time constants for operands less
1121 than a word wide. Constraints for these operands should use @samp{n}
1122 rather than @samp{i}.
1124 @cindex @samp{I} in constraint
1125 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
1126 Other letters in the range @samp{I} through @samp{P} may be defined in
1127 a machine-dependent fashion to permit immediate integer operands with
1128 explicit integer values in specified ranges. For example, on the
1129 68000, @samp{I} is defined to stand for the range of values 1 to 8.
1130 This is the range permitted as a shift count in the shift
1133 @cindex @samp{E} in constraint
1135 An immediate floating operand (expression code @code{const_double}) is
1136 allowed, but only if the target floating point format is the same as
1137 that of the host machine (on which the compiler is running).
1139 @cindex @samp{F} in constraint
1141 An immediate floating operand (expression code @code{const_double} or
1142 @code{const_vector}) is allowed.
1144 @cindex @samp{G} in constraint
1145 @cindex @samp{H} in constraint
1146 @item @samp{G}, @samp{H}
1147 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
1148 permit immediate floating operands in particular ranges of values.
1150 @cindex @samp{s} in constraint
1152 An immediate integer operand whose value is not an explicit integer is
1155 This might appear strange; if an insn allows a constant operand with a
1156 value not known at compile time, it certainly must allow any known
1157 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
1158 better code to be generated.
1160 For example, on the 68000 in a fullword instruction it is possible to
1161 use an immediate operand; but if the immediate value is between @minus{}128
1162 and 127, better code results from loading the value into a register and
1163 using the register. This is because the load into the register can be
1164 done with a @samp{moveq} instruction. We arrange for this to happen
1165 by defining the letter @samp{K} to mean ``any integer outside the
1166 range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand
1169 @cindex @samp{g} in constraint
1171 Any register, memory or immediate integer operand is allowed, except for
1172 registers that are not general registers.
1174 @cindex @samp{X} in constraint
1177 Any operand whatsoever is allowed, even if it does not satisfy
1178 @code{general_operand}. This is normally used in the constraint of
1179 a @code{match_scratch} when certain alternatives will not actually
1180 require a scratch register.
1183 Any operand whatsoever is allowed.
1186 @cindex @samp{0} in constraint
1187 @cindex digits in constraint
1188 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
1189 An operand that matches the specified operand number is allowed. If a
1190 digit is used together with letters within the same alternative, the
1191 digit should come last.
1193 This number is allowed to be more than a single digit. If multiple
1194 digits are encountered consecutively, they are interpreted as a single
1195 decimal integer. There is scant chance for ambiguity, since to-date
1196 it has never been desirable that @samp{10} be interpreted as matching
1197 either operand 1 @emph{or} operand 0. Should this be desired, one
1198 can use multiple alternatives instead.
1200 @cindex matching constraint
1201 @cindex constraint, matching
1202 This is called a @dfn{matching constraint} and what it really means is
1203 that the assembler has only a single operand that fills two roles
1205 considered separate in the RTL insn. For example, an add insn has two
1206 input operands and one output operand in the RTL, but on most CISC
1209 which @code{asm} distinguishes. For example, an add instruction uses
1210 two input operands and an output operand, but on most CISC
1212 machines an add instruction really has only two operands, one of them an
1213 input-output operand:
1219 Matching constraints are used in these circumstances.
1220 More precisely, the two operands that match must include one input-only
1221 operand and one output-only operand. Moreover, the digit must be a
1222 smaller number than the number of the operand that uses it in the
1226 For operands to match in a particular case usually means that they
1227 are identical-looking RTL expressions. But in a few special cases
1228 specific kinds of dissimilarity are allowed. For example, @code{*x}
1229 as an input operand will match @code{*x++} as an output operand.
1230 For proper results in such cases, the output template should always
1231 use the output-operand's number when printing the operand.
1234 @cindex load address instruction
1235 @cindex push address instruction
1236 @cindex address constraints
1237 @cindex @samp{p} in constraint
1239 An operand that is a valid memory address is allowed. This is
1240 for ``load address'' and ``push address'' instructions.
1242 @findex address_operand
1243 @samp{p} in the constraint must be accompanied by @code{address_operand}
1244 as the predicate in the @code{match_operand}. This predicate interprets
1245 the mode specified in the @code{match_operand} as the mode of the memory
1246 reference for which the address would be valid.
1248 @cindex other register constraints
1249 @cindex extensible constraints
1250 @item @var{other-letters}
1251 Other letters can be defined in machine-dependent fashion to stand for
1252 particular classes of registers or other arbitrary operand types.
1253 @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
1254 for data, address and floating point registers.
1257 The machine description macro @code{REG_CLASS_FROM_LETTER} has first
1258 cut at the otherwise unused letters. If it evaluates to @code{NO_REGS},
1259 then @code{EXTRA_CONSTRAINT} is evaluated.
1261 A typical use for @code{EXTRA_CONSTRAINT} would be to distinguish certain
1262 types of memory references that affect other insn operands.
1267 In order to have valid assembler code, each operand must satisfy
1268 its constraint. But a failure to do so does not prevent the pattern
1269 from applying to an insn. Instead, it directs the compiler to modify
1270 the code so that the constraint will be satisfied. Usually this is
1271 done by copying an operand into a register.
1273 Contrast, therefore, the two instruction patterns that follow:
1277 [(set (match_operand:SI 0 "general_operand" "=r")
1278 (plus:SI (match_dup 0)
1279 (match_operand:SI 1 "general_operand" "r")))]
1285 which has two operands, one of which must appear in two places, and
1289 [(set (match_operand:SI 0 "general_operand" "=r")
1290 (plus:SI (match_operand:SI 1 "general_operand" "0")
1291 (match_operand:SI 2 "general_operand" "r")))]
1297 which has three operands, two of which are required by a constraint to be
1298 identical. If we are considering an insn of the form
1301 (insn @var{n} @var{prev} @var{next}
1303 (plus:SI (reg:SI 6) (reg:SI 109)))
1308 the first pattern would not apply at all, because this insn does not
1309 contain two identical subexpressions in the right place. The pattern would
1310 say, ``That does not look like an add instruction; try other patterns''.
1311 The second pattern would say, ``Yes, that's an add instruction, but there
1312 is something wrong with it''. It would direct the reload pass of the
1313 compiler to generate additional insns to make the constraint true. The
1314 results might look like this:
1317 (insn @var{n2} @var{prev} @var{n}
1318 (set (reg:SI 3) (reg:SI 6))
1321 (insn @var{n} @var{n2} @var{next}
1323 (plus:SI (reg:SI 3) (reg:SI 109)))
1327 It is up to you to make sure that each operand, in each pattern, has
1328 constraints that can handle any RTL expression that could be present for
1329 that operand. (When multiple alternatives are in use, each pattern must,
1330 for each possible combination of operand expressions, have at least one
1331 alternative which can handle that combination of operands.) The
1332 constraints don't need to @emph{allow} any possible operand---when this is
1333 the case, they do not constrain---but they must at least point the way to
1334 reloading any possible operand so that it will fit.
1338 If the constraint accepts whatever operands the predicate permits,
1339 there is no problem: reloading is never necessary for this operand.
1341 For example, an operand whose constraints permit everything except
1342 registers is safe provided its predicate rejects registers.
1344 An operand whose predicate accepts only constant values is safe
1345 provided its constraints include the letter @samp{i}. If any possible
1346 constant value is accepted, then nothing less than @samp{i} will do;
1347 if the predicate is more selective, then the constraints may also be
1351 Any operand expression can be reloaded by copying it into a register.
1352 So if an operand's constraints allow some kind of register, it is
1353 certain to be safe. It need not permit all classes of registers; the
1354 compiler knows how to copy a register into another register of the
1355 proper class in order to make an instruction valid.
1357 @cindex nonoffsettable memory reference
1358 @cindex memory reference, nonoffsettable
1360 A nonoffsettable memory reference can be reloaded by copying the
1361 address into a register. So if the constraint uses the letter
1362 @samp{o}, all memory references are taken care of.
1365 A constant operand can be reloaded by allocating space in memory to
1366 hold it as preinitialized data. Then the memory reference can be used
1367 in place of the constant. So if the constraint uses the letters
1368 @samp{o} or @samp{m}, constant operands are not a problem.
1371 If the constraint permits a constant and a pseudo register used in an insn
1372 was not allocated to a hard register and is equivalent to a constant,
1373 the register will be replaced with the constant. If the predicate does
1374 not permit a constant and the insn is re-recognized for some reason, the
1375 compiler will crash. Thus the predicate must always recognize any
1376 objects allowed by the constraint.
1379 If the operand's predicate can recognize registers, but the constraint does
1380 not permit them, it can make the compiler crash. When this operand happens
1381 to be a register, the reload pass will be stymied, because it does not know
1382 how to copy a register temporarily into memory.
1384 If the predicate accepts a unary operator, the constraint applies to the
1385 operand. For example, the MIPS processor at ISA level 3 supports an
1386 instruction which adds two registers in @code{SImode} to produce a
1387 @code{DImode} result, but only if the registers are correctly sign
1388 extended. This predicate for the input operands accepts a
1389 @code{sign_extend} of an @code{SImode} register. Write the constraint
1390 to indicate the type of register that is required for the operand of the
1394 @node Multi-Alternative
1395 @subsection Multiple Alternative Constraints
1396 @cindex multiple alternative constraints
1398 Sometimes a single instruction has multiple alternative sets of possible
1399 operands. For example, on the 68000, a logical-or instruction can combine
1400 register or an immediate value into memory, or it can combine any kind of
1401 operand into a register; but it cannot combine one memory location into
1404 These constraints are represented as multiple alternatives. An alternative
1405 can be described by a series of letters for each operand. The overall
1406 constraint for an operand is made from the letters for this operand
1407 from the first alternative, a comma, the letters for this operand from
1408 the second alternative, a comma, and so on until the last alternative.
1410 Here is how it is done for fullword logical-or on the 68000:
1413 (define_insn "iorsi3"
1414 [(set (match_operand:SI 0 "general_operand" "=m,d")
1415 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1416 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1420 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1421 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1422 2. The second alternative has @samp{d} (data register) for operand 0,
1423 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1424 @samp{%} in the constraints apply to all the alternatives; their
1425 meaning is explained in the next section (@pxref{Class Preferences}).
1428 @c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL
1429 If all the operands fit any one alternative, the instruction is valid.
1430 Otherwise, for each alternative, the compiler counts how many instructions
1431 must be added to copy the operands so that that alternative applies.
1432 The alternative requiring the least copying is chosen. If two alternatives
1433 need the same amount of copying, the one that comes first is chosen.
1434 These choices can be altered with the @samp{?} and @samp{!} characters:
1437 @cindex @samp{?} in constraint
1438 @cindex question mark
1440 Disparage slightly the alternative that the @samp{?} appears in,
1441 as a choice when no alternative applies exactly. The compiler regards
1442 this alternative as one unit more costly for each @samp{?} that appears
1445 @cindex @samp{!} in constraint
1446 @cindex exclamation point
1448 Disparage severely the alternative that the @samp{!} appears in.
1449 This alternative can still be used if it fits without reloading,
1450 but if reloading is needed, some other alternative will be used.
1454 When an insn pattern has multiple alternatives in its constraints, often
1455 the appearance of the assembler code is determined mostly by which
1456 alternative was matched. When this is so, the C code for writing the
1457 assembler code can use the variable @code{which_alternative}, which is
1458 the ordinal number of the alternative that was actually satisfied (0 for
1459 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1463 @node Class Preferences
1464 @subsection Register Class Preferences
1465 @cindex class preference constraints
1466 @cindex register class preference constraints
1468 @cindex voting between constraint alternatives
1469 The operand constraints have another function: they enable the compiler
1470 to decide which kind of hardware register a pseudo register is best
1471 allocated to. The compiler examines the constraints that apply to the
1472 insns that use the pseudo register, looking for the machine-dependent
1473 letters such as @samp{d} and @samp{a} that specify classes of registers.
1474 The pseudo register is put in whichever class gets the most ``votes''.
1475 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1476 favor of a general register. The machine description says which registers
1477 are considered general.
1479 Of course, on some machines all registers are equivalent, and no register
1480 classes are defined. Then none of this complexity is relevant.
1484 @subsection Constraint Modifier Characters
1485 @cindex modifiers in constraints
1486 @cindex constraint modifier characters
1488 @c prevent bad page break with this line
1489 Here are constraint modifier characters.
1492 @cindex @samp{=} in constraint
1494 Means that this operand is write-only for this instruction: the previous
1495 value is discarded and replaced by output data.
1497 @cindex @samp{+} in constraint
1499 Means that this operand is both read and written by the instruction.
1501 When the compiler fixes up the operands to satisfy the constraints,
1502 it needs to know which operands are inputs to the instruction and
1503 which are outputs from it. @samp{=} identifies an output; @samp{+}
1504 identifies an operand that is both input and output; all other operands
1505 are assumed to be input only.
1507 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1508 first character of the constraint string.
1510 @cindex @samp{&} in constraint
1511 @cindex earlyclobber operand
1513 Means (in a particular alternative) that this operand is an
1514 @dfn{earlyclobber} operand, which is modified before the instruction is
1515 finished using the input operands. Therefore, this operand may not lie
1516 in a register that is used as an input operand or as part of any memory
1519 @samp{&} applies only to the alternative in which it is written. In
1520 constraints with multiple alternatives, sometimes one alternative
1521 requires @samp{&} while others do not. See, for example, the
1522 @samp{movdf} insn of the 68000.
1524 An input operand can be tied to an earlyclobber operand if its only
1525 use as an input occurs before the early result is written. Adding
1526 alternatives of this form often allows GCC to produce better code
1527 when only some of the inputs can be affected by the earlyclobber.
1528 See, for example, the @samp{mulsi3} insn of the ARM@.
1530 @samp{&} does not obviate the need to write @samp{=}.
1532 @cindex @samp{%} in constraint
1534 Declares the instruction to be commutative for this operand and the
1535 following operand. This means that the compiler may interchange the
1536 two operands if that is the cheapest way to make all operands fit the
1539 This is often used in patterns for addition instructions
1540 that really have only two operands: the result must go in one of the
1541 arguments. Here for example, is how the 68000 halfword-add
1542 instruction is defined:
1545 (define_insn "addhi3"
1546 [(set (match_operand:HI 0 "general_operand" "=m,r")
1547 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1548 (match_operand:HI 2 "general_operand" "di,g")))]
1552 GCC can only handle one commutative pair in an asm; if you use more,
1553 the compiler may fail. Note that you need not use the modifier if
1554 the two alternatives are strictly identical; this would only waste
1555 time in the reload pass.
1557 @cindex @samp{#} in constraint
1559 Says that all following characters, up to the next comma, are to be
1560 ignored as a constraint. They are significant only for choosing
1561 register preferences.
1563 @cindex @samp{*} in constraint
1565 Says that the following character should be ignored when choosing
1566 register preferences. @samp{*} has no effect on the meaning of the
1567 constraint as a constraint, and no effect on reloading.
1570 Here is an example: the 68000 has an instruction to sign-extend a
1571 halfword in a data register, and can also sign-extend a value by
1572 copying it into an address register. While either kind of register is
1573 acceptable, the constraints on an address-register destination are
1574 less strict, so it is best if register allocation makes an address
1575 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1576 constraint letter (for data register) is ignored when computing
1577 register preferences.
1580 (define_insn "extendhisi2"
1581 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1583 (match_operand:HI 1 "general_operand" "0,g")))]
1589 @node Machine Constraints
1590 @subsection Constraints for Particular Machines
1591 @cindex machine specific constraints
1592 @cindex constraints, machine specific
1594 Whenever possible, you should use the general-purpose constraint letters
1595 in @code{asm} arguments, since they will convey meaning more readily to
1596 people reading your code. Failing that, use the constraint letters
1597 that usually have very similar meanings across architectures. The most
1598 commonly used constraints are @samp{m} and @samp{r} (for memory and
1599 general-purpose registers respectively; @pxref{Simple Constraints}), and
1600 @samp{I}, usually the letter indicating the most common
1601 immediate-constant format.
1603 For each machine architecture, the
1604 @file{config/@var{machine}/@var{machine}.h} file defines additional
1605 constraints. These constraints are used by the compiler itself for
1606 instruction generation, as well as for @code{asm} statements; therefore,
1607 some of the constraints are not particularly interesting for @code{asm}.
1608 The constraints are defined through these macros:
1611 @item REG_CLASS_FROM_LETTER
1612 Register class constraints (usually lowercase).
1614 @item CONST_OK_FOR_LETTER_P
1615 Immediate constant constraints, for non-floating point constants of
1616 word size or smaller precision (usually uppercase).
1618 @item CONST_DOUBLE_OK_FOR_LETTER_P
1619 Immediate constant constraints, for all floating point constants and for
1620 constants of greater than word size precision (usually uppercase).
1622 @item EXTRA_CONSTRAINT
1623 Special cases of registers or memory. This macro is not required, and
1624 is only defined for some machines.
1627 Inspecting these macro definitions in the compiler source for your
1628 machine is the best way to be certain you have the right constraints.
1629 However, here is a summary of the machine-dependent constraints
1630 available on some particular machines.
1633 @item ARM family---@file{arm.h}
1636 Floating-point register
1639 VFP floating-point register
1642 One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0
1646 Floating-point constant that would satisfy the constraint @samp{F} if it
1650 Integer that is valid as an immediate operand in a data processing
1651 instruction. That is, an integer in the range 0 to 255 rotated by a
1655 Integer in the range @minus{}4095 to 4095
1658 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1661 Integer that satisfies constraint @samp{I} when negated (twos complement)
1664 Integer in the range 0 to 32
1667 A memory reference where the exact address is in a single register
1668 (`@samp{m}' is preferable for @code{asm} statements)
1671 An item in the constant pool
1674 A symbol in the text segment of the current file
1677 A memory reference suitable for VFP load/store insns (reg+constant offset)
1680 A memory reference suitable for iWMMXt load/store instructions.
1683 A memory reference suitable for the ARMv4 ldrsb instruction.
1686 @item AVR family---@file{avr.h}
1689 Registers from r0 to r15
1692 Registers from r16 to r23
1695 Registers from r16 to r31
1698 Registers from r24 to r31. These registers can be used in @samp{adiw} command
1701 Pointer register (r26--r31)
1704 Base pointer register (r28--r31)
1707 Stack pointer register (SPH:SPL)
1710 Temporary register r0
1713 Register pair X (r27:r26)
1716 Register pair Y (r29:r28)
1719 Register pair Z (r31:r30)
1722 Constant greater than @minus{}1, less than 64
1725 Constant greater than @minus{}64, less than 1
1734 Constant that fits in 8 bits
1737 Constant integer @minus{}1
1740 Constant integer 8, 16, or 24
1746 A floating point constant 0.0
1749 @item CRX Architecture---@file{crx.h}
1753 Registers from r0 to r14 (registers without stack pointer)
1756 Register r16 (64-bit accumulator lo register)
1759 Register r17 (64-bit accumulator hi register)
1762 Register pair r16-r17. (64-bit accumulator lo-hi pair)
1765 Constant that fits in 3 bits
1768 Constant that fits in 4 bits
1771 Constant that fits in 5 bits
1774 Constant that is one of -1, 4, -4, 7, 8, 12, 16, 20, 32, 48
1777 Floating point constant that is legal for store immediate
1780 @item PowerPC and IBM RS6000---@file{rs6000.h}
1783 Address base register
1786 Floating point register
1792 @samp{MQ}, @samp{CTR}, or @samp{LINK} register
1801 @samp{LINK} register
1804 @samp{CR} register (condition register) number 0
1807 @samp{CR} register (condition register)
1810 @samp{FPMEM} stack memory for FPR-GPR transfers
1813 Signed 16-bit constant
1816 Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for
1817 @code{SImode} constants)
1820 Unsigned 16-bit constant
1823 Signed 16-bit constant shifted left 16 bits
1826 Constant larger than 31
1835 Constant whose negation is a signed 16-bit constant
1838 Floating point constant that can be loaded into a register with one
1839 instruction per word
1842 Memory operand that is an offset from a register (@samp{m} is preferable
1843 for @code{asm} statements)
1849 Constant suitable as a 64-bit mask operand
1852 Constant suitable as a 32-bit mask operand
1855 System V Release 4 small data area reference
1858 @item MorphoRISC family---@file{ms1.h}
1861 Constant for an arithmetic insn (16-bit signed integer).
1867 Constant for a logical insn (16-bit zero-extended integer).
1870 A constant that can be loaded with @code{lui} (i.e.@: the bottom 16
1874 A constant that takes two words to load (i.e.@: not matched by
1875 @code{I}, @code{K}, or @code{L}).
1878 Negative 16-bit constants other than -65536.
1881 A 15-bit signed integer constant.
1884 A positive 16-bit constant.
1887 @item Intel 386---@file{i386.h}
1890 @samp{a}, @code{b}, @code{c}, or @code{d} register for the i386.
1891 For x86-64 it is equivalent to @samp{r} class (for 8-bit instructions that
1892 do not use upper halves).
1895 @samp{a}, @code{b}, @code{c}, or @code{d} register (for 8-bit instructions,
1896 that do use upper halves).
1899 Legacy register---equivalent to @code{r} class in i386 mode.
1900 (for non-8-bit registers used together with 8-bit upper halves in a single
1904 Specifies the @samp{a} or @samp{d} registers. This is primarily useful
1905 for 64-bit integer values (when in 32-bit mode) intended to be returned
1906 with the @samp{d} register holding the most significant bits and the
1907 @samp{a} register holding the least significant bits.
1910 Floating point register
1913 First (top of stack) floating point register
1916 Second floating point register
1928 Specifies constant that can be easily constructed in SSE register without
1929 loading it from memory.
1941 @samp{xmm} SSE register
1947 Constant in range 0 to 31 (for 32-bit shifts)
1950 Constant in range 0 to 63 (for 64-bit shifts)
1959 0, 1, 2, or 3 (shifts for @code{lea} instruction)
1962 Constant in range 0 to 255 (for @code{out} instruction)
1965 Constant in range 0 to @code{0xffffffff} or symbolic reference known to fit specified range.
1966 (for using immediates in zero extending 32-bit to 64-bit x86-64 instructions)
1969 Constant in range @minus{}2147483648 to 2147483647 or symbolic reference known to fit specified range.
1970 (for using immediates in 64-bit x86-64 instructions)
1973 Standard 80387 floating point constant
1976 @item Intel IA-64---@file{ia64.h}
1979 General register @code{r0} to @code{r3} for @code{addl} instruction
1985 Predicate register (@samp{c} as in ``conditional'')
1988 Application register residing in M-unit
1991 Application register residing in I-unit
1994 Floating-point register
1998 Remember that @samp{m} allows postincrement and postdecrement which
1999 require printing with @samp{%Pn} on IA-64.
2000 Use @samp{S} to disallow postincrement and postdecrement.
2003 Floating-point constant 0.0 or 1.0
2006 14-bit signed integer constant
2009 22-bit signed integer constant
2012 8-bit signed integer constant for logical instructions
2015 8-bit adjusted signed integer constant for compare pseudo-ops
2018 6-bit unsigned integer constant for shift counts
2021 9-bit signed integer constant for load and store postincrements
2027 0 or @minus{}1 for @code{dep} instruction
2030 Non-volatile memory for floating-point loads and stores
2033 Integer constant in the range 1 to 4 for @code{shladd} instruction
2036 Memory operand except postincrement and postdecrement
2039 @item FRV---@file{frv.h}
2042 Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}).
2045 Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}).
2048 Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and
2049 @code{icc0} to @code{icc3}).
2052 Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}).
2055 Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}).
2056 Odd registers are excluded not in the class but through the use of a machine
2057 mode larger than 4 bytes.
2060 Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}).
2063 Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}).
2064 Odd registers are excluded not in the class but through the use of a machine
2065 mode larger than 4 bytes.
2068 Register in the class @code{LR_REG} (the @code{lr} register).
2071 Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}).
2072 Register numbers not divisible by 4 are excluded not in the class but through
2073 the use of a machine mode larger than 8 bytes.
2076 Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}).
2079 Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}).
2082 Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}).
2085 Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}).
2088 Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}).
2089 Register numbers not divisible by 4 are excluded not in the class but through
2090 the use of a machine mode larger than 8 bytes.
2093 Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}).
2096 Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}).
2099 Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}).
2102 Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}).
2105 Floating point constant zero
2108 6-bit signed integer constant
2111 10-bit signed integer constant
2114 16-bit signed integer constant
2117 16-bit unsigned integer constant
2120 12-bit signed integer constant that is negative---i.e.@: in the
2121 range of @minus{}2048 to @minus{}1
2127 12-bit signed integer constant that is greater than zero---i.e.@: in the
2132 @item Blackfin family---@file{bfin.h}
2141 A call clobbered P register.
2144 Even-numbered D register
2147 Odd-numbered D register
2150 Accumulator register.
2153 Even-numbered accumulator register.
2156 Odd-numbered accumulator register.
2168 Registers used for circular buffering, i.e. I, B, or L registers.
2174 Any D, P, B, M, I or L register.
2177 Additional registers typically used only in prologues and epilogues: RETS,
2178 RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.
2181 Any register except accumulators or CC.
2184 Signed 16 bit integer (in the range -32768 to 32767)
2187 Unsigned 16 bit integer (in the range 0 to 65535)
2190 Signed 7 bit integer (in the range -64 to 63)
2193 Unsigned 7 bit integer (in the range 0 to 127)
2196 Unsigned 5 bit integer (in the range 0 to 31)
2199 Signed 4 bit integer (in the range -8 to 7)
2202 Signed 3 bit integer (in the range -3 to 4)
2205 Unsigned 3 bit integer (in the range 0 to 7)
2208 Constant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4.
2217 An integer constant with exactly a single bit set.
2220 An integer constant with all bits set except exactly one.
2228 @item M32C---@file{m32c.c}
2233 @samp{$sp}, @samp{$fb}, @samp{$sb}.
2236 Any control register, when they're 16 bits wide (nothing if control
2237 registers are 24 bits wide)
2240 Any control register, when they're 24 bits wide.
2249 $r0 or $r2, or $r2r0 for 32 bit values.
2252 $r1 or $r3, or $r3r1 for 32 bit values.
2255 A register that can hold a 64 bit value.
2258 $r0 or $r1 (registers with addressable high/low bytes)
2267 Address registers when they're 16 bits wide.
2270 Address registers when they're 24 bits wide.
2273 Registers that can hold QI values.
2276 Registers that can be used with displacements ($a0, $a1, $sb).
2279 Registers that can hold 32 bit values.
2282 Registers that can hold 16 bit values.
2285 Registers chat can hold 16 bit values, including all control
2289 $r0 through R1, plus $a0 and $a1.
2295 The memory-based pseudo-registers $mem0 through $mem15.
2298 Registers that can hold pointers (16 bit registers for r8c, m16c; 24
2299 bit registers for m32cm, m32c).
2302 Matches multiple registers in a PARALLEL to form a larger register.
2303 Used to match function return values.
2312 -32768 @dots{} 32767
2318 -8 @dots{} -1 or 1 @dots{} 8
2321 -16 @dots{} -1 or 1 @dots{} 16
2324 -8 @dots{} -1 or 1 @dots{} 8
2330 An 8 bit value with exactly one bit set.
2333 A 16 bit value with exactly one bit set.
2336 The common src/dest memory addressing modes.
2339 Memory addressed using $a0 or $a1.
2342 Memory addressed with immediate addresses.
2345 Memory addressed using the stack pointer ($sp).
2348 Memory addressed using the frame base register ($fb).
2351 Memory addressed using the small base register ($sb).
2357 @item MIPS---@file{mips.h}
2360 General-purpose integer register
2363 Floating-point register (if available)
2372 @samp{Hi} or @samp{Lo} register
2375 General-purpose integer register
2378 Floating-point status register
2381 Signed 16-bit constant (for arithmetic instructions)
2387 Zero-extended 16-bit constant (for logic instructions)
2390 Constant with low 16 bits zero (can be loaded with @code{lui})
2393 32-bit constant which requires two instructions to load (a constant
2394 which is not @samp{I}, @samp{K}, or @samp{L})
2397 Negative 16-bit constant
2403 Positive 16-bit constant
2409 Memory reference that can be loaded with more than one instruction
2410 (@samp{m} is preferable for @code{asm} statements)
2413 Memory reference that can be loaded with one instruction
2414 (@samp{m} is preferable for @code{asm} statements)
2417 Memory reference in external OSF/rose PIC format
2418 (@samp{m} is preferable for @code{asm} statements)
2421 @item Motorola 680x0---@file{m68k.h}
2430 68881 floating-point register, if available
2433 Integer in the range 1 to 8
2436 16-bit signed number
2439 Signed number whose magnitude is greater than 0x80
2442 Integer in the range @minus{}8 to @minus{}1
2445 Signed number whose magnitude is greater than 0x100
2448 Floating point constant that is not a 68881 constant
2451 @item Motorola 68HC11 & 68HC12 families---@file{m68hc11.h}
2466 Temporary soft register _.tmp
2469 A soft register _.d1 to _.d31
2472 Stack pointer register
2481 Pseudo register `z' (replaced by `x' or `y' at the end)
2484 An address register: x, y or z
2487 An address register: x or y
2490 Register pair (x:d) to form a 32-bit value
2493 Constants in the range @minus{}65536 to 65535
2496 Constants whose 16-bit low part is zero
2499 Constant integer 1 or @minus{}1
2505 Constants in the range @minus{}8 to 2
2510 @item SPARC---@file{sparc.h}
2513 Floating-point register on the SPARC-V8 architecture and
2514 lower floating-point register on the SPARC-V9 architecture.
2517 Floating-point register. It is equivalent to @samp{f} on the
2518 SPARC-V8 architecture and contains both lower and upper
2519 floating-point registers on the SPARC-V9 architecture.
2522 Floating-point condition code register.
2525 Lower floating-point register. It is only valid on the SPARC-V9
2526 architecture when the Visual Instruction Set is available.
2529 Floating-point register. It is only valid on the SPARC-V9 architecture
2530 when the Visual Instruction Set is available.
2533 64-bit global or out register for the SPARC-V8+ architecture.
2536 Signed 13-bit constant
2542 32-bit constant with the low 12 bits clear (a constant that can be
2543 loaded with the @code{sethi} instruction)
2546 A constant in the range supported by @code{movcc} instructions
2549 A constant in the range supported by @code{movrcc} instructions
2552 Same as @samp{K}, except that it verifies that bits that are not in the
2553 lower 32-bit range are all zero. Must be used instead of @samp{K} for
2554 modes wider than @code{SImode}
2563 Signed 13-bit constant, sign-extended to 32 or 64 bits
2566 Floating-point constant whose integral representation can
2567 be moved into an integer register using a single sethi
2571 Floating-point constant whose integral representation can
2572 be moved into an integer register using a single mov
2576 Floating-point constant whose integral representation can
2577 be moved into an integer register using a high/lo_sum
2578 instruction sequence
2581 Memory address aligned to an 8-byte boundary
2587 Memory address for @samp{e} constraint registers
2594 @item TMS320C3x/C4x---@file{c4x.h}
2597 Auxiliary (address) register (ar0-ar7)
2600 Stack pointer register (sp)
2603 Standard (32-bit) precision integer register
2606 Extended (40-bit) precision register (r0-r11)
2609 Block count register (bk)
2612 Extended (40-bit) precision low register (r0-r7)
2615 Extended (40-bit) precision register (r0-r1)
2618 Extended (40-bit) precision register (r2-r3)
2621 Repeat count register (rc)
2624 Index register (ir0-ir1)
2627 Status (condition code) register (st)
2630 Data page register (dp)
2636 Immediate 16-bit floating-point constant
2639 Signed 16-bit constant
2642 Signed 8-bit constant
2645 Signed 5-bit constant
2648 Unsigned 16-bit constant
2651 Unsigned 8-bit constant
2654 Ones complement of unsigned 16-bit constant
2657 High 16-bit constant (32-bit constant with 16 LSBs zero)
2660 Indirect memory reference with signed 8-bit or index register displacement
2663 Indirect memory reference with unsigned 5-bit displacement
2666 Indirect memory reference with 1 bit or index register displacement
2669 Direct memory reference
2676 @item S/390 and zSeries---@file{s390.h}
2679 Address register (general purpose register except r0)
2682 Condition code register
2685 Data register (arbitrary general purpose register)
2688 Floating-point register
2691 Unsigned 8-bit constant (0--255)
2694 Unsigned 12-bit constant (0--4095)
2697 Signed 16-bit constant (@minus{}32768--32767)
2700 Value appropriate as displacement.
2703 for short displacement
2704 @item (-524288..524287)
2705 for long displacement
2709 Constant integer with a value of 0x7fffffff.
2712 Multiple letter constraint followed by 4 parameter letters.
2715 number of the part counting from most to least significant
2719 mode of the containing operand
2721 value of the other parts (F---all bits set)
2723 The constraint matches if the specified part of a constant
2724 has a value different from it's other parts.
2727 Memory reference without index register and with short displacement.
2730 Memory reference with index register and short displacement.
2733 Memory reference without index register but with long displacement.
2736 Memory reference with index register and long displacement.
2739 Pointer with short displacement.
2742 Pointer with long displacement.
2745 Shift count operand.
2749 @item Xstormy16---@file{stormy16.h}
2764 Registers r0 through r7.
2767 Registers r0 and r1.
2773 Registers r8 and r9.
2776 A constant between 0 and 3 inclusive.
2779 A constant that has exactly one bit set.
2782 A constant that has exactly one bit clear.
2785 A constant between 0 and 255 inclusive.
2788 A constant between @minus{}255 and 0 inclusive.
2791 A constant between @minus{}3 and 0 inclusive.
2794 A constant between 1 and 4 inclusive.
2797 A constant between @minus{}4 and @minus{}1 inclusive.
2800 A memory reference that is a stack push.
2803 A memory reference that is a stack pop.
2806 A memory reference that refers to a constant address of known value.
2809 The register indicated by Rx (not implemented yet).
2812 A constant that is not between 2 and 15 inclusive.
2819 @item Xtensa---@file{xtensa.h}
2822 General-purpose 32-bit register
2825 One-bit boolean register
2828 MAC16 40-bit accumulator register
2831 Signed 12-bit integer constant, for use in MOVI instructions
2834 Signed 8-bit integer constant, for use in ADDI instructions
2837 Integer constant valid for BccI instructions
2840 Unsigned constant valid for BccUI instructions
2847 @node Standard Names
2848 @section Standard Pattern Names For Generation
2849 @cindex standard pattern names
2850 @cindex pattern names
2851 @cindex names, pattern
2853 Here is a table of the instruction names that are meaningful in the RTL
2854 generation pass of the compiler. Giving one of these names to an
2855 instruction pattern tells the RTL generation pass that it can use the
2856 pattern to accomplish a certain task.
2859 @cindex @code{mov@var{m}} instruction pattern
2860 @item @samp{mov@var{m}}
2861 Here @var{m} stands for a two-letter machine mode name, in lowercase.
2862 This instruction pattern moves data with that machine mode from operand
2863 1 to operand 0. For example, @samp{movsi} moves full-word data.
2865 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
2866 own mode is wider than @var{m}, the effect of this instruction is
2867 to store the specified value in the part of the register that corresponds
2868 to mode @var{m}. Bits outside of @var{m}, but which are within the
2869 same target word as the @code{subreg} are undefined. Bits which are
2870 outside the target word are left unchanged.
2872 This class of patterns is special in several ways. First of all, each
2873 of these names up to and including full word size @emph{must} be defined,
2874 because there is no other way to copy a datum from one place to another.
2875 If there are patterns accepting operands in larger modes,
2876 @samp{mov@var{m}} must be defined for integer modes of those sizes.
2878 Second, these patterns are not used solely in the RTL generation pass.
2879 Even the reload pass can generate move insns to copy values from stack
2880 slots into temporary registers. When it does so, one of the operands is
2881 a hard register and the other is an operand that can need to be reloaded
2885 Therefore, when given such a pair of operands, the pattern must generate
2886 RTL which needs no reloading and needs no temporary registers---no
2887 registers other than the operands. For example, if you support the
2888 pattern with a @code{define_expand}, then in such a case the
2889 @code{define_expand} mustn't call @code{force_reg} or any other such
2890 function which might generate new pseudo registers.
2892 This requirement exists even for subword modes on a RISC machine where
2893 fetching those modes from memory normally requires several insns and
2894 some temporary registers.
2896 @findex change_address
2897 During reload a memory reference with an invalid address may be passed
2898 as an operand. Such an address will be replaced with a valid address
2899 later in the reload pass. In this case, nothing may be done with the
2900 address except to use it as it stands. If it is copied, it will not be
2901 replaced with a valid address. No attempt should be made to make such
2902 an address into a valid address and no routine (such as
2903 @code{change_address}) that will do so may be called. Note that
2904 @code{general_operand} will fail when applied to such an address.
2906 @findex reload_in_progress
2907 The global variable @code{reload_in_progress} (which must be explicitly
2908 declared if required) can be used to determine whether such special
2909 handling is required.
2911 The variety of operands that have reloads depends on the rest of the
2912 machine description, but typically on a RISC machine these can only be
2913 pseudo registers that did not get hard registers, while on other
2914 machines explicit memory references will get optional reloads.
2916 If a scratch register is required to move an object to or from memory,
2917 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
2919 If there are cases which need scratch registers during or after reload,
2920 you must define @code{SECONDARY_INPUT_RELOAD_CLASS} and/or
2921 @code{SECONDARY_OUTPUT_RELOAD_CLASS} to detect them, and provide
2922 patterns @samp{reload_in@var{m}} or @samp{reload_out@var{m}} to handle
2923 them. @xref{Register Classes}.
2925 @findex no_new_pseudos
2926 The global variable @code{no_new_pseudos} can be used to determine if it
2927 is unsafe to create new pseudo registers. If this variable is nonzero, then
2928 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
2930 The constraints on a @samp{mov@var{m}} must permit moving any hard
2931 register to any other hard register provided that
2932 @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
2933 @code{REGISTER_MOVE_COST} applied to their classes returns a value of 2.
2935 It is obligatory to support floating point @samp{mov@var{m}}
2936 instructions into and out of any registers that can hold fixed point
2937 values, because unions and structures (which have modes @code{SImode} or
2938 @code{DImode}) can be in those registers and they may have floating
2941 There may also be a need to support fixed point @samp{mov@var{m}}
2942 instructions in and out of floating point registers. Unfortunately, I
2943 have forgotten why this was so, and I don't know whether it is still
2944 true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
2945 floating point registers, then the constraints of the fixed point
2946 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
2947 reload into a floating point register.
2949 @cindex @code{reload_in} instruction pattern
2950 @cindex @code{reload_out} instruction pattern
2951 @item @samp{reload_in@var{m}}
2952 @itemx @samp{reload_out@var{m}}
2953 Like @samp{mov@var{m}}, but used when a scratch register is required to
2954 move between operand 0 and operand 1. Operand 2 describes the scratch
2955 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
2956 macro in @pxref{Register Classes}.
2958 There are special restrictions on the form of the @code{match_operand}s
2959 used in these patterns. First, only the predicate for the reload
2960 operand is examined, i.e., @code{reload_in} examines operand 1, but not
2961 the predicates for operand 0 or 2. Second, there may be only one
2962 alternative in the constraints. Third, only a single register class
2963 letter may be used for the constraint; subsequent constraint letters
2964 are ignored. As a special exception, an empty constraint string
2965 matches the @code{ALL_REGS} register class. This may relieve ports
2966 of the burden of defining an @code{ALL_REGS} constraint letter just
2969 @cindex @code{movstrict@var{m}} instruction pattern
2970 @item @samp{movstrict@var{m}}
2971 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
2972 with mode @var{m} of a register whose natural mode is wider,
2973 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
2974 any of the register except the part which belongs to mode @var{m}.
2976 @cindex @code{movmisalign@var{m}} instruction pattern
2977 @item @samp{movmisalign@var{m}}
2978 This variant of a move pattern is designed to load or store a value
2979 from a memory address that is not naturally aligned for its mode.
2980 For a store, the memory will be in operand 0; for a load, the memory
2981 will be in operand 1. The other operand is guaranteed not to be a
2982 memory, so that it's easy to tell whether this is a load or store.
2984 This pattern is used by the autovectorizer, and when expanding a
2985 @code{MISALIGNED_INDIRECT_REF} expression.
2987 @cindex @code{load_multiple} instruction pattern
2988 @item @samp{load_multiple}
2989 Load several consecutive memory locations into consecutive registers.
2990 Operand 0 is the first of the consecutive registers, operand 1
2991 is the first memory location, and operand 2 is a constant: the
2992 number of consecutive registers.
2994 Define this only if the target machine really has such an instruction;
2995 do not define this if the most efficient way of loading consecutive
2996 registers from memory is to do them one at a time.
2998 On some machines, there are restrictions as to which consecutive
2999 registers can be stored into memory, such as particular starting or
3000 ending register numbers or only a range of valid counts. For those
3001 machines, use a @code{define_expand} (@pxref{Expander Definitions})
3002 and make the pattern fail if the restrictions are not met.
3004 Write the generated insn as a @code{parallel} with elements being a
3005 @code{set} of one register from the appropriate memory location (you may
3006 also need @code{use} or @code{clobber} elements). Use a
3007 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
3008 @file{rs6000.md} for examples of the use of this insn pattern.
3010 @cindex @samp{store_multiple} instruction pattern
3011 @item @samp{store_multiple}
3012 Similar to @samp{load_multiple}, but store several consecutive registers
3013 into consecutive memory locations. Operand 0 is the first of the
3014 consecutive memory locations, operand 1 is the first register, and
3015 operand 2 is a constant: the number of consecutive registers.
3017 @cindex @code{vec_set@var{m}} instruction pattern
3018 @item @samp{vec_set@var{m}}
3019 Set given field in the vector value. Operand 0 is the vector to modify,
3020 operand 1 is new value of field and operand 2 specify the field index.
3022 @cindex @code{vec_extract@var{m}} instruction pattern
3023 @item @samp{vec_extract@var{m}}
3024 Extract given field from the vector value. Operand 1 is the vector, operand 2
3025 specify field index and operand 0 place to store value into.
3027 @cindex @code{vec_init@var{m}} instruction pattern
3028 @item @samp{vec_init@var{m}}
3029 Initialize the vector to given values. Operand 0 is the vector to initialize
3030 and operand 1 is parallel containing values for individual fields.
3032 @cindex @code{push@var{m}} instruction pattern
3033 @item @samp{push@var{m}}
3034 Output a push instruction. Operand 0 is value to push. Used only when
3035 @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be
3036 missing and in such case an @code{mov} expander is used instead, with a
3037 @code{MEM} expression forming the push operation. The @code{mov} expander
3038 method is deprecated.
3040 @cindex @code{add@var{m}3} instruction pattern
3041 @item @samp{add@var{m}3}
3042 Add operand 2 and operand 1, storing the result in operand 0. All operands
3043 must have mode @var{m}. This can be used even on two-address machines, by
3044 means of constraints requiring operands 1 and 0 to be the same location.
3046 @cindex @code{sub@var{m}3} instruction pattern
3047 @cindex @code{mul@var{m}3} instruction pattern
3048 @cindex @code{div@var{m}3} instruction pattern
3049 @cindex @code{udiv@var{m}3} instruction pattern
3050 @cindex @code{mod@var{m}3} instruction pattern
3051 @cindex @code{umod@var{m}3} instruction pattern
3052 @cindex @code{umin@var{m}3} instruction pattern
3053 @cindex @code{umax@var{m}3} instruction pattern
3054 @cindex @code{and@var{m}3} instruction pattern
3055 @cindex @code{ior@var{m}3} instruction pattern
3056 @cindex @code{xor@var{m}3} instruction pattern
3057 @item @samp{sub@var{m}3}, @samp{mul@var{m}3}
3058 @itemx @samp{div@var{m}3}, @samp{udiv@var{m}3}
3059 @itemx @samp{mod@var{m}3}, @samp{umod@var{m}3}
3060 @itemx @samp{umin@var{m}3}, @samp{umax@var{m}3}
3061 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
3062 Similar, for other arithmetic operations.
3064 @cindex @code{min@var{m}3} instruction pattern
3065 @cindex @code{max@var{m}3} instruction pattern
3066 @item @samp{smin@var{m}3}, @samp{smax@var{m}3}
3067 Signed minimum and maximum operations. When used with floating point,
3068 if both operands are zeros, or if either operand is @code{NaN}, then
3069 it is unspecified which of the two operands is returned as the result.
3071 @cindex @code{reduc_smin_@var{m}} instruction pattern
3072 @cindex @code{reduc_smax_@var{m}} instruction pattern
3073 @item @samp{reduc_smin_@var{m}}, @samp{reduc_smax_@var{m}}
3074 Find the signed minimum/maximum of the elements of a vector. The vector is
3075 operand 1, and the scalar result is stored in the least significant bits of
3076 operand 0 (also a vector). The output and input vector should have the same
3079 @cindex @code{reduc_umin_@var{m}} instruction pattern
3080 @cindex @code{reduc_umax_@var{m}} instruction pattern
3081 @item @samp{reduc_umin_@var{m}}, @samp{reduc_umax_@var{m}}
3082 Find the unsigned minimum/maximum of the elements of a vector. The vector is
3083 operand 1, and the scalar result is stored in the least significant bits of
3084 operand 0 (also a vector). The output and input vector should have the same
3087 @cindex @code{reduc_splus_@var{m}} instruction pattern
3088 @item @samp{reduc_splus_@var{m}}
3089 Compute the sum of the signed elements of a vector. The vector is opernad 1,
3090 and the scalar result is stored in the least significant bits of opernad 0
3091 (also a vector). The output and input vector should have the same modes.
3093 @cindex @code{reduc_uplus_@var{m}} instruction pattern
3094 @item @samp{reduc_uplus_@var{m}}
3095 Compute the sum of the unsigned elements of a vector. The vector is opernad 1,
3096 and the scalar result is stored in the least significant bits of opernad 0
3097 (also a vector). The output and input vector should have the same modes.
3099 @cindex @code{vec_shl_@var{m}} instruction pattern
3100 @cindex @code{vec_shr_@var{m}} instruction pattern
3101 @item @samp{vec_shl_@var{m}}, @samp{vec_shr_@var{m}}
3102 Whole vector left/right shift in bits.
3103 Operand 1 is a vector to be shifted.
3104 Operand 2 is an integer shift amount in bits.
3105 Operand 0 is where the resulting shifted vector is stored.
3106 The output and input vectors should have the same modes.
3108 @cindex @code{mulhisi3} instruction pattern
3109 @item @samp{mulhisi3}
3110 Multiply operands 1 and 2, which have mode @code{HImode}, and store
3111 a @code{SImode} product in operand 0.
3113 @cindex @code{mulqihi3} instruction pattern
3114 @cindex @code{mulsidi3} instruction pattern
3115 @item @samp{mulqihi3}, @samp{mulsidi3}
3116 Similar widening-multiplication instructions of other widths.
3118 @cindex @code{umulqihi3} instruction pattern
3119 @cindex @code{umulhisi3} instruction pattern
3120 @cindex @code{umulsidi3} instruction pattern
3121 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
3122 Similar widening-multiplication instructions that do unsigned
3125 @cindex @code{smul@var{m}3_highpart} instruction pattern
3126 @item @samp{smul@var{m}3_highpart}
3127 Perform a signed multiplication of operands 1 and 2, which have mode
3128 @var{m}, and store the most significant half of the product in operand 0.
3129 The least significant half of the product is discarded.
3131 @cindex @code{umul@var{m}3_highpart} instruction pattern
3132 @item @samp{umul@var{m}3_highpart}
3133 Similar, but the multiplication is unsigned.
3135 @cindex @code{divmod@var{m}4} instruction pattern
3136 @item @samp{divmod@var{m}4}
3137 Signed division that produces both a quotient and a remainder.
3138 Operand 1 is divided by operand 2 to produce a quotient stored
3139 in operand 0 and a remainder stored in operand 3.
3141 For machines with an instruction that produces both a quotient and a
3142 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
3143 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
3144 allows optimization in the relatively common case when both the quotient
3145 and remainder are computed.
3147 If an instruction that just produces a quotient or just a remainder
3148 exists and is more efficient than the instruction that produces both,
3149 write the output routine of @samp{divmod@var{m}4} to call
3150 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
3151 quotient or remainder and generate the appropriate instruction.
3153 @cindex @code{udivmod@var{m}4} instruction pattern
3154 @item @samp{udivmod@var{m}4}
3155 Similar, but does unsigned division.
3157 @anchor{shift patterns}
3158 @cindex @code{ashl@var{m}3} instruction pattern
3159 @item @samp{ashl@var{m}3}
3160 Arithmetic-shift operand 1 left by a number of bits specified by operand
3161 2, and store the result in operand 0. Here @var{m} is the mode of
3162 operand 0 and operand 1; operand 2's mode is specified by the
3163 instruction pattern, and the compiler will convert the operand to that
3164 mode before generating the instruction. The meaning of out-of-range shift
3165 counts can optionally be specified by @code{TARGET_SHIFT_TRUNCATION_MASK}.
3166 @xref{TARGET_SHIFT_TRUNCATION_MASK}.
3168 @cindex @code{ashr@var{m}3} instruction pattern
3169 @cindex @code{lshr@var{m}3} instruction pattern
3170 @cindex @code{rotl@var{m}3} instruction pattern
3171 @cindex @code{rotr@var{m}3} instruction pattern
3172 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
3173 Other shift and rotate instructions, analogous to the
3174 @code{ashl@var{m}3} instructions.
3176 @cindex @code{neg@var{m}2} instruction pattern
3177 @item @samp{neg@var{m}2}
3178 Negate operand 1 and store the result in operand 0.
3180 @cindex @code{abs@var{m}2} instruction pattern
3181 @item @samp{abs@var{m}2}
3182 Store the absolute value of operand 1 into operand 0.
3184 @cindex @code{sqrt@var{m}2} instruction pattern
3185 @item @samp{sqrt@var{m}2}
3186 Store the square root of operand 1 into operand 0.
3188 The @code{sqrt} built-in function of C always uses the mode which
3189 corresponds to the C data type @code{double} and the @code{sqrtf}
3190 built-in function uses the mode which corresponds to the C data
3193 @cindex @code{cos@var{m}2} instruction pattern
3194 @item @samp{cos@var{m}2}
3195 Store the cosine of operand 1 into operand 0.
3197 The @code{cos} built-in function of C always uses the mode which
3198 corresponds to the C data type @code{double} and the @code{cosf}
3199 built-in function uses the mode which corresponds to the C data
3202 @cindex @code{sin@var{m}2} instruction pattern
3203 @item @samp{sin@var{m}2}
3204 Store the sine of operand 1 into operand 0.
3206 The @code{sin} built-in function of C always uses the mode which
3207 corresponds to the C data type @code{double} and the @code{sinf}
3208 built-in function uses the mode which corresponds to the C data
3211 @cindex @code{exp@var{m}2} instruction pattern
3212 @item @samp{exp@var{m}2}
3213 Store the exponential of operand 1 into operand 0.
3215 The @code{exp} built-in function of C always uses the mode which
3216 corresponds to the C data type @code{double} and the @code{expf}
3217 built-in function uses the mode which corresponds to the C data
3220 @cindex @code{log@var{m}2} instruction pattern
3221 @item @samp{log@var{m}2}
3222 Store the natural logarithm of operand 1 into operand 0.
3224 The @code{log} built-in function of C always uses the mode which
3225 corresponds to the C data type @code{double} and the @code{logf}
3226 built-in function uses the mode which corresponds to the C data
3229 @cindex @code{pow@var{m}3} instruction pattern
3230 @item @samp{pow@var{m}3}
3231 Store the value of operand 1 raised to the exponent operand 2
3234 The @code{pow} built-in function of C always uses the mode which
3235 corresponds to the C data type @code{double} and the @code{powf}
3236 built-in function uses the mode which corresponds to the C data
3239 @cindex @code{atan2@var{m}3} instruction pattern
3240 @item @samp{atan2@var{m}3}
3241 Store the arc tangent (inverse tangent) of operand 1 divided by
3242 operand 2 into operand 0, using the signs of both arguments to
3243 determine the quadrant of the result.
3245 The @code{atan2} built-in function of C always uses the mode which
3246 corresponds to the C data type @code{double} and the @code{atan2f}
3247 built-in function uses the mode which corresponds to the C data
3250 @cindex @code{floor@var{m}2} instruction pattern
3251 @item @samp{floor@var{m}2}
3252 Store the largest integral value not greater than argument.
3254 The @code{floor} built-in function of C always uses the mode which
3255 corresponds to the C data type @code{double} and the @code{floorf}
3256 built-in function uses the mode which corresponds to the C data
3259 @cindex @code{btrunc@var{m}2} instruction pattern
3260 @item @samp{btrunc@var{m}2}
3261 Store the argument rounded to integer towards zero.
3263 The @code{trunc} built-in function of C always uses the mode which
3264 corresponds to the C data type @code{double} and the @code{truncf}
3265 built-in function uses the mode which corresponds to the C data
3268 @cindex @code{round@var{m}2} instruction pattern
3269 @item @samp{round@var{m}2}
3270 Store the argument rounded to integer away from zero.
3272 The @code{round} built-in function of C always uses the mode which
3273 corresponds to the C data type @code{double} and the @code{roundf}
3274 built-in function uses the mode which corresponds to the C data
3277 @cindex @code{ceil@var{m}2} instruction pattern
3278 @item @samp{ceil@var{m}2}
3279 Store the argument rounded to integer away from zero.
3281 The @code{ceil} built-in function of C always uses the mode which
3282 corresponds to the C data type @code{double} and the @code{ceilf}
3283 built-in function uses the mode which corresponds to the C data
3286 @cindex @code{nearbyint@var{m}2} instruction pattern
3287 @item @samp{nearbyint@var{m}2}
3288 Store the argument rounded according to the default rounding mode
3290 The @code{nearbyint} built-in function of C always uses the mode which
3291 corresponds to the C data type @code{double} and the @code{nearbyintf}
3292 built-in function uses the mode which corresponds to the C data
3295 @cindex @code{rint@var{m}2} instruction pattern
3296 @item @samp{rint@var{m}2}
3297 Store the argument rounded according to the default rounding mode and
3298 raise the inexact exception when the result differs in value from
3301 The @code{rint} built-in function of C always uses the mode which
3302 corresponds to the C data type @code{double} and the @code{rintf}
3303 built-in function uses the mode which corresponds to the C data
3306 @cindex @code{ffs@var{m}2} instruction pattern
3307 @item @samp{ffs@var{m}2}
3308 Store into operand 0 one plus the index of the least significant 1-bit
3309 of operand 1. If operand 1 is zero, store zero. @var{m} is the mode
3310 of operand 0; operand 1's mode is specified by the instruction
3311 pattern, and the compiler will convert the operand to that mode before
3312 generating the instruction.
3314 The @code{ffs} built-in function of C always uses the mode which
3315 corresponds to the C data type @code{int}.
3317 @cindex @code{clz@var{m}2} instruction pattern
3318 @item @samp{clz@var{m}2}
3319 Store into operand 0 the number of leading 0-bits in @var{x}, starting
3320 at the most significant bit position. If @var{x} is 0, the result is
3321 undefined. @var{m} is the mode of operand 0; operand 1's mode is
3322 specified by the instruction pattern, and the compiler will convert the
3323 operand to that mode before generating the instruction.
3325 @cindex @code{ctz@var{m}2} instruction pattern
3326 @item @samp{ctz@var{m}2}
3327 Store into operand 0 the number of trailing 0-bits in @var{x}, starting
3328 at the least significant bit position. If @var{x} is 0, the result is
3329 undefined. @var{m} is the mode of operand 0; operand 1's mode is
3330 specified by the instruction pattern, and the compiler will convert the
3331 operand to that mode before generating the instruction.
3333 @cindex @code{popcount@var{m}2} instruction pattern
3334 @item @samp{popcount@var{m}2}
3335 Store into operand 0 the number of 1-bits in @var{x}. @var{m} is the
3336 mode of operand 0; operand 1's mode is specified by the instruction
3337 pattern, and the compiler will convert the operand to that mode before
3338 generating the instruction.
3340 @cindex @code{parity@var{m}2} instruction pattern
3341 @item @samp{parity@var{m}2}
3342 Store into operand 0 the parity of @var{x}, i.e.@: the number of 1-bits
3343 in @var{x} modulo 2. @var{m} is the mode of operand 0; operand 1's mode
3344 is specified by the instruction pattern, and the compiler will convert
3345 the operand to that mode before generating the instruction.
3347 @cindex @code{one_cmpl@var{m}2} instruction pattern
3348 @item @samp{one_cmpl@var{m}2}
3349 Store the bitwise-complement of operand 1 into operand 0.
3351 @cindex @code{cmp@var{m}} instruction pattern
3352 @item @samp{cmp@var{m}}
3353 Compare operand 0 and operand 1, and set the condition codes.
3354 The RTL pattern should look like this:
3357 (set (cc0) (compare (match_operand:@var{m} 0 @dots{})
3358 (match_operand:@var{m} 1 @dots{})))
3361 @cindex @code{tst@var{m}} instruction pattern
3362 @item @samp{tst@var{m}}
3363 Compare operand 0 against zero, and set the condition codes.
3364 The RTL pattern should look like this:
3367 (set (cc0) (match_operand:@var{m} 0 @dots{}))
3370 @samp{tst@var{m}} patterns should not be defined for machines that do
3371 not use @code{(cc0)}. Doing so would confuse the optimizer since it
3372 would no longer be clear which @code{set} operations were comparisons.
3373 The @samp{cmp@var{m}} patterns should be used instead.
3375 @cindex @code{movmem@var{m}} instruction pattern
3376 @item @samp{movmem@var{m}}
3377 Block move instruction. The destination and source blocks of memory
3378 are the first two operands, and both are @code{mem:BLK}s with an
3379 address in mode @code{Pmode}.
3381 The number of bytes to move is the third operand, in mode @var{m}.
3382 Usually, you specify @code{word_mode} for @var{m}. However, if you can
3383 generate better code knowing the range of valid lengths is smaller than
3384 those representable in a full word, you should provide a pattern with a
3385 mode corresponding to the range of values you can handle efficiently
3386 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
3387 that appear negative) and also a pattern with @code{word_mode}.
3389 The fourth operand is the known shared alignment of the source and
3390 destination, in the form of a @code{const_int} rtx. Thus, if the
3391 compiler knows that both source and destination are word-aligned,
3392 it may provide the value 4 for this operand.
3394 Descriptions of multiple @code{movmem@var{m}} patterns can only be
3395 beneficial if the patterns for smaller modes have fewer restrictions
3396 on their first, second and fourth operands. Note that the mode @var{m}
3397 in @code{movmem@var{m}} does not impose any restriction on the mode of
3398 individually moved data units in the block.
3400 These patterns need not give special consideration to the possibility
3401 that the source and destination strings might overlap.
3403 @cindex @code{movstr} instruction pattern
3405 String copy instruction, with @code{stpcpy} semantics. Operand 0 is
3406 an output operand in mode @code{Pmode}. The addresses of the
3407 destination and source strings are operands 1 and 2, and both are
3408 @code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of
3409 the expansion of this pattern should store in operand 0 the address in
3410 which the @code{NUL} terminator was stored in the destination string.
3412 @cindex @code{setmem@var{m}} instruction pattern
3413 @item @samp{setmem@var{m}}
3414 Block set instruction. The destination string is the first operand,
3415 given as a @code{mem:BLK} whose address is in mode @code{Pmode}. The
3416 number of bytes to set is the second operand, in mode @var{m}. The value to
3417 initialize the memory with is the third operand. Targets that only support the
3418 clearing of memory should reject any value that is not the constant 0. See
3419 @samp{movmem@var{m}} for a discussion of the choice of mode.
3421 The fourth operand is the known alignment of the destination, in the form
3422 of a @code{const_int} rtx. Thus, if the compiler knows that the
3423 destination is word-aligned, it may provide the value 4 for this
3426 The use for multiple @code{setmem@var{m}} is as for @code{movmem@var{m}}.
3428 @cindex @code{cmpstrn@var{m}} instruction pattern
3429 @item @samp{cmpstrn@var{m}}
3430 String compare instruction, with five operands. Operand 0 is the output;
3431 it has mode @var{m}. The remaining four operands are like the operands
3432 of @samp{movmem@var{m}}. The two memory blocks specified are compared
3433 byte by byte in lexicographic order starting at the beginning of each
3434 string. The instruction is not allowed to prefetch more than one byte
3435 at a time since either string may end in the first byte and reading past
3436 that may access an invalid page or segment and cause a fault. The
3437 effect of the instruction is to store a value in operand 0 whose sign
3438 indicates the result of the comparison.
3440 @cindex @code{cmpstr@var{m}} instruction pattern
3441 @item @samp{cmpstr@var{m}}
3442 String compare instruction, without known maximum length. Operand 0 is the
3443 output; it has mode @var{m}. The second and third operand are the blocks of
3444 memory to be compared; both are @code{mem:BLK} with an address in mode
3447 The fourth operand is the known shared alignment of the source and
3448 destination, in the form of a @code{const_int} rtx. Thus, if the
3449 compiler knows that both source and destination are word-aligned,
3450 it may provide the value 4 for this operand.
3452 The two memory blocks specified are compared byte by byte in lexicographic
3453 order starting at the beginning of each string. The instruction is not allowed
3454 to prefetch more than one byte at a time since either string may end in the
3455 first byte and reading past that may access an invalid page or segment and
3456 cause a fault. The effect of the instruction is to store a value in operand 0
3457 whose sign indicates the result of the comparison.
3459 @cindex @code{cmpmem@var{m}} instruction pattern
3460 @item @samp{cmpmem@var{m}}
3461 Block compare instruction, with five operands like the operands
3462 of @samp{cmpstr@var{m}}. The two memory blocks specified are compared
3463 byte by byte in lexicographic order starting at the beginning of each
3464 block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch
3465 any bytes in the two memory blocks. The effect of the instruction is
3466 to store a value in operand 0 whose sign indicates the result of the
3469 @cindex @code{strlen@var{m}} instruction pattern
3470 @item @samp{strlen@var{m}}
3471 Compute the length of a string, with three operands.
3472 Operand 0 is the result (of mode @var{m}), operand 1 is
3473 a @code{mem} referring to the first character of the string,
3474 operand 2 is the character to search for (normally zero),
3475 and operand 3 is a constant describing the known alignment
3476 of the beginning of the string.
3478 @cindex @code{float@var{mn}2} instruction pattern
3479 @item @samp{float@var{m}@var{n}2}
3480 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
3481 floating point mode @var{n} and store in operand 0 (which has mode
3484 @cindex @code{floatuns@var{mn}2} instruction pattern
3485 @item @samp{floatuns@var{m}@var{n}2}
3486 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
3487 to floating point mode @var{n} and store in operand 0 (which has mode
3490 @cindex @code{fix@var{mn}2} instruction pattern
3491 @item @samp{fix@var{m}@var{n}2}
3492 Convert operand 1 (valid for floating point mode @var{m}) to fixed
3493 point mode @var{n} as a signed number and store in operand 0 (which
3494 has mode @var{n}). This instruction's result is defined only when
3495 the value of operand 1 is an integer.
3497 If the machine description defines this pattern, it also needs to
3498 define the @code{ftrunc} pattern.
3500 @cindex @code{fixuns@var{mn}2} instruction pattern
3501 @item @samp{fixuns@var{m}@var{n}2}
3502 Convert operand 1 (valid for floating point mode @var{m}) to fixed
3503 point mode @var{n} as an unsigned number and store in operand 0 (which
3504 has mode @var{n}). This instruction's result is defined only when the
3505 value of operand 1 is an integer.
3507 @cindex @code{ftrunc@var{m}2} instruction pattern
3508 @item @samp{ftrunc@var{m}2}
3509 Convert operand 1 (valid for floating point mode @var{m}) to an
3510 integer value, still represented in floating point mode @var{m}, and
3511 store it in operand 0 (valid for floating point mode @var{m}).
3513 @cindex @code{fix_trunc@var{mn}2} instruction pattern
3514 @item @samp{fix_trunc@var{m}@var{n}2}
3515 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
3516 of mode @var{m} by converting the value to an integer.
3518 @cindex @code{fixuns_trunc@var{mn}2} instruction pattern
3519 @item @samp{fixuns_trunc@var{m}@var{n}2}
3520 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
3521 value of mode @var{m} by converting the value to an integer.
3523 @cindex @code{trunc@var{mn}2} instruction pattern
3524 @item @samp{trunc@var{m}@var{n}2}
3525 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
3526 store in operand 0 (which has mode @var{n}). Both modes must be fixed
3527 point or both floating point.
3529 @cindex @code{extend@var{mn}2} instruction pattern
3530 @item @samp{extend@var{m}@var{n}2}
3531 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
3532 store in operand 0 (which has mode @var{n}). Both modes must be fixed
3533 point or both floating point.
3535 @cindex @code{zero_extend@var{mn}2} instruction pattern
3536 @item @samp{zero_extend@var{m}@var{n}2}
3537 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
3538 store in operand 0 (which has mode @var{n}). Both modes must be fixed
3541 @cindex @code{extv} instruction pattern
3543 Extract a bit-field from operand 1 (a register or memory operand), where
3544 operand 2 specifies the width in bits and operand 3 the starting bit,
3545 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
3546 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
3547 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
3548 be valid for @code{word_mode}.
3550 The RTL generation pass generates this instruction only with constants
3551 for operands 2 and 3.
3553 The bit-field value is sign-extended to a full word integer
3554 before it is stored in operand 0.
3556 @cindex @code{extzv} instruction pattern
3558 Like @samp{extv} except that the bit-field value is zero-extended.
3560 @cindex @code{insv} instruction pattern
3562 Store operand 3 (which must be valid for @code{word_mode}) into a
3563 bit-field in operand 0, where operand 1 specifies the width in bits and
3564 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
3565 @code{word_mode}; often @code{word_mode} is allowed only for registers.
3566 Operands 1 and 2 must be valid for @code{word_mode}.
3568 The RTL generation pass generates this instruction only with constants
3569 for operands 1 and 2.
3571 @cindex @code{mov@var{mode}cc} instruction pattern
3572 @item @samp{mov@var{mode}cc}
3573 Conditionally move operand 2 or operand 3 into operand 0 according to the
3574 comparison in operand 1. If the comparison is true, operand 2 is moved
3575 into operand 0, otherwise operand 3 is moved.
3577 The mode of the operands being compared need not be the same as the operands
3578 being moved. Some machines, sparc64 for example, have instructions that
3579 conditionally move an integer value based on the floating point condition
3580 codes and vice versa.
3582 If the machine does not have conditional move instructions, do not
3583 define these patterns.
3585 @cindex @code{add@var{mode}cc} instruction pattern
3586 @item @samp{add@var{mode}cc}
3587 Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally
3588 move operand 2 or (operands 2 + operand 3) into operand 0 according to the
3589 comparison in operand 1. If the comparison is true, operand 2 is moved into
3590 operand 0, otherwise (operand 2 + operand 3) is moved.
3592 @cindex @code{s@var{cond}} instruction pattern
3593 @item @samp{s@var{cond}}
3594 Store zero or nonzero in the operand according to the condition codes.
3595 Value stored is nonzero iff the condition @var{cond} is true.
3596 @var{cond} is the name of a comparison operation expression code, such
3597 as @code{eq}, @code{lt} or @code{leu}.
3599 You specify the mode that the operand must have when you write the
3600 @code{match_operand} expression. The compiler automatically sees
3601 which mode you have used and supplies an operand of that mode.
3603 The value stored for a true condition must have 1 as its low bit, or
3604 else must be negative. Otherwise the instruction is not suitable and
3605 you should omit it from the machine description. You describe to the
3606 compiler exactly which value is stored by defining the macro
3607 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
3608 found that can be used for all the @samp{s@var{cond}} patterns, you
3609 should omit those operations from the machine description.
3611 These operations may fail, but should do so only in relatively
3612 uncommon cases; if they would fail for common cases involving
3613 integer comparisons, it is best to omit these patterns.
3615 If these operations are omitted, the compiler will usually generate code
3616 that copies the constant one to the target and branches around an
3617 assignment of zero to the target. If this code is more efficient than
3618 the potential instructions used for the @samp{s@var{cond}} pattern
3619 followed by those required to convert the result into a 1 or a zero in
3620 @code{SImode}, you should omit the @samp{s@var{cond}} operations from
3621 the machine description.
3623 @cindex @code{b@var{cond}} instruction pattern
3624 @item @samp{b@var{cond}}
3625 Conditional branch instruction. Operand 0 is a @code{label_ref} that
3626 refers to the label to jump to. Jump if the condition codes meet
3627 condition @var{cond}.
3629 Some machines do not follow the model assumed here where a comparison
3630 instruction is followed by a conditional branch instruction. In that
3631 case, the @samp{cmp@var{m}} (and @samp{tst@var{m}}) patterns should
3632 simply store the operands away and generate all the required insns in a
3633 @code{define_expand} (@pxref{Expander Definitions}) for the conditional
3634 branch operations. All calls to expand @samp{b@var{cond}} patterns are
3635 immediately preceded by calls to expand either a @samp{cmp@var{m}}
3636 pattern or a @samp{tst@var{m}} pattern.
3638 Machines that use a pseudo register for the condition code value, or
3639 where the mode used for the comparison depends on the condition being
3640 tested, should also use the above mechanism. @xref{Jump Patterns}.
3642 The above discussion also applies to the @samp{mov@var{mode}cc} and
3643 @samp{s@var{cond}} patterns.
3645 @cindex @code{cbranch@var{mode}4} instruction pattern
3646 @item @samp{cbranch@var{mode}4}
3647 Conditional branch instruction combined with a compare instruction.
3648 Operand 0 is a comparison operator. Operand 1 and operand 2 are the
3649 first and second operands of the comparison, respectively. Operand 3
3650 is a @code{label_ref} that refers to the label to jump to.
3652 @cindex @code{jump} instruction pattern
3654 A jump inside a function; an unconditional branch. Operand 0 is the
3655 @code{label_ref} of the label to jump to. This pattern name is mandatory
3658 @cindex @code{call} instruction pattern
3660 Subroutine call instruction returning no value. Operand 0 is the
3661 function to call; operand 1 is the number of bytes of arguments pushed
3662 as a @code{const_int}; operand 2 is the number of registers used as
3665 On most machines, operand 2 is not actually stored into the RTL
3666 pattern. It is supplied for the sake of some RISC machines which need
3667 to put this information into the assembler code; they can put it in
3668 the RTL instead of operand 1.
3670 Operand 0 should be a @code{mem} RTX whose address is the address of the
3671 function. Note, however, that this address can be a @code{symbol_ref}
3672 expression even if it would not be a legitimate memory address on the
3673 target machine. If it is also not a valid argument for a call
3674 instruction, the pattern for this operation should be a
3675 @code{define_expand} (@pxref{Expander Definitions}) that places the
3676 address into a register and uses that register in the call instruction.
3678 @cindex @code{call_value} instruction pattern
3679 @item @samp{call_value}
3680 Subroutine call instruction returning a value. Operand 0 is the hard
3681 register in which the value is returned. There are three more
3682 operands, the same as the three operands of the @samp{call}
3683 instruction (but with numbers increased by one).
3685 Subroutines that return @code{BLKmode} objects use the @samp{call}
3688 @cindex @code{call_pop} instruction pattern
3689 @cindex @code{call_value_pop} instruction pattern
3690 @item @samp{call_pop}, @samp{call_value_pop}
3691 Similar to @samp{call} and @samp{call_value}, except used if defined and
3692 if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel}
3693 that contains both the function call and a @code{set} to indicate the
3694 adjustment made to the frame pointer.
3696 For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these
3697 patterns increases the number of functions for which the frame pointer
3698 can be eliminated, if desired.
3700 @cindex @code{untyped_call} instruction pattern
3701 @item @samp{untyped_call}
3702 Subroutine call instruction returning a value of any type. Operand 0 is
3703 the function to call; operand 1 is a memory location where the result of
3704 calling the function is to be stored; operand 2 is a @code{parallel}
3705 expression where each element is a @code{set} expression that indicates
3706 the saving of a function return value into the result block.
3708 This instruction pattern should be defined to support
3709 @code{__builtin_apply} on machines where special instructions are needed
3710 to call a subroutine with arbitrary arguments or to save the value
3711 returned. This instruction pattern is required on machines that have
3712 multiple registers that can hold a return value
3713 (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
3715 @cindex @code{return} instruction pattern
3717 Subroutine return instruction. This instruction pattern name should be
3718 defined only if a single instruction can do all the work of returning
3721 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
3722 RTL generation phase. In this case it is to support machines where
3723 multiple instructions are usually needed to return from a function, but
3724 some class of functions only requires one instruction to implement a
3725 return. Normally, the applicable functions are those which do not need
3726 to save any registers or allocate stack space.
3728 @findex reload_completed
3729 @findex leaf_function_p
3730 For such machines, the condition specified in this pattern should only
3731 be true when @code{reload_completed} is nonzero and the function's
3732 epilogue would only be a single instruction. For machines with register
3733 windows, the routine @code{leaf_function_p} may be used to determine if
3734 a register window push is required.
3736 Machines that have conditional return instructions should define patterns
3742 (if_then_else (match_operator
3743 0 "comparison_operator"
3744 [(cc0) (const_int 0)])
3751 where @var{condition} would normally be the same condition specified on the
3752 named @samp{return} pattern.
3754 @cindex @code{untyped_return} instruction pattern
3755 @item @samp{untyped_return}
3756 Untyped subroutine return instruction. This instruction pattern should
3757 be defined to support @code{__builtin_return} on machines where special
3758 instructions are needed to return a value of any type.
3760 Operand 0 is a memory location where the result of calling a function
3761 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
3762 expression where each element is a @code{set} expression that indicates
3763 the restoring of a function return value from the result block.
3765 @cindex @code{nop} instruction pattern
3767 No-op instruction. This instruction pattern name should always be defined
3768 to output a no-op in assembler code. @code{(const_int 0)} will do as an
3771 @cindex @code{indirect_jump} instruction pattern
3772 @item @samp{indirect_jump}
3773 An instruction to jump to an address which is operand zero.
3774 This pattern name is mandatory on all machines.
3776 @cindex @code{casesi} instruction pattern
3778 Instruction to jump through a dispatch table, including bounds checking.
3779 This instruction takes five operands:
3783 The index to dispatch on, which has mode @code{SImode}.
3786 The lower bound for indices in the table, an integer constant.
3789 The total range of indices in the table---the largest index
3790 minus the smallest one (both inclusive).
3793 A label that precedes the table itself.
3796 A label to jump to if the index has a value outside the bounds.
3799 The table is a @code{addr_vec} or @code{addr_diff_vec} inside of a
3800 @code{jump_insn}. The number of elements in the table is one plus the
3801 difference between the upper bound and the lower bound.
3803 @cindex @code{tablejump} instruction pattern
3804 @item @samp{tablejump}
3805 Instruction to jump to a variable address. This is a low-level
3806 capability which can be used to implement a dispatch table when there
3807 is no @samp{casesi} pattern.
3809 This pattern requires two operands: the address or offset, and a label
3810 which should immediately precede the jump table. If the macro
3811 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
3812 operand is an offset which counts from the address of the table; otherwise,
3813 it is an absolute address to jump to. In either case, the first operand has
3816 The @samp{tablejump} insn is always the last insn before the jump
3817 table it uses. Its assembler code normally has no need to use the
3818 second operand, but you should incorporate it in the RTL pattern so
3819 that the jump optimizer will not delete the table as unreachable code.
3822 @cindex @code{decrement_and_branch_until_zero} instruction pattern
3823 @item @samp{decrement_and_branch_until_zero}
3824 Conditional branch instruction that decrements a register and
3825 jumps if the register is nonzero. Operand 0 is the register to
3826 decrement and test; operand 1 is the label to jump to if the
3827 register is nonzero. @xref{Looping Patterns}.
3829 This optional instruction pattern is only used by the combiner,
3830 typically for loops reversed by the loop optimizer when strength
3831 reduction is enabled.
3833 @cindex @code{doloop_end} instruction pattern
3834 @item @samp{doloop_end}
3835 Conditional branch instruction that decrements a register and jumps if
3836 the register is nonzero. This instruction takes five operands: Operand
3837 0 is the register to decrement and test; operand 1 is the number of loop
3838 iterations as a @code{const_int} or @code{const0_rtx} if this cannot be
3839 determined until run-time; operand 2 is the actual or estimated maximum
3840 number of iterations as a @code{const_int}; operand 3 is the number of
3841 enclosed loops as a @code{const_int} (an innermost loop has a value of
3842 1); operand 4 is the label to jump to if the register is nonzero.
3843 @xref{Looping Patterns}.
3845 This optional instruction pattern should be defined for machines with
3846 low-overhead looping instructions as the loop optimizer will try to
3847 modify suitable loops to utilize it. If nested low-overhead looping is
3848 not supported, use a @code{define_expand} (@pxref{Expander Definitions})
3849 and make the pattern fail if operand 3 is not @code{const1_rtx}.
3850 Similarly, if the actual or estimated maximum number of iterations is
3851 too large for this instruction, make it fail.
3853 @cindex @code{doloop_begin} instruction pattern
3854 @item @samp{doloop_begin}
3855 Companion instruction to @code{doloop_end} required for machines that
3856 need to perform some initialization, such as loading special registers
3857 used by a low-overhead looping instruction. If initialization insns do
3858 not always need to be emitted, use a @code{define_expand}
3859 (@pxref{Expander Definitions}) and make it fail.
3862 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
3863 @item @samp{canonicalize_funcptr_for_compare}
3864 Canonicalize the function pointer in operand 1 and store the result
3867 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
3868 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
3869 and also has mode @code{Pmode}.
3871 Canonicalization of a function pointer usually involves computing
3872 the address of the function which would be called if the function
3873 pointer were used in an indirect call.
3875 Only define this pattern if function pointers on the target machine
3876 can have different values but still call the same function when
3877 used in an indirect call.
3879 @cindex @code{save_stack_block} instruction pattern
3880 @cindex @code{save_stack_function} instruction pattern
3881 @cindex @code{save_stack_nonlocal} instruction pattern
3882 @cindex @code{restore_stack_block} instruction pattern
3883 @cindex @code{restore_stack_function} instruction pattern
3884 @cindex @code{restore_stack_nonlocal} instruction pattern
3885 @item @samp{save_stack_block}
3886 @itemx @samp{save_stack_function}
3887 @itemx @samp{save_stack_nonlocal}
3888 @itemx @samp{restore_stack_block}
3889 @itemx @samp{restore_stack_function}
3890 @itemx @samp{restore_stack_nonlocal}
3891 Most machines save and restore the stack pointer by copying it to or
3892 from an object of mode @code{Pmode}. Do not define these patterns on
3895 Some machines require special handling for stack pointer saves and
3896 restores. On those machines, define the patterns corresponding to the
3897 non-standard cases by using a @code{define_expand} (@pxref{Expander
3898 Definitions}) that produces the required insns. The three types of
3899 saves and restores are:
3903 @samp{save_stack_block} saves the stack pointer at the start of a block
3904 that allocates a variable-sized object, and @samp{restore_stack_block}
3905 restores the stack pointer when the block is exited.
3908 @samp{save_stack_function} and @samp{restore_stack_function} do a
3909 similar job for the outermost block of a function and are used when the
3910 function allocates variable-sized objects or calls @code{alloca}. Only
3911 the epilogue uses the restored stack pointer, allowing a simpler save or
3912 restore sequence on some machines.
3915 @samp{save_stack_nonlocal} is used in functions that contain labels
3916 branched to by nested functions. It saves the stack pointer in such a
3917 way that the inner function can use @samp{restore_stack_nonlocal} to
3918 restore the stack pointer. The compiler generates code to restore the
3919 frame and argument pointer registers, but some machines require saving
3920 and restoring additional data such as register window information or
3921 stack backchains. Place insns in these patterns to save and restore any
3925 When saving the stack pointer, operand 0 is the save area and operand 1
3926 is the stack pointer. The mode used to allocate the save area defaults
3927 to @code{Pmode} but you can override that choice by defining the
3928 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
3929 specify an integral mode, or @code{VOIDmode} if no save area is needed
3930 for a particular type of save (either because no save is needed or
3931 because a machine-specific save area can be used). Operand 0 is the
3932 stack pointer and operand 1 is the save area for restore operations. If
3933 @samp{save_stack_block} is defined, operand 0 must not be
3934 @code{VOIDmode} since these saves can be arbitrarily nested.
3936 A save area is a @code{mem} that is at a constant offset from
3937 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
3938 nonlocal gotos and a @code{reg} in the other two cases.
3940 @cindex @code{allocate_stack} instruction pattern
3941 @item @samp{allocate_stack}
3942 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
3943 the stack pointer to create space for dynamically allocated data.
3945 Store the resultant pointer to this space into operand 0. If you
3946 are allocating space from the main stack, do this by emitting a
3947 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
3948 If you are allocating the space elsewhere, generate code to copy the
3949 location of the space to operand 0. In the latter case, you must
3950 ensure this space gets freed when the corresponding space on the main
3953 Do not define this pattern if all that must be done is the subtraction.
3954 Some machines require other operations such as stack probes or
3955 maintaining the back chain. Define this pattern to emit those
3956 operations in addition to updating the stack pointer.
3958 @cindex @code{check_stack} instruction pattern
3959 @item @samp{check_stack}
3960 If stack checking cannot be done on your system by probing the stack with
3961 a load or store instruction (@pxref{Stack Checking}), define this pattern
3962 to perform the needed check and signaling an error if the stack
3963 has overflowed. The single operand is the location in the stack furthest
3964 from the current stack pointer that you need to validate. Normally,
3965 on machines where this pattern is needed, you would obtain the stack
3966 limit from a global or thread-specific variable or register.
3968 @cindex @code{nonlocal_goto} instruction pattern
3969 @item @samp{nonlocal_goto}
3970 Emit code to generate a non-local goto, e.g., a jump from one function
3971 to a label in an outer function. This pattern has four arguments,
3972 each representing a value to be used in the jump. The first
3973 argument is to be loaded into the frame pointer, the second is
3974 the address to branch to (code to dispatch to the actual label),
3975 the third is the address of a location where the stack is saved,
3976 and the last is the address of the label, to be placed in the
3977 location for the incoming static chain.
3979 On most machines you need not define this pattern, since GCC will
3980 already generate the correct code, which is to load the frame pointer
3981 and static chain, restore the stack (using the
3982 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
3983 to the dispatcher. You need only define this pattern if this code will
3984 not work on your machine.
3986 @cindex @code{nonlocal_goto_receiver} instruction pattern
3987 @item @samp{nonlocal_goto_receiver}
3988 This pattern, if defined, contains code needed at the target of a
3989 nonlocal goto after the code already generated by GCC@. You will not
3990 normally need to define this pattern. A typical reason why you might
3991 need this pattern is if some value, such as a pointer to a global table,
3992 must be restored when the frame pointer is restored. Note that a nonlocal
3993 goto only occurs within a unit-of-translation, so a global table pointer
3994 that is shared by all functions of a given module need not be restored.
3995 There are no arguments.
3997 @cindex @code{exception_receiver} instruction pattern
3998 @item @samp{exception_receiver}
3999 This pattern, if defined, contains code needed at the site of an
4000 exception handler that isn't needed at the site of a nonlocal goto. You
4001 will not normally need to define this pattern. A typical reason why you
4002 might need this pattern is if some value, such as a pointer to a global
4003 table, must be restored after control flow is branched to the handler of
4004 an exception. There are no arguments.
4006 @cindex @code{builtin_setjmp_setup} instruction pattern
4007 @item @samp{builtin_setjmp_setup}
4008 This pattern, if defined, contains additional code needed to initialize
4009 the @code{jmp_buf}. You will not normally need to define this pattern.
4010 A typical reason why you might need this pattern is if some value, such
4011 as a pointer to a global table, must be restored. Though it is
4012 preferred that the pointer value be recalculated if possible (given the
4013 address of a label for instance). The single argument is a pointer to
4014 the @code{jmp_buf}. Note that the buffer is five words long and that
4015 the first three are normally used by the generic mechanism.
4017 @cindex @code{builtin_setjmp_receiver} instruction pattern
4018 @item @samp{builtin_setjmp_receiver}
4019 This pattern, if defined, contains code needed at the site of an
4020 built-in setjmp that isn't needed at the site of a nonlocal goto. You
4021 will not normally need to define this pattern. A typical reason why you
4022 might need this pattern is if some value, such as a pointer to a global
4023 table, must be restored. It takes one argument, which is the label
4024 to which builtin_longjmp transfered control; this pattern may be emitted
4025 at a small offset from that label.
4027 @cindex @code{builtin_longjmp} instruction pattern
4028 @item @samp{builtin_longjmp}
4029 This pattern, if defined, performs the entire action of the longjmp.
4030 You will not normally need to define this pattern unless you also define
4031 @code{builtin_setjmp_setup}. The single argument is a pointer to the
4034 @cindex @code{eh_return} instruction pattern
4035 @item @samp{eh_return}
4036 This pattern, if defined, affects the way @code{__builtin_eh_return},
4037 and thence the call frame exception handling library routines, are
4038 built. It is intended to handle non-trivial actions needed along
4039 the abnormal return path.
4041 The address of the exception handler to which the function should return
4042 is passed as operand to this pattern. It will normally need to copied by
4043 the pattern to some special register or memory location.
4044 If the pattern needs to determine the location of the target call
4045 frame in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX},
4046 if defined; it will have already been assigned.
4048 If this pattern is not defined, the default action will be to simply
4049 copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either
4050 that macro or this pattern needs to be defined if call frame exception
4051 handling is to be used.
4053 @cindex @code{prologue} instruction pattern
4054 @anchor{prologue instruction pattern}
4055 @item @samp{prologue}
4056 This pattern, if defined, emits RTL for entry to a function. The function
4057 entry is responsible for setting up the stack frame, initializing the frame
4058 pointer register, saving callee saved registers, etc.
4060 Using a prologue pattern is generally preferred over defining
4061 @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue.
4063 The @code{prologue} pattern is particularly useful for targets which perform
4064 instruction scheduling.
4066 @cindex @code{epilogue} instruction pattern
4067 @anchor{epilogue instruction pattern}
4068 @item @samp{epilogue}
4069 This pattern emits RTL for exit from a function. The function
4070 exit is responsible for deallocating the stack frame, restoring callee saved
4071 registers and emitting the return instruction.
4073 Using an epilogue pattern is generally preferred over defining
4074 @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue.
4076 The @code{epilogue} pattern is particularly useful for targets which perform
4077 instruction scheduling or which have delay slots for their return instruction.
4079 @cindex @code{sibcall_epilogue} instruction pattern
4080 @item @samp{sibcall_epilogue}
4081 This pattern, if defined, emits RTL for exit from a function without the final
4082 branch back to the calling function. This pattern will be emitted before any
4083 sibling call (aka tail call) sites.
4085 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
4086 parameter passing or any stack slots for arguments passed to the current
4089 @cindex @code{trap} instruction pattern
4091 This pattern, if defined, signals an error, typically by causing some
4092 kind of signal to be raised. Among other places, it is used by the Java
4093 front end to signal `invalid array index' exceptions.
4095 @cindex @code{conditional_trap} instruction pattern
4096 @item @samp{conditional_trap}
4097 Conditional trap instruction. Operand 0 is a piece of RTL which
4098 performs a comparison. Operand 1 is the trap code, an integer.
4100 A typical @code{conditional_trap} pattern looks like
4103 (define_insn "conditional_trap"
4104 [(trap_if (match_operator 0 "trap_operator"
4105 [(cc0) (const_int 0)])
4106 (match_operand 1 "const_int_operand" "i"))]
4111 @cindex @code{prefetch} instruction pattern
4112 @item @samp{prefetch}
4114 This pattern, if defined, emits code for a non-faulting data prefetch
4115 instruction. Operand 0 is the address of the memory to prefetch. Operand 1
4116 is a constant 1 if the prefetch is preparing for a write to the memory
4117 address, or a constant 0 otherwise. Operand 2 is the expected degree of
4118 temporal locality of the data and is a value between 0 and 3, inclusive; 0
4119 means that the data has no temporal locality, so it need not be left in the
4120 cache after the access; 3 means that the data has a high degree of temporal
4121 locality and should be left in all levels of cache possible; 1 and 2 mean,
4122 respectively, a low or moderate degree of temporal locality.
4124 Targets that do not support write prefetches or locality hints can ignore
4125 the values of operands 1 and 2.
4127 @cindex @code{memory_barrier} instruction pattern
4128 @item @samp{memory_barrier}
4130 If the target memory model is not fully synchronous, then this pattern
4131 should be defined to an instruction that orders both loads and stores
4132 before the instruction with respect to loads and stores after the instruction.
4133 This pattern has no operands.
4135 @cindex @code{sync_compare_and_swap@var{mode}} instruction pattern
4136 @item @samp{sync_compare_and_swap@var{mode}}
4138 This pattern, if defined, emits code for an atomic compare-and-swap
4139 operation. Operand 1 is the memory on which the atomic operation is
4140 performed. Operand 2 is the ``old'' value to be compared against the
4141 current contents of the memory location. Operand 3 is the ``new'' value
4142 to store in the memory if the compare succeeds. Operand 0 is the result
4143 of the operation; it should contain the contents of the memory
4144 before the operation. If the compare succeeds, this should obviously be
4145 a copy of operand 2.
4147 This pattern must show that both operand 0 and operand 1 are modified.
4149 This pattern must issue any memory barrier instructions such that all
4150 memory operations before the atomic operation occur before the atomic
4151 operation and all memory operations after the atomic operation occur
4152 after the atomic operation.
4154 @cindex @code{sync_compare_and_swap_cc@var{mode}} instruction pattern
4155 @item @samp{sync_compare_and_swap_cc@var{mode}}
4157 This pattern is just like @code{sync_compare_and_swap@var{mode}}, except
4158 it should act as if compare part of the compare-and-swap were issued via
4159 @code{cmp@var{m}}. This comparison will only be used with @code{EQ} and
4160 @code{NE} branches and @code{setcc} operations.
4162 Some targets do expose the success or failure of the compare-and-swap
4163 operation via the status flags. Ideally we wouldn't need a separate
4164 named pattern in order to take advantage of this, but the combine pass
4165 does not handle patterns with multiple sets, which is required by
4166 definition for @code{sync_compare_and_swap@var{mode}}.
4168 @cindex @code{sync_add@var{mode}} instruction pattern
4169 @cindex @code{sync_sub@var{mode}} instruction pattern
4170 @cindex @code{sync_ior@var{mode}} instruction pattern
4171 @cindex @code{sync_and@var{mode}} instruction pattern
4172 @cindex @code{sync_xor@var{mode}} instruction pattern
4173 @cindex @code{sync_nand@var{mode}} instruction pattern
4174 @item @samp{sync_add@var{mode}}, @samp{sync_sub@var{mode}}
4175 @itemx @samp{sync_ior@var{mode}}, @samp{sync_and@var{mode}}
4176 @itemx @samp{sync_xor@var{mode}}, @samp{sync_nand@var{mode}}
4178 These patterns emit code for an atomic operation on memory.
4179 Operand 0 is the memory on which the atomic operation is performed.
4180 Operand 1 is the second operand to the binary operator.
4182 The ``nand'' operation is @code{op0 & ~op1}.
4184 This pattern must issue any memory barrier instructions such that all
4185 memory operations before the atomic operation occur before the atomic
4186 operation and all memory operations after the atomic operation occur
4187 after the atomic operation.
4189 If these patterns are not defined, the operation will be constructed
4190 from a compare-and-swap operation, if defined.
4192 @cindex @code{sync_old_add@var{mode}} instruction pattern
4193 @cindex @code{sync_old_sub@var{mode}} instruction pattern
4194 @cindex @code{sync_old_ior@var{mode}} instruction pattern
4195 @cindex @code{sync_old_and@var{mode}} instruction pattern
4196 @cindex @code{sync_old_xor@var{mode}} instruction pattern
4197 @cindex @code{sync_old_nand@var{mode}} instruction pattern
4198 @item @samp{sync_old_add@var{mode}}, @samp{sync_old_sub@var{mode}}
4199 @itemx @samp{sync_old_ior@var{mode}}, @samp{sync_old_and@var{mode}}
4200 @itemx @samp{sync_old_xor@var{mode}}, @samp{sync_old_nand@var{mode}}
4202 These patterns are emit code for an atomic operation on memory,
4203 and return the value that the memory contained before the operation.
4204 Operand 0 is the result value, operand 1 is the memory on which the
4205 atomic operation is performed, and operand 2 is the second operand
4206 to the binary operator.
4208 This pattern must issue any memory barrier instructions such that all
4209 memory operations before the atomic operation occur before the atomic
4210 operation and all memory operations after the atomic operation occur
4211 after the atomic operation.
4213 If these patterns are not defined, the operation will be constructed
4214 from a compare-and-swap operation, if defined.
4216 @cindex @code{sync_new_add@var{mode}} instruction pattern
4217 @cindex @code{sync_new_sub@var{mode}} instruction pattern
4218 @cindex @code{sync_new_ior@var{mode}} instruction pattern
4219 @cindex @code{sync_new_and@var{mode}} instruction pattern
4220 @cindex @code{sync_new_xor@var{mode}} instruction pattern
4221 @cindex @code{sync_new_nand@var{mode}} instruction pattern
4222 @item @samp{sync_new_add@var{mode}}, @samp{sync_new_sub@var{mode}}
4223 @itemx @samp{sync_new_ior@var{mode}}, @samp{sync_new_and@var{mode}}
4224 @itemx @samp{sync_new_xor@var{mode}}, @samp{sync_new_nand@var{mode}}
4226 These patterns are like their @code{sync_old_@var{op}} counterparts,
4227 except that they return the value that exists in the memory location
4228 after the operation, rather than before the operation.
4230 @cindex @code{sync_lock_test_and_set@var{mode}} instruction pattern
4231 @item @samp{sync_lock_test_and_set@var{mode}}
4233 This pattern takes two forms, based on the capabilities of the target.
4234 In either case, operand 0 is the result of the operand, operand 1 is
4235 the memory on which the atomic operation is performed, and operand 2
4236 is the value to set in the lock.
4238 In the ideal case, this operation is an atomic exchange operation, in
4239 which the previous value in memory operand is copied into the result
4240 operand, and the value operand is stored in the memory operand.
4242 For less capable targets, any value operand that is not the constant 1
4243 should be rejected with @code{FAIL}. In this case the target may use
4244 an atomic test-and-set bit operation. The result operand should contain
4245 1 if the bit was previously set and 0 if the bit was previously clear.
4246 The true contents of the memory operand are implementation defined.
4248 This pattern must issue any memory barrier instructions such that the
4249 pattern as a whole acts as an acquire barrier, that is all memory
4250 operations after the pattern do not occur until the lock is acquired.
4252 If this pattern is not defined, the operation will be constructed from
4253 a compare-and-swap operation, if defined.
4255 @cindex @code{sync_lock_release@var{mode}} instruction pattern
4256 @item @samp{sync_lock_release@var{mode}}
4258 This pattern, if defined, releases a lock set by
4259 @code{sync_lock_test_and_set@var{mode}}. Operand 0 is the memory
4260 that contains the lock; operand 1 is the value to store in the lock.
4262 If the target doesn't implement full semantics for
4263 @code{sync_lock_test_and_set@var{mode}}, any value operand which is not
4264 the constant 0 should be rejected with @code{FAIL}, and the true contents
4265 of the memory operand are implementation defined.
4267 This pattern must issue any memory barrier instructions such that the
4268 pattern as a whole acts as a release barrier, that is the lock is
4269 released only after all previous memory operations have completed.
4271 If this pattern is not defined, then a @code{memory_barrier} pattern
4272 will be emitted, followed by a store of the value to the memory operand.
4274 @cindex @code{stack_protect_set} instruction pattern
4275 @item @samp{stack_protect_set}
4277 This pattern, if defined, moves a @code{Pmode} value from the memory
4278 in operand 1 to the memory in operand 0 without leaving the value in
4279 a register afterward. This is to avoid leaking the value some place
4280 that an attacker might use to rewrite the stack guard slot after
4281 having clobbered it.
4283 If this pattern is not defined, then a plain move pattern is generated.
4285 @cindex @code{stack_protect_test} instruction pattern
4286 @item @samp{stack_protect_test}
4288 This pattern, if defined, compares a @code{Pmode} value from the
4289 memory in operand 1 with the memory in operand 0 without leaving the
4290 value in a register afterward and branches to operand 2 if the values
4293 If this pattern is not defined, then a plain compare pattern and
4294 conditional branch pattern is used.
4299 @c Each of the following nodes are wrapped in separate
4300 @c "@ifset INTERNALS" to work around memory limits for the default
4301 @c configuration in older tetex distributions. Known to not work:
4302 @c tetex-1.0.7, known to work: tetex-2.0.2.
4304 @node Pattern Ordering
4305 @section When the Order of Patterns Matters
4306 @cindex Pattern Ordering
4307 @cindex Ordering of Patterns
4309 Sometimes an insn can match more than one instruction pattern. Then the
4310 pattern that appears first in the machine description is the one used.
4311 Therefore, more specific patterns (patterns that will match fewer things)
4312 and faster instructions (those that will produce better code when they
4313 do match) should usually go first in the description.
4315 In some cases the effect of ordering the patterns can be used to hide
4316 a pattern when it is not valid. For example, the 68000 has an
4317 instruction for converting a fullword to floating point and another
4318 for converting a byte to floating point. An instruction converting
4319 an integer to floating point could match either one. We put the
4320 pattern to convert the fullword first to make sure that one will
4321 be used rather than the other. (Otherwise a large integer might
4322 be generated as a single-byte immediate quantity, which would not work.)
4323 Instead of using this pattern ordering it would be possible to make the
4324 pattern for convert-a-byte smart enough to deal properly with any
4329 @node Dependent Patterns
4330 @section Interdependence of Patterns
4331 @cindex Dependent Patterns
4332 @cindex Interdependence of Patterns
4334 Every machine description must have a named pattern for each of the
4335 conditional branch names @samp{b@var{cond}}. The recognition template
4336 must always have the form
4340 (if_then_else (@var{cond} (cc0) (const_int 0))
4341 (label_ref (match_operand 0 "" ""))
4346 In addition, every machine description must have an anonymous pattern
4347 for each of the possible reverse-conditional branches. Their templates
4352 (if_then_else (@var{cond} (cc0) (const_int 0))
4354 (label_ref (match_operand 0 "" ""))))
4358 They are necessary because jump optimization can turn direct-conditional
4359 branches into reverse-conditional branches.
4361 It is often convenient to use the @code{match_operator} construct to
4362 reduce the number of patterns that must be specified for branches. For
4368 (if_then_else (match_operator 0 "comparison_operator"
4369 [(cc0) (const_int 0)])
4371 (label_ref (match_operand 1 "" ""))))]
4376 In some cases machines support instructions identical except for the
4377 machine mode of one or more operands. For example, there may be
4378 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
4382 (set (match_operand:SI 0 @dots{})
4383 (extend:SI (match_operand:HI 1 @dots{})))
4385 (set (match_operand:SI 0 @dots{})
4386 (extend:SI (match_operand:QI 1 @dots{})))
4390 Constant integers do not specify a machine mode, so an instruction to
4391 extend a constant value could match either pattern. The pattern it
4392 actually will match is the one that appears first in the file. For correct
4393 results, this must be the one for the widest possible mode (@code{HImode},
4394 here). If the pattern matches the @code{QImode} instruction, the results
4395 will be incorrect if the constant value does not actually fit that mode.
4397 Such instructions to extend constants are rarely generated because they are
4398 optimized away, but they do occasionally happen in nonoptimized
4401 If a constraint in a pattern allows a constant, the reload pass may
4402 replace a register with a constant permitted by the constraint in some
4403 cases. Similarly for memory references. Because of this substitution,
4404 you should not provide separate patterns for increment and decrement
4405 instructions. Instead, they should be generated from the same pattern
4406 that supports register-register add insns by examining the operands and
4407 generating the appropriate machine instruction.
4412 @section Defining Jump Instruction Patterns
4413 @cindex jump instruction patterns
4414 @cindex defining jump instruction patterns
4416 For most machines, GCC assumes that the machine has a condition code.
4417 A comparison insn sets the condition code, recording the results of both
4418 signed and unsigned comparison of the given operands. A separate branch
4419 insn tests the condition code and branches or not according its value.
4420 The branch insns come in distinct signed and unsigned flavors. Many
4421 common machines, such as the VAX, the 68000 and the 32000, work this
4424 Some machines have distinct signed and unsigned compare instructions, and
4425 only one set of conditional branch instructions. The easiest way to handle
4426 these machines is to treat them just like the others until the final stage
4427 where assembly code is written. At this time, when outputting code for the
4428 compare instruction, peek ahead at the following branch using
4429 @code{next_cc0_user (insn)}. (The variable @code{insn} refers to the insn
4430 being output, in the output-writing code in an instruction pattern.) If
4431 the RTL says that is an unsigned branch, output an unsigned compare;
4432 otherwise output a signed compare. When the branch itself is output, you
4433 can treat signed and unsigned branches identically.
4435 The reason you can do this is that GCC always generates a pair of
4436 consecutive RTL insns, possibly separated by @code{note} insns, one to
4437 set the condition code and one to test it, and keeps the pair inviolate
4440 To go with this technique, you must define the machine-description macro
4441 @code{NOTICE_UPDATE_CC} to do @code{CC_STATUS_INIT}; in other words, no
4442 compare instruction is superfluous.
4444 Some machines have compare-and-branch instructions and no condition code.
4445 A similar technique works for them. When it is time to ``output'' a
4446 compare instruction, record its operands in two static variables. When
4447 outputting the branch-on-condition-code instruction that follows, actually
4448 output a compare-and-branch instruction that uses the remembered operands.
4450 It also works to define patterns for compare-and-branch instructions.
4451 In optimizing compilation, the pair of compare and branch instructions
4452 will be combined according to these patterns. But this does not happen
4453 if optimization is not requested. So you must use one of the solutions
4454 above in addition to any special patterns you define.
4456 In many RISC machines, most instructions do not affect the condition
4457 code and there may not even be a separate condition code register. On
4458 these machines, the restriction that the definition and use of the
4459 condition code be adjacent insns is not necessary and can prevent
4460 important optimizations. For example, on the IBM RS/6000, there is a
4461 delay for taken branches unless the condition code register is set three
4462 instructions earlier than the conditional branch. The instruction
4463 scheduler cannot perform this optimization if it is not permitted to
4464 separate the definition and use of the condition code register.
4466 On these machines, do not use @code{(cc0)}, but instead use a register
4467 to represent the condition code. If there is a specific condition code
4468 register in the machine, use a hard register. If the condition code or
4469 comparison result can be placed in any general register, or if there are
4470 multiple condition registers, use a pseudo register.
4472 @findex prev_cc0_setter
4473 @findex next_cc0_user
4474 On some machines, the type of branch instruction generated may depend on
4475 the way the condition code was produced; for example, on the 68k and
4476 SPARC, setting the condition code directly from an add or subtract
4477 instruction does not clear the overflow bit the way that a test
4478 instruction does, so a different branch instruction must be used for
4479 some conditional branches. For machines that use @code{(cc0)}, the set
4480 and use of the condition code must be adjacent (separated only by
4481 @code{note} insns) allowing flags in @code{cc_status} to be used.
4482 (@xref{Condition Code}.) Also, the comparison and branch insns can be
4483 located from each other by using the functions @code{prev_cc0_setter}
4484 and @code{next_cc0_user}.
4486 However, this is not true on machines that do not use @code{(cc0)}. On
4487 those machines, no assumptions can be made about the adjacency of the
4488 compare and branch insns and the above methods cannot be used. Instead,
4489 we use the machine mode of the condition code register to record
4490 different formats of the condition code register.
4492 Registers used to store the condition code value should have a mode that
4493 is in class @code{MODE_CC}. Normally, it will be @code{CCmode}. If
4494 additional modes are required (as for the add example mentioned above in
4495 the SPARC), define them in @file{@var{machine}-modes.def}
4496 (@pxref{Condition Code}). Also define @code{SELECT_CC_MODE} to choose
4497 a mode given an operand of a compare.
4499 If it is known during RTL generation that a different mode will be
4500 required (for example, if the machine has separate compare instructions
4501 for signed and unsigned quantities, like most IBM processors), they can
4502 be specified at that time.
4504 If the cases that require different modes would be made by instruction
4505 combination, the macro @code{SELECT_CC_MODE} determines which machine
4506 mode should be used for the comparison result. The patterns should be
4507 written using that mode. To support the case of the add on the SPARC
4508 discussed above, we have the pattern
4512 [(set (reg:CC_NOOV 0)
4514 (plus:SI (match_operand:SI 0 "register_operand" "%r")
4515 (match_operand:SI 1 "arith_operand" "rI"))
4521 The @code{SELECT_CC_MODE} macro on the SPARC returns @code{CC_NOOVmode}
4522 for comparisons whose argument is a @code{plus}.
4526 @node Looping Patterns
4527 @section Defining Looping Instruction Patterns
4528 @cindex looping instruction patterns
4529 @cindex defining looping instruction patterns
4531 Some machines have special jump instructions that can be utilized to
4532 make loops more efficient. A common example is the 68000 @samp{dbra}
4533 instruction which performs a decrement of a register and a branch if the
4534 result was greater than zero. Other machines, in particular digital
4535 signal processors (DSPs), have special block repeat instructions to
4536 provide low-overhead loop support. For example, the TI TMS320C3x/C4x
4537 DSPs have a block repeat instruction that loads special registers to
4538 mark the top and end of a loop and to count the number of loop
4539 iterations. This avoids the need for fetching and executing a
4540 @samp{dbra}-like instruction and avoids pipeline stalls associated with
4543 GCC has three special named patterns to support low overhead looping.
4544 They are @samp{decrement_and_branch_until_zero}, @samp{doloop_begin},
4545 and @samp{doloop_end}. The first pattern,
4546 @samp{decrement_and_branch_until_zero}, is not emitted during RTL
4547 generation but may be emitted during the instruction combination phase.
4548 This requires the assistance of the loop optimizer, using information
4549 collected during strength reduction, to reverse a loop to count down to
4550 zero. Some targets also require the loop optimizer to add a
4551 @code{REG_NONNEG} note to indicate that the iteration count is always
4552 positive. This is needed if the target performs a signed loop
4553 termination test. For example, the 68000 uses a pattern similar to the
4554 following for its @code{dbra} instruction:
4558 (define_insn "decrement_and_branch_until_zero"
4561 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
4564 (label_ref (match_operand 1 "" ""))
4567 (plus:SI (match_dup 0)
4569 "find_reg_note (insn, REG_NONNEG, 0)"
4574 Note that since the insn is both a jump insn and has an output, it must
4575 deal with its own reloads, hence the `m' constraints. Also note that
4576 since this insn is generated by the instruction combination phase
4577 combining two sequential insns together into an implicit parallel insn,
4578 the iteration counter needs to be biased by the same amount as the
4579 decrement operation, in this case @minus{}1. Note that the following similar
4580 pattern will not be matched by the combiner.
4584 (define_insn "decrement_and_branch_until_zero"
4587 (ge (match_operand:SI 0 "general_operand" "+d*am")
4589 (label_ref (match_operand 1 "" ""))
4592 (plus:SI (match_dup 0)
4594 "find_reg_note (insn, REG_NONNEG, 0)"
4599 The other two special looping patterns, @samp{doloop_begin} and
4600 @samp{doloop_end}, are emitted by the loop optimizer for certain
4601 well-behaved loops with a finite number of loop iterations using
4602 information collected during strength reduction.
4604 The @samp{doloop_end} pattern describes the actual looping instruction
4605 (or the implicit looping operation) and the @samp{doloop_begin} pattern
4606 is an optional companion pattern that can be used for initialization
4607 needed for some low-overhead looping instructions.
4609 Note that some machines require the actual looping instruction to be
4610 emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
4611 the true RTL for a looping instruction at the top of the loop can cause
4612 problems with flow analysis. So instead, a dummy @code{doloop} insn is
4613 emitted at the end of the loop. The machine dependent reorg pass checks
4614 for the presence of this @code{doloop} insn and then searches back to
4615 the top of the loop, where it inserts the true looping insn (provided
4616 there are no instructions in the loop which would cause problems). Any
4617 additional labels can be emitted at this point. In addition, if the
4618 desired special iteration counter register was not allocated, this
4619 machine dependent reorg pass could emit a traditional compare and jump
4622 The essential difference between the
4623 @samp{decrement_and_branch_until_zero} and the @samp{doloop_end}
4624 patterns is that the loop optimizer allocates an additional pseudo
4625 register for the latter as an iteration counter. This pseudo register
4626 cannot be used within the loop (i.e., general induction variables cannot
4627 be derived from it), however, in many cases the loop induction variable
4628 may become redundant and removed by the flow pass.
4633 @node Insn Canonicalizations
4634 @section Canonicalization of Instructions
4635 @cindex canonicalization of instructions
4636 @cindex insn canonicalization
4638 There are often cases where multiple RTL expressions could represent an
4639 operation performed by a single machine instruction. This situation is
4640 most commonly encountered with logical, branch, and multiply-accumulate
4641 instructions. In such cases, the compiler attempts to convert these
4642 multiple RTL expressions into a single canonical form to reduce the
4643 number of insn patterns required.
4645 In addition to algebraic simplifications, following canonicalizations
4650 For commutative and comparison operators, a constant is always made the
4651 second operand. If a machine only supports a constant as the second
4652 operand, only patterns that match a constant in the second operand need
4656 For associative operators, a sequence of operators will always chain
4657 to the left; for instance, only the left operand of an integer @code{plus}
4658 can itself be a @code{plus}. @code{and}, @code{ior}, @code{xor},
4659 @code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and
4660 @code{umax} are associative when applied to integers, and sometimes to
4664 @cindex @code{neg}, canonicalization of
4665 @cindex @code{not}, canonicalization of
4666 @cindex @code{mult}, canonicalization of
4667 @cindex @code{plus}, canonicalization of
4668 @cindex @code{minus}, canonicalization of
4669 For these operators, if only one operand is a @code{neg}, @code{not},
4670 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
4674 In combinations of @code{neg}, @code{mult}, @code{plus}, and
4675 @code{minus}, the @code{neg} operations (if any) will be moved inside
4676 the operations as far as possible. For instance,
4677 @code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but
4678 @code{(plus (mult (neg A) B) C)} is canonicalized as
4679 @code{(minus A (mult B C))}.
4681 @cindex @code{compare}, canonicalization of
4683 For the @code{compare} operator, a constant is always the second operand
4684 on machines where @code{cc0} is used (@pxref{Jump Patterns}). On other
4685 machines, there are rare cases where the compiler might want to construct
4686 a @code{compare} with a constant as the first operand. However, these
4687 cases are not common enough for it to be worthwhile to provide a pattern
4688 matching a constant as the first operand unless the machine actually has
4689 such an instruction.
4691 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
4692 @code{minus} is made the first operand under the same conditions as
4696 @code{(minus @var{x} (const_int @var{n}))} is converted to
4697 @code{(plus @var{x} (const_int @var{-n}))}.
4700 Within address computations (i.e., inside @code{mem}), a left shift is
4701 converted into the appropriate multiplication by a power of two.
4703 @cindex @code{ior}, canonicalization of
4704 @cindex @code{and}, canonicalization of
4705 @cindex De Morgan's law
4707 De Morgan's Law is used to move bitwise negation inside a bitwise
4708 logical-and or logical-or operation. If this results in only one
4709 operand being a @code{not} expression, it will be the first one.
4711 A machine that has an instruction that performs a bitwise logical-and of one
4712 operand with the bitwise negation of the other should specify the pattern
4713 for that instruction as
4717 [(set (match_operand:@var{m} 0 @dots{})
4718 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
4719 (match_operand:@var{m} 2 @dots{})))]
4725 Similarly, a pattern for a ``NAND'' instruction should be written
4729 [(set (match_operand:@var{m} 0 @dots{})
4730 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
4731 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
4736 In both cases, it is not necessary to include patterns for the many
4737 logically equivalent RTL expressions.
4739 @cindex @code{xor}, canonicalization of
4741 The only possible RTL expressions involving both bitwise exclusive-or
4742 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
4743 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
4746 The sum of three items, one of which is a constant, will only appear in
4750 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
4754 On machines that do not use @code{cc0},
4755 @code{(compare @var{x} (const_int 0))} will be converted to
4758 @cindex @code{zero_extract}, canonicalization of
4759 @cindex @code{sign_extract}, canonicalization of
4761 Equality comparisons of a group of bits (usually a single bit) with zero
4762 will be written using @code{zero_extract} rather than the equivalent
4763 @code{and} or @code{sign_extract} operations.
4769 @node Expander Definitions
4770 @section Defining RTL Sequences for Code Generation
4771 @cindex expander definitions
4772 @cindex code generation RTL sequences
4773 @cindex defining RTL sequences for code generation
4775 On some target machines, some standard pattern names for RTL generation
4776 cannot be handled with single insn, but a sequence of RTL insns can
4777 represent them. For these target machines, you can write a
4778 @code{define_expand} to specify how to generate the sequence of RTL@.
4780 @findex define_expand
4781 A @code{define_expand} is an RTL expression that looks almost like a
4782 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
4783 only for RTL generation and it can produce more than one RTL insn.
4785 A @code{define_expand} RTX has four operands:
4789 The name. Each @code{define_expand} must have a name, since the only
4790 use for it is to refer to it by name.
4793 The RTL template. This is a vector of RTL expressions representing
4794 a sequence of separate instructions. Unlike @code{define_insn}, there
4795 is no implicit surrounding @code{PARALLEL}.
4798 The condition, a string containing a C expression. This expression is
4799 used to express how the availability of this pattern depends on
4800 subclasses of target machine, selected by command-line options when GCC
4801 is run. This is just like the condition of a @code{define_insn} that
4802 has a standard name. Therefore, the condition (if present) may not
4803 depend on the data in the insn being matched, but only the
4804 target-machine-type flags. The compiler needs to test these conditions
4805 during initialization in order to learn exactly which named instructions
4806 are available in a particular run.
4809 The preparation statements, a string containing zero or more C
4810 statements which are to be executed before RTL code is generated from
4813 Usually these statements prepare temporary registers for use as
4814 internal operands in the RTL template, but they can also generate RTL
4815 insns directly by calling routines such as @code{emit_insn}, etc.
4816 Any such insns precede the ones that come from the RTL template.
4819 Every RTL insn emitted by a @code{define_expand} must match some
4820 @code{define_insn} in the machine description. Otherwise, the compiler
4821 will crash when trying to generate code for the insn or trying to optimize
4824 The RTL template, in addition to controlling generation of RTL insns,
4825 also describes the operands that need to be specified when this pattern
4826 is used. In particular, it gives a predicate for each operand.
4828 A true operand, which needs to be specified in order to generate RTL from
4829 the pattern, should be described with a @code{match_operand} in its first
4830 occurrence in the RTL template. This enters information on the operand's
4831 predicate into the tables that record such things. GCC uses the
4832 information to preload the operand into a register if that is required for
4833 valid RTL code. If the operand is referred to more than once, subsequent
4834 references should use @code{match_dup}.
4836 The RTL template may also refer to internal ``operands'' which are
4837 temporary registers or labels used only within the sequence made by the
4838 @code{define_expand}. Internal operands are substituted into the RTL
4839 template with @code{match_dup}, never with @code{match_operand}. The
4840 values of the internal operands are not passed in as arguments by the
4841 compiler when it requests use of this pattern. Instead, they are computed
4842 within the pattern, in the preparation statements. These statements
4843 compute the values and store them into the appropriate elements of
4844 @code{operands} so that @code{match_dup} can find them.
4846 There are two special macros defined for use in the preparation statements:
4847 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
4854 Use the @code{DONE} macro to end RTL generation for the pattern. The
4855 only RTL insns resulting from the pattern on this occasion will be
4856 those already emitted by explicit calls to @code{emit_insn} within the
4857 preparation statements; the RTL template will not be generated.
4861 Make the pattern fail on this occasion. When a pattern fails, it means
4862 that the pattern was not truly available. The calling routines in the
4863 compiler will try other strategies for code generation using other patterns.
4865 Failure is currently supported only for binary (addition, multiplication,
4866 shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv})
4870 If the preparation falls through (invokes neither @code{DONE} nor
4871 @code{FAIL}), then the @code{define_expand} acts like a
4872 @code{define_insn} in that the RTL template is used to generate the
4875 The RTL template is not used for matching, only for generating the
4876 initial insn list. If the preparation statement always invokes
4877 @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple
4878 list of operands, such as this example:
4882 (define_expand "addsi3"
4883 [(match_operand:SI 0 "register_operand" "")
4884 (match_operand:SI 1 "register_operand" "")
4885 (match_operand:SI 2 "register_operand" "")]
4891 handle_add (operands[0], operands[1], operands[2]);
4897 Here is an example, the definition of left-shift for the SPUR chip:
4901 (define_expand "ashlsi3"
4902 [(set (match_operand:SI 0 "register_operand" "")
4906 (match_operand:SI 1 "register_operand" "")
4907 (match_operand:SI 2 "nonmemory_operand" "")))]
4916 if (GET_CODE (operands[2]) != CONST_INT
4917 || (unsigned) INTVAL (operands[2]) > 3)
4924 This example uses @code{define_expand} so that it can generate an RTL insn
4925 for shifting when the shift-count is in the supported range of 0 to 3 but
4926 fail in other cases where machine insns aren't available. When it fails,
4927 the compiler tries another strategy using different patterns (such as, a
4930 If the compiler were able to handle nontrivial condition-strings in
4931 patterns with names, then it would be possible to use a
4932 @code{define_insn} in that case. Here is another case (zero-extension
4933 on the 68000) which makes more use of the power of @code{define_expand}:
4936 (define_expand "zero_extendhisi2"
4937 [(set (match_operand:SI 0 "general_operand" "")
4939 (set (strict_low_part
4943 (match_operand:HI 1 "general_operand" ""))]
4945 "operands[1] = make_safe_from (operands[1], operands[0]);")
4949 @findex make_safe_from
4950 Here two RTL insns are generated, one to clear the entire output operand
4951 and the other to copy the input operand into its low half. This sequence
4952 is incorrect if the input operand refers to [the old value of] the output
4953 operand, so the preparation statement makes sure this isn't so. The
4954 function @code{make_safe_from} copies the @code{operands[1]} into a
4955 temporary register if it refers to @code{operands[0]}. It does this
4956 by emitting another RTL insn.
4958 Finally, a third example shows the use of an internal operand.
4959 Zero-extension on the SPUR chip is done by @code{and}-ing the result
4960 against a halfword mask. But this mask cannot be represented by a
4961 @code{const_int} because the constant value is too large to be legitimate
4962 on this machine. So it must be copied into a register with
4963 @code{force_reg} and then the register used in the @code{and}.
4966 (define_expand "zero_extendhisi2"
4967 [(set (match_operand:SI 0 "register_operand" "")
4969 (match_operand:HI 1 "register_operand" "")
4974 = force_reg (SImode, GEN_INT (65535)); ")
4977 @emph{Note:} If the @code{define_expand} is used to serve a
4978 standard binary or unary arithmetic operation or a bit-field operation,
4979 then the last insn it generates must not be a @code{code_label},
4980 @code{barrier} or @code{note}. It must be an @code{insn},
4981 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
4982 at the end, emit an insn to copy the result of the operation into
4983 itself. Such an insn will generate no code, but it can avoid problems
4988 @node Insn Splitting
4989 @section Defining How to Split Instructions
4990 @cindex insn splitting
4991 @cindex instruction splitting
4992 @cindex splitting instructions
4994 There are two cases where you should specify how to split a pattern
4995 into multiple insns. On machines that have instructions requiring
4996 delay slots (@pxref{Delay Slots}) or that have instructions whose
4997 output is not available for multiple cycles (@pxref{Processor pipeline
4998 description}), the compiler phases that optimize these cases need to
4999 be able to move insns into one-instruction delay slots. However, some
5000 insns may generate more than one machine instruction. These insns
5001 cannot be placed into a delay slot.
5003 Often you can rewrite the single insn as a list of individual insns,
5004 each corresponding to one machine instruction. The disadvantage of
5005 doing so is that it will cause the compilation to be slower and require
5006 more space. If the resulting insns are too complex, it may also
5007 suppress some optimizations. The compiler splits the insn if there is a
5008 reason to believe that it might improve instruction or delay slot
5011 The insn combiner phase also splits putative insns. If three insns are
5012 merged into one insn with a complex expression that cannot be matched by
5013 some @code{define_insn} pattern, the combiner phase attempts to split
5014 the complex pattern into two insns that are recognized. Usually it can
5015 break the complex pattern into two patterns by splitting out some
5016 subexpression. However, in some other cases, such as performing an
5017 addition of a large constant in two insns on a RISC machine, the way to
5018 split the addition into two insns is machine-dependent.
5020 @findex define_split
5021 The @code{define_split} definition tells the compiler how to split a
5022 complex insn into several simpler insns. It looks like this:
5026 [@var{insn-pattern}]
5028 [@var{new-insn-pattern-1}
5029 @var{new-insn-pattern-2}
5031 "@var{preparation-statements}")
5034 @var{insn-pattern} is a pattern that needs to be split and
5035 @var{condition} is the final condition to be tested, as in a
5036 @code{define_insn}. When an insn matching @var{insn-pattern} and
5037 satisfying @var{condition} is found, it is replaced in the insn list
5038 with the insns given by @var{new-insn-pattern-1},
5039 @var{new-insn-pattern-2}, etc.
5041 The @var{preparation-statements} are similar to those statements that
5042 are specified for @code{define_expand} (@pxref{Expander Definitions})
5043 and are executed before the new RTL is generated to prepare for the
5044 generated code or emit some insns whose pattern is not fixed. Unlike
5045 those in @code{define_expand}, however, these statements must not
5046 generate any new pseudo-registers. Once reload has completed, they also
5047 must not allocate any space in the stack frame.
5049 Patterns are matched against @var{insn-pattern} in two different
5050 circumstances. If an insn needs to be split for delay slot scheduling
5051 or insn scheduling, the insn is already known to be valid, which means
5052 that it must have been matched by some @code{define_insn} and, if
5053 @code{reload_completed} is nonzero, is known to satisfy the constraints
5054 of that @code{define_insn}. In that case, the new insn patterns must
5055 also be insns that are matched by some @code{define_insn} and, if
5056 @code{reload_completed} is nonzero, must also satisfy the constraints
5057 of those definitions.
5059 As an example of this usage of @code{define_split}, consider the following
5060 example from @file{a29k.md}, which splits a @code{sign_extend} from
5061 @code{HImode} to @code{SImode} into a pair of shift insns:
5065 [(set (match_operand:SI 0 "gen_reg_operand" "")
5066 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
5069 (ashift:SI (match_dup 1)
5072 (ashiftrt:SI (match_dup 0)
5075 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
5078 When the combiner phase tries to split an insn pattern, it is always the
5079 case that the pattern is @emph{not} matched by any @code{define_insn}.
5080 The combiner pass first tries to split a single @code{set} expression
5081 and then the same @code{set} expression inside a @code{parallel}, but
5082 followed by a @code{clobber} of a pseudo-reg to use as a scratch
5083 register. In these cases, the combiner expects exactly two new insn
5084 patterns to be generated. It will verify that these patterns match some
5085 @code{define_insn} definitions, so you need not do this test in the
5086 @code{define_split} (of course, there is no point in writing a
5087 @code{define_split} that will never produce insns that match).
5089 Here is an example of this use of @code{define_split}, taken from
5094 [(set (match_operand:SI 0 "gen_reg_operand" "")
5095 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
5096 (match_operand:SI 2 "non_add_cint_operand" "")))]
5098 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
5099 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
5102 int low = INTVAL (operands[2]) & 0xffff;
5103 int high = (unsigned) INTVAL (operands[2]) >> 16;
5106 high++, low |= 0xffff0000;
5108 operands[3] = GEN_INT (high << 16);
5109 operands[4] = GEN_INT (low);
5113 Here the predicate @code{non_add_cint_operand} matches any
5114 @code{const_int} that is @emph{not} a valid operand of a single add
5115 insn. The add with the smaller displacement is written so that it
5116 can be substituted into the address of a subsequent operation.
5118 An example that uses a scratch register, from the same file, generates
5119 an equality comparison of a register and a large constant:
5123 [(set (match_operand:CC 0 "cc_reg_operand" "")
5124 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
5125 (match_operand:SI 2 "non_short_cint_operand" "")))
5126 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
5127 "find_single_use (operands[0], insn, 0)
5128 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
5129 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
5130 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
5131 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
5134 /* @r{Get the constant we are comparing against, C, and see what it
5135 looks like sign-extended to 16 bits. Then see what constant
5136 could be XOR'ed with C to get the sign-extended value.} */
5138 int c = INTVAL (operands[2]);
5139 int sextc = (c << 16) >> 16;
5140 int xorv = c ^ sextc;
5142 operands[4] = GEN_INT (xorv);
5143 operands[5] = GEN_INT (sextc);
5147 To avoid confusion, don't write a single @code{define_split} that
5148 accepts some insns that match some @code{define_insn} as well as some
5149 insns that don't. Instead, write two separate @code{define_split}
5150 definitions, one for the insns that are valid and one for the insns that
5153 The splitter is allowed to split jump instructions into sequence of
5154 jumps or create new jumps in while splitting non-jump instructions. As
5155 the central flowgraph and branch prediction information needs to be updated,
5156 several restriction apply.
5158 Splitting of jump instruction into sequence that over by another jump
5159 instruction is always valid, as compiler expect identical behavior of new
5160 jump. When new sequence contains multiple jump instructions or new labels,
5161 more assistance is needed. Splitter is required to create only unconditional
5162 jumps, or simple conditional jump instructions. Additionally it must attach a
5163 @code{REG_BR_PROB} note to each conditional jump. A global variable
5164 @code{split_branch_probability} holds the probability of the original branch in case
5165 it was an simple conditional jump, @minus{}1 otherwise. To simplify
5166 recomputing of edge frequencies, the new sequence is required to have only
5167 forward jumps to the newly created labels.
5169 @findex define_insn_and_split
5170 For the common case where the pattern of a define_split exactly matches the
5171 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
5175 (define_insn_and_split
5176 [@var{insn-pattern}]
5178 "@var{output-template}"
5179 "@var{split-condition}"
5180 [@var{new-insn-pattern-1}
5181 @var{new-insn-pattern-2}
5183 "@var{preparation-statements}"
5184 [@var{insn-attributes}])
5188 @var{insn-pattern}, @var{condition}, @var{output-template}, and
5189 @var{insn-attributes} are used as in @code{define_insn}. The
5190 @var{new-insn-pattern} vector and the @var{preparation-statements} are used as
5191 in a @code{define_split}. The @var{split-condition} is also used as in
5192 @code{define_split}, with the additional behavior that if the condition starts
5193 with @samp{&&}, the condition used for the split will be the constructed as a
5194 logical ``and'' of the split condition with the insn condition. For example,
5198 (define_insn_and_split "zero_extendhisi2_and"
5199 [(set (match_operand:SI 0 "register_operand" "=r")
5200 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
5201 (clobber (reg:CC 17))]
5202 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
5204 "&& reload_completed"
5205 [(parallel [(set (match_dup 0)
5206 (and:SI (match_dup 0) (const_int 65535)))
5207 (clobber (reg:CC 17))])]
5209 [(set_attr "type" "alu1")])
5213 In this case, the actual split condition will be
5214 @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
5216 The @code{define_insn_and_split} construction provides exactly the same
5217 functionality as two separate @code{define_insn} and @code{define_split}
5218 patterns. It exists for compactness, and as a maintenance tool to prevent
5219 having to ensure the two patterns' templates match.
5223 @node Including Patterns
5224 @section Including Patterns in Machine Descriptions.
5225 @cindex insn includes
5228 The @code{include} pattern tells the compiler tools where to
5229 look for patterns that are in files other than in the file
5230 @file{.md}. This is used only at build time and there is no preprocessing allowed.
5244 (include "filestuff")
5248 Where @var{pathname} is a string that specifies the location of the file,
5249 specifies the include file to be in @file{gcc/config/target/filestuff}. The
5250 directory @file{gcc/config/target} is regarded as the default directory.
5253 Machine descriptions may be split up into smaller more manageable subsections
5254 and placed into subdirectories.
5260 (include "BOGUS/filestuff")
5264 the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}.
5266 Specifying an absolute path for the include file such as;
5269 (include "/u2/BOGUS/filestuff")
5272 is permitted but is not encouraged.
5274 @subsection RTL Generation Tool Options for Directory Search
5275 @cindex directory options .md
5276 @cindex options, directory search
5277 @cindex search options
5279 The @option{-I@var{dir}} option specifies directories to search for machine descriptions.
5284 genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md
5289 Add the directory @var{dir} to the head of the list of directories to be
5290 searched for header files. This can be used to override a system machine definition
5291 file, substituting your own version, since these directories are
5292 searched before the default machine description file directories. If you use more than
5293 one @option{-I} option, the directories are scanned in left-to-right
5294 order; the standard default directory come after.
5299 @node Peephole Definitions
5300 @section Machine-Specific Peephole Optimizers
5301 @cindex peephole optimizer definitions
5302 @cindex defining peephole optimizers
5304 In addition to instruction patterns the @file{md} file may contain
5305 definitions of machine-specific peephole optimizations.
5307 The combiner does not notice certain peephole optimizations when the data
5308 flow in the program does not suggest that it should try them. For example,
5309 sometimes two consecutive insns related in purpose can be combined even
5310 though the second one does not appear to use a register computed in the
5311 first one. A machine-specific peephole optimizer can detect such
5314 There are two forms of peephole definitions that may be used. The
5315 original @code{define_peephole} is run at assembly output time to
5316 match insns and substitute assembly text. Use of @code{define_peephole}
5319 A newer @code{define_peephole2} matches insns and substitutes new
5320 insns. The @code{peephole2} pass is run after register allocation
5321 but before scheduling, which may result in much better code for
5322 targets that do scheduling.
5325 * define_peephole:: RTL to Text Peephole Optimizers
5326 * define_peephole2:: RTL to RTL Peephole Optimizers
5331 @node define_peephole
5332 @subsection RTL to Text Peephole Optimizers
5333 @findex define_peephole
5336 A definition looks like this:
5340 [@var{insn-pattern-1}
5341 @var{insn-pattern-2}
5345 "@var{optional-insn-attributes}")
5349 The last string operand may be omitted if you are not using any
5350 machine-specific information in this machine description. If present,
5351 it must obey the same rules as in a @code{define_insn}.
5353 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
5354 consecutive insns. The optimization applies to a sequence of insns when
5355 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
5356 the next, and so on.
5358 Each of the insns matched by a peephole must also match a
5359 @code{define_insn}. Peepholes are checked only at the last stage just
5360 before code generation, and only optionally. Therefore, any insn which
5361 would match a peephole but no @code{define_insn} will cause a crash in code
5362 generation in an unoptimized compilation, or at various optimization
5365 The operands of the insns are matched with @code{match_operands},
5366 @code{match_operator}, and @code{match_dup}, as usual. What is not
5367 usual is that the operand numbers apply to all the insn patterns in the
5368 definition. So, you can check for identical operands in two insns by
5369 using @code{match_operand} in one insn and @code{match_dup} in the
5372 The operand constraints used in @code{match_operand} patterns do not have
5373 any direct effect on the applicability of the peephole, but they will
5374 be validated afterward, so make sure your constraints are general enough
5375 to apply whenever the peephole matches. If the peephole matches
5376 but the constraints are not satisfied, the compiler will crash.
5378 It is safe to omit constraints in all the operands of the peephole; or
5379 you can write constraints which serve as a double-check on the criteria
5382 Once a sequence of insns matches the patterns, the @var{condition} is
5383 checked. This is a C expression which makes the final decision whether to
5384 perform the optimization (we do so if the expression is nonzero). If
5385 @var{condition} is omitted (in other words, the string is empty) then the
5386 optimization is applied to every sequence of insns that matches the
5389 The defined peephole optimizations are applied after register allocation
5390 is complete. Therefore, the peephole definition can check which
5391 operands have ended up in which kinds of registers, just by looking at
5394 @findex prev_active_insn
5395 The way to refer to the operands in @var{condition} is to write
5396 @code{operands[@var{i}]} for operand number @var{i} (as matched by
5397 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
5398 to refer to the last of the insns being matched; use
5399 @code{prev_active_insn} to find the preceding insns.
5401 @findex dead_or_set_p
5402 When optimizing computations with intermediate results, you can use
5403 @var{condition} to match only when the intermediate results are not used
5404 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
5405 @var{op})}, where @var{insn} is the insn in which you expect the value
5406 to be used for the last time (from the value of @code{insn}, together
5407 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
5408 value (from @code{operands[@var{i}]}).
5410 Applying the optimization means replacing the sequence of insns with one
5411 new insn. The @var{template} controls ultimate output of assembler code
5412 for this combined insn. It works exactly like the template of a
5413 @code{define_insn}. Operand numbers in this template are the same ones
5414 used in matching the original sequence of insns.
5416 The result of a defined peephole optimizer does not need to match any of
5417 the insn patterns in the machine description; it does not even have an
5418 opportunity to match them. The peephole optimizer definition itself serves
5419 as the insn pattern to control how the insn is output.
5421 Defined peephole optimizers are run as assembler code is being output,
5422 so the insns they produce are never combined or rearranged in any way.
5424 Here is an example, taken from the 68000 machine description:
5428 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
5429 (set (match_operand:DF 0 "register_operand" "=f")
5430 (match_operand:DF 1 "register_operand" "ad"))]
5431 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
5434 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
5436 output_asm_insn ("move.l %1,(sp)", xoperands);
5437 output_asm_insn ("move.l %1,-(sp)", operands);
5438 return "fmove.d (sp)+,%0";
5440 output_asm_insn ("movel %1,sp@@", xoperands);
5441 output_asm_insn ("movel %1,sp@@-", operands);
5442 return "fmoved sp@@+,%0";
5448 The effect of this optimization is to change
5474 If a peephole matches a sequence including one or more jump insns, you must
5475 take account of the flags such as @code{CC_REVERSED} which specify that the
5476 condition codes are represented in an unusual manner. The compiler
5477 automatically alters any ordinary conditional jumps which occur in such
5478 situations, but the compiler cannot alter jumps which have been replaced by
5479 peephole optimizations. So it is up to you to alter the assembler code
5480 that the peephole produces. Supply C code to write the assembler output,
5481 and in this C code check the condition code status flags and change the
5482 assembler code as appropriate.
5485 @var{insn-pattern-1} and so on look @emph{almost} like the second
5486 operand of @code{define_insn}. There is one important difference: the
5487 second operand of @code{define_insn} consists of one or more RTX's
5488 enclosed in square brackets. Usually, there is only one: then the same
5489 action can be written as an element of a @code{define_peephole}. But
5490 when there are multiple actions in a @code{define_insn}, they are
5491 implicitly enclosed in a @code{parallel}. Then you must explicitly
5492 write the @code{parallel}, and the square brackets within it, in the
5493 @code{define_peephole}. Thus, if an insn pattern looks like this,
5496 (define_insn "divmodsi4"
5497 [(set (match_operand:SI 0 "general_operand" "=d")
5498 (div:SI (match_operand:SI 1 "general_operand" "0")
5499 (match_operand:SI 2 "general_operand" "dmsK")))
5500 (set (match_operand:SI 3 "general_operand" "=d")
5501 (mod:SI (match_dup 1) (match_dup 2)))]
5503 "divsl%.l %2,%3:%0")
5507 then the way to mention this insn in a peephole is as follows:
5513 [(set (match_operand:SI 0 "general_operand" "=d")
5514 (div:SI (match_operand:SI 1 "general_operand" "0")
5515 (match_operand:SI 2 "general_operand" "dmsK")))
5516 (set (match_operand:SI 3 "general_operand" "=d")
5517 (mod:SI (match_dup 1) (match_dup 2)))])
5524 @node define_peephole2
5525 @subsection RTL to RTL Peephole Optimizers
5526 @findex define_peephole2
5528 The @code{define_peephole2} definition tells the compiler how to
5529 substitute one sequence of instructions for another sequence,
5530 what additional scratch registers may be needed and what their
5535 [@var{insn-pattern-1}
5536 @var{insn-pattern-2}
5539 [@var{new-insn-pattern-1}
5540 @var{new-insn-pattern-2}
5542 "@var{preparation-statements}")
5545 The definition is almost identical to @code{define_split}
5546 (@pxref{Insn Splitting}) except that the pattern to match is not a
5547 single instruction, but a sequence of instructions.
5549 It is possible to request additional scratch registers for use in the
5550 output template. If appropriate registers are not free, the pattern
5551 will simply not match.
5553 @findex match_scratch
5555 Scratch registers are requested with a @code{match_scratch} pattern at
5556 the top level of the input pattern. The allocated register (initially) will
5557 be dead at the point requested within the original sequence. If the scratch
5558 is used at more than a single point, a @code{match_dup} pattern at the
5559 top level of the input pattern marks the last position in the input sequence
5560 at which the register must be available.
5562 Here is an example from the IA-32 machine description:
5566 [(match_scratch:SI 2 "r")
5567 (parallel [(set (match_operand:SI 0 "register_operand" "")
5568 (match_operator:SI 3 "arith_or_logical_operator"
5570 (match_operand:SI 1 "memory_operand" "")]))
5571 (clobber (reg:CC 17))])]
5572 "! optimize_size && ! TARGET_READ_MODIFY"
5573 [(set (match_dup 2) (match_dup 1))
5574 (parallel [(set (match_dup 0)
5575 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
5576 (clobber (reg:CC 17))])]
5581 This pattern tries to split a load from its use in the hopes that we'll be
5582 able to schedule around the memory load latency. It allocates a single
5583 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
5584 to be live only at the point just before the arithmetic.
5586 A real example requiring extended scratch lifetimes is harder to come by,
5587 so here's a silly made-up example:
5591 [(match_scratch:SI 4 "r")
5592 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
5593 (set (match_operand:SI 2 "" "") (match_dup 1))
5595 (set (match_operand:SI 3 "" "") (match_dup 1))]
5596 "/* @r{determine 1 does not overlap 0 and 2} */"
5597 [(set (match_dup 4) (match_dup 1))
5598 (set (match_dup 0) (match_dup 4))
5599 (set (match_dup 2) (match_dup 4))]
5600 (set (match_dup 3) (match_dup 4))]
5605 If we had not added the @code{(match_dup 4)} in the middle of the input
5606 sequence, it might have been the case that the register we chose at the
5607 beginning of the sequence is killed by the first or second @code{set}.
5611 @node Insn Attributes
5612 @section Instruction Attributes
5613 @cindex insn attributes
5614 @cindex instruction attributes
5616 In addition to describing the instruction supported by the target machine,
5617 the @file{md} file also defines a group of @dfn{attributes} and a set of
5618 values for each. Every generated insn is assigned a value for each attribute.
5619 One possible attribute would be the effect that the insn has on the machine's
5620 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
5621 to track the condition codes.
5624 * Defining Attributes:: Specifying attributes and their values.
5625 * Expressions:: Valid expressions for attribute values.
5626 * Tagging Insns:: Assigning attribute values to insns.
5627 * Attr Example:: An example of assigning attributes.
5628 * Insn Lengths:: Computing the length of insns.
5629 * Constant Attributes:: Defining attributes that are constant.
5630 * Delay Slots:: Defining delay slots required for a machine.
5631 * Processor pipeline description:: Specifying information for insn scheduling.
5636 @node Defining Attributes
5637 @subsection Defining Attributes and their Values
5638 @cindex defining attributes and their values
5639 @cindex attributes, defining
5642 The @code{define_attr} expression is used to define each attribute required
5643 by the target machine. It looks like:
5646 (define_attr @var{name} @var{list-of-values} @var{default})
5649 @var{name} is a string specifying the name of the attribute being defined.
5651 @var{list-of-values} is either a string that specifies a comma-separated
5652 list of values that can be assigned to the attribute, or a null string to
5653 indicate that the attribute takes numeric values.
5655 @var{default} is an attribute expression that gives the value of this
5656 attribute for insns that match patterns whose definition does not include
5657 an explicit value for this attribute. @xref{Attr Example}, for more
5658 information on the handling of defaults. @xref{Constant Attributes},
5659 for information on attributes that do not depend on any particular insn.
5662 For each defined attribute, a number of definitions are written to the
5663 @file{insn-attr.h} file. For cases where an explicit set of values is
5664 specified for an attribute, the following are defined:
5668 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
5671 An enumerated class is defined for @samp{attr_@var{name}} with
5672 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
5673 the attribute name and value are first converted to uppercase.
5676 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
5677 returns the attribute value for that insn.
5680 For example, if the following is present in the @file{md} file:
5683 (define_attr "type" "branch,fp,load,store,arith" @dots{})
5687 the following lines will be written to the file @file{insn-attr.h}.
5690 #define HAVE_ATTR_type
5691 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
5692 TYPE_STORE, TYPE_ARITH@};
5693 extern enum attr_type get_attr_type ();
5696 If the attribute takes numeric values, no @code{enum} type will be
5697 defined and the function to obtain the attribute's value will return
5703 @subsection Attribute Expressions
5704 @cindex attribute expressions
5706 RTL expressions used to define attributes use the codes described above
5707 plus a few specific to attribute definitions, to be discussed below.
5708 Attribute value expressions must have one of the following forms:
5711 @cindex @code{const_int} and attributes
5712 @item (const_int @var{i})
5713 The integer @var{i} specifies the value of a numeric attribute. @var{i}
5714 must be non-negative.
5716 The value of a numeric attribute can be specified either with a
5717 @code{const_int}, or as an integer represented as a string in
5718 @code{const_string}, @code{eq_attr} (see below), @code{attr},
5719 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
5720 overrides on specific instructions (@pxref{Tagging Insns}).
5722 @cindex @code{const_string} and attributes
5723 @item (const_string @var{value})
5724 The string @var{value} specifies a constant attribute value.
5725 If @var{value} is specified as @samp{"*"}, it means that the default value of
5726 the attribute is to be used for the insn containing this expression.
5727 @samp{"*"} obviously cannot be used in the @var{default} expression
5728 of a @code{define_attr}.
5730 If the attribute whose value is being specified is numeric, @var{value}
5731 must be a string containing a non-negative integer (normally
5732 @code{const_int} would be used in this case). Otherwise, it must
5733 contain one of the valid values for the attribute.
5735 @cindex @code{if_then_else} and attributes
5736 @item (if_then_else @var{test} @var{true-value} @var{false-value})
5737 @var{test} specifies an attribute test, whose format is defined below.
5738 The value of this expression is @var{true-value} if @var{test} is true,
5739 otherwise it is @var{false-value}.
5741 @cindex @code{cond} and attributes
5742 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
5743 The first operand of this expression is a vector containing an even
5744 number of expressions and consisting of pairs of @var{test} and @var{value}
5745 expressions. The value of the @code{cond} expression is that of the
5746 @var{value} corresponding to the first true @var{test} expression. If
5747 none of the @var{test} expressions are true, the value of the @code{cond}
5748 expression is that of the @var{default} expression.
5751 @var{test} expressions can have one of the following forms:
5754 @cindex @code{const_int} and attribute tests
5755 @item (const_int @var{i})
5756 This test is true if @var{i} is nonzero and false otherwise.
5758 @cindex @code{not} and attributes
5759 @cindex @code{ior} and attributes
5760 @cindex @code{and} and attributes
5761 @item (not @var{test})
5762 @itemx (ior @var{test1} @var{test2})
5763 @itemx (and @var{test1} @var{test2})
5764 These tests are true if the indicated logical function is true.
5766 @cindex @code{match_operand} and attributes
5767 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
5768 This test is true if operand @var{n} of the insn whose attribute value
5769 is being determined has mode @var{m} (this part of the test is ignored
5770 if @var{m} is @code{VOIDmode}) and the function specified by the string
5771 @var{pred} returns a nonzero value when passed operand @var{n} and mode
5772 @var{m} (this part of the test is ignored if @var{pred} is the null
5775 The @var{constraints} operand is ignored and should be the null string.
5777 @cindex @code{le} and attributes
5778 @cindex @code{leu} and attributes
5779 @cindex @code{lt} and attributes
5780 @cindex @code{gt} and attributes
5781 @cindex @code{gtu} and attributes
5782 @cindex @code{ge} and attributes
5783 @cindex @code{geu} and attributes
5784 @cindex @code{ne} and attributes
5785 @cindex @code{eq} and attributes
5786 @cindex @code{plus} and attributes
5787 @cindex @code{minus} and attributes
5788 @cindex @code{mult} and attributes
5789 @cindex @code{div} and attributes
5790 @cindex @code{mod} and attributes
5791 @cindex @code{abs} and attributes
5792 @cindex @code{neg} and attributes
5793 @cindex @code{ashift} and attributes
5794 @cindex @code{lshiftrt} and attributes
5795 @cindex @code{ashiftrt} and attributes
5796 @item (le @var{arith1} @var{arith2})
5797 @itemx (leu @var{arith1} @var{arith2})
5798 @itemx (lt @var{arith1} @var{arith2})
5799 @itemx (ltu @var{arith1} @var{arith2})
5800 @itemx (gt @var{arith1} @var{arith2})
5801 @itemx (gtu @var{arith1} @var{arith2})
5802 @itemx (ge @var{arith1} @var{arith2})
5803 @itemx (geu @var{arith1} @var{arith2})
5804 @itemx (ne @var{arith1} @var{arith2})
5805 @itemx (eq @var{arith1} @var{arith2})
5806 These tests are true if the indicated comparison of the two arithmetic
5807 expressions is true. Arithmetic expressions are formed with
5808 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
5809 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
5810 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
5813 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
5814 Lengths},for additional forms). @code{symbol_ref} is a string
5815 denoting a C expression that yields an @code{int} when evaluated by the
5816 @samp{get_attr_@dots{}} routine. It should normally be a global
5820 @item (eq_attr @var{name} @var{value})
5821 @var{name} is a string specifying the name of an attribute.
5823 @var{value} is a string that is either a valid value for attribute
5824 @var{name}, a comma-separated list of values, or @samp{!} followed by a
5825 value or list. If @var{value} does not begin with a @samp{!}, this
5826 test is true if the value of the @var{name} attribute of the current
5827 insn is in the list specified by @var{value}. If @var{value} begins
5828 with a @samp{!}, this test is true if the attribute's value is
5829 @emph{not} in the specified list.
5834 (eq_attr "type" "load,store")
5841 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
5844 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
5845 value of the compiler variable @code{which_alternative}
5846 (@pxref{Output Statement}) and the values must be small integers. For
5850 (eq_attr "alternative" "2,3")
5857 (ior (eq (symbol_ref "which_alternative") (const_int 2))
5858 (eq (symbol_ref "which_alternative") (const_int 3)))
5861 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
5862 where the value of the attribute being tested is known for all insns matching
5863 a particular pattern. This is by far the most common case.
5866 @item (attr_flag @var{name})
5867 The value of an @code{attr_flag} expression is true if the flag
5868 specified by @var{name} is true for the @code{insn} currently being
5871 @var{name} is a string specifying one of a fixed set of flags to test.
5872 Test the flags @code{forward} and @code{backward} to determine the
5873 direction of a conditional branch. Test the flags @code{very_likely},
5874 @code{likely}, @code{very_unlikely}, and @code{unlikely} to determine
5875 if a conditional branch is expected to be taken.
5877 If the @code{very_likely} flag is true, then the @code{likely} flag is also
5878 true. Likewise for the @code{very_unlikely} and @code{unlikely} flags.
5880 This example describes a conditional branch delay slot which
5881 can be nullified for forward branches that are taken (annul-true) or
5882 for backward branches which are not taken (annul-false).
5885 (define_delay (eq_attr "type" "cbranch")
5886 [(eq_attr "in_branch_delay" "true")
5887 (and (eq_attr "in_branch_delay" "true")
5888 (attr_flag "forward"))
5889 (and (eq_attr "in_branch_delay" "true")
5890 (attr_flag "backward"))])
5893 The @code{forward} and @code{backward} flags are false if the current
5894 @code{insn} being scheduled is not a conditional branch.
5896 The @code{very_likely} and @code{likely} flags are true if the
5897 @code{insn} being scheduled is not a conditional branch.
5898 The @code{very_unlikely} and @code{unlikely} flags are false if the
5899 @code{insn} being scheduled is not a conditional branch.
5901 @code{attr_flag} is only used during delay slot scheduling and has no
5902 meaning to other passes of the compiler.
5905 @item (attr @var{name})
5906 The value of another attribute is returned. This is most useful
5907 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
5908 produce more efficient code for non-numeric attributes.
5914 @subsection Assigning Attribute Values to Insns
5915 @cindex tagging insns
5916 @cindex assigning attribute values to insns
5918 The value assigned to an attribute of an insn is primarily determined by
5919 which pattern is matched by that insn (or which @code{define_peephole}
5920 generated it). Every @code{define_insn} and @code{define_peephole} can
5921 have an optional last argument to specify the values of attributes for
5922 matching insns. The value of any attribute not specified in a particular
5923 insn is set to the default value for that attribute, as specified in its
5924 @code{define_attr}. Extensive use of default values for attributes
5925 permits the specification of the values for only one or two attributes
5926 in the definition of most insn patterns, as seen in the example in the
5929 The optional last argument of @code{define_insn} and
5930 @code{define_peephole} is a vector of expressions, each of which defines
5931 the value for a single attribute. The most general way of assigning an
5932 attribute's value is to use a @code{set} expression whose first operand is an
5933 @code{attr} expression giving the name of the attribute being set. The
5934 second operand of the @code{set} is an attribute expression
5935 (@pxref{Expressions}) giving the value of the attribute.
5937 When the attribute value depends on the @samp{alternative} attribute
5938 (i.e., which is the applicable alternative in the constraint of the
5939 insn), the @code{set_attr_alternative} expression can be used. It
5940 allows the specification of a vector of attribute expressions, one for
5944 When the generality of arbitrary attribute expressions is not required,
5945 the simpler @code{set_attr} expression can be used, which allows
5946 specifying a string giving either a single attribute value or a list
5947 of attribute values, one for each alternative.
5949 The form of each of the above specifications is shown below. In each case,
5950 @var{name} is a string specifying the attribute to be set.
5953 @item (set_attr @var{name} @var{value-string})
5954 @var{value-string} is either a string giving the desired attribute value,
5955 or a string containing a comma-separated list giving the values for
5956 succeeding alternatives. The number of elements must match the number
5957 of alternatives in the constraint of the insn pattern.
5959 Note that it may be useful to specify @samp{*} for some alternative, in
5960 which case the attribute will assume its default value for insns matching
5963 @findex set_attr_alternative
5964 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
5965 Depending on the alternative of the insn, the value will be one of the
5966 specified values. This is a shorthand for using a @code{cond} with
5967 tests on the @samp{alternative} attribute.
5970 @item (set (attr @var{name}) @var{value})
5971 The first operand of this @code{set} must be the special RTL expression
5972 @code{attr}, whose sole operand is a string giving the name of the
5973 attribute being set. @var{value} is the value of the attribute.
5976 The following shows three different ways of representing the same
5977 attribute value specification:
5980 (set_attr "type" "load,store,arith")
5982 (set_attr_alternative "type"
5983 [(const_string "load") (const_string "store")
5984 (const_string "arith")])
5987 (cond [(eq_attr "alternative" "1") (const_string "load")
5988 (eq_attr "alternative" "2") (const_string "store")]
5989 (const_string "arith")))
5993 @findex define_asm_attributes
5994 The @code{define_asm_attributes} expression provides a mechanism to
5995 specify the attributes assigned to insns produced from an @code{asm}
5996 statement. It has the form:
5999 (define_asm_attributes [@var{attr-sets}])
6003 where @var{attr-sets} is specified the same as for both the
6004 @code{define_insn} and the @code{define_peephole} expressions.
6006 These values will typically be the ``worst case'' attribute values. For
6007 example, they might indicate that the condition code will be clobbered.
6009 A specification for a @code{length} attribute is handled specially. The
6010 way to compute the length of an @code{asm} insn is to multiply the
6011 length specified in the expression @code{define_asm_attributes} by the
6012 number of machine instructions specified in the @code{asm} statement,
6013 determined by counting the number of semicolons and newlines in the
6014 string. Therefore, the value of the @code{length} attribute specified
6015 in a @code{define_asm_attributes} should be the maximum possible length
6016 of a single machine instruction.
6021 @subsection Example of Attribute Specifications
6022 @cindex attribute specifications example
6023 @cindex attribute specifications
6025 The judicious use of defaulting is important in the efficient use of
6026 insn attributes. Typically, insns are divided into @dfn{types} and an
6027 attribute, customarily called @code{type}, is used to represent this
6028 value. This attribute is normally used only to define the default value
6029 for other attributes. An example will clarify this usage.
6031 Assume we have a RISC machine with a condition code and in which only
6032 full-word operations are performed in registers. Let us assume that we
6033 can divide all insns into loads, stores, (integer) arithmetic
6034 operations, floating point operations, and branches.
6036 Here we will concern ourselves with determining the effect of an insn on
6037 the condition code and will limit ourselves to the following possible
6038 effects: The condition code can be set unpredictably (clobbered), not
6039 be changed, be set to agree with the results of the operation, or only
6040 changed if the item previously set into the condition code has been
6043 Here is part of a sample @file{md} file for such a machine:
6046 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
6048 (define_attr "cc" "clobber,unchanged,set,change0"
6049 (cond [(eq_attr "type" "load")
6050 (const_string "change0")
6051 (eq_attr "type" "store,branch")
6052 (const_string "unchanged")
6053 (eq_attr "type" "arith")
6054 (if_then_else (match_operand:SI 0 "" "")
6055 (const_string "set")
6056 (const_string "clobber"))]
6057 (const_string "clobber")))
6060 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
6061 (match_operand:SI 1 "general_operand" "r,m,r"))]
6067 [(set_attr "type" "arith,load,store")])
6070 Note that we assume in the above example that arithmetic operations
6071 performed on quantities smaller than a machine word clobber the condition
6072 code since they will set the condition code to a value corresponding to the
6078 @subsection Computing the Length of an Insn
6079 @cindex insn lengths, computing
6080 @cindex computing the length of an insn
6082 For many machines, multiple types of branch instructions are provided, each
6083 for different length branch displacements. In most cases, the assembler
6084 will choose the correct instruction to use. However, when the assembler
6085 cannot do so, GCC can when a special attribute, the @code{length}
6086 attribute, is defined. This attribute must be defined to have numeric
6087 values by specifying a null string in its @code{define_attr}.
6089 In the case of the @code{length} attribute, two additional forms of
6090 arithmetic terms are allowed in test expressions:
6093 @cindex @code{match_dup} and attributes
6094 @item (match_dup @var{n})
6095 This refers to the address of operand @var{n} of the current insn, which
6096 must be a @code{label_ref}.
6098 @cindex @code{pc} and attributes
6100 This refers to the address of the @emph{current} insn. It might have
6101 been more consistent with other usage to make this the address of the
6102 @emph{next} insn but this would be confusing because the length of the
6103 current insn is to be computed.
6106 @cindex @code{addr_vec}, length of
6107 @cindex @code{addr_diff_vec}, length of
6108 For normal insns, the length will be determined by value of the
6109 @code{length} attribute. In the case of @code{addr_vec} and
6110 @code{addr_diff_vec} insn patterns, the length is computed as
6111 the number of vectors multiplied by the size of each vector.
6113 Lengths are measured in addressable storage units (bytes).
6115 The following macros can be used to refine the length computation:
6118 @findex ADJUST_INSN_LENGTH
6119 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
6120 If defined, modifies the length assigned to instruction @var{insn} as a
6121 function of the context in which it is used. @var{length} is an lvalue
6122 that contains the initially computed length of the insn and should be
6123 updated with the correct length of the insn.
6125 This macro will normally not be required. A case in which it is
6126 required is the ROMP@. On this machine, the size of an @code{addr_vec}
6127 insn must be increased by two to compensate for the fact that alignment
6131 @findex get_attr_length
6132 The routine that returns @code{get_attr_length} (the value of the
6133 @code{length} attribute) can be used by the output routine to
6134 determine the form of the branch instruction to be written, as the
6135 example below illustrates.
6137 As an example of the specification of variable-length branches, consider
6138 the IBM 360. If we adopt the convention that a register will be set to
6139 the starting address of a function, we can jump to labels within 4k of
6140 the start using a four-byte instruction. Otherwise, we need a six-byte
6141 sequence to load the address from memory and then branch to it.
6143 On such a machine, a pattern for a branch instruction might be specified
6149 (label_ref (match_operand 0 "" "")))]
6152 return (get_attr_length (insn) == 4
6153 ? "b %l0" : "l r15,=a(%l0); br r15");
6155 [(set (attr "length")
6156 (if_then_else (lt (match_dup 0) (const_int 4096))
6163 @node Constant Attributes
6164 @subsection Constant Attributes
6165 @cindex constant attributes
6167 A special form of @code{define_attr}, where the expression for the
6168 default value is a @code{const} expression, indicates an attribute that
6169 is constant for a given run of the compiler. Constant attributes may be
6170 used to specify which variety of processor is used. For example,
6173 (define_attr "cpu" "m88100,m88110,m88000"
6175 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
6176 (symbol_ref "TARGET_88110") (const_string "m88110")]
6177 (const_string "m88000"))))
6179 (define_attr "memory" "fast,slow"
6181 (if_then_else (symbol_ref "TARGET_FAST_MEM")
6182 (const_string "fast")
6183 (const_string "slow"))))
6186 The routine generated for constant attributes has no parameters as it
6187 does not depend on any particular insn. RTL expressions used to define
6188 the value of a constant attribute may use the @code{symbol_ref} form,
6189 but may not use either the @code{match_operand} form or @code{eq_attr}
6190 forms involving insn attributes.
6195 @subsection Delay Slot Scheduling
6196 @cindex delay slots, defining
6198 The insn attribute mechanism can be used to specify the requirements for
6199 delay slots, if any, on a target machine. An instruction is said to
6200 require a @dfn{delay slot} if some instructions that are physically
6201 after the instruction are executed as if they were located before it.
6202 Classic examples are branch and call instructions, which often execute
6203 the following instruction before the branch or call is performed.
6205 On some machines, conditional branch instructions can optionally
6206 @dfn{annul} instructions in the delay slot. This means that the
6207 instruction will not be executed for certain branch outcomes. Both
6208 instructions that annul if the branch is true and instructions that
6209 annul if the branch is false are supported.
6211 Delay slot scheduling differs from instruction scheduling in that
6212 determining whether an instruction needs a delay slot is dependent only
6213 on the type of instruction being generated, not on data flow between the
6214 instructions. See the next section for a discussion of data-dependent
6215 instruction scheduling.
6217 @findex define_delay
6218 The requirement of an insn needing one or more delay slots is indicated
6219 via the @code{define_delay} expression. It has the following form:
6222 (define_delay @var{test}
6223 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
6224 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
6228 @var{test} is an attribute test that indicates whether this
6229 @code{define_delay} applies to a particular insn. If so, the number of
6230 required delay slots is determined by the length of the vector specified
6231 as the second argument. An insn placed in delay slot @var{n} must
6232 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
6233 attribute test that specifies which insns may be annulled if the branch
6234 is true. Similarly, @var{annul-false-n} specifies which insns in the
6235 delay slot may be annulled if the branch is false. If annulling is not
6236 supported for that delay slot, @code{(nil)} should be coded.
6238 For example, in the common case where branch and call insns require
6239 a single delay slot, which may contain any insn other than a branch or
6240 call, the following would be placed in the @file{md} file:
6243 (define_delay (eq_attr "type" "branch,call")
6244 [(eq_attr "type" "!branch,call") (nil) (nil)])
6247 Multiple @code{define_delay} expressions may be specified. In this
6248 case, each such expression specifies different delay slot requirements
6249 and there must be no insn for which tests in two @code{define_delay}
6250 expressions are both true.
6252 For example, if we have a machine that requires one delay slot for branches
6253 but two for calls, no delay slot can contain a branch or call insn,
6254 and any valid insn in the delay slot for the branch can be annulled if the
6255 branch is true, we might represent this as follows:
6258 (define_delay (eq_attr "type" "branch")
6259 [(eq_attr "type" "!branch,call")
6260 (eq_attr "type" "!branch,call")
6263 (define_delay (eq_attr "type" "call")
6264 [(eq_attr "type" "!branch,call") (nil) (nil)
6265 (eq_attr "type" "!branch,call") (nil) (nil)])
6267 @c the above is *still* too long. --mew 4feb93
6271 @node Processor pipeline description
6272 @subsection Specifying processor pipeline description
6273 @cindex processor pipeline description
6274 @cindex processor functional units
6275 @cindex instruction latency time
6276 @cindex interlock delays
6277 @cindex data dependence delays
6278 @cindex reservation delays
6279 @cindex pipeline hazard recognizer
6280 @cindex automaton based pipeline description
6281 @cindex regular expressions
6282 @cindex deterministic finite state automaton
6283 @cindex automaton based scheduler
6287 To achieve better performance, most modern processors
6288 (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW}
6289 processors) have many @dfn{functional units} on which several
6290 instructions can be executed simultaneously. An instruction starts
6291 execution if its issue conditions are satisfied. If not, the
6292 instruction is stalled until its conditions are satisfied. Such
6293 @dfn{interlock (pipeline) delay} causes interruption of the fetching
6294 of successor instructions (or demands nop instructions, e.g.@: for some
6297 There are two major kinds of interlock delays in modern processors.
6298 The first one is a data dependence delay determining @dfn{instruction
6299 latency time}. The instruction execution is not started until all
6300 source data have been evaluated by prior instructions (there are more
6301 complex cases when the instruction execution starts even when the data
6302 are not available but will be ready in given time after the
6303 instruction execution start). Taking the data dependence delays into
6304 account is simple. The data dependence (true, output, and
6305 anti-dependence) delay between two instructions is given by a
6306 constant. In most cases this approach is adequate. The second kind
6307 of interlock delays is a reservation delay. The reservation delay
6308 means that two instructions under execution will be in need of shared
6309 processors resources, i.e.@: buses, internal registers, and/or
6310 functional units, which are reserved for some time. Taking this kind
6311 of delay into account is complex especially for modern @acronym{RISC}
6314 The task of exploiting more processor parallelism is solved by an
6315 instruction scheduler. For a better solution to this problem, the
6316 instruction scheduler has to have an adequate description of the
6317 processor parallelism (or @dfn{pipeline description}). GCC
6318 machine descriptions describe processor parallelism and functional
6319 unit reservations for groups of instructions with the aid of
6320 @dfn{regular expressions}.
6322 The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to
6323 figure out the possibility of the instruction issue by the processor
6324 on a given simulated processor cycle. The pipeline hazard recognizer is
6325 automatically generated from the processor pipeline description. The
6326 pipeline hazard recognizer generated from the machine description
6327 is based on a deterministic finite state automaton (@acronym{DFA}):
6328 the instruction issue is possible if there is a transition from one
6329 automaton state to another one. This algorithm is very fast, and
6330 furthermore, its speed is not dependent on processor
6331 complexity@footnote{However, the size of the automaton depends on
6332 processor complexity. To limit this effect, machine descriptions
6333 can split orthogonal parts of the machine description among several
6334 automata: but then, since each of these must be stepped independently,
6335 this does cause a small decrease in the algorithm's performance.}.
6337 @cindex automaton based pipeline description
6338 The rest of this section describes the directives that constitute
6339 an automaton-based processor pipeline description. The order of
6340 these constructions within the machine description file is not
6343 @findex define_automaton
6344 @cindex pipeline hazard recognizer
6345 The following optional construction describes names of automata
6346 generated and used for the pipeline hazards recognition. Sometimes
6347 the generated finite state automaton used by the pipeline hazard
6348 recognizer is large. If we use more than one automaton and bind functional
6349 units to the automata, the total size of the automata is usually
6350 less than the size of the single automaton. If there is no one such
6351 construction, only one finite state automaton is generated.
6354 (define_automaton @var{automata-names})
6357 @var{automata-names} is a string giving names of the automata. The
6358 names are separated by commas. All the automata should have unique names.
6359 The automaton name is used in the constructions @code{define_cpu_unit} and
6360 @code{define_query_cpu_unit}.
6362 @findex define_cpu_unit
6363 @cindex processor functional units
6364 Each processor functional unit used in the description of instruction
6365 reservations should be described by the following construction.
6368 (define_cpu_unit @var{unit-names} [@var{automaton-name}])
6371 @var{unit-names} is a string giving the names of the functional units
6372 separated by commas. Don't use name @samp{nothing}, it is reserved
6375 @var{automaton-name} is a string giving the name of the automaton with
6376 which the unit is bound. The automaton should be described in
6377 construction @code{define_automaton}. You should give
6378 @dfn{automaton-name}, if there is a defined automaton.
6380 The assignment of units to automata are constrained by the uses of the
6381 units in insn reservations. The most important constraint is: if a
6382 unit reservation is present on a particular cycle of an alternative
6383 for an insn reservation, then some unit from the same automaton must
6384 be present on the same cycle for the other alternatives of the insn
6385 reservation. The rest of the constraints are mentioned in the
6386 description of the subsequent constructions.
6388 @findex define_query_cpu_unit
6389 @cindex querying function unit reservations
6390 The following construction describes CPU functional units analogously
6391 to @code{define_cpu_unit}. The reservation of such units can be
6392 queried for an automaton state. The instruction scheduler never
6393 queries reservation of functional units for given automaton state. So
6394 as a rule, you don't need this construction. This construction could
6395 be used for future code generation goals (e.g.@: to generate
6396 @acronym{VLIW} insn templates).
6399 (define_query_cpu_unit @var{unit-names} [@var{automaton-name}])
6402 @var{unit-names} is a string giving names of the functional units
6403 separated by commas.
6405 @var{automaton-name} is a string giving the name of the automaton with
6406 which the unit is bound.
6408 @findex define_insn_reservation
6409 @cindex instruction latency time
6410 @cindex regular expressions
6412 The following construction is the major one to describe pipeline
6413 characteristics of an instruction.
6416 (define_insn_reservation @var{insn-name} @var{default_latency}
6417 @var{condition} @var{regexp})
6420 @var{default_latency} is a number giving latency time of the
6421 instruction. There is an important difference between the old
6422 description and the automaton based pipeline description. The latency
6423 time is used for all dependencies when we use the old description. In
6424 the automaton based pipeline description, the given latency time is only
6425 used for true dependencies. The cost of anti-dependencies is always
6426 zero and the cost of output dependencies is the difference between
6427 latency times of the producing and consuming insns (if the difference
6428 is negative, the cost is considered to be zero). You can always
6429 change the default costs for any description by using the target hook
6430 @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}).
6432 @var{insn-name} is a string giving the internal name of the insn. The
6433 internal names are used in constructions @code{define_bypass} and in
6434 the automaton description file generated for debugging. The internal
6435 name has nothing in common with the names in @code{define_insn}. It is a
6436 good practice to use insn classes described in the processor manual.
6438 @var{condition} defines what RTL insns are described by this
6439 construction. You should remember that you will be in trouble if
6440 @var{condition} for two or more different
6441 @code{define_insn_reservation} constructions is TRUE for an insn. In
6442 this case what reservation will be used for the insn is not defined.
6443 Such cases are not checked during generation of the pipeline hazards
6444 recognizer because in general recognizing that two conditions may have
6445 the same value is quite difficult (especially if the conditions
6446 contain @code{symbol_ref}). It is also not checked during the
6447 pipeline hazard recognizer work because it would slow down the
6448 recognizer considerably.
6450 @var{regexp} is a string describing the reservation of the cpu's functional
6451 units by the instruction. The reservations are described by a regular
6452 expression according to the following syntax:
6455 regexp = regexp "," oneof
6458 oneof = oneof "|" allof
6461 allof = allof "+" repeat
6464 repeat = element "*" number
6467 element = cpu_function_unit_name
6476 @samp{,} is used for describing the start of the next cycle in
6480 @samp{|} is used for describing a reservation described by the first
6481 regular expression @strong{or} a reservation described by the second
6482 regular expression @strong{or} etc.
6485 @samp{+} is used for describing a reservation described by the first
6486 regular expression @strong{and} a reservation described by the
6487 second regular expression @strong{and} etc.
6490 @samp{*} is used for convenience and simply means a sequence in which
6491 the regular expression are repeated @var{number} times with cycle
6492 advancing (see @samp{,}).
6495 @samp{cpu_function_unit_name} denotes reservation of the named
6499 @samp{reservation_name} --- see description of construction
6500 @samp{define_reservation}.
6503 @samp{nothing} denotes no unit reservations.
6506 @findex define_reservation
6507 Sometimes unit reservations for different insns contain common parts.
6508 In such case, you can simplify the pipeline description by describing
6509 the common part by the following construction
6512 (define_reservation @var{reservation-name} @var{regexp})
6515 @var{reservation-name} is a string giving name of @var{regexp}.
6516 Functional unit names and reservation names are in the same name
6517 space. So the reservation names should be different from the
6518 functional unit names and can not be the reserved name @samp{nothing}.
6520 @findex define_bypass
6521 @cindex instruction latency time
6523 The following construction is used to describe exceptions in the
6524 latency time for given instruction pair. This is so called bypasses.
6527 (define_bypass @var{number} @var{out_insn_names} @var{in_insn_names}
6531 @var{number} defines when the result generated by the instructions
6532 given in string @var{out_insn_names} will be ready for the
6533 instructions given in string @var{in_insn_names}. The instructions in
6534 the string are separated by commas.
6536 @var{guard} is an optional string giving the name of a C function which
6537 defines an additional guard for the bypass. The function will get the
6538 two insns as parameters. If the function returns zero the bypass will
6539 be ignored for this case. The additional guard is necessary to
6540 recognize complicated bypasses, e.g.@: when the consumer is only an address
6541 of insn @samp{store} (not a stored value).
6543 @findex exclusion_set
6544 @findex presence_set
6545 @findex final_presence_set
6547 @findex final_absence_set
6550 The following five constructions are usually used to describe
6551 @acronym{VLIW} processors, or more precisely, to describe a placement
6552 of small instructions into @acronym{VLIW} instruction slots. They
6553 can be used for @acronym{RISC} processors, too.
6556 (exclusion_set @var{unit-names} @var{unit-names})
6557 (presence_set @var{unit-names} @var{patterns})
6558 (final_presence_set @var{unit-names} @var{patterns})
6559 (absence_set @var{unit-names} @var{patterns})
6560 (final_absence_set @var{unit-names} @var{patterns})
6563 @var{unit-names} is a string giving names of functional units
6564 separated by commas.
6566 @var{patterns} is a string giving patterns of functional units
6567 separated by comma. Currently pattern is one unit or units
6568 separated by white-spaces.
6570 The first construction (@samp{exclusion_set}) means that each
6571 functional unit in the first string can not be reserved simultaneously
6572 with a unit whose name is in the second string and vice versa. For
6573 example, the construction is useful for describing processors
6574 (e.g.@: some SPARC processors) with a fully pipelined floating point
6575 functional unit which can execute simultaneously only single floating
6576 point insns or only double floating point insns.
6578 The second construction (@samp{presence_set}) means that each
6579 functional unit in the first string can not be reserved unless at
6580 least one of pattern of units whose names are in the second string is
6581 reserved. This is an asymmetric relation. For example, it is useful
6582 for description that @acronym{VLIW} @samp{slot1} is reserved after
6583 @samp{slot0} reservation. We could describe it by the following
6587 (presence_set "slot1" "slot0")
6590 Or @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0}
6591 reservation. In this case we could write
6594 (presence_set "slot1" "slot0 b0")
6597 The third construction (@samp{final_presence_set}) is analogous to
6598 @samp{presence_set}. The difference between them is when checking is
6599 done. When an instruction is issued in given automaton state
6600 reflecting all current and planned unit reservations, the automaton
6601 state is changed. The first state is a source state, the second one
6602 is a result state. Checking for @samp{presence_set} is done on the
6603 source state reservation, checking for @samp{final_presence_set} is
6604 done on the result reservation. This construction is useful to
6605 describe a reservation which is actually two subsequent reservations.
6606 For example, if we use
6609 (presence_set "slot1" "slot0")
6612 the following insn will be never issued (because @samp{slot1} requires
6613 @samp{slot0} which is absent in the source state).
6616 (define_reservation "insn_and_nop" "slot0 + slot1")
6619 but it can be issued if we use analogous @samp{final_presence_set}.
6621 The forth construction (@samp{absence_set}) means that each functional
6622 unit in the first string can be reserved only if each pattern of units
6623 whose names are in the second string is not reserved. This is an
6624 asymmetric relation (actually @samp{exclusion_set} is analogous to
6625 this one but it is symmetric). For example, it is useful for
6626 description that @acronym{VLIW} @samp{slot0} can not be reserved after
6627 @samp{slot1} or @samp{slot2} reservation. We could describe it by the
6628 following construction
6631 (absence_set "slot2" "slot0, slot1")
6634 Or @samp{slot2} can not be reserved if @samp{slot0} and unit @samp{b0}
6635 are reserved or @samp{slot1} and unit @samp{b1} are reserved. In
6636 this case we could write
6639 (absence_set "slot2" "slot0 b0, slot1 b1")
6642 All functional units mentioned in a set should belong to the same
6645 The last construction (@samp{final_absence_set}) is analogous to
6646 @samp{absence_set} but checking is done on the result (state)
6647 reservation. See comments for @samp{final_presence_set}.
6649 @findex automata_option
6650 @cindex deterministic finite state automaton
6651 @cindex nondeterministic finite state automaton
6652 @cindex finite state automaton minimization
6653 You can control the generator of the pipeline hazard recognizer with
6654 the following construction.
6657 (automata_option @var{options})
6660 @var{options} is a string giving options which affect the generated
6661 code. Currently there are the following options:
6665 @dfn{no-minimization} makes no minimization of the automaton. This is
6666 only worth to do when we are debugging the description and need to
6667 look more accurately at reservations of states.
6670 @dfn{time} means printing additional time statistics about
6671 generation of automata.
6674 @dfn{v} means a generation of the file describing the result automata.
6675 The file has suffix @samp{.dfa} and can be used for the description
6676 verification and debugging.
6679 @dfn{w} means a generation of warning instead of error for
6680 non-critical errors.
6683 @dfn{ndfa} makes nondeterministic finite state automata. This affects
6684 the treatment of operator @samp{|} in the regular expressions. The
6685 usual treatment of the operator is to try the first alternative and,
6686 if the reservation is not possible, the second alternative. The
6687 nondeterministic treatment means trying all alternatives, some of them
6688 may be rejected by reservations in the subsequent insns.
6691 @dfn{progress} means output of a progress bar showing how many states
6692 were generated so far for automaton being processed. This is useful
6693 during debugging a @acronym{DFA} description. If you see too many
6694 generated states, you could interrupt the generator of the pipeline
6695 hazard recognizer and try to figure out a reason for generation of the
6699 As an example, consider a superscalar @acronym{RISC} machine which can
6700 issue three insns (two integer insns and one floating point insn) on
6701 the cycle but can finish only two insns. To describe this, we define
6702 the following functional units.
6705 (define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline")
6706 (define_cpu_unit "port0, port1")
6709 All simple integer insns can be executed in any integer pipeline and
6710 their result is ready in two cycles. The simple integer insns are
6711 issued into the first pipeline unless it is reserved, otherwise they
6712 are issued into the second pipeline. Integer division and
6713 multiplication insns can be executed only in the second integer
6714 pipeline and their results are ready correspondingly in 8 and 4
6715 cycles. The integer division is not pipelined, i.e.@: the subsequent
6716 integer division insn can not be issued until the current division
6717 insn finished. Floating point insns are fully pipelined and their
6718 results are ready in 3 cycles. Where the result of a floating point
6719 insn is used by an integer insn, an additional delay of one cycle is
6720 incurred. To describe all of this we could specify
6723 (define_cpu_unit "div")
6725 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
6726 "(i0_pipeline | i1_pipeline), (port0 | port1)")
6728 (define_insn_reservation "mult" 4 (eq_attr "type" "mult")
6729 "i1_pipeline, nothing*2, (port0 | port1)")
6731 (define_insn_reservation "div" 8 (eq_attr "type" "div")
6732 "i1_pipeline, div*7, div + (port0 | port1)")
6734 (define_insn_reservation "float" 3 (eq_attr "type" "float")
6735 "f_pipeline, nothing, (port0 | port1))
6737 (define_bypass 4 "float" "simple,mult,div")
6740 To simplify the description we could describe the following reservation
6743 (define_reservation "finish" "port0|port1")
6746 and use it in all @code{define_insn_reservation} as in the following
6750 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
6751 "(i0_pipeline | i1_pipeline), finish")
6757 @node Conditional Execution
6758 @section Conditional Execution
6759 @cindex conditional execution
6762 A number of architectures provide for some form of conditional
6763 execution, or predication. The hallmark of this feature is the
6764 ability to nullify most of the instructions in the instruction set.
6765 When the instruction set is large and not entirely symmetric, it
6766 can be quite tedious to describe these forms directly in the
6767 @file{.md} file. An alternative is the @code{define_cond_exec} template.
6769 @findex define_cond_exec
6772 [@var{predicate-pattern}]
6774 "@var{output-template}")
6777 @var{predicate-pattern} is the condition that must be true for the
6778 insn to be executed at runtime and should match a relational operator.
6779 One can use @code{match_operator} to match several relational operators
6780 at once. Any @code{match_operand} operands must have no more than one
6783 @var{condition} is a C expression that must be true for the generated
6786 @findex current_insn_predicate
6787 @var{output-template} is a string similar to the @code{define_insn}
6788 output template (@pxref{Output Template}), except that the @samp{*}
6789 and @samp{@@} special cases do not apply. This is only useful if the
6790 assembly text for the predicate is a simple prefix to the main insn.
6791 In order to handle the general case, there is a global variable
6792 @code{current_insn_predicate} that will contain the entire predicate
6793 if the current insn is predicated, and will otherwise be @code{NULL}.
6795 When @code{define_cond_exec} is used, an implicit reference to
6796 the @code{predicable} instruction attribute is made.
6797 @xref{Insn Attributes}. This attribute must be boolean (i.e.@: have
6798 exactly two elements in its @var{list-of-values}). Further, it must
6799 not be used with complex expressions. That is, the default and all
6800 uses in the insns must be a simple constant, not dependent on the
6801 alternative or anything else.
6803 For each @code{define_insn} for which the @code{predicable}
6804 attribute is true, a new @code{define_insn} pattern will be
6805 generated that matches a predicated version of the instruction.
6809 (define_insn "addsi"
6810 [(set (match_operand:SI 0 "register_operand" "r")
6811 (plus:SI (match_operand:SI 1 "register_operand" "r")
6812 (match_operand:SI 2 "register_operand" "r")))]
6817 [(ne (match_operand:CC 0 "register_operand" "c")
6824 generates a new pattern
6829 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
6830 (set (match_operand:SI 0 "register_operand" "r")
6831 (plus:SI (match_operand:SI 1 "register_operand" "r")
6832 (match_operand:SI 2 "register_operand" "r"))))]
6833 "(@var{test2}) && (@var{test1})"
6834 "(%3) add %2,%1,%0")
6839 @node Constant Definitions
6840 @section Constant Definitions
6841 @cindex constant definitions
6842 @findex define_constants
6844 Using literal constants inside instruction patterns reduces legibility and
6845 can be a maintenance problem.
6847 To overcome this problem, you may use the @code{define_constants}
6848 expression. It contains a vector of name-value pairs. From that
6849 point on, wherever any of the names appears in the MD file, it is as
6850 if the corresponding value had been written instead. You may use
6851 @code{define_constants} multiple times; each appearance adds more
6852 constants to the table. It is an error to redefine a constant with
6855 To come back to the a29k load multiple example, instead of
6859 [(match_parallel 0 "load_multiple_operation"
6860 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
6861 (match_operand:SI 2 "memory_operand" "m"))
6863 (clobber (reg:SI 179))])]
6879 [(match_parallel 0 "load_multiple_operation"
6880 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
6881 (match_operand:SI 2 "memory_operand" "m"))
6883 (clobber (reg:SI R_CR))])]
6888 The constants that are defined with a define_constant are also output
6889 in the insn-codes.h header file as #defines.
6894 @cindex macros in @file{.md} files
6896 Ports often need to define similar patterns for more than one machine
6897 mode or for more than one rtx code. GCC provides some simple macro
6898 facilities to make this process easier.
6901 * Mode Macros:: Generating variations of patterns for different modes.
6902 * Code Macros:: Doing the same for codes.
6906 @subsection Mode Macros
6907 @cindex mode macros in @file{.md} files
6909 Ports often need to define similar patterns for two or more different modes.
6914 If a processor has hardware support for both single and double
6915 floating-point arithmetic, the @code{SFmode} patterns tend to be
6916 very similar to the @code{DFmode} ones.
6919 If a port uses @code{SImode} pointers in one configuration and
6920 @code{DImode} pointers in another, it will usually have very similar
6921 @code{SImode} and @code{DImode} patterns for manipulating pointers.
6924 Mode macros allow several patterns to be instantiated from one
6925 @file{.md} file template. They can be used with any type of
6926 rtx-based construct, such as a @code{define_insn},
6927 @code{define_split}, or @code{define_peephole2}.
6930 * Defining Mode Macros:: Defining a new mode macro.
6931 * Substitutions:: Combining mode macros with substitutions
6932 * Examples:: Examples
6935 @node Defining Mode Macros
6936 @subsubsection Defining Mode Macros
6937 @findex define_mode_macro
6939 The syntax for defining a mode macro is:
6942 (define_mode_macro @var{name} [(@var{mode1} "@var{cond1}") ... (@var{moden} "@var{condn}")])
6945 This allows subsequent @file{.md} file constructs to use the mode suffix
6946 @code{:@var{name}}. Every construct that does so will be expanded
6947 @var{n} times, once with every use of @code{:@var{name}} replaced by
6948 @code{:@var{mode1}}, once with every use replaced by @code{:@var{mode2}},
6949 and so on. In the expansion for a particular @var{modei}, every
6950 C condition will also require that @var{condi} be true.
6955 (define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
6958 defines a new mode suffix @code{:P}. Every construct that uses
6959 @code{:P} will be expanded twice, once with every @code{:P} replaced
6960 by @code{:SI} and once with every @code{:P} replaced by @code{:DI}.
6961 The @code{:SI} version will only apply if @code{Pmode == SImode} and
6962 the @code{:DI} version will only apply if @code{Pmode == DImode}.
6964 As with other @file{.md} conditions, an empty string is treated
6965 as ``always true''. @code{(@var{mode} "")} can also be abbreviated
6966 to @code{@var{mode}}. For example:
6969 (define_mode_macro GPR [SI (DI "TARGET_64BIT")])
6972 means that the @code{:DI} expansion only applies if @code{TARGET_64BIT}
6973 but that the @code{:SI} expansion has no such constraint.
6975 Macros are applied in the order they are defined. This can be
6976 significant if two macros are used in a construct that requires
6977 substitutions. @xref{Substitutions}.
6980 @subsubsection Substitution in Mode Macros
6981 @findex define_mode_attr
6983 If an @file{.md} file construct uses mode macros, each version of the
6984 construct will often need slightly different strings or modes. For
6989 When a @code{define_expand} defines several @code{add@var{m}3} patterns
6990 (@pxref{Standard Names}), each expander will need to use the
6991 appropriate mode name for @var{m}.
6994 When a @code{define_insn} defines several instruction patterns,
6995 each instruction will often use a different assembler mnemonic.
6998 When a @code{define_insn} requires operands with different modes,
6999 using a macro for one of the operand modes usually requires a specific
7000 mode for the other operand(s).
7003 GCC supports such variations through a system of ``mode attributes''.
7004 There are two standard attributes: @code{mode}, which is the name of
7005 the mode in lower case, and @code{MODE}, which is the same thing in
7006 upper case. You can define other attributes using:
7009 (define_mode_attr @var{name} [(@var{mode1} "@var{value1}") ... (@var{moden} "@var{valuen}")])
7012 where @var{name} is the name of the attribute and @var{valuei}
7013 is the value associated with @var{modei}.
7015 When GCC replaces some @var{:macro} with @var{:mode}, it will scan
7016 each string and mode in the pattern for sequences of the form
7017 @code{<@var{macro}:@var{attr}>}, where @var{attr} is the name of a
7018 mode attribute. If the attribute is defined for @var{mode}, the whole
7019 @code{<...>} sequence will be replaced by the appropriate attribute
7022 For example, suppose an @file{.md} file has:
7025 (define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
7026 (define_mode_attr load [(SI "lw") (DI "ld")])
7029 If one of the patterns that uses @code{:P} contains the string
7030 @code{"<P:load>\t%0,%1"}, the @code{SI} version of that pattern
7031 will use @code{"lw\t%0,%1"} and the @code{DI} version will use
7034 Here is an example of using an attribute for a mode:
7037 (define_mode_macro LONG [SI DI])
7038 (define_mode_attr SHORT [(SI "HI") (DI "SI")])
7040 (sign_extend:LONG (match_operand:<LONG:SHORT> ...)) ...)
7043 The @code{@var{macro}:} prefix may be omitted, in which case the
7044 substitution will be attempted for every macro expansion.
7047 @subsubsection Mode Macro Examples
7049 Here is an example from the MIPS port. It defines the following
7050 modes and attributes (among others):
7053 (define_mode_macro GPR [SI (DI "TARGET_64BIT")])
7054 (define_mode_attr d [(SI "") (DI "d")])
7057 and uses the following template to define both @code{subsi3}
7061 (define_insn "sub<mode>3"
7062 [(set (match_operand:GPR 0 "register_operand" "=d")
7063 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
7064 (match_operand:GPR 2 "register_operand" "d")))]
7067 [(set_attr "type" "arith")
7068 (set_attr "mode" "<MODE>")])
7071 This is exactly equivalent to:
7074 (define_insn "subsi3"
7075 [(set (match_operand:SI 0 "register_operand" "=d")
7076 (minus:SI (match_operand:SI 1 "register_operand" "d")
7077 (match_operand:SI 2 "register_operand" "d")))]
7080 [(set_attr "type" "arith")
7081 (set_attr "mode" "SI")])
7083 (define_insn "subdi3"
7084 [(set (match_operand:DI 0 "register_operand" "=d")
7085 (minus:DI (match_operand:DI 1 "register_operand" "d")
7086 (match_operand:DI 2 "register_operand" "d")))]
7089 [(set_attr "type" "arith")
7090 (set_attr "mode" "DI")])
7094 @subsection Code Macros
7095 @cindex code macros in @file{.md} files
7096 @findex define_code_macro
7097 @findex define_code_attr
7099 Code macros operate in a similar way to mode macros. @xref{Mode Macros}.
7104 (define_code_macro @var{name} [(@var{code1} "@var{cond1}") ... (@var{coden} "@var{condn}")])
7107 defines a pseudo rtx code @var{name} that can be instantiated as
7108 @var{codei} if condition @var{condi} is true. Each @var{codei}
7109 must have the same rtx format. @xref{RTL Classes}.
7111 As with mode macros, each pattern that uses @var{name} will be
7112 expanded @var{n} times, once with all uses of @var{name} replaced by
7113 @var{code1}, once with all uses replaced by @var{code2}, and so on.
7114 @xref{Defining Mode Macros}.
7116 It is possible to define attributes for codes as well as for modes.
7117 There are two standard code attributes: @code{code}, the name of the
7118 code in lower case, and @code{CODE}, the name of the code in upper case.
7119 Other attributes are defined using:
7122 (define_code_attr @var{name} [(@var{code1} "@var{value1}") ... (@var{coden} "@var{valuen}")])
7125 Here's an example of code macros in action, taken from the MIPS port:
7128 (define_code_macro any_cond [unordered ordered unlt unge uneq ltgt unle ungt
7129 eq ne gt ge lt le gtu geu ltu leu])
7131 (define_expand "b<code>"
7133 (if_then_else (any_cond:CC (cc0)
7135 (label_ref (match_operand 0 ""))
7139 gen_conditional_branch (operands, <CODE>);
7144 This is equivalent to:
7147 (define_expand "bunordered"
7149 (if_then_else (unordered:CC (cc0)
7151 (label_ref (match_operand 0 ""))
7155 gen_conditional_branch (operands, UNORDERED);
7159 (define_expand "bordered"
7161 (if_then_else (ordered:CC (cc0)
7163 (label_ref (match_operand 0 ""))
7167 gen_conditional_branch (operands, ORDERED);