1 @c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 1999, 2000, 2001,
2 @c 2002, 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
3 @c This is part of the GCC manual.
4 @c For copying conditions, see the file gcc.texi.
8 @chapter Machine Descriptions
9 @cindex machine descriptions
11 A machine description has two parts: a file of instruction patterns
12 (@file{.md} file) and a C header file of macro definitions.
14 The @file{.md} file for a target machine contains a pattern for each
15 instruction that the target machine supports (or at least each instruction
16 that is worth telling the compiler about). It may also contain comments.
17 A semicolon causes the rest of the line to be a comment, unless the semicolon
18 is inside a quoted string.
20 See the next chapter for information on the C header file.
23 * Overview:: How the machine description is used.
24 * Patterns:: How to write instruction patterns.
25 * Example:: An explained example of a @code{define_insn} pattern.
26 * RTL Template:: The RTL template defines what insns match a pattern.
27 * Output Template:: The output template says how to make assembler code
29 * Output Statement:: For more generality, write C code to output
31 * Predicates:: Controlling what kinds of operands can be used
33 * Constraints:: Fine-tuning operand selection.
34 * Standard Names:: Names mark patterns to use for code generation.
35 * Pattern Ordering:: When the order of patterns makes a difference.
36 * Dependent Patterns:: Having one pattern may make you need another.
37 * Jump Patterns:: Special considerations for patterns for jump insns.
38 * Looping Patterns:: How to define patterns for special looping insns.
39 * Insn Canonicalizations::Canonicalization of Instructions
40 * Expander Definitions::Generating a sequence of several RTL insns
41 for a standard operation.
42 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
43 * Including Patterns:: Including Patterns in Machine Descriptions.
44 * Peephole Definitions::Defining machine-specific peephole optimizations.
45 * Insn Attributes:: Specifying the value of attributes for generated insns.
46 * Conditional Execution::Generating @code{define_insn} patterns for
48 * Constant Definitions::Defining symbolic constants that can be used in the
50 * Iterators:: Using iterators to generate patterns from a template.
54 @section Overview of How the Machine Description is Used
56 There are three main conversions that happen in the compiler:
61 The front end reads the source code and builds a parse tree.
64 The parse tree is used to generate an RTL insn list based on named
68 The insn list is matched against the RTL templates to produce assembler
73 For the generate pass, only the names of the insns matter, from either a
74 named @code{define_insn} or a @code{define_expand}. The compiler will
75 choose the pattern with the right name and apply the operands according
76 to the documentation later in this chapter, without regard for the RTL
77 template or operand constraints. Note that the names the compiler looks
78 for are hard-coded in the compiler---it will ignore unnamed patterns and
79 patterns with names it doesn't know about, but if you don't provide a
80 named pattern it needs, it will abort.
82 If a @code{define_insn} is used, the template given is inserted into the
83 insn list. If a @code{define_expand} is used, one of three things
84 happens, based on the condition logic. The condition logic may manually
85 create new insns for the insn list, say via @code{emit_insn()}, and
86 invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
87 compiler to use an alternate way of performing that task. If it invokes
88 neither @code{DONE} nor @code{FAIL}, the template given in the pattern
89 is inserted, as if the @code{define_expand} were a @code{define_insn}.
91 Once the insn list is generated, various optimization passes convert,
92 replace, and rearrange the insns in the insn list. This is where the
93 @code{define_split} and @code{define_peephole} patterns get used, for
96 Finally, the insn list's RTL is matched up with the RTL templates in the
97 @code{define_insn} patterns, and those patterns are used to emit the
98 final assembly code. For this purpose, each named @code{define_insn}
99 acts like it's unnamed, since the names are ignored.
102 @section Everything about Instruction Patterns
104 @cindex instruction patterns
107 Each instruction pattern contains an incomplete RTL expression, with pieces
108 to be filled in later, operand constraints that restrict how the pieces can
109 be filled in, and an output pattern or C code to generate the assembler
110 output, all wrapped up in a @code{define_insn} expression.
112 A @code{define_insn} is an RTL expression containing four or five operands:
116 An optional name. The presence of a name indicate that this instruction
117 pattern can perform a certain standard job for the RTL-generation
118 pass of the compiler. This pass knows certain names and will use
119 the instruction patterns with those names, if the names are defined
120 in the machine description.
122 The absence of a name is indicated by writing an empty string
123 where the name should go. Nameless instruction patterns are never
124 used for generating RTL code, but they may permit several simpler insns
125 to be combined later on.
127 Names that are not thus known and used in RTL-generation have no
128 effect; they are equivalent to no name at all.
130 For the purpose of debugging the compiler, you may also specify a
131 name beginning with the @samp{*} character. Such a name is used only
132 for identifying the instruction in RTL dumps; it is entirely equivalent
133 to having a nameless pattern for all other purposes.
136 The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete
137 RTL expressions which show what the instruction should look like. It is
138 incomplete because it may contain @code{match_operand},
139 @code{match_operator}, and @code{match_dup} expressions that stand for
140 operands of the instruction.
142 If the vector has only one element, that element is the template for the
143 instruction pattern. If the vector has multiple elements, then the
144 instruction pattern is a @code{parallel} expression containing the
148 @cindex pattern conditions
149 @cindex conditions, in patterns
150 A condition. This is a string which contains a C expression that is
151 the final test to decide whether an insn body matches this pattern.
153 @cindex named patterns and conditions
154 For a named pattern, the condition (if present) may not depend on
155 the data in the insn being matched, but only the target-machine-type
156 flags. The compiler needs to test these conditions during
157 initialization in order to learn exactly which named instructions are
158 available in a particular run.
161 For nameless patterns, the condition is applied only when matching an
162 individual insn, and only after the insn has matched the pattern's
163 recognition template. The insn's operands may be found in the vector
164 @code{operands}. For an insn where the condition has once matched, it
165 can't be used to control register allocation, for example by excluding
166 certain hard registers or hard register combinations.
169 The @dfn{output template}: a string that says how to output matching
170 insns as assembler code. @samp{%} in this string specifies where
171 to substitute the value of an operand. @xref{Output Template}.
173 When simple substitution isn't general enough, you can specify a piece
174 of C code to compute the output. @xref{Output Statement}.
177 Optionally, a vector containing the values of attributes for insns matching
178 this pattern. @xref{Insn Attributes}.
182 @section Example of @code{define_insn}
183 @cindex @code{define_insn} example
185 Here is an actual example of an instruction pattern, for the 68000/68020.
190 (match_operand:SI 0 "general_operand" "rm"))]
194 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
196 return \"cmpl #0,%0\";
201 This can also be written using braced strings:
206 (match_operand:SI 0 "general_operand" "rm"))]
209 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
215 This is an instruction that sets the condition codes based on the value of
216 a general operand. It has no condition, so any insn whose RTL description
217 has the form shown may be handled according to this pattern. The name
218 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation
219 pass that, when it is necessary to test such a value, an insn to do so
220 can be constructed using this pattern.
222 The output control string is a piece of C code which chooses which
223 output template to return based on the kind of operand and the specific
224 type of CPU for which code is being generated.
226 @samp{"rm"} is an operand constraint. Its meaning is explained below.
229 @section RTL Template
230 @cindex RTL insn template
231 @cindex generating insns
232 @cindex insns, generating
233 @cindex recognizing insns
234 @cindex insns, recognizing
236 The RTL template is used to define which insns match the particular pattern
237 and how to find their operands. For named patterns, the RTL template also
238 says how to construct an insn from specified operands.
240 Construction involves substituting specified operands into a copy of the
241 template. Matching involves determining the values that serve as the
242 operands in the insn being matched. Both of these activities are
243 controlled by special expression types that direct matching and
244 substitution of the operands.
247 @findex match_operand
248 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
249 This expression is a placeholder for operand number @var{n} of
250 the insn. When constructing an insn, operand number @var{n}
251 will be substituted at this point. When matching an insn, whatever
252 appears at this position in the insn will be taken as operand
253 number @var{n}; but it must satisfy @var{predicate} or this instruction
254 pattern will not match at all.
256 Operand numbers must be chosen consecutively counting from zero in
257 each instruction pattern. There may be only one @code{match_operand}
258 expression in the pattern for each operand number. Usually operands
259 are numbered in the order of appearance in @code{match_operand}
260 expressions. In the case of a @code{define_expand}, any operand numbers
261 used only in @code{match_dup} expressions have higher values than all
262 other operand numbers.
264 @var{predicate} is a string that is the name of a function that
265 accepts two arguments, an expression and a machine mode.
266 @xref{Predicates}. During matching, the function will be called with
267 the putative operand as the expression and @var{m} as the mode
268 argument (if @var{m} is not specified, @code{VOIDmode} will be used,
269 which normally causes @var{predicate} to accept any mode). If it
270 returns zero, this instruction pattern fails to match.
271 @var{predicate} may be an empty string; then it means no test is to be
272 done on the operand, so anything which occurs in this position is
275 Most of the time, @var{predicate} will reject modes other than @var{m}---but
276 not always. For example, the predicate @code{address_operand} uses
277 @var{m} as the mode of memory ref that the address should be valid for.
278 Many predicates accept @code{const_int} nodes even though their mode is
281 @var{constraint} controls reloading and the choice of the best register
282 class to use for a value, as explained later (@pxref{Constraints}).
283 If the constraint would be an empty string, it can be omitted.
285 People are often unclear on the difference between the constraint and the
286 predicate. The predicate helps decide whether a given insn matches the
287 pattern. The constraint plays no role in this decision; instead, it
288 controls various decisions in the case of an insn which does match.
290 @findex match_scratch
291 @item (match_scratch:@var{m} @var{n} @var{constraint})
292 This expression is also a placeholder for operand number @var{n}
293 and indicates that operand must be a @code{scratch} or @code{reg}
296 When matching patterns, this is equivalent to
299 (match_operand:@var{m} @var{n} "scratch_operand" @var{pred})
302 but, when generating RTL, it produces a (@code{scratch}:@var{m})
305 If the last few expressions in a @code{parallel} are @code{clobber}
306 expressions whose operands are either a hard register or
307 @code{match_scratch}, the combiner can add or delete them when
308 necessary. @xref{Side Effects}.
311 @item (match_dup @var{n})
312 This expression is also a placeholder for operand number @var{n}.
313 It is used when the operand needs to appear more than once in the
316 In construction, @code{match_dup} acts just like @code{match_operand}:
317 the operand is substituted into the insn being constructed. But in
318 matching, @code{match_dup} behaves differently. It assumes that operand
319 number @var{n} has already been determined by a @code{match_operand}
320 appearing earlier in the recognition template, and it matches only an
321 identical-looking expression.
323 Note that @code{match_dup} should not be used to tell the compiler that
324 a particular register is being used for two operands (example:
325 @code{add} that adds one register to another; the second register is
326 both an input operand and the output operand). Use a matching
327 constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
328 operand is used in two places in the template, such as an instruction
329 that computes both a quotient and a remainder, where the opcode takes
330 two input operands but the RTL template has to refer to each of those
331 twice; once for the quotient pattern and once for the remainder pattern.
333 @findex match_operator
334 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
335 This pattern is a kind of placeholder for a variable RTL expression
338 When constructing an insn, it stands for an RTL expression whose
339 expression code is taken from that of operand @var{n}, and whose
340 operands are constructed from the patterns @var{operands}.
342 When matching an expression, it matches an expression if the function
343 @var{predicate} returns nonzero on that expression @emph{and} the
344 patterns @var{operands} match the operands of the expression.
346 Suppose that the function @code{commutative_operator} is defined as
347 follows, to match any expression whose operator is one of the
348 commutative arithmetic operators of RTL and whose mode is @var{mode}:
352 commutative_integer_operator (x, mode)
354 enum machine_mode mode;
356 enum rtx_code code = GET_CODE (x);
357 if (GET_MODE (x) != mode)
359 return (GET_RTX_CLASS (code) == RTX_COMM_ARITH
360 || code == EQ || code == NE);
364 Then the following pattern will match any RTL expression consisting
365 of a commutative operator applied to two general operands:
368 (match_operator:SI 3 "commutative_operator"
369 [(match_operand:SI 1 "general_operand" "g")
370 (match_operand:SI 2 "general_operand" "g")])
373 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
374 because the expressions to be matched all contain two operands.
376 When this pattern does match, the two operands of the commutative
377 operator are recorded as operands 1 and 2 of the insn. (This is done
378 by the two instances of @code{match_operand}.) Operand 3 of the insn
379 will be the entire commutative expression: use @code{GET_CODE
380 (operands[3])} to see which commutative operator was used.
382 The machine mode @var{m} of @code{match_operator} works like that of
383 @code{match_operand}: it is passed as the second argument to the
384 predicate function, and that function is solely responsible for
385 deciding whether the expression to be matched ``has'' that mode.
387 When constructing an insn, argument 3 of the gen-function will specify
388 the operation (i.e.@: the expression code) for the expression to be
389 made. It should be an RTL expression, whose expression code is copied
390 into a new expression whose operands are arguments 1 and 2 of the
391 gen-function. The subexpressions of argument 3 are not used;
392 only its expression code matters.
394 When @code{match_operator} is used in a pattern for matching an insn,
395 it usually best if the operand number of the @code{match_operator}
396 is higher than that of the actual operands of the insn. This improves
397 register allocation because the register allocator often looks at
398 operands 1 and 2 of insns to see if it can do register tying.
400 There is no way to specify constraints in @code{match_operator}. The
401 operand of the insn which corresponds to the @code{match_operator}
402 never has any constraints because it is never reloaded as a whole.
403 However, if parts of its @var{operands} are matched by
404 @code{match_operand} patterns, those parts may have constraints of
408 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
409 Like @code{match_dup}, except that it applies to operators instead of
410 operands. When constructing an insn, operand number @var{n} will be
411 substituted at this point. But in matching, @code{match_op_dup} behaves
412 differently. It assumes that operand number @var{n} has already been
413 determined by a @code{match_operator} appearing earlier in the
414 recognition template, and it matches only an identical-looking
417 @findex match_parallel
418 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
419 This pattern is a placeholder for an insn that consists of a
420 @code{parallel} expression with a variable number of elements. This
421 expression should only appear at the top level of an insn pattern.
423 When constructing an insn, operand number @var{n} will be substituted at
424 this point. When matching an insn, it matches if the body of the insn
425 is a @code{parallel} expression with at least as many elements as the
426 vector of @var{subpat} expressions in the @code{match_parallel}, if each
427 @var{subpat} matches the corresponding element of the @code{parallel},
428 @emph{and} the function @var{predicate} returns nonzero on the
429 @code{parallel} that is the body of the insn. It is the responsibility
430 of the predicate to validate elements of the @code{parallel} beyond
431 those listed in the @code{match_parallel}.
433 A typical use of @code{match_parallel} is to match load and store
434 multiple expressions, which can contain a variable number of elements
435 in a @code{parallel}. For example,
439 [(match_parallel 0 "load_multiple_operation"
440 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
441 (match_operand:SI 2 "memory_operand" "m"))
443 (clobber (reg:SI 179))])]
448 This example comes from @file{a29k.md}. The function
449 @code{load_multiple_operation} is defined in @file{a29k.c} and checks
450 that subsequent elements in the @code{parallel} are the same as the
451 @code{set} in the pattern, except that they are referencing subsequent
452 registers and memory locations.
454 An insn that matches this pattern might look like:
458 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
460 (clobber (reg:SI 179))
462 (mem:SI (plus:SI (reg:SI 100)
465 (mem:SI (plus:SI (reg:SI 100)
469 @findex match_par_dup
470 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
471 Like @code{match_op_dup}, but for @code{match_parallel} instead of
472 @code{match_operator}.
476 @node Output Template
477 @section Output Templates and Operand Substitution
478 @cindex output templates
479 @cindex operand substitution
481 @cindex @samp{%} in template
483 The @dfn{output template} is a string which specifies how to output the
484 assembler code for an instruction pattern. Most of the template is a
485 fixed string which is output literally. The character @samp{%} is used
486 to specify where to substitute an operand; it can also be used to
487 identify places where different variants of the assembler require
490 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
491 operand @var{n} at that point in the string.
493 @samp{%} followed by a letter and a digit says to output an operand in an
494 alternate fashion. Four letters have standard, built-in meanings described
495 below. The machine description macro @code{PRINT_OPERAND} can define
496 additional letters with nonstandard meanings.
498 @samp{%c@var{digit}} can be used to substitute an operand that is a
499 constant value without the syntax that normally indicates an immediate
502 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
503 the constant is negated before printing.
505 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
506 memory reference, with the actual operand treated as the address. This may
507 be useful when outputting a ``load address'' instruction, because often the
508 assembler syntax for such an instruction requires you to write the operand
509 as if it were a memory reference.
511 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
514 @samp{%=} outputs a number which is unique to each instruction in the
515 entire compilation. This is useful for making local labels to be
516 referred to more than once in a single template that generates multiple
517 assembler instructions.
519 @samp{%} followed by a punctuation character specifies a substitution that
520 does not use an operand. Only one case is standard: @samp{%%} outputs a
521 @samp{%} into the assembler code. Other nonstandard cases can be
522 defined in the @code{PRINT_OPERAND} macro. You must also define
523 which punctuation characters are valid with the
524 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
528 The template may generate multiple assembler instructions. Write the text
529 for the instructions, with @samp{\;} between them.
531 @cindex matching operands
532 When the RTL contains two operands which are required by constraint to match
533 each other, the output template must refer only to the lower-numbered operand.
534 Matching operands are not always identical, and the rest of the compiler
535 arranges to put the proper RTL expression for printing into the lower-numbered
538 One use of nonstandard letters or punctuation following @samp{%} is to
539 distinguish between different assembler languages for the same machine; for
540 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
541 requires periods in most opcode names, while MIT syntax does not. For
542 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
543 syntax. The same file of patterns is used for both kinds of output syntax,
544 but the character sequence @samp{%.} is used in each place where Motorola
545 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
546 defines the sequence to output a period; the macro for MIT syntax defines
549 @cindex @code{#} in template
550 As a special case, a template consisting of the single character @code{#}
551 instructs the compiler to first split the insn, and then output the
552 resulting instructions separately. This helps eliminate redundancy in the
553 output templates. If you have a @code{define_insn} that needs to emit
554 multiple assembler instructions, and there is an matching @code{define_split}
555 already defined, then you can simply use @code{#} as the output template
556 instead of writing an output template that emits the multiple assembler
559 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
560 of the form @samp{@{option0|option1|option2@}} in the templates. These
561 describe multiple variants of assembler language syntax.
562 @xref{Instruction Output}.
564 @node Output Statement
565 @section C Statements for Assembler Output
566 @cindex output statements
567 @cindex C statements for assembler output
568 @cindex generating assembler output
570 Often a single fixed template string cannot produce correct and efficient
571 assembler code for all the cases that are recognized by a single
572 instruction pattern. For example, the opcodes may depend on the kinds of
573 operands; or some unfortunate combinations of operands may require extra
574 machine instructions.
576 If the output control string starts with a @samp{@@}, then it is actually
577 a series of templates, each on a separate line. (Blank lines and
578 leading spaces and tabs are ignored.) The templates correspond to the
579 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
580 if a target machine has a two-address add instruction @samp{addr} to add
581 into a register and another @samp{addm} to add a register to memory, you
582 might write this pattern:
585 (define_insn "addsi3"
586 [(set (match_operand:SI 0 "general_operand" "=r,m")
587 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
588 (match_operand:SI 2 "general_operand" "g,r")))]
595 @cindex @code{*} in template
596 @cindex asterisk in template
597 If the output control string starts with a @samp{*}, then it is not an
598 output template but rather a piece of C program that should compute a
599 template. It should execute a @code{return} statement to return the
600 template-string you want. Most such templates use C string literals, which
601 require doublequote characters to delimit them. To include these
602 doublequote characters in the string, prefix each one with @samp{\}.
604 If the output control string is written as a brace block instead of a
605 double-quoted string, it is automatically assumed to be C code. In that
606 case, it is not necessary to put in a leading asterisk, or to escape the
607 doublequotes surrounding C string literals.
609 The operands may be found in the array @code{operands}, whose C data type
612 It is very common to select different ways of generating assembler code
613 based on whether an immediate operand is within a certain range. Be
614 careful when doing this, because the result of @code{INTVAL} is an
615 integer on the host machine. If the host machine has more bits in an
616 @code{int} than the target machine has in the mode in which the constant
617 will be used, then some of the bits you get from @code{INTVAL} will be
618 superfluous. For proper results, you must carefully disregard the
619 values of those bits.
621 @findex output_asm_insn
622 It is possible to output an assembler instruction and then go on to output
623 or compute more of them, using the subroutine @code{output_asm_insn}. This
624 receives two arguments: a template-string and a vector of operands. The
625 vector may be @code{operands}, or it may be another array of @code{rtx}
626 that you declare locally and initialize yourself.
628 @findex which_alternative
629 When an insn pattern has multiple alternatives in its constraints, often
630 the appearance of the assembler code is determined mostly by which alternative
631 was matched. When this is so, the C code can test the variable
632 @code{which_alternative}, which is the ordinal number of the alternative
633 that was actually satisfied (0 for the first, 1 for the second alternative,
636 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
637 for registers and @samp{clrmem} for memory locations. Here is how
638 a pattern could use @code{which_alternative} to choose between them:
642 [(set (match_operand:SI 0 "general_operand" "=r,m")
646 return (which_alternative == 0
647 ? "clrreg %0" : "clrmem %0");
651 The example above, where the assembler code to generate was
652 @emph{solely} determined by the alternative, could also have been specified
653 as follows, having the output control string start with a @samp{@@}:
658 [(set (match_operand:SI 0 "general_operand" "=r,m")
670 @cindex operand predicates
671 @cindex operator predicates
673 A predicate determines whether a @code{match_operand} or
674 @code{match_operator} expression matches, and therefore whether the
675 surrounding instruction pattern will be used for that combination of
676 operands. GCC has a number of machine-independent predicates, and you
677 can define machine-specific predicates as needed. By convention,
678 predicates used with @code{match_operand} have names that end in
679 @samp{_operand}, and those used with @code{match_operator} have names
680 that end in @samp{_operator}.
682 All predicates are Boolean functions (in the mathematical sense) of
683 two arguments: the RTL expression that is being considered at that
684 position in the instruction pattern, and the machine mode that the
685 @code{match_operand} or @code{match_operator} specifies. In this
686 section, the first argument is called @var{op} and the second argument
687 @var{mode}. Predicates can be called from C as ordinary two-argument
688 functions; this can be useful in output templates or other
689 machine-specific code.
691 Operand predicates can allow operands that are not actually acceptable
692 to the hardware, as long as the constraints give reload the ability to
693 fix them up (@pxref{Constraints}). However, GCC will usually generate
694 better code if the predicates specify the requirements of the machine
695 instructions as closely as possible. Reload cannot fix up operands
696 that must be constants (``immediate operands''); you must use a
697 predicate that allows only constants, or else enforce the requirement
698 in the extra condition.
700 @cindex predicates and machine modes
701 @cindex normal predicates
702 @cindex special predicates
703 Most predicates handle their @var{mode} argument in a uniform manner.
704 If @var{mode} is @code{VOIDmode} (unspecified), then @var{op} can have
705 any mode. If @var{mode} is anything else, then @var{op} must have the
706 same mode, unless @var{op} is a @code{CONST_INT} or integer
707 @code{CONST_DOUBLE}. These RTL expressions always have
708 @code{VOIDmode}, so it would be counterproductive to check that their
709 mode matches. Instead, predicates that accept @code{CONST_INT} and/or
710 integer @code{CONST_DOUBLE} check that the value stored in the
711 constant will fit in the requested mode.
713 Predicates with this behavior are called @dfn{normal}.
714 @command{genrecog} can optimize the instruction recognizer based on
715 knowledge of how normal predicates treat modes. It can also diagnose
716 certain kinds of common errors in the use of normal predicates; for
717 instance, it is almost always an error to use a normal predicate
718 without specifying a mode.
720 Predicates that do something different with their @var{mode} argument
721 are called @dfn{special}. The generic predicates
722 @code{address_operand} and @code{pmode_register_operand} are special
723 predicates. @command{genrecog} does not do any optimizations or
724 diagnosis when special predicates are used.
727 * Machine-Independent Predicates:: Predicates available to all back ends.
728 * Defining Predicates:: How to write machine-specific predicate
732 @node Machine-Independent Predicates
733 @subsection Machine-Independent Predicates
734 @cindex machine-independent predicates
735 @cindex generic predicates
737 These are the generic predicates available to all back ends. They are
738 defined in @file{recog.c}. The first category of predicates allow
739 only constant, or @dfn{immediate}, operands.
741 @defun immediate_operand
742 This predicate allows any sort of constant that fits in @var{mode}.
743 It is an appropriate choice for instructions that take operands that
747 @defun const_int_operand
748 This predicate allows any @code{CONST_INT} expression that fits in
749 @var{mode}. It is an appropriate choice for an immediate operand that
750 does not allow a symbol or label.
753 @defun const_double_operand
754 This predicate accepts any @code{CONST_DOUBLE} expression that has
755 exactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also
756 accept @code{CONST_INT}. It is intended for immediate floating point
761 The second category of predicates allow only some kind of machine
764 @defun register_operand
765 This predicate allows any @code{REG} or @code{SUBREG} expression that
766 is valid for @var{mode}. It is often suitable for arithmetic
767 instruction operands on a RISC machine.
770 @defun pmode_register_operand
771 This is a slight variant on @code{register_operand} which works around
772 a limitation in the machine-description reader.
775 (match_operand @var{n} "pmode_register_operand" @var{constraint})
782 (match_operand:P @var{n} "register_operand" @var{constraint})
786 would mean, if the machine-description reader accepted @samp{:P}
787 mode suffixes. Unfortunately, it cannot, because @code{Pmode} is an
788 alias for some other mode, and might vary with machine-specific
789 options. @xref{Misc}.
792 @defun scratch_operand
793 This predicate allows hard registers and @code{SCRATCH} expressions,
794 but not pseudo-registers. It is used internally by @code{match_scratch};
795 it should not be used directly.
799 The third category of predicates allow only some kind of memory reference.
801 @defun memory_operand
802 This predicate allows any valid reference to a quantity of mode
803 @var{mode} in memory, as determined by the weak form of
804 @code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}).
807 @defun address_operand
808 This predicate is a little unusual; it allows any operand that is a
809 valid expression for the @emph{address} of a quantity of mode
810 @var{mode}, again determined by the weak form of
811 @code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if
812 @samp{@w{(mem:@var{mode} (@var{exp}))}} is acceptable to
813 @code{memory_operand}, then @var{exp} is acceptable to
814 @code{address_operand}. Note that @var{exp} does not necessarily have
818 @defun indirect_operand
819 This is a stricter form of @code{memory_operand} which allows only
820 memory references with a @code{general_operand} as the address
821 expression. New uses of this predicate are discouraged, because
822 @code{general_operand} is very permissive, so it's hard to tell what
823 an @code{indirect_operand} does or does not allow. If a target has
824 different requirements for memory operands for different instructions,
825 it is better to define target-specific predicates which enforce the
826 hardware's requirements explicitly.
830 This predicate allows a memory reference suitable for pushing a value
831 onto the stack. This will be a @code{MEM} which refers to
832 @code{stack_pointer_rtx}, with a side-effect in its address expression
833 (@pxref{Incdec}); which one is determined by the
834 @code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}).
838 This predicate allows a memory reference suitable for popping a value
839 off the stack. Again, this will be a @code{MEM} referring to
840 @code{stack_pointer_rtx}, with a side-effect in its address
841 expression. However, this time @code{STACK_POP_CODE} is expected.
845 The fourth category of predicates allow some combination of the above
848 @defun nonmemory_operand
849 This predicate allows any immediate or register operand valid for @var{mode}.
852 @defun nonimmediate_operand
853 This predicate allows any register or memory operand valid for @var{mode}.
856 @defun general_operand
857 This predicate allows any immediate, register, or memory operand
858 valid for @var{mode}.
862 Finally, there is one generic operator predicate.
864 @defun comparison_operator
865 This predicate matches any expression which performs an arithmetic
866 comparison in @var{mode}; that is, @code{COMPARISON_P} is true for the
870 @node Defining Predicates
871 @subsection Defining Machine-Specific Predicates
872 @cindex defining predicates
873 @findex define_predicate
874 @findex define_special_predicate
876 Many machines have requirements for their operands that cannot be
877 expressed precisely using the generic predicates. You can define
878 additional predicates using @code{define_predicate} and
879 @code{define_special_predicate} expressions. These expressions have
884 The name of the predicate, as it will be referred to in
885 @code{match_operand} or @code{match_operator} expressions.
888 An RTL expression which evaluates to true if the predicate allows the
889 operand @var{op}, false if it does not. This expression can only use
890 the following RTL codes:
894 When written inside a predicate expression, a @code{MATCH_OPERAND}
895 expression evaluates to true if the predicate it names would allow
896 @var{op}. The operand number and constraint are ignored. Due to
897 limitations in @command{genrecog}, you can only refer to generic
898 predicates and predicates that have already been defined.
901 This expression evaluates to true if @var{op} or a specified
902 subexpression of @var{op} has one of a given list of RTX codes.
904 The first operand of this expression is a string constant containing a
905 comma-separated list of RTX code names (in lower case). These are the
906 codes for which the @code{MATCH_CODE} will be true.
908 The second operand is a string constant which indicates what
909 subexpression of @var{op} to examine. If it is absent or the empty
910 string, @var{op} itself is examined. Otherwise, the string constant
911 must be a sequence of digits and/or lowercase letters. Each character
912 indicates a subexpression to extract from the current expression; for
913 the first character this is @var{op}, for the second and subsequent
914 characters it is the result of the previous character. A digit
915 @var{n} extracts @samp{@w{XEXP (@var{e}, @var{n})}}; a letter @var{l}
916 extracts @samp{@w{XVECEXP (@var{e}, 0, @var{n})}} where @var{n} is the
917 alphabetic ordinal of @var{l} (0 for `a', 1 for 'b', and so on). The
918 @code{MATCH_CODE} then examines the RTX code of the subexpression
919 extracted by the complete string. It is not possible to extract
920 components of an @code{rtvec} that is not at position 0 within its RTX
924 This expression has one operand, a string constant containing a C
925 expression. The predicate's arguments, @var{op} and @var{mode}, are
926 available with those names in the C expression. The @code{MATCH_TEST}
927 evaluates to true if the C expression evaluates to a nonzero value.
928 @code{MATCH_TEST} expressions must not have side effects.
934 The basic @samp{MATCH_} expressions can be combined using these
935 logical operators, which have the semantics of the C operators
936 @samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively. As
937 in Common Lisp, you may give an @code{AND} or @code{IOR} expression an
938 arbitrary number of arguments; this has exactly the same effect as
939 writing a chain of two-argument @code{AND} or @code{IOR} expressions.
943 An optional block of C code, which should execute
944 @samp{@w{return true}} if the predicate is found to match and
945 @samp{@w{return false}} if it does not. It must not have any side
946 effects. The predicate arguments, @var{op} and @var{mode}, are
947 available with those names.
949 If a code block is present in a predicate definition, then the RTL
950 expression must evaluate to true @emph{and} the code block must
951 execute @samp{@w{return true}} for the predicate to allow the operand.
952 The RTL expression is evaluated first; do not re-check anything in the
953 code block that was checked in the RTL expression.
956 The program @command{genrecog} scans @code{define_predicate} and
957 @code{define_special_predicate} expressions to determine which RTX
958 codes are possibly allowed. You should always make this explicit in
959 the RTL predicate expression, using @code{MATCH_OPERAND} and
962 Here is an example of a simple predicate definition, from the IA64
967 ;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.}
968 (define_predicate "small_addr_symbolic_operand"
969 (and (match_code "symbol_ref")
970 (match_test "SYMBOL_REF_SMALL_ADDR_P (op)")))
975 And here is another, showing the use of the C block.
979 ;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.}
980 (define_predicate "gr_register_operand"
981 (match_operand 0 "register_operand")
984 if (GET_CODE (op) == SUBREG)
985 op = SUBREG_REG (op);
988 return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno));
993 Predicates written with @code{define_predicate} automatically include
994 a test that @var{mode} is @code{VOIDmode}, or @var{op} has the same
995 mode as @var{mode}, or @var{op} is a @code{CONST_INT} or
996 @code{CONST_DOUBLE}. They do @emph{not} check specifically for
997 integer @code{CONST_DOUBLE}, nor do they test that the value of either
998 kind of constant fits in the requested mode. This is because
999 target-specific predicates that take constants usually have to do more
1000 stringent value checks anyway. If you need the exact same treatment
1001 of @code{CONST_INT} or @code{CONST_DOUBLE} that the generic predicates
1002 provide, use a @code{MATCH_OPERAND} subexpression to call
1003 @code{const_int_operand}, @code{const_double_operand}, or
1004 @code{immediate_operand}.
1006 Predicates written with @code{define_special_predicate} do not get any
1007 automatic mode checks, and are treated as having special mode handling
1008 by @command{genrecog}.
1010 The program @command{genpreds} is responsible for generating code to
1011 test predicates. It also writes a header file containing function
1012 declarations for all machine-specific predicates. It is not necessary
1013 to declare these predicates in @file{@var{cpu}-protos.h}.
1016 @c Most of this node appears by itself (in a different place) even
1017 @c when the INTERNALS flag is clear. Passages that require the internals
1018 @c manual's context are conditionalized to appear only in the internals manual.
1021 @section Operand Constraints
1022 @cindex operand constraints
1025 Each @code{match_operand} in an instruction pattern can specify
1026 constraints for the operands allowed. The constraints allow you to
1027 fine-tune matching within the set of operands allowed by the
1033 @section Constraints for @code{asm} Operands
1034 @cindex operand constraints, @code{asm}
1035 @cindex constraints, @code{asm}
1036 @cindex @code{asm} constraints
1038 Here are specific details on what constraint letters you can use with
1039 @code{asm} operands.
1041 Constraints can say whether
1042 an operand may be in a register, and which kinds of register; whether the
1043 operand can be a memory reference, and which kinds of address; whether the
1044 operand may be an immediate constant, and which possible values it may
1045 have. Constraints can also require two operands to match.
1049 * Simple Constraints:: Basic use of constraints.
1050 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1051 * Class Preferences:: Constraints guide which hard register to put things in.
1052 * Modifiers:: More precise control over effects of constraints.
1053 * Disable Insn Alternatives:: Disable insn alternatives using the @code{enabled} attribute.
1054 * Machine Constraints:: Existing constraints for some particular machines.
1055 * Define Constraints:: How to define machine-specific constraints.
1056 * C Constraint Interface:: How to test constraints from C code.
1062 * Simple Constraints:: Basic use of constraints.
1063 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1064 * Modifiers:: More precise control over effects of constraints.
1065 * Machine Constraints:: Special constraints for some particular machines.
1069 @node Simple Constraints
1070 @subsection Simple Constraints
1071 @cindex simple constraints
1073 The simplest kind of constraint is a string full of letters, each of
1074 which describes one kind of operand that is permitted. Here are
1075 the letters that are allowed:
1079 Whitespace characters are ignored and can be inserted at any position
1080 except the first. This enables each alternative for different operands to
1081 be visually aligned in the machine description even if they have different
1082 number of constraints and modifiers.
1084 @cindex @samp{m} in constraint
1085 @cindex memory references in constraints
1087 A memory operand is allowed, with any kind of address that the machine
1088 supports in general.
1089 Note that the letter used for the general memory constraint can be
1090 re-defined by a back end using the @code{TARGET_MEM_CONSTRAINT} macro.
1092 @cindex offsettable address
1093 @cindex @samp{o} in constraint
1095 A memory operand is allowed, but only if the address is
1096 @dfn{offsettable}. This means that adding a small integer (actually,
1097 the width in bytes of the operand, as determined by its machine mode)
1098 may be added to the address and the result is also a valid memory
1101 @cindex autoincrement/decrement addressing
1102 For example, an address which is constant is offsettable; so is an
1103 address that is the sum of a register and a constant (as long as a
1104 slightly larger constant is also within the range of address-offsets
1105 supported by the machine); but an autoincrement or autodecrement
1106 address is not offsettable. More complicated indirect/indexed
1107 addresses may or may not be offsettable depending on the other
1108 addressing modes that the machine supports.
1110 Note that in an output operand which can be matched by another
1111 operand, the constraint letter @samp{o} is valid only when accompanied
1112 by both @samp{<} (if the target machine has predecrement addressing)
1113 and @samp{>} (if the target machine has preincrement addressing).
1115 @cindex @samp{V} in constraint
1117 A memory operand that is not offsettable. In other words, anything that
1118 would fit the @samp{m} constraint but not the @samp{o} constraint.
1120 @cindex @samp{<} in constraint
1122 A memory operand with autodecrement addressing (either predecrement or
1123 postdecrement) is allowed.
1125 @cindex @samp{>} in constraint
1127 A memory operand with autoincrement addressing (either preincrement or
1128 postincrement) is allowed.
1130 @cindex @samp{r} in constraint
1131 @cindex registers in constraints
1133 A register operand is allowed provided that it is in a general
1136 @cindex constants in constraints
1137 @cindex @samp{i} in constraint
1139 An immediate integer operand (one with constant value) is allowed.
1140 This includes symbolic constants whose values will be known only at
1141 assembly time or later.
1143 @cindex @samp{n} in constraint
1145 An immediate integer operand with a known numeric value is allowed.
1146 Many systems cannot support assembly-time constants for operands less
1147 than a word wide. Constraints for these operands should use @samp{n}
1148 rather than @samp{i}.
1150 @cindex @samp{I} in constraint
1151 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
1152 Other letters in the range @samp{I} through @samp{P} may be defined in
1153 a machine-dependent fashion to permit immediate integer operands with
1154 explicit integer values in specified ranges. For example, on the
1155 68000, @samp{I} is defined to stand for the range of values 1 to 8.
1156 This is the range permitted as a shift count in the shift
1159 @cindex @samp{E} in constraint
1161 An immediate floating operand (expression code @code{const_double}) is
1162 allowed, but only if the target floating point format is the same as
1163 that of the host machine (on which the compiler is running).
1165 @cindex @samp{F} in constraint
1167 An immediate floating operand (expression code @code{const_double} or
1168 @code{const_vector}) is allowed.
1170 @cindex @samp{G} in constraint
1171 @cindex @samp{H} in constraint
1172 @item @samp{G}, @samp{H}
1173 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
1174 permit immediate floating operands in particular ranges of values.
1176 @cindex @samp{s} in constraint
1178 An immediate integer operand whose value is not an explicit integer is
1181 This might appear strange; if an insn allows a constant operand with a
1182 value not known at compile time, it certainly must allow any known
1183 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
1184 better code to be generated.
1186 For example, on the 68000 in a fullword instruction it is possible to
1187 use an immediate operand; but if the immediate value is between @minus{}128
1188 and 127, better code results from loading the value into a register and
1189 using the register. This is because the load into the register can be
1190 done with a @samp{moveq} instruction. We arrange for this to happen
1191 by defining the letter @samp{K} to mean ``any integer outside the
1192 range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand
1195 @cindex @samp{g} in constraint
1197 Any register, memory or immediate integer operand is allowed, except for
1198 registers that are not general registers.
1200 @cindex @samp{X} in constraint
1203 Any operand whatsoever is allowed, even if it does not satisfy
1204 @code{general_operand}. This is normally used in the constraint of
1205 a @code{match_scratch} when certain alternatives will not actually
1206 require a scratch register.
1209 Any operand whatsoever is allowed.
1212 @cindex @samp{0} in constraint
1213 @cindex digits in constraint
1214 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
1215 An operand that matches the specified operand number is allowed. If a
1216 digit is used together with letters within the same alternative, the
1217 digit should come last.
1219 This number is allowed to be more than a single digit. If multiple
1220 digits are encountered consecutively, they are interpreted as a single
1221 decimal integer. There is scant chance for ambiguity, since to-date
1222 it has never been desirable that @samp{10} be interpreted as matching
1223 either operand 1 @emph{or} operand 0. Should this be desired, one
1224 can use multiple alternatives instead.
1226 @cindex matching constraint
1227 @cindex constraint, matching
1228 This is called a @dfn{matching constraint} and what it really means is
1229 that the assembler has only a single operand that fills two roles
1231 considered separate in the RTL insn. For example, an add insn has two
1232 input operands and one output operand in the RTL, but on most CISC
1235 which @code{asm} distinguishes. For example, an add instruction uses
1236 two input operands and an output operand, but on most CISC
1238 machines an add instruction really has only two operands, one of them an
1239 input-output operand:
1245 Matching constraints are used in these circumstances.
1246 More precisely, the two operands that match must include one input-only
1247 operand and one output-only operand. Moreover, the digit must be a
1248 smaller number than the number of the operand that uses it in the
1252 For operands to match in a particular case usually means that they
1253 are identical-looking RTL expressions. But in a few special cases
1254 specific kinds of dissimilarity are allowed. For example, @code{*x}
1255 as an input operand will match @code{*x++} as an output operand.
1256 For proper results in such cases, the output template should always
1257 use the output-operand's number when printing the operand.
1260 @cindex load address instruction
1261 @cindex push address instruction
1262 @cindex address constraints
1263 @cindex @samp{p} in constraint
1265 An operand that is a valid memory address is allowed. This is
1266 for ``load address'' and ``push address'' instructions.
1268 @findex address_operand
1269 @samp{p} in the constraint must be accompanied by @code{address_operand}
1270 as the predicate in the @code{match_operand}. This predicate interprets
1271 the mode specified in the @code{match_operand} as the mode of the memory
1272 reference for which the address would be valid.
1274 @cindex other register constraints
1275 @cindex extensible constraints
1276 @item @var{other-letters}
1277 Other letters can be defined in machine-dependent fashion to stand for
1278 particular classes of registers or other arbitrary operand types.
1279 @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
1280 for data, address and floating point registers.
1284 In order to have valid assembler code, each operand must satisfy
1285 its constraint. But a failure to do so does not prevent the pattern
1286 from applying to an insn. Instead, it directs the compiler to modify
1287 the code so that the constraint will be satisfied. Usually this is
1288 done by copying an operand into a register.
1290 Contrast, therefore, the two instruction patterns that follow:
1294 [(set (match_operand:SI 0 "general_operand" "=r")
1295 (plus:SI (match_dup 0)
1296 (match_operand:SI 1 "general_operand" "r")))]
1302 which has two operands, one of which must appear in two places, and
1306 [(set (match_operand:SI 0 "general_operand" "=r")
1307 (plus:SI (match_operand:SI 1 "general_operand" "0")
1308 (match_operand:SI 2 "general_operand" "r")))]
1314 which has three operands, two of which are required by a constraint to be
1315 identical. If we are considering an insn of the form
1318 (insn @var{n} @var{prev} @var{next}
1320 (plus:SI (reg:SI 6) (reg:SI 109)))
1325 the first pattern would not apply at all, because this insn does not
1326 contain two identical subexpressions in the right place. The pattern would
1327 say, ``That does not look like an add instruction; try other patterns''.
1328 The second pattern would say, ``Yes, that's an add instruction, but there
1329 is something wrong with it''. It would direct the reload pass of the
1330 compiler to generate additional insns to make the constraint true. The
1331 results might look like this:
1334 (insn @var{n2} @var{prev} @var{n}
1335 (set (reg:SI 3) (reg:SI 6))
1338 (insn @var{n} @var{n2} @var{next}
1340 (plus:SI (reg:SI 3) (reg:SI 109)))
1344 It is up to you to make sure that each operand, in each pattern, has
1345 constraints that can handle any RTL expression that could be present for
1346 that operand. (When multiple alternatives are in use, each pattern must,
1347 for each possible combination of operand expressions, have at least one
1348 alternative which can handle that combination of operands.) The
1349 constraints don't need to @emph{allow} any possible operand---when this is
1350 the case, they do not constrain---but they must at least point the way to
1351 reloading any possible operand so that it will fit.
1355 If the constraint accepts whatever operands the predicate permits,
1356 there is no problem: reloading is never necessary for this operand.
1358 For example, an operand whose constraints permit everything except
1359 registers is safe provided its predicate rejects registers.
1361 An operand whose predicate accepts only constant values is safe
1362 provided its constraints include the letter @samp{i}. If any possible
1363 constant value is accepted, then nothing less than @samp{i} will do;
1364 if the predicate is more selective, then the constraints may also be
1368 Any operand expression can be reloaded by copying it into a register.
1369 So if an operand's constraints allow some kind of register, it is
1370 certain to be safe. It need not permit all classes of registers; the
1371 compiler knows how to copy a register into another register of the
1372 proper class in order to make an instruction valid.
1374 @cindex nonoffsettable memory reference
1375 @cindex memory reference, nonoffsettable
1377 A nonoffsettable memory reference can be reloaded by copying the
1378 address into a register. So if the constraint uses the letter
1379 @samp{o}, all memory references are taken care of.
1382 A constant operand can be reloaded by allocating space in memory to
1383 hold it as preinitialized data. Then the memory reference can be used
1384 in place of the constant. So if the constraint uses the letters
1385 @samp{o} or @samp{m}, constant operands are not a problem.
1388 If the constraint permits a constant and a pseudo register used in an insn
1389 was not allocated to a hard register and is equivalent to a constant,
1390 the register will be replaced with the constant. If the predicate does
1391 not permit a constant and the insn is re-recognized for some reason, the
1392 compiler will crash. Thus the predicate must always recognize any
1393 objects allowed by the constraint.
1396 If the operand's predicate can recognize registers, but the constraint does
1397 not permit them, it can make the compiler crash. When this operand happens
1398 to be a register, the reload pass will be stymied, because it does not know
1399 how to copy a register temporarily into memory.
1401 If the predicate accepts a unary operator, the constraint applies to the
1402 operand. For example, the MIPS processor at ISA level 3 supports an
1403 instruction which adds two registers in @code{SImode} to produce a
1404 @code{DImode} result, but only if the registers are correctly sign
1405 extended. This predicate for the input operands accepts a
1406 @code{sign_extend} of an @code{SImode} register. Write the constraint
1407 to indicate the type of register that is required for the operand of the
1411 @node Multi-Alternative
1412 @subsection Multiple Alternative Constraints
1413 @cindex multiple alternative constraints
1415 Sometimes a single instruction has multiple alternative sets of possible
1416 operands. For example, on the 68000, a logical-or instruction can combine
1417 register or an immediate value into memory, or it can combine any kind of
1418 operand into a register; but it cannot combine one memory location into
1421 These constraints are represented as multiple alternatives. An alternative
1422 can be described by a series of letters for each operand. The overall
1423 constraint for an operand is made from the letters for this operand
1424 from the first alternative, a comma, the letters for this operand from
1425 the second alternative, a comma, and so on until the last alternative.
1427 Here is how it is done for fullword logical-or on the 68000:
1430 (define_insn "iorsi3"
1431 [(set (match_operand:SI 0 "general_operand" "=m,d")
1432 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1433 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1437 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1438 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1439 2. The second alternative has @samp{d} (data register) for operand 0,
1440 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1441 @samp{%} in the constraints apply to all the alternatives; their
1442 meaning is explained in the next section (@pxref{Class Preferences}).
1445 @c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL
1446 If all the operands fit any one alternative, the instruction is valid.
1447 Otherwise, for each alternative, the compiler counts how many instructions
1448 must be added to copy the operands so that that alternative applies.
1449 The alternative requiring the least copying is chosen. If two alternatives
1450 need the same amount of copying, the one that comes first is chosen.
1451 These choices can be altered with the @samp{?} and @samp{!} characters:
1454 @cindex @samp{?} in constraint
1455 @cindex question mark
1457 Disparage slightly the alternative that the @samp{?} appears in,
1458 as a choice when no alternative applies exactly. The compiler regards
1459 this alternative as one unit more costly for each @samp{?} that appears
1462 @cindex @samp{!} in constraint
1463 @cindex exclamation point
1465 Disparage severely the alternative that the @samp{!} appears in.
1466 This alternative can still be used if it fits without reloading,
1467 but if reloading is needed, some other alternative will be used.
1471 When an insn pattern has multiple alternatives in its constraints, often
1472 the appearance of the assembler code is determined mostly by which
1473 alternative was matched. When this is so, the C code for writing the
1474 assembler code can use the variable @code{which_alternative}, which is
1475 the ordinal number of the alternative that was actually satisfied (0 for
1476 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1480 @node Class Preferences
1481 @subsection Register Class Preferences
1482 @cindex class preference constraints
1483 @cindex register class preference constraints
1485 @cindex voting between constraint alternatives
1486 The operand constraints have another function: they enable the compiler
1487 to decide which kind of hardware register a pseudo register is best
1488 allocated to. The compiler examines the constraints that apply to the
1489 insns that use the pseudo register, looking for the machine-dependent
1490 letters such as @samp{d} and @samp{a} that specify classes of registers.
1491 The pseudo register is put in whichever class gets the most ``votes''.
1492 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1493 favor of a general register. The machine description says which registers
1494 are considered general.
1496 Of course, on some machines all registers are equivalent, and no register
1497 classes are defined. Then none of this complexity is relevant.
1501 @subsection Constraint Modifier Characters
1502 @cindex modifiers in constraints
1503 @cindex constraint modifier characters
1505 @c prevent bad page break with this line
1506 Here are constraint modifier characters.
1509 @cindex @samp{=} in constraint
1511 Means that this operand is write-only for this instruction: the previous
1512 value is discarded and replaced by output data.
1514 @cindex @samp{+} in constraint
1516 Means that this operand is both read and written by the instruction.
1518 When the compiler fixes up the operands to satisfy the constraints,
1519 it needs to know which operands are inputs to the instruction and
1520 which are outputs from it. @samp{=} identifies an output; @samp{+}
1521 identifies an operand that is both input and output; all other operands
1522 are assumed to be input only.
1524 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1525 first character of the constraint string.
1527 @cindex @samp{&} in constraint
1528 @cindex earlyclobber operand
1530 Means (in a particular alternative) that this operand is an
1531 @dfn{earlyclobber} operand, which is modified before the instruction is
1532 finished using the input operands. Therefore, this operand may not lie
1533 in a register that is used as an input operand or as part of any memory
1536 @samp{&} applies only to the alternative in which it is written. In
1537 constraints with multiple alternatives, sometimes one alternative
1538 requires @samp{&} while others do not. See, for example, the
1539 @samp{movdf} insn of the 68000.
1541 An input operand can be tied to an earlyclobber operand if its only
1542 use as an input occurs before the early result is written. Adding
1543 alternatives of this form often allows GCC to produce better code
1544 when only some of the inputs can be affected by the earlyclobber.
1545 See, for example, the @samp{mulsi3} insn of the ARM@.
1547 @samp{&} does not obviate the need to write @samp{=}.
1549 @cindex @samp{%} in constraint
1551 Declares the instruction to be commutative for this operand and the
1552 following operand. This means that the compiler may interchange the
1553 two operands if that is the cheapest way to make all operands fit the
1556 This is often used in patterns for addition instructions
1557 that really have only two operands: the result must go in one of the
1558 arguments. Here for example, is how the 68000 halfword-add
1559 instruction is defined:
1562 (define_insn "addhi3"
1563 [(set (match_operand:HI 0 "general_operand" "=m,r")
1564 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1565 (match_operand:HI 2 "general_operand" "di,g")))]
1569 GCC can only handle one commutative pair in an asm; if you use more,
1570 the compiler may fail. Note that you need not use the modifier if
1571 the two alternatives are strictly identical; this would only waste
1572 time in the reload pass. The modifier is not operational after
1573 register allocation, so the result of @code{define_peephole2}
1574 and @code{define_split}s performed after reload cannot rely on
1575 @samp{%} to make the intended insn match.
1577 @cindex @samp{#} in constraint
1579 Says that all following characters, up to the next comma, are to be
1580 ignored as a constraint. They are significant only for choosing
1581 register preferences.
1583 @cindex @samp{*} in constraint
1585 Says that the following character should be ignored when choosing
1586 register preferences. @samp{*} has no effect on the meaning of the
1587 constraint as a constraint, and no effect on reloading.
1590 Here is an example: the 68000 has an instruction to sign-extend a
1591 halfword in a data register, and can also sign-extend a value by
1592 copying it into an address register. While either kind of register is
1593 acceptable, the constraints on an address-register destination are
1594 less strict, so it is best if register allocation makes an address
1595 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1596 constraint letter (for data register) is ignored when computing
1597 register preferences.
1600 (define_insn "extendhisi2"
1601 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1603 (match_operand:HI 1 "general_operand" "0,g")))]
1609 @node Machine Constraints
1610 @subsection Constraints for Particular Machines
1611 @cindex machine specific constraints
1612 @cindex constraints, machine specific
1614 Whenever possible, you should use the general-purpose constraint letters
1615 in @code{asm} arguments, since they will convey meaning more readily to
1616 people reading your code. Failing that, use the constraint letters
1617 that usually have very similar meanings across architectures. The most
1618 commonly used constraints are @samp{m} and @samp{r} (for memory and
1619 general-purpose registers respectively; @pxref{Simple Constraints}), and
1620 @samp{I}, usually the letter indicating the most common
1621 immediate-constant format.
1623 Each architecture defines additional constraints. These constraints
1624 are used by the compiler itself for instruction generation, as well as
1625 for @code{asm} statements; therefore, some of the constraints are not
1626 particularly useful for @code{asm}. Here is a summary of some of the
1627 machine-dependent constraints available on some particular machines;
1628 it includes both constraints that are useful for @code{asm} and
1629 constraints that aren't. The compiler source file mentioned in the
1630 table heading for each architecture is the definitive reference for
1631 the meanings of that architecture's constraints.
1634 @item ARM family---@file{config/arm/arm.h}
1637 Floating-point register
1640 VFP floating-point register
1643 One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0
1647 Floating-point constant that would satisfy the constraint @samp{F} if it
1651 Integer that is valid as an immediate operand in a data processing
1652 instruction. That is, an integer in the range 0 to 255 rotated by a
1656 Integer in the range @minus{}4095 to 4095
1659 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1662 Integer that satisfies constraint @samp{I} when negated (twos complement)
1665 Integer in the range 0 to 32
1668 A memory reference where the exact address is in a single register
1669 (`@samp{m}' is preferable for @code{asm} statements)
1672 An item in the constant pool
1675 A symbol in the text segment of the current file
1678 A memory reference suitable for VFP load/store insns (reg+constant offset)
1681 A memory reference suitable for iWMMXt load/store instructions.
1684 A memory reference suitable for the ARMv4 ldrsb instruction.
1687 @item AVR family---@file{config/avr/constraints.md}
1690 Registers from r0 to r15
1693 Registers from r16 to r23
1696 Registers from r16 to r31
1699 Registers from r24 to r31. These registers can be used in @samp{adiw} command
1702 Pointer register (r26--r31)
1705 Base pointer register (r28--r31)
1708 Stack pointer register (SPH:SPL)
1711 Temporary register r0
1714 Register pair X (r27:r26)
1717 Register pair Y (r29:r28)
1720 Register pair Z (r31:r30)
1723 Constant greater than @minus{}1, less than 64
1726 Constant greater than @minus{}64, less than 1
1735 Constant that fits in 8 bits
1738 Constant integer @minus{}1
1741 Constant integer 8, 16, or 24
1747 A floating point constant 0.0
1750 Integer constant in the range -6 @dots{} 5.
1753 A memory address based on Y or Z pointer with displacement.
1756 @item CRX Architecture---@file{config/crx/crx.h}
1760 Registers from r0 to r14 (registers without stack pointer)
1763 Register r16 (64-bit accumulator lo register)
1766 Register r17 (64-bit accumulator hi register)
1769 Register pair r16-r17. (64-bit accumulator lo-hi pair)
1772 Constant that fits in 3 bits
1775 Constant that fits in 4 bits
1778 Constant that fits in 5 bits
1781 Constant that is one of -1, 4, -4, 7, 8, 12, 16, 20, 32, 48
1784 Floating point constant that is legal for store immediate
1787 @item Hewlett-Packard PA-RISC---@file{config/pa/pa.h}
1793 Floating point register
1796 Shift amount register
1799 Floating point register (deprecated)
1802 Upper floating point register (32-bit), floating point register (64-bit)
1808 Signed 11-bit integer constant
1811 Signed 14-bit integer constant
1814 Integer constant that can be deposited with a @code{zdepi} instruction
1817 Signed 5-bit integer constant
1823 Integer constant that can be loaded with a @code{ldil} instruction
1826 Integer constant whose value plus one is a power of 2
1829 Integer constant that can be used for @code{and} operations in @code{depi}
1830 and @code{extru} instructions
1839 Floating-point constant 0.0
1842 A @code{lo_sum} data-linkage-table memory operand
1845 A memory operand that can be used as the destination operand of an
1846 integer store instruction
1849 A scaled or unscaled indexed memory operand
1852 A memory operand for floating-point loads and stores
1855 A register indirect memory operand
1858 @item picoChip family---@file{picochip.h}
1864 Pointer register. A register which can be used to access memory without
1865 supplying an offset. Any other register can be used to access memory,
1866 but will need a constant offset. In the case of the offset being zero,
1867 it is more efficient to use a pointer register, since this reduces code
1871 A twin register. A register which may be paired with an adjacent
1872 register to create a 32-bit register.
1875 Any absolute memory address (e.g., symbolic constant, symbolic
1879 4-bit signed integer.
1882 4-bit unsigned integer.
1885 8-bit signed integer.
1888 Any constant whose absolute value is no greater than 4-bits.
1891 10-bit signed integer
1894 16-bit signed integer.
1898 @item PowerPC and IBM RS6000---@file{config/rs6000/rs6000.h}
1901 Address base register
1904 Floating point register
1910 @samp{MQ}, @samp{CTR}, or @samp{LINK} register
1919 @samp{LINK} register
1922 @samp{CR} register (condition register) number 0
1925 @samp{CR} register (condition register)
1928 @samp{FPMEM} stack memory for FPR-GPR transfers
1931 Signed 16-bit constant
1934 Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for
1935 @code{SImode} constants)
1938 Unsigned 16-bit constant
1941 Signed 16-bit constant shifted left 16 bits
1944 Constant larger than 31
1953 Constant whose negation is a signed 16-bit constant
1956 Floating point constant that can be loaded into a register with one
1957 instruction per word
1960 Integer/Floating point constant that can be loaded into a register using
1964 Memory operand that is an offset from a register (@samp{m} is preferable
1965 for @code{asm} statements)
1968 Memory operand that is an indexed or indirect from a register (@samp{m} is
1969 preferable for @code{asm} statements)
1975 Address operand that is an indexed or indirect from a register (@samp{p} is
1976 preferable for @code{asm} statements)
1979 Constant suitable as a 64-bit mask operand
1982 Constant suitable as a 32-bit mask operand
1985 System V Release 4 small data area reference
1988 AND masks that can be performed by two rldic@{l, r@} instructions
1991 Vector constant that does not require memory
1995 @item Intel 386---@file{config/i386/constraints.md}
1998 Legacy register---the eight integer registers available on all
1999 i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
2000 @code{si}, @code{di}, @code{bp}, @code{sp}).
2003 Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a},
2004 @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.
2007 Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
2008 @code{c}, and @code{d}.
2012 Any register that can be used as the index in a base+index memory
2013 access: that is, any general register except the stack pointer.
2017 The @code{a} register.
2020 The @code{b} register.
2023 The @code{c} register.
2026 The @code{d} register.
2029 The @code{si} register.
2032 The @code{di} register.
2035 The @code{a} and @code{d} registers, as a pair (for instructions that
2036 return half the result in one and half in the other).
2039 Any 80387 floating-point (stack) register.
2042 Top of 80387 floating-point stack (@code{%st(0)}).
2045 Second from top of 80387 floating-point stack (@code{%st(1)}).
2059 Integer constant in the range 0 @dots{} 31, for 32-bit shifts.
2062 Integer constant in the range 0 @dots{} 63, for 64-bit shifts.
2065 Signed 8-bit integer constant.
2068 @code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move.
2071 0, 1, 2, or 3 (shifts for the @code{lea} instruction).
2074 Unsigned 8-bit integer constant (for @code{in} and @code{out}
2079 Integer constant in the range 0 @dots{} 127, for 128-bit shifts.
2083 Standard 80387 floating point constant.
2086 Standard SSE floating point constant.
2089 32-bit signed integer constant, or a symbolic reference known
2090 to fit that range (for immediate operands in sign-extending x86-64
2094 32-bit unsigned integer constant, or a symbolic reference known
2095 to fit that range (for immediate operands in zero-extending x86-64
2100 @item Intel IA-64---@file{config/ia64/ia64.h}
2103 General register @code{r0} to @code{r3} for @code{addl} instruction
2109 Predicate register (@samp{c} as in ``conditional'')
2112 Application register residing in M-unit
2115 Application register residing in I-unit
2118 Floating-point register
2122 Remember that @samp{m} allows postincrement and postdecrement which
2123 require printing with @samp{%Pn} on IA-64.
2124 Use @samp{S} to disallow postincrement and postdecrement.
2127 Floating-point constant 0.0 or 1.0
2130 14-bit signed integer constant
2133 22-bit signed integer constant
2136 8-bit signed integer constant for logical instructions
2139 8-bit adjusted signed integer constant for compare pseudo-ops
2142 6-bit unsigned integer constant for shift counts
2145 9-bit signed integer constant for load and store postincrements
2151 0 or @minus{}1 for @code{dep} instruction
2154 Non-volatile memory for floating-point loads and stores
2157 Integer constant in the range 1 to 4 for @code{shladd} instruction
2160 Memory operand except postincrement and postdecrement
2163 @item FRV---@file{config/frv/frv.h}
2166 Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}).
2169 Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}).
2172 Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and
2173 @code{icc0} to @code{icc3}).
2176 Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}).
2179 Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}).
2180 Odd registers are excluded not in the class but through the use of a machine
2181 mode larger than 4 bytes.
2184 Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}).
2187 Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}).
2188 Odd registers are excluded not in the class but through the use of a machine
2189 mode larger than 4 bytes.
2192 Register in the class @code{LR_REG} (the @code{lr} register).
2195 Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}).
2196 Register numbers not divisible by 4 are excluded not in the class but through
2197 the use of a machine mode larger than 8 bytes.
2200 Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}).
2203 Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}).
2206 Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}).
2209 Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}).
2212 Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}).
2213 Register numbers not divisible by 4 are excluded not in the class but through
2214 the use of a machine mode larger than 8 bytes.
2217 Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}).
2220 Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}).
2223 Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}).
2226 Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}).
2229 Floating point constant zero
2232 6-bit signed integer constant
2235 10-bit signed integer constant
2238 16-bit signed integer constant
2241 16-bit unsigned integer constant
2244 12-bit signed integer constant that is negative---i.e.@: in the
2245 range of @minus{}2048 to @minus{}1
2251 12-bit signed integer constant that is greater than zero---i.e.@: in the
2256 @item Blackfin family---@file{config/bfin/constraints.md}
2265 A call clobbered P register.
2268 A single register. If @var{n} is in the range 0 to 7, the corresponding D
2269 register. If it is @code{A}, then the register P0.
2272 Even-numbered D register
2275 Odd-numbered D register
2278 Accumulator register.
2281 Even-numbered accumulator register.
2284 Odd-numbered accumulator register.
2296 Registers used for circular buffering, i.e. I, B, or L registers.
2311 Any D, P, B, M, I or L register.
2314 Additional registers typically used only in prologues and epilogues: RETS,
2315 RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.
2318 Any register except accumulators or CC.
2321 Signed 16 bit integer (in the range -32768 to 32767)
2324 Unsigned 16 bit integer (in the range 0 to 65535)
2327 Signed 7 bit integer (in the range -64 to 63)
2330 Unsigned 7 bit integer (in the range 0 to 127)
2333 Unsigned 5 bit integer (in the range 0 to 31)
2336 Signed 4 bit integer (in the range -8 to 7)
2339 Signed 3 bit integer (in the range -3 to 4)
2342 Unsigned 3 bit integer (in the range 0 to 7)
2345 Constant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4.
2348 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2349 use with either accumulator.
2352 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2353 use only with accumulator A1.
2362 An integer constant with exactly a single bit set.
2365 An integer constant with all bits set except exactly one.
2373 @item M32C---@file{config/m32c/m32c.c}
2378 @samp{$sp}, @samp{$fb}, @samp{$sb}.
2381 Any control register, when they're 16 bits wide (nothing if control
2382 registers are 24 bits wide)
2385 Any control register, when they're 24 bits wide.
2394 $r0 or $r2, or $r2r0 for 32 bit values.
2397 $r1 or $r3, or $r3r1 for 32 bit values.
2400 A register that can hold a 64 bit value.
2403 $r0 or $r1 (registers with addressable high/low bytes)
2412 Address registers when they're 16 bits wide.
2415 Address registers when they're 24 bits wide.
2418 Registers that can hold QI values.
2421 Registers that can be used with displacements ($a0, $a1, $sb).
2424 Registers that can hold 32 bit values.
2427 Registers that can hold 16 bit values.
2430 Registers chat can hold 16 bit values, including all control
2434 $r0 through R1, plus $a0 and $a1.
2440 The memory-based pseudo-registers $mem0 through $mem15.
2443 Registers that can hold pointers (16 bit registers for r8c, m16c; 24
2444 bit registers for m32cm, m32c).
2447 Matches multiple registers in a PARALLEL to form a larger register.
2448 Used to match function return values.
2457 -32768 @dots{} 32767
2463 -8 @dots{} -1 or 1 @dots{} 8
2466 -16 @dots{} -1 or 1 @dots{} 16
2469 -32 @dots{} -1 or 1 @dots{} 32
2475 An 8 bit value with exactly one bit set.
2478 A 16 bit value with exactly one bit set.
2481 The common src/dest memory addressing modes.
2484 Memory addressed using $a0 or $a1.
2487 Memory addressed with immediate addresses.
2490 Memory addressed using the stack pointer ($sp).
2493 Memory addressed using the frame base register ($fb).
2496 Memory addressed using the small base register ($sb).
2502 @item MIPS---@file{config/mips/constraints.md}
2505 An address register. This is equivalent to @code{r} unless
2506 generating MIPS16 code.
2509 A floating-point register (if available).
2512 Formerly the @code{hi} register. This constraint is no longer supported.
2515 The @code{lo} register. Use this register to store values that are
2516 no bigger than a word.
2519 The concatenated @code{hi} and @code{lo} registers. Use this register
2520 to store doubleword values.
2523 A register suitable for use in an indirect jump. This will always be
2524 @code{$25} for @option{-mabicalls}.
2527 Register @code{$3}. Do not use this constraint in new code;
2528 it is retained only for compatibility with glibc.
2531 Equivalent to @code{r}; retained for backwards compatibility.
2534 A floating-point condition code register.
2537 A signed 16-bit constant (for arithmetic instructions).
2543 An unsigned 16-bit constant (for logic instructions).
2546 A signed 32-bit constant in which the lower 16 bits are zero.
2547 Such constants can be loaded using @code{lui}.
2550 A constant that cannot be loaded using @code{lui}, @code{addiu}
2554 A constant in the range -65535 to -1 (inclusive).
2557 A signed 15-bit constant.
2560 A constant in the range 1 to 65535 (inclusive).
2563 Floating-point zero.
2566 An address that can be used in a non-macro load or store.
2569 @item Motorola 680x0---@file{config/m68k/constraints.md}
2578 68881 floating-point register, if available
2581 Integer in the range 1 to 8
2584 16-bit signed number
2587 Signed number whose magnitude is greater than 0x80
2590 Integer in the range @minus{}8 to @minus{}1
2593 Signed number whose magnitude is greater than 0x100
2596 Range 24 to 31, rotatert:SI 8 to 1 expressed as rotate
2599 16 (for rotate using swap)
2602 Range 8 to 15, rotatert:HI 8 to 1 expressed as rotate
2605 Numbers that mov3q can handle
2608 Floating point constant that is not a 68881 constant
2611 Operands that satisfy 'm' when -mpcrel is in effect
2614 Operands that satisfy 's' when -mpcrel is not in effect
2617 Address register indirect addressing mode
2620 Register offset addressing
2635 Range of signed numbers that don't fit in 16 bits
2638 Integers valid for mvq
2641 Integers valid for a moveq followed by a swap
2644 Integers valid for mvz
2647 Integers valid for mvs
2653 Non-register operands allowed in clr
2657 @item Motorola 68HC11 & 68HC12 families---@file{config/m68hc11/m68hc11.h}
2672 Temporary soft register _.tmp
2675 A soft register _.d1 to _.d31
2678 Stack pointer register
2687 Pseudo register `z' (replaced by `x' or `y' at the end)
2690 An address register: x, y or z
2693 An address register: x or y
2696 Register pair (x:d) to form a 32-bit value
2699 Constants in the range @minus{}65536 to 65535
2702 Constants whose 16-bit low part is zero
2705 Constant integer 1 or @minus{}1
2711 Constants in the range @minus{}8 to 2
2716 @item SPARC---@file{config/sparc/sparc.h}
2719 Floating-point register on the SPARC-V8 architecture and
2720 lower floating-point register on the SPARC-V9 architecture.
2723 Floating-point register. It is equivalent to @samp{f} on the
2724 SPARC-V8 architecture and contains both lower and upper
2725 floating-point registers on the SPARC-V9 architecture.
2728 Floating-point condition code register.
2731 Lower floating-point register. It is only valid on the SPARC-V9
2732 architecture when the Visual Instruction Set is available.
2735 Floating-point register. It is only valid on the SPARC-V9 architecture
2736 when the Visual Instruction Set is available.
2739 64-bit global or out register for the SPARC-V8+ architecture.
2745 Signed 13-bit constant
2751 32-bit constant with the low 12 bits clear (a constant that can be
2752 loaded with the @code{sethi} instruction)
2755 A constant in the range supported by @code{movcc} instructions
2758 A constant in the range supported by @code{movrcc} instructions
2761 Same as @samp{K}, except that it verifies that bits that are not in the
2762 lower 32-bit range are all zero. Must be used instead of @samp{K} for
2763 modes wider than @code{SImode}
2772 Signed 13-bit constant, sign-extended to 32 or 64 bits
2775 Floating-point constant whose integral representation can
2776 be moved into an integer register using a single sethi
2780 Floating-point constant whose integral representation can
2781 be moved into an integer register using a single mov
2785 Floating-point constant whose integral representation can
2786 be moved into an integer register using a high/lo_sum
2787 instruction sequence
2790 Memory address aligned to an 8-byte boundary
2796 Memory address for @samp{e} constraint registers
2803 @item SPU---@file{config/spu/spu.h}
2806 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value.
2809 An immediate for and/xor/or instructions. const_int is treated as a 64 bit value.
2812 An immediate for the @code{iohl} instruction. const_int is treated as a 64 bit value.
2815 An immediate which can be loaded with @code{fsmbi}.
2818 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value.
2821 An immediate for most arithmetic instructions. const_int is treated as a 32 bit value.
2824 An immediate for and/xor/or instructions. const_int is treated as a 32 bit value.
2827 An immediate for the @code{iohl} instruction. const_int is treated as a 32 bit value.
2830 A constant in the range [-64, 63] for shift/rotate instructions.
2833 An unsigned 7-bit constant for conversion/nop/channel instructions.
2836 A signed 10-bit constant for most arithmetic instructions.
2839 A signed 16 bit immediate for @code{stop}.
2842 An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}.
2845 An unsigned 7-bit constant whose 3 least significant bits are 0.
2848 An unsigned 3-bit constant for 16-byte rotates and shifts
2851 Call operand, reg, for indirect calls
2854 Call operand, symbol, for relative calls.
2857 Call operand, const_int, for absolute calls.
2860 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit.
2863 An immediate for shift and rotate instructions. const_int is treated as a 32 bit value.
2866 An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit.
2869 An immediate for the @code{iohl} instruction. const_int is sign extended to 128 bit.
2873 @item S/390 and zSeries---@file{config/s390/s390.h}
2876 Address register (general purpose register except r0)
2879 Condition code register
2882 Data register (arbitrary general purpose register)
2885 Floating-point register
2888 Unsigned 8-bit constant (0--255)
2891 Unsigned 12-bit constant (0--4095)
2894 Signed 16-bit constant (@minus{}32768--32767)
2897 Value appropriate as displacement.
2900 for short displacement
2901 @item (-524288..524287)
2902 for long displacement
2906 Constant integer with a value of 0x7fffffff.
2909 Multiple letter constraint followed by 4 parameter letters.
2912 number of the part counting from most to least significant
2916 mode of the containing operand
2918 value of the other parts (F---all bits set)
2920 The constraint matches if the specified part of a constant
2921 has a value different from its other parts.
2924 Memory reference without index register and with short displacement.
2927 Memory reference with index register and short displacement.
2930 Memory reference without index register but with long displacement.
2933 Memory reference with index register and long displacement.
2936 Pointer with short displacement.
2939 Pointer with long displacement.
2942 Shift count operand.
2946 @item Score family---@file{config/score/score.h}
2949 Registers from r0 to r32.
2952 Registers from r0 to r16.
2955 r8---r11 or r22---r27 registers.
2976 cnt + lcb + scb register.
2979 cr0---cr15 register.
2991 cp1 + cp2 + cp3 registers.
2994 High 16-bit constant (32-bit constant with 16 LSBs zero).
2997 Unsigned 5 bit integer (in the range 0 to 31).
3000 Unsigned 16 bit integer (in the range 0 to 65535).
3003 Signed 16 bit integer (in the range @minus{}32768 to 32767).
3006 Unsigned 14 bit integer (in the range 0 to 16383).
3009 Signed 14 bit integer (in the range @minus{}8192 to 8191).
3015 @item Xstormy16---@file{config/stormy16/stormy16.h}
3030 Registers r0 through r7.
3033 Registers r0 and r1.
3039 Registers r8 and r9.
3042 A constant between 0 and 3 inclusive.
3045 A constant that has exactly one bit set.
3048 A constant that has exactly one bit clear.
3051 A constant between 0 and 255 inclusive.
3054 A constant between @minus{}255 and 0 inclusive.
3057 A constant between @minus{}3 and 0 inclusive.
3060 A constant between 1 and 4 inclusive.
3063 A constant between @minus{}4 and @minus{}1 inclusive.
3066 A memory reference that is a stack push.
3069 A memory reference that is a stack pop.
3072 A memory reference that refers to a constant address of known value.
3075 The register indicated by Rx (not implemented yet).
3078 A constant that is not between 2 and 15 inclusive.
3085 @item Xtensa---@file{config/xtensa/constraints.md}
3088 General-purpose 32-bit register
3091 One-bit boolean register
3094 MAC16 40-bit accumulator register
3097 Signed 12-bit integer constant, for use in MOVI instructions
3100 Signed 8-bit integer constant, for use in ADDI instructions
3103 Integer constant valid for BccI instructions
3106 Unsigned constant valid for BccUI instructions
3113 @node Disable Insn Alternatives
3114 @subsection Disable insn alternatives using the @code{enabled} attribute
3117 The @code{enabled} insn attribute may be used to disable certain insn
3118 alternatives for machine-specific reasons. This is useful when adding
3119 new instructions to an existing pattern which are only available for
3120 certain cpu architecture levels as specified with the @code{-march=}
3123 If an insn alternative is disabled, then it will never be used. The
3124 compiler treats the constraints for the disabled alternative as
3127 In order to make use of the @code{enabled} attribute a back end has to add
3128 in the machine description files:
3132 A definition of the @code{enabled} insn attribute. The attribute is
3133 defined as usual using the @code{define_attr} command. This
3134 definition should be based on other insn attributes and/or target flags.
3135 The @code{enabled} attribute is a numeric attribute and should evaluate to
3136 @code{(const_int 1)} for an enabled alternative and to
3137 @code{(const_int 0)} otherwise.
3139 A definition of another insn attribute used to describe for what
3140 reason an insn alternative might be available or
3141 not. E.g. @code{cpu_facility} as in the example below.
3143 An assignement for the second attribute to each insn definition
3144 combining instructions which are not all available under the same
3145 circumstances. (Note: It obviously only makes sense for definitions
3146 with more than one alternative. Otherwise the insn pattern should be
3147 disabled or enabled using the insn condition.)
3150 E.g. the following two patterns could easily be merged using the @code{enabled}
3155 (define_insn "*movdi_old"
3156 [(set (match_operand:DI 0 "register_operand" "=d")
3157 (match_operand:DI 1 "register_operand" " d"))]
3161 (define_insn "*movdi_new"
3162 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
3163 (match_operand:DI 1 "register_operand" " d,d,f"))]
3176 (define_insn "*movdi_combined"
3177 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
3178 (match_operand:DI 1 "register_operand" " d,d,f"))]
3184 [(set_attr "cpu_facility" "*,new,new")])
3188 with the @code{enabled} attribute defined like this:
3192 (define_attr "cpu_facility" "standard,new" (const_string "standard"))
3194 (define_attr "enabled" ""
3195 (cond [(eq_attr "cpu_facility" "standard") (const_int 1)
3196 (and (eq_attr "cpu_facility" "new")
3197 (ne (symbol_ref "TARGET_NEW") (const_int 0)))
3206 @node Define Constraints
3207 @subsection Defining Machine-Specific Constraints
3208 @cindex defining constraints
3209 @cindex constraints, defining
3211 Machine-specific constraints fall into two categories: register and
3212 non-register constraints. Within the latter category, constraints
3213 which allow subsets of all possible memory or address operands should
3214 be specially marked, to give @code{reload} more information.
3216 Machine-specific constraints can be given names of arbitrary length,
3217 but they must be entirely composed of letters, digits, underscores
3218 (@samp{_}), and angle brackets (@samp{< >}). Like C identifiers, they
3219 must begin with a letter or underscore.
3221 In order to avoid ambiguity in operand constraint strings, no
3222 constraint can have a name that begins with any other constraint's
3223 name. For example, if @code{x} is defined as a constraint name,
3224 @code{xy} may not be, and vice versa. As a consequence of this rule,
3225 no constraint may begin with one of the generic constraint letters:
3226 @samp{E F V X g i m n o p r s}.
3228 Register constraints correspond directly to register classes.
3229 @xref{Register Classes}. There is thus not much flexibility in their
3232 @deffn {MD Expression} define_register_constraint name regclass docstring
3233 All three arguments are string constants.
3234 @var{name} is the name of the constraint, as it will appear in
3235 @code{match_operand} expressions. If @var{name} is a multi-letter
3236 constraint its length shall be the same for all constraints starting
3237 with the same letter. @var{regclass} can be either the
3238 name of the corresponding register class (@pxref{Register Classes}),
3239 or a C expression which evaluates to the appropriate register class.
3240 If it is an expression, it must have no side effects, and it cannot
3241 look at the operand. The usual use of expressions is to map some
3242 register constraints to @code{NO_REGS} when the register class
3243 is not available on a given subarchitecture.
3245 @var{docstring} is a sentence documenting the meaning of the
3246 constraint. Docstrings are explained further below.
3249 Non-register constraints are more like predicates: the constraint
3250 definition gives a Boolean expression which indicates whether the
3253 @deffn {MD Expression} define_constraint name docstring exp
3254 The @var{name} and @var{docstring} arguments are the same as for
3255 @code{define_register_constraint}, but note that the docstring comes
3256 immediately after the name for these expressions. @var{exp} is an RTL
3257 expression, obeying the same rules as the RTL expressions in predicate
3258 definitions. @xref{Defining Predicates}, for details. If it
3259 evaluates true, the constraint matches; if it evaluates false, it
3260 doesn't. Constraint expressions should indicate which RTL codes they
3261 might match, just like predicate expressions.
3263 @code{match_test} C expressions have access to the
3264 following variables:
3268 The RTL object defining the operand.
3270 The machine mode of @var{op}.
3272 @samp{INTVAL (@var{op})}, if @var{op} is a @code{const_int}.
3274 @samp{CONST_DOUBLE_HIGH (@var{op})}, if @var{op} is an integer
3275 @code{const_double}.
3277 @samp{CONST_DOUBLE_LOW (@var{op})}, if @var{op} is an integer
3278 @code{const_double}.
3280 @samp{CONST_DOUBLE_REAL_VALUE (@var{op})}, if @var{op} is a floating-point
3281 @code{const_double}.
3284 The @var{*val} variables should only be used once another piece of the
3285 expression has verified that @var{op} is the appropriate kind of RTL
3289 Most non-register constraints should be defined with
3290 @code{define_constraint}. The remaining two definition expressions
3291 are only appropriate for constraints that should be handled specially
3292 by @code{reload} if they fail to match.
3294 @deffn {MD Expression} define_memory_constraint name docstring exp
3295 Use this expression for constraints that match a subset of all memory
3296 operands: that is, @code{reload} can make them match by converting the
3297 operand to the form @samp{@w{(mem (reg @var{X}))}}, where @var{X} is a
3298 base register (from the register class specified by
3299 @code{BASE_REG_CLASS}, @pxref{Register Classes}).
3301 For example, on the S/390, some instructions do not accept arbitrary
3302 memory references, but only those that do not make use of an index
3303 register. The constraint letter @samp{Q} is defined to represent a
3304 memory address of this type. If @samp{Q} is defined with
3305 @code{define_memory_constraint}, a @samp{Q} constraint can handle any
3306 memory operand, because @code{reload} knows it can simply copy the
3307 memory address into a base register if required. This is analogous to
3308 the way a @samp{o} constraint can handle any memory operand.
3310 The syntax and semantics are otherwise identical to
3311 @code{define_constraint}.
3314 @deffn {MD Expression} define_address_constraint name docstring exp
3315 Use this expression for constraints that match a subset of all address
3316 operands: that is, @code{reload} can make the constraint match by
3317 converting the operand to the form @samp{@w{(reg @var{X})}}, again
3318 with @var{X} a base register.
3320 Constraints defined with @code{define_address_constraint} can only be
3321 used with the @code{address_operand} predicate, or machine-specific
3322 predicates that work the same way. They are treated analogously to
3323 the generic @samp{p} constraint.
3325 The syntax and semantics are otherwise identical to
3326 @code{define_constraint}.
3329 For historical reasons, names beginning with the letters @samp{G H}
3330 are reserved for constraints that match only @code{const_double}s, and
3331 names beginning with the letters @samp{I J K L M N O P} are reserved
3332 for constraints that match only @code{const_int}s. This may change in
3333 the future. For the time being, constraints with these names must be
3334 written in a stylized form, so that @code{genpreds} can tell you did
3339 (define_constraint "[@var{GHIJKLMNOP}]@dots{}"
3341 (and (match_code "const_int") ; @r{@code{const_double} for G/H}
3342 @var{condition}@dots{})) ; @r{usually a @code{match_test}}
3345 @c the semicolons line up in the formatted manual
3347 It is fine to use names beginning with other letters for constraints
3348 that match @code{const_double}s or @code{const_int}s.
3350 Each docstring in a constraint definition should be one or more complete
3351 sentences, marked up in Texinfo format. @emph{They are currently unused.}
3352 In the future they will be copied into the GCC manual, in @ref{Machine
3353 Constraints}, replacing the hand-maintained tables currently found in
3354 that section. Also, in the future the compiler may use this to give
3355 more helpful diagnostics when poor choice of @code{asm} constraints
3356 causes a reload failure.
3358 If you put the pseudo-Texinfo directive @samp{@@internal} at the
3359 beginning of a docstring, then (in the future) it will appear only in
3360 the internals manual's version of the machine-specific constraint tables.
3361 Use this for constraints that should not appear in @code{asm} statements.
3363 @node C Constraint Interface
3364 @subsection Testing constraints from C
3365 @cindex testing constraints
3366 @cindex constraints, testing
3368 It is occasionally useful to test a constraint from C code rather than
3369 implicitly via the constraint string in a @code{match_operand}. The
3370 generated file @file{tm_p.h} declares a few interfaces for working
3371 with machine-specific constraints. None of these interfaces work with
3372 the generic constraints described in @ref{Simple Constraints}. This
3373 may change in the future.
3375 @strong{Warning:} @file{tm_p.h} may declare other functions that
3376 operate on constraints, besides the ones documented here. Do not use
3377 those functions from machine-dependent code. They exist to implement
3378 the old constraint interface that machine-independent components of
3379 the compiler still expect. They will change or disappear in the
3382 Some valid constraint names are not valid C identifiers, so there is a
3383 mangling scheme for referring to them from C@. Constraint names that
3384 do not contain angle brackets or underscores are left unchanged.
3385 Underscores are doubled, each @samp{<} is replaced with @samp{_l}, and
3386 each @samp{>} with @samp{_g}. Here are some examples:
3388 @c the @c's prevent double blank lines in the printed manual.
3390 @multitable {Original} {Mangled}
3391 @item @strong{Original} @tab @strong{Mangled} @c
3392 @item @code{x} @tab @code{x} @c
3393 @item @code{P42x} @tab @code{P42x} @c
3394 @item @code{P4_x} @tab @code{P4__x} @c
3395 @item @code{P4>x} @tab @code{P4_gx} @c
3396 @item @code{P4>>} @tab @code{P4_g_g} @c
3397 @item @code{P4_g>} @tab @code{P4__g_g} @c
3401 Throughout this section, the variable @var{c} is either a constraint
3402 in the abstract sense, or a constant from @code{enum constraint_num};
3403 the variable @var{m} is a mangled constraint name (usually as part of
3404 a larger identifier).
3406 @deftp Enum constraint_num
3407 For each machine-specific constraint, there is a corresponding
3408 enumeration constant: @samp{CONSTRAINT_} plus the mangled name of the
3409 constraint. Functions that take an @code{enum constraint_num} as an
3410 argument expect one of these constants.
3412 Machine-independent constraints do not have associated constants.
3413 This may change in the future.
3416 @deftypefun {inline bool} satisfies_constraint_@var{m} (rtx @var{exp})
3417 For each machine-specific, non-register constraint @var{m}, there is
3418 one of these functions; it returns @code{true} if @var{exp} satisfies the
3419 constraint. These functions are only visible if @file{rtl.h} was included
3420 before @file{tm_p.h}.
3423 @deftypefun bool constraint_satisfied_p (rtx @var{exp}, enum constraint_num @var{c})
3424 Like the @code{satisfies_constraint_@var{m}} functions, but the
3425 constraint to test is given as an argument, @var{c}. If @var{c}
3426 specifies a register constraint, this function will always return
3430 @deftypefun {enum reg_class} regclass_for_constraint (enum constraint_num @var{c})
3431 Returns the register class associated with @var{c}. If @var{c} is not
3432 a register constraint, or those registers are not available for the
3433 currently selected subtarget, returns @code{NO_REGS}.
3436 Here is an example use of @code{satisfies_constraint_@var{m}}. In
3437 peephole optimizations (@pxref{Peephole Definitions}), operand
3438 constraint strings are ignored, so if there are relevant constraints,
3439 they must be tested in the C condition. In the example, the
3440 optimization is applied if operand 2 does @emph{not} satisfy the
3441 @samp{K} constraint. (This is a simplified version of a peephole
3442 definition from the i386 machine description.)
3446 [(match_scratch:SI 3 "r")
3447 (set (match_operand:SI 0 "register_operand" "")
3448 (mult:SI (match_operand:SI 1 "memory_operand" "")
3449 (match_operand:SI 2 "immediate_operand" "")))]
3451 "!satisfies_constraint_K (operands[2])"
3453 [(set (match_dup 3) (match_dup 1))
3454 (set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))]
3459 @node Standard Names
3460 @section Standard Pattern Names For Generation
3461 @cindex standard pattern names
3462 @cindex pattern names
3463 @cindex names, pattern
3465 Here is a table of the instruction names that are meaningful in the RTL
3466 generation pass of the compiler. Giving one of these names to an
3467 instruction pattern tells the RTL generation pass that it can use the
3468 pattern to accomplish a certain task.
3471 @cindex @code{mov@var{m}} instruction pattern
3472 @item @samp{mov@var{m}}
3473 Here @var{m} stands for a two-letter machine mode name, in lowercase.
3474 This instruction pattern moves data with that machine mode from operand
3475 1 to operand 0. For example, @samp{movsi} moves full-word data.
3477 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
3478 own mode is wider than @var{m}, the effect of this instruction is
3479 to store the specified value in the part of the register that corresponds
3480 to mode @var{m}. Bits outside of @var{m}, but which are within the
3481 same target word as the @code{subreg} are undefined. Bits which are
3482 outside the target word are left unchanged.
3484 This class of patterns is special in several ways. First of all, each
3485 of these names up to and including full word size @emph{must} be defined,
3486 because there is no other way to copy a datum from one place to another.
3487 If there are patterns accepting operands in larger modes,
3488 @samp{mov@var{m}} must be defined for integer modes of those sizes.
3490 Second, these patterns are not used solely in the RTL generation pass.
3491 Even the reload pass can generate move insns to copy values from stack
3492 slots into temporary registers. When it does so, one of the operands is
3493 a hard register and the other is an operand that can need to be reloaded
3497 Therefore, when given such a pair of operands, the pattern must generate
3498 RTL which needs no reloading and needs no temporary registers---no
3499 registers other than the operands. For example, if you support the
3500 pattern with a @code{define_expand}, then in such a case the
3501 @code{define_expand} mustn't call @code{force_reg} or any other such
3502 function which might generate new pseudo registers.
3504 This requirement exists even for subword modes on a RISC machine where
3505 fetching those modes from memory normally requires several insns and
3506 some temporary registers.
3508 @findex change_address
3509 During reload a memory reference with an invalid address may be passed
3510 as an operand. Such an address will be replaced with a valid address
3511 later in the reload pass. In this case, nothing may be done with the
3512 address except to use it as it stands. If it is copied, it will not be
3513 replaced with a valid address. No attempt should be made to make such
3514 an address into a valid address and no routine (such as
3515 @code{change_address}) that will do so may be called. Note that
3516 @code{general_operand} will fail when applied to such an address.
3518 @findex reload_in_progress
3519 The global variable @code{reload_in_progress} (which must be explicitly
3520 declared if required) can be used to determine whether such special
3521 handling is required.
3523 The variety of operands that have reloads depends on the rest of the
3524 machine description, but typically on a RISC machine these can only be
3525 pseudo registers that did not get hard registers, while on other
3526 machines explicit memory references will get optional reloads.
3528 If a scratch register is required to move an object to or from memory,
3529 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
3531 If there are cases which need scratch registers during or after reload,
3532 you must provide an appropriate secondary_reload target hook.
3534 @findex can_create_pseudo_p
3535 The macro @code{can_create_pseudo_p} can be used to determine if it
3536 is unsafe to create new pseudo registers. If this variable is nonzero, then
3537 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
3539 The constraints on a @samp{mov@var{m}} must permit moving any hard
3540 register to any other hard register provided that
3541 @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
3542 @code{REGISTER_MOVE_COST} applied to their classes returns a value of 2.
3544 It is obligatory to support floating point @samp{mov@var{m}}
3545 instructions into and out of any registers that can hold fixed point
3546 values, because unions and structures (which have modes @code{SImode} or
3547 @code{DImode}) can be in those registers and they may have floating
3550 There may also be a need to support fixed point @samp{mov@var{m}}
3551 instructions in and out of floating point registers. Unfortunately, I
3552 have forgotten why this was so, and I don't know whether it is still
3553 true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
3554 floating point registers, then the constraints of the fixed point
3555 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
3556 reload into a floating point register.
3558 @cindex @code{reload_in} instruction pattern
3559 @cindex @code{reload_out} instruction pattern
3560 @item @samp{reload_in@var{m}}
3561 @itemx @samp{reload_out@var{m}}
3562 These named patterns have been obsoleted by the target hook
3563 @code{secondary_reload}.
3565 Like @samp{mov@var{m}}, but used when a scratch register is required to
3566 move between operand 0 and operand 1. Operand 2 describes the scratch
3567 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
3568 macro in @pxref{Register Classes}.
3570 There are special restrictions on the form of the @code{match_operand}s
3571 used in these patterns. First, only the predicate for the reload
3572 operand is examined, i.e., @code{reload_in} examines operand 1, but not
3573 the predicates for operand 0 or 2. Second, there may be only one
3574 alternative in the constraints. Third, only a single register class
3575 letter may be used for the constraint; subsequent constraint letters
3576 are ignored. As a special exception, an empty constraint string
3577 matches the @code{ALL_REGS} register class. This may relieve ports
3578 of the burden of defining an @code{ALL_REGS} constraint letter just
3581 @cindex @code{movstrict@var{m}} instruction pattern
3582 @item @samp{movstrict@var{m}}
3583 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
3584 with mode @var{m} of a register whose natural mode is wider,
3585 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
3586 any of the register except the part which belongs to mode @var{m}.
3588 @cindex @code{movmisalign@var{m}} instruction pattern
3589 @item @samp{movmisalign@var{m}}
3590 This variant of a move pattern is designed to load or store a value
3591 from a memory address that is not naturally aligned for its mode.
3592 For a store, the memory will be in operand 0; for a load, the memory
3593 will be in operand 1. The other operand is guaranteed not to be a
3594 memory, so that it's easy to tell whether this is a load or store.
3596 This pattern is used by the autovectorizer, and when expanding a
3597 @code{MISALIGNED_INDIRECT_REF} expression.
3599 @cindex @code{load_multiple} instruction pattern
3600 @item @samp{load_multiple}
3601 Load several consecutive memory locations into consecutive registers.
3602 Operand 0 is the first of the consecutive registers, operand 1
3603 is the first memory location, and operand 2 is a constant: the
3604 number of consecutive registers.
3606 Define this only if the target machine really has such an instruction;
3607 do not define this if the most efficient way of loading consecutive
3608 registers from memory is to do them one at a time.
3610 On some machines, there are restrictions as to which consecutive
3611 registers can be stored into memory, such as particular starting or
3612 ending register numbers or only a range of valid counts. For those
3613 machines, use a @code{define_expand} (@pxref{Expander Definitions})
3614 and make the pattern fail if the restrictions are not met.
3616 Write the generated insn as a @code{parallel} with elements being a
3617 @code{set} of one register from the appropriate memory location (you may
3618 also need @code{use} or @code{clobber} elements). Use a
3619 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
3620 @file{rs6000.md} for examples of the use of this insn pattern.
3622 @cindex @samp{store_multiple} instruction pattern
3623 @item @samp{store_multiple}
3624 Similar to @samp{load_multiple}, but store several consecutive registers
3625 into consecutive memory locations. Operand 0 is the first of the
3626 consecutive memory locations, operand 1 is the first register, and
3627 operand 2 is a constant: the number of consecutive registers.
3629 @cindex @code{vec_set@var{m}} instruction pattern
3630 @item @samp{vec_set@var{m}}
3631 Set given field in the vector value. Operand 0 is the vector to modify,
3632 operand 1 is new value of field and operand 2 specify the field index.
3634 @cindex @code{vec_extract@var{m}} instruction pattern
3635 @item @samp{vec_extract@var{m}}
3636 Extract given field from the vector value. Operand 1 is the vector, operand 2
3637 specify field index and operand 0 place to store value into.
3639 @cindex @code{vec_extract_even@var{m}} instruction pattern
3640 @item @samp{vec_extract_even@var{m}}
3641 Extract even elements from the input vectors (operand 1 and operand 2).
3642 The even elements of operand 2 are concatenated to the even elements of operand
3643 1 in their original order. The result is stored in operand 0.
3644 The output and input vectors should have the same modes.
3646 @cindex @code{vec_extract_odd@var{m}} instruction pattern
3647 @item @samp{vec_extract_odd@var{m}}
3648 Extract odd elements from the input vectors (operand 1 and operand 2).
3649 The odd elements of operand 2 are concatenated to the odd elements of operand
3650 1 in their original order. The result is stored in operand 0.
3651 The output and input vectors should have the same modes.
3653 @cindex @code{vec_interleave_high@var{m}} instruction pattern
3654 @item @samp{vec_interleave_high@var{m}}
3655 Merge high elements of the two input vectors into the output vector. The output
3656 and input vectors should have the same modes (@code{N} elements). The high
3657 @code{N/2} elements of the first input vector are interleaved with the high
3658 @code{N/2} elements of the second input vector.
3660 @cindex @code{vec_interleave_low@var{m}} instruction pattern
3661 @item @samp{vec_interleave_low@var{m}}
3662 Merge low elements of the two input vectors into the output vector. The output
3663 and input vectors should have the same modes (@code{N} elements). The low
3664 @code{N/2} elements of the first input vector are interleaved with the low
3665 @code{N/2} elements of the second input vector.
3667 @cindex @code{vec_init@var{m}} instruction pattern
3668 @item @samp{vec_init@var{m}}
3669 Initialize the vector to given values. Operand 0 is the vector to initialize
3670 and operand 1 is parallel containing values for individual fields.
3672 @cindex @code{push@var{m}1} instruction pattern
3673 @item @samp{push@var{m}1}
3674 Output a push instruction. Operand 0 is value to push. Used only when
3675 @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be
3676 missing and in such case an @code{mov} expander is used instead, with a
3677 @code{MEM} expression forming the push operation. The @code{mov} expander
3678 method is deprecated.
3680 @cindex @code{add@var{m}3} instruction pattern
3681 @item @samp{add@var{m}3}
3682 Add operand 2 and operand 1, storing the result in operand 0. All operands
3683 must have mode @var{m}. This can be used even on two-address machines, by
3684 means of constraints requiring operands 1 and 0 to be the same location.
3686 @cindex @code{ssadd@var{m}3} instruction pattern
3687 @cindex @code{usadd@var{m}3} instruction pattern
3688 @cindex @code{sub@var{m}3} instruction pattern
3689 @cindex @code{sssub@var{m}3} instruction pattern
3690 @cindex @code{ussub@var{m}3} instruction pattern
3691 @cindex @code{mul@var{m}3} instruction pattern
3692 @cindex @code{ssmul@var{m}3} instruction pattern
3693 @cindex @code{usmul@var{m}3} instruction pattern
3694 @cindex @code{div@var{m}3} instruction pattern
3695 @cindex @code{ssdiv@var{m}3} instruction pattern
3696 @cindex @code{udiv@var{m}3} instruction pattern
3697 @cindex @code{usdiv@var{m}3} instruction pattern
3698 @cindex @code{mod@var{m}3} instruction pattern
3699 @cindex @code{umod@var{m}3} instruction pattern
3700 @cindex @code{umin@var{m}3} instruction pattern
3701 @cindex @code{umax@var{m}3} instruction pattern
3702 @cindex @code{and@var{m}3} instruction pattern
3703 @cindex @code{ior@var{m}3} instruction pattern
3704 @cindex @code{xor@var{m}3} instruction pattern
3705 @item @samp{ssadd@var{m}3}, @samp{usadd@var{m}3}
3706 @item @samp{sub@var{m}3}, @samp{sssub@var{m}3}, @samp{ussub@var{m}3}
3707 @item @samp{mul@var{m}3}, @samp{ssmul@var{m}3}, @samp{usmul@var{m}3}
3708 @itemx @samp{div@var{m}3}, @samp{ssdiv@var{m}3}
3709 @itemx @samp{udiv@var{m}3}, @samp{usdiv@var{m}3}
3710 @itemx @samp{mod@var{m}3}, @samp{umod@var{m}3}
3711 @itemx @samp{umin@var{m}3}, @samp{umax@var{m}3}
3712 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
3713 Similar, for other arithmetic operations.
3715 @cindex @code{min@var{m}3} instruction pattern
3716 @cindex @code{max@var{m}3} instruction pattern
3717 @item @samp{smin@var{m}3}, @samp{smax@var{m}3}
3718 Signed minimum and maximum operations. When used with floating point,
3719 if both operands are zeros, or if either operand is @code{NaN}, then
3720 it is unspecified which of the two operands is returned as the result.
3722 @cindex @code{reduc_smin_@var{m}} instruction pattern
3723 @cindex @code{reduc_smax_@var{m}} instruction pattern
3724 @item @samp{reduc_smin_@var{m}}, @samp{reduc_smax_@var{m}}
3725 Find the signed minimum/maximum of the elements of a vector. The vector is
3726 operand 1, and the scalar result is stored in the least significant bits of
3727 operand 0 (also a vector). The output and input vector should have the same
3730 @cindex @code{reduc_umin_@var{m}} instruction pattern
3731 @cindex @code{reduc_umax_@var{m}} instruction pattern
3732 @item @samp{reduc_umin_@var{m}}, @samp{reduc_umax_@var{m}}
3733 Find the unsigned minimum/maximum of the elements of a vector. The vector is
3734 operand 1, and the scalar result is stored in the least significant bits of
3735 operand 0 (also a vector). The output and input vector should have the same
3738 @cindex @code{reduc_splus_@var{m}} instruction pattern
3739 @item @samp{reduc_splus_@var{m}}
3740 Compute the sum of the signed elements of a vector. The vector is operand 1,
3741 and the scalar result is stored in the least significant bits of operand 0
3742 (also a vector). The output and input vector should have the same modes.
3744 @cindex @code{reduc_uplus_@var{m}} instruction pattern
3745 @item @samp{reduc_uplus_@var{m}}
3746 Compute the sum of the unsigned elements of a vector. The vector is operand 1,
3747 and the scalar result is stored in the least significant bits of operand 0
3748 (also a vector). The output and input vector should have the same modes.
3750 @cindex @code{sdot_prod@var{m}} instruction pattern
3751 @item @samp{sdot_prod@var{m}}
3752 @cindex @code{udot_prod@var{m}} instruction pattern
3753 @item @samp{udot_prod@var{m}}
3754 Compute the sum of the products of two signed/unsigned elements.
3755 Operand 1 and operand 2 are of the same mode. Their product, which is of a
3756 wider mode, is computed and added to operand 3. Operand 3 is of a mode equal or
3757 wider than the mode of the product. The result is placed in operand 0, which
3758 is of the same mode as operand 3.
3760 @cindex @code{ssum_widen@var{m3}} instruction pattern
3761 @item @samp{ssum_widen@var{m3}}
3762 @cindex @code{usum_widen@var{m3}} instruction pattern
3763 @item @samp{usum_widen@var{m3}}
3764 Operands 0 and 2 are of the same mode, which is wider than the mode of
3765 operand 1. Add operand 1 to operand 2 and place the widened result in
3766 operand 0. (This is used express accumulation of elements into an accumulator
3769 @cindex @code{vec_shl_@var{m}} instruction pattern
3770 @cindex @code{vec_shr_@var{m}} instruction pattern
3771 @item @samp{vec_shl_@var{m}}, @samp{vec_shr_@var{m}}
3772 Whole vector left/right shift in bits.
3773 Operand 1 is a vector to be shifted.
3774 Operand 2 is an integer shift amount in bits.
3775 Operand 0 is where the resulting shifted vector is stored.
3776 The output and input vectors should have the same modes.
3778 @cindex @code{vec_pack_trunc_@var{m}} instruction pattern
3779 @item @samp{vec_pack_trunc_@var{m}}
3780 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
3781 are vectors of the same mode having N integral or floating point elements
3782 of size S@. Operand 0 is the resulting vector in which 2*N elements of
3783 size N/2 are concatenated after narrowing them down using truncation.
3785 @cindex @code{vec_pack_ssat_@var{m}} instruction pattern
3786 @cindex @code{vec_pack_usat_@var{m}} instruction pattern
3787 @item @samp{vec_pack_ssat_@var{m}}, @samp{vec_pack_usat_@var{m}}
3788 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
3789 are vectors of the same mode having N integral elements of size S.
3790 Operand 0 is the resulting vector in which the elements of the two input
3791 vectors are concatenated after narrowing them down using signed/unsigned
3792 saturating arithmetic.
3794 @cindex @code{vec_pack_sfix_trunc_@var{m}} instruction pattern
3795 @cindex @code{vec_pack_ufix_trunc_@var{m}} instruction pattern
3796 @item @samp{vec_pack_sfix_trunc_@var{m}}, @samp{vec_pack_ufix_trunc_@var{m}}
3797 Narrow, convert to signed/unsigned integral type and merge the elements
3798 of two vectors. Operands 1 and 2 are vectors of the same mode having N
3799 floating point elements of size S@. Operand 0 is the resulting vector
3800 in which 2*N elements of size N/2 are concatenated.
3802 @cindex @code{vec_unpacks_hi_@var{m}} instruction pattern
3803 @cindex @code{vec_unpacks_lo_@var{m}} instruction pattern
3804 @item @samp{vec_unpacks_hi_@var{m}}, @samp{vec_unpacks_lo_@var{m}}
3805 Extract and widen (promote) the high/low part of a vector of signed
3806 integral or floating point elements. The input vector (operand 1) has N
3807 elements of size S@. Widen (promote) the high/low elements of the vector
3808 using signed or floating point extension and place the resulting N/2
3809 values of size 2*S in the output vector (operand 0).
3811 @cindex @code{vec_unpacku_hi_@var{m}} instruction pattern
3812 @cindex @code{vec_unpacku_lo_@var{m}} instruction pattern
3813 @item @samp{vec_unpacku_hi_@var{m}}, @samp{vec_unpacku_lo_@var{m}}
3814 Extract and widen (promote) the high/low part of a vector of unsigned
3815 integral elements. The input vector (operand 1) has N elements of size S.
3816 Widen (promote) the high/low elements of the vector using zero extension and
3817 place the resulting N/2 values of size 2*S in the output vector (operand 0).
3819 @cindex @code{vec_unpacks_float_hi_@var{m}} instruction pattern
3820 @cindex @code{vec_unpacks_float_lo_@var{m}} instruction pattern
3821 @cindex @code{vec_unpacku_float_hi_@var{m}} instruction pattern
3822 @cindex @code{vec_unpacku_float_lo_@var{m}} instruction pattern
3823 @item @samp{vec_unpacks_float_hi_@var{m}}, @samp{vec_unpacks_float_lo_@var{m}}
3824 @itemx @samp{vec_unpacku_float_hi_@var{m}}, @samp{vec_unpacku_float_lo_@var{m}}
3825 Extract, convert to floating point type and widen the high/low part of a
3826 vector of signed/unsigned integral elements. The input vector (operand 1)
3827 has N elements of size S@. Convert the high/low elements of the vector using
3828 floating point conversion and place the resulting N/2 values of size 2*S in
3829 the output vector (operand 0).
3831 @cindex @code{vec_widen_umult_hi_@var{m}} instruction pattern
3832 @cindex @code{vec_widen_umult_lo__@var{m}} instruction pattern
3833 @cindex @code{vec_widen_smult_hi_@var{m}} instruction pattern
3834 @cindex @code{vec_widen_smult_lo_@var{m}} instruction pattern
3835 @item @samp{vec_widen_umult_hi_@var{m}}, @samp{vec_widen_umult_lo_@var{m}}
3836 @itemx @samp{vec_widen_smult_hi_@var{m}}, @samp{vec_widen_smult_lo_@var{m}}
3837 Signed/Unsigned widening multiplication. The two inputs (operands 1 and 2)
3838 are vectors with N signed/unsigned elements of size S@. Multiply the high/low
3839 elements of the two vectors, and put the N/2 products of size 2*S in the
3840 output vector (operand 0).
3842 @cindex @code{mulhisi3} instruction pattern
3843 @item @samp{mulhisi3}
3844 Multiply operands 1 and 2, which have mode @code{HImode}, and store
3845 a @code{SImode} product in operand 0.
3847 @cindex @code{mulqihi3} instruction pattern
3848 @cindex @code{mulsidi3} instruction pattern
3849 @item @samp{mulqihi3}, @samp{mulsidi3}
3850 Similar widening-multiplication instructions of other widths.
3852 @cindex @code{umulqihi3} instruction pattern
3853 @cindex @code{umulhisi3} instruction pattern
3854 @cindex @code{umulsidi3} instruction pattern
3855 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
3856 Similar widening-multiplication instructions that do unsigned
3859 @cindex @code{usmulqihi3} instruction pattern
3860 @cindex @code{usmulhisi3} instruction pattern
3861 @cindex @code{usmulsidi3} instruction pattern
3862 @item @samp{usmulqihi3}, @samp{usmulhisi3}, @samp{usmulsidi3}
3863 Similar widening-multiplication instructions that interpret the first
3864 operand as unsigned and the second operand as signed, then do a signed
3867 @cindex @code{smul@var{m}3_highpart} instruction pattern
3868 @item @samp{smul@var{m}3_highpart}
3869 Perform a signed multiplication of operands 1 and 2, which have mode
3870 @var{m}, and store the most significant half of the product in operand 0.
3871 The least significant half of the product is discarded.
3873 @cindex @code{umul@var{m}3_highpart} instruction pattern
3874 @item @samp{umul@var{m}3_highpart}
3875 Similar, but the multiplication is unsigned.
3877 @cindex @code{madd@var{m}@var{n}4} instruction pattern
3878 @item @samp{madd@var{m}@var{n}4}
3879 Multiply operands 1 and 2, sign-extend them to mode @var{n}, add
3880 operand 3, and store the result in operand 0. Operands 1 and 2
3881 have mode @var{m} and operands 0 and 3 have mode @var{n}.
3882 Both modes must be integer or fixed-point modes and @var{n} must be twice
3883 the size of @var{m}.
3885 In other words, @code{madd@var{m}@var{n}4} is like
3886 @code{mul@var{m}@var{n}3} except that it also adds operand 3.
3888 These instructions are not allowed to @code{FAIL}.
3890 @cindex @code{umadd@var{m}@var{n}4} instruction pattern
3891 @item @samp{umadd@var{m}@var{n}4}
3892 Like @code{madd@var{m}@var{n}4}, but zero-extend the multiplication
3893 operands instead of sign-extending them.
3895 @cindex @code{ssmadd@var{m}@var{n}4} instruction pattern
3896 @item @samp{ssmadd@var{m}@var{n}4}
3897 Like @code{madd@var{m}@var{n}4}, but all involved operations must be
3900 @cindex @code{usmadd@var{m}@var{n}4} instruction pattern
3901 @item @samp{usmadd@var{m}@var{n}4}
3902 Like @code{umadd@var{m}@var{n}4}, but all involved operations must be
3903 unsigned-saturating.
3905 @cindex @code{msub@var{m}@var{n}4} instruction pattern
3906 @item @samp{msub@var{m}@var{n}4}
3907 Multiply operands 1 and 2, sign-extend them to mode @var{n}, subtract the
3908 result from operand 3, and store the result in operand 0. Operands 1 and 2
3909 have mode @var{m} and operands 0 and 3 have mode @var{n}.
3910 Both modes must be integer or fixed-point modes and @var{n} must be twice
3911 the size of @var{m}.
3913 In other words, @code{msub@var{m}@var{n}4} is like
3914 @code{mul@var{m}@var{n}3} except that it also subtracts the result
3917 These instructions are not allowed to @code{FAIL}.
3919 @cindex @code{umsub@var{m}@var{n}4} instruction pattern
3920 @item @samp{umsub@var{m}@var{n}4}
3921 Like @code{msub@var{m}@var{n}4}, but zero-extend the multiplication
3922 operands instead of sign-extending them.
3924 @cindex @code{ssmsub@var{m}@var{n}4} instruction pattern
3925 @item @samp{ssmsub@var{m}@var{n}4}
3926 Like @code{msub@var{m}@var{n}4}, but all involved operations must be
3929 @cindex @code{usmsub@var{m}@var{n}4} instruction pattern
3930 @item @samp{usmsub@var{m}@var{n}4}
3931 Like @code{umsub@var{m}@var{n}4}, but all involved operations must be
3932 unsigned-saturating.
3934 @cindex @code{divmod@var{m}4} instruction pattern
3935 @item @samp{divmod@var{m}4}
3936 Signed division that produces both a quotient and a remainder.
3937 Operand 1 is divided by operand 2 to produce a quotient stored
3938 in operand 0 and a remainder stored in operand 3.
3940 For machines with an instruction that produces both a quotient and a
3941 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
3942 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
3943 allows optimization in the relatively common case when both the quotient
3944 and remainder are computed.
3946 If an instruction that just produces a quotient or just a remainder
3947 exists and is more efficient than the instruction that produces both,
3948 write the output routine of @samp{divmod@var{m}4} to call
3949 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
3950 quotient or remainder and generate the appropriate instruction.
3952 @cindex @code{udivmod@var{m}4} instruction pattern
3953 @item @samp{udivmod@var{m}4}
3954 Similar, but does unsigned division.
3956 @anchor{shift patterns}
3957 @cindex @code{ashl@var{m}3} instruction pattern
3958 @cindex @code{ssashl@var{m}3} instruction pattern
3959 @cindex @code{usashl@var{m}3} instruction pattern
3960 @item @samp{ashl@var{m}3}, @samp{ssashl@var{m}3}, @samp{usashl@var{m}3}
3961 Arithmetic-shift operand 1 left by a number of bits specified by operand
3962 2, and store the result in operand 0. Here @var{m} is the mode of
3963 operand 0 and operand 1; operand 2's mode is specified by the
3964 instruction pattern, and the compiler will convert the operand to that
3965 mode before generating the instruction. The meaning of out-of-range shift
3966 counts can optionally be specified by @code{TARGET_SHIFT_TRUNCATION_MASK}.
3967 @xref{TARGET_SHIFT_TRUNCATION_MASK}. Operand 2 is always a scalar type.
3969 @cindex @code{ashr@var{m}3} instruction pattern
3970 @cindex @code{lshr@var{m}3} instruction pattern
3971 @cindex @code{rotl@var{m}3} instruction pattern
3972 @cindex @code{rotr@var{m}3} instruction pattern
3973 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
3974 Other shift and rotate instructions, analogous to the
3975 @code{ashl@var{m}3} instructions. Operand 2 is always a scalar type.
3977 @cindex @code{vashl@var{m}3} instruction pattern
3978 @cindex @code{vashr@var{m}3} instruction pattern
3979 @cindex @code{vlshr@var{m}3} instruction pattern
3980 @cindex @code{vrotl@var{m}3} instruction pattern
3981 @cindex @code{vrotr@var{m}3} instruction pattern
3982 @item @samp{vashl@var{m}3}, @samp{vashr@var{m}3}, @samp{vlshr@var{m}3}, @samp{vrotl@var{m}3}, @samp{vrotr@var{m}3}
3983 Vector shift and rotate instructions that take vectors as operand 2
3984 instead of a scalar type.
3986 @cindex @code{neg@var{m}2} instruction pattern
3987 @cindex @code{ssneg@var{m}2} instruction pattern
3988 @cindex @code{usneg@var{m}2} instruction pattern
3989 @item @samp{neg@var{m}2}, @samp{ssneg@var{m}2}, @samp{usneg@var{m}2}
3990 Negate operand 1 and store the result in operand 0.
3992 @cindex @code{abs@var{m}2} instruction pattern
3993 @item @samp{abs@var{m}2}
3994 Store the absolute value of operand 1 into operand 0.
3996 @cindex @code{sqrt@var{m}2} instruction pattern
3997 @item @samp{sqrt@var{m}2}
3998 Store the square root of operand 1 into operand 0.
4000 The @code{sqrt} built-in function of C always uses the mode which
4001 corresponds to the C data type @code{double} and the @code{sqrtf}
4002 built-in function uses the mode which corresponds to the C data
4005 @cindex @code{fmod@var{m}3} instruction pattern
4006 @item @samp{fmod@var{m}3}
4007 Store the remainder of dividing operand 1 by operand 2 into
4008 operand 0, rounded towards zero to an integer.
4010 The @code{fmod} built-in function of C always uses the mode which
4011 corresponds to the C data type @code{double} and the @code{fmodf}
4012 built-in function uses the mode which corresponds to the C data
4015 @cindex @code{remainder@var{m}3} instruction pattern
4016 @item @samp{remainder@var{m}3}
4017 Store the remainder of dividing operand 1 by operand 2 into
4018 operand 0, rounded to the nearest integer.
4020 The @code{remainder} built-in function of C always uses the mode
4021 which corresponds to the C data type @code{double} and the
4022 @code{remainderf} built-in function uses the mode which corresponds
4023 to the C data type @code{float}.
4025 @cindex @code{cos@var{m}2} instruction pattern
4026 @item @samp{cos@var{m}2}
4027 Store the cosine of operand 1 into operand 0.
4029 The @code{cos} built-in function of C always uses the mode which
4030 corresponds to the C data type @code{double} and the @code{cosf}
4031 built-in function uses the mode which corresponds to the C data
4034 @cindex @code{sin@var{m}2} instruction pattern
4035 @item @samp{sin@var{m}2}
4036 Store the sine of operand 1 into operand 0.
4038 The @code{sin} built-in function of C always uses the mode which
4039 corresponds to the C data type @code{double} and the @code{sinf}
4040 built-in function uses the mode which corresponds to the C data
4043 @cindex @code{exp@var{m}2} instruction pattern
4044 @item @samp{exp@var{m}2}
4045 Store the exponential of operand 1 into operand 0.
4047 The @code{exp} built-in function of C always uses the mode which
4048 corresponds to the C data type @code{double} and the @code{expf}
4049 built-in function uses the mode which corresponds to the C data
4052 @cindex @code{log@var{m}2} instruction pattern
4053 @item @samp{log@var{m}2}
4054 Store the natural logarithm of operand 1 into operand 0.
4056 The @code{log} built-in function of C always uses the mode which
4057 corresponds to the C data type @code{double} and the @code{logf}
4058 built-in function uses the mode which corresponds to the C data
4061 @cindex @code{pow@var{m}3} instruction pattern
4062 @item @samp{pow@var{m}3}
4063 Store the value of operand 1 raised to the exponent operand 2
4066 The @code{pow} built-in function of C always uses the mode which
4067 corresponds to the C data type @code{double} and the @code{powf}
4068 built-in function uses the mode which corresponds to the C data
4071 @cindex @code{atan2@var{m}3} instruction pattern
4072 @item @samp{atan2@var{m}3}
4073 Store the arc tangent (inverse tangent) of operand 1 divided by
4074 operand 2 into operand 0, using the signs of both arguments to
4075 determine the quadrant of the result.
4077 The @code{atan2} built-in function of C always uses the mode which
4078 corresponds to the C data type @code{double} and the @code{atan2f}
4079 built-in function uses the mode which corresponds to the C data
4082 @cindex @code{floor@var{m}2} instruction pattern
4083 @item @samp{floor@var{m}2}
4084 Store the largest integral value not greater than argument.
4086 The @code{floor} built-in function of C always uses the mode which
4087 corresponds to the C data type @code{double} and the @code{floorf}
4088 built-in function uses the mode which corresponds to the C data
4091 @cindex @code{btrunc@var{m}2} instruction pattern
4092 @item @samp{btrunc@var{m}2}
4093 Store the argument rounded to integer towards zero.
4095 The @code{trunc} built-in function of C always uses the mode which
4096 corresponds to the C data type @code{double} and the @code{truncf}
4097 built-in function uses the mode which corresponds to the C data
4100 @cindex @code{round@var{m}2} instruction pattern
4101 @item @samp{round@var{m}2}
4102 Store the argument rounded to integer away from zero.
4104 The @code{round} built-in function of C always uses the mode which
4105 corresponds to the C data type @code{double} and the @code{roundf}
4106 built-in function uses the mode which corresponds to the C data
4109 @cindex @code{ceil@var{m}2} instruction pattern
4110 @item @samp{ceil@var{m}2}
4111 Store the argument rounded to integer away from zero.
4113 The @code{ceil} built-in function of C always uses the mode which
4114 corresponds to the C data type @code{double} and the @code{ceilf}
4115 built-in function uses the mode which corresponds to the C data
4118 @cindex @code{nearbyint@var{m}2} instruction pattern
4119 @item @samp{nearbyint@var{m}2}
4120 Store the argument rounded according to the default rounding mode
4122 The @code{nearbyint} built-in function of C always uses the mode which
4123 corresponds to the C data type @code{double} and the @code{nearbyintf}
4124 built-in function uses the mode which corresponds to the C data
4127 @cindex @code{rint@var{m}2} instruction pattern
4128 @item @samp{rint@var{m}2}
4129 Store the argument rounded according to the default rounding mode and
4130 raise the inexact exception when the result differs in value from
4133 The @code{rint} built-in function of C always uses the mode which
4134 corresponds to the C data type @code{double} and the @code{rintf}
4135 built-in function uses the mode which corresponds to the C data
4138 @cindex @code{lrint@var{m}@var{n}2}
4139 @item @samp{lrint@var{m}@var{n}2}
4140 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4141 point mode @var{n} as a signed number according to the current
4142 rounding mode and store in operand 0 (which has mode @var{n}).
4144 @cindex @code{lround@var{m}@var{n}2}
4145 @item @samp{lround@var{m}2}
4146 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4147 point mode @var{n} as a signed number rounding to nearest and away
4148 from zero and store in operand 0 (which has mode @var{n}).
4150 @cindex @code{lfloor@var{m}@var{n}2}
4151 @item @samp{lfloor@var{m}2}
4152 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4153 point mode @var{n} as a signed number rounding down and store in
4154 operand 0 (which has mode @var{n}).
4156 @cindex @code{lceil@var{m}@var{n}2}
4157 @item @samp{lceil@var{m}2}
4158 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4159 point mode @var{n} as a signed number rounding up and store in
4160 operand 0 (which has mode @var{n}).
4162 @cindex @code{copysign@var{m}3} instruction pattern
4163 @item @samp{copysign@var{m}3}
4164 Store a value with the magnitude of operand 1 and the sign of operand
4167 The @code{copysign} built-in function of C always uses the mode which
4168 corresponds to the C data type @code{double} and the @code{copysignf}
4169 built-in function uses the mode which corresponds to the C data
4172 @cindex @code{ffs@var{m}2} instruction pattern
4173 @item @samp{ffs@var{m}2}
4174 Store into operand 0 one plus the index of the least significant 1-bit
4175 of operand 1. If operand 1 is zero, store zero. @var{m} is the mode
4176 of operand 0; operand 1's mode is specified by the instruction
4177 pattern, and the compiler will convert the operand to that mode before
4178 generating the instruction.
4180 The @code{ffs} built-in function of C always uses the mode which
4181 corresponds to the C data type @code{int}.
4183 @cindex @code{clz@var{m}2} instruction pattern
4184 @item @samp{clz@var{m}2}
4185 Store into operand 0 the number of leading 0-bits in @var{x}, starting
4186 at the most significant bit position. If @var{x} is 0, the
4187 @code{CLZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
4188 the result is undefined or has a useful value.
4189 @var{m} is the mode of operand 0; operand 1's mode is
4190 specified by the instruction pattern, and the compiler will convert the
4191 operand to that mode before generating the instruction.
4193 @cindex @code{ctz@var{m}2} instruction pattern
4194 @item @samp{ctz@var{m}2}
4195 Store into operand 0 the number of trailing 0-bits in @var{x}, starting
4196 at the least significant bit position. If @var{x} is 0, the
4197 @code{CTZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
4198 the result is undefined or has a useful value.
4199 @var{m} is the mode of operand 0; operand 1's mode is
4200 specified by the instruction pattern, and the compiler will convert the
4201 operand to that mode before generating the instruction.
4203 @cindex @code{popcount@var{m}2} instruction pattern
4204 @item @samp{popcount@var{m}2}
4205 Store into operand 0 the number of 1-bits in @var{x}. @var{m} is the
4206 mode of operand 0; operand 1's mode is specified by the instruction
4207 pattern, and the compiler will convert the operand to that mode before
4208 generating the instruction.
4210 @cindex @code{parity@var{m}2} instruction pattern
4211 @item @samp{parity@var{m}2}
4212 Store into operand 0 the parity of @var{x}, i.e.@: the number of 1-bits
4213 in @var{x} modulo 2. @var{m} is the mode of operand 0; operand 1's mode
4214 is specified by the instruction pattern, and the compiler will convert
4215 the operand to that mode before generating the instruction.
4217 @cindex @code{one_cmpl@var{m}2} instruction pattern
4218 @item @samp{one_cmpl@var{m}2}
4219 Store the bitwise-complement of operand 1 into operand 0.
4221 @cindex @code{cmp@var{m}} instruction pattern
4222 @item @samp{cmp@var{m}}
4223 Compare operand 0 and operand 1, and set the condition codes.
4224 The RTL pattern should look like this:
4227 (set (cc0) (compare (match_operand:@var{m} 0 @dots{})
4228 (match_operand:@var{m} 1 @dots{})))
4231 @cindex @code{tst@var{m}} instruction pattern
4232 @item @samp{tst@var{m}}
4233 Compare operand 0 against zero, and set the condition codes.
4234 The RTL pattern should look like this:
4237 (set (cc0) (match_operand:@var{m} 0 @dots{}))
4240 @samp{tst@var{m}} patterns should not be defined for machines that do
4241 not use @code{(cc0)}. Doing so would confuse the optimizer since it
4242 would no longer be clear which @code{set} operations were comparisons.
4243 The @samp{cmp@var{m}} patterns should be used instead.
4245 @cindex @code{movmem@var{m}} instruction pattern
4246 @item @samp{movmem@var{m}}
4247 Block move instruction. The destination and source blocks of memory
4248 are the first two operands, and both are @code{mem:BLK}s with an
4249 address in mode @code{Pmode}.
4251 The number of bytes to move is the third operand, in mode @var{m}.
4252 Usually, you specify @code{word_mode} for @var{m}. However, if you can
4253 generate better code knowing the range of valid lengths is smaller than
4254 those representable in a full word, you should provide a pattern with a
4255 mode corresponding to the range of values you can handle efficiently
4256 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
4257 that appear negative) and also a pattern with @code{word_mode}.
4259 The fourth operand is the known shared alignment of the source and
4260 destination, in the form of a @code{const_int} rtx. Thus, if the
4261 compiler knows that both source and destination are word-aligned,
4262 it may provide the value 4 for this operand.
4264 Optional operands 5 and 6 specify expected alignment and size of block
4265 respectively. The expected alignment differs from alignment in operand 4
4266 in a way that the blocks are not required to be aligned according to it in
4267 all cases. This expected alignment is also in bytes, just like operand 4.
4268 Expected size, when unknown, is set to @code{(const_int -1)}.
4270 Descriptions of multiple @code{movmem@var{m}} patterns can only be
4271 beneficial if the patterns for smaller modes have fewer restrictions
4272 on their first, second and fourth operands. Note that the mode @var{m}
4273 in @code{movmem@var{m}} does not impose any restriction on the mode of
4274 individually moved data units in the block.
4276 These patterns need not give special consideration to the possibility
4277 that the source and destination strings might overlap.
4279 @cindex @code{movstr} instruction pattern
4281 String copy instruction, with @code{stpcpy} semantics. Operand 0 is
4282 an output operand in mode @code{Pmode}. The addresses of the
4283 destination and source strings are operands 1 and 2, and both are
4284 @code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of
4285 the expansion of this pattern should store in operand 0 the address in
4286 which the @code{NUL} terminator was stored in the destination string.
4288 @cindex @code{setmem@var{m}} instruction pattern
4289 @item @samp{setmem@var{m}}
4290 Block set instruction. The destination string is the first operand,
4291 given as a @code{mem:BLK} whose address is in mode @code{Pmode}. The
4292 number of bytes to set is the second operand, in mode @var{m}. The value to
4293 initialize the memory with is the third operand. Targets that only support the
4294 clearing of memory should reject any value that is not the constant 0. See
4295 @samp{movmem@var{m}} for a discussion of the choice of mode.
4297 The fourth operand is the known alignment of the destination, in the form
4298 of a @code{const_int} rtx. Thus, if the compiler knows that the
4299 destination is word-aligned, it may provide the value 4 for this
4302 Optional operands 5 and 6 specify expected alignment and size of block
4303 respectively. The expected alignment differs from alignment in operand 4
4304 in a way that the blocks are not required to be aligned according to it in
4305 all cases. This expected alignment is also in bytes, just like operand 4.
4306 Expected size, when unknown, is set to @code{(const_int -1)}.
4308 The use for multiple @code{setmem@var{m}} is as for @code{movmem@var{m}}.
4310 @cindex @code{cmpstrn@var{m}} instruction pattern
4311 @item @samp{cmpstrn@var{m}}
4312 String compare instruction, with five operands. Operand 0 is the output;
4313 it has mode @var{m}. The remaining four operands are like the operands
4314 of @samp{movmem@var{m}}. The two memory blocks specified are compared
4315 byte by byte in lexicographic order starting at the beginning of each
4316 string. The instruction is not allowed to prefetch more than one byte
4317 at a time since either string may end in the first byte and reading past
4318 that may access an invalid page or segment and cause a fault. The
4319 effect of the instruction is to store a value in operand 0 whose sign
4320 indicates the result of the comparison.
4322 @cindex @code{cmpstr@var{m}} instruction pattern
4323 @item @samp{cmpstr@var{m}}
4324 String compare instruction, without known maximum length. Operand 0 is the
4325 output; it has mode @var{m}. The second and third operand are the blocks of
4326 memory to be compared; both are @code{mem:BLK} with an address in mode
4329 The fourth operand is the known shared alignment of the source and
4330 destination, in the form of a @code{const_int} rtx. Thus, if the
4331 compiler knows that both source and destination are word-aligned,
4332 it may provide the value 4 for this operand.
4334 The two memory blocks specified are compared byte by byte in lexicographic
4335 order starting at the beginning of each string. The instruction is not allowed
4336 to prefetch more than one byte at a time since either string may end in the
4337 first byte and reading past that may access an invalid page or segment and
4338 cause a fault. The effect of the instruction is to store a value in operand 0
4339 whose sign indicates the result of the comparison.
4341 @cindex @code{cmpmem@var{m}} instruction pattern
4342 @item @samp{cmpmem@var{m}}
4343 Block compare instruction, with five operands like the operands
4344 of @samp{cmpstr@var{m}}. The two memory blocks specified are compared
4345 byte by byte in lexicographic order starting at the beginning of each
4346 block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch
4347 any bytes in the two memory blocks. The effect of the instruction is
4348 to store a value in operand 0 whose sign indicates the result of the
4351 @cindex @code{strlen@var{m}} instruction pattern
4352 @item @samp{strlen@var{m}}
4353 Compute the length of a string, with three operands.
4354 Operand 0 is the result (of mode @var{m}), operand 1 is
4355 a @code{mem} referring to the first character of the string,
4356 operand 2 is the character to search for (normally zero),
4357 and operand 3 is a constant describing the known alignment
4358 of the beginning of the string.
4360 @cindex @code{float@var{mn}2} instruction pattern
4361 @item @samp{float@var{m}@var{n}2}
4362 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
4363 floating point mode @var{n} and store in operand 0 (which has mode
4366 @cindex @code{floatuns@var{mn}2} instruction pattern
4367 @item @samp{floatuns@var{m}@var{n}2}
4368 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
4369 to floating point mode @var{n} and store in operand 0 (which has mode
4372 @cindex @code{fix@var{mn}2} instruction pattern
4373 @item @samp{fix@var{m}@var{n}2}
4374 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4375 point mode @var{n} as a signed number and store in operand 0 (which
4376 has mode @var{n}). This instruction's result is defined only when
4377 the value of operand 1 is an integer.
4379 If the machine description defines this pattern, it also needs to
4380 define the @code{ftrunc} pattern.
4382 @cindex @code{fixuns@var{mn}2} instruction pattern
4383 @item @samp{fixuns@var{m}@var{n}2}
4384 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4385 point mode @var{n} as an unsigned number and store in operand 0 (which
4386 has mode @var{n}). This instruction's result is defined only when the
4387 value of operand 1 is an integer.
4389 @cindex @code{ftrunc@var{m}2} instruction pattern
4390 @item @samp{ftrunc@var{m}2}
4391 Convert operand 1 (valid for floating point mode @var{m}) to an
4392 integer value, still represented in floating point mode @var{m}, and
4393 store it in operand 0 (valid for floating point mode @var{m}).
4395 @cindex @code{fix_trunc@var{mn}2} instruction pattern
4396 @item @samp{fix_trunc@var{m}@var{n}2}
4397 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
4398 of mode @var{m} by converting the value to an integer.
4400 @cindex @code{fixuns_trunc@var{mn}2} instruction pattern
4401 @item @samp{fixuns_trunc@var{m}@var{n}2}
4402 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
4403 value of mode @var{m} by converting the value to an integer.
4405 @cindex @code{trunc@var{mn}2} instruction pattern
4406 @item @samp{trunc@var{m}@var{n}2}
4407 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
4408 store in operand 0 (which has mode @var{n}). Both modes must be fixed
4409 point or both floating point.
4411 @cindex @code{extend@var{mn}2} instruction pattern
4412 @item @samp{extend@var{m}@var{n}2}
4413 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
4414 store in operand 0 (which has mode @var{n}). Both modes must be fixed
4415 point or both floating point.
4417 @cindex @code{zero_extend@var{mn}2} instruction pattern
4418 @item @samp{zero_extend@var{m}@var{n}2}
4419 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
4420 store in operand 0 (which has mode @var{n}). Both modes must be fixed
4423 @cindex @code{fract@var{mn}2} instruction pattern
4424 @item @samp{fract@var{m}@var{n}2}
4425 Convert operand 1 of mode @var{m} to mode @var{n} and store in
4426 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
4427 could be fixed-point to fixed-point, signed integer to fixed-point,
4428 fixed-point to signed integer, floating-point to fixed-point,
4429 or fixed-point to floating-point.
4430 When overflows or underflows happen, the results are undefined.
4432 @cindex @code{satfract@var{mn}2} instruction pattern
4433 @item @samp{satfract@var{m}@var{n}2}
4434 Convert operand 1 of mode @var{m} to mode @var{n} and store in
4435 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
4436 could be fixed-point to fixed-point, signed integer to fixed-point,
4437 or floating-point to fixed-point.
4438 When overflows or underflows happen, the instruction saturates the
4439 results to the maximum or the minimum.
4441 @cindex @code{fractuns@var{mn}2} instruction pattern
4442 @item @samp{fractuns@var{m}@var{n}2}
4443 Convert operand 1 of mode @var{m} to mode @var{n} and store in
4444 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
4445 could be unsigned integer to fixed-point, or
4446 fixed-point to unsigned integer.
4447 When overflows or underflows happen, the results are undefined.
4449 @cindex @code{satfractuns@var{mn}2} instruction pattern
4450 @item @samp{satfractuns@var{m}@var{n}2}
4451 Convert unsigned integer operand 1 of mode @var{m} to fixed-point mode
4452 @var{n} and store in operand 0 (which has mode @var{n}).
4453 When overflows or underflows happen, the instruction saturates the
4454 results to the maximum or the minimum.
4456 @cindex @code{extv} instruction pattern
4458 Extract a bit-field from operand 1 (a register or memory operand), where
4459 operand 2 specifies the width in bits and operand 3 the starting bit,
4460 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
4461 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
4462 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
4463 be valid for @code{word_mode}.
4465 The RTL generation pass generates this instruction only with constants
4466 for operands 2 and 3 and the constant is never zero for operand 2.
4468 The bit-field value is sign-extended to a full word integer
4469 before it is stored in operand 0.
4471 @cindex @code{extzv} instruction pattern
4473 Like @samp{extv} except that the bit-field value is zero-extended.
4475 @cindex @code{insv} instruction pattern
4477 Store operand 3 (which must be valid for @code{word_mode}) into a
4478 bit-field in operand 0, where operand 1 specifies the width in bits and
4479 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
4480 @code{word_mode}; often @code{word_mode} is allowed only for registers.
4481 Operands 1 and 2 must be valid for @code{word_mode}.
4483 The RTL generation pass generates this instruction only with constants
4484 for operands 1 and 2 and the constant is never zero for operand 1.
4486 @cindex @code{mov@var{mode}cc} instruction pattern
4487 @item @samp{mov@var{mode}cc}
4488 Conditionally move operand 2 or operand 3 into operand 0 according to the
4489 comparison in operand 1. If the comparison is true, operand 2 is moved
4490 into operand 0, otherwise operand 3 is moved.
4492 The mode of the operands being compared need not be the same as the operands
4493 being moved. Some machines, sparc64 for example, have instructions that
4494 conditionally move an integer value based on the floating point condition
4495 codes and vice versa.
4497 If the machine does not have conditional move instructions, do not
4498 define these patterns.
4500 @cindex @code{add@var{mode}cc} instruction pattern
4501 @item @samp{add@var{mode}cc}
4502 Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally
4503 move operand 2 or (operands 2 + operand 3) into operand 0 according to the
4504 comparison in operand 1. If the comparison is true, operand 2 is moved into
4505 operand 0, otherwise (operand 2 + operand 3) is moved.
4507 @cindex @code{s@var{cond}} instruction pattern
4508 @item @samp{s@var{cond}}
4509 Store zero or nonzero in the operand according to the condition codes.
4510 Value stored is nonzero iff the condition @var{cond} is true.
4511 @var{cond} is the name of a comparison operation expression code, such
4512 as @code{eq}, @code{lt} or @code{leu}.
4514 You specify the mode that the operand must have when you write the
4515 @code{match_operand} expression. The compiler automatically sees
4516 which mode you have used and supplies an operand of that mode.
4518 The value stored for a true condition must have 1 as its low bit, or
4519 else must be negative. Otherwise the instruction is not suitable and
4520 you should omit it from the machine description. You describe to the
4521 compiler exactly which value is stored by defining the macro
4522 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
4523 found that can be used for all the @samp{s@var{cond}} patterns, you
4524 should omit those operations from the machine description.
4526 These operations may fail, but should do so only in relatively
4527 uncommon cases; if they would fail for common cases involving
4528 integer comparisons, it is best to omit these patterns.
4530 If these operations are omitted, the compiler will usually generate code
4531 that copies the constant one to the target and branches around an
4532 assignment of zero to the target. If this code is more efficient than
4533 the potential instructions used for the @samp{s@var{cond}} pattern
4534 followed by those required to convert the result into a 1 or a zero in
4535 @code{SImode}, you should omit the @samp{s@var{cond}} operations from
4536 the machine description.
4538 @cindex @code{b@var{cond}} instruction pattern
4539 @item @samp{b@var{cond}}
4540 Conditional branch instruction. Operand 0 is a @code{label_ref} that
4541 refers to the label to jump to. Jump if the condition codes meet
4542 condition @var{cond}.
4544 Some machines do not follow the model assumed here where a comparison
4545 instruction is followed by a conditional branch instruction. In that
4546 case, the @samp{cmp@var{m}} (and @samp{tst@var{m}}) patterns should
4547 simply store the operands away and generate all the required insns in a
4548 @code{define_expand} (@pxref{Expander Definitions}) for the conditional
4549 branch operations. All calls to expand @samp{b@var{cond}} patterns are
4550 immediately preceded by calls to expand either a @samp{cmp@var{m}}
4551 pattern or a @samp{tst@var{m}} pattern.
4553 Machines that use a pseudo register for the condition code value, or
4554 where the mode used for the comparison depends on the condition being
4555 tested, should also use the above mechanism. @xref{Jump Patterns}.
4557 The above discussion also applies to the @samp{mov@var{mode}cc} and
4558 @samp{s@var{cond}} patterns.
4560 @cindex @code{cbranch@var{mode}4} instruction pattern
4561 @item @samp{cbranch@var{mode}4}
4562 Conditional branch instruction combined with a compare instruction.
4563 Operand 0 is a comparison operator. Operand 1 and operand 2 are the
4564 first and second operands of the comparison, respectively. Operand 3
4565 is a @code{label_ref} that refers to the label to jump to.
4567 @cindex @code{jump} instruction pattern
4569 A jump inside a function; an unconditional branch. Operand 0 is the
4570 @code{label_ref} of the label to jump to. This pattern name is mandatory
4573 @cindex @code{call} instruction pattern
4575 Subroutine call instruction returning no value. Operand 0 is the
4576 function to call; operand 1 is the number of bytes of arguments pushed
4577 as a @code{const_int}; operand 2 is the number of registers used as
4580 On most machines, operand 2 is not actually stored into the RTL
4581 pattern. It is supplied for the sake of some RISC machines which need
4582 to put this information into the assembler code; they can put it in
4583 the RTL instead of operand 1.
4585 Operand 0 should be a @code{mem} RTX whose address is the address of the
4586 function. Note, however, that this address can be a @code{symbol_ref}
4587 expression even if it would not be a legitimate memory address on the
4588 target machine. If it is also not a valid argument for a call
4589 instruction, the pattern for this operation should be a
4590 @code{define_expand} (@pxref{Expander Definitions}) that places the
4591 address into a register and uses that register in the call instruction.
4593 @cindex @code{call_value} instruction pattern
4594 @item @samp{call_value}
4595 Subroutine call instruction returning a value. Operand 0 is the hard
4596 register in which the value is returned. There are three more
4597 operands, the same as the three operands of the @samp{call}
4598 instruction (but with numbers increased by one).
4600 Subroutines that return @code{BLKmode} objects use the @samp{call}
4603 @cindex @code{call_pop} instruction pattern
4604 @cindex @code{call_value_pop} instruction pattern
4605 @item @samp{call_pop}, @samp{call_value_pop}
4606 Similar to @samp{call} and @samp{call_value}, except used if defined and
4607 if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel}
4608 that contains both the function call and a @code{set} to indicate the
4609 adjustment made to the frame pointer.
4611 For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these
4612 patterns increases the number of functions for which the frame pointer
4613 can be eliminated, if desired.
4615 @cindex @code{untyped_call} instruction pattern
4616 @item @samp{untyped_call}
4617 Subroutine call instruction returning a value of any type. Operand 0 is
4618 the function to call; operand 1 is a memory location where the result of
4619 calling the function is to be stored; operand 2 is a @code{parallel}
4620 expression where each element is a @code{set} expression that indicates
4621 the saving of a function return value into the result block.
4623 This instruction pattern should be defined to support
4624 @code{__builtin_apply} on machines where special instructions are needed
4625 to call a subroutine with arbitrary arguments or to save the value
4626 returned. This instruction pattern is required on machines that have
4627 multiple registers that can hold a return value
4628 (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
4630 @cindex @code{return} instruction pattern
4632 Subroutine return instruction. This instruction pattern name should be
4633 defined only if a single instruction can do all the work of returning
4636 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
4637 RTL generation phase. In this case it is to support machines where
4638 multiple instructions are usually needed to return from a function, but
4639 some class of functions only requires one instruction to implement a
4640 return. Normally, the applicable functions are those which do not need
4641 to save any registers or allocate stack space.
4643 @findex reload_completed
4644 @findex leaf_function_p
4645 For such machines, the condition specified in this pattern should only
4646 be true when @code{reload_completed} is nonzero and the function's
4647 epilogue would only be a single instruction. For machines with register
4648 windows, the routine @code{leaf_function_p} may be used to determine if
4649 a register window push is required.
4651 Machines that have conditional return instructions should define patterns
4657 (if_then_else (match_operator
4658 0 "comparison_operator"
4659 [(cc0) (const_int 0)])
4666 where @var{condition} would normally be the same condition specified on the
4667 named @samp{return} pattern.
4669 @cindex @code{untyped_return} instruction pattern
4670 @item @samp{untyped_return}
4671 Untyped subroutine return instruction. This instruction pattern should
4672 be defined to support @code{__builtin_return} on machines where special
4673 instructions are needed to return a value of any type.
4675 Operand 0 is a memory location where the result of calling a function
4676 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
4677 expression where each element is a @code{set} expression that indicates
4678 the restoring of a function return value from the result block.
4680 @cindex @code{nop} instruction pattern
4682 No-op instruction. This instruction pattern name should always be defined
4683 to output a no-op in assembler code. @code{(const_int 0)} will do as an
4686 @cindex @code{indirect_jump} instruction pattern
4687 @item @samp{indirect_jump}
4688 An instruction to jump to an address which is operand zero.
4689 This pattern name is mandatory on all machines.
4691 @cindex @code{casesi} instruction pattern
4693 Instruction to jump through a dispatch table, including bounds checking.
4694 This instruction takes five operands:
4698 The index to dispatch on, which has mode @code{SImode}.
4701 The lower bound for indices in the table, an integer constant.
4704 The total range of indices in the table---the largest index
4705 minus the smallest one (both inclusive).
4708 A label that precedes the table itself.
4711 A label to jump to if the index has a value outside the bounds.
4714 The table is a @code{addr_vec} or @code{addr_diff_vec} inside of a
4715 @code{jump_insn}. The number of elements in the table is one plus the
4716 difference between the upper bound and the lower bound.
4718 @cindex @code{tablejump} instruction pattern
4719 @item @samp{tablejump}
4720 Instruction to jump to a variable address. This is a low-level
4721 capability which can be used to implement a dispatch table when there
4722 is no @samp{casesi} pattern.
4724 This pattern requires two operands: the address or offset, and a label
4725 which should immediately precede the jump table. If the macro
4726 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
4727 operand is an offset which counts from the address of the table; otherwise,
4728 it is an absolute address to jump to. In either case, the first operand has
4731 The @samp{tablejump} insn is always the last insn before the jump
4732 table it uses. Its assembler code normally has no need to use the
4733 second operand, but you should incorporate it in the RTL pattern so
4734 that the jump optimizer will not delete the table as unreachable code.
4737 @cindex @code{decrement_and_branch_until_zero} instruction pattern
4738 @item @samp{decrement_and_branch_until_zero}
4739 Conditional branch instruction that decrements a register and
4740 jumps if the register is nonzero. Operand 0 is the register to
4741 decrement and test; operand 1 is the label to jump to if the
4742 register is nonzero. @xref{Looping Patterns}.
4744 This optional instruction pattern is only used by the combiner,
4745 typically for loops reversed by the loop optimizer when strength
4746 reduction is enabled.
4748 @cindex @code{doloop_end} instruction pattern
4749 @item @samp{doloop_end}
4750 Conditional branch instruction that decrements a register and jumps if
4751 the register is nonzero. This instruction takes five operands: Operand
4752 0 is the register to decrement and test; operand 1 is the number of loop
4753 iterations as a @code{const_int} or @code{const0_rtx} if this cannot be
4754 determined until run-time; operand 2 is the actual or estimated maximum
4755 number of iterations as a @code{const_int}; operand 3 is the number of
4756 enclosed loops as a @code{const_int} (an innermost loop has a value of
4757 1); operand 4 is the label to jump to if the register is nonzero.
4758 @xref{Looping Patterns}.
4760 This optional instruction pattern should be defined for machines with
4761 low-overhead looping instructions as the loop optimizer will try to
4762 modify suitable loops to utilize it. If nested low-overhead looping is
4763 not supported, use a @code{define_expand} (@pxref{Expander Definitions})
4764 and make the pattern fail if operand 3 is not @code{const1_rtx}.
4765 Similarly, if the actual or estimated maximum number of iterations is
4766 too large for this instruction, make it fail.
4768 @cindex @code{doloop_begin} instruction pattern
4769 @item @samp{doloop_begin}
4770 Companion instruction to @code{doloop_end} required for machines that
4771 need to perform some initialization, such as loading special registers
4772 used by a low-overhead looping instruction. If initialization insns do
4773 not always need to be emitted, use a @code{define_expand}
4774 (@pxref{Expander Definitions}) and make it fail.
4777 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
4778 @item @samp{canonicalize_funcptr_for_compare}
4779 Canonicalize the function pointer in operand 1 and store the result
4782 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
4783 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
4784 and also has mode @code{Pmode}.
4786 Canonicalization of a function pointer usually involves computing
4787 the address of the function which would be called if the function
4788 pointer were used in an indirect call.
4790 Only define this pattern if function pointers on the target machine
4791 can have different values but still call the same function when
4792 used in an indirect call.
4794 @cindex @code{save_stack_block} instruction pattern
4795 @cindex @code{save_stack_function} instruction pattern
4796 @cindex @code{save_stack_nonlocal} instruction pattern
4797 @cindex @code{restore_stack_block} instruction pattern
4798 @cindex @code{restore_stack_function} instruction pattern
4799 @cindex @code{restore_stack_nonlocal} instruction pattern
4800 @item @samp{save_stack_block}
4801 @itemx @samp{save_stack_function}
4802 @itemx @samp{save_stack_nonlocal}
4803 @itemx @samp{restore_stack_block}
4804 @itemx @samp{restore_stack_function}
4805 @itemx @samp{restore_stack_nonlocal}
4806 Most machines save and restore the stack pointer by copying it to or
4807 from an object of mode @code{Pmode}. Do not define these patterns on
4810 Some machines require special handling for stack pointer saves and
4811 restores. On those machines, define the patterns corresponding to the
4812 non-standard cases by using a @code{define_expand} (@pxref{Expander
4813 Definitions}) that produces the required insns. The three types of
4814 saves and restores are:
4818 @samp{save_stack_block} saves the stack pointer at the start of a block
4819 that allocates a variable-sized object, and @samp{restore_stack_block}
4820 restores the stack pointer when the block is exited.
4823 @samp{save_stack_function} and @samp{restore_stack_function} do a
4824 similar job for the outermost block of a function and are used when the
4825 function allocates variable-sized objects or calls @code{alloca}. Only
4826 the epilogue uses the restored stack pointer, allowing a simpler save or
4827 restore sequence on some machines.
4830 @samp{save_stack_nonlocal} is used in functions that contain labels
4831 branched to by nested functions. It saves the stack pointer in such a
4832 way that the inner function can use @samp{restore_stack_nonlocal} to
4833 restore the stack pointer. The compiler generates code to restore the
4834 frame and argument pointer registers, but some machines require saving
4835 and restoring additional data such as register window information or
4836 stack backchains. Place insns in these patterns to save and restore any
4840 When saving the stack pointer, operand 0 is the save area and operand 1
4841 is the stack pointer. The mode used to allocate the save area defaults
4842 to @code{Pmode} but you can override that choice by defining the
4843 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
4844 specify an integral mode, or @code{VOIDmode} if no save area is needed
4845 for a particular type of save (either because no save is needed or
4846 because a machine-specific save area can be used). Operand 0 is the
4847 stack pointer and operand 1 is the save area for restore operations. If
4848 @samp{save_stack_block} is defined, operand 0 must not be
4849 @code{VOIDmode} since these saves can be arbitrarily nested.
4851 A save area is a @code{mem} that is at a constant offset from
4852 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
4853 nonlocal gotos and a @code{reg} in the other two cases.
4855 @cindex @code{allocate_stack} instruction pattern
4856 @item @samp{allocate_stack}
4857 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
4858 the stack pointer to create space for dynamically allocated data.
4860 Store the resultant pointer to this space into operand 0. If you
4861 are allocating space from the main stack, do this by emitting a
4862 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
4863 If you are allocating the space elsewhere, generate code to copy the
4864 location of the space to operand 0. In the latter case, you must
4865 ensure this space gets freed when the corresponding space on the main
4868 Do not define this pattern if all that must be done is the subtraction.
4869 Some machines require other operations such as stack probes or
4870 maintaining the back chain. Define this pattern to emit those
4871 operations in addition to updating the stack pointer.
4873 @cindex @code{check_stack} instruction pattern
4874 @item @samp{check_stack}
4875 If stack checking cannot be done on your system by probing the stack with
4876 a load or store instruction (@pxref{Stack Checking}), define this pattern
4877 to perform the needed check and signaling an error if the stack
4878 has overflowed. The single operand is the location in the stack furthest
4879 from the current stack pointer that you need to validate. Normally,
4880 on machines where this pattern is needed, you would obtain the stack
4881 limit from a global or thread-specific variable or register.
4883 @cindex @code{nonlocal_goto} instruction pattern
4884 @item @samp{nonlocal_goto}
4885 Emit code to generate a non-local goto, e.g., a jump from one function
4886 to a label in an outer function. This pattern has four arguments,
4887 each representing a value to be used in the jump. The first
4888 argument is to be loaded into the frame pointer, the second is
4889 the address to branch to (code to dispatch to the actual label),
4890 the third is the address of a location where the stack is saved,
4891 and the last is the address of the label, to be placed in the
4892 location for the incoming static chain.
4894 On most machines you need not define this pattern, since GCC will
4895 already generate the correct code, which is to load the frame pointer
4896 and static chain, restore the stack (using the
4897 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
4898 to the dispatcher. You need only define this pattern if this code will
4899 not work on your machine.
4901 @cindex @code{nonlocal_goto_receiver} instruction pattern
4902 @item @samp{nonlocal_goto_receiver}
4903 This pattern, if defined, contains code needed at the target of a
4904 nonlocal goto after the code already generated by GCC@. You will not
4905 normally need to define this pattern. A typical reason why you might
4906 need this pattern is if some value, such as a pointer to a global table,
4907 must be restored when the frame pointer is restored. Note that a nonlocal
4908 goto only occurs within a unit-of-translation, so a global table pointer
4909 that is shared by all functions of a given module need not be restored.
4910 There are no arguments.
4912 @cindex @code{exception_receiver} instruction pattern
4913 @item @samp{exception_receiver}
4914 This pattern, if defined, contains code needed at the site of an
4915 exception handler that isn't needed at the site of a nonlocal goto. You
4916 will not normally need to define this pattern. A typical reason why you
4917 might need this pattern is if some value, such as a pointer to a global
4918 table, must be restored after control flow is branched to the handler of
4919 an exception. There are no arguments.
4921 @cindex @code{builtin_setjmp_setup} instruction pattern
4922 @item @samp{builtin_setjmp_setup}
4923 This pattern, if defined, contains additional code needed to initialize
4924 the @code{jmp_buf}. You will not normally need to define this pattern.
4925 A typical reason why you might need this pattern is if some value, such
4926 as a pointer to a global table, must be restored. Though it is
4927 preferred that the pointer value be recalculated if possible (given the
4928 address of a label for instance). The single argument is a pointer to
4929 the @code{jmp_buf}. Note that the buffer is five words long and that
4930 the first three are normally used by the generic mechanism.
4932 @cindex @code{builtin_setjmp_receiver} instruction pattern
4933 @item @samp{builtin_setjmp_receiver}
4934 This pattern, if defined, contains code needed at the site of an
4935 built-in setjmp that isn't needed at the site of a nonlocal goto. You
4936 will not normally need to define this pattern. A typical reason why you
4937 might need this pattern is if some value, such as a pointer to a global
4938 table, must be restored. It takes one argument, which is the label
4939 to which builtin_longjmp transfered control; this pattern may be emitted
4940 at a small offset from that label.
4942 @cindex @code{builtin_longjmp} instruction pattern
4943 @item @samp{builtin_longjmp}
4944 This pattern, if defined, performs the entire action of the longjmp.
4945 You will not normally need to define this pattern unless you also define
4946 @code{builtin_setjmp_setup}. The single argument is a pointer to the
4949 @cindex @code{eh_return} instruction pattern
4950 @item @samp{eh_return}
4951 This pattern, if defined, affects the way @code{__builtin_eh_return},
4952 and thence the call frame exception handling library routines, are
4953 built. It is intended to handle non-trivial actions needed along
4954 the abnormal return path.
4956 The address of the exception handler to which the function should return
4957 is passed as operand to this pattern. It will normally need to copied by
4958 the pattern to some special register or memory location.
4959 If the pattern needs to determine the location of the target call
4960 frame in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX},
4961 if defined; it will have already been assigned.
4963 If this pattern is not defined, the default action will be to simply
4964 copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either
4965 that macro or this pattern needs to be defined if call frame exception
4966 handling is to be used.
4968 @cindex @code{prologue} instruction pattern
4969 @anchor{prologue instruction pattern}
4970 @item @samp{prologue}
4971 This pattern, if defined, emits RTL for entry to a function. The function
4972 entry is responsible for setting up the stack frame, initializing the frame
4973 pointer register, saving callee saved registers, etc.
4975 Using a prologue pattern is generally preferred over defining
4976 @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue.
4978 The @code{prologue} pattern is particularly useful for targets which perform
4979 instruction scheduling.
4981 @cindex @code{epilogue} instruction pattern
4982 @anchor{epilogue instruction pattern}
4983 @item @samp{epilogue}
4984 This pattern emits RTL for exit from a function. The function
4985 exit is responsible for deallocating the stack frame, restoring callee saved
4986 registers and emitting the return instruction.
4988 Using an epilogue pattern is generally preferred over defining
4989 @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue.
4991 The @code{epilogue} pattern is particularly useful for targets which perform
4992 instruction scheduling or which have delay slots for their return instruction.
4994 @cindex @code{sibcall_epilogue} instruction pattern
4995 @item @samp{sibcall_epilogue}
4996 This pattern, if defined, emits RTL for exit from a function without the final
4997 branch back to the calling function. This pattern will be emitted before any
4998 sibling call (aka tail call) sites.
5000 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
5001 parameter passing or any stack slots for arguments passed to the current
5004 @cindex @code{trap} instruction pattern
5006 This pattern, if defined, signals an error, typically by causing some
5007 kind of signal to be raised. Among other places, it is used by the Java
5008 front end to signal `invalid array index' exceptions.
5010 @cindex @code{conditional_trap} instruction pattern
5011 @item @samp{conditional_trap}
5012 Conditional trap instruction. Operand 0 is a piece of RTL which
5013 performs a comparison. Operand 1 is the trap code, an integer.
5015 A typical @code{conditional_trap} pattern looks like
5018 (define_insn "conditional_trap"
5019 [(trap_if (match_operator 0 "trap_operator"
5020 [(cc0) (const_int 0)])
5021 (match_operand 1 "const_int_operand" "i"))]
5026 @cindex @code{prefetch} instruction pattern
5027 @item @samp{prefetch}
5029 This pattern, if defined, emits code for a non-faulting data prefetch
5030 instruction. Operand 0 is the address of the memory to prefetch. Operand 1
5031 is a constant 1 if the prefetch is preparing for a write to the memory
5032 address, or a constant 0 otherwise. Operand 2 is the expected degree of
5033 temporal locality of the data and is a value between 0 and 3, inclusive; 0
5034 means that the data has no temporal locality, so it need not be left in the
5035 cache after the access; 3 means that the data has a high degree of temporal
5036 locality and should be left in all levels of cache possible; 1 and 2 mean,
5037 respectively, a low or moderate degree of temporal locality.
5039 Targets that do not support write prefetches or locality hints can ignore
5040 the values of operands 1 and 2.
5042 @cindex @code{blockage} instruction pattern
5043 @item @samp{blockage}
5045 This pattern defines a pseudo insn that prevents the instruction
5046 scheduler from moving instructions across the boundary defined by the
5047 blockage insn. Normally an UNSPEC_VOLATILE pattern.
5049 @cindex @code{memory_barrier} instruction pattern
5050 @item @samp{memory_barrier}
5052 If the target memory model is not fully synchronous, then this pattern
5053 should be defined to an instruction that orders both loads and stores
5054 before the instruction with respect to loads and stores after the instruction.
5055 This pattern has no operands.
5057 @cindex @code{sync_compare_and_swap@var{mode}} instruction pattern
5058 @item @samp{sync_compare_and_swap@var{mode}}
5060 This pattern, if defined, emits code for an atomic compare-and-swap
5061 operation. Operand 1 is the memory on which the atomic operation is
5062 performed. Operand 2 is the ``old'' value to be compared against the
5063 current contents of the memory location. Operand 3 is the ``new'' value
5064 to store in the memory if the compare succeeds. Operand 0 is the result
5065 of the operation; it should contain the contents of the memory
5066 before the operation. If the compare succeeds, this should obviously be
5067 a copy of operand 2.
5069 This pattern must show that both operand 0 and operand 1 are modified.
5071 This pattern must issue any memory barrier instructions such that all
5072 memory operations before the atomic operation occur before the atomic
5073 operation and all memory operations after the atomic operation occur
5074 after the atomic operation.
5076 @cindex @code{sync_compare_and_swap_cc@var{mode}} instruction pattern
5077 @item @samp{sync_compare_and_swap_cc@var{mode}}
5079 This pattern is just like @code{sync_compare_and_swap@var{mode}}, except
5080 it should act as if compare part of the compare-and-swap were issued via
5081 @code{cmp@var{m}}. This comparison will only be used with @code{EQ} and
5082 @code{NE} branches and @code{setcc} operations.
5084 Some targets do expose the success or failure of the compare-and-swap
5085 operation via the status flags. Ideally we wouldn't need a separate
5086 named pattern in order to take advantage of this, but the combine pass
5087 does not handle patterns with multiple sets, which is required by
5088 definition for @code{sync_compare_and_swap@var{mode}}.
5090 @cindex @code{sync_add@var{mode}} instruction pattern
5091 @cindex @code{sync_sub@var{mode}} instruction pattern
5092 @cindex @code{sync_ior@var{mode}} instruction pattern
5093 @cindex @code{sync_and@var{mode}} instruction pattern
5094 @cindex @code{sync_xor@var{mode}} instruction pattern
5095 @cindex @code{sync_nand@var{mode}} instruction pattern
5096 @item @samp{sync_add@var{mode}}, @samp{sync_sub@var{mode}}
5097 @itemx @samp{sync_ior@var{mode}}, @samp{sync_and@var{mode}}
5098 @itemx @samp{sync_xor@var{mode}}, @samp{sync_nand@var{mode}}
5100 These patterns emit code for an atomic operation on memory.
5101 Operand 0 is the memory on which the atomic operation is performed.
5102 Operand 1 is the second operand to the binary operator.
5104 The ``nand'' operation is @code{~op0 & op1}.
5106 This pattern must issue any memory barrier instructions such that all
5107 memory operations before the atomic operation occur before the atomic
5108 operation and all memory operations after the atomic operation occur
5109 after the atomic operation.
5111 If these patterns are not defined, the operation will be constructed
5112 from a compare-and-swap operation, if defined.
5114 @cindex @code{sync_old_add@var{mode}} instruction pattern
5115 @cindex @code{sync_old_sub@var{mode}} instruction pattern
5116 @cindex @code{sync_old_ior@var{mode}} instruction pattern
5117 @cindex @code{sync_old_and@var{mode}} instruction pattern
5118 @cindex @code{sync_old_xor@var{mode}} instruction pattern
5119 @cindex @code{sync_old_nand@var{mode}} instruction pattern
5120 @item @samp{sync_old_add@var{mode}}, @samp{sync_old_sub@var{mode}}
5121 @itemx @samp{sync_old_ior@var{mode}}, @samp{sync_old_and@var{mode}}
5122 @itemx @samp{sync_old_xor@var{mode}}, @samp{sync_old_nand@var{mode}}
5124 These patterns are emit code for an atomic operation on memory,
5125 and return the value that the memory contained before the operation.
5126 Operand 0 is the result value, operand 1 is the memory on which the
5127 atomic operation is performed, and operand 2 is the second operand
5128 to the binary operator.
5130 This pattern must issue any memory barrier instructions such that all
5131 memory operations before the atomic operation occur before the atomic
5132 operation and all memory operations after the atomic operation occur
5133 after the atomic operation.
5135 If these patterns are not defined, the operation will be constructed
5136 from a compare-and-swap operation, if defined.
5138 @cindex @code{sync_new_add@var{mode}} instruction pattern
5139 @cindex @code{sync_new_sub@var{mode}} instruction pattern
5140 @cindex @code{sync_new_ior@var{mode}} instruction pattern
5141 @cindex @code{sync_new_and@var{mode}} instruction pattern
5142 @cindex @code{sync_new_xor@var{mode}} instruction pattern
5143 @cindex @code{sync_new_nand@var{mode}} instruction pattern
5144 @item @samp{sync_new_add@var{mode}}, @samp{sync_new_sub@var{mode}}
5145 @itemx @samp{sync_new_ior@var{mode}}, @samp{sync_new_and@var{mode}}
5146 @itemx @samp{sync_new_xor@var{mode}}, @samp{sync_new_nand@var{mode}}
5148 These patterns are like their @code{sync_old_@var{op}} counterparts,
5149 except that they return the value that exists in the memory location
5150 after the operation, rather than before the operation.
5152 @cindex @code{sync_lock_test_and_set@var{mode}} instruction pattern
5153 @item @samp{sync_lock_test_and_set@var{mode}}
5155 This pattern takes two forms, based on the capabilities of the target.
5156 In either case, operand 0 is the result of the operand, operand 1 is
5157 the memory on which the atomic operation is performed, and operand 2
5158 is the value to set in the lock.
5160 In the ideal case, this operation is an atomic exchange operation, in
5161 which the previous value in memory operand is copied into the result
5162 operand, and the value operand is stored in the memory operand.
5164 For less capable targets, any value operand that is not the constant 1
5165 should be rejected with @code{FAIL}. In this case the target may use
5166 an atomic test-and-set bit operation. The result operand should contain
5167 1 if the bit was previously set and 0 if the bit was previously clear.
5168 The true contents of the memory operand are implementation defined.
5170 This pattern must issue any memory barrier instructions such that the
5171 pattern as a whole acts as an acquire barrier, that is all memory
5172 operations after the pattern do not occur until the lock is acquired.
5174 If this pattern is not defined, the operation will be constructed from
5175 a compare-and-swap operation, if defined.
5177 @cindex @code{sync_lock_release@var{mode}} instruction pattern
5178 @item @samp{sync_lock_release@var{mode}}
5180 This pattern, if defined, releases a lock set by
5181 @code{sync_lock_test_and_set@var{mode}}. Operand 0 is the memory
5182 that contains the lock; operand 1 is the value to store in the lock.
5184 If the target doesn't implement full semantics for
5185 @code{sync_lock_test_and_set@var{mode}}, any value operand which is not
5186 the constant 0 should be rejected with @code{FAIL}, and the true contents
5187 of the memory operand are implementation defined.
5189 This pattern must issue any memory barrier instructions such that the
5190 pattern as a whole acts as a release barrier, that is the lock is
5191 released only after all previous memory operations have completed.
5193 If this pattern is not defined, then a @code{memory_barrier} pattern
5194 will be emitted, followed by a store of the value to the memory operand.
5196 @cindex @code{stack_protect_set} instruction pattern
5197 @item @samp{stack_protect_set}
5199 This pattern, if defined, moves a @code{Pmode} value from the memory
5200 in operand 1 to the memory in operand 0 without leaving the value in
5201 a register afterward. This is to avoid leaking the value some place
5202 that an attacker might use to rewrite the stack guard slot after
5203 having clobbered it.
5205 If this pattern is not defined, then a plain move pattern is generated.
5207 @cindex @code{stack_protect_test} instruction pattern
5208 @item @samp{stack_protect_test}
5210 This pattern, if defined, compares a @code{Pmode} value from the
5211 memory in operand 1 with the memory in operand 0 without leaving the
5212 value in a register afterward and branches to operand 2 if the values
5215 If this pattern is not defined, then a plain compare pattern and
5216 conditional branch pattern is used.
5218 @cindex @code{clear_cache} instruction pattern
5219 @item @samp{clear_cache}
5221 This pattern, if defined, flushes the instruction cache for a region of
5222 memory. The region is bounded to by the Pmode pointers in operand 0
5223 inclusive and operand 1 exclusive.
5225 If this pattern is not defined, a call to the library function
5226 @code{__clear_cache} is used.
5231 @c Each of the following nodes are wrapped in separate
5232 @c "@ifset INTERNALS" to work around memory limits for the default
5233 @c configuration in older tetex distributions. Known to not work:
5234 @c tetex-1.0.7, known to work: tetex-2.0.2.
5236 @node Pattern Ordering
5237 @section When the Order of Patterns Matters
5238 @cindex Pattern Ordering
5239 @cindex Ordering of Patterns
5241 Sometimes an insn can match more than one instruction pattern. Then the
5242 pattern that appears first in the machine description is the one used.
5243 Therefore, more specific patterns (patterns that will match fewer things)
5244 and faster instructions (those that will produce better code when they
5245 do match) should usually go first in the description.
5247 In some cases the effect of ordering the patterns can be used to hide
5248 a pattern when it is not valid. For example, the 68000 has an
5249 instruction for converting a fullword to floating point and another
5250 for converting a byte to floating point. An instruction converting
5251 an integer to floating point could match either one. We put the
5252 pattern to convert the fullword first to make sure that one will
5253 be used rather than the other. (Otherwise a large integer might
5254 be generated as a single-byte immediate quantity, which would not work.)
5255 Instead of using this pattern ordering it would be possible to make the
5256 pattern for convert-a-byte smart enough to deal properly with any
5261 @node Dependent Patterns
5262 @section Interdependence of Patterns
5263 @cindex Dependent Patterns
5264 @cindex Interdependence of Patterns
5266 Every machine description must have a named pattern for each of the
5267 conditional branch names @samp{b@var{cond}}. The recognition template
5268 must always have the form
5272 (if_then_else (@var{cond} (cc0) (const_int 0))
5273 (label_ref (match_operand 0 "" ""))
5278 In addition, every machine description must have an anonymous pattern
5279 for each of the possible reverse-conditional branches. Their templates
5284 (if_then_else (@var{cond} (cc0) (const_int 0))
5286 (label_ref (match_operand 0 "" ""))))
5290 They are necessary because jump optimization can turn direct-conditional
5291 branches into reverse-conditional branches.
5293 It is often convenient to use the @code{match_operator} construct to
5294 reduce the number of patterns that must be specified for branches. For
5300 (if_then_else (match_operator 0 "comparison_operator"
5301 [(cc0) (const_int 0)])
5303 (label_ref (match_operand 1 "" ""))))]
5308 In some cases machines support instructions identical except for the
5309 machine mode of one or more operands. For example, there may be
5310 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
5314 (set (match_operand:SI 0 @dots{})
5315 (extend:SI (match_operand:HI 1 @dots{})))
5317 (set (match_operand:SI 0 @dots{})
5318 (extend:SI (match_operand:QI 1 @dots{})))
5322 Constant integers do not specify a machine mode, so an instruction to
5323 extend a constant value could match either pattern. The pattern it
5324 actually will match is the one that appears first in the file. For correct
5325 results, this must be the one for the widest possible mode (@code{HImode},
5326 here). If the pattern matches the @code{QImode} instruction, the results
5327 will be incorrect if the constant value does not actually fit that mode.
5329 Such instructions to extend constants are rarely generated because they are
5330 optimized away, but they do occasionally happen in nonoptimized
5333 If a constraint in a pattern allows a constant, the reload pass may
5334 replace a register with a constant permitted by the constraint in some
5335 cases. Similarly for memory references. Because of this substitution,
5336 you should not provide separate patterns for increment and decrement
5337 instructions. Instead, they should be generated from the same pattern
5338 that supports register-register add insns by examining the operands and
5339 generating the appropriate machine instruction.
5344 @section Defining Jump Instruction Patterns
5345 @cindex jump instruction patterns
5346 @cindex defining jump instruction patterns
5348 For most machines, GCC assumes that the machine has a condition code.
5349 A comparison insn sets the condition code, recording the results of both
5350 signed and unsigned comparison of the given operands. A separate branch
5351 insn tests the condition code and branches or not according its value.
5352 The branch insns come in distinct signed and unsigned flavors. Many
5353 common machines, such as the VAX, the 68000 and the 32000, work this
5356 Some machines have distinct signed and unsigned compare instructions, and
5357 only one set of conditional branch instructions. The easiest way to handle
5358 these machines is to treat them just like the others until the final stage
5359 where assembly code is written. At this time, when outputting code for the
5360 compare instruction, peek ahead at the following branch using
5361 @code{next_cc0_user (insn)}. (The variable @code{insn} refers to the insn
5362 being output, in the output-writing code in an instruction pattern.) If
5363 the RTL says that is an unsigned branch, output an unsigned compare;
5364 otherwise output a signed compare. When the branch itself is output, you
5365 can treat signed and unsigned branches identically.
5367 The reason you can do this is that GCC always generates a pair of
5368 consecutive RTL insns, possibly separated by @code{note} insns, one to
5369 set the condition code and one to test it, and keeps the pair inviolate
5372 To go with this technique, you must define the machine-description macro
5373 @code{NOTICE_UPDATE_CC} to do @code{CC_STATUS_INIT}; in other words, no
5374 compare instruction is superfluous.
5376 Some machines have compare-and-branch instructions and no condition code.
5377 A similar technique works for them. When it is time to ``output'' a
5378 compare instruction, record its operands in two static variables. When
5379 outputting the branch-on-condition-code instruction that follows, actually
5380 output a compare-and-branch instruction that uses the remembered operands.
5382 It also works to define patterns for compare-and-branch instructions.
5383 In optimizing compilation, the pair of compare and branch instructions
5384 will be combined according to these patterns. But this does not happen
5385 if optimization is not requested. So you must use one of the solutions
5386 above in addition to any special patterns you define.
5388 In many RISC machines, most instructions do not affect the condition
5389 code and there may not even be a separate condition code register. On
5390 these machines, the restriction that the definition and use of the
5391 condition code be adjacent insns is not necessary and can prevent
5392 important optimizations. For example, on the IBM RS/6000, there is a
5393 delay for taken branches unless the condition code register is set three
5394 instructions earlier than the conditional branch. The instruction
5395 scheduler cannot perform this optimization if it is not permitted to
5396 separate the definition and use of the condition code register.
5398 On these machines, do not use @code{(cc0)}, but instead use a register
5399 to represent the condition code. If there is a specific condition code
5400 register in the machine, use a hard register. If the condition code or
5401 comparison result can be placed in any general register, or if there are
5402 multiple condition registers, use a pseudo register.
5404 @findex prev_cc0_setter
5405 @findex next_cc0_user
5406 On some machines, the type of branch instruction generated may depend on
5407 the way the condition code was produced; for example, on the 68k and
5408 SPARC, setting the condition code directly from an add or subtract
5409 instruction does not clear the overflow bit the way that a test
5410 instruction does, so a different branch instruction must be used for
5411 some conditional branches. For machines that use @code{(cc0)}, the set
5412 and use of the condition code must be adjacent (separated only by
5413 @code{note} insns) allowing flags in @code{cc_status} to be used.
5414 (@xref{Condition Code}.) Also, the comparison and branch insns can be
5415 located from each other by using the functions @code{prev_cc0_setter}
5416 and @code{next_cc0_user}.
5418 However, this is not true on machines that do not use @code{(cc0)}. On
5419 those machines, no assumptions can be made about the adjacency of the
5420 compare and branch insns and the above methods cannot be used. Instead,
5421 we use the machine mode of the condition code register to record
5422 different formats of the condition code register.
5424 Registers used to store the condition code value should have a mode that
5425 is in class @code{MODE_CC}. Normally, it will be @code{CCmode}. If
5426 additional modes are required (as for the add example mentioned above in
5427 the SPARC), define them in @file{@var{machine}-modes.def}
5428 (@pxref{Condition Code}). Also define @code{SELECT_CC_MODE} to choose
5429 a mode given an operand of a compare.
5431 If it is known during RTL generation that a different mode will be
5432 required (for example, if the machine has separate compare instructions
5433 for signed and unsigned quantities, like most IBM processors), they can
5434 be specified at that time.
5436 If the cases that require different modes would be made by instruction
5437 combination, the macro @code{SELECT_CC_MODE} determines which machine
5438 mode should be used for the comparison result. The patterns should be
5439 written using that mode. To support the case of the add on the SPARC
5440 discussed above, we have the pattern
5444 [(set (reg:CC_NOOV 0)
5446 (plus:SI (match_operand:SI 0 "register_operand" "%r")
5447 (match_operand:SI 1 "arith_operand" "rI"))
5453 The @code{SELECT_CC_MODE} macro on the SPARC returns @code{CC_NOOVmode}
5454 for comparisons whose argument is a @code{plus}.
5458 @node Looping Patterns
5459 @section Defining Looping Instruction Patterns
5460 @cindex looping instruction patterns
5461 @cindex defining looping instruction patterns
5463 Some machines have special jump instructions that can be utilized to
5464 make loops more efficient. A common example is the 68000 @samp{dbra}
5465 instruction which performs a decrement of a register and a branch if the
5466 result was greater than zero. Other machines, in particular digital
5467 signal processors (DSPs), have special block repeat instructions to
5468 provide low-overhead loop support. For example, the TI TMS320C3x/C4x
5469 DSPs have a block repeat instruction that loads special registers to
5470 mark the top and end of a loop and to count the number of loop
5471 iterations. This avoids the need for fetching and executing a
5472 @samp{dbra}-like instruction and avoids pipeline stalls associated with
5475 GCC has three special named patterns to support low overhead looping.
5476 They are @samp{decrement_and_branch_until_zero}, @samp{doloop_begin},
5477 and @samp{doloop_end}. The first pattern,
5478 @samp{decrement_and_branch_until_zero}, is not emitted during RTL
5479 generation but may be emitted during the instruction combination phase.
5480 This requires the assistance of the loop optimizer, using information
5481 collected during strength reduction, to reverse a loop to count down to
5482 zero. Some targets also require the loop optimizer to add a
5483 @code{REG_NONNEG} note to indicate that the iteration count is always
5484 positive. This is needed if the target performs a signed loop
5485 termination test. For example, the 68000 uses a pattern similar to the
5486 following for its @code{dbra} instruction:
5490 (define_insn "decrement_and_branch_until_zero"
5493 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
5496 (label_ref (match_operand 1 "" ""))
5499 (plus:SI (match_dup 0)
5501 "find_reg_note (insn, REG_NONNEG, 0)"
5506 Note that since the insn is both a jump insn and has an output, it must
5507 deal with its own reloads, hence the `m' constraints. Also note that
5508 since this insn is generated by the instruction combination phase
5509 combining two sequential insns together into an implicit parallel insn,
5510 the iteration counter needs to be biased by the same amount as the
5511 decrement operation, in this case @minus{}1. Note that the following similar
5512 pattern will not be matched by the combiner.
5516 (define_insn "decrement_and_branch_until_zero"
5519 (ge (match_operand:SI 0 "general_operand" "+d*am")
5521 (label_ref (match_operand 1 "" ""))
5524 (plus:SI (match_dup 0)
5526 "find_reg_note (insn, REG_NONNEG, 0)"
5531 The other two special looping patterns, @samp{doloop_begin} and
5532 @samp{doloop_end}, are emitted by the loop optimizer for certain
5533 well-behaved loops with a finite number of loop iterations using
5534 information collected during strength reduction.
5536 The @samp{doloop_end} pattern describes the actual looping instruction
5537 (or the implicit looping operation) and the @samp{doloop_begin} pattern
5538 is an optional companion pattern that can be used for initialization
5539 needed for some low-overhead looping instructions.
5541 Note that some machines require the actual looping instruction to be
5542 emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
5543 the true RTL for a looping instruction at the top of the loop can cause
5544 problems with flow analysis. So instead, a dummy @code{doloop} insn is
5545 emitted at the end of the loop. The machine dependent reorg pass checks
5546 for the presence of this @code{doloop} insn and then searches back to
5547 the top of the loop, where it inserts the true looping insn (provided
5548 there are no instructions in the loop which would cause problems). Any
5549 additional labels can be emitted at this point. In addition, if the
5550 desired special iteration counter register was not allocated, this
5551 machine dependent reorg pass could emit a traditional compare and jump
5554 The essential difference between the
5555 @samp{decrement_and_branch_until_zero} and the @samp{doloop_end}
5556 patterns is that the loop optimizer allocates an additional pseudo
5557 register for the latter as an iteration counter. This pseudo register
5558 cannot be used within the loop (i.e., general induction variables cannot
5559 be derived from it), however, in many cases the loop induction variable
5560 may become redundant and removed by the flow pass.
5565 @node Insn Canonicalizations
5566 @section Canonicalization of Instructions
5567 @cindex canonicalization of instructions
5568 @cindex insn canonicalization
5570 There are often cases where multiple RTL expressions could represent an
5571 operation performed by a single machine instruction. This situation is
5572 most commonly encountered with logical, branch, and multiply-accumulate
5573 instructions. In such cases, the compiler attempts to convert these
5574 multiple RTL expressions into a single canonical form to reduce the
5575 number of insn patterns required.
5577 In addition to algebraic simplifications, following canonicalizations
5582 For commutative and comparison operators, a constant is always made the
5583 second operand. If a machine only supports a constant as the second
5584 operand, only patterns that match a constant in the second operand need
5588 For associative operators, a sequence of operators will always chain
5589 to the left; for instance, only the left operand of an integer @code{plus}
5590 can itself be a @code{plus}. @code{and}, @code{ior}, @code{xor},
5591 @code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and
5592 @code{umax} are associative when applied to integers, and sometimes to
5596 @cindex @code{neg}, canonicalization of
5597 @cindex @code{not}, canonicalization of
5598 @cindex @code{mult}, canonicalization of
5599 @cindex @code{plus}, canonicalization of
5600 @cindex @code{minus}, canonicalization of
5601 For these operators, if only one operand is a @code{neg}, @code{not},
5602 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
5606 In combinations of @code{neg}, @code{mult}, @code{plus}, and
5607 @code{minus}, the @code{neg} operations (if any) will be moved inside
5608 the operations as far as possible. For instance,
5609 @code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but
5610 @code{(plus (mult (neg A) B) C)} is canonicalized as
5611 @code{(minus A (mult B C))}.
5613 @cindex @code{compare}, canonicalization of
5615 For the @code{compare} operator, a constant is always the second operand
5616 on machines where @code{cc0} is used (@pxref{Jump Patterns}). On other
5617 machines, there are rare cases where the compiler might want to construct
5618 a @code{compare} with a constant as the first operand. However, these
5619 cases are not common enough for it to be worthwhile to provide a pattern
5620 matching a constant as the first operand unless the machine actually has
5621 such an instruction.
5623 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
5624 @code{minus} is made the first operand under the same conditions as
5628 @code{(ltu (plus @var{a} @var{b}) @var{b})} is converted to
5629 @code{(ltu (plus @var{a} @var{b}) @var{a})}. Likewise with @code{geu} instead
5633 @code{(minus @var{x} (const_int @var{n}))} is converted to
5634 @code{(plus @var{x} (const_int @var{-n}))}.
5637 Within address computations (i.e., inside @code{mem}), a left shift is
5638 converted into the appropriate multiplication by a power of two.
5640 @cindex @code{ior}, canonicalization of
5641 @cindex @code{and}, canonicalization of
5642 @cindex De Morgan's law
5644 De Morgan's Law is used to move bitwise negation inside a bitwise
5645 logical-and or logical-or operation. If this results in only one
5646 operand being a @code{not} expression, it will be the first one.
5648 A machine that has an instruction that performs a bitwise logical-and of one
5649 operand with the bitwise negation of the other should specify the pattern
5650 for that instruction as
5654 [(set (match_operand:@var{m} 0 @dots{})
5655 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
5656 (match_operand:@var{m} 2 @dots{})))]
5662 Similarly, a pattern for a ``NAND'' instruction should be written
5666 [(set (match_operand:@var{m} 0 @dots{})
5667 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
5668 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
5673 In both cases, it is not necessary to include patterns for the many
5674 logically equivalent RTL expressions.
5676 @cindex @code{xor}, canonicalization of
5678 The only possible RTL expressions involving both bitwise exclusive-or
5679 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
5680 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
5683 The sum of three items, one of which is a constant, will only appear in
5687 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
5691 On machines that do not use @code{cc0},
5692 @code{(compare @var{x} (const_int 0))} will be converted to
5695 @cindex @code{zero_extract}, canonicalization of
5696 @cindex @code{sign_extract}, canonicalization of
5698 Equality comparisons of a group of bits (usually a single bit) with zero
5699 will be written using @code{zero_extract} rather than the equivalent
5700 @code{and} or @code{sign_extract} operations.
5704 Further canonicalization rules are defined in the function
5705 @code{commutative_operand_precedence} in @file{gcc/rtlanal.c}.
5709 @node Expander Definitions
5710 @section Defining RTL Sequences for Code Generation
5711 @cindex expander definitions
5712 @cindex code generation RTL sequences
5713 @cindex defining RTL sequences for code generation
5715 On some target machines, some standard pattern names for RTL generation
5716 cannot be handled with single insn, but a sequence of RTL insns can
5717 represent them. For these target machines, you can write a
5718 @code{define_expand} to specify how to generate the sequence of RTL@.
5720 @findex define_expand
5721 A @code{define_expand} is an RTL expression that looks almost like a
5722 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
5723 only for RTL generation and it can produce more than one RTL insn.
5725 A @code{define_expand} RTX has four operands:
5729 The name. Each @code{define_expand} must have a name, since the only
5730 use for it is to refer to it by name.
5733 The RTL template. This is a vector of RTL expressions representing
5734 a sequence of separate instructions. Unlike @code{define_insn}, there
5735 is no implicit surrounding @code{PARALLEL}.
5738 The condition, a string containing a C expression. This expression is
5739 used to express how the availability of this pattern depends on
5740 subclasses of target machine, selected by command-line options when GCC
5741 is run. This is just like the condition of a @code{define_insn} that
5742 has a standard name. Therefore, the condition (if present) may not
5743 depend on the data in the insn being matched, but only the
5744 target-machine-type flags. The compiler needs to test these conditions
5745 during initialization in order to learn exactly which named instructions
5746 are available in a particular run.
5749 The preparation statements, a string containing zero or more C
5750 statements which are to be executed before RTL code is generated from
5753 Usually these statements prepare temporary registers for use as
5754 internal operands in the RTL template, but they can also generate RTL
5755 insns directly by calling routines such as @code{emit_insn}, etc.
5756 Any such insns precede the ones that come from the RTL template.
5759 Every RTL insn emitted by a @code{define_expand} must match some
5760 @code{define_insn} in the machine description. Otherwise, the compiler
5761 will crash when trying to generate code for the insn or trying to optimize
5764 The RTL template, in addition to controlling generation of RTL insns,
5765 also describes the operands that need to be specified when this pattern
5766 is used. In particular, it gives a predicate for each operand.
5768 A true operand, which needs to be specified in order to generate RTL from
5769 the pattern, should be described with a @code{match_operand} in its first
5770 occurrence in the RTL template. This enters information on the operand's
5771 predicate into the tables that record such things. GCC uses the
5772 information to preload the operand into a register if that is required for
5773 valid RTL code. If the operand is referred to more than once, subsequent
5774 references should use @code{match_dup}.
5776 The RTL template may also refer to internal ``operands'' which are
5777 temporary registers or labels used only within the sequence made by the
5778 @code{define_expand}. Internal operands are substituted into the RTL
5779 template with @code{match_dup}, never with @code{match_operand}. The
5780 values of the internal operands are not passed in as arguments by the
5781 compiler when it requests use of this pattern. Instead, they are computed
5782 within the pattern, in the preparation statements. These statements
5783 compute the values and store them into the appropriate elements of
5784 @code{operands} so that @code{match_dup} can find them.
5786 There are two special macros defined for use in the preparation statements:
5787 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
5794 Use the @code{DONE} macro to end RTL generation for the pattern. The
5795 only RTL insns resulting from the pattern on this occasion will be
5796 those already emitted by explicit calls to @code{emit_insn} within the
5797 preparation statements; the RTL template will not be generated.
5801 Make the pattern fail on this occasion. When a pattern fails, it means
5802 that the pattern was not truly available. The calling routines in the
5803 compiler will try other strategies for code generation using other patterns.
5805 Failure is currently supported only for binary (addition, multiplication,
5806 shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv})
5810 If the preparation falls through (invokes neither @code{DONE} nor
5811 @code{FAIL}), then the @code{define_expand} acts like a
5812 @code{define_insn} in that the RTL template is used to generate the
5815 The RTL template is not used for matching, only for generating the
5816 initial insn list. If the preparation statement always invokes
5817 @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple
5818 list of operands, such as this example:
5822 (define_expand "addsi3"
5823 [(match_operand:SI 0 "register_operand" "")
5824 (match_operand:SI 1 "register_operand" "")
5825 (match_operand:SI 2 "register_operand" "")]
5831 handle_add (operands[0], operands[1], operands[2]);
5837 Here is an example, the definition of left-shift for the SPUR chip:
5841 (define_expand "ashlsi3"
5842 [(set (match_operand:SI 0 "register_operand" "")
5846 (match_operand:SI 1 "register_operand" "")
5847 (match_operand:SI 2 "nonmemory_operand" "")))]
5856 if (GET_CODE (operands[2]) != CONST_INT
5857 || (unsigned) INTVAL (operands[2]) > 3)
5864 This example uses @code{define_expand} so that it can generate an RTL insn
5865 for shifting when the shift-count is in the supported range of 0 to 3 but
5866 fail in other cases where machine insns aren't available. When it fails,
5867 the compiler tries another strategy using different patterns (such as, a
5870 If the compiler were able to handle nontrivial condition-strings in
5871 patterns with names, then it would be possible to use a
5872 @code{define_insn} in that case. Here is another case (zero-extension
5873 on the 68000) which makes more use of the power of @code{define_expand}:
5876 (define_expand "zero_extendhisi2"
5877 [(set (match_operand:SI 0 "general_operand" "")
5879 (set (strict_low_part
5883 (match_operand:HI 1 "general_operand" ""))]
5885 "operands[1] = make_safe_from (operands[1], operands[0]);")
5889 @findex make_safe_from
5890 Here two RTL insns are generated, one to clear the entire output operand
5891 and the other to copy the input operand into its low half. This sequence
5892 is incorrect if the input operand refers to [the old value of] the output
5893 operand, so the preparation statement makes sure this isn't so. The
5894 function @code{make_safe_from} copies the @code{operands[1]} into a
5895 temporary register if it refers to @code{operands[0]}. It does this
5896 by emitting another RTL insn.
5898 Finally, a third example shows the use of an internal operand.
5899 Zero-extension on the SPUR chip is done by @code{and}-ing the result
5900 against a halfword mask. But this mask cannot be represented by a
5901 @code{const_int} because the constant value is too large to be legitimate
5902 on this machine. So it must be copied into a register with
5903 @code{force_reg} and then the register used in the @code{and}.
5906 (define_expand "zero_extendhisi2"
5907 [(set (match_operand:SI 0 "register_operand" "")
5909 (match_operand:HI 1 "register_operand" "")
5914 = force_reg (SImode, GEN_INT (65535)); ")
5917 @emph{Note:} If the @code{define_expand} is used to serve a
5918 standard binary or unary arithmetic operation or a bit-field operation,
5919 then the last insn it generates must not be a @code{code_label},
5920 @code{barrier} or @code{note}. It must be an @code{insn},
5921 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
5922 at the end, emit an insn to copy the result of the operation into
5923 itself. Such an insn will generate no code, but it can avoid problems
5928 @node Insn Splitting
5929 @section Defining How to Split Instructions
5930 @cindex insn splitting
5931 @cindex instruction splitting
5932 @cindex splitting instructions
5934 There are two cases where you should specify how to split a pattern
5935 into multiple insns. On machines that have instructions requiring
5936 delay slots (@pxref{Delay Slots}) or that have instructions whose
5937 output is not available for multiple cycles (@pxref{Processor pipeline
5938 description}), the compiler phases that optimize these cases need to
5939 be able to move insns into one-instruction delay slots. However, some
5940 insns may generate more than one machine instruction. These insns
5941 cannot be placed into a delay slot.
5943 Often you can rewrite the single insn as a list of individual insns,
5944 each corresponding to one machine instruction. The disadvantage of
5945 doing so is that it will cause the compilation to be slower and require
5946 more space. If the resulting insns are too complex, it may also
5947 suppress some optimizations. The compiler splits the insn if there is a
5948 reason to believe that it might improve instruction or delay slot
5951 The insn combiner phase also splits putative insns. If three insns are
5952 merged into one insn with a complex expression that cannot be matched by
5953 some @code{define_insn} pattern, the combiner phase attempts to split
5954 the complex pattern into two insns that are recognized. Usually it can
5955 break the complex pattern into two patterns by splitting out some
5956 subexpression. However, in some other cases, such as performing an
5957 addition of a large constant in two insns on a RISC machine, the way to
5958 split the addition into two insns is machine-dependent.
5960 @findex define_split
5961 The @code{define_split} definition tells the compiler how to split a
5962 complex insn into several simpler insns. It looks like this:
5966 [@var{insn-pattern}]
5968 [@var{new-insn-pattern-1}
5969 @var{new-insn-pattern-2}
5971 "@var{preparation-statements}")
5974 @var{insn-pattern} is a pattern that needs to be split and
5975 @var{condition} is the final condition to be tested, as in a
5976 @code{define_insn}. When an insn matching @var{insn-pattern} and
5977 satisfying @var{condition} is found, it is replaced in the insn list
5978 with the insns given by @var{new-insn-pattern-1},
5979 @var{new-insn-pattern-2}, etc.
5981 The @var{preparation-statements} are similar to those statements that
5982 are specified for @code{define_expand} (@pxref{Expander Definitions})
5983 and are executed before the new RTL is generated to prepare for the
5984 generated code or emit some insns whose pattern is not fixed. Unlike
5985 those in @code{define_expand}, however, these statements must not
5986 generate any new pseudo-registers. Once reload has completed, they also
5987 must not allocate any space in the stack frame.
5989 Patterns are matched against @var{insn-pattern} in two different
5990 circumstances. If an insn needs to be split for delay slot scheduling
5991 or insn scheduling, the insn is already known to be valid, which means
5992 that it must have been matched by some @code{define_insn} and, if
5993 @code{reload_completed} is nonzero, is known to satisfy the constraints
5994 of that @code{define_insn}. In that case, the new insn patterns must
5995 also be insns that are matched by some @code{define_insn} and, if
5996 @code{reload_completed} is nonzero, must also satisfy the constraints
5997 of those definitions.
5999 As an example of this usage of @code{define_split}, consider the following
6000 example from @file{a29k.md}, which splits a @code{sign_extend} from
6001 @code{HImode} to @code{SImode} into a pair of shift insns:
6005 [(set (match_operand:SI 0 "gen_reg_operand" "")
6006 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
6009 (ashift:SI (match_dup 1)
6012 (ashiftrt:SI (match_dup 0)
6015 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
6018 When the combiner phase tries to split an insn pattern, it is always the
6019 case that the pattern is @emph{not} matched by any @code{define_insn}.
6020 The combiner pass first tries to split a single @code{set} expression
6021 and then the same @code{set} expression inside a @code{parallel}, but
6022 followed by a @code{clobber} of a pseudo-reg to use as a scratch
6023 register. In these cases, the combiner expects exactly two new insn
6024 patterns to be generated. It will verify that these patterns match some
6025 @code{define_insn} definitions, so you need not do this test in the
6026 @code{define_split} (of course, there is no point in writing a
6027 @code{define_split} that will never produce insns that match).
6029 Here is an example of this use of @code{define_split}, taken from
6034 [(set (match_operand:SI 0 "gen_reg_operand" "")
6035 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
6036 (match_operand:SI 2 "non_add_cint_operand" "")))]
6038 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
6039 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
6042 int low = INTVAL (operands[2]) & 0xffff;
6043 int high = (unsigned) INTVAL (operands[2]) >> 16;
6046 high++, low |= 0xffff0000;
6048 operands[3] = GEN_INT (high << 16);
6049 operands[4] = GEN_INT (low);
6053 Here the predicate @code{non_add_cint_operand} matches any
6054 @code{const_int} that is @emph{not} a valid operand of a single add
6055 insn. The add with the smaller displacement is written so that it
6056 can be substituted into the address of a subsequent operation.
6058 An example that uses a scratch register, from the same file, generates
6059 an equality comparison of a register and a large constant:
6063 [(set (match_operand:CC 0 "cc_reg_operand" "")
6064 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
6065 (match_operand:SI 2 "non_short_cint_operand" "")))
6066 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
6067 "find_single_use (operands[0], insn, 0)
6068 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
6069 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
6070 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
6071 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
6074 /* @r{Get the constant we are comparing against, C, and see what it
6075 looks like sign-extended to 16 bits. Then see what constant
6076 could be XOR'ed with C to get the sign-extended value.} */
6078 int c = INTVAL (operands[2]);
6079 int sextc = (c << 16) >> 16;
6080 int xorv = c ^ sextc;
6082 operands[4] = GEN_INT (xorv);
6083 operands[5] = GEN_INT (sextc);
6087 To avoid confusion, don't write a single @code{define_split} that
6088 accepts some insns that match some @code{define_insn} as well as some
6089 insns that don't. Instead, write two separate @code{define_split}
6090 definitions, one for the insns that are valid and one for the insns that
6093 The splitter is allowed to split jump instructions into sequence of
6094 jumps or create new jumps in while splitting non-jump instructions. As
6095 the central flowgraph and branch prediction information needs to be updated,
6096 several restriction apply.
6098 Splitting of jump instruction into sequence that over by another jump
6099 instruction is always valid, as compiler expect identical behavior of new
6100 jump. When new sequence contains multiple jump instructions or new labels,
6101 more assistance is needed. Splitter is required to create only unconditional
6102 jumps, or simple conditional jump instructions. Additionally it must attach a
6103 @code{REG_BR_PROB} note to each conditional jump. A global variable
6104 @code{split_branch_probability} holds the probability of the original branch in case
6105 it was an simple conditional jump, @minus{}1 otherwise. To simplify
6106 recomputing of edge frequencies, the new sequence is required to have only
6107 forward jumps to the newly created labels.
6109 @findex define_insn_and_split
6110 For the common case where the pattern of a define_split exactly matches the
6111 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
6115 (define_insn_and_split
6116 [@var{insn-pattern}]
6118 "@var{output-template}"
6119 "@var{split-condition}"
6120 [@var{new-insn-pattern-1}
6121 @var{new-insn-pattern-2}
6123 "@var{preparation-statements}"
6124 [@var{insn-attributes}])
6128 @var{insn-pattern}, @var{condition}, @var{output-template}, and
6129 @var{insn-attributes} are used as in @code{define_insn}. The
6130 @var{new-insn-pattern} vector and the @var{preparation-statements} are used as
6131 in a @code{define_split}. The @var{split-condition} is also used as in
6132 @code{define_split}, with the additional behavior that if the condition starts
6133 with @samp{&&}, the condition used for the split will be the constructed as a
6134 logical ``and'' of the split condition with the insn condition. For example,
6138 (define_insn_and_split "zero_extendhisi2_and"
6139 [(set (match_operand:SI 0 "register_operand" "=r")
6140 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
6141 (clobber (reg:CC 17))]
6142 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
6144 "&& reload_completed"
6145 [(parallel [(set (match_dup 0)
6146 (and:SI (match_dup 0) (const_int 65535)))
6147 (clobber (reg:CC 17))])]
6149 [(set_attr "type" "alu1")])
6153 In this case, the actual split condition will be
6154 @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
6156 The @code{define_insn_and_split} construction provides exactly the same
6157 functionality as two separate @code{define_insn} and @code{define_split}
6158 patterns. It exists for compactness, and as a maintenance tool to prevent
6159 having to ensure the two patterns' templates match.
6163 @node Including Patterns
6164 @section Including Patterns in Machine Descriptions.
6165 @cindex insn includes
6168 The @code{include} pattern tells the compiler tools where to
6169 look for patterns that are in files other than in the file
6170 @file{.md}. This is used only at build time and there is no preprocessing allowed.
6184 (include "filestuff")
6188 Where @var{pathname} is a string that specifies the location of the file,
6189 specifies the include file to be in @file{gcc/config/target/filestuff}. The
6190 directory @file{gcc/config/target} is regarded as the default directory.
6193 Machine descriptions may be split up into smaller more manageable subsections
6194 and placed into subdirectories.
6200 (include "BOGUS/filestuff")
6204 the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}.
6206 Specifying an absolute path for the include file such as;
6209 (include "/u2/BOGUS/filestuff")
6212 is permitted but is not encouraged.
6214 @subsection RTL Generation Tool Options for Directory Search
6215 @cindex directory options .md
6216 @cindex options, directory search
6217 @cindex search options
6219 The @option{-I@var{dir}} option specifies directories to search for machine descriptions.
6224 genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md
6229 Add the directory @var{dir} to the head of the list of directories to be
6230 searched for header files. This can be used to override a system machine definition
6231 file, substituting your own version, since these directories are
6232 searched before the default machine description file directories. If you use more than
6233 one @option{-I} option, the directories are scanned in left-to-right
6234 order; the standard default directory come after.
6239 @node Peephole Definitions
6240 @section Machine-Specific Peephole Optimizers
6241 @cindex peephole optimizer definitions
6242 @cindex defining peephole optimizers
6244 In addition to instruction patterns the @file{md} file may contain
6245 definitions of machine-specific peephole optimizations.
6247 The combiner does not notice certain peephole optimizations when the data
6248 flow in the program does not suggest that it should try them. For example,
6249 sometimes two consecutive insns related in purpose can be combined even
6250 though the second one does not appear to use a register computed in the
6251 first one. A machine-specific peephole optimizer can detect such
6254 There are two forms of peephole definitions that may be used. The
6255 original @code{define_peephole} is run at assembly output time to
6256 match insns and substitute assembly text. Use of @code{define_peephole}
6259 A newer @code{define_peephole2} matches insns and substitutes new
6260 insns. The @code{peephole2} pass is run after register allocation
6261 but before scheduling, which may result in much better code for
6262 targets that do scheduling.
6265 * define_peephole:: RTL to Text Peephole Optimizers
6266 * define_peephole2:: RTL to RTL Peephole Optimizers
6271 @node define_peephole
6272 @subsection RTL to Text Peephole Optimizers
6273 @findex define_peephole
6276 A definition looks like this:
6280 [@var{insn-pattern-1}
6281 @var{insn-pattern-2}
6285 "@var{optional-insn-attributes}")
6289 The last string operand may be omitted if you are not using any
6290 machine-specific information in this machine description. If present,
6291 it must obey the same rules as in a @code{define_insn}.
6293 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
6294 consecutive insns. The optimization applies to a sequence of insns when
6295 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
6296 the next, and so on.
6298 Each of the insns matched by a peephole must also match a
6299 @code{define_insn}. Peepholes are checked only at the last stage just
6300 before code generation, and only optionally. Therefore, any insn which
6301 would match a peephole but no @code{define_insn} will cause a crash in code
6302 generation in an unoptimized compilation, or at various optimization
6305 The operands of the insns are matched with @code{match_operands},
6306 @code{match_operator}, and @code{match_dup}, as usual. What is not
6307 usual is that the operand numbers apply to all the insn patterns in the
6308 definition. So, you can check for identical operands in two insns by
6309 using @code{match_operand} in one insn and @code{match_dup} in the
6312 The operand constraints used in @code{match_operand} patterns do not have
6313 any direct effect on the applicability of the peephole, but they will
6314 be validated afterward, so make sure your constraints are general enough
6315 to apply whenever the peephole matches. If the peephole matches
6316 but the constraints are not satisfied, the compiler will crash.
6318 It is safe to omit constraints in all the operands of the peephole; or
6319 you can write constraints which serve as a double-check on the criteria
6322 Once a sequence of insns matches the patterns, the @var{condition} is
6323 checked. This is a C expression which makes the final decision whether to
6324 perform the optimization (we do so if the expression is nonzero). If
6325 @var{condition} is omitted (in other words, the string is empty) then the
6326 optimization is applied to every sequence of insns that matches the
6329 The defined peephole optimizations are applied after register allocation
6330 is complete. Therefore, the peephole definition can check which
6331 operands have ended up in which kinds of registers, just by looking at
6334 @findex prev_active_insn
6335 The way to refer to the operands in @var{condition} is to write
6336 @code{operands[@var{i}]} for operand number @var{i} (as matched by
6337 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
6338 to refer to the last of the insns being matched; use
6339 @code{prev_active_insn} to find the preceding insns.
6341 @findex dead_or_set_p
6342 When optimizing computations with intermediate results, you can use
6343 @var{condition} to match only when the intermediate results are not used
6344 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
6345 @var{op})}, where @var{insn} is the insn in which you expect the value
6346 to be used for the last time (from the value of @code{insn}, together
6347 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
6348 value (from @code{operands[@var{i}]}).
6350 Applying the optimization means replacing the sequence of insns with one
6351 new insn. The @var{template} controls ultimate output of assembler code
6352 for this combined insn. It works exactly like the template of a
6353 @code{define_insn}. Operand numbers in this template are the same ones
6354 used in matching the original sequence of insns.
6356 The result of a defined peephole optimizer does not need to match any of
6357 the insn patterns in the machine description; it does not even have an
6358 opportunity to match them. The peephole optimizer definition itself serves
6359 as the insn pattern to control how the insn is output.
6361 Defined peephole optimizers are run as assembler code is being output,
6362 so the insns they produce are never combined or rearranged in any way.
6364 Here is an example, taken from the 68000 machine description:
6368 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
6369 (set (match_operand:DF 0 "register_operand" "=f")
6370 (match_operand:DF 1 "register_operand" "ad"))]
6371 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
6374 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
6376 output_asm_insn ("move.l %1,(sp)", xoperands);
6377 output_asm_insn ("move.l %1,-(sp)", operands);
6378 return "fmove.d (sp)+,%0";
6380 output_asm_insn ("movel %1,sp@@", xoperands);
6381 output_asm_insn ("movel %1,sp@@-", operands);
6382 return "fmoved sp@@+,%0";
6388 The effect of this optimization is to change
6414 If a peephole matches a sequence including one or more jump insns, you must
6415 take account of the flags such as @code{CC_REVERSED} which specify that the
6416 condition codes are represented in an unusual manner. The compiler
6417 automatically alters any ordinary conditional jumps which occur in such
6418 situations, but the compiler cannot alter jumps which have been replaced by
6419 peephole optimizations. So it is up to you to alter the assembler code
6420 that the peephole produces. Supply C code to write the assembler output,
6421 and in this C code check the condition code status flags and change the
6422 assembler code as appropriate.
6425 @var{insn-pattern-1} and so on look @emph{almost} like the second
6426 operand of @code{define_insn}. There is one important difference: the
6427 second operand of @code{define_insn} consists of one or more RTX's
6428 enclosed in square brackets. Usually, there is only one: then the same
6429 action can be written as an element of a @code{define_peephole}. But
6430 when there are multiple actions in a @code{define_insn}, they are
6431 implicitly enclosed in a @code{parallel}. Then you must explicitly
6432 write the @code{parallel}, and the square brackets within it, in the
6433 @code{define_peephole}. Thus, if an insn pattern looks like this,
6436 (define_insn "divmodsi4"
6437 [(set (match_operand:SI 0 "general_operand" "=d")
6438 (div:SI (match_operand:SI 1 "general_operand" "0")
6439 (match_operand:SI 2 "general_operand" "dmsK")))
6440 (set (match_operand:SI 3 "general_operand" "=d")
6441 (mod:SI (match_dup 1) (match_dup 2)))]
6443 "divsl%.l %2,%3:%0")
6447 then the way to mention this insn in a peephole is as follows:
6453 [(set (match_operand:SI 0 "general_operand" "=d")
6454 (div:SI (match_operand:SI 1 "general_operand" "0")
6455 (match_operand:SI 2 "general_operand" "dmsK")))
6456 (set (match_operand:SI 3 "general_operand" "=d")
6457 (mod:SI (match_dup 1) (match_dup 2)))])
6464 @node define_peephole2
6465 @subsection RTL to RTL Peephole Optimizers
6466 @findex define_peephole2
6468 The @code{define_peephole2} definition tells the compiler how to
6469 substitute one sequence of instructions for another sequence,
6470 what additional scratch registers may be needed and what their
6475 [@var{insn-pattern-1}
6476 @var{insn-pattern-2}
6479 [@var{new-insn-pattern-1}
6480 @var{new-insn-pattern-2}
6482 "@var{preparation-statements}")
6485 The definition is almost identical to @code{define_split}
6486 (@pxref{Insn Splitting}) except that the pattern to match is not a
6487 single instruction, but a sequence of instructions.
6489 It is possible to request additional scratch registers for use in the
6490 output template. If appropriate registers are not free, the pattern
6491 will simply not match.
6493 @findex match_scratch
6495 Scratch registers are requested with a @code{match_scratch} pattern at
6496 the top level of the input pattern. The allocated register (initially) will
6497 be dead at the point requested within the original sequence. If the scratch
6498 is used at more than a single point, a @code{match_dup} pattern at the
6499 top level of the input pattern marks the last position in the input sequence
6500 at which the register must be available.
6502 Here is an example from the IA-32 machine description:
6506 [(match_scratch:SI 2 "r")
6507 (parallel [(set (match_operand:SI 0 "register_operand" "")
6508 (match_operator:SI 3 "arith_or_logical_operator"
6510 (match_operand:SI 1 "memory_operand" "")]))
6511 (clobber (reg:CC 17))])]
6512 "! optimize_size && ! TARGET_READ_MODIFY"
6513 [(set (match_dup 2) (match_dup 1))
6514 (parallel [(set (match_dup 0)
6515 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
6516 (clobber (reg:CC 17))])]
6521 This pattern tries to split a load from its use in the hopes that we'll be
6522 able to schedule around the memory load latency. It allocates a single
6523 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
6524 to be live only at the point just before the arithmetic.
6526 A real example requiring extended scratch lifetimes is harder to come by,
6527 so here's a silly made-up example:
6531 [(match_scratch:SI 4 "r")
6532 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
6533 (set (match_operand:SI 2 "" "") (match_dup 1))
6535 (set (match_operand:SI 3 "" "") (match_dup 1))]
6536 "/* @r{determine 1 does not overlap 0 and 2} */"
6537 [(set (match_dup 4) (match_dup 1))
6538 (set (match_dup 0) (match_dup 4))
6539 (set (match_dup 2) (match_dup 4))]
6540 (set (match_dup 3) (match_dup 4))]
6545 If we had not added the @code{(match_dup 4)} in the middle of the input
6546 sequence, it might have been the case that the register we chose at the
6547 beginning of the sequence is killed by the first or second @code{set}.
6551 @node Insn Attributes
6552 @section Instruction Attributes
6553 @cindex insn attributes
6554 @cindex instruction attributes
6556 In addition to describing the instruction supported by the target machine,
6557 the @file{md} file also defines a group of @dfn{attributes} and a set of
6558 values for each. Every generated insn is assigned a value for each attribute.
6559 One possible attribute would be the effect that the insn has on the machine's
6560 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
6561 to track the condition codes.
6564 * Defining Attributes:: Specifying attributes and their values.
6565 * Expressions:: Valid expressions for attribute values.
6566 * Tagging Insns:: Assigning attribute values to insns.
6567 * Attr Example:: An example of assigning attributes.
6568 * Insn Lengths:: Computing the length of insns.
6569 * Constant Attributes:: Defining attributes that are constant.
6570 * Delay Slots:: Defining delay slots required for a machine.
6571 * Processor pipeline description:: Specifying information for insn scheduling.
6576 @node Defining Attributes
6577 @subsection Defining Attributes and their Values
6578 @cindex defining attributes and their values
6579 @cindex attributes, defining
6582 The @code{define_attr} expression is used to define each attribute required
6583 by the target machine. It looks like:
6586 (define_attr @var{name} @var{list-of-values} @var{default})
6589 @var{name} is a string specifying the name of the attribute being defined.
6591 @var{list-of-values} is either a string that specifies a comma-separated
6592 list of values that can be assigned to the attribute, or a null string to
6593 indicate that the attribute takes numeric values.
6595 @var{default} is an attribute expression that gives the value of this
6596 attribute for insns that match patterns whose definition does not include
6597 an explicit value for this attribute. @xref{Attr Example}, for more
6598 information on the handling of defaults. @xref{Constant Attributes},
6599 for information on attributes that do not depend on any particular insn.
6602 For each defined attribute, a number of definitions are written to the
6603 @file{insn-attr.h} file. For cases where an explicit set of values is
6604 specified for an attribute, the following are defined:
6608 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
6611 An enumerated class is defined for @samp{attr_@var{name}} with
6612 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
6613 the attribute name and value are first converted to uppercase.
6616 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
6617 returns the attribute value for that insn.
6620 For example, if the following is present in the @file{md} file:
6623 (define_attr "type" "branch,fp,load,store,arith" @dots{})
6627 the following lines will be written to the file @file{insn-attr.h}.
6630 #define HAVE_ATTR_type
6631 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
6632 TYPE_STORE, TYPE_ARITH@};
6633 extern enum attr_type get_attr_type ();
6636 If the attribute takes numeric values, no @code{enum} type will be
6637 defined and the function to obtain the attribute's value will return
6640 There are attributes which are tied to a specific meaning. These
6641 attributes are not free to use for other purposes:
6645 The @code{length} attribute is used to calculate the length of emitted
6646 code chunks. This is especially important when verifying branch
6647 distances. @xref{Insn Lengths}.
6650 The @code{enabled} attribute can be defined to prevent certain
6651 alternatives of an insn definition from being used during code
6652 generation. @xref{Disable Insn Alternatives}.
6659 @subsection Attribute Expressions
6660 @cindex attribute expressions
6662 RTL expressions used to define attributes use the codes described above
6663 plus a few specific to attribute definitions, to be discussed below.
6664 Attribute value expressions must have one of the following forms:
6667 @cindex @code{const_int} and attributes
6668 @item (const_int @var{i})
6669 The integer @var{i} specifies the value of a numeric attribute. @var{i}
6670 must be non-negative.
6672 The value of a numeric attribute can be specified either with a
6673 @code{const_int}, or as an integer represented as a string in
6674 @code{const_string}, @code{eq_attr} (see below), @code{attr},
6675 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
6676 overrides on specific instructions (@pxref{Tagging Insns}).
6678 @cindex @code{const_string} and attributes
6679 @item (const_string @var{value})
6680 The string @var{value} specifies a constant attribute value.
6681 If @var{value} is specified as @samp{"*"}, it means that the default value of
6682 the attribute is to be used for the insn containing this expression.
6683 @samp{"*"} obviously cannot be used in the @var{default} expression
6684 of a @code{define_attr}.
6686 If the attribute whose value is being specified is numeric, @var{value}
6687 must be a string containing a non-negative integer (normally
6688 @code{const_int} would be used in this case). Otherwise, it must
6689 contain one of the valid values for the attribute.
6691 @cindex @code{if_then_else} and attributes
6692 @item (if_then_else @var{test} @var{true-value} @var{false-value})
6693 @var{test} specifies an attribute test, whose format is defined below.
6694 The value of this expression is @var{true-value} if @var{test} is true,
6695 otherwise it is @var{false-value}.
6697 @cindex @code{cond} and attributes
6698 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
6699 The first operand of this expression is a vector containing an even
6700 number of expressions and consisting of pairs of @var{test} and @var{value}
6701 expressions. The value of the @code{cond} expression is that of the
6702 @var{value} corresponding to the first true @var{test} expression. If
6703 none of the @var{test} expressions are true, the value of the @code{cond}
6704 expression is that of the @var{default} expression.
6707 @var{test} expressions can have one of the following forms:
6710 @cindex @code{const_int} and attribute tests
6711 @item (const_int @var{i})
6712 This test is true if @var{i} is nonzero and false otherwise.
6714 @cindex @code{not} and attributes
6715 @cindex @code{ior} and attributes
6716 @cindex @code{and} and attributes
6717 @item (not @var{test})
6718 @itemx (ior @var{test1} @var{test2})
6719 @itemx (and @var{test1} @var{test2})
6720 These tests are true if the indicated logical function is true.
6722 @cindex @code{match_operand} and attributes
6723 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
6724 This test is true if operand @var{n} of the insn whose attribute value
6725 is being determined has mode @var{m} (this part of the test is ignored
6726 if @var{m} is @code{VOIDmode}) and the function specified by the string
6727 @var{pred} returns a nonzero value when passed operand @var{n} and mode
6728 @var{m} (this part of the test is ignored if @var{pred} is the null
6731 The @var{constraints} operand is ignored and should be the null string.
6733 @cindex @code{le} and attributes
6734 @cindex @code{leu} and attributes
6735 @cindex @code{lt} and attributes
6736 @cindex @code{gt} and attributes
6737 @cindex @code{gtu} and attributes
6738 @cindex @code{ge} and attributes
6739 @cindex @code{geu} and attributes
6740 @cindex @code{ne} and attributes
6741 @cindex @code{eq} and attributes
6742 @cindex @code{plus} and attributes
6743 @cindex @code{minus} and attributes
6744 @cindex @code{mult} and attributes
6745 @cindex @code{div} and attributes
6746 @cindex @code{mod} and attributes
6747 @cindex @code{abs} and attributes
6748 @cindex @code{neg} and attributes
6749 @cindex @code{ashift} and attributes
6750 @cindex @code{lshiftrt} and attributes
6751 @cindex @code{ashiftrt} and attributes
6752 @item (le @var{arith1} @var{arith2})
6753 @itemx (leu @var{arith1} @var{arith2})
6754 @itemx (lt @var{arith1} @var{arith2})
6755 @itemx (ltu @var{arith1} @var{arith2})
6756 @itemx (gt @var{arith1} @var{arith2})
6757 @itemx (gtu @var{arith1} @var{arith2})
6758 @itemx (ge @var{arith1} @var{arith2})
6759 @itemx (geu @var{arith1} @var{arith2})
6760 @itemx (ne @var{arith1} @var{arith2})
6761 @itemx (eq @var{arith1} @var{arith2})
6762 These tests are true if the indicated comparison of the two arithmetic
6763 expressions is true. Arithmetic expressions are formed with
6764 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
6765 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
6766 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
6769 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
6770 Lengths},for additional forms). @code{symbol_ref} is a string
6771 denoting a C expression that yields an @code{int} when evaluated by the
6772 @samp{get_attr_@dots{}} routine. It should normally be a global
6776 @item (eq_attr @var{name} @var{value})
6777 @var{name} is a string specifying the name of an attribute.
6779 @var{value} is a string that is either a valid value for attribute
6780 @var{name}, a comma-separated list of values, or @samp{!} followed by a
6781 value or list. If @var{value} does not begin with a @samp{!}, this
6782 test is true if the value of the @var{name} attribute of the current
6783 insn is in the list specified by @var{value}. If @var{value} begins
6784 with a @samp{!}, this test is true if the attribute's value is
6785 @emph{not} in the specified list.
6790 (eq_attr "type" "load,store")
6797 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
6800 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
6801 value of the compiler variable @code{which_alternative}
6802 (@pxref{Output Statement}) and the values must be small integers. For
6806 (eq_attr "alternative" "2,3")
6813 (ior (eq (symbol_ref "which_alternative") (const_int 2))
6814 (eq (symbol_ref "which_alternative") (const_int 3)))
6817 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
6818 where the value of the attribute being tested is known for all insns matching
6819 a particular pattern. This is by far the most common case.
6822 @item (attr_flag @var{name})
6823 The value of an @code{attr_flag} expression is true if the flag
6824 specified by @var{name} is true for the @code{insn} currently being
6827 @var{name} is a string specifying one of a fixed set of flags to test.
6828 Test the flags @code{forward} and @code{backward} to determine the
6829 direction of a conditional branch. Test the flags @code{very_likely},
6830 @code{likely}, @code{very_unlikely}, and @code{unlikely} to determine
6831 if a conditional branch is expected to be taken.
6833 If the @code{very_likely} flag is true, then the @code{likely} flag is also
6834 true. Likewise for the @code{very_unlikely} and @code{unlikely} flags.
6836 This example describes a conditional branch delay slot which
6837 can be nullified for forward branches that are taken (annul-true) or
6838 for backward branches which are not taken (annul-false).
6841 (define_delay (eq_attr "type" "cbranch")
6842 [(eq_attr "in_branch_delay" "true")
6843 (and (eq_attr "in_branch_delay" "true")
6844 (attr_flag "forward"))
6845 (and (eq_attr "in_branch_delay" "true")
6846 (attr_flag "backward"))])
6849 The @code{forward} and @code{backward} flags are false if the current
6850 @code{insn} being scheduled is not a conditional branch.
6852 The @code{very_likely} and @code{likely} flags are true if the
6853 @code{insn} being scheduled is not a conditional branch.
6854 The @code{very_unlikely} and @code{unlikely} flags are false if the
6855 @code{insn} being scheduled is not a conditional branch.
6857 @code{attr_flag} is only used during delay slot scheduling and has no
6858 meaning to other passes of the compiler.
6861 @item (attr @var{name})
6862 The value of another attribute is returned. This is most useful
6863 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
6864 produce more efficient code for non-numeric attributes.
6870 @subsection Assigning Attribute Values to Insns
6871 @cindex tagging insns
6872 @cindex assigning attribute values to insns
6874 The value assigned to an attribute of an insn is primarily determined by
6875 which pattern is matched by that insn (or which @code{define_peephole}
6876 generated it). Every @code{define_insn} and @code{define_peephole} can
6877 have an optional last argument to specify the values of attributes for
6878 matching insns. The value of any attribute not specified in a particular
6879 insn is set to the default value for that attribute, as specified in its
6880 @code{define_attr}. Extensive use of default values for attributes
6881 permits the specification of the values for only one or two attributes
6882 in the definition of most insn patterns, as seen in the example in the
6885 The optional last argument of @code{define_insn} and
6886 @code{define_peephole} is a vector of expressions, each of which defines
6887 the value for a single attribute. The most general way of assigning an
6888 attribute's value is to use a @code{set} expression whose first operand is an
6889 @code{attr} expression giving the name of the attribute being set. The
6890 second operand of the @code{set} is an attribute expression
6891 (@pxref{Expressions}) giving the value of the attribute.
6893 When the attribute value depends on the @samp{alternative} attribute
6894 (i.e., which is the applicable alternative in the constraint of the
6895 insn), the @code{set_attr_alternative} expression can be used. It
6896 allows the specification of a vector of attribute expressions, one for
6900 When the generality of arbitrary attribute expressions is not required,
6901 the simpler @code{set_attr} expression can be used, which allows
6902 specifying a string giving either a single attribute value or a list
6903 of attribute values, one for each alternative.
6905 The form of each of the above specifications is shown below. In each case,
6906 @var{name} is a string specifying the attribute to be set.
6909 @item (set_attr @var{name} @var{value-string})
6910 @var{value-string} is either a string giving the desired attribute value,
6911 or a string containing a comma-separated list giving the values for
6912 succeeding alternatives. The number of elements must match the number
6913 of alternatives in the constraint of the insn pattern.
6915 Note that it may be useful to specify @samp{*} for some alternative, in
6916 which case the attribute will assume its default value for insns matching
6919 @findex set_attr_alternative
6920 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
6921 Depending on the alternative of the insn, the value will be one of the
6922 specified values. This is a shorthand for using a @code{cond} with
6923 tests on the @samp{alternative} attribute.
6926 @item (set (attr @var{name}) @var{value})
6927 The first operand of this @code{set} must be the special RTL expression
6928 @code{attr}, whose sole operand is a string giving the name of the
6929 attribute being set. @var{value} is the value of the attribute.
6932 The following shows three different ways of representing the same
6933 attribute value specification:
6936 (set_attr "type" "load,store,arith")
6938 (set_attr_alternative "type"
6939 [(const_string "load") (const_string "store")
6940 (const_string "arith")])
6943 (cond [(eq_attr "alternative" "1") (const_string "load")
6944 (eq_attr "alternative" "2") (const_string "store")]
6945 (const_string "arith")))
6949 @findex define_asm_attributes
6950 The @code{define_asm_attributes} expression provides a mechanism to
6951 specify the attributes assigned to insns produced from an @code{asm}
6952 statement. It has the form:
6955 (define_asm_attributes [@var{attr-sets}])
6959 where @var{attr-sets} is specified the same as for both the
6960 @code{define_insn} and the @code{define_peephole} expressions.
6962 These values will typically be the ``worst case'' attribute values. For
6963 example, they might indicate that the condition code will be clobbered.
6965 A specification for a @code{length} attribute is handled specially. The
6966 way to compute the length of an @code{asm} insn is to multiply the
6967 length specified in the expression @code{define_asm_attributes} by the
6968 number of machine instructions specified in the @code{asm} statement,
6969 determined by counting the number of semicolons and newlines in the
6970 string. Therefore, the value of the @code{length} attribute specified
6971 in a @code{define_asm_attributes} should be the maximum possible length
6972 of a single machine instruction.
6977 @subsection Example of Attribute Specifications
6978 @cindex attribute specifications example
6979 @cindex attribute specifications
6981 The judicious use of defaulting is important in the efficient use of
6982 insn attributes. Typically, insns are divided into @dfn{types} and an
6983 attribute, customarily called @code{type}, is used to represent this
6984 value. This attribute is normally used only to define the default value
6985 for other attributes. An example will clarify this usage.
6987 Assume we have a RISC machine with a condition code and in which only
6988 full-word operations are performed in registers. Let us assume that we
6989 can divide all insns into loads, stores, (integer) arithmetic
6990 operations, floating point operations, and branches.
6992 Here we will concern ourselves with determining the effect of an insn on
6993 the condition code and will limit ourselves to the following possible
6994 effects: The condition code can be set unpredictably (clobbered), not
6995 be changed, be set to agree with the results of the operation, or only
6996 changed if the item previously set into the condition code has been
6999 Here is part of a sample @file{md} file for such a machine:
7002 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
7004 (define_attr "cc" "clobber,unchanged,set,change0"
7005 (cond [(eq_attr "type" "load")
7006 (const_string "change0")
7007 (eq_attr "type" "store,branch")
7008 (const_string "unchanged")
7009 (eq_attr "type" "arith")
7010 (if_then_else (match_operand:SI 0 "" "")
7011 (const_string "set")
7012 (const_string "clobber"))]
7013 (const_string "clobber")))
7016 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
7017 (match_operand:SI 1 "general_operand" "r,m,r"))]
7023 [(set_attr "type" "arith,load,store")])
7026 Note that we assume in the above example that arithmetic operations
7027 performed on quantities smaller than a machine word clobber the condition
7028 code since they will set the condition code to a value corresponding to the
7034 @subsection Computing the Length of an Insn
7035 @cindex insn lengths, computing
7036 @cindex computing the length of an insn
7038 For many machines, multiple types of branch instructions are provided, each
7039 for different length branch displacements. In most cases, the assembler
7040 will choose the correct instruction to use. However, when the assembler
7041 cannot do so, GCC can when a special attribute, the @code{length}
7042 attribute, is defined. This attribute must be defined to have numeric
7043 values by specifying a null string in its @code{define_attr}.
7045 In the case of the @code{length} attribute, two additional forms of
7046 arithmetic terms are allowed in test expressions:
7049 @cindex @code{match_dup} and attributes
7050 @item (match_dup @var{n})
7051 This refers to the address of operand @var{n} of the current insn, which
7052 must be a @code{label_ref}.
7054 @cindex @code{pc} and attributes
7056 This refers to the address of the @emph{current} insn. It might have
7057 been more consistent with other usage to make this the address of the
7058 @emph{next} insn but this would be confusing because the length of the
7059 current insn is to be computed.
7062 @cindex @code{addr_vec}, length of
7063 @cindex @code{addr_diff_vec}, length of
7064 For normal insns, the length will be determined by value of the
7065 @code{length} attribute. In the case of @code{addr_vec} and
7066 @code{addr_diff_vec} insn patterns, the length is computed as
7067 the number of vectors multiplied by the size of each vector.
7069 Lengths are measured in addressable storage units (bytes).
7071 The following macros can be used to refine the length computation:
7074 @findex ADJUST_INSN_LENGTH
7075 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
7076 If defined, modifies the length assigned to instruction @var{insn} as a
7077 function of the context in which it is used. @var{length} is an lvalue
7078 that contains the initially computed length of the insn and should be
7079 updated with the correct length of the insn.
7081 This macro will normally not be required. A case in which it is
7082 required is the ROMP@. On this machine, the size of an @code{addr_vec}
7083 insn must be increased by two to compensate for the fact that alignment
7087 @findex get_attr_length
7088 The routine that returns @code{get_attr_length} (the value of the
7089 @code{length} attribute) can be used by the output routine to
7090 determine the form of the branch instruction to be written, as the
7091 example below illustrates.
7093 As an example of the specification of variable-length branches, consider
7094 the IBM 360. If we adopt the convention that a register will be set to
7095 the starting address of a function, we can jump to labels within 4k of
7096 the start using a four-byte instruction. Otherwise, we need a six-byte
7097 sequence to load the address from memory and then branch to it.
7099 On such a machine, a pattern for a branch instruction might be specified
7105 (label_ref (match_operand 0 "" "")))]
7108 return (get_attr_length (insn) == 4
7109 ? "b %l0" : "l r15,=a(%l0); br r15");
7111 [(set (attr "length")
7112 (if_then_else (lt (match_dup 0) (const_int 4096))
7119 @node Constant Attributes
7120 @subsection Constant Attributes
7121 @cindex constant attributes
7123 A special form of @code{define_attr}, where the expression for the
7124 default value is a @code{const} expression, indicates an attribute that
7125 is constant for a given run of the compiler. Constant attributes may be
7126 used to specify which variety of processor is used. For example,
7129 (define_attr "cpu" "m88100,m88110,m88000"
7131 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
7132 (symbol_ref "TARGET_88110") (const_string "m88110")]
7133 (const_string "m88000"))))
7135 (define_attr "memory" "fast,slow"
7137 (if_then_else (symbol_ref "TARGET_FAST_MEM")
7138 (const_string "fast")
7139 (const_string "slow"))))
7142 The routine generated for constant attributes has no parameters as it
7143 does not depend on any particular insn. RTL expressions used to define
7144 the value of a constant attribute may use the @code{symbol_ref} form,
7145 but may not use either the @code{match_operand} form or @code{eq_attr}
7146 forms involving insn attributes.
7151 @subsection Delay Slot Scheduling
7152 @cindex delay slots, defining
7154 The insn attribute mechanism can be used to specify the requirements for
7155 delay slots, if any, on a target machine. An instruction is said to
7156 require a @dfn{delay slot} if some instructions that are physically
7157 after the instruction are executed as if they were located before it.
7158 Classic examples are branch and call instructions, which often execute
7159 the following instruction before the branch or call is performed.
7161 On some machines, conditional branch instructions can optionally
7162 @dfn{annul} instructions in the delay slot. This means that the
7163 instruction will not be executed for certain branch outcomes. Both
7164 instructions that annul if the branch is true and instructions that
7165 annul if the branch is false are supported.
7167 Delay slot scheduling differs from instruction scheduling in that
7168 determining whether an instruction needs a delay slot is dependent only
7169 on the type of instruction being generated, not on data flow between the
7170 instructions. See the next section for a discussion of data-dependent
7171 instruction scheduling.
7173 @findex define_delay
7174 The requirement of an insn needing one or more delay slots is indicated
7175 via the @code{define_delay} expression. It has the following form:
7178 (define_delay @var{test}
7179 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
7180 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
7184 @var{test} is an attribute test that indicates whether this
7185 @code{define_delay} applies to a particular insn. If so, the number of
7186 required delay slots is determined by the length of the vector specified
7187 as the second argument. An insn placed in delay slot @var{n} must
7188 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
7189 attribute test that specifies which insns may be annulled if the branch
7190 is true. Similarly, @var{annul-false-n} specifies which insns in the
7191 delay slot may be annulled if the branch is false. If annulling is not
7192 supported for that delay slot, @code{(nil)} should be coded.
7194 For example, in the common case where branch and call insns require
7195 a single delay slot, which may contain any insn other than a branch or
7196 call, the following would be placed in the @file{md} file:
7199 (define_delay (eq_attr "type" "branch,call")
7200 [(eq_attr "type" "!branch,call") (nil) (nil)])
7203 Multiple @code{define_delay} expressions may be specified. In this
7204 case, each such expression specifies different delay slot requirements
7205 and there must be no insn for which tests in two @code{define_delay}
7206 expressions are both true.
7208 For example, if we have a machine that requires one delay slot for branches
7209 but two for calls, no delay slot can contain a branch or call insn,
7210 and any valid insn in the delay slot for the branch can be annulled if the
7211 branch is true, we might represent this as follows:
7214 (define_delay (eq_attr "type" "branch")
7215 [(eq_attr "type" "!branch,call")
7216 (eq_attr "type" "!branch,call")
7219 (define_delay (eq_attr "type" "call")
7220 [(eq_attr "type" "!branch,call") (nil) (nil)
7221 (eq_attr "type" "!branch,call") (nil) (nil)])
7223 @c the above is *still* too long. --mew 4feb93
7227 @node Processor pipeline description
7228 @subsection Specifying processor pipeline description
7229 @cindex processor pipeline description
7230 @cindex processor functional units
7231 @cindex instruction latency time
7232 @cindex interlock delays
7233 @cindex data dependence delays
7234 @cindex reservation delays
7235 @cindex pipeline hazard recognizer
7236 @cindex automaton based pipeline description
7237 @cindex regular expressions
7238 @cindex deterministic finite state automaton
7239 @cindex automaton based scheduler
7243 To achieve better performance, most modern processors
7244 (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW}
7245 processors) have many @dfn{functional units} on which several
7246 instructions can be executed simultaneously. An instruction starts
7247 execution if its issue conditions are satisfied. If not, the
7248 instruction is stalled until its conditions are satisfied. Such
7249 @dfn{interlock (pipeline) delay} causes interruption of the fetching
7250 of successor instructions (or demands nop instructions, e.g.@: for some
7253 There are two major kinds of interlock delays in modern processors.
7254 The first one is a data dependence delay determining @dfn{instruction
7255 latency time}. The instruction execution is not started until all
7256 source data have been evaluated by prior instructions (there are more
7257 complex cases when the instruction execution starts even when the data
7258 are not available but will be ready in given time after the
7259 instruction execution start). Taking the data dependence delays into
7260 account is simple. The data dependence (true, output, and
7261 anti-dependence) delay between two instructions is given by a
7262 constant. In most cases this approach is adequate. The second kind
7263 of interlock delays is a reservation delay. The reservation delay
7264 means that two instructions under execution will be in need of shared
7265 processors resources, i.e.@: buses, internal registers, and/or
7266 functional units, which are reserved for some time. Taking this kind
7267 of delay into account is complex especially for modern @acronym{RISC}
7270 The task of exploiting more processor parallelism is solved by an
7271 instruction scheduler. For a better solution to this problem, the
7272 instruction scheduler has to have an adequate description of the
7273 processor parallelism (or @dfn{pipeline description}). GCC
7274 machine descriptions describe processor parallelism and functional
7275 unit reservations for groups of instructions with the aid of
7276 @dfn{regular expressions}.
7278 The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to
7279 figure out the possibility of the instruction issue by the processor
7280 on a given simulated processor cycle. The pipeline hazard recognizer is
7281 automatically generated from the processor pipeline description. The
7282 pipeline hazard recognizer generated from the machine description
7283 is based on a deterministic finite state automaton (@acronym{DFA}):
7284 the instruction issue is possible if there is a transition from one
7285 automaton state to another one. This algorithm is very fast, and
7286 furthermore, its speed is not dependent on processor
7287 complexity@footnote{However, the size of the automaton depends on
7288 processor complexity. To limit this effect, machine descriptions
7289 can split orthogonal parts of the machine description among several
7290 automata: but then, since each of these must be stepped independently,
7291 this does cause a small decrease in the algorithm's performance.}.
7293 @cindex automaton based pipeline description
7294 The rest of this section describes the directives that constitute
7295 an automaton-based processor pipeline description. The order of
7296 these constructions within the machine description file is not
7299 @findex define_automaton
7300 @cindex pipeline hazard recognizer
7301 The following optional construction describes names of automata
7302 generated and used for the pipeline hazards recognition. Sometimes
7303 the generated finite state automaton used by the pipeline hazard
7304 recognizer is large. If we use more than one automaton and bind functional
7305 units to the automata, the total size of the automata is usually
7306 less than the size of the single automaton. If there is no one such
7307 construction, only one finite state automaton is generated.
7310 (define_automaton @var{automata-names})
7313 @var{automata-names} is a string giving names of the automata. The
7314 names are separated by commas. All the automata should have unique names.
7315 The automaton name is used in the constructions @code{define_cpu_unit} and
7316 @code{define_query_cpu_unit}.
7318 @findex define_cpu_unit
7319 @cindex processor functional units
7320 Each processor functional unit used in the description of instruction
7321 reservations should be described by the following construction.
7324 (define_cpu_unit @var{unit-names} [@var{automaton-name}])
7327 @var{unit-names} is a string giving the names of the functional units
7328 separated by commas. Don't use name @samp{nothing}, it is reserved
7331 @var{automaton-name} is a string giving the name of the automaton with
7332 which the unit is bound. The automaton should be described in
7333 construction @code{define_automaton}. You should give
7334 @dfn{automaton-name}, if there is a defined automaton.
7336 The assignment of units to automata are constrained by the uses of the
7337 units in insn reservations. The most important constraint is: if a
7338 unit reservation is present on a particular cycle of an alternative
7339 for an insn reservation, then some unit from the same automaton must
7340 be present on the same cycle for the other alternatives of the insn
7341 reservation. The rest of the constraints are mentioned in the
7342 description of the subsequent constructions.
7344 @findex define_query_cpu_unit
7345 @cindex querying function unit reservations
7346 The following construction describes CPU functional units analogously
7347 to @code{define_cpu_unit}. The reservation of such units can be
7348 queried for an automaton state. The instruction scheduler never
7349 queries reservation of functional units for given automaton state. So
7350 as a rule, you don't need this construction. This construction could
7351 be used for future code generation goals (e.g.@: to generate
7352 @acronym{VLIW} insn templates).
7355 (define_query_cpu_unit @var{unit-names} [@var{automaton-name}])
7358 @var{unit-names} is a string giving names of the functional units
7359 separated by commas.
7361 @var{automaton-name} is a string giving the name of the automaton with
7362 which the unit is bound.
7364 @findex define_insn_reservation
7365 @cindex instruction latency time
7366 @cindex regular expressions
7368 The following construction is the major one to describe pipeline
7369 characteristics of an instruction.
7372 (define_insn_reservation @var{insn-name} @var{default_latency}
7373 @var{condition} @var{regexp})
7376 @var{default_latency} is a number giving latency time of the
7377 instruction. There is an important difference between the old
7378 description and the automaton based pipeline description. The latency
7379 time is used for all dependencies when we use the old description. In
7380 the automaton based pipeline description, the given latency time is only
7381 used for true dependencies. The cost of anti-dependencies is always
7382 zero and the cost of output dependencies is the difference between
7383 latency times of the producing and consuming insns (if the difference
7384 is negative, the cost is considered to be zero). You can always
7385 change the default costs for any description by using the target hook
7386 @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}).
7388 @var{insn-name} is a string giving the internal name of the insn. The
7389 internal names are used in constructions @code{define_bypass} and in
7390 the automaton description file generated for debugging. The internal
7391 name has nothing in common with the names in @code{define_insn}. It is a
7392 good practice to use insn classes described in the processor manual.
7394 @var{condition} defines what RTL insns are described by this
7395 construction. You should remember that you will be in trouble if
7396 @var{condition} for two or more different
7397 @code{define_insn_reservation} constructions is TRUE for an insn. In
7398 this case what reservation will be used for the insn is not defined.
7399 Such cases are not checked during generation of the pipeline hazards
7400 recognizer because in general recognizing that two conditions may have
7401 the same value is quite difficult (especially if the conditions
7402 contain @code{symbol_ref}). It is also not checked during the
7403 pipeline hazard recognizer work because it would slow down the
7404 recognizer considerably.
7406 @var{regexp} is a string describing the reservation of the cpu's functional
7407 units by the instruction. The reservations are described by a regular
7408 expression according to the following syntax:
7411 regexp = regexp "," oneof
7414 oneof = oneof "|" allof
7417 allof = allof "+" repeat
7420 repeat = element "*" number
7423 element = cpu_function_unit_name
7432 @samp{,} is used for describing the start of the next cycle in
7436 @samp{|} is used for describing a reservation described by the first
7437 regular expression @strong{or} a reservation described by the second
7438 regular expression @strong{or} etc.
7441 @samp{+} is used for describing a reservation described by the first
7442 regular expression @strong{and} a reservation described by the
7443 second regular expression @strong{and} etc.
7446 @samp{*} is used for convenience and simply means a sequence in which
7447 the regular expression are repeated @var{number} times with cycle
7448 advancing (see @samp{,}).
7451 @samp{cpu_function_unit_name} denotes reservation of the named
7455 @samp{reservation_name} --- see description of construction
7456 @samp{define_reservation}.
7459 @samp{nothing} denotes no unit reservations.
7462 @findex define_reservation
7463 Sometimes unit reservations for different insns contain common parts.
7464 In such case, you can simplify the pipeline description by describing
7465 the common part by the following construction
7468 (define_reservation @var{reservation-name} @var{regexp})
7471 @var{reservation-name} is a string giving name of @var{regexp}.
7472 Functional unit names and reservation names are in the same name
7473 space. So the reservation names should be different from the
7474 functional unit names and can not be the reserved name @samp{nothing}.
7476 @findex define_bypass
7477 @cindex instruction latency time
7479 The following construction is used to describe exceptions in the
7480 latency time for given instruction pair. This is so called bypasses.
7483 (define_bypass @var{number} @var{out_insn_names} @var{in_insn_names}
7487 @var{number} defines when the result generated by the instructions
7488 given in string @var{out_insn_names} will be ready for the
7489 instructions given in string @var{in_insn_names}. The instructions in
7490 the string are separated by commas.
7492 @var{guard} is an optional string giving the name of a C function which
7493 defines an additional guard for the bypass. The function will get the
7494 two insns as parameters. If the function returns zero the bypass will
7495 be ignored for this case. The additional guard is necessary to
7496 recognize complicated bypasses, e.g.@: when the consumer is only an address
7497 of insn @samp{store} (not a stored value).
7499 @findex exclusion_set
7500 @findex presence_set
7501 @findex final_presence_set
7503 @findex final_absence_set
7506 The following five constructions are usually used to describe
7507 @acronym{VLIW} processors, or more precisely, to describe a placement
7508 of small instructions into @acronym{VLIW} instruction slots. They
7509 can be used for @acronym{RISC} processors, too.
7512 (exclusion_set @var{unit-names} @var{unit-names})
7513 (presence_set @var{unit-names} @var{patterns})
7514 (final_presence_set @var{unit-names} @var{patterns})
7515 (absence_set @var{unit-names} @var{patterns})
7516 (final_absence_set @var{unit-names} @var{patterns})
7519 @var{unit-names} is a string giving names of functional units
7520 separated by commas.
7522 @var{patterns} is a string giving patterns of functional units
7523 separated by comma. Currently pattern is one unit or units
7524 separated by white-spaces.
7526 The first construction (@samp{exclusion_set}) means that each
7527 functional unit in the first string can not be reserved simultaneously
7528 with a unit whose name is in the second string and vice versa. For
7529 example, the construction is useful for describing processors
7530 (e.g.@: some SPARC processors) with a fully pipelined floating point
7531 functional unit which can execute simultaneously only single floating
7532 point insns or only double floating point insns.
7534 The second construction (@samp{presence_set}) means that each
7535 functional unit in the first string can not be reserved unless at
7536 least one of pattern of units whose names are in the second string is
7537 reserved. This is an asymmetric relation. For example, it is useful
7538 for description that @acronym{VLIW} @samp{slot1} is reserved after
7539 @samp{slot0} reservation. We could describe it by the following
7543 (presence_set "slot1" "slot0")
7546 Or @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0}
7547 reservation. In this case we could write
7550 (presence_set "slot1" "slot0 b0")
7553 The third construction (@samp{final_presence_set}) is analogous to
7554 @samp{presence_set}. The difference between them is when checking is
7555 done. When an instruction is issued in given automaton state
7556 reflecting all current and planned unit reservations, the automaton
7557 state is changed. The first state is a source state, the second one
7558 is a result state. Checking for @samp{presence_set} is done on the
7559 source state reservation, checking for @samp{final_presence_set} is
7560 done on the result reservation. This construction is useful to
7561 describe a reservation which is actually two subsequent reservations.
7562 For example, if we use
7565 (presence_set "slot1" "slot0")
7568 the following insn will be never issued (because @samp{slot1} requires
7569 @samp{slot0} which is absent in the source state).
7572 (define_reservation "insn_and_nop" "slot0 + slot1")
7575 but it can be issued if we use analogous @samp{final_presence_set}.
7577 The forth construction (@samp{absence_set}) means that each functional
7578 unit in the first string can be reserved only if each pattern of units
7579 whose names are in the second string is not reserved. This is an
7580 asymmetric relation (actually @samp{exclusion_set} is analogous to
7581 this one but it is symmetric). For example it might be useful in a
7582 @acronym{VLIW} description to say that @samp{slot0} cannot be reserved
7583 after either @samp{slot1} or @samp{slot2} have been reserved. This
7584 can be described as:
7587 (absence_set "slot0" "slot1, slot2")
7590 Or @samp{slot2} can not be reserved if @samp{slot0} and unit @samp{b0}
7591 are reserved or @samp{slot1} and unit @samp{b1} are reserved. In
7592 this case we could write
7595 (absence_set "slot2" "slot0 b0, slot1 b1")
7598 All functional units mentioned in a set should belong to the same
7601 The last construction (@samp{final_absence_set}) is analogous to
7602 @samp{absence_set} but checking is done on the result (state)
7603 reservation. See comments for @samp{final_presence_set}.
7605 @findex automata_option
7606 @cindex deterministic finite state automaton
7607 @cindex nondeterministic finite state automaton
7608 @cindex finite state automaton minimization
7609 You can control the generator of the pipeline hazard recognizer with
7610 the following construction.
7613 (automata_option @var{options})
7616 @var{options} is a string giving options which affect the generated
7617 code. Currently there are the following options:
7621 @dfn{no-minimization} makes no minimization of the automaton. This is
7622 only worth to do when we are debugging the description and need to
7623 look more accurately at reservations of states.
7626 @dfn{time} means printing time statistics about the generation of
7630 @dfn{stats} means printing statistics about the generated automata
7631 such as the number of DFA states, NDFA states and arcs.
7634 @dfn{v} means a generation of the file describing the result automata.
7635 The file has suffix @samp{.dfa} and can be used for the description
7636 verification and debugging.
7639 @dfn{w} means a generation of warning instead of error for
7640 non-critical errors.
7643 @dfn{ndfa} makes nondeterministic finite state automata. This affects
7644 the treatment of operator @samp{|} in the regular expressions. The
7645 usual treatment of the operator is to try the first alternative and,
7646 if the reservation is not possible, the second alternative. The
7647 nondeterministic treatment means trying all alternatives, some of them
7648 may be rejected by reservations in the subsequent insns.
7651 @dfn{progress} means output of a progress bar showing how many states
7652 were generated so far for automaton being processed. This is useful
7653 during debugging a @acronym{DFA} description. If you see too many
7654 generated states, you could interrupt the generator of the pipeline
7655 hazard recognizer and try to figure out a reason for generation of the
7659 As an example, consider a superscalar @acronym{RISC} machine which can
7660 issue three insns (two integer insns and one floating point insn) on
7661 the cycle but can finish only two insns. To describe this, we define
7662 the following functional units.
7665 (define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline")
7666 (define_cpu_unit "port0, port1")
7669 All simple integer insns can be executed in any integer pipeline and
7670 their result is ready in two cycles. The simple integer insns are
7671 issued into the first pipeline unless it is reserved, otherwise they
7672 are issued into the second pipeline. Integer division and
7673 multiplication insns can be executed only in the second integer
7674 pipeline and their results are ready correspondingly in 8 and 4
7675 cycles. The integer division is not pipelined, i.e.@: the subsequent
7676 integer division insn can not be issued until the current division
7677 insn finished. Floating point insns are fully pipelined and their
7678 results are ready in 3 cycles. Where the result of a floating point
7679 insn is used by an integer insn, an additional delay of one cycle is
7680 incurred. To describe all of this we could specify
7683 (define_cpu_unit "div")
7685 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
7686 "(i0_pipeline | i1_pipeline), (port0 | port1)")
7688 (define_insn_reservation "mult" 4 (eq_attr "type" "mult")
7689 "i1_pipeline, nothing*2, (port0 | port1)")
7691 (define_insn_reservation "div" 8 (eq_attr "type" "div")
7692 "i1_pipeline, div*7, div + (port0 | port1)")
7694 (define_insn_reservation "float" 3 (eq_attr "type" "float")
7695 "f_pipeline, nothing, (port0 | port1))
7697 (define_bypass 4 "float" "simple,mult,div")
7700 To simplify the description we could describe the following reservation
7703 (define_reservation "finish" "port0|port1")
7706 and use it in all @code{define_insn_reservation} as in the following
7710 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
7711 "(i0_pipeline | i1_pipeline), finish")
7717 @node Conditional Execution
7718 @section Conditional Execution
7719 @cindex conditional execution
7722 A number of architectures provide for some form of conditional
7723 execution, or predication. The hallmark of this feature is the
7724 ability to nullify most of the instructions in the instruction set.
7725 When the instruction set is large and not entirely symmetric, it
7726 can be quite tedious to describe these forms directly in the
7727 @file{.md} file. An alternative is the @code{define_cond_exec} template.
7729 @findex define_cond_exec
7732 [@var{predicate-pattern}]
7734 "@var{output-template}")
7737 @var{predicate-pattern} is the condition that must be true for the
7738 insn to be executed at runtime and should match a relational operator.
7739 One can use @code{match_operator} to match several relational operators
7740 at once. Any @code{match_operand} operands must have no more than one
7743 @var{condition} is a C expression that must be true for the generated
7746 @findex current_insn_predicate
7747 @var{output-template} is a string similar to the @code{define_insn}
7748 output template (@pxref{Output Template}), except that the @samp{*}
7749 and @samp{@@} special cases do not apply. This is only useful if the
7750 assembly text for the predicate is a simple prefix to the main insn.
7751 In order to handle the general case, there is a global variable
7752 @code{current_insn_predicate} that will contain the entire predicate
7753 if the current insn is predicated, and will otherwise be @code{NULL}.
7755 When @code{define_cond_exec} is used, an implicit reference to
7756 the @code{predicable} instruction attribute is made.
7757 @xref{Insn Attributes}. This attribute must be boolean (i.e.@: have
7758 exactly two elements in its @var{list-of-values}). Further, it must
7759 not be used with complex expressions. That is, the default and all
7760 uses in the insns must be a simple constant, not dependent on the
7761 alternative or anything else.
7763 For each @code{define_insn} for which the @code{predicable}
7764 attribute is true, a new @code{define_insn} pattern will be
7765 generated that matches a predicated version of the instruction.
7769 (define_insn "addsi"
7770 [(set (match_operand:SI 0 "register_operand" "r")
7771 (plus:SI (match_operand:SI 1 "register_operand" "r")
7772 (match_operand:SI 2 "register_operand" "r")))]
7777 [(ne (match_operand:CC 0 "register_operand" "c")
7784 generates a new pattern
7789 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
7790 (set (match_operand:SI 0 "register_operand" "r")
7791 (plus:SI (match_operand:SI 1 "register_operand" "r")
7792 (match_operand:SI 2 "register_operand" "r"))))]
7793 "(@var{test2}) && (@var{test1})"
7794 "(%3) add %2,%1,%0")
7799 @node Constant Definitions
7800 @section Constant Definitions
7801 @cindex constant definitions
7802 @findex define_constants
7804 Using literal constants inside instruction patterns reduces legibility and
7805 can be a maintenance problem.
7807 To overcome this problem, you may use the @code{define_constants}
7808 expression. It contains a vector of name-value pairs. From that
7809 point on, wherever any of the names appears in the MD file, it is as
7810 if the corresponding value had been written instead. You may use
7811 @code{define_constants} multiple times; each appearance adds more
7812 constants to the table. It is an error to redefine a constant with
7815 To come back to the a29k load multiple example, instead of
7819 [(match_parallel 0 "load_multiple_operation"
7820 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
7821 (match_operand:SI 2 "memory_operand" "m"))
7823 (clobber (reg:SI 179))])]
7839 [(match_parallel 0 "load_multiple_operation"
7840 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
7841 (match_operand:SI 2 "memory_operand" "m"))
7843 (clobber (reg:SI R_CR))])]
7848 The constants that are defined with a define_constant are also output
7849 in the insn-codes.h header file as #defines.
7854 @cindex iterators in @file{.md} files
7856 Ports often need to define similar patterns for more than one machine
7857 mode or for more than one rtx code. GCC provides some simple iterator
7858 facilities to make this process easier.
7861 * Mode Iterators:: Generating variations of patterns for different modes.
7862 * Code Iterators:: Doing the same for codes.
7865 @node Mode Iterators
7866 @subsection Mode Iterators
7867 @cindex mode iterators in @file{.md} files
7869 Ports often need to define similar patterns for two or more different modes.
7874 If a processor has hardware support for both single and double
7875 floating-point arithmetic, the @code{SFmode} patterns tend to be
7876 very similar to the @code{DFmode} ones.
7879 If a port uses @code{SImode} pointers in one configuration and
7880 @code{DImode} pointers in another, it will usually have very similar
7881 @code{SImode} and @code{DImode} patterns for manipulating pointers.
7884 Mode iterators allow several patterns to be instantiated from one
7885 @file{.md} file template. They can be used with any type of
7886 rtx-based construct, such as a @code{define_insn},
7887 @code{define_split}, or @code{define_peephole2}.
7890 * Defining Mode Iterators:: Defining a new mode iterator.
7891 * Substitutions:: Combining mode iterators with substitutions
7892 * Examples:: Examples
7895 @node Defining Mode Iterators
7896 @subsubsection Defining Mode Iterators
7897 @findex define_mode_iterator
7899 The syntax for defining a mode iterator is:
7902 (define_mode_iterator @var{name} [(@var{mode1} "@var{cond1}") @dots{} (@var{moden} "@var{condn}")])
7905 This allows subsequent @file{.md} file constructs to use the mode suffix
7906 @code{:@var{name}}. Every construct that does so will be expanded
7907 @var{n} times, once with every use of @code{:@var{name}} replaced by
7908 @code{:@var{mode1}}, once with every use replaced by @code{:@var{mode2}},
7909 and so on. In the expansion for a particular @var{modei}, every
7910 C condition will also require that @var{condi} be true.
7915 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
7918 defines a new mode suffix @code{:P}. Every construct that uses
7919 @code{:P} will be expanded twice, once with every @code{:P} replaced
7920 by @code{:SI} and once with every @code{:P} replaced by @code{:DI}.
7921 The @code{:SI} version will only apply if @code{Pmode == SImode} and
7922 the @code{:DI} version will only apply if @code{Pmode == DImode}.
7924 As with other @file{.md} conditions, an empty string is treated
7925 as ``always true''. @code{(@var{mode} "")} can also be abbreviated
7926 to @code{@var{mode}}. For example:
7929 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
7932 means that the @code{:DI} expansion only applies if @code{TARGET_64BIT}
7933 but that the @code{:SI} expansion has no such constraint.
7935 Iterators are applied in the order they are defined. This can be
7936 significant if two iterators are used in a construct that requires
7937 substitutions. @xref{Substitutions}.
7940 @subsubsection Substitution in Mode Iterators
7941 @findex define_mode_attr
7943 If an @file{.md} file construct uses mode iterators, each version of the
7944 construct will often need slightly different strings or modes. For
7949 When a @code{define_expand} defines several @code{add@var{m}3} patterns
7950 (@pxref{Standard Names}), each expander will need to use the
7951 appropriate mode name for @var{m}.
7954 When a @code{define_insn} defines several instruction patterns,
7955 each instruction will often use a different assembler mnemonic.
7958 When a @code{define_insn} requires operands with different modes,
7959 using an iterator for one of the operand modes usually requires a specific
7960 mode for the other operand(s).
7963 GCC supports such variations through a system of ``mode attributes''.
7964 There are two standard attributes: @code{mode}, which is the name of
7965 the mode in lower case, and @code{MODE}, which is the same thing in
7966 upper case. You can define other attributes using:
7969 (define_mode_attr @var{name} [(@var{mode1} "@var{value1}") @dots{} (@var{moden} "@var{valuen}")])
7972 where @var{name} is the name of the attribute and @var{valuei}
7973 is the value associated with @var{modei}.
7975 When GCC replaces some @var{:iterator} with @var{:mode}, it will scan
7976 each string and mode in the pattern for sequences of the form
7977 @code{<@var{iterator}:@var{attr}>}, where @var{attr} is the name of a
7978 mode attribute. If the attribute is defined for @var{mode}, the whole
7979 @code{<@dots{}>} sequence will be replaced by the appropriate attribute
7982 For example, suppose an @file{.md} file has:
7985 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
7986 (define_mode_attr load [(SI "lw") (DI "ld")])
7989 If one of the patterns that uses @code{:P} contains the string
7990 @code{"<P:load>\t%0,%1"}, the @code{SI} version of that pattern
7991 will use @code{"lw\t%0,%1"} and the @code{DI} version will use
7994 Here is an example of using an attribute for a mode:
7997 (define_mode_iterator LONG [SI DI])
7998 (define_mode_attr SHORT [(SI "HI") (DI "SI")])
7999 (define_insn @dots{}
8000 (sign_extend:LONG (match_operand:<LONG:SHORT> @dots{})) @dots{})
8003 The @code{@var{iterator}:} prefix may be omitted, in which case the
8004 substitution will be attempted for every iterator expansion.
8007 @subsubsection Mode Iterator Examples
8009 Here is an example from the MIPS port. It defines the following
8010 modes and attributes (among others):
8013 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
8014 (define_mode_attr d [(SI "") (DI "d")])
8017 and uses the following template to define both @code{subsi3}
8021 (define_insn "sub<mode>3"
8022 [(set (match_operand:GPR 0 "register_operand" "=d")
8023 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
8024 (match_operand:GPR 2 "register_operand" "d")))]
8027 [(set_attr "type" "arith")
8028 (set_attr "mode" "<MODE>")])
8031 This is exactly equivalent to:
8034 (define_insn "subsi3"
8035 [(set (match_operand:SI 0 "register_operand" "=d")
8036 (minus:SI (match_operand:SI 1 "register_operand" "d")
8037 (match_operand:SI 2 "register_operand" "d")))]
8040 [(set_attr "type" "arith")
8041 (set_attr "mode" "SI")])
8043 (define_insn "subdi3"
8044 [(set (match_operand:DI 0 "register_operand" "=d")
8045 (minus:DI (match_operand:DI 1 "register_operand" "d")
8046 (match_operand:DI 2 "register_operand" "d")))]
8049 [(set_attr "type" "arith")
8050 (set_attr "mode" "DI")])
8053 @node Code Iterators
8054 @subsection Code Iterators
8055 @cindex code iterators in @file{.md} files
8056 @findex define_code_iterator
8057 @findex define_code_attr
8059 Code iterators operate in a similar way to mode iterators. @xref{Mode Iterators}.
8064 (define_code_iterator @var{name} [(@var{code1} "@var{cond1}") @dots{} (@var{coden} "@var{condn}")])
8067 defines a pseudo rtx code @var{name} that can be instantiated as
8068 @var{codei} if condition @var{condi} is true. Each @var{codei}
8069 must have the same rtx format. @xref{RTL Classes}.
8071 As with mode iterators, each pattern that uses @var{name} will be
8072 expanded @var{n} times, once with all uses of @var{name} replaced by
8073 @var{code1}, once with all uses replaced by @var{code2}, and so on.
8074 @xref{Defining Mode Iterators}.
8076 It is possible to define attributes for codes as well as for modes.
8077 There are two standard code attributes: @code{code}, the name of the
8078 code in lower case, and @code{CODE}, the name of the code in upper case.
8079 Other attributes are defined using:
8082 (define_code_attr @var{name} [(@var{code1} "@var{value1}") @dots{} (@var{coden} "@var{valuen}")])
8085 Here's an example of code iterators in action, taken from the MIPS port:
8088 (define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
8089 eq ne gt ge lt le gtu geu ltu leu])
8091 (define_expand "b<code>"
8093 (if_then_else (any_cond:CC (cc0)
8095 (label_ref (match_operand 0 ""))
8099 gen_conditional_branch (operands, <CODE>);
8104 This is equivalent to:
8107 (define_expand "bunordered"
8109 (if_then_else (unordered:CC (cc0)
8111 (label_ref (match_operand 0 ""))
8115 gen_conditional_branch (operands, UNORDERED);
8119 (define_expand "bordered"
8121 (if_then_else (ordered:CC (cc0)
8123 (label_ref (match_operand 0 ""))
8127 gen_conditional_branch (operands, ORDERED);