1 @c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 2000, 2001
2 @c Free Software Foundation, Inc.
3 @c This is part of the GCC manual.
4 @c For copying conditions, see the file gcc.texi.
8 @chapter Machine Descriptions
9 @cindex machine descriptions
11 A machine description has two parts: a file of instruction patterns
12 (@file{.md} file) and a C header file of macro definitions.
14 The @file{.md} file for a target machine contains a pattern for each
15 instruction that the target machine supports (or at least each instruction
16 that is worth telling the compiler about). It may also contain comments.
17 A semicolon causes the rest of the line to be a comment, unless the semicolon
18 is inside a quoted string.
20 See the next chapter for information on the C header file.
23 * Overview:: How the machine description is used.
24 * Patterns:: How to write instruction patterns.
25 * Example:: An explained example of a @code{define_insn} pattern.
26 * RTL Template:: The RTL template defines what insns match a pattern.
27 * Output Template:: The output template says how to make assembler code
29 * Output Statement:: For more generality, write C code to output
31 * Constraints:: When not all operands are general operands.
32 * Standard Names:: Names mark patterns to use for code generation.
33 * Pattern Ordering:: When the order of patterns makes a difference.
34 * Dependent Patterns:: Having one pattern may make you need another.
35 * Jump Patterns:: Special considerations for patterns for jump insns.
36 * Looping Patterns:: How to define patterns for special looping insns.
37 * Insn Canonicalizations::Canonicalization of Instructions
38 * Expander Definitions::Generating a sequence of several RTL insns
39 for a standard operation.
40 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
41 * Peephole Definitions::Defining machine-specific peephole optimizations.
42 * Insn Attributes:: Specifying the value of attributes for generated insns.
43 * Conditional Execution::Generating @code{define_insn} patterns for
45 * Constant Definitions::Defining symbolic constants that can be used in the
50 @section Overview of How the Machine Description is Used
52 There are three main conversions that happen in the compiler:
57 The front end reads the source code and builds a parse tree.
60 The parse tree is used to generate an RTL insn list based on named
64 The insn list is matched against the RTL templates to produce assembler
69 For the generate pass, only the names of the insns matter, from either a
70 named @code{define_insn} or a @code{define_expand}. The compiler will
71 choose the pattern with the right name and apply the operands according
72 to the documentation later in this chapter, without regard for the RTL
73 template or operand constraints. Note that the names the compiler looks
74 for are hard-coded in the compiler---it will ignore unnamed patterns and
75 patterns with names it doesn't know about, but if you don't provide a
76 named pattern it needs, it will abort.
78 If a @code{define_insn} is used, the template given is inserted into the
79 insn list. If a @code{define_expand} is used, one of three things
80 happens, based on the condition logic. The condition logic may manually
81 create new insns for the insn list, say via @code{emit_insn()}, and
82 invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
83 compiler to use an alternate way of performing that task. If it invokes
84 neither @code{DONE} nor @code{FAIL}, the template given in the pattern
85 is inserted, as if the @code{define_expand} were a @code{define_insn}.
87 Once the insn list is generated, various optimization passes convert,
88 replace, and rearrange the insns in the insn list. This is where the
89 @code{define_split} and @code{define_peephole} patterns get used, for
92 Finally, the insn list's RTL is matched up with the RTL templates in the
93 @code{define_insn} patterns, and those patterns are used to emit the
94 final assembly code. For this purpose, each named @code{define_insn}
95 acts like it's unnamed, since the names are ignored.
98 @section Everything about Instruction Patterns
100 @cindex instruction patterns
103 Each instruction pattern contains an incomplete RTL expression, with pieces
104 to be filled in later, operand constraints that restrict how the pieces can
105 be filled in, and an output pattern or C code to generate the assembler
106 output, all wrapped up in a @code{define_insn} expression.
108 A @code{define_insn} is an RTL expression containing four or five operands:
112 An optional name. The presence of a name indicate that this instruction
113 pattern can perform a certain standard job for the RTL-generation
114 pass of the compiler. This pass knows certain names and will use
115 the instruction patterns with those names, if the names are defined
116 in the machine description.
118 The absence of a name is indicated by writing an empty string
119 where the name should go. Nameless instruction patterns are never
120 used for generating RTL code, but they may permit several simpler insns
121 to be combined later on.
123 Names that are not thus known and used in RTL-generation have no
124 effect; they are equivalent to no name at all.
126 For the purpose of debugging the compiler, you may also specify a
127 name beginning with the @samp{*} character. Such a name is used only
128 for identifying the instruction in RTL dumps; it is entirely equivalent
129 to having a nameless pattern for all other purposes.
132 The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete
133 RTL expressions which show what the instruction should look like. It is
134 incomplete because it may contain @code{match_operand},
135 @code{match_operator}, and @code{match_dup} expressions that stand for
136 operands of the instruction.
138 If the vector has only one element, that element is the template for the
139 instruction pattern. If the vector has multiple elements, then the
140 instruction pattern is a @code{parallel} expression containing the
144 @cindex pattern conditions
145 @cindex conditions, in patterns
146 A condition. This is a string which contains a C expression that is
147 the final test to decide whether an insn body matches this pattern.
149 @cindex named patterns and conditions
150 For a named pattern, the condition (if present) may not depend on
151 the data in the insn being matched, but only the target-machine-type
152 flags. The compiler needs to test these conditions during
153 initialization in order to learn exactly which named instructions are
154 available in a particular run.
157 For nameless patterns, the condition is applied only when matching an
158 individual insn, and only after the insn has matched the pattern's
159 recognition template. The insn's operands may be found in the vector
163 The @dfn{output template}: a string that says how to output matching
164 insns as assembler code. @samp{%} in this string specifies where
165 to substitute the value of an operand. @xref{Output Template}.
167 When simple substitution isn't general enough, you can specify a piece
168 of C code to compute the output. @xref{Output Statement}.
171 Optionally, a vector containing the values of attributes for insns matching
172 this pattern. @xref{Insn Attributes}.
176 @section Example of @code{define_insn}
177 @cindex @code{define_insn} example
179 Here is an actual example of an instruction pattern, for the 68000/68020.
184 (match_operand:SI 0 "general_operand" "rm"))]
188 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
190 return \"cmpl #0,%0\";
195 This can also be written using braced strings:
200 (match_operand:SI 0 "general_operand" "rm"))]
203 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
209 This is an instruction that sets the condition codes based on the value of
210 a general operand. It has no condition, so any insn whose RTL description
211 has the form shown may be handled according to this pattern. The name
212 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation
213 pass that, when it is necessary to test such a value, an insn to do so
214 can be constructed using this pattern.
216 The output control string is a piece of C code which chooses which
217 output template to return based on the kind of operand and the specific
218 type of CPU for which code is being generated.
220 @samp{"rm"} is an operand constraint. Its meaning is explained below.
223 @section RTL Template
224 @cindex RTL insn template
225 @cindex generating insns
226 @cindex insns, generating
227 @cindex recognizing insns
228 @cindex insns, recognizing
230 The RTL template is used to define which insns match the particular pattern
231 and how to find their operands. For named patterns, the RTL template also
232 says how to construct an insn from specified operands.
234 Construction involves substituting specified operands into a copy of the
235 template. Matching involves determining the values that serve as the
236 operands in the insn being matched. Both of these activities are
237 controlled by special expression types that direct matching and
238 substitution of the operands.
241 @findex match_operand
242 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
243 This expression is a placeholder for operand number @var{n} of
244 the insn. When constructing an insn, operand number @var{n}
245 will be substituted at this point. When matching an insn, whatever
246 appears at this position in the insn will be taken as operand
247 number @var{n}; but it must satisfy @var{predicate} or this instruction
248 pattern will not match at all.
250 Operand numbers must be chosen consecutively counting from zero in
251 each instruction pattern. There may be only one @code{match_operand}
252 expression in the pattern for each operand number. Usually operands
253 are numbered in the order of appearance in @code{match_operand}
254 expressions. In the case of a @code{define_expand}, any operand numbers
255 used only in @code{match_dup} expressions have higher values than all
256 other operand numbers.
258 @var{predicate} is a string that is the name of a C function that accepts two
259 arguments, an expression and a machine mode. During matching, the
260 function will be called with the putative operand as the expression and
261 @var{m} as the mode argument (if @var{m} is not specified,
262 @code{VOIDmode} will be used, which normally causes @var{predicate} to accept
263 any mode). If it returns zero, this instruction pattern fails to match.
264 @var{predicate} may be an empty string; then it means no test is to be done
265 on the operand, so anything which occurs in this position is valid.
267 Most of the time, @var{predicate} will reject modes other than @var{m}---but
268 not always. For example, the predicate @code{address_operand} uses
269 @var{m} as the mode of memory ref that the address should be valid for.
270 Many predicates accept @code{const_int} nodes even though their mode is
273 @var{constraint} controls reloading and the choice of the best register
274 class to use for a value, as explained later (@pxref{Constraints}).
276 People are often unclear on the difference between the constraint and the
277 predicate. The predicate helps decide whether a given insn matches the
278 pattern. The constraint plays no role in this decision; instead, it
279 controls various decisions in the case of an insn which does match.
281 @findex general_operand
282 On CISC machines, the most common @var{predicate} is
283 @code{"general_operand"}. This function checks that the putative
284 operand is either a constant, a register or a memory reference, and that
285 it is valid for mode @var{m}.
287 @findex register_operand
288 For an operand that must be a register, @var{predicate} should be
289 @code{"register_operand"}. Using @code{"general_operand"} would be
290 valid, since the reload pass would copy any non-register operands
291 through registers, but this would make GCC do extra work, it would
292 prevent invariant operands (such as constant) from being removed from
293 loops, and it would prevent the register allocator from doing the best
294 possible job. On RISC machines, it is usually most efficient to allow
295 @var{predicate} to accept only objects that the constraints allow.
297 @findex immediate_operand
298 For an operand that must be a constant, you must be sure to either use
299 @code{"immediate_operand"} for @var{predicate}, or make the instruction
300 pattern's extra condition require a constant, or both. You cannot
301 expect the constraints to do this work! If the constraints allow only
302 constants, but the predicate allows something else, the compiler will
303 crash when that case arises.
305 @findex match_scratch
306 @item (match_scratch:@var{m} @var{n} @var{constraint})
307 This expression is also a placeholder for operand number @var{n}
308 and indicates that operand must be a @code{scratch} or @code{reg}
311 When matching patterns, this is equivalent to
314 (match_operand:@var{m} @var{n} "scratch_operand" @var{pred})
317 but, when generating RTL, it produces a (@code{scratch}:@var{m})
320 If the last few expressions in a @code{parallel} are @code{clobber}
321 expressions whose operands are either a hard register or
322 @code{match_scratch}, the combiner can add or delete them when
323 necessary. @xref{Side Effects}.
326 @item (match_dup @var{n})
327 This expression is also a placeholder for operand number @var{n}.
328 It is used when the operand needs to appear more than once in the
331 In construction, @code{match_dup} acts just like @code{match_operand}:
332 the operand is substituted into the insn being constructed. But in
333 matching, @code{match_dup} behaves differently. It assumes that operand
334 number @var{n} has already been determined by a @code{match_operand}
335 appearing earlier in the recognition template, and it matches only an
336 identical-looking expression.
338 Note that @code{match_dup} should not be used to tell the compiler that
339 a particular register is being used for two operands (example:
340 @code{add} that adds one register to another; the second register is
341 both an input operand and the output operand). Use a matching
342 constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
343 operand is used in two places in the template, such as an instruction
344 that computes both a quotient and a remainder, where the opcode takes
345 two input operands but the RTL template has to refer to each of those
346 twice; once for the quotient pattern and once for the remainder pattern.
348 @findex match_operator
349 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
350 This pattern is a kind of placeholder for a variable RTL expression
353 When constructing an insn, it stands for an RTL expression whose
354 expression code is taken from that of operand @var{n}, and whose
355 operands are constructed from the patterns @var{operands}.
357 When matching an expression, it matches an expression if the function
358 @var{predicate} returns nonzero on that expression @emph{and} the
359 patterns @var{operands} match the operands of the expression.
361 Suppose that the function @code{commutative_operator} is defined as
362 follows, to match any expression whose operator is one of the
363 commutative arithmetic operators of RTL and whose mode is @var{mode}:
367 commutative_operator (x, mode)
369 enum machine_mode mode;
371 enum rtx_code code = GET_CODE (x);
372 if (GET_MODE (x) != mode)
374 return (GET_RTX_CLASS (code) == 'c'
375 || code == EQ || code == NE);
379 Then the following pattern will match any RTL expression consisting
380 of a commutative operator applied to two general operands:
383 (match_operator:SI 3 "commutative_operator"
384 [(match_operand:SI 1 "general_operand" "g")
385 (match_operand:SI 2 "general_operand" "g")])
388 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
389 because the expressions to be matched all contain two operands.
391 When this pattern does match, the two operands of the commutative
392 operator are recorded as operands 1 and 2 of the insn. (This is done
393 by the two instances of @code{match_operand}.) Operand 3 of the insn
394 will be the entire commutative expression: use @code{GET_CODE
395 (operands[3])} to see which commutative operator was used.
397 The machine mode @var{m} of @code{match_operator} works like that of
398 @code{match_operand}: it is passed as the second argument to the
399 predicate function, and that function is solely responsible for
400 deciding whether the expression to be matched ``has'' that mode.
402 When constructing an insn, argument 3 of the gen-function will specify
403 the operation (i.e.@: the expression code) for the expression to be
404 made. It should be an RTL expression, whose expression code is copied
405 into a new expression whose operands are arguments 1 and 2 of the
406 gen-function. The subexpressions of argument 3 are not used;
407 only its expression code matters.
409 When @code{match_operator} is used in a pattern for matching an insn,
410 it usually best if the operand number of the @code{match_operator}
411 is higher than that of the actual operands of the insn. This improves
412 register allocation because the register allocator often looks at
413 operands 1 and 2 of insns to see if it can do register tying.
415 There is no way to specify constraints in @code{match_operator}. The
416 operand of the insn which corresponds to the @code{match_operator}
417 never has any constraints because it is never reloaded as a whole.
418 However, if parts of its @var{operands} are matched by
419 @code{match_operand} patterns, those parts may have constraints of
423 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
424 Like @code{match_dup}, except that it applies to operators instead of
425 operands. When constructing an insn, operand number @var{n} will be
426 substituted at this point. But in matching, @code{match_op_dup} behaves
427 differently. It assumes that operand number @var{n} has already been
428 determined by a @code{match_operator} appearing earlier in the
429 recognition template, and it matches only an identical-looking
432 @findex match_parallel
433 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
434 This pattern is a placeholder for an insn that consists of a
435 @code{parallel} expression with a variable number of elements. This
436 expression should only appear at the top level of an insn pattern.
438 When constructing an insn, operand number @var{n} will be substituted at
439 this point. When matching an insn, it matches if the body of the insn
440 is a @code{parallel} expression with at least as many elements as the
441 vector of @var{subpat} expressions in the @code{match_parallel}, if each
442 @var{subpat} matches the corresponding element of the @code{parallel},
443 @emph{and} the function @var{predicate} returns nonzero on the
444 @code{parallel} that is the body of the insn. It is the responsibility
445 of the predicate to validate elements of the @code{parallel} beyond
446 those listed in the @code{match_parallel}.
448 A typical use of @code{match_parallel} is to match load and store
449 multiple expressions, which can contain a variable number of elements
450 in a @code{parallel}. For example,
451 @c the following is *still* going over. need to change the code.
452 @c also need to work on grouping of this example. --mew 1feb93
456 [(match_parallel 0 "load_multiple_operation"
457 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
458 (match_operand:SI 2 "memory_operand" "m"))
460 (clobber (reg:SI 179))])]
465 This example comes from @file{a29k.md}. The function
466 @code{load_multiple_operations} is defined in @file{a29k.c} and checks
467 that subsequent elements in the @code{parallel} are the same as the
468 @code{set} in the pattern, except that they are referencing subsequent
469 registers and memory locations.
471 An insn that matches this pattern might look like:
475 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
477 (clobber (reg:SI 179))
479 (mem:SI (plus:SI (reg:SI 100)
482 (mem:SI (plus:SI (reg:SI 100)
486 @findex match_par_dup
487 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
488 Like @code{match_op_dup}, but for @code{match_parallel} instead of
489 @code{match_operator}.
492 @item (match_insn @var{predicate})
493 Match a complete insn. Unlike the other @code{match_*} recognizers,
494 @code{match_insn} does not take an operand number.
496 The machine mode @var{m} of @code{match_insn} works like that of
497 @code{match_operand}: it is passed as the second argument to the
498 predicate function, and that function is solely responsible for
499 deciding whether the expression to be matched ``has'' that mode.
502 @item (match_insn2 @var{n} @var{predicate})
503 Match a complete insn.
505 The machine mode @var{m} of @code{match_insn2} works like that of
506 @code{match_operand}: it is passed as the second argument to the
507 predicate function, and that function is solely responsible for
508 deciding whether the expression to be matched ``has'' that mode.
512 @node Output Template
513 @section Output Templates and Operand Substitution
514 @cindex output templates
515 @cindex operand substitution
517 @cindex @samp{%} in template
519 The @dfn{output template} is a string which specifies how to output the
520 assembler code for an instruction pattern. Most of the template is a
521 fixed string which is output literally. The character @samp{%} is used
522 to specify where to substitute an operand; it can also be used to
523 identify places where different variants of the assembler require
526 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
527 operand @var{n} at that point in the string.
529 @samp{%} followed by a letter and a digit says to output an operand in an
530 alternate fashion. Four letters have standard, built-in meanings described
531 below. The machine description macro @code{PRINT_OPERAND} can define
532 additional letters with nonstandard meanings.
534 @samp{%c@var{digit}} can be used to substitute an operand that is a
535 constant value without the syntax that normally indicates an immediate
538 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
539 the constant is negated before printing.
541 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
542 memory reference, with the actual operand treated as the address. This may
543 be useful when outputting a ``load address'' instruction, because often the
544 assembler syntax for such an instruction requires you to write the operand
545 as if it were a memory reference.
547 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
550 @samp{%=} outputs a number which is unique to each instruction in the
551 entire compilation. This is useful for making local labels to be
552 referred to more than once in a single template that generates multiple
553 assembler instructions.
555 @samp{%} followed by a punctuation character specifies a substitution that
556 does not use an operand. Only one case is standard: @samp{%%} outputs a
557 @samp{%} into the assembler code. Other nonstandard cases can be
558 defined in the @code{PRINT_OPERAND} macro. You must also define
559 which punctuation characters are valid with the
560 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
564 The template may generate multiple assembler instructions. Write the text
565 for the instructions, with @samp{\;} between them.
567 @cindex matching operands
568 When the RTL contains two operands which are required by constraint to match
569 each other, the output template must refer only to the lower-numbered operand.
570 Matching operands are not always identical, and the rest of the compiler
571 arranges to put the proper RTL expression for printing into the lower-numbered
574 One use of nonstandard letters or punctuation following @samp{%} is to
575 distinguish between different assembler languages for the same machine; for
576 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
577 requires periods in most opcode names, while MIT syntax does not. For
578 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
579 syntax. The same file of patterns is used for both kinds of output syntax,
580 but the character sequence @samp{%.} is used in each place where Motorola
581 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
582 defines the sequence to output a period; the macro for MIT syntax defines
585 @cindex @code{#} in template
586 As a special case, a template consisting of the single character @code{#}
587 instructs the compiler to first split the insn, and then output the
588 resulting instructions separately. This helps eliminate redundancy in the
589 output templates. If you have a @code{define_insn} that needs to emit
590 multiple assembler instructions, and there is an matching @code{define_split}
591 already defined, then you can simply use @code{#} as the output template
592 instead of writing an output template that emits the multiple assembler
595 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
596 of the form @samp{@{option0|option1|option2@}} in the templates. These
597 describe multiple variants of assembler language syntax.
598 @xref{Instruction Output}.
600 @node Output Statement
601 @section C Statements for Assembler Output
602 @cindex output statements
603 @cindex C statements for assembler output
604 @cindex generating assembler output
606 Often a single fixed template string cannot produce correct and efficient
607 assembler code for all the cases that are recognized by a single
608 instruction pattern. For example, the opcodes may depend on the kinds of
609 operands; or some unfortunate combinations of operands may require extra
610 machine instructions.
612 If the output control string starts with a @samp{@@}, then it is actually
613 a series of templates, each on a separate line. (Blank lines and
614 leading spaces and tabs are ignored.) The templates correspond to the
615 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
616 if a target machine has a two-address add instruction @samp{addr} to add
617 into a register and another @samp{addm} to add a register to memory, you
618 might write this pattern:
621 (define_insn "addsi3"
622 [(set (match_operand:SI 0 "general_operand" "=r,m")
623 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
624 (match_operand:SI 2 "general_operand" "g,r")))]
631 @cindex @code{*} in template
632 @cindex asterisk in template
633 If the output control string starts with a @samp{*}, then it is not an
634 output template but rather a piece of C program that should compute a
635 template. It should execute a @code{return} statement to return the
636 template-string you want. Most such templates use C string literals, which
637 require doublequote characters to delimit them. To include these
638 doublequote characters in the string, prefix each one with @samp{\}.
640 If the output control string is written as a brace block instead of a
641 double-quoted string, it is automatically assumed to be C code. In that
642 case, it is not necessary to put in a leading asterisk, or to escape the
643 doublequotes surrounding C string literals.
645 The operands may be found in the array @code{operands}, whose C data type
648 It is very common to select different ways of generating assembler code
649 based on whether an immediate operand is within a certain range. Be
650 careful when doing this, because the result of @code{INTVAL} is an
651 integer on the host machine. If the host machine has more bits in an
652 @code{int} than the target machine has in the mode in which the constant
653 will be used, then some of the bits you get from @code{INTVAL} will be
654 superfluous. For proper results, you must carefully disregard the
655 values of those bits.
657 @findex output_asm_insn
658 It is possible to output an assembler instruction and then go on to output
659 or compute more of them, using the subroutine @code{output_asm_insn}. This
660 receives two arguments: a template-string and a vector of operands. The
661 vector may be @code{operands}, or it may be another array of @code{rtx}
662 that you declare locally and initialize yourself.
664 @findex which_alternative
665 When an insn pattern has multiple alternatives in its constraints, often
666 the appearance of the assembler code is determined mostly by which alternative
667 was matched. When this is so, the C code can test the variable
668 @code{which_alternative}, which is the ordinal number of the alternative
669 that was actually satisfied (0 for the first, 1 for the second alternative,
672 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
673 for registers and @samp{clrmem} for memory locations. Here is how
674 a pattern could use @code{which_alternative} to choose between them:
678 [(set (match_operand:SI 0 "general_operand" "=r,m")
682 return (which_alternative == 0
683 ? "clrreg %0" : "clrmem %0");
687 The example above, where the assembler code to generate was
688 @emph{solely} determined by the alternative, could also have been specified
689 as follows, having the output control string start with a @samp{@@}:
694 [(set (match_operand:SI 0 "general_operand" "=r,m")
704 @c Most of this node appears by itself (in a different place) even
705 @c when the INTERNALS flag is clear. Passages that require the full
706 @c manual's context are conditionalized to appear only in the full manual.
709 @section Operand Constraints
710 @cindex operand constraints
713 Each @code{match_operand} in an instruction pattern can specify a
714 constraint for the type of operands allowed.
718 @section Constraints for @code{asm} Operands
719 @cindex operand constraints, @code{asm}
720 @cindex constraints, @code{asm}
721 @cindex @code{asm} constraints
723 Here are specific details on what constraint letters you can use with
726 Constraints can say whether
727 an operand may be in a register, and which kinds of register; whether the
728 operand can be a memory reference, and which kinds of address; whether the
729 operand may be an immediate constant, and which possible values it may
730 have. Constraints can also require two operands to match.
734 * Simple Constraints:: Basic use of constraints.
735 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
736 * Class Preferences:: Constraints guide which hard register to put things in.
737 * Modifiers:: More precise control over effects of constraints.
738 * Machine Constraints:: Existing constraints for some particular machines.
744 * Simple Constraints:: Basic use of constraints.
745 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
746 * Modifiers:: More precise control over effects of constraints.
747 * Machine Constraints:: Special constraints for some particular machines.
751 @node Simple Constraints
752 @subsection Simple Constraints
753 @cindex simple constraints
755 The simplest kind of constraint is a string full of letters, each of
756 which describes one kind of operand that is permitted. Here are
757 the letters that are allowed:
761 Whitespace characters are ignored and can be inserted at any position
762 except the first. This enables each alternative for different operands to
763 be visually aligned in the machine description even if they have different
764 number of constraints and modifiers.
766 @cindex @samp{m} in constraint
767 @cindex memory references in constraints
769 A memory operand is allowed, with any kind of address that the machine
772 @cindex offsettable address
773 @cindex @samp{o} in constraint
775 A memory operand is allowed, but only if the address is
776 @dfn{offsettable}. This means that adding a small integer (actually,
777 the width in bytes of the operand, as determined by its machine mode)
778 may be added to the address and the result is also a valid memory
781 @cindex autoincrement/decrement addressing
782 For example, an address which is constant is offsettable; so is an
783 address that is the sum of a register and a constant (as long as a
784 slightly larger constant is also within the range of address-offsets
785 supported by the machine); but an autoincrement or autodecrement
786 address is not offsettable. More complicated indirect/indexed
787 addresses may or may not be offsettable depending on the other
788 addressing modes that the machine supports.
790 Note that in an output operand which can be matched by another
791 operand, the constraint letter @samp{o} is valid only when accompanied
792 by both @samp{<} (if the target machine has predecrement addressing)
793 and @samp{>} (if the target machine has preincrement addressing).
795 @cindex @samp{V} in constraint
797 A memory operand that is not offsettable. In other words, anything that
798 would fit the @samp{m} constraint but not the @samp{o} constraint.
800 @cindex @samp{<} in constraint
802 A memory operand with autodecrement addressing (either predecrement or
803 postdecrement) is allowed.
805 @cindex @samp{>} in constraint
807 A memory operand with autoincrement addressing (either preincrement or
808 postincrement) is allowed.
810 @cindex @samp{r} in constraint
811 @cindex registers in constraints
813 A register operand is allowed provided that it is in a general
816 @cindex constants in constraints
817 @cindex @samp{i} in constraint
819 An immediate integer operand (one with constant value) is allowed.
820 This includes symbolic constants whose values will be known only at
823 @cindex @samp{n} in constraint
825 An immediate integer operand with a known numeric value is allowed.
826 Many systems cannot support assembly-time constants for operands less
827 than a word wide. Constraints for these operands should use @samp{n}
828 rather than @samp{i}.
830 @cindex @samp{I} in constraint
831 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
832 Other letters in the range @samp{I} through @samp{P} may be defined in
833 a machine-dependent fashion to permit immediate integer operands with
834 explicit integer values in specified ranges. For example, on the
835 68000, @samp{I} is defined to stand for the range of values 1 to 8.
836 This is the range permitted as a shift count in the shift
839 @cindex @samp{E} in constraint
841 An immediate floating operand (expression code @code{const_double}) is
842 allowed, but only if the target floating point format is the same as
843 that of the host machine (on which the compiler is running).
845 @cindex @samp{F} in constraint
847 An immediate floating operand (expression code @code{const_double}) is
850 @cindex @samp{G} in constraint
851 @cindex @samp{H} in constraint
852 @item @samp{G}, @samp{H}
853 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
854 permit immediate floating operands in particular ranges of values.
856 @cindex @samp{s} in constraint
858 An immediate integer operand whose value is not an explicit integer is
861 This might appear strange; if an insn allows a constant operand with a
862 value not known at compile time, it certainly must allow any known
863 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
864 better code to be generated.
866 For example, on the 68000 in a fullword instruction it is possible to
867 use an immediate operand; but if the immediate value is between @minus{}128
868 and 127, better code results from loading the value into a register and
869 using the register. This is because the load into the register can be
870 done with a @samp{moveq} instruction. We arrange for this to happen
871 by defining the letter @samp{K} to mean ``any integer outside the
872 range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand
875 @cindex @samp{g} in constraint
877 Any register, memory or immediate integer operand is allowed, except for
878 registers that are not general registers.
880 @cindex @samp{X} in constraint
883 Any operand whatsoever is allowed, even if it does not satisfy
884 @code{general_operand}. This is normally used in the constraint of
885 a @code{match_scratch} when certain alternatives will not actually
886 require a scratch register.
889 Any operand whatsoever is allowed.
892 @cindex @samp{0} in constraint
893 @cindex digits in constraint
894 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
895 An operand that matches the specified operand number is allowed. If a
896 digit is used together with letters within the same alternative, the
897 digit should come last.
899 @cindex matching constraint
900 @cindex constraint, matching
901 This is called a @dfn{matching constraint} and what it really means is
902 that the assembler has only a single operand that fills two roles
904 considered separate in the RTL insn. For example, an add insn has two
905 input operands and one output operand in the RTL, but on most CISC
908 which @code{asm} distinguishes. For example, an add instruction uses
909 two input operands and an output operand, but on most CISC
911 machines an add instruction really has only two operands, one of them an
912 input-output operand:
918 Matching constraints are used in these circumstances.
919 More precisely, the two operands that match must include one input-only
920 operand and one output-only operand. Moreover, the digit must be a
921 smaller number than the number of the operand that uses it in the
925 For operands to match in a particular case usually means that they
926 are identical-looking RTL expressions. But in a few special cases
927 specific kinds of dissimilarity are allowed. For example, @code{*x}
928 as an input operand will match @code{*x++} as an output operand.
929 For proper results in such cases, the output template should always
930 use the output-operand's number when printing the operand.
933 @cindex load address instruction
934 @cindex push address instruction
935 @cindex address constraints
936 @cindex @samp{p} in constraint
938 An operand that is a valid memory address is allowed. This is
939 for ``load address'' and ``push address'' instructions.
941 @findex address_operand
942 @samp{p} in the constraint must be accompanied by @code{address_operand}
943 as the predicate in the @code{match_operand}. This predicate interprets
944 the mode specified in the @code{match_operand} as the mode of the memory
945 reference for which the address would be valid.
947 @cindex other register constraints
948 @cindex extensible constraints
949 @item @var{other-letters}
950 Other letters can be defined in machine-dependent fashion to stand for
951 particular classes of registers or other arbitrary operand types.
952 @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
953 for data, address and floating point registers.
956 The machine description macro @code{REG_CLASS_FROM_LETTER} has first
957 cut at the otherwise unused letters. If it evaluates to @code{NO_REGS},
958 then @code{EXTRA_CONSTRAINT} is evaluated.
960 A typical use for @code{EXTRA_CONSTRANT} would be to distinguish certain
961 types of memory references that affect other insn operands.
966 In order to have valid assembler code, each operand must satisfy
967 its constraint. But a failure to do so does not prevent the pattern
968 from applying to an insn. Instead, it directs the compiler to modify
969 the code so that the constraint will be satisfied. Usually this is
970 done by copying an operand into a register.
972 Contrast, therefore, the two instruction patterns that follow:
976 [(set (match_operand:SI 0 "general_operand" "=r")
977 (plus:SI (match_dup 0)
978 (match_operand:SI 1 "general_operand" "r")))]
984 which has two operands, one of which must appear in two places, and
988 [(set (match_operand:SI 0 "general_operand" "=r")
989 (plus:SI (match_operand:SI 1 "general_operand" "0")
990 (match_operand:SI 2 "general_operand" "r")))]
996 which has three operands, two of which are required by a constraint to be
997 identical. If we are considering an insn of the form
1000 (insn @var{n} @var{prev} @var{next}
1002 (plus:SI (reg:SI 6) (reg:SI 109)))
1007 the first pattern would not apply at all, because this insn does not
1008 contain two identical subexpressions in the right place. The pattern would
1009 say, ``That does not look like an add instruction; try other patterns.''
1010 The second pattern would say, ``Yes, that's an add instruction, but there
1011 is something wrong with it.'' It would direct the reload pass of the
1012 compiler to generate additional insns to make the constraint true. The
1013 results might look like this:
1016 (insn @var{n2} @var{prev} @var{n}
1017 (set (reg:SI 3) (reg:SI 6))
1020 (insn @var{n} @var{n2} @var{next}
1022 (plus:SI (reg:SI 3) (reg:SI 109)))
1026 It is up to you to make sure that each operand, in each pattern, has
1027 constraints that can handle any RTL expression that could be present for
1028 that operand. (When multiple alternatives are in use, each pattern must,
1029 for each possible combination of operand expressions, have at least one
1030 alternative which can handle that combination of operands.) The
1031 constraints don't need to @emph{allow} any possible operand---when this is
1032 the case, they do not constrain---but they must at least point the way to
1033 reloading any possible operand so that it will fit.
1037 If the constraint accepts whatever operands the predicate permits,
1038 there is no problem: reloading is never necessary for this operand.
1040 For example, an operand whose constraints permit everything except
1041 registers is safe provided its predicate rejects registers.
1043 An operand whose predicate accepts only constant values is safe
1044 provided its constraints include the letter @samp{i}. If any possible
1045 constant value is accepted, then nothing less than @samp{i} will do;
1046 if the predicate is more selective, then the constraints may also be
1050 Any operand expression can be reloaded by copying it into a register.
1051 So if an operand's constraints allow some kind of register, it is
1052 certain to be safe. It need not permit all classes of registers; the
1053 compiler knows how to copy a register into another register of the
1054 proper class in order to make an instruction valid.
1056 @cindex nonoffsettable memory reference
1057 @cindex memory reference, nonoffsettable
1059 A nonoffsettable memory reference can be reloaded by copying the
1060 address into a register. So if the constraint uses the letter
1061 @samp{o}, all memory references are taken care of.
1064 A constant operand can be reloaded by allocating space in memory to
1065 hold it as preinitialized data. Then the memory reference can be used
1066 in place of the constant. So if the constraint uses the letters
1067 @samp{o} or @samp{m}, constant operands are not a problem.
1070 If the constraint permits a constant and a pseudo register used in an insn
1071 was not allocated to a hard register and is equivalent to a constant,
1072 the register will be replaced with the constant. If the predicate does
1073 not permit a constant and the insn is re-recognized for some reason, the
1074 compiler will crash. Thus the predicate must always recognize any
1075 objects allowed by the constraint.
1078 If the operand's predicate can recognize registers, but the constraint does
1079 not permit them, it can make the compiler crash. When this operand happens
1080 to be a register, the reload pass will be stymied, because it does not know
1081 how to copy a register temporarily into memory.
1083 If the predicate accepts a unary operator, the constraint applies to the
1084 operand. For example, the MIPS processor at ISA level 3 supports an
1085 instruction which adds two registers in @code{SImode} to produce a
1086 @code{DImode} result, but only if the registers are correctly sign
1087 extended. This predicate for the input operands accepts a
1088 @code{sign_extend} of an @code{SImode} register. Write the constraint
1089 to indicate the type of register that is required for the operand of the
1093 @node Multi-Alternative
1094 @subsection Multiple Alternative Constraints
1095 @cindex multiple alternative constraints
1097 Sometimes a single instruction has multiple alternative sets of possible
1098 operands. For example, on the 68000, a logical-or instruction can combine
1099 register or an immediate value into memory, or it can combine any kind of
1100 operand into a register; but it cannot combine one memory location into
1103 These constraints are represented as multiple alternatives. An alternative
1104 can be described by a series of letters for each operand. The overall
1105 constraint for an operand is made from the letters for this operand
1106 from the first alternative, a comma, the letters for this operand from
1107 the second alternative, a comma, and so on until the last alternative.
1109 Here is how it is done for fullword logical-or on the 68000:
1112 (define_insn "iorsi3"
1113 [(set (match_operand:SI 0 "general_operand" "=m,d")
1114 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1115 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1119 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1120 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1121 2. The second alternative has @samp{d} (data register) for operand 0,
1122 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1123 @samp{%} in the constraints apply to all the alternatives; their
1124 meaning is explained in the next section (@pxref{Class Preferences}).
1127 @c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL
1128 If all the operands fit any one alternative, the instruction is valid.
1129 Otherwise, for each alternative, the compiler counts how many instructions
1130 must be added to copy the operands so that that alternative applies.
1131 The alternative requiring the least copying is chosen. If two alternatives
1132 need the same amount of copying, the one that comes first is chosen.
1133 These choices can be altered with the @samp{?} and @samp{!} characters:
1136 @cindex @samp{?} in constraint
1137 @cindex question mark
1139 Disparage slightly the alternative that the @samp{?} appears in,
1140 as a choice when no alternative applies exactly. The compiler regards
1141 this alternative as one unit more costly for each @samp{?} that appears
1144 @cindex @samp{!} in constraint
1145 @cindex exclamation point
1147 Disparage severely the alternative that the @samp{!} appears in.
1148 This alternative can still be used if it fits without reloading,
1149 but if reloading is needed, some other alternative will be used.
1153 When an insn pattern has multiple alternatives in its constraints, often
1154 the appearance of the assembler code is determined mostly by which
1155 alternative was matched. When this is so, the C code for writing the
1156 assembler code can use the variable @code{which_alternative}, which is
1157 the ordinal number of the alternative that was actually satisfied (0 for
1158 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1162 @node Class Preferences
1163 @subsection Register Class Preferences
1164 @cindex class preference constraints
1165 @cindex register class preference constraints
1167 @cindex voting between constraint alternatives
1168 The operand constraints have another function: they enable the compiler
1169 to decide which kind of hardware register a pseudo register is best
1170 allocated to. The compiler examines the constraints that apply to the
1171 insns that use the pseudo register, looking for the machine-dependent
1172 letters such as @samp{d} and @samp{a} that specify classes of registers.
1173 The pseudo register is put in whichever class gets the most ``votes''.
1174 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1175 favor of a general register. The machine description says which registers
1176 are considered general.
1178 Of course, on some machines all registers are equivalent, and no register
1179 classes are defined. Then none of this complexity is relevant.
1183 @subsection Constraint Modifier Characters
1184 @cindex modifiers in constraints
1185 @cindex constraint modifier characters
1187 @c prevent bad page break with this line
1188 Here are constraint modifier characters.
1191 @cindex @samp{=} in constraint
1193 Means that this operand is write-only for this instruction: the previous
1194 value is discarded and replaced by output data.
1196 @cindex @samp{+} in constraint
1198 Means that this operand is both read and written by the instruction.
1200 When the compiler fixes up the operands to satisfy the constraints,
1201 it needs to know which operands are inputs to the instruction and
1202 which are outputs from it. @samp{=} identifies an output; @samp{+}
1203 identifies an operand that is both input and output; all other operands
1204 are assumed to be input only.
1206 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1207 first character of the constraint string.
1209 @cindex @samp{&} in constraint
1210 @cindex earlyclobber operand
1212 Means (in a particular alternative) that this operand is an
1213 @dfn{earlyclobber} operand, which is modified before the instruction is
1214 finished using the input operands. Therefore, this operand may not lie
1215 in a register that is used as an input operand or as part of any memory
1218 @samp{&} applies only to the alternative in which it is written. In
1219 constraints with multiple alternatives, sometimes one alternative
1220 requires @samp{&} while others do not. See, for example, the
1221 @samp{movdf} insn of the 68000.
1223 An input operand can be tied to an earlyclobber operand if its only
1224 use as an input occurs before the early result is written. Adding
1225 alternatives of this form often allows GCC to produce better code
1226 when only some of the inputs can be affected by the earlyclobber.
1227 See, for example, the @samp{mulsi3} insn of the ARM@.
1229 @samp{&} does not obviate the need to write @samp{=}.
1231 @cindex @samp{%} in constraint
1233 Declares the instruction to be commutative for this operand and the
1234 following operand. This means that the compiler may interchange the
1235 two operands if that is the cheapest way to make all operands fit the
1238 This is often used in patterns for addition instructions
1239 that really have only two operands: the result must go in one of the
1240 arguments. Here for example, is how the 68000 halfword-add
1241 instruction is defined:
1244 (define_insn "addhi3"
1245 [(set (match_operand:HI 0 "general_operand" "=m,r")
1246 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1247 (match_operand:HI 2 "general_operand" "di,g")))]
1252 @cindex @samp{#} in constraint
1254 Says that all following characters, up to the next comma, are to be
1255 ignored as a constraint. They are significant only for choosing
1256 register preferences.
1259 @cindex @samp{*} in constraint
1261 Says that the following character should be ignored when choosing
1262 register preferences. @samp{*} has no effect on the meaning of the
1263 constraint as a constraint, and no effect on reloading.
1265 Here is an example: the 68000 has an instruction to sign-extend a
1266 halfword in a data register, and can also sign-extend a value by
1267 copying it into an address register. While either kind of register is
1268 acceptable, the constraints on an address-register destination are
1269 less strict, so it is best if register allocation makes an address
1270 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1271 constraint letter (for data register) is ignored when computing
1272 register preferences.
1275 (define_insn "extendhisi2"
1276 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1278 (match_operand:HI 1 "general_operand" "0,g")))]
1284 @node Machine Constraints
1285 @subsection Constraints for Particular Machines
1286 @cindex machine specific constraints
1287 @cindex constraints, machine specific
1289 Whenever possible, you should use the general-purpose constraint letters
1290 in @code{asm} arguments, since they will convey meaning more readily to
1291 people reading your code. Failing that, use the constraint letters
1292 that usually have very similar meanings across architectures. The most
1293 commonly used constraints are @samp{m} and @samp{r} (for memory and
1294 general-purpose registers respectively; @pxref{Simple Constraints}), and
1295 @samp{I}, usually the letter indicating the most common
1296 immediate-constant format.
1298 For each machine architecture, the @file{config/@var{machine}.h} file
1299 defines additional constraints. These constraints are used by the
1300 compiler itself for instruction generation, as well as for @code{asm}
1301 statements; therefore, some of the constraints are not particularly
1302 interesting for @code{asm}. The constraints are defined through these
1306 @item REG_CLASS_FROM_LETTER
1307 Register class constraints (usually lower case).
1309 @item CONST_OK_FOR_LETTER_P
1310 Immediate constant constraints, for non-floating point constants of
1311 word size or smaller precision (usually upper case).
1313 @item CONST_DOUBLE_OK_FOR_LETTER_P
1314 Immediate constant constraints, for all floating point constants and for
1315 constants of greater than word size precision (usually upper case).
1317 @item EXTRA_CONSTRAINT
1318 Special cases of registers or memory. This macro is not required, and
1319 is only defined for some machines.
1322 Inspecting these macro definitions in the compiler source for your
1323 machine is the best way to be certain you have the right constraints.
1324 However, here is a summary of the machine-dependent constraints
1325 available on some particular machines.
1328 @item ARM family---@file{arm.h}
1331 Floating-point register
1334 One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0
1338 Floating-point constant that would satisfy the constraint @samp{F} if it
1342 Integer that is valid as an immediate operand in a data processing
1343 instruction. That is, an integer in the range 0 to 255 rotated by a
1347 Integer in the range @minus{}4095 to 4095
1350 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1353 Integer that satisfies constraint @samp{I} when negated (twos complement)
1356 Integer in the range 0 to 32
1359 A memory reference where the exact address is in a single register
1360 (`@samp{m}' is preferable for @code{asm} statements)
1363 An item in the constant pool
1366 A symbol in the text segment of the current file
1369 @item AMD 29000 family---@file{a29k.h}
1375 Byte Pointer (@samp{BP}) register
1381 Special purpose register
1384 First accumulator register
1387 Other accumulator register
1390 Floating point register
1393 Constant greater than 0, less than 0x100
1396 Constant greater than 0, less than 0x10000
1399 Constant whose high 24 bits are on (1)
1402 16-bit constant whose high 8 bits are on (1)
1405 32-bit constant whose high 16 bits are on (1)
1408 32-bit negative constant that fits in 8 bits
1411 The constant 0x80000000 or, on the 29050, any 32-bit constant
1412 whose low 16 bits are 0.
1415 16-bit negative constant that fits in 8 bits
1419 A floating point constant (in @code{asm} statements, use the machine
1420 independent @samp{E} or @samp{F} instead)
1423 @item AVR family---@file{avr.h}
1426 Registers from r0 to r15
1429 Registers from r16 to r23
1432 Registers from r16 to r31
1435 Registers from r24 to r31. These registers can be used in @samp{adiw} command
1438 Pointer register (r26--r31)
1441 Base pointer register (r28--r31)
1444 Stack pointer register (SPH:SPL)
1447 Temporary register r0
1450 Register pair X (r27:r26)
1453 Register pair Y (r29:r28)
1456 Register pair Z (r31:r30)
1459 Constant greater than @minus{}1, less than 64
1462 Constant greater than @minus{}64, less than 1
1471 Constant that fits in 8 bits
1474 Constant integer @minus{}1
1477 Constant integer 8, 16, or 24
1483 A floating point constant 0.0
1486 @item IBM RS6000---@file{rs6000.h}
1489 Address base register
1492 Floating point register
1495 @samp{MQ}, @samp{CTR}, or @samp{LINK} register
1504 @samp{LINK} register
1507 @samp{CR} register (condition register) number 0
1510 @samp{CR} register (condition register)
1513 @samp{FPMEM} stack memory for FPR-GPR transfers
1516 Signed 16-bit constant
1519 Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for
1520 @code{SImode} constants)
1523 Unsigned 16-bit constant
1526 Signed 16-bit constant shifted left 16 bits
1529 Constant larger than 31
1538 Constant whose negation is a signed 16-bit constant
1541 Floating point constant that can be loaded into a register with one
1542 instruction per word
1545 Memory operand that is an offset from a register (@samp{m} is preferable
1546 for @code{asm} statements)
1552 Constant suitable as a 64-bit mask operand
1555 Constant suitable as a 32-bit mask operand
1558 System V Release 4 small data area reference
1561 @item Intel 386---@file{i386.h}
1564 @samp{a}, @code{b}, @code{c}, or @code{d} register for the i386.
1565 For x86-64 it is equivalent to @samp{r} class. (for 8-bit instructions that
1566 do not use upper halves)
1569 @samp{a}, @code{b}, @code{c}, or @code{d} register. (for 8-bit instructions,
1570 that do use upper halves)
1573 Legacy register---equivalent to @code{r} class in i386 mode.
1574 (for non-8-bit registers used together with 8-bit upper halves in a single
1578 Specifies the @samp{a} or @samp{d} registers. This is primarily useful
1579 for 64-bit integer values (when in 32-bit mode) intended to be returned
1580 with the @samp{d} register holding the most significant bits and the
1581 @samp{a} register holding the least significant bits.
1584 Floating point register
1587 First (top of stack) floating point register
1590 Second floating point register
1611 @samp{xmm} SSE register
1617 Constant in range 0 to 31 (for 32-bit shifts)
1620 Constant in range 0 to 63 (for 64-bit shifts)
1629 0, 1, 2, or 3 (shifts for @code{lea} instruction)
1632 Constant in range 0 to 255 (for @code{out} instruction)
1635 Constant in range 0 to @code{0xffffffff} or symbolic reference known to fit specified range.
1636 (for using immediates in zero extending 32-bit to 64-bit x86-64 instructions)
1639 Constant in range @minus{}2147483648 to 2147483647 or symbolic reference known to fit specified range.
1640 (for using immediates in 64-bit x86-64 instructions)
1643 Standard 80387 floating point constant
1646 @item Intel 960---@file{i960.h}
1649 Floating point register (@code{fp0} to @code{fp3})
1652 Local register (@code{r0} to @code{r15})
1655 Global register (@code{g0} to @code{g15})
1658 Any local or global register
1661 Integers from 0 to 31
1667 Integers from @minus{}31 to 0
1676 @item MIPS---@file{mips.h}
1679 General-purpose integer register
1682 Floating-point register (if available)
1691 @samp{Hi} or @samp{Lo} register
1694 General-purpose integer register
1697 Floating-point status register
1700 Signed 16-bit constant (for arithmetic instructions)
1706 Zero-extended 16-bit constant (for logic instructions)
1709 Constant with low 16 bits zero (can be loaded with @code{lui})
1712 32-bit constant which requires two instructions to load (a constant
1713 which is not @samp{I}, @samp{K}, or @samp{L})
1716 Negative 16-bit constant
1722 Positive 16-bit constant
1728 Memory reference that can be loaded with more than one instruction
1729 (@samp{m} is preferable for @code{asm} statements)
1732 Memory reference that can be loaded with one instruction
1733 (@samp{m} is preferable for @code{asm} statements)
1736 Memory reference in external OSF/rose PIC format
1737 (@samp{m} is preferable for @code{asm} statements)
1740 @item Motorola 680x0---@file{m68k.h}
1749 68881 floating-point register, if available
1752 Sun FPA (floating-point) register, if available
1755 First 16 Sun FPA registers, if available
1758 Integer in the range 1 to 8
1761 16-bit signed number
1764 Signed number whose magnitude is greater than 0x80
1767 Integer in the range @minus{}8 to @minus{}1
1770 Signed number whose magnitude is greater than 0x100
1773 Floating point constant that is not a 68881 constant
1776 Floating point constant that can be used by Sun FPA
1779 @item Motorola 68HC11 & 68HC12 families---@file{m68hc11.h}
1794 Temporary soft register _.tmp
1797 A soft register _.d1 to _.d31
1800 Stack pointer register
1809 Pseudo register 'z' (replaced by 'x' or 'y' at the end)
1812 An address register: x, y or z
1815 An address register: x or y
1818 Register pair (x:d) to form a 32-bit value
1821 Constants in the range @minus{}65536 to 65535
1824 Constants whose 16-bit low part is zero
1827 Constant integer 1 or @minus{}1
1833 Constants in the range @minus{}8 to 2
1838 @item SPARC---@file{sparc.h}
1841 Floating-point register that can hold 32- or 64-bit values.
1844 Floating-point register that can hold 64- or 128-bit values.
1847 Signed 13-bit constant
1853 32-bit constant with the low 12 bits clear (a constant that can be
1854 loaded with the @code{sethi} instruction)
1860 Signed 13-bit constant, sign-extended to 32 or 64 bits
1863 Floating-point constant whose integral representation can
1864 be moved into an integer register using a single sethi
1868 Floating-point constant whose integral representation can
1869 be moved into an integer register using a single mov
1873 Floating-point constant whose integral representation can
1874 be moved into an integer register using a high/lo_sum
1875 instruction sequence
1878 Memory address aligned to an 8-byte boundary
1885 @item TMS320C3x/C4x---@file{c4x.h}
1888 Auxiliary (address) register (ar0-ar7)
1891 Stack pointer register (sp)
1894 Standard (32-bit) precision integer register
1897 Extended (40-bit) precision register (r0-r11)
1900 Block count register (bk)
1903 Extended (40-bit) precision low register (r0-r7)
1906 Extended (40-bit) precision register (r0-r1)
1909 Extended (40-bit) precision register (r2-r3)
1912 Repeat count register (rc)
1915 Index register (ir0-ir1)
1918 Status (condition code) register (st)
1921 Data page register (dp)
1927 Immediate 16-bit floating-point constant
1930 Signed 16-bit constant
1933 Signed 8-bit constant
1936 Signed 5-bit constant
1939 Unsigned 16-bit constant
1942 Unsigned 8-bit constant
1945 Ones complement of unsigned 16-bit constant
1948 High 16-bit constant (32-bit constant with 16 LSBs zero)
1951 Indirect memory reference with signed 8-bit or index register displacement
1954 Indirect memory reference with unsigned 5-bit displacement
1957 Indirect memory reference with 1 bit or index register displacement
1960 Direct memory reference
1969 @node Standard Names
1970 @section Standard Pattern Names For Generation
1971 @cindex standard pattern names
1972 @cindex pattern names
1973 @cindex names, pattern
1975 Here is a table of the instruction names that are meaningful in the RTL
1976 generation pass of the compiler. Giving one of these names to an
1977 instruction pattern tells the RTL generation pass that it can use the
1978 pattern to accomplish a certain task.
1981 @cindex @code{mov@var{m}} instruction pattern
1982 @item @samp{mov@var{m}}
1983 Here @var{m} stands for a two-letter machine mode name, in lower case.
1984 This instruction pattern moves data with that machine mode from operand
1985 1 to operand 0. For example, @samp{movsi} moves full-word data.
1987 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
1988 own mode is wider than @var{m}, the effect of this instruction is
1989 to store the specified value in the part of the register that corresponds
1990 to mode @var{m}. The effect on the rest of the register is undefined.
1992 This class of patterns is special in several ways. First of all, each
1993 of these names up to and including full word size @emph{must} be defined,
1994 because there is no other way to copy a datum from one place to another.
1995 If there are patterns accepting operands in larger modes,
1996 @samp{mov@var{m}} must be defined for integer modes of those sizes.
1998 Second, these patterns are not used solely in the RTL generation pass.
1999 Even the reload pass can generate move insns to copy values from stack
2000 slots into temporary registers. When it does so, one of the operands is
2001 a hard register and the other is an operand that can need to be reloaded
2005 Therefore, when given such a pair of operands, the pattern must generate
2006 RTL which needs no reloading and needs no temporary registers---no
2007 registers other than the operands. For example, if you support the
2008 pattern with a @code{define_expand}, then in such a case the
2009 @code{define_expand} mustn't call @code{force_reg} or any other such
2010 function which might generate new pseudo registers.
2012 This requirement exists even for subword modes on a RISC machine where
2013 fetching those modes from memory normally requires several insns and
2014 some temporary registers.
2016 @findex change_address
2017 During reload a memory reference with an invalid address may be passed
2018 as an operand. Such an address will be replaced with a valid address
2019 later in the reload pass. In this case, nothing may be done with the
2020 address except to use it as it stands. If it is copied, it will not be
2021 replaced with a valid address. No attempt should be made to make such
2022 an address into a valid address and no routine (such as
2023 @code{change_address}) that will do so may be called. Note that
2024 @code{general_operand} will fail when applied to such an address.
2026 @findex reload_in_progress
2027 The global variable @code{reload_in_progress} (which must be explicitly
2028 declared if required) can be used to determine whether such special
2029 handling is required.
2031 The variety of operands that have reloads depends on the rest of the
2032 machine description, but typically on a RISC machine these can only be
2033 pseudo registers that did not get hard registers, while on other
2034 machines explicit memory references will get optional reloads.
2036 If a scratch register is required to move an object to or from memory,
2037 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
2039 If there are cases needing
2040 scratch registers after reload, you must define
2041 @code{SECONDARY_INPUT_RELOAD_CLASS} and perhaps also
2042 @code{SECONDARY_OUTPUT_RELOAD_CLASS} to detect them, and provide
2043 patterns @samp{reload_in@var{m}} or @samp{reload_out@var{m}} to handle
2044 them. @xref{Register Classes}.
2046 @findex no_new_pseudos
2047 The global variable @code{no_new_pseudos} can be used to determine if it
2048 is unsafe to create new pseudo registers. If this variable is nonzero, then
2049 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
2051 The constraints on a @samp{mov@var{m}} must permit moving any hard
2052 register to any other hard register provided that
2053 @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
2054 @code{REGISTER_MOVE_COST} applied to their classes returns a value of 2.
2056 It is obligatory to support floating point @samp{mov@var{m}}
2057 instructions into and out of any registers that can hold fixed point
2058 values, because unions and structures (which have modes @code{SImode} or
2059 @code{DImode}) can be in those registers and they may have floating
2062 There may also be a need to support fixed point @samp{mov@var{m}}
2063 instructions in and out of floating point registers. Unfortunately, I
2064 have forgotten why this was so, and I don't know whether it is still
2065 true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
2066 floating point registers, then the constraints of the fixed point
2067 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
2068 reload into a floating point register.
2070 @cindex @code{reload_in} instruction pattern
2071 @cindex @code{reload_out} instruction pattern
2072 @item @samp{reload_in@var{m}}
2073 @itemx @samp{reload_out@var{m}}
2074 Like @samp{mov@var{m}}, but used when a scratch register is required to
2075 move between operand 0 and operand 1. Operand 2 describes the scratch
2076 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
2077 macro in @pxref{Register Classes}.
2079 @cindex @code{movstrict@var{m}} instruction pattern
2080 @item @samp{movstrict@var{m}}
2081 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
2082 with mode @var{m} of a register whose natural mode is wider,
2083 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
2084 any of the register except the part which belongs to mode @var{m}.
2086 @cindex @code{load_multiple} instruction pattern
2087 @item @samp{load_multiple}
2088 Load several consecutive memory locations into consecutive registers.
2089 Operand 0 is the first of the consecutive registers, operand 1
2090 is the first memory location, and operand 2 is a constant: the
2091 number of consecutive registers.
2093 Define this only if the target machine really has such an instruction;
2094 do not define this if the most efficient way of loading consecutive
2095 registers from memory is to do them one at a time.
2097 On some machines, there are restrictions as to which consecutive
2098 registers can be stored into memory, such as particular starting or
2099 ending register numbers or only a range of valid counts. For those
2100 machines, use a @code{define_expand} (@pxref{Expander Definitions})
2101 and make the pattern fail if the restrictions are not met.
2103 Write the generated insn as a @code{parallel} with elements being a
2104 @code{set} of one register from the appropriate memory location (you may
2105 also need @code{use} or @code{clobber} elements). Use a
2106 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
2107 @file{a29k.md} and @file{rs6000.md} for examples of the use of this insn
2110 @cindex @samp{store_multiple} instruction pattern
2111 @item @samp{store_multiple}
2112 Similar to @samp{load_multiple}, but store several consecutive registers
2113 into consecutive memory locations. Operand 0 is the first of the
2114 consecutive memory locations, operand 1 is the first register, and
2115 operand 2 is a constant: the number of consecutive registers.
2117 @cindex @code{add@var{m}3} instruction pattern
2118 @item @samp{add@var{m}3}
2119 Add operand 2 and operand 1, storing the result in operand 0. All operands
2120 must have mode @var{m}. This can be used even on two-address machines, by
2121 means of constraints requiring operands 1 and 0 to be the same location.
2123 @cindex @code{sub@var{m}3} instruction pattern
2124 @cindex @code{mul@var{m}3} instruction pattern
2125 @cindex @code{div@var{m}3} instruction pattern
2126 @cindex @code{udiv@var{m}3} instruction pattern
2127 @cindex @code{mod@var{m}3} instruction pattern
2128 @cindex @code{umod@var{m}3} instruction pattern
2129 @cindex @code{smin@var{m}3} instruction pattern
2130 @cindex @code{smax@var{m}3} instruction pattern
2131 @cindex @code{umin@var{m}3} instruction pattern
2132 @cindex @code{umax@var{m}3} instruction pattern
2133 @cindex @code{and@var{m}3} instruction pattern
2134 @cindex @code{ior@var{m}3} instruction pattern
2135 @cindex @code{xor@var{m}3} instruction pattern
2136 @item @samp{sub@var{m}3}, @samp{mul@var{m}3}
2137 @itemx @samp{div@var{m}3}, @samp{udiv@var{m}3}, @samp{mod@var{m}3}, @samp{umod@var{m}3}
2138 @itemx @samp{smin@var{m}3}, @samp{smax@var{m}3}, @samp{umin@var{m}3}, @samp{umax@var{m}3}
2139 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
2140 Similar, for other arithmetic operations.
2141 @cindex @code{min@var{m}3} instruction pattern
2142 @cindex @code{max@var{m}3} instruction pattern
2143 @itemx @samp{min@var{m}3}, @samp{max@var{m}3}
2144 Floating point min and max operations. If both operands are zeros,
2145 or if either operand is NaN, then it is unspecified which of the two
2146 operands is returned as the result.
2149 @cindex @code{mulhisi3} instruction pattern
2150 @item @samp{mulhisi3}
2151 Multiply operands 1 and 2, which have mode @code{HImode}, and store
2152 a @code{SImode} product in operand 0.
2154 @cindex @code{mulqihi3} instruction pattern
2155 @cindex @code{mulsidi3} instruction pattern
2156 @item @samp{mulqihi3}, @samp{mulsidi3}
2157 Similar widening-multiplication instructions of other widths.
2159 @cindex @code{umulqihi3} instruction pattern
2160 @cindex @code{umulhisi3} instruction pattern
2161 @cindex @code{umulsidi3} instruction pattern
2162 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
2163 Similar widening-multiplication instructions that do unsigned
2166 @cindex @code{smul@var{m}3_highpart} instruction pattern
2167 @item @samp{smul@var{m}3_highpart}
2168 Perform a signed multiplication of operands 1 and 2, which have mode
2169 @var{m}, and store the most significant half of the product in operand 0.
2170 The least significant half of the product is discarded.
2172 @cindex @code{umul@var{m}3_highpart} instruction pattern
2173 @item @samp{umul@var{m}3_highpart}
2174 Similar, but the multiplication is unsigned.
2176 @cindex @code{divmod@var{m}4} instruction pattern
2177 @item @samp{divmod@var{m}4}
2178 Signed division that produces both a quotient and a remainder.
2179 Operand 1 is divided by operand 2 to produce a quotient stored
2180 in operand 0 and a remainder stored in operand 3.
2182 For machines with an instruction that produces both a quotient and a
2183 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
2184 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
2185 allows optimization in the relatively common case when both the quotient
2186 and remainder are computed.
2188 If an instruction that just produces a quotient or just a remainder
2189 exists and is more efficient than the instruction that produces both,
2190 write the output routine of @samp{divmod@var{m}4} to call
2191 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
2192 quotient or remainder and generate the appropriate instruction.
2194 @cindex @code{udivmod@var{m}4} instruction pattern
2195 @item @samp{udivmod@var{m}4}
2196 Similar, but does unsigned division.
2198 @cindex @code{ashl@var{m}3} instruction pattern
2199 @item @samp{ashl@var{m}3}
2200 Arithmetic-shift operand 1 left by a number of bits specified by operand
2201 2, and store the result in operand 0. Here @var{m} is the mode of
2202 operand 0 and operand 1; operand 2's mode is specified by the
2203 instruction pattern, and the compiler will convert the operand to that
2204 mode before generating the instruction.
2206 @cindex @code{ashr@var{m}3} instruction pattern
2207 @cindex @code{lshr@var{m}3} instruction pattern
2208 @cindex @code{rotl@var{m}3} instruction pattern
2209 @cindex @code{rotr@var{m}3} instruction pattern
2210 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
2211 Other shift and rotate instructions, analogous to the
2212 @code{ashl@var{m}3} instructions.
2214 @cindex @code{neg@var{m}2} instruction pattern
2215 @item @samp{neg@var{m}2}
2216 Negate operand 1 and store the result in operand 0.
2218 @cindex @code{abs@var{m}2} instruction pattern
2219 @item @samp{abs@var{m}2}
2220 Store the absolute value of operand 1 into operand 0.
2222 @cindex @code{sqrt@var{m}2} instruction pattern
2223 @item @samp{sqrt@var{m}2}
2224 Store the square root of operand 1 into operand 0.
2226 The @code{sqrt} built-in function of C always uses the mode which
2227 corresponds to the C data type @code{double}.
2229 @cindex @code{ffs@var{m}2} instruction pattern
2230 @item @samp{ffs@var{m}2}
2231 Store into operand 0 one plus the index of the least significant 1-bit
2232 of operand 1. If operand 1 is zero, store zero. @var{m} is the mode
2233 of operand 0; operand 1's mode is specified by the instruction
2234 pattern, and the compiler will convert the operand to that mode before
2235 generating the instruction.
2237 The @code{ffs} built-in function of C always uses the mode which
2238 corresponds to the C data type @code{int}.
2240 @cindex @code{one_cmpl@var{m}2} instruction pattern
2241 @item @samp{one_cmpl@var{m}2}
2242 Store the bitwise-complement of operand 1 into operand 0.
2244 @cindex @code{cmp@var{m}} instruction pattern
2245 @item @samp{cmp@var{m}}
2246 Compare operand 0 and operand 1, and set the condition codes.
2247 The RTL pattern should look like this:
2250 (set (cc0) (compare (match_operand:@var{m} 0 @dots{})
2251 (match_operand:@var{m} 1 @dots{})))
2254 @cindex @code{tst@var{m}} instruction pattern
2255 @item @samp{tst@var{m}}
2256 Compare operand 0 against zero, and set the condition codes.
2257 The RTL pattern should look like this:
2260 (set (cc0) (match_operand:@var{m} 0 @dots{}))
2263 @samp{tst@var{m}} patterns should not be defined for machines that do
2264 not use @code{(cc0)}. Doing so would confuse the optimizer since it
2265 would no longer be clear which @code{set} operations were comparisons.
2266 The @samp{cmp@var{m}} patterns should be used instead.
2268 @cindex @code{movstr@var{m}} instruction pattern
2269 @item @samp{movstr@var{m}}
2270 Block move instruction. The addresses of the destination and source
2271 strings are the first two operands, and both are in mode @code{Pmode}.
2273 The number of bytes to move is the third operand, in mode @var{m}.
2274 Usually, you specify @code{word_mode} for @var{m}. However, if you can
2275 generate better code knowing the range of valid lengths is smaller than
2276 those representable in a full word, you should provide a pattern with a
2277 mode corresponding to the range of values you can handle efficiently
2278 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
2279 that appear negative) and also a pattern with @code{word_mode}.
2281 The fourth operand is the known shared alignment of the source and
2282 destination, in the form of a @code{const_int} rtx. Thus, if the
2283 compiler knows that both source and destination are word-aligned,
2284 it may provide the value 4 for this operand.
2286 Descriptions of multiple @code{movstr@var{m}} patterns can only be
2287 beneficial if the patterns for smaller modes have fewer restrictions
2288 on their first, second and fourth operands. Note that the mode @var{m}
2289 in @code{movstr@var{m}} does not impose any restriction on the mode of
2290 individually moved data units in the block.
2292 These patterns need not give special consideration to the possibility
2293 that the source and destination strings might overlap.
2295 @cindex @code{clrstr@var{m}} instruction pattern
2296 @item @samp{clrstr@var{m}}
2297 Block clear instruction. The addresses of the destination string is the
2298 first operand, in mode @code{Pmode}. The number of bytes to clear is
2299 the second operand, in mode @var{m}. See @samp{movstr@var{m}} for
2300 a discussion of the choice of mode.
2302 The third operand is the known alignment of the destination, in the form
2303 of a @code{const_int} rtx. Thus, if the compiler knows that the
2304 destination is word-aligned, it may provide the value 4 for this
2307 The use for multiple @code{clrstr@var{m}} is as for @code{movstr@var{m}}.
2309 @cindex @code{cmpstr@var{m}} instruction pattern
2310 @item @samp{cmpstr@var{m}}
2311 Block compare instruction, with five operands. Operand 0 is the output;
2312 it has mode @var{m}. The remaining four operands are like the operands
2313 of @samp{movstr@var{m}}. The two memory blocks specified are compared
2314 byte by byte in lexicographic order. The effect of the instruction is
2315 to store a value in operand 0 whose sign indicates the result of the
2318 @cindex @code{strlen@var{m}} instruction pattern
2319 @item @samp{strlen@var{m}}
2320 Compute the length of a string, with three operands.
2321 Operand 0 is the result (of mode @var{m}), operand 1 is
2322 a @code{mem} referring to the first character of the string,
2323 operand 2 is the character to search for (normally zero),
2324 and operand 3 is a constant describing the known alignment
2325 of the beginning of the string.
2327 @cindex @code{float@var{mn}2} instruction pattern
2328 @item @samp{float@var{m}@var{n}2}
2329 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
2330 floating point mode @var{n} and store in operand 0 (which has mode
2333 @cindex @code{floatuns@var{mn}2} instruction pattern
2334 @item @samp{floatuns@var{m}@var{n}2}
2335 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
2336 to floating point mode @var{n} and store in operand 0 (which has mode
2339 @cindex @code{fix@var{mn}2} instruction pattern
2340 @item @samp{fix@var{m}@var{n}2}
2341 Convert operand 1 (valid for floating point mode @var{m}) to fixed
2342 point mode @var{n} as a signed number and store in operand 0 (which
2343 has mode @var{n}). This instruction's result is defined only when
2344 the value of operand 1 is an integer.
2346 @cindex @code{fixuns@var{mn}2} instruction pattern
2347 @item @samp{fixuns@var{m}@var{n}2}
2348 Convert operand 1 (valid for floating point mode @var{m}) to fixed
2349 point mode @var{n} as an unsigned number and store in operand 0 (which
2350 has mode @var{n}). This instruction's result is defined only when the
2351 value of operand 1 is an integer.
2353 @cindex @code{ftrunc@var{m}2} instruction pattern
2354 @item @samp{ftrunc@var{m}2}
2355 Convert operand 1 (valid for floating point mode @var{m}) to an
2356 integer value, still represented in floating point mode @var{m}, and
2357 store it in operand 0 (valid for floating point mode @var{m}).
2359 @cindex @code{fix_trunc@var{mn}2} instruction pattern
2360 @item @samp{fix_trunc@var{m}@var{n}2}
2361 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
2362 of mode @var{m} by converting the value to an integer.
2364 @cindex @code{fixuns_trunc@var{mn}2} instruction pattern
2365 @item @samp{fixuns_trunc@var{m}@var{n}2}
2366 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
2367 value of mode @var{m} by converting the value to an integer.
2369 @cindex @code{trunc@var{mn}2} instruction pattern
2370 @item @samp{trunc@var{m}@var{n}2}
2371 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
2372 store in operand 0 (which has mode @var{n}). Both modes must be fixed
2373 point or both floating point.
2375 @cindex @code{extend@var{mn}2} instruction pattern
2376 @item @samp{extend@var{m}@var{n}2}
2377 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
2378 store in operand 0 (which has mode @var{n}). Both modes must be fixed
2379 point or both floating point.
2381 @cindex @code{zero_extend@var{mn}2} instruction pattern
2382 @item @samp{zero_extend@var{m}@var{n}2}
2383 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
2384 store in operand 0 (which has mode @var{n}). Both modes must be fixed
2387 @cindex @code{extv} instruction pattern
2389 Extract a bit-field from operand 1 (a register or memory operand), where
2390 operand 2 specifies the width in bits and operand 3 the starting bit,
2391 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
2392 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
2393 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
2394 be valid for @code{word_mode}.
2396 The RTL generation pass generates this instruction only with constants
2397 for operands 2 and 3.
2399 The bit-field value is sign-extended to a full word integer
2400 before it is stored in operand 0.
2402 @cindex @code{extzv} instruction pattern
2404 Like @samp{extv} except that the bit-field value is zero-extended.
2406 @cindex @code{insv} instruction pattern
2408 Store operand 3 (which must be valid for @code{word_mode}) into a
2409 bit-field in operand 0, where operand 1 specifies the width in bits and
2410 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
2411 @code{word_mode}; often @code{word_mode} is allowed only for registers.
2412 Operands 1 and 2 must be valid for @code{word_mode}.
2414 The RTL generation pass generates this instruction only with constants
2415 for operands 1 and 2.
2417 @cindex @code{mov@var{mode}cc} instruction pattern
2418 @item @samp{mov@var{mode}cc}
2419 Conditionally move operand 2 or operand 3 into operand 0 according to the
2420 comparison in operand 1. If the comparison is true, operand 2 is moved
2421 into operand 0, otherwise operand 3 is moved.
2423 The mode of the operands being compared need not be the same as the operands
2424 being moved. Some machines, sparc64 for example, have instructions that
2425 conditionally move an integer value based on the floating point condition
2426 codes and vice versa.
2428 If the machine does not have conditional move instructions, do not
2429 define these patterns.
2431 @cindex @code{s@var{cond}} instruction pattern
2432 @item @samp{s@var{cond}}
2433 Store zero or nonzero in the operand according to the condition codes.
2434 Value stored is nonzero iff the condition @var{cond} is true.
2435 @var{cond} is the name of a comparison operation expression code, such
2436 as @code{eq}, @code{lt} or @code{leu}.
2438 You specify the mode that the operand must have when you write the
2439 @code{match_operand} expression. The compiler automatically sees
2440 which mode you have used and supplies an operand of that mode.
2442 The value stored for a true condition must have 1 as its low bit, or
2443 else must be negative. Otherwise the instruction is not suitable and
2444 you should omit it from the machine description. You describe to the
2445 compiler exactly which value is stored by defining the macro
2446 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
2447 found that can be used for all the @samp{s@var{cond}} patterns, you
2448 should omit those operations from the machine description.
2450 These operations may fail, but should do so only in relatively
2451 uncommon cases; if they would fail for common cases involving
2452 integer comparisons, it is best to omit these patterns.
2454 If these operations are omitted, the compiler will usually generate code
2455 that copies the constant one to the target and branches around an
2456 assignment of zero to the target. If this code is more efficient than
2457 the potential instructions used for the @samp{s@var{cond}} pattern
2458 followed by those required to convert the result into a 1 or a zero in
2459 @code{SImode}, you should omit the @samp{s@var{cond}} operations from
2460 the machine description.
2462 @cindex @code{b@var{cond}} instruction pattern
2463 @item @samp{b@var{cond}}
2464 Conditional branch instruction. Operand 0 is a @code{label_ref} that
2465 refers to the label to jump to. Jump if the condition codes meet
2466 condition @var{cond}.
2468 Some machines do not follow the model assumed here where a comparison
2469 instruction is followed by a conditional branch instruction. In that
2470 case, the @samp{cmp@var{m}} (and @samp{tst@var{m}}) patterns should
2471 simply store the operands away and generate all the required insns in a
2472 @code{define_expand} (@pxref{Expander Definitions}) for the conditional
2473 branch operations. All calls to expand @samp{b@var{cond}} patterns are
2474 immediately preceded by calls to expand either a @samp{cmp@var{m}}
2475 pattern or a @samp{tst@var{m}} pattern.
2477 Machines that use a pseudo register for the condition code value, or
2478 where the mode used for the comparison depends on the condition being
2479 tested, should also use the above mechanism. @xref{Jump Patterns}.
2481 The above discussion also applies to the @samp{mov@var{mode}cc} and
2482 @samp{s@var{cond}} patterns.
2484 @cindex @code{jump} instruction pattern
2486 A jump inside a function; an unconditional branch. Operand 0 is the
2487 @code{label_ref} of the label to jump to. This pattern name is mandatory
2490 @cindex @code{call} instruction pattern
2492 Subroutine call instruction returning no value. Operand 0 is the
2493 function to call; operand 1 is the number of bytes of arguments pushed
2494 as a @code{const_int}; operand 2 is the number of registers used as
2497 On most machines, operand 2 is not actually stored into the RTL
2498 pattern. It is supplied for the sake of some RISC machines which need
2499 to put this information into the assembler code; they can put it in
2500 the RTL instead of operand 1.
2502 Operand 0 should be a @code{mem} RTX whose address is the address of the
2503 function. Note, however, that this address can be a @code{symbol_ref}
2504 expression even if it would not be a legitimate memory address on the
2505 target machine. If it is also not a valid argument for a call
2506 instruction, the pattern for this operation should be a
2507 @code{define_expand} (@pxref{Expander Definitions}) that places the
2508 address into a register and uses that register in the call instruction.
2510 @cindex @code{call_value} instruction pattern
2511 @item @samp{call_value}
2512 Subroutine call instruction returning a value. Operand 0 is the hard
2513 register in which the value is returned. There are three more
2514 operands, the same as the three operands of the @samp{call}
2515 instruction (but with numbers increased by one).
2517 Subroutines that return @code{BLKmode} objects use the @samp{call}
2520 @cindex @code{call_pop} instruction pattern
2521 @cindex @code{call_value_pop} instruction pattern
2522 @item @samp{call_pop}, @samp{call_value_pop}
2523 Similar to @samp{call} and @samp{call_value}, except used if defined and
2524 if @code{RETURN_POPS_ARGS} is non-zero. They should emit a @code{parallel}
2525 that contains both the function call and a @code{set} to indicate the
2526 adjustment made to the frame pointer.
2528 For machines where @code{RETURN_POPS_ARGS} can be non-zero, the use of these
2529 patterns increases the number of functions for which the frame pointer
2530 can be eliminated, if desired.
2532 @cindex @code{untyped_call} instruction pattern
2533 @item @samp{untyped_call}
2534 Subroutine call instruction returning a value of any type. Operand 0 is
2535 the function to call; operand 1 is a memory location where the result of
2536 calling the function is to be stored; operand 2 is a @code{parallel}
2537 expression where each element is a @code{set} expression that indicates
2538 the saving of a function return value into the result block.
2540 This instruction pattern should be defined to support
2541 @code{__builtin_apply} on machines where special instructions are needed
2542 to call a subroutine with arbitrary arguments or to save the value
2543 returned. This instruction pattern is required on machines that have
2544 multiple registers that can hold a return value
2545 (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
2547 @cindex @code{return} instruction pattern
2549 Subroutine return instruction. This instruction pattern name should be
2550 defined only if a single instruction can do all the work of returning
2553 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
2554 RTL generation phase. In this case it is to support machines where
2555 multiple instructions are usually needed to return from a function, but
2556 some class of functions only requires one instruction to implement a
2557 return. Normally, the applicable functions are those which do not need
2558 to save any registers or allocate stack space.
2560 @findex reload_completed
2561 @findex leaf_function_p
2562 For such machines, the condition specified in this pattern should only
2563 be true when @code{reload_completed} is non-zero and the function's
2564 epilogue would only be a single instruction. For machines with register
2565 windows, the routine @code{leaf_function_p} may be used to determine if
2566 a register window push is required.
2568 Machines that have conditional return instructions should define patterns
2574 (if_then_else (match_operator
2575 0 "comparison_operator"
2576 [(cc0) (const_int 0)])
2583 where @var{condition} would normally be the same condition specified on the
2584 named @samp{return} pattern.
2586 @cindex @code{untyped_return} instruction pattern
2587 @item @samp{untyped_return}
2588 Untyped subroutine return instruction. This instruction pattern should
2589 be defined to support @code{__builtin_return} on machines where special
2590 instructions are needed to return a value of any type.
2592 Operand 0 is a memory location where the result of calling a function
2593 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
2594 expression where each element is a @code{set} expression that indicates
2595 the restoring of a function return value from the result block.
2597 @cindex @code{nop} instruction pattern
2599 No-op instruction. This instruction pattern name should always be defined
2600 to output a no-op in assembler code. @code{(const_int 0)} will do as an
2603 @cindex @code{indirect_jump} instruction pattern
2604 @item @samp{indirect_jump}
2605 An instruction to jump to an address which is operand zero.
2606 This pattern name is mandatory on all machines.
2608 @cindex @code{casesi} instruction pattern
2610 Instruction to jump through a dispatch table, including bounds checking.
2611 This instruction takes five operands:
2615 The index to dispatch on, which has mode @code{SImode}.
2618 The lower bound for indices in the table, an integer constant.
2621 The total range of indices in the table---the largest index
2622 minus the smallest one (both inclusive).
2625 A label that precedes the table itself.
2628 A label to jump to if the index has a value outside the bounds.
2629 (If the machine-description macro @code{CASE_DROPS_THROUGH} is defined,
2630 then an out-of-bounds index drops through to the code following
2631 the jump table instead of jumping to this label. In that case,
2632 this label is not actually used by the @samp{casesi} instruction,
2633 but it is always provided as an operand.)
2636 The table is a @code{addr_vec} or @code{addr_diff_vec} inside of a
2637 @code{jump_insn}. The number of elements in the table is one plus the
2638 difference between the upper bound and the lower bound.
2640 @cindex @code{tablejump} instruction pattern
2641 @item @samp{tablejump}
2642 Instruction to jump to a variable address. This is a low-level
2643 capability which can be used to implement a dispatch table when there
2644 is no @samp{casesi} pattern.
2646 This pattern requires two operands: the address or offset, and a label
2647 which should immediately precede the jump table. If the macro
2648 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
2649 operand is an offset which counts from the address of the table; otherwise,
2650 it is an absolute address to jump to. In either case, the first operand has
2653 The @samp{tablejump} insn is always the last insn before the jump
2654 table it uses. Its assembler code normally has no need to use the
2655 second operand, but you should incorporate it in the RTL pattern so
2656 that the jump optimizer will not delete the table as unreachable code.
2659 @cindex @code{decrement_and_branch_until_zero} instruction pattern
2660 @item @samp{decrement_and_branch_until_zero}
2661 Conditional branch instruction that decrements a register and
2662 jumps if the register is non-zero. Operand 0 is the register to
2663 decrement and test; operand 1 is the label to jump to if the
2664 register is non-zero. @xref{Looping Patterns}.
2666 This optional instruction pattern is only used by the combiner,
2667 typically for loops reversed by the loop optimizer when strength
2668 reduction is enabled.
2670 @cindex @code{doloop_end} instruction pattern
2671 @item @samp{doloop_end}
2672 Conditional branch instruction that decrements a register and jumps if
2673 the register is non-zero. This instruction takes five operands: Operand
2674 0 is the register to decrement and test; operand 1 is the number of loop
2675 iterations as a @code{const_int} or @code{const0_rtx} if this cannot be
2676 determined until run-time; operand 2 is the actual or estimated maximum
2677 number of iterations as a @code{const_int}; operand 3 is the number of
2678 enclosed loops as a @code{const_int} (an innermost loop has a value of
2679 1); operand 4 is the label to jump to if the register is non-zero.
2680 @xref{Looping Patterns}.
2682 This optional instruction pattern should be defined for machines with
2683 low-overhead looping instructions as the loop optimizer will try to
2684 modify suitable loops to utilize it. If nested low-overhead looping is
2685 not supported, use a @code{define_expand} (@pxref{Expander Definitions})
2686 and make the pattern fail if operand 3 is not @code{const1_rtx}.
2687 Similarly, if the actual or estimated maximum number of iterations is
2688 too large for this instruction, make it fail.
2690 @cindex @code{doloop_begin} instruction pattern
2691 @item @samp{doloop_begin}
2692 Companion instruction to @code{doloop_end} required for machines that
2693 need to perform some initialisation, such as loading special registers
2694 used by a low-overhead looping instruction. If initialisation insns do
2695 not always need to be emitted, use a @code{define_expand}
2696 (@pxref{Expander Definitions}) and make it fail.
2699 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
2700 @item @samp{canonicalize_funcptr_for_compare}
2701 Canonicalize the function pointer in operand 1 and store the result
2704 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
2705 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
2706 and also has mode @code{Pmode}.
2708 Canonicalization of a function pointer usually involves computing
2709 the address of the function which would be called if the function
2710 pointer were used in an indirect call.
2712 Only define this pattern if function pointers on the target machine
2713 can have different values but still call the same function when
2714 used in an indirect call.
2716 @cindex @code{save_stack_block} instruction pattern
2717 @cindex @code{save_stack_function} instruction pattern
2718 @cindex @code{save_stack_nonlocal} instruction pattern
2719 @cindex @code{restore_stack_block} instruction pattern
2720 @cindex @code{restore_stack_function} instruction pattern
2721 @cindex @code{restore_stack_nonlocal} instruction pattern
2722 @item @samp{save_stack_block}
2723 @itemx @samp{save_stack_function}
2724 @itemx @samp{save_stack_nonlocal}
2725 @itemx @samp{restore_stack_block}
2726 @itemx @samp{restore_stack_function}
2727 @itemx @samp{restore_stack_nonlocal}
2728 Most machines save and restore the stack pointer by copying it to or
2729 from an object of mode @code{Pmode}. Do not define these patterns on
2732 Some machines require special handling for stack pointer saves and
2733 restores. On those machines, define the patterns corresponding to the
2734 non-standard cases by using a @code{define_expand} (@pxref{Expander
2735 Definitions}) that produces the required insns. The three types of
2736 saves and restores are:
2740 @samp{save_stack_block} saves the stack pointer at the start of a block
2741 that allocates a variable-sized object, and @samp{restore_stack_block}
2742 restores the stack pointer when the block is exited.
2745 @samp{save_stack_function} and @samp{restore_stack_function} do a
2746 similar job for the outermost block of a function and are used when the
2747 function allocates variable-sized objects or calls @code{alloca}. Only
2748 the epilogue uses the restored stack pointer, allowing a simpler save or
2749 restore sequence on some machines.
2752 @samp{save_stack_nonlocal} is used in functions that contain labels
2753 branched to by nested functions. It saves the stack pointer in such a
2754 way that the inner function can use @samp{restore_stack_nonlocal} to
2755 restore the stack pointer. The compiler generates code to restore the
2756 frame and argument pointer registers, but some machines require saving
2757 and restoring additional data such as register window information or
2758 stack backchains. Place insns in these patterns to save and restore any
2762 When saving the stack pointer, operand 0 is the save area and operand 1
2763 is the stack pointer. The mode used to allocate the save area defaults
2764 to @code{Pmode} but you can override that choice by defining the
2765 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
2766 specify an integral mode, or @code{VOIDmode} if no save area is needed
2767 for a particular type of save (either because no save is needed or
2768 because a machine-specific save area can be used). Operand 0 is the
2769 stack pointer and operand 1 is the save area for restore operations. If
2770 @samp{save_stack_block} is defined, operand 0 must not be
2771 @code{VOIDmode} since these saves can be arbitrarily nested.
2773 A save area is a @code{mem} that is at a constant offset from
2774 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
2775 nonlocal gotos and a @code{reg} in the other two cases.
2777 @cindex @code{allocate_stack} instruction pattern
2778 @item @samp{allocate_stack}
2779 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
2780 the stack pointer to create space for dynamically allocated data.
2782 Store the resultant pointer to this space into operand 0. If you
2783 are allocating space from the main stack, do this by emitting a
2784 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
2785 If you are allocating the space elsewhere, generate code to copy the
2786 location of the space to operand 0. In the latter case, you must
2787 ensure this space gets freed when the corresponding space on the main
2790 Do not define this pattern if all that must be done is the subtraction.
2791 Some machines require other operations such as stack probes or
2792 maintaining the back chain. Define this pattern to emit those
2793 operations in addition to updating the stack pointer.
2795 @cindex @code{probe} instruction pattern
2797 Some machines require instructions to be executed after space is
2798 allocated from the stack, for example to generate a reference at
2799 the bottom of the stack.
2801 If you need to emit instructions before the stack has been adjusted,
2802 put them into the @samp{allocate_stack} pattern. Otherwise, define
2803 this pattern to emit the required instructions.
2805 No operands are provided.
2807 @cindex @code{check_stack} instruction pattern
2808 @item @samp{check_stack}
2809 If stack checking cannot be done on your system by probing the stack with
2810 a load or store instruction (@pxref{Stack Checking}), define this pattern
2811 to perform the needed check and signaling an error if the stack
2812 has overflowed. The single operand is the location in the stack furthest
2813 from the current stack pointer that you need to validate. Normally,
2814 on machines where this pattern is needed, you would obtain the stack
2815 limit from a global or thread-specific variable or register.
2817 @cindex @code{nonlocal_goto} instruction pattern
2818 @item @samp{nonlocal_goto}
2819 Emit code to generate a non-local goto, e.g., a jump from one function
2820 to a label in an outer function. This pattern has four arguments,
2821 each representing a value to be used in the jump. The first
2822 argument is to be loaded into the frame pointer, the second is
2823 the address to branch to (code to dispatch to the actual label),
2824 the third is the address of a location where the stack is saved,
2825 and the last is the address of the label, to be placed in the
2826 location for the incoming static chain.
2828 On most machines you need not define this pattern, since GCC will
2829 already generate the correct code, which is to load the frame pointer
2830 and static chain, restore the stack (using the
2831 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
2832 to the dispatcher. You need only define this pattern if this code will
2833 not work on your machine.
2835 @cindex @code{nonlocal_goto_receiver} instruction pattern
2836 @item @samp{nonlocal_goto_receiver}
2837 This pattern, if defined, contains code needed at the target of a
2838 nonlocal goto after the code already generated by GCC@. You will not
2839 normally need to define this pattern. A typical reason why you might
2840 need this pattern is if some value, such as a pointer to a global table,
2841 must be restored when the frame pointer is restored. Note that a nonlocal
2842 goto only occurs within a unit-of-translation, so a global table pointer
2843 that is shared by all functions of a given module need not be restored.
2844 There are no arguments.
2846 @cindex @code{exception_receiver} instruction pattern
2847 @item @samp{exception_receiver}
2848 This pattern, if defined, contains code needed at the site of an
2849 exception handler that isn't needed at the site of a nonlocal goto. You
2850 will not normally need to define this pattern. A typical reason why you
2851 might need this pattern is if some value, such as a pointer to a global
2852 table, must be restored after control flow is branched to the handler of
2853 an exception. There are no arguments.
2855 @cindex @code{builtin_setjmp_setup} instruction pattern
2856 @item @samp{builtin_setjmp_setup}
2857 This pattern, if defined, contains additional code needed to initialize
2858 the @code{jmp_buf}. You will not normally need to define this pattern.
2859 A typical reason why you might need this pattern is if some value, such
2860 as a pointer to a global table, must be restored. Though it is
2861 preferred that the pointer value be recalculated if possible (given the
2862 address of a label for instance). The single argument is a pointer to
2863 the @code{jmp_buf}. Note that the buffer is five words long and that
2864 the first three are normally used by the generic mechanism.
2866 @cindex @code{builtin_setjmp_receiver} instruction pattern
2867 @item @samp{builtin_setjmp_receiver}
2868 This pattern, if defined, contains code needed at the site of an
2869 built-in setjmp that isn't needed at the site of a nonlocal goto. You
2870 will not normally need to define this pattern. A typical reason why you
2871 might need this pattern is if some value, such as a pointer to a global
2872 table, must be restored. It takes one argument, which is the label
2873 to which builtin_longjmp transfered control; this pattern may be emitted
2874 at a small offset from that label.
2876 @cindex @code{builtin_longjmp} instruction pattern
2877 @item @samp{builtin_longjmp}
2878 This pattern, if defined, performs the entire action of the longjmp.
2879 You will not normally need to define this pattern unless you also define
2880 @code{builtin_setjmp_setup}. The single argument is a pointer to the
2883 @cindex @code{eh_return} instruction pattern
2884 @item @samp{eh_return}
2885 This pattern, if defined, affects the way @code{__builtin_eh_return},
2886 and thence the call frame exception handling library routines, are
2887 built. It is intended to handle non-trivial actions needed along
2888 the abnormal return path.
2890 The pattern takes two arguments. The first is an offset to be applied
2891 to the stack pointer. It will have been copied to some appropriate
2892 location (typically @code{EH_RETURN_STACKADJ_RTX}) which will survive
2893 until after reload to when the normal epilogue is generated.
2894 The second argument is the address of the exception handler to which
2895 the function should return. This will normally need to copied by the
2896 pattern to some special register or memory location.
2898 This pattern only needs to be defined if call frame exception handling
2899 is to be used, and simple moves to @code{EH_RETURN_STACKADJ_RTX} and
2900 @code{EH_RETURN_HANDLER_RTX} are not sufficient.
2902 @cindex @code{prologue} instruction pattern
2903 @item @samp{prologue}
2904 This pattern, if defined, emits RTL for entry to a function. The function
2905 entry is responsible for setting up the stack frame, initializing the frame
2906 pointer register, saving callee saved registers, etc.
2908 Using a prologue pattern is generally preferred over defining
2909 @code{FUNCTION_PROLOGUE} to emit assembly code for the prologue.
2911 The @code{prologue} pattern is particularly useful for targets which perform
2912 instruction scheduling.
2914 @cindex @code{epilogue} instruction pattern
2915 @item @samp{epilogue}
2916 This pattern, if defined, emits RTL for exit from a function. The function
2917 exit is responsible for deallocating the stack frame, restoring callee saved
2918 registers and emitting the return instruction.
2920 Using an epilogue pattern is generally preferred over defining
2921 @code{FUNCTION_EPILOGUE} to emit assembly code for the prologue.
2923 The @code{epilogue} pattern is particularly useful for targets which perform
2924 instruction scheduling or which have delay slots for their return instruction.
2926 @cindex @code{sibcall_epilogue} instruction pattern
2927 @item @samp{sibcall_epilogue}
2928 This pattern, if defined, emits RTL for exit from a function without the final
2929 branch back to the calling function. This pattern will be emitted before any
2930 sibling call (aka tail call) sites.
2932 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
2933 parameter passing or any stack slots for arguments passed to the current
2936 @cindex @code{trap} instruction pattern
2938 This pattern, if defined, signals an error, typically by causing some
2939 kind of signal to be raised. Among other places, it is used by the Java
2940 front end to signal `invalid array index' exceptions.
2942 @cindex @code{conditional_trap} instruction pattern
2943 @item @samp{conditional_trap}
2944 Conditional trap instruction. Operand 0 is a piece of RTL which
2945 performs a comparison. Operand 1 is the trap code, an integer.
2947 A typical @code{conditional_trap} pattern looks like
2950 (define_insn "conditional_trap"
2951 [(trap_if (match_operator 0 "trap_operator"
2952 [(cc0) (const_int 0)])
2953 (match_operand 1 "const_int_operand" "i"))]
2958 @cindex @code{cycle_display} instruction pattern
2959 @item @samp{cycle_display}
2961 This pattern, if present, will be emitted by the instruction scheduler at
2962 the beginning of each new clock cycle. This can be used for annotating the
2963 assembler output with cycle counts. Operand 0 is a @code{const_int} that
2964 holds the clock cycle.
2968 @node Pattern Ordering
2969 @section When the Order of Patterns Matters
2970 @cindex Pattern Ordering
2971 @cindex Ordering of Patterns
2973 Sometimes an insn can match more than one instruction pattern. Then the
2974 pattern that appears first in the machine description is the one used.
2975 Therefore, more specific patterns (patterns that will match fewer things)
2976 and faster instructions (those that will produce better code when they
2977 do match) should usually go first in the description.
2979 In some cases the effect of ordering the patterns can be used to hide
2980 a pattern when it is not valid. For example, the 68000 has an
2981 instruction for converting a fullword to floating point and another
2982 for converting a byte to floating point. An instruction converting
2983 an integer to floating point could match either one. We put the
2984 pattern to convert the fullword first to make sure that one will
2985 be used rather than the other. (Otherwise a large integer might
2986 be generated as a single-byte immediate quantity, which would not work.)
2987 Instead of using this pattern ordering it would be possible to make the
2988 pattern for convert-a-byte smart enough to deal properly with any
2991 @node Dependent Patterns
2992 @section Interdependence of Patterns
2993 @cindex Dependent Patterns
2994 @cindex Interdependence of Patterns
2996 Every machine description must have a named pattern for each of the
2997 conditional branch names @samp{b@var{cond}}. The recognition template
2998 must always have the form
3002 (if_then_else (@var{cond} (cc0) (const_int 0))
3003 (label_ref (match_operand 0 "" ""))
3008 In addition, every machine description must have an anonymous pattern
3009 for each of the possible reverse-conditional branches. Their templates
3014 (if_then_else (@var{cond} (cc0) (const_int 0))
3016 (label_ref (match_operand 0 "" ""))))
3020 They are necessary because jump optimization can turn direct-conditional
3021 branches into reverse-conditional branches.
3023 It is often convenient to use the @code{match_operator} construct to
3024 reduce the number of patterns that must be specified for branches. For
3030 (if_then_else (match_operator 0 "comparison_operator"
3031 [(cc0) (const_int 0)])
3033 (label_ref (match_operand 1 "" ""))))]
3038 In some cases machines support instructions identical except for the
3039 machine mode of one or more operands. For example, there may be
3040 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
3044 (set (match_operand:SI 0 @dots{})
3045 (extend:SI (match_operand:HI 1 @dots{})))
3047 (set (match_operand:SI 0 @dots{})
3048 (extend:SI (match_operand:QI 1 @dots{})))
3052 Constant integers do not specify a machine mode, so an instruction to
3053 extend a constant value could match either pattern. The pattern it
3054 actually will match is the one that appears first in the file. For correct
3055 results, this must be the one for the widest possible mode (@code{HImode},
3056 here). If the pattern matches the @code{QImode} instruction, the results
3057 will be incorrect if the constant value does not actually fit that mode.
3059 Such instructions to extend constants are rarely generated because they are
3060 optimized away, but they do occasionally happen in nonoptimized
3063 If a constraint in a pattern allows a constant, the reload pass may
3064 replace a register with a constant permitted by the constraint in some
3065 cases. Similarly for memory references. Because of this substitution,
3066 you should not provide separate patterns for increment and decrement
3067 instructions. Instead, they should be generated from the same pattern
3068 that supports register-register add insns by examining the operands and
3069 generating the appropriate machine instruction.
3072 @section Defining Jump Instruction Patterns
3073 @cindex jump instruction patterns
3074 @cindex defining jump instruction patterns
3076 For most machines, GCC assumes that the machine has a condition code.
3077 A comparison insn sets the condition code, recording the results of both
3078 signed and unsigned comparison of the given operands. A separate branch
3079 insn tests the condition code and branches or not according its value.
3080 The branch insns come in distinct signed and unsigned flavors. Many
3081 common machines, such as the Vax, the 68000 and the 32000, work this
3084 Some machines have distinct signed and unsigned compare instructions, and
3085 only one set of conditional branch instructions. The easiest way to handle
3086 these machines is to treat them just like the others until the final stage
3087 where assembly code is written. At this time, when outputting code for the
3088 compare instruction, peek ahead at the following branch using
3089 @code{next_cc0_user (insn)}. (The variable @code{insn} refers to the insn
3090 being output, in the output-writing code in an instruction pattern.) If
3091 the RTL says that is an unsigned branch, output an unsigned compare;
3092 otherwise output a signed compare. When the branch itself is output, you
3093 can treat signed and unsigned branches identically.
3095 The reason you can do this is that GCC always generates a pair of
3096 consecutive RTL insns, possibly separated by @code{note} insns, one to
3097 set the condition code and one to test it, and keeps the pair inviolate
3100 To go with this technique, you must define the machine-description macro
3101 @code{NOTICE_UPDATE_CC} to do @code{CC_STATUS_INIT}; in other words, no
3102 compare instruction is superfluous.
3104 Some machines have compare-and-branch instructions and no condition code.
3105 A similar technique works for them. When it is time to ``output'' a
3106 compare instruction, record its operands in two static variables. When
3107 outputting the branch-on-condition-code instruction that follows, actually
3108 output a compare-and-branch instruction that uses the remembered operands.
3110 It also works to define patterns for compare-and-branch instructions.
3111 In optimizing compilation, the pair of compare and branch instructions
3112 will be combined according to these patterns. But this does not happen
3113 if optimization is not requested. So you must use one of the solutions
3114 above in addition to any special patterns you define.
3116 In many RISC machines, most instructions do not affect the condition
3117 code and there may not even be a separate condition code register. On
3118 these machines, the restriction that the definition and use of the
3119 condition code be adjacent insns is not necessary and can prevent
3120 important optimizations. For example, on the IBM RS/6000, there is a
3121 delay for taken branches unless the condition code register is set three
3122 instructions earlier than the conditional branch. The instruction
3123 scheduler cannot perform this optimization if it is not permitted to
3124 separate the definition and use of the condition code register.
3126 On these machines, do not use @code{(cc0)}, but instead use a register
3127 to represent the condition code. If there is a specific condition code
3128 register in the machine, use a hard register. If the condition code or
3129 comparison result can be placed in any general register, or if there are
3130 multiple condition registers, use a pseudo register.
3132 @findex prev_cc0_setter
3133 @findex next_cc0_user
3134 On some machines, the type of branch instruction generated may depend on
3135 the way the condition code was produced; for example, on the 68k and
3136 Sparc, setting the condition code directly from an add or subtract
3137 instruction does not clear the overflow bit the way that a test
3138 instruction does, so a different branch instruction must be used for
3139 some conditional branches. For machines that use @code{(cc0)}, the set
3140 and use of the condition code must be adjacent (separated only by
3141 @code{note} insns) allowing flags in @code{cc_status} to be used.
3142 (@xref{Condition Code}.) Also, the comparison and branch insns can be
3143 located from each other by using the functions @code{prev_cc0_setter}
3144 and @code{next_cc0_user}.
3146 However, this is not true on machines that do not use @code{(cc0)}. On
3147 those machines, no assumptions can be made about the adjacency of the
3148 compare and branch insns and the above methods cannot be used. Instead,
3149 we use the machine mode of the condition code register to record
3150 different formats of the condition code register.
3152 Registers used to store the condition code value should have a mode that
3153 is in class @code{MODE_CC}. Normally, it will be @code{CCmode}. If
3154 additional modes are required (as for the add example mentioned above in
3155 the Sparc), define the macro @code{EXTRA_CC_MODES} to list the
3156 additional modes required (@pxref{Condition Code}). Also define
3157 @code{SELECT_CC_MODE} to choose a mode given an operand of a compare.
3159 If it is known during RTL generation that a different mode will be
3160 required (for example, if the machine has separate compare instructions
3161 for signed and unsigned quantities, like most IBM processors), they can
3162 be specified at that time.
3164 If the cases that require different modes would be made by instruction
3165 combination, the macro @code{SELECT_CC_MODE} determines which machine
3166 mode should be used for the comparison result. The patterns should be
3167 written using that mode. To support the case of the add on the Sparc
3168 discussed above, we have the pattern
3172 [(set (reg:CC_NOOV 0)
3174 (plus:SI (match_operand:SI 0 "register_operand" "%r")
3175 (match_operand:SI 1 "arith_operand" "rI"))
3181 The @code{SELECT_CC_MODE} macro on the Sparc returns @code{CC_NOOVmode}
3182 for comparisons whose argument is a @code{plus}.
3184 @node Looping Patterns
3185 @section Defining Looping Instruction Patterns
3186 @cindex looping instruction patterns
3187 @cindex defining looping instruction patterns
3189 Some machines have special jump instructions that can be utilised to
3190 make loops more efficient. A common example is the 68000 @samp{dbra}
3191 instruction which performs a decrement of a register and a branch if the
3192 result was greater than zero. Other machines, in particular digital
3193 signal processors (DSPs), have special block repeat instructions to
3194 provide low-overhead loop support. For example, the TI TMS320C3x/C4x
3195 DSPs have a block repeat instruction that loads special registers to
3196 mark the top and end of a loop and to count the number of loop
3197 iterations. This avoids the need for fetching and executing a
3198 @samp{dbra}-like instruction and avoids pipeline stalls associated with
3201 GCC has three special named patterns to support low overhead looping,
3202 @samp{decrement_and_branch_until_zero}, @samp{doloop_begin}, and
3203 @samp{doloop_end}. The first pattern,
3204 @samp{decrement_and_branch_until_zero}, is not emitted during RTL
3205 generation but may be emitted during the instruction combination phase.
3206 This requires the assistance of the loop optimizer, using information
3207 collected during strength reduction, to reverse a loop to count down to
3208 zero. Some targets also require the loop optimizer to add a
3209 @code{REG_NONNEG} note to indicate that the iteration count is always
3210 positive. This is needed if the target performs a signed loop
3211 termination test. For example, the 68000 uses a pattern similar to the
3212 following for its @code{dbra} instruction:
3216 (define_insn "decrement_and_branch_until_zero"
3219 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
3222 (label_ref (match_operand 1 "" ""))
3225 (plus:SI (match_dup 0)
3227 "find_reg_note (insn, REG_NONNEG, 0)"
3232 Note that since the insn is both a jump insn and has an output, it must
3233 deal with its own reloads, hence the `m' constraints. Also note that
3234 since this insn is generated by the instruction combination phase
3235 combining two sequential insns together into an implicit parallel insn,
3236 the iteration counter needs to be biased by the same amount as the
3237 decrement operation, in this case @minus{}1. Note that the following similar
3238 pattern will not be matched by the combiner.
3242 (define_insn "decrement_and_branch_until_zero"
3245 (ge (match_operand:SI 0 "general_operand" "+d*am")
3247 (label_ref (match_operand 1 "" ""))
3250 (plus:SI (match_dup 0)
3252 "find_reg_note (insn, REG_NONNEG, 0)"
3257 The other two special looping patterns, @samp{doloop_begin} and
3258 @samp{doloop_end}, are emitted by the loop optimiser for certain
3259 well-behaved loops with a finite number of loop iterations using
3260 information collected during strength reduction.
3262 The @samp{doloop_end} pattern describes the actual looping instruction
3263 (or the implicit looping operation) and the @samp{doloop_begin} pattern
3264 is an optional companion pattern that can be used for initialisation
3265 needed for some low-overhead looping instructions.
3267 Note that some machines require the actual looping instruction to be
3268 emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
3269 the true RTL for a looping instruction at the top of the loop can cause
3270 problems with flow analysis. So instead, a dummy @code{doloop} insn is
3271 emitted at the end of the loop. The machine dependent reorg pass checks
3272 for the presence of this @code{doloop} insn and then searches back to
3273 the top of the loop, where it inserts the true looping insn (provided
3274 there are no instructions in the loop which would cause problems). Any
3275 additional labels can be emitted at this point. In addition, if the
3276 desired special iteration counter register was not allocated, this
3277 machine dependent reorg pass could emit a traditional compare and jump
3280 The essential difference between the
3281 @samp{decrement_and_branch_until_zero} and the @samp{doloop_end}
3282 patterns is that the loop optimizer allocates an additional pseudo
3283 register for the latter as an iteration counter. This pseudo register
3284 cannot be used within the loop (i.e., general induction variables cannot
3285 be derived from it), however, in many cases the loop induction variable
3286 may become redundant and removed by the flow pass.
3289 @node Insn Canonicalizations
3290 @section Canonicalization of Instructions
3291 @cindex canonicalization of instructions
3292 @cindex insn canonicalization
3294 There are often cases where multiple RTL expressions could represent an
3295 operation performed by a single machine instruction. This situation is
3296 most commonly encountered with logical, branch, and multiply-accumulate
3297 instructions. In such cases, the compiler attempts to convert these
3298 multiple RTL expressions into a single canonical form to reduce the
3299 number of insn patterns required.
3301 In addition to algebraic simplifications, following canonicalizations
3306 For commutative and comparison operators, a constant is always made the
3307 second operand. If a machine only supports a constant as the second
3308 operand, only patterns that match a constant in the second operand need
3311 @cindex @code{neg}, canonicalization of
3312 @cindex @code{not}, canonicalization of
3313 @cindex @code{mult}, canonicalization of
3314 @cindex @code{plus}, canonicalization of
3315 @cindex @code{minus}, canonicalization of
3316 For these operators, if only one operand is a @code{neg}, @code{not},
3317 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
3320 @cindex @code{compare}, canonicalization of
3322 For the @code{compare} operator, a constant is always the second operand
3323 on machines where @code{cc0} is used (@pxref{Jump Patterns}). On other
3324 machines, there are rare cases where the compiler might want to construct
3325 a @code{compare} with a constant as the first operand. However, these
3326 cases are not common enough for it to be worthwhile to provide a pattern
3327 matching a constant as the first operand unless the machine actually has
3328 such an instruction.
3330 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
3331 @code{minus} is made the first operand under the same conditions as
3335 @code{(minus @var{x} (const_int @var{n}))} is converted to
3336 @code{(plus @var{x} (const_int @var{-n}))}.
3339 Within address computations (i.e., inside @code{mem}), a left shift is
3340 converted into the appropriate multiplication by a power of two.
3342 @cindex @code{ior}, canonicalization of
3343 @cindex @code{and}, canonicalization of
3344 @cindex De Morgan's law
3346 De`Morgan's Law is used to move bitwise negation inside a bitwise
3347 logical-and or logical-or operation. If this results in only one
3348 operand being a @code{not} expression, it will be the first one.
3350 A machine that has an instruction that performs a bitwise logical-and of one
3351 operand with the bitwise negation of the other should specify the pattern
3352 for that instruction as
3356 [(set (match_operand:@var{m} 0 @dots{})
3357 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
3358 (match_operand:@var{m} 2 @dots{})))]
3364 Similarly, a pattern for a ``NAND'' instruction should be written
3368 [(set (match_operand:@var{m} 0 @dots{})
3369 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
3370 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
3375 In both cases, it is not necessary to include patterns for the many
3376 logically equivalent RTL expressions.
3378 @cindex @code{xor}, canonicalization of
3380 The only possible RTL expressions involving both bitwise exclusive-or
3381 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
3382 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
3385 The sum of three items, one of which is a constant, will only appear in
3389 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
3393 On machines that do not use @code{cc0},
3394 @code{(compare @var{x} (const_int 0))} will be converted to
3397 @cindex @code{zero_extract}, canonicalization of
3398 @cindex @code{sign_extract}, canonicalization of
3400 Equality comparisons of a group of bits (usually a single bit) with zero
3401 will be written using @code{zero_extract} rather than the equivalent
3402 @code{and} or @code{sign_extract} operations.
3406 @node Expander Definitions
3407 @section Defining RTL Sequences for Code Generation
3408 @cindex expander definitions
3409 @cindex code generation RTL sequences
3410 @cindex defining RTL sequences for code generation
3412 On some target machines, some standard pattern names for RTL generation
3413 cannot be handled with single insn, but a sequence of RTL insns can
3414 represent them. For these target machines, you can write a
3415 @code{define_expand} to specify how to generate the sequence of RTL@.
3417 @findex define_expand
3418 A @code{define_expand} is an RTL expression that looks almost like a
3419 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
3420 only for RTL generation and it can produce more than one RTL insn.
3422 A @code{define_expand} RTX has four operands:
3426 The name. Each @code{define_expand} must have a name, since the only
3427 use for it is to refer to it by name.
3430 The RTL template. This is a vector of RTL expressions representing
3431 a sequence of separate instructions. Unlike @code{define_insn}, there
3432 is no implicit surrounding @code{PARALLEL}.
3435 The condition, a string containing a C expression. This expression is
3436 used to express how the availability of this pattern depends on
3437 subclasses of target machine, selected by command-line options when GCC
3438 is run. This is just like the condition of a @code{define_insn} that
3439 has a standard name. Therefore, the condition (if present) may not
3440 depend on the data in the insn being matched, but only the
3441 target-machine-type flags. The compiler needs to test these conditions
3442 during initialization in order to learn exactly which named instructions
3443 are available in a particular run.
3446 The preparation statements, a string containing zero or more C
3447 statements which are to be executed before RTL code is generated from
3450 Usually these statements prepare temporary registers for use as
3451 internal operands in the RTL template, but they can also generate RTL
3452 insns directly by calling routines such as @code{emit_insn}, etc.
3453 Any such insns precede the ones that come from the RTL template.
3456 Every RTL insn emitted by a @code{define_expand} must match some
3457 @code{define_insn} in the machine description. Otherwise, the compiler
3458 will crash when trying to generate code for the insn or trying to optimize
3461 The RTL template, in addition to controlling generation of RTL insns,
3462 also describes the operands that need to be specified when this pattern
3463 is used. In particular, it gives a predicate for each operand.
3465 A true operand, which needs to be specified in order to generate RTL from
3466 the pattern, should be described with a @code{match_operand} in its first
3467 occurrence in the RTL template. This enters information on the operand's
3468 predicate into the tables that record such things. GCC uses the
3469 information to preload the operand into a register if that is required for
3470 valid RTL code. If the operand is referred to more than once, subsequent
3471 references should use @code{match_dup}.
3473 The RTL template may also refer to internal ``operands'' which are
3474 temporary registers or labels used only within the sequence made by the
3475 @code{define_expand}. Internal operands are substituted into the RTL
3476 template with @code{match_dup}, never with @code{match_operand}. The
3477 values of the internal operands are not passed in as arguments by the
3478 compiler when it requests use of this pattern. Instead, they are computed
3479 within the pattern, in the preparation statements. These statements
3480 compute the values and store them into the appropriate elements of
3481 @code{operands} so that @code{match_dup} can find them.
3483 There are two special macros defined for use in the preparation statements:
3484 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
3491 Use the @code{DONE} macro to end RTL generation for the pattern. The
3492 only RTL insns resulting from the pattern on this occasion will be
3493 those already emitted by explicit calls to @code{emit_insn} within the
3494 preparation statements; the RTL template will not be generated.
3498 Make the pattern fail on this occasion. When a pattern fails, it means
3499 that the pattern was not truly available. The calling routines in the
3500 compiler will try other strategies for code generation using other patterns.
3502 Failure is currently supported only for binary (addition, multiplication,
3503 shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv})
3507 If the preparation falls through (invokes neither @code{DONE} nor
3508 @code{FAIL}), then the @code{define_expand} acts like a
3509 @code{define_insn} in that the RTL template is used to generate the
3512 The RTL template is not used for matching, only for generating the
3513 initial insn list. If the preparation statement always invokes
3514 @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple
3515 list of operands, such as this example:
3519 (define_expand "addsi3"
3520 [(match_operand:SI 0 "register_operand" "")
3521 (match_operand:SI 1 "register_operand" "")
3522 (match_operand:SI 2 "register_operand" "")]
3528 handle_add (operands[0], operands[1], operands[2]);
3534 Here is an example, the definition of left-shift for the SPUR chip:
3538 (define_expand "ashlsi3"
3539 [(set (match_operand:SI 0 "register_operand" "")
3543 (match_operand:SI 1 "register_operand" "")
3544 (match_operand:SI 2 "nonmemory_operand" "")))]
3553 if (GET_CODE (operands[2]) != CONST_INT
3554 || (unsigned) INTVAL (operands[2]) > 3)
3561 This example uses @code{define_expand} so that it can generate an RTL insn
3562 for shifting when the shift-count is in the supported range of 0 to 3 but
3563 fail in other cases where machine insns aren't available. When it fails,
3564 the compiler tries another strategy using different patterns (such as, a
3567 If the compiler were able to handle nontrivial condition-strings in
3568 patterns with names, then it would be possible to use a
3569 @code{define_insn} in that case. Here is another case (zero-extension
3570 on the 68000) which makes more use of the power of @code{define_expand}:
3573 (define_expand "zero_extendhisi2"
3574 [(set (match_operand:SI 0 "general_operand" "")
3576 (set (strict_low_part
3580 (match_operand:HI 1 "general_operand" ""))]
3582 "operands[1] = make_safe_from (operands[1], operands[0]);")
3586 @findex make_safe_from
3587 Here two RTL insns are generated, one to clear the entire output operand
3588 and the other to copy the input operand into its low half. This sequence
3589 is incorrect if the input operand refers to [the old value of] the output
3590 operand, so the preparation statement makes sure this isn't so. The
3591 function @code{make_safe_from} copies the @code{operands[1]} into a
3592 temporary register if it refers to @code{operands[0]}. It does this
3593 by emitting another RTL insn.
3595 Finally, a third example shows the use of an internal operand.
3596 Zero-extension on the SPUR chip is done by @code{and}-ing the result
3597 against a halfword mask. But this mask cannot be represented by a
3598 @code{const_int} because the constant value is too large to be legitimate
3599 on this machine. So it must be copied into a register with
3600 @code{force_reg} and then the register used in the @code{and}.
3603 (define_expand "zero_extendhisi2"
3604 [(set (match_operand:SI 0 "register_operand" "")
3606 (match_operand:HI 1 "register_operand" "")
3611 = force_reg (SImode, GEN_INT (65535)); ")
3614 @strong{Note:} If the @code{define_expand} is used to serve a
3615 standard binary or unary arithmetic operation or a bit-field operation,
3616 then the last insn it generates must not be a @code{code_label},
3617 @code{barrier} or @code{note}. It must be an @code{insn},
3618 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
3619 at the end, emit an insn to copy the result of the operation into
3620 itself. Such an insn will generate no code, but it can avoid problems
3623 @node Insn Splitting
3624 @section Defining How to Split Instructions
3625 @cindex insn splitting
3626 @cindex instruction splitting
3627 @cindex splitting instructions
3629 There are two cases where you should specify how to split a pattern into
3630 multiple insns. On machines that have instructions requiring delay
3631 slots (@pxref{Delay Slots}) or that have instructions whose output is
3632 not available for multiple cycles (@pxref{Function Units}), the compiler
3633 phases that optimize these cases need to be able to move insns into
3634 one-instruction delay slots. However, some insns may generate more than one
3635 machine instruction. These insns cannot be placed into a delay slot.
3637 Often you can rewrite the single insn as a list of individual insns,
3638 each corresponding to one machine instruction. The disadvantage of
3639 doing so is that it will cause the compilation to be slower and require
3640 more space. If the resulting insns are too complex, it may also
3641 suppress some optimizations. The compiler splits the insn if there is a
3642 reason to believe that it might improve instruction or delay slot
3645 The insn combiner phase also splits putative insns. If three insns are
3646 merged into one insn with a complex expression that cannot be matched by
3647 some @code{define_insn} pattern, the combiner phase attempts to split
3648 the complex pattern into two insns that are recognized. Usually it can
3649 break the complex pattern into two patterns by splitting out some
3650 subexpression. However, in some other cases, such as performing an
3651 addition of a large constant in two insns on a RISC machine, the way to
3652 split the addition into two insns is machine-dependent.
3654 @findex define_split
3655 The @code{define_split} definition tells the compiler how to split a
3656 complex insn into several simpler insns. It looks like this:
3660 [@var{insn-pattern}]
3662 [@var{new-insn-pattern-1}
3663 @var{new-insn-pattern-2}
3665 "@var{preparation-statements}")
3668 @var{insn-pattern} is a pattern that needs to be split and
3669 @var{condition} is the final condition to be tested, as in a
3670 @code{define_insn}. When an insn matching @var{insn-pattern} and
3671 satisfying @var{condition} is found, it is replaced in the insn list
3672 with the insns given by @var{new-insn-pattern-1},
3673 @var{new-insn-pattern-2}, etc.
3675 The @var{preparation-statements} are similar to those statements that
3676 are specified for @code{define_expand} (@pxref{Expander Definitions})
3677 and are executed before the new RTL is generated to prepare for the
3678 generated code or emit some insns whose pattern is not fixed. Unlike
3679 those in @code{define_expand}, however, these statements must not
3680 generate any new pseudo-registers. Once reload has completed, they also
3681 must not allocate any space in the stack frame.
3683 Patterns are matched against @var{insn-pattern} in two different
3684 circumstances. If an insn needs to be split for delay slot scheduling
3685 or insn scheduling, the insn is already known to be valid, which means
3686 that it must have been matched by some @code{define_insn} and, if
3687 @code{reload_completed} is non-zero, is known to satisfy the constraints
3688 of that @code{define_insn}. In that case, the new insn patterns must
3689 also be insns that are matched by some @code{define_insn} and, if
3690 @code{reload_completed} is non-zero, must also satisfy the constraints
3691 of those definitions.
3693 As an example of this usage of @code{define_split}, consider the following
3694 example from @file{a29k.md}, which splits a @code{sign_extend} from
3695 @code{HImode} to @code{SImode} into a pair of shift insns:
3699 [(set (match_operand:SI 0 "gen_reg_operand" "")
3700 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
3703 (ashift:SI (match_dup 1)
3706 (ashiftrt:SI (match_dup 0)
3709 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
3712 When the combiner phase tries to split an insn pattern, it is always the
3713 case that the pattern is @emph{not} matched by any @code{define_insn}.
3714 The combiner pass first tries to split a single @code{set} expression
3715 and then the same @code{set} expression inside a @code{parallel}, but
3716 followed by a @code{clobber} of a pseudo-reg to use as a scratch
3717 register. In these cases, the combiner expects exactly two new insn
3718 patterns to be generated. It will verify that these patterns match some
3719 @code{define_insn} definitions, so you need not do this test in the
3720 @code{define_split} (of course, there is no point in writing a
3721 @code{define_split} that will never produce insns that match).
3723 Here is an example of this use of @code{define_split}, taken from
3728 [(set (match_operand:SI 0 "gen_reg_operand" "")
3729 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
3730 (match_operand:SI 2 "non_add_cint_operand" "")))]
3732 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
3733 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
3736 int low = INTVAL (operands[2]) & 0xffff;
3737 int high = (unsigned) INTVAL (operands[2]) >> 16;
3740 high++, low |= 0xffff0000;
3742 operands[3] = GEN_INT (high << 16);
3743 operands[4] = GEN_INT (low);
3747 Here the predicate @code{non_add_cint_operand} matches any
3748 @code{const_int} that is @emph{not} a valid operand of a single add
3749 insn. The add with the smaller displacement is written so that it
3750 can be substituted into the address of a subsequent operation.
3752 An example that uses a scratch register, from the same file, generates
3753 an equality comparison of a register and a large constant:
3757 [(set (match_operand:CC 0 "cc_reg_operand" "")
3758 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
3759 (match_operand:SI 2 "non_short_cint_operand" "")))
3760 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
3761 "find_single_use (operands[0], insn, 0)
3762 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
3763 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
3764 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
3765 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
3768 /* Get the constant we are comparing against, C, and see what it
3769 looks like sign-extended to 16 bits. Then see what constant
3770 could be XOR'ed with C to get the sign-extended value. */
3772 int c = INTVAL (operands[2]);
3773 int sextc = (c << 16) >> 16;
3774 int xorv = c ^ sextc;
3776 operands[4] = GEN_INT (xorv);
3777 operands[5] = GEN_INT (sextc);
3781 To avoid confusion, don't write a single @code{define_split} that
3782 accepts some insns that match some @code{define_insn} as well as some
3783 insns that don't. Instead, write two separate @code{define_split}
3784 definitions, one for the insns that are valid and one for the insns that
3787 For the common case where the pattern of a define_split exactly matches the
3788 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
3792 (define_insn_and_split
3793 [@var{insn-pattern}]
3795 "@var{output-template}"
3796 "@var{split-condition}"
3797 [@var{new-insn-pattern-1}
3798 @var{new-insn-pattern-2}
3800 "@var{preparation-statements}"
3801 [@var{insn-attributes}])
3805 @var{insn-pattern}, @var{condition}, @var{output-template}, and
3806 @var{insn-attributes} are used as in @code{define_insn}. The
3807 @var{new-insn-pattern} vector and the @var{preparation-statements} are used as
3808 in a @code{define_split}. The @var{split-condition} is also used as in
3809 @code{define_split}, with the additional behavior that if the condition starts
3810 with @samp{&&}, the condition used for the split will be the constructed as a
3811 logical ``and'' of the split condition with the insn condition. For example,
3815 (define_insn_and_split "zero_extendhisi2_and"
3816 [(set (match_operand:SI 0 "register_operand" "=r")
3817 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
3818 (clobber (reg:CC 17))]
3819 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3821 "&& reload_completed"
3822 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
3823 (clobber (reg:CC 17))])]
3825 [(set_attr "type" "alu1")])
3829 In this case, the actual split condition will be
3830 @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
3832 The @code{define_insn_and_split} construction provides exactly the same
3833 functionality as two separate @code{define_insn} and @code{define_split}
3834 patterns. It exists for compactness, and as a maintenance tool to prevent
3835 having to ensure the two patterns' templates match.
3837 @node Peephole Definitions
3838 @section Machine-Specific Peephole Optimizers
3839 @cindex peephole optimizer definitions
3840 @cindex defining peephole optimizers
3842 In addition to instruction patterns the @file{md} file may contain
3843 definitions of machine-specific peephole optimizations.
3845 The combiner does not notice certain peephole optimizations when the data
3846 flow in the program does not suggest that it should try them. For example,
3847 sometimes two consecutive insns related in purpose can be combined even
3848 though the second one does not appear to use a register computed in the
3849 first one. A machine-specific peephole optimizer can detect such
3852 There are two forms of peephole definitions that may be used. The
3853 original @code{define_peephole} is run at assembly output time to
3854 match insns and substitute assembly text. Use of @code{define_peephole}
3857 A newer @code{define_peephole2} matches insns and substitutes new
3858 insns. The @code{peephole2} pass is run after register allocation
3859 but before scheduling, which may result in much better code for
3860 targets that do scheduling.
3863 * define_peephole:: RTL to Text Peephole Optimizers
3864 * define_peephole2:: RTL to RTL Peephole Optimizers
3867 @node define_peephole
3868 @subsection RTL to Text Peephole Optimizers
3869 @findex define_peephole
3872 A definition looks like this:
3876 [@var{insn-pattern-1}
3877 @var{insn-pattern-2}
3881 "@var{optional-insn-attributes}")
3885 The last string operand may be omitted if you are not using any
3886 machine-specific information in this machine description. If present,
3887 it must obey the same rules as in a @code{define_insn}.
3889 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
3890 consecutive insns. The optimization applies to a sequence of insns when
3891 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
3892 the next, and so on.
3894 Each of the insns matched by a peephole must also match a
3895 @code{define_insn}. Peepholes are checked only at the last stage just
3896 before code generation, and only optionally. Therefore, any insn which
3897 would match a peephole but no @code{define_insn} will cause a crash in code
3898 generation in an unoptimized compilation, or at various optimization
3901 The operands of the insns are matched with @code{match_operands},
3902 @code{match_operator}, and @code{match_dup}, as usual. What is not
3903 usual is that the operand numbers apply to all the insn patterns in the
3904 definition. So, you can check for identical operands in two insns by
3905 using @code{match_operand} in one insn and @code{match_dup} in the
3908 The operand constraints used in @code{match_operand} patterns do not have
3909 any direct effect on the applicability of the peephole, but they will
3910 be validated afterward, so make sure your constraints are general enough
3911 to apply whenever the peephole matches. If the peephole matches
3912 but the constraints are not satisfied, the compiler will crash.
3914 It is safe to omit constraints in all the operands of the peephole; or
3915 you can write constraints which serve as a double-check on the criteria
3918 Once a sequence of insns matches the patterns, the @var{condition} is
3919 checked. This is a C expression which makes the final decision whether to
3920 perform the optimization (we do so if the expression is nonzero). If
3921 @var{condition} is omitted (in other words, the string is empty) then the
3922 optimization is applied to every sequence of insns that matches the
3925 The defined peephole optimizations are applied after register allocation
3926 is complete. Therefore, the peephole definition can check which
3927 operands have ended up in which kinds of registers, just by looking at
3930 @findex prev_active_insn
3931 The way to refer to the operands in @var{condition} is to write
3932 @code{operands[@var{i}]} for operand number @var{i} (as matched by
3933 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
3934 to refer to the last of the insns being matched; use
3935 @code{prev_active_insn} to find the preceding insns.
3937 @findex dead_or_set_p
3938 When optimizing computations with intermediate results, you can use
3939 @var{condition} to match only when the intermediate results are not used
3940 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
3941 @var{op})}, where @var{insn} is the insn in which you expect the value
3942 to be used for the last time (from the value of @code{insn}, together
3943 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
3944 value (from @code{operands[@var{i}]}).
3946 Applying the optimization means replacing the sequence of insns with one
3947 new insn. The @var{template} controls ultimate output of assembler code
3948 for this combined insn. It works exactly like the template of a
3949 @code{define_insn}. Operand numbers in this template are the same ones
3950 used in matching the original sequence of insns.
3952 The result of a defined peephole optimizer does not need to match any of
3953 the insn patterns in the machine description; it does not even have an
3954 opportunity to match them. The peephole optimizer definition itself serves
3955 as the insn pattern to control how the insn is output.
3957 Defined peephole optimizers are run as assembler code is being output,
3958 so the insns they produce are never combined or rearranged in any way.
3960 Here is an example, taken from the 68000 machine description:
3964 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
3965 (set (match_operand:DF 0 "register_operand" "=f")
3966 (match_operand:DF 1 "register_operand" "ad"))]
3967 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
3970 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
3972 output_asm_insn ("move.l %1,(sp)", xoperands);
3973 output_asm_insn ("move.l %1,-(sp)", operands);
3974 return "fmove.d (sp)+,%0";
3976 output_asm_insn ("movel %1,sp@@", xoperands);
3977 output_asm_insn ("movel %1,sp@@-", operands);
3978 return "fmoved sp@@+,%0";
3984 The effect of this optimization is to change
4010 If a peephole matches a sequence including one or more jump insns, you must
4011 take account of the flags such as @code{CC_REVERSED} which specify that the
4012 condition codes are represented in an unusual manner. The compiler
4013 automatically alters any ordinary conditional jumps which occur in such
4014 situations, but the compiler cannot alter jumps which have been replaced by
4015 peephole optimizations. So it is up to you to alter the assembler code
4016 that the peephole produces. Supply C code to write the assembler output,
4017 and in this C code check the condition code status flags and change the
4018 assembler code as appropriate.
4021 @var{insn-pattern-1} and so on look @emph{almost} like the second
4022 operand of @code{define_insn}. There is one important difference: the
4023 second operand of @code{define_insn} consists of one or more RTX's
4024 enclosed in square brackets. Usually, there is only one: then the same
4025 action can be written as an element of a @code{define_peephole}. But
4026 when there are multiple actions in a @code{define_insn}, they are
4027 implicitly enclosed in a @code{parallel}. Then you must explicitly
4028 write the @code{parallel}, and the square brackets within it, in the
4029 @code{define_peephole}. Thus, if an insn pattern looks like this,
4032 (define_insn "divmodsi4"
4033 [(set (match_operand:SI 0 "general_operand" "=d")
4034 (div:SI (match_operand:SI 1 "general_operand" "0")
4035 (match_operand:SI 2 "general_operand" "dmsK")))
4036 (set (match_operand:SI 3 "general_operand" "=d")
4037 (mod:SI (match_dup 1) (match_dup 2)))]
4039 "divsl%.l %2,%3:%0")
4043 then the way to mention this insn in a peephole is as follows:
4049 [(set (match_operand:SI 0 "general_operand" "=d")
4050 (div:SI (match_operand:SI 1 "general_operand" "0")
4051 (match_operand:SI 2 "general_operand" "dmsK")))
4052 (set (match_operand:SI 3 "general_operand" "=d")
4053 (mod:SI (match_dup 1) (match_dup 2)))])
4058 @node define_peephole2
4059 @subsection RTL to RTL Peephole Optimizers
4060 @findex define_peephole2
4062 The @code{define_peephole2} definition tells the compiler how to
4063 substitute one sequence of instructions for another sequence,
4064 what additional scratch registers may be needed and what their
4069 [@var{insn-pattern-1}
4070 @var{insn-pattern-2}
4073 [@var{new-insn-pattern-1}
4074 @var{new-insn-pattern-2}
4076 "@var{preparation-statements}")
4079 The definition is almost identical to @code{define_split}
4080 (@pxref{Insn Splitting}) except that the pattern to match is not a
4081 single instruction, but a sequence of instructions.
4083 It is possible to request additional scratch registers for use in the
4084 output template. If appropriate registers are not free, the pattern
4085 will simply not match.
4087 @findex match_scratch
4089 Scratch registers are requested with a @code{match_scratch} pattern at
4090 the top level of the input pattern. The allocated register (initially) will
4091 be dead at the point requested within the original sequence. If the scratch
4092 is used at more than a single point, a @code{match_dup} pattern at the
4093 top level of the input pattern marks the last position in the input sequence
4094 at which the register must be available.
4096 Here is an example from the IA-32 machine description:
4100 [(match_scratch:SI 2 "r")
4101 (parallel [(set (match_operand:SI 0 "register_operand" "")
4102 (match_operator:SI 3 "arith_or_logical_operator"
4104 (match_operand:SI 1 "memory_operand" "")]))
4105 (clobber (reg:CC 17))])]
4106 "! optimize_size && ! TARGET_READ_MODIFY"
4107 [(set (match_dup 2) (match_dup 1))
4108 (parallel [(set (match_dup 0)
4109 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
4110 (clobber (reg:CC 17))])]
4115 This pattern tries to split a load from its use in the hopes that we'll be
4116 able to schedule around the memory load latency. It allocates a single
4117 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
4118 to be live only at the point just before the arithmetic.
4120 A real example requiring extended scratch lifetimes is harder to come by,
4121 so here's a silly made-up example:
4125 [(match_scratch:SI 4 "r")
4126 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
4127 (set (match_operand:SI 2 "" "") (match_dup 1))
4129 (set (match_operand:SI 3 "" "") (match_dup 1))]
4130 "/* @r{determine 1 does not overlap 0 and 2} */"
4131 [(set (match_dup 4) (match_dup 1))
4132 (set (match_dup 0) (match_dup 4))
4133 (set (match_dup 2) (match_dup 4))]
4134 (set (match_dup 3) (match_dup 4))]
4139 If we had not added the @code{(match_dup 4)} in the middle of the input
4140 sequence, it might have been the case that the register we chose at the
4141 beginning of the sequence is killed by the first or second @code{set}.
4143 @node Insn Attributes
4144 @section Instruction Attributes
4145 @cindex insn attributes
4146 @cindex instruction attributes
4148 In addition to describing the instruction supported by the target machine,
4149 the @file{md} file also defines a group of @dfn{attributes} and a set of
4150 values for each. Every generated insn is assigned a value for each attribute.
4151 One possible attribute would be the effect that the insn has on the machine's
4152 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
4153 to track the condition codes.
4156 * Defining Attributes:: Specifying attributes and their values.
4157 * Expressions:: Valid expressions for attribute values.
4158 * Tagging Insns:: Assigning attribute values to insns.
4159 * Attr Example:: An example of assigning attributes.
4160 * Insn Lengths:: Computing the length of insns.
4161 * Constant Attributes:: Defining attributes that are constant.
4162 * Delay Slots:: Defining delay slots required for a machine.
4163 * Function Units:: Specifying information for insn scheduling.
4166 @node Defining Attributes
4167 @subsection Defining Attributes and their Values
4168 @cindex defining attributes and their values
4169 @cindex attributes, defining
4172 The @code{define_attr} expression is used to define each attribute required
4173 by the target machine. It looks like:
4176 (define_attr @var{name} @var{list-of-values} @var{default})
4179 @var{name} is a string specifying the name of the attribute being defined.
4181 @var{list-of-values} is either a string that specifies a comma-separated
4182 list of values that can be assigned to the attribute, or a null string to
4183 indicate that the attribute takes numeric values.
4185 @var{default} is an attribute expression that gives the value of this
4186 attribute for insns that match patterns whose definition does not include
4187 an explicit value for this attribute. @xref{Attr Example}, for more
4188 information on the handling of defaults. @xref{Constant Attributes},
4189 for information on attributes that do not depend on any particular insn.
4192 For each defined attribute, a number of definitions are written to the
4193 @file{insn-attr.h} file. For cases where an explicit set of values is
4194 specified for an attribute, the following are defined:
4198 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
4201 An enumeral class is defined for @samp{attr_@var{name}} with
4202 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
4203 the attribute name and value are first converted to upper case.
4206 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
4207 returns the attribute value for that insn.
4210 For example, if the following is present in the @file{md} file:
4213 (define_attr "type" "branch,fp,load,store,arith" @dots{})
4217 the following lines will be written to the file @file{insn-attr.h}.
4220 #define HAVE_ATTR_type
4221 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
4222 TYPE_STORE, TYPE_ARITH@};
4223 extern enum attr_type get_attr_type ();
4226 If the attribute takes numeric values, no @code{enum} type will be
4227 defined and the function to obtain the attribute's value will return
4231 @subsection Attribute Expressions
4232 @cindex attribute expressions
4234 RTL expressions used to define attributes use the codes described above
4235 plus a few specific to attribute definitions, to be discussed below.
4236 Attribute value expressions must have one of the following forms:
4239 @cindex @code{const_int} and attributes
4240 @item (const_int @var{i})
4241 The integer @var{i} specifies the value of a numeric attribute. @var{i}
4242 must be non-negative.
4244 The value of a numeric attribute can be specified either with a
4245 @code{const_int}, or as an integer represented as a string in
4246 @code{const_string}, @code{eq_attr} (see below), @code{attr},
4247 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
4248 overrides on specific instructions (@pxref{Tagging Insns}).
4250 @cindex @code{const_string} and attributes
4251 @item (const_string @var{value})
4252 The string @var{value} specifies a constant attribute value.
4253 If @var{value} is specified as @samp{"*"}, it means that the default value of
4254 the attribute is to be used for the insn containing this expression.
4255 @samp{"*"} obviously cannot be used in the @var{default} expression
4256 of a @code{define_attr}.
4258 If the attribute whose value is being specified is numeric, @var{value}
4259 must be a string containing a non-negative integer (normally
4260 @code{const_int} would be used in this case). Otherwise, it must
4261 contain one of the valid values for the attribute.
4263 @cindex @code{if_then_else} and attributes
4264 @item (if_then_else @var{test} @var{true-value} @var{false-value})
4265 @var{test} specifies an attribute test, whose format is defined below.
4266 The value of this expression is @var{true-value} if @var{test} is true,
4267 otherwise it is @var{false-value}.
4269 @cindex @code{cond} and attributes
4270 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
4271 The first operand of this expression is a vector containing an even
4272 number of expressions and consisting of pairs of @var{test} and @var{value}
4273 expressions. The value of the @code{cond} expression is that of the
4274 @var{value} corresponding to the first true @var{test} expression. If
4275 none of the @var{test} expressions are true, the value of the @code{cond}
4276 expression is that of the @var{default} expression.
4279 @var{test} expressions can have one of the following forms:
4282 @cindex @code{const_int} and attribute tests
4283 @item (const_int @var{i})
4284 This test is true if @var{i} is non-zero and false otherwise.
4286 @cindex @code{not} and attributes
4287 @cindex @code{ior} and attributes
4288 @cindex @code{and} and attributes
4289 @item (not @var{test})
4290 @itemx (ior @var{test1} @var{test2})
4291 @itemx (and @var{test1} @var{test2})
4292 These tests are true if the indicated logical function is true.
4294 @cindex @code{match_operand} and attributes
4295 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
4296 This test is true if operand @var{n} of the insn whose attribute value
4297 is being determined has mode @var{m} (this part of the test is ignored
4298 if @var{m} is @code{VOIDmode}) and the function specified by the string
4299 @var{pred} returns a non-zero value when passed operand @var{n} and mode
4300 @var{m} (this part of the test is ignored if @var{pred} is the null
4303 The @var{constraints} operand is ignored and should be the null string.
4305 @cindex @code{le} and attributes
4306 @cindex @code{leu} and attributes
4307 @cindex @code{lt} and attributes
4308 @cindex @code{gt} and attributes
4309 @cindex @code{gtu} and attributes
4310 @cindex @code{ge} and attributes
4311 @cindex @code{geu} and attributes
4312 @cindex @code{ne} and attributes
4313 @cindex @code{eq} and attributes
4314 @cindex @code{plus} and attributes
4315 @cindex @code{minus} and attributes
4316 @cindex @code{mult} and attributes
4317 @cindex @code{div} and attributes
4318 @cindex @code{mod} and attributes
4319 @cindex @code{abs} and attributes
4320 @cindex @code{neg} and attributes
4321 @cindex @code{ashift} and attributes
4322 @cindex @code{lshiftrt} and attributes
4323 @cindex @code{ashiftrt} and attributes
4324 @item (le @var{arith1} @var{arith2})
4325 @itemx (leu @var{arith1} @var{arith2})
4326 @itemx (lt @var{arith1} @var{arith2})
4327 @itemx (ltu @var{arith1} @var{arith2})
4328 @itemx (gt @var{arith1} @var{arith2})
4329 @itemx (gtu @var{arith1} @var{arith2})
4330 @itemx (ge @var{arith1} @var{arith2})
4331 @itemx (geu @var{arith1} @var{arith2})
4332 @itemx (ne @var{arith1} @var{arith2})
4333 @itemx (eq @var{arith1} @var{arith2})
4334 These tests are true if the indicated comparison of the two arithmetic
4335 expressions is true. Arithmetic expressions are formed with
4336 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
4337 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
4338 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
4341 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
4342 Lengths},for additional forms). @code{symbol_ref} is a string
4343 denoting a C expression that yields an @code{int} when evaluated by the
4344 @samp{get_attr_@dots{}} routine. It should normally be a global
4348 @item (eq_attr @var{name} @var{value})
4349 @var{name} is a string specifying the name of an attribute.
4351 @var{value} is a string that is either a valid value for attribute
4352 @var{name}, a comma-separated list of values, or @samp{!} followed by a
4353 value or list. If @var{value} does not begin with a @samp{!}, this
4354 test is true if the value of the @var{name} attribute of the current
4355 insn is in the list specified by @var{value}. If @var{value} begins
4356 with a @samp{!}, this test is true if the attribute's value is
4357 @emph{not} in the specified list.
4362 (eq_attr "type" "load,store")
4369 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
4372 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
4373 value of the compiler variable @code{which_alternative}
4374 (@pxref{Output Statement}) and the values must be small integers. For
4378 (eq_attr "alternative" "2,3")
4385 (ior (eq (symbol_ref "which_alternative") (const_int 2))
4386 (eq (symbol_ref "which_alternative") (const_int 3)))
4389 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
4390 where the value of the attribute being tested is known for all insns matching
4391 a particular pattern. This is by far the most common case.
4394 @item (attr_flag @var{name})
4395 The value of an @code{attr_flag} expression is true if the flag
4396 specified by @var{name} is true for the @code{insn} currently being
4399 @var{name} is a string specifying one of a fixed set of flags to test.
4400 Test the flags @code{forward} and @code{backward} to determine the
4401 direction of a conditional branch. Test the flags @code{very_likely},
4402 @code{likely}, @code{very_unlikely}, and @code{unlikely} to determine
4403 if a conditional branch is expected to be taken.
4405 If the @code{very_likely} flag is true, then the @code{likely} flag is also
4406 true. Likewise for the @code{very_unlikely} and @code{unlikely} flags.
4408 This example describes a conditional branch delay slot which
4409 can be nullified for forward branches that are taken (annul-true) or
4410 for backward branches which are not taken (annul-false).
4413 (define_delay (eq_attr "type" "cbranch")
4414 [(eq_attr "in_branch_delay" "true")
4415 (and (eq_attr "in_branch_delay" "true")
4416 (attr_flag "forward"))
4417 (and (eq_attr "in_branch_delay" "true")
4418 (attr_flag "backward"))])
4421 The @code{forward} and @code{backward} flags are false if the current
4422 @code{insn} being scheduled is not a conditional branch.
4424 The @code{very_likely} and @code{likely} flags are true if the
4425 @code{insn} being scheduled is not a conditional branch.
4426 The @code{very_unlikely} and @code{unlikely} flags are false if the
4427 @code{insn} being scheduled is not a conditional branch.
4429 @code{attr_flag} is only used during delay slot scheduling and has no
4430 meaning to other passes of the compiler.
4433 @item (attr @var{name})
4434 The value of another attribute is returned. This is most useful
4435 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
4436 produce more efficient code for non-numeric attributes.
4440 @subsection Assigning Attribute Values to Insns
4441 @cindex tagging insns
4442 @cindex assigning attribute values to insns
4444 The value assigned to an attribute of an insn is primarily determined by
4445 which pattern is matched by that insn (or which @code{define_peephole}
4446 generated it). Every @code{define_insn} and @code{define_peephole} can
4447 have an optional last argument to specify the values of attributes for
4448 matching insns. The value of any attribute not specified in a particular
4449 insn is set to the default value for that attribute, as specified in its
4450 @code{define_attr}. Extensive use of default values for attributes
4451 permits the specification of the values for only one or two attributes
4452 in the definition of most insn patterns, as seen in the example in the
4455 The optional last argument of @code{define_insn} and
4456 @code{define_peephole} is a vector of expressions, each of which defines
4457 the value for a single attribute. The most general way of assigning an
4458 attribute's value is to use a @code{set} expression whose first operand is an
4459 @code{attr} expression giving the name of the attribute being set. The
4460 second operand of the @code{set} is an attribute expression
4461 (@pxref{Expressions}) giving the value of the attribute.
4463 When the attribute value depends on the @samp{alternative} attribute
4464 (i.e., which is the applicable alternative in the constraint of the
4465 insn), the @code{set_attr_alternative} expression can be used. It
4466 allows the specification of a vector of attribute expressions, one for
4470 When the generality of arbitrary attribute expressions is not required,
4471 the simpler @code{set_attr} expression can be used, which allows
4472 specifying a string giving either a single attribute value or a list
4473 of attribute values, one for each alternative.
4475 The form of each of the above specifications is shown below. In each case,
4476 @var{name} is a string specifying the attribute to be set.
4479 @item (set_attr @var{name} @var{value-string})
4480 @var{value-string} is either a string giving the desired attribute value,
4481 or a string containing a comma-separated list giving the values for
4482 succeeding alternatives. The number of elements must match the number
4483 of alternatives in the constraint of the insn pattern.
4485 Note that it may be useful to specify @samp{*} for some alternative, in
4486 which case the attribute will assume its default value for insns matching
4489 @findex set_attr_alternative
4490 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
4491 Depending on the alternative of the insn, the value will be one of the
4492 specified values. This is a shorthand for using a @code{cond} with
4493 tests on the @samp{alternative} attribute.
4496 @item (set (attr @var{name}) @var{value})
4497 The first operand of this @code{set} must be the special RTL expression
4498 @code{attr}, whose sole operand is a string giving the name of the
4499 attribute being set. @var{value} is the value of the attribute.
4502 The following shows three different ways of representing the same
4503 attribute value specification:
4506 (set_attr "type" "load,store,arith")
4508 (set_attr_alternative "type"
4509 [(const_string "load") (const_string "store")
4510 (const_string "arith")])
4513 (cond [(eq_attr "alternative" "1") (const_string "load")
4514 (eq_attr "alternative" "2") (const_string "store")]
4515 (const_string "arith")))
4519 @findex define_asm_attributes
4520 The @code{define_asm_attributes} expression provides a mechanism to
4521 specify the attributes assigned to insns produced from an @code{asm}
4522 statement. It has the form:
4525 (define_asm_attributes [@var{attr-sets}])
4529 where @var{attr-sets} is specified the same as for both the
4530 @code{define_insn} and the @code{define_peephole} expressions.
4532 These values will typically be the ``worst case'' attribute values. For
4533 example, they might indicate that the condition code will be clobbered.
4535 A specification for a @code{length} attribute is handled specially. The
4536 way to compute the length of an @code{asm} insn is to multiply the
4537 length specified in the expression @code{define_asm_attributes} by the
4538 number of machine instructions specified in the @code{asm} statement,
4539 determined by counting the number of semicolons and newlines in the
4540 string. Therefore, the value of the @code{length} attribute specified
4541 in a @code{define_asm_attributes} should be the maximum possible length
4542 of a single machine instruction.
4545 @subsection Example of Attribute Specifications
4546 @cindex attribute specifications example
4547 @cindex attribute specifications
4549 The judicious use of defaulting is important in the efficient use of
4550 insn attributes. Typically, insns are divided into @dfn{types} and an
4551 attribute, customarily called @code{type}, is used to represent this
4552 value. This attribute is normally used only to define the default value
4553 for other attributes. An example will clarify this usage.
4555 Assume we have a RISC machine with a condition code and in which only
4556 full-word operations are performed in registers. Let us assume that we
4557 can divide all insns into loads, stores, (integer) arithmetic
4558 operations, floating point operations, and branches.
4560 Here we will concern ourselves with determining the effect of an insn on
4561 the condition code and will limit ourselves to the following possible
4562 effects: The condition code can be set unpredictably (clobbered), not
4563 be changed, be set to agree with the results of the operation, or only
4564 changed if the item previously set into the condition code has been
4567 Here is part of a sample @file{md} file for such a machine:
4570 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
4572 (define_attr "cc" "clobber,unchanged,set,change0"
4573 (cond [(eq_attr "type" "load")
4574 (const_string "change0")
4575 (eq_attr "type" "store,branch")
4576 (const_string "unchanged")
4577 (eq_attr "type" "arith")
4578 (if_then_else (match_operand:SI 0 "" "")
4579 (const_string "set")
4580 (const_string "clobber"))]
4581 (const_string "clobber")))
4584 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
4585 (match_operand:SI 1 "general_operand" "r,m,r"))]
4591 [(set_attr "type" "arith,load,store")])
4594 Note that we assume in the above example that arithmetic operations
4595 performed on quantities smaller than a machine word clobber the condition
4596 code since they will set the condition code to a value corresponding to the
4600 @subsection Computing the Length of an Insn
4601 @cindex insn lengths, computing
4602 @cindex computing the length of an insn
4604 For many machines, multiple types of branch instructions are provided, each
4605 for different length branch displacements. In most cases, the assembler
4606 will choose the correct instruction to use. However, when the assembler
4607 cannot do so, GCC can when a special attribute, the @samp{length}
4608 attribute, is defined. This attribute must be defined to have numeric
4609 values by specifying a null string in its @code{define_attr}.
4611 In the case of the @samp{length} attribute, two additional forms of
4612 arithmetic terms are allowed in test expressions:
4615 @cindex @code{match_dup} and attributes
4616 @item (match_dup @var{n})
4617 This refers to the address of operand @var{n} of the current insn, which
4618 must be a @code{label_ref}.
4620 @cindex @code{pc} and attributes
4622 This refers to the address of the @emph{current} insn. It might have
4623 been more consistent with other usage to make this the address of the
4624 @emph{next} insn but this would be confusing because the length of the
4625 current insn is to be computed.
4628 @cindex @code{addr_vec}, length of
4629 @cindex @code{addr_diff_vec}, length of
4630 For normal insns, the length will be determined by value of the
4631 @samp{length} attribute. In the case of @code{addr_vec} and
4632 @code{addr_diff_vec} insn patterns, the length is computed as
4633 the number of vectors multiplied by the size of each vector.
4635 Lengths are measured in addressable storage units (bytes).
4637 The following macros can be used to refine the length computation:
4640 @findex FIRST_INSN_ADDRESS
4641 @item FIRST_INSN_ADDRESS
4642 When the @code{length} insn attribute is used, this macro specifies the
4643 value to be assigned to the address of the first insn in a function. If
4644 not specified, 0 is used.
4646 @findex ADJUST_INSN_LENGTH
4647 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
4648 If defined, modifies the length assigned to instruction @var{insn} as a
4649 function of the context in which it is used. @var{length} is an lvalue
4650 that contains the initially computed length of the insn and should be
4651 updated with the correct length of the insn.
4653 This macro will normally not be required. A case in which it is
4654 required is the ROMP@. On this machine, the size of an @code{addr_vec}
4655 insn must be increased by two to compensate for the fact that alignment
4659 @findex get_attr_length
4660 The routine that returns @code{get_attr_length} (the value of the
4661 @code{length} attribute) can be used by the output routine to
4662 determine the form of the branch instruction to be written, as the
4663 example below illustrates.
4665 As an example of the specification of variable-length branches, consider
4666 the IBM 360. If we adopt the convention that a register will be set to
4667 the starting address of a function, we can jump to labels within 4k of
4668 the start using a four-byte instruction. Otherwise, we need a six-byte
4669 sequence to load the address from memory and then branch to it.
4671 On such a machine, a pattern for a branch instruction might be specified
4677 (label_ref (match_operand 0 "" "")))]
4680 return (get_attr_length (insn) == 4
4681 ? "b %l0" : "l r15,=a(%l0); br r15");
4683 [(set (attr "length") (if_then_else (lt (match_dup 0) (const_int 4096))
4688 @node Constant Attributes
4689 @subsection Constant Attributes
4690 @cindex constant attributes
4692 A special form of @code{define_attr}, where the expression for the
4693 default value is a @code{const} expression, indicates an attribute that
4694 is constant for a given run of the compiler. Constant attributes may be
4695 used to specify which variety of processor is used. For example,
4698 (define_attr "cpu" "m88100,m88110,m88000"
4700 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
4701 (symbol_ref "TARGET_88110") (const_string "m88110")]
4702 (const_string "m88000"))))
4704 (define_attr "memory" "fast,slow"
4706 (if_then_else (symbol_ref "TARGET_FAST_MEM")
4707 (const_string "fast")
4708 (const_string "slow"))))
4711 The routine generated for constant attributes has no parameters as it
4712 does not depend on any particular insn. RTL expressions used to define
4713 the value of a constant attribute may use the @code{symbol_ref} form,
4714 but may not use either the @code{match_operand} form or @code{eq_attr}
4715 forms involving insn attributes.
4718 @subsection Delay Slot Scheduling
4719 @cindex delay slots, defining
4721 The insn attribute mechanism can be used to specify the requirements for
4722 delay slots, if any, on a target machine. An instruction is said to
4723 require a @dfn{delay slot} if some instructions that are physically
4724 after the instruction are executed as if they were located before it.
4725 Classic examples are branch and call instructions, which often execute
4726 the following instruction before the branch or call is performed.
4728 On some machines, conditional branch instructions can optionally
4729 @dfn{annul} instructions in the delay slot. This means that the
4730 instruction will not be executed for certain branch outcomes. Both
4731 instructions that annul if the branch is true and instructions that
4732 annul if the branch is false are supported.
4734 Delay slot scheduling differs from instruction scheduling in that
4735 determining whether an instruction needs a delay slot is dependent only
4736 on the type of instruction being generated, not on data flow between the
4737 instructions. See the next section for a discussion of data-dependent
4738 instruction scheduling.
4740 @findex define_delay
4741 The requirement of an insn needing one or more delay slots is indicated
4742 via the @code{define_delay} expression. It has the following form:
4745 (define_delay @var{test}
4746 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
4747 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
4751 @var{test} is an attribute test that indicates whether this
4752 @code{define_delay} applies to a particular insn. If so, the number of
4753 required delay slots is determined by the length of the vector specified
4754 as the second argument. An insn placed in delay slot @var{n} must
4755 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
4756 attribute test that specifies which insns may be annulled if the branch
4757 is true. Similarly, @var{annul-false-n} specifies which insns in the
4758 delay slot may be annulled if the branch is false. If annulling is not
4759 supported for that delay slot, @code{(nil)} should be coded.
4761 For example, in the common case where branch and call insns require
4762 a single delay slot, which may contain any insn other than a branch or
4763 call, the following would be placed in the @file{md} file:
4766 (define_delay (eq_attr "type" "branch,call")
4767 [(eq_attr "type" "!branch,call") (nil) (nil)])
4770 Multiple @code{define_delay} expressions may be specified. In this
4771 case, each such expression specifies different delay slot requirements
4772 and there must be no insn for which tests in two @code{define_delay}
4773 expressions are both true.
4775 For example, if we have a machine that requires one delay slot for branches
4776 but two for calls, no delay slot can contain a branch or call insn,
4777 and any valid insn in the delay slot for the branch can be annulled if the
4778 branch is true, we might represent this as follows:
4781 (define_delay (eq_attr "type" "branch")
4782 [(eq_attr "type" "!branch,call")
4783 (eq_attr "type" "!branch,call")
4786 (define_delay (eq_attr "type" "call")
4787 [(eq_attr "type" "!branch,call") (nil) (nil)
4788 (eq_attr "type" "!branch,call") (nil) (nil)])
4790 @c the above is *still* too long. --mew 4feb93
4792 @node Function Units
4793 @subsection Specifying Function Units
4794 @cindex function units, for scheduling
4796 On most RISC machines, there are instructions whose results are not
4797 available for a specific number of cycles. Common cases are instructions
4798 that load data from memory. On many machines, a pipeline stall will result
4799 if the data is referenced too soon after the load instruction.
4801 In addition, many newer microprocessors have multiple function units, usually
4802 one for integer and one for floating point, and often will incur pipeline
4803 stalls when a result that is needed is not yet ready.
4805 The descriptions in this section allow the specification of how much
4806 time must elapse between the execution of an instruction and the time
4807 when its result is used. It also allows specification of when the
4808 execution of an instruction will delay execution of similar instructions
4809 due to function unit conflicts.
4811 For the purposes of the specifications in this section, a machine is
4812 divided into @dfn{function units}, each of which execute a specific
4813 class of instructions in first-in-first-out order. Function units that
4814 accept one instruction each cycle and allow a result to be used in the
4815 succeeding instruction (usually via forwarding) need not be specified.
4816 Classic RISC microprocessors will normally have a single function unit,
4817 which we can call @samp{memory}. The newer ``superscalar'' processors
4818 will often have function units for floating point operations, usually at
4819 least a floating point adder and multiplier.
4821 @findex define_function_unit
4822 Each usage of a function units by a class of insns is specified with a
4823 @code{define_function_unit} expression, which looks like this:
4826 (define_function_unit @var{name} @var{multiplicity} @var{simultaneity}
4827 @var{test} @var{ready-delay} @var{issue-delay}
4828 [@var{conflict-list}])
4831 @var{name} is a string giving the name of the function unit.
4833 @var{multiplicity} is an integer specifying the number of identical
4834 units in the processor. If more than one unit is specified, they will
4835 be scheduled independently. Only truly independent units should be
4836 counted; a pipelined unit should be specified as a single unit. (The
4837 only common example of a machine that has multiple function units for a
4838 single instruction class that are truly independent and not pipelined
4839 are the two multiply and two increment units of the CDC 6600.)
4841 @var{simultaneity} specifies the maximum number of insns that can be
4842 executing in each instance of the function unit simultaneously or zero
4843 if the unit is pipelined and has no limit.
4845 All @code{define_function_unit} definitions referring to function unit
4846 @var{name} must have the same name and values for @var{multiplicity} and
4849 @var{test} is an attribute test that selects the insns we are describing
4850 in this definition. Note that an insn may use more than one function
4851 unit and a function unit may be specified in more than one
4852 @code{define_function_unit}.
4854 @var{ready-delay} is an integer that specifies the number of cycles
4855 after which the result of the instruction can be used without
4856 introducing any stalls.
4858 @var{issue-delay} is an integer that specifies the number of cycles
4859 after the instruction matching the @var{test} expression begins using
4860 this unit until a subsequent instruction can begin. A cost of @var{N}
4861 indicates an @var{N-1} cycle delay. A subsequent instruction may also
4862 be delayed if an earlier instruction has a longer @var{ready-delay}
4863 value. This blocking effect is computed using the @var{simultaneity},
4864 @var{ready-delay}, @var{issue-delay}, and @var{conflict-list} terms.
4865 For a normal non-pipelined function unit, @var{simultaneity} is one, the
4866 unit is taken to block for the @var{ready-delay} cycles of the executing
4867 insn, and smaller values of @var{issue-delay} are ignored.
4869 @var{conflict-list} is an optional list giving detailed conflict costs
4870 for this unit. If specified, it is a list of condition test expressions
4871 to be applied to insns chosen to execute in @var{name} following the
4872 particular insn matching @var{test} that is already executing in
4873 @var{name}. For each insn in the list, @var{issue-delay} specifies the
4874 conflict cost; for insns not in the list, the cost is zero. If not
4875 specified, @var{conflict-list} defaults to all instructions that use the
4878 Typical uses of this vector are where a floating point function unit can
4879 pipeline either single- or double-precision operations, but not both, or
4880 where a memory unit can pipeline loads, but not stores, etc.
4882 As an example, consider a classic RISC machine where the result of a
4883 load instruction is not available for two cycles (a single ``delay''
4884 instruction is required) and where only one load instruction can be executed
4885 simultaneously. This would be specified as:
4888 (define_function_unit "memory" 1 1 (eq_attr "type" "load") 2 0)
4891 For the case of a floating point function unit that can pipeline either
4892 single or double precision, but not both, the following could be specified:
4895 (define_function_unit
4896 "fp" 1 0 (eq_attr "type" "sp_fp") 4 4 [(eq_attr "type" "dp_fp")])
4897 (define_function_unit
4898 "fp" 1 0 (eq_attr "type" "dp_fp") 4 4 [(eq_attr "type" "sp_fp")])
4901 @strong{Note:} The scheduler attempts to avoid function unit conflicts
4902 and uses all the specifications in the @code{define_function_unit}
4903 expression. It has recently come to our attention that these
4904 specifications may not allow modeling of some of the newer
4905 ``superscalar'' processors that have insns using multiple pipelined
4906 units. These insns will cause a potential conflict for the second unit
4907 used during their execution and there is no way of representing that
4908 conflict. We welcome any examples of how function unit conflicts work
4909 in such processors and suggestions for their representation.
4912 @node Conditional Execution
4913 @section Conditional Execution
4914 @cindex conditional execution
4917 A number of architectures provide for some form of conditional
4918 execution, or predication. The hallmark of this feature is the
4919 ability to nullify most of the instructions in the instruction set.
4920 When the instruction set is large and not entirely symmetric, it
4921 can be quite tedious to describe these forms directly in the
4922 @file{.md} file. An alternative is the @code{define_cond_exec} template.
4924 @findex define_cond_exec
4927 [@var{predicate-pattern}]
4929 "@var{output-template}")
4932 @var{predicate-pattern} is the condition that must be true for the
4933 insn to be executed at runtime and should match a relational operator.
4934 One can use @code{match_operator} to match several relational operators
4935 at once. Any @code{match_operand} operands must have no more than one
4938 @var{condition} is a C expression that must be true for the generated
4941 @findex current_insn_predicate
4942 @var{output-template} is a string similar to the @code{define_insn}
4943 output template (@pxref{Output Template}), except that the @samp{*}
4944 and @samp{@@} special cases do not apply. This is only useful if the
4945 assembly text for the predicate is a simple prefix to the main insn.
4946 In order to handle the general case, there is a global variable
4947 @code{current_insn_predicate} that will contain the entire predicate
4948 if the current insn is predicated, and will otherwise be @code{NULL}.
4950 When @code{define_cond_exec} is used, an implicit reference to
4951 the @code{predicable} instruction attribute is made.
4952 @xref{Insn Attributes}. This attribute must be boolean (i.e.@: have
4953 exactly two elements in its @var{list-of-values}). Further, it must
4954 not be used with complex expressions. That is, the default and all
4955 uses in the insns must be a simple constant, not dependent on the
4956 alternative or anything else.
4958 For each @code{define_insn} for which the @code{predicable}
4959 attribute is true, a new @code{define_insn} pattern will be
4960 generated that matches a predicated version of the instruction.
4964 (define_insn "addsi"
4965 [(set (match_operand:SI 0 "register_operand" "r")
4966 (plus:SI (match_operand:SI 1 "register_operand" "r")
4967 (match_operand:SI 2 "register_operand" "r")))]
4972 [(ne (match_operand:CC 0 "register_operand" "c")
4979 generates a new pattern
4984 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
4985 (set (match_operand:SI 0 "register_operand" "r")
4986 (plus:SI (match_operand:SI 1 "register_operand" "r")
4987 (match_operand:SI 2 "register_operand" "r"))))]
4988 "(@var{test2}) && (@var{test1})"
4989 "(%3) add %2,%1,%0")
4992 @node Constant Definitions
4993 @section Constant Definitions
4994 @cindex constant definitions
4995 @findex define_constants
4997 Using literal constants inside instruction patterns reduces legibility and
4998 can be a maintenance problem.
5000 To overcome this problem, you may use the @code{define_constants}
5001 expression. It contains a vector of name-value pairs. From that
5002 point on, wherever any of the names appears in the MD file, it is as
5003 if the corresponding value had been written instead. You may use
5004 @code{define_constants} multiple times; each appearance adds more
5005 constants to the table. It is an error to redefine a constant with
5008 To come back to the a29k load multiple example, instead of
5012 [(match_parallel 0 "load_multiple_operation"
5013 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
5014 (match_operand:SI 2 "memory_operand" "m"))
5016 (clobber (reg:SI 179))])]
5032 [(match_parallel 0 "load_multiple_operation"
5033 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
5034 (match_operand:SI 2 "memory_operand" "m"))
5036 (clobber (reg:SI R_CR))])]
5041 The constants that are defined with a define_constant are also output
5042 in the insn-codes.h header file as #defines.