1 @c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 1999, 2000, 2001,
2 @c 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
3 @c Free Software Foundation, Inc.
4 @c This is part of the GCC manual.
5 @c For copying conditions, see the file gcc.texi.
9 @chapter Machine Descriptions
10 @cindex machine descriptions
12 A machine description has two parts: a file of instruction patterns
13 (@file{.md} file) and a C header file of macro definitions.
15 The @file{.md} file for a target machine contains a pattern for each
16 instruction that the target machine supports (or at least each instruction
17 that is worth telling the compiler about). It may also contain comments.
18 A semicolon causes the rest of the line to be a comment, unless the semicolon
19 is inside a quoted string.
21 See the next chapter for information on the C header file.
24 * Overview:: How the machine description is used.
25 * Patterns:: How to write instruction patterns.
26 * Example:: An explained example of a @code{define_insn} pattern.
27 * RTL Template:: The RTL template defines what insns match a pattern.
28 * Output Template:: The output template says how to make assembler code
30 * Output Statement:: For more generality, write C code to output
32 * Predicates:: Controlling what kinds of operands can be used
34 * Constraints:: Fine-tuning operand selection.
35 * Standard Names:: Names mark patterns to use for code generation.
36 * Pattern Ordering:: When the order of patterns makes a difference.
37 * Dependent Patterns:: Having one pattern may make you need another.
38 * Jump Patterns:: Special considerations for patterns for jump insns.
39 * Looping Patterns:: How to define patterns for special looping insns.
40 * Insn Canonicalizations::Canonicalization of Instructions
41 * Expander Definitions::Generating a sequence of several RTL insns
42 for a standard operation.
43 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
44 * Including Patterns:: Including Patterns in Machine Descriptions.
45 * Peephole Definitions::Defining machine-specific peephole optimizations.
46 * Insn Attributes:: Specifying the value of attributes for generated insns.
47 * Conditional Execution::Generating @code{define_insn} patterns for
49 * Constant Definitions::Defining symbolic constants that can be used in the
51 * Iterators:: Using iterators to generate patterns from a template.
55 @section Overview of How the Machine Description is Used
57 There are three main conversions that happen in the compiler:
62 The front end reads the source code and builds a parse tree.
65 The parse tree is used to generate an RTL insn list based on named
69 The insn list is matched against the RTL templates to produce assembler
74 For the generate pass, only the names of the insns matter, from either a
75 named @code{define_insn} or a @code{define_expand}. The compiler will
76 choose the pattern with the right name and apply the operands according
77 to the documentation later in this chapter, without regard for the RTL
78 template or operand constraints. Note that the names the compiler looks
79 for are hard-coded in the compiler---it will ignore unnamed patterns and
80 patterns with names it doesn't know about, but if you don't provide a
81 named pattern it needs, it will abort.
83 If a @code{define_insn} is used, the template given is inserted into the
84 insn list. If a @code{define_expand} is used, one of three things
85 happens, based on the condition logic. The condition logic may manually
86 create new insns for the insn list, say via @code{emit_insn()}, and
87 invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
88 compiler to use an alternate way of performing that task. If it invokes
89 neither @code{DONE} nor @code{FAIL}, the template given in the pattern
90 is inserted, as if the @code{define_expand} were a @code{define_insn}.
92 Once the insn list is generated, various optimization passes convert,
93 replace, and rearrange the insns in the insn list. This is where the
94 @code{define_split} and @code{define_peephole} patterns get used, for
97 Finally, the insn list's RTL is matched up with the RTL templates in the
98 @code{define_insn} patterns, and those patterns are used to emit the
99 final assembly code. For this purpose, each named @code{define_insn}
100 acts like it's unnamed, since the names are ignored.
103 @section Everything about Instruction Patterns
105 @cindex instruction patterns
108 Each instruction pattern contains an incomplete RTL expression, with pieces
109 to be filled in later, operand constraints that restrict how the pieces can
110 be filled in, and an output pattern or C code to generate the assembler
111 output, all wrapped up in a @code{define_insn} expression.
113 A @code{define_insn} is an RTL expression containing four or five operands:
117 An optional name. The presence of a name indicate that this instruction
118 pattern can perform a certain standard job for the RTL-generation
119 pass of the compiler. This pass knows certain names and will use
120 the instruction patterns with those names, if the names are defined
121 in the machine description.
123 The absence of a name is indicated by writing an empty string
124 where the name should go. Nameless instruction patterns are never
125 used for generating RTL code, but they may permit several simpler insns
126 to be combined later on.
128 Names that are not thus known and used in RTL-generation have no
129 effect; they are equivalent to no name at all.
131 For the purpose of debugging the compiler, you may also specify a
132 name beginning with the @samp{*} character. Such a name is used only
133 for identifying the instruction in RTL dumps; it is entirely equivalent
134 to having a nameless pattern for all other purposes.
137 The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete
138 RTL expressions which show what the instruction should look like. It is
139 incomplete because it may contain @code{match_operand},
140 @code{match_operator}, and @code{match_dup} expressions that stand for
141 operands of the instruction.
143 If the vector has only one element, that element is the template for the
144 instruction pattern. If the vector has multiple elements, then the
145 instruction pattern is a @code{parallel} expression containing the
149 @cindex pattern conditions
150 @cindex conditions, in patterns
151 A condition. This is a string which contains a C expression that is
152 the final test to decide whether an insn body matches this pattern.
154 @cindex named patterns and conditions
155 For a named pattern, the condition (if present) may not depend on
156 the data in the insn being matched, but only the target-machine-type
157 flags. The compiler needs to test these conditions during
158 initialization in order to learn exactly which named instructions are
159 available in a particular run.
162 For nameless patterns, the condition is applied only when matching an
163 individual insn, and only after the insn has matched the pattern's
164 recognition template. The insn's operands may be found in the vector
165 @code{operands}. For an insn where the condition has once matched, it
166 can't be used to control register allocation, for example by excluding
167 certain hard registers or hard register combinations.
170 The @dfn{output template}: a string that says how to output matching
171 insns as assembler code. @samp{%} in this string specifies where
172 to substitute the value of an operand. @xref{Output Template}.
174 When simple substitution isn't general enough, you can specify a piece
175 of C code to compute the output. @xref{Output Statement}.
178 Optionally, a vector containing the values of attributes for insns matching
179 this pattern. @xref{Insn Attributes}.
183 @section Example of @code{define_insn}
184 @cindex @code{define_insn} example
186 Here is an actual example of an instruction pattern, for the 68000/68020.
191 (match_operand:SI 0 "general_operand" "rm"))]
195 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
197 return \"cmpl #0,%0\";
202 This can also be written using braced strings:
207 (match_operand:SI 0 "general_operand" "rm"))]
210 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
216 This is an instruction that sets the condition codes based on the value of
217 a general operand. It has no condition, so any insn whose RTL description
218 has the form shown may be handled according to this pattern. The name
219 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation
220 pass that, when it is necessary to test such a value, an insn to do so
221 can be constructed using this pattern.
223 The output control string is a piece of C code which chooses which
224 output template to return based on the kind of operand and the specific
225 type of CPU for which code is being generated.
227 @samp{"rm"} is an operand constraint. Its meaning is explained below.
230 @section RTL Template
231 @cindex RTL insn template
232 @cindex generating insns
233 @cindex insns, generating
234 @cindex recognizing insns
235 @cindex insns, recognizing
237 The RTL template is used to define which insns match the particular pattern
238 and how to find their operands. For named patterns, the RTL template also
239 says how to construct an insn from specified operands.
241 Construction involves substituting specified operands into a copy of the
242 template. Matching involves determining the values that serve as the
243 operands in the insn being matched. Both of these activities are
244 controlled by special expression types that direct matching and
245 substitution of the operands.
248 @findex match_operand
249 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
250 This expression is a placeholder for operand number @var{n} of
251 the insn. When constructing an insn, operand number @var{n}
252 will be substituted at this point. When matching an insn, whatever
253 appears at this position in the insn will be taken as operand
254 number @var{n}; but it must satisfy @var{predicate} or this instruction
255 pattern will not match at all.
257 Operand numbers must be chosen consecutively counting from zero in
258 each instruction pattern. There may be only one @code{match_operand}
259 expression in the pattern for each operand number. Usually operands
260 are numbered in the order of appearance in @code{match_operand}
261 expressions. In the case of a @code{define_expand}, any operand numbers
262 used only in @code{match_dup} expressions have higher values than all
263 other operand numbers.
265 @var{predicate} is a string that is the name of a function that
266 accepts two arguments, an expression and a machine mode.
267 @xref{Predicates}. During matching, the function will be called with
268 the putative operand as the expression and @var{m} as the mode
269 argument (if @var{m} is not specified, @code{VOIDmode} will be used,
270 which normally causes @var{predicate} to accept any mode). If it
271 returns zero, this instruction pattern fails to match.
272 @var{predicate} may be an empty string; then it means no test is to be
273 done on the operand, so anything which occurs in this position is
276 Most of the time, @var{predicate} will reject modes other than @var{m}---but
277 not always. For example, the predicate @code{address_operand} uses
278 @var{m} as the mode of memory ref that the address should be valid for.
279 Many predicates accept @code{const_int} nodes even though their mode is
282 @var{constraint} controls reloading and the choice of the best register
283 class to use for a value, as explained later (@pxref{Constraints}).
284 If the constraint would be an empty string, it can be omitted.
286 People are often unclear on the difference between the constraint and the
287 predicate. The predicate helps decide whether a given insn matches the
288 pattern. The constraint plays no role in this decision; instead, it
289 controls various decisions in the case of an insn which does match.
291 @findex match_scratch
292 @item (match_scratch:@var{m} @var{n} @var{constraint})
293 This expression is also a placeholder for operand number @var{n}
294 and indicates that operand must be a @code{scratch} or @code{reg}
297 When matching patterns, this is equivalent to
300 (match_operand:@var{m} @var{n} "scratch_operand" @var{pred})
303 but, when generating RTL, it produces a (@code{scratch}:@var{m})
306 If the last few expressions in a @code{parallel} are @code{clobber}
307 expressions whose operands are either a hard register or
308 @code{match_scratch}, the combiner can add or delete them when
309 necessary. @xref{Side Effects}.
312 @item (match_dup @var{n})
313 This expression is also a placeholder for operand number @var{n}.
314 It is used when the operand needs to appear more than once in the
317 In construction, @code{match_dup} acts just like @code{match_operand}:
318 the operand is substituted into the insn being constructed. But in
319 matching, @code{match_dup} behaves differently. It assumes that operand
320 number @var{n} has already been determined by a @code{match_operand}
321 appearing earlier in the recognition template, and it matches only an
322 identical-looking expression.
324 Note that @code{match_dup} should not be used to tell the compiler that
325 a particular register is being used for two operands (example:
326 @code{add} that adds one register to another; the second register is
327 both an input operand and the output operand). Use a matching
328 constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
329 operand is used in two places in the template, such as an instruction
330 that computes both a quotient and a remainder, where the opcode takes
331 two input operands but the RTL template has to refer to each of those
332 twice; once for the quotient pattern and once for the remainder pattern.
334 @findex match_operator
335 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
336 This pattern is a kind of placeholder for a variable RTL expression
339 When constructing an insn, it stands for an RTL expression whose
340 expression code is taken from that of operand @var{n}, and whose
341 operands are constructed from the patterns @var{operands}.
343 When matching an expression, it matches an expression if the function
344 @var{predicate} returns nonzero on that expression @emph{and} the
345 patterns @var{operands} match the operands of the expression.
347 Suppose that the function @code{commutative_operator} is defined as
348 follows, to match any expression whose operator is one of the
349 commutative arithmetic operators of RTL and whose mode is @var{mode}:
353 commutative_integer_operator (x, mode)
355 enum machine_mode mode;
357 enum rtx_code code = GET_CODE (x);
358 if (GET_MODE (x) != mode)
360 return (GET_RTX_CLASS (code) == RTX_COMM_ARITH
361 || code == EQ || code == NE);
365 Then the following pattern will match any RTL expression consisting
366 of a commutative operator applied to two general operands:
369 (match_operator:SI 3 "commutative_operator"
370 [(match_operand:SI 1 "general_operand" "g")
371 (match_operand:SI 2 "general_operand" "g")])
374 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
375 because the expressions to be matched all contain two operands.
377 When this pattern does match, the two operands of the commutative
378 operator are recorded as operands 1 and 2 of the insn. (This is done
379 by the two instances of @code{match_operand}.) Operand 3 of the insn
380 will be the entire commutative expression: use @code{GET_CODE
381 (operands[3])} to see which commutative operator was used.
383 The machine mode @var{m} of @code{match_operator} works like that of
384 @code{match_operand}: it is passed as the second argument to the
385 predicate function, and that function is solely responsible for
386 deciding whether the expression to be matched ``has'' that mode.
388 When constructing an insn, argument 3 of the gen-function will specify
389 the operation (i.e.@: the expression code) for the expression to be
390 made. It should be an RTL expression, whose expression code is copied
391 into a new expression whose operands are arguments 1 and 2 of the
392 gen-function. The subexpressions of argument 3 are not used;
393 only its expression code matters.
395 When @code{match_operator} is used in a pattern for matching an insn,
396 it usually best if the operand number of the @code{match_operator}
397 is higher than that of the actual operands of the insn. This improves
398 register allocation because the register allocator often looks at
399 operands 1 and 2 of insns to see if it can do register tying.
401 There is no way to specify constraints in @code{match_operator}. The
402 operand of the insn which corresponds to the @code{match_operator}
403 never has any constraints because it is never reloaded as a whole.
404 However, if parts of its @var{operands} are matched by
405 @code{match_operand} patterns, those parts may have constraints of
409 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
410 Like @code{match_dup}, except that it applies to operators instead of
411 operands. When constructing an insn, operand number @var{n} will be
412 substituted at this point. But in matching, @code{match_op_dup} behaves
413 differently. It assumes that operand number @var{n} has already been
414 determined by a @code{match_operator} appearing earlier in the
415 recognition template, and it matches only an identical-looking
418 @findex match_parallel
419 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
420 This pattern is a placeholder for an insn that consists of a
421 @code{parallel} expression with a variable number of elements. This
422 expression should only appear at the top level of an insn pattern.
424 When constructing an insn, operand number @var{n} will be substituted at
425 this point. When matching an insn, it matches if the body of the insn
426 is a @code{parallel} expression with at least as many elements as the
427 vector of @var{subpat} expressions in the @code{match_parallel}, if each
428 @var{subpat} matches the corresponding element of the @code{parallel},
429 @emph{and} the function @var{predicate} returns nonzero on the
430 @code{parallel} that is the body of the insn. It is the responsibility
431 of the predicate to validate elements of the @code{parallel} beyond
432 those listed in the @code{match_parallel}.
434 A typical use of @code{match_parallel} is to match load and store
435 multiple expressions, which can contain a variable number of elements
436 in a @code{parallel}. For example,
440 [(match_parallel 0 "load_multiple_operation"
441 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
442 (match_operand:SI 2 "memory_operand" "m"))
444 (clobber (reg:SI 179))])]
449 This example comes from @file{a29k.md}. The function
450 @code{load_multiple_operation} is defined in @file{a29k.c} and checks
451 that subsequent elements in the @code{parallel} are the same as the
452 @code{set} in the pattern, except that they are referencing subsequent
453 registers and memory locations.
455 An insn that matches this pattern might look like:
459 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
461 (clobber (reg:SI 179))
463 (mem:SI (plus:SI (reg:SI 100)
466 (mem:SI (plus:SI (reg:SI 100)
470 @findex match_par_dup
471 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
472 Like @code{match_op_dup}, but for @code{match_parallel} instead of
473 @code{match_operator}.
477 @node Output Template
478 @section Output Templates and Operand Substitution
479 @cindex output templates
480 @cindex operand substitution
482 @cindex @samp{%} in template
484 The @dfn{output template} is a string which specifies how to output the
485 assembler code for an instruction pattern. Most of the template is a
486 fixed string which is output literally. The character @samp{%} is used
487 to specify where to substitute an operand; it can also be used to
488 identify places where different variants of the assembler require
491 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
492 operand @var{n} at that point in the string.
494 @samp{%} followed by a letter and a digit says to output an operand in an
495 alternate fashion. Four letters have standard, built-in meanings described
496 below. The machine description macro @code{PRINT_OPERAND} can define
497 additional letters with nonstandard meanings.
499 @samp{%c@var{digit}} can be used to substitute an operand that is a
500 constant value without the syntax that normally indicates an immediate
503 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
504 the constant is negated before printing.
506 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
507 memory reference, with the actual operand treated as the address. This may
508 be useful when outputting a ``load address'' instruction, because often the
509 assembler syntax for such an instruction requires you to write the operand
510 as if it were a memory reference.
512 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
515 @samp{%=} outputs a number which is unique to each instruction in the
516 entire compilation. This is useful for making local labels to be
517 referred to more than once in a single template that generates multiple
518 assembler instructions.
520 @samp{%} followed by a punctuation character specifies a substitution that
521 does not use an operand. Only one case is standard: @samp{%%} outputs a
522 @samp{%} into the assembler code. Other nonstandard cases can be
523 defined in the @code{PRINT_OPERAND} macro. You must also define
524 which punctuation characters are valid with the
525 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
529 The template may generate multiple assembler instructions. Write the text
530 for the instructions, with @samp{\;} between them.
532 @cindex matching operands
533 When the RTL contains two operands which are required by constraint to match
534 each other, the output template must refer only to the lower-numbered operand.
535 Matching operands are not always identical, and the rest of the compiler
536 arranges to put the proper RTL expression for printing into the lower-numbered
539 One use of nonstandard letters or punctuation following @samp{%} is to
540 distinguish between different assembler languages for the same machine; for
541 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
542 requires periods in most opcode names, while MIT syntax does not. For
543 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
544 syntax. The same file of patterns is used for both kinds of output syntax,
545 but the character sequence @samp{%.} is used in each place where Motorola
546 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
547 defines the sequence to output a period; the macro for MIT syntax defines
550 @cindex @code{#} in template
551 As a special case, a template consisting of the single character @code{#}
552 instructs the compiler to first split the insn, and then output the
553 resulting instructions separately. This helps eliminate redundancy in the
554 output templates. If you have a @code{define_insn} that needs to emit
555 multiple assembler instructions, and there is a matching @code{define_split}
556 already defined, then you can simply use @code{#} as the output template
557 instead of writing an output template that emits the multiple assembler
560 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
561 of the form @samp{@{option0|option1|option2@}} in the templates. These
562 describe multiple variants of assembler language syntax.
563 @xref{Instruction Output}.
565 @node Output Statement
566 @section C Statements for Assembler Output
567 @cindex output statements
568 @cindex C statements for assembler output
569 @cindex generating assembler output
571 Often a single fixed template string cannot produce correct and efficient
572 assembler code for all the cases that are recognized by a single
573 instruction pattern. For example, the opcodes may depend on the kinds of
574 operands; or some unfortunate combinations of operands may require extra
575 machine instructions.
577 If the output control string starts with a @samp{@@}, then it is actually
578 a series of templates, each on a separate line. (Blank lines and
579 leading spaces and tabs are ignored.) The templates correspond to the
580 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
581 if a target machine has a two-address add instruction @samp{addr} to add
582 into a register and another @samp{addm} to add a register to memory, you
583 might write this pattern:
586 (define_insn "addsi3"
587 [(set (match_operand:SI 0 "general_operand" "=r,m")
588 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
589 (match_operand:SI 2 "general_operand" "g,r")))]
596 @cindex @code{*} in template
597 @cindex asterisk in template
598 If the output control string starts with a @samp{*}, then it is not an
599 output template but rather a piece of C program that should compute a
600 template. It should execute a @code{return} statement to return the
601 template-string you want. Most such templates use C string literals, which
602 require doublequote characters to delimit them. To include these
603 doublequote characters in the string, prefix each one with @samp{\}.
605 If the output control string is written as a brace block instead of a
606 double-quoted string, it is automatically assumed to be C code. In that
607 case, it is not necessary to put in a leading asterisk, or to escape the
608 doublequotes surrounding C string literals.
610 The operands may be found in the array @code{operands}, whose C data type
613 It is very common to select different ways of generating assembler code
614 based on whether an immediate operand is within a certain range. Be
615 careful when doing this, because the result of @code{INTVAL} is an
616 integer on the host machine. If the host machine has more bits in an
617 @code{int} than the target machine has in the mode in which the constant
618 will be used, then some of the bits you get from @code{INTVAL} will be
619 superfluous. For proper results, you must carefully disregard the
620 values of those bits.
622 @findex output_asm_insn
623 It is possible to output an assembler instruction and then go on to output
624 or compute more of them, using the subroutine @code{output_asm_insn}. This
625 receives two arguments: a template-string and a vector of operands. The
626 vector may be @code{operands}, or it may be another array of @code{rtx}
627 that you declare locally and initialize yourself.
629 @findex which_alternative
630 When an insn pattern has multiple alternatives in its constraints, often
631 the appearance of the assembler code is determined mostly by which alternative
632 was matched. When this is so, the C code can test the variable
633 @code{which_alternative}, which is the ordinal number of the alternative
634 that was actually satisfied (0 for the first, 1 for the second alternative,
637 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
638 for registers and @samp{clrmem} for memory locations. Here is how
639 a pattern could use @code{which_alternative} to choose between them:
643 [(set (match_operand:SI 0 "general_operand" "=r,m")
647 return (which_alternative == 0
648 ? "clrreg %0" : "clrmem %0");
652 The example above, where the assembler code to generate was
653 @emph{solely} determined by the alternative, could also have been specified
654 as follows, having the output control string start with a @samp{@@}:
659 [(set (match_operand:SI 0 "general_operand" "=r,m")
671 @cindex operand predicates
672 @cindex operator predicates
674 A predicate determines whether a @code{match_operand} or
675 @code{match_operator} expression matches, and therefore whether the
676 surrounding instruction pattern will be used for that combination of
677 operands. GCC has a number of machine-independent predicates, and you
678 can define machine-specific predicates as needed. By convention,
679 predicates used with @code{match_operand} have names that end in
680 @samp{_operand}, and those used with @code{match_operator} have names
681 that end in @samp{_operator}.
683 All predicates are Boolean functions (in the mathematical sense) of
684 two arguments: the RTL expression that is being considered at that
685 position in the instruction pattern, and the machine mode that the
686 @code{match_operand} or @code{match_operator} specifies. In this
687 section, the first argument is called @var{op} and the second argument
688 @var{mode}. Predicates can be called from C as ordinary two-argument
689 functions; this can be useful in output templates or other
690 machine-specific code.
692 Operand predicates can allow operands that are not actually acceptable
693 to the hardware, as long as the constraints give reload the ability to
694 fix them up (@pxref{Constraints}). However, GCC will usually generate
695 better code if the predicates specify the requirements of the machine
696 instructions as closely as possible. Reload cannot fix up operands
697 that must be constants (``immediate operands''); you must use a
698 predicate that allows only constants, or else enforce the requirement
699 in the extra condition.
701 @cindex predicates and machine modes
702 @cindex normal predicates
703 @cindex special predicates
704 Most predicates handle their @var{mode} argument in a uniform manner.
705 If @var{mode} is @code{VOIDmode} (unspecified), then @var{op} can have
706 any mode. If @var{mode} is anything else, then @var{op} must have the
707 same mode, unless @var{op} is a @code{CONST_INT} or integer
708 @code{CONST_DOUBLE}. These RTL expressions always have
709 @code{VOIDmode}, so it would be counterproductive to check that their
710 mode matches. Instead, predicates that accept @code{CONST_INT} and/or
711 integer @code{CONST_DOUBLE} check that the value stored in the
712 constant will fit in the requested mode.
714 Predicates with this behavior are called @dfn{normal}.
715 @command{genrecog} can optimize the instruction recognizer based on
716 knowledge of how normal predicates treat modes. It can also diagnose
717 certain kinds of common errors in the use of normal predicates; for
718 instance, it is almost always an error to use a normal predicate
719 without specifying a mode.
721 Predicates that do something different with their @var{mode} argument
722 are called @dfn{special}. The generic predicates
723 @code{address_operand} and @code{pmode_register_operand} are special
724 predicates. @command{genrecog} does not do any optimizations or
725 diagnosis when special predicates are used.
728 * Machine-Independent Predicates:: Predicates available to all back ends.
729 * Defining Predicates:: How to write machine-specific predicate
733 @node Machine-Independent Predicates
734 @subsection Machine-Independent Predicates
735 @cindex machine-independent predicates
736 @cindex generic predicates
738 These are the generic predicates available to all back ends. They are
739 defined in @file{recog.c}. The first category of predicates allow
740 only constant, or @dfn{immediate}, operands.
742 @defun immediate_operand
743 This predicate allows any sort of constant that fits in @var{mode}.
744 It is an appropriate choice for instructions that take operands that
748 @defun const_int_operand
749 This predicate allows any @code{CONST_INT} expression that fits in
750 @var{mode}. It is an appropriate choice for an immediate operand that
751 does not allow a symbol or label.
754 @defun const_double_operand
755 This predicate accepts any @code{CONST_DOUBLE} expression that has
756 exactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also
757 accept @code{CONST_INT}. It is intended for immediate floating point
762 The second category of predicates allow only some kind of machine
765 @defun register_operand
766 This predicate allows any @code{REG} or @code{SUBREG} expression that
767 is valid for @var{mode}. It is often suitable for arithmetic
768 instruction operands on a RISC machine.
771 @defun pmode_register_operand
772 This is a slight variant on @code{register_operand} which works around
773 a limitation in the machine-description reader.
776 (match_operand @var{n} "pmode_register_operand" @var{constraint})
783 (match_operand:P @var{n} "register_operand" @var{constraint})
787 would mean, if the machine-description reader accepted @samp{:P}
788 mode suffixes. Unfortunately, it cannot, because @code{Pmode} is an
789 alias for some other mode, and might vary with machine-specific
790 options. @xref{Misc}.
793 @defun scratch_operand
794 This predicate allows hard registers and @code{SCRATCH} expressions,
795 but not pseudo-registers. It is used internally by @code{match_scratch};
796 it should not be used directly.
800 The third category of predicates allow only some kind of memory reference.
802 @defun memory_operand
803 This predicate allows any valid reference to a quantity of mode
804 @var{mode} in memory, as determined by the weak form of
805 @code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}).
808 @defun address_operand
809 This predicate is a little unusual; it allows any operand that is a
810 valid expression for the @emph{address} of a quantity of mode
811 @var{mode}, again determined by the weak form of
812 @code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if
813 @samp{@w{(mem:@var{mode} (@var{exp}))}} is acceptable to
814 @code{memory_operand}, then @var{exp} is acceptable to
815 @code{address_operand}. Note that @var{exp} does not necessarily have
819 @defun indirect_operand
820 This is a stricter form of @code{memory_operand} which allows only
821 memory references with a @code{general_operand} as the address
822 expression. New uses of this predicate are discouraged, because
823 @code{general_operand} is very permissive, so it's hard to tell what
824 an @code{indirect_operand} does or does not allow. If a target has
825 different requirements for memory operands for different instructions,
826 it is better to define target-specific predicates which enforce the
827 hardware's requirements explicitly.
831 This predicate allows a memory reference suitable for pushing a value
832 onto the stack. This will be a @code{MEM} which refers to
833 @code{stack_pointer_rtx}, with a side-effect in its address expression
834 (@pxref{Incdec}); which one is determined by the
835 @code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}).
839 This predicate allows a memory reference suitable for popping a value
840 off the stack. Again, this will be a @code{MEM} referring to
841 @code{stack_pointer_rtx}, with a side-effect in its address
842 expression. However, this time @code{STACK_POP_CODE} is expected.
846 The fourth category of predicates allow some combination of the above
849 @defun nonmemory_operand
850 This predicate allows any immediate or register operand valid for @var{mode}.
853 @defun nonimmediate_operand
854 This predicate allows any register or memory operand valid for @var{mode}.
857 @defun general_operand
858 This predicate allows any immediate, register, or memory operand
859 valid for @var{mode}.
863 Finally, there are two generic operator predicates.
865 @defun comparison_operator
866 This predicate matches any expression which performs an arithmetic
867 comparison in @var{mode}; that is, @code{COMPARISON_P} is true for the
871 @defun ordered_comparison_operator
872 This predicate matches any expression which performs an arithmetic
873 comparison in @var{mode} and whose expression code is valid for integer
874 modes; that is, the expression code will be one of @code{eq}, @code{ne},
875 @code{lt}, @code{ltu}, @code{le}, @code{leu}, @code{gt}, @code{gtu},
876 @code{ge}, @code{geu}.
879 @node Defining Predicates
880 @subsection Defining Machine-Specific Predicates
881 @cindex defining predicates
882 @findex define_predicate
883 @findex define_special_predicate
885 Many machines have requirements for their operands that cannot be
886 expressed precisely using the generic predicates. You can define
887 additional predicates using @code{define_predicate} and
888 @code{define_special_predicate} expressions. These expressions have
893 The name of the predicate, as it will be referred to in
894 @code{match_operand} or @code{match_operator} expressions.
897 An RTL expression which evaluates to true if the predicate allows the
898 operand @var{op}, false if it does not. This expression can only use
899 the following RTL codes:
903 When written inside a predicate expression, a @code{MATCH_OPERAND}
904 expression evaluates to true if the predicate it names would allow
905 @var{op}. The operand number and constraint are ignored. Due to
906 limitations in @command{genrecog}, you can only refer to generic
907 predicates and predicates that have already been defined.
910 This expression evaluates to true if @var{op} or a specified
911 subexpression of @var{op} has one of a given list of RTX codes.
913 The first operand of this expression is a string constant containing a
914 comma-separated list of RTX code names (in lower case). These are the
915 codes for which the @code{MATCH_CODE} will be true.
917 The second operand is a string constant which indicates what
918 subexpression of @var{op} to examine. If it is absent or the empty
919 string, @var{op} itself is examined. Otherwise, the string constant
920 must be a sequence of digits and/or lowercase letters. Each character
921 indicates a subexpression to extract from the current expression; for
922 the first character this is @var{op}, for the second and subsequent
923 characters it is the result of the previous character. A digit
924 @var{n} extracts @samp{@w{XEXP (@var{e}, @var{n})}}; a letter @var{l}
925 extracts @samp{@w{XVECEXP (@var{e}, 0, @var{n})}} where @var{n} is the
926 alphabetic ordinal of @var{l} (0 for `a', 1 for 'b', and so on). The
927 @code{MATCH_CODE} then examines the RTX code of the subexpression
928 extracted by the complete string. It is not possible to extract
929 components of an @code{rtvec} that is not at position 0 within its RTX
933 This expression has one operand, a string constant containing a C
934 expression. The predicate's arguments, @var{op} and @var{mode}, are
935 available with those names in the C expression. The @code{MATCH_TEST}
936 evaluates to true if the C expression evaluates to a nonzero value.
937 @code{MATCH_TEST} expressions must not have side effects.
943 The basic @samp{MATCH_} expressions can be combined using these
944 logical operators, which have the semantics of the C operators
945 @samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively. As
946 in Common Lisp, you may give an @code{AND} or @code{IOR} expression an
947 arbitrary number of arguments; this has exactly the same effect as
948 writing a chain of two-argument @code{AND} or @code{IOR} expressions.
952 An optional block of C code, which should execute
953 @samp{@w{return true}} if the predicate is found to match and
954 @samp{@w{return false}} if it does not. It must not have any side
955 effects. The predicate arguments, @var{op} and @var{mode}, are
956 available with those names.
958 If a code block is present in a predicate definition, then the RTL
959 expression must evaluate to true @emph{and} the code block must
960 execute @samp{@w{return true}} for the predicate to allow the operand.
961 The RTL expression is evaluated first; do not re-check anything in the
962 code block that was checked in the RTL expression.
965 The program @command{genrecog} scans @code{define_predicate} and
966 @code{define_special_predicate} expressions to determine which RTX
967 codes are possibly allowed. You should always make this explicit in
968 the RTL predicate expression, using @code{MATCH_OPERAND} and
971 Here is an example of a simple predicate definition, from the IA64
976 ;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.}
977 (define_predicate "small_addr_symbolic_operand"
978 (and (match_code "symbol_ref")
979 (match_test "SYMBOL_REF_SMALL_ADDR_P (op)")))
984 And here is another, showing the use of the C block.
988 ;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.}
989 (define_predicate "gr_register_operand"
990 (match_operand 0 "register_operand")
993 if (GET_CODE (op) == SUBREG)
994 op = SUBREG_REG (op);
997 return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno));
1002 Predicates written with @code{define_predicate} automatically include
1003 a test that @var{mode} is @code{VOIDmode}, or @var{op} has the same
1004 mode as @var{mode}, or @var{op} is a @code{CONST_INT} or
1005 @code{CONST_DOUBLE}. They do @emph{not} check specifically for
1006 integer @code{CONST_DOUBLE}, nor do they test that the value of either
1007 kind of constant fits in the requested mode. This is because
1008 target-specific predicates that take constants usually have to do more
1009 stringent value checks anyway. If you need the exact same treatment
1010 of @code{CONST_INT} or @code{CONST_DOUBLE} that the generic predicates
1011 provide, use a @code{MATCH_OPERAND} subexpression to call
1012 @code{const_int_operand}, @code{const_double_operand}, or
1013 @code{immediate_operand}.
1015 Predicates written with @code{define_special_predicate} do not get any
1016 automatic mode checks, and are treated as having special mode handling
1017 by @command{genrecog}.
1019 The program @command{genpreds} is responsible for generating code to
1020 test predicates. It also writes a header file containing function
1021 declarations for all machine-specific predicates. It is not necessary
1022 to declare these predicates in @file{@var{cpu}-protos.h}.
1025 @c Most of this node appears by itself (in a different place) even
1026 @c when the INTERNALS flag is clear. Passages that require the internals
1027 @c manual's context are conditionalized to appear only in the internals manual.
1030 @section Operand Constraints
1031 @cindex operand constraints
1034 Each @code{match_operand} in an instruction pattern can specify
1035 constraints for the operands allowed. The constraints allow you to
1036 fine-tune matching within the set of operands allowed by the
1042 @section Constraints for @code{asm} Operands
1043 @cindex operand constraints, @code{asm}
1044 @cindex constraints, @code{asm}
1045 @cindex @code{asm} constraints
1047 Here are specific details on what constraint letters you can use with
1048 @code{asm} operands.
1050 Constraints can say whether
1051 an operand may be in a register, and which kinds of register; whether the
1052 operand can be a memory reference, and which kinds of address; whether the
1053 operand may be an immediate constant, and which possible values it may
1054 have. Constraints can also require two operands to match.
1058 * Simple Constraints:: Basic use of constraints.
1059 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1060 * Class Preferences:: Constraints guide which hard register to put things in.
1061 * Modifiers:: More precise control over effects of constraints.
1062 * Disable Insn Alternatives:: Disable insn alternatives using the @code{enabled} attribute.
1063 * Machine Constraints:: Existing constraints for some particular machines.
1064 * Define Constraints:: How to define machine-specific constraints.
1065 * C Constraint Interface:: How to test constraints from C code.
1071 * Simple Constraints:: Basic use of constraints.
1072 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1073 * Modifiers:: More precise control over effects of constraints.
1074 * Machine Constraints:: Special constraints for some particular machines.
1078 @node Simple Constraints
1079 @subsection Simple Constraints
1080 @cindex simple constraints
1082 The simplest kind of constraint is a string full of letters, each of
1083 which describes one kind of operand that is permitted. Here are
1084 the letters that are allowed:
1088 Whitespace characters are ignored and can be inserted at any position
1089 except the first. This enables each alternative for different operands to
1090 be visually aligned in the machine description even if they have different
1091 number of constraints and modifiers.
1093 @cindex @samp{m} in constraint
1094 @cindex memory references in constraints
1096 A memory operand is allowed, with any kind of address that the machine
1097 supports in general.
1098 Note that the letter used for the general memory constraint can be
1099 re-defined by a back end using the @code{TARGET_MEM_CONSTRAINT} macro.
1101 @cindex offsettable address
1102 @cindex @samp{o} in constraint
1104 A memory operand is allowed, but only if the address is
1105 @dfn{offsettable}. This means that adding a small integer (actually,
1106 the width in bytes of the operand, as determined by its machine mode)
1107 may be added to the address and the result is also a valid memory
1110 @cindex autoincrement/decrement addressing
1111 For example, an address which is constant is offsettable; so is an
1112 address that is the sum of a register and a constant (as long as a
1113 slightly larger constant is also within the range of address-offsets
1114 supported by the machine); but an autoincrement or autodecrement
1115 address is not offsettable. More complicated indirect/indexed
1116 addresses may or may not be offsettable depending on the other
1117 addressing modes that the machine supports.
1119 Note that in an output operand which can be matched by another
1120 operand, the constraint letter @samp{o} is valid only when accompanied
1121 by both @samp{<} (if the target machine has predecrement addressing)
1122 and @samp{>} (if the target machine has preincrement addressing).
1124 @cindex @samp{V} in constraint
1126 A memory operand that is not offsettable. In other words, anything that
1127 would fit the @samp{m} constraint but not the @samp{o} constraint.
1129 @cindex @samp{<} in constraint
1131 A memory operand with autodecrement addressing (either predecrement or
1132 postdecrement) is allowed.
1134 @cindex @samp{>} in constraint
1136 A memory operand with autoincrement addressing (either preincrement or
1137 postincrement) is allowed.
1139 @cindex @samp{r} in constraint
1140 @cindex registers in constraints
1142 A register operand is allowed provided that it is in a general
1145 @cindex constants in constraints
1146 @cindex @samp{i} in constraint
1148 An immediate integer operand (one with constant value) is allowed.
1149 This includes symbolic constants whose values will be known only at
1150 assembly time or later.
1152 @cindex @samp{n} in constraint
1154 An immediate integer operand with a known numeric value is allowed.
1155 Many systems cannot support assembly-time constants for operands less
1156 than a word wide. Constraints for these operands should use @samp{n}
1157 rather than @samp{i}.
1159 @cindex @samp{I} in constraint
1160 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
1161 Other letters in the range @samp{I} through @samp{P} may be defined in
1162 a machine-dependent fashion to permit immediate integer operands with
1163 explicit integer values in specified ranges. For example, on the
1164 68000, @samp{I} is defined to stand for the range of values 1 to 8.
1165 This is the range permitted as a shift count in the shift
1168 @cindex @samp{E} in constraint
1170 An immediate floating operand (expression code @code{const_double}) is
1171 allowed, but only if the target floating point format is the same as
1172 that of the host machine (on which the compiler is running).
1174 @cindex @samp{F} in constraint
1176 An immediate floating operand (expression code @code{const_double} or
1177 @code{const_vector}) is allowed.
1179 @cindex @samp{G} in constraint
1180 @cindex @samp{H} in constraint
1181 @item @samp{G}, @samp{H}
1182 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
1183 permit immediate floating operands in particular ranges of values.
1185 @cindex @samp{s} in constraint
1187 An immediate integer operand whose value is not an explicit integer is
1190 This might appear strange; if an insn allows a constant operand with a
1191 value not known at compile time, it certainly must allow any known
1192 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
1193 better code to be generated.
1195 For example, on the 68000 in a fullword instruction it is possible to
1196 use an immediate operand; but if the immediate value is between @minus{}128
1197 and 127, better code results from loading the value into a register and
1198 using the register. This is because the load into the register can be
1199 done with a @samp{moveq} instruction. We arrange for this to happen
1200 by defining the letter @samp{K} to mean ``any integer outside the
1201 range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand
1204 @cindex @samp{g} in constraint
1206 Any register, memory or immediate integer operand is allowed, except for
1207 registers that are not general registers.
1209 @cindex @samp{X} in constraint
1212 Any operand whatsoever is allowed, even if it does not satisfy
1213 @code{general_operand}. This is normally used in the constraint of
1214 a @code{match_scratch} when certain alternatives will not actually
1215 require a scratch register.
1218 Any operand whatsoever is allowed.
1221 @cindex @samp{0} in constraint
1222 @cindex digits in constraint
1223 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
1224 An operand that matches the specified operand number is allowed. If a
1225 digit is used together with letters within the same alternative, the
1226 digit should come last.
1228 This number is allowed to be more than a single digit. If multiple
1229 digits are encountered consecutively, they are interpreted as a single
1230 decimal integer. There is scant chance for ambiguity, since to-date
1231 it has never been desirable that @samp{10} be interpreted as matching
1232 either operand 1 @emph{or} operand 0. Should this be desired, one
1233 can use multiple alternatives instead.
1235 @cindex matching constraint
1236 @cindex constraint, matching
1237 This is called a @dfn{matching constraint} and what it really means is
1238 that the assembler has only a single operand that fills two roles
1240 considered separate in the RTL insn. For example, an add insn has two
1241 input operands and one output operand in the RTL, but on most CISC
1244 which @code{asm} distinguishes. For example, an add instruction uses
1245 two input operands and an output operand, but on most CISC
1247 machines an add instruction really has only two operands, one of them an
1248 input-output operand:
1254 Matching constraints are used in these circumstances.
1255 More precisely, the two operands that match must include one input-only
1256 operand and one output-only operand. Moreover, the digit must be a
1257 smaller number than the number of the operand that uses it in the
1261 For operands to match in a particular case usually means that they
1262 are identical-looking RTL expressions. But in a few special cases
1263 specific kinds of dissimilarity are allowed. For example, @code{*x}
1264 as an input operand will match @code{*x++} as an output operand.
1265 For proper results in such cases, the output template should always
1266 use the output-operand's number when printing the operand.
1269 @cindex load address instruction
1270 @cindex push address instruction
1271 @cindex address constraints
1272 @cindex @samp{p} in constraint
1274 An operand that is a valid memory address is allowed. This is
1275 for ``load address'' and ``push address'' instructions.
1277 @findex address_operand
1278 @samp{p} in the constraint must be accompanied by @code{address_operand}
1279 as the predicate in the @code{match_operand}. This predicate interprets
1280 the mode specified in the @code{match_operand} as the mode of the memory
1281 reference for which the address would be valid.
1283 @cindex other register constraints
1284 @cindex extensible constraints
1285 @item @var{other-letters}
1286 Other letters can be defined in machine-dependent fashion to stand for
1287 particular classes of registers or other arbitrary operand types.
1288 @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
1289 for data, address and floating point registers.
1293 In order to have valid assembler code, each operand must satisfy
1294 its constraint. But a failure to do so does not prevent the pattern
1295 from applying to an insn. Instead, it directs the compiler to modify
1296 the code so that the constraint will be satisfied. Usually this is
1297 done by copying an operand into a register.
1299 Contrast, therefore, the two instruction patterns that follow:
1303 [(set (match_operand:SI 0 "general_operand" "=r")
1304 (plus:SI (match_dup 0)
1305 (match_operand:SI 1 "general_operand" "r")))]
1311 which has two operands, one of which must appear in two places, and
1315 [(set (match_operand:SI 0 "general_operand" "=r")
1316 (plus:SI (match_operand:SI 1 "general_operand" "0")
1317 (match_operand:SI 2 "general_operand" "r")))]
1323 which has three operands, two of which are required by a constraint to be
1324 identical. If we are considering an insn of the form
1327 (insn @var{n} @var{prev} @var{next}
1329 (plus:SI (reg:SI 6) (reg:SI 109)))
1334 the first pattern would not apply at all, because this insn does not
1335 contain two identical subexpressions in the right place. The pattern would
1336 say, ``That does not look like an add instruction; try other patterns''.
1337 The second pattern would say, ``Yes, that's an add instruction, but there
1338 is something wrong with it''. It would direct the reload pass of the
1339 compiler to generate additional insns to make the constraint true. The
1340 results might look like this:
1343 (insn @var{n2} @var{prev} @var{n}
1344 (set (reg:SI 3) (reg:SI 6))
1347 (insn @var{n} @var{n2} @var{next}
1349 (plus:SI (reg:SI 3) (reg:SI 109)))
1353 It is up to you to make sure that each operand, in each pattern, has
1354 constraints that can handle any RTL expression that could be present for
1355 that operand. (When multiple alternatives are in use, each pattern must,
1356 for each possible combination of operand expressions, have at least one
1357 alternative which can handle that combination of operands.) The
1358 constraints don't need to @emph{allow} any possible operand---when this is
1359 the case, they do not constrain---but they must at least point the way to
1360 reloading any possible operand so that it will fit.
1364 If the constraint accepts whatever operands the predicate permits,
1365 there is no problem: reloading is never necessary for this operand.
1367 For example, an operand whose constraints permit everything except
1368 registers is safe provided its predicate rejects registers.
1370 An operand whose predicate accepts only constant values is safe
1371 provided its constraints include the letter @samp{i}. If any possible
1372 constant value is accepted, then nothing less than @samp{i} will do;
1373 if the predicate is more selective, then the constraints may also be
1377 Any operand expression can be reloaded by copying it into a register.
1378 So if an operand's constraints allow some kind of register, it is
1379 certain to be safe. It need not permit all classes of registers; the
1380 compiler knows how to copy a register into another register of the
1381 proper class in order to make an instruction valid.
1383 @cindex nonoffsettable memory reference
1384 @cindex memory reference, nonoffsettable
1386 A nonoffsettable memory reference can be reloaded by copying the
1387 address into a register. So if the constraint uses the letter
1388 @samp{o}, all memory references are taken care of.
1391 A constant operand can be reloaded by allocating space in memory to
1392 hold it as preinitialized data. Then the memory reference can be used
1393 in place of the constant. So if the constraint uses the letters
1394 @samp{o} or @samp{m}, constant operands are not a problem.
1397 If the constraint permits a constant and a pseudo register used in an insn
1398 was not allocated to a hard register and is equivalent to a constant,
1399 the register will be replaced with the constant. If the predicate does
1400 not permit a constant and the insn is re-recognized for some reason, the
1401 compiler will crash. Thus the predicate must always recognize any
1402 objects allowed by the constraint.
1405 If the operand's predicate can recognize registers, but the constraint does
1406 not permit them, it can make the compiler crash. When this operand happens
1407 to be a register, the reload pass will be stymied, because it does not know
1408 how to copy a register temporarily into memory.
1410 If the predicate accepts a unary operator, the constraint applies to the
1411 operand. For example, the MIPS processor at ISA level 3 supports an
1412 instruction which adds two registers in @code{SImode} to produce a
1413 @code{DImode} result, but only if the registers are correctly sign
1414 extended. This predicate for the input operands accepts a
1415 @code{sign_extend} of an @code{SImode} register. Write the constraint
1416 to indicate the type of register that is required for the operand of the
1420 @node Multi-Alternative
1421 @subsection Multiple Alternative Constraints
1422 @cindex multiple alternative constraints
1424 Sometimes a single instruction has multiple alternative sets of possible
1425 operands. For example, on the 68000, a logical-or instruction can combine
1426 register or an immediate value into memory, or it can combine any kind of
1427 operand into a register; but it cannot combine one memory location into
1430 These constraints are represented as multiple alternatives. An alternative
1431 can be described by a series of letters for each operand. The overall
1432 constraint for an operand is made from the letters for this operand
1433 from the first alternative, a comma, the letters for this operand from
1434 the second alternative, a comma, and so on until the last alternative.
1436 Here is how it is done for fullword logical-or on the 68000:
1439 (define_insn "iorsi3"
1440 [(set (match_operand:SI 0 "general_operand" "=m,d")
1441 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1442 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1446 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1447 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1448 2. The second alternative has @samp{d} (data register) for operand 0,
1449 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1450 @samp{%} in the constraints apply to all the alternatives; their
1451 meaning is explained in the next section (@pxref{Class Preferences}).
1454 @c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL
1455 If all the operands fit any one alternative, the instruction is valid.
1456 Otherwise, for each alternative, the compiler counts how many instructions
1457 must be added to copy the operands so that that alternative applies.
1458 The alternative requiring the least copying is chosen. If two alternatives
1459 need the same amount of copying, the one that comes first is chosen.
1460 These choices can be altered with the @samp{?} and @samp{!} characters:
1463 @cindex @samp{?} in constraint
1464 @cindex question mark
1466 Disparage slightly the alternative that the @samp{?} appears in,
1467 as a choice when no alternative applies exactly. The compiler regards
1468 this alternative as one unit more costly for each @samp{?} that appears
1471 @cindex @samp{!} in constraint
1472 @cindex exclamation point
1474 Disparage severely the alternative that the @samp{!} appears in.
1475 This alternative can still be used if it fits without reloading,
1476 but if reloading is needed, some other alternative will be used.
1480 When an insn pattern has multiple alternatives in its constraints, often
1481 the appearance of the assembler code is determined mostly by which
1482 alternative was matched. When this is so, the C code for writing the
1483 assembler code can use the variable @code{which_alternative}, which is
1484 the ordinal number of the alternative that was actually satisfied (0 for
1485 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1489 @node Class Preferences
1490 @subsection Register Class Preferences
1491 @cindex class preference constraints
1492 @cindex register class preference constraints
1494 @cindex voting between constraint alternatives
1495 The operand constraints have another function: they enable the compiler
1496 to decide which kind of hardware register a pseudo register is best
1497 allocated to. The compiler examines the constraints that apply to the
1498 insns that use the pseudo register, looking for the machine-dependent
1499 letters such as @samp{d} and @samp{a} that specify classes of registers.
1500 The pseudo register is put in whichever class gets the most ``votes''.
1501 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1502 favor of a general register. The machine description says which registers
1503 are considered general.
1505 Of course, on some machines all registers are equivalent, and no register
1506 classes are defined. Then none of this complexity is relevant.
1510 @subsection Constraint Modifier Characters
1511 @cindex modifiers in constraints
1512 @cindex constraint modifier characters
1514 @c prevent bad page break with this line
1515 Here are constraint modifier characters.
1518 @cindex @samp{=} in constraint
1520 Means that this operand is write-only for this instruction: the previous
1521 value is discarded and replaced by output data.
1523 @cindex @samp{+} in constraint
1525 Means that this operand is both read and written by the instruction.
1527 When the compiler fixes up the operands to satisfy the constraints,
1528 it needs to know which operands are inputs to the instruction and
1529 which are outputs from it. @samp{=} identifies an output; @samp{+}
1530 identifies an operand that is both input and output; all other operands
1531 are assumed to be input only.
1533 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1534 first character of the constraint string.
1536 @cindex @samp{&} in constraint
1537 @cindex earlyclobber operand
1539 Means (in a particular alternative) that this operand is an
1540 @dfn{earlyclobber} operand, which is modified before the instruction is
1541 finished using the input operands. Therefore, this operand may not lie
1542 in a register that is used as an input operand or as part of any memory
1545 @samp{&} applies only to the alternative in which it is written. In
1546 constraints with multiple alternatives, sometimes one alternative
1547 requires @samp{&} while others do not. See, for example, the
1548 @samp{movdf} insn of the 68000.
1550 An input operand can be tied to an earlyclobber operand if its only
1551 use as an input occurs before the early result is written. Adding
1552 alternatives of this form often allows GCC to produce better code
1553 when only some of the inputs can be affected by the earlyclobber.
1554 See, for example, the @samp{mulsi3} insn of the ARM@.
1556 @samp{&} does not obviate the need to write @samp{=}.
1558 @cindex @samp{%} in constraint
1560 Declares the instruction to be commutative for this operand and the
1561 following operand. This means that the compiler may interchange the
1562 two operands if that is the cheapest way to make all operands fit the
1565 This is often used in patterns for addition instructions
1566 that really have only two operands: the result must go in one of the
1567 arguments. Here for example, is how the 68000 halfword-add
1568 instruction is defined:
1571 (define_insn "addhi3"
1572 [(set (match_operand:HI 0 "general_operand" "=m,r")
1573 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1574 (match_operand:HI 2 "general_operand" "di,g")))]
1578 GCC can only handle one commutative pair in an asm; if you use more,
1579 the compiler may fail. Note that you need not use the modifier if
1580 the two alternatives are strictly identical; this would only waste
1581 time in the reload pass. The modifier is not operational after
1582 register allocation, so the result of @code{define_peephole2}
1583 and @code{define_split}s performed after reload cannot rely on
1584 @samp{%} to make the intended insn match.
1586 @cindex @samp{#} in constraint
1588 Says that all following characters, up to the next comma, are to be
1589 ignored as a constraint. They are significant only for choosing
1590 register preferences.
1592 @cindex @samp{*} in constraint
1594 Says that the following character should be ignored when choosing
1595 register preferences. @samp{*} has no effect on the meaning of the
1596 constraint as a constraint, and no effect on reloading.
1599 Here is an example: the 68000 has an instruction to sign-extend a
1600 halfword in a data register, and can also sign-extend a value by
1601 copying it into an address register. While either kind of register is
1602 acceptable, the constraints on an address-register destination are
1603 less strict, so it is best if register allocation makes an address
1604 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1605 constraint letter (for data register) is ignored when computing
1606 register preferences.
1609 (define_insn "extendhisi2"
1610 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1612 (match_operand:HI 1 "general_operand" "0,g")))]
1618 @node Machine Constraints
1619 @subsection Constraints for Particular Machines
1620 @cindex machine specific constraints
1621 @cindex constraints, machine specific
1623 Whenever possible, you should use the general-purpose constraint letters
1624 in @code{asm} arguments, since they will convey meaning more readily to
1625 people reading your code. Failing that, use the constraint letters
1626 that usually have very similar meanings across architectures. The most
1627 commonly used constraints are @samp{m} and @samp{r} (for memory and
1628 general-purpose registers respectively; @pxref{Simple Constraints}), and
1629 @samp{I}, usually the letter indicating the most common
1630 immediate-constant format.
1632 Each architecture defines additional constraints. These constraints
1633 are used by the compiler itself for instruction generation, as well as
1634 for @code{asm} statements; therefore, some of the constraints are not
1635 particularly useful for @code{asm}. Here is a summary of some of the
1636 machine-dependent constraints available on some particular machines;
1637 it includes both constraints that are useful for @code{asm} and
1638 constraints that aren't. The compiler source file mentioned in the
1639 table heading for each architecture is the definitive reference for
1640 the meanings of that architecture's constraints.
1643 @item ARM family---@file{config/arm/arm.h}
1646 Floating-point register
1649 VFP floating-point register
1652 One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0
1656 Floating-point constant that would satisfy the constraint @samp{F} if it
1660 Integer that is valid as an immediate operand in a data processing
1661 instruction. That is, an integer in the range 0 to 255 rotated by a
1665 Integer in the range @minus{}4095 to 4095
1668 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1671 Integer that satisfies constraint @samp{I} when negated (twos complement)
1674 Integer in the range 0 to 32
1677 A memory reference where the exact address is in a single register
1678 (`@samp{m}' is preferable for @code{asm} statements)
1681 An item in the constant pool
1684 A symbol in the text segment of the current file
1687 A memory reference suitable for VFP load/store insns (reg+constant offset)
1690 A memory reference suitable for iWMMXt load/store instructions.
1693 A memory reference suitable for the ARMv4 ldrsb instruction.
1696 @item AVR family---@file{config/avr/constraints.md}
1699 Registers from r0 to r15
1702 Registers from r16 to r23
1705 Registers from r16 to r31
1708 Registers from r24 to r31. These registers can be used in @samp{adiw} command
1711 Pointer register (r26--r31)
1714 Base pointer register (r28--r31)
1717 Stack pointer register (SPH:SPL)
1720 Temporary register r0
1723 Register pair X (r27:r26)
1726 Register pair Y (r29:r28)
1729 Register pair Z (r31:r30)
1732 Constant greater than @minus{}1, less than 64
1735 Constant greater than @minus{}64, less than 1
1744 Constant that fits in 8 bits
1747 Constant integer @minus{}1
1750 Constant integer 8, 16, or 24
1756 A floating point constant 0.0
1759 Integer constant in the range -6 @dots{} 5.
1762 A memory address based on Y or Z pointer with displacement.
1765 @item CRX Architecture---@file{config/crx/crx.h}
1769 Registers from r0 to r14 (registers without stack pointer)
1772 Register r16 (64-bit accumulator lo register)
1775 Register r17 (64-bit accumulator hi register)
1778 Register pair r16-r17. (64-bit accumulator lo-hi pair)
1781 Constant that fits in 3 bits
1784 Constant that fits in 4 bits
1787 Constant that fits in 5 bits
1790 Constant that is one of -1, 4, -4, 7, 8, 12, 16, 20, 32, 48
1793 Floating point constant that is legal for store immediate
1796 @item Hewlett-Packard PA-RISC---@file{config/pa/pa.h}
1802 Floating point register
1805 Shift amount register
1808 Floating point register (deprecated)
1811 Upper floating point register (32-bit), floating point register (64-bit)
1817 Signed 11-bit integer constant
1820 Signed 14-bit integer constant
1823 Integer constant that can be deposited with a @code{zdepi} instruction
1826 Signed 5-bit integer constant
1832 Integer constant that can be loaded with a @code{ldil} instruction
1835 Integer constant whose value plus one is a power of 2
1838 Integer constant that can be used for @code{and} operations in @code{depi}
1839 and @code{extru} instructions
1848 Floating-point constant 0.0
1851 A @code{lo_sum} data-linkage-table memory operand
1854 A memory operand that can be used as the destination operand of an
1855 integer store instruction
1858 A scaled or unscaled indexed memory operand
1861 A memory operand for floating-point loads and stores
1864 A register indirect memory operand
1867 @item picoChip family---@file{picochip.h}
1873 Pointer register. A register which can be used to access memory without
1874 supplying an offset. Any other register can be used to access memory,
1875 but will need a constant offset. In the case of the offset being zero,
1876 it is more efficient to use a pointer register, since this reduces code
1880 A twin register. A register which may be paired with an adjacent
1881 register to create a 32-bit register.
1884 Any absolute memory address (e.g., symbolic constant, symbolic
1888 4-bit signed integer.
1891 4-bit unsigned integer.
1894 8-bit signed integer.
1897 Any constant whose absolute value is no greater than 4-bits.
1900 10-bit signed integer
1903 16-bit signed integer.
1907 @item PowerPC and IBM RS6000---@file{config/rs6000/rs6000.h}
1910 Address base register
1913 Floating point register (containing 64-bit value)
1916 Floating point register (containing 32-bit value)
1922 @samp{MQ}, @samp{CTR}, or @samp{LINK} register
1931 @samp{LINK} register
1934 @samp{CR} register (condition register) number 0
1937 @samp{CR} register (condition register)
1940 @samp{FPMEM} stack memory for FPR-GPR transfers
1943 Signed 16-bit constant
1946 Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for
1947 @code{SImode} constants)
1950 Unsigned 16-bit constant
1953 Signed 16-bit constant shifted left 16 bits
1956 Constant larger than 31
1965 Constant whose negation is a signed 16-bit constant
1968 Floating point constant that can be loaded into a register with one
1969 instruction per word
1972 Integer/Floating point constant that can be loaded into a register using
1976 Memory operand. Note that on PowerPC targets, @code{m} can include
1977 addresses that update the base register. It is therefore only safe
1978 to use @samp{m} in an @code{asm} statement if that @code{asm} statement
1979 accesses the operand exactly once. The @code{asm} statement must also
1980 use @samp{%U@var{<opno>}} as a placeholder for the ``update'' flag in the
1981 corresponding load or store instruction. For example:
1984 asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
1990 asm ("st %1,%0" : "=m" (mem) : "r" (val));
1993 is not. Use @code{es} rather than @code{m} if you don't want the
1994 base register to be updated.
1997 A ``stable'' memory operand; that is, one which does not include any
1998 automodification of the base register. Unlike @samp{m}, this constraint
1999 can be used in @code{asm} statements that might access the operand
2000 several times, or that might not access it at all.
2003 Memory operand that is an offset from a register (it is usually better
2004 to use @samp{m} or @samp{es} in @code{asm} statements)
2007 Memory operand that is an indexed or indirect from a register (it is
2008 usually better to use @samp{m} or @samp{es} in @code{asm} statements)
2014 Address operand that is an indexed or indirect from a register (@samp{p} is
2015 preferable for @code{asm} statements)
2018 Constant suitable as a 64-bit mask operand
2021 Constant suitable as a 32-bit mask operand
2024 System V Release 4 small data area reference
2027 AND masks that can be performed by two rldic@{l, r@} instructions
2030 Vector constant that does not require memory
2034 @item Intel 386---@file{config/i386/constraints.md}
2037 Legacy register---the eight integer registers available on all
2038 i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
2039 @code{si}, @code{di}, @code{bp}, @code{sp}).
2042 Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a},
2043 @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.
2046 Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
2047 @code{c}, and @code{d}.
2051 Any register that can be used as the index in a base+index memory
2052 access: that is, any general register except the stack pointer.
2056 The @code{a} register.
2059 The @code{b} register.
2062 The @code{c} register.
2065 The @code{d} register.
2068 The @code{si} register.
2071 The @code{di} register.
2074 The @code{a} and @code{d} registers, as a pair (for instructions that
2075 return half the result in one and half in the other).
2078 Any 80387 floating-point (stack) register.
2081 Top of 80387 floating-point stack (@code{%st(0)}).
2084 Second from top of 80387 floating-point stack (@code{%st(1)}).
2093 First SSE register (@code{%xmm0}).
2097 Any SSE register, when SSE2 is enabled.
2100 Any SSE register, when SSE2 and inter-unit moves are enabled.
2103 Any MMX register, when inter-unit moves are enabled.
2107 Integer constant in the range 0 @dots{} 31, for 32-bit shifts.
2110 Integer constant in the range 0 @dots{} 63, for 64-bit shifts.
2113 Signed 8-bit integer constant.
2116 @code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move.
2119 0, 1, 2, or 3 (shifts for the @code{lea} instruction).
2122 Unsigned 8-bit integer constant (for @code{in} and @code{out}
2127 Integer constant in the range 0 @dots{} 127, for 128-bit shifts.
2131 Standard 80387 floating point constant.
2134 Standard SSE floating point constant.
2137 32-bit signed integer constant, or a symbolic reference known
2138 to fit that range (for immediate operands in sign-extending x86-64
2142 32-bit unsigned integer constant, or a symbolic reference known
2143 to fit that range (for immediate operands in zero-extending x86-64
2148 @item Intel IA-64---@file{config/ia64/ia64.h}
2151 General register @code{r0} to @code{r3} for @code{addl} instruction
2157 Predicate register (@samp{c} as in ``conditional'')
2160 Application register residing in M-unit
2163 Application register residing in I-unit
2166 Floating-point register
2170 Remember that @samp{m} allows postincrement and postdecrement which
2171 require printing with @samp{%Pn} on IA-64.
2172 Use @samp{S} to disallow postincrement and postdecrement.
2175 Floating-point constant 0.0 or 1.0
2178 14-bit signed integer constant
2181 22-bit signed integer constant
2184 8-bit signed integer constant for logical instructions
2187 8-bit adjusted signed integer constant for compare pseudo-ops
2190 6-bit unsigned integer constant for shift counts
2193 9-bit signed integer constant for load and store postincrements
2199 0 or @minus{}1 for @code{dep} instruction
2202 Non-volatile memory for floating-point loads and stores
2205 Integer constant in the range 1 to 4 for @code{shladd} instruction
2208 Memory operand except postincrement and postdecrement
2211 @item FRV---@file{config/frv/frv.h}
2214 Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}).
2217 Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}).
2220 Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and
2221 @code{icc0} to @code{icc3}).
2224 Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}).
2227 Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}).
2228 Odd registers are excluded not in the class but through the use of a machine
2229 mode larger than 4 bytes.
2232 Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}).
2235 Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}).
2236 Odd registers are excluded not in the class but through the use of a machine
2237 mode larger than 4 bytes.
2240 Register in the class @code{LR_REG} (the @code{lr} register).
2243 Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}).
2244 Register numbers not divisible by 4 are excluded not in the class but through
2245 the use of a machine mode larger than 8 bytes.
2248 Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}).
2251 Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}).
2254 Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}).
2257 Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}).
2260 Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}).
2261 Register numbers not divisible by 4 are excluded not in the class but through
2262 the use of a machine mode larger than 8 bytes.
2265 Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}).
2268 Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}).
2271 Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}).
2274 Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}).
2277 Floating point constant zero
2280 6-bit signed integer constant
2283 10-bit signed integer constant
2286 16-bit signed integer constant
2289 16-bit unsigned integer constant
2292 12-bit signed integer constant that is negative---i.e.@: in the
2293 range of @minus{}2048 to @minus{}1
2299 12-bit signed integer constant that is greater than zero---i.e.@: in the
2304 @item Blackfin family---@file{config/bfin/constraints.md}
2313 A call clobbered P register.
2316 A single register. If @var{n} is in the range 0 to 7, the corresponding D
2317 register. If it is @code{A}, then the register P0.
2320 Even-numbered D register
2323 Odd-numbered D register
2326 Accumulator register.
2329 Even-numbered accumulator register.
2332 Odd-numbered accumulator register.
2344 Registers used for circular buffering, i.e. I, B, or L registers.
2359 Any D, P, B, M, I or L register.
2362 Additional registers typically used only in prologues and epilogues: RETS,
2363 RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.
2366 Any register except accumulators or CC.
2369 Signed 16 bit integer (in the range -32768 to 32767)
2372 Unsigned 16 bit integer (in the range 0 to 65535)
2375 Signed 7 bit integer (in the range -64 to 63)
2378 Unsigned 7 bit integer (in the range 0 to 127)
2381 Unsigned 5 bit integer (in the range 0 to 31)
2384 Signed 4 bit integer (in the range -8 to 7)
2387 Signed 3 bit integer (in the range -3 to 4)
2390 Unsigned 3 bit integer (in the range 0 to 7)
2393 Constant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4.
2396 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2397 use with either accumulator.
2400 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2401 use only with accumulator A1.
2410 An integer constant with exactly a single bit set.
2413 An integer constant with all bits set except exactly one.
2421 @item M32C---@file{config/m32c/m32c.c}
2426 @samp{$sp}, @samp{$fb}, @samp{$sb}.
2429 Any control register, when they're 16 bits wide (nothing if control
2430 registers are 24 bits wide)
2433 Any control register, when they're 24 bits wide.
2442 $r0 or $r2, or $r2r0 for 32 bit values.
2445 $r1 or $r3, or $r3r1 for 32 bit values.
2448 A register that can hold a 64 bit value.
2451 $r0 or $r1 (registers with addressable high/low bytes)
2460 Address registers when they're 16 bits wide.
2463 Address registers when they're 24 bits wide.
2466 Registers that can hold QI values.
2469 Registers that can be used with displacements ($a0, $a1, $sb).
2472 Registers that can hold 32 bit values.
2475 Registers that can hold 16 bit values.
2478 Registers chat can hold 16 bit values, including all control
2482 $r0 through R1, plus $a0 and $a1.
2488 The memory-based pseudo-registers $mem0 through $mem15.
2491 Registers that can hold pointers (16 bit registers for r8c, m16c; 24
2492 bit registers for m32cm, m32c).
2495 Matches multiple registers in a PARALLEL to form a larger register.
2496 Used to match function return values.
2505 -32768 @dots{} 32767
2511 -8 @dots{} -1 or 1 @dots{} 8
2514 -16 @dots{} -1 or 1 @dots{} 16
2517 -32 @dots{} -1 or 1 @dots{} 32
2523 An 8 bit value with exactly one bit set.
2526 A 16 bit value with exactly one bit set.
2529 The common src/dest memory addressing modes.
2532 Memory addressed using $a0 or $a1.
2535 Memory addressed with immediate addresses.
2538 Memory addressed using the stack pointer ($sp).
2541 Memory addressed using the frame base register ($fb).
2544 Memory addressed using the small base register ($sb).
2550 @item MeP---@file{config/mep/constraints.md}
2560 Any control register.
2563 Either the $hi or the $lo register.
2566 Coprocessor registers that can be directly loaded ($c0-$c15).
2569 Coprocessor registers that can be moved to each other.
2572 Coprocessor registers that can be moved to core registers.
2584 Registers which can be used in $tp-relative addressing.
2590 The coprocessor registers.
2593 The coprocessor control registers.
2599 User-defined register set A.
2602 User-defined register set B.
2605 User-defined register set C.
2608 User-defined register set D.
2611 Offsets for $gp-rel addressing.
2614 Constants that can be used directly with boolean insns.
2617 Constants that can be moved directly to registers.
2620 Small constants that can be added to registers.
2626 Small constants that can be compared to registers.
2629 Constants that can be loaded into the top half of registers.
2632 Signed 8-bit immediates.
2635 Symbols encoded for $tp-rel or $gp-rel addressing.
2638 Non-constant addresses for loading/saving coprocessor registers.
2641 The top half of a symbol's value.
2644 A register indirect address without offset.
2647 Symbolic references to the control bus.
2653 @item MIPS---@file{config/mips/constraints.md}
2656 An address register. This is equivalent to @code{r} unless
2657 generating MIPS16 code.
2660 A floating-point register (if available).
2663 Formerly the @code{hi} register. This constraint is no longer supported.
2666 The @code{lo} register. Use this register to store values that are
2667 no bigger than a word.
2670 The concatenated @code{hi} and @code{lo} registers. Use this register
2671 to store doubleword values.
2674 A register suitable for use in an indirect jump. This will always be
2675 @code{$25} for @option{-mabicalls}.
2678 Register @code{$3}. Do not use this constraint in new code;
2679 it is retained only for compatibility with glibc.
2682 Equivalent to @code{r}; retained for backwards compatibility.
2685 A floating-point condition code register.
2688 A signed 16-bit constant (for arithmetic instructions).
2694 An unsigned 16-bit constant (for logic instructions).
2697 A signed 32-bit constant in which the lower 16 bits are zero.
2698 Such constants can be loaded using @code{lui}.
2701 A constant that cannot be loaded using @code{lui}, @code{addiu}
2705 A constant in the range -65535 to -1 (inclusive).
2708 A signed 15-bit constant.
2711 A constant in the range 1 to 65535 (inclusive).
2714 Floating-point zero.
2717 An address that can be used in a non-macro load or store.
2720 @item Motorola 680x0---@file{config/m68k/constraints.md}
2729 68881 floating-point register, if available
2732 Integer in the range 1 to 8
2735 16-bit signed number
2738 Signed number whose magnitude is greater than 0x80
2741 Integer in the range @minus{}8 to @minus{}1
2744 Signed number whose magnitude is greater than 0x100
2747 Range 24 to 31, rotatert:SI 8 to 1 expressed as rotate
2750 16 (for rotate using swap)
2753 Range 8 to 15, rotatert:HI 8 to 1 expressed as rotate
2756 Numbers that mov3q can handle
2759 Floating point constant that is not a 68881 constant
2762 Operands that satisfy 'm' when -mpcrel is in effect
2765 Operands that satisfy 's' when -mpcrel is not in effect
2768 Address register indirect addressing mode
2771 Register offset addressing
2786 Range of signed numbers that don't fit in 16 bits
2789 Integers valid for mvq
2792 Integers valid for a moveq followed by a swap
2795 Integers valid for mvz
2798 Integers valid for mvs
2804 Non-register operands allowed in clr
2808 @item Motorola 68HC11 & 68HC12 families---@file{config/m68hc11/m68hc11.h}
2823 Temporary soft register _.tmp
2826 A soft register _.d1 to _.d31
2829 Stack pointer register
2838 Pseudo register `z' (replaced by `x' or `y' at the end)
2841 An address register: x, y or z
2844 An address register: x or y
2847 Register pair (x:d) to form a 32-bit value
2850 Constants in the range @minus{}65536 to 65535
2853 Constants whose 16-bit low part is zero
2856 Constant integer 1 or @minus{}1
2862 Constants in the range @minus{}8 to 2
2866 @item Moxie---@file{config/moxie/constraints.md}
2875 A register indirect memory operand
2878 A constant in the range of 0 to 255.
2881 A constant in the range of 0 to -255.
2886 @item SPARC---@file{config/sparc/sparc.h}
2889 Floating-point register on the SPARC-V8 architecture and
2890 lower floating-point register on the SPARC-V9 architecture.
2893 Floating-point register. It is equivalent to @samp{f} on the
2894 SPARC-V8 architecture and contains both lower and upper
2895 floating-point registers on the SPARC-V9 architecture.
2898 Floating-point condition code register.
2901 Lower floating-point register. It is only valid on the SPARC-V9
2902 architecture when the Visual Instruction Set is available.
2905 Floating-point register. It is only valid on the SPARC-V9 architecture
2906 when the Visual Instruction Set is available.
2909 64-bit global or out register for the SPARC-V8+ architecture.
2915 Signed 13-bit constant
2921 32-bit constant with the low 12 bits clear (a constant that can be
2922 loaded with the @code{sethi} instruction)
2925 A constant in the range supported by @code{movcc} instructions
2928 A constant in the range supported by @code{movrcc} instructions
2931 Same as @samp{K}, except that it verifies that bits that are not in the
2932 lower 32-bit range are all zero. Must be used instead of @samp{K} for
2933 modes wider than @code{SImode}
2942 Signed 13-bit constant, sign-extended to 32 or 64 bits
2945 Floating-point constant whose integral representation can
2946 be moved into an integer register using a single sethi
2950 Floating-point constant whose integral representation can
2951 be moved into an integer register using a single mov
2955 Floating-point constant whose integral representation can
2956 be moved into an integer register using a high/lo_sum
2957 instruction sequence
2960 Memory address aligned to an 8-byte boundary
2966 Memory address for @samp{e} constraint registers
2973 @item SPU---@file{config/spu/spu.h}
2976 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value.
2979 An immediate for and/xor/or instructions. const_int is treated as a 64 bit value.
2982 An immediate for the @code{iohl} instruction. const_int is treated as a 64 bit value.
2985 An immediate which can be loaded with @code{fsmbi}.
2988 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value.
2991 An immediate for most arithmetic instructions. const_int is treated as a 32 bit value.
2994 An immediate for and/xor/or instructions. const_int is treated as a 32 bit value.
2997 An immediate for the @code{iohl} instruction. const_int is treated as a 32 bit value.
3000 A constant in the range [-64, 63] for shift/rotate instructions.
3003 An unsigned 7-bit constant for conversion/nop/channel instructions.
3006 A signed 10-bit constant for most arithmetic instructions.
3009 A signed 16 bit immediate for @code{stop}.
3012 An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}.
3015 An unsigned 7-bit constant whose 3 least significant bits are 0.
3018 An unsigned 3-bit constant for 16-byte rotates and shifts
3021 Call operand, reg, for indirect calls
3024 Call operand, symbol, for relative calls.
3027 Call operand, const_int, for absolute calls.
3030 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit.
3033 An immediate for shift and rotate instructions. const_int is treated as a 32 bit value.
3036 An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit.
3039 An immediate for the @code{iohl} instruction. const_int is sign extended to 128 bit.
3043 @item S/390 and zSeries---@file{config/s390/s390.h}
3046 Address register (general purpose register except r0)
3049 Condition code register
3052 Data register (arbitrary general purpose register)
3055 Floating-point register
3058 Unsigned 8-bit constant (0--255)
3061 Unsigned 12-bit constant (0--4095)
3064 Signed 16-bit constant (@minus{}32768--32767)
3067 Value appropriate as displacement.
3070 for short displacement
3071 @item (-524288..524287)
3072 for long displacement
3076 Constant integer with a value of 0x7fffffff.
3079 Multiple letter constraint followed by 4 parameter letters.
3082 number of the part counting from most to least significant
3086 mode of the containing operand
3088 value of the other parts (F---all bits set)
3090 The constraint matches if the specified part of a constant
3091 has a value different from its other parts.
3094 Memory reference without index register and with short displacement.
3097 Memory reference with index register and short displacement.
3100 Memory reference without index register but with long displacement.
3103 Memory reference with index register and long displacement.
3106 Pointer with short displacement.
3109 Pointer with long displacement.
3112 Shift count operand.
3116 @item Score family---@file{config/score/score.h}
3119 Registers from r0 to r32.
3122 Registers from r0 to r16.
3125 r8---r11 or r22---r27 registers.
3146 cnt + lcb + scb register.
3149 cr0---cr15 register.
3161 cp1 + cp2 + cp3 registers.
3164 High 16-bit constant (32-bit constant with 16 LSBs zero).
3167 Unsigned 5 bit integer (in the range 0 to 31).
3170 Unsigned 16 bit integer (in the range 0 to 65535).
3173 Signed 16 bit integer (in the range @minus{}32768 to 32767).
3176 Unsigned 14 bit integer (in the range 0 to 16383).
3179 Signed 14 bit integer (in the range @minus{}8192 to 8191).
3185 @item Xstormy16---@file{config/stormy16/stormy16.h}
3200 Registers r0 through r7.
3203 Registers r0 and r1.
3209 Registers r8 and r9.
3212 A constant between 0 and 3 inclusive.
3215 A constant that has exactly one bit set.
3218 A constant that has exactly one bit clear.
3221 A constant between 0 and 255 inclusive.
3224 A constant between @minus{}255 and 0 inclusive.
3227 A constant between @minus{}3 and 0 inclusive.
3230 A constant between 1 and 4 inclusive.
3233 A constant between @minus{}4 and @minus{}1 inclusive.
3236 A memory reference that is a stack push.
3239 A memory reference that is a stack pop.
3242 A memory reference that refers to a constant address of known value.
3245 The register indicated by Rx (not implemented yet).
3248 A constant that is not between 2 and 15 inclusive.
3255 @item Xtensa---@file{config/xtensa/constraints.md}
3258 General-purpose 32-bit register
3261 One-bit boolean register
3264 MAC16 40-bit accumulator register
3267 Signed 12-bit integer constant, for use in MOVI instructions
3270 Signed 8-bit integer constant, for use in ADDI instructions
3273 Integer constant valid for BccI instructions
3276 Unsigned constant valid for BccUI instructions
3283 @node Disable Insn Alternatives
3284 @subsection Disable insn alternatives using the @code{enabled} attribute
3287 The @code{enabled} insn attribute may be used to disable certain insn
3288 alternatives for machine-specific reasons. This is useful when adding
3289 new instructions to an existing pattern which are only available for
3290 certain cpu architecture levels as specified with the @code{-march=}
3293 If an insn alternative is disabled, then it will never be used. The
3294 compiler treats the constraints for the disabled alternative as
3297 In order to make use of the @code{enabled} attribute a back end has to add
3298 in the machine description files:
3302 A definition of the @code{enabled} insn attribute. The attribute is
3303 defined as usual using the @code{define_attr} command. This
3304 definition should be based on other insn attributes and/or target flags.
3305 The @code{enabled} attribute is a numeric attribute and should evaluate to
3306 @code{(const_int 1)} for an enabled alternative and to
3307 @code{(const_int 0)} otherwise.
3309 A definition of another insn attribute used to describe for what
3310 reason an insn alternative might be available or
3311 not. E.g. @code{cpu_facility} as in the example below.
3313 An assignment for the second attribute to each insn definition
3314 combining instructions which are not all available under the same
3315 circumstances. (Note: It obviously only makes sense for definitions
3316 with more than one alternative. Otherwise the insn pattern should be
3317 disabled or enabled using the insn condition.)
3320 E.g. the following two patterns could easily be merged using the @code{enabled}
3325 (define_insn "*movdi_old"
3326 [(set (match_operand:DI 0 "register_operand" "=d")
3327 (match_operand:DI 1 "register_operand" " d"))]
3331 (define_insn "*movdi_new"
3332 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
3333 (match_operand:DI 1 "register_operand" " d,d,f"))]
3346 (define_insn "*movdi_combined"
3347 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
3348 (match_operand:DI 1 "register_operand" " d,d,f"))]
3354 [(set_attr "cpu_facility" "*,new,new")])
3358 with the @code{enabled} attribute defined like this:
3362 (define_attr "cpu_facility" "standard,new" (const_string "standard"))
3364 (define_attr "enabled" ""
3365 (cond [(eq_attr "cpu_facility" "standard") (const_int 1)
3366 (and (eq_attr "cpu_facility" "new")
3367 (ne (symbol_ref "TARGET_NEW") (const_int 0)))
3376 @node Define Constraints
3377 @subsection Defining Machine-Specific Constraints
3378 @cindex defining constraints
3379 @cindex constraints, defining
3381 Machine-specific constraints fall into two categories: register and
3382 non-register constraints. Within the latter category, constraints
3383 which allow subsets of all possible memory or address operands should
3384 be specially marked, to give @code{reload} more information.
3386 Machine-specific constraints can be given names of arbitrary length,
3387 but they must be entirely composed of letters, digits, underscores
3388 (@samp{_}), and angle brackets (@samp{< >}). Like C identifiers, they
3389 must begin with a letter or underscore.
3391 In order to avoid ambiguity in operand constraint strings, no
3392 constraint can have a name that begins with any other constraint's
3393 name. For example, if @code{x} is defined as a constraint name,
3394 @code{xy} may not be, and vice versa. As a consequence of this rule,
3395 no constraint may begin with one of the generic constraint letters:
3396 @samp{E F V X g i m n o p r s}.
3398 Register constraints correspond directly to register classes.
3399 @xref{Register Classes}. There is thus not much flexibility in their
3402 @deffn {MD Expression} define_register_constraint name regclass docstring
3403 All three arguments are string constants.
3404 @var{name} is the name of the constraint, as it will appear in
3405 @code{match_operand} expressions. If @var{name} is a multi-letter
3406 constraint its length shall be the same for all constraints starting
3407 with the same letter. @var{regclass} can be either the
3408 name of the corresponding register class (@pxref{Register Classes}),
3409 or a C expression which evaluates to the appropriate register class.
3410 If it is an expression, it must have no side effects, and it cannot
3411 look at the operand. The usual use of expressions is to map some
3412 register constraints to @code{NO_REGS} when the register class
3413 is not available on a given subarchitecture.
3415 @var{docstring} is a sentence documenting the meaning of the
3416 constraint. Docstrings are explained further below.
3419 Non-register constraints are more like predicates: the constraint
3420 definition gives a Boolean expression which indicates whether the
3423 @deffn {MD Expression} define_constraint name docstring exp
3424 The @var{name} and @var{docstring} arguments are the same as for
3425 @code{define_register_constraint}, but note that the docstring comes
3426 immediately after the name for these expressions. @var{exp} is an RTL
3427 expression, obeying the same rules as the RTL expressions in predicate
3428 definitions. @xref{Defining Predicates}, for details. If it
3429 evaluates true, the constraint matches; if it evaluates false, it
3430 doesn't. Constraint expressions should indicate which RTL codes they
3431 might match, just like predicate expressions.
3433 @code{match_test} C expressions have access to the
3434 following variables:
3438 The RTL object defining the operand.
3440 The machine mode of @var{op}.
3442 @samp{INTVAL (@var{op})}, if @var{op} is a @code{const_int}.
3444 @samp{CONST_DOUBLE_HIGH (@var{op})}, if @var{op} is an integer
3445 @code{const_double}.
3447 @samp{CONST_DOUBLE_LOW (@var{op})}, if @var{op} is an integer
3448 @code{const_double}.
3450 @samp{CONST_DOUBLE_REAL_VALUE (@var{op})}, if @var{op} is a floating-point
3451 @code{const_double}.
3454 The @var{*val} variables should only be used once another piece of the
3455 expression has verified that @var{op} is the appropriate kind of RTL
3459 Most non-register constraints should be defined with
3460 @code{define_constraint}. The remaining two definition expressions
3461 are only appropriate for constraints that should be handled specially
3462 by @code{reload} if they fail to match.
3464 @deffn {MD Expression} define_memory_constraint name docstring exp
3465 Use this expression for constraints that match a subset of all memory
3466 operands: that is, @code{reload} can make them match by converting the
3467 operand to the form @samp{@w{(mem (reg @var{X}))}}, where @var{X} is a
3468 base register (from the register class specified by
3469 @code{BASE_REG_CLASS}, @pxref{Register Classes}).
3471 For example, on the S/390, some instructions do not accept arbitrary
3472 memory references, but only those that do not make use of an index
3473 register. The constraint letter @samp{Q} is defined to represent a
3474 memory address of this type. If @samp{Q} is defined with
3475 @code{define_memory_constraint}, a @samp{Q} constraint can handle any
3476 memory operand, because @code{reload} knows it can simply copy the
3477 memory address into a base register if required. This is analogous to
3478 the way an @samp{o} constraint can handle any memory operand.
3480 The syntax and semantics are otherwise identical to
3481 @code{define_constraint}.
3484 @deffn {MD Expression} define_address_constraint name docstring exp
3485 Use this expression for constraints that match a subset of all address
3486 operands: that is, @code{reload} can make the constraint match by
3487 converting the operand to the form @samp{@w{(reg @var{X})}}, again
3488 with @var{X} a base register.
3490 Constraints defined with @code{define_address_constraint} can only be
3491 used with the @code{address_operand} predicate, or machine-specific
3492 predicates that work the same way. They are treated analogously to
3493 the generic @samp{p} constraint.
3495 The syntax and semantics are otherwise identical to
3496 @code{define_constraint}.
3499 For historical reasons, names beginning with the letters @samp{G H}
3500 are reserved for constraints that match only @code{const_double}s, and
3501 names beginning with the letters @samp{I J K L M N O P} are reserved
3502 for constraints that match only @code{const_int}s. This may change in
3503 the future. For the time being, constraints with these names must be
3504 written in a stylized form, so that @code{genpreds} can tell you did
3509 (define_constraint "[@var{GHIJKLMNOP}]@dots{}"
3511 (and (match_code "const_int") ; @r{@code{const_double} for G/H}
3512 @var{condition}@dots{})) ; @r{usually a @code{match_test}}
3515 @c the semicolons line up in the formatted manual
3517 It is fine to use names beginning with other letters for constraints
3518 that match @code{const_double}s or @code{const_int}s.
3520 Each docstring in a constraint definition should be one or more complete
3521 sentences, marked up in Texinfo format. @emph{They are currently unused.}
3522 In the future they will be copied into the GCC manual, in @ref{Machine
3523 Constraints}, replacing the hand-maintained tables currently found in
3524 that section. Also, in the future the compiler may use this to give
3525 more helpful diagnostics when poor choice of @code{asm} constraints
3526 causes a reload failure.
3528 If you put the pseudo-Texinfo directive @samp{@@internal} at the
3529 beginning of a docstring, then (in the future) it will appear only in
3530 the internals manual's version of the machine-specific constraint tables.
3531 Use this for constraints that should not appear in @code{asm} statements.
3533 @node C Constraint Interface
3534 @subsection Testing constraints from C
3535 @cindex testing constraints
3536 @cindex constraints, testing
3538 It is occasionally useful to test a constraint from C code rather than
3539 implicitly via the constraint string in a @code{match_operand}. The
3540 generated file @file{tm_p.h} declares a few interfaces for working
3541 with machine-specific constraints. None of these interfaces work with
3542 the generic constraints described in @ref{Simple Constraints}. This
3543 may change in the future.
3545 @strong{Warning:} @file{tm_p.h} may declare other functions that
3546 operate on constraints, besides the ones documented here. Do not use
3547 those functions from machine-dependent code. They exist to implement
3548 the old constraint interface that machine-independent components of
3549 the compiler still expect. They will change or disappear in the
3552 Some valid constraint names are not valid C identifiers, so there is a
3553 mangling scheme for referring to them from C@. Constraint names that
3554 do not contain angle brackets or underscores are left unchanged.
3555 Underscores are doubled, each @samp{<} is replaced with @samp{_l}, and
3556 each @samp{>} with @samp{_g}. Here are some examples:
3558 @c the @c's prevent double blank lines in the printed manual.
3560 @multitable {Original} {Mangled}
3561 @item @strong{Original} @tab @strong{Mangled} @c
3562 @item @code{x} @tab @code{x} @c
3563 @item @code{P42x} @tab @code{P42x} @c
3564 @item @code{P4_x} @tab @code{P4__x} @c
3565 @item @code{P4>x} @tab @code{P4_gx} @c
3566 @item @code{P4>>} @tab @code{P4_g_g} @c
3567 @item @code{P4_g>} @tab @code{P4__g_g} @c
3571 Throughout this section, the variable @var{c} is either a constraint
3572 in the abstract sense, or a constant from @code{enum constraint_num};
3573 the variable @var{m} is a mangled constraint name (usually as part of
3574 a larger identifier).
3576 @deftp Enum constraint_num
3577 For each machine-specific constraint, there is a corresponding
3578 enumeration constant: @samp{CONSTRAINT_} plus the mangled name of the
3579 constraint. Functions that take an @code{enum constraint_num} as an
3580 argument expect one of these constants.
3582 Machine-independent constraints do not have associated constants.
3583 This may change in the future.
3586 @deftypefun {inline bool} satisfies_constraint_@var{m} (rtx @var{exp})
3587 For each machine-specific, non-register constraint @var{m}, there is
3588 one of these functions; it returns @code{true} if @var{exp} satisfies the
3589 constraint. These functions are only visible if @file{rtl.h} was included
3590 before @file{tm_p.h}.
3593 @deftypefun bool constraint_satisfied_p (rtx @var{exp}, enum constraint_num @var{c})
3594 Like the @code{satisfies_constraint_@var{m}} functions, but the
3595 constraint to test is given as an argument, @var{c}. If @var{c}
3596 specifies a register constraint, this function will always return
3600 @deftypefun {enum reg_class} regclass_for_constraint (enum constraint_num @var{c})
3601 Returns the register class associated with @var{c}. If @var{c} is not
3602 a register constraint, or those registers are not available for the
3603 currently selected subtarget, returns @code{NO_REGS}.
3606 Here is an example use of @code{satisfies_constraint_@var{m}}. In
3607 peephole optimizations (@pxref{Peephole Definitions}), operand
3608 constraint strings are ignored, so if there are relevant constraints,
3609 they must be tested in the C condition. In the example, the
3610 optimization is applied if operand 2 does @emph{not} satisfy the
3611 @samp{K} constraint. (This is a simplified version of a peephole
3612 definition from the i386 machine description.)
3616 [(match_scratch:SI 3 "r")
3617 (set (match_operand:SI 0 "register_operand" "")
3618 (mult:SI (match_operand:SI 1 "memory_operand" "")
3619 (match_operand:SI 2 "immediate_operand" "")))]
3621 "!satisfies_constraint_K (operands[2])"
3623 [(set (match_dup 3) (match_dup 1))
3624 (set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))]
3629 @node Standard Names
3630 @section Standard Pattern Names For Generation
3631 @cindex standard pattern names
3632 @cindex pattern names
3633 @cindex names, pattern
3635 Here is a table of the instruction names that are meaningful in the RTL
3636 generation pass of the compiler. Giving one of these names to an
3637 instruction pattern tells the RTL generation pass that it can use the
3638 pattern to accomplish a certain task.
3641 @cindex @code{mov@var{m}} instruction pattern
3642 @item @samp{mov@var{m}}
3643 Here @var{m} stands for a two-letter machine mode name, in lowercase.
3644 This instruction pattern moves data with that machine mode from operand
3645 1 to operand 0. For example, @samp{movsi} moves full-word data.
3647 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
3648 own mode is wider than @var{m}, the effect of this instruction is
3649 to store the specified value in the part of the register that corresponds
3650 to mode @var{m}. Bits outside of @var{m}, but which are within the
3651 same target word as the @code{subreg} are undefined. Bits which are
3652 outside the target word are left unchanged.
3654 This class of patterns is special in several ways. First of all, each
3655 of these names up to and including full word size @emph{must} be defined,
3656 because there is no other way to copy a datum from one place to another.
3657 If there are patterns accepting operands in larger modes,
3658 @samp{mov@var{m}} must be defined for integer modes of those sizes.
3660 Second, these patterns are not used solely in the RTL generation pass.
3661 Even the reload pass can generate move insns to copy values from stack
3662 slots into temporary registers. When it does so, one of the operands is
3663 a hard register and the other is an operand that can need to be reloaded
3667 Therefore, when given such a pair of operands, the pattern must generate
3668 RTL which needs no reloading and needs no temporary registers---no
3669 registers other than the operands. For example, if you support the
3670 pattern with a @code{define_expand}, then in such a case the
3671 @code{define_expand} mustn't call @code{force_reg} or any other such
3672 function which might generate new pseudo registers.
3674 This requirement exists even for subword modes on a RISC machine where
3675 fetching those modes from memory normally requires several insns and
3676 some temporary registers.
3678 @findex change_address
3679 During reload a memory reference with an invalid address may be passed
3680 as an operand. Such an address will be replaced with a valid address
3681 later in the reload pass. In this case, nothing may be done with the
3682 address except to use it as it stands. If it is copied, it will not be
3683 replaced with a valid address. No attempt should be made to make such
3684 an address into a valid address and no routine (such as
3685 @code{change_address}) that will do so may be called. Note that
3686 @code{general_operand} will fail when applied to such an address.
3688 @findex reload_in_progress
3689 The global variable @code{reload_in_progress} (which must be explicitly
3690 declared if required) can be used to determine whether such special
3691 handling is required.
3693 The variety of operands that have reloads depends on the rest of the
3694 machine description, but typically on a RISC machine these can only be
3695 pseudo registers that did not get hard registers, while on other
3696 machines explicit memory references will get optional reloads.
3698 If a scratch register is required to move an object to or from memory,
3699 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
3701 If there are cases which need scratch registers during or after reload,
3702 you must provide an appropriate secondary_reload target hook.
3704 @findex can_create_pseudo_p
3705 The macro @code{can_create_pseudo_p} can be used to determine if it
3706 is unsafe to create new pseudo registers. If this variable is nonzero, then
3707 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
3709 The constraints on a @samp{mov@var{m}} must permit moving any hard
3710 register to any other hard register provided that
3711 @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
3712 @code{REGISTER_MOVE_COST} applied to their classes returns a value of 2.
3714 It is obligatory to support floating point @samp{mov@var{m}}
3715 instructions into and out of any registers that can hold fixed point
3716 values, because unions and structures (which have modes @code{SImode} or
3717 @code{DImode}) can be in those registers and they may have floating
3720 There may also be a need to support fixed point @samp{mov@var{m}}
3721 instructions in and out of floating point registers. Unfortunately, I
3722 have forgotten why this was so, and I don't know whether it is still
3723 true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
3724 floating point registers, then the constraints of the fixed point
3725 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
3726 reload into a floating point register.
3728 @cindex @code{reload_in} instruction pattern
3729 @cindex @code{reload_out} instruction pattern
3730 @item @samp{reload_in@var{m}}
3731 @itemx @samp{reload_out@var{m}}
3732 These named patterns have been obsoleted by the target hook
3733 @code{secondary_reload}.
3735 Like @samp{mov@var{m}}, but used when a scratch register is required to
3736 move between operand 0 and operand 1. Operand 2 describes the scratch
3737 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
3738 macro in @pxref{Register Classes}.
3740 There are special restrictions on the form of the @code{match_operand}s
3741 used in these patterns. First, only the predicate for the reload
3742 operand is examined, i.e., @code{reload_in} examines operand 1, but not
3743 the predicates for operand 0 or 2. Second, there may be only one
3744 alternative in the constraints. Third, only a single register class
3745 letter may be used for the constraint; subsequent constraint letters
3746 are ignored. As a special exception, an empty constraint string
3747 matches the @code{ALL_REGS} register class. This may relieve ports
3748 of the burden of defining an @code{ALL_REGS} constraint letter just
3751 @cindex @code{movstrict@var{m}} instruction pattern
3752 @item @samp{movstrict@var{m}}
3753 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
3754 with mode @var{m} of a register whose natural mode is wider,
3755 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
3756 any of the register except the part which belongs to mode @var{m}.
3758 @cindex @code{movmisalign@var{m}} instruction pattern
3759 @item @samp{movmisalign@var{m}}
3760 This variant of a move pattern is designed to load or store a value
3761 from a memory address that is not naturally aligned for its mode.
3762 For a store, the memory will be in operand 0; for a load, the memory
3763 will be in operand 1. The other operand is guaranteed not to be a
3764 memory, so that it's easy to tell whether this is a load or store.
3766 This pattern is used by the autovectorizer, and when expanding a
3767 @code{MISALIGNED_INDIRECT_REF} expression.
3769 @cindex @code{load_multiple} instruction pattern
3770 @item @samp{load_multiple}
3771 Load several consecutive memory locations into consecutive registers.
3772 Operand 0 is the first of the consecutive registers, operand 1
3773 is the first memory location, and operand 2 is a constant: the
3774 number of consecutive registers.
3776 Define this only if the target machine really has such an instruction;
3777 do not define this if the most efficient way of loading consecutive
3778 registers from memory is to do them one at a time.
3780 On some machines, there are restrictions as to which consecutive
3781 registers can be stored into memory, such as particular starting or
3782 ending register numbers or only a range of valid counts. For those
3783 machines, use a @code{define_expand} (@pxref{Expander Definitions})
3784 and make the pattern fail if the restrictions are not met.
3786 Write the generated insn as a @code{parallel} with elements being a
3787 @code{set} of one register from the appropriate memory location (you may
3788 also need @code{use} or @code{clobber} elements). Use a
3789 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
3790 @file{rs6000.md} for examples of the use of this insn pattern.
3792 @cindex @samp{store_multiple} instruction pattern
3793 @item @samp{store_multiple}
3794 Similar to @samp{load_multiple}, but store several consecutive registers
3795 into consecutive memory locations. Operand 0 is the first of the
3796 consecutive memory locations, operand 1 is the first register, and
3797 operand 2 is a constant: the number of consecutive registers.
3799 @cindex @code{vec_set@var{m}} instruction pattern
3800 @item @samp{vec_set@var{m}}
3801 Set given field in the vector value. Operand 0 is the vector to modify,
3802 operand 1 is new value of field and operand 2 specify the field index.
3804 @cindex @code{vec_extract@var{m}} instruction pattern
3805 @item @samp{vec_extract@var{m}}
3806 Extract given field from the vector value. Operand 1 is the vector, operand 2
3807 specify field index and operand 0 place to store value into.
3809 @cindex @code{vec_extract_even@var{m}} instruction pattern
3810 @item @samp{vec_extract_even@var{m}}
3811 Extract even elements from the input vectors (operand 1 and operand 2).
3812 The even elements of operand 2 are concatenated to the even elements of operand
3813 1 in their original order. The result is stored in operand 0.
3814 The output and input vectors should have the same modes.
3816 @cindex @code{vec_extract_odd@var{m}} instruction pattern
3817 @item @samp{vec_extract_odd@var{m}}
3818 Extract odd elements from the input vectors (operand 1 and operand 2).
3819 The odd elements of operand 2 are concatenated to the odd elements of operand
3820 1 in their original order. The result is stored in operand 0.
3821 The output and input vectors should have the same modes.
3823 @cindex @code{vec_interleave_high@var{m}} instruction pattern
3824 @item @samp{vec_interleave_high@var{m}}
3825 Merge high elements of the two input vectors into the output vector. The output
3826 and input vectors should have the same modes (@code{N} elements). The high
3827 @code{N/2} elements of the first input vector are interleaved with the high
3828 @code{N/2} elements of the second input vector.
3830 @cindex @code{vec_interleave_low@var{m}} instruction pattern
3831 @item @samp{vec_interleave_low@var{m}}
3832 Merge low elements of the two input vectors into the output vector. The output
3833 and input vectors should have the same modes (@code{N} elements). The low
3834 @code{N/2} elements of the first input vector are interleaved with the low
3835 @code{N/2} elements of the second input vector.
3837 @cindex @code{vec_init@var{m}} instruction pattern
3838 @item @samp{vec_init@var{m}}
3839 Initialize the vector to given values. Operand 0 is the vector to initialize
3840 and operand 1 is parallel containing values for individual fields.
3842 @cindex @code{push@var{m}1} instruction pattern
3843 @item @samp{push@var{m}1}
3844 Output a push instruction. Operand 0 is value to push. Used only when
3845 @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be
3846 missing and in such case an @code{mov} expander is used instead, with a
3847 @code{MEM} expression forming the push operation. The @code{mov} expander
3848 method is deprecated.
3850 @cindex @code{add@var{m}3} instruction pattern
3851 @item @samp{add@var{m}3}
3852 Add operand 2 and operand 1, storing the result in operand 0. All operands
3853 must have mode @var{m}. This can be used even on two-address machines, by
3854 means of constraints requiring operands 1 and 0 to be the same location.
3856 @cindex @code{ssadd@var{m}3} instruction pattern
3857 @cindex @code{usadd@var{m}3} instruction pattern
3858 @cindex @code{sub@var{m}3} instruction pattern
3859 @cindex @code{sssub@var{m}3} instruction pattern
3860 @cindex @code{ussub@var{m}3} instruction pattern
3861 @cindex @code{mul@var{m}3} instruction pattern
3862 @cindex @code{ssmul@var{m}3} instruction pattern
3863 @cindex @code{usmul@var{m}3} instruction pattern
3864 @cindex @code{div@var{m}3} instruction pattern
3865 @cindex @code{ssdiv@var{m}3} instruction pattern
3866 @cindex @code{udiv@var{m}3} instruction pattern
3867 @cindex @code{usdiv@var{m}3} instruction pattern
3868 @cindex @code{mod@var{m}3} instruction pattern
3869 @cindex @code{umod@var{m}3} instruction pattern
3870 @cindex @code{umin@var{m}3} instruction pattern
3871 @cindex @code{umax@var{m}3} instruction pattern
3872 @cindex @code{and@var{m}3} instruction pattern
3873 @cindex @code{ior@var{m}3} instruction pattern
3874 @cindex @code{xor@var{m}3} instruction pattern
3875 @item @samp{ssadd@var{m}3}, @samp{usadd@var{m}3}
3876 @item @samp{sub@var{m}3}, @samp{sssub@var{m}3}, @samp{ussub@var{m}3}
3877 @item @samp{mul@var{m}3}, @samp{ssmul@var{m}3}, @samp{usmul@var{m}3}
3878 @itemx @samp{div@var{m}3}, @samp{ssdiv@var{m}3}
3879 @itemx @samp{udiv@var{m}3}, @samp{usdiv@var{m}3}
3880 @itemx @samp{mod@var{m}3}, @samp{umod@var{m}3}
3881 @itemx @samp{umin@var{m}3}, @samp{umax@var{m}3}
3882 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
3883 Similar, for other arithmetic operations.
3885 @cindex @code{min@var{m}3} instruction pattern
3886 @cindex @code{max@var{m}3} instruction pattern
3887 @item @samp{smin@var{m}3}, @samp{smax@var{m}3}
3888 Signed minimum and maximum operations. When used with floating point,
3889 if both operands are zeros, or if either operand is @code{NaN}, then
3890 it is unspecified which of the two operands is returned as the result.
3892 @cindex @code{reduc_smin_@var{m}} instruction pattern
3893 @cindex @code{reduc_smax_@var{m}} instruction pattern
3894 @item @samp{reduc_smin_@var{m}}, @samp{reduc_smax_@var{m}}
3895 Find the signed minimum/maximum of the elements of a vector. The vector is
3896 operand 1, and the scalar result is stored in the least significant bits of
3897 operand 0 (also a vector). The output and input vector should have the same
3900 @cindex @code{reduc_umin_@var{m}} instruction pattern
3901 @cindex @code{reduc_umax_@var{m}} instruction pattern
3902 @item @samp{reduc_umin_@var{m}}, @samp{reduc_umax_@var{m}}
3903 Find the unsigned minimum/maximum of the elements of a vector. The vector is
3904 operand 1, and the scalar result is stored in the least significant bits of
3905 operand 0 (also a vector). The output and input vector should have the same
3908 @cindex @code{reduc_splus_@var{m}} instruction pattern
3909 @item @samp{reduc_splus_@var{m}}
3910 Compute the sum of the signed elements of a vector. The vector is operand 1,
3911 and the scalar result is stored in the least significant bits of operand 0
3912 (also a vector). The output and input vector should have the same modes.
3914 @cindex @code{reduc_uplus_@var{m}} instruction pattern
3915 @item @samp{reduc_uplus_@var{m}}
3916 Compute the sum of the unsigned elements of a vector. The vector is operand 1,
3917 and the scalar result is stored in the least significant bits of operand 0
3918 (also a vector). The output and input vector should have the same modes.
3920 @cindex @code{sdot_prod@var{m}} instruction pattern
3921 @item @samp{sdot_prod@var{m}}
3922 @cindex @code{udot_prod@var{m}} instruction pattern
3923 @item @samp{udot_prod@var{m}}
3924 Compute the sum of the products of two signed/unsigned elements.
3925 Operand 1 and operand 2 are of the same mode. Their product, which is of a
3926 wider mode, is computed and added to operand 3. Operand 3 is of a mode equal or
3927 wider than the mode of the product. The result is placed in operand 0, which
3928 is of the same mode as operand 3.
3930 @cindex @code{ssum_widen@var{m3}} instruction pattern
3931 @item @samp{ssum_widen@var{m3}}
3932 @cindex @code{usum_widen@var{m3}} instruction pattern
3933 @item @samp{usum_widen@var{m3}}
3934 Operands 0 and 2 are of the same mode, which is wider than the mode of
3935 operand 1. Add operand 1 to operand 2 and place the widened result in
3936 operand 0. (This is used express accumulation of elements into an accumulator
3939 @cindex @code{vec_shl_@var{m}} instruction pattern
3940 @cindex @code{vec_shr_@var{m}} instruction pattern
3941 @item @samp{vec_shl_@var{m}}, @samp{vec_shr_@var{m}}
3942 Whole vector left/right shift in bits.
3943 Operand 1 is a vector to be shifted.
3944 Operand 2 is an integer shift amount in bits.
3945 Operand 0 is where the resulting shifted vector is stored.
3946 The output and input vectors should have the same modes.
3948 @cindex @code{vec_pack_trunc_@var{m}} instruction pattern
3949 @item @samp{vec_pack_trunc_@var{m}}
3950 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
3951 are vectors of the same mode having N integral or floating point elements
3952 of size S@. Operand 0 is the resulting vector in which 2*N elements of
3953 size N/2 are concatenated after narrowing them down using truncation.
3955 @cindex @code{vec_pack_ssat_@var{m}} instruction pattern
3956 @cindex @code{vec_pack_usat_@var{m}} instruction pattern
3957 @item @samp{vec_pack_ssat_@var{m}}, @samp{vec_pack_usat_@var{m}}
3958 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
3959 are vectors of the same mode having N integral elements of size S.
3960 Operand 0 is the resulting vector in which the elements of the two input
3961 vectors are concatenated after narrowing them down using signed/unsigned
3962 saturating arithmetic.
3964 @cindex @code{vec_pack_sfix_trunc_@var{m}} instruction pattern
3965 @cindex @code{vec_pack_ufix_trunc_@var{m}} instruction pattern
3966 @item @samp{vec_pack_sfix_trunc_@var{m}}, @samp{vec_pack_ufix_trunc_@var{m}}
3967 Narrow, convert to signed/unsigned integral type and merge the elements
3968 of two vectors. Operands 1 and 2 are vectors of the same mode having N
3969 floating point elements of size S@. Operand 0 is the resulting vector
3970 in which 2*N elements of size N/2 are concatenated.
3972 @cindex @code{vec_unpacks_hi_@var{m}} instruction pattern
3973 @cindex @code{vec_unpacks_lo_@var{m}} instruction pattern
3974 @item @samp{vec_unpacks_hi_@var{m}}, @samp{vec_unpacks_lo_@var{m}}
3975 Extract and widen (promote) the high/low part of a vector of signed
3976 integral or floating point elements. The input vector (operand 1) has N
3977 elements of size S@. Widen (promote) the high/low elements of the vector
3978 using signed or floating point extension and place the resulting N/2
3979 values of size 2*S in the output vector (operand 0).
3981 @cindex @code{vec_unpacku_hi_@var{m}} instruction pattern
3982 @cindex @code{vec_unpacku_lo_@var{m}} instruction pattern
3983 @item @samp{vec_unpacku_hi_@var{m}}, @samp{vec_unpacku_lo_@var{m}}
3984 Extract and widen (promote) the high/low part of a vector of unsigned
3985 integral elements. The input vector (operand 1) has N elements of size S.
3986 Widen (promote) the high/low elements of the vector using zero extension and
3987 place the resulting N/2 values of size 2*S in the output vector (operand 0).
3989 @cindex @code{vec_unpacks_float_hi_@var{m}} instruction pattern
3990 @cindex @code{vec_unpacks_float_lo_@var{m}} instruction pattern
3991 @cindex @code{vec_unpacku_float_hi_@var{m}} instruction pattern
3992 @cindex @code{vec_unpacku_float_lo_@var{m}} instruction pattern
3993 @item @samp{vec_unpacks_float_hi_@var{m}}, @samp{vec_unpacks_float_lo_@var{m}}
3994 @itemx @samp{vec_unpacku_float_hi_@var{m}}, @samp{vec_unpacku_float_lo_@var{m}}
3995 Extract, convert to floating point type and widen the high/low part of a
3996 vector of signed/unsigned integral elements. The input vector (operand 1)
3997 has N elements of size S@. Convert the high/low elements of the vector using
3998 floating point conversion and place the resulting N/2 values of size 2*S in
3999 the output vector (operand 0).
4001 @cindex @code{vec_widen_umult_hi_@var{m}} instruction pattern
4002 @cindex @code{vec_widen_umult_lo__@var{m}} instruction pattern
4003 @cindex @code{vec_widen_smult_hi_@var{m}} instruction pattern
4004 @cindex @code{vec_widen_smult_lo_@var{m}} instruction pattern
4005 @item @samp{vec_widen_umult_hi_@var{m}}, @samp{vec_widen_umult_lo_@var{m}}
4006 @itemx @samp{vec_widen_smult_hi_@var{m}}, @samp{vec_widen_smult_lo_@var{m}}
4007 Signed/Unsigned widening multiplication. The two inputs (operands 1 and 2)
4008 are vectors with N signed/unsigned elements of size S@. Multiply the high/low
4009 elements of the two vectors, and put the N/2 products of size 2*S in the
4010 output vector (operand 0).
4012 @cindex @code{mulhisi3} instruction pattern
4013 @item @samp{mulhisi3}
4014 Multiply operands 1 and 2, which have mode @code{HImode}, and store
4015 a @code{SImode} product in operand 0.
4017 @cindex @code{mulqihi3} instruction pattern
4018 @cindex @code{mulsidi3} instruction pattern
4019 @item @samp{mulqihi3}, @samp{mulsidi3}
4020 Similar widening-multiplication instructions of other widths.
4022 @cindex @code{umulqihi3} instruction pattern
4023 @cindex @code{umulhisi3} instruction pattern
4024 @cindex @code{umulsidi3} instruction pattern
4025 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
4026 Similar widening-multiplication instructions that do unsigned
4029 @cindex @code{usmulqihi3} instruction pattern
4030 @cindex @code{usmulhisi3} instruction pattern
4031 @cindex @code{usmulsidi3} instruction pattern
4032 @item @samp{usmulqihi3}, @samp{usmulhisi3}, @samp{usmulsidi3}
4033 Similar widening-multiplication instructions that interpret the first
4034 operand as unsigned and the second operand as signed, then do a signed
4037 @cindex @code{smul@var{m}3_highpart} instruction pattern
4038 @item @samp{smul@var{m}3_highpart}
4039 Perform a signed multiplication of operands 1 and 2, which have mode
4040 @var{m}, and store the most significant half of the product in operand 0.
4041 The least significant half of the product is discarded.
4043 @cindex @code{umul@var{m}3_highpart} instruction pattern
4044 @item @samp{umul@var{m}3_highpart}
4045 Similar, but the multiplication is unsigned.
4047 @cindex @code{madd@var{m}@var{n}4} instruction pattern
4048 @item @samp{madd@var{m}@var{n}4}
4049 Multiply operands 1 and 2, sign-extend them to mode @var{n}, add
4050 operand 3, and store the result in operand 0. Operands 1 and 2
4051 have mode @var{m} and operands 0 and 3 have mode @var{n}.
4052 Both modes must be integer or fixed-point modes and @var{n} must be twice
4053 the size of @var{m}.
4055 In other words, @code{madd@var{m}@var{n}4} is like
4056 @code{mul@var{m}@var{n}3} except that it also adds operand 3.
4058 These instructions are not allowed to @code{FAIL}.
4060 @cindex @code{umadd@var{m}@var{n}4} instruction pattern
4061 @item @samp{umadd@var{m}@var{n}4}
4062 Like @code{madd@var{m}@var{n}4}, but zero-extend the multiplication
4063 operands instead of sign-extending them.
4065 @cindex @code{ssmadd@var{m}@var{n}4} instruction pattern
4066 @item @samp{ssmadd@var{m}@var{n}4}
4067 Like @code{madd@var{m}@var{n}4}, but all involved operations must be
4070 @cindex @code{usmadd@var{m}@var{n}4} instruction pattern
4071 @item @samp{usmadd@var{m}@var{n}4}
4072 Like @code{umadd@var{m}@var{n}4}, but all involved operations must be
4073 unsigned-saturating.
4075 @cindex @code{msub@var{m}@var{n}4} instruction pattern
4076 @item @samp{msub@var{m}@var{n}4}
4077 Multiply operands 1 and 2, sign-extend them to mode @var{n}, subtract the
4078 result from operand 3, and store the result in operand 0. Operands 1 and 2
4079 have mode @var{m} and operands 0 and 3 have mode @var{n}.
4080 Both modes must be integer or fixed-point modes and @var{n} must be twice
4081 the size of @var{m}.
4083 In other words, @code{msub@var{m}@var{n}4} is like
4084 @code{mul@var{m}@var{n}3} except that it also subtracts the result
4087 These instructions are not allowed to @code{FAIL}.
4089 @cindex @code{umsub@var{m}@var{n}4} instruction pattern
4090 @item @samp{umsub@var{m}@var{n}4}
4091 Like @code{msub@var{m}@var{n}4}, but zero-extend the multiplication
4092 operands instead of sign-extending them.
4094 @cindex @code{ssmsub@var{m}@var{n}4} instruction pattern
4095 @item @samp{ssmsub@var{m}@var{n}4}
4096 Like @code{msub@var{m}@var{n}4}, but all involved operations must be
4099 @cindex @code{usmsub@var{m}@var{n}4} instruction pattern
4100 @item @samp{usmsub@var{m}@var{n}4}
4101 Like @code{umsub@var{m}@var{n}4}, but all involved operations must be
4102 unsigned-saturating.
4104 @cindex @code{divmod@var{m}4} instruction pattern
4105 @item @samp{divmod@var{m}4}
4106 Signed division that produces both a quotient and a remainder.
4107 Operand 1 is divided by operand 2 to produce a quotient stored
4108 in operand 0 and a remainder stored in operand 3.
4110 For machines with an instruction that produces both a quotient and a
4111 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
4112 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
4113 allows optimization in the relatively common case when both the quotient
4114 and remainder are computed.
4116 If an instruction that just produces a quotient or just a remainder
4117 exists and is more efficient than the instruction that produces both,
4118 write the output routine of @samp{divmod@var{m}4} to call
4119 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
4120 quotient or remainder and generate the appropriate instruction.
4122 @cindex @code{udivmod@var{m}4} instruction pattern
4123 @item @samp{udivmod@var{m}4}
4124 Similar, but does unsigned division.
4126 @anchor{shift patterns}
4127 @cindex @code{ashl@var{m}3} instruction pattern
4128 @cindex @code{ssashl@var{m}3} instruction pattern
4129 @cindex @code{usashl@var{m}3} instruction pattern
4130 @item @samp{ashl@var{m}3}, @samp{ssashl@var{m}3}, @samp{usashl@var{m}3}
4131 Arithmetic-shift operand 1 left by a number of bits specified by operand
4132 2, and store the result in operand 0. Here @var{m} is the mode of
4133 operand 0 and operand 1; operand 2's mode is specified by the
4134 instruction pattern, and the compiler will convert the operand to that
4135 mode before generating the instruction. The meaning of out-of-range shift
4136 counts can optionally be specified by @code{TARGET_SHIFT_TRUNCATION_MASK}.
4137 @xref{TARGET_SHIFT_TRUNCATION_MASK}. Operand 2 is always a scalar type.
4139 @cindex @code{ashr@var{m}3} instruction pattern
4140 @cindex @code{lshr@var{m}3} instruction pattern
4141 @cindex @code{rotl@var{m}3} instruction pattern
4142 @cindex @code{rotr@var{m}3} instruction pattern
4143 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
4144 Other shift and rotate instructions, analogous to the
4145 @code{ashl@var{m}3} instructions. Operand 2 is always a scalar type.
4147 @cindex @code{vashl@var{m}3} instruction pattern
4148 @cindex @code{vashr@var{m}3} instruction pattern
4149 @cindex @code{vlshr@var{m}3} instruction pattern
4150 @cindex @code{vrotl@var{m}3} instruction pattern
4151 @cindex @code{vrotr@var{m}3} instruction pattern
4152 @item @samp{vashl@var{m}3}, @samp{vashr@var{m}3}, @samp{vlshr@var{m}3}, @samp{vrotl@var{m}3}, @samp{vrotr@var{m}3}
4153 Vector shift and rotate instructions that take vectors as operand 2
4154 instead of a scalar type.
4156 @cindex @code{neg@var{m}2} instruction pattern
4157 @cindex @code{ssneg@var{m}2} instruction pattern
4158 @cindex @code{usneg@var{m}2} instruction pattern
4159 @item @samp{neg@var{m}2}, @samp{ssneg@var{m}2}, @samp{usneg@var{m}2}
4160 Negate operand 1 and store the result in operand 0.
4162 @cindex @code{abs@var{m}2} instruction pattern
4163 @item @samp{abs@var{m}2}
4164 Store the absolute value of operand 1 into operand 0.
4166 @cindex @code{sqrt@var{m}2} instruction pattern
4167 @item @samp{sqrt@var{m}2}
4168 Store the square root of operand 1 into operand 0.
4170 The @code{sqrt} built-in function of C always uses the mode which
4171 corresponds to the C data type @code{double} and the @code{sqrtf}
4172 built-in function uses the mode which corresponds to the C data
4175 @cindex @code{fmod@var{m}3} instruction pattern
4176 @item @samp{fmod@var{m}3}
4177 Store the remainder of dividing operand 1 by operand 2 into
4178 operand 0, rounded towards zero to an integer.
4180 The @code{fmod} built-in function of C always uses the mode which
4181 corresponds to the C data type @code{double} and the @code{fmodf}
4182 built-in function uses the mode which corresponds to the C data
4185 @cindex @code{remainder@var{m}3} instruction pattern
4186 @item @samp{remainder@var{m}3}
4187 Store the remainder of dividing operand 1 by operand 2 into
4188 operand 0, rounded to the nearest integer.
4190 The @code{remainder} built-in function of C always uses the mode
4191 which corresponds to the C data type @code{double} and the
4192 @code{remainderf} built-in function uses the mode which corresponds
4193 to the C data type @code{float}.
4195 @cindex @code{cos@var{m}2} instruction pattern
4196 @item @samp{cos@var{m}2}
4197 Store the cosine of operand 1 into operand 0.
4199 The @code{cos} built-in function of C always uses the mode which
4200 corresponds to the C data type @code{double} and the @code{cosf}
4201 built-in function uses the mode which corresponds to the C data
4204 @cindex @code{sin@var{m}2} instruction pattern
4205 @item @samp{sin@var{m}2}
4206 Store the sine of operand 1 into operand 0.
4208 The @code{sin} built-in function of C always uses the mode which
4209 corresponds to the C data type @code{double} and the @code{sinf}
4210 built-in function uses the mode which corresponds to the C data
4213 @cindex @code{exp@var{m}2} instruction pattern
4214 @item @samp{exp@var{m}2}
4215 Store the exponential of operand 1 into operand 0.
4217 The @code{exp} built-in function of C always uses the mode which
4218 corresponds to the C data type @code{double} and the @code{expf}
4219 built-in function uses the mode which corresponds to the C data
4222 @cindex @code{log@var{m}2} instruction pattern
4223 @item @samp{log@var{m}2}
4224 Store the natural logarithm of operand 1 into operand 0.
4226 The @code{log} built-in function of C always uses the mode which
4227 corresponds to the C data type @code{double} and the @code{logf}
4228 built-in function uses the mode which corresponds to the C data
4231 @cindex @code{pow@var{m}3} instruction pattern
4232 @item @samp{pow@var{m}3}
4233 Store the value of operand 1 raised to the exponent operand 2
4236 The @code{pow} built-in function of C always uses the mode which
4237 corresponds to the C data type @code{double} and the @code{powf}
4238 built-in function uses the mode which corresponds to the C data
4241 @cindex @code{atan2@var{m}3} instruction pattern
4242 @item @samp{atan2@var{m}3}
4243 Store the arc tangent (inverse tangent) of operand 1 divided by
4244 operand 2 into operand 0, using the signs of both arguments to
4245 determine the quadrant of the result.
4247 The @code{atan2} built-in function of C always uses the mode which
4248 corresponds to the C data type @code{double} and the @code{atan2f}
4249 built-in function uses the mode which corresponds to the C data
4252 @cindex @code{floor@var{m}2} instruction pattern
4253 @item @samp{floor@var{m}2}
4254 Store the largest integral value not greater than argument.
4256 The @code{floor} built-in function of C always uses the mode which
4257 corresponds to the C data type @code{double} and the @code{floorf}
4258 built-in function uses the mode which corresponds to the C data
4261 @cindex @code{btrunc@var{m}2} instruction pattern
4262 @item @samp{btrunc@var{m}2}
4263 Store the argument rounded to integer towards zero.
4265 The @code{trunc} built-in function of C always uses the mode which
4266 corresponds to the C data type @code{double} and the @code{truncf}
4267 built-in function uses the mode which corresponds to the C data
4270 @cindex @code{round@var{m}2} instruction pattern
4271 @item @samp{round@var{m}2}
4272 Store the argument rounded to integer away from zero.
4274 The @code{round} built-in function of C always uses the mode which
4275 corresponds to the C data type @code{double} and the @code{roundf}
4276 built-in function uses the mode which corresponds to the C data
4279 @cindex @code{ceil@var{m}2} instruction pattern
4280 @item @samp{ceil@var{m}2}
4281 Store the argument rounded to integer away from zero.
4283 The @code{ceil} built-in function of C always uses the mode which
4284 corresponds to the C data type @code{double} and the @code{ceilf}
4285 built-in function uses the mode which corresponds to the C data
4288 @cindex @code{nearbyint@var{m}2} instruction pattern
4289 @item @samp{nearbyint@var{m}2}
4290 Store the argument rounded according to the default rounding mode
4292 The @code{nearbyint} built-in function of C always uses the mode which
4293 corresponds to the C data type @code{double} and the @code{nearbyintf}
4294 built-in function uses the mode which corresponds to the C data
4297 @cindex @code{rint@var{m}2} instruction pattern
4298 @item @samp{rint@var{m}2}
4299 Store the argument rounded according to the default rounding mode and
4300 raise the inexact exception when the result differs in value from
4303 The @code{rint} built-in function of C always uses the mode which
4304 corresponds to the C data type @code{double} and the @code{rintf}
4305 built-in function uses the mode which corresponds to the C data
4308 @cindex @code{lrint@var{m}@var{n}2}
4309 @item @samp{lrint@var{m}@var{n}2}
4310 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4311 point mode @var{n} as a signed number according to the current
4312 rounding mode and store in operand 0 (which has mode @var{n}).
4314 @cindex @code{lround@var{m}@var{n}2}
4315 @item @samp{lround@var{m}2}
4316 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4317 point mode @var{n} as a signed number rounding to nearest and away
4318 from zero and store in operand 0 (which has mode @var{n}).
4320 @cindex @code{lfloor@var{m}@var{n}2}
4321 @item @samp{lfloor@var{m}2}
4322 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4323 point mode @var{n} as a signed number rounding down and store in
4324 operand 0 (which has mode @var{n}).
4326 @cindex @code{lceil@var{m}@var{n}2}
4327 @item @samp{lceil@var{m}2}
4328 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4329 point mode @var{n} as a signed number rounding up and store in
4330 operand 0 (which has mode @var{n}).
4332 @cindex @code{copysign@var{m}3} instruction pattern
4333 @item @samp{copysign@var{m}3}
4334 Store a value with the magnitude of operand 1 and the sign of operand
4337 The @code{copysign} built-in function of C always uses the mode which
4338 corresponds to the C data type @code{double} and the @code{copysignf}
4339 built-in function uses the mode which corresponds to the C data
4342 @cindex @code{ffs@var{m}2} instruction pattern
4343 @item @samp{ffs@var{m}2}
4344 Store into operand 0 one plus the index of the least significant 1-bit
4345 of operand 1. If operand 1 is zero, store zero. @var{m} is the mode
4346 of operand 0; operand 1's mode is specified by the instruction
4347 pattern, and the compiler will convert the operand to that mode before
4348 generating the instruction.
4350 The @code{ffs} built-in function of C always uses the mode which
4351 corresponds to the C data type @code{int}.
4353 @cindex @code{clz@var{m}2} instruction pattern
4354 @item @samp{clz@var{m}2}
4355 Store into operand 0 the number of leading 0-bits in @var{x}, starting
4356 at the most significant bit position. If @var{x} is 0, the
4357 @code{CLZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
4358 the result is undefined or has a useful value.
4359 @var{m} is the mode of operand 0; operand 1's mode is
4360 specified by the instruction pattern, and the compiler will convert the
4361 operand to that mode before generating the instruction.
4363 @cindex @code{ctz@var{m}2} instruction pattern
4364 @item @samp{ctz@var{m}2}
4365 Store into operand 0 the number of trailing 0-bits in @var{x}, starting
4366 at the least significant bit position. If @var{x} is 0, the
4367 @code{CTZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
4368 the result is undefined or has a useful value.
4369 @var{m} is the mode of operand 0; operand 1's mode is
4370 specified by the instruction pattern, and the compiler will convert the
4371 operand to that mode before generating the instruction.
4373 @cindex @code{popcount@var{m}2} instruction pattern
4374 @item @samp{popcount@var{m}2}
4375 Store into operand 0 the number of 1-bits in @var{x}. @var{m} is the
4376 mode of operand 0; operand 1's mode is specified by the instruction
4377 pattern, and the compiler will convert the operand to that mode before
4378 generating the instruction.
4380 @cindex @code{parity@var{m}2} instruction pattern
4381 @item @samp{parity@var{m}2}
4382 Store into operand 0 the parity of @var{x}, i.e.@: the number of 1-bits
4383 in @var{x} modulo 2. @var{m} is the mode of operand 0; operand 1's mode
4384 is specified by the instruction pattern, and the compiler will convert
4385 the operand to that mode before generating the instruction.
4387 @cindex @code{one_cmpl@var{m}2} instruction pattern
4388 @item @samp{one_cmpl@var{m}2}
4389 Store the bitwise-complement of operand 1 into operand 0.
4391 @cindex @code{movmem@var{m}} instruction pattern
4392 @item @samp{movmem@var{m}}
4393 Block move instruction. The destination and source blocks of memory
4394 are the first two operands, and both are @code{mem:BLK}s with an
4395 address in mode @code{Pmode}.
4397 The number of bytes to move is the third operand, in mode @var{m}.
4398 Usually, you specify @code{word_mode} for @var{m}. However, if you can
4399 generate better code knowing the range of valid lengths is smaller than
4400 those representable in a full word, you should provide a pattern with a
4401 mode corresponding to the range of values you can handle efficiently
4402 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
4403 that appear negative) and also a pattern with @code{word_mode}.
4405 The fourth operand is the known shared alignment of the source and
4406 destination, in the form of a @code{const_int} rtx. Thus, if the
4407 compiler knows that both source and destination are word-aligned,
4408 it may provide the value 4 for this operand.
4410 Optional operands 5 and 6 specify expected alignment and size of block
4411 respectively. The expected alignment differs from alignment in operand 4
4412 in a way that the blocks are not required to be aligned according to it in
4413 all cases. This expected alignment is also in bytes, just like operand 4.
4414 Expected size, when unknown, is set to @code{(const_int -1)}.
4416 Descriptions of multiple @code{movmem@var{m}} patterns can only be
4417 beneficial if the patterns for smaller modes have fewer restrictions
4418 on their first, second and fourth operands. Note that the mode @var{m}
4419 in @code{movmem@var{m}} does not impose any restriction on the mode of
4420 individually moved data units in the block.
4422 These patterns need not give special consideration to the possibility
4423 that the source and destination strings might overlap.
4425 @cindex @code{movstr} instruction pattern
4427 String copy instruction, with @code{stpcpy} semantics. Operand 0 is
4428 an output operand in mode @code{Pmode}. The addresses of the
4429 destination and source strings are operands 1 and 2, and both are
4430 @code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of
4431 the expansion of this pattern should store in operand 0 the address in
4432 which the @code{NUL} terminator was stored in the destination string.
4434 @cindex @code{setmem@var{m}} instruction pattern
4435 @item @samp{setmem@var{m}}
4436 Block set instruction. The destination string is the first operand,
4437 given as a @code{mem:BLK} whose address is in mode @code{Pmode}. The
4438 number of bytes to set is the second operand, in mode @var{m}. The value to
4439 initialize the memory with is the third operand. Targets that only support the
4440 clearing of memory should reject any value that is not the constant 0. See
4441 @samp{movmem@var{m}} for a discussion of the choice of mode.
4443 The fourth operand is the known alignment of the destination, in the form
4444 of a @code{const_int} rtx. Thus, if the compiler knows that the
4445 destination is word-aligned, it may provide the value 4 for this
4448 Optional operands 5 and 6 specify expected alignment and size of block
4449 respectively. The expected alignment differs from alignment in operand 4
4450 in a way that the blocks are not required to be aligned according to it in
4451 all cases. This expected alignment is also in bytes, just like operand 4.
4452 Expected size, when unknown, is set to @code{(const_int -1)}.
4454 The use for multiple @code{setmem@var{m}} is as for @code{movmem@var{m}}.
4456 @cindex @code{cmpstrn@var{m}} instruction pattern
4457 @item @samp{cmpstrn@var{m}}
4458 String compare instruction, with five operands. Operand 0 is the output;
4459 it has mode @var{m}. The remaining four operands are like the operands
4460 of @samp{movmem@var{m}}. The two memory blocks specified are compared
4461 byte by byte in lexicographic order starting at the beginning of each
4462 string. The instruction is not allowed to prefetch more than one byte
4463 at a time since either string may end in the first byte and reading past
4464 that may access an invalid page or segment and cause a fault. The
4465 effect of the instruction is to store a value in operand 0 whose sign
4466 indicates the result of the comparison.
4468 @cindex @code{cmpstr@var{m}} instruction pattern
4469 @item @samp{cmpstr@var{m}}
4470 String compare instruction, without known maximum length. Operand 0 is the
4471 output; it has mode @var{m}. The second and third operand are the blocks of
4472 memory to be compared; both are @code{mem:BLK} with an address in mode
4475 The fourth operand is the known shared alignment of the source and
4476 destination, in the form of a @code{const_int} rtx. Thus, if the
4477 compiler knows that both source and destination are word-aligned,
4478 it may provide the value 4 for this operand.
4480 The two memory blocks specified are compared byte by byte in lexicographic
4481 order starting at the beginning of each string. The instruction is not allowed
4482 to prefetch more than one byte at a time since either string may end in the
4483 first byte and reading past that may access an invalid page or segment and
4484 cause a fault. The effect of the instruction is to store a value in operand 0
4485 whose sign indicates the result of the comparison.
4487 @cindex @code{cmpmem@var{m}} instruction pattern
4488 @item @samp{cmpmem@var{m}}
4489 Block compare instruction, with five operands like the operands
4490 of @samp{cmpstr@var{m}}. The two memory blocks specified are compared
4491 byte by byte in lexicographic order starting at the beginning of each
4492 block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch
4493 any bytes in the two memory blocks. The effect of the instruction is
4494 to store a value in operand 0 whose sign indicates the result of the
4497 @cindex @code{strlen@var{m}} instruction pattern
4498 @item @samp{strlen@var{m}}
4499 Compute the length of a string, with three operands.
4500 Operand 0 is the result (of mode @var{m}), operand 1 is
4501 a @code{mem} referring to the first character of the string,
4502 operand 2 is the character to search for (normally zero),
4503 and operand 3 is a constant describing the known alignment
4504 of the beginning of the string.
4506 @cindex @code{float@var{mn}2} instruction pattern
4507 @item @samp{float@var{m}@var{n}2}
4508 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
4509 floating point mode @var{n} and store in operand 0 (which has mode
4512 @cindex @code{floatuns@var{mn}2} instruction pattern
4513 @item @samp{floatuns@var{m}@var{n}2}
4514 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
4515 to floating point mode @var{n} and store in operand 0 (which has mode
4518 @cindex @code{fix@var{mn}2} instruction pattern
4519 @item @samp{fix@var{m}@var{n}2}
4520 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4521 point mode @var{n} as a signed number and store in operand 0 (which
4522 has mode @var{n}). This instruction's result is defined only when
4523 the value of operand 1 is an integer.
4525 If the machine description defines this pattern, it also needs to
4526 define the @code{ftrunc} pattern.
4528 @cindex @code{fixuns@var{mn}2} instruction pattern
4529 @item @samp{fixuns@var{m}@var{n}2}
4530 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4531 point mode @var{n} as an unsigned number and store in operand 0 (which
4532 has mode @var{n}). This instruction's result is defined only when the
4533 value of operand 1 is an integer.
4535 @cindex @code{ftrunc@var{m}2} instruction pattern
4536 @item @samp{ftrunc@var{m}2}
4537 Convert operand 1 (valid for floating point mode @var{m}) to an
4538 integer value, still represented in floating point mode @var{m}, and
4539 store it in operand 0 (valid for floating point mode @var{m}).
4541 @cindex @code{fix_trunc@var{mn}2} instruction pattern
4542 @item @samp{fix_trunc@var{m}@var{n}2}
4543 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
4544 of mode @var{m} by converting the value to an integer.
4546 @cindex @code{fixuns_trunc@var{mn}2} instruction pattern
4547 @item @samp{fixuns_trunc@var{m}@var{n}2}
4548 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
4549 value of mode @var{m} by converting the value to an integer.
4551 @cindex @code{trunc@var{mn}2} instruction pattern
4552 @item @samp{trunc@var{m}@var{n}2}
4553 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
4554 store in operand 0 (which has mode @var{n}). Both modes must be fixed
4555 point or both floating point.
4557 @cindex @code{extend@var{mn}2} instruction pattern
4558 @item @samp{extend@var{m}@var{n}2}
4559 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
4560 store in operand 0 (which has mode @var{n}). Both modes must be fixed
4561 point or both floating point.
4563 @cindex @code{zero_extend@var{mn}2} instruction pattern
4564 @item @samp{zero_extend@var{m}@var{n}2}
4565 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
4566 store in operand 0 (which has mode @var{n}). Both modes must be fixed
4569 @cindex @code{fract@var{mn}2} instruction pattern
4570 @item @samp{fract@var{m}@var{n}2}
4571 Convert operand 1 of mode @var{m} to mode @var{n} and store in
4572 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
4573 could be fixed-point to fixed-point, signed integer to fixed-point,
4574 fixed-point to signed integer, floating-point to fixed-point,
4575 or fixed-point to floating-point.
4576 When overflows or underflows happen, the results are undefined.
4578 @cindex @code{satfract@var{mn}2} instruction pattern
4579 @item @samp{satfract@var{m}@var{n}2}
4580 Convert operand 1 of mode @var{m} to mode @var{n} and store in
4581 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
4582 could be fixed-point to fixed-point, signed integer to fixed-point,
4583 or floating-point to fixed-point.
4584 When overflows or underflows happen, the instruction saturates the
4585 results to the maximum or the minimum.
4587 @cindex @code{fractuns@var{mn}2} instruction pattern
4588 @item @samp{fractuns@var{m}@var{n}2}
4589 Convert operand 1 of mode @var{m} to mode @var{n} and store in
4590 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
4591 could be unsigned integer to fixed-point, or
4592 fixed-point to unsigned integer.
4593 When overflows or underflows happen, the results are undefined.
4595 @cindex @code{satfractuns@var{mn}2} instruction pattern
4596 @item @samp{satfractuns@var{m}@var{n}2}
4597 Convert unsigned integer operand 1 of mode @var{m} to fixed-point mode
4598 @var{n} and store in operand 0 (which has mode @var{n}).
4599 When overflows or underflows happen, the instruction saturates the
4600 results to the maximum or the minimum.
4602 @cindex @code{extv} instruction pattern
4604 Extract a bit-field from operand 1 (a register or memory operand), where
4605 operand 2 specifies the width in bits and operand 3 the starting bit,
4606 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
4607 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
4608 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
4609 be valid for @code{word_mode}.
4611 The RTL generation pass generates this instruction only with constants
4612 for operands 2 and 3 and the constant is never zero for operand 2.
4614 The bit-field value is sign-extended to a full word integer
4615 before it is stored in operand 0.
4617 @cindex @code{extzv} instruction pattern
4619 Like @samp{extv} except that the bit-field value is zero-extended.
4621 @cindex @code{insv} instruction pattern
4623 Store operand 3 (which must be valid for @code{word_mode}) into a
4624 bit-field in operand 0, where operand 1 specifies the width in bits and
4625 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
4626 @code{word_mode}; often @code{word_mode} is allowed only for registers.
4627 Operands 1 and 2 must be valid for @code{word_mode}.
4629 The RTL generation pass generates this instruction only with constants
4630 for operands 1 and 2 and the constant is never zero for operand 1.
4632 @cindex @code{mov@var{mode}cc} instruction pattern
4633 @item @samp{mov@var{mode}cc}
4634 Conditionally move operand 2 or operand 3 into operand 0 according to the
4635 comparison in operand 1. If the comparison is true, operand 2 is moved
4636 into operand 0, otherwise operand 3 is moved.
4638 The mode of the operands being compared need not be the same as the operands
4639 being moved. Some machines, sparc64 for example, have instructions that
4640 conditionally move an integer value based on the floating point condition
4641 codes and vice versa.
4643 If the machine does not have conditional move instructions, do not
4644 define these patterns.
4646 @cindex @code{add@var{mode}cc} instruction pattern
4647 @item @samp{add@var{mode}cc}
4648 Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally
4649 move operand 2 or (operands 2 + operand 3) into operand 0 according to the
4650 comparison in operand 1. If the comparison is true, operand 2 is moved into
4651 operand 0, otherwise (operand 2 + operand 3) is moved.
4653 @cindex @code{cstore@var{mode}4} instruction pattern
4654 @item @samp{cstore@var{mode}4}
4655 Store zero or nonzero in operand 0 according to whether a comparison
4656 is true. Operand 1 is a comparison operator. Operand 2 and operand 3
4657 are the first and second operand of the comparison, respectively.
4658 You specify the mode that operand 0 must have when you write the
4659 @code{match_operand} expression. The compiler automatically sees which
4660 mode you have used and supplies an operand of that mode.
4662 The value stored for a true condition must have 1 as its low bit, or
4663 else must be negative. Otherwise the instruction is not suitable and
4664 you should omit it from the machine description. You describe to the
4665 compiler exactly which value is stored by defining the macro
4666 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
4667 found that can be used for all the @samp{s@var{cond}} patterns, you
4668 should omit those operations from the machine description.
4670 These operations may fail, but should do so only in relatively
4671 uncommon cases; if they would fail for common cases involving
4672 integer comparisons, it is best to omit these patterns.
4674 If these operations are omitted, the compiler will usually generate code
4675 that copies the constant one to the target and branches around an
4676 assignment of zero to the target. If this code is more efficient than
4677 the potential instructions used for the @samp{cstore@var{mode}4} pattern
4678 followed by those required to convert the result into a 1 or a zero in
4679 @code{SImode}, you should omit the @samp{cstore@var{mode}4} operations from
4680 the machine description.
4682 @cindex @code{cbranch@var{mode}4} instruction pattern
4683 @item @samp{cbranch@var{mode}4}
4684 Conditional branch instruction combined with a compare instruction.
4685 Operand 0 is a comparison operator. Operand 1 and operand 2 are the
4686 first and second operands of the comparison, respectively. Operand 3
4687 is a @code{label_ref} that refers to the label to jump to.
4689 @cindex @code{jump} instruction pattern
4691 A jump inside a function; an unconditional branch. Operand 0 is the
4692 @code{label_ref} of the label to jump to. This pattern name is mandatory
4695 @cindex @code{call} instruction pattern
4697 Subroutine call instruction returning no value. Operand 0 is the
4698 function to call; operand 1 is the number of bytes of arguments pushed
4699 as a @code{const_int}; operand 2 is the number of registers used as
4702 On most machines, operand 2 is not actually stored into the RTL
4703 pattern. It is supplied for the sake of some RISC machines which need
4704 to put this information into the assembler code; they can put it in
4705 the RTL instead of operand 1.
4707 Operand 0 should be a @code{mem} RTX whose address is the address of the
4708 function. Note, however, that this address can be a @code{symbol_ref}
4709 expression even if it would not be a legitimate memory address on the
4710 target machine. If it is also not a valid argument for a call
4711 instruction, the pattern for this operation should be a
4712 @code{define_expand} (@pxref{Expander Definitions}) that places the
4713 address into a register and uses that register in the call instruction.
4715 @cindex @code{call_value} instruction pattern
4716 @item @samp{call_value}
4717 Subroutine call instruction returning a value. Operand 0 is the hard
4718 register in which the value is returned. There are three more
4719 operands, the same as the three operands of the @samp{call}
4720 instruction (but with numbers increased by one).
4722 Subroutines that return @code{BLKmode} objects use the @samp{call}
4725 @cindex @code{call_pop} instruction pattern
4726 @cindex @code{call_value_pop} instruction pattern
4727 @item @samp{call_pop}, @samp{call_value_pop}
4728 Similar to @samp{call} and @samp{call_value}, except used if defined and
4729 if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel}
4730 that contains both the function call and a @code{set} to indicate the
4731 adjustment made to the frame pointer.
4733 For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these
4734 patterns increases the number of functions for which the frame pointer
4735 can be eliminated, if desired.
4737 @cindex @code{untyped_call} instruction pattern
4738 @item @samp{untyped_call}
4739 Subroutine call instruction returning a value of any type. Operand 0 is
4740 the function to call; operand 1 is a memory location where the result of
4741 calling the function is to be stored; operand 2 is a @code{parallel}
4742 expression where each element is a @code{set} expression that indicates
4743 the saving of a function return value into the result block.
4745 This instruction pattern should be defined to support
4746 @code{__builtin_apply} on machines where special instructions are needed
4747 to call a subroutine with arbitrary arguments or to save the value
4748 returned. This instruction pattern is required on machines that have
4749 multiple registers that can hold a return value
4750 (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
4752 @cindex @code{return} instruction pattern
4754 Subroutine return instruction. This instruction pattern name should be
4755 defined only if a single instruction can do all the work of returning
4758 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
4759 RTL generation phase. In this case it is to support machines where
4760 multiple instructions are usually needed to return from a function, but
4761 some class of functions only requires one instruction to implement a
4762 return. Normally, the applicable functions are those which do not need
4763 to save any registers or allocate stack space.
4765 @findex reload_completed
4766 @findex leaf_function_p
4767 For such machines, the condition specified in this pattern should only
4768 be true when @code{reload_completed} is nonzero and the function's
4769 epilogue would only be a single instruction. For machines with register
4770 windows, the routine @code{leaf_function_p} may be used to determine if
4771 a register window push is required.
4773 Machines that have conditional return instructions should define patterns
4779 (if_then_else (match_operator
4780 0 "comparison_operator"
4781 [(cc0) (const_int 0)])
4788 where @var{condition} would normally be the same condition specified on the
4789 named @samp{return} pattern.
4791 @cindex @code{untyped_return} instruction pattern
4792 @item @samp{untyped_return}
4793 Untyped subroutine return instruction. This instruction pattern should
4794 be defined to support @code{__builtin_return} on machines where special
4795 instructions are needed to return a value of any type.
4797 Operand 0 is a memory location where the result of calling a function
4798 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
4799 expression where each element is a @code{set} expression that indicates
4800 the restoring of a function return value from the result block.
4802 @cindex @code{nop} instruction pattern
4804 No-op instruction. This instruction pattern name should always be defined
4805 to output a no-op in assembler code. @code{(const_int 0)} will do as an
4808 @cindex @code{indirect_jump} instruction pattern
4809 @item @samp{indirect_jump}
4810 An instruction to jump to an address which is operand zero.
4811 This pattern name is mandatory on all machines.
4813 @cindex @code{casesi} instruction pattern
4815 Instruction to jump through a dispatch table, including bounds checking.
4816 This instruction takes five operands:
4820 The index to dispatch on, which has mode @code{SImode}.
4823 The lower bound for indices in the table, an integer constant.
4826 The total range of indices in the table---the largest index
4827 minus the smallest one (both inclusive).
4830 A label that precedes the table itself.
4833 A label to jump to if the index has a value outside the bounds.
4836 The table is an @code{addr_vec} or @code{addr_diff_vec} inside of a
4837 @code{jump_insn}. The number of elements in the table is one plus the
4838 difference between the upper bound and the lower bound.
4840 @cindex @code{tablejump} instruction pattern
4841 @item @samp{tablejump}
4842 Instruction to jump to a variable address. This is a low-level
4843 capability which can be used to implement a dispatch table when there
4844 is no @samp{casesi} pattern.
4846 This pattern requires two operands: the address or offset, and a label
4847 which should immediately precede the jump table. If the macro
4848 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
4849 operand is an offset which counts from the address of the table; otherwise,
4850 it is an absolute address to jump to. In either case, the first operand has
4853 The @samp{tablejump} insn is always the last insn before the jump
4854 table it uses. Its assembler code normally has no need to use the
4855 second operand, but you should incorporate it in the RTL pattern so
4856 that the jump optimizer will not delete the table as unreachable code.
4859 @cindex @code{decrement_and_branch_until_zero} instruction pattern
4860 @item @samp{decrement_and_branch_until_zero}
4861 Conditional branch instruction that decrements a register and
4862 jumps if the register is nonzero. Operand 0 is the register to
4863 decrement and test; operand 1 is the label to jump to if the
4864 register is nonzero. @xref{Looping Patterns}.
4866 This optional instruction pattern is only used by the combiner,
4867 typically for loops reversed by the loop optimizer when strength
4868 reduction is enabled.
4870 @cindex @code{doloop_end} instruction pattern
4871 @item @samp{doloop_end}
4872 Conditional branch instruction that decrements a register and jumps if
4873 the register is nonzero. This instruction takes five operands: Operand
4874 0 is the register to decrement and test; operand 1 is the number of loop
4875 iterations as a @code{const_int} or @code{const0_rtx} if this cannot be
4876 determined until run-time; operand 2 is the actual or estimated maximum
4877 number of iterations as a @code{const_int}; operand 3 is the number of
4878 enclosed loops as a @code{const_int} (an innermost loop has a value of
4879 1); operand 4 is the label to jump to if the register is nonzero.
4880 @xref{Looping Patterns}.
4882 This optional instruction pattern should be defined for machines with
4883 low-overhead looping instructions as the loop optimizer will try to
4884 modify suitable loops to utilize it. If nested low-overhead looping is
4885 not supported, use a @code{define_expand} (@pxref{Expander Definitions})
4886 and make the pattern fail if operand 3 is not @code{const1_rtx}.
4887 Similarly, if the actual or estimated maximum number of iterations is
4888 too large for this instruction, make it fail.
4890 @cindex @code{doloop_begin} instruction pattern
4891 @item @samp{doloop_begin}
4892 Companion instruction to @code{doloop_end} required for machines that
4893 need to perform some initialization, such as loading special registers
4894 used by a low-overhead looping instruction. If initialization insns do
4895 not always need to be emitted, use a @code{define_expand}
4896 (@pxref{Expander Definitions}) and make it fail.
4899 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
4900 @item @samp{canonicalize_funcptr_for_compare}
4901 Canonicalize the function pointer in operand 1 and store the result
4904 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
4905 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
4906 and also has mode @code{Pmode}.
4908 Canonicalization of a function pointer usually involves computing
4909 the address of the function which would be called if the function
4910 pointer were used in an indirect call.
4912 Only define this pattern if function pointers on the target machine
4913 can have different values but still call the same function when
4914 used in an indirect call.
4916 @cindex @code{save_stack_block} instruction pattern
4917 @cindex @code{save_stack_function} instruction pattern
4918 @cindex @code{save_stack_nonlocal} instruction pattern
4919 @cindex @code{restore_stack_block} instruction pattern
4920 @cindex @code{restore_stack_function} instruction pattern
4921 @cindex @code{restore_stack_nonlocal} instruction pattern
4922 @item @samp{save_stack_block}
4923 @itemx @samp{save_stack_function}
4924 @itemx @samp{save_stack_nonlocal}
4925 @itemx @samp{restore_stack_block}
4926 @itemx @samp{restore_stack_function}
4927 @itemx @samp{restore_stack_nonlocal}
4928 Most machines save and restore the stack pointer by copying it to or
4929 from an object of mode @code{Pmode}. Do not define these patterns on
4932 Some machines require special handling for stack pointer saves and
4933 restores. On those machines, define the patterns corresponding to the
4934 non-standard cases by using a @code{define_expand} (@pxref{Expander
4935 Definitions}) that produces the required insns. The three types of
4936 saves and restores are:
4940 @samp{save_stack_block} saves the stack pointer at the start of a block
4941 that allocates a variable-sized object, and @samp{restore_stack_block}
4942 restores the stack pointer when the block is exited.
4945 @samp{save_stack_function} and @samp{restore_stack_function} do a
4946 similar job for the outermost block of a function and are used when the
4947 function allocates variable-sized objects or calls @code{alloca}. Only
4948 the epilogue uses the restored stack pointer, allowing a simpler save or
4949 restore sequence on some machines.
4952 @samp{save_stack_nonlocal} is used in functions that contain labels
4953 branched to by nested functions. It saves the stack pointer in such a
4954 way that the inner function can use @samp{restore_stack_nonlocal} to
4955 restore the stack pointer. The compiler generates code to restore the
4956 frame and argument pointer registers, but some machines require saving
4957 and restoring additional data such as register window information or
4958 stack backchains. Place insns in these patterns to save and restore any
4962 When saving the stack pointer, operand 0 is the save area and operand 1
4963 is the stack pointer. The mode used to allocate the save area defaults
4964 to @code{Pmode} but you can override that choice by defining the
4965 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
4966 specify an integral mode, or @code{VOIDmode} if no save area is needed
4967 for a particular type of save (either because no save is needed or
4968 because a machine-specific save area can be used). Operand 0 is the
4969 stack pointer and operand 1 is the save area for restore operations. If
4970 @samp{save_stack_block} is defined, operand 0 must not be
4971 @code{VOIDmode} since these saves can be arbitrarily nested.
4973 A save area is a @code{mem} that is at a constant offset from
4974 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
4975 nonlocal gotos and a @code{reg} in the other two cases.
4977 @cindex @code{allocate_stack} instruction pattern
4978 @item @samp{allocate_stack}
4979 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
4980 the stack pointer to create space for dynamically allocated data.
4982 Store the resultant pointer to this space into operand 0. If you
4983 are allocating space from the main stack, do this by emitting a
4984 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
4985 If you are allocating the space elsewhere, generate code to copy the
4986 location of the space to operand 0. In the latter case, you must
4987 ensure this space gets freed when the corresponding space on the main
4990 Do not define this pattern if all that must be done is the subtraction.
4991 Some machines require other operations such as stack probes or
4992 maintaining the back chain. Define this pattern to emit those
4993 operations in addition to updating the stack pointer.
4995 @cindex @code{check_stack} instruction pattern
4996 @item @samp{check_stack}
4997 If stack checking cannot be done on your system by probing the stack with
4998 a load or store instruction (@pxref{Stack Checking}), define this pattern
4999 to perform the needed check and signaling an error if the stack
5000 has overflowed. The single operand is the location in the stack furthest
5001 from the current stack pointer that you need to validate. Normally,
5002 on machines where this pattern is needed, you would obtain the stack
5003 limit from a global or thread-specific variable or register.
5005 @cindex @code{nonlocal_goto} instruction pattern
5006 @item @samp{nonlocal_goto}
5007 Emit code to generate a non-local goto, e.g., a jump from one function
5008 to a label in an outer function. This pattern has four arguments,
5009 each representing a value to be used in the jump. The first
5010 argument is to be loaded into the frame pointer, the second is
5011 the address to branch to (code to dispatch to the actual label),
5012 the third is the address of a location where the stack is saved,
5013 and the last is the address of the label, to be placed in the
5014 location for the incoming static chain.
5016 On most machines you need not define this pattern, since GCC will
5017 already generate the correct code, which is to load the frame pointer
5018 and static chain, restore the stack (using the
5019 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
5020 to the dispatcher. You need only define this pattern if this code will
5021 not work on your machine.
5023 @cindex @code{nonlocal_goto_receiver} instruction pattern
5024 @item @samp{nonlocal_goto_receiver}
5025 This pattern, if defined, contains code needed at the target of a
5026 nonlocal goto after the code already generated by GCC@. You will not
5027 normally need to define this pattern. A typical reason why you might
5028 need this pattern is if some value, such as a pointer to a global table,
5029 must be restored when the frame pointer is restored. Note that a nonlocal
5030 goto only occurs within a unit-of-translation, so a global table pointer
5031 that is shared by all functions of a given module need not be restored.
5032 There are no arguments.
5034 @cindex @code{exception_receiver} instruction pattern
5035 @item @samp{exception_receiver}
5036 This pattern, if defined, contains code needed at the site of an
5037 exception handler that isn't needed at the site of a nonlocal goto. You
5038 will not normally need to define this pattern. A typical reason why you
5039 might need this pattern is if some value, such as a pointer to a global
5040 table, must be restored after control flow is branched to the handler of
5041 an exception. There are no arguments.
5043 @cindex @code{builtin_setjmp_setup} instruction pattern
5044 @item @samp{builtin_setjmp_setup}
5045 This pattern, if defined, contains additional code needed to initialize
5046 the @code{jmp_buf}. You will not normally need to define this pattern.
5047 A typical reason why you might need this pattern is if some value, such
5048 as a pointer to a global table, must be restored. Though it is
5049 preferred that the pointer value be recalculated if possible (given the
5050 address of a label for instance). The single argument is a pointer to
5051 the @code{jmp_buf}. Note that the buffer is five words long and that
5052 the first three are normally used by the generic mechanism.
5054 @cindex @code{builtin_setjmp_receiver} instruction pattern
5055 @item @samp{builtin_setjmp_receiver}
5056 This pattern, if defined, contains code needed at the site of a
5057 built-in setjmp that isn't needed at the site of a nonlocal goto. You
5058 will not normally need to define this pattern. A typical reason why you
5059 might need this pattern is if some value, such as a pointer to a global
5060 table, must be restored. It takes one argument, which is the label
5061 to which builtin_longjmp transfered control; this pattern may be emitted
5062 at a small offset from that label.
5064 @cindex @code{builtin_longjmp} instruction pattern
5065 @item @samp{builtin_longjmp}
5066 This pattern, if defined, performs the entire action of the longjmp.
5067 You will not normally need to define this pattern unless you also define
5068 @code{builtin_setjmp_setup}. The single argument is a pointer to the
5071 @cindex @code{eh_return} instruction pattern
5072 @item @samp{eh_return}
5073 This pattern, if defined, affects the way @code{__builtin_eh_return},
5074 and thence the call frame exception handling library routines, are
5075 built. It is intended to handle non-trivial actions needed along
5076 the abnormal return path.
5078 The address of the exception handler to which the function should return
5079 is passed as operand to this pattern. It will normally need to copied by
5080 the pattern to some special register or memory location.
5081 If the pattern needs to determine the location of the target call
5082 frame in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX},
5083 if defined; it will have already been assigned.
5085 If this pattern is not defined, the default action will be to simply
5086 copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either
5087 that macro or this pattern needs to be defined if call frame exception
5088 handling is to be used.
5090 @cindex @code{prologue} instruction pattern
5091 @anchor{prologue instruction pattern}
5092 @item @samp{prologue}
5093 This pattern, if defined, emits RTL for entry to a function. The function
5094 entry is responsible for setting up the stack frame, initializing the frame
5095 pointer register, saving callee saved registers, etc.
5097 Using a prologue pattern is generally preferred over defining
5098 @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue.
5100 The @code{prologue} pattern is particularly useful for targets which perform
5101 instruction scheduling.
5103 @cindex @code{epilogue} instruction pattern
5104 @anchor{epilogue instruction pattern}
5105 @item @samp{epilogue}
5106 This pattern emits RTL for exit from a function. The function
5107 exit is responsible for deallocating the stack frame, restoring callee saved
5108 registers and emitting the return instruction.
5110 Using an epilogue pattern is generally preferred over defining
5111 @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue.
5113 The @code{epilogue} pattern is particularly useful for targets which perform
5114 instruction scheduling or which have delay slots for their return instruction.
5116 @cindex @code{sibcall_epilogue} instruction pattern
5117 @item @samp{sibcall_epilogue}
5118 This pattern, if defined, emits RTL for exit from a function without the final
5119 branch back to the calling function. This pattern will be emitted before any
5120 sibling call (aka tail call) sites.
5122 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
5123 parameter passing or any stack slots for arguments passed to the current
5126 @cindex @code{trap} instruction pattern
5128 This pattern, if defined, signals an error, typically by causing some
5129 kind of signal to be raised. Among other places, it is used by the Java
5130 front end to signal `invalid array index' exceptions.
5132 @cindex @code{ctrap@var{MM}4} instruction pattern
5133 @item @samp{ctrap@var{MM}4}
5134 Conditional trap instruction. Operand 0 is a piece of RTL which
5135 performs a comparison, and operands 1 and 2 are the arms of the
5136 comparison. Operand 3 is the trap code, an integer.
5138 A typical @code{ctrap} pattern looks like
5141 (define_insn "ctrapsi4"
5142 [(trap_if (match_operator 0 "trap_operator"
5143 [(match_operand 1 "register_operand")
5144 (match_operand 2 "immediate_operand")])
5145 (match_operand 3 "const_int_operand" "i"))]
5150 @cindex @code{prefetch} instruction pattern
5151 @item @samp{prefetch}
5153 This pattern, if defined, emits code for a non-faulting data prefetch
5154 instruction. Operand 0 is the address of the memory to prefetch. Operand 1
5155 is a constant 1 if the prefetch is preparing for a write to the memory
5156 address, or a constant 0 otherwise. Operand 2 is the expected degree of
5157 temporal locality of the data and is a value between 0 and 3, inclusive; 0
5158 means that the data has no temporal locality, so it need not be left in the
5159 cache after the access; 3 means that the data has a high degree of temporal
5160 locality and should be left in all levels of cache possible; 1 and 2 mean,
5161 respectively, a low or moderate degree of temporal locality.
5163 Targets that do not support write prefetches or locality hints can ignore
5164 the values of operands 1 and 2.
5166 @cindex @code{blockage} instruction pattern
5167 @item @samp{blockage}
5169 This pattern defines a pseudo insn that prevents the instruction
5170 scheduler from moving instructions across the boundary defined by the
5171 blockage insn. Normally an UNSPEC_VOLATILE pattern.
5173 @cindex @code{memory_barrier} instruction pattern
5174 @item @samp{memory_barrier}
5176 If the target memory model is not fully synchronous, then this pattern
5177 should be defined to an instruction that orders both loads and stores
5178 before the instruction with respect to loads and stores after the instruction.
5179 This pattern has no operands.
5181 @cindex @code{sync_compare_and_swap@var{mode}} instruction pattern
5182 @item @samp{sync_compare_and_swap@var{mode}}
5184 This pattern, if defined, emits code for an atomic compare-and-swap
5185 operation. Operand 1 is the memory on which the atomic operation is
5186 performed. Operand 2 is the ``old'' value to be compared against the
5187 current contents of the memory location. Operand 3 is the ``new'' value
5188 to store in the memory if the compare succeeds. Operand 0 is the result
5189 of the operation; it should contain the contents of the memory
5190 before the operation. If the compare succeeds, this should obviously be
5191 a copy of operand 2.
5193 This pattern must show that both operand 0 and operand 1 are modified.
5195 This pattern must issue any memory barrier instructions such that all
5196 memory operations before the atomic operation occur before the atomic
5197 operation and all memory operations after the atomic operation occur
5198 after the atomic operation.
5200 For targets where the success or failure of the compare-and-swap
5201 operation is available via the status flags, it is possible to
5202 avoid a separate compare operation and issue the subsequent
5203 branch or store-flag operation immediately after the compare-and-swap.
5204 To this end, GCC will look for a @code{MODE_CC} set in the
5205 output of @code{sync_compare_and_swap@var{mode}}; if the machine
5206 description includes such a set, the target should also define special
5207 @code{cbranchcc4} and/or @code{cstorecc4} instructions. GCC will then
5208 be able to take the destination of the @code{MODE_CC} set and pass it
5209 to the @code{cbranchcc4} or @code{cstorecc4} pattern as the first
5210 operand of the comparison (the second will be @code{(const_int 0)}).
5212 @cindex @code{sync_add@var{mode}} instruction pattern
5213 @cindex @code{sync_sub@var{mode}} instruction pattern
5214 @cindex @code{sync_ior@var{mode}} instruction pattern
5215 @cindex @code{sync_and@var{mode}} instruction pattern
5216 @cindex @code{sync_xor@var{mode}} instruction pattern
5217 @cindex @code{sync_nand@var{mode}} instruction pattern
5218 @item @samp{sync_add@var{mode}}, @samp{sync_sub@var{mode}}
5219 @itemx @samp{sync_ior@var{mode}}, @samp{sync_and@var{mode}}
5220 @itemx @samp{sync_xor@var{mode}}, @samp{sync_nand@var{mode}}
5222 These patterns emit code for an atomic operation on memory.
5223 Operand 0 is the memory on which the atomic operation is performed.
5224 Operand 1 is the second operand to the binary operator.
5226 This pattern must issue any memory barrier instructions such that all
5227 memory operations before the atomic operation occur before the atomic
5228 operation and all memory operations after the atomic operation occur
5229 after the atomic operation.
5231 If these patterns are not defined, the operation will be constructed
5232 from a compare-and-swap operation, if defined.
5234 @cindex @code{sync_old_add@var{mode}} instruction pattern
5235 @cindex @code{sync_old_sub@var{mode}} instruction pattern
5236 @cindex @code{sync_old_ior@var{mode}} instruction pattern
5237 @cindex @code{sync_old_and@var{mode}} instruction pattern
5238 @cindex @code{sync_old_xor@var{mode}} instruction pattern
5239 @cindex @code{sync_old_nand@var{mode}} instruction pattern
5240 @item @samp{sync_old_add@var{mode}}, @samp{sync_old_sub@var{mode}}
5241 @itemx @samp{sync_old_ior@var{mode}}, @samp{sync_old_and@var{mode}}
5242 @itemx @samp{sync_old_xor@var{mode}}, @samp{sync_old_nand@var{mode}}
5244 These patterns are emit code for an atomic operation on memory,
5245 and return the value that the memory contained before the operation.
5246 Operand 0 is the result value, operand 1 is the memory on which the
5247 atomic operation is performed, and operand 2 is the second operand
5248 to the binary operator.
5250 This pattern must issue any memory barrier instructions such that all
5251 memory operations before the atomic operation occur before the atomic
5252 operation and all memory operations after the atomic operation occur
5253 after the atomic operation.
5255 If these patterns are not defined, the operation will be constructed
5256 from a compare-and-swap operation, if defined.
5258 @cindex @code{sync_new_add@var{mode}} instruction pattern
5259 @cindex @code{sync_new_sub@var{mode}} instruction pattern
5260 @cindex @code{sync_new_ior@var{mode}} instruction pattern
5261 @cindex @code{sync_new_and@var{mode}} instruction pattern
5262 @cindex @code{sync_new_xor@var{mode}} instruction pattern
5263 @cindex @code{sync_new_nand@var{mode}} instruction pattern
5264 @item @samp{sync_new_add@var{mode}}, @samp{sync_new_sub@var{mode}}
5265 @itemx @samp{sync_new_ior@var{mode}}, @samp{sync_new_and@var{mode}}
5266 @itemx @samp{sync_new_xor@var{mode}}, @samp{sync_new_nand@var{mode}}
5268 These patterns are like their @code{sync_old_@var{op}} counterparts,
5269 except that they return the value that exists in the memory location
5270 after the operation, rather than before the operation.
5272 @cindex @code{sync_lock_test_and_set@var{mode}} instruction pattern
5273 @item @samp{sync_lock_test_and_set@var{mode}}
5275 This pattern takes two forms, based on the capabilities of the target.
5276 In either case, operand 0 is the result of the operand, operand 1 is
5277 the memory on which the atomic operation is performed, and operand 2
5278 is the value to set in the lock.
5280 In the ideal case, this operation is an atomic exchange operation, in
5281 which the previous value in memory operand is copied into the result
5282 operand, and the value operand is stored in the memory operand.
5284 For less capable targets, any value operand that is not the constant 1
5285 should be rejected with @code{FAIL}. In this case the target may use
5286 an atomic test-and-set bit operation. The result operand should contain
5287 1 if the bit was previously set and 0 if the bit was previously clear.
5288 The true contents of the memory operand are implementation defined.
5290 This pattern must issue any memory barrier instructions such that the
5291 pattern as a whole acts as an acquire barrier, that is all memory
5292 operations after the pattern do not occur until the lock is acquired.
5294 If this pattern is not defined, the operation will be constructed from
5295 a compare-and-swap operation, if defined.
5297 @cindex @code{sync_lock_release@var{mode}} instruction pattern
5298 @item @samp{sync_lock_release@var{mode}}
5300 This pattern, if defined, releases a lock set by
5301 @code{sync_lock_test_and_set@var{mode}}. Operand 0 is the memory
5302 that contains the lock; operand 1 is the value to store in the lock.
5304 If the target doesn't implement full semantics for
5305 @code{sync_lock_test_and_set@var{mode}}, any value operand which is not
5306 the constant 0 should be rejected with @code{FAIL}, and the true contents
5307 of the memory operand are implementation defined.
5309 This pattern must issue any memory barrier instructions such that the
5310 pattern as a whole acts as a release barrier, that is the lock is
5311 released only after all previous memory operations have completed.
5313 If this pattern is not defined, then a @code{memory_barrier} pattern
5314 will be emitted, followed by a store of the value to the memory operand.
5316 @cindex @code{stack_protect_set} instruction pattern
5317 @item @samp{stack_protect_set}
5319 This pattern, if defined, moves a @code{Pmode} value from the memory
5320 in operand 1 to the memory in operand 0 without leaving the value in
5321 a register afterward. This is to avoid leaking the value some place
5322 that an attacker might use to rewrite the stack guard slot after
5323 having clobbered it.
5325 If this pattern is not defined, then a plain move pattern is generated.
5327 @cindex @code{stack_protect_test} instruction pattern
5328 @item @samp{stack_protect_test}
5330 This pattern, if defined, compares a @code{Pmode} value from the
5331 memory in operand 1 with the memory in operand 0 without leaving the
5332 value in a register afterward and branches to operand 2 if the values
5335 If this pattern is not defined, then a plain compare pattern and
5336 conditional branch pattern is used.
5338 @cindex @code{clear_cache} instruction pattern
5339 @item @samp{clear_cache}
5341 This pattern, if defined, flushes the instruction cache for a region of
5342 memory. The region is bounded to by the Pmode pointers in operand 0
5343 inclusive and operand 1 exclusive.
5345 If this pattern is not defined, a call to the library function
5346 @code{__clear_cache} is used.
5351 @c Each of the following nodes are wrapped in separate
5352 @c "@ifset INTERNALS" to work around memory limits for the default
5353 @c configuration in older tetex distributions. Known to not work:
5354 @c tetex-1.0.7, known to work: tetex-2.0.2.
5356 @node Pattern Ordering
5357 @section When the Order of Patterns Matters
5358 @cindex Pattern Ordering
5359 @cindex Ordering of Patterns
5361 Sometimes an insn can match more than one instruction pattern. Then the
5362 pattern that appears first in the machine description is the one used.
5363 Therefore, more specific patterns (patterns that will match fewer things)
5364 and faster instructions (those that will produce better code when they
5365 do match) should usually go first in the description.
5367 In some cases the effect of ordering the patterns can be used to hide
5368 a pattern when it is not valid. For example, the 68000 has an
5369 instruction for converting a fullword to floating point and another
5370 for converting a byte to floating point. An instruction converting
5371 an integer to floating point could match either one. We put the
5372 pattern to convert the fullword first to make sure that one will
5373 be used rather than the other. (Otherwise a large integer might
5374 be generated as a single-byte immediate quantity, which would not work.)
5375 Instead of using this pattern ordering it would be possible to make the
5376 pattern for convert-a-byte smart enough to deal properly with any
5381 @node Dependent Patterns
5382 @section Interdependence of Patterns
5383 @cindex Dependent Patterns
5384 @cindex Interdependence of Patterns
5386 In some cases machines support instructions identical except for the
5387 machine mode of one or more operands. For example, there may be
5388 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
5392 (set (match_operand:SI 0 @dots{})
5393 (extend:SI (match_operand:HI 1 @dots{})))
5395 (set (match_operand:SI 0 @dots{})
5396 (extend:SI (match_operand:QI 1 @dots{})))
5400 Constant integers do not specify a machine mode, so an instruction to
5401 extend a constant value could match either pattern. The pattern it
5402 actually will match is the one that appears first in the file. For correct
5403 results, this must be the one for the widest possible mode (@code{HImode},
5404 here). If the pattern matches the @code{QImode} instruction, the results
5405 will be incorrect if the constant value does not actually fit that mode.
5407 Such instructions to extend constants are rarely generated because they are
5408 optimized away, but they do occasionally happen in nonoptimized
5411 If a constraint in a pattern allows a constant, the reload pass may
5412 replace a register with a constant permitted by the constraint in some
5413 cases. Similarly for memory references. Because of this substitution,
5414 you should not provide separate patterns for increment and decrement
5415 instructions. Instead, they should be generated from the same pattern
5416 that supports register-register add insns by examining the operands and
5417 generating the appropriate machine instruction.
5422 @section Defining Jump Instruction Patterns
5423 @cindex jump instruction patterns
5424 @cindex defining jump instruction patterns
5426 GCC does not assume anything about how the machine realizes jumps.
5427 The machine description should define a single pattern, usually
5428 a @code{define_expand}, which expands to all the required insns.
5430 Usually, this would be a comparison insn to set the condition code
5431 and a separate branch insn testing the condition code and branching
5432 or not according to its value. For many machines, however,
5433 separating compares and branches is limiting, which is why the
5434 more flexible approach with one @code{define_expand} is used in GCC.
5435 The machine description becomes clearer for architectures that
5436 have compare-and-branch instructions but no condition code. It also
5437 works better when different sets of comparison operators are supported
5438 by different kinds of conditional branches (e.g. integer vs. floating-point),
5439 or by conditional branches with respect to conditional stores.
5441 Two separate insns are always used if the machine description represents
5442 a condition code register using the legacy RTL expression @code{(cc0)},
5443 and on most machines that use a separate condition code register
5444 (@pxref{Condition Code}). For machines that use @code{(cc0)}, in
5445 fact, the set and use of the condition code must be separate and
5446 adjacent@footnote{@code{note} insns can separate them, though.}, thus
5447 allowing flags in @code{cc_status} to be used (@pxref{Condition Code}) and
5448 so that the comparison and branch insns could be located from each other
5449 by using the functions @code{prev_cc0_setter} and @code{next_cc0_user}.
5451 Even in this case having a single entry point for conditional branches
5452 is advantageous, because it handles equally well the case where a single
5453 comparison instruction records the results of both signed and unsigned
5454 comparison of the given operands (with the branch insns coming in distinct
5455 signed and unsigned flavors) as in the x86 or SPARC, and the case where
5456 there are distinct signed and unsigned compare instructions and only
5457 one set of conditional branch instructions as in the PowerPC.
5461 @node Looping Patterns
5462 @section Defining Looping Instruction Patterns
5463 @cindex looping instruction patterns
5464 @cindex defining looping instruction patterns
5466 Some machines have special jump instructions that can be utilized to
5467 make loops more efficient. A common example is the 68000 @samp{dbra}
5468 instruction which performs a decrement of a register and a branch if the
5469 result was greater than zero. Other machines, in particular digital
5470 signal processors (DSPs), have special block repeat instructions to
5471 provide low-overhead loop support. For example, the TI TMS320C3x/C4x
5472 DSPs have a block repeat instruction that loads special registers to
5473 mark the top and end of a loop and to count the number of loop
5474 iterations. This avoids the need for fetching and executing a
5475 @samp{dbra}-like instruction and avoids pipeline stalls associated with
5478 GCC has three special named patterns to support low overhead looping.
5479 They are @samp{decrement_and_branch_until_zero}, @samp{doloop_begin},
5480 and @samp{doloop_end}. The first pattern,
5481 @samp{decrement_and_branch_until_zero}, is not emitted during RTL
5482 generation but may be emitted during the instruction combination phase.
5483 This requires the assistance of the loop optimizer, using information
5484 collected during strength reduction, to reverse a loop to count down to
5485 zero. Some targets also require the loop optimizer to add a
5486 @code{REG_NONNEG} note to indicate that the iteration count is always
5487 positive. This is needed if the target performs a signed loop
5488 termination test. For example, the 68000 uses a pattern similar to the
5489 following for its @code{dbra} instruction:
5493 (define_insn "decrement_and_branch_until_zero"
5496 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
5499 (label_ref (match_operand 1 "" ""))
5502 (plus:SI (match_dup 0)
5504 "find_reg_note (insn, REG_NONNEG, 0)"
5509 Note that since the insn is both a jump insn and has an output, it must
5510 deal with its own reloads, hence the `m' constraints. Also note that
5511 since this insn is generated by the instruction combination phase
5512 combining two sequential insns together into an implicit parallel insn,
5513 the iteration counter needs to be biased by the same amount as the
5514 decrement operation, in this case @minus{}1. Note that the following similar
5515 pattern will not be matched by the combiner.
5519 (define_insn "decrement_and_branch_until_zero"
5522 (ge (match_operand:SI 0 "general_operand" "+d*am")
5524 (label_ref (match_operand 1 "" ""))
5527 (plus:SI (match_dup 0)
5529 "find_reg_note (insn, REG_NONNEG, 0)"
5534 The other two special looping patterns, @samp{doloop_begin} and
5535 @samp{doloop_end}, are emitted by the loop optimizer for certain
5536 well-behaved loops with a finite number of loop iterations using
5537 information collected during strength reduction.
5539 The @samp{doloop_end} pattern describes the actual looping instruction
5540 (or the implicit looping operation) and the @samp{doloop_begin} pattern
5541 is an optional companion pattern that can be used for initialization
5542 needed for some low-overhead looping instructions.
5544 Note that some machines require the actual looping instruction to be
5545 emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
5546 the true RTL for a looping instruction at the top of the loop can cause
5547 problems with flow analysis. So instead, a dummy @code{doloop} insn is
5548 emitted at the end of the loop. The machine dependent reorg pass checks
5549 for the presence of this @code{doloop} insn and then searches back to
5550 the top of the loop, where it inserts the true looping insn (provided
5551 there are no instructions in the loop which would cause problems). Any
5552 additional labels can be emitted at this point. In addition, if the
5553 desired special iteration counter register was not allocated, this
5554 machine dependent reorg pass could emit a traditional compare and jump
5557 The essential difference between the
5558 @samp{decrement_and_branch_until_zero} and the @samp{doloop_end}
5559 patterns is that the loop optimizer allocates an additional pseudo
5560 register for the latter as an iteration counter. This pseudo register
5561 cannot be used within the loop (i.e., general induction variables cannot
5562 be derived from it), however, in many cases the loop induction variable
5563 may become redundant and removed by the flow pass.
5568 @node Insn Canonicalizations
5569 @section Canonicalization of Instructions
5570 @cindex canonicalization of instructions
5571 @cindex insn canonicalization
5573 There are often cases where multiple RTL expressions could represent an
5574 operation performed by a single machine instruction. This situation is
5575 most commonly encountered with logical, branch, and multiply-accumulate
5576 instructions. In such cases, the compiler attempts to convert these
5577 multiple RTL expressions into a single canonical form to reduce the
5578 number of insn patterns required.
5580 In addition to algebraic simplifications, following canonicalizations
5585 For commutative and comparison operators, a constant is always made the
5586 second operand. If a machine only supports a constant as the second
5587 operand, only patterns that match a constant in the second operand need
5591 For associative operators, a sequence of operators will always chain
5592 to the left; for instance, only the left operand of an integer @code{plus}
5593 can itself be a @code{plus}. @code{and}, @code{ior}, @code{xor},
5594 @code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and
5595 @code{umax} are associative when applied to integers, and sometimes to
5599 @cindex @code{neg}, canonicalization of
5600 @cindex @code{not}, canonicalization of
5601 @cindex @code{mult}, canonicalization of
5602 @cindex @code{plus}, canonicalization of
5603 @cindex @code{minus}, canonicalization of
5604 For these operators, if only one operand is a @code{neg}, @code{not},
5605 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
5609 In combinations of @code{neg}, @code{mult}, @code{plus}, and
5610 @code{minus}, the @code{neg} operations (if any) will be moved inside
5611 the operations as far as possible. For instance,
5612 @code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but
5613 @code{(plus (mult (neg A) B) C)} is canonicalized as
5614 @code{(minus A (mult B C))}.
5616 @cindex @code{compare}, canonicalization of
5618 For the @code{compare} operator, a constant is always the second operand
5619 if the first argument is a condition code register or @code{(cc0)}.
5622 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
5623 @code{minus} is made the first operand under the same conditions as
5627 @code{(ltu (plus @var{a} @var{b}) @var{b})} is converted to
5628 @code{(ltu (plus @var{a} @var{b}) @var{a})}. Likewise with @code{geu} instead
5632 @code{(minus @var{x} (const_int @var{n}))} is converted to
5633 @code{(plus @var{x} (const_int @var{-n}))}.
5636 Within address computations (i.e., inside @code{mem}), a left shift is
5637 converted into the appropriate multiplication by a power of two.
5639 @cindex @code{ior}, canonicalization of
5640 @cindex @code{and}, canonicalization of
5641 @cindex De Morgan's law
5643 De Morgan's Law is used to move bitwise negation inside a bitwise
5644 logical-and or logical-or operation. If this results in only one
5645 operand being a @code{not} expression, it will be the first one.
5647 A machine that has an instruction that performs a bitwise logical-and of one
5648 operand with the bitwise negation of the other should specify the pattern
5649 for that instruction as
5653 [(set (match_operand:@var{m} 0 @dots{})
5654 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
5655 (match_operand:@var{m} 2 @dots{})))]
5661 Similarly, a pattern for a ``NAND'' instruction should be written
5665 [(set (match_operand:@var{m} 0 @dots{})
5666 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
5667 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
5672 In both cases, it is not necessary to include patterns for the many
5673 logically equivalent RTL expressions.
5675 @cindex @code{xor}, canonicalization of
5677 The only possible RTL expressions involving both bitwise exclusive-or
5678 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
5679 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
5682 The sum of three items, one of which is a constant, will only appear in
5686 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
5689 @cindex @code{zero_extract}, canonicalization of
5690 @cindex @code{sign_extract}, canonicalization of
5692 Equality comparisons of a group of bits (usually a single bit) with zero
5693 will be written using @code{zero_extract} rather than the equivalent
5694 @code{and} or @code{sign_extract} operations.
5698 Further canonicalization rules are defined in the function
5699 @code{commutative_operand_precedence} in @file{gcc/rtlanal.c}.
5703 @node Expander Definitions
5704 @section Defining RTL Sequences for Code Generation
5705 @cindex expander definitions
5706 @cindex code generation RTL sequences
5707 @cindex defining RTL sequences for code generation
5709 On some target machines, some standard pattern names for RTL generation
5710 cannot be handled with single insn, but a sequence of RTL insns can
5711 represent them. For these target machines, you can write a
5712 @code{define_expand} to specify how to generate the sequence of RTL@.
5714 @findex define_expand
5715 A @code{define_expand} is an RTL expression that looks almost like a
5716 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
5717 only for RTL generation and it can produce more than one RTL insn.
5719 A @code{define_expand} RTX has four operands:
5723 The name. Each @code{define_expand} must have a name, since the only
5724 use for it is to refer to it by name.
5727 The RTL template. This is a vector of RTL expressions representing
5728 a sequence of separate instructions. Unlike @code{define_insn}, there
5729 is no implicit surrounding @code{PARALLEL}.
5732 The condition, a string containing a C expression. This expression is
5733 used to express how the availability of this pattern depends on
5734 subclasses of target machine, selected by command-line options when GCC
5735 is run. This is just like the condition of a @code{define_insn} that
5736 has a standard name. Therefore, the condition (if present) may not
5737 depend on the data in the insn being matched, but only the
5738 target-machine-type flags. The compiler needs to test these conditions
5739 during initialization in order to learn exactly which named instructions
5740 are available in a particular run.
5743 The preparation statements, a string containing zero or more C
5744 statements which are to be executed before RTL code is generated from
5747 Usually these statements prepare temporary registers for use as
5748 internal operands in the RTL template, but they can also generate RTL
5749 insns directly by calling routines such as @code{emit_insn}, etc.
5750 Any such insns precede the ones that come from the RTL template.
5753 Every RTL insn emitted by a @code{define_expand} must match some
5754 @code{define_insn} in the machine description. Otherwise, the compiler
5755 will crash when trying to generate code for the insn or trying to optimize
5758 The RTL template, in addition to controlling generation of RTL insns,
5759 also describes the operands that need to be specified when this pattern
5760 is used. In particular, it gives a predicate for each operand.
5762 A true operand, which needs to be specified in order to generate RTL from
5763 the pattern, should be described with a @code{match_operand} in its first
5764 occurrence in the RTL template. This enters information on the operand's
5765 predicate into the tables that record such things. GCC uses the
5766 information to preload the operand into a register if that is required for
5767 valid RTL code. If the operand is referred to more than once, subsequent
5768 references should use @code{match_dup}.
5770 The RTL template may also refer to internal ``operands'' which are
5771 temporary registers or labels used only within the sequence made by the
5772 @code{define_expand}. Internal operands are substituted into the RTL
5773 template with @code{match_dup}, never with @code{match_operand}. The
5774 values of the internal operands are not passed in as arguments by the
5775 compiler when it requests use of this pattern. Instead, they are computed
5776 within the pattern, in the preparation statements. These statements
5777 compute the values and store them into the appropriate elements of
5778 @code{operands} so that @code{match_dup} can find them.
5780 There are two special macros defined for use in the preparation statements:
5781 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
5788 Use the @code{DONE} macro to end RTL generation for the pattern. The
5789 only RTL insns resulting from the pattern on this occasion will be
5790 those already emitted by explicit calls to @code{emit_insn} within the
5791 preparation statements; the RTL template will not be generated.
5795 Make the pattern fail on this occasion. When a pattern fails, it means
5796 that the pattern was not truly available. The calling routines in the
5797 compiler will try other strategies for code generation using other patterns.
5799 Failure is currently supported only for binary (addition, multiplication,
5800 shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv})
5804 If the preparation falls through (invokes neither @code{DONE} nor
5805 @code{FAIL}), then the @code{define_expand} acts like a
5806 @code{define_insn} in that the RTL template is used to generate the
5809 The RTL template is not used for matching, only for generating the
5810 initial insn list. If the preparation statement always invokes
5811 @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple
5812 list of operands, such as this example:
5816 (define_expand "addsi3"
5817 [(match_operand:SI 0 "register_operand" "")
5818 (match_operand:SI 1 "register_operand" "")
5819 (match_operand:SI 2 "register_operand" "")]
5825 handle_add (operands[0], operands[1], operands[2]);
5831 Here is an example, the definition of left-shift for the SPUR chip:
5835 (define_expand "ashlsi3"
5836 [(set (match_operand:SI 0 "register_operand" "")
5840 (match_operand:SI 1 "register_operand" "")
5841 (match_operand:SI 2 "nonmemory_operand" "")))]
5850 if (GET_CODE (operands[2]) != CONST_INT
5851 || (unsigned) INTVAL (operands[2]) > 3)
5858 This example uses @code{define_expand} so that it can generate an RTL insn
5859 for shifting when the shift-count is in the supported range of 0 to 3 but
5860 fail in other cases where machine insns aren't available. When it fails,
5861 the compiler tries another strategy using different patterns (such as, a
5864 If the compiler were able to handle nontrivial condition-strings in
5865 patterns with names, then it would be possible to use a
5866 @code{define_insn} in that case. Here is another case (zero-extension
5867 on the 68000) which makes more use of the power of @code{define_expand}:
5870 (define_expand "zero_extendhisi2"
5871 [(set (match_operand:SI 0 "general_operand" "")
5873 (set (strict_low_part
5877 (match_operand:HI 1 "general_operand" ""))]
5879 "operands[1] = make_safe_from (operands[1], operands[0]);")
5883 @findex make_safe_from
5884 Here two RTL insns are generated, one to clear the entire output operand
5885 and the other to copy the input operand into its low half. This sequence
5886 is incorrect if the input operand refers to [the old value of] the output
5887 operand, so the preparation statement makes sure this isn't so. The
5888 function @code{make_safe_from} copies the @code{operands[1]} into a
5889 temporary register if it refers to @code{operands[0]}. It does this
5890 by emitting another RTL insn.
5892 Finally, a third example shows the use of an internal operand.
5893 Zero-extension on the SPUR chip is done by @code{and}-ing the result
5894 against a halfword mask. But this mask cannot be represented by a
5895 @code{const_int} because the constant value is too large to be legitimate
5896 on this machine. So it must be copied into a register with
5897 @code{force_reg} and then the register used in the @code{and}.
5900 (define_expand "zero_extendhisi2"
5901 [(set (match_operand:SI 0 "register_operand" "")
5903 (match_operand:HI 1 "register_operand" "")
5908 = force_reg (SImode, GEN_INT (65535)); ")
5911 @emph{Note:} If the @code{define_expand} is used to serve a
5912 standard binary or unary arithmetic operation or a bit-field operation,
5913 then the last insn it generates must not be a @code{code_label},
5914 @code{barrier} or @code{note}. It must be an @code{insn},
5915 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
5916 at the end, emit an insn to copy the result of the operation into
5917 itself. Such an insn will generate no code, but it can avoid problems
5922 @node Insn Splitting
5923 @section Defining How to Split Instructions
5924 @cindex insn splitting
5925 @cindex instruction splitting
5926 @cindex splitting instructions
5928 There are two cases where you should specify how to split a pattern
5929 into multiple insns. On machines that have instructions requiring
5930 delay slots (@pxref{Delay Slots}) or that have instructions whose
5931 output is not available for multiple cycles (@pxref{Processor pipeline
5932 description}), the compiler phases that optimize these cases need to
5933 be able to move insns into one-instruction delay slots. However, some
5934 insns may generate more than one machine instruction. These insns
5935 cannot be placed into a delay slot.
5937 Often you can rewrite the single insn as a list of individual insns,
5938 each corresponding to one machine instruction. The disadvantage of
5939 doing so is that it will cause the compilation to be slower and require
5940 more space. If the resulting insns are too complex, it may also
5941 suppress some optimizations. The compiler splits the insn if there is a
5942 reason to believe that it might improve instruction or delay slot
5945 The insn combiner phase also splits putative insns. If three insns are
5946 merged into one insn with a complex expression that cannot be matched by
5947 some @code{define_insn} pattern, the combiner phase attempts to split
5948 the complex pattern into two insns that are recognized. Usually it can
5949 break the complex pattern into two patterns by splitting out some
5950 subexpression. However, in some other cases, such as performing an
5951 addition of a large constant in two insns on a RISC machine, the way to
5952 split the addition into two insns is machine-dependent.
5954 @findex define_split
5955 The @code{define_split} definition tells the compiler how to split a
5956 complex insn into several simpler insns. It looks like this:
5960 [@var{insn-pattern}]
5962 [@var{new-insn-pattern-1}
5963 @var{new-insn-pattern-2}
5965 "@var{preparation-statements}")
5968 @var{insn-pattern} is a pattern that needs to be split and
5969 @var{condition} is the final condition to be tested, as in a
5970 @code{define_insn}. When an insn matching @var{insn-pattern} and
5971 satisfying @var{condition} is found, it is replaced in the insn list
5972 with the insns given by @var{new-insn-pattern-1},
5973 @var{new-insn-pattern-2}, etc.
5975 The @var{preparation-statements} are similar to those statements that
5976 are specified for @code{define_expand} (@pxref{Expander Definitions})
5977 and are executed before the new RTL is generated to prepare for the
5978 generated code or emit some insns whose pattern is not fixed. Unlike
5979 those in @code{define_expand}, however, these statements must not
5980 generate any new pseudo-registers. Once reload has completed, they also
5981 must not allocate any space in the stack frame.
5983 Patterns are matched against @var{insn-pattern} in two different
5984 circumstances. If an insn needs to be split for delay slot scheduling
5985 or insn scheduling, the insn is already known to be valid, which means
5986 that it must have been matched by some @code{define_insn} and, if
5987 @code{reload_completed} is nonzero, is known to satisfy the constraints
5988 of that @code{define_insn}. In that case, the new insn patterns must
5989 also be insns that are matched by some @code{define_insn} and, if
5990 @code{reload_completed} is nonzero, must also satisfy the constraints
5991 of those definitions.
5993 As an example of this usage of @code{define_split}, consider the following
5994 example from @file{a29k.md}, which splits a @code{sign_extend} from
5995 @code{HImode} to @code{SImode} into a pair of shift insns:
5999 [(set (match_operand:SI 0 "gen_reg_operand" "")
6000 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
6003 (ashift:SI (match_dup 1)
6006 (ashiftrt:SI (match_dup 0)
6009 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
6012 When the combiner phase tries to split an insn pattern, it is always the
6013 case that the pattern is @emph{not} matched by any @code{define_insn}.
6014 The combiner pass first tries to split a single @code{set} expression
6015 and then the same @code{set} expression inside a @code{parallel}, but
6016 followed by a @code{clobber} of a pseudo-reg to use as a scratch
6017 register. In these cases, the combiner expects exactly two new insn
6018 patterns to be generated. It will verify that these patterns match some
6019 @code{define_insn} definitions, so you need not do this test in the
6020 @code{define_split} (of course, there is no point in writing a
6021 @code{define_split} that will never produce insns that match).
6023 Here is an example of this use of @code{define_split}, taken from
6028 [(set (match_operand:SI 0 "gen_reg_operand" "")
6029 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
6030 (match_operand:SI 2 "non_add_cint_operand" "")))]
6032 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
6033 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
6036 int low = INTVAL (operands[2]) & 0xffff;
6037 int high = (unsigned) INTVAL (operands[2]) >> 16;
6040 high++, low |= 0xffff0000;
6042 operands[3] = GEN_INT (high << 16);
6043 operands[4] = GEN_INT (low);
6047 Here the predicate @code{non_add_cint_operand} matches any
6048 @code{const_int} that is @emph{not} a valid operand of a single add
6049 insn. The add with the smaller displacement is written so that it
6050 can be substituted into the address of a subsequent operation.
6052 An example that uses a scratch register, from the same file, generates
6053 an equality comparison of a register and a large constant:
6057 [(set (match_operand:CC 0 "cc_reg_operand" "")
6058 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
6059 (match_operand:SI 2 "non_short_cint_operand" "")))
6060 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
6061 "find_single_use (operands[0], insn, 0)
6062 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
6063 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
6064 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
6065 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
6068 /* @r{Get the constant we are comparing against, C, and see what it
6069 looks like sign-extended to 16 bits. Then see what constant
6070 could be XOR'ed with C to get the sign-extended value.} */
6072 int c = INTVAL (operands[2]);
6073 int sextc = (c << 16) >> 16;
6074 int xorv = c ^ sextc;
6076 operands[4] = GEN_INT (xorv);
6077 operands[5] = GEN_INT (sextc);
6081 To avoid confusion, don't write a single @code{define_split} that
6082 accepts some insns that match some @code{define_insn} as well as some
6083 insns that don't. Instead, write two separate @code{define_split}
6084 definitions, one for the insns that are valid and one for the insns that
6087 The splitter is allowed to split jump instructions into sequence of
6088 jumps or create new jumps in while splitting non-jump instructions. As
6089 the central flowgraph and branch prediction information needs to be updated,
6090 several restriction apply.
6092 Splitting of jump instruction into sequence that over by another jump
6093 instruction is always valid, as compiler expect identical behavior of new
6094 jump. When new sequence contains multiple jump instructions or new labels,
6095 more assistance is needed. Splitter is required to create only unconditional
6096 jumps, or simple conditional jump instructions. Additionally it must attach a
6097 @code{REG_BR_PROB} note to each conditional jump. A global variable
6098 @code{split_branch_probability} holds the probability of the original branch in case
6099 it was a simple conditional jump, @minus{}1 otherwise. To simplify
6100 recomputing of edge frequencies, the new sequence is required to have only
6101 forward jumps to the newly created labels.
6103 @findex define_insn_and_split
6104 For the common case where the pattern of a define_split exactly matches the
6105 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
6109 (define_insn_and_split
6110 [@var{insn-pattern}]
6112 "@var{output-template}"
6113 "@var{split-condition}"
6114 [@var{new-insn-pattern-1}
6115 @var{new-insn-pattern-2}
6117 "@var{preparation-statements}"
6118 [@var{insn-attributes}])
6122 @var{insn-pattern}, @var{condition}, @var{output-template}, and
6123 @var{insn-attributes} are used as in @code{define_insn}. The
6124 @var{new-insn-pattern} vector and the @var{preparation-statements} are used as
6125 in a @code{define_split}. The @var{split-condition} is also used as in
6126 @code{define_split}, with the additional behavior that if the condition starts
6127 with @samp{&&}, the condition used for the split will be the constructed as a
6128 logical ``and'' of the split condition with the insn condition. For example,
6132 (define_insn_and_split "zero_extendhisi2_and"
6133 [(set (match_operand:SI 0 "register_operand" "=r")
6134 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
6135 (clobber (reg:CC 17))]
6136 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
6138 "&& reload_completed"
6139 [(parallel [(set (match_dup 0)
6140 (and:SI (match_dup 0) (const_int 65535)))
6141 (clobber (reg:CC 17))])]
6143 [(set_attr "type" "alu1")])
6147 In this case, the actual split condition will be
6148 @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
6150 The @code{define_insn_and_split} construction provides exactly the same
6151 functionality as two separate @code{define_insn} and @code{define_split}
6152 patterns. It exists for compactness, and as a maintenance tool to prevent
6153 having to ensure the two patterns' templates match.
6157 @node Including Patterns
6158 @section Including Patterns in Machine Descriptions.
6159 @cindex insn includes
6162 The @code{include} pattern tells the compiler tools where to
6163 look for patterns that are in files other than in the file
6164 @file{.md}. This is used only at build time and there is no preprocessing allowed.
6178 (include "filestuff")
6182 Where @var{pathname} is a string that specifies the location of the file,
6183 specifies the include file to be in @file{gcc/config/target/filestuff}. The
6184 directory @file{gcc/config/target} is regarded as the default directory.
6187 Machine descriptions may be split up into smaller more manageable subsections
6188 and placed into subdirectories.
6194 (include "BOGUS/filestuff")
6198 the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}.
6200 Specifying an absolute path for the include file such as;
6203 (include "/u2/BOGUS/filestuff")
6206 is permitted but is not encouraged.
6208 @subsection RTL Generation Tool Options for Directory Search
6209 @cindex directory options .md
6210 @cindex options, directory search
6211 @cindex search options
6213 The @option{-I@var{dir}} option specifies directories to search for machine descriptions.
6218 genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md
6223 Add the directory @var{dir} to the head of the list of directories to be
6224 searched for header files. This can be used to override a system machine definition
6225 file, substituting your own version, since these directories are
6226 searched before the default machine description file directories. If you use more than
6227 one @option{-I} option, the directories are scanned in left-to-right
6228 order; the standard default directory come after.
6233 @node Peephole Definitions
6234 @section Machine-Specific Peephole Optimizers
6235 @cindex peephole optimizer definitions
6236 @cindex defining peephole optimizers
6238 In addition to instruction patterns the @file{md} file may contain
6239 definitions of machine-specific peephole optimizations.
6241 The combiner does not notice certain peephole optimizations when the data
6242 flow in the program does not suggest that it should try them. For example,
6243 sometimes two consecutive insns related in purpose can be combined even
6244 though the second one does not appear to use a register computed in the
6245 first one. A machine-specific peephole optimizer can detect such
6248 There are two forms of peephole definitions that may be used. The
6249 original @code{define_peephole} is run at assembly output time to
6250 match insns and substitute assembly text. Use of @code{define_peephole}
6253 A newer @code{define_peephole2} matches insns and substitutes new
6254 insns. The @code{peephole2} pass is run after register allocation
6255 but before scheduling, which may result in much better code for
6256 targets that do scheduling.
6259 * define_peephole:: RTL to Text Peephole Optimizers
6260 * define_peephole2:: RTL to RTL Peephole Optimizers
6265 @node define_peephole
6266 @subsection RTL to Text Peephole Optimizers
6267 @findex define_peephole
6270 A definition looks like this:
6274 [@var{insn-pattern-1}
6275 @var{insn-pattern-2}
6279 "@var{optional-insn-attributes}")
6283 The last string operand may be omitted if you are not using any
6284 machine-specific information in this machine description. If present,
6285 it must obey the same rules as in a @code{define_insn}.
6287 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
6288 consecutive insns. The optimization applies to a sequence of insns when
6289 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
6290 the next, and so on.
6292 Each of the insns matched by a peephole must also match a
6293 @code{define_insn}. Peepholes are checked only at the last stage just
6294 before code generation, and only optionally. Therefore, any insn which
6295 would match a peephole but no @code{define_insn} will cause a crash in code
6296 generation in an unoptimized compilation, or at various optimization
6299 The operands of the insns are matched with @code{match_operands},
6300 @code{match_operator}, and @code{match_dup}, as usual. What is not
6301 usual is that the operand numbers apply to all the insn patterns in the
6302 definition. So, you can check for identical operands in two insns by
6303 using @code{match_operand} in one insn and @code{match_dup} in the
6306 The operand constraints used in @code{match_operand} patterns do not have
6307 any direct effect on the applicability of the peephole, but they will
6308 be validated afterward, so make sure your constraints are general enough
6309 to apply whenever the peephole matches. If the peephole matches
6310 but the constraints are not satisfied, the compiler will crash.
6312 It is safe to omit constraints in all the operands of the peephole; or
6313 you can write constraints which serve as a double-check on the criteria
6316 Once a sequence of insns matches the patterns, the @var{condition} is
6317 checked. This is a C expression which makes the final decision whether to
6318 perform the optimization (we do so if the expression is nonzero). If
6319 @var{condition} is omitted (in other words, the string is empty) then the
6320 optimization is applied to every sequence of insns that matches the
6323 The defined peephole optimizations are applied after register allocation
6324 is complete. Therefore, the peephole definition can check which
6325 operands have ended up in which kinds of registers, just by looking at
6328 @findex prev_active_insn
6329 The way to refer to the operands in @var{condition} is to write
6330 @code{operands[@var{i}]} for operand number @var{i} (as matched by
6331 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
6332 to refer to the last of the insns being matched; use
6333 @code{prev_active_insn} to find the preceding insns.
6335 @findex dead_or_set_p
6336 When optimizing computations with intermediate results, you can use
6337 @var{condition} to match only when the intermediate results are not used
6338 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
6339 @var{op})}, where @var{insn} is the insn in which you expect the value
6340 to be used for the last time (from the value of @code{insn}, together
6341 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
6342 value (from @code{operands[@var{i}]}).
6344 Applying the optimization means replacing the sequence of insns with one
6345 new insn. The @var{template} controls ultimate output of assembler code
6346 for this combined insn. It works exactly like the template of a
6347 @code{define_insn}. Operand numbers in this template are the same ones
6348 used in matching the original sequence of insns.
6350 The result of a defined peephole optimizer does not need to match any of
6351 the insn patterns in the machine description; it does not even have an
6352 opportunity to match them. The peephole optimizer definition itself serves
6353 as the insn pattern to control how the insn is output.
6355 Defined peephole optimizers are run as assembler code is being output,
6356 so the insns they produce are never combined or rearranged in any way.
6358 Here is an example, taken from the 68000 machine description:
6362 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
6363 (set (match_operand:DF 0 "register_operand" "=f")
6364 (match_operand:DF 1 "register_operand" "ad"))]
6365 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
6368 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
6370 output_asm_insn ("move.l %1,(sp)", xoperands);
6371 output_asm_insn ("move.l %1,-(sp)", operands);
6372 return "fmove.d (sp)+,%0";
6374 output_asm_insn ("movel %1,sp@@", xoperands);
6375 output_asm_insn ("movel %1,sp@@-", operands);
6376 return "fmoved sp@@+,%0";
6382 The effect of this optimization is to change
6408 If a peephole matches a sequence including one or more jump insns, you must
6409 take account of the flags such as @code{CC_REVERSED} which specify that the
6410 condition codes are represented in an unusual manner. The compiler
6411 automatically alters any ordinary conditional jumps which occur in such
6412 situations, but the compiler cannot alter jumps which have been replaced by
6413 peephole optimizations. So it is up to you to alter the assembler code
6414 that the peephole produces. Supply C code to write the assembler output,
6415 and in this C code check the condition code status flags and change the
6416 assembler code as appropriate.
6419 @var{insn-pattern-1} and so on look @emph{almost} like the second
6420 operand of @code{define_insn}. There is one important difference: the
6421 second operand of @code{define_insn} consists of one or more RTX's
6422 enclosed in square brackets. Usually, there is only one: then the same
6423 action can be written as an element of a @code{define_peephole}. But
6424 when there are multiple actions in a @code{define_insn}, they are
6425 implicitly enclosed in a @code{parallel}. Then you must explicitly
6426 write the @code{parallel}, and the square brackets within it, in the
6427 @code{define_peephole}. Thus, if an insn pattern looks like this,
6430 (define_insn "divmodsi4"
6431 [(set (match_operand:SI 0 "general_operand" "=d")
6432 (div:SI (match_operand:SI 1 "general_operand" "0")
6433 (match_operand:SI 2 "general_operand" "dmsK")))
6434 (set (match_operand:SI 3 "general_operand" "=d")
6435 (mod:SI (match_dup 1) (match_dup 2)))]
6437 "divsl%.l %2,%3:%0")
6441 then the way to mention this insn in a peephole is as follows:
6447 [(set (match_operand:SI 0 "general_operand" "=d")
6448 (div:SI (match_operand:SI 1 "general_operand" "0")
6449 (match_operand:SI 2 "general_operand" "dmsK")))
6450 (set (match_operand:SI 3 "general_operand" "=d")
6451 (mod:SI (match_dup 1) (match_dup 2)))])
6458 @node define_peephole2
6459 @subsection RTL to RTL Peephole Optimizers
6460 @findex define_peephole2
6462 The @code{define_peephole2} definition tells the compiler how to
6463 substitute one sequence of instructions for another sequence,
6464 what additional scratch registers may be needed and what their
6469 [@var{insn-pattern-1}
6470 @var{insn-pattern-2}
6473 [@var{new-insn-pattern-1}
6474 @var{new-insn-pattern-2}
6476 "@var{preparation-statements}")
6479 The definition is almost identical to @code{define_split}
6480 (@pxref{Insn Splitting}) except that the pattern to match is not a
6481 single instruction, but a sequence of instructions.
6483 It is possible to request additional scratch registers for use in the
6484 output template. If appropriate registers are not free, the pattern
6485 will simply not match.
6487 @findex match_scratch
6489 Scratch registers are requested with a @code{match_scratch} pattern at
6490 the top level of the input pattern. The allocated register (initially) will
6491 be dead at the point requested within the original sequence. If the scratch
6492 is used at more than a single point, a @code{match_dup} pattern at the
6493 top level of the input pattern marks the last position in the input sequence
6494 at which the register must be available.
6496 Here is an example from the IA-32 machine description:
6500 [(match_scratch:SI 2 "r")
6501 (parallel [(set (match_operand:SI 0 "register_operand" "")
6502 (match_operator:SI 3 "arith_or_logical_operator"
6504 (match_operand:SI 1 "memory_operand" "")]))
6505 (clobber (reg:CC 17))])]
6506 "! optimize_size && ! TARGET_READ_MODIFY"
6507 [(set (match_dup 2) (match_dup 1))
6508 (parallel [(set (match_dup 0)
6509 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
6510 (clobber (reg:CC 17))])]
6515 This pattern tries to split a load from its use in the hopes that we'll be
6516 able to schedule around the memory load latency. It allocates a single
6517 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
6518 to be live only at the point just before the arithmetic.
6520 A real example requiring extended scratch lifetimes is harder to come by,
6521 so here's a silly made-up example:
6525 [(match_scratch:SI 4 "r")
6526 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
6527 (set (match_operand:SI 2 "" "") (match_dup 1))
6529 (set (match_operand:SI 3 "" "") (match_dup 1))]
6530 "/* @r{determine 1 does not overlap 0 and 2} */"
6531 [(set (match_dup 4) (match_dup 1))
6532 (set (match_dup 0) (match_dup 4))
6533 (set (match_dup 2) (match_dup 4))]
6534 (set (match_dup 3) (match_dup 4))]
6539 If we had not added the @code{(match_dup 4)} in the middle of the input
6540 sequence, it might have been the case that the register we chose at the
6541 beginning of the sequence is killed by the first or second @code{set}.
6545 @node Insn Attributes
6546 @section Instruction Attributes
6547 @cindex insn attributes
6548 @cindex instruction attributes
6550 In addition to describing the instruction supported by the target machine,
6551 the @file{md} file also defines a group of @dfn{attributes} and a set of
6552 values for each. Every generated insn is assigned a value for each attribute.
6553 One possible attribute would be the effect that the insn has on the machine's
6554 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
6555 to track the condition codes.
6558 * Defining Attributes:: Specifying attributes and their values.
6559 * Expressions:: Valid expressions for attribute values.
6560 * Tagging Insns:: Assigning attribute values to insns.
6561 * Attr Example:: An example of assigning attributes.
6562 * Insn Lengths:: Computing the length of insns.
6563 * Constant Attributes:: Defining attributes that are constant.
6564 * Delay Slots:: Defining delay slots required for a machine.
6565 * Processor pipeline description:: Specifying information for insn scheduling.
6570 @node Defining Attributes
6571 @subsection Defining Attributes and their Values
6572 @cindex defining attributes and their values
6573 @cindex attributes, defining
6576 The @code{define_attr} expression is used to define each attribute required
6577 by the target machine. It looks like:
6580 (define_attr @var{name} @var{list-of-values} @var{default})
6583 @var{name} is a string specifying the name of the attribute being defined.
6585 @var{list-of-values} is either a string that specifies a comma-separated
6586 list of values that can be assigned to the attribute, or a null string to
6587 indicate that the attribute takes numeric values.
6589 @var{default} is an attribute expression that gives the value of this
6590 attribute for insns that match patterns whose definition does not include
6591 an explicit value for this attribute. @xref{Attr Example}, for more
6592 information on the handling of defaults. @xref{Constant Attributes},
6593 for information on attributes that do not depend on any particular insn.
6596 For each defined attribute, a number of definitions are written to the
6597 @file{insn-attr.h} file. For cases where an explicit set of values is
6598 specified for an attribute, the following are defined:
6602 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
6605 An enumerated class is defined for @samp{attr_@var{name}} with
6606 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
6607 the attribute name and value are first converted to uppercase.
6610 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
6611 returns the attribute value for that insn.
6614 For example, if the following is present in the @file{md} file:
6617 (define_attr "type" "branch,fp,load,store,arith" @dots{})
6621 the following lines will be written to the file @file{insn-attr.h}.
6624 #define HAVE_ATTR_type
6625 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
6626 TYPE_STORE, TYPE_ARITH@};
6627 extern enum attr_type get_attr_type ();
6630 If the attribute takes numeric values, no @code{enum} type will be
6631 defined and the function to obtain the attribute's value will return
6634 There are attributes which are tied to a specific meaning. These
6635 attributes are not free to use for other purposes:
6639 The @code{length} attribute is used to calculate the length of emitted
6640 code chunks. This is especially important when verifying branch
6641 distances. @xref{Insn Lengths}.
6644 The @code{enabled} attribute can be defined to prevent certain
6645 alternatives of an insn definition from being used during code
6646 generation. @xref{Disable Insn Alternatives}.
6653 @subsection Attribute Expressions
6654 @cindex attribute expressions
6656 RTL expressions used to define attributes use the codes described above
6657 plus a few specific to attribute definitions, to be discussed below.
6658 Attribute value expressions must have one of the following forms:
6661 @cindex @code{const_int} and attributes
6662 @item (const_int @var{i})
6663 The integer @var{i} specifies the value of a numeric attribute. @var{i}
6664 must be non-negative.
6666 The value of a numeric attribute can be specified either with a
6667 @code{const_int}, or as an integer represented as a string in
6668 @code{const_string}, @code{eq_attr} (see below), @code{attr},
6669 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
6670 overrides on specific instructions (@pxref{Tagging Insns}).
6672 @cindex @code{const_string} and attributes
6673 @item (const_string @var{value})
6674 The string @var{value} specifies a constant attribute value.
6675 If @var{value} is specified as @samp{"*"}, it means that the default value of
6676 the attribute is to be used for the insn containing this expression.
6677 @samp{"*"} obviously cannot be used in the @var{default} expression
6678 of a @code{define_attr}.
6680 If the attribute whose value is being specified is numeric, @var{value}
6681 must be a string containing a non-negative integer (normally
6682 @code{const_int} would be used in this case). Otherwise, it must
6683 contain one of the valid values for the attribute.
6685 @cindex @code{if_then_else} and attributes
6686 @item (if_then_else @var{test} @var{true-value} @var{false-value})
6687 @var{test} specifies an attribute test, whose format is defined below.
6688 The value of this expression is @var{true-value} if @var{test} is true,
6689 otherwise it is @var{false-value}.
6691 @cindex @code{cond} and attributes
6692 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
6693 The first operand of this expression is a vector containing an even
6694 number of expressions and consisting of pairs of @var{test} and @var{value}
6695 expressions. The value of the @code{cond} expression is that of the
6696 @var{value} corresponding to the first true @var{test} expression. If
6697 none of the @var{test} expressions are true, the value of the @code{cond}
6698 expression is that of the @var{default} expression.
6701 @var{test} expressions can have one of the following forms:
6704 @cindex @code{const_int} and attribute tests
6705 @item (const_int @var{i})
6706 This test is true if @var{i} is nonzero and false otherwise.
6708 @cindex @code{not} and attributes
6709 @cindex @code{ior} and attributes
6710 @cindex @code{and} and attributes
6711 @item (not @var{test})
6712 @itemx (ior @var{test1} @var{test2})
6713 @itemx (and @var{test1} @var{test2})
6714 These tests are true if the indicated logical function is true.
6716 @cindex @code{match_operand} and attributes
6717 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
6718 This test is true if operand @var{n} of the insn whose attribute value
6719 is being determined has mode @var{m} (this part of the test is ignored
6720 if @var{m} is @code{VOIDmode}) and the function specified by the string
6721 @var{pred} returns a nonzero value when passed operand @var{n} and mode
6722 @var{m} (this part of the test is ignored if @var{pred} is the null
6725 The @var{constraints} operand is ignored and should be the null string.
6727 @cindex @code{le} and attributes
6728 @cindex @code{leu} and attributes
6729 @cindex @code{lt} and attributes
6730 @cindex @code{gt} and attributes
6731 @cindex @code{gtu} and attributes
6732 @cindex @code{ge} and attributes
6733 @cindex @code{geu} and attributes
6734 @cindex @code{ne} and attributes
6735 @cindex @code{eq} and attributes
6736 @cindex @code{plus} and attributes
6737 @cindex @code{minus} and attributes
6738 @cindex @code{mult} and attributes
6739 @cindex @code{div} and attributes
6740 @cindex @code{mod} and attributes
6741 @cindex @code{abs} and attributes
6742 @cindex @code{neg} and attributes
6743 @cindex @code{ashift} and attributes
6744 @cindex @code{lshiftrt} and attributes
6745 @cindex @code{ashiftrt} and attributes
6746 @item (le @var{arith1} @var{arith2})
6747 @itemx (leu @var{arith1} @var{arith2})
6748 @itemx (lt @var{arith1} @var{arith2})
6749 @itemx (ltu @var{arith1} @var{arith2})
6750 @itemx (gt @var{arith1} @var{arith2})
6751 @itemx (gtu @var{arith1} @var{arith2})
6752 @itemx (ge @var{arith1} @var{arith2})
6753 @itemx (geu @var{arith1} @var{arith2})
6754 @itemx (ne @var{arith1} @var{arith2})
6755 @itemx (eq @var{arith1} @var{arith2})
6756 These tests are true if the indicated comparison of the two arithmetic
6757 expressions is true. Arithmetic expressions are formed with
6758 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
6759 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
6760 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
6763 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
6764 Lengths},for additional forms). @code{symbol_ref} is a string
6765 denoting a C expression that yields an @code{int} when evaluated by the
6766 @samp{get_attr_@dots{}} routine. It should normally be a global
6770 @item (eq_attr @var{name} @var{value})
6771 @var{name} is a string specifying the name of an attribute.
6773 @var{value} is a string that is either a valid value for attribute
6774 @var{name}, a comma-separated list of values, or @samp{!} followed by a
6775 value or list. If @var{value} does not begin with a @samp{!}, this
6776 test is true if the value of the @var{name} attribute of the current
6777 insn is in the list specified by @var{value}. If @var{value} begins
6778 with a @samp{!}, this test is true if the attribute's value is
6779 @emph{not} in the specified list.
6784 (eq_attr "type" "load,store")
6791 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
6794 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
6795 value of the compiler variable @code{which_alternative}
6796 (@pxref{Output Statement}) and the values must be small integers. For
6800 (eq_attr "alternative" "2,3")
6807 (ior (eq (symbol_ref "which_alternative") (const_int 2))
6808 (eq (symbol_ref "which_alternative") (const_int 3)))
6811 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
6812 where the value of the attribute being tested is known for all insns matching
6813 a particular pattern. This is by far the most common case.
6816 @item (attr_flag @var{name})
6817 The value of an @code{attr_flag} expression is true if the flag
6818 specified by @var{name} is true for the @code{insn} currently being
6821 @var{name} is a string specifying one of a fixed set of flags to test.
6822 Test the flags @code{forward} and @code{backward} to determine the
6823 direction of a conditional branch. Test the flags @code{very_likely},
6824 @code{likely}, @code{very_unlikely}, and @code{unlikely} to determine
6825 if a conditional branch is expected to be taken.
6827 If the @code{very_likely} flag is true, then the @code{likely} flag is also
6828 true. Likewise for the @code{very_unlikely} and @code{unlikely} flags.
6830 This example describes a conditional branch delay slot which
6831 can be nullified for forward branches that are taken (annul-true) or
6832 for backward branches which are not taken (annul-false).
6835 (define_delay (eq_attr "type" "cbranch")
6836 [(eq_attr "in_branch_delay" "true")
6837 (and (eq_attr "in_branch_delay" "true")
6838 (attr_flag "forward"))
6839 (and (eq_attr "in_branch_delay" "true")
6840 (attr_flag "backward"))])
6843 The @code{forward} and @code{backward} flags are false if the current
6844 @code{insn} being scheduled is not a conditional branch.
6846 The @code{very_likely} and @code{likely} flags are true if the
6847 @code{insn} being scheduled is not a conditional branch.
6848 The @code{very_unlikely} and @code{unlikely} flags are false if the
6849 @code{insn} being scheduled is not a conditional branch.
6851 @code{attr_flag} is only used during delay slot scheduling and has no
6852 meaning to other passes of the compiler.
6855 @item (attr @var{name})
6856 The value of another attribute is returned. This is most useful
6857 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
6858 produce more efficient code for non-numeric attributes.
6864 @subsection Assigning Attribute Values to Insns
6865 @cindex tagging insns
6866 @cindex assigning attribute values to insns
6868 The value assigned to an attribute of an insn is primarily determined by
6869 which pattern is matched by that insn (or which @code{define_peephole}
6870 generated it). Every @code{define_insn} and @code{define_peephole} can
6871 have an optional last argument to specify the values of attributes for
6872 matching insns. The value of any attribute not specified in a particular
6873 insn is set to the default value for that attribute, as specified in its
6874 @code{define_attr}. Extensive use of default values for attributes
6875 permits the specification of the values for only one or two attributes
6876 in the definition of most insn patterns, as seen in the example in the
6879 The optional last argument of @code{define_insn} and
6880 @code{define_peephole} is a vector of expressions, each of which defines
6881 the value for a single attribute. The most general way of assigning an
6882 attribute's value is to use a @code{set} expression whose first operand is an
6883 @code{attr} expression giving the name of the attribute being set. The
6884 second operand of the @code{set} is an attribute expression
6885 (@pxref{Expressions}) giving the value of the attribute.
6887 When the attribute value depends on the @samp{alternative} attribute
6888 (i.e., which is the applicable alternative in the constraint of the
6889 insn), the @code{set_attr_alternative} expression can be used. It
6890 allows the specification of a vector of attribute expressions, one for
6894 When the generality of arbitrary attribute expressions is not required,
6895 the simpler @code{set_attr} expression can be used, which allows
6896 specifying a string giving either a single attribute value or a list
6897 of attribute values, one for each alternative.
6899 The form of each of the above specifications is shown below. In each case,
6900 @var{name} is a string specifying the attribute to be set.
6903 @item (set_attr @var{name} @var{value-string})
6904 @var{value-string} is either a string giving the desired attribute value,
6905 or a string containing a comma-separated list giving the values for
6906 succeeding alternatives. The number of elements must match the number
6907 of alternatives in the constraint of the insn pattern.
6909 Note that it may be useful to specify @samp{*} for some alternative, in
6910 which case the attribute will assume its default value for insns matching
6913 @findex set_attr_alternative
6914 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
6915 Depending on the alternative of the insn, the value will be one of the
6916 specified values. This is a shorthand for using a @code{cond} with
6917 tests on the @samp{alternative} attribute.
6920 @item (set (attr @var{name}) @var{value})
6921 The first operand of this @code{set} must be the special RTL expression
6922 @code{attr}, whose sole operand is a string giving the name of the
6923 attribute being set. @var{value} is the value of the attribute.
6926 The following shows three different ways of representing the same
6927 attribute value specification:
6930 (set_attr "type" "load,store,arith")
6932 (set_attr_alternative "type"
6933 [(const_string "load") (const_string "store")
6934 (const_string "arith")])
6937 (cond [(eq_attr "alternative" "1") (const_string "load")
6938 (eq_attr "alternative" "2") (const_string "store")]
6939 (const_string "arith")))
6943 @findex define_asm_attributes
6944 The @code{define_asm_attributes} expression provides a mechanism to
6945 specify the attributes assigned to insns produced from an @code{asm}
6946 statement. It has the form:
6949 (define_asm_attributes [@var{attr-sets}])
6953 where @var{attr-sets} is specified the same as for both the
6954 @code{define_insn} and the @code{define_peephole} expressions.
6956 These values will typically be the ``worst case'' attribute values. For
6957 example, they might indicate that the condition code will be clobbered.
6959 A specification for a @code{length} attribute is handled specially. The
6960 way to compute the length of an @code{asm} insn is to multiply the
6961 length specified in the expression @code{define_asm_attributes} by the
6962 number of machine instructions specified in the @code{asm} statement,
6963 determined by counting the number of semicolons and newlines in the
6964 string. Therefore, the value of the @code{length} attribute specified
6965 in a @code{define_asm_attributes} should be the maximum possible length
6966 of a single machine instruction.
6971 @subsection Example of Attribute Specifications
6972 @cindex attribute specifications example
6973 @cindex attribute specifications
6975 The judicious use of defaulting is important in the efficient use of
6976 insn attributes. Typically, insns are divided into @dfn{types} and an
6977 attribute, customarily called @code{type}, is used to represent this
6978 value. This attribute is normally used only to define the default value
6979 for other attributes. An example will clarify this usage.
6981 Assume we have a RISC machine with a condition code and in which only
6982 full-word operations are performed in registers. Let us assume that we
6983 can divide all insns into loads, stores, (integer) arithmetic
6984 operations, floating point operations, and branches.
6986 Here we will concern ourselves with determining the effect of an insn on
6987 the condition code and will limit ourselves to the following possible
6988 effects: The condition code can be set unpredictably (clobbered), not
6989 be changed, be set to agree with the results of the operation, or only
6990 changed if the item previously set into the condition code has been
6993 Here is part of a sample @file{md} file for such a machine:
6996 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
6998 (define_attr "cc" "clobber,unchanged,set,change0"
6999 (cond [(eq_attr "type" "load")
7000 (const_string "change0")
7001 (eq_attr "type" "store,branch")
7002 (const_string "unchanged")
7003 (eq_attr "type" "arith")
7004 (if_then_else (match_operand:SI 0 "" "")
7005 (const_string "set")
7006 (const_string "clobber"))]
7007 (const_string "clobber")))
7010 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
7011 (match_operand:SI 1 "general_operand" "r,m,r"))]
7017 [(set_attr "type" "arith,load,store")])
7020 Note that we assume in the above example that arithmetic operations
7021 performed on quantities smaller than a machine word clobber the condition
7022 code since they will set the condition code to a value corresponding to the
7028 @subsection Computing the Length of an Insn
7029 @cindex insn lengths, computing
7030 @cindex computing the length of an insn
7032 For many machines, multiple types of branch instructions are provided, each
7033 for different length branch displacements. In most cases, the assembler
7034 will choose the correct instruction to use. However, when the assembler
7035 cannot do so, GCC can when a special attribute, the @code{length}
7036 attribute, is defined. This attribute must be defined to have numeric
7037 values by specifying a null string in its @code{define_attr}.
7039 In the case of the @code{length} attribute, two additional forms of
7040 arithmetic terms are allowed in test expressions:
7043 @cindex @code{match_dup} and attributes
7044 @item (match_dup @var{n})
7045 This refers to the address of operand @var{n} of the current insn, which
7046 must be a @code{label_ref}.
7048 @cindex @code{pc} and attributes
7050 This refers to the address of the @emph{current} insn. It might have
7051 been more consistent with other usage to make this the address of the
7052 @emph{next} insn but this would be confusing because the length of the
7053 current insn is to be computed.
7056 @cindex @code{addr_vec}, length of
7057 @cindex @code{addr_diff_vec}, length of
7058 For normal insns, the length will be determined by value of the
7059 @code{length} attribute. In the case of @code{addr_vec} and
7060 @code{addr_diff_vec} insn patterns, the length is computed as
7061 the number of vectors multiplied by the size of each vector.
7063 Lengths are measured in addressable storage units (bytes).
7065 The following macros can be used to refine the length computation:
7068 @findex ADJUST_INSN_LENGTH
7069 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
7070 If defined, modifies the length assigned to instruction @var{insn} as a
7071 function of the context in which it is used. @var{length} is an lvalue
7072 that contains the initially computed length of the insn and should be
7073 updated with the correct length of the insn.
7075 This macro will normally not be required. A case in which it is
7076 required is the ROMP@. On this machine, the size of an @code{addr_vec}
7077 insn must be increased by two to compensate for the fact that alignment
7081 @findex get_attr_length
7082 The routine that returns @code{get_attr_length} (the value of the
7083 @code{length} attribute) can be used by the output routine to
7084 determine the form of the branch instruction to be written, as the
7085 example below illustrates.
7087 As an example of the specification of variable-length branches, consider
7088 the IBM 360. If we adopt the convention that a register will be set to
7089 the starting address of a function, we can jump to labels within 4k of
7090 the start using a four-byte instruction. Otherwise, we need a six-byte
7091 sequence to load the address from memory and then branch to it.
7093 On such a machine, a pattern for a branch instruction might be specified
7099 (label_ref (match_operand 0 "" "")))]
7102 return (get_attr_length (insn) == 4
7103 ? "b %l0" : "l r15,=a(%l0); br r15");
7105 [(set (attr "length")
7106 (if_then_else (lt (match_dup 0) (const_int 4096))
7113 @node Constant Attributes
7114 @subsection Constant Attributes
7115 @cindex constant attributes
7117 A special form of @code{define_attr}, where the expression for the
7118 default value is a @code{const} expression, indicates an attribute that
7119 is constant for a given run of the compiler. Constant attributes may be
7120 used to specify which variety of processor is used. For example,
7123 (define_attr "cpu" "m88100,m88110,m88000"
7125 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
7126 (symbol_ref "TARGET_88110") (const_string "m88110")]
7127 (const_string "m88000"))))
7129 (define_attr "memory" "fast,slow"
7131 (if_then_else (symbol_ref "TARGET_FAST_MEM")
7132 (const_string "fast")
7133 (const_string "slow"))))
7136 The routine generated for constant attributes has no parameters as it
7137 does not depend on any particular insn. RTL expressions used to define
7138 the value of a constant attribute may use the @code{symbol_ref} form,
7139 but may not use either the @code{match_operand} form or @code{eq_attr}
7140 forms involving insn attributes.
7145 @subsection Delay Slot Scheduling
7146 @cindex delay slots, defining
7148 The insn attribute mechanism can be used to specify the requirements for
7149 delay slots, if any, on a target machine. An instruction is said to
7150 require a @dfn{delay slot} if some instructions that are physically
7151 after the instruction are executed as if they were located before it.
7152 Classic examples are branch and call instructions, which often execute
7153 the following instruction before the branch or call is performed.
7155 On some machines, conditional branch instructions can optionally
7156 @dfn{annul} instructions in the delay slot. This means that the
7157 instruction will not be executed for certain branch outcomes. Both
7158 instructions that annul if the branch is true and instructions that
7159 annul if the branch is false are supported.
7161 Delay slot scheduling differs from instruction scheduling in that
7162 determining whether an instruction needs a delay slot is dependent only
7163 on the type of instruction being generated, not on data flow between the
7164 instructions. See the next section for a discussion of data-dependent
7165 instruction scheduling.
7167 @findex define_delay
7168 The requirement of an insn needing one or more delay slots is indicated
7169 via the @code{define_delay} expression. It has the following form:
7172 (define_delay @var{test}
7173 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
7174 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
7178 @var{test} is an attribute test that indicates whether this
7179 @code{define_delay} applies to a particular insn. If so, the number of
7180 required delay slots is determined by the length of the vector specified
7181 as the second argument. An insn placed in delay slot @var{n} must
7182 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
7183 attribute test that specifies which insns may be annulled if the branch
7184 is true. Similarly, @var{annul-false-n} specifies which insns in the
7185 delay slot may be annulled if the branch is false. If annulling is not
7186 supported for that delay slot, @code{(nil)} should be coded.
7188 For example, in the common case where branch and call insns require
7189 a single delay slot, which may contain any insn other than a branch or
7190 call, the following would be placed in the @file{md} file:
7193 (define_delay (eq_attr "type" "branch,call")
7194 [(eq_attr "type" "!branch,call") (nil) (nil)])
7197 Multiple @code{define_delay} expressions may be specified. In this
7198 case, each such expression specifies different delay slot requirements
7199 and there must be no insn for which tests in two @code{define_delay}
7200 expressions are both true.
7202 For example, if we have a machine that requires one delay slot for branches
7203 but two for calls, no delay slot can contain a branch or call insn,
7204 and any valid insn in the delay slot for the branch can be annulled if the
7205 branch is true, we might represent this as follows:
7208 (define_delay (eq_attr "type" "branch")
7209 [(eq_attr "type" "!branch,call")
7210 (eq_attr "type" "!branch,call")
7213 (define_delay (eq_attr "type" "call")
7214 [(eq_attr "type" "!branch,call") (nil) (nil)
7215 (eq_attr "type" "!branch,call") (nil) (nil)])
7217 @c the above is *still* too long. --mew 4feb93
7221 @node Processor pipeline description
7222 @subsection Specifying processor pipeline description
7223 @cindex processor pipeline description
7224 @cindex processor functional units
7225 @cindex instruction latency time
7226 @cindex interlock delays
7227 @cindex data dependence delays
7228 @cindex reservation delays
7229 @cindex pipeline hazard recognizer
7230 @cindex automaton based pipeline description
7231 @cindex regular expressions
7232 @cindex deterministic finite state automaton
7233 @cindex automaton based scheduler
7237 To achieve better performance, most modern processors
7238 (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW}
7239 processors) have many @dfn{functional units} on which several
7240 instructions can be executed simultaneously. An instruction starts
7241 execution if its issue conditions are satisfied. If not, the
7242 instruction is stalled until its conditions are satisfied. Such
7243 @dfn{interlock (pipeline) delay} causes interruption of the fetching
7244 of successor instructions (or demands nop instructions, e.g.@: for some
7247 There are two major kinds of interlock delays in modern processors.
7248 The first one is a data dependence delay determining @dfn{instruction
7249 latency time}. The instruction execution is not started until all
7250 source data have been evaluated by prior instructions (there are more
7251 complex cases when the instruction execution starts even when the data
7252 are not available but will be ready in given time after the
7253 instruction execution start). Taking the data dependence delays into
7254 account is simple. The data dependence (true, output, and
7255 anti-dependence) delay between two instructions is given by a
7256 constant. In most cases this approach is adequate. The second kind
7257 of interlock delays is a reservation delay. The reservation delay
7258 means that two instructions under execution will be in need of shared
7259 processors resources, i.e.@: buses, internal registers, and/or
7260 functional units, which are reserved for some time. Taking this kind
7261 of delay into account is complex especially for modern @acronym{RISC}
7264 The task of exploiting more processor parallelism is solved by an
7265 instruction scheduler. For a better solution to this problem, the
7266 instruction scheduler has to have an adequate description of the
7267 processor parallelism (or @dfn{pipeline description}). GCC
7268 machine descriptions describe processor parallelism and functional
7269 unit reservations for groups of instructions with the aid of
7270 @dfn{regular expressions}.
7272 The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to
7273 figure out the possibility of the instruction issue by the processor
7274 on a given simulated processor cycle. The pipeline hazard recognizer is
7275 automatically generated from the processor pipeline description. The
7276 pipeline hazard recognizer generated from the machine description
7277 is based on a deterministic finite state automaton (@acronym{DFA}):
7278 the instruction issue is possible if there is a transition from one
7279 automaton state to another one. This algorithm is very fast, and
7280 furthermore, its speed is not dependent on processor
7281 complexity@footnote{However, the size of the automaton depends on
7282 processor complexity. To limit this effect, machine descriptions
7283 can split orthogonal parts of the machine description among several
7284 automata: but then, since each of these must be stepped independently,
7285 this does cause a small decrease in the algorithm's performance.}.
7287 @cindex automaton based pipeline description
7288 The rest of this section describes the directives that constitute
7289 an automaton-based processor pipeline description. The order of
7290 these constructions within the machine description file is not
7293 @findex define_automaton
7294 @cindex pipeline hazard recognizer
7295 The following optional construction describes names of automata
7296 generated and used for the pipeline hazards recognition. Sometimes
7297 the generated finite state automaton used by the pipeline hazard
7298 recognizer is large. If we use more than one automaton and bind functional
7299 units to the automata, the total size of the automata is usually
7300 less than the size of the single automaton. If there is no one such
7301 construction, only one finite state automaton is generated.
7304 (define_automaton @var{automata-names})
7307 @var{automata-names} is a string giving names of the automata. The
7308 names are separated by commas. All the automata should have unique names.
7309 The automaton name is used in the constructions @code{define_cpu_unit} and
7310 @code{define_query_cpu_unit}.
7312 @findex define_cpu_unit
7313 @cindex processor functional units
7314 Each processor functional unit used in the description of instruction
7315 reservations should be described by the following construction.
7318 (define_cpu_unit @var{unit-names} [@var{automaton-name}])
7321 @var{unit-names} is a string giving the names of the functional units
7322 separated by commas. Don't use name @samp{nothing}, it is reserved
7325 @var{automaton-name} is a string giving the name of the automaton with
7326 which the unit is bound. The automaton should be described in
7327 construction @code{define_automaton}. You should give
7328 @dfn{automaton-name}, if there is a defined automaton.
7330 The assignment of units to automata are constrained by the uses of the
7331 units in insn reservations. The most important constraint is: if a
7332 unit reservation is present on a particular cycle of an alternative
7333 for an insn reservation, then some unit from the same automaton must
7334 be present on the same cycle for the other alternatives of the insn
7335 reservation. The rest of the constraints are mentioned in the
7336 description of the subsequent constructions.
7338 @findex define_query_cpu_unit
7339 @cindex querying function unit reservations
7340 The following construction describes CPU functional units analogously
7341 to @code{define_cpu_unit}. The reservation of such units can be
7342 queried for an automaton state. The instruction scheduler never
7343 queries reservation of functional units for given automaton state. So
7344 as a rule, you don't need this construction. This construction could
7345 be used for future code generation goals (e.g.@: to generate
7346 @acronym{VLIW} insn templates).
7349 (define_query_cpu_unit @var{unit-names} [@var{automaton-name}])
7352 @var{unit-names} is a string giving names of the functional units
7353 separated by commas.
7355 @var{automaton-name} is a string giving the name of the automaton with
7356 which the unit is bound.
7358 @findex define_insn_reservation
7359 @cindex instruction latency time
7360 @cindex regular expressions
7362 The following construction is the major one to describe pipeline
7363 characteristics of an instruction.
7366 (define_insn_reservation @var{insn-name} @var{default_latency}
7367 @var{condition} @var{regexp})
7370 @var{default_latency} is a number giving latency time of the
7371 instruction. There is an important difference between the old
7372 description and the automaton based pipeline description. The latency
7373 time is used for all dependencies when we use the old description. In
7374 the automaton based pipeline description, the given latency time is only
7375 used for true dependencies. The cost of anti-dependencies is always
7376 zero and the cost of output dependencies is the difference between
7377 latency times of the producing and consuming insns (if the difference
7378 is negative, the cost is considered to be zero). You can always
7379 change the default costs for any description by using the target hook
7380 @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}).
7382 @var{insn-name} is a string giving the internal name of the insn. The
7383 internal names are used in constructions @code{define_bypass} and in
7384 the automaton description file generated for debugging. The internal
7385 name has nothing in common with the names in @code{define_insn}. It is a
7386 good practice to use insn classes described in the processor manual.
7388 @var{condition} defines what RTL insns are described by this
7389 construction. You should remember that you will be in trouble if
7390 @var{condition} for two or more different
7391 @code{define_insn_reservation} constructions is TRUE for an insn. In
7392 this case what reservation will be used for the insn is not defined.
7393 Such cases are not checked during generation of the pipeline hazards
7394 recognizer because in general recognizing that two conditions may have
7395 the same value is quite difficult (especially if the conditions
7396 contain @code{symbol_ref}). It is also not checked during the
7397 pipeline hazard recognizer work because it would slow down the
7398 recognizer considerably.
7400 @var{regexp} is a string describing the reservation of the cpu's functional
7401 units by the instruction. The reservations are described by a regular
7402 expression according to the following syntax:
7405 regexp = regexp "," oneof
7408 oneof = oneof "|" allof
7411 allof = allof "+" repeat
7414 repeat = element "*" number
7417 element = cpu_function_unit_name
7426 @samp{,} is used for describing the start of the next cycle in
7430 @samp{|} is used for describing a reservation described by the first
7431 regular expression @strong{or} a reservation described by the second
7432 regular expression @strong{or} etc.
7435 @samp{+} is used for describing a reservation described by the first
7436 regular expression @strong{and} a reservation described by the
7437 second regular expression @strong{and} etc.
7440 @samp{*} is used for convenience and simply means a sequence in which
7441 the regular expression are repeated @var{number} times with cycle
7442 advancing (see @samp{,}).
7445 @samp{cpu_function_unit_name} denotes reservation of the named
7449 @samp{reservation_name} --- see description of construction
7450 @samp{define_reservation}.
7453 @samp{nothing} denotes no unit reservations.
7456 @findex define_reservation
7457 Sometimes unit reservations for different insns contain common parts.
7458 In such case, you can simplify the pipeline description by describing
7459 the common part by the following construction
7462 (define_reservation @var{reservation-name} @var{regexp})
7465 @var{reservation-name} is a string giving name of @var{regexp}.
7466 Functional unit names and reservation names are in the same name
7467 space. So the reservation names should be different from the
7468 functional unit names and can not be the reserved name @samp{nothing}.
7470 @findex define_bypass
7471 @cindex instruction latency time
7473 The following construction is used to describe exceptions in the
7474 latency time for given instruction pair. This is so called bypasses.
7477 (define_bypass @var{number} @var{out_insn_names} @var{in_insn_names}
7481 @var{number} defines when the result generated by the instructions
7482 given in string @var{out_insn_names} will be ready for the
7483 instructions given in string @var{in_insn_names}. The instructions in
7484 the string are separated by commas.
7486 @var{guard} is an optional string giving the name of a C function which
7487 defines an additional guard for the bypass. The function will get the
7488 two insns as parameters. If the function returns zero the bypass will
7489 be ignored for this case. The additional guard is necessary to
7490 recognize complicated bypasses, e.g.@: when the consumer is only an address
7491 of insn @samp{store} (not a stored value).
7493 If there are more one bypass with the same output and input insns, the
7494 chosen bypass is the first bypass with a guard in description whose
7495 guard function returns nonzero. If there is no such bypass, then
7496 bypass without the guard function is chosen.
7498 @findex exclusion_set
7499 @findex presence_set
7500 @findex final_presence_set
7502 @findex final_absence_set
7505 The following five constructions are usually used to describe
7506 @acronym{VLIW} processors, or more precisely, to describe a placement
7507 of small instructions into @acronym{VLIW} instruction slots. They
7508 can be used for @acronym{RISC} processors, too.
7511 (exclusion_set @var{unit-names} @var{unit-names})
7512 (presence_set @var{unit-names} @var{patterns})
7513 (final_presence_set @var{unit-names} @var{patterns})
7514 (absence_set @var{unit-names} @var{patterns})
7515 (final_absence_set @var{unit-names} @var{patterns})
7518 @var{unit-names} is a string giving names of functional units
7519 separated by commas.
7521 @var{patterns} is a string giving patterns of functional units
7522 separated by comma. Currently pattern is one unit or units
7523 separated by white-spaces.
7525 The first construction (@samp{exclusion_set}) means that each
7526 functional unit in the first string can not be reserved simultaneously
7527 with a unit whose name is in the second string and vice versa. For
7528 example, the construction is useful for describing processors
7529 (e.g.@: some SPARC processors) with a fully pipelined floating point
7530 functional unit which can execute simultaneously only single floating
7531 point insns or only double floating point insns.
7533 The second construction (@samp{presence_set}) means that each
7534 functional unit in the first string can not be reserved unless at
7535 least one of pattern of units whose names are in the second string is
7536 reserved. This is an asymmetric relation. For example, it is useful
7537 for description that @acronym{VLIW} @samp{slot1} is reserved after
7538 @samp{slot0} reservation. We could describe it by the following
7542 (presence_set "slot1" "slot0")
7545 Or @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0}
7546 reservation. In this case we could write
7549 (presence_set "slot1" "slot0 b0")
7552 The third construction (@samp{final_presence_set}) is analogous to
7553 @samp{presence_set}. The difference between them is when checking is
7554 done. When an instruction is issued in given automaton state
7555 reflecting all current and planned unit reservations, the automaton
7556 state is changed. The first state is a source state, the second one
7557 is a result state. Checking for @samp{presence_set} is done on the
7558 source state reservation, checking for @samp{final_presence_set} is
7559 done on the result reservation. This construction is useful to
7560 describe a reservation which is actually two subsequent reservations.
7561 For example, if we use
7564 (presence_set "slot1" "slot0")
7567 the following insn will be never issued (because @samp{slot1} requires
7568 @samp{slot0} which is absent in the source state).
7571 (define_reservation "insn_and_nop" "slot0 + slot1")
7574 but it can be issued if we use analogous @samp{final_presence_set}.
7576 The forth construction (@samp{absence_set}) means that each functional
7577 unit in the first string can be reserved only if each pattern of units
7578 whose names are in the second string is not reserved. This is an
7579 asymmetric relation (actually @samp{exclusion_set} is analogous to
7580 this one but it is symmetric). For example it might be useful in a
7581 @acronym{VLIW} description to say that @samp{slot0} cannot be reserved
7582 after either @samp{slot1} or @samp{slot2} have been reserved. This
7583 can be described as:
7586 (absence_set "slot0" "slot1, slot2")
7589 Or @samp{slot2} can not be reserved if @samp{slot0} and unit @samp{b0}
7590 are reserved or @samp{slot1} and unit @samp{b1} are reserved. In
7591 this case we could write
7594 (absence_set "slot2" "slot0 b0, slot1 b1")
7597 All functional units mentioned in a set should belong to the same
7600 The last construction (@samp{final_absence_set}) is analogous to
7601 @samp{absence_set} but checking is done on the result (state)
7602 reservation. See comments for @samp{final_presence_set}.
7604 @findex automata_option
7605 @cindex deterministic finite state automaton
7606 @cindex nondeterministic finite state automaton
7607 @cindex finite state automaton minimization
7608 You can control the generator of the pipeline hazard recognizer with
7609 the following construction.
7612 (automata_option @var{options})
7615 @var{options} is a string giving options which affect the generated
7616 code. Currently there are the following options:
7620 @dfn{no-minimization} makes no minimization of the automaton. This is
7621 only worth to do when we are debugging the description and need to
7622 look more accurately at reservations of states.
7625 @dfn{time} means printing time statistics about the generation of
7629 @dfn{stats} means printing statistics about the generated automata
7630 such as the number of DFA states, NDFA states and arcs.
7633 @dfn{v} means a generation of the file describing the result automata.
7634 The file has suffix @samp{.dfa} and can be used for the description
7635 verification and debugging.
7638 @dfn{w} means a generation of warning instead of error for
7639 non-critical errors.
7642 @dfn{ndfa} makes nondeterministic finite state automata. This affects
7643 the treatment of operator @samp{|} in the regular expressions. The
7644 usual treatment of the operator is to try the first alternative and,
7645 if the reservation is not possible, the second alternative. The
7646 nondeterministic treatment means trying all alternatives, some of them
7647 may be rejected by reservations in the subsequent insns.
7650 @dfn{progress} means output of a progress bar showing how many states
7651 were generated so far for automaton being processed. This is useful
7652 during debugging a @acronym{DFA} description. If you see too many
7653 generated states, you could interrupt the generator of the pipeline
7654 hazard recognizer and try to figure out a reason for generation of the
7658 As an example, consider a superscalar @acronym{RISC} machine which can
7659 issue three insns (two integer insns and one floating point insn) on
7660 the cycle but can finish only two insns. To describe this, we define
7661 the following functional units.
7664 (define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline")
7665 (define_cpu_unit "port0, port1")
7668 All simple integer insns can be executed in any integer pipeline and
7669 their result is ready in two cycles. The simple integer insns are
7670 issued into the first pipeline unless it is reserved, otherwise they
7671 are issued into the second pipeline. Integer division and
7672 multiplication insns can be executed only in the second integer
7673 pipeline and their results are ready correspondingly in 8 and 4
7674 cycles. The integer division is not pipelined, i.e.@: the subsequent
7675 integer division insn can not be issued until the current division
7676 insn finished. Floating point insns are fully pipelined and their
7677 results are ready in 3 cycles. Where the result of a floating point
7678 insn is used by an integer insn, an additional delay of one cycle is
7679 incurred. To describe all of this we could specify
7682 (define_cpu_unit "div")
7684 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
7685 "(i0_pipeline | i1_pipeline), (port0 | port1)")
7687 (define_insn_reservation "mult" 4 (eq_attr "type" "mult")
7688 "i1_pipeline, nothing*2, (port0 | port1)")
7690 (define_insn_reservation "div" 8 (eq_attr "type" "div")
7691 "i1_pipeline, div*7, div + (port0 | port1)")
7693 (define_insn_reservation "float" 3 (eq_attr "type" "float")
7694 "f_pipeline, nothing, (port0 | port1))
7696 (define_bypass 4 "float" "simple,mult,div")
7699 To simplify the description we could describe the following reservation
7702 (define_reservation "finish" "port0|port1")
7705 and use it in all @code{define_insn_reservation} as in the following
7709 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
7710 "(i0_pipeline | i1_pipeline), finish")
7716 @node Conditional Execution
7717 @section Conditional Execution
7718 @cindex conditional execution
7721 A number of architectures provide for some form of conditional
7722 execution, or predication. The hallmark of this feature is the
7723 ability to nullify most of the instructions in the instruction set.
7724 When the instruction set is large and not entirely symmetric, it
7725 can be quite tedious to describe these forms directly in the
7726 @file{.md} file. An alternative is the @code{define_cond_exec} template.
7728 @findex define_cond_exec
7731 [@var{predicate-pattern}]
7733 "@var{output-template}")
7736 @var{predicate-pattern} is the condition that must be true for the
7737 insn to be executed at runtime and should match a relational operator.
7738 One can use @code{match_operator} to match several relational operators
7739 at once. Any @code{match_operand} operands must have no more than one
7742 @var{condition} is a C expression that must be true for the generated
7745 @findex current_insn_predicate
7746 @var{output-template} is a string similar to the @code{define_insn}
7747 output template (@pxref{Output Template}), except that the @samp{*}
7748 and @samp{@@} special cases do not apply. This is only useful if the
7749 assembly text for the predicate is a simple prefix to the main insn.
7750 In order to handle the general case, there is a global variable
7751 @code{current_insn_predicate} that will contain the entire predicate
7752 if the current insn is predicated, and will otherwise be @code{NULL}.
7754 When @code{define_cond_exec} is used, an implicit reference to
7755 the @code{predicable} instruction attribute is made.
7756 @xref{Insn Attributes}. This attribute must be boolean (i.e.@: have
7757 exactly two elements in its @var{list-of-values}). Further, it must
7758 not be used with complex expressions. That is, the default and all
7759 uses in the insns must be a simple constant, not dependent on the
7760 alternative or anything else.
7762 For each @code{define_insn} for which the @code{predicable}
7763 attribute is true, a new @code{define_insn} pattern will be
7764 generated that matches a predicated version of the instruction.
7768 (define_insn "addsi"
7769 [(set (match_operand:SI 0 "register_operand" "r")
7770 (plus:SI (match_operand:SI 1 "register_operand" "r")
7771 (match_operand:SI 2 "register_operand" "r")))]
7776 [(ne (match_operand:CC 0 "register_operand" "c")
7783 generates a new pattern
7788 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
7789 (set (match_operand:SI 0 "register_operand" "r")
7790 (plus:SI (match_operand:SI 1 "register_operand" "r")
7791 (match_operand:SI 2 "register_operand" "r"))))]
7792 "(@var{test2}) && (@var{test1})"
7793 "(%3) add %2,%1,%0")
7798 @node Constant Definitions
7799 @section Constant Definitions
7800 @cindex constant definitions
7801 @findex define_constants
7803 Using literal constants inside instruction patterns reduces legibility and
7804 can be a maintenance problem.
7806 To overcome this problem, you may use the @code{define_constants}
7807 expression. It contains a vector of name-value pairs. From that
7808 point on, wherever any of the names appears in the MD file, it is as
7809 if the corresponding value had been written instead. You may use
7810 @code{define_constants} multiple times; each appearance adds more
7811 constants to the table. It is an error to redefine a constant with
7814 To come back to the a29k load multiple example, instead of
7818 [(match_parallel 0 "load_multiple_operation"
7819 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
7820 (match_operand:SI 2 "memory_operand" "m"))
7822 (clobber (reg:SI 179))])]
7838 [(match_parallel 0 "load_multiple_operation"
7839 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
7840 (match_operand:SI 2 "memory_operand" "m"))
7842 (clobber (reg:SI R_CR))])]
7847 The constants that are defined with a define_constant are also output
7848 in the insn-codes.h header file as #defines.
7853 @cindex iterators in @file{.md} files
7855 Ports often need to define similar patterns for more than one machine
7856 mode or for more than one rtx code. GCC provides some simple iterator
7857 facilities to make this process easier.
7860 * Mode Iterators:: Generating variations of patterns for different modes.
7861 * Code Iterators:: Doing the same for codes.
7864 @node Mode Iterators
7865 @subsection Mode Iterators
7866 @cindex mode iterators in @file{.md} files
7868 Ports often need to define similar patterns for two or more different modes.
7873 If a processor has hardware support for both single and double
7874 floating-point arithmetic, the @code{SFmode} patterns tend to be
7875 very similar to the @code{DFmode} ones.
7878 If a port uses @code{SImode} pointers in one configuration and
7879 @code{DImode} pointers in another, it will usually have very similar
7880 @code{SImode} and @code{DImode} patterns for manipulating pointers.
7883 Mode iterators allow several patterns to be instantiated from one
7884 @file{.md} file template. They can be used with any type of
7885 rtx-based construct, such as a @code{define_insn},
7886 @code{define_split}, or @code{define_peephole2}.
7889 * Defining Mode Iterators:: Defining a new mode iterator.
7890 * Substitutions:: Combining mode iterators with substitutions
7891 * Examples:: Examples
7894 @node Defining Mode Iterators
7895 @subsubsection Defining Mode Iterators
7896 @findex define_mode_iterator
7898 The syntax for defining a mode iterator is:
7901 (define_mode_iterator @var{name} [(@var{mode1} "@var{cond1}") @dots{} (@var{moden} "@var{condn}")])
7904 This allows subsequent @file{.md} file constructs to use the mode suffix
7905 @code{:@var{name}}. Every construct that does so will be expanded
7906 @var{n} times, once with every use of @code{:@var{name}} replaced by
7907 @code{:@var{mode1}}, once with every use replaced by @code{:@var{mode2}},
7908 and so on. In the expansion for a particular @var{modei}, every
7909 C condition will also require that @var{condi} be true.
7914 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
7917 defines a new mode suffix @code{:P}. Every construct that uses
7918 @code{:P} will be expanded twice, once with every @code{:P} replaced
7919 by @code{:SI} and once with every @code{:P} replaced by @code{:DI}.
7920 The @code{:SI} version will only apply if @code{Pmode == SImode} and
7921 the @code{:DI} version will only apply if @code{Pmode == DImode}.
7923 As with other @file{.md} conditions, an empty string is treated
7924 as ``always true''. @code{(@var{mode} "")} can also be abbreviated
7925 to @code{@var{mode}}. For example:
7928 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
7931 means that the @code{:DI} expansion only applies if @code{TARGET_64BIT}
7932 but that the @code{:SI} expansion has no such constraint.
7934 Iterators are applied in the order they are defined. This can be
7935 significant if two iterators are used in a construct that requires
7936 substitutions. @xref{Substitutions}.
7939 @subsubsection Substitution in Mode Iterators
7940 @findex define_mode_attr
7942 If an @file{.md} file construct uses mode iterators, each version of the
7943 construct will often need slightly different strings or modes. For
7948 When a @code{define_expand} defines several @code{add@var{m}3} patterns
7949 (@pxref{Standard Names}), each expander will need to use the
7950 appropriate mode name for @var{m}.
7953 When a @code{define_insn} defines several instruction patterns,
7954 each instruction will often use a different assembler mnemonic.
7957 When a @code{define_insn} requires operands with different modes,
7958 using an iterator for one of the operand modes usually requires a specific
7959 mode for the other operand(s).
7962 GCC supports such variations through a system of ``mode attributes''.
7963 There are two standard attributes: @code{mode}, which is the name of
7964 the mode in lower case, and @code{MODE}, which is the same thing in
7965 upper case. You can define other attributes using:
7968 (define_mode_attr @var{name} [(@var{mode1} "@var{value1}") @dots{} (@var{moden} "@var{valuen}")])
7971 where @var{name} is the name of the attribute and @var{valuei}
7972 is the value associated with @var{modei}.
7974 When GCC replaces some @var{:iterator} with @var{:mode}, it will scan
7975 each string and mode in the pattern for sequences of the form
7976 @code{<@var{iterator}:@var{attr}>}, where @var{attr} is the name of a
7977 mode attribute. If the attribute is defined for @var{mode}, the whole
7978 @code{<@dots{}>} sequence will be replaced by the appropriate attribute
7981 For example, suppose an @file{.md} file has:
7984 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
7985 (define_mode_attr load [(SI "lw") (DI "ld")])
7988 If one of the patterns that uses @code{:P} contains the string
7989 @code{"<P:load>\t%0,%1"}, the @code{SI} version of that pattern
7990 will use @code{"lw\t%0,%1"} and the @code{DI} version will use
7993 Here is an example of using an attribute for a mode:
7996 (define_mode_iterator LONG [SI DI])
7997 (define_mode_attr SHORT [(SI "HI") (DI "SI")])
7998 (define_insn @dots{}
7999 (sign_extend:LONG (match_operand:<LONG:SHORT> @dots{})) @dots{})
8002 The @code{@var{iterator}:} prefix may be omitted, in which case the
8003 substitution will be attempted for every iterator expansion.
8006 @subsubsection Mode Iterator Examples
8008 Here is an example from the MIPS port. It defines the following
8009 modes and attributes (among others):
8012 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
8013 (define_mode_attr d [(SI "") (DI "d")])
8016 and uses the following template to define both @code{subsi3}
8020 (define_insn "sub<mode>3"
8021 [(set (match_operand:GPR 0 "register_operand" "=d")
8022 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
8023 (match_operand:GPR 2 "register_operand" "d")))]
8026 [(set_attr "type" "arith")
8027 (set_attr "mode" "<MODE>")])
8030 This is exactly equivalent to:
8033 (define_insn "subsi3"
8034 [(set (match_operand:SI 0 "register_operand" "=d")
8035 (minus:SI (match_operand:SI 1 "register_operand" "d")
8036 (match_operand:SI 2 "register_operand" "d")))]
8039 [(set_attr "type" "arith")
8040 (set_attr "mode" "SI")])
8042 (define_insn "subdi3"
8043 [(set (match_operand:DI 0 "register_operand" "=d")
8044 (minus:DI (match_operand:DI 1 "register_operand" "d")
8045 (match_operand:DI 2 "register_operand" "d")))]
8048 [(set_attr "type" "arith")
8049 (set_attr "mode" "DI")])
8052 @node Code Iterators
8053 @subsection Code Iterators
8054 @cindex code iterators in @file{.md} files
8055 @findex define_code_iterator
8056 @findex define_code_attr
8058 Code iterators operate in a similar way to mode iterators. @xref{Mode Iterators}.
8063 (define_code_iterator @var{name} [(@var{code1} "@var{cond1}") @dots{} (@var{coden} "@var{condn}")])
8066 defines a pseudo rtx code @var{name} that can be instantiated as
8067 @var{codei} if condition @var{condi} is true. Each @var{codei}
8068 must have the same rtx format. @xref{RTL Classes}.
8070 As with mode iterators, each pattern that uses @var{name} will be
8071 expanded @var{n} times, once with all uses of @var{name} replaced by
8072 @var{code1}, once with all uses replaced by @var{code2}, and so on.
8073 @xref{Defining Mode Iterators}.
8075 It is possible to define attributes for codes as well as for modes.
8076 There are two standard code attributes: @code{code}, the name of the
8077 code in lower case, and @code{CODE}, the name of the code in upper case.
8078 Other attributes are defined using:
8081 (define_code_attr @var{name} [(@var{code1} "@var{value1}") @dots{} (@var{coden} "@var{valuen}")])
8084 Here's an example of code iterators in action, taken from the MIPS port:
8087 (define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
8088 eq ne gt ge lt le gtu geu ltu leu])
8090 (define_expand "b<code>"
8092 (if_then_else (any_cond:CC (cc0)
8094 (label_ref (match_operand 0 ""))
8098 gen_conditional_branch (operands, <CODE>);
8103 This is equivalent to:
8106 (define_expand "bunordered"
8108 (if_then_else (unordered:CC (cc0)
8110 (label_ref (match_operand 0 ""))
8114 gen_conditional_branch (operands, UNORDERED);
8118 (define_expand "bordered"
8120 (if_then_else (ordered:CC (cc0)
8122 (label_ref (match_operand 0 ""))
8126 gen_conditional_branch (operands, ORDERED);