1 @c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 2000, 2001
2 @c Free Software Foundation, Inc.
3 @c This is part of the GCC manual.
4 @c For copying conditions, see the file gcc.texi.
8 @chapter Machine Descriptions
9 @cindex machine descriptions
11 A machine description has two parts: a file of instruction patterns
12 (@file{.md} file) and a C header file of macro definitions.
14 The @file{.md} file for a target machine contains a pattern for each
15 instruction that the target machine supports (or at least each instruction
16 that is worth telling the compiler about). It may also contain comments.
17 A semicolon causes the rest of the line to be a comment, unless the semicolon
18 is inside a quoted string.
20 See the next chapter for information on the C header file.
23 * Overview:: How the machine description is used.
24 * Patterns:: How to write instruction patterns.
25 * Example:: An explained example of a @code{define_insn} pattern.
26 * RTL Template:: The RTL template defines what insns match a pattern.
27 * Output Template:: The output template says how to make assembler code
29 * Output Statement:: For more generality, write C code to output
31 * Constraints:: When not all operands are general operands.
32 * Standard Names:: Names mark patterns to use for code generation.
33 * Pattern Ordering:: When the order of patterns makes a difference.
34 * Dependent Patterns:: Having one pattern may make you need another.
35 * Jump Patterns:: Special considerations for patterns for jump insns.
36 * Looping Patterns:: How to define patterns for special looping insns.
37 * Insn Canonicalizations::Canonicalization of Instructions
38 * Expander Definitions::Generating a sequence of several RTL insns
39 for a standard operation.
40 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
41 * Peephole Definitions::Defining machine-specific peephole optimizations.
42 * Insn Attributes:: Specifying the value of attributes for generated insns.
43 * Conditional Execution::Generating @code{define_insn} patterns for
45 * Constant Definitions::Defining symbolic constants that can be used in the
50 @section Overview of How the Machine Description is Used
52 There are three main conversions that happen in the compiler:
57 The front end reads the source code and builds a parse tree.
60 The parse tree is used to generate an RTL insn list based on named
64 The insn list is matched against the RTL templates to produce assembler
69 For the generate pass, only the names of the insns matter, from either a
70 named @code{define_insn} or a @code{define_expand}. The compiler will
71 choose the pattern with the right name and apply the operands according
72 to the documentation later in this chapter, without regard for the RTL
73 template or operand constraints. Note that the names the compiler looks
74 for are hard-coded in the compiler---it will ignore unnamed patterns and
75 patterns with names it doesn't know about, but if you don't provide a
76 named pattern it needs, it will abort.
78 If a @code{define_insn} is used, the template given is inserted into the
79 insn list. If a @code{define_expand} is used, one of three things
80 happens, based on the condition logic. The condition logic may manually
81 create new insns for the insn list, say via @code{emit_insn()}, and
82 invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
83 compiler to use an alternate way of performing that task. If it invokes
84 neither @code{DONE} nor @code{FAIL}, the template given in the pattern
85 is inserted, as if the @code{define_expand} were a @code{define_insn}.
87 Once the insn list is generated, various optimization passes convert,
88 replace, and rearrange the insns in the insn list. This is where the
89 @code{define_split} and @code{define_peephole} patterns get used, for
92 Finally, the insn list's RTL is matched up with the RTL templates in the
93 @code{define_insn} patterns, and those patterns are used to emit the
94 final assembly code. For this purpose, each named @code{define_insn}
95 acts like it's unnamed, since the names are ignored.
98 @section Everything about Instruction Patterns
100 @cindex instruction patterns
103 Each instruction pattern contains an incomplete RTL expression, with pieces
104 to be filled in later, operand constraints that restrict how the pieces can
105 be filled in, and an output pattern or C code to generate the assembler
106 output, all wrapped up in a @code{define_insn} expression.
108 A @code{define_insn} is an RTL expression containing four or five operands:
112 An optional name. The presence of a name indicate that this instruction
113 pattern can perform a certain standard job for the RTL-generation
114 pass of the compiler. This pass knows certain names and will use
115 the instruction patterns with those names, if the names are defined
116 in the machine description.
118 The absence of a name is indicated by writing an empty string
119 where the name should go. Nameless instruction patterns are never
120 used for generating RTL code, but they may permit several simpler insns
121 to be combined later on.
123 Names that are not thus known and used in RTL-generation have no
124 effect; they are equivalent to no name at all.
126 For the purpose of debugging the compiler, you may also specify a
127 name beginning with the @samp{*} character. Such a name is used only
128 for identifying the instruction in RTL dumps; it is entirely equivalent
129 to having a nameless pattern for all other purposes.
132 The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete
133 RTL expressions which show what the instruction should look like. It is
134 incomplete because it may contain @code{match_operand},
135 @code{match_operator}, and @code{match_dup} expressions that stand for
136 operands of the instruction.
138 If the vector has only one element, that element is the template for the
139 instruction pattern. If the vector has multiple elements, then the
140 instruction pattern is a @code{parallel} expression containing the
144 @cindex pattern conditions
145 @cindex conditions, in patterns
146 A condition. This is a string which contains a C expression that is
147 the final test to decide whether an insn body matches this pattern.
149 @cindex named patterns and conditions
150 For a named pattern, the condition (if present) may not depend on
151 the data in the insn being matched, but only the target-machine-type
152 flags. The compiler needs to test these conditions during
153 initialization in order to learn exactly which named instructions are
154 available in a particular run.
157 For nameless patterns, the condition is applied only when matching an
158 individual insn, and only after the insn has matched the pattern's
159 recognition template. The insn's operands may be found in the vector
163 The @dfn{output template}: a string that says how to output matching
164 insns as assembler code. @samp{%} in this string specifies where
165 to substitute the value of an operand. @xref{Output Template}.
167 When simple substitution isn't general enough, you can specify a piece
168 of C code to compute the output. @xref{Output Statement}.
171 Optionally, a vector containing the values of attributes for insns matching
172 this pattern. @xref{Insn Attributes}.
176 @section Example of @code{define_insn}
177 @cindex @code{define_insn} example
179 Here is an actual example of an instruction pattern, for the 68000/68020.
184 (match_operand:SI 0 "general_operand" "rm"))]
188 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
190 return \"cmpl #0,%0\";
195 This can also be written using braced strings:
200 (match_operand:SI 0 "general_operand" "rm"))]
203 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
209 This is an instruction that sets the condition codes based on the value of
210 a general operand. It has no condition, so any insn whose RTL description
211 has the form shown may be handled according to this pattern. The name
212 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation
213 pass that, when it is necessary to test such a value, an insn to do so
214 can be constructed using this pattern.
216 The output control string is a piece of C code which chooses which
217 output template to return based on the kind of operand and the specific
218 type of CPU for which code is being generated.
220 @samp{"rm"} is an operand constraint. Its meaning is explained below.
223 @section RTL Template
224 @cindex RTL insn template
225 @cindex generating insns
226 @cindex insns, generating
227 @cindex recognizing insns
228 @cindex insns, recognizing
230 The RTL template is used to define which insns match the particular pattern
231 and how to find their operands. For named patterns, the RTL template also
232 says how to construct an insn from specified operands.
234 Construction involves substituting specified operands into a copy of the
235 template. Matching involves determining the values that serve as the
236 operands in the insn being matched. Both of these activities are
237 controlled by special expression types that direct matching and
238 substitution of the operands.
241 @findex match_operand
242 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
243 This expression is a placeholder for operand number @var{n} of
244 the insn. When constructing an insn, operand number @var{n}
245 will be substituted at this point. When matching an insn, whatever
246 appears at this position in the insn will be taken as operand
247 number @var{n}; but it must satisfy @var{predicate} or this instruction
248 pattern will not match at all.
250 Operand numbers must be chosen consecutively counting from zero in
251 each instruction pattern. There may be only one @code{match_operand}
252 expression in the pattern for each operand number. Usually operands
253 are numbered in the order of appearance in @code{match_operand}
254 expressions. In the case of a @code{define_expand}, any operand numbers
255 used only in @code{match_dup} expressions have higher values than all
256 other operand numbers.
258 @var{predicate} is a string that is the name of a C function that accepts two
259 arguments, an expression and a machine mode. During matching, the
260 function will be called with the putative operand as the expression and
261 @var{m} as the mode argument (if @var{m} is not specified,
262 @code{VOIDmode} will be used, which normally causes @var{predicate} to accept
263 any mode). If it returns zero, this instruction pattern fails to match.
264 @var{predicate} may be an empty string; then it means no test is to be done
265 on the operand, so anything which occurs in this position is valid.
267 Most of the time, @var{predicate} will reject modes other than @var{m}---but
268 not always. For example, the predicate @code{address_operand} uses
269 @var{m} as the mode of memory ref that the address should be valid for.
270 Many predicates accept @code{const_int} nodes even though their mode is
273 @var{constraint} controls reloading and the choice of the best register
274 class to use for a value, as explained later (@pxref{Constraints}).
276 People are often unclear on the difference between the constraint and the
277 predicate. The predicate helps decide whether a given insn matches the
278 pattern. The constraint plays no role in this decision; instead, it
279 controls various decisions in the case of an insn which does match.
281 @findex general_operand
282 On CISC machines, the most common @var{predicate} is
283 @code{"general_operand"}. This function checks that the putative
284 operand is either a constant, a register or a memory reference, and that
285 it is valid for mode @var{m}.
287 @findex register_operand
288 For an operand that must be a register, @var{predicate} should be
289 @code{"register_operand"}. Using @code{"general_operand"} would be
290 valid, since the reload pass would copy any non-register operands
291 through registers, but this would make GCC do extra work, it would
292 prevent invariant operands (such as constant) from being removed from
293 loops, and it would prevent the register allocator from doing the best
294 possible job. On RISC machines, it is usually most efficient to allow
295 @var{predicate} to accept only objects that the constraints allow.
297 @findex immediate_operand
298 For an operand that must be a constant, you must be sure to either use
299 @code{"immediate_operand"} for @var{predicate}, or make the instruction
300 pattern's extra condition require a constant, or both. You cannot
301 expect the constraints to do this work! If the constraints allow only
302 constants, but the predicate allows something else, the compiler will
303 crash when that case arises.
305 @findex match_scratch
306 @item (match_scratch:@var{m} @var{n} @var{constraint})
307 This expression is also a placeholder for operand number @var{n}
308 and indicates that operand must be a @code{scratch} or @code{reg}
311 When matching patterns, this is equivalent to
314 (match_operand:@var{m} @var{n} "scratch_operand" @var{pred})
317 but, when generating RTL, it produces a (@code{scratch}:@var{m})
320 If the last few expressions in a @code{parallel} are @code{clobber}
321 expressions whose operands are either a hard register or
322 @code{match_scratch}, the combiner can add or delete them when
323 necessary. @xref{Side Effects}.
326 @item (match_dup @var{n})
327 This expression is also a placeholder for operand number @var{n}.
328 It is used when the operand needs to appear more than once in the
331 In construction, @code{match_dup} acts just like @code{match_operand}:
332 the operand is substituted into the insn being constructed. But in
333 matching, @code{match_dup} behaves differently. It assumes that operand
334 number @var{n} has already been determined by a @code{match_operand}
335 appearing earlier in the recognition template, and it matches only an
336 identical-looking expression.
338 Note that @code{match_dup} should not be used to tell the compiler that
339 a particular register is being used for two operands (example:
340 @code{add} that adds one register to another; the second register is
341 both an input operand and the output operand). Use a matching
342 constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
343 operand is used in two places in the template, such as an instruction
344 that computes both a quotient and a remainder, where the opcode takes
345 two input operands but the RTL template has to refer to each of those
346 twice; once for the quotient pattern and once for the remainder pattern.
348 @findex match_operator
349 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
350 This pattern is a kind of placeholder for a variable RTL expression
353 When constructing an insn, it stands for an RTL expression whose
354 expression code is taken from that of operand @var{n}, and whose
355 operands are constructed from the patterns @var{operands}.
357 When matching an expression, it matches an expression if the function
358 @var{predicate} returns nonzero on that expression @emph{and} the
359 patterns @var{operands} match the operands of the expression.
361 Suppose that the function @code{commutative_operator} is defined as
362 follows, to match any expression whose operator is one of the
363 commutative arithmetic operators of RTL and whose mode is @var{mode}:
367 commutative_operator (x, mode)
369 enum machine_mode mode;
371 enum rtx_code code = GET_CODE (x);
372 if (GET_MODE (x) != mode)
374 return (GET_RTX_CLASS (code) == 'c'
375 || code == EQ || code == NE);
379 Then the following pattern will match any RTL expression consisting
380 of a commutative operator applied to two general operands:
383 (match_operator:SI 3 "commutative_operator"
384 [(match_operand:SI 1 "general_operand" "g")
385 (match_operand:SI 2 "general_operand" "g")])
388 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
389 because the expressions to be matched all contain two operands.
391 When this pattern does match, the two operands of the commutative
392 operator are recorded as operands 1 and 2 of the insn. (This is done
393 by the two instances of @code{match_operand}.) Operand 3 of the insn
394 will be the entire commutative expression: use @code{GET_CODE
395 (operands[3])} to see which commutative operator was used.
397 The machine mode @var{m} of @code{match_operator} works like that of
398 @code{match_operand}: it is passed as the second argument to the
399 predicate function, and that function is solely responsible for
400 deciding whether the expression to be matched ``has'' that mode.
402 When constructing an insn, argument 3 of the gen-function will specify
403 the operation (i.e.@: the expression code) for the expression to be
404 made. It should be an RTL expression, whose expression code is copied
405 into a new expression whose operands are arguments 1 and 2 of the
406 gen-function. The subexpressions of argument 3 are not used;
407 only its expression code matters.
409 When @code{match_operator} is used in a pattern for matching an insn,
410 it usually best if the operand number of the @code{match_operator}
411 is higher than that of the actual operands of the insn. This improves
412 register allocation because the register allocator often looks at
413 operands 1 and 2 of insns to see if it can do register tying.
415 There is no way to specify constraints in @code{match_operator}. The
416 operand of the insn which corresponds to the @code{match_operator}
417 never has any constraints because it is never reloaded as a whole.
418 However, if parts of its @var{operands} are matched by
419 @code{match_operand} patterns, those parts may have constraints of
423 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
424 Like @code{match_dup}, except that it applies to operators instead of
425 operands. When constructing an insn, operand number @var{n} will be
426 substituted at this point. But in matching, @code{match_op_dup} behaves
427 differently. It assumes that operand number @var{n} has already been
428 determined by a @code{match_operator} appearing earlier in the
429 recognition template, and it matches only an identical-looking
432 @findex match_parallel
433 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
434 This pattern is a placeholder for an insn that consists of a
435 @code{parallel} expression with a variable number of elements. This
436 expression should only appear at the top level of an insn pattern.
438 When constructing an insn, operand number @var{n} will be substituted at
439 this point. When matching an insn, it matches if the body of the insn
440 is a @code{parallel} expression with at least as many elements as the
441 vector of @var{subpat} expressions in the @code{match_parallel}, if each
442 @var{subpat} matches the corresponding element of the @code{parallel},
443 @emph{and} the function @var{predicate} returns nonzero on the
444 @code{parallel} that is the body of the insn. It is the responsibility
445 of the predicate to validate elements of the @code{parallel} beyond
446 those listed in the @code{match_parallel}.
448 A typical use of @code{match_parallel} is to match load and store
449 multiple expressions, which can contain a variable number of elements
450 in a @code{parallel}. For example,
454 [(match_parallel 0 "load_multiple_operation"
455 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
456 (match_operand:SI 2 "memory_operand" "m"))
458 (clobber (reg:SI 179))])]
463 This example comes from @file{a29k.md}. The function
464 @code{load_multiple_operation} is defined in @file{a29k.c} and checks
465 that subsequent elements in the @code{parallel} are the same as the
466 @code{set} in the pattern, except that they are referencing subsequent
467 registers and memory locations.
469 An insn that matches this pattern might look like:
473 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
475 (clobber (reg:SI 179))
477 (mem:SI (plus:SI (reg:SI 100)
480 (mem:SI (plus:SI (reg:SI 100)
484 @findex match_par_dup
485 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
486 Like @code{match_op_dup}, but for @code{match_parallel} instead of
487 @code{match_operator}.
490 @item (match_insn @var{predicate})
491 Match a complete insn. Unlike the other @code{match_*} recognizers,
492 @code{match_insn} does not take an operand number.
494 The machine mode @var{m} of @code{match_insn} works like that of
495 @code{match_operand}: it is passed as the second argument to the
496 predicate function, and that function is solely responsible for
497 deciding whether the expression to be matched ``has'' that mode.
500 @item (match_insn2 @var{n} @var{predicate})
501 Match a complete insn.
503 The machine mode @var{m} of @code{match_insn2} works like that of
504 @code{match_operand}: it is passed as the second argument to the
505 predicate function, and that function is solely responsible for
506 deciding whether the expression to be matched ``has'' that mode.
510 @node Output Template
511 @section Output Templates and Operand Substitution
512 @cindex output templates
513 @cindex operand substitution
515 @cindex @samp{%} in template
517 The @dfn{output template} is a string which specifies how to output the
518 assembler code for an instruction pattern. Most of the template is a
519 fixed string which is output literally. The character @samp{%} is used
520 to specify where to substitute an operand; it can also be used to
521 identify places where different variants of the assembler require
524 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
525 operand @var{n} at that point in the string.
527 @samp{%} followed by a letter and a digit says to output an operand in an
528 alternate fashion. Four letters have standard, built-in meanings described
529 below. The machine description macro @code{PRINT_OPERAND} can define
530 additional letters with nonstandard meanings.
532 @samp{%c@var{digit}} can be used to substitute an operand that is a
533 constant value without the syntax that normally indicates an immediate
536 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
537 the constant is negated before printing.
539 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
540 memory reference, with the actual operand treated as the address. This may
541 be useful when outputting a ``load address'' instruction, because often the
542 assembler syntax for such an instruction requires you to write the operand
543 as if it were a memory reference.
545 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
548 @samp{%=} outputs a number which is unique to each instruction in the
549 entire compilation. This is useful for making local labels to be
550 referred to more than once in a single template that generates multiple
551 assembler instructions.
553 @samp{%} followed by a punctuation character specifies a substitution that
554 does not use an operand. Only one case is standard: @samp{%%} outputs a
555 @samp{%} into the assembler code. Other nonstandard cases can be
556 defined in the @code{PRINT_OPERAND} macro. You must also define
557 which punctuation characters are valid with the
558 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
562 The template may generate multiple assembler instructions. Write the text
563 for the instructions, with @samp{\;} between them.
565 @cindex matching operands
566 When the RTL contains two operands which are required by constraint to match
567 each other, the output template must refer only to the lower-numbered operand.
568 Matching operands are not always identical, and the rest of the compiler
569 arranges to put the proper RTL expression for printing into the lower-numbered
572 One use of nonstandard letters or punctuation following @samp{%} is to
573 distinguish between different assembler languages for the same machine; for
574 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
575 requires periods in most opcode names, while MIT syntax does not. For
576 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
577 syntax. The same file of patterns is used for both kinds of output syntax,
578 but the character sequence @samp{%.} is used in each place where Motorola
579 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
580 defines the sequence to output a period; the macro for MIT syntax defines
583 @cindex @code{#} in template
584 As a special case, a template consisting of the single character @code{#}
585 instructs the compiler to first split the insn, and then output the
586 resulting instructions separately. This helps eliminate redundancy in the
587 output templates. If you have a @code{define_insn} that needs to emit
588 multiple assembler instructions, and there is an matching @code{define_split}
589 already defined, then you can simply use @code{#} as the output template
590 instead of writing an output template that emits the multiple assembler
593 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
594 of the form @samp{@{option0|option1|option2@}} in the templates. These
595 describe multiple variants of assembler language syntax.
596 @xref{Instruction Output}.
598 @node Output Statement
599 @section C Statements for Assembler Output
600 @cindex output statements
601 @cindex C statements for assembler output
602 @cindex generating assembler output
604 Often a single fixed template string cannot produce correct and efficient
605 assembler code for all the cases that are recognized by a single
606 instruction pattern. For example, the opcodes may depend on the kinds of
607 operands; or some unfortunate combinations of operands may require extra
608 machine instructions.
610 If the output control string starts with a @samp{@@}, then it is actually
611 a series of templates, each on a separate line. (Blank lines and
612 leading spaces and tabs are ignored.) The templates correspond to the
613 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
614 if a target machine has a two-address add instruction @samp{addr} to add
615 into a register and another @samp{addm} to add a register to memory, you
616 might write this pattern:
619 (define_insn "addsi3"
620 [(set (match_operand:SI 0 "general_operand" "=r,m")
621 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
622 (match_operand:SI 2 "general_operand" "g,r")))]
629 @cindex @code{*} in template
630 @cindex asterisk in template
631 If the output control string starts with a @samp{*}, then it is not an
632 output template but rather a piece of C program that should compute a
633 template. It should execute a @code{return} statement to return the
634 template-string you want. Most such templates use C string literals, which
635 require doublequote characters to delimit them. To include these
636 doublequote characters in the string, prefix each one with @samp{\}.
638 If the output control string is written as a brace block instead of a
639 double-quoted string, it is automatically assumed to be C code. In that
640 case, it is not necessary to put in a leading asterisk, or to escape the
641 doublequotes surrounding C string literals.
643 The operands may be found in the array @code{operands}, whose C data type
646 It is very common to select different ways of generating assembler code
647 based on whether an immediate operand is within a certain range. Be
648 careful when doing this, because the result of @code{INTVAL} is an
649 integer on the host machine. If the host machine has more bits in an
650 @code{int} than the target machine has in the mode in which the constant
651 will be used, then some of the bits you get from @code{INTVAL} will be
652 superfluous. For proper results, you must carefully disregard the
653 values of those bits.
655 @findex output_asm_insn
656 It is possible to output an assembler instruction and then go on to output
657 or compute more of them, using the subroutine @code{output_asm_insn}. This
658 receives two arguments: a template-string and a vector of operands. The
659 vector may be @code{operands}, or it may be another array of @code{rtx}
660 that you declare locally and initialize yourself.
662 @findex which_alternative
663 When an insn pattern has multiple alternatives in its constraints, often
664 the appearance of the assembler code is determined mostly by which alternative
665 was matched. When this is so, the C code can test the variable
666 @code{which_alternative}, which is the ordinal number of the alternative
667 that was actually satisfied (0 for the first, 1 for the second alternative,
670 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
671 for registers and @samp{clrmem} for memory locations. Here is how
672 a pattern could use @code{which_alternative} to choose between them:
676 [(set (match_operand:SI 0 "general_operand" "=r,m")
680 return (which_alternative == 0
681 ? "clrreg %0" : "clrmem %0");
685 The example above, where the assembler code to generate was
686 @emph{solely} determined by the alternative, could also have been specified
687 as follows, having the output control string start with a @samp{@@}:
692 [(set (match_operand:SI 0 "general_operand" "=r,m")
702 @c Most of this node appears by itself (in a different place) even
703 @c when the INTERNALS flag is clear. Passages that require the full
704 @c manual's context are conditionalized to appear only in the full manual.
707 @section Operand Constraints
708 @cindex operand constraints
711 Each @code{match_operand} in an instruction pattern can specify a
712 constraint for the type of operands allowed.
716 @section Constraints for @code{asm} Operands
717 @cindex operand constraints, @code{asm}
718 @cindex constraints, @code{asm}
719 @cindex @code{asm} constraints
721 Here are specific details on what constraint letters you can use with
724 Constraints can say whether
725 an operand may be in a register, and which kinds of register; whether the
726 operand can be a memory reference, and which kinds of address; whether the
727 operand may be an immediate constant, and which possible values it may
728 have. Constraints can also require two operands to match.
732 * Simple Constraints:: Basic use of constraints.
733 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
734 * Class Preferences:: Constraints guide which hard register to put things in.
735 * Modifiers:: More precise control over effects of constraints.
736 * Machine Constraints:: Existing constraints for some particular machines.
742 * Simple Constraints:: Basic use of constraints.
743 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
744 * Modifiers:: More precise control over effects of constraints.
745 * Machine Constraints:: Special constraints for some particular machines.
749 @node Simple Constraints
750 @subsection Simple Constraints
751 @cindex simple constraints
753 The simplest kind of constraint is a string full of letters, each of
754 which describes one kind of operand that is permitted. Here are
755 the letters that are allowed:
759 Whitespace characters are ignored and can be inserted at any position
760 except the first. This enables each alternative for different operands to
761 be visually aligned in the machine description even if they have different
762 number of constraints and modifiers.
764 @cindex @samp{m} in constraint
765 @cindex memory references in constraints
767 A memory operand is allowed, with any kind of address that the machine
770 @cindex offsettable address
771 @cindex @samp{o} in constraint
773 A memory operand is allowed, but only if the address is
774 @dfn{offsettable}. This means that adding a small integer (actually,
775 the width in bytes of the operand, as determined by its machine mode)
776 may be added to the address and the result is also a valid memory
779 @cindex autoincrement/decrement addressing
780 For example, an address which is constant is offsettable; so is an
781 address that is the sum of a register and a constant (as long as a
782 slightly larger constant is also within the range of address-offsets
783 supported by the machine); but an autoincrement or autodecrement
784 address is not offsettable. More complicated indirect/indexed
785 addresses may or may not be offsettable depending on the other
786 addressing modes that the machine supports.
788 Note that in an output operand which can be matched by another
789 operand, the constraint letter @samp{o} is valid only when accompanied
790 by both @samp{<} (if the target machine has predecrement addressing)
791 and @samp{>} (if the target machine has preincrement addressing).
793 @cindex @samp{V} in constraint
795 A memory operand that is not offsettable. In other words, anything that
796 would fit the @samp{m} constraint but not the @samp{o} constraint.
798 @cindex @samp{<} in constraint
800 A memory operand with autodecrement addressing (either predecrement or
801 postdecrement) is allowed.
803 @cindex @samp{>} in constraint
805 A memory operand with autoincrement addressing (either preincrement or
806 postincrement) is allowed.
808 @cindex @samp{r} in constraint
809 @cindex registers in constraints
811 A register operand is allowed provided that it is in a general
814 @cindex constants in constraints
815 @cindex @samp{i} in constraint
817 An immediate integer operand (one with constant value) is allowed.
818 This includes symbolic constants whose values will be known only at
821 @cindex @samp{n} in constraint
823 An immediate integer operand with a known numeric value is allowed.
824 Many systems cannot support assembly-time constants for operands less
825 than a word wide. Constraints for these operands should use @samp{n}
826 rather than @samp{i}.
828 @cindex @samp{I} in constraint
829 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
830 Other letters in the range @samp{I} through @samp{P} may be defined in
831 a machine-dependent fashion to permit immediate integer operands with
832 explicit integer values in specified ranges. For example, on the
833 68000, @samp{I} is defined to stand for the range of values 1 to 8.
834 This is the range permitted as a shift count in the shift
837 @cindex @samp{E} in constraint
839 An immediate floating operand (expression code @code{const_double}) is
840 allowed, but only if the target floating point format is the same as
841 that of the host machine (on which the compiler is running).
843 @cindex @samp{F} in constraint
845 An immediate floating operand (expression code @code{const_double}) is
848 @cindex @samp{G} in constraint
849 @cindex @samp{H} in constraint
850 @item @samp{G}, @samp{H}
851 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
852 permit immediate floating operands in particular ranges of values.
854 @cindex @samp{s} in constraint
856 An immediate integer operand whose value is not an explicit integer is
859 This might appear strange; if an insn allows a constant operand with a
860 value not known at compile time, it certainly must allow any known
861 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
862 better code to be generated.
864 For example, on the 68000 in a fullword instruction it is possible to
865 use an immediate operand; but if the immediate value is between @minus{}128
866 and 127, better code results from loading the value into a register and
867 using the register. This is because the load into the register can be
868 done with a @samp{moveq} instruction. We arrange for this to happen
869 by defining the letter @samp{K} to mean ``any integer outside the
870 range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand
873 @cindex @samp{g} in constraint
875 Any register, memory or immediate integer operand is allowed, except for
876 registers that are not general registers.
878 @cindex @samp{X} in constraint
881 Any operand whatsoever is allowed, even if it does not satisfy
882 @code{general_operand}. This is normally used in the constraint of
883 a @code{match_scratch} when certain alternatives will not actually
884 require a scratch register.
887 Any operand whatsoever is allowed.
890 @cindex @samp{0} in constraint
891 @cindex digits in constraint
892 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
893 An operand that matches the specified operand number is allowed. If a
894 digit is used together with letters within the same alternative, the
895 digit should come last.
897 @cindex matching constraint
898 @cindex constraint, matching
899 This is called a @dfn{matching constraint} and what it really means is
900 that the assembler has only a single operand that fills two roles
902 considered separate in the RTL insn. For example, an add insn has two
903 input operands and one output operand in the RTL, but on most CISC
906 which @code{asm} distinguishes. For example, an add instruction uses
907 two input operands and an output operand, but on most CISC
909 machines an add instruction really has only two operands, one of them an
910 input-output operand:
916 Matching constraints are used in these circumstances.
917 More precisely, the two operands that match must include one input-only
918 operand and one output-only operand. Moreover, the digit must be a
919 smaller number than the number of the operand that uses it in the
923 For operands to match in a particular case usually means that they
924 are identical-looking RTL expressions. But in a few special cases
925 specific kinds of dissimilarity are allowed. For example, @code{*x}
926 as an input operand will match @code{*x++} as an output operand.
927 For proper results in such cases, the output template should always
928 use the output-operand's number when printing the operand.
931 @cindex load address instruction
932 @cindex push address instruction
933 @cindex address constraints
934 @cindex @samp{p} in constraint
936 An operand that is a valid memory address is allowed. This is
937 for ``load address'' and ``push address'' instructions.
939 @findex address_operand
940 @samp{p} in the constraint must be accompanied by @code{address_operand}
941 as the predicate in the @code{match_operand}. This predicate interprets
942 the mode specified in the @code{match_operand} as the mode of the memory
943 reference for which the address would be valid.
945 @cindex other register constraints
946 @cindex extensible constraints
947 @item @var{other-letters}
948 Other letters can be defined in machine-dependent fashion to stand for
949 particular classes of registers or other arbitrary operand types.
950 @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
951 for data, address and floating point registers.
954 The machine description macro @code{REG_CLASS_FROM_LETTER} has first
955 cut at the otherwise unused letters. If it evaluates to @code{NO_REGS},
956 then @code{EXTRA_CONSTRAINT} is evaluated.
958 A typical use for @code{EXTRA_CONSTRANT} would be to distinguish certain
959 types of memory references that affect other insn operands.
964 In order to have valid assembler code, each operand must satisfy
965 its constraint. But a failure to do so does not prevent the pattern
966 from applying to an insn. Instead, it directs the compiler to modify
967 the code so that the constraint will be satisfied. Usually this is
968 done by copying an operand into a register.
970 Contrast, therefore, the two instruction patterns that follow:
974 [(set (match_operand:SI 0 "general_operand" "=r")
975 (plus:SI (match_dup 0)
976 (match_operand:SI 1 "general_operand" "r")))]
982 which has two operands, one of which must appear in two places, and
986 [(set (match_operand:SI 0 "general_operand" "=r")
987 (plus:SI (match_operand:SI 1 "general_operand" "0")
988 (match_operand:SI 2 "general_operand" "r")))]
994 which has three operands, two of which are required by a constraint to be
995 identical. If we are considering an insn of the form
998 (insn @var{n} @var{prev} @var{next}
1000 (plus:SI (reg:SI 6) (reg:SI 109)))
1005 the first pattern would not apply at all, because this insn does not
1006 contain two identical subexpressions in the right place. The pattern would
1007 say, ``That does not look like an add instruction; try other patterns.''
1008 The second pattern would say, ``Yes, that's an add instruction, but there
1009 is something wrong with it.'' It would direct the reload pass of the
1010 compiler to generate additional insns to make the constraint true. The
1011 results might look like this:
1014 (insn @var{n2} @var{prev} @var{n}
1015 (set (reg:SI 3) (reg:SI 6))
1018 (insn @var{n} @var{n2} @var{next}
1020 (plus:SI (reg:SI 3) (reg:SI 109)))
1024 It is up to you to make sure that each operand, in each pattern, has
1025 constraints that can handle any RTL expression that could be present for
1026 that operand. (When multiple alternatives are in use, each pattern must,
1027 for each possible combination of operand expressions, have at least one
1028 alternative which can handle that combination of operands.) The
1029 constraints don't need to @emph{allow} any possible operand---when this is
1030 the case, they do not constrain---but they must at least point the way to
1031 reloading any possible operand so that it will fit.
1035 If the constraint accepts whatever operands the predicate permits,
1036 there is no problem: reloading is never necessary for this operand.
1038 For example, an operand whose constraints permit everything except
1039 registers is safe provided its predicate rejects registers.
1041 An operand whose predicate accepts only constant values is safe
1042 provided its constraints include the letter @samp{i}. If any possible
1043 constant value is accepted, then nothing less than @samp{i} will do;
1044 if the predicate is more selective, then the constraints may also be
1048 Any operand expression can be reloaded by copying it into a register.
1049 So if an operand's constraints allow some kind of register, it is
1050 certain to be safe. It need not permit all classes of registers; the
1051 compiler knows how to copy a register into another register of the
1052 proper class in order to make an instruction valid.
1054 @cindex nonoffsettable memory reference
1055 @cindex memory reference, nonoffsettable
1057 A nonoffsettable memory reference can be reloaded by copying the
1058 address into a register. So if the constraint uses the letter
1059 @samp{o}, all memory references are taken care of.
1062 A constant operand can be reloaded by allocating space in memory to
1063 hold it as preinitialized data. Then the memory reference can be used
1064 in place of the constant. So if the constraint uses the letters
1065 @samp{o} or @samp{m}, constant operands are not a problem.
1068 If the constraint permits a constant and a pseudo register used in an insn
1069 was not allocated to a hard register and is equivalent to a constant,
1070 the register will be replaced with the constant. If the predicate does
1071 not permit a constant and the insn is re-recognized for some reason, the
1072 compiler will crash. Thus the predicate must always recognize any
1073 objects allowed by the constraint.
1076 If the operand's predicate can recognize registers, but the constraint does
1077 not permit them, it can make the compiler crash. When this operand happens
1078 to be a register, the reload pass will be stymied, because it does not know
1079 how to copy a register temporarily into memory.
1081 If the predicate accepts a unary operator, the constraint applies to the
1082 operand. For example, the MIPS processor at ISA level 3 supports an
1083 instruction which adds two registers in @code{SImode} to produce a
1084 @code{DImode} result, but only if the registers are correctly sign
1085 extended. This predicate for the input operands accepts a
1086 @code{sign_extend} of an @code{SImode} register. Write the constraint
1087 to indicate the type of register that is required for the operand of the
1091 @node Multi-Alternative
1092 @subsection Multiple Alternative Constraints
1093 @cindex multiple alternative constraints
1095 Sometimes a single instruction has multiple alternative sets of possible
1096 operands. For example, on the 68000, a logical-or instruction can combine
1097 register or an immediate value into memory, or it can combine any kind of
1098 operand into a register; but it cannot combine one memory location into
1101 These constraints are represented as multiple alternatives. An alternative
1102 can be described by a series of letters for each operand. The overall
1103 constraint for an operand is made from the letters for this operand
1104 from the first alternative, a comma, the letters for this operand from
1105 the second alternative, a comma, and so on until the last alternative.
1107 Here is how it is done for fullword logical-or on the 68000:
1110 (define_insn "iorsi3"
1111 [(set (match_operand:SI 0 "general_operand" "=m,d")
1112 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1113 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1117 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1118 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1119 2. The second alternative has @samp{d} (data register) for operand 0,
1120 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1121 @samp{%} in the constraints apply to all the alternatives; their
1122 meaning is explained in the next section (@pxref{Class Preferences}).
1125 @c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL
1126 If all the operands fit any one alternative, the instruction is valid.
1127 Otherwise, for each alternative, the compiler counts how many instructions
1128 must be added to copy the operands so that that alternative applies.
1129 The alternative requiring the least copying is chosen. If two alternatives
1130 need the same amount of copying, the one that comes first is chosen.
1131 These choices can be altered with the @samp{?} and @samp{!} characters:
1134 @cindex @samp{?} in constraint
1135 @cindex question mark
1137 Disparage slightly the alternative that the @samp{?} appears in,
1138 as a choice when no alternative applies exactly. The compiler regards
1139 this alternative as one unit more costly for each @samp{?} that appears
1142 @cindex @samp{!} in constraint
1143 @cindex exclamation point
1145 Disparage severely the alternative that the @samp{!} appears in.
1146 This alternative can still be used if it fits without reloading,
1147 but if reloading is needed, some other alternative will be used.
1151 When an insn pattern has multiple alternatives in its constraints, often
1152 the appearance of the assembler code is determined mostly by which
1153 alternative was matched. When this is so, the C code for writing the
1154 assembler code can use the variable @code{which_alternative}, which is
1155 the ordinal number of the alternative that was actually satisfied (0 for
1156 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1160 @node Class Preferences
1161 @subsection Register Class Preferences
1162 @cindex class preference constraints
1163 @cindex register class preference constraints
1165 @cindex voting between constraint alternatives
1166 The operand constraints have another function: they enable the compiler
1167 to decide which kind of hardware register a pseudo register is best
1168 allocated to. The compiler examines the constraints that apply to the
1169 insns that use the pseudo register, looking for the machine-dependent
1170 letters such as @samp{d} and @samp{a} that specify classes of registers.
1171 The pseudo register is put in whichever class gets the most ``votes''.
1172 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1173 favor of a general register. The machine description says which registers
1174 are considered general.
1176 Of course, on some machines all registers are equivalent, and no register
1177 classes are defined. Then none of this complexity is relevant.
1181 @subsection Constraint Modifier Characters
1182 @cindex modifiers in constraints
1183 @cindex constraint modifier characters
1185 @c prevent bad page break with this line
1186 Here are constraint modifier characters.
1189 @cindex @samp{=} in constraint
1191 Means that this operand is write-only for this instruction: the previous
1192 value is discarded and replaced by output data.
1194 @cindex @samp{+} in constraint
1196 Means that this operand is both read and written by the instruction.
1198 When the compiler fixes up the operands to satisfy the constraints,
1199 it needs to know which operands are inputs to the instruction and
1200 which are outputs from it. @samp{=} identifies an output; @samp{+}
1201 identifies an operand that is both input and output; all other operands
1202 are assumed to be input only.
1204 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1205 first character of the constraint string.
1207 @cindex @samp{&} in constraint
1208 @cindex earlyclobber operand
1210 Means (in a particular alternative) that this operand is an
1211 @dfn{earlyclobber} operand, which is modified before the instruction is
1212 finished using the input operands. Therefore, this operand may not lie
1213 in a register that is used as an input operand or as part of any memory
1216 @samp{&} applies only to the alternative in which it is written. In
1217 constraints with multiple alternatives, sometimes one alternative
1218 requires @samp{&} while others do not. See, for example, the
1219 @samp{movdf} insn of the 68000.
1221 An input operand can be tied to an earlyclobber operand if its only
1222 use as an input occurs before the early result is written. Adding
1223 alternatives of this form often allows GCC to produce better code
1224 when only some of the inputs can be affected by the earlyclobber.
1225 See, for example, the @samp{mulsi3} insn of the ARM@.
1227 @samp{&} does not obviate the need to write @samp{=}.
1229 @cindex @samp{%} in constraint
1231 Declares the instruction to be commutative for this operand and the
1232 following operand. This means that the compiler may interchange the
1233 two operands if that is the cheapest way to make all operands fit the
1236 This is often used in patterns for addition instructions
1237 that really have only two operands: the result must go in one of the
1238 arguments. Here for example, is how the 68000 halfword-add
1239 instruction is defined:
1242 (define_insn "addhi3"
1243 [(set (match_operand:HI 0 "general_operand" "=m,r")
1244 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1245 (match_operand:HI 2 "general_operand" "di,g")))]
1250 @cindex @samp{#} in constraint
1252 Says that all following characters, up to the next comma, are to be
1253 ignored as a constraint. They are significant only for choosing
1254 register preferences.
1257 @cindex @samp{*} in constraint
1259 Says that the following character should be ignored when choosing
1260 register preferences. @samp{*} has no effect on the meaning of the
1261 constraint as a constraint, and no effect on reloading.
1263 Here is an example: the 68000 has an instruction to sign-extend a
1264 halfword in a data register, and can also sign-extend a value by
1265 copying it into an address register. While either kind of register is
1266 acceptable, the constraints on an address-register destination are
1267 less strict, so it is best if register allocation makes an address
1268 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1269 constraint letter (for data register) is ignored when computing
1270 register preferences.
1273 (define_insn "extendhisi2"
1274 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1276 (match_operand:HI 1 "general_operand" "0,g")))]
1282 @node Machine Constraints
1283 @subsection Constraints for Particular Machines
1284 @cindex machine specific constraints
1285 @cindex constraints, machine specific
1287 Whenever possible, you should use the general-purpose constraint letters
1288 in @code{asm} arguments, since they will convey meaning more readily to
1289 people reading your code. Failing that, use the constraint letters
1290 that usually have very similar meanings across architectures. The most
1291 commonly used constraints are @samp{m} and @samp{r} (for memory and
1292 general-purpose registers respectively; @pxref{Simple Constraints}), and
1293 @samp{I}, usually the letter indicating the most common
1294 immediate-constant format.
1296 For each machine architecture, the
1297 @file{config/@var{machine}/@var{machine}.h} file defines additional
1298 constraints. These constraints are used by the compiler itself for
1299 instruction generation, as well as for @code{asm} statements; therefore,
1300 some of the constraints are not particularly interesting for @code{asm}.
1301 The constraints are defined through these macros:
1304 @item REG_CLASS_FROM_LETTER
1305 Register class constraints (usually lower case).
1307 @item CONST_OK_FOR_LETTER_P
1308 Immediate constant constraints, for non-floating point constants of
1309 word size or smaller precision (usually upper case).
1311 @item CONST_DOUBLE_OK_FOR_LETTER_P
1312 Immediate constant constraints, for all floating point constants and for
1313 constants of greater than word size precision (usually upper case).
1315 @item EXTRA_CONSTRAINT
1316 Special cases of registers or memory. This macro is not required, and
1317 is only defined for some machines.
1320 Inspecting these macro definitions in the compiler source for your
1321 machine is the best way to be certain you have the right constraints.
1322 However, here is a summary of the machine-dependent constraints
1323 available on some particular machines.
1326 @item ARM family---@file{arm.h}
1329 Floating-point register
1332 One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0
1336 Floating-point constant that would satisfy the constraint @samp{F} if it
1340 Integer that is valid as an immediate operand in a data processing
1341 instruction. That is, an integer in the range 0 to 255 rotated by a
1345 Integer in the range @minus{}4095 to 4095
1348 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1351 Integer that satisfies constraint @samp{I} when negated (twos complement)
1354 Integer in the range 0 to 32
1357 A memory reference where the exact address is in a single register
1358 (`@samp{m}' is preferable for @code{asm} statements)
1361 An item in the constant pool
1364 A symbol in the text segment of the current file
1367 @item AMD 29000 family---@file{a29k.h}
1373 Byte Pointer (@samp{BP}) register
1379 Special purpose register
1382 First accumulator register
1385 Other accumulator register
1388 Floating point register
1391 Constant greater than 0, less than 0x100
1394 Constant greater than 0, less than 0x10000
1397 Constant whose high 24 bits are on (1)
1400 16-bit constant whose high 8 bits are on (1)
1403 32-bit constant whose high 16 bits are on (1)
1406 32-bit negative constant that fits in 8 bits
1409 The constant 0x80000000 or, on the 29050, any 32-bit constant
1410 whose low 16 bits are 0.
1413 16-bit negative constant that fits in 8 bits
1417 A floating point constant (in @code{asm} statements, use the machine
1418 independent @samp{E} or @samp{F} instead)
1421 @item AVR family---@file{avr.h}
1424 Registers from r0 to r15
1427 Registers from r16 to r23
1430 Registers from r16 to r31
1433 Registers from r24 to r31. These registers can be used in @samp{adiw} command
1436 Pointer register (r26--r31)
1439 Base pointer register (r28--r31)
1442 Stack pointer register (SPH:SPL)
1445 Temporary register r0
1448 Register pair X (r27:r26)
1451 Register pair Y (r29:r28)
1454 Register pair Z (r31:r30)
1457 Constant greater than @minus{}1, less than 64
1460 Constant greater than @minus{}64, less than 1
1469 Constant that fits in 8 bits
1472 Constant integer @minus{}1
1475 Constant integer 8, 16, or 24
1481 A floating point constant 0.0
1484 @item IBM RS6000---@file{rs6000.h}
1487 Address base register
1490 Floating point register
1493 @samp{MQ}, @samp{CTR}, or @samp{LINK} register
1502 @samp{LINK} register
1505 @samp{CR} register (condition register) number 0
1508 @samp{CR} register (condition register)
1511 @samp{FPMEM} stack memory for FPR-GPR transfers
1514 Signed 16-bit constant
1517 Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for
1518 @code{SImode} constants)
1521 Unsigned 16-bit constant
1524 Signed 16-bit constant shifted left 16 bits
1527 Constant larger than 31
1536 Constant whose negation is a signed 16-bit constant
1539 Floating point constant that can be loaded into a register with one
1540 instruction per word
1543 Memory operand that is an offset from a register (@samp{m} is preferable
1544 for @code{asm} statements)
1550 Constant suitable as a 64-bit mask operand
1553 Constant suitable as a 32-bit mask operand
1556 System V Release 4 small data area reference
1559 @item Intel 386---@file{i386.h}
1562 @samp{a}, @code{b}, @code{c}, or @code{d} register for the i386.
1563 For x86-64 it is equivalent to @samp{r} class. (for 8-bit instructions that
1564 do not use upper halves)
1567 @samp{a}, @code{b}, @code{c}, or @code{d} register. (for 8-bit instructions,
1568 that do use upper halves)
1571 Legacy register---equivalent to @code{r} class in i386 mode.
1572 (for non-8-bit registers used together with 8-bit upper halves in a single
1576 Specifies the @samp{a} or @samp{d} registers. This is primarily useful
1577 for 64-bit integer values (when in 32-bit mode) intended to be returned
1578 with the @samp{d} register holding the most significant bits and the
1579 @samp{a} register holding the least significant bits.
1582 Floating point register
1585 First (top of stack) floating point register
1588 Second floating point register
1609 @samp{xmm} SSE register
1615 Constant in range 0 to 31 (for 32-bit shifts)
1618 Constant in range 0 to 63 (for 64-bit shifts)
1627 0, 1, 2, or 3 (shifts for @code{lea} instruction)
1630 Constant in range 0 to 255 (for @code{out} instruction)
1633 Constant in range 0 to @code{0xffffffff} or symbolic reference known to fit specified range.
1634 (for using immediates in zero extending 32-bit to 64-bit x86-64 instructions)
1637 Constant in range @minus{}2147483648 to 2147483647 or symbolic reference known to fit specified range.
1638 (for using immediates in 64-bit x86-64 instructions)
1641 Standard 80387 floating point constant
1644 @item Intel 960---@file{i960.h}
1647 Floating point register (@code{fp0} to @code{fp3})
1650 Local register (@code{r0} to @code{r15})
1653 Global register (@code{g0} to @code{g15})
1656 Any local or global register
1659 Integers from 0 to 31
1665 Integers from @minus{}31 to 0
1674 @item MIPS---@file{mips.h}
1677 General-purpose integer register
1680 Floating-point register (if available)
1689 @samp{Hi} or @samp{Lo} register
1692 General-purpose integer register
1695 Floating-point status register
1698 Signed 16-bit constant (for arithmetic instructions)
1704 Zero-extended 16-bit constant (for logic instructions)
1707 Constant with low 16 bits zero (can be loaded with @code{lui})
1710 32-bit constant which requires two instructions to load (a constant
1711 which is not @samp{I}, @samp{K}, or @samp{L})
1714 Negative 16-bit constant
1720 Positive 16-bit constant
1726 Memory reference that can be loaded with more than one instruction
1727 (@samp{m} is preferable for @code{asm} statements)
1730 Memory reference that can be loaded with one instruction
1731 (@samp{m} is preferable for @code{asm} statements)
1734 Memory reference in external OSF/rose PIC format
1735 (@samp{m} is preferable for @code{asm} statements)
1738 @item Motorola 680x0---@file{m68k.h}
1747 68881 floating-point register, if available
1750 Sun FPA (floating-point) register, if available
1753 First 16 Sun FPA registers, if available
1756 Integer in the range 1 to 8
1759 16-bit signed number
1762 Signed number whose magnitude is greater than 0x80
1765 Integer in the range @minus{}8 to @minus{}1
1768 Signed number whose magnitude is greater than 0x100
1771 Floating point constant that is not a 68881 constant
1774 Floating point constant that can be used by Sun FPA
1777 @item Motorola 68HC11 & 68HC12 families---@file{m68hc11.h}
1792 Temporary soft register _.tmp
1795 A soft register _.d1 to _.d31
1798 Stack pointer register
1807 Pseudo register 'z' (replaced by 'x' or 'y' at the end)
1810 An address register: x, y or z
1813 An address register: x or y
1816 Register pair (x:d) to form a 32-bit value
1819 Constants in the range @minus{}65536 to 65535
1822 Constants whose 16-bit low part is zero
1825 Constant integer 1 or @minus{}1
1831 Constants in the range @minus{}8 to 2
1836 @item SPARC---@file{sparc.h}
1839 Floating-point register that can hold 32- or 64-bit values.
1842 Floating-point register that can hold 64- or 128-bit values.
1845 Signed 13-bit constant
1851 32-bit constant with the low 12 bits clear (a constant that can be
1852 loaded with the @code{sethi} instruction)
1858 Signed 13-bit constant, sign-extended to 32 or 64 bits
1861 Floating-point constant whose integral representation can
1862 be moved into an integer register using a single sethi
1866 Floating-point constant whose integral representation can
1867 be moved into an integer register using a single mov
1871 Floating-point constant whose integral representation can
1872 be moved into an integer register using a high/lo_sum
1873 instruction sequence
1876 Memory address aligned to an 8-byte boundary
1883 @item TMS320C3x/C4x---@file{c4x.h}
1886 Auxiliary (address) register (ar0-ar7)
1889 Stack pointer register (sp)
1892 Standard (32-bit) precision integer register
1895 Extended (40-bit) precision register (r0-r11)
1898 Block count register (bk)
1901 Extended (40-bit) precision low register (r0-r7)
1904 Extended (40-bit) precision register (r0-r1)
1907 Extended (40-bit) precision register (r2-r3)
1910 Repeat count register (rc)
1913 Index register (ir0-ir1)
1916 Status (condition code) register (st)
1919 Data page register (dp)
1925 Immediate 16-bit floating-point constant
1928 Signed 16-bit constant
1931 Signed 8-bit constant
1934 Signed 5-bit constant
1937 Unsigned 16-bit constant
1940 Unsigned 8-bit constant
1943 Ones complement of unsigned 16-bit constant
1946 High 16-bit constant (32-bit constant with 16 LSBs zero)
1949 Indirect memory reference with signed 8-bit or index register displacement
1952 Indirect memory reference with unsigned 5-bit displacement
1955 Indirect memory reference with 1 bit or index register displacement
1958 Direct memory reference
1965 @item S/390 and zSeries---@file{s390.h}
1968 Address register (general purpose register except r0)
1971 Data register (arbitrary general purpose register)
1974 Floating-point register
1977 Unsigned 8-bit constant (0--255)
1980 Unsigned 12-bit constant (0--4095)
1983 Signed 16-bit constant (@minus{}32768--32767)
1986 Unsigned 16-bit constant (0--65535)
1989 Memory reference without index register
1992 Symbolic constant suitable for use with the @code{larl} instruction
1999 @node Standard Names
2000 @section Standard Pattern Names For Generation
2001 @cindex standard pattern names
2002 @cindex pattern names
2003 @cindex names, pattern
2005 Here is a table of the instruction names that are meaningful in the RTL
2006 generation pass of the compiler. Giving one of these names to an
2007 instruction pattern tells the RTL generation pass that it can use the
2008 pattern to accomplish a certain task.
2011 @cindex @code{mov@var{m}} instruction pattern
2012 @item @samp{mov@var{m}}
2013 Here @var{m} stands for a two-letter machine mode name, in lower case.
2014 This instruction pattern moves data with that machine mode from operand
2015 1 to operand 0. For example, @samp{movsi} moves full-word data.
2017 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
2018 own mode is wider than @var{m}, the effect of this instruction is
2019 to store the specified value in the part of the register that corresponds
2020 to mode @var{m}. The effect on the rest of the register is undefined.
2022 This class of patterns is special in several ways. First of all, each
2023 of these names up to and including full word size @emph{must} be defined,
2024 because there is no other way to copy a datum from one place to another.
2025 If there are patterns accepting operands in larger modes,
2026 @samp{mov@var{m}} must be defined for integer modes of those sizes.
2028 Second, these patterns are not used solely in the RTL generation pass.
2029 Even the reload pass can generate move insns to copy values from stack
2030 slots into temporary registers. When it does so, one of the operands is
2031 a hard register and the other is an operand that can need to be reloaded
2035 Therefore, when given such a pair of operands, the pattern must generate
2036 RTL which needs no reloading and needs no temporary registers---no
2037 registers other than the operands. For example, if you support the
2038 pattern with a @code{define_expand}, then in such a case the
2039 @code{define_expand} mustn't call @code{force_reg} or any other such
2040 function which might generate new pseudo registers.
2042 This requirement exists even for subword modes on a RISC machine where
2043 fetching those modes from memory normally requires several insns and
2044 some temporary registers.
2046 @findex change_address
2047 During reload a memory reference with an invalid address may be passed
2048 as an operand. Such an address will be replaced with a valid address
2049 later in the reload pass. In this case, nothing may be done with the
2050 address except to use it as it stands. If it is copied, it will not be
2051 replaced with a valid address. No attempt should be made to make such
2052 an address into a valid address and no routine (such as
2053 @code{change_address}) that will do so may be called. Note that
2054 @code{general_operand} will fail when applied to such an address.
2056 @findex reload_in_progress
2057 The global variable @code{reload_in_progress} (which must be explicitly
2058 declared if required) can be used to determine whether such special
2059 handling is required.
2061 The variety of operands that have reloads depends on the rest of the
2062 machine description, but typically on a RISC machine these can only be
2063 pseudo registers that did not get hard registers, while on other
2064 machines explicit memory references will get optional reloads.
2066 If a scratch register is required to move an object to or from memory,
2067 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
2069 If there are cases which need scratch registers during or after reload,
2070 you must define @code{SECONDARY_INPUT_RELOAD_CLASS} and/or
2071 @code{SECONDARY_OUTPUT_RELOAD_CLASS} to detect them, and provide
2072 patterns @samp{reload_in@var{m}} or @samp{reload_out@var{m}} to handle
2073 them. @xref{Register Classes}.
2075 @findex no_new_pseudos
2076 The global variable @code{no_new_pseudos} can be used to determine if it
2077 is unsafe to create new pseudo registers. If this variable is nonzero, then
2078 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
2080 The constraints on a @samp{mov@var{m}} must permit moving any hard
2081 register to any other hard register provided that
2082 @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
2083 @code{REGISTER_MOVE_COST} applied to their classes returns a value of 2.
2085 It is obligatory to support floating point @samp{mov@var{m}}
2086 instructions into and out of any registers that can hold fixed point
2087 values, because unions and structures (which have modes @code{SImode} or
2088 @code{DImode}) can be in those registers and they may have floating
2091 There may also be a need to support fixed point @samp{mov@var{m}}
2092 instructions in and out of floating point registers. Unfortunately, I
2093 have forgotten why this was so, and I don't know whether it is still
2094 true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
2095 floating point registers, then the constraints of the fixed point
2096 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
2097 reload into a floating point register.
2099 @cindex @code{reload_in} instruction pattern
2100 @cindex @code{reload_out} instruction pattern
2101 @item @samp{reload_in@var{m}}
2102 @itemx @samp{reload_out@var{m}}
2103 Like @samp{mov@var{m}}, but used when a scratch register is required to
2104 move between operand 0 and operand 1. Operand 2 describes the scratch
2105 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
2106 macro in @pxref{Register Classes}.
2108 There are special restrictions on the form of the @code{match_operand}s
2109 used in these patterns. First, only the predicate for the reload
2110 operand is examined, i.e., @code{reload_in} examines operand 1, but not
2111 the predicates for operand 0 or 2. Second, there may be only one
2112 alternative in the constraints. Third, only a single register class
2113 letter may be used for the constraint; subsequent constraint letters
2114 are ignored. As a special exception, an empty constraint string
2115 matches the @code{ALL_REGS} register class. This may relieve ports
2116 of the burden of defining an @code{ALL_REGS} constraint letter just
2119 @cindex @code{movstrict@var{m}} instruction pattern
2120 @item @samp{movstrict@var{m}}
2121 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
2122 with mode @var{m} of a register whose natural mode is wider,
2123 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
2124 any of the register except the part which belongs to mode @var{m}.
2126 @cindex @code{load_multiple} instruction pattern
2127 @item @samp{load_multiple}
2128 Load several consecutive memory locations into consecutive registers.
2129 Operand 0 is the first of the consecutive registers, operand 1
2130 is the first memory location, and operand 2 is a constant: the
2131 number of consecutive registers.
2133 Define this only if the target machine really has such an instruction;
2134 do not define this if the most efficient way of loading consecutive
2135 registers from memory is to do them one at a time.
2137 On some machines, there are restrictions as to which consecutive
2138 registers can be stored into memory, such as particular starting or
2139 ending register numbers or only a range of valid counts. For those
2140 machines, use a @code{define_expand} (@pxref{Expander Definitions})
2141 and make the pattern fail if the restrictions are not met.
2143 Write the generated insn as a @code{parallel} with elements being a
2144 @code{set} of one register from the appropriate memory location (you may
2145 also need @code{use} or @code{clobber} elements). Use a
2146 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
2147 @file{a29k.md} and @file{rs6000.md} for examples of the use of this insn
2150 @cindex @samp{store_multiple} instruction pattern
2151 @item @samp{store_multiple}
2152 Similar to @samp{load_multiple}, but store several consecutive registers
2153 into consecutive memory locations. Operand 0 is the first of the
2154 consecutive memory locations, operand 1 is the first register, and
2155 operand 2 is a constant: the number of consecutive registers.
2157 @cindex @code{push@var{m}} instruction pattern
2158 @item @samp{push@var{m}}
2159 Output an push instruction. Operand 0 is value to push. Used only when
2160 @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be
2161 missing and in such case an @code{mov} expander is used instead, with a
2162 @code{MEM} expression forming the push operation. The @code{mov} expander
2163 method is deprecated.
2165 @cindex @code{add@var{m}3} instruction pattern
2166 @item @samp{add@var{m}3}
2167 Add operand 2 and operand 1, storing the result in operand 0. All operands
2168 must have mode @var{m}. This can be used even on two-address machines, by
2169 means of constraints requiring operands 1 and 0 to be the same location.
2171 @cindex @code{sub@var{m}3} instruction pattern
2172 @cindex @code{mul@var{m}3} instruction pattern
2173 @cindex @code{div@var{m}3} instruction pattern
2174 @cindex @code{udiv@var{m}3} instruction pattern
2175 @cindex @code{mod@var{m}3} instruction pattern
2176 @cindex @code{umod@var{m}3} instruction pattern
2177 @cindex @code{smin@var{m}3} instruction pattern
2178 @cindex @code{smax@var{m}3} instruction pattern
2179 @cindex @code{umin@var{m}3} instruction pattern
2180 @cindex @code{umax@var{m}3} instruction pattern
2181 @cindex @code{and@var{m}3} instruction pattern
2182 @cindex @code{ior@var{m}3} instruction pattern
2183 @cindex @code{xor@var{m}3} instruction pattern
2184 @item @samp{sub@var{m}3}, @samp{mul@var{m}3}
2185 @itemx @samp{div@var{m}3}, @samp{udiv@var{m}3}, @samp{mod@var{m}3}, @samp{umod@var{m}3}
2186 @itemx @samp{smin@var{m}3}, @samp{smax@var{m}3}, @samp{umin@var{m}3}, @samp{umax@var{m}3}
2187 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
2188 Similar, for other arithmetic operations.
2189 @cindex @code{min@var{m}3} instruction pattern
2190 @cindex @code{max@var{m}3} instruction pattern
2191 @itemx @samp{min@var{m}3}, @samp{max@var{m}3}
2192 Floating point min and max operations. If both operands are zeros,
2193 or if either operand is NaN, then it is unspecified which of the two
2194 operands is returned as the result.
2197 @cindex @code{mulhisi3} instruction pattern
2198 @item @samp{mulhisi3}
2199 Multiply operands 1 and 2, which have mode @code{HImode}, and store
2200 a @code{SImode} product in operand 0.
2202 @cindex @code{mulqihi3} instruction pattern
2203 @cindex @code{mulsidi3} instruction pattern
2204 @item @samp{mulqihi3}, @samp{mulsidi3}
2205 Similar widening-multiplication instructions of other widths.
2207 @cindex @code{umulqihi3} instruction pattern
2208 @cindex @code{umulhisi3} instruction pattern
2209 @cindex @code{umulsidi3} instruction pattern
2210 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
2211 Similar widening-multiplication instructions that do unsigned
2214 @cindex @code{smul@var{m}3_highpart} instruction pattern
2215 @item @samp{smul@var{m}3_highpart}
2216 Perform a signed multiplication of operands 1 and 2, which have mode
2217 @var{m}, and store the most significant half of the product in operand 0.
2218 The least significant half of the product is discarded.
2220 @cindex @code{umul@var{m}3_highpart} instruction pattern
2221 @item @samp{umul@var{m}3_highpart}
2222 Similar, but the multiplication is unsigned.
2224 @cindex @code{divmod@var{m}4} instruction pattern
2225 @item @samp{divmod@var{m}4}
2226 Signed division that produces both a quotient and a remainder.
2227 Operand 1 is divided by operand 2 to produce a quotient stored
2228 in operand 0 and a remainder stored in operand 3.
2230 For machines with an instruction that produces both a quotient and a
2231 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
2232 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
2233 allows optimization in the relatively common case when both the quotient
2234 and remainder are computed.
2236 If an instruction that just produces a quotient or just a remainder
2237 exists and is more efficient than the instruction that produces both,
2238 write the output routine of @samp{divmod@var{m}4} to call
2239 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
2240 quotient or remainder and generate the appropriate instruction.
2242 @cindex @code{udivmod@var{m}4} instruction pattern
2243 @item @samp{udivmod@var{m}4}
2244 Similar, but does unsigned division.
2246 @cindex @code{ashl@var{m}3} instruction pattern
2247 @item @samp{ashl@var{m}3}
2248 Arithmetic-shift operand 1 left by a number of bits specified by operand
2249 2, and store the result in operand 0. Here @var{m} is the mode of
2250 operand 0 and operand 1; operand 2's mode is specified by the
2251 instruction pattern, and the compiler will convert the operand to that
2252 mode before generating the instruction.
2254 @cindex @code{ashr@var{m}3} instruction pattern
2255 @cindex @code{lshr@var{m}3} instruction pattern
2256 @cindex @code{rotl@var{m}3} instruction pattern
2257 @cindex @code{rotr@var{m}3} instruction pattern
2258 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
2259 Other shift and rotate instructions, analogous to the
2260 @code{ashl@var{m}3} instructions.
2262 @cindex @code{neg@var{m}2} instruction pattern
2263 @item @samp{neg@var{m}2}
2264 Negate operand 1 and store the result in operand 0.
2266 @cindex @code{abs@var{m}2} instruction pattern
2267 @item @samp{abs@var{m}2}
2268 Store the absolute value of operand 1 into operand 0.
2270 @cindex @code{sqrt@var{m}2} instruction pattern
2271 @item @samp{sqrt@var{m}2}
2272 Store the square root of operand 1 into operand 0.
2274 The @code{sqrt} built-in function of C always uses the mode which
2275 corresponds to the C data type @code{double}.
2277 @cindex @code{ffs@var{m}2} instruction pattern
2278 @item @samp{ffs@var{m}2}
2279 Store into operand 0 one plus the index of the least significant 1-bit
2280 of operand 1. If operand 1 is zero, store zero. @var{m} is the mode
2281 of operand 0; operand 1's mode is specified by the instruction
2282 pattern, and the compiler will convert the operand to that mode before
2283 generating the instruction.
2285 The @code{ffs} built-in function of C always uses the mode which
2286 corresponds to the C data type @code{int}.
2288 @cindex @code{one_cmpl@var{m}2} instruction pattern
2289 @item @samp{one_cmpl@var{m}2}
2290 Store the bitwise-complement of operand 1 into operand 0.
2292 @cindex @code{cmp@var{m}} instruction pattern
2293 @item @samp{cmp@var{m}}
2294 Compare operand 0 and operand 1, and set the condition codes.
2295 The RTL pattern should look like this:
2298 (set (cc0) (compare (match_operand:@var{m} 0 @dots{})
2299 (match_operand:@var{m} 1 @dots{})))
2302 @cindex @code{tst@var{m}} instruction pattern
2303 @item @samp{tst@var{m}}
2304 Compare operand 0 against zero, and set the condition codes.
2305 The RTL pattern should look like this:
2308 (set (cc0) (match_operand:@var{m} 0 @dots{}))
2311 @samp{tst@var{m}} patterns should not be defined for machines that do
2312 not use @code{(cc0)}. Doing so would confuse the optimizer since it
2313 would no longer be clear which @code{set} operations were comparisons.
2314 The @samp{cmp@var{m}} patterns should be used instead.
2316 @cindex @code{movstr@var{m}} instruction pattern
2317 @item @samp{movstr@var{m}}
2318 Block move instruction. The addresses of the destination and source
2319 strings are the first two operands, and both are in mode @code{Pmode}.
2321 The number of bytes to move is the third operand, in mode @var{m}.
2322 Usually, you specify @code{word_mode} for @var{m}. However, if you can
2323 generate better code knowing the range of valid lengths is smaller than
2324 those representable in a full word, you should provide a pattern with a
2325 mode corresponding to the range of values you can handle efficiently
2326 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
2327 that appear negative) and also a pattern with @code{word_mode}.
2329 The fourth operand is the known shared alignment of the source and
2330 destination, in the form of a @code{const_int} rtx. Thus, if the
2331 compiler knows that both source and destination are word-aligned,
2332 it may provide the value 4 for this operand.
2334 Descriptions of multiple @code{movstr@var{m}} patterns can only be
2335 beneficial if the patterns for smaller modes have fewer restrictions
2336 on their first, second and fourth operands. Note that the mode @var{m}
2337 in @code{movstr@var{m}} does not impose any restriction on the mode of
2338 individually moved data units in the block.
2340 These patterns need not give special consideration to the possibility
2341 that the source and destination strings might overlap.
2343 @cindex @code{clrstr@var{m}} instruction pattern
2344 @item @samp{clrstr@var{m}}
2345 Block clear instruction. The addresses of the destination string is the
2346 first operand, in mode @code{Pmode}. The number of bytes to clear is
2347 the second operand, in mode @var{m}. See @samp{movstr@var{m}} for
2348 a discussion of the choice of mode.
2350 The third operand is the known alignment of the destination, in the form
2351 of a @code{const_int} rtx. Thus, if the compiler knows that the
2352 destination is word-aligned, it may provide the value 4 for this
2355 The use for multiple @code{clrstr@var{m}} is as for @code{movstr@var{m}}.
2357 @cindex @code{cmpstr@var{m}} instruction pattern
2358 @item @samp{cmpstr@var{m}}
2359 Block compare instruction, with five operands. Operand 0 is the output;
2360 it has mode @var{m}. The remaining four operands are like the operands
2361 of @samp{movstr@var{m}}. The two memory blocks specified are compared
2362 byte by byte in lexicographic order. The effect of the instruction is
2363 to store a value in operand 0 whose sign indicates the result of the
2366 @cindex @code{strlen@var{m}} instruction pattern
2367 @item @samp{strlen@var{m}}
2368 Compute the length of a string, with three operands.
2369 Operand 0 is the result (of mode @var{m}), operand 1 is
2370 a @code{mem} referring to the first character of the string,
2371 operand 2 is the character to search for (normally zero),
2372 and operand 3 is a constant describing the known alignment
2373 of the beginning of the string.
2375 @cindex @code{float@var{mn}2} instruction pattern
2376 @item @samp{float@var{m}@var{n}2}
2377 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
2378 floating point mode @var{n} and store in operand 0 (which has mode
2381 @cindex @code{floatuns@var{mn}2} instruction pattern
2382 @item @samp{floatuns@var{m}@var{n}2}
2383 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
2384 to floating point mode @var{n} and store in operand 0 (which has mode
2387 @cindex @code{fix@var{mn}2} instruction pattern
2388 @item @samp{fix@var{m}@var{n}2}
2389 Convert operand 1 (valid for floating point mode @var{m}) to fixed
2390 point mode @var{n} as a signed number and store in operand 0 (which
2391 has mode @var{n}). This instruction's result is defined only when
2392 the value of operand 1 is an integer.
2394 @cindex @code{fixuns@var{mn}2} instruction pattern
2395 @item @samp{fixuns@var{m}@var{n}2}
2396 Convert operand 1 (valid for floating point mode @var{m}) to fixed
2397 point mode @var{n} as an unsigned number and store in operand 0 (which
2398 has mode @var{n}). This instruction's result is defined only when the
2399 value of operand 1 is an integer.
2401 @cindex @code{ftrunc@var{m}2} instruction pattern
2402 @item @samp{ftrunc@var{m}2}
2403 Convert operand 1 (valid for floating point mode @var{m}) to an
2404 integer value, still represented in floating point mode @var{m}, and
2405 store it in operand 0 (valid for floating point mode @var{m}).
2407 @cindex @code{fix_trunc@var{mn}2} instruction pattern
2408 @item @samp{fix_trunc@var{m}@var{n}2}
2409 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
2410 of mode @var{m} by converting the value to an integer.
2412 @cindex @code{fixuns_trunc@var{mn}2} instruction pattern
2413 @item @samp{fixuns_trunc@var{m}@var{n}2}
2414 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
2415 value of mode @var{m} by converting the value to an integer.
2417 @cindex @code{trunc@var{mn}2} instruction pattern
2418 @item @samp{trunc@var{m}@var{n}2}
2419 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
2420 store in operand 0 (which has mode @var{n}). Both modes must be fixed
2421 point or both floating point.
2423 @cindex @code{extend@var{mn}2} instruction pattern
2424 @item @samp{extend@var{m}@var{n}2}
2425 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
2426 store in operand 0 (which has mode @var{n}). Both modes must be fixed
2427 point or both floating point.
2429 @cindex @code{zero_extend@var{mn}2} instruction pattern
2430 @item @samp{zero_extend@var{m}@var{n}2}
2431 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
2432 store in operand 0 (which has mode @var{n}). Both modes must be fixed
2435 @cindex @code{extv} instruction pattern
2437 Extract a bit-field from operand 1 (a register or memory operand), where
2438 operand 2 specifies the width in bits and operand 3 the starting bit,
2439 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
2440 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
2441 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
2442 be valid for @code{word_mode}.
2444 The RTL generation pass generates this instruction only with constants
2445 for operands 2 and 3.
2447 The bit-field value is sign-extended to a full word integer
2448 before it is stored in operand 0.
2450 @cindex @code{extzv} instruction pattern
2452 Like @samp{extv} except that the bit-field value is zero-extended.
2454 @cindex @code{insv} instruction pattern
2456 Store operand 3 (which must be valid for @code{word_mode}) into a
2457 bit-field in operand 0, where operand 1 specifies the width in bits and
2458 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
2459 @code{word_mode}; often @code{word_mode} is allowed only for registers.
2460 Operands 1 and 2 must be valid for @code{word_mode}.
2462 The RTL generation pass generates this instruction only with constants
2463 for operands 1 and 2.
2465 @cindex @code{mov@var{mode}cc} instruction pattern
2466 @item @samp{mov@var{mode}cc}
2467 Conditionally move operand 2 or operand 3 into operand 0 according to the
2468 comparison in operand 1. If the comparison is true, operand 2 is moved
2469 into operand 0, otherwise operand 3 is moved.
2471 The mode of the operands being compared need not be the same as the operands
2472 being moved. Some machines, sparc64 for example, have instructions that
2473 conditionally move an integer value based on the floating point condition
2474 codes and vice versa.
2476 If the machine does not have conditional move instructions, do not
2477 define these patterns.
2479 @cindex @code{s@var{cond}} instruction pattern
2480 @item @samp{s@var{cond}}
2481 Store zero or nonzero in the operand according to the condition codes.
2482 Value stored is nonzero iff the condition @var{cond} is true.
2483 @var{cond} is the name of a comparison operation expression code, such
2484 as @code{eq}, @code{lt} or @code{leu}.
2486 You specify the mode that the operand must have when you write the
2487 @code{match_operand} expression. The compiler automatically sees
2488 which mode you have used and supplies an operand of that mode.
2490 The value stored for a true condition must have 1 as its low bit, or
2491 else must be negative. Otherwise the instruction is not suitable and
2492 you should omit it from the machine description. You describe to the
2493 compiler exactly which value is stored by defining the macro
2494 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
2495 found that can be used for all the @samp{s@var{cond}} patterns, you
2496 should omit those operations from the machine description.
2498 These operations may fail, but should do so only in relatively
2499 uncommon cases; if they would fail for common cases involving
2500 integer comparisons, it is best to omit these patterns.
2502 If these operations are omitted, the compiler will usually generate code
2503 that copies the constant one to the target and branches around an
2504 assignment of zero to the target. If this code is more efficient than
2505 the potential instructions used for the @samp{s@var{cond}} pattern
2506 followed by those required to convert the result into a 1 or a zero in
2507 @code{SImode}, you should omit the @samp{s@var{cond}} operations from
2508 the machine description.
2510 @cindex @code{b@var{cond}} instruction pattern
2511 @item @samp{b@var{cond}}
2512 Conditional branch instruction. Operand 0 is a @code{label_ref} that
2513 refers to the label to jump to. Jump if the condition codes meet
2514 condition @var{cond}.
2516 Some machines do not follow the model assumed here where a comparison
2517 instruction is followed by a conditional branch instruction. In that
2518 case, the @samp{cmp@var{m}} (and @samp{tst@var{m}}) patterns should
2519 simply store the operands away and generate all the required insns in a
2520 @code{define_expand} (@pxref{Expander Definitions}) for the conditional
2521 branch operations. All calls to expand @samp{b@var{cond}} patterns are
2522 immediately preceded by calls to expand either a @samp{cmp@var{m}}
2523 pattern or a @samp{tst@var{m}} pattern.
2525 Machines that use a pseudo register for the condition code value, or
2526 where the mode used for the comparison depends on the condition being
2527 tested, should also use the above mechanism. @xref{Jump Patterns}.
2529 The above discussion also applies to the @samp{mov@var{mode}cc} and
2530 @samp{s@var{cond}} patterns.
2532 @cindex @code{jump} instruction pattern
2534 A jump inside a function; an unconditional branch. Operand 0 is the
2535 @code{label_ref} of the label to jump to. This pattern name is mandatory
2538 @cindex @code{call} instruction pattern
2540 Subroutine call instruction returning no value. Operand 0 is the
2541 function to call; operand 1 is the number of bytes of arguments pushed
2542 as a @code{const_int}; operand 2 is the number of registers used as
2545 On most machines, operand 2 is not actually stored into the RTL
2546 pattern. It is supplied for the sake of some RISC machines which need
2547 to put this information into the assembler code; they can put it in
2548 the RTL instead of operand 1.
2550 Operand 0 should be a @code{mem} RTX whose address is the address of the
2551 function. Note, however, that this address can be a @code{symbol_ref}
2552 expression even if it would not be a legitimate memory address on the
2553 target machine. If it is also not a valid argument for a call
2554 instruction, the pattern for this operation should be a
2555 @code{define_expand} (@pxref{Expander Definitions}) that places the
2556 address into a register and uses that register in the call instruction.
2558 @cindex @code{call_value} instruction pattern
2559 @item @samp{call_value}
2560 Subroutine call instruction returning a value. Operand 0 is the hard
2561 register in which the value is returned. There are three more
2562 operands, the same as the three operands of the @samp{call}
2563 instruction (but with numbers increased by one).
2565 Subroutines that return @code{BLKmode} objects use the @samp{call}
2568 @cindex @code{call_pop} instruction pattern
2569 @cindex @code{call_value_pop} instruction pattern
2570 @item @samp{call_pop}, @samp{call_value_pop}
2571 Similar to @samp{call} and @samp{call_value}, except used if defined and
2572 if @code{RETURN_POPS_ARGS} is non-zero. They should emit a @code{parallel}
2573 that contains both the function call and a @code{set} to indicate the
2574 adjustment made to the frame pointer.
2576 For machines where @code{RETURN_POPS_ARGS} can be non-zero, the use of these
2577 patterns increases the number of functions for which the frame pointer
2578 can be eliminated, if desired.
2580 @cindex @code{untyped_call} instruction pattern
2581 @item @samp{untyped_call}
2582 Subroutine call instruction returning a value of any type. Operand 0 is
2583 the function to call; operand 1 is a memory location where the result of
2584 calling the function is to be stored; operand 2 is a @code{parallel}
2585 expression where each element is a @code{set} expression that indicates
2586 the saving of a function return value into the result block.
2588 This instruction pattern should be defined to support
2589 @code{__builtin_apply} on machines where special instructions are needed
2590 to call a subroutine with arbitrary arguments or to save the value
2591 returned. This instruction pattern is required on machines that have
2592 multiple registers that can hold a return value
2593 (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
2595 @cindex @code{return} instruction pattern
2597 Subroutine return instruction. This instruction pattern name should be
2598 defined only if a single instruction can do all the work of returning
2601 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
2602 RTL generation phase. In this case it is to support machines where
2603 multiple instructions are usually needed to return from a function, but
2604 some class of functions only requires one instruction to implement a
2605 return. Normally, the applicable functions are those which do not need
2606 to save any registers or allocate stack space.
2608 @findex reload_completed
2609 @findex leaf_function_p
2610 For such machines, the condition specified in this pattern should only
2611 be true when @code{reload_completed} is non-zero and the function's
2612 epilogue would only be a single instruction. For machines with register
2613 windows, the routine @code{leaf_function_p} may be used to determine if
2614 a register window push is required.
2616 Machines that have conditional return instructions should define patterns
2622 (if_then_else (match_operator
2623 0 "comparison_operator"
2624 [(cc0) (const_int 0)])
2631 where @var{condition} would normally be the same condition specified on the
2632 named @samp{return} pattern.
2634 @cindex @code{untyped_return} instruction pattern
2635 @item @samp{untyped_return}
2636 Untyped subroutine return instruction. This instruction pattern should
2637 be defined to support @code{__builtin_return} on machines where special
2638 instructions are needed to return a value of any type.
2640 Operand 0 is a memory location where the result of calling a function
2641 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
2642 expression where each element is a @code{set} expression that indicates
2643 the restoring of a function return value from the result block.
2645 @cindex @code{nop} instruction pattern
2647 No-op instruction. This instruction pattern name should always be defined
2648 to output a no-op in assembler code. @code{(const_int 0)} will do as an
2651 @cindex @code{indirect_jump} instruction pattern
2652 @item @samp{indirect_jump}
2653 An instruction to jump to an address which is operand zero.
2654 This pattern name is mandatory on all machines.
2656 @cindex @code{casesi} instruction pattern
2658 Instruction to jump through a dispatch table, including bounds checking.
2659 This instruction takes five operands:
2663 The index to dispatch on, which has mode @code{SImode}.
2666 The lower bound for indices in the table, an integer constant.
2669 The total range of indices in the table---the largest index
2670 minus the smallest one (both inclusive).
2673 A label that precedes the table itself.
2676 A label to jump to if the index has a value outside the bounds.
2677 (If the machine-description macro @code{CASE_DROPS_THROUGH} is defined,
2678 then an out-of-bounds index drops through to the code following
2679 the jump table instead of jumping to this label. In that case,
2680 this label is not actually used by the @samp{casesi} instruction,
2681 but it is always provided as an operand.)
2684 The table is a @code{addr_vec} or @code{addr_diff_vec} inside of a
2685 @code{jump_insn}. The number of elements in the table is one plus the
2686 difference between the upper bound and the lower bound.
2688 @cindex @code{tablejump} instruction pattern
2689 @item @samp{tablejump}
2690 Instruction to jump to a variable address. This is a low-level
2691 capability which can be used to implement a dispatch table when there
2692 is no @samp{casesi} pattern.
2694 This pattern requires two operands: the address or offset, and a label
2695 which should immediately precede the jump table. If the macro
2696 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
2697 operand is an offset which counts from the address of the table; otherwise,
2698 it is an absolute address to jump to. In either case, the first operand has
2701 The @samp{tablejump} insn is always the last insn before the jump
2702 table it uses. Its assembler code normally has no need to use the
2703 second operand, but you should incorporate it in the RTL pattern so
2704 that the jump optimizer will not delete the table as unreachable code.
2707 @cindex @code{decrement_and_branch_until_zero} instruction pattern
2708 @item @samp{decrement_and_branch_until_zero}
2709 Conditional branch instruction that decrements a register and
2710 jumps if the register is non-zero. Operand 0 is the register to
2711 decrement and test; operand 1 is the label to jump to if the
2712 register is non-zero. @xref{Looping Patterns}.
2714 This optional instruction pattern is only used by the combiner,
2715 typically for loops reversed by the loop optimizer when strength
2716 reduction is enabled.
2718 @cindex @code{doloop_end} instruction pattern
2719 @item @samp{doloop_end}
2720 Conditional branch instruction that decrements a register and jumps if
2721 the register is non-zero. This instruction takes five operands: Operand
2722 0 is the register to decrement and test; operand 1 is the number of loop
2723 iterations as a @code{const_int} or @code{const0_rtx} if this cannot be
2724 determined until run-time; operand 2 is the actual or estimated maximum
2725 number of iterations as a @code{const_int}; operand 3 is the number of
2726 enclosed loops as a @code{const_int} (an innermost loop has a value of
2727 1); operand 4 is the label to jump to if the register is non-zero.
2728 @xref{Looping Patterns}.
2730 This optional instruction pattern should be defined for machines with
2731 low-overhead looping instructions as the loop optimizer will try to
2732 modify suitable loops to utilize it. If nested low-overhead looping is
2733 not supported, use a @code{define_expand} (@pxref{Expander Definitions})
2734 and make the pattern fail if operand 3 is not @code{const1_rtx}.
2735 Similarly, if the actual or estimated maximum number of iterations is
2736 too large for this instruction, make it fail.
2738 @cindex @code{doloop_begin} instruction pattern
2739 @item @samp{doloop_begin}
2740 Companion instruction to @code{doloop_end} required for machines that
2741 need to perform some initialisation, such as loading special registers
2742 used by a low-overhead looping instruction. If initialisation insns do
2743 not always need to be emitted, use a @code{define_expand}
2744 (@pxref{Expander Definitions}) and make it fail.
2747 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
2748 @item @samp{canonicalize_funcptr_for_compare}
2749 Canonicalize the function pointer in operand 1 and store the result
2752 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
2753 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
2754 and also has mode @code{Pmode}.
2756 Canonicalization of a function pointer usually involves computing
2757 the address of the function which would be called if the function
2758 pointer were used in an indirect call.
2760 Only define this pattern if function pointers on the target machine
2761 can have different values but still call the same function when
2762 used in an indirect call.
2764 @cindex @code{save_stack_block} instruction pattern
2765 @cindex @code{save_stack_function} instruction pattern
2766 @cindex @code{save_stack_nonlocal} instruction pattern
2767 @cindex @code{restore_stack_block} instruction pattern
2768 @cindex @code{restore_stack_function} instruction pattern
2769 @cindex @code{restore_stack_nonlocal} instruction pattern
2770 @item @samp{save_stack_block}
2771 @itemx @samp{save_stack_function}
2772 @itemx @samp{save_stack_nonlocal}
2773 @itemx @samp{restore_stack_block}
2774 @itemx @samp{restore_stack_function}
2775 @itemx @samp{restore_stack_nonlocal}
2776 Most machines save and restore the stack pointer by copying it to or
2777 from an object of mode @code{Pmode}. Do not define these patterns on
2780 Some machines require special handling for stack pointer saves and
2781 restores. On those machines, define the patterns corresponding to the
2782 non-standard cases by using a @code{define_expand} (@pxref{Expander
2783 Definitions}) that produces the required insns. The three types of
2784 saves and restores are:
2788 @samp{save_stack_block} saves the stack pointer at the start of a block
2789 that allocates a variable-sized object, and @samp{restore_stack_block}
2790 restores the stack pointer when the block is exited.
2793 @samp{save_stack_function} and @samp{restore_stack_function} do a
2794 similar job for the outermost block of a function and are used when the
2795 function allocates variable-sized objects or calls @code{alloca}. Only
2796 the epilogue uses the restored stack pointer, allowing a simpler save or
2797 restore sequence on some machines.
2800 @samp{save_stack_nonlocal} is used in functions that contain labels
2801 branched to by nested functions. It saves the stack pointer in such a
2802 way that the inner function can use @samp{restore_stack_nonlocal} to
2803 restore the stack pointer. The compiler generates code to restore the
2804 frame and argument pointer registers, but some machines require saving
2805 and restoring additional data such as register window information or
2806 stack backchains. Place insns in these patterns to save and restore any
2810 When saving the stack pointer, operand 0 is the save area and operand 1
2811 is the stack pointer. The mode used to allocate the save area defaults
2812 to @code{Pmode} but you can override that choice by defining the
2813 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
2814 specify an integral mode, or @code{VOIDmode} if no save area is needed
2815 for a particular type of save (either because no save is needed or
2816 because a machine-specific save area can be used). Operand 0 is the
2817 stack pointer and operand 1 is the save area for restore operations. If
2818 @samp{save_stack_block} is defined, operand 0 must not be
2819 @code{VOIDmode} since these saves can be arbitrarily nested.
2821 A save area is a @code{mem} that is at a constant offset from
2822 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
2823 nonlocal gotos and a @code{reg} in the other two cases.
2825 @cindex @code{allocate_stack} instruction pattern
2826 @item @samp{allocate_stack}
2827 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
2828 the stack pointer to create space for dynamically allocated data.
2830 Store the resultant pointer to this space into operand 0. If you
2831 are allocating space from the main stack, do this by emitting a
2832 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
2833 If you are allocating the space elsewhere, generate code to copy the
2834 location of the space to operand 0. In the latter case, you must
2835 ensure this space gets freed when the corresponding space on the main
2838 Do not define this pattern if all that must be done is the subtraction.
2839 Some machines require other operations such as stack probes or
2840 maintaining the back chain. Define this pattern to emit those
2841 operations in addition to updating the stack pointer.
2843 @cindex @code{probe} instruction pattern
2845 Some machines require instructions to be executed after space is
2846 allocated from the stack, for example to generate a reference at
2847 the bottom of the stack.
2849 If you need to emit instructions before the stack has been adjusted,
2850 put them into the @samp{allocate_stack} pattern. Otherwise, define
2851 this pattern to emit the required instructions.
2853 No operands are provided.
2855 @cindex @code{check_stack} instruction pattern
2856 @item @samp{check_stack}
2857 If stack checking cannot be done on your system by probing the stack with
2858 a load or store instruction (@pxref{Stack Checking}), define this pattern
2859 to perform the needed check and signaling an error if the stack
2860 has overflowed. The single operand is the location in the stack furthest
2861 from the current stack pointer that you need to validate. Normally,
2862 on machines where this pattern is needed, you would obtain the stack
2863 limit from a global or thread-specific variable or register.
2865 @cindex @code{nonlocal_goto} instruction pattern
2866 @item @samp{nonlocal_goto}
2867 Emit code to generate a non-local goto, e.g., a jump from one function
2868 to a label in an outer function. This pattern has four arguments,
2869 each representing a value to be used in the jump. The first
2870 argument is to be loaded into the frame pointer, the second is
2871 the address to branch to (code to dispatch to the actual label),
2872 the third is the address of a location where the stack is saved,
2873 and the last is the address of the label, to be placed in the
2874 location for the incoming static chain.
2876 On most machines you need not define this pattern, since GCC will
2877 already generate the correct code, which is to load the frame pointer
2878 and static chain, restore the stack (using the
2879 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
2880 to the dispatcher. You need only define this pattern if this code will
2881 not work on your machine.
2883 @cindex @code{nonlocal_goto_receiver} instruction pattern
2884 @item @samp{nonlocal_goto_receiver}
2885 This pattern, if defined, contains code needed at the target of a
2886 nonlocal goto after the code already generated by GCC@. You will not
2887 normally need to define this pattern. A typical reason why you might
2888 need this pattern is if some value, such as a pointer to a global table,
2889 must be restored when the frame pointer is restored. Note that a nonlocal
2890 goto only occurs within a unit-of-translation, so a global table pointer
2891 that is shared by all functions of a given module need not be restored.
2892 There are no arguments.
2894 @cindex @code{exception_receiver} instruction pattern
2895 @item @samp{exception_receiver}
2896 This pattern, if defined, contains code needed at the site of an
2897 exception handler that isn't needed at the site of a nonlocal goto. You
2898 will not normally need to define this pattern. A typical reason why you
2899 might need this pattern is if some value, such as a pointer to a global
2900 table, must be restored after control flow is branched to the handler of
2901 an exception. There are no arguments.
2903 @cindex @code{builtin_setjmp_setup} instruction pattern
2904 @item @samp{builtin_setjmp_setup}
2905 This pattern, if defined, contains additional code needed to initialize
2906 the @code{jmp_buf}. You will not normally need to define this pattern.
2907 A typical reason why you might need this pattern is if some value, such
2908 as a pointer to a global table, must be restored. Though it is
2909 preferred that the pointer value be recalculated if possible (given the
2910 address of a label for instance). The single argument is a pointer to
2911 the @code{jmp_buf}. Note that the buffer is five words long and that
2912 the first three are normally used by the generic mechanism.
2914 @cindex @code{builtin_setjmp_receiver} instruction pattern
2915 @item @samp{builtin_setjmp_receiver}
2916 This pattern, if defined, contains code needed at the site of an
2917 built-in setjmp that isn't needed at the site of a nonlocal goto. You
2918 will not normally need to define this pattern. A typical reason why you
2919 might need this pattern is if some value, such as a pointer to a global
2920 table, must be restored. It takes one argument, which is the label
2921 to which builtin_longjmp transfered control; this pattern may be emitted
2922 at a small offset from that label.
2924 @cindex @code{builtin_longjmp} instruction pattern
2925 @item @samp{builtin_longjmp}
2926 This pattern, if defined, performs the entire action of the longjmp.
2927 You will not normally need to define this pattern unless you also define
2928 @code{builtin_setjmp_setup}. The single argument is a pointer to the
2931 @cindex @code{eh_return} instruction pattern
2932 @item @samp{eh_return}
2933 This pattern, if defined, affects the way @code{__builtin_eh_return},
2934 and thence the call frame exception handling library routines, are
2935 built. It is intended to handle non-trivial actions needed along
2936 the abnormal return path.
2938 The pattern takes two arguments. The first is an offset to be applied
2939 to the stack pointer. It will have been copied to some appropriate
2940 location (typically @code{EH_RETURN_STACKADJ_RTX}) which will survive
2941 until after reload to when the normal epilogue is generated.
2942 The second argument is the address of the exception handler to which
2943 the function should return. This will normally need to copied by the
2944 pattern to some special register or memory location.
2946 This pattern only needs to be defined if call frame exception handling
2947 is to be used, and simple moves involving @code{EH_RETURN_STACKADJ_RTX}
2948 and @code{EH_RETURN_HANDLER_RTX} are not sufficient.
2950 @cindex @code{prologue} instruction pattern
2951 @anchor{prologue instruction pattern}
2952 @item @samp{prologue}
2953 This pattern, if defined, emits RTL for entry to a function. The function
2954 entry is responsible for setting up the stack frame, initializing the frame
2955 pointer register, saving callee saved registers, etc.
2957 Using a prologue pattern is generally preferred over defining
2958 @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue.
2960 The @code{prologue} pattern is particularly useful for targets which perform
2961 instruction scheduling.
2963 @cindex @code{epilogue} instruction pattern
2964 @anchor{epilogue instruction pattern}
2965 @item @samp{epilogue}
2966 This pattern emits RTL for exit from a function. The function
2967 exit is responsible for deallocating the stack frame, restoring callee saved
2968 registers and emitting the return instruction.
2970 Using an epilogue pattern is generally preferred over defining
2971 @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue.
2973 The @code{epilogue} pattern is particularly useful for targets which perform
2974 instruction scheduling or which have delay slots for their return instruction.
2976 @cindex @code{sibcall_epilogue} instruction pattern
2977 @item @samp{sibcall_epilogue}
2978 This pattern, if defined, emits RTL for exit from a function without the final
2979 branch back to the calling function. This pattern will be emitted before any
2980 sibling call (aka tail call) sites.
2982 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
2983 parameter passing or any stack slots for arguments passed to the current
2986 @cindex @code{trap} instruction pattern
2988 This pattern, if defined, signals an error, typically by causing some
2989 kind of signal to be raised. Among other places, it is used by the Java
2990 front end to signal `invalid array index' exceptions.
2992 @cindex @code{conditional_trap} instruction pattern
2993 @item @samp{conditional_trap}
2994 Conditional trap instruction. Operand 0 is a piece of RTL which
2995 performs a comparison. Operand 1 is the trap code, an integer.
2997 A typical @code{conditional_trap} pattern looks like
3000 (define_insn "conditional_trap"
3001 [(trap_if (match_operator 0 "trap_operator"
3002 [(cc0) (const_int 0)])
3003 (match_operand 1 "const_int_operand" "i"))]
3008 @cindex @code{cycle_display} instruction pattern
3009 @item @samp{cycle_display}
3011 This pattern, if present, will be emitted by the instruction scheduler at
3012 the beginning of each new clock cycle. This can be used for annotating the
3013 assembler output with cycle counts. Operand 0 is a @code{const_int} that
3014 holds the clock cycle.
3018 @node Pattern Ordering
3019 @section When the Order of Patterns Matters
3020 @cindex Pattern Ordering
3021 @cindex Ordering of Patterns
3023 Sometimes an insn can match more than one instruction pattern. Then the
3024 pattern that appears first in the machine description is the one used.
3025 Therefore, more specific patterns (patterns that will match fewer things)
3026 and faster instructions (those that will produce better code when they
3027 do match) should usually go first in the description.
3029 In some cases the effect of ordering the patterns can be used to hide
3030 a pattern when it is not valid. For example, the 68000 has an
3031 instruction for converting a fullword to floating point and another
3032 for converting a byte to floating point. An instruction converting
3033 an integer to floating point could match either one. We put the
3034 pattern to convert the fullword first to make sure that one will
3035 be used rather than the other. (Otherwise a large integer might
3036 be generated as a single-byte immediate quantity, which would not work.)
3037 Instead of using this pattern ordering it would be possible to make the
3038 pattern for convert-a-byte smart enough to deal properly with any
3041 @node Dependent Patterns
3042 @section Interdependence of Patterns
3043 @cindex Dependent Patterns
3044 @cindex Interdependence of Patterns
3046 Every machine description must have a named pattern for each of the
3047 conditional branch names @samp{b@var{cond}}. The recognition template
3048 must always have the form
3052 (if_then_else (@var{cond} (cc0) (const_int 0))
3053 (label_ref (match_operand 0 "" ""))
3058 In addition, every machine description must have an anonymous pattern
3059 for each of the possible reverse-conditional branches. Their templates
3064 (if_then_else (@var{cond} (cc0) (const_int 0))
3066 (label_ref (match_operand 0 "" ""))))
3070 They are necessary because jump optimization can turn direct-conditional
3071 branches into reverse-conditional branches.
3073 It is often convenient to use the @code{match_operator} construct to
3074 reduce the number of patterns that must be specified for branches. For
3080 (if_then_else (match_operator 0 "comparison_operator"
3081 [(cc0) (const_int 0)])
3083 (label_ref (match_operand 1 "" ""))))]
3088 In some cases machines support instructions identical except for the
3089 machine mode of one or more operands. For example, there may be
3090 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
3094 (set (match_operand:SI 0 @dots{})
3095 (extend:SI (match_operand:HI 1 @dots{})))
3097 (set (match_operand:SI 0 @dots{})
3098 (extend:SI (match_operand:QI 1 @dots{})))
3102 Constant integers do not specify a machine mode, so an instruction to
3103 extend a constant value could match either pattern. The pattern it
3104 actually will match is the one that appears first in the file. For correct
3105 results, this must be the one for the widest possible mode (@code{HImode},
3106 here). If the pattern matches the @code{QImode} instruction, the results
3107 will be incorrect if the constant value does not actually fit that mode.
3109 Such instructions to extend constants are rarely generated because they are
3110 optimized away, but they do occasionally happen in nonoptimized
3113 If a constraint in a pattern allows a constant, the reload pass may
3114 replace a register with a constant permitted by the constraint in some
3115 cases. Similarly for memory references. Because of this substitution,
3116 you should not provide separate patterns for increment and decrement
3117 instructions. Instead, they should be generated from the same pattern
3118 that supports register-register add insns by examining the operands and
3119 generating the appropriate machine instruction.
3122 @section Defining Jump Instruction Patterns
3123 @cindex jump instruction patterns
3124 @cindex defining jump instruction patterns
3126 For most machines, GCC assumes that the machine has a condition code.
3127 A comparison insn sets the condition code, recording the results of both
3128 signed and unsigned comparison of the given operands. A separate branch
3129 insn tests the condition code and branches or not according its value.
3130 The branch insns come in distinct signed and unsigned flavors. Many
3131 common machines, such as the VAX, the 68000 and the 32000, work this
3134 Some machines have distinct signed and unsigned compare instructions, and
3135 only one set of conditional branch instructions. The easiest way to handle
3136 these machines is to treat them just like the others until the final stage
3137 where assembly code is written. At this time, when outputting code for the
3138 compare instruction, peek ahead at the following branch using
3139 @code{next_cc0_user (insn)}. (The variable @code{insn} refers to the insn
3140 being output, in the output-writing code in an instruction pattern.) If
3141 the RTL says that is an unsigned branch, output an unsigned compare;
3142 otherwise output a signed compare. When the branch itself is output, you
3143 can treat signed and unsigned branches identically.
3145 The reason you can do this is that GCC always generates a pair of
3146 consecutive RTL insns, possibly separated by @code{note} insns, one to
3147 set the condition code and one to test it, and keeps the pair inviolate
3150 To go with this technique, you must define the machine-description macro
3151 @code{NOTICE_UPDATE_CC} to do @code{CC_STATUS_INIT}; in other words, no
3152 compare instruction is superfluous.
3154 Some machines have compare-and-branch instructions and no condition code.
3155 A similar technique works for them. When it is time to ``output'' a
3156 compare instruction, record its operands in two static variables. When
3157 outputting the branch-on-condition-code instruction that follows, actually
3158 output a compare-and-branch instruction that uses the remembered operands.
3160 It also works to define patterns for compare-and-branch instructions.
3161 In optimizing compilation, the pair of compare and branch instructions
3162 will be combined according to these patterns. But this does not happen
3163 if optimization is not requested. So you must use one of the solutions
3164 above in addition to any special patterns you define.
3166 In many RISC machines, most instructions do not affect the condition
3167 code and there may not even be a separate condition code register. On
3168 these machines, the restriction that the definition and use of the
3169 condition code be adjacent insns is not necessary and can prevent
3170 important optimizations. For example, on the IBM RS/6000, there is a
3171 delay for taken branches unless the condition code register is set three
3172 instructions earlier than the conditional branch. The instruction
3173 scheduler cannot perform this optimization if it is not permitted to
3174 separate the definition and use of the condition code register.
3176 On these machines, do not use @code{(cc0)}, but instead use a register
3177 to represent the condition code. If there is a specific condition code
3178 register in the machine, use a hard register. If the condition code or
3179 comparison result can be placed in any general register, or if there are
3180 multiple condition registers, use a pseudo register.
3182 @findex prev_cc0_setter
3183 @findex next_cc0_user
3184 On some machines, the type of branch instruction generated may depend on
3185 the way the condition code was produced; for example, on the 68k and
3186 Sparc, setting the condition code directly from an add or subtract
3187 instruction does not clear the overflow bit the way that a test
3188 instruction does, so a different branch instruction must be used for
3189 some conditional branches. For machines that use @code{(cc0)}, the set
3190 and use of the condition code must be adjacent (separated only by
3191 @code{note} insns) allowing flags in @code{cc_status} to be used.
3192 (@xref{Condition Code}.) Also, the comparison and branch insns can be
3193 located from each other by using the functions @code{prev_cc0_setter}
3194 and @code{next_cc0_user}.
3196 However, this is not true on machines that do not use @code{(cc0)}. On
3197 those machines, no assumptions can be made about the adjacency of the
3198 compare and branch insns and the above methods cannot be used. Instead,
3199 we use the machine mode of the condition code register to record
3200 different formats of the condition code register.
3202 Registers used to store the condition code value should have a mode that
3203 is in class @code{MODE_CC}. Normally, it will be @code{CCmode}. If
3204 additional modes are required (as for the add example mentioned above in
3205 the Sparc), define the macro @code{EXTRA_CC_MODES} to list the
3206 additional modes required (@pxref{Condition Code}). Also define
3207 @code{SELECT_CC_MODE} to choose a mode given an operand of a compare.
3209 If it is known during RTL generation that a different mode will be
3210 required (for example, if the machine has separate compare instructions
3211 for signed and unsigned quantities, like most IBM processors), they can
3212 be specified at that time.
3214 If the cases that require different modes would be made by instruction
3215 combination, the macro @code{SELECT_CC_MODE} determines which machine
3216 mode should be used for the comparison result. The patterns should be
3217 written using that mode. To support the case of the add on the Sparc
3218 discussed above, we have the pattern
3222 [(set (reg:CC_NOOV 0)
3224 (plus:SI (match_operand:SI 0 "register_operand" "%r")
3225 (match_operand:SI 1 "arith_operand" "rI"))
3231 The @code{SELECT_CC_MODE} macro on the Sparc returns @code{CC_NOOVmode}
3232 for comparisons whose argument is a @code{plus}.
3234 @node Looping Patterns
3235 @section Defining Looping Instruction Patterns
3236 @cindex looping instruction patterns
3237 @cindex defining looping instruction patterns
3239 Some machines have special jump instructions that can be utilised to
3240 make loops more efficient. A common example is the 68000 @samp{dbra}
3241 instruction which performs a decrement of a register and a branch if the
3242 result was greater than zero. Other machines, in particular digital
3243 signal processors (DSPs), have special block repeat instructions to
3244 provide low-overhead loop support. For example, the TI TMS320C3x/C4x
3245 DSPs have a block repeat instruction that loads special registers to
3246 mark the top and end of a loop and to count the number of loop
3247 iterations. This avoids the need for fetching and executing a
3248 @samp{dbra}-like instruction and avoids pipeline stalls associated with
3251 GCC has three special named patterns to support low overhead looping.
3252 They are @samp{decrement_and_branch_until_zero}, @samp{doloop_begin},
3253 and @samp{doloop_end}. The first pattern,
3254 @samp{decrement_and_branch_until_zero}, is not emitted during RTL
3255 generation but may be emitted during the instruction combination phase.
3256 This requires the assistance of the loop optimizer, using information
3257 collected during strength reduction, to reverse a loop to count down to
3258 zero. Some targets also require the loop optimizer to add a
3259 @code{REG_NONNEG} note to indicate that the iteration count is always
3260 positive. This is needed if the target performs a signed loop
3261 termination test. For example, the 68000 uses a pattern similar to the
3262 following for its @code{dbra} instruction:
3266 (define_insn "decrement_and_branch_until_zero"
3269 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
3272 (label_ref (match_operand 1 "" ""))
3275 (plus:SI (match_dup 0)
3277 "find_reg_note (insn, REG_NONNEG, 0)"
3282 Note that since the insn is both a jump insn and has an output, it must
3283 deal with its own reloads, hence the `m' constraints. Also note that
3284 since this insn is generated by the instruction combination phase
3285 combining two sequential insns together into an implicit parallel insn,
3286 the iteration counter needs to be biased by the same amount as the
3287 decrement operation, in this case @minus{}1. Note that the following similar
3288 pattern will not be matched by the combiner.
3292 (define_insn "decrement_and_branch_until_zero"
3295 (ge (match_operand:SI 0 "general_operand" "+d*am")
3297 (label_ref (match_operand 1 "" ""))
3300 (plus:SI (match_dup 0)
3302 "find_reg_note (insn, REG_NONNEG, 0)"
3307 The other two special looping patterns, @samp{doloop_begin} and
3308 @samp{doloop_end}, are emitted by the loop optimiser for certain
3309 well-behaved loops with a finite number of loop iterations using
3310 information collected during strength reduction.
3312 The @samp{doloop_end} pattern describes the actual looping instruction
3313 (or the implicit looping operation) and the @samp{doloop_begin} pattern
3314 is an optional companion pattern that can be used for initialisation
3315 needed for some low-overhead looping instructions.
3317 Note that some machines require the actual looping instruction to be
3318 emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
3319 the true RTL for a looping instruction at the top of the loop can cause
3320 problems with flow analysis. So instead, a dummy @code{doloop} insn is
3321 emitted at the end of the loop. The machine dependent reorg pass checks
3322 for the presence of this @code{doloop} insn and then searches back to
3323 the top of the loop, where it inserts the true looping insn (provided
3324 there are no instructions in the loop which would cause problems). Any
3325 additional labels can be emitted at this point. In addition, if the
3326 desired special iteration counter register was not allocated, this
3327 machine dependent reorg pass could emit a traditional compare and jump
3330 The essential difference between the
3331 @samp{decrement_and_branch_until_zero} and the @samp{doloop_end}
3332 patterns is that the loop optimizer allocates an additional pseudo
3333 register for the latter as an iteration counter. This pseudo register
3334 cannot be used within the loop (i.e., general induction variables cannot
3335 be derived from it), however, in many cases the loop induction variable
3336 may become redundant and removed by the flow pass.
3339 @node Insn Canonicalizations
3340 @section Canonicalization of Instructions
3341 @cindex canonicalization of instructions
3342 @cindex insn canonicalization
3344 There are often cases where multiple RTL expressions could represent an
3345 operation performed by a single machine instruction. This situation is
3346 most commonly encountered with logical, branch, and multiply-accumulate
3347 instructions. In such cases, the compiler attempts to convert these
3348 multiple RTL expressions into a single canonical form to reduce the
3349 number of insn patterns required.
3351 In addition to algebraic simplifications, following canonicalizations
3356 For commutative and comparison operators, a constant is always made the
3357 second operand. If a machine only supports a constant as the second
3358 operand, only patterns that match a constant in the second operand need
3361 @cindex @code{neg}, canonicalization of
3362 @cindex @code{not}, canonicalization of
3363 @cindex @code{mult}, canonicalization of
3364 @cindex @code{plus}, canonicalization of
3365 @cindex @code{minus}, canonicalization of
3366 For these operators, if only one operand is a @code{neg}, @code{not},
3367 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
3370 @cindex @code{compare}, canonicalization of
3372 For the @code{compare} operator, a constant is always the second operand
3373 on machines where @code{cc0} is used (@pxref{Jump Patterns}). On other
3374 machines, there are rare cases where the compiler might want to construct
3375 a @code{compare} with a constant as the first operand. However, these
3376 cases are not common enough for it to be worthwhile to provide a pattern
3377 matching a constant as the first operand unless the machine actually has
3378 such an instruction.
3380 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
3381 @code{minus} is made the first operand under the same conditions as
3385 @code{(minus @var{x} (const_int @var{n}))} is converted to
3386 @code{(plus @var{x} (const_int @var{-n}))}.
3389 Within address computations (i.e., inside @code{mem}), a left shift is
3390 converted into the appropriate multiplication by a power of two.
3392 @cindex @code{ior}, canonicalization of
3393 @cindex @code{and}, canonicalization of
3394 @cindex De Morgan's law
3396 De`Morgan's Law is used to move bitwise negation inside a bitwise
3397 logical-and or logical-or operation. If this results in only one
3398 operand being a @code{not} expression, it will be the first one.
3400 A machine that has an instruction that performs a bitwise logical-and of one
3401 operand with the bitwise negation of the other should specify the pattern
3402 for that instruction as
3406 [(set (match_operand:@var{m} 0 @dots{})
3407 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
3408 (match_operand:@var{m} 2 @dots{})))]
3414 Similarly, a pattern for a ``NAND'' instruction should be written
3418 [(set (match_operand:@var{m} 0 @dots{})
3419 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
3420 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
3425 In both cases, it is not necessary to include patterns for the many
3426 logically equivalent RTL expressions.
3428 @cindex @code{xor}, canonicalization of
3430 The only possible RTL expressions involving both bitwise exclusive-or
3431 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
3432 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
3435 The sum of three items, one of which is a constant, will only appear in
3439 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
3443 On machines that do not use @code{cc0},
3444 @code{(compare @var{x} (const_int 0))} will be converted to
3447 @cindex @code{zero_extract}, canonicalization of
3448 @cindex @code{sign_extract}, canonicalization of
3450 Equality comparisons of a group of bits (usually a single bit) with zero
3451 will be written using @code{zero_extract} rather than the equivalent
3452 @code{and} or @code{sign_extract} operations.
3456 @node Expander Definitions
3457 @section Defining RTL Sequences for Code Generation
3458 @cindex expander definitions
3459 @cindex code generation RTL sequences
3460 @cindex defining RTL sequences for code generation
3462 On some target machines, some standard pattern names for RTL generation
3463 cannot be handled with single insn, but a sequence of RTL insns can
3464 represent them. For these target machines, you can write a
3465 @code{define_expand} to specify how to generate the sequence of RTL@.
3467 @findex define_expand
3468 A @code{define_expand} is an RTL expression that looks almost like a
3469 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
3470 only for RTL generation and it can produce more than one RTL insn.
3472 A @code{define_expand} RTX has four operands:
3476 The name. Each @code{define_expand} must have a name, since the only
3477 use for it is to refer to it by name.
3480 The RTL template. This is a vector of RTL expressions representing
3481 a sequence of separate instructions. Unlike @code{define_insn}, there
3482 is no implicit surrounding @code{PARALLEL}.
3485 The condition, a string containing a C expression. This expression is
3486 used to express how the availability of this pattern depends on
3487 subclasses of target machine, selected by command-line options when GCC
3488 is run. This is just like the condition of a @code{define_insn} that
3489 has a standard name. Therefore, the condition (if present) may not
3490 depend on the data in the insn being matched, but only the
3491 target-machine-type flags. The compiler needs to test these conditions
3492 during initialization in order to learn exactly which named instructions
3493 are available in a particular run.
3496 The preparation statements, a string containing zero or more C
3497 statements which are to be executed before RTL code is generated from
3500 Usually these statements prepare temporary registers for use as
3501 internal operands in the RTL template, but they can also generate RTL
3502 insns directly by calling routines such as @code{emit_insn}, etc.
3503 Any such insns precede the ones that come from the RTL template.
3506 Every RTL insn emitted by a @code{define_expand} must match some
3507 @code{define_insn} in the machine description. Otherwise, the compiler
3508 will crash when trying to generate code for the insn or trying to optimize
3511 The RTL template, in addition to controlling generation of RTL insns,
3512 also describes the operands that need to be specified when this pattern
3513 is used. In particular, it gives a predicate for each operand.
3515 A true operand, which needs to be specified in order to generate RTL from
3516 the pattern, should be described with a @code{match_operand} in its first
3517 occurrence in the RTL template. This enters information on the operand's
3518 predicate into the tables that record such things. GCC uses the
3519 information to preload the operand into a register if that is required for
3520 valid RTL code. If the operand is referred to more than once, subsequent
3521 references should use @code{match_dup}.
3523 The RTL template may also refer to internal ``operands'' which are
3524 temporary registers or labels used only within the sequence made by the
3525 @code{define_expand}. Internal operands are substituted into the RTL
3526 template with @code{match_dup}, never with @code{match_operand}. The
3527 values of the internal operands are not passed in as arguments by the
3528 compiler when it requests use of this pattern. Instead, they are computed
3529 within the pattern, in the preparation statements. These statements
3530 compute the values and store them into the appropriate elements of
3531 @code{operands} so that @code{match_dup} can find them.
3533 There are two special macros defined for use in the preparation statements:
3534 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
3541 Use the @code{DONE} macro to end RTL generation for the pattern. The
3542 only RTL insns resulting from the pattern on this occasion will be
3543 those already emitted by explicit calls to @code{emit_insn} within the
3544 preparation statements; the RTL template will not be generated.
3548 Make the pattern fail on this occasion. When a pattern fails, it means
3549 that the pattern was not truly available. The calling routines in the
3550 compiler will try other strategies for code generation using other patterns.
3552 Failure is currently supported only for binary (addition, multiplication,
3553 shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv})
3557 If the preparation falls through (invokes neither @code{DONE} nor
3558 @code{FAIL}), then the @code{define_expand} acts like a
3559 @code{define_insn} in that the RTL template is used to generate the
3562 The RTL template is not used for matching, only for generating the
3563 initial insn list. If the preparation statement always invokes
3564 @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple
3565 list of operands, such as this example:
3569 (define_expand "addsi3"
3570 [(match_operand:SI 0 "register_operand" "")
3571 (match_operand:SI 1 "register_operand" "")
3572 (match_operand:SI 2 "register_operand" "")]
3578 handle_add (operands[0], operands[1], operands[2]);
3584 Here is an example, the definition of left-shift for the SPUR chip:
3588 (define_expand "ashlsi3"
3589 [(set (match_operand:SI 0 "register_operand" "")
3593 (match_operand:SI 1 "register_operand" "")
3594 (match_operand:SI 2 "nonmemory_operand" "")))]
3603 if (GET_CODE (operands[2]) != CONST_INT
3604 || (unsigned) INTVAL (operands[2]) > 3)
3611 This example uses @code{define_expand} so that it can generate an RTL insn
3612 for shifting when the shift-count is in the supported range of 0 to 3 but
3613 fail in other cases where machine insns aren't available. When it fails,
3614 the compiler tries another strategy using different patterns (such as, a
3617 If the compiler were able to handle nontrivial condition-strings in
3618 patterns with names, then it would be possible to use a
3619 @code{define_insn} in that case. Here is another case (zero-extension
3620 on the 68000) which makes more use of the power of @code{define_expand}:
3623 (define_expand "zero_extendhisi2"
3624 [(set (match_operand:SI 0 "general_operand" "")
3626 (set (strict_low_part
3630 (match_operand:HI 1 "general_operand" ""))]
3632 "operands[1] = make_safe_from (operands[1], operands[0]);")
3636 @findex make_safe_from
3637 Here two RTL insns are generated, one to clear the entire output operand
3638 and the other to copy the input operand into its low half. This sequence
3639 is incorrect if the input operand refers to [the old value of] the output
3640 operand, so the preparation statement makes sure this isn't so. The
3641 function @code{make_safe_from} copies the @code{operands[1]} into a
3642 temporary register if it refers to @code{operands[0]}. It does this
3643 by emitting another RTL insn.
3645 Finally, a third example shows the use of an internal operand.
3646 Zero-extension on the SPUR chip is done by @code{and}-ing the result
3647 against a halfword mask. But this mask cannot be represented by a
3648 @code{const_int} because the constant value is too large to be legitimate
3649 on this machine. So it must be copied into a register with
3650 @code{force_reg} and then the register used in the @code{and}.
3653 (define_expand "zero_extendhisi2"
3654 [(set (match_operand:SI 0 "register_operand" "")
3656 (match_operand:HI 1 "register_operand" "")
3661 = force_reg (SImode, GEN_INT (65535)); ")
3664 @strong{Note:} If the @code{define_expand} is used to serve a
3665 standard binary or unary arithmetic operation or a bit-field operation,
3666 then the last insn it generates must not be a @code{code_label},
3667 @code{barrier} or @code{note}. It must be an @code{insn},
3668 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
3669 at the end, emit an insn to copy the result of the operation into
3670 itself. Such an insn will generate no code, but it can avoid problems
3673 @node Insn Splitting
3674 @section Defining How to Split Instructions
3675 @cindex insn splitting
3676 @cindex instruction splitting
3677 @cindex splitting instructions
3679 There are two cases where you should specify how to split a pattern into
3680 multiple insns. On machines that have instructions requiring delay
3681 slots (@pxref{Delay Slots}) or that have instructions whose output is
3682 not available for multiple cycles (@pxref{Function Units}), the compiler
3683 phases that optimize these cases need to be able to move insns into
3684 one-instruction delay slots. However, some insns may generate more than one
3685 machine instruction. These insns cannot be placed into a delay slot.
3687 Often you can rewrite the single insn as a list of individual insns,
3688 each corresponding to one machine instruction. The disadvantage of
3689 doing so is that it will cause the compilation to be slower and require
3690 more space. If the resulting insns are too complex, it may also
3691 suppress some optimizations. The compiler splits the insn if there is a
3692 reason to believe that it might improve instruction or delay slot
3695 The insn combiner phase also splits putative insns. If three insns are
3696 merged into one insn with a complex expression that cannot be matched by
3697 some @code{define_insn} pattern, the combiner phase attempts to split
3698 the complex pattern into two insns that are recognized. Usually it can
3699 break the complex pattern into two patterns by splitting out some
3700 subexpression. However, in some other cases, such as performing an
3701 addition of a large constant in two insns on a RISC machine, the way to
3702 split the addition into two insns is machine-dependent.
3704 @findex define_split
3705 The @code{define_split} definition tells the compiler how to split a
3706 complex insn into several simpler insns. It looks like this:
3710 [@var{insn-pattern}]
3712 [@var{new-insn-pattern-1}
3713 @var{new-insn-pattern-2}
3715 "@var{preparation-statements}")
3718 @var{insn-pattern} is a pattern that needs to be split and
3719 @var{condition} is the final condition to be tested, as in a
3720 @code{define_insn}. When an insn matching @var{insn-pattern} and
3721 satisfying @var{condition} is found, it is replaced in the insn list
3722 with the insns given by @var{new-insn-pattern-1},
3723 @var{new-insn-pattern-2}, etc.
3725 The @var{preparation-statements} are similar to those statements that
3726 are specified for @code{define_expand} (@pxref{Expander Definitions})
3727 and are executed before the new RTL is generated to prepare for the
3728 generated code or emit some insns whose pattern is not fixed. Unlike
3729 those in @code{define_expand}, however, these statements must not
3730 generate any new pseudo-registers. Once reload has completed, they also
3731 must not allocate any space in the stack frame.
3733 Patterns are matched against @var{insn-pattern} in two different
3734 circumstances. If an insn needs to be split for delay slot scheduling
3735 or insn scheduling, the insn is already known to be valid, which means
3736 that it must have been matched by some @code{define_insn} and, if
3737 @code{reload_completed} is non-zero, is known to satisfy the constraints
3738 of that @code{define_insn}. In that case, the new insn patterns must
3739 also be insns that are matched by some @code{define_insn} and, if
3740 @code{reload_completed} is non-zero, must also satisfy the constraints
3741 of those definitions.
3743 As an example of this usage of @code{define_split}, consider the following
3744 example from @file{a29k.md}, which splits a @code{sign_extend} from
3745 @code{HImode} to @code{SImode} into a pair of shift insns:
3749 [(set (match_operand:SI 0 "gen_reg_operand" "")
3750 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
3753 (ashift:SI (match_dup 1)
3756 (ashiftrt:SI (match_dup 0)
3759 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
3762 When the combiner phase tries to split an insn pattern, it is always the
3763 case that the pattern is @emph{not} matched by any @code{define_insn}.
3764 The combiner pass first tries to split a single @code{set} expression
3765 and then the same @code{set} expression inside a @code{parallel}, but
3766 followed by a @code{clobber} of a pseudo-reg to use as a scratch
3767 register. In these cases, the combiner expects exactly two new insn
3768 patterns to be generated. It will verify that these patterns match some
3769 @code{define_insn} definitions, so you need not do this test in the
3770 @code{define_split} (of course, there is no point in writing a
3771 @code{define_split} that will never produce insns that match).
3773 Here is an example of this use of @code{define_split}, taken from
3778 [(set (match_operand:SI 0 "gen_reg_operand" "")
3779 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
3780 (match_operand:SI 2 "non_add_cint_operand" "")))]
3782 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
3783 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
3786 int low = INTVAL (operands[2]) & 0xffff;
3787 int high = (unsigned) INTVAL (operands[2]) >> 16;
3790 high++, low |= 0xffff0000;
3792 operands[3] = GEN_INT (high << 16);
3793 operands[4] = GEN_INT (low);
3797 Here the predicate @code{non_add_cint_operand} matches any
3798 @code{const_int} that is @emph{not} a valid operand of a single add
3799 insn. The add with the smaller displacement is written so that it
3800 can be substituted into the address of a subsequent operation.
3802 An example that uses a scratch register, from the same file, generates
3803 an equality comparison of a register and a large constant:
3807 [(set (match_operand:CC 0 "cc_reg_operand" "")
3808 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
3809 (match_operand:SI 2 "non_short_cint_operand" "")))
3810 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
3811 "find_single_use (operands[0], insn, 0)
3812 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
3813 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
3814 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
3815 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
3818 /* Get the constant we are comparing against, C, and see what it
3819 looks like sign-extended to 16 bits. Then see what constant
3820 could be XOR'ed with C to get the sign-extended value. */
3822 int c = INTVAL (operands[2]);
3823 int sextc = (c << 16) >> 16;
3824 int xorv = c ^ sextc;
3826 operands[4] = GEN_INT (xorv);
3827 operands[5] = GEN_INT (sextc);
3831 To avoid confusion, don't write a single @code{define_split} that
3832 accepts some insns that match some @code{define_insn} as well as some
3833 insns that don't. Instead, write two separate @code{define_split}
3834 definitions, one for the insns that are valid and one for the insns that
3837 The splitter is allowed to split jump instructions into sequence of
3838 jumps or create new jumps in while splitting non-jump instructions. As
3839 the central flowgraph and branch prediction information needs to be updated,
3840 several restriction apply.
3842 Splitting of jump instruction into sequence that over by another jump
3843 instruction is always valid, as compiler expect identical behaviour of new
3844 jump. When new sequence contains multiple jump instructions or new labels,
3845 more assistance is needed. Splitter is required to create only unconditional
3846 jumps, or simple conditional jump instructions. Additionally it must attach a
3847 @code{REG_BR_PROB} note to each conditional jump. An global variable
3848 @code{split_branch_probability} hold the probability of original branch in case
3849 it was an simple conditional jump, @minus{}1 otherwise. To simplify
3850 recomputing of edge frequencies, new sequence is required to have only
3851 forward jumps to the newly created labels.
3853 For the common case where the pattern of a define_split exactly matches the
3854 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
3858 (define_insn_and_split
3859 [@var{insn-pattern}]
3861 "@var{output-template}"
3862 "@var{split-condition}"
3863 [@var{new-insn-pattern-1}
3864 @var{new-insn-pattern-2}
3866 "@var{preparation-statements}"
3867 [@var{insn-attributes}])
3871 @var{insn-pattern}, @var{condition}, @var{output-template}, and
3872 @var{insn-attributes} are used as in @code{define_insn}. The
3873 @var{new-insn-pattern} vector and the @var{preparation-statements} are used as
3874 in a @code{define_split}. The @var{split-condition} is also used as in
3875 @code{define_split}, with the additional behavior that if the condition starts
3876 with @samp{&&}, the condition used for the split will be the constructed as a
3877 logical ``and'' of the split condition with the insn condition. For example,
3881 (define_insn_and_split "zero_extendhisi2_and"
3882 [(set (match_operand:SI 0 "register_operand" "=r")
3883 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
3884 (clobber (reg:CC 17))]
3885 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3887 "&& reload_completed"
3888 [(parallel [(set (match_dup 0)
3889 (and:SI (match_dup 0) (const_int 65535)))
3890 (clobber (reg:CC 17))])]
3892 [(set_attr "type" "alu1")])
3896 In this case, the actual split condition will be
3897 @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
3899 The @code{define_insn_and_split} construction provides exactly the same
3900 functionality as two separate @code{define_insn} and @code{define_split}
3901 patterns. It exists for compactness, and as a maintenance tool to prevent
3902 having to ensure the two patterns' templates match.
3904 @node Peephole Definitions
3905 @section Machine-Specific Peephole Optimizers
3906 @cindex peephole optimizer definitions
3907 @cindex defining peephole optimizers
3909 In addition to instruction patterns the @file{md} file may contain
3910 definitions of machine-specific peephole optimizations.
3912 The combiner does not notice certain peephole optimizations when the data
3913 flow in the program does not suggest that it should try them. For example,
3914 sometimes two consecutive insns related in purpose can be combined even
3915 though the second one does not appear to use a register computed in the
3916 first one. A machine-specific peephole optimizer can detect such
3919 There are two forms of peephole definitions that may be used. The
3920 original @code{define_peephole} is run at assembly output time to
3921 match insns and substitute assembly text. Use of @code{define_peephole}
3924 A newer @code{define_peephole2} matches insns and substitutes new
3925 insns. The @code{peephole2} pass is run after register allocation
3926 but before scheduling, which may result in much better code for
3927 targets that do scheduling.
3930 * define_peephole:: RTL to Text Peephole Optimizers
3931 * define_peephole2:: RTL to RTL Peephole Optimizers
3934 @node define_peephole
3935 @subsection RTL to Text Peephole Optimizers
3936 @findex define_peephole
3939 A definition looks like this:
3943 [@var{insn-pattern-1}
3944 @var{insn-pattern-2}
3948 "@var{optional-insn-attributes}")
3952 The last string operand may be omitted if you are not using any
3953 machine-specific information in this machine description. If present,
3954 it must obey the same rules as in a @code{define_insn}.
3956 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
3957 consecutive insns. The optimization applies to a sequence of insns when
3958 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
3959 the next, and so on.
3961 Each of the insns matched by a peephole must also match a
3962 @code{define_insn}. Peepholes are checked only at the last stage just
3963 before code generation, and only optionally. Therefore, any insn which
3964 would match a peephole but no @code{define_insn} will cause a crash in code
3965 generation in an unoptimized compilation, or at various optimization
3968 The operands of the insns are matched with @code{match_operands},
3969 @code{match_operator}, and @code{match_dup}, as usual. What is not
3970 usual is that the operand numbers apply to all the insn patterns in the
3971 definition. So, you can check for identical operands in two insns by
3972 using @code{match_operand} in one insn and @code{match_dup} in the
3975 The operand constraints used in @code{match_operand} patterns do not have
3976 any direct effect on the applicability of the peephole, but they will
3977 be validated afterward, so make sure your constraints are general enough
3978 to apply whenever the peephole matches. If the peephole matches
3979 but the constraints are not satisfied, the compiler will crash.
3981 It is safe to omit constraints in all the operands of the peephole; or
3982 you can write constraints which serve as a double-check on the criteria
3985 Once a sequence of insns matches the patterns, the @var{condition} is
3986 checked. This is a C expression which makes the final decision whether to
3987 perform the optimization (we do so if the expression is nonzero). If
3988 @var{condition} is omitted (in other words, the string is empty) then the
3989 optimization is applied to every sequence of insns that matches the
3992 The defined peephole optimizations are applied after register allocation
3993 is complete. Therefore, the peephole definition can check which
3994 operands have ended up in which kinds of registers, just by looking at
3997 @findex prev_active_insn
3998 The way to refer to the operands in @var{condition} is to write
3999 @code{operands[@var{i}]} for operand number @var{i} (as matched by
4000 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
4001 to refer to the last of the insns being matched; use
4002 @code{prev_active_insn} to find the preceding insns.
4004 @findex dead_or_set_p
4005 When optimizing computations with intermediate results, you can use
4006 @var{condition} to match only when the intermediate results are not used
4007 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
4008 @var{op})}, where @var{insn} is the insn in which you expect the value
4009 to be used for the last time (from the value of @code{insn}, together
4010 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
4011 value (from @code{operands[@var{i}]}).
4013 Applying the optimization means replacing the sequence of insns with one
4014 new insn. The @var{template} controls ultimate output of assembler code
4015 for this combined insn. It works exactly like the template of a
4016 @code{define_insn}. Operand numbers in this template are the same ones
4017 used in matching the original sequence of insns.
4019 The result of a defined peephole optimizer does not need to match any of
4020 the insn patterns in the machine description; it does not even have an
4021 opportunity to match them. The peephole optimizer definition itself serves
4022 as the insn pattern to control how the insn is output.
4024 Defined peephole optimizers are run as assembler code is being output,
4025 so the insns they produce are never combined or rearranged in any way.
4027 Here is an example, taken from the 68000 machine description:
4031 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
4032 (set (match_operand:DF 0 "register_operand" "=f")
4033 (match_operand:DF 1 "register_operand" "ad"))]
4034 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
4037 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4039 output_asm_insn ("move.l %1,(sp)", xoperands);
4040 output_asm_insn ("move.l %1,-(sp)", operands);
4041 return "fmove.d (sp)+,%0";
4043 output_asm_insn ("movel %1,sp@@", xoperands);
4044 output_asm_insn ("movel %1,sp@@-", operands);
4045 return "fmoved sp@@+,%0";
4051 The effect of this optimization is to change
4077 If a peephole matches a sequence including one or more jump insns, you must
4078 take account of the flags such as @code{CC_REVERSED} which specify that the
4079 condition codes are represented in an unusual manner. The compiler
4080 automatically alters any ordinary conditional jumps which occur in such
4081 situations, but the compiler cannot alter jumps which have been replaced by
4082 peephole optimizations. So it is up to you to alter the assembler code
4083 that the peephole produces. Supply C code to write the assembler output,
4084 and in this C code check the condition code status flags and change the
4085 assembler code as appropriate.
4088 @var{insn-pattern-1} and so on look @emph{almost} like the second
4089 operand of @code{define_insn}. There is one important difference: the
4090 second operand of @code{define_insn} consists of one or more RTX's
4091 enclosed in square brackets. Usually, there is only one: then the same
4092 action can be written as an element of a @code{define_peephole}. But
4093 when there are multiple actions in a @code{define_insn}, they are
4094 implicitly enclosed in a @code{parallel}. Then you must explicitly
4095 write the @code{parallel}, and the square brackets within it, in the
4096 @code{define_peephole}. Thus, if an insn pattern looks like this,
4099 (define_insn "divmodsi4"
4100 [(set (match_operand:SI 0 "general_operand" "=d")
4101 (div:SI (match_operand:SI 1 "general_operand" "0")
4102 (match_operand:SI 2 "general_operand" "dmsK")))
4103 (set (match_operand:SI 3 "general_operand" "=d")
4104 (mod:SI (match_dup 1) (match_dup 2)))]
4106 "divsl%.l %2,%3:%0")
4110 then the way to mention this insn in a peephole is as follows:
4116 [(set (match_operand:SI 0 "general_operand" "=d")
4117 (div:SI (match_operand:SI 1 "general_operand" "0")
4118 (match_operand:SI 2 "general_operand" "dmsK")))
4119 (set (match_operand:SI 3 "general_operand" "=d")
4120 (mod:SI (match_dup 1) (match_dup 2)))])
4125 @node define_peephole2
4126 @subsection RTL to RTL Peephole Optimizers
4127 @findex define_peephole2
4129 The @code{define_peephole2} definition tells the compiler how to
4130 substitute one sequence of instructions for another sequence,
4131 what additional scratch registers may be needed and what their
4136 [@var{insn-pattern-1}
4137 @var{insn-pattern-2}
4140 [@var{new-insn-pattern-1}
4141 @var{new-insn-pattern-2}
4143 "@var{preparation-statements}")
4146 The definition is almost identical to @code{define_split}
4147 (@pxref{Insn Splitting}) except that the pattern to match is not a
4148 single instruction, but a sequence of instructions.
4150 It is possible to request additional scratch registers for use in the
4151 output template. If appropriate registers are not free, the pattern
4152 will simply not match.
4154 @findex match_scratch
4156 Scratch registers are requested with a @code{match_scratch} pattern at
4157 the top level of the input pattern. The allocated register (initially) will
4158 be dead at the point requested within the original sequence. If the scratch
4159 is used at more than a single point, a @code{match_dup} pattern at the
4160 top level of the input pattern marks the last position in the input sequence
4161 at which the register must be available.
4163 Here is an example from the IA-32 machine description:
4167 [(match_scratch:SI 2 "r")
4168 (parallel [(set (match_operand:SI 0 "register_operand" "")
4169 (match_operator:SI 3 "arith_or_logical_operator"
4171 (match_operand:SI 1 "memory_operand" "")]))
4172 (clobber (reg:CC 17))])]
4173 "! optimize_size && ! TARGET_READ_MODIFY"
4174 [(set (match_dup 2) (match_dup 1))
4175 (parallel [(set (match_dup 0)
4176 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
4177 (clobber (reg:CC 17))])]
4182 This pattern tries to split a load from its use in the hopes that we'll be
4183 able to schedule around the memory load latency. It allocates a single
4184 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
4185 to be live only at the point just before the arithmetic.
4187 A real example requiring extended scratch lifetimes is harder to come by,
4188 so here's a silly made-up example:
4192 [(match_scratch:SI 4 "r")
4193 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
4194 (set (match_operand:SI 2 "" "") (match_dup 1))
4196 (set (match_operand:SI 3 "" "") (match_dup 1))]
4197 "/* @r{determine 1 does not overlap 0 and 2} */"
4198 [(set (match_dup 4) (match_dup 1))
4199 (set (match_dup 0) (match_dup 4))
4200 (set (match_dup 2) (match_dup 4))]
4201 (set (match_dup 3) (match_dup 4))]
4206 If we had not added the @code{(match_dup 4)} in the middle of the input
4207 sequence, it might have been the case that the register we chose at the
4208 beginning of the sequence is killed by the first or second @code{set}.
4210 @node Insn Attributes
4211 @section Instruction Attributes
4212 @cindex insn attributes
4213 @cindex instruction attributes
4215 In addition to describing the instruction supported by the target machine,
4216 the @file{md} file also defines a group of @dfn{attributes} and a set of
4217 values for each. Every generated insn is assigned a value for each attribute.
4218 One possible attribute would be the effect that the insn has on the machine's
4219 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
4220 to track the condition codes.
4223 * Defining Attributes:: Specifying attributes and their values.
4224 * Expressions:: Valid expressions for attribute values.
4225 * Tagging Insns:: Assigning attribute values to insns.
4226 * Attr Example:: An example of assigning attributes.
4227 * Insn Lengths:: Computing the length of insns.
4228 * Constant Attributes:: Defining attributes that are constant.
4229 * Delay Slots:: Defining delay slots required for a machine.
4230 * Function Units:: Specifying information for insn scheduling.
4233 @node Defining Attributes
4234 @subsection Defining Attributes and their Values
4235 @cindex defining attributes and their values
4236 @cindex attributes, defining
4239 The @code{define_attr} expression is used to define each attribute required
4240 by the target machine. It looks like:
4243 (define_attr @var{name} @var{list-of-values} @var{default})
4246 @var{name} is a string specifying the name of the attribute being defined.
4248 @var{list-of-values} is either a string that specifies a comma-separated
4249 list of values that can be assigned to the attribute, or a null string to
4250 indicate that the attribute takes numeric values.
4252 @var{default} is an attribute expression that gives the value of this
4253 attribute for insns that match patterns whose definition does not include
4254 an explicit value for this attribute. @xref{Attr Example}, for more
4255 information on the handling of defaults. @xref{Constant Attributes},
4256 for information on attributes that do not depend on any particular insn.
4259 For each defined attribute, a number of definitions are written to the
4260 @file{insn-attr.h} file. For cases where an explicit set of values is
4261 specified for an attribute, the following are defined:
4265 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
4268 An enumeral class is defined for @samp{attr_@var{name}} with
4269 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
4270 the attribute name and value are first converted to upper case.
4273 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
4274 returns the attribute value for that insn.
4277 For example, if the following is present in the @file{md} file:
4280 (define_attr "type" "branch,fp,load,store,arith" @dots{})
4284 the following lines will be written to the file @file{insn-attr.h}.
4287 #define HAVE_ATTR_type
4288 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
4289 TYPE_STORE, TYPE_ARITH@};
4290 extern enum attr_type get_attr_type ();
4293 If the attribute takes numeric values, no @code{enum} type will be
4294 defined and the function to obtain the attribute's value will return
4298 @subsection Attribute Expressions
4299 @cindex attribute expressions
4301 RTL expressions used to define attributes use the codes described above
4302 plus a few specific to attribute definitions, to be discussed below.
4303 Attribute value expressions must have one of the following forms:
4306 @cindex @code{const_int} and attributes
4307 @item (const_int @var{i})
4308 The integer @var{i} specifies the value of a numeric attribute. @var{i}
4309 must be non-negative.
4311 The value of a numeric attribute can be specified either with a
4312 @code{const_int}, or as an integer represented as a string in
4313 @code{const_string}, @code{eq_attr} (see below), @code{attr},
4314 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
4315 overrides on specific instructions (@pxref{Tagging Insns}).
4317 @cindex @code{const_string} and attributes
4318 @item (const_string @var{value})
4319 The string @var{value} specifies a constant attribute value.
4320 If @var{value} is specified as @samp{"*"}, it means that the default value of
4321 the attribute is to be used for the insn containing this expression.
4322 @samp{"*"} obviously cannot be used in the @var{default} expression
4323 of a @code{define_attr}.
4325 If the attribute whose value is being specified is numeric, @var{value}
4326 must be a string containing a non-negative integer (normally
4327 @code{const_int} would be used in this case). Otherwise, it must
4328 contain one of the valid values for the attribute.
4330 @cindex @code{if_then_else} and attributes
4331 @item (if_then_else @var{test} @var{true-value} @var{false-value})
4332 @var{test} specifies an attribute test, whose format is defined below.
4333 The value of this expression is @var{true-value} if @var{test} is true,
4334 otherwise it is @var{false-value}.
4336 @cindex @code{cond} and attributes
4337 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
4338 The first operand of this expression is a vector containing an even
4339 number of expressions and consisting of pairs of @var{test} and @var{value}
4340 expressions. The value of the @code{cond} expression is that of the
4341 @var{value} corresponding to the first true @var{test} expression. If
4342 none of the @var{test} expressions are true, the value of the @code{cond}
4343 expression is that of the @var{default} expression.
4346 @var{test} expressions can have one of the following forms:
4349 @cindex @code{const_int} and attribute tests
4350 @item (const_int @var{i})
4351 This test is true if @var{i} is non-zero and false otherwise.
4353 @cindex @code{not} and attributes
4354 @cindex @code{ior} and attributes
4355 @cindex @code{and} and attributes
4356 @item (not @var{test})
4357 @itemx (ior @var{test1} @var{test2})
4358 @itemx (and @var{test1} @var{test2})
4359 These tests are true if the indicated logical function is true.
4361 @cindex @code{match_operand} and attributes
4362 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
4363 This test is true if operand @var{n} of the insn whose attribute value
4364 is being determined has mode @var{m} (this part of the test is ignored
4365 if @var{m} is @code{VOIDmode}) and the function specified by the string
4366 @var{pred} returns a non-zero value when passed operand @var{n} and mode
4367 @var{m} (this part of the test is ignored if @var{pred} is the null
4370 The @var{constraints} operand is ignored and should be the null string.
4372 @cindex @code{le} and attributes
4373 @cindex @code{leu} and attributes
4374 @cindex @code{lt} and attributes
4375 @cindex @code{gt} and attributes
4376 @cindex @code{gtu} and attributes
4377 @cindex @code{ge} and attributes
4378 @cindex @code{geu} and attributes
4379 @cindex @code{ne} and attributes
4380 @cindex @code{eq} and attributes
4381 @cindex @code{plus} and attributes
4382 @cindex @code{minus} and attributes
4383 @cindex @code{mult} and attributes
4384 @cindex @code{div} and attributes
4385 @cindex @code{mod} and attributes
4386 @cindex @code{abs} and attributes
4387 @cindex @code{neg} and attributes
4388 @cindex @code{ashift} and attributes
4389 @cindex @code{lshiftrt} and attributes
4390 @cindex @code{ashiftrt} and attributes
4391 @item (le @var{arith1} @var{arith2})
4392 @itemx (leu @var{arith1} @var{arith2})
4393 @itemx (lt @var{arith1} @var{arith2})
4394 @itemx (ltu @var{arith1} @var{arith2})
4395 @itemx (gt @var{arith1} @var{arith2})
4396 @itemx (gtu @var{arith1} @var{arith2})
4397 @itemx (ge @var{arith1} @var{arith2})
4398 @itemx (geu @var{arith1} @var{arith2})
4399 @itemx (ne @var{arith1} @var{arith2})
4400 @itemx (eq @var{arith1} @var{arith2})
4401 These tests are true if the indicated comparison of the two arithmetic
4402 expressions is true. Arithmetic expressions are formed with
4403 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
4404 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
4405 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
4408 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
4409 Lengths},for additional forms). @code{symbol_ref} is a string
4410 denoting a C expression that yields an @code{int} when evaluated by the
4411 @samp{get_attr_@dots{}} routine. It should normally be a global
4415 @item (eq_attr @var{name} @var{value})
4416 @var{name} is a string specifying the name of an attribute.
4418 @var{value} is a string that is either a valid value for attribute
4419 @var{name}, a comma-separated list of values, or @samp{!} followed by a
4420 value or list. If @var{value} does not begin with a @samp{!}, this
4421 test is true if the value of the @var{name} attribute of the current
4422 insn is in the list specified by @var{value}. If @var{value} begins
4423 with a @samp{!}, this test is true if the attribute's value is
4424 @emph{not} in the specified list.
4429 (eq_attr "type" "load,store")
4436 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
4439 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
4440 value of the compiler variable @code{which_alternative}
4441 (@pxref{Output Statement}) and the values must be small integers. For
4445 (eq_attr "alternative" "2,3")
4452 (ior (eq (symbol_ref "which_alternative") (const_int 2))
4453 (eq (symbol_ref "which_alternative") (const_int 3)))
4456 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
4457 where the value of the attribute being tested is known for all insns matching
4458 a particular pattern. This is by far the most common case.
4461 @item (attr_flag @var{name})
4462 The value of an @code{attr_flag} expression is true if the flag
4463 specified by @var{name} is true for the @code{insn} currently being
4466 @var{name} is a string specifying one of a fixed set of flags to test.
4467 Test the flags @code{forward} and @code{backward} to determine the
4468 direction of a conditional branch. Test the flags @code{very_likely},
4469 @code{likely}, @code{very_unlikely}, and @code{unlikely} to determine
4470 if a conditional branch is expected to be taken.
4472 If the @code{very_likely} flag is true, then the @code{likely} flag is also
4473 true. Likewise for the @code{very_unlikely} and @code{unlikely} flags.
4475 This example describes a conditional branch delay slot which
4476 can be nullified for forward branches that are taken (annul-true) or
4477 for backward branches which are not taken (annul-false).
4480 (define_delay (eq_attr "type" "cbranch")
4481 [(eq_attr "in_branch_delay" "true")
4482 (and (eq_attr "in_branch_delay" "true")
4483 (attr_flag "forward"))
4484 (and (eq_attr "in_branch_delay" "true")
4485 (attr_flag "backward"))])
4488 The @code{forward} and @code{backward} flags are false if the current
4489 @code{insn} being scheduled is not a conditional branch.
4491 The @code{very_likely} and @code{likely} flags are true if the
4492 @code{insn} being scheduled is not a conditional branch.
4493 The @code{very_unlikely} and @code{unlikely} flags are false if the
4494 @code{insn} being scheduled is not a conditional branch.
4496 @code{attr_flag} is only used during delay slot scheduling and has no
4497 meaning to other passes of the compiler.
4500 @item (attr @var{name})
4501 The value of another attribute is returned. This is most useful
4502 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
4503 produce more efficient code for non-numeric attributes.
4507 @subsection Assigning Attribute Values to Insns
4508 @cindex tagging insns
4509 @cindex assigning attribute values to insns
4511 The value assigned to an attribute of an insn is primarily determined by
4512 which pattern is matched by that insn (or which @code{define_peephole}
4513 generated it). Every @code{define_insn} and @code{define_peephole} can
4514 have an optional last argument to specify the values of attributes for
4515 matching insns. The value of any attribute not specified in a particular
4516 insn is set to the default value for that attribute, as specified in its
4517 @code{define_attr}. Extensive use of default values for attributes
4518 permits the specification of the values for only one or two attributes
4519 in the definition of most insn patterns, as seen in the example in the
4522 The optional last argument of @code{define_insn} and
4523 @code{define_peephole} is a vector of expressions, each of which defines
4524 the value for a single attribute. The most general way of assigning an
4525 attribute's value is to use a @code{set} expression whose first operand is an
4526 @code{attr} expression giving the name of the attribute being set. The
4527 second operand of the @code{set} is an attribute expression
4528 (@pxref{Expressions}) giving the value of the attribute.
4530 When the attribute value depends on the @samp{alternative} attribute
4531 (i.e., which is the applicable alternative in the constraint of the
4532 insn), the @code{set_attr_alternative} expression can be used. It
4533 allows the specification of a vector of attribute expressions, one for
4537 When the generality of arbitrary attribute expressions is not required,
4538 the simpler @code{set_attr} expression can be used, which allows
4539 specifying a string giving either a single attribute value or a list
4540 of attribute values, one for each alternative.
4542 The form of each of the above specifications is shown below. In each case,
4543 @var{name} is a string specifying the attribute to be set.
4546 @item (set_attr @var{name} @var{value-string})
4547 @var{value-string} is either a string giving the desired attribute value,
4548 or a string containing a comma-separated list giving the values for
4549 succeeding alternatives. The number of elements must match the number
4550 of alternatives in the constraint of the insn pattern.
4552 Note that it may be useful to specify @samp{*} for some alternative, in
4553 which case the attribute will assume its default value for insns matching
4556 @findex set_attr_alternative
4557 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
4558 Depending on the alternative of the insn, the value will be one of the
4559 specified values. This is a shorthand for using a @code{cond} with
4560 tests on the @samp{alternative} attribute.
4563 @item (set (attr @var{name}) @var{value})
4564 The first operand of this @code{set} must be the special RTL expression
4565 @code{attr}, whose sole operand is a string giving the name of the
4566 attribute being set. @var{value} is the value of the attribute.
4569 The following shows three different ways of representing the same
4570 attribute value specification:
4573 (set_attr "type" "load,store,arith")
4575 (set_attr_alternative "type"
4576 [(const_string "load") (const_string "store")
4577 (const_string "arith")])
4580 (cond [(eq_attr "alternative" "1") (const_string "load")
4581 (eq_attr "alternative" "2") (const_string "store")]
4582 (const_string "arith")))
4586 @findex define_asm_attributes
4587 The @code{define_asm_attributes} expression provides a mechanism to
4588 specify the attributes assigned to insns produced from an @code{asm}
4589 statement. It has the form:
4592 (define_asm_attributes [@var{attr-sets}])
4596 where @var{attr-sets} is specified the same as for both the
4597 @code{define_insn} and the @code{define_peephole} expressions.
4599 These values will typically be the ``worst case'' attribute values. For
4600 example, they might indicate that the condition code will be clobbered.
4602 A specification for a @code{length} attribute is handled specially. The
4603 way to compute the length of an @code{asm} insn is to multiply the
4604 length specified in the expression @code{define_asm_attributes} by the
4605 number of machine instructions specified in the @code{asm} statement,
4606 determined by counting the number of semicolons and newlines in the
4607 string. Therefore, the value of the @code{length} attribute specified
4608 in a @code{define_asm_attributes} should be the maximum possible length
4609 of a single machine instruction.
4612 @subsection Example of Attribute Specifications
4613 @cindex attribute specifications example
4614 @cindex attribute specifications
4616 The judicious use of defaulting is important in the efficient use of
4617 insn attributes. Typically, insns are divided into @dfn{types} and an
4618 attribute, customarily called @code{type}, is used to represent this
4619 value. This attribute is normally used only to define the default value
4620 for other attributes. An example will clarify this usage.
4622 Assume we have a RISC machine with a condition code and in which only
4623 full-word operations are performed in registers. Let us assume that we
4624 can divide all insns into loads, stores, (integer) arithmetic
4625 operations, floating point operations, and branches.
4627 Here we will concern ourselves with determining the effect of an insn on
4628 the condition code and will limit ourselves to the following possible
4629 effects: The condition code can be set unpredictably (clobbered), not
4630 be changed, be set to agree with the results of the operation, or only
4631 changed if the item previously set into the condition code has been
4634 Here is part of a sample @file{md} file for such a machine:
4637 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
4639 (define_attr "cc" "clobber,unchanged,set,change0"
4640 (cond [(eq_attr "type" "load")
4641 (const_string "change0")
4642 (eq_attr "type" "store,branch")
4643 (const_string "unchanged")
4644 (eq_attr "type" "arith")
4645 (if_then_else (match_operand:SI 0 "" "")
4646 (const_string "set")
4647 (const_string "clobber"))]
4648 (const_string "clobber")))
4651 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
4652 (match_operand:SI 1 "general_operand" "r,m,r"))]
4658 [(set_attr "type" "arith,load,store")])
4661 Note that we assume in the above example that arithmetic operations
4662 performed on quantities smaller than a machine word clobber the condition
4663 code since they will set the condition code to a value corresponding to the
4667 @subsection Computing the Length of an Insn
4668 @cindex insn lengths, computing
4669 @cindex computing the length of an insn
4671 For many machines, multiple types of branch instructions are provided, each
4672 for different length branch displacements. In most cases, the assembler
4673 will choose the correct instruction to use. However, when the assembler
4674 cannot do so, GCC can when a special attribute, the @samp{length}
4675 attribute, is defined. This attribute must be defined to have numeric
4676 values by specifying a null string in its @code{define_attr}.
4678 In the case of the @samp{length} attribute, two additional forms of
4679 arithmetic terms are allowed in test expressions:
4682 @cindex @code{match_dup} and attributes
4683 @item (match_dup @var{n})
4684 This refers to the address of operand @var{n} of the current insn, which
4685 must be a @code{label_ref}.
4687 @cindex @code{pc} and attributes
4689 This refers to the address of the @emph{current} insn. It might have
4690 been more consistent with other usage to make this the address of the
4691 @emph{next} insn but this would be confusing because the length of the
4692 current insn is to be computed.
4695 @cindex @code{addr_vec}, length of
4696 @cindex @code{addr_diff_vec}, length of
4697 For normal insns, the length will be determined by value of the
4698 @samp{length} attribute. In the case of @code{addr_vec} and
4699 @code{addr_diff_vec} insn patterns, the length is computed as
4700 the number of vectors multiplied by the size of each vector.
4702 Lengths are measured in addressable storage units (bytes).
4704 The following macros can be used to refine the length computation:
4707 @findex FIRST_INSN_ADDRESS
4708 @item FIRST_INSN_ADDRESS
4709 When the @code{length} insn attribute is used, this macro specifies the
4710 value to be assigned to the address of the first insn in a function. If
4711 not specified, 0 is used.
4713 @findex ADJUST_INSN_LENGTH
4714 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
4715 If defined, modifies the length assigned to instruction @var{insn} as a
4716 function of the context in which it is used. @var{length} is an lvalue
4717 that contains the initially computed length of the insn and should be
4718 updated with the correct length of the insn.
4720 This macro will normally not be required. A case in which it is
4721 required is the ROMP@. On this machine, the size of an @code{addr_vec}
4722 insn must be increased by two to compensate for the fact that alignment
4726 @findex get_attr_length
4727 The routine that returns @code{get_attr_length} (the value of the
4728 @code{length} attribute) can be used by the output routine to
4729 determine the form of the branch instruction to be written, as the
4730 example below illustrates.
4732 As an example of the specification of variable-length branches, consider
4733 the IBM 360. If we adopt the convention that a register will be set to
4734 the starting address of a function, we can jump to labels within 4k of
4735 the start using a four-byte instruction. Otherwise, we need a six-byte
4736 sequence to load the address from memory and then branch to it.
4738 On such a machine, a pattern for a branch instruction might be specified
4744 (label_ref (match_operand 0 "" "")))]
4747 return (get_attr_length (insn) == 4
4748 ? "b %l0" : "l r15,=a(%l0); br r15");
4750 [(set (attr "length")
4751 (if_then_else (lt (match_dup 0) (const_int 4096))
4756 @node Constant Attributes
4757 @subsection Constant Attributes
4758 @cindex constant attributes
4760 A special form of @code{define_attr}, where the expression for the
4761 default value is a @code{const} expression, indicates an attribute that
4762 is constant for a given run of the compiler. Constant attributes may be
4763 used to specify which variety of processor is used. For example,
4766 (define_attr "cpu" "m88100,m88110,m88000"
4768 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
4769 (symbol_ref "TARGET_88110") (const_string "m88110")]
4770 (const_string "m88000"))))
4772 (define_attr "memory" "fast,slow"
4774 (if_then_else (symbol_ref "TARGET_FAST_MEM")
4775 (const_string "fast")
4776 (const_string "slow"))))
4779 The routine generated for constant attributes has no parameters as it
4780 does not depend on any particular insn. RTL expressions used to define
4781 the value of a constant attribute may use the @code{symbol_ref} form,
4782 but may not use either the @code{match_operand} form or @code{eq_attr}
4783 forms involving insn attributes.
4786 @subsection Delay Slot Scheduling
4787 @cindex delay slots, defining
4789 The insn attribute mechanism can be used to specify the requirements for
4790 delay slots, if any, on a target machine. An instruction is said to
4791 require a @dfn{delay slot} if some instructions that are physically
4792 after the instruction are executed as if they were located before it.
4793 Classic examples are branch and call instructions, which often execute
4794 the following instruction before the branch or call is performed.
4796 On some machines, conditional branch instructions can optionally
4797 @dfn{annul} instructions in the delay slot. This means that the
4798 instruction will not be executed for certain branch outcomes. Both
4799 instructions that annul if the branch is true and instructions that
4800 annul if the branch is false are supported.
4802 Delay slot scheduling differs from instruction scheduling in that
4803 determining whether an instruction needs a delay slot is dependent only
4804 on the type of instruction being generated, not on data flow between the
4805 instructions. See the next section for a discussion of data-dependent
4806 instruction scheduling.
4808 @findex define_delay
4809 The requirement of an insn needing one or more delay slots is indicated
4810 via the @code{define_delay} expression. It has the following form:
4813 (define_delay @var{test}
4814 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
4815 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
4819 @var{test} is an attribute test that indicates whether this
4820 @code{define_delay} applies to a particular insn. If so, the number of
4821 required delay slots is determined by the length of the vector specified
4822 as the second argument. An insn placed in delay slot @var{n} must
4823 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
4824 attribute test that specifies which insns may be annulled if the branch
4825 is true. Similarly, @var{annul-false-n} specifies which insns in the
4826 delay slot may be annulled if the branch is false. If annulling is not
4827 supported for that delay slot, @code{(nil)} should be coded.
4829 For example, in the common case where branch and call insns require
4830 a single delay slot, which may contain any insn other than a branch or
4831 call, the following would be placed in the @file{md} file:
4834 (define_delay (eq_attr "type" "branch,call")
4835 [(eq_attr "type" "!branch,call") (nil) (nil)])
4838 Multiple @code{define_delay} expressions may be specified. In this
4839 case, each such expression specifies different delay slot requirements
4840 and there must be no insn for which tests in two @code{define_delay}
4841 expressions are both true.
4843 For example, if we have a machine that requires one delay slot for branches
4844 but two for calls, no delay slot can contain a branch or call insn,
4845 and any valid insn in the delay slot for the branch can be annulled if the
4846 branch is true, we might represent this as follows:
4849 (define_delay (eq_attr "type" "branch")
4850 [(eq_attr "type" "!branch,call")
4851 (eq_attr "type" "!branch,call")
4854 (define_delay (eq_attr "type" "call")
4855 [(eq_attr "type" "!branch,call") (nil) (nil)
4856 (eq_attr "type" "!branch,call") (nil) (nil)])
4858 @c the above is *still* too long. --mew 4feb93
4860 @node Function Units
4861 @subsection Specifying Function Units
4862 @cindex function units, for scheduling
4864 On most RISC machines, there are instructions whose results are not
4865 available for a specific number of cycles. Common cases are instructions
4866 that load data from memory. On many machines, a pipeline stall will result
4867 if the data is referenced too soon after the load instruction.
4869 In addition, many newer microprocessors have multiple function units, usually
4870 one for integer and one for floating point, and often will incur pipeline
4871 stalls when a result that is needed is not yet ready.
4873 The descriptions in this section allow the specification of how much
4874 time must elapse between the execution of an instruction and the time
4875 when its result is used. It also allows specification of when the
4876 execution of an instruction will delay execution of similar instructions
4877 due to function unit conflicts.
4879 For the purposes of the specifications in this section, a machine is
4880 divided into @dfn{function units}, each of which execute a specific
4881 class of instructions in first-in-first-out order. Function units that
4882 accept one instruction each cycle and allow a result to be used in the
4883 succeeding instruction (usually via forwarding) need not be specified.
4884 Classic RISC microprocessors will normally have a single function unit,
4885 which we can call @samp{memory}. The newer ``superscalar'' processors
4886 will often have function units for floating point operations, usually at
4887 least a floating point adder and multiplier.
4889 @findex define_function_unit
4890 Each usage of a function units by a class of insns is specified with a
4891 @code{define_function_unit} expression, which looks like this:
4894 (define_function_unit @var{name} @var{multiplicity} @var{simultaneity}
4895 @var{test} @var{ready-delay} @var{issue-delay}
4896 [@var{conflict-list}])
4899 @var{name} is a string giving the name of the function unit.
4901 @var{multiplicity} is an integer specifying the number of identical
4902 units in the processor. If more than one unit is specified, they will
4903 be scheduled independently. Only truly independent units should be
4904 counted; a pipelined unit should be specified as a single unit. (The
4905 only common example of a machine that has multiple function units for a
4906 single instruction class that are truly independent and not pipelined
4907 are the two multiply and two increment units of the CDC 6600.)
4909 @var{simultaneity} specifies the maximum number of insns that can be
4910 executing in each instance of the function unit simultaneously or zero
4911 if the unit is pipelined and has no limit.
4913 All @code{define_function_unit} definitions referring to function unit
4914 @var{name} must have the same name and values for @var{multiplicity} and
4917 @var{test} is an attribute test that selects the insns we are describing
4918 in this definition. Note that an insn may use more than one function
4919 unit and a function unit may be specified in more than one
4920 @code{define_function_unit}.
4922 @var{ready-delay} is an integer that specifies the number of cycles
4923 after which the result of the instruction can be used without
4924 introducing any stalls.
4926 @var{issue-delay} is an integer that specifies the number of cycles
4927 after the instruction matching the @var{test} expression begins using
4928 this unit until a subsequent instruction can begin. A cost of @var{N}
4929 indicates an @var{N-1} cycle delay. A subsequent instruction may also
4930 be delayed if an earlier instruction has a longer @var{ready-delay}
4931 value. This blocking effect is computed using the @var{simultaneity},
4932 @var{ready-delay}, @var{issue-delay}, and @var{conflict-list} terms.
4933 For a normal non-pipelined function unit, @var{simultaneity} is one, the
4934 unit is taken to block for the @var{ready-delay} cycles of the executing
4935 insn, and smaller values of @var{issue-delay} are ignored.
4937 @var{conflict-list} is an optional list giving detailed conflict costs
4938 for this unit. If specified, it is a list of condition test expressions
4939 to be applied to insns chosen to execute in @var{name} following the
4940 particular insn matching @var{test} that is already executing in
4941 @var{name}. For each insn in the list, @var{issue-delay} specifies the
4942 conflict cost; for insns not in the list, the cost is zero. If not
4943 specified, @var{conflict-list} defaults to all instructions that use the
4946 Typical uses of this vector are where a floating point function unit can
4947 pipeline either single- or double-precision operations, but not both, or
4948 where a memory unit can pipeline loads, but not stores, etc.
4950 As an example, consider a classic RISC machine where the result of a
4951 load instruction is not available for two cycles (a single ``delay''
4952 instruction is required) and where only one load instruction can be executed
4953 simultaneously. This would be specified as:
4956 (define_function_unit "memory" 1 1 (eq_attr "type" "load") 2 0)
4959 For the case of a floating point function unit that can pipeline either
4960 single or double precision, but not both, the following could be specified:
4963 (define_function_unit
4964 "fp" 1 0 (eq_attr "type" "sp_fp") 4 4 [(eq_attr "type" "dp_fp")])
4965 (define_function_unit
4966 "fp" 1 0 (eq_attr "type" "dp_fp") 4 4 [(eq_attr "type" "sp_fp")])
4969 @strong{Note:} The scheduler attempts to avoid function unit conflicts
4970 and uses all the specifications in the @code{define_function_unit}
4971 expression. It has recently come to our attention that these
4972 specifications may not allow modeling of some of the newer
4973 ``superscalar'' processors that have insns using multiple pipelined
4974 units. These insns will cause a potential conflict for the second unit
4975 used during their execution and there is no way of representing that
4976 conflict. We welcome any examples of how function unit conflicts work
4977 in such processors and suggestions for their representation.
4980 @node Conditional Execution
4981 @section Conditional Execution
4982 @cindex conditional execution
4985 A number of architectures provide for some form of conditional
4986 execution, or predication. The hallmark of this feature is the
4987 ability to nullify most of the instructions in the instruction set.
4988 When the instruction set is large and not entirely symmetric, it
4989 can be quite tedious to describe these forms directly in the
4990 @file{.md} file. An alternative is the @code{define_cond_exec} template.
4992 @findex define_cond_exec
4995 [@var{predicate-pattern}]
4997 "@var{output-template}")
5000 @var{predicate-pattern} is the condition that must be true for the
5001 insn to be executed at runtime and should match a relational operator.
5002 One can use @code{match_operator} to match several relational operators
5003 at once. Any @code{match_operand} operands must have no more than one
5006 @var{condition} is a C expression that must be true for the generated
5009 @findex current_insn_predicate
5010 @var{output-template} is a string similar to the @code{define_insn}
5011 output template (@pxref{Output Template}), except that the @samp{*}
5012 and @samp{@@} special cases do not apply. This is only useful if the
5013 assembly text for the predicate is a simple prefix to the main insn.
5014 In order to handle the general case, there is a global variable
5015 @code{current_insn_predicate} that will contain the entire predicate
5016 if the current insn is predicated, and will otherwise be @code{NULL}.
5018 When @code{define_cond_exec} is used, an implicit reference to
5019 the @code{predicable} instruction attribute is made.
5020 @xref{Insn Attributes}. This attribute must be boolean (i.e.@: have
5021 exactly two elements in its @var{list-of-values}). Further, it must
5022 not be used with complex expressions. That is, the default and all
5023 uses in the insns must be a simple constant, not dependent on the
5024 alternative or anything else.
5026 For each @code{define_insn} for which the @code{predicable}
5027 attribute is true, a new @code{define_insn} pattern will be
5028 generated that matches a predicated version of the instruction.
5032 (define_insn "addsi"
5033 [(set (match_operand:SI 0 "register_operand" "r")
5034 (plus:SI (match_operand:SI 1 "register_operand" "r")
5035 (match_operand:SI 2 "register_operand" "r")))]
5040 [(ne (match_operand:CC 0 "register_operand" "c")
5047 generates a new pattern
5052 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
5053 (set (match_operand:SI 0 "register_operand" "r")
5054 (plus:SI (match_operand:SI 1 "register_operand" "r")
5055 (match_operand:SI 2 "register_operand" "r"))))]
5056 "(@var{test2}) && (@var{test1})"
5057 "(%3) add %2,%1,%0")
5060 @node Constant Definitions
5061 @section Constant Definitions
5062 @cindex constant definitions
5063 @findex define_constants
5065 Using literal constants inside instruction patterns reduces legibility and
5066 can be a maintenance problem.
5068 To overcome this problem, you may use the @code{define_constants}
5069 expression. It contains a vector of name-value pairs. From that
5070 point on, wherever any of the names appears in the MD file, it is as
5071 if the corresponding value had been written instead. You may use
5072 @code{define_constants} multiple times; each appearance adds more
5073 constants to the table. It is an error to redefine a constant with
5076 To come back to the a29k load multiple example, instead of
5080 [(match_parallel 0 "load_multiple_operation"
5081 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
5082 (match_operand:SI 2 "memory_operand" "m"))
5084 (clobber (reg:SI 179))])]
5100 [(match_parallel 0 "load_multiple_operation"
5101 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
5102 (match_operand:SI 2 "memory_operand" "m"))
5104 (clobber (reg:SI R_CR))])]
5109 The constants that are defined with a define_constant are also output
5110 in the insn-codes.h header file as #defines.