1 @c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 1999, 2000, 2001,
2 @c 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
3 @c Free Software Foundation, Inc.
4 @c This is part of the GCC manual.
5 @c For copying conditions, see the file gcc.texi.
9 @chapter Machine Descriptions
10 @cindex machine descriptions
12 A machine description has two parts: a file of instruction patterns
13 (@file{.md} file) and a C header file of macro definitions.
15 The @file{.md} file for a target machine contains a pattern for each
16 instruction that the target machine supports (or at least each instruction
17 that is worth telling the compiler about). It may also contain comments.
18 A semicolon causes the rest of the line to be a comment, unless the semicolon
19 is inside a quoted string.
21 See the next chapter for information on the C header file.
24 * Overview:: How the machine description is used.
25 * Patterns:: How to write instruction patterns.
26 * Example:: An explained example of a @code{define_insn} pattern.
27 * RTL Template:: The RTL template defines what insns match a pattern.
28 * Output Template:: The output template says how to make assembler code
30 * Output Statement:: For more generality, write C code to output
32 * Predicates:: Controlling what kinds of operands can be used
34 * Constraints:: Fine-tuning operand selection.
35 * Standard Names:: Names mark patterns to use for code generation.
36 * Pattern Ordering:: When the order of patterns makes a difference.
37 * Dependent Patterns:: Having one pattern may make you need another.
38 * Jump Patterns:: Special considerations for patterns for jump insns.
39 * Looping Patterns:: How to define patterns for special looping insns.
40 * Insn Canonicalizations::Canonicalization of Instructions
41 * Expander Definitions::Generating a sequence of several RTL insns
42 for a standard operation.
43 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
44 * Including Patterns:: Including Patterns in Machine Descriptions.
45 * Peephole Definitions::Defining machine-specific peephole optimizations.
46 * Insn Attributes:: Specifying the value of attributes for generated insns.
47 * Conditional Execution::Generating @code{define_insn} patterns for
49 * Constant Definitions::Defining symbolic constants that can be used in the
51 * Iterators:: Using iterators to generate patterns from a template.
55 @section Overview of How the Machine Description is Used
57 There are three main conversions that happen in the compiler:
62 The front end reads the source code and builds a parse tree.
65 The parse tree is used to generate an RTL insn list based on named
69 The insn list is matched against the RTL templates to produce assembler
74 For the generate pass, only the names of the insns matter, from either a
75 named @code{define_insn} or a @code{define_expand}. The compiler will
76 choose the pattern with the right name and apply the operands according
77 to the documentation later in this chapter, without regard for the RTL
78 template or operand constraints. Note that the names the compiler looks
79 for are hard-coded in the compiler---it will ignore unnamed patterns and
80 patterns with names it doesn't know about, but if you don't provide a
81 named pattern it needs, it will abort.
83 If a @code{define_insn} is used, the template given is inserted into the
84 insn list. If a @code{define_expand} is used, one of three things
85 happens, based on the condition logic. The condition logic may manually
86 create new insns for the insn list, say via @code{emit_insn()}, and
87 invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
88 compiler to use an alternate way of performing that task. If it invokes
89 neither @code{DONE} nor @code{FAIL}, the template given in the pattern
90 is inserted, as if the @code{define_expand} were a @code{define_insn}.
92 Once the insn list is generated, various optimization passes convert,
93 replace, and rearrange the insns in the insn list. This is where the
94 @code{define_split} and @code{define_peephole} patterns get used, for
97 Finally, the insn list's RTL is matched up with the RTL templates in the
98 @code{define_insn} patterns, and those patterns are used to emit the
99 final assembly code. For this purpose, each named @code{define_insn}
100 acts like it's unnamed, since the names are ignored.
103 @section Everything about Instruction Patterns
105 @cindex instruction patterns
108 Each instruction pattern contains an incomplete RTL expression, with pieces
109 to be filled in later, operand constraints that restrict how the pieces can
110 be filled in, and an output pattern or C code to generate the assembler
111 output, all wrapped up in a @code{define_insn} expression.
113 A @code{define_insn} is an RTL expression containing four or five operands:
117 An optional name. The presence of a name indicate that this instruction
118 pattern can perform a certain standard job for the RTL-generation
119 pass of the compiler. This pass knows certain names and will use
120 the instruction patterns with those names, if the names are defined
121 in the machine description.
123 The absence of a name is indicated by writing an empty string
124 where the name should go. Nameless instruction patterns are never
125 used for generating RTL code, but they may permit several simpler insns
126 to be combined later on.
128 Names that are not thus known and used in RTL-generation have no
129 effect; they are equivalent to no name at all.
131 For the purpose of debugging the compiler, you may also specify a
132 name beginning with the @samp{*} character. Such a name is used only
133 for identifying the instruction in RTL dumps; it is entirely equivalent
134 to having a nameless pattern for all other purposes.
137 The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete
138 RTL expressions which show what the instruction should look like. It is
139 incomplete because it may contain @code{match_operand},
140 @code{match_operator}, and @code{match_dup} expressions that stand for
141 operands of the instruction.
143 If the vector has only one element, that element is the template for the
144 instruction pattern. If the vector has multiple elements, then the
145 instruction pattern is a @code{parallel} expression containing the
149 @cindex pattern conditions
150 @cindex conditions, in patterns
151 A condition. This is a string which contains a C expression that is
152 the final test to decide whether an insn body matches this pattern.
154 @cindex named patterns and conditions
155 For a named pattern, the condition (if present) may not depend on
156 the data in the insn being matched, but only the target-machine-type
157 flags. The compiler needs to test these conditions during
158 initialization in order to learn exactly which named instructions are
159 available in a particular run.
162 For nameless patterns, the condition is applied only when matching an
163 individual insn, and only after the insn has matched the pattern's
164 recognition template. The insn's operands may be found in the vector
165 @code{operands}. For an insn where the condition has once matched, it
166 can't be used to control register allocation, for example by excluding
167 certain hard registers or hard register combinations.
170 The @dfn{output template}: a string that says how to output matching
171 insns as assembler code. @samp{%} in this string specifies where
172 to substitute the value of an operand. @xref{Output Template}.
174 When simple substitution isn't general enough, you can specify a piece
175 of C code to compute the output. @xref{Output Statement}.
178 Optionally, a vector containing the values of attributes for insns matching
179 this pattern. @xref{Insn Attributes}.
183 @section Example of @code{define_insn}
184 @cindex @code{define_insn} example
186 Here is an actual example of an instruction pattern, for the 68000/68020.
191 (match_operand:SI 0 "general_operand" "rm"))]
195 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
197 return \"cmpl #0,%0\";
202 This can also be written using braced strings:
207 (match_operand:SI 0 "general_operand" "rm"))]
210 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
216 This is an instruction that sets the condition codes based on the value of
217 a general operand. It has no condition, so any insn whose RTL description
218 has the form shown may be handled according to this pattern. The name
219 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation
220 pass that, when it is necessary to test such a value, an insn to do so
221 can be constructed using this pattern.
223 The output control string is a piece of C code which chooses which
224 output template to return based on the kind of operand and the specific
225 type of CPU for which code is being generated.
227 @samp{"rm"} is an operand constraint. Its meaning is explained below.
230 @section RTL Template
231 @cindex RTL insn template
232 @cindex generating insns
233 @cindex insns, generating
234 @cindex recognizing insns
235 @cindex insns, recognizing
237 The RTL template is used to define which insns match the particular pattern
238 and how to find their operands. For named patterns, the RTL template also
239 says how to construct an insn from specified operands.
241 Construction involves substituting specified operands into a copy of the
242 template. Matching involves determining the values that serve as the
243 operands in the insn being matched. Both of these activities are
244 controlled by special expression types that direct matching and
245 substitution of the operands.
248 @findex match_operand
249 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
250 This expression is a placeholder for operand number @var{n} of
251 the insn. When constructing an insn, operand number @var{n}
252 will be substituted at this point. When matching an insn, whatever
253 appears at this position in the insn will be taken as operand
254 number @var{n}; but it must satisfy @var{predicate} or this instruction
255 pattern will not match at all.
257 Operand numbers must be chosen consecutively counting from zero in
258 each instruction pattern. There may be only one @code{match_operand}
259 expression in the pattern for each operand number. Usually operands
260 are numbered in the order of appearance in @code{match_operand}
261 expressions. In the case of a @code{define_expand}, any operand numbers
262 used only in @code{match_dup} expressions have higher values than all
263 other operand numbers.
265 @var{predicate} is a string that is the name of a function that
266 accepts two arguments, an expression and a machine mode.
267 @xref{Predicates}. During matching, the function will be called with
268 the putative operand as the expression and @var{m} as the mode
269 argument (if @var{m} is not specified, @code{VOIDmode} will be used,
270 which normally causes @var{predicate} to accept any mode). If it
271 returns zero, this instruction pattern fails to match.
272 @var{predicate} may be an empty string; then it means no test is to be
273 done on the operand, so anything which occurs in this position is
276 Most of the time, @var{predicate} will reject modes other than @var{m}---but
277 not always. For example, the predicate @code{address_operand} uses
278 @var{m} as the mode of memory ref that the address should be valid for.
279 Many predicates accept @code{const_int} nodes even though their mode is
282 @var{constraint} controls reloading and the choice of the best register
283 class to use for a value, as explained later (@pxref{Constraints}).
284 If the constraint would be an empty string, it can be omitted.
286 People are often unclear on the difference between the constraint and the
287 predicate. The predicate helps decide whether a given insn matches the
288 pattern. The constraint plays no role in this decision; instead, it
289 controls various decisions in the case of an insn which does match.
291 @findex match_scratch
292 @item (match_scratch:@var{m} @var{n} @var{constraint})
293 This expression is also a placeholder for operand number @var{n}
294 and indicates that operand must be a @code{scratch} or @code{reg}
297 When matching patterns, this is equivalent to
300 (match_operand:@var{m} @var{n} "scratch_operand" @var{pred})
303 but, when generating RTL, it produces a (@code{scratch}:@var{m})
306 If the last few expressions in a @code{parallel} are @code{clobber}
307 expressions whose operands are either a hard register or
308 @code{match_scratch}, the combiner can add or delete them when
309 necessary. @xref{Side Effects}.
312 @item (match_dup @var{n})
313 This expression is also a placeholder for operand number @var{n}.
314 It is used when the operand needs to appear more than once in the
317 In construction, @code{match_dup} acts just like @code{match_operand}:
318 the operand is substituted into the insn being constructed. But in
319 matching, @code{match_dup} behaves differently. It assumes that operand
320 number @var{n} has already been determined by a @code{match_operand}
321 appearing earlier in the recognition template, and it matches only an
322 identical-looking expression.
324 Note that @code{match_dup} should not be used to tell the compiler that
325 a particular register is being used for two operands (example:
326 @code{add} that adds one register to another; the second register is
327 both an input operand and the output operand). Use a matching
328 constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
329 operand is used in two places in the template, such as an instruction
330 that computes both a quotient and a remainder, where the opcode takes
331 two input operands but the RTL template has to refer to each of those
332 twice; once for the quotient pattern and once for the remainder pattern.
334 @findex match_operator
335 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
336 This pattern is a kind of placeholder for a variable RTL expression
339 When constructing an insn, it stands for an RTL expression whose
340 expression code is taken from that of operand @var{n}, and whose
341 operands are constructed from the patterns @var{operands}.
343 When matching an expression, it matches an expression if the function
344 @var{predicate} returns nonzero on that expression @emph{and} the
345 patterns @var{operands} match the operands of the expression.
347 Suppose that the function @code{commutative_operator} is defined as
348 follows, to match any expression whose operator is one of the
349 commutative arithmetic operators of RTL and whose mode is @var{mode}:
353 commutative_integer_operator (x, mode)
355 enum machine_mode mode;
357 enum rtx_code code = GET_CODE (x);
358 if (GET_MODE (x) != mode)
360 return (GET_RTX_CLASS (code) == RTX_COMM_ARITH
361 || code == EQ || code == NE);
365 Then the following pattern will match any RTL expression consisting
366 of a commutative operator applied to two general operands:
369 (match_operator:SI 3 "commutative_operator"
370 [(match_operand:SI 1 "general_operand" "g")
371 (match_operand:SI 2 "general_operand" "g")])
374 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
375 because the expressions to be matched all contain two operands.
377 When this pattern does match, the two operands of the commutative
378 operator are recorded as operands 1 and 2 of the insn. (This is done
379 by the two instances of @code{match_operand}.) Operand 3 of the insn
380 will be the entire commutative expression: use @code{GET_CODE
381 (operands[3])} to see which commutative operator was used.
383 The machine mode @var{m} of @code{match_operator} works like that of
384 @code{match_operand}: it is passed as the second argument to the
385 predicate function, and that function is solely responsible for
386 deciding whether the expression to be matched ``has'' that mode.
388 When constructing an insn, argument 3 of the gen-function will specify
389 the operation (i.e.@: the expression code) for the expression to be
390 made. It should be an RTL expression, whose expression code is copied
391 into a new expression whose operands are arguments 1 and 2 of the
392 gen-function. The subexpressions of argument 3 are not used;
393 only its expression code matters.
395 When @code{match_operator} is used in a pattern for matching an insn,
396 it usually best if the operand number of the @code{match_operator}
397 is higher than that of the actual operands of the insn. This improves
398 register allocation because the register allocator often looks at
399 operands 1 and 2 of insns to see if it can do register tying.
401 There is no way to specify constraints in @code{match_operator}. The
402 operand of the insn which corresponds to the @code{match_operator}
403 never has any constraints because it is never reloaded as a whole.
404 However, if parts of its @var{operands} are matched by
405 @code{match_operand} patterns, those parts may have constraints of
409 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
410 Like @code{match_dup}, except that it applies to operators instead of
411 operands. When constructing an insn, operand number @var{n} will be
412 substituted at this point. But in matching, @code{match_op_dup} behaves
413 differently. It assumes that operand number @var{n} has already been
414 determined by a @code{match_operator} appearing earlier in the
415 recognition template, and it matches only an identical-looking
418 @findex match_parallel
419 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
420 This pattern is a placeholder for an insn that consists of a
421 @code{parallel} expression with a variable number of elements. This
422 expression should only appear at the top level of an insn pattern.
424 When constructing an insn, operand number @var{n} will be substituted at
425 this point. When matching an insn, it matches if the body of the insn
426 is a @code{parallel} expression with at least as many elements as the
427 vector of @var{subpat} expressions in the @code{match_parallel}, if each
428 @var{subpat} matches the corresponding element of the @code{parallel},
429 @emph{and} the function @var{predicate} returns nonzero on the
430 @code{parallel} that is the body of the insn. It is the responsibility
431 of the predicate to validate elements of the @code{parallel} beyond
432 those listed in the @code{match_parallel}.
434 A typical use of @code{match_parallel} is to match load and store
435 multiple expressions, which can contain a variable number of elements
436 in a @code{parallel}. For example,
440 [(match_parallel 0 "load_multiple_operation"
441 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
442 (match_operand:SI 2 "memory_operand" "m"))
444 (clobber (reg:SI 179))])]
449 This example comes from @file{a29k.md}. The function
450 @code{load_multiple_operation} is defined in @file{a29k.c} and checks
451 that subsequent elements in the @code{parallel} are the same as the
452 @code{set} in the pattern, except that they are referencing subsequent
453 registers and memory locations.
455 An insn that matches this pattern might look like:
459 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
461 (clobber (reg:SI 179))
463 (mem:SI (plus:SI (reg:SI 100)
466 (mem:SI (plus:SI (reg:SI 100)
470 @findex match_par_dup
471 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
472 Like @code{match_op_dup}, but for @code{match_parallel} instead of
473 @code{match_operator}.
477 @node Output Template
478 @section Output Templates and Operand Substitution
479 @cindex output templates
480 @cindex operand substitution
482 @cindex @samp{%} in template
484 The @dfn{output template} is a string which specifies how to output the
485 assembler code for an instruction pattern. Most of the template is a
486 fixed string which is output literally. The character @samp{%} is used
487 to specify where to substitute an operand; it can also be used to
488 identify places where different variants of the assembler require
491 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
492 operand @var{n} at that point in the string.
494 @samp{%} followed by a letter and a digit says to output an operand in an
495 alternate fashion. Four letters have standard, built-in meanings described
496 below. The machine description macro @code{PRINT_OPERAND} can define
497 additional letters with nonstandard meanings.
499 @samp{%c@var{digit}} can be used to substitute an operand that is a
500 constant value without the syntax that normally indicates an immediate
503 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
504 the constant is negated before printing.
506 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
507 memory reference, with the actual operand treated as the address. This may
508 be useful when outputting a ``load address'' instruction, because often the
509 assembler syntax for such an instruction requires you to write the operand
510 as if it were a memory reference.
512 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
515 @samp{%=} outputs a number which is unique to each instruction in the
516 entire compilation. This is useful for making local labels to be
517 referred to more than once in a single template that generates multiple
518 assembler instructions.
520 @samp{%} followed by a punctuation character specifies a substitution that
521 does not use an operand. Only one case is standard: @samp{%%} outputs a
522 @samp{%} into the assembler code. Other nonstandard cases can be
523 defined in the @code{PRINT_OPERAND} macro. You must also define
524 which punctuation characters are valid with the
525 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
529 The template may generate multiple assembler instructions. Write the text
530 for the instructions, with @samp{\;} between them.
532 @cindex matching operands
533 When the RTL contains two operands which are required by constraint to match
534 each other, the output template must refer only to the lower-numbered operand.
535 Matching operands are not always identical, and the rest of the compiler
536 arranges to put the proper RTL expression for printing into the lower-numbered
539 One use of nonstandard letters or punctuation following @samp{%} is to
540 distinguish between different assembler languages for the same machine; for
541 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
542 requires periods in most opcode names, while MIT syntax does not. For
543 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
544 syntax. The same file of patterns is used for both kinds of output syntax,
545 but the character sequence @samp{%.} is used in each place where Motorola
546 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
547 defines the sequence to output a period; the macro for MIT syntax defines
550 @cindex @code{#} in template
551 As a special case, a template consisting of the single character @code{#}
552 instructs the compiler to first split the insn, and then output the
553 resulting instructions separately. This helps eliminate redundancy in the
554 output templates. If you have a @code{define_insn} that needs to emit
555 multiple assembler instructions, and there is a matching @code{define_split}
556 already defined, then you can simply use @code{#} as the output template
557 instead of writing an output template that emits the multiple assembler
560 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
561 of the form @samp{@{option0|option1|option2@}} in the templates. These
562 describe multiple variants of assembler language syntax.
563 @xref{Instruction Output}.
565 @node Output Statement
566 @section C Statements for Assembler Output
567 @cindex output statements
568 @cindex C statements for assembler output
569 @cindex generating assembler output
571 Often a single fixed template string cannot produce correct and efficient
572 assembler code for all the cases that are recognized by a single
573 instruction pattern. For example, the opcodes may depend on the kinds of
574 operands; or some unfortunate combinations of operands may require extra
575 machine instructions.
577 If the output control string starts with a @samp{@@}, then it is actually
578 a series of templates, each on a separate line. (Blank lines and
579 leading spaces and tabs are ignored.) The templates correspond to the
580 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
581 if a target machine has a two-address add instruction @samp{addr} to add
582 into a register and another @samp{addm} to add a register to memory, you
583 might write this pattern:
586 (define_insn "addsi3"
587 [(set (match_operand:SI 0 "general_operand" "=r,m")
588 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
589 (match_operand:SI 2 "general_operand" "g,r")))]
596 @cindex @code{*} in template
597 @cindex asterisk in template
598 If the output control string starts with a @samp{*}, then it is not an
599 output template but rather a piece of C program that should compute a
600 template. It should execute a @code{return} statement to return the
601 template-string you want. Most such templates use C string literals, which
602 require doublequote characters to delimit them. To include these
603 doublequote characters in the string, prefix each one with @samp{\}.
605 If the output control string is written as a brace block instead of a
606 double-quoted string, it is automatically assumed to be C code. In that
607 case, it is not necessary to put in a leading asterisk, or to escape the
608 doublequotes surrounding C string literals.
610 The operands may be found in the array @code{operands}, whose C data type
613 It is very common to select different ways of generating assembler code
614 based on whether an immediate operand is within a certain range. Be
615 careful when doing this, because the result of @code{INTVAL} is an
616 integer on the host machine. If the host machine has more bits in an
617 @code{int} than the target machine has in the mode in which the constant
618 will be used, then some of the bits you get from @code{INTVAL} will be
619 superfluous. For proper results, you must carefully disregard the
620 values of those bits.
622 @findex output_asm_insn
623 It is possible to output an assembler instruction and then go on to output
624 or compute more of them, using the subroutine @code{output_asm_insn}. This
625 receives two arguments: a template-string and a vector of operands. The
626 vector may be @code{operands}, or it may be another array of @code{rtx}
627 that you declare locally and initialize yourself.
629 @findex which_alternative
630 When an insn pattern has multiple alternatives in its constraints, often
631 the appearance of the assembler code is determined mostly by which alternative
632 was matched. When this is so, the C code can test the variable
633 @code{which_alternative}, which is the ordinal number of the alternative
634 that was actually satisfied (0 for the first, 1 for the second alternative,
637 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
638 for registers and @samp{clrmem} for memory locations. Here is how
639 a pattern could use @code{which_alternative} to choose between them:
643 [(set (match_operand:SI 0 "general_operand" "=r,m")
647 return (which_alternative == 0
648 ? "clrreg %0" : "clrmem %0");
652 The example above, where the assembler code to generate was
653 @emph{solely} determined by the alternative, could also have been specified
654 as follows, having the output control string start with a @samp{@@}:
659 [(set (match_operand:SI 0 "general_operand" "=r,m")
671 @cindex operand predicates
672 @cindex operator predicates
674 A predicate determines whether a @code{match_operand} or
675 @code{match_operator} expression matches, and therefore whether the
676 surrounding instruction pattern will be used for that combination of
677 operands. GCC has a number of machine-independent predicates, and you
678 can define machine-specific predicates as needed. By convention,
679 predicates used with @code{match_operand} have names that end in
680 @samp{_operand}, and those used with @code{match_operator} have names
681 that end in @samp{_operator}.
683 All predicates are Boolean functions (in the mathematical sense) of
684 two arguments: the RTL expression that is being considered at that
685 position in the instruction pattern, and the machine mode that the
686 @code{match_operand} or @code{match_operator} specifies. In this
687 section, the first argument is called @var{op} and the second argument
688 @var{mode}. Predicates can be called from C as ordinary two-argument
689 functions; this can be useful in output templates or other
690 machine-specific code.
692 Operand predicates can allow operands that are not actually acceptable
693 to the hardware, as long as the constraints give reload the ability to
694 fix them up (@pxref{Constraints}). However, GCC will usually generate
695 better code if the predicates specify the requirements of the machine
696 instructions as closely as possible. Reload cannot fix up operands
697 that must be constants (``immediate operands''); you must use a
698 predicate that allows only constants, or else enforce the requirement
699 in the extra condition.
701 @cindex predicates and machine modes
702 @cindex normal predicates
703 @cindex special predicates
704 Most predicates handle their @var{mode} argument in a uniform manner.
705 If @var{mode} is @code{VOIDmode} (unspecified), then @var{op} can have
706 any mode. If @var{mode} is anything else, then @var{op} must have the
707 same mode, unless @var{op} is a @code{CONST_INT} or integer
708 @code{CONST_DOUBLE}. These RTL expressions always have
709 @code{VOIDmode}, so it would be counterproductive to check that their
710 mode matches. Instead, predicates that accept @code{CONST_INT} and/or
711 integer @code{CONST_DOUBLE} check that the value stored in the
712 constant will fit in the requested mode.
714 Predicates with this behavior are called @dfn{normal}.
715 @command{genrecog} can optimize the instruction recognizer based on
716 knowledge of how normal predicates treat modes. It can also diagnose
717 certain kinds of common errors in the use of normal predicates; for
718 instance, it is almost always an error to use a normal predicate
719 without specifying a mode.
721 Predicates that do something different with their @var{mode} argument
722 are called @dfn{special}. The generic predicates
723 @code{address_operand} and @code{pmode_register_operand} are special
724 predicates. @command{genrecog} does not do any optimizations or
725 diagnosis when special predicates are used.
728 * Machine-Independent Predicates:: Predicates available to all back ends.
729 * Defining Predicates:: How to write machine-specific predicate
733 @node Machine-Independent Predicates
734 @subsection Machine-Independent Predicates
735 @cindex machine-independent predicates
736 @cindex generic predicates
738 These are the generic predicates available to all back ends. They are
739 defined in @file{recog.c}. The first category of predicates allow
740 only constant, or @dfn{immediate}, operands.
742 @defun immediate_operand
743 This predicate allows any sort of constant that fits in @var{mode}.
744 It is an appropriate choice for instructions that take operands that
748 @defun const_int_operand
749 This predicate allows any @code{CONST_INT} expression that fits in
750 @var{mode}. It is an appropriate choice for an immediate operand that
751 does not allow a symbol or label.
754 @defun const_double_operand
755 This predicate accepts any @code{CONST_DOUBLE} expression that has
756 exactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also
757 accept @code{CONST_INT}. It is intended for immediate floating point
762 The second category of predicates allow only some kind of machine
765 @defun register_operand
766 This predicate allows any @code{REG} or @code{SUBREG} expression that
767 is valid for @var{mode}. It is often suitable for arithmetic
768 instruction operands on a RISC machine.
771 @defun pmode_register_operand
772 This is a slight variant on @code{register_operand} which works around
773 a limitation in the machine-description reader.
776 (match_operand @var{n} "pmode_register_operand" @var{constraint})
783 (match_operand:P @var{n} "register_operand" @var{constraint})
787 would mean, if the machine-description reader accepted @samp{:P}
788 mode suffixes. Unfortunately, it cannot, because @code{Pmode} is an
789 alias for some other mode, and might vary with machine-specific
790 options. @xref{Misc}.
793 @defun scratch_operand
794 This predicate allows hard registers and @code{SCRATCH} expressions,
795 but not pseudo-registers. It is used internally by @code{match_scratch};
796 it should not be used directly.
800 The third category of predicates allow only some kind of memory reference.
802 @defun memory_operand
803 This predicate allows any valid reference to a quantity of mode
804 @var{mode} in memory, as determined by the weak form of
805 @code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}).
808 @defun address_operand
809 This predicate is a little unusual; it allows any operand that is a
810 valid expression for the @emph{address} of a quantity of mode
811 @var{mode}, again determined by the weak form of
812 @code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if
813 @samp{@w{(mem:@var{mode} (@var{exp}))}} is acceptable to
814 @code{memory_operand}, then @var{exp} is acceptable to
815 @code{address_operand}. Note that @var{exp} does not necessarily have
819 @defun indirect_operand
820 This is a stricter form of @code{memory_operand} which allows only
821 memory references with a @code{general_operand} as the address
822 expression. New uses of this predicate are discouraged, because
823 @code{general_operand} is very permissive, so it's hard to tell what
824 an @code{indirect_operand} does or does not allow. If a target has
825 different requirements for memory operands for different instructions,
826 it is better to define target-specific predicates which enforce the
827 hardware's requirements explicitly.
831 This predicate allows a memory reference suitable for pushing a value
832 onto the stack. This will be a @code{MEM} which refers to
833 @code{stack_pointer_rtx}, with a side-effect in its address expression
834 (@pxref{Incdec}); which one is determined by the
835 @code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}).
839 This predicate allows a memory reference suitable for popping a value
840 off the stack. Again, this will be a @code{MEM} referring to
841 @code{stack_pointer_rtx}, with a side-effect in its address
842 expression. However, this time @code{STACK_POP_CODE} is expected.
846 The fourth category of predicates allow some combination of the above
849 @defun nonmemory_operand
850 This predicate allows any immediate or register operand valid for @var{mode}.
853 @defun nonimmediate_operand
854 This predicate allows any register or memory operand valid for @var{mode}.
857 @defun general_operand
858 This predicate allows any immediate, register, or memory operand
859 valid for @var{mode}.
863 Finally, there are two generic operator predicates.
865 @defun comparison_operator
866 This predicate matches any expression which performs an arithmetic
867 comparison in @var{mode}; that is, @code{COMPARISON_P} is true for the
871 @defun ordered_comparison_operator
872 This predicate matches any expression which performs an arithmetic
873 comparison in @var{mode} and whose expression code is valid for integer
874 modes; that is, the expression code will be one of @code{eq}, @code{ne},
875 @code{lt}, @code{ltu}, @code{le}, @code{leu}, @code{gt}, @code{gtu},
876 @code{ge}, @code{geu}.
879 @node Defining Predicates
880 @subsection Defining Machine-Specific Predicates
881 @cindex defining predicates
882 @findex define_predicate
883 @findex define_special_predicate
885 Many machines have requirements for their operands that cannot be
886 expressed precisely using the generic predicates. You can define
887 additional predicates using @code{define_predicate} and
888 @code{define_special_predicate} expressions. These expressions have
893 The name of the predicate, as it will be referred to in
894 @code{match_operand} or @code{match_operator} expressions.
897 An RTL expression which evaluates to true if the predicate allows the
898 operand @var{op}, false if it does not. This expression can only use
899 the following RTL codes:
903 When written inside a predicate expression, a @code{MATCH_OPERAND}
904 expression evaluates to true if the predicate it names would allow
905 @var{op}. The operand number and constraint are ignored. Due to
906 limitations in @command{genrecog}, you can only refer to generic
907 predicates and predicates that have already been defined.
910 This expression evaluates to true if @var{op} or a specified
911 subexpression of @var{op} has one of a given list of RTX codes.
913 The first operand of this expression is a string constant containing a
914 comma-separated list of RTX code names (in lower case). These are the
915 codes for which the @code{MATCH_CODE} will be true.
917 The second operand is a string constant which indicates what
918 subexpression of @var{op} to examine. If it is absent or the empty
919 string, @var{op} itself is examined. Otherwise, the string constant
920 must be a sequence of digits and/or lowercase letters. Each character
921 indicates a subexpression to extract from the current expression; for
922 the first character this is @var{op}, for the second and subsequent
923 characters it is the result of the previous character. A digit
924 @var{n} extracts @samp{@w{XEXP (@var{e}, @var{n})}}; a letter @var{l}
925 extracts @samp{@w{XVECEXP (@var{e}, 0, @var{n})}} where @var{n} is the
926 alphabetic ordinal of @var{l} (0 for `a', 1 for 'b', and so on). The
927 @code{MATCH_CODE} then examines the RTX code of the subexpression
928 extracted by the complete string. It is not possible to extract
929 components of an @code{rtvec} that is not at position 0 within its RTX
933 This expression has one operand, a string constant containing a C
934 expression. The predicate's arguments, @var{op} and @var{mode}, are
935 available with those names in the C expression. The @code{MATCH_TEST}
936 evaluates to true if the C expression evaluates to a nonzero value.
937 @code{MATCH_TEST} expressions must not have side effects.
943 The basic @samp{MATCH_} expressions can be combined using these
944 logical operators, which have the semantics of the C operators
945 @samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively. As
946 in Common Lisp, you may give an @code{AND} or @code{IOR} expression an
947 arbitrary number of arguments; this has exactly the same effect as
948 writing a chain of two-argument @code{AND} or @code{IOR} expressions.
952 An optional block of C code, which should execute
953 @samp{@w{return true}} if the predicate is found to match and
954 @samp{@w{return false}} if it does not. It must not have any side
955 effects. The predicate arguments, @var{op} and @var{mode}, are
956 available with those names.
958 If a code block is present in a predicate definition, then the RTL
959 expression must evaluate to true @emph{and} the code block must
960 execute @samp{@w{return true}} for the predicate to allow the operand.
961 The RTL expression is evaluated first; do not re-check anything in the
962 code block that was checked in the RTL expression.
965 The program @command{genrecog} scans @code{define_predicate} and
966 @code{define_special_predicate} expressions to determine which RTX
967 codes are possibly allowed. You should always make this explicit in
968 the RTL predicate expression, using @code{MATCH_OPERAND} and
971 Here is an example of a simple predicate definition, from the IA64
976 ;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.}
977 (define_predicate "small_addr_symbolic_operand"
978 (and (match_code "symbol_ref")
979 (match_test "SYMBOL_REF_SMALL_ADDR_P (op)")))
984 And here is another, showing the use of the C block.
988 ;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.}
989 (define_predicate "gr_register_operand"
990 (match_operand 0 "register_operand")
993 if (GET_CODE (op) == SUBREG)
994 op = SUBREG_REG (op);
997 return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno));
1002 Predicates written with @code{define_predicate} automatically include
1003 a test that @var{mode} is @code{VOIDmode}, or @var{op} has the same
1004 mode as @var{mode}, or @var{op} is a @code{CONST_INT} or
1005 @code{CONST_DOUBLE}. They do @emph{not} check specifically for
1006 integer @code{CONST_DOUBLE}, nor do they test that the value of either
1007 kind of constant fits in the requested mode. This is because
1008 target-specific predicates that take constants usually have to do more
1009 stringent value checks anyway. If you need the exact same treatment
1010 of @code{CONST_INT} or @code{CONST_DOUBLE} that the generic predicates
1011 provide, use a @code{MATCH_OPERAND} subexpression to call
1012 @code{const_int_operand}, @code{const_double_operand}, or
1013 @code{immediate_operand}.
1015 Predicates written with @code{define_special_predicate} do not get any
1016 automatic mode checks, and are treated as having special mode handling
1017 by @command{genrecog}.
1019 The program @command{genpreds} is responsible for generating code to
1020 test predicates. It also writes a header file containing function
1021 declarations for all machine-specific predicates. It is not necessary
1022 to declare these predicates in @file{@var{cpu}-protos.h}.
1025 @c Most of this node appears by itself (in a different place) even
1026 @c when the INTERNALS flag is clear. Passages that require the internals
1027 @c manual's context are conditionalized to appear only in the internals manual.
1030 @section Operand Constraints
1031 @cindex operand constraints
1034 Each @code{match_operand} in an instruction pattern can specify
1035 constraints for the operands allowed. The constraints allow you to
1036 fine-tune matching within the set of operands allowed by the
1042 @section Constraints for @code{asm} Operands
1043 @cindex operand constraints, @code{asm}
1044 @cindex constraints, @code{asm}
1045 @cindex @code{asm} constraints
1047 Here are specific details on what constraint letters you can use with
1048 @code{asm} operands.
1050 Constraints can say whether
1051 an operand may be in a register, and which kinds of register; whether the
1052 operand can be a memory reference, and which kinds of address; whether the
1053 operand may be an immediate constant, and which possible values it may
1054 have. Constraints can also require two operands to match.
1055 Side-effects aren't allowed in operands of inline @code{asm}, unless
1056 @samp{<} or @samp{>} constraints are used, because there is no guarantee
1057 that the side-effects will happen exactly once in an instruction that can update
1058 the addressing register.
1062 * Simple Constraints:: Basic use of constraints.
1063 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1064 * Class Preferences:: Constraints guide which hard register to put things in.
1065 * Modifiers:: More precise control over effects of constraints.
1066 * Disable Insn Alternatives:: Disable insn alternatives using the @code{enabled} attribute.
1067 * Machine Constraints:: Existing constraints for some particular machines.
1068 * Define Constraints:: How to define machine-specific constraints.
1069 * C Constraint Interface:: How to test constraints from C code.
1075 * Simple Constraints:: Basic use of constraints.
1076 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1077 * Modifiers:: More precise control over effects of constraints.
1078 * Machine Constraints:: Special constraints for some particular machines.
1082 @node Simple Constraints
1083 @subsection Simple Constraints
1084 @cindex simple constraints
1086 The simplest kind of constraint is a string full of letters, each of
1087 which describes one kind of operand that is permitted. Here are
1088 the letters that are allowed:
1092 Whitespace characters are ignored and can be inserted at any position
1093 except the first. This enables each alternative for different operands to
1094 be visually aligned in the machine description even if they have different
1095 number of constraints and modifiers.
1097 @cindex @samp{m} in constraint
1098 @cindex memory references in constraints
1100 A memory operand is allowed, with any kind of address that the machine
1101 supports in general.
1102 Note that the letter used for the general memory constraint can be
1103 re-defined by a back end using the @code{TARGET_MEM_CONSTRAINT} macro.
1105 @cindex offsettable address
1106 @cindex @samp{o} in constraint
1108 A memory operand is allowed, but only if the address is
1109 @dfn{offsettable}. This means that adding a small integer (actually,
1110 the width in bytes of the operand, as determined by its machine mode)
1111 may be added to the address and the result is also a valid memory
1114 @cindex autoincrement/decrement addressing
1115 For example, an address which is constant is offsettable; so is an
1116 address that is the sum of a register and a constant (as long as a
1117 slightly larger constant is also within the range of address-offsets
1118 supported by the machine); but an autoincrement or autodecrement
1119 address is not offsettable. More complicated indirect/indexed
1120 addresses may or may not be offsettable depending on the other
1121 addressing modes that the machine supports.
1123 Note that in an output operand which can be matched by another
1124 operand, the constraint letter @samp{o} is valid only when accompanied
1125 by both @samp{<} (if the target machine has predecrement addressing)
1126 and @samp{>} (if the target machine has preincrement addressing).
1128 @cindex @samp{V} in constraint
1130 A memory operand that is not offsettable. In other words, anything that
1131 would fit the @samp{m} constraint but not the @samp{o} constraint.
1133 @cindex @samp{<} in constraint
1135 A memory operand with autodecrement addressing (either predecrement or
1136 postdecrement) is allowed. In inline @code{asm} this constraint is only
1137 allowed if the operand is used exactly once in an instruction that can
1138 handle the side-effects. Not using an operand with @samp{<} in constraint
1139 string in the inline @code{asm} pattern at all or using it in multiple
1140 instructions isn't valid, because the side-effects wouldn't be performed
1141 or would be performed more than once. Furthermore, on some targets
1142 the operand with @samp{<} in constraint string must be accompanied by
1143 special instruction suffixes like @code{%U0} instruction suffix on PowerPC
1144 or @code{%P0} on IA-64.
1146 @cindex @samp{>} in constraint
1148 A memory operand with autoincrement addressing (either preincrement or
1149 postincrement) is allowed. In inline @code{asm} the same restrictions
1150 as for @samp{<} apply.
1152 @cindex @samp{r} in constraint
1153 @cindex registers in constraints
1155 A register operand is allowed provided that it is in a general
1158 @cindex constants in constraints
1159 @cindex @samp{i} in constraint
1161 An immediate integer operand (one with constant value) is allowed.
1162 This includes symbolic constants whose values will be known only at
1163 assembly time or later.
1165 @cindex @samp{n} in constraint
1167 An immediate integer operand with a known numeric value is allowed.
1168 Many systems cannot support assembly-time constants for operands less
1169 than a word wide. Constraints for these operands should use @samp{n}
1170 rather than @samp{i}.
1172 @cindex @samp{I} in constraint
1173 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
1174 Other letters in the range @samp{I} through @samp{P} may be defined in
1175 a machine-dependent fashion to permit immediate integer operands with
1176 explicit integer values in specified ranges. For example, on the
1177 68000, @samp{I} is defined to stand for the range of values 1 to 8.
1178 This is the range permitted as a shift count in the shift
1181 @cindex @samp{E} in constraint
1183 An immediate floating operand (expression code @code{const_double}) is
1184 allowed, but only if the target floating point format is the same as
1185 that of the host machine (on which the compiler is running).
1187 @cindex @samp{F} in constraint
1189 An immediate floating operand (expression code @code{const_double} or
1190 @code{const_vector}) is allowed.
1192 @cindex @samp{G} in constraint
1193 @cindex @samp{H} in constraint
1194 @item @samp{G}, @samp{H}
1195 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
1196 permit immediate floating operands in particular ranges of values.
1198 @cindex @samp{s} in constraint
1200 An immediate integer operand whose value is not an explicit integer is
1203 This might appear strange; if an insn allows a constant operand with a
1204 value not known at compile time, it certainly must allow any known
1205 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
1206 better code to be generated.
1208 For example, on the 68000 in a fullword instruction it is possible to
1209 use an immediate operand; but if the immediate value is between @minus{}128
1210 and 127, better code results from loading the value into a register and
1211 using the register. This is because the load into the register can be
1212 done with a @samp{moveq} instruction. We arrange for this to happen
1213 by defining the letter @samp{K} to mean ``any integer outside the
1214 range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand
1217 @cindex @samp{g} in constraint
1219 Any register, memory or immediate integer operand is allowed, except for
1220 registers that are not general registers.
1222 @cindex @samp{X} in constraint
1225 Any operand whatsoever is allowed, even if it does not satisfy
1226 @code{general_operand}. This is normally used in the constraint of
1227 a @code{match_scratch} when certain alternatives will not actually
1228 require a scratch register.
1231 Any operand whatsoever is allowed.
1234 @cindex @samp{0} in constraint
1235 @cindex digits in constraint
1236 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
1237 An operand that matches the specified operand number is allowed. If a
1238 digit is used together with letters within the same alternative, the
1239 digit should come last.
1241 This number is allowed to be more than a single digit. If multiple
1242 digits are encountered consecutively, they are interpreted as a single
1243 decimal integer. There is scant chance for ambiguity, since to-date
1244 it has never been desirable that @samp{10} be interpreted as matching
1245 either operand 1 @emph{or} operand 0. Should this be desired, one
1246 can use multiple alternatives instead.
1248 @cindex matching constraint
1249 @cindex constraint, matching
1250 This is called a @dfn{matching constraint} and what it really means is
1251 that the assembler has only a single operand that fills two roles
1253 considered separate in the RTL insn. For example, an add insn has two
1254 input operands and one output operand in the RTL, but on most CISC
1257 which @code{asm} distinguishes. For example, an add instruction uses
1258 two input operands and an output operand, but on most CISC
1260 machines an add instruction really has only two operands, one of them an
1261 input-output operand:
1267 Matching constraints are used in these circumstances.
1268 More precisely, the two operands that match must include one input-only
1269 operand and one output-only operand. Moreover, the digit must be a
1270 smaller number than the number of the operand that uses it in the
1274 For operands to match in a particular case usually means that they
1275 are identical-looking RTL expressions. But in a few special cases
1276 specific kinds of dissimilarity are allowed. For example, @code{*x}
1277 as an input operand will match @code{*x++} as an output operand.
1278 For proper results in such cases, the output template should always
1279 use the output-operand's number when printing the operand.
1282 @cindex load address instruction
1283 @cindex push address instruction
1284 @cindex address constraints
1285 @cindex @samp{p} in constraint
1287 An operand that is a valid memory address is allowed. This is
1288 for ``load address'' and ``push address'' instructions.
1290 @findex address_operand
1291 @samp{p} in the constraint must be accompanied by @code{address_operand}
1292 as the predicate in the @code{match_operand}. This predicate interprets
1293 the mode specified in the @code{match_operand} as the mode of the memory
1294 reference for which the address would be valid.
1296 @cindex other register constraints
1297 @cindex extensible constraints
1298 @item @var{other-letters}
1299 Other letters can be defined in machine-dependent fashion to stand for
1300 particular classes of registers or other arbitrary operand types.
1301 @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
1302 for data, address and floating point registers.
1306 In order to have valid assembler code, each operand must satisfy
1307 its constraint. But a failure to do so does not prevent the pattern
1308 from applying to an insn. Instead, it directs the compiler to modify
1309 the code so that the constraint will be satisfied. Usually this is
1310 done by copying an operand into a register.
1312 Contrast, therefore, the two instruction patterns that follow:
1316 [(set (match_operand:SI 0 "general_operand" "=r")
1317 (plus:SI (match_dup 0)
1318 (match_operand:SI 1 "general_operand" "r")))]
1324 which has two operands, one of which must appear in two places, and
1328 [(set (match_operand:SI 0 "general_operand" "=r")
1329 (plus:SI (match_operand:SI 1 "general_operand" "0")
1330 (match_operand:SI 2 "general_operand" "r")))]
1336 which has three operands, two of which are required by a constraint to be
1337 identical. If we are considering an insn of the form
1340 (insn @var{n} @var{prev} @var{next}
1342 (plus:SI (reg:SI 6) (reg:SI 109)))
1347 the first pattern would not apply at all, because this insn does not
1348 contain two identical subexpressions in the right place. The pattern would
1349 say, ``That does not look like an add instruction; try other patterns''.
1350 The second pattern would say, ``Yes, that's an add instruction, but there
1351 is something wrong with it''. It would direct the reload pass of the
1352 compiler to generate additional insns to make the constraint true. The
1353 results might look like this:
1356 (insn @var{n2} @var{prev} @var{n}
1357 (set (reg:SI 3) (reg:SI 6))
1360 (insn @var{n} @var{n2} @var{next}
1362 (plus:SI (reg:SI 3) (reg:SI 109)))
1366 It is up to you to make sure that each operand, in each pattern, has
1367 constraints that can handle any RTL expression that could be present for
1368 that operand. (When multiple alternatives are in use, each pattern must,
1369 for each possible combination of operand expressions, have at least one
1370 alternative which can handle that combination of operands.) The
1371 constraints don't need to @emph{allow} any possible operand---when this is
1372 the case, they do not constrain---but they must at least point the way to
1373 reloading any possible operand so that it will fit.
1377 If the constraint accepts whatever operands the predicate permits,
1378 there is no problem: reloading is never necessary for this operand.
1380 For example, an operand whose constraints permit everything except
1381 registers is safe provided its predicate rejects registers.
1383 An operand whose predicate accepts only constant values is safe
1384 provided its constraints include the letter @samp{i}. If any possible
1385 constant value is accepted, then nothing less than @samp{i} will do;
1386 if the predicate is more selective, then the constraints may also be
1390 Any operand expression can be reloaded by copying it into a register.
1391 So if an operand's constraints allow some kind of register, it is
1392 certain to be safe. It need not permit all classes of registers; the
1393 compiler knows how to copy a register into another register of the
1394 proper class in order to make an instruction valid.
1396 @cindex nonoffsettable memory reference
1397 @cindex memory reference, nonoffsettable
1399 A nonoffsettable memory reference can be reloaded by copying the
1400 address into a register. So if the constraint uses the letter
1401 @samp{o}, all memory references are taken care of.
1404 A constant operand can be reloaded by allocating space in memory to
1405 hold it as preinitialized data. Then the memory reference can be used
1406 in place of the constant. So if the constraint uses the letters
1407 @samp{o} or @samp{m}, constant operands are not a problem.
1410 If the constraint permits a constant and a pseudo register used in an insn
1411 was not allocated to a hard register and is equivalent to a constant,
1412 the register will be replaced with the constant. If the predicate does
1413 not permit a constant and the insn is re-recognized for some reason, the
1414 compiler will crash. Thus the predicate must always recognize any
1415 objects allowed by the constraint.
1418 If the operand's predicate can recognize registers, but the constraint does
1419 not permit them, it can make the compiler crash. When this operand happens
1420 to be a register, the reload pass will be stymied, because it does not know
1421 how to copy a register temporarily into memory.
1423 If the predicate accepts a unary operator, the constraint applies to the
1424 operand. For example, the MIPS processor at ISA level 3 supports an
1425 instruction which adds two registers in @code{SImode} to produce a
1426 @code{DImode} result, but only if the registers are correctly sign
1427 extended. This predicate for the input operands accepts a
1428 @code{sign_extend} of an @code{SImode} register. Write the constraint
1429 to indicate the type of register that is required for the operand of the
1433 @node Multi-Alternative
1434 @subsection Multiple Alternative Constraints
1435 @cindex multiple alternative constraints
1437 Sometimes a single instruction has multiple alternative sets of possible
1438 operands. For example, on the 68000, a logical-or instruction can combine
1439 register or an immediate value into memory, or it can combine any kind of
1440 operand into a register; but it cannot combine one memory location into
1443 These constraints are represented as multiple alternatives. An alternative
1444 can be described by a series of letters for each operand. The overall
1445 constraint for an operand is made from the letters for this operand
1446 from the first alternative, a comma, the letters for this operand from
1447 the second alternative, a comma, and so on until the last alternative.
1449 Here is how it is done for fullword logical-or on the 68000:
1452 (define_insn "iorsi3"
1453 [(set (match_operand:SI 0 "general_operand" "=m,d")
1454 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1455 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1459 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1460 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1461 2. The second alternative has @samp{d} (data register) for operand 0,
1462 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1463 @samp{%} in the constraints apply to all the alternatives; their
1464 meaning is explained in the next section (@pxref{Class Preferences}).
1467 @c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL
1468 If all the operands fit any one alternative, the instruction is valid.
1469 Otherwise, for each alternative, the compiler counts how many instructions
1470 must be added to copy the operands so that that alternative applies.
1471 The alternative requiring the least copying is chosen. If two alternatives
1472 need the same amount of copying, the one that comes first is chosen.
1473 These choices can be altered with the @samp{?} and @samp{!} characters:
1476 @cindex @samp{?} in constraint
1477 @cindex question mark
1479 Disparage slightly the alternative that the @samp{?} appears in,
1480 as a choice when no alternative applies exactly. The compiler regards
1481 this alternative as one unit more costly for each @samp{?} that appears
1484 @cindex @samp{!} in constraint
1485 @cindex exclamation point
1487 Disparage severely the alternative that the @samp{!} appears in.
1488 This alternative can still be used if it fits without reloading,
1489 but if reloading is needed, some other alternative will be used.
1493 When an insn pattern has multiple alternatives in its constraints, often
1494 the appearance of the assembler code is determined mostly by which
1495 alternative was matched. When this is so, the C code for writing the
1496 assembler code can use the variable @code{which_alternative}, which is
1497 the ordinal number of the alternative that was actually satisfied (0 for
1498 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1502 @node Class Preferences
1503 @subsection Register Class Preferences
1504 @cindex class preference constraints
1505 @cindex register class preference constraints
1507 @cindex voting between constraint alternatives
1508 The operand constraints have another function: they enable the compiler
1509 to decide which kind of hardware register a pseudo register is best
1510 allocated to. The compiler examines the constraints that apply to the
1511 insns that use the pseudo register, looking for the machine-dependent
1512 letters such as @samp{d} and @samp{a} that specify classes of registers.
1513 The pseudo register is put in whichever class gets the most ``votes''.
1514 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1515 favor of a general register. The machine description says which registers
1516 are considered general.
1518 Of course, on some machines all registers are equivalent, and no register
1519 classes are defined. Then none of this complexity is relevant.
1523 @subsection Constraint Modifier Characters
1524 @cindex modifiers in constraints
1525 @cindex constraint modifier characters
1527 @c prevent bad page break with this line
1528 Here are constraint modifier characters.
1531 @cindex @samp{=} in constraint
1533 Means that this operand is write-only for this instruction: the previous
1534 value is discarded and replaced by output data.
1536 @cindex @samp{+} in constraint
1538 Means that this operand is both read and written by the instruction.
1540 When the compiler fixes up the operands to satisfy the constraints,
1541 it needs to know which operands are inputs to the instruction and
1542 which are outputs from it. @samp{=} identifies an output; @samp{+}
1543 identifies an operand that is both input and output; all other operands
1544 are assumed to be input only.
1546 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1547 first character of the constraint string.
1549 @cindex @samp{&} in constraint
1550 @cindex earlyclobber operand
1552 Means (in a particular alternative) that this operand is an
1553 @dfn{earlyclobber} operand, which is modified before the instruction is
1554 finished using the input operands. Therefore, this operand may not lie
1555 in a register that is used as an input operand or as part of any memory
1558 @samp{&} applies only to the alternative in which it is written. In
1559 constraints with multiple alternatives, sometimes one alternative
1560 requires @samp{&} while others do not. See, for example, the
1561 @samp{movdf} insn of the 68000.
1563 An input operand can be tied to an earlyclobber operand if its only
1564 use as an input occurs before the early result is written. Adding
1565 alternatives of this form often allows GCC to produce better code
1566 when only some of the inputs can be affected by the earlyclobber.
1567 See, for example, the @samp{mulsi3} insn of the ARM@.
1569 @samp{&} does not obviate the need to write @samp{=}.
1571 @cindex @samp{%} in constraint
1573 Declares the instruction to be commutative for this operand and the
1574 following operand. This means that the compiler may interchange the
1575 two operands if that is the cheapest way to make all operands fit the
1578 This is often used in patterns for addition instructions
1579 that really have only two operands: the result must go in one of the
1580 arguments. Here for example, is how the 68000 halfword-add
1581 instruction is defined:
1584 (define_insn "addhi3"
1585 [(set (match_operand:HI 0 "general_operand" "=m,r")
1586 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1587 (match_operand:HI 2 "general_operand" "di,g")))]
1591 GCC can only handle one commutative pair in an asm; if you use more,
1592 the compiler may fail. Note that you need not use the modifier if
1593 the two alternatives are strictly identical; this would only waste
1594 time in the reload pass. The modifier is not operational after
1595 register allocation, so the result of @code{define_peephole2}
1596 and @code{define_split}s performed after reload cannot rely on
1597 @samp{%} to make the intended insn match.
1599 @cindex @samp{#} in constraint
1601 Says that all following characters, up to the next comma, are to be
1602 ignored as a constraint. They are significant only for choosing
1603 register preferences.
1605 @cindex @samp{*} in constraint
1607 Says that the following character should be ignored when choosing
1608 register preferences. @samp{*} has no effect on the meaning of the
1609 constraint as a constraint, and no effect on reloading.
1612 Here is an example: the 68000 has an instruction to sign-extend a
1613 halfword in a data register, and can also sign-extend a value by
1614 copying it into an address register. While either kind of register is
1615 acceptable, the constraints on an address-register destination are
1616 less strict, so it is best if register allocation makes an address
1617 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1618 constraint letter (for data register) is ignored when computing
1619 register preferences.
1622 (define_insn "extendhisi2"
1623 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1625 (match_operand:HI 1 "general_operand" "0,g")))]
1631 @node Machine Constraints
1632 @subsection Constraints for Particular Machines
1633 @cindex machine specific constraints
1634 @cindex constraints, machine specific
1636 Whenever possible, you should use the general-purpose constraint letters
1637 in @code{asm} arguments, since they will convey meaning more readily to
1638 people reading your code. Failing that, use the constraint letters
1639 that usually have very similar meanings across architectures. The most
1640 commonly used constraints are @samp{m} and @samp{r} (for memory and
1641 general-purpose registers respectively; @pxref{Simple Constraints}), and
1642 @samp{I}, usually the letter indicating the most common
1643 immediate-constant format.
1645 Each architecture defines additional constraints. These constraints
1646 are used by the compiler itself for instruction generation, as well as
1647 for @code{asm} statements; therefore, some of the constraints are not
1648 particularly useful for @code{asm}. Here is a summary of some of the
1649 machine-dependent constraints available on some particular machines;
1650 it includes both constraints that are useful for @code{asm} and
1651 constraints that aren't. The compiler source file mentioned in the
1652 table heading for each architecture is the definitive reference for
1653 the meanings of that architecture's constraints.
1656 @item ARM family---@file{config/arm/arm.h}
1659 Floating-point register
1662 VFP floating-point register
1665 One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0
1669 Floating-point constant that would satisfy the constraint @samp{F} if it
1673 Integer that is valid as an immediate operand in a data processing
1674 instruction. That is, an integer in the range 0 to 255 rotated by a
1678 Integer in the range @minus{}4095 to 4095
1681 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1684 Integer that satisfies constraint @samp{I} when negated (twos complement)
1687 Integer in the range 0 to 32
1690 A memory reference where the exact address is in a single register
1691 (`@samp{m}' is preferable for @code{asm} statements)
1694 An item in the constant pool
1697 A symbol in the text segment of the current file
1700 A memory reference suitable for VFP load/store insns (reg+constant offset)
1703 A memory reference suitable for iWMMXt load/store instructions.
1706 A memory reference suitable for the ARMv4 ldrsb instruction.
1709 @item AVR family---@file{config/avr/constraints.md}
1712 Registers from r0 to r15
1715 Registers from r16 to r23
1718 Registers from r16 to r31
1721 Registers from r24 to r31. These registers can be used in @samp{adiw} command
1724 Pointer register (r26--r31)
1727 Base pointer register (r28--r31)
1730 Stack pointer register (SPH:SPL)
1733 Temporary register r0
1736 Register pair X (r27:r26)
1739 Register pair Y (r29:r28)
1742 Register pair Z (r31:r30)
1745 Constant greater than @minus{}1, less than 64
1748 Constant greater than @minus{}64, less than 1
1757 Constant that fits in 8 bits
1760 Constant integer @minus{}1
1763 Constant integer 8, 16, or 24
1769 A floating point constant 0.0
1772 Integer constant in the range @minus{}6 @dots{} 5.
1775 A memory address based on Y or Z pointer with displacement.
1781 @item Hewlett-Packard PA-RISC---@file{config/pa/pa.h}
1787 Floating point register
1790 Shift amount register
1793 Floating point register (deprecated)
1796 Upper floating point register (32-bit), floating point register (64-bit)
1802 Signed 11-bit integer constant
1805 Signed 14-bit integer constant
1808 Integer constant that can be deposited with a @code{zdepi} instruction
1811 Signed 5-bit integer constant
1817 Integer constant that can be loaded with a @code{ldil} instruction
1820 Integer constant whose value plus one is a power of 2
1823 Integer constant that can be used for @code{and} operations in @code{depi}
1824 and @code{extru} instructions
1833 Floating-point constant 0.0
1836 A @code{lo_sum} data-linkage-table memory operand
1839 A memory operand that can be used as the destination operand of an
1840 integer store instruction
1843 A scaled or unscaled indexed memory operand
1846 A memory operand for floating-point loads and stores
1849 A register indirect memory operand
1852 @item picoChip family---@file{picochip.h}
1858 Pointer register. A register which can be used to access memory without
1859 supplying an offset. Any other register can be used to access memory,
1860 but will need a constant offset. In the case of the offset being zero,
1861 it is more efficient to use a pointer register, since this reduces code
1865 A twin register. A register which may be paired with an adjacent
1866 register to create a 32-bit register.
1869 Any absolute memory address (e.g., symbolic constant, symbolic
1873 4-bit signed integer.
1876 4-bit unsigned integer.
1879 8-bit signed integer.
1882 Any constant whose absolute value is no greater than 4-bits.
1885 10-bit signed integer
1888 16-bit signed integer.
1892 @item PowerPC and IBM RS6000---@file{config/rs6000/rs6000.h}
1895 Address base register
1898 Floating point register (containing 64-bit value)
1901 Floating point register (containing 32-bit value)
1904 Altivec vector register
1907 VSX vector register to hold vector double data
1910 VSX vector register to hold vector float data
1913 VSX vector register to hold scalar float data
1919 @samp{MQ}, @samp{CTR}, or @samp{LINK} register
1928 @samp{LINK} register
1931 @samp{CR} register (condition register) number 0
1934 @samp{CR} register (condition register)
1937 @samp{XER[CA]} carry bit (part of the XER register)
1940 Signed 16-bit constant
1943 Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for
1944 @code{SImode} constants)
1947 Unsigned 16-bit constant
1950 Signed 16-bit constant shifted left 16 bits
1953 Constant larger than 31
1962 Constant whose negation is a signed 16-bit constant
1965 Floating point constant that can be loaded into a register with one
1966 instruction per word
1969 Integer/Floating point constant that can be loaded into a register using
1974 Normally, @code{m} does not allow addresses that update the base register.
1975 If @samp{<} or @samp{>} constraint is also used, they are allowed and
1976 therefore on PowerPC targets in that case it is only safe
1977 to use @samp{m<>} in an @code{asm} statement if that @code{asm} statement
1978 accesses the operand exactly once. The @code{asm} statement must also
1979 use @samp{%U@var{<opno>}} as a placeholder for the ``update'' flag in the
1980 corresponding load or store instruction. For example:
1983 asm ("st%U0 %1,%0" : "=m<>" (mem) : "r" (val));
1989 asm ("st %1,%0" : "=m<>" (mem) : "r" (val));
1995 A ``stable'' memory operand; that is, one which does not include any
1996 automodification of the base register. This used to be useful when
1997 @samp{m} allowed automodification of the base register, but as those are now only
1998 allowed when @samp{<} or @samp{>} is used, @samp{es} is basically the same
1999 as @samp{m} without @samp{<} and @samp{>}.
2002 Memory operand that is an offset from a register (it is usually better
2003 to use @samp{m} or @samp{es} in @code{asm} statements)
2006 Memory operand that is an indexed or indirect from a register (it is
2007 usually better to use @samp{m} or @samp{es} in @code{asm} statements)
2013 Address operand that is an indexed or indirect from a register (@samp{p} is
2014 preferable for @code{asm} statements)
2017 Constant suitable as a 64-bit mask operand
2020 Constant suitable as a 32-bit mask operand
2023 System V Release 4 small data area reference
2026 AND masks that can be performed by two rldic@{l, r@} instructions
2029 Vector constant that does not require memory
2032 Vector constant that is all zeros.
2036 @item Intel 386---@file{config/i386/constraints.md}
2039 Legacy register---the eight integer registers available on all
2040 i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
2041 @code{si}, @code{di}, @code{bp}, @code{sp}).
2044 Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a},
2045 @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.
2048 Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
2049 @code{c}, and @code{d}.
2053 Any register that can be used as the index in a base+index memory
2054 access: that is, any general register except the stack pointer.
2058 The @code{a} register.
2061 The @code{b} register.
2064 The @code{c} register.
2067 The @code{d} register.
2070 The @code{si} register.
2073 The @code{di} register.
2076 The @code{a} and @code{d} registers. This class is used for instructions
2077 that return double word results in the @code{ax:dx} register pair. Single
2078 word values will be allocated either in @code{ax} or @code{dx}.
2079 For example on i386 the following implements @code{rdtsc}:
2082 unsigned long long rdtsc (void)
2084 unsigned long long tick;
2085 __asm__ __volatile__("rdtsc":"=A"(tick));
2090 This is not correct on x86_64 as it would allocate tick in either @code{ax}
2091 or @code{dx}. You have to use the following variant instead:
2094 unsigned long long rdtsc (void)
2096 unsigned int tickl, tickh;
2097 __asm__ __volatile__("rdtsc":"=a"(tickl),"=d"(tickh));
2098 return ((unsigned long long)tickh << 32)|tickl;
2104 Any 80387 floating-point (stack) register.
2107 Top of 80387 floating-point stack (@code{%st(0)}).
2110 Second from top of 80387 floating-point stack (@code{%st(1)}).
2119 First SSE register (@code{%xmm0}).
2123 Any SSE register, when SSE2 is enabled.
2126 Any SSE register, when SSE2 and inter-unit moves are enabled.
2129 Any MMX register, when inter-unit moves are enabled.
2133 Integer constant in the range 0 @dots{} 31, for 32-bit shifts.
2136 Integer constant in the range 0 @dots{} 63, for 64-bit shifts.
2139 Signed 8-bit integer constant.
2142 @code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move.
2145 0, 1, 2, or 3 (shifts for the @code{lea} instruction).
2148 Unsigned 8-bit integer constant (for @code{in} and @code{out}
2153 Integer constant in the range 0 @dots{} 127, for 128-bit shifts.
2157 Standard 80387 floating point constant.
2160 Standard SSE floating point constant.
2163 32-bit signed integer constant, or a symbolic reference known
2164 to fit that range (for immediate operands in sign-extending x86-64
2168 32-bit unsigned integer constant, or a symbolic reference known
2169 to fit that range (for immediate operands in zero-extending x86-64
2174 @item Intel IA-64---@file{config/ia64/ia64.h}
2177 General register @code{r0} to @code{r3} for @code{addl} instruction
2183 Predicate register (@samp{c} as in ``conditional'')
2186 Application register residing in M-unit
2189 Application register residing in I-unit
2192 Floating-point register
2195 Memory operand. If used together with @samp{<} or @samp{>},
2196 the operand can have postincrement and postdecrement which
2197 require printing with @samp{%Pn} on IA-64.
2200 Floating-point constant 0.0 or 1.0
2203 14-bit signed integer constant
2206 22-bit signed integer constant
2209 8-bit signed integer constant for logical instructions
2212 8-bit adjusted signed integer constant for compare pseudo-ops
2215 6-bit unsigned integer constant for shift counts
2218 9-bit signed integer constant for load and store postincrements
2224 0 or @minus{}1 for @code{dep} instruction
2227 Non-volatile memory for floating-point loads and stores
2230 Integer constant in the range 1 to 4 for @code{shladd} instruction
2233 Memory operand except postincrement and postdecrement. This is
2234 now roughly the same as @samp{m} when not used together with @samp{<}
2238 @item FRV---@file{config/frv/frv.h}
2241 Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}).
2244 Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}).
2247 Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and
2248 @code{icc0} to @code{icc3}).
2251 Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}).
2254 Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}).
2255 Odd registers are excluded not in the class but through the use of a machine
2256 mode larger than 4 bytes.
2259 Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}).
2262 Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}).
2263 Odd registers are excluded not in the class but through the use of a machine
2264 mode larger than 4 bytes.
2267 Register in the class @code{LR_REG} (the @code{lr} register).
2270 Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}).
2271 Register numbers not divisible by 4 are excluded not in the class but through
2272 the use of a machine mode larger than 8 bytes.
2275 Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}).
2278 Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}).
2281 Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}).
2284 Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}).
2287 Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}).
2288 Register numbers not divisible by 4 are excluded not in the class but through
2289 the use of a machine mode larger than 8 bytes.
2292 Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}).
2295 Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}).
2298 Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}).
2301 Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}).
2304 Floating point constant zero
2307 6-bit signed integer constant
2310 10-bit signed integer constant
2313 16-bit signed integer constant
2316 16-bit unsigned integer constant
2319 12-bit signed integer constant that is negative---i.e.@: in the
2320 range of @minus{}2048 to @minus{}1
2326 12-bit signed integer constant that is greater than zero---i.e.@: in the
2331 @item Blackfin family---@file{config/bfin/constraints.md}
2340 A call clobbered P register.
2343 A single register. If @var{n} is in the range 0 to 7, the corresponding D
2344 register. If it is @code{A}, then the register P0.
2347 Even-numbered D register
2350 Odd-numbered D register
2353 Accumulator register.
2356 Even-numbered accumulator register.
2359 Odd-numbered accumulator register.
2371 Registers used for circular buffering, i.e. I, B, or L registers.
2386 Any D, P, B, M, I or L register.
2389 Additional registers typically used only in prologues and epilogues: RETS,
2390 RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.
2393 Any register except accumulators or CC.
2396 Signed 16 bit integer (in the range @minus{}32768 to 32767)
2399 Unsigned 16 bit integer (in the range 0 to 65535)
2402 Signed 7 bit integer (in the range @minus{}64 to 63)
2405 Unsigned 7 bit integer (in the range 0 to 127)
2408 Unsigned 5 bit integer (in the range 0 to 31)
2411 Signed 4 bit integer (in the range @minus{}8 to 7)
2414 Signed 3 bit integer (in the range @minus{}3 to 4)
2417 Unsigned 3 bit integer (in the range 0 to 7)
2420 Constant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4.
2423 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2424 use with either accumulator.
2427 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2428 use only with accumulator A1.
2437 An integer constant with exactly a single bit set.
2440 An integer constant with all bits set except exactly one.
2448 @item M32C---@file{config/m32c/m32c.c}
2453 @samp{$sp}, @samp{$fb}, @samp{$sb}.
2456 Any control register, when they're 16 bits wide (nothing if control
2457 registers are 24 bits wide)
2460 Any control register, when they're 24 bits wide.
2469 $r0 or $r2, or $r2r0 for 32 bit values.
2472 $r1 or $r3, or $r3r1 for 32 bit values.
2475 A register that can hold a 64 bit value.
2478 $r0 or $r1 (registers with addressable high/low bytes)
2487 Address registers when they're 16 bits wide.
2490 Address registers when they're 24 bits wide.
2493 Registers that can hold QI values.
2496 Registers that can be used with displacements ($a0, $a1, $sb).
2499 Registers that can hold 32 bit values.
2502 Registers that can hold 16 bit values.
2505 Registers chat can hold 16 bit values, including all control
2509 $r0 through R1, plus $a0 and $a1.
2515 The memory-based pseudo-registers $mem0 through $mem15.
2518 Registers that can hold pointers (16 bit registers for r8c, m16c; 24
2519 bit registers for m32cm, m32c).
2522 Matches multiple registers in a PARALLEL to form a larger register.
2523 Used to match function return values.
2529 @minus{}128 @dots{} 127
2532 @minus{}32768 @dots{} 32767
2538 @minus{}8 @dots{} @minus{}1 or 1 @dots{} 8
2541 @minus{}16 @dots{} @minus{}1 or 1 @dots{} 16
2544 @minus{}32 @dots{} @minus{}1 or 1 @dots{} 32
2547 @minus{}65536 @dots{} @minus{}1
2550 An 8 bit value with exactly one bit set.
2553 A 16 bit value with exactly one bit set.
2556 The common src/dest memory addressing modes.
2559 Memory addressed using $a0 or $a1.
2562 Memory addressed with immediate addresses.
2565 Memory addressed using the stack pointer ($sp).
2568 Memory addressed using the frame base register ($fb).
2571 Memory addressed using the small base register ($sb).
2577 @item MeP---@file{config/mep/constraints.md}
2587 Any control register.
2590 Either the $hi or the $lo register.
2593 Coprocessor registers that can be directly loaded ($c0-$c15).
2596 Coprocessor registers that can be moved to each other.
2599 Coprocessor registers that can be moved to core registers.
2611 Registers which can be used in $tp-relative addressing.
2617 The coprocessor registers.
2620 The coprocessor control registers.
2626 User-defined register set A.
2629 User-defined register set B.
2632 User-defined register set C.
2635 User-defined register set D.
2638 Offsets for $gp-rel addressing.
2641 Constants that can be used directly with boolean insns.
2644 Constants that can be moved directly to registers.
2647 Small constants that can be added to registers.
2653 Small constants that can be compared to registers.
2656 Constants that can be loaded into the top half of registers.
2659 Signed 8-bit immediates.
2662 Symbols encoded for $tp-rel or $gp-rel addressing.
2665 Non-constant addresses for loading/saving coprocessor registers.
2668 The top half of a symbol's value.
2671 A register indirect address without offset.
2674 Symbolic references to the control bus.
2678 @item MicroBlaze---@file{config/microblaze/constraints.md}
2681 A general register (@code{r0} to @code{r31}).
2684 A status register (@code{rmsr}, @code{$fcc1} to @code{$fcc7}).
2688 @item MIPS---@file{config/mips/constraints.md}
2691 An address register. This is equivalent to @code{r} unless
2692 generating MIPS16 code.
2695 A floating-point register (if available).
2698 Formerly the @code{hi} register. This constraint is no longer supported.
2701 The @code{lo} register. Use this register to store values that are
2702 no bigger than a word.
2705 The concatenated @code{hi} and @code{lo} registers. Use this register
2706 to store doubleword values.
2709 A register suitable for use in an indirect jump. This will always be
2710 @code{$25} for @option{-mabicalls}.
2713 Register @code{$3}. Do not use this constraint in new code;
2714 it is retained only for compatibility with glibc.
2717 Equivalent to @code{r}; retained for backwards compatibility.
2720 A floating-point condition code register.
2723 A signed 16-bit constant (for arithmetic instructions).
2729 An unsigned 16-bit constant (for logic instructions).
2732 A signed 32-bit constant in which the lower 16 bits are zero.
2733 Such constants can be loaded using @code{lui}.
2736 A constant that cannot be loaded using @code{lui}, @code{addiu}
2740 A constant in the range @minus{}65535 to @minus{}1 (inclusive).
2743 A signed 15-bit constant.
2746 A constant in the range 1 to 65535 (inclusive).
2749 Floating-point zero.
2752 An address that can be used in a non-macro load or store.
2755 @item Motorola 680x0---@file{config/m68k/constraints.md}
2764 68881 floating-point register, if available
2767 Integer in the range 1 to 8
2770 16-bit signed number
2773 Signed number whose magnitude is greater than 0x80
2776 Integer in the range @minus{}8 to @minus{}1
2779 Signed number whose magnitude is greater than 0x100
2782 Range 24 to 31, rotatert:SI 8 to 1 expressed as rotate
2785 16 (for rotate using swap)
2788 Range 8 to 15, rotatert:HI 8 to 1 expressed as rotate
2791 Numbers that mov3q can handle
2794 Floating point constant that is not a 68881 constant
2797 Operands that satisfy 'm' when -mpcrel is in effect
2800 Operands that satisfy 's' when -mpcrel is not in effect
2803 Address register indirect addressing mode
2806 Register offset addressing
2821 Range of signed numbers that don't fit in 16 bits
2824 Integers valid for mvq
2827 Integers valid for a moveq followed by a swap
2830 Integers valid for mvz
2833 Integers valid for mvs
2839 Non-register operands allowed in clr
2843 @item Moxie---@file{config/moxie/constraints.md}
2852 A register indirect memory operand
2855 A constant in the range of 0 to 255.
2858 A constant in the range of 0 to @minus{}255.
2862 @item PDP-11---@file{config/pdp11/constraints.md}
2865 Floating point registers AC0 through AC3. These can be loaded from/to
2866 memory with a single instruction.
2869 Odd numbered general registers (R1, R3, R5). These are used for
2870 16-bit multiply operations.
2873 Any of the floating point registers (AC0 through AC5).
2876 Floating point constant 0.
2879 An integer constant that fits in 16 bits.
2882 An integer constant whose low order 16 bits are zero.
2885 An integer constant that does not meet the constraints for codes
2886 @samp{I} or @samp{J}.
2889 The integer constant 1.
2892 The integer constant @minus{}1.
2895 The integer constant 0.
2898 Integer constants @minus{}4 through @minus{}1 and 1 through 4; shifts by these
2899 amounts are handled as multiple single-bit shifts rather than a single
2900 variable-length shift.
2903 A memory reference which requires an additional word (address or
2904 offset) after the opcode.
2907 A memory reference that is encoded within the opcode.
2911 @item RX---@file{config/rx/constraints.md}
2914 An address which does not involve register indirect addressing or
2915 pre/post increment/decrement addressing.
2921 A constant in the range @minus{}256 to 255, inclusive.
2924 A constant in the range @minus{}128 to 127, inclusive.
2927 A constant in the range @minus{}32768 to 32767, inclusive.
2930 A constant in the range @minus{}8388608 to 8388607, inclusive.
2933 A constant in the range 0 to 15, inclusive.
2938 @item SPARC---@file{config/sparc/sparc.h}
2941 Floating-point register on the SPARC-V8 architecture and
2942 lower floating-point register on the SPARC-V9 architecture.
2945 Floating-point register. It is equivalent to @samp{f} on the
2946 SPARC-V8 architecture and contains both lower and upper
2947 floating-point registers on the SPARC-V9 architecture.
2950 Floating-point condition code register.
2953 Lower floating-point register. It is only valid on the SPARC-V9
2954 architecture when the Visual Instruction Set is available.
2957 Floating-point register. It is only valid on the SPARC-V9 architecture
2958 when the Visual Instruction Set is available.
2961 64-bit global or out register for the SPARC-V8+ architecture.
2967 Signed 13-bit constant
2973 32-bit constant with the low 12 bits clear (a constant that can be
2974 loaded with the @code{sethi} instruction)
2977 A constant in the range supported by @code{movcc} instructions
2980 A constant in the range supported by @code{movrcc} instructions
2983 Same as @samp{K}, except that it verifies that bits that are not in the
2984 lower 32-bit range are all zero. Must be used instead of @samp{K} for
2985 modes wider than @code{SImode}
2994 Signed 13-bit constant, sign-extended to 32 or 64 bits
2997 Floating-point constant whose integral representation can
2998 be moved into an integer register using a single sethi
3002 Floating-point constant whose integral representation can
3003 be moved into an integer register using a single mov
3007 Floating-point constant whose integral representation can
3008 be moved into an integer register using a high/lo_sum
3009 instruction sequence
3012 Memory address aligned to an 8-byte boundary
3018 Memory address for @samp{e} constraint registers
3025 @item SPU---@file{config/spu/spu.h}
3028 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value.
3031 An immediate for and/xor/or instructions. const_int is treated as a 64 bit value.
3034 An immediate for the @code{iohl} instruction. const_int is treated as a 64 bit value.
3037 An immediate which can be loaded with @code{fsmbi}.
3040 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value.
3043 An immediate for most arithmetic instructions. const_int is treated as a 32 bit value.
3046 An immediate for and/xor/or instructions. const_int is treated as a 32 bit value.
3049 An immediate for the @code{iohl} instruction. const_int is treated as a 32 bit value.
3052 A constant in the range [@minus{}64, 63] for shift/rotate instructions.
3055 An unsigned 7-bit constant for conversion/nop/channel instructions.
3058 A signed 10-bit constant for most arithmetic instructions.
3061 A signed 16 bit immediate for @code{stop}.
3064 An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}.
3067 An unsigned 7-bit constant whose 3 least significant bits are 0.
3070 An unsigned 3-bit constant for 16-byte rotates and shifts
3073 Call operand, reg, for indirect calls
3076 Call operand, symbol, for relative calls.
3079 Call operand, const_int, for absolute calls.
3082 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit.
3085 An immediate for shift and rotate instructions. const_int is treated as a 32 bit value.
3088 An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit.
3091 An immediate for the @code{iohl} instruction. const_int is sign extended to 128 bit.
3095 @item S/390 and zSeries---@file{config/s390/s390.h}
3098 Address register (general purpose register except r0)
3101 Condition code register
3104 Data register (arbitrary general purpose register)
3107 Floating-point register
3110 Unsigned 8-bit constant (0--255)
3113 Unsigned 12-bit constant (0--4095)
3116 Signed 16-bit constant (@minus{}32768--32767)
3119 Value appropriate as displacement.
3122 for short displacement
3123 @item (@minus{}524288..524287)
3124 for long displacement
3128 Constant integer with a value of 0x7fffffff.
3131 Multiple letter constraint followed by 4 parameter letters.
3134 number of the part counting from most to least significant
3138 mode of the containing operand
3140 value of the other parts (F---all bits set)
3142 The constraint matches if the specified part of a constant
3143 has a value different from its other parts.
3146 Memory reference without index register and with short displacement.
3149 Memory reference with index register and short displacement.
3152 Memory reference without index register but with long displacement.
3155 Memory reference with index register and long displacement.
3158 Pointer with short displacement.
3161 Pointer with long displacement.
3164 Shift count operand.
3168 @item Score family---@file{config/score/score.h}
3171 Registers from r0 to r32.
3174 Registers from r0 to r16.
3177 r8---r11 or r22---r27 registers.
3198 cnt + lcb + scb register.
3201 cr0---cr15 register.
3213 cp1 + cp2 + cp3 registers.
3216 High 16-bit constant (32-bit constant with 16 LSBs zero).
3219 Unsigned 5 bit integer (in the range 0 to 31).
3222 Unsigned 16 bit integer (in the range 0 to 65535).
3225 Signed 16 bit integer (in the range @minus{}32768 to 32767).
3228 Unsigned 14 bit integer (in the range 0 to 16383).
3231 Signed 14 bit integer (in the range @minus{}8192 to 8191).
3237 @item Xstormy16---@file{config/stormy16/stormy16.h}
3252 Registers r0 through r7.
3255 Registers r0 and r1.
3261 Registers r8 and r9.
3264 A constant between 0 and 3 inclusive.
3267 A constant that has exactly one bit set.
3270 A constant that has exactly one bit clear.
3273 A constant between 0 and 255 inclusive.
3276 A constant between @minus{}255 and 0 inclusive.
3279 A constant between @minus{}3 and 0 inclusive.
3282 A constant between 1 and 4 inclusive.
3285 A constant between @minus{}4 and @minus{}1 inclusive.
3288 A memory reference that is a stack push.
3291 A memory reference that is a stack pop.
3294 A memory reference that refers to a constant address of known value.
3297 The register indicated by Rx (not implemented yet).
3300 A constant that is not between 2 and 15 inclusive.
3307 @item TI C6X family---@file{config/c6x/constraints.md}
3310 Register file A (A0--A31).
3313 Register file B (B0--B31).
3316 Predicate registers in register file A (A0--A2 on C64X and
3317 higher, A1 and A2 otherwise).
3320 Predicate registers in register file B (B0--B2).
3323 A call-used register in register file B (B0--B9, B16--B31).
3326 Register file A, excluding predicate registers (A3--A31,
3327 plus A0 if not C64X or higher).
3330 Register file B, excluding predicate registers (B3--B31).
3333 Integer constant in the range 0 @dots{} 15.
3336 Integer constant in the range 0 @dots{} 31.
3339 Integer constant in the range @minus{}31 @dots{} 0.
3342 Integer constant in the range @minus{}16 @dots{} 15.
3345 Integer constant that can be the operand of an ADDA or a SUBA insn.
3348 Integer constant in the range 0 @dots{} 65535.
3351 Integer constant in the range @minus{}32768 @dots{} 32767.
3354 Integer constant in the range @math{-2^{20}} @dots{} @math{2^{20} - 1}.
3357 Integer constant that is a valid mask for the clr instruction.
3360 Integer constant that is a valid mask for the set instruction.
3363 Memory location with A base register.
3366 Memory location with B base register.
3370 On C64x+ targets, a GP-relative small data reference.
3373 Any kind of @code{SYMBOL_REF}, for use in a call address.
3376 Any kind of immediate operand, unless it matches the S0 constraint.
3379 Memory location with B base register, but not using a long offset.
3382 A memory operand with an address that can't be used in an unaligned access.
3386 Register B14 (aka DP).
3390 @item Xtensa---@file{config/xtensa/constraints.md}
3393 General-purpose 32-bit register
3396 One-bit boolean register
3399 MAC16 40-bit accumulator register
3402 Signed 12-bit integer constant, for use in MOVI instructions
3405 Signed 8-bit integer constant, for use in ADDI instructions
3408 Integer constant valid for BccI instructions
3411 Unsigned constant valid for BccUI instructions
3418 @node Disable Insn Alternatives
3419 @subsection Disable insn alternatives using the @code{enabled} attribute
3422 The @code{enabled} insn attribute may be used to disable certain insn
3423 alternatives for machine-specific reasons. This is useful when adding
3424 new instructions to an existing pattern which are only available for
3425 certain cpu architecture levels as specified with the @code{-march=}
3428 If an insn alternative is disabled, then it will never be used. The
3429 compiler treats the constraints for the disabled alternative as
3432 In order to make use of the @code{enabled} attribute a back end has to add
3433 in the machine description files:
3437 A definition of the @code{enabled} insn attribute. The attribute is
3438 defined as usual using the @code{define_attr} command. This
3439 definition should be based on other insn attributes and/or target flags.
3440 The @code{enabled} attribute is a numeric attribute and should evaluate to
3441 @code{(const_int 1)} for an enabled alternative and to
3442 @code{(const_int 0)} otherwise.
3444 A definition of another insn attribute used to describe for what
3445 reason an insn alternative might be available or
3446 not. E.g. @code{cpu_facility} as in the example below.
3448 An assignment for the second attribute to each insn definition
3449 combining instructions which are not all available under the same
3450 circumstances. (Note: It obviously only makes sense for definitions
3451 with more than one alternative. Otherwise the insn pattern should be
3452 disabled or enabled using the insn condition.)
3455 E.g. the following two patterns could easily be merged using the @code{enabled}
3460 (define_insn "*movdi_old"
3461 [(set (match_operand:DI 0 "register_operand" "=d")
3462 (match_operand:DI 1 "register_operand" " d"))]
3466 (define_insn "*movdi_new"
3467 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
3468 (match_operand:DI 1 "register_operand" " d,d,f"))]
3481 (define_insn "*movdi_combined"
3482 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
3483 (match_operand:DI 1 "register_operand" " d,d,f"))]
3489 [(set_attr "cpu_facility" "*,new,new")])
3493 with the @code{enabled} attribute defined like this:
3497 (define_attr "cpu_facility" "standard,new" (const_string "standard"))
3499 (define_attr "enabled" ""
3500 (cond [(eq_attr "cpu_facility" "standard") (const_int 1)
3501 (and (eq_attr "cpu_facility" "new")
3502 (ne (symbol_ref "TARGET_NEW") (const_int 0)))
3511 @node Define Constraints
3512 @subsection Defining Machine-Specific Constraints
3513 @cindex defining constraints
3514 @cindex constraints, defining
3516 Machine-specific constraints fall into two categories: register and
3517 non-register constraints. Within the latter category, constraints
3518 which allow subsets of all possible memory or address operands should
3519 be specially marked, to give @code{reload} more information.
3521 Machine-specific constraints can be given names of arbitrary length,
3522 but they must be entirely composed of letters, digits, underscores
3523 (@samp{_}), and angle brackets (@samp{< >}). Like C identifiers, they
3524 must begin with a letter or underscore.
3526 In order to avoid ambiguity in operand constraint strings, no
3527 constraint can have a name that begins with any other constraint's
3528 name. For example, if @code{x} is defined as a constraint name,
3529 @code{xy} may not be, and vice versa. As a consequence of this rule,
3530 no constraint may begin with one of the generic constraint letters:
3531 @samp{E F V X g i m n o p r s}.
3533 Register constraints correspond directly to register classes.
3534 @xref{Register Classes}. There is thus not much flexibility in their
3537 @deffn {MD Expression} define_register_constraint name regclass docstring
3538 All three arguments are string constants.
3539 @var{name} is the name of the constraint, as it will appear in
3540 @code{match_operand} expressions. If @var{name} is a multi-letter
3541 constraint its length shall be the same for all constraints starting
3542 with the same letter. @var{regclass} can be either the
3543 name of the corresponding register class (@pxref{Register Classes}),
3544 or a C expression which evaluates to the appropriate register class.
3545 If it is an expression, it must have no side effects, and it cannot
3546 look at the operand. The usual use of expressions is to map some
3547 register constraints to @code{NO_REGS} when the register class
3548 is not available on a given subarchitecture.
3550 @var{docstring} is a sentence documenting the meaning of the
3551 constraint. Docstrings are explained further below.
3554 Non-register constraints are more like predicates: the constraint
3555 definition gives a Boolean expression which indicates whether the
3558 @deffn {MD Expression} define_constraint name docstring exp
3559 The @var{name} and @var{docstring} arguments are the same as for
3560 @code{define_register_constraint}, but note that the docstring comes
3561 immediately after the name for these expressions. @var{exp} is an RTL
3562 expression, obeying the same rules as the RTL expressions in predicate
3563 definitions. @xref{Defining Predicates}, for details. If it
3564 evaluates true, the constraint matches; if it evaluates false, it
3565 doesn't. Constraint expressions should indicate which RTL codes they
3566 might match, just like predicate expressions.
3568 @code{match_test} C expressions have access to the
3569 following variables:
3573 The RTL object defining the operand.
3575 The machine mode of @var{op}.
3577 @samp{INTVAL (@var{op})}, if @var{op} is a @code{const_int}.
3579 @samp{CONST_DOUBLE_HIGH (@var{op})}, if @var{op} is an integer
3580 @code{const_double}.
3582 @samp{CONST_DOUBLE_LOW (@var{op})}, if @var{op} is an integer
3583 @code{const_double}.
3585 @samp{CONST_DOUBLE_REAL_VALUE (@var{op})}, if @var{op} is a floating-point
3586 @code{const_double}.
3589 The @var{*val} variables should only be used once another piece of the
3590 expression has verified that @var{op} is the appropriate kind of RTL
3594 Most non-register constraints should be defined with
3595 @code{define_constraint}. The remaining two definition expressions
3596 are only appropriate for constraints that should be handled specially
3597 by @code{reload} if they fail to match.
3599 @deffn {MD Expression} define_memory_constraint name docstring exp
3600 Use this expression for constraints that match a subset of all memory
3601 operands: that is, @code{reload} can make them match by converting the
3602 operand to the form @samp{@w{(mem (reg @var{X}))}}, where @var{X} is a
3603 base register (from the register class specified by
3604 @code{BASE_REG_CLASS}, @pxref{Register Classes}).
3606 For example, on the S/390, some instructions do not accept arbitrary
3607 memory references, but only those that do not make use of an index
3608 register. The constraint letter @samp{Q} is defined to represent a
3609 memory address of this type. If @samp{Q} is defined with
3610 @code{define_memory_constraint}, a @samp{Q} constraint can handle any
3611 memory operand, because @code{reload} knows it can simply copy the
3612 memory address into a base register if required. This is analogous to
3613 the way an @samp{o} constraint can handle any memory operand.
3615 The syntax and semantics are otherwise identical to
3616 @code{define_constraint}.
3619 @deffn {MD Expression} define_address_constraint name docstring exp
3620 Use this expression for constraints that match a subset of all address
3621 operands: that is, @code{reload} can make the constraint match by
3622 converting the operand to the form @samp{@w{(reg @var{X})}}, again
3623 with @var{X} a base register.
3625 Constraints defined with @code{define_address_constraint} can only be
3626 used with the @code{address_operand} predicate, or machine-specific
3627 predicates that work the same way. They are treated analogously to
3628 the generic @samp{p} constraint.
3630 The syntax and semantics are otherwise identical to
3631 @code{define_constraint}.
3634 For historical reasons, names beginning with the letters @samp{G H}
3635 are reserved for constraints that match only @code{const_double}s, and
3636 names beginning with the letters @samp{I J K L M N O P} are reserved
3637 for constraints that match only @code{const_int}s. This may change in
3638 the future. For the time being, constraints with these names must be
3639 written in a stylized form, so that @code{genpreds} can tell you did
3644 (define_constraint "[@var{GHIJKLMNOP}]@dots{}"
3646 (and (match_code "const_int") ; @r{@code{const_double} for G/H}
3647 @var{condition}@dots{})) ; @r{usually a @code{match_test}}
3650 @c the semicolons line up in the formatted manual
3652 It is fine to use names beginning with other letters for constraints
3653 that match @code{const_double}s or @code{const_int}s.
3655 Each docstring in a constraint definition should be one or more complete
3656 sentences, marked up in Texinfo format. @emph{They are currently unused.}
3657 In the future they will be copied into the GCC manual, in @ref{Machine
3658 Constraints}, replacing the hand-maintained tables currently found in
3659 that section. Also, in the future the compiler may use this to give
3660 more helpful diagnostics when poor choice of @code{asm} constraints
3661 causes a reload failure.
3663 If you put the pseudo-Texinfo directive @samp{@@internal} at the
3664 beginning of a docstring, then (in the future) it will appear only in
3665 the internals manual's version of the machine-specific constraint tables.
3666 Use this for constraints that should not appear in @code{asm} statements.
3668 @node C Constraint Interface
3669 @subsection Testing constraints from C
3670 @cindex testing constraints
3671 @cindex constraints, testing
3673 It is occasionally useful to test a constraint from C code rather than
3674 implicitly via the constraint string in a @code{match_operand}. The
3675 generated file @file{tm_p.h} declares a few interfaces for working
3676 with machine-specific constraints. None of these interfaces work with
3677 the generic constraints described in @ref{Simple Constraints}. This
3678 may change in the future.
3680 @strong{Warning:} @file{tm_p.h} may declare other functions that
3681 operate on constraints, besides the ones documented here. Do not use
3682 those functions from machine-dependent code. They exist to implement
3683 the old constraint interface that machine-independent components of
3684 the compiler still expect. They will change or disappear in the
3687 Some valid constraint names are not valid C identifiers, so there is a
3688 mangling scheme for referring to them from C@. Constraint names that
3689 do not contain angle brackets or underscores are left unchanged.
3690 Underscores are doubled, each @samp{<} is replaced with @samp{_l}, and
3691 each @samp{>} with @samp{_g}. Here are some examples:
3693 @c the @c's prevent double blank lines in the printed manual.
3695 @multitable {Original} {Mangled}
3696 @item @strong{Original} @tab @strong{Mangled} @c
3697 @item @code{x} @tab @code{x} @c
3698 @item @code{P42x} @tab @code{P42x} @c
3699 @item @code{P4_x} @tab @code{P4__x} @c
3700 @item @code{P4>x} @tab @code{P4_gx} @c
3701 @item @code{P4>>} @tab @code{P4_g_g} @c
3702 @item @code{P4_g>} @tab @code{P4__g_g} @c
3706 Throughout this section, the variable @var{c} is either a constraint
3707 in the abstract sense, or a constant from @code{enum constraint_num};
3708 the variable @var{m} is a mangled constraint name (usually as part of
3709 a larger identifier).
3711 @deftp Enum constraint_num
3712 For each machine-specific constraint, there is a corresponding
3713 enumeration constant: @samp{CONSTRAINT_} plus the mangled name of the
3714 constraint. Functions that take an @code{enum constraint_num} as an
3715 argument expect one of these constants.
3717 Machine-independent constraints do not have associated constants.
3718 This may change in the future.
3721 @deftypefun {inline bool} satisfies_constraint_@var{m} (rtx @var{exp})
3722 For each machine-specific, non-register constraint @var{m}, there is
3723 one of these functions; it returns @code{true} if @var{exp} satisfies the
3724 constraint. These functions are only visible if @file{rtl.h} was included
3725 before @file{tm_p.h}.
3728 @deftypefun bool constraint_satisfied_p (rtx @var{exp}, enum constraint_num @var{c})
3729 Like the @code{satisfies_constraint_@var{m}} functions, but the
3730 constraint to test is given as an argument, @var{c}. If @var{c}
3731 specifies a register constraint, this function will always return
3735 @deftypefun {enum reg_class} regclass_for_constraint (enum constraint_num @var{c})
3736 Returns the register class associated with @var{c}. If @var{c} is not
3737 a register constraint, or those registers are not available for the
3738 currently selected subtarget, returns @code{NO_REGS}.
3741 Here is an example use of @code{satisfies_constraint_@var{m}}. In
3742 peephole optimizations (@pxref{Peephole Definitions}), operand
3743 constraint strings are ignored, so if there are relevant constraints,
3744 they must be tested in the C condition. In the example, the
3745 optimization is applied if operand 2 does @emph{not} satisfy the
3746 @samp{K} constraint. (This is a simplified version of a peephole
3747 definition from the i386 machine description.)
3751 [(match_scratch:SI 3 "r")
3752 (set (match_operand:SI 0 "register_operand" "")
3753 (mult:SI (match_operand:SI 1 "memory_operand" "")
3754 (match_operand:SI 2 "immediate_operand" "")))]
3756 "!satisfies_constraint_K (operands[2])"
3758 [(set (match_dup 3) (match_dup 1))
3759 (set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))]
3764 @node Standard Names
3765 @section Standard Pattern Names For Generation
3766 @cindex standard pattern names
3767 @cindex pattern names
3768 @cindex names, pattern
3770 Here is a table of the instruction names that are meaningful in the RTL
3771 generation pass of the compiler. Giving one of these names to an
3772 instruction pattern tells the RTL generation pass that it can use the
3773 pattern to accomplish a certain task.
3776 @cindex @code{mov@var{m}} instruction pattern
3777 @item @samp{mov@var{m}}
3778 Here @var{m} stands for a two-letter machine mode name, in lowercase.
3779 This instruction pattern moves data with that machine mode from operand
3780 1 to operand 0. For example, @samp{movsi} moves full-word data.
3782 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
3783 own mode is wider than @var{m}, the effect of this instruction is
3784 to store the specified value in the part of the register that corresponds
3785 to mode @var{m}. Bits outside of @var{m}, but which are within the
3786 same target word as the @code{subreg} are undefined. Bits which are
3787 outside the target word are left unchanged.
3789 This class of patterns is special in several ways. First of all, each
3790 of these names up to and including full word size @emph{must} be defined,
3791 because there is no other way to copy a datum from one place to another.
3792 If there are patterns accepting operands in larger modes,
3793 @samp{mov@var{m}} must be defined for integer modes of those sizes.
3795 Second, these patterns are not used solely in the RTL generation pass.
3796 Even the reload pass can generate move insns to copy values from stack
3797 slots into temporary registers. When it does so, one of the operands is
3798 a hard register and the other is an operand that can need to be reloaded
3802 Therefore, when given such a pair of operands, the pattern must generate
3803 RTL which needs no reloading and needs no temporary registers---no
3804 registers other than the operands. For example, if you support the
3805 pattern with a @code{define_expand}, then in such a case the
3806 @code{define_expand} mustn't call @code{force_reg} or any other such
3807 function which might generate new pseudo registers.
3809 This requirement exists even for subword modes on a RISC machine where
3810 fetching those modes from memory normally requires several insns and
3811 some temporary registers.
3813 @findex change_address
3814 During reload a memory reference with an invalid address may be passed
3815 as an operand. Such an address will be replaced with a valid address
3816 later in the reload pass. In this case, nothing may be done with the
3817 address except to use it as it stands. If it is copied, it will not be
3818 replaced with a valid address. No attempt should be made to make such
3819 an address into a valid address and no routine (such as
3820 @code{change_address}) that will do so may be called. Note that
3821 @code{general_operand} will fail when applied to such an address.
3823 @findex reload_in_progress
3824 The global variable @code{reload_in_progress} (which must be explicitly
3825 declared if required) can be used to determine whether such special
3826 handling is required.
3828 The variety of operands that have reloads depends on the rest of the
3829 machine description, but typically on a RISC machine these can only be
3830 pseudo registers that did not get hard registers, while on other
3831 machines explicit memory references will get optional reloads.
3833 If a scratch register is required to move an object to or from memory,
3834 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
3836 If there are cases which need scratch registers during or after reload,
3837 you must provide an appropriate secondary_reload target hook.
3839 @findex can_create_pseudo_p
3840 The macro @code{can_create_pseudo_p} can be used to determine if it
3841 is unsafe to create new pseudo registers. If this variable is nonzero, then
3842 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
3844 The constraints on a @samp{mov@var{m}} must permit moving any hard
3845 register to any other hard register provided that
3846 @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
3847 @code{TARGET_REGISTER_MOVE_COST} applied to their classes returns a value
3850 It is obligatory to support floating point @samp{mov@var{m}}
3851 instructions into and out of any registers that can hold fixed point
3852 values, because unions and structures (which have modes @code{SImode} or
3853 @code{DImode}) can be in those registers and they may have floating
3856 There may also be a need to support fixed point @samp{mov@var{m}}
3857 instructions in and out of floating point registers. Unfortunately, I
3858 have forgotten why this was so, and I don't know whether it is still
3859 true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
3860 floating point registers, then the constraints of the fixed point
3861 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
3862 reload into a floating point register.
3864 @cindex @code{reload_in} instruction pattern
3865 @cindex @code{reload_out} instruction pattern
3866 @item @samp{reload_in@var{m}}
3867 @itemx @samp{reload_out@var{m}}
3868 These named patterns have been obsoleted by the target hook
3869 @code{secondary_reload}.
3871 Like @samp{mov@var{m}}, but used when a scratch register is required to
3872 move between operand 0 and operand 1. Operand 2 describes the scratch
3873 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
3874 macro in @pxref{Register Classes}.
3876 There are special restrictions on the form of the @code{match_operand}s
3877 used in these patterns. First, only the predicate for the reload
3878 operand is examined, i.e., @code{reload_in} examines operand 1, but not
3879 the predicates for operand 0 or 2. Second, there may be only one
3880 alternative in the constraints. Third, only a single register class
3881 letter may be used for the constraint; subsequent constraint letters
3882 are ignored. As a special exception, an empty constraint string
3883 matches the @code{ALL_REGS} register class. This may relieve ports
3884 of the burden of defining an @code{ALL_REGS} constraint letter just
3887 @cindex @code{movstrict@var{m}} instruction pattern
3888 @item @samp{movstrict@var{m}}
3889 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
3890 with mode @var{m} of a register whose natural mode is wider,
3891 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
3892 any of the register except the part which belongs to mode @var{m}.
3894 @cindex @code{movmisalign@var{m}} instruction pattern
3895 @item @samp{movmisalign@var{m}}
3896 This variant of a move pattern is designed to load or store a value
3897 from a memory address that is not naturally aligned for its mode.
3898 For a store, the memory will be in operand 0; for a load, the memory
3899 will be in operand 1. The other operand is guaranteed not to be a
3900 memory, so that it's easy to tell whether this is a load or store.
3902 This pattern is used by the autovectorizer, and when expanding a
3903 @code{MISALIGNED_INDIRECT_REF} expression.
3905 @cindex @code{load_multiple} instruction pattern
3906 @item @samp{load_multiple}
3907 Load several consecutive memory locations into consecutive registers.
3908 Operand 0 is the first of the consecutive registers, operand 1
3909 is the first memory location, and operand 2 is a constant: the
3910 number of consecutive registers.
3912 Define this only if the target machine really has such an instruction;
3913 do not define this if the most efficient way of loading consecutive
3914 registers from memory is to do them one at a time.
3916 On some machines, there are restrictions as to which consecutive
3917 registers can be stored into memory, such as particular starting or
3918 ending register numbers or only a range of valid counts. For those
3919 machines, use a @code{define_expand} (@pxref{Expander Definitions})
3920 and make the pattern fail if the restrictions are not met.
3922 Write the generated insn as a @code{parallel} with elements being a
3923 @code{set} of one register from the appropriate memory location (you may
3924 also need @code{use} or @code{clobber} elements). Use a
3925 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
3926 @file{rs6000.md} for examples of the use of this insn pattern.
3928 @cindex @samp{store_multiple} instruction pattern
3929 @item @samp{store_multiple}
3930 Similar to @samp{load_multiple}, but store several consecutive registers
3931 into consecutive memory locations. Operand 0 is the first of the
3932 consecutive memory locations, operand 1 is the first register, and
3933 operand 2 is a constant: the number of consecutive registers.
3935 @cindex @code{vec_load_lanes@var{m}@var{n}} instruction pattern
3936 @item @samp{vec_load_lanes@var{m}@var{n}}
3937 Perform an interleaved load of several vectors from memory operand 1
3938 into register operand 0. Both operands have mode @var{m}. The register
3939 operand is viewed as holding consecutive vectors of mode @var{n},
3940 while the memory operand is a flat array that contains the same number
3941 of elements. The operation is equivalent to:
3944 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
3945 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
3946 for (i = 0; i < c; i++)
3947 operand0[i][j] = operand1[j * c + i];
3950 For example, @samp{vec_load_lanestiv4hi} loads 8 16-bit values
3951 from memory into a register of mode @samp{TI}@. The register
3952 contains two consecutive vectors of mode @samp{V4HI}@.
3954 This pattern can only be used if:
3956 TARGET_ARRAY_MODE_SUPPORTED_P (@var{n}, @var{c})
3958 is true. GCC assumes that, if a target supports this kind of
3959 instruction for some mode @var{n}, it also supports unaligned
3960 loads for vectors of mode @var{n}.
3962 @cindex @code{vec_store_lanes@var{m}@var{n}} instruction pattern
3963 @item @samp{vec_store_lanes@var{m}@var{n}}
3964 Equivalent to @samp{vec_load_lanes@var{m}@var{n}}, with the memory
3965 and register operands reversed. That is, the instruction is
3969 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
3970 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
3971 for (i = 0; i < c; i++)
3972 operand0[j * c + i] = operand1[i][j];
3975 for a memory operand 0 and register operand 1.
3977 @cindex @code{vec_set@var{m}} instruction pattern
3978 @item @samp{vec_set@var{m}}
3979 Set given field in the vector value. Operand 0 is the vector to modify,
3980 operand 1 is new value of field and operand 2 specify the field index.
3982 @cindex @code{vec_extract@var{m}} instruction pattern
3983 @item @samp{vec_extract@var{m}}
3984 Extract given field from the vector value. Operand 1 is the vector, operand 2
3985 specify field index and operand 0 place to store value into.
3987 @cindex @code{vec_extract_even@var{m}} instruction pattern
3988 @item @samp{vec_extract_even@var{m}}
3989 Extract even elements from the input vectors (operand 1 and operand 2).
3990 The even elements of operand 2 are concatenated to the even elements of operand
3991 1 in their original order. The result is stored in operand 0.
3992 The output and input vectors should have the same modes.
3994 @cindex @code{vec_extract_odd@var{m}} instruction pattern
3995 @item @samp{vec_extract_odd@var{m}}
3996 Extract odd elements from the input vectors (operand 1 and operand 2).
3997 The odd elements of operand 2 are concatenated to the odd elements of operand
3998 1 in their original order. The result is stored in operand 0.
3999 The output and input vectors should have the same modes.
4001 @cindex @code{vec_interleave_high@var{m}} instruction pattern
4002 @item @samp{vec_interleave_high@var{m}}
4003 Merge high elements of the two input vectors into the output vector. The output
4004 and input vectors should have the same modes (@code{N} elements). The high
4005 @code{N/2} elements of the first input vector are interleaved with the high
4006 @code{N/2} elements of the second input vector.
4008 @cindex @code{vec_interleave_low@var{m}} instruction pattern
4009 @item @samp{vec_interleave_low@var{m}}
4010 Merge low elements of the two input vectors into the output vector. The output
4011 and input vectors should have the same modes (@code{N} elements). The low
4012 @code{N/2} elements of the first input vector are interleaved with the low
4013 @code{N/2} elements of the second input vector.
4015 @cindex @code{vec_init@var{m}} instruction pattern
4016 @item @samp{vec_init@var{m}}
4017 Initialize the vector to given values. Operand 0 is the vector to initialize
4018 and operand 1 is parallel containing values for individual fields.
4020 @cindex @code{vcond@var{m}@var{n}} instruction pattern
4021 @item @samp{vcond@var{m}@var{n}}
4022 Output a conditional vector move. Operand 0 is the destination to
4023 receive a combination of operand 1 and operand 2, which are of mode @var{m},
4024 dependent on the outcome of the predicate in operand 3 which is a
4025 vector comparison with operands of mode @var{n} in operands 4 and 5. The
4026 modes @var{m} and @var{n} should have the same size. Operand 0
4027 will be set to the value @var{op1} & @var{msk} | @var{op2} & ~@var{msk}
4028 where @var{msk} is computed by element-wise evaluation of the vector
4029 comparison with a truth value of all-ones and a false value of all-zeros.
4031 @cindex @code{vec_perm@var{m}} instruction pattern
4032 @item @samp{vec_perm@var{m}}
4033 Output a (variable) vector permutation. Operand 0 is the destination
4034 to receive elements from operand 1 and operand 2, which are of mode
4035 @var{m}. Operand 3 is the @dfn{selector}. It is an integral mode
4036 vector of the same width and number of elements as mode @var{m}.
4038 The input elements are numbered from 0 in operand 1 through
4039 @math{2*@var{N}-1} in operand 2. The elements of the selector must
4040 be computed modulo @math{2*@var{N}}. Note that if
4041 @code{rtx_equal_p(operand1, operand2)}, this can be implemented
4042 with just operand 1 and selector elements modulo @var{N}.
4044 In order to make things easy for a number of targets, if there is no
4045 @samp{vec_perm} pattern for mode @var{m}, but there is for mode @var{q}
4046 where @var{q} is a vector of @code{QImode} of the same width as @var{m},
4047 the middle-end will lower the mode @var{m} @code{VEC_PERM_EXPR} to
4050 @cindex @code{vec_perm_const@var{m}} instruction pattern
4051 @item @samp{vec_perm_const@var{m}}
4052 Like @samp{vec_perm} except that the permutation is a compile-time
4053 constant. That is, operand 3, the @dfn{selector}, is a @code{CONST_VECTOR}.
4055 Some targets cannot perform a permutation with a variable selector,
4056 but can efficiently perform a constant permutation. Further, the
4057 target hook @code{vec_perm_ok} is queried to determine if the
4058 specific constant permutation is available efficiently; the named
4059 pattern is never expanded without @code{vec_perm_ok} returning true.
4061 There is no need for a target to supply both @samp{vec_perm@var{m}}
4062 and @samp{vec_perm_const@var{m}} if the former can trivially implement
4063 the operation with, say, the vector constant loaded into a register.
4065 @cindex @code{push@var{m}1} instruction pattern
4066 @item @samp{push@var{m}1}
4067 Output a push instruction. Operand 0 is value to push. Used only when
4068 @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be
4069 missing and in such case an @code{mov} expander is used instead, with a
4070 @code{MEM} expression forming the push operation. The @code{mov} expander
4071 method is deprecated.
4073 @cindex @code{add@var{m}3} instruction pattern
4074 @item @samp{add@var{m}3}
4075 Add operand 2 and operand 1, storing the result in operand 0. All operands
4076 must have mode @var{m}. This can be used even on two-address machines, by
4077 means of constraints requiring operands 1 and 0 to be the same location.
4079 @cindex @code{ssadd@var{m}3} instruction pattern
4080 @cindex @code{usadd@var{m}3} instruction pattern
4081 @cindex @code{sub@var{m}3} instruction pattern
4082 @cindex @code{sssub@var{m}3} instruction pattern
4083 @cindex @code{ussub@var{m}3} instruction pattern
4084 @cindex @code{mul@var{m}3} instruction pattern
4085 @cindex @code{ssmul@var{m}3} instruction pattern
4086 @cindex @code{usmul@var{m}3} instruction pattern
4087 @cindex @code{div@var{m}3} instruction pattern
4088 @cindex @code{ssdiv@var{m}3} instruction pattern
4089 @cindex @code{udiv@var{m}3} instruction pattern
4090 @cindex @code{usdiv@var{m}3} instruction pattern
4091 @cindex @code{mod@var{m}3} instruction pattern
4092 @cindex @code{umod@var{m}3} instruction pattern
4093 @cindex @code{umin@var{m}3} instruction pattern
4094 @cindex @code{umax@var{m}3} instruction pattern
4095 @cindex @code{and@var{m}3} instruction pattern
4096 @cindex @code{ior@var{m}3} instruction pattern
4097 @cindex @code{xor@var{m}3} instruction pattern
4098 @item @samp{ssadd@var{m}3}, @samp{usadd@var{m}3}
4099 @item @samp{sub@var{m}3}, @samp{sssub@var{m}3}, @samp{ussub@var{m}3}
4100 @item @samp{mul@var{m}3}, @samp{ssmul@var{m}3}, @samp{usmul@var{m}3}
4101 @itemx @samp{div@var{m}3}, @samp{ssdiv@var{m}3}
4102 @itemx @samp{udiv@var{m}3}, @samp{usdiv@var{m}3}
4103 @itemx @samp{mod@var{m}3}, @samp{umod@var{m}3}
4104 @itemx @samp{umin@var{m}3}, @samp{umax@var{m}3}
4105 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
4106 Similar, for other arithmetic operations.
4108 @cindex @code{fma@var{m}4} instruction pattern
4109 @item @samp{fma@var{m}4}
4110 Multiply operand 2 and operand 1, then add operand 3, storing the
4111 result in operand 0. All operands must have mode @var{m}. This
4112 pattern is used to implement the @code{fma}, @code{fmaf}, and
4113 @code{fmal} builtin functions from the ISO C99 standard. The
4114 @code{fma} operation may produce different results than doing the
4115 multiply followed by the add if the machine does not perform a
4116 rounding step between the operations.
4118 @cindex @code{fms@var{m}4} instruction pattern
4119 @item @samp{fms@var{m}4}
4120 Like @code{fma@var{m}4}, except operand 3 subtracted from the
4121 product instead of added to the product. This is represented
4125 (fma:@var{m} @var{op1} @var{op2} (neg:@var{m} @var{op3}))
4128 @cindex @code{fnma@var{m}4} instruction pattern
4129 @item @samp{fnma@var{m}4}
4130 Like @code{fma@var{m}4} except that the intermediate product
4131 is negated before being added to operand 3. This is represented
4135 (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} @var{op3})
4138 @cindex @code{fnms@var{m}4} instruction pattern
4139 @item @samp{fnms@var{m}4}
4140 Like @code{fms@var{m}4} except that the intermediate product
4141 is negated before subtracting operand 3. This is represented
4145 (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} (neg:@var{m} @var{op3}))
4148 @cindex @code{min@var{m}3} instruction pattern
4149 @cindex @code{max@var{m}3} instruction pattern
4150 @item @samp{smin@var{m}3}, @samp{smax@var{m}3}
4151 Signed minimum and maximum operations. When used with floating point,
4152 if both operands are zeros, or if either operand is @code{NaN}, then
4153 it is unspecified which of the two operands is returned as the result.
4155 @cindex @code{reduc_smin_@var{m}} instruction pattern
4156 @cindex @code{reduc_smax_@var{m}} instruction pattern
4157 @item @samp{reduc_smin_@var{m}}, @samp{reduc_smax_@var{m}}
4158 Find the signed minimum/maximum of the elements of a vector. The vector is
4159 operand 1, and the scalar result is stored in the least significant bits of
4160 operand 0 (also a vector). The output and input vector should have the same
4163 @cindex @code{reduc_umin_@var{m}} instruction pattern
4164 @cindex @code{reduc_umax_@var{m}} instruction pattern
4165 @item @samp{reduc_umin_@var{m}}, @samp{reduc_umax_@var{m}}
4166 Find the unsigned minimum/maximum of the elements of a vector. The vector is
4167 operand 1, and the scalar result is stored in the least significant bits of
4168 operand 0 (also a vector). The output and input vector should have the same
4171 @cindex @code{reduc_splus_@var{m}} instruction pattern
4172 @item @samp{reduc_splus_@var{m}}
4173 Compute the sum of the signed elements of a vector. The vector is operand 1,
4174 and the scalar result is stored in the least significant bits of operand 0
4175 (also a vector). The output and input vector should have the same modes.
4177 @cindex @code{reduc_uplus_@var{m}} instruction pattern
4178 @item @samp{reduc_uplus_@var{m}}
4179 Compute the sum of the unsigned elements of a vector. The vector is operand 1,
4180 and the scalar result is stored in the least significant bits of operand 0
4181 (also a vector). The output and input vector should have the same modes.
4183 @cindex @code{sdot_prod@var{m}} instruction pattern
4184 @item @samp{sdot_prod@var{m}}
4185 @cindex @code{udot_prod@var{m}} instruction pattern
4186 @item @samp{udot_prod@var{m}}
4187 Compute the sum of the products of two signed/unsigned elements.
4188 Operand 1 and operand 2 are of the same mode. Their product, which is of a
4189 wider mode, is computed and added to operand 3. Operand 3 is of a mode equal or
4190 wider than the mode of the product. The result is placed in operand 0, which
4191 is of the same mode as operand 3.
4193 @cindex @code{ssum_widen@var{m3}} instruction pattern
4194 @item @samp{ssum_widen@var{m3}}
4195 @cindex @code{usum_widen@var{m3}} instruction pattern
4196 @item @samp{usum_widen@var{m3}}
4197 Operands 0 and 2 are of the same mode, which is wider than the mode of
4198 operand 1. Add operand 1 to operand 2 and place the widened result in
4199 operand 0. (This is used express accumulation of elements into an accumulator
4202 @cindex @code{vec_shl_@var{m}} instruction pattern
4203 @cindex @code{vec_shr_@var{m}} instruction pattern
4204 @item @samp{vec_shl_@var{m}}, @samp{vec_shr_@var{m}}
4205 Whole vector left/right shift in bits.
4206 Operand 1 is a vector to be shifted.
4207 Operand 2 is an integer shift amount in bits.
4208 Operand 0 is where the resulting shifted vector is stored.
4209 The output and input vectors should have the same modes.
4211 @cindex @code{vec_pack_trunc_@var{m}} instruction pattern
4212 @item @samp{vec_pack_trunc_@var{m}}
4213 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
4214 are vectors of the same mode having N integral or floating point elements
4215 of size S@. Operand 0 is the resulting vector in which 2*N elements of
4216 size N/2 are concatenated after narrowing them down using truncation.
4218 @cindex @code{vec_pack_ssat_@var{m}} instruction pattern
4219 @cindex @code{vec_pack_usat_@var{m}} instruction pattern
4220 @item @samp{vec_pack_ssat_@var{m}}, @samp{vec_pack_usat_@var{m}}
4221 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
4222 are vectors of the same mode having N integral elements of size S.
4223 Operand 0 is the resulting vector in which the elements of the two input
4224 vectors are concatenated after narrowing them down using signed/unsigned
4225 saturating arithmetic.
4227 @cindex @code{vec_pack_sfix_trunc_@var{m}} instruction pattern
4228 @cindex @code{vec_pack_ufix_trunc_@var{m}} instruction pattern
4229 @item @samp{vec_pack_sfix_trunc_@var{m}}, @samp{vec_pack_ufix_trunc_@var{m}}
4230 Narrow, convert to signed/unsigned integral type and merge the elements
4231 of two vectors. Operands 1 and 2 are vectors of the same mode having N
4232 floating point elements of size S@. Operand 0 is the resulting vector
4233 in which 2*N elements of size N/2 are concatenated.
4235 @cindex @code{vec_unpacks_hi_@var{m}} instruction pattern
4236 @cindex @code{vec_unpacks_lo_@var{m}} instruction pattern
4237 @item @samp{vec_unpacks_hi_@var{m}}, @samp{vec_unpacks_lo_@var{m}}
4238 Extract and widen (promote) the high/low part of a vector of signed
4239 integral or floating point elements. The input vector (operand 1) has N
4240 elements of size S@. Widen (promote) the high/low elements of the vector
4241 using signed or floating point extension and place the resulting N/2
4242 values of size 2*S in the output vector (operand 0).
4244 @cindex @code{vec_unpacku_hi_@var{m}} instruction pattern
4245 @cindex @code{vec_unpacku_lo_@var{m}} instruction pattern
4246 @item @samp{vec_unpacku_hi_@var{m}}, @samp{vec_unpacku_lo_@var{m}}
4247 Extract and widen (promote) the high/low part of a vector of unsigned
4248 integral elements. The input vector (operand 1) has N elements of size S.
4249 Widen (promote) the high/low elements of the vector using zero extension and
4250 place the resulting N/2 values of size 2*S in the output vector (operand 0).
4252 @cindex @code{vec_unpacks_float_hi_@var{m}} instruction pattern
4253 @cindex @code{vec_unpacks_float_lo_@var{m}} instruction pattern
4254 @cindex @code{vec_unpacku_float_hi_@var{m}} instruction pattern
4255 @cindex @code{vec_unpacku_float_lo_@var{m}} instruction pattern
4256 @item @samp{vec_unpacks_float_hi_@var{m}}, @samp{vec_unpacks_float_lo_@var{m}}
4257 @itemx @samp{vec_unpacku_float_hi_@var{m}}, @samp{vec_unpacku_float_lo_@var{m}}
4258 Extract, convert to floating point type and widen the high/low part of a
4259 vector of signed/unsigned integral elements. The input vector (operand 1)
4260 has N elements of size S@. Convert the high/low elements of the vector using
4261 floating point conversion and place the resulting N/2 values of size 2*S in
4262 the output vector (operand 0).
4264 @cindex @code{vec_widen_umult_hi_@var{m}} instruction pattern
4265 @cindex @code{vec_widen_umult_lo__@var{m}} instruction pattern
4266 @cindex @code{vec_widen_smult_hi_@var{m}} instruction pattern
4267 @cindex @code{vec_widen_smult_lo_@var{m}} instruction pattern
4268 @item @samp{vec_widen_umult_hi_@var{m}}, @samp{vec_widen_umult_lo_@var{m}}
4269 @itemx @samp{vec_widen_smult_hi_@var{m}}, @samp{vec_widen_smult_lo_@var{m}}
4270 Signed/Unsigned widening multiplication. The two inputs (operands 1 and 2)
4271 are vectors with N signed/unsigned elements of size S@. Multiply the high/low
4272 elements of the two vectors, and put the N/2 products of size 2*S in the
4273 output vector (operand 0).
4275 @cindex @code{mulhisi3} instruction pattern
4276 @item @samp{mulhisi3}
4277 Multiply operands 1 and 2, which have mode @code{HImode}, and store
4278 a @code{SImode} product in operand 0.
4280 @cindex @code{mulqihi3} instruction pattern
4281 @cindex @code{mulsidi3} instruction pattern
4282 @item @samp{mulqihi3}, @samp{mulsidi3}
4283 Similar widening-multiplication instructions of other widths.
4285 @cindex @code{umulqihi3} instruction pattern
4286 @cindex @code{umulhisi3} instruction pattern
4287 @cindex @code{umulsidi3} instruction pattern
4288 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
4289 Similar widening-multiplication instructions that do unsigned
4292 @cindex @code{usmulqihi3} instruction pattern
4293 @cindex @code{usmulhisi3} instruction pattern
4294 @cindex @code{usmulsidi3} instruction pattern
4295 @item @samp{usmulqihi3}, @samp{usmulhisi3}, @samp{usmulsidi3}
4296 Similar widening-multiplication instructions that interpret the first
4297 operand as unsigned and the second operand as signed, then do a signed
4300 @cindex @code{smul@var{m}3_highpart} instruction pattern
4301 @item @samp{smul@var{m}3_highpart}
4302 Perform a signed multiplication of operands 1 and 2, which have mode
4303 @var{m}, and store the most significant half of the product in operand 0.
4304 The least significant half of the product is discarded.
4306 @cindex @code{umul@var{m}3_highpart} instruction pattern
4307 @item @samp{umul@var{m}3_highpart}
4308 Similar, but the multiplication is unsigned.
4310 @cindex @code{madd@var{m}@var{n}4} instruction pattern
4311 @item @samp{madd@var{m}@var{n}4}
4312 Multiply operands 1 and 2, sign-extend them to mode @var{n}, add
4313 operand 3, and store the result in operand 0. Operands 1 and 2
4314 have mode @var{m} and operands 0 and 3 have mode @var{n}.
4315 Both modes must be integer or fixed-point modes and @var{n} must be twice
4316 the size of @var{m}.
4318 In other words, @code{madd@var{m}@var{n}4} is like
4319 @code{mul@var{m}@var{n}3} except that it also adds operand 3.
4321 These instructions are not allowed to @code{FAIL}.
4323 @cindex @code{umadd@var{m}@var{n}4} instruction pattern
4324 @item @samp{umadd@var{m}@var{n}4}
4325 Like @code{madd@var{m}@var{n}4}, but zero-extend the multiplication
4326 operands instead of sign-extending them.
4328 @cindex @code{ssmadd@var{m}@var{n}4} instruction pattern
4329 @item @samp{ssmadd@var{m}@var{n}4}
4330 Like @code{madd@var{m}@var{n}4}, but all involved operations must be
4333 @cindex @code{usmadd@var{m}@var{n}4} instruction pattern
4334 @item @samp{usmadd@var{m}@var{n}4}
4335 Like @code{umadd@var{m}@var{n}4}, but all involved operations must be
4336 unsigned-saturating.
4338 @cindex @code{msub@var{m}@var{n}4} instruction pattern
4339 @item @samp{msub@var{m}@var{n}4}
4340 Multiply operands 1 and 2, sign-extend them to mode @var{n}, subtract the
4341 result from operand 3, and store the result in operand 0. Operands 1 and 2
4342 have mode @var{m} and operands 0 and 3 have mode @var{n}.
4343 Both modes must be integer or fixed-point modes and @var{n} must be twice
4344 the size of @var{m}.
4346 In other words, @code{msub@var{m}@var{n}4} is like
4347 @code{mul@var{m}@var{n}3} except that it also subtracts the result
4350 These instructions are not allowed to @code{FAIL}.
4352 @cindex @code{umsub@var{m}@var{n}4} instruction pattern
4353 @item @samp{umsub@var{m}@var{n}4}
4354 Like @code{msub@var{m}@var{n}4}, but zero-extend the multiplication
4355 operands instead of sign-extending them.
4357 @cindex @code{ssmsub@var{m}@var{n}4} instruction pattern
4358 @item @samp{ssmsub@var{m}@var{n}4}
4359 Like @code{msub@var{m}@var{n}4}, but all involved operations must be
4362 @cindex @code{usmsub@var{m}@var{n}4} instruction pattern
4363 @item @samp{usmsub@var{m}@var{n}4}
4364 Like @code{umsub@var{m}@var{n}4}, but all involved operations must be
4365 unsigned-saturating.
4367 @cindex @code{divmod@var{m}4} instruction pattern
4368 @item @samp{divmod@var{m}4}
4369 Signed division that produces both a quotient and a remainder.
4370 Operand 1 is divided by operand 2 to produce a quotient stored
4371 in operand 0 and a remainder stored in operand 3.
4373 For machines with an instruction that produces both a quotient and a
4374 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
4375 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
4376 allows optimization in the relatively common case when both the quotient
4377 and remainder are computed.
4379 If an instruction that just produces a quotient or just a remainder
4380 exists and is more efficient than the instruction that produces both,
4381 write the output routine of @samp{divmod@var{m}4} to call
4382 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
4383 quotient or remainder and generate the appropriate instruction.
4385 @cindex @code{udivmod@var{m}4} instruction pattern
4386 @item @samp{udivmod@var{m}4}
4387 Similar, but does unsigned division.
4389 @anchor{shift patterns}
4390 @cindex @code{ashl@var{m}3} instruction pattern
4391 @cindex @code{ssashl@var{m}3} instruction pattern
4392 @cindex @code{usashl@var{m}3} instruction pattern
4393 @item @samp{ashl@var{m}3}, @samp{ssashl@var{m}3}, @samp{usashl@var{m}3}
4394 Arithmetic-shift operand 1 left by a number of bits specified by operand
4395 2, and store the result in operand 0. Here @var{m} is the mode of
4396 operand 0 and operand 1; operand 2's mode is specified by the
4397 instruction pattern, and the compiler will convert the operand to that
4398 mode before generating the instruction. The meaning of out-of-range shift
4399 counts can optionally be specified by @code{TARGET_SHIFT_TRUNCATION_MASK}.
4400 @xref{TARGET_SHIFT_TRUNCATION_MASK}. Operand 2 is always a scalar type.
4402 @cindex @code{ashr@var{m}3} instruction pattern
4403 @cindex @code{lshr@var{m}3} instruction pattern
4404 @cindex @code{rotl@var{m}3} instruction pattern
4405 @cindex @code{rotr@var{m}3} instruction pattern
4406 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
4407 Other shift and rotate instructions, analogous to the
4408 @code{ashl@var{m}3} instructions. Operand 2 is always a scalar type.
4410 @cindex @code{vashl@var{m}3} instruction pattern
4411 @cindex @code{vashr@var{m}3} instruction pattern
4412 @cindex @code{vlshr@var{m}3} instruction pattern
4413 @cindex @code{vrotl@var{m}3} instruction pattern
4414 @cindex @code{vrotr@var{m}3} instruction pattern
4415 @item @samp{vashl@var{m}3}, @samp{vashr@var{m}3}, @samp{vlshr@var{m}3}, @samp{vrotl@var{m}3}, @samp{vrotr@var{m}3}
4416 Vector shift and rotate instructions that take vectors as operand 2
4417 instead of a scalar type.
4419 @cindex @code{neg@var{m}2} instruction pattern
4420 @cindex @code{ssneg@var{m}2} instruction pattern
4421 @cindex @code{usneg@var{m}2} instruction pattern
4422 @item @samp{neg@var{m}2}, @samp{ssneg@var{m}2}, @samp{usneg@var{m}2}
4423 Negate operand 1 and store the result in operand 0.
4425 @cindex @code{abs@var{m}2} instruction pattern
4426 @item @samp{abs@var{m}2}
4427 Store the absolute value of operand 1 into operand 0.
4429 @cindex @code{sqrt@var{m}2} instruction pattern
4430 @item @samp{sqrt@var{m}2}
4431 Store the square root of operand 1 into operand 0.
4433 The @code{sqrt} built-in function of C always uses the mode which
4434 corresponds to the C data type @code{double} and the @code{sqrtf}
4435 built-in function uses the mode which corresponds to the C data
4438 @cindex @code{fmod@var{m}3} instruction pattern
4439 @item @samp{fmod@var{m}3}
4440 Store the remainder of dividing operand 1 by operand 2 into
4441 operand 0, rounded towards zero to an integer.
4443 The @code{fmod} built-in function of C always uses the mode which
4444 corresponds to the C data type @code{double} and the @code{fmodf}
4445 built-in function uses the mode which corresponds to the C data
4448 @cindex @code{remainder@var{m}3} instruction pattern
4449 @item @samp{remainder@var{m}3}
4450 Store the remainder of dividing operand 1 by operand 2 into
4451 operand 0, rounded to the nearest integer.
4453 The @code{remainder} built-in function of C always uses the mode
4454 which corresponds to the C data type @code{double} and the
4455 @code{remainderf} built-in function uses the mode which corresponds
4456 to the C data type @code{float}.
4458 @cindex @code{cos@var{m}2} instruction pattern
4459 @item @samp{cos@var{m}2}
4460 Store the cosine of operand 1 into operand 0.
4462 The @code{cos} built-in function of C always uses the mode which
4463 corresponds to the C data type @code{double} and the @code{cosf}
4464 built-in function uses the mode which corresponds to the C data
4467 @cindex @code{sin@var{m}2} instruction pattern
4468 @item @samp{sin@var{m}2}
4469 Store the sine of operand 1 into operand 0.
4471 The @code{sin} built-in function of C always uses the mode which
4472 corresponds to the C data type @code{double} and the @code{sinf}
4473 built-in function uses the mode which corresponds to the C data
4476 @cindex @code{exp@var{m}2} instruction pattern
4477 @item @samp{exp@var{m}2}
4478 Store the exponential of operand 1 into operand 0.
4480 The @code{exp} built-in function of C always uses the mode which
4481 corresponds to the C data type @code{double} and the @code{expf}
4482 built-in function uses the mode which corresponds to the C data
4485 @cindex @code{log@var{m}2} instruction pattern
4486 @item @samp{log@var{m}2}
4487 Store the natural logarithm of operand 1 into operand 0.
4489 The @code{log} built-in function of C always uses the mode which
4490 corresponds to the C data type @code{double} and the @code{logf}
4491 built-in function uses the mode which corresponds to the C data
4494 @cindex @code{pow@var{m}3} instruction pattern
4495 @item @samp{pow@var{m}3}
4496 Store the value of operand 1 raised to the exponent operand 2
4499 The @code{pow} built-in function of C always uses the mode which
4500 corresponds to the C data type @code{double} and the @code{powf}
4501 built-in function uses the mode which corresponds to the C data
4504 @cindex @code{atan2@var{m}3} instruction pattern
4505 @item @samp{atan2@var{m}3}
4506 Store the arc tangent (inverse tangent) of operand 1 divided by
4507 operand 2 into operand 0, using the signs of both arguments to
4508 determine the quadrant of the result.
4510 The @code{atan2} built-in function of C always uses the mode which
4511 corresponds to the C data type @code{double} and the @code{atan2f}
4512 built-in function uses the mode which corresponds to the C data
4515 @cindex @code{floor@var{m}2} instruction pattern
4516 @item @samp{floor@var{m}2}
4517 Store the largest integral value not greater than argument.
4519 The @code{floor} built-in function of C always uses the mode which
4520 corresponds to the C data type @code{double} and the @code{floorf}
4521 built-in function uses the mode which corresponds to the C data
4524 @cindex @code{btrunc@var{m}2} instruction pattern
4525 @item @samp{btrunc@var{m}2}
4526 Store the argument rounded to integer towards zero.
4528 The @code{trunc} built-in function of C always uses the mode which
4529 corresponds to the C data type @code{double} and the @code{truncf}
4530 built-in function uses the mode which corresponds to the C data
4533 @cindex @code{round@var{m}2} instruction pattern
4534 @item @samp{round@var{m}2}
4535 Store the argument rounded to integer away from zero.
4537 The @code{round} built-in function of C always uses the mode which
4538 corresponds to the C data type @code{double} and the @code{roundf}
4539 built-in function uses the mode which corresponds to the C data
4542 @cindex @code{ceil@var{m}2} instruction pattern
4543 @item @samp{ceil@var{m}2}
4544 Store the argument rounded to integer away from zero.
4546 The @code{ceil} built-in function of C always uses the mode which
4547 corresponds to the C data type @code{double} and the @code{ceilf}
4548 built-in function uses the mode which corresponds to the C data
4551 @cindex @code{nearbyint@var{m}2} instruction pattern
4552 @item @samp{nearbyint@var{m}2}
4553 Store the argument rounded according to the default rounding mode
4555 The @code{nearbyint} built-in function of C always uses the mode which
4556 corresponds to the C data type @code{double} and the @code{nearbyintf}
4557 built-in function uses the mode which corresponds to the C data
4560 @cindex @code{rint@var{m}2} instruction pattern
4561 @item @samp{rint@var{m}2}
4562 Store the argument rounded according to the default rounding mode and
4563 raise the inexact exception when the result differs in value from
4566 The @code{rint} built-in function of C always uses the mode which
4567 corresponds to the C data type @code{double} and the @code{rintf}
4568 built-in function uses the mode which corresponds to the C data
4571 @cindex @code{lrint@var{m}@var{n}2}
4572 @item @samp{lrint@var{m}@var{n}2}
4573 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4574 point mode @var{n} as a signed number according to the current
4575 rounding mode and store in operand 0 (which has mode @var{n}).
4577 @cindex @code{lround@var{m}@var{n}2}
4578 @item @samp{lround@var{m}@var{n}2}
4579 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4580 point mode @var{n} as a signed number rounding to nearest and away
4581 from zero and store in operand 0 (which has mode @var{n}).
4583 @cindex @code{lfloor@var{m}@var{n}2}
4584 @item @samp{lfloor@var{m}@var{n}2}
4585 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4586 point mode @var{n} as a signed number rounding down and store in
4587 operand 0 (which has mode @var{n}).
4589 @cindex @code{lceil@var{m}@var{n}2}
4590 @item @samp{lceil@var{m}@var{n}2}
4591 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4592 point mode @var{n} as a signed number rounding up and store in
4593 operand 0 (which has mode @var{n}).
4595 @cindex @code{copysign@var{m}3} instruction pattern
4596 @item @samp{copysign@var{m}3}
4597 Store a value with the magnitude of operand 1 and the sign of operand
4600 The @code{copysign} built-in function of C always uses the mode which
4601 corresponds to the C data type @code{double} and the @code{copysignf}
4602 built-in function uses the mode which corresponds to the C data
4605 @cindex @code{ffs@var{m}2} instruction pattern
4606 @item @samp{ffs@var{m}2}
4607 Store into operand 0 one plus the index of the least significant 1-bit
4608 of operand 1. If operand 1 is zero, store zero. @var{m} is the mode
4609 of operand 0; operand 1's mode is specified by the instruction
4610 pattern, and the compiler will convert the operand to that mode before
4611 generating the instruction.
4613 The @code{ffs} built-in function of C always uses the mode which
4614 corresponds to the C data type @code{int}.
4616 @cindex @code{clz@var{m}2} instruction pattern
4617 @item @samp{clz@var{m}2}
4618 Store into operand 0 the number of leading 0-bits in @var{x}, starting
4619 at the most significant bit position. If @var{x} is 0, the
4620 @code{CLZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
4621 the result is undefined or has a useful value.
4622 @var{m} is the mode of operand 0; operand 1's mode is
4623 specified by the instruction pattern, and the compiler will convert the
4624 operand to that mode before generating the instruction.
4626 @cindex @code{ctz@var{m}2} instruction pattern
4627 @item @samp{ctz@var{m}2}
4628 Store into operand 0 the number of trailing 0-bits in @var{x}, starting
4629 at the least significant bit position. If @var{x} is 0, the
4630 @code{CTZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
4631 the result is undefined or has a useful value.
4632 @var{m} is the mode of operand 0; operand 1's mode is
4633 specified by the instruction pattern, and the compiler will convert the
4634 operand to that mode before generating the instruction.
4636 @cindex @code{popcount@var{m}2} instruction pattern
4637 @item @samp{popcount@var{m}2}
4638 Store into operand 0 the number of 1-bits in @var{x}. @var{m} is the
4639 mode of operand 0; operand 1's mode is specified by the instruction
4640 pattern, and the compiler will convert the operand to that mode before
4641 generating the instruction.
4643 @cindex @code{parity@var{m}2} instruction pattern
4644 @item @samp{parity@var{m}2}
4645 Store into operand 0 the parity of @var{x}, i.e.@: the number of 1-bits
4646 in @var{x} modulo 2. @var{m} is the mode of operand 0; operand 1's mode
4647 is specified by the instruction pattern, and the compiler will convert
4648 the operand to that mode before generating the instruction.
4650 @cindex @code{one_cmpl@var{m}2} instruction pattern
4651 @item @samp{one_cmpl@var{m}2}
4652 Store the bitwise-complement of operand 1 into operand 0.
4654 @cindex @code{movmem@var{m}} instruction pattern
4655 @item @samp{movmem@var{m}}
4656 Block move instruction. The destination and source blocks of memory
4657 are the first two operands, and both are @code{mem:BLK}s with an
4658 address in mode @code{Pmode}.
4660 The number of bytes to move is the third operand, in mode @var{m}.
4661 Usually, you specify @code{word_mode} for @var{m}. However, if you can
4662 generate better code knowing the range of valid lengths is smaller than
4663 those representable in a full word, you should provide a pattern with a
4664 mode corresponding to the range of values you can handle efficiently
4665 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
4666 that appear negative) and also a pattern with @code{word_mode}.
4668 The fourth operand is the known shared alignment of the source and
4669 destination, in the form of a @code{const_int} rtx. Thus, if the
4670 compiler knows that both source and destination are word-aligned,
4671 it may provide the value 4 for this operand.
4673 Optional operands 5 and 6 specify expected alignment and size of block
4674 respectively. The expected alignment differs from alignment in operand 4
4675 in a way that the blocks are not required to be aligned according to it in
4676 all cases. This expected alignment is also in bytes, just like operand 4.
4677 Expected size, when unknown, is set to @code{(const_int -1)}.
4679 Descriptions of multiple @code{movmem@var{m}} patterns can only be
4680 beneficial if the patterns for smaller modes have fewer restrictions
4681 on their first, second and fourth operands. Note that the mode @var{m}
4682 in @code{movmem@var{m}} does not impose any restriction on the mode of
4683 individually moved data units in the block.
4685 These patterns need not give special consideration to the possibility
4686 that the source and destination strings might overlap.
4688 @cindex @code{movstr} instruction pattern
4690 String copy instruction, with @code{stpcpy} semantics. Operand 0 is
4691 an output operand in mode @code{Pmode}. The addresses of the
4692 destination and source strings are operands 1 and 2, and both are
4693 @code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of
4694 the expansion of this pattern should store in operand 0 the address in
4695 which the @code{NUL} terminator was stored in the destination string.
4697 @cindex @code{setmem@var{m}} instruction pattern
4698 @item @samp{setmem@var{m}}
4699 Block set instruction. The destination string is the first operand,
4700 given as a @code{mem:BLK} whose address is in mode @code{Pmode}. The
4701 number of bytes to set is the second operand, in mode @var{m}. The value to
4702 initialize the memory with is the third operand. Targets that only support the
4703 clearing of memory should reject any value that is not the constant 0. See
4704 @samp{movmem@var{m}} for a discussion of the choice of mode.
4706 The fourth operand is the known alignment of the destination, in the form
4707 of a @code{const_int} rtx. Thus, if the compiler knows that the
4708 destination is word-aligned, it may provide the value 4 for this
4711 Optional operands 5 and 6 specify expected alignment and size of block
4712 respectively. The expected alignment differs from alignment in operand 4
4713 in a way that the blocks are not required to be aligned according to it in
4714 all cases. This expected alignment is also in bytes, just like operand 4.
4715 Expected size, when unknown, is set to @code{(const_int -1)}.
4717 The use for multiple @code{setmem@var{m}} is as for @code{movmem@var{m}}.
4719 @cindex @code{cmpstrn@var{m}} instruction pattern
4720 @item @samp{cmpstrn@var{m}}
4721 String compare instruction, with five operands. Operand 0 is the output;
4722 it has mode @var{m}. The remaining four operands are like the operands
4723 of @samp{movmem@var{m}}. The two memory blocks specified are compared
4724 byte by byte in lexicographic order starting at the beginning of each
4725 string. The instruction is not allowed to prefetch more than one byte
4726 at a time since either string may end in the first byte and reading past
4727 that may access an invalid page or segment and cause a fault. The
4728 comparison terminates early if the fetched bytes are different or if
4729 they are equal to zero. The effect of the instruction is to store a
4730 value in operand 0 whose sign indicates the result of the comparison.
4732 @cindex @code{cmpstr@var{m}} instruction pattern
4733 @item @samp{cmpstr@var{m}}
4734 String compare instruction, without known maximum length. Operand 0 is the
4735 output; it has mode @var{m}. The second and third operand are the blocks of
4736 memory to be compared; both are @code{mem:BLK} with an address in mode
4739 The fourth operand is the known shared alignment of the source and
4740 destination, in the form of a @code{const_int} rtx. Thus, if the
4741 compiler knows that both source and destination are word-aligned,
4742 it may provide the value 4 for this operand.
4744 The two memory blocks specified are compared byte by byte in lexicographic
4745 order starting at the beginning of each string. The instruction is not allowed
4746 to prefetch more than one byte at a time since either string may end in the
4747 first byte and reading past that may access an invalid page or segment and
4748 cause a fault. The comparison will terminate when the fetched bytes
4749 are different or if they are equal to zero. The effect of the
4750 instruction is to store a value in operand 0 whose sign indicates the
4751 result of the comparison.
4753 @cindex @code{cmpmem@var{m}} instruction pattern
4754 @item @samp{cmpmem@var{m}}
4755 Block compare instruction, with five operands like the operands
4756 of @samp{cmpstr@var{m}}. The two memory blocks specified are compared
4757 byte by byte in lexicographic order starting at the beginning of each
4758 block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch
4759 any bytes in the two memory blocks. Also unlike @samp{cmpstr@var{m}}
4760 the comparison will not stop if both bytes are zero. The effect of
4761 the instruction is to store a value in operand 0 whose sign indicates
4762 the result of the comparison.
4764 @cindex @code{strlen@var{m}} instruction pattern
4765 @item @samp{strlen@var{m}}
4766 Compute the length of a string, with three operands.
4767 Operand 0 is the result (of mode @var{m}), operand 1 is
4768 a @code{mem} referring to the first character of the string,
4769 operand 2 is the character to search for (normally zero),
4770 and operand 3 is a constant describing the known alignment
4771 of the beginning of the string.
4773 @cindex @code{float@var{m}@var{n}2} instruction pattern
4774 @item @samp{float@var{m}@var{n}2}
4775 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
4776 floating point mode @var{n} and store in operand 0 (which has mode
4779 @cindex @code{floatuns@var{m}@var{n}2} instruction pattern
4780 @item @samp{floatuns@var{m}@var{n}2}
4781 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
4782 to floating point mode @var{n} and store in operand 0 (which has mode
4785 @cindex @code{fix@var{m}@var{n}2} instruction pattern
4786 @item @samp{fix@var{m}@var{n}2}
4787 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4788 point mode @var{n} as a signed number and store in operand 0 (which
4789 has mode @var{n}). This instruction's result is defined only when
4790 the value of operand 1 is an integer.
4792 If the machine description defines this pattern, it also needs to
4793 define the @code{ftrunc} pattern.
4795 @cindex @code{fixuns@var{m}@var{n}2} instruction pattern
4796 @item @samp{fixuns@var{m}@var{n}2}
4797 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4798 point mode @var{n} as an unsigned number and store in operand 0 (which
4799 has mode @var{n}). This instruction's result is defined only when the
4800 value of operand 1 is an integer.
4802 @cindex @code{ftrunc@var{m}2} instruction pattern
4803 @item @samp{ftrunc@var{m}2}
4804 Convert operand 1 (valid for floating point mode @var{m}) to an
4805 integer value, still represented in floating point mode @var{m}, and
4806 store it in operand 0 (valid for floating point mode @var{m}).
4808 @cindex @code{fix_trunc@var{m}@var{n}2} instruction pattern
4809 @item @samp{fix_trunc@var{m}@var{n}2}
4810 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
4811 of mode @var{m} by converting the value to an integer.
4813 @cindex @code{fixuns_trunc@var{m}@var{n}2} instruction pattern
4814 @item @samp{fixuns_trunc@var{m}@var{n}2}
4815 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
4816 value of mode @var{m} by converting the value to an integer.
4818 @cindex @code{trunc@var{m}@var{n}2} instruction pattern
4819 @item @samp{trunc@var{m}@var{n}2}
4820 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
4821 store in operand 0 (which has mode @var{n}). Both modes must be fixed
4822 point or both floating point.
4824 @cindex @code{extend@var{m}@var{n}2} instruction pattern
4825 @item @samp{extend@var{m}@var{n}2}
4826 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
4827 store in operand 0 (which has mode @var{n}). Both modes must be fixed
4828 point or both floating point.
4830 @cindex @code{zero_extend@var{m}@var{n}2} instruction pattern
4831 @item @samp{zero_extend@var{m}@var{n}2}
4832 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
4833 store in operand 0 (which has mode @var{n}). Both modes must be fixed
4836 @cindex @code{fract@var{m}@var{n}2} instruction pattern
4837 @item @samp{fract@var{m}@var{n}2}
4838 Convert operand 1 of mode @var{m} to mode @var{n} and store in
4839 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
4840 could be fixed-point to fixed-point, signed integer to fixed-point,
4841 fixed-point to signed integer, floating-point to fixed-point,
4842 or fixed-point to floating-point.
4843 When overflows or underflows happen, the results are undefined.
4845 @cindex @code{satfract@var{m}@var{n}2} instruction pattern
4846 @item @samp{satfract@var{m}@var{n}2}
4847 Convert operand 1 of mode @var{m} to mode @var{n} and store in
4848 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
4849 could be fixed-point to fixed-point, signed integer to fixed-point,
4850 or floating-point to fixed-point.
4851 When overflows or underflows happen, the instruction saturates the
4852 results to the maximum or the minimum.
4854 @cindex @code{fractuns@var{m}@var{n}2} instruction pattern
4855 @item @samp{fractuns@var{m}@var{n}2}
4856 Convert operand 1 of mode @var{m} to mode @var{n} and store in
4857 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
4858 could be unsigned integer to fixed-point, or
4859 fixed-point to unsigned integer.
4860 When overflows or underflows happen, the results are undefined.
4862 @cindex @code{satfractuns@var{m}@var{n}2} instruction pattern
4863 @item @samp{satfractuns@var{m}@var{n}2}
4864 Convert unsigned integer operand 1 of mode @var{m} to fixed-point mode
4865 @var{n} and store in operand 0 (which has mode @var{n}).
4866 When overflows or underflows happen, the instruction saturates the
4867 results to the maximum or the minimum.
4869 @cindex @code{extv} instruction pattern
4871 Extract a bit-field from operand 1 (a register or memory operand), where
4872 operand 2 specifies the width in bits and operand 3 the starting bit,
4873 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
4874 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
4875 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
4876 be valid for @code{word_mode}.
4878 The RTL generation pass generates this instruction only with constants
4879 for operands 2 and 3 and the constant is never zero for operand 2.
4881 The bit-field value is sign-extended to a full word integer
4882 before it is stored in operand 0.
4884 @cindex @code{extzv} instruction pattern
4886 Like @samp{extv} except that the bit-field value is zero-extended.
4888 @cindex @code{insv} instruction pattern
4890 Store operand 3 (which must be valid for @code{word_mode}) into a
4891 bit-field in operand 0, where operand 1 specifies the width in bits and
4892 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
4893 @code{word_mode}; often @code{word_mode} is allowed only for registers.
4894 Operands 1 and 2 must be valid for @code{word_mode}.
4896 The RTL generation pass generates this instruction only with constants
4897 for operands 1 and 2 and the constant is never zero for operand 1.
4899 @cindex @code{mov@var{mode}cc} instruction pattern
4900 @item @samp{mov@var{mode}cc}
4901 Conditionally move operand 2 or operand 3 into operand 0 according to the
4902 comparison in operand 1. If the comparison is true, operand 2 is moved
4903 into operand 0, otherwise operand 3 is moved.
4905 The mode of the operands being compared need not be the same as the operands
4906 being moved. Some machines, sparc64 for example, have instructions that
4907 conditionally move an integer value based on the floating point condition
4908 codes and vice versa.
4910 If the machine does not have conditional move instructions, do not
4911 define these patterns.
4913 @cindex @code{add@var{mode}cc} instruction pattern
4914 @item @samp{add@var{mode}cc}
4915 Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally
4916 move operand 2 or (operands 2 + operand 3) into operand 0 according to the
4917 comparison in operand 1. If the comparison is true, operand 2 is moved into
4918 operand 0, otherwise (operand 2 + operand 3) is moved.
4920 @cindex @code{cstore@var{mode}4} instruction pattern
4921 @item @samp{cstore@var{mode}4}
4922 Store zero or nonzero in operand 0 according to whether a comparison
4923 is true. Operand 1 is a comparison operator. Operand 2 and operand 3
4924 are the first and second operand of the comparison, respectively.
4925 You specify the mode that operand 0 must have when you write the
4926 @code{match_operand} expression. The compiler automatically sees which
4927 mode you have used and supplies an operand of that mode.
4929 The value stored for a true condition must have 1 as its low bit, or
4930 else must be negative. Otherwise the instruction is not suitable and
4931 you should omit it from the machine description. You describe to the
4932 compiler exactly which value is stored by defining the macro
4933 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
4934 found that can be used for all the possible comparison operators, you
4935 should pick one and use a @code{define_expand} to map all results
4936 onto the one you chose.
4938 These operations may @code{FAIL}, but should do so only in relatively
4939 uncommon cases; if they would @code{FAIL} for common cases involving
4940 integer comparisons, it is best to restrict the predicates to not
4941 allow these operands. Likewise if a given comparison operator will
4942 always fail, independent of the operands (for floating-point modes, the
4943 @code{ordered_comparison_operator} predicate is often useful in this case).
4945 If this pattern is omitted, the compiler will generate a conditional
4946 branch---for example, it may copy a constant one to the target and branching
4947 around an assignment of zero to the target---or a libcall. If the predicate
4948 for operand 1 only rejects some operators, it will also try reordering the
4949 operands and/or inverting the result value (e.g.@: by an exclusive OR).
4950 These possibilities could be cheaper or equivalent to the instructions
4951 used for the @samp{cstore@var{mode}4} pattern followed by those required
4952 to convert a positive result from @code{STORE_FLAG_VALUE} to 1; in this
4953 case, you can and should make operand 1's predicate reject some operators
4954 in the @samp{cstore@var{mode}4} pattern, or remove the pattern altogether
4955 from the machine description.
4957 @cindex @code{cbranch@var{mode}4} instruction pattern
4958 @item @samp{cbranch@var{mode}4}
4959 Conditional branch instruction combined with a compare instruction.
4960 Operand 0 is a comparison operator. Operand 1 and operand 2 are the
4961 first and second operands of the comparison, respectively. Operand 3
4962 is a @code{label_ref} that refers to the label to jump to.
4964 @cindex @code{jump} instruction pattern
4966 A jump inside a function; an unconditional branch. Operand 0 is the
4967 @code{label_ref} of the label to jump to. This pattern name is mandatory
4970 @cindex @code{call} instruction pattern
4972 Subroutine call instruction returning no value. Operand 0 is the
4973 function to call; operand 1 is the number of bytes of arguments pushed
4974 as a @code{const_int}; operand 2 is the number of registers used as
4977 On most machines, operand 2 is not actually stored into the RTL
4978 pattern. It is supplied for the sake of some RISC machines which need
4979 to put this information into the assembler code; they can put it in
4980 the RTL instead of operand 1.
4982 Operand 0 should be a @code{mem} RTX whose address is the address of the
4983 function. Note, however, that this address can be a @code{symbol_ref}
4984 expression even if it would not be a legitimate memory address on the
4985 target machine. If it is also not a valid argument for a call
4986 instruction, the pattern for this operation should be a
4987 @code{define_expand} (@pxref{Expander Definitions}) that places the
4988 address into a register and uses that register in the call instruction.
4990 @cindex @code{call_value} instruction pattern
4991 @item @samp{call_value}
4992 Subroutine call instruction returning a value. Operand 0 is the hard
4993 register in which the value is returned. There are three more
4994 operands, the same as the three operands of the @samp{call}
4995 instruction (but with numbers increased by one).
4997 Subroutines that return @code{BLKmode} objects use the @samp{call}
5000 @cindex @code{call_pop} instruction pattern
5001 @cindex @code{call_value_pop} instruction pattern
5002 @item @samp{call_pop}, @samp{call_value_pop}
5003 Similar to @samp{call} and @samp{call_value}, except used if defined and
5004 if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel}
5005 that contains both the function call and a @code{set} to indicate the
5006 adjustment made to the frame pointer.
5008 For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these
5009 patterns increases the number of functions for which the frame pointer
5010 can be eliminated, if desired.
5012 @cindex @code{untyped_call} instruction pattern
5013 @item @samp{untyped_call}
5014 Subroutine call instruction returning a value of any type. Operand 0 is
5015 the function to call; operand 1 is a memory location where the result of
5016 calling the function is to be stored; operand 2 is a @code{parallel}
5017 expression where each element is a @code{set} expression that indicates
5018 the saving of a function return value into the result block.
5020 This instruction pattern should be defined to support
5021 @code{__builtin_apply} on machines where special instructions are needed
5022 to call a subroutine with arbitrary arguments or to save the value
5023 returned. This instruction pattern is required on machines that have
5024 multiple registers that can hold a return value
5025 (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
5027 @cindex @code{return} instruction pattern
5029 Subroutine return instruction. This instruction pattern name should be
5030 defined only if a single instruction can do all the work of returning
5033 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
5034 RTL generation phase. In this case it is to support machines where
5035 multiple instructions are usually needed to return from a function, but
5036 some class of functions only requires one instruction to implement a
5037 return. Normally, the applicable functions are those which do not need
5038 to save any registers or allocate stack space.
5040 It is valid for this pattern to expand to an instruction using
5041 @code{simple_return} if no epilogue is required.
5043 @cindex @code{simple_return} instruction pattern
5044 @item @samp{simple_return}
5045 Subroutine return instruction. This instruction pattern name should be
5046 defined only if a single instruction can do all the work of returning
5047 from a function on a path where no epilogue is required. This pattern
5048 is very similar to the @code{return} instruction pattern, but it is emitted
5049 only by the shrink-wrapping optimization on paths where the function
5050 prologue has not been executed, and a function return should occur without
5051 any of the effects of the epilogue. Additional uses may be introduced on
5052 paths where both the prologue and the epilogue have executed.
5054 @findex reload_completed
5055 @findex leaf_function_p
5056 For such machines, the condition specified in this pattern should only
5057 be true when @code{reload_completed} is nonzero and the function's
5058 epilogue would only be a single instruction. For machines with register
5059 windows, the routine @code{leaf_function_p} may be used to determine if
5060 a register window push is required.
5062 Machines that have conditional return instructions should define patterns
5068 (if_then_else (match_operator
5069 0 "comparison_operator"
5070 [(cc0) (const_int 0)])
5077 where @var{condition} would normally be the same condition specified on the
5078 named @samp{return} pattern.
5080 @cindex @code{untyped_return} instruction pattern
5081 @item @samp{untyped_return}
5082 Untyped subroutine return instruction. This instruction pattern should
5083 be defined to support @code{__builtin_return} on machines where special
5084 instructions are needed to return a value of any type.
5086 Operand 0 is a memory location where the result of calling a function
5087 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
5088 expression where each element is a @code{set} expression that indicates
5089 the restoring of a function return value from the result block.
5091 @cindex @code{nop} instruction pattern
5093 No-op instruction. This instruction pattern name should always be defined
5094 to output a no-op in assembler code. @code{(const_int 0)} will do as an
5097 @cindex @code{indirect_jump} instruction pattern
5098 @item @samp{indirect_jump}
5099 An instruction to jump to an address which is operand zero.
5100 This pattern name is mandatory on all machines.
5102 @cindex @code{casesi} instruction pattern
5104 Instruction to jump through a dispatch table, including bounds checking.
5105 This instruction takes five operands:
5109 The index to dispatch on, which has mode @code{SImode}.
5112 The lower bound for indices in the table, an integer constant.
5115 The total range of indices in the table---the largest index
5116 minus the smallest one (both inclusive).
5119 A label that precedes the table itself.
5122 A label to jump to if the index has a value outside the bounds.
5125 The table is an @code{addr_vec} or @code{addr_diff_vec} inside of a
5126 @code{jump_insn}. The number of elements in the table is one plus the
5127 difference between the upper bound and the lower bound.
5129 @cindex @code{tablejump} instruction pattern
5130 @item @samp{tablejump}
5131 Instruction to jump to a variable address. This is a low-level
5132 capability which can be used to implement a dispatch table when there
5133 is no @samp{casesi} pattern.
5135 This pattern requires two operands: the address or offset, and a label
5136 which should immediately precede the jump table. If the macro
5137 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
5138 operand is an offset which counts from the address of the table; otherwise,
5139 it is an absolute address to jump to. In either case, the first operand has
5142 The @samp{tablejump} insn is always the last insn before the jump
5143 table it uses. Its assembler code normally has no need to use the
5144 second operand, but you should incorporate it in the RTL pattern so
5145 that the jump optimizer will not delete the table as unreachable code.
5148 @cindex @code{decrement_and_branch_until_zero} instruction pattern
5149 @item @samp{decrement_and_branch_until_zero}
5150 Conditional branch instruction that decrements a register and
5151 jumps if the register is nonzero. Operand 0 is the register to
5152 decrement and test; operand 1 is the label to jump to if the
5153 register is nonzero. @xref{Looping Patterns}.
5155 This optional instruction pattern is only used by the combiner,
5156 typically for loops reversed by the loop optimizer when strength
5157 reduction is enabled.
5159 @cindex @code{doloop_end} instruction pattern
5160 @item @samp{doloop_end}
5161 Conditional branch instruction that decrements a register and jumps if
5162 the register is nonzero. This instruction takes five operands: Operand
5163 0 is the register to decrement and test; operand 1 is the number of loop
5164 iterations as a @code{const_int} or @code{const0_rtx} if this cannot be
5165 determined until run-time; operand 2 is the actual or estimated maximum
5166 number of iterations as a @code{const_int}; operand 3 is the number of
5167 enclosed loops as a @code{const_int} (an innermost loop has a value of
5168 1); operand 4 is the label to jump to if the register is nonzero.
5169 @xref{Looping Patterns}.
5171 This optional instruction pattern should be defined for machines with
5172 low-overhead looping instructions as the loop optimizer will try to
5173 modify suitable loops to utilize it. If nested low-overhead looping is
5174 not supported, use a @code{define_expand} (@pxref{Expander Definitions})
5175 and make the pattern fail if operand 3 is not @code{const1_rtx}.
5176 Similarly, if the actual or estimated maximum number of iterations is
5177 too large for this instruction, make it fail.
5179 @cindex @code{doloop_begin} instruction pattern
5180 @item @samp{doloop_begin}
5181 Companion instruction to @code{doloop_end} required for machines that
5182 need to perform some initialization, such as loading special registers
5183 used by a low-overhead looping instruction. If initialization insns do
5184 not always need to be emitted, use a @code{define_expand}
5185 (@pxref{Expander Definitions}) and make it fail.
5188 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
5189 @item @samp{canonicalize_funcptr_for_compare}
5190 Canonicalize the function pointer in operand 1 and store the result
5193 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
5194 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
5195 and also has mode @code{Pmode}.
5197 Canonicalization of a function pointer usually involves computing
5198 the address of the function which would be called if the function
5199 pointer were used in an indirect call.
5201 Only define this pattern if function pointers on the target machine
5202 can have different values but still call the same function when
5203 used in an indirect call.
5205 @cindex @code{save_stack_block} instruction pattern
5206 @cindex @code{save_stack_function} instruction pattern
5207 @cindex @code{save_stack_nonlocal} instruction pattern
5208 @cindex @code{restore_stack_block} instruction pattern
5209 @cindex @code{restore_stack_function} instruction pattern
5210 @cindex @code{restore_stack_nonlocal} instruction pattern
5211 @item @samp{save_stack_block}
5212 @itemx @samp{save_stack_function}
5213 @itemx @samp{save_stack_nonlocal}
5214 @itemx @samp{restore_stack_block}
5215 @itemx @samp{restore_stack_function}
5216 @itemx @samp{restore_stack_nonlocal}
5217 Most machines save and restore the stack pointer by copying it to or
5218 from an object of mode @code{Pmode}. Do not define these patterns on
5221 Some machines require special handling for stack pointer saves and
5222 restores. On those machines, define the patterns corresponding to the
5223 non-standard cases by using a @code{define_expand} (@pxref{Expander
5224 Definitions}) that produces the required insns. The three types of
5225 saves and restores are:
5229 @samp{save_stack_block} saves the stack pointer at the start of a block
5230 that allocates a variable-sized object, and @samp{restore_stack_block}
5231 restores the stack pointer when the block is exited.
5234 @samp{save_stack_function} and @samp{restore_stack_function} do a
5235 similar job for the outermost block of a function and are used when the
5236 function allocates variable-sized objects or calls @code{alloca}. Only
5237 the epilogue uses the restored stack pointer, allowing a simpler save or
5238 restore sequence on some machines.
5241 @samp{save_stack_nonlocal} is used in functions that contain labels
5242 branched to by nested functions. It saves the stack pointer in such a
5243 way that the inner function can use @samp{restore_stack_nonlocal} to
5244 restore the stack pointer. The compiler generates code to restore the
5245 frame and argument pointer registers, but some machines require saving
5246 and restoring additional data such as register window information or
5247 stack backchains. Place insns in these patterns to save and restore any
5251 When saving the stack pointer, operand 0 is the save area and operand 1
5252 is the stack pointer. The mode used to allocate the save area defaults
5253 to @code{Pmode} but you can override that choice by defining the
5254 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
5255 specify an integral mode, or @code{VOIDmode} if no save area is needed
5256 for a particular type of save (either because no save is needed or
5257 because a machine-specific save area can be used). Operand 0 is the
5258 stack pointer and operand 1 is the save area for restore operations. If
5259 @samp{save_stack_block} is defined, operand 0 must not be
5260 @code{VOIDmode} since these saves can be arbitrarily nested.
5262 A save area is a @code{mem} that is at a constant offset from
5263 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
5264 nonlocal gotos and a @code{reg} in the other two cases.
5266 @cindex @code{allocate_stack} instruction pattern
5267 @item @samp{allocate_stack}
5268 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
5269 the stack pointer to create space for dynamically allocated data.
5271 Store the resultant pointer to this space into operand 0. If you
5272 are allocating space from the main stack, do this by emitting a
5273 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
5274 If you are allocating the space elsewhere, generate code to copy the
5275 location of the space to operand 0. In the latter case, you must
5276 ensure this space gets freed when the corresponding space on the main
5279 Do not define this pattern if all that must be done is the subtraction.
5280 Some machines require other operations such as stack probes or
5281 maintaining the back chain. Define this pattern to emit those
5282 operations in addition to updating the stack pointer.
5284 @cindex @code{check_stack} instruction pattern
5285 @item @samp{check_stack}
5286 If stack checking (@pxref{Stack Checking}) cannot be done on your system by
5287 probing the stack, define this pattern to perform the needed check and signal
5288 an error if the stack has overflowed. The single operand is the address in
5289 the stack farthest from the current stack pointer that you need to validate.
5290 Normally, on platforms where this pattern is needed, you would obtain the
5291 stack limit from a global or thread-specific variable or register.
5293 @cindex @code{probe_stack} instruction pattern
5294 @item @samp{probe_stack}
5295 If stack checking (@pxref{Stack Checking}) can be done on your system by
5296 probing the stack but doing it with a ``store zero'' instruction is not valid
5297 or optimal, define this pattern to do the probing differently and signal an
5298 error if the stack has overflowed. The single operand is the memory reference
5299 in the stack that needs to be probed.
5301 @cindex @code{nonlocal_goto} instruction pattern
5302 @item @samp{nonlocal_goto}
5303 Emit code to generate a non-local goto, e.g., a jump from one function
5304 to a label in an outer function. This pattern has four arguments,
5305 each representing a value to be used in the jump. The first
5306 argument is to be loaded into the frame pointer, the second is
5307 the address to branch to (code to dispatch to the actual label),
5308 the third is the address of a location where the stack is saved,
5309 and the last is the address of the label, to be placed in the
5310 location for the incoming static chain.
5312 On most machines you need not define this pattern, since GCC will
5313 already generate the correct code, which is to load the frame pointer
5314 and static chain, restore the stack (using the
5315 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
5316 to the dispatcher. You need only define this pattern if this code will
5317 not work on your machine.
5319 @cindex @code{nonlocal_goto_receiver} instruction pattern
5320 @item @samp{nonlocal_goto_receiver}
5321 This pattern, if defined, contains code needed at the target of a
5322 nonlocal goto after the code already generated by GCC@. You will not
5323 normally need to define this pattern. A typical reason why you might
5324 need this pattern is if some value, such as a pointer to a global table,
5325 must be restored when the frame pointer is restored. Note that a nonlocal
5326 goto only occurs within a unit-of-translation, so a global table pointer
5327 that is shared by all functions of a given module need not be restored.
5328 There are no arguments.
5330 @cindex @code{exception_receiver} instruction pattern
5331 @item @samp{exception_receiver}
5332 This pattern, if defined, contains code needed at the site of an
5333 exception handler that isn't needed at the site of a nonlocal goto. You
5334 will not normally need to define this pattern. A typical reason why you
5335 might need this pattern is if some value, such as a pointer to a global
5336 table, must be restored after control flow is branched to the handler of
5337 an exception. There are no arguments.
5339 @cindex @code{builtin_setjmp_setup} instruction pattern
5340 @item @samp{builtin_setjmp_setup}
5341 This pattern, if defined, contains additional code needed to initialize
5342 the @code{jmp_buf}. You will not normally need to define this pattern.
5343 A typical reason why you might need this pattern is if some value, such
5344 as a pointer to a global table, must be restored. Though it is
5345 preferred that the pointer value be recalculated if possible (given the
5346 address of a label for instance). The single argument is a pointer to
5347 the @code{jmp_buf}. Note that the buffer is five words long and that
5348 the first three are normally used by the generic mechanism.
5350 @cindex @code{builtin_setjmp_receiver} instruction pattern
5351 @item @samp{builtin_setjmp_receiver}
5352 This pattern, if defined, contains code needed at the site of a
5353 built-in setjmp that isn't needed at the site of a nonlocal goto. You
5354 will not normally need to define this pattern. A typical reason why you
5355 might need this pattern is if some value, such as a pointer to a global
5356 table, must be restored. It takes one argument, which is the label
5357 to which builtin_longjmp transfered control; this pattern may be emitted
5358 at a small offset from that label.
5360 @cindex @code{builtin_longjmp} instruction pattern
5361 @item @samp{builtin_longjmp}
5362 This pattern, if defined, performs the entire action of the longjmp.
5363 You will not normally need to define this pattern unless you also define
5364 @code{builtin_setjmp_setup}. The single argument is a pointer to the
5367 @cindex @code{eh_return} instruction pattern
5368 @item @samp{eh_return}
5369 This pattern, if defined, affects the way @code{__builtin_eh_return},
5370 and thence the call frame exception handling library routines, are
5371 built. It is intended to handle non-trivial actions needed along
5372 the abnormal return path.
5374 The address of the exception handler to which the function should return
5375 is passed as operand to this pattern. It will normally need to copied by
5376 the pattern to some special register or memory location.
5377 If the pattern needs to determine the location of the target call
5378 frame in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX},
5379 if defined; it will have already been assigned.
5381 If this pattern is not defined, the default action will be to simply
5382 copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either
5383 that macro or this pattern needs to be defined if call frame exception
5384 handling is to be used.
5386 @cindex @code{prologue} instruction pattern
5387 @anchor{prologue instruction pattern}
5388 @item @samp{prologue}
5389 This pattern, if defined, emits RTL for entry to a function. The function
5390 entry is responsible for setting up the stack frame, initializing the frame
5391 pointer register, saving callee saved registers, etc.
5393 Using a prologue pattern is generally preferred over defining
5394 @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue.
5396 The @code{prologue} pattern is particularly useful for targets which perform
5397 instruction scheduling.
5399 @cindex @code{window_save} instruction pattern
5400 @anchor{window_save instruction pattern}
5401 @item @samp{window_save}
5402 This pattern, if defined, emits RTL for a register window save. It should
5403 be defined if the target machine has register windows but the window events
5404 are decoupled from calls to subroutines. The canonical example is the SPARC
5407 @cindex @code{epilogue} instruction pattern
5408 @anchor{epilogue instruction pattern}
5409 @item @samp{epilogue}
5410 This pattern emits RTL for exit from a function. The function
5411 exit is responsible for deallocating the stack frame, restoring callee saved
5412 registers and emitting the return instruction.
5414 Using an epilogue pattern is generally preferred over defining
5415 @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue.
5417 The @code{epilogue} pattern is particularly useful for targets which perform
5418 instruction scheduling or which have delay slots for their return instruction.
5420 @cindex @code{sibcall_epilogue} instruction pattern
5421 @item @samp{sibcall_epilogue}
5422 This pattern, if defined, emits RTL for exit from a function without the final
5423 branch back to the calling function. This pattern will be emitted before any
5424 sibling call (aka tail call) sites.
5426 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
5427 parameter passing or any stack slots for arguments passed to the current
5430 @cindex @code{trap} instruction pattern
5432 This pattern, if defined, signals an error, typically by causing some
5433 kind of signal to be raised. Among other places, it is used by the Java
5434 front end to signal `invalid array index' exceptions.
5436 @cindex @code{ctrap@var{MM}4} instruction pattern
5437 @item @samp{ctrap@var{MM}4}
5438 Conditional trap instruction. Operand 0 is a piece of RTL which
5439 performs a comparison, and operands 1 and 2 are the arms of the
5440 comparison. Operand 3 is the trap code, an integer.
5442 A typical @code{ctrap} pattern looks like
5445 (define_insn "ctrapsi4"
5446 [(trap_if (match_operator 0 "trap_operator"
5447 [(match_operand 1 "register_operand")
5448 (match_operand 2 "immediate_operand")])
5449 (match_operand 3 "const_int_operand" "i"))]
5454 @cindex @code{prefetch} instruction pattern
5455 @item @samp{prefetch}
5457 This pattern, if defined, emits code for a non-faulting data prefetch
5458 instruction. Operand 0 is the address of the memory to prefetch. Operand 1
5459 is a constant 1 if the prefetch is preparing for a write to the memory
5460 address, or a constant 0 otherwise. Operand 2 is the expected degree of
5461 temporal locality of the data and is a value between 0 and 3, inclusive; 0
5462 means that the data has no temporal locality, so it need not be left in the
5463 cache after the access; 3 means that the data has a high degree of temporal
5464 locality and should be left in all levels of cache possible; 1 and 2 mean,
5465 respectively, a low or moderate degree of temporal locality.
5467 Targets that do not support write prefetches or locality hints can ignore
5468 the values of operands 1 and 2.
5470 @cindex @code{blockage} instruction pattern
5471 @item @samp{blockage}
5473 This pattern defines a pseudo insn that prevents the instruction
5474 scheduler from moving instructions across the boundary defined by the
5475 blockage insn. Normally an UNSPEC_VOLATILE pattern.
5477 @cindex @code{memory_barrier} instruction pattern
5478 @item @samp{memory_barrier}
5480 If the target memory model is not fully synchronous, then this pattern
5481 should be defined to an instruction that orders both loads and stores
5482 before the instruction with respect to loads and stores after the instruction.
5483 This pattern has no operands.
5485 @cindex @code{sync_compare_and_swap@var{mode}} instruction pattern
5486 @item @samp{sync_compare_and_swap@var{mode}}
5488 This pattern, if defined, emits code for an atomic compare-and-swap
5489 operation. Operand 1 is the memory on which the atomic operation is
5490 performed. Operand 2 is the ``old'' value to be compared against the
5491 current contents of the memory location. Operand 3 is the ``new'' value
5492 to store in the memory if the compare succeeds. Operand 0 is the result
5493 of the operation; it should contain the contents of the memory
5494 before the operation. If the compare succeeds, this should obviously be
5495 a copy of operand 2.
5497 This pattern must show that both operand 0 and operand 1 are modified.
5499 This pattern must issue any memory barrier instructions such that all
5500 memory operations before the atomic operation occur before the atomic
5501 operation and all memory operations after the atomic operation occur
5502 after the atomic operation.
5504 For targets where the success or failure of the compare-and-swap
5505 operation is available via the status flags, it is possible to
5506 avoid a separate compare operation and issue the subsequent
5507 branch or store-flag operation immediately after the compare-and-swap.
5508 To this end, GCC will look for a @code{MODE_CC} set in the
5509 output of @code{sync_compare_and_swap@var{mode}}; if the machine
5510 description includes such a set, the target should also define special
5511 @code{cbranchcc4} and/or @code{cstorecc4} instructions. GCC will then
5512 be able to take the destination of the @code{MODE_CC} set and pass it
5513 to the @code{cbranchcc4} or @code{cstorecc4} pattern as the first
5514 operand of the comparison (the second will be @code{(const_int 0)}).
5516 @cindex @code{sync_add@var{mode}} instruction pattern
5517 @cindex @code{sync_sub@var{mode}} instruction pattern
5518 @cindex @code{sync_ior@var{mode}} instruction pattern
5519 @cindex @code{sync_and@var{mode}} instruction pattern
5520 @cindex @code{sync_xor@var{mode}} instruction pattern
5521 @cindex @code{sync_nand@var{mode}} instruction pattern
5522 @item @samp{sync_add@var{mode}}, @samp{sync_sub@var{mode}}
5523 @itemx @samp{sync_ior@var{mode}}, @samp{sync_and@var{mode}}
5524 @itemx @samp{sync_xor@var{mode}}, @samp{sync_nand@var{mode}}
5526 These patterns emit code for an atomic operation on memory.
5527 Operand 0 is the memory on which the atomic operation is performed.
5528 Operand 1 is the second operand to the binary operator.
5530 This pattern must issue any memory barrier instructions such that all
5531 memory operations before the atomic operation occur before the atomic
5532 operation and all memory operations after the atomic operation occur
5533 after the atomic operation.
5535 If these patterns are not defined, the operation will be constructed
5536 from a compare-and-swap operation, if defined.
5538 @cindex @code{sync_old_add@var{mode}} instruction pattern
5539 @cindex @code{sync_old_sub@var{mode}} instruction pattern
5540 @cindex @code{sync_old_ior@var{mode}} instruction pattern
5541 @cindex @code{sync_old_and@var{mode}} instruction pattern
5542 @cindex @code{sync_old_xor@var{mode}} instruction pattern
5543 @cindex @code{sync_old_nand@var{mode}} instruction pattern
5544 @item @samp{sync_old_add@var{mode}}, @samp{sync_old_sub@var{mode}}
5545 @itemx @samp{sync_old_ior@var{mode}}, @samp{sync_old_and@var{mode}}
5546 @itemx @samp{sync_old_xor@var{mode}}, @samp{sync_old_nand@var{mode}}
5548 These patterns are emit code for an atomic operation on memory,
5549 and return the value that the memory contained before the operation.
5550 Operand 0 is the result value, operand 1 is the memory on which the
5551 atomic operation is performed, and operand 2 is the second operand
5552 to the binary operator.
5554 This pattern must issue any memory barrier instructions such that all
5555 memory operations before the atomic operation occur before the atomic
5556 operation and all memory operations after the atomic operation occur
5557 after the atomic operation.
5559 If these patterns are not defined, the operation will be constructed
5560 from a compare-and-swap operation, if defined.
5562 @cindex @code{sync_new_add@var{mode}} instruction pattern
5563 @cindex @code{sync_new_sub@var{mode}} instruction pattern
5564 @cindex @code{sync_new_ior@var{mode}} instruction pattern
5565 @cindex @code{sync_new_and@var{mode}} instruction pattern
5566 @cindex @code{sync_new_xor@var{mode}} instruction pattern
5567 @cindex @code{sync_new_nand@var{mode}} instruction pattern
5568 @item @samp{sync_new_add@var{mode}}, @samp{sync_new_sub@var{mode}}
5569 @itemx @samp{sync_new_ior@var{mode}}, @samp{sync_new_and@var{mode}}
5570 @itemx @samp{sync_new_xor@var{mode}}, @samp{sync_new_nand@var{mode}}
5572 These patterns are like their @code{sync_old_@var{op}} counterparts,
5573 except that they return the value that exists in the memory location
5574 after the operation, rather than before the operation.
5576 @cindex @code{sync_lock_test_and_set@var{mode}} instruction pattern
5577 @item @samp{sync_lock_test_and_set@var{mode}}
5579 This pattern takes two forms, based on the capabilities of the target.
5580 In either case, operand 0 is the result of the operand, operand 1 is
5581 the memory on which the atomic operation is performed, and operand 2
5582 is the value to set in the lock.
5584 In the ideal case, this operation is an atomic exchange operation, in
5585 which the previous value in memory operand is copied into the result
5586 operand, and the value operand is stored in the memory operand.
5588 For less capable targets, any value operand that is not the constant 1
5589 should be rejected with @code{FAIL}. In this case the target may use
5590 an atomic test-and-set bit operation. The result operand should contain
5591 1 if the bit was previously set and 0 if the bit was previously clear.
5592 The true contents of the memory operand are implementation defined.
5594 This pattern must issue any memory barrier instructions such that the
5595 pattern as a whole acts as an acquire barrier, that is all memory
5596 operations after the pattern do not occur until the lock is acquired.
5598 If this pattern is not defined, the operation will be constructed from
5599 a compare-and-swap operation, if defined.
5601 @cindex @code{sync_lock_release@var{mode}} instruction pattern
5602 @item @samp{sync_lock_release@var{mode}}
5604 This pattern, if defined, releases a lock set by
5605 @code{sync_lock_test_and_set@var{mode}}. Operand 0 is the memory
5606 that contains the lock; operand 1 is the value to store in the lock.
5608 If the target doesn't implement full semantics for
5609 @code{sync_lock_test_and_set@var{mode}}, any value operand which is not
5610 the constant 0 should be rejected with @code{FAIL}, and the true contents
5611 of the memory operand are implementation defined.
5613 This pattern must issue any memory barrier instructions such that the
5614 pattern as a whole acts as a release barrier, that is the lock is
5615 released only after all previous memory operations have completed.
5617 If this pattern is not defined, then a @code{memory_barrier} pattern
5618 will be emitted, followed by a store of the value to the memory operand.
5620 @cindex @code{stack_protect_set} instruction pattern
5621 @item @samp{stack_protect_set}
5623 This pattern, if defined, moves a @code{ptr_mode} value from the memory
5624 in operand 1 to the memory in operand 0 without leaving the value in
5625 a register afterward. This is to avoid leaking the value some place
5626 that an attacker might use to rewrite the stack guard slot after
5627 having clobbered it.
5629 If this pattern is not defined, then a plain move pattern is generated.
5631 @cindex @code{stack_protect_test} instruction pattern
5632 @item @samp{stack_protect_test}
5634 This pattern, if defined, compares a @code{ptr_mode} value from the
5635 memory in operand 1 with the memory in operand 0 without leaving the
5636 value in a register afterward and branches to operand 2 if the values
5639 If this pattern is not defined, then a plain compare pattern and
5640 conditional branch pattern is used.
5642 @cindex @code{clear_cache} instruction pattern
5643 @item @samp{clear_cache}
5645 This pattern, if defined, flushes the instruction cache for a region of
5646 memory. The region is bounded to by the Pmode pointers in operand 0
5647 inclusive and operand 1 exclusive.
5649 If this pattern is not defined, a call to the library function
5650 @code{__clear_cache} is used.
5655 @c Each of the following nodes are wrapped in separate
5656 @c "@ifset INTERNALS" to work around memory limits for the default
5657 @c configuration in older tetex distributions. Known to not work:
5658 @c tetex-1.0.7, known to work: tetex-2.0.2.
5660 @node Pattern Ordering
5661 @section When the Order of Patterns Matters
5662 @cindex Pattern Ordering
5663 @cindex Ordering of Patterns
5665 Sometimes an insn can match more than one instruction pattern. Then the
5666 pattern that appears first in the machine description is the one used.
5667 Therefore, more specific patterns (patterns that will match fewer things)
5668 and faster instructions (those that will produce better code when they
5669 do match) should usually go first in the description.
5671 In some cases the effect of ordering the patterns can be used to hide
5672 a pattern when it is not valid. For example, the 68000 has an
5673 instruction for converting a fullword to floating point and another
5674 for converting a byte to floating point. An instruction converting
5675 an integer to floating point could match either one. We put the
5676 pattern to convert the fullword first to make sure that one will
5677 be used rather than the other. (Otherwise a large integer might
5678 be generated as a single-byte immediate quantity, which would not work.)
5679 Instead of using this pattern ordering it would be possible to make the
5680 pattern for convert-a-byte smart enough to deal properly with any
5685 @node Dependent Patterns
5686 @section Interdependence of Patterns
5687 @cindex Dependent Patterns
5688 @cindex Interdependence of Patterns
5690 In some cases machines support instructions identical except for the
5691 machine mode of one or more operands. For example, there may be
5692 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
5696 (set (match_operand:SI 0 @dots{})
5697 (extend:SI (match_operand:HI 1 @dots{})))
5699 (set (match_operand:SI 0 @dots{})
5700 (extend:SI (match_operand:QI 1 @dots{})))
5704 Constant integers do not specify a machine mode, so an instruction to
5705 extend a constant value could match either pattern. The pattern it
5706 actually will match is the one that appears first in the file. For correct
5707 results, this must be the one for the widest possible mode (@code{HImode},
5708 here). If the pattern matches the @code{QImode} instruction, the results
5709 will be incorrect if the constant value does not actually fit that mode.
5711 Such instructions to extend constants are rarely generated because they are
5712 optimized away, but they do occasionally happen in nonoptimized
5715 If a constraint in a pattern allows a constant, the reload pass may
5716 replace a register with a constant permitted by the constraint in some
5717 cases. Similarly for memory references. Because of this substitution,
5718 you should not provide separate patterns for increment and decrement
5719 instructions. Instead, they should be generated from the same pattern
5720 that supports register-register add insns by examining the operands and
5721 generating the appropriate machine instruction.
5726 @section Defining Jump Instruction Patterns
5727 @cindex jump instruction patterns
5728 @cindex defining jump instruction patterns
5730 GCC does not assume anything about how the machine realizes jumps.
5731 The machine description should define a single pattern, usually
5732 a @code{define_expand}, which expands to all the required insns.
5734 Usually, this would be a comparison insn to set the condition code
5735 and a separate branch insn testing the condition code and branching
5736 or not according to its value. For many machines, however,
5737 separating compares and branches is limiting, which is why the
5738 more flexible approach with one @code{define_expand} is used in GCC.
5739 The machine description becomes clearer for architectures that
5740 have compare-and-branch instructions but no condition code. It also
5741 works better when different sets of comparison operators are supported
5742 by different kinds of conditional branches (e.g. integer vs. floating-point),
5743 or by conditional branches with respect to conditional stores.
5745 Two separate insns are always used if the machine description represents
5746 a condition code register using the legacy RTL expression @code{(cc0)},
5747 and on most machines that use a separate condition code register
5748 (@pxref{Condition Code}). For machines that use @code{(cc0)}, in
5749 fact, the set and use of the condition code must be separate and
5750 adjacent@footnote{@code{note} insns can separate them, though.}, thus
5751 allowing flags in @code{cc_status} to be used (@pxref{Condition Code}) and
5752 so that the comparison and branch insns could be located from each other
5753 by using the functions @code{prev_cc0_setter} and @code{next_cc0_user}.
5755 Even in this case having a single entry point for conditional branches
5756 is advantageous, because it handles equally well the case where a single
5757 comparison instruction records the results of both signed and unsigned
5758 comparison of the given operands (with the branch insns coming in distinct
5759 signed and unsigned flavors) as in the x86 or SPARC, and the case where
5760 there are distinct signed and unsigned compare instructions and only
5761 one set of conditional branch instructions as in the PowerPC.
5765 @node Looping Patterns
5766 @section Defining Looping Instruction Patterns
5767 @cindex looping instruction patterns
5768 @cindex defining looping instruction patterns
5770 Some machines have special jump instructions that can be utilized to
5771 make loops more efficient. A common example is the 68000 @samp{dbra}
5772 instruction which performs a decrement of a register and a branch if the
5773 result was greater than zero. Other machines, in particular digital
5774 signal processors (DSPs), have special block repeat instructions to
5775 provide low-overhead loop support. For example, the TI TMS320C3x/C4x
5776 DSPs have a block repeat instruction that loads special registers to
5777 mark the top and end of a loop and to count the number of loop
5778 iterations. This avoids the need for fetching and executing a
5779 @samp{dbra}-like instruction and avoids pipeline stalls associated with
5782 GCC has three special named patterns to support low overhead looping.
5783 They are @samp{decrement_and_branch_until_zero}, @samp{doloop_begin},
5784 and @samp{doloop_end}. The first pattern,
5785 @samp{decrement_and_branch_until_zero}, is not emitted during RTL
5786 generation but may be emitted during the instruction combination phase.
5787 This requires the assistance of the loop optimizer, using information
5788 collected during strength reduction, to reverse a loop to count down to
5789 zero. Some targets also require the loop optimizer to add a
5790 @code{REG_NONNEG} note to indicate that the iteration count is always
5791 positive. This is needed if the target performs a signed loop
5792 termination test. For example, the 68000 uses a pattern similar to the
5793 following for its @code{dbra} instruction:
5797 (define_insn "decrement_and_branch_until_zero"
5800 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
5803 (label_ref (match_operand 1 "" ""))
5806 (plus:SI (match_dup 0)
5808 "find_reg_note (insn, REG_NONNEG, 0)"
5813 Note that since the insn is both a jump insn and has an output, it must
5814 deal with its own reloads, hence the `m' constraints. Also note that
5815 since this insn is generated by the instruction combination phase
5816 combining two sequential insns together into an implicit parallel insn,
5817 the iteration counter needs to be biased by the same amount as the
5818 decrement operation, in this case @minus{}1. Note that the following similar
5819 pattern will not be matched by the combiner.
5823 (define_insn "decrement_and_branch_until_zero"
5826 (ge (match_operand:SI 0 "general_operand" "+d*am")
5828 (label_ref (match_operand 1 "" ""))
5831 (plus:SI (match_dup 0)
5833 "find_reg_note (insn, REG_NONNEG, 0)"
5838 The other two special looping patterns, @samp{doloop_begin} and
5839 @samp{doloop_end}, are emitted by the loop optimizer for certain
5840 well-behaved loops with a finite number of loop iterations using
5841 information collected during strength reduction.
5843 The @samp{doloop_end} pattern describes the actual looping instruction
5844 (or the implicit looping operation) and the @samp{doloop_begin} pattern
5845 is an optional companion pattern that can be used for initialization
5846 needed for some low-overhead looping instructions.
5848 Note that some machines require the actual looping instruction to be
5849 emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
5850 the true RTL for a looping instruction at the top of the loop can cause
5851 problems with flow analysis. So instead, a dummy @code{doloop} insn is
5852 emitted at the end of the loop. The machine dependent reorg pass checks
5853 for the presence of this @code{doloop} insn and then searches back to
5854 the top of the loop, where it inserts the true looping insn (provided
5855 there are no instructions in the loop which would cause problems). Any
5856 additional labels can be emitted at this point. In addition, if the
5857 desired special iteration counter register was not allocated, this
5858 machine dependent reorg pass could emit a traditional compare and jump
5861 The essential difference between the
5862 @samp{decrement_and_branch_until_zero} and the @samp{doloop_end}
5863 patterns is that the loop optimizer allocates an additional pseudo
5864 register for the latter as an iteration counter. This pseudo register
5865 cannot be used within the loop (i.e., general induction variables cannot
5866 be derived from it), however, in many cases the loop induction variable
5867 may become redundant and removed by the flow pass.
5872 @node Insn Canonicalizations
5873 @section Canonicalization of Instructions
5874 @cindex canonicalization of instructions
5875 @cindex insn canonicalization
5877 There are often cases where multiple RTL expressions could represent an
5878 operation performed by a single machine instruction. This situation is
5879 most commonly encountered with logical, branch, and multiply-accumulate
5880 instructions. In such cases, the compiler attempts to convert these
5881 multiple RTL expressions into a single canonical form to reduce the
5882 number of insn patterns required.
5884 In addition to algebraic simplifications, following canonicalizations
5889 For commutative and comparison operators, a constant is always made the
5890 second operand. If a machine only supports a constant as the second
5891 operand, only patterns that match a constant in the second operand need
5895 For associative operators, a sequence of operators will always chain
5896 to the left; for instance, only the left operand of an integer @code{plus}
5897 can itself be a @code{plus}. @code{and}, @code{ior}, @code{xor},
5898 @code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and
5899 @code{umax} are associative when applied to integers, and sometimes to
5903 @cindex @code{neg}, canonicalization of
5904 @cindex @code{not}, canonicalization of
5905 @cindex @code{mult}, canonicalization of
5906 @cindex @code{plus}, canonicalization of
5907 @cindex @code{minus}, canonicalization of
5908 For these operators, if only one operand is a @code{neg}, @code{not},
5909 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
5913 In combinations of @code{neg}, @code{mult}, @code{plus}, and
5914 @code{minus}, the @code{neg} operations (if any) will be moved inside
5915 the operations as far as possible. For instance,
5916 @code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but
5917 @code{(plus (mult (neg B) C) A)} is canonicalized as
5918 @code{(minus A (mult B C))}.
5920 @cindex @code{compare}, canonicalization of
5922 For the @code{compare} operator, a constant is always the second operand
5923 if the first argument is a condition code register or @code{(cc0)}.
5926 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
5927 @code{minus} is made the first operand under the same conditions as
5931 @code{(ltu (plus @var{a} @var{b}) @var{b})} is converted to
5932 @code{(ltu (plus @var{a} @var{b}) @var{a})}. Likewise with @code{geu} instead
5936 @code{(minus @var{x} (const_int @var{n}))} is converted to
5937 @code{(plus @var{x} (const_int @var{-n}))}.
5940 Within address computations (i.e., inside @code{mem}), a left shift is
5941 converted into the appropriate multiplication by a power of two.
5943 @cindex @code{ior}, canonicalization of
5944 @cindex @code{and}, canonicalization of
5945 @cindex De Morgan's law
5947 De Morgan's Law is used to move bitwise negation inside a bitwise
5948 logical-and or logical-or operation. If this results in only one
5949 operand being a @code{not} expression, it will be the first one.
5951 A machine that has an instruction that performs a bitwise logical-and of one
5952 operand with the bitwise negation of the other should specify the pattern
5953 for that instruction as
5957 [(set (match_operand:@var{m} 0 @dots{})
5958 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
5959 (match_operand:@var{m} 2 @dots{})))]
5965 Similarly, a pattern for a ``NAND'' instruction should be written
5969 [(set (match_operand:@var{m} 0 @dots{})
5970 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
5971 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
5976 In both cases, it is not necessary to include patterns for the many
5977 logically equivalent RTL expressions.
5979 @cindex @code{xor}, canonicalization of
5981 The only possible RTL expressions involving both bitwise exclusive-or
5982 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
5983 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
5986 The sum of three items, one of which is a constant, will only appear in
5990 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
5993 @cindex @code{zero_extract}, canonicalization of
5994 @cindex @code{sign_extract}, canonicalization of
5996 Equality comparisons of a group of bits (usually a single bit) with zero
5997 will be written using @code{zero_extract} rather than the equivalent
5998 @code{and} or @code{sign_extract} operations.
6000 @cindex @code{mult}, canonicalization of
6002 @code{(sign_extend:@var{m1} (mult:@var{m2} (sign_extend:@var{m2} @var{x})
6003 (sign_extend:@var{m2} @var{y})))} is converted to @code{(mult:@var{m1}
6004 (sign_extend:@var{m1} @var{x}) (sign_extend:@var{m1} @var{y}))}, and likewise
6005 for @code{zero_extend}.
6008 @code{(sign_extend:@var{m1} (mult:@var{m2} (ashiftrt:@var{m2}
6009 @var{x} @var{s}) (sign_extend:@var{m2} @var{y})))} is converted
6010 to @code{(mult:@var{m1} (sign_extend:@var{m1} (ashiftrt:@var{m2}
6011 @var{x} @var{s})) (sign_extend:@var{m1} @var{y}))}, and likewise for
6012 patterns using @code{zero_extend} and @code{lshiftrt}. If the second
6013 operand of @code{mult} is also a shift, then that is extended also.
6014 This transformation is only applied when it can be proven that the
6015 original operation had sufficient precision to prevent overflow.
6019 Further canonicalization rules are defined in the function
6020 @code{commutative_operand_precedence} in @file{gcc/rtlanal.c}.
6024 @node Expander Definitions
6025 @section Defining RTL Sequences for Code Generation
6026 @cindex expander definitions
6027 @cindex code generation RTL sequences
6028 @cindex defining RTL sequences for code generation
6030 On some target machines, some standard pattern names for RTL generation
6031 cannot be handled with single insn, but a sequence of RTL insns can
6032 represent them. For these target machines, you can write a
6033 @code{define_expand} to specify how to generate the sequence of RTL@.
6035 @findex define_expand
6036 A @code{define_expand} is an RTL expression that looks almost like a
6037 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
6038 only for RTL generation and it can produce more than one RTL insn.
6040 A @code{define_expand} RTX has four operands:
6044 The name. Each @code{define_expand} must have a name, since the only
6045 use for it is to refer to it by name.
6048 The RTL template. This is a vector of RTL expressions representing
6049 a sequence of separate instructions. Unlike @code{define_insn}, there
6050 is no implicit surrounding @code{PARALLEL}.
6053 The condition, a string containing a C expression. This expression is
6054 used to express how the availability of this pattern depends on
6055 subclasses of target machine, selected by command-line options when GCC
6056 is run. This is just like the condition of a @code{define_insn} that
6057 has a standard name. Therefore, the condition (if present) may not
6058 depend on the data in the insn being matched, but only the
6059 target-machine-type flags. The compiler needs to test these conditions
6060 during initialization in order to learn exactly which named instructions
6061 are available in a particular run.
6064 The preparation statements, a string containing zero or more C
6065 statements which are to be executed before RTL code is generated from
6068 Usually these statements prepare temporary registers for use as
6069 internal operands in the RTL template, but they can also generate RTL
6070 insns directly by calling routines such as @code{emit_insn}, etc.
6071 Any such insns precede the ones that come from the RTL template.
6074 Every RTL insn emitted by a @code{define_expand} must match some
6075 @code{define_insn} in the machine description. Otherwise, the compiler
6076 will crash when trying to generate code for the insn or trying to optimize
6079 The RTL template, in addition to controlling generation of RTL insns,
6080 also describes the operands that need to be specified when this pattern
6081 is used. In particular, it gives a predicate for each operand.
6083 A true operand, which needs to be specified in order to generate RTL from
6084 the pattern, should be described with a @code{match_operand} in its first
6085 occurrence in the RTL template. This enters information on the operand's
6086 predicate into the tables that record such things. GCC uses the
6087 information to preload the operand into a register if that is required for
6088 valid RTL code. If the operand is referred to more than once, subsequent
6089 references should use @code{match_dup}.
6091 The RTL template may also refer to internal ``operands'' which are
6092 temporary registers or labels used only within the sequence made by the
6093 @code{define_expand}. Internal operands are substituted into the RTL
6094 template with @code{match_dup}, never with @code{match_operand}. The
6095 values of the internal operands are not passed in as arguments by the
6096 compiler when it requests use of this pattern. Instead, they are computed
6097 within the pattern, in the preparation statements. These statements
6098 compute the values and store them into the appropriate elements of
6099 @code{operands} so that @code{match_dup} can find them.
6101 There are two special macros defined for use in the preparation statements:
6102 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
6109 Use the @code{DONE} macro to end RTL generation for the pattern. The
6110 only RTL insns resulting from the pattern on this occasion will be
6111 those already emitted by explicit calls to @code{emit_insn} within the
6112 preparation statements; the RTL template will not be generated.
6116 Make the pattern fail on this occasion. When a pattern fails, it means
6117 that the pattern was not truly available. The calling routines in the
6118 compiler will try other strategies for code generation using other patterns.
6120 Failure is currently supported only for binary (addition, multiplication,
6121 shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv})
6125 If the preparation falls through (invokes neither @code{DONE} nor
6126 @code{FAIL}), then the @code{define_expand} acts like a
6127 @code{define_insn} in that the RTL template is used to generate the
6130 The RTL template is not used for matching, only for generating the
6131 initial insn list. If the preparation statement always invokes
6132 @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple
6133 list of operands, such as this example:
6137 (define_expand "addsi3"
6138 [(match_operand:SI 0 "register_operand" "")
6139 (match_operand:SI 1 "register_operand" "")
6140 (match_operand:SI 2 "register_operand" "")]
6146 handle_add (operands[0], operands[1], operands[2]);
6152 Here is an example, the definition of left-shift for the SPUR chip:
6156 (define_expand "ashlsi3"
6157 [(set (match_operand:SI 0 "register_operand" "")
6161 (match_operand:SI 1 "register_operand" "")
6162 (match_operand:SI 2 "nonmemory_operand" "")))]
6171 if (GET_CODE (operands[2]) != CONST_INT
6172 || (unsigned) INTVAL (operands[2]) > 3)
6179 This example uses @code{define_expand} so that it can generate an RTL insn
6180 for shifting when the shift-count is in the supported range of 0 to 3 but
6181 fail in other cases where machine insns aren't available. When it fails,
6182 the compiler tries another strategy using different patterns (such as, a
6185 If the compiler were able to handle nontrivial condition-strings in
6186 patterns with names, then it would be possible to use a
6187 @code{define_insn} in that case. Here is another case (zero-extension
6188 on the 68000) which makes more use of the power of @code{define_expand}:
6191 (define_expand "zero_extendhisi2"
6192 [(set (match_operand:SI 0 "general_operand" "")
6194 (set (strict_low_part
6198 (match_operand:HI 1 "general_operand" ""))]
6200 "operands[1] = make_safe_from (operands[1], operands[0]);")
6204 @findex make_safe_from
6205 Here two RTL insns are generated, one to clear the entire output operand
6206 and the other to copy the input operand into its low half. This sequence
6207 is incorrect if the input operand refers to [the old value of] the output
6208 operand, so the preparation statement makes sure this isn't so. The
6209 function @code{make_safe_from} copies the @code{operands[1]} into a
6210 temporary register if it refers to @code{operands[0]}. It does this
6211 by emitting another RTL insn.
6213 Finally, a third example shows the use of an internal operand.
6214 Zero-extension on the SPUR chip is done by @code{and}-ing the result
6215 against a halfword mask. But this mask cannot be represented by a
6216 @code{const_int} because the constant value is too large to be legitimate
6217 on this machine. So it must be copied into a register with
6218 @code{force_reg} and then the register used in the @code{and}.
6221 (define_expand "zero_extendhisi2"
6222 [(set (match_operand:SI 0 "register_operand" "")
6224 (match_operand:HI 1 "register_operand" "")
6229 = force_reg (SImode, GEN_INT (65535)); ")
6232 @emph{Note:} If the @code{define_expand} is used to serve a
6233 standard binary or unary arithmetic operation or a bit-field operation,
6234 then the last insn it generates must not be a @code{code_label},
6235 @code{barrier} or @code{note}. It must be an @code{insn},
6236 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
6237 at the end, emit an insn to copy the result of the operation into
6238 itself. Such an insn will generate no code, but it can avoid problems
6243 @node Insn Splitting
6244 @section Defining How to Split Instructions
6245 @cindex insn splitting
6246 @cindex instruction splitting
6247 @cindex splitting instructions
6249 There are two cases where you should specify how to split a pattern
6250 into multiple insns. On machines that have instructions requiring
6251 delay slots (@pxref{Delay Slots}) or that have instructions whose
6252 output is not available for multiple cycles (@pxref{Processor pipeline
6253 description}), the compiler phases that optimize these cases need to
6254 be able to move insns into one-instruction delay slots. However, some
6255 insns may generate more than one machine instruction. These insns
6256 cannot be placed into a delay slot.
6258 Often you can rewrite the single insn as a list of individual insns,
6259 each corresponding to one machine instruction. The disadvantage of
6260 doing so is that it will cause the compilation to be slower and require
6261 more space. If the resulting insns are too complex, it may also
6262 suppress some optimizations. The compiler splits the insn if there is a
6263 reason to believe that it might improve instruction or delay slot
6266 The insn combiner phase also splits putative insns. If three insns are
6267 merged into one insn with a complex expression that cannot be matched by
6268 some @code{define_insn} pattern, the combiner phase attempts to split
6269 the complex pattern into two insns that are recognized. Usually it can
6270 break the complex pattern into two patterns by splitting out some
6271 subexpression. However, in some other cases, such as performing an
6272 addition of a large constant in two insns on a RISC machine, the way to
6273 split the addition into two insns is machine-dependent.
6275 @findex define_split
6276 The @code{define_split} definition tells the compiler how to split a
6277 complex insn into several simpler insns. It looks like this:
6281 [@var{insn-pattern}]
6283 [@var{new-insn-pattern-1}
6284 @var{new-insn-pattern-2}
6286 "@var{preparation-statements}")
6289 @var{insn-pattern} is a pattern that needs to be split and
6290 @var{condition} is the final condition to be tested, as in a
6291 @code{define_insn}. When an insn matching @var{insn-pattern} and
6292 satisfying @var{condition} is found, it is replaced in the insn list
6293 with the insns given by @var{new-insn-pattern-1},
6294 @var{new-insn-pattern-2}, etc.
6296 The @var{preparation-statements} are similar to those statements that
6297 are specified for @code{define_expand} (@pxref{Expander Definitions})
6298 and are executed before the new RTL is generated to prepare for the
6299 generated code or emit some insns whose pattern is not fixed. Unlike
6300 those in @code{define_expand}, however, these statements must not
6301 generate any new pseudo-registers. Once reload has completed, they also
6302 must not allocate any space in the stack frame.
6304 Patterns are matched against @var{insn-pattern} in two different
6305 circumstances. If an insn needs to be split for delay slot scheduling
6306 or insn scheduling, the insn is already known to be valid, which means
6307 that it must have been matched by some @code{define_insn} and, if
6308 @code{reload_completed} is nonzero, is known to satisfy the constraints
6309 of that @code{define_insn}. In that case, the new insn patterns must
6310 also be insns that are matched by some @code{define_insn} and, if
6311 @code{reload_completed} is nonzero, must also satisfy the constraints
6312 of those definitions.
6314 As an example of this usage of @code{define_split}, consider the following
6315 example from @file{a29k.md}, which splits a @code{sign_extend} from
6316 @code{HImode} to @code{SImode} into a pair of shift insns:
6320 [(set (match_operand:SI 0 "gen_reg_operand" "")
6321 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
6324 (ashift:SI (match_dup 1)
6327 (ashiftrt:SI (match_dup 0)
6330 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
6333 When the combiner phase tries to split an insn pattern, it is always the
6334 case that the pattern is @emph{not} matched by any @code{define_insn}.
6335 The combiner pass first tries to split a single @code{set} expression
6336 and then the same @code{set} expression inside a @code{parallel}, but
6337 followed by a @code{clobber} of a pseudo-reg to use as a scratch
6338 register. In these cases, the combiner expects exactly two new insn
6339 patterns to be generated. It will verify that these patterns match some
6340 @code{define_insn} definitions, so you need not do this test in the
6341 @code{define_split} (of course, there is no point in writing a
6342 @code{define_split} that will never produce insns that match).
6344 Here is an example of this use of @code{define_split}, taken from
6349 [(set (match_operand:SI 0 "gen_reg_operand" "")
6350 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
6351 (match_operand:SI 2 "non_add_cint_operand" "")))]
6353 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
6354 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
6357 int low = INTVAL (operands[2]) & 0xffff;
6358 int high = (unsigned) INTVAL (operands[2]) >> 16;
6361 high++, low |= 0xffff0000;
6363 operands[3] = GEN_INT (high << 16);
6364 operands[4] = GEN_INT (low);
6368 Here the predicate @code{non_add_cint_operand} matches any
6369 @code{const_int} that is @emph{not} a valid operand of a single add
6370 insn. The add with the smaller displacement is written so that it
6371 can be substituted into the address of a subsequent operation.
6373 An example that uses a scratch register, from the same file, generates
6374 an equality comparison of a register and a large constant:
6378 [(set (match_operand:CC 0 "cc_reg_operand" "")
6379 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
6380 (match_operand:SI 2 "non_short_cint_operand" "")))
6381 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
6382 "find_single_use (operands[0], insn, 0)
6383 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
6384 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
6385 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
6386 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
6389 /* @r{Get the constant we are comparing against, C, and see what it
6390 looks like sign-extended to 16 bits. Then see what constant
6391 could be XOR'ed with C to get the sign-extended value.} */
6393 int c = INTVAL (operands[2]);
6394 int sextc = (c << 16) >> 16;
6395 int xorv = c ^ sextc;
6397 operands[4] = GEN_INT (xorv);
6398 operands[5] = GEN_INT (sextc);
6402 To avoid confusion, don't write a single @code{define_split} that
6403 accepts some insns that match some @code{define_insn} as well as some
6404 insns that don't. Instead, write two separate @code{define_split}
6405 definitions, one for the insns that are valid and one for the insns that
6408 The splitter is allowed to split jump instructions into sequence of
6409 jumps or create new jumps in while splitting non-jump instructions. As
6410 the central flowgraph and branch prediction information needs to be updated,
6411 several restriction apply.
6413 Splitting of jump instruction into sequence that over by another jump
6414 instruction is always valid, as compiler expect identical behavior of new
6415 jump. When new sequence contains multiple jump instructions or new labels,
6416 more assistance is needed. Splitter is required to create only unconditional
6417 jumps, or simple conditional jump instructions. Additionally it must attach a
6418 @code{REG_BR_PROB} note to each conditional jump. A global variable
6419 @code{split_branch_probability} holds the probability of the original branch in case
6420 it was a simple conditional jump, @minus{}1 otherwise. To simplify
6421 recomputing of edge frequencies, the new sequence is required to have only
6422 forward jumps to the newly created labels.
6424 @findex define_insn_and_split
6425 For the common case where the pattern of a define_split exactly matches the
6426 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
6430 (define_insn_and_split
6431 [@var{insn-pattern}]
6433 "@var{output-template}"
6434 "@var{split-condition}"
6435 [@var{new-insn-pattern-1}
6436 @var{new-insn-pattern-2}
6438 "@var{preparation-statements}"
6439 [@var{insn-attributes}])
6443 @var{insn-pattern}, @var{condition}, @var{output-template}, and
6444 @var{insn-attributes} are used as in @code{define_insn}. The
6445 @var{new-insn-pattern} vector and the @var{preparation-statements} are used as
6446 in a @code{define_split}. The @var{split-condition} is also used as in
6447 @code{define_split}, with the additional behavior that if the condition starts
6448 with @samp{&&}, the condition used for the split will be the constructed as a
6449 logical ``and'' of the split condition with the insn condition. For example,
6453 (define_insn_and_split "zero_extendhisi2_and"
6454 [(set (match_operand:SI 0 "register_operand" "=r")
6455 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
6456 (clobber (reg:CC 17))]
6457 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
6459 "&& reload_completed"
6460 [(parallel [(set (match_dup 0)
6461 (and:SI (match_dup 0) (const_int 65535)))
6462 (clobber (reg:CC 17))])]
6464 [(set_attr "type" "alu1")])
6468 In this case, the actual split condition will be
6469 @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
6471 The @code{define_insn_and_split} construction provides exactly the same
6472 functionality as two separate @code{define_insn} and @code{define_split}
6473 patterns. It exists for compactness, and as a maintenance tool to prevent
6474 having to ensure the two patterns' templates match.
6478 @node Including Patterns
6479 @section Including Patterns in Machine Descriptions.
6480 @cindex insn includes
6483 The @code{include} pattern tells the compiler tools where to
6484 look for patterns that are in files other than in the file
6485 @file{.md}. This is used only at build time and there is no preprocessing allowed.
6499 (include "filestuff")
6503 Where @var{pathname} is a string that specifies the location of the file,
6504 specifies the include file to be in @file{gcc/config/target/filestuff}. The
6505 directory @file{gcc/config/target} is regarded as the default directory.
6508 Machine descriptions may be split up into smaller more manageable subsections
6509 and placed into subdirectories.
6515 (include "BOGUS/filestuff")
6519 the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}.
6521 Specifying an absolute path for the include file such as;
6524 (include "/u2/BOGUS/filestuff")
6527 is permitted but is not encouraged.
6529 @subsection RTL Generation Tool Options for Directory Search
6530 @cindex directory options .md
6531 @cindex options, directory search
6532 @cindex search options
6534 The @option{-I@var{dir}} option specifies directories to search for machine descriptions.
6539 genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md
6544 Add the directory @var{dir} to the head of the list of directories to be
6545 searched for header files. This can be used to override a system machine definition
6546 file, substituting your own version, since these directories are
6547 searched before the default machine description file directories. If you use more than
6548 one @option{-I} option, the directories are scanned in left-to-right
6549 order; the standard default directory come after.
6554 @node Peephole Definitions
6555 @section Machine-Specific Peephole Optimizers
6556 @cindex peephole optimizer definitions
6557 @cindex defining peephole optimizers
6559 In addition to instruction patterns the @file{md} file may contain
6560 definitions of machine-specific peephole optimizations.
6562 The combiner does not notice certain peephole optimizations when the data
6563 flow in the program does not suggest that it should try them. For example,
6564 sometimes two consecutive insns related in purpose can be combined even
6565 though the second one does not appear to use a register computed in the
6566 first one. A machine-specific peephole optimizer can detect such
6569 There are two forms of peephole definitions that may be used. The
6570 original @code{define_peephole} is run at assembly output time to
6571 match insns and substitute assembly text. Use of @code{define_peephole}
6574 A newer @code{define_peephole2} matches insns and substitutes new
6575 insns. The @code{peephole2} pass is run after register allocation
6576 but before scheduling, which may result in much better code for
6577 targets that do scheduling.
6580 * define_peephole:: RTL to Text Peephole Optimizers
6581 * define_peephole2:: RTL to RTL Peephole Optimizers
6586 @node define_peephole
6587 @subsection RTL to Text Peephole Optimizers
6588 @findex define_peephole
6591 A definition looks like this:
6595 [@var{insn-pattern-1}
6596 @var{insn-pattern-2}
6600 "@var{optional-insn-attributes}")
6604 The last string operand may be omitted if you are not using any
6605 machine-specific information in this machine description. If present,
6606 it must obey the same rules as in a @code{define_insn}.
6608 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
6609 consecutive insns. The optimization applies to a sequence of insns when
6610 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
6611 the next, and so on.
6613 Each of the insns matched by a peephole must also match a
6614 @code{define_insn}. Peepholes are checked only at the last stage just
6615 before code generation, and only optionally. Therefore, any insn which
6616 would match a peephole but no @code{define_insn} will cause a crash in code
6617 generation in an unoptimized compilation, or at various optimization
6620 The operands of the insns are matched with @code{match_operands},
6621 @code{match_operator}, and @code{match_dup}, as usual. What is not
6622 usual is that the operand numbers apply to all the insn patterns in the
6623 definition. So, you can check for identical operands in two insns by
6624 using @code{match_operand} in one insn and @code{match_dup} in the
6627 The operand constraints used in @code{match_operand} patterns do not have
6628 any direct effect on the applicability of the peephole, but they will
6629 be validated afterward, so make sure your constraints are general enough
6630 to apply whenever the peephole matches. If the peephole matches
6631 but the constraints are not satisfied, the compiler will crash.
6633 It is safe to omit constraints in all the operands of the peephole; or
6634 you can write constraints which serve as a double-check on the criteria
6637 Once a sequence of insns matches the patterns, the @var{condition} is
6638 checked. This is a C expression which makes the final decision whether to
6639 perform the optimization (we do so if the expression is nonzero). If
6640 @var{condition} is omitted (in other words, the string is empty) then the
6641 optimization is applied to every sequence of insns that matches the
6644 The defined peephole optimizations are applied after register allocation
6645 is complete. Therefore, the peephole definition can check which
6646 operands have ended up in which kinds of registers, just by looking at
6649 @findex prev_active_insn
6650 The way to refer to the operands in @var{condition} is to write
6651 @code{operands[@var{i}]} for operand number @var{i} (as matched by
6652 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
6653 to refer to the last of the insns being matched; use
6654 @code{prev_active_insn} to find the preceding insns.
6656 @findex dead_or_set_p
6657 When optimizing computations with intermediate results, you can use
6658 @var{condition} to match only when the intermediate results are not used
6659 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
6660 @var{op})}, where @var{insn} is the insn in which you expect the value
6661 to be used for the last time (from the value of @code{insn}, together
6662 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
6663 value (from @code{operands[@var{i}]}).
6665 Applying the optimization means replacing the sequence of insns with one
6666 new insn. The @var{template} controls ultimate output of assembler code
6667 for this combined insn. It works exactly like the template of a
6668 @code{define_insn}. Operand numbers in this template are the same ones
6669 used in matching the original sequence of insns.
6671 The result of a defined peephole optimizer does not need to match any of
6672 the insn patterns in the machine description; it does not even have an
6673 opportunity to match them. The peephole optimizer definition itself serves
6674 as the insn pattern to control how the insn is output.
6676 Defined peephole optimizers are run as assembler code is being output,
6677 so the insns they produce are never combined or rearranged in any way.
6679 Here is an example, taken from the 68000 machine description:
6683 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
6684 (set (match_operand:DF 0 "register_operand" "=f")
6685 (match_operand:DF 1 "register_operand" "ad"))]
6686 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
6689 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
6691 output_asm_insn ("move.l %1,(sp)", xoperands);
6692 output_asm_insn ("move.l %1,-(sp)", operands);
6693 return "fmove.d (sp)+,%0";
6695 output_asm_insn ("movel %1,sp@@", xoperands);
6696 output_asm_insn ("movel %1,sp@@-", operands);
6697 return "fmoved sp@@+,%0";
6703 The effect of this optimization is to change
6729 If a peephole matches a sequence including one or more jump insns, you must
6730 take account of the flags such as @code{CC_REVERSED} which specify that the
6731 condition codes are represented in an unusual manner. The compiler
6732 automatically alters any ordinary conditional jumps which occur in such
6733 situations, but the compiler cannot alter jumps which have been replaced by
6734 peephole optimizations. So it is up to you to alter the assembler code
6735 that the peephole produces. Supply C code to write the assembler output,
6736 and in this C code check the condition code status flags and change the
6737 assembler code as appropriate.
6740 @var{insn-pattern-1} and so on look @emph{almost} like the second
6741 operand of @code{define_insn}. There is one important difference: the
6742 second operand of @code{define_insn} consists of one or more RTX's
6743 enclosed in square brackets. Usually, there is only one: then the same
6744 action can be written as an element of a @code{define_peephole}. But
6745 when there are multiple actions in a @code{define_insn}, they are
6746 implicitly enclosed in a @code{parallel}. Then you must explicitly
6747 write the @code{parallel}, and the square brackets within it, in the
6748 @code{define_peephole}. Thus, if an insn pattern looks like this,
6751 (define_insn "divmodsi4"
6752 [(set (match_operand:SI 0 "general_operand" "=d")
6753 (div:SI (match_operand:SI 1 "general_operand" "0")
6754 (match_operand:SI 2 "general_operand" "dmsK")))
6755 (set (match_operand:SI 3 "general_operand" "=d")
6756 (mod:SI (match_dup 1) (match_dup 2)))]
6758 "divsl%.l %2,%3:%0")
6762 then the way to mention this insn in a peephole is as follows:
6768 [(set (match_operand:SI 0 "general_operand" "=d")
6769 (div:SI (match_operand:SI 1 "general_operand" "0")
6770 (match_operand:SI 2 "general_operand" "dmsK")))
6771 (set (match_operand:SI 3 "general_operand" "=d")
6772 (mod:SI (match_dup 1) (match_dup 2)))])
6779 @node define_peephole2
6780 @subsection RTL to RTL Peephole Optimizers
6781 @findex define_peephole2
6783 The @code{define_peephole2} definition tells the compiler how to
6784 substitute one sequence of instructions for another sequence,
6785 what additional scratch registers may be needed and what their
6790 [@var{insn-pattern-1}
6791 @var{insn-pattern-2}
6794 [@var{new-insn-pattern-1}
6795 @var{new-insn-pattern-2}
6797 "@var{preparation-statements}")
6800 The definition is almost identical to @code{define_split}
6801 (@pxref{Insn Splitting}) except that the pattern to match is not a
6802 single instruction, but a sequence of instructions.
6804 It is possible to request additional scratch registers for use in the
6805 output template. If appropriate registers are not free, the pattern
6806 will simply not match.
6808 @findex match_scratch
6810 Scratch registers are requested with a @code{match_scratch} pattern at
6811 the top level of the input pattern. The allocated register (initially) will
6812 be dead at the point requested within the original sequence. If the scratch
6813 is used at more than a single point, a @code{match_dup} pattern at the
6814 top level of the input pattern marks the last position in the input sequence
6815 at which the register must be available.
6817 Here is an example from the IA-32 machine description:
6821 [(match_scratch:SI 2 "r")
6822 (parallel [(set (match_operand:SI 0 "register_operand" "")
6823 (match_operator:SI 3 "arith_or_logical_operator"
6825 (match_operand:SI 1 "memory_operand" "")]))
6826 (clobber (reg:CC 17))])]
6827 "! optimize_size && ! TARGET_READ_MODIFY"
6828 [(set (match_dup 2) (match_dup 1))
6829 (parallel [(set (match_dup 0)
6830 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
6831 (clobber (reg:CC 17))])]
6836 This pattern tries to split a load from its use in the hopes that we'll be
6837 able to schedule around the memory load latency. It allocates a single
6838 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
6839 to be live only at the point just before the arithmetic.
6841 A real example requiring extended scratch lifetimes is harder to come by,
6842 so here's a silly made-up example:
6846 [(match_scratch:SI 4 "r")
6847 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
6848 (set (match_operand:SI 2 "" "") (match_dup 1))
6850 (set (match_operand:SI 3 "" "") (match_dup 1))]
6851 "/* @r{determine 1 does not overlap 0 and 2} */"
6852 [(set (match_dup 4) (match_dup 1))
6853 (set (match_dup 0) (match_dup 4))
6854 (set (match_dup 2) (match_dup 4))]
6855 (set (match_dup 3) (match_dup 4))]
6860 If we had not added the @code{(match_dup 4)} in the middle of the input
6861 sequence, it might have been the case that the register we chose at the
6862 beginning of the sequence is killed by the first or second @code{set}.
6866 @node Insn Attributes
6867 @section Instruction Attributes
6868 @cindex insn attributes
6869 @cindex instruction attributes
6871 In addition to describing the instruction supported by the target machine,
6872 the @file{md} file also defines a group of @dfn{attributes} and a set of
6873 values for each. Every generated insn is assigned a value for each attribute.
6874 One possible attribute would be the effect that the insn has on the machine's
6875 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
6876 to track the condition codes.
6879 * Defining Attributes:: Specifying attributes and their values.
6880 * Expressions:: Valid expressions for attribute values.
6881 * Tagging Insns:: Assigning attribute values to insns.
6882 * Attr Example:: An example of assigning attributes.
6883 * Insn Lengths:: Computing the length of insns.
6884 * Constant Attributes:: Defining attributes that are constant.
6885 * Delay Slots:: Defining delay slots required for a machine.
6886 * Processor pipeline description:: Specifying information for insn scheduling.
6891 @node Defining Attributes
6892 @subsection Defining Attributes and their Values
6893 @cindex defining attributes and their values
6894 @cindex attributes, defining
6897 The @code{define_attr} expression is used to define each attribute required
6898 by the target machine. It looks like:
6901 (define_attr @var{name} @var{list-of-values} @var{default})
6904 @var{name} is a string specifying the name of the attribute being defined.
6905 Some attributes are used in a special way by the rest of the compiler. The
6906 @code{enabled} attribute can be used to conditionally enable or disable
6907 insn alternatives (@pxref{Disable Insn Alternatives}). The @code{predicable}
6908 attribute, together with a suitable @code{define_cond_exec}
6909 (@pxref{Conditional Execution}), can be used to automatically generate
6910 conditional variants of instruction patterns. The compiler internally uses
6911 the names @code{ce_enabled} and @code{nonce_enabled}, so they should not be
6912 used elsewhere as alternative names.
6914 @var{list-of-values} is either a string that specifies a comma-separated
6915 list of values that can be assigned to the attribute, or a null string to
6916 indicate that the attribute takes numeric values.
6918 @var{default} is an attribute expression that gives the value of this
6919 attribute for insns that match patterns whose definition does not include
6920 an explicit value for this attribute. @xref{Attr Example}, for more
6921 information on the handling of defaults. @xref{Constant Attributes},
6922 for information on attributes that do not depend on any particular insn.
6925 For each defined attribute, a number of definitions are written to the
6926 @file{insn-attr.h} file. For cases where an explicit set of values is
6927 specified for an attribute, the following are defined:
6931 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
6934 An enumerated class is defined for @samp{attr_@var{name}} with
6935 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
6936 the attribute name and value are first converted to uppercase.
6939 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
6940 returns the attribute value for that insn.
6943 For example, if the following is present in the @file{md} file:
6946 (define_attr "type" "branch,fp,load,store,arith" @dots{})
6950 the following lines will be written to the file @file{insn-attr.h}.
6953 #define HAVE_ATTR_type
6954 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
6955 TYPE_STORE, TYPE_ARITH@};
6956 extern enum attr_type get_attr_type ();
6959 If the attribute takes numeric values, no @code{enum} type will be
6960 defined and the function to obtain the attribute's value will return
6963 There are attributes which are tied to a specific meaning. These
6964 attributes are not free to use for other purposes:
6968 The @code{length} attribute is used to calculate the length of emitted
6969 code chunks. This is especially important when verifying branch
6970 distances. @xref{Insn Lengths}.
6973 The @code{enabled} attribute can be defined to prevent certain
6974 alternatives of an insn definition from being used during code
6975 generation. @xref{Disable Insn Alternatives}.
6978 @findex define_enum_attr
6979 @anchor{define_enum_attr}
6980 Another way of defining an attribute is to use:
6983 (define_enum_attr "@var{attr}" "@var{enum}" @var{default})
6986 This works in just the same way as @code{define_attr}, except that
6987 the list of values is taken from a separate enumeration called
6988 @var{enum} (@pxref{define_enum}). This form allows you to use
6989 the same list of values for several attributes without having to
6990 repeat the list each time. For example:
6993 (define_enum "processor" [
6998 (define_enum_attr "arch" "processor"
6999 (const (symbol_ref "target_arch")))
7000 (define_enum_attr "tune" "processor"
7001 (const (symbol_ref "target_tune")))
7004 defines the same attributes as:
7007 (define_attr "arch" "model_a,model_b,@dots{}"
7008 (const (symbol_ref "target_arch")))
7009 (define_attr "tune" "model_a,model_b,@dots{}"
7010 (const (symbol_ref "target_tune")))
7013 but without duplicating the processor list. The second example defines two
7014 separate C enums (@code{attr_arch} and @code{attr_tune}) whereas the first
7015 defines a single C enum (@code{processor}).
7019 @subsection Attribute Expressions
7020 @cindex attribute expressions
7022 RTL expressions used to define attributes use the codes described above
7023 plus a few specific to attribute definitions, to be discussed below.
7024 Attribute value expressions must have one of the following forms:
7027 @cindex @code{const_int} and attributes
7028 @item (const_int @var{i})
7029 The integer @var{i} specifies the value of a numeric attribute. @var{i}
7030 must be non-negative.
7032 The value of a numeric attribute can be specified either with a
7033 @code{const_int}, or as an integer represented as a string in
7034 @code{const_string}, @code{eq_attr} (see below), @code{attr},
7035 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
7036 overrides on specific instructions (@pxref{Tagging Insns}).
7038 @cindex @code{const_string} and attributes
7039 @item (const_string @var{value})
7040 The string @var{value} specifies a constant attribute value.
7041 If @var{value} is specified as @samp{"*"}, it means that the default value of
7042 the attribute is to be used for the insn containing this expression.
7043 @samp{"*"} obviously cannot be used in the @var{default} expression
7044 of a @code{define_attr}.
7046 If the attribute whose value is being specified is numeric, @var{value}
7047 must be a string containing a non-negative integer (normally
7048 @code{const_int} would be used in this case). Otherwise, it must
7049 contain one of the valid values for the attribute.
7051 @cindex @code{if_then_else} and attributes
7052 @item (if_then_else @var{test} @var{true-value} @var{false-value})
7053 @var{test} specifies an attribute test, whose format is defined below.
7054 The value of this expression is @var{true-value} if @var{test} is true,
7055 otherwise it is @var{false-value}.
7057 @cindex @code{cond} and attributes
7058 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
7059 The first operand of this expression is a vector containing an even
7060 number of expressions and consisting of pairs of @var{test} and @var{value}
7061 expressions. The value of the @code{cond} expression is that of the
7062 @var{value} corresponding to the first true @var{test} expression. If
7063 none of the @var{test} expressions are true, the value of the @code{cond}
7064 expression is that of the @var{default} expression.
7067 @var{test} expressions can have one of the following forms:
7070 @cindex @code{const_int} and attribute tests
7071 @item (const_int @var{i})
7072 This test is true if @var{i} is nonzero and false otherwise.
7074 @cindex @code{not} and attributes
7075 @cindex @code{ior} and attributes
7076 @cindex @code{and} and attributes
7077 @item (not @var{test})
7078 @itemx (ior @var{test1} @var{test2})
7079 @itemx (and @var{test1} @var{test2})
7080 These tests are true if the indicated logical function is true.
7082 @cindex @code{match_operand} and attributes
7083 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
7084 This test is true if operand @var{n} of the insn whose attribute value
7085 is being determined has mode @var{m} (this part of the test is ignored
7086 if @var{m} is @code{VOIDmode}) and the function specified by the string
7087 @var{pred} returns a nonzero value when passed operand @var{n} and mode
7088 @var{m} (this part of the test is ignored if @var{pred} is the null
7091 The @var{constraints} operand is ignored and should be the null string.
7093 @cindex @code{match_test} and attributes
7094 @item (match_test @var{c-expr})
7095 The test is true if C expression @var{c-expr} is true. In non-constant
7096 attributes, @var{c-expr} has access to the following variables:
7100 The rtl instruction under test.
7101 @item which_alternative
7102 The @code{define_insn} alternative that @var{insn} matches.
7103 @xref{Output Statement}.
7105 An array of @var{insn}'s rtl operands.
7108 @var{c-expr} behaves like the condition in a C @code{if} statement,
7109 so there is no need to explicitly convert the expression into a boolean
7110 0 or 1 value. For example, the following two tests are equivalent:
7113 (match_test "x & 2")
7114 (match_test "(x & 2) != 0")
7117 @cindex @code{le} and attributes
7118 @cindex @code{leu} and attributes
7119 @cindex @code{lt} and attributes
7120 @cindex @code{gt} and attributes
7121 @cindex @code{gtu} and attributes
7122 @cindex @code{ge} and attributes
7123 @cindex @code{geu} and attributes
7124 @cindex @code{ne} and attributes
7125 @cindex @code{eq} and attributes
7126 @cindex @code{plus} and attributes
7127 @cindex @code{minus} and attributes
7128 @cindex @code{mult} and attributes
7129 @cindex @code{div} and attributes
7130 @cindex @code{mod} and attributes
7131 @cindex @code{abs} and attributes
7132 @cindex @code{neg} and attributes
7133 @cindex @code{ashift} and attributes
7134 @cindex @code{lshiftrt} and attributes
7135 @cindex @code{ashiftrt} and attributes
7136 @item (le @var{arith1} @var{arith2})
7137 @itemx (leu @var{arith1} @var{arith2})
7138 @itemx (lt @var{arith1} @var{arith2})
7139 @itemx (ltu @var{arith1} @var{arith2})
7140 @itemx (gt @var{arith1} @var{arith2})
7141 @itemx (gtu @var{arith1} @var{arith2})
7142 @itemx (ge @var{arith1} @var{arith2})
7143 @itemx (geu @var{arith1} @var{arith2})
7144 @itemx (ne @var{arith1} @var{arith2})
7145 @itemx (eq @var{arith1} @var{arith2})
7146 These tests are true if the indicated comparison of the two arithmetic
7147 expressions is true. Arithmetic expressions are formed with
7148 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
7149 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
7150 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
7153 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
7154 Lengths},for additional forms). @code{symbol_ref} is a string
7155 denoting a C expression that yields an @code{int} when evaluated by the
7156 @samp{get_attr_@dots{}} routine. It should normally be a global
7160 @item (eq_attr @var{name} @var{value})
7161 @var{name} is a string specifying the name of an attribute.
7163 @var{value} is a string that is either a valid value for attribute
7164 @var{name}, a comma-separated list of values, or @samp{!} followed by a
7165 value or list. If @var{value} does not begin with a @samp{!}, this
7166 test is true if the value of the @var{name} attribute of the current
7167 insn is in the list specified by @var{value}. If @var{value} begins
7168 with a @samp{!}, this test is true if the attribute's value is
7169 @emph{not} in the specified list.
7174 (eq_attr "type" "load,store")
7181 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
7184 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
7185 value of the compiler variable @code{which_alternative}
7186 (@pxref{Output Statement}) and the values must be small integers. For
7190 (eq_attr "alternative" "2,3")
7197 (ior (eq (symbol_ref "which_alternative") (const_int 2))
7198 (eq (symbol_ref "which_alternative") (const_int 3)))
7201 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
7202 where the value of the attribute being tested is known for all insns matching
7203 a particular pattern. This is by far the most common case.
7206 @item (attr_flag @var{name})
7207 The value of an @code{attr_flag} expression is true if the flag
7208 specified by @var{name} is true for the @code{insn} currently being
7211 @var{name} is a string specifying one of a fixed set of flags to test.
7212 Test the flags @code{forward} and @code{backward} to determine the
7213 direction of a conditional branch. Test the flags @code{very_likely},
7214 @code{likely}, @code{very_unlikely}, and @code{unlikely} to determine
7215 if a conditional branch is expected to be taken.
7217 If the @code{very_likely} flag is true, then the @code{likely} flag is also
7218 true. Likewise for the @code{very_unlikely} and @code{unlikely} flags.
7220 This example describes a conditional branch delay slot which
7221 can be nullified for forward branches that are taken (annul-true) or
7222 for backward branches which are not taken (annul-false).
7225 (define_delay (eq_attr "type" "cbranch")
7226 [(eq_attr "in_branch_delay" "true")
7227 (and (eq_attr "in_branch_delay" "true")
7228 (attr_flag "forward"))
7229 (and (eq_attr "in_branch_delay" "true")
7230 (attr_flag "backward"))])
7233 The @code{forward} and @code{backward} flags are false if the current
7234 @code{insn} being scheduled is not a conditional branch.
7236 The @code{very_likely} and @code{likely} flags are true if the
7237 @code{insn} being scheduled is not a conditional branch.
7238 The @code{very_unlikely} and @code{unlikely} flags are false if the
7239 @code{insn} being scheduled is not a conditional branch.
7241 @code{attr_flag} is only used during delay slot scheduling and has no
7242 meaning to other passes of the compiler.
7245 @item (attr @var{name})
7246 The value of another attribute is returned. This is most useful
7247 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
7248 produce more efficient code for non-numeric attributes.
7254 @subsection Assigning Attribute Values to Insns
7255 @cindex tagging insns
7256 @cindex assigning attribute values to insns
7258 The value assigned to an attribute of an insn is primarily determined by
7259 which pattern is matched by that insn (or which @code{define_peephole}
7260 generated it). Every @code{define_insn} and @code{define_peephole} can
7261 have an optional last argument to specify the values of attributes for
7262 matching insns. The value of any attribute not specified in a particular
7263 insn is set to the default value for that attribute, as specified in its
7264 @code{define_attr}. Extensive use of default values for attributes
7265 permits the specification of the values for only one or two attributes
7266 in the definition of most insn patterns, as seen in the example in the
7269 The optional last argument of @code{define_insn} and
7270 @code{define_peephole} is a vector of expressions, each of which defines
7271 the value for a single attribute. The most general way of assigning an
7272 attribute's value is to use a @code{set} expression whose first operand is an
7273 @code{attr} expression giving the name of the attribute being set. The
7274 second operand of the @code{set} is an attribute expression
7275 (@pxref{Expressions}) giving the value of the attribute.
7277 When the attribute value depends on the @samp{alternative} attribute
7278 (i.e., which is the applicable alternative in the constraint of the
7279 insn), the @code{set_attr_alternative} expression can be used. It
7280 allows the specification of a vector of attribute expressions, one for
7284 When the generality of arbitrary attribute expressions is not required,
7285 the simpler @code{set_attr} expression can be used, which allows
7286 specifying a string giving either a single attribute value or a list
7287 of attribute values, one for each alternative.
7289 The form of each of the above specifications is shown below. In each case,
7290 @var{name} is a string specifying the attribute to be set.
7293 @item (set_attr @var{name} @var{value-string})
7294 @var{value-string} is either a string giving the desired attribute value,
7295 or a string containing a comma-separated list giving the values for
7296 succeeding alternatives. The number of elements must match the number
7297 of alternatives in the constraint of the insn pattern.
7299 Note that it may be useful to specify @samp{*} for some alternative, in
7300 which case the attribute will assume its default value for insns matching
7303 @findex set_attr_alternative
7304 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
7305 Depending on the alternative of the insn, the value will be one of the
7306 specified values. This is a shorthand for using a @code{cond} with
7307 tests on the @samp{alternative} attribute.
7310 @item (set (attr @var{name}) @var{value})
7311 The first operand of this @code{set} must be the special RTL expression
7312 @code{attr}, whose sole operand is a string giving the name of the
7313 attribute being set. @var{value} is the value of the attribute.
7316 The following shows three different ways of representing the same
7317 attribute value specification:
7320 (set_attr "type" "load,store,arith")
7322 (set_attr_alternative "type"
7323 [(const_string "load") (const_string "store")
7324 (const_string "arith")])
7327 (cond [(eq_attr "alternative" "1") (const_string "load")
7328 (eq_attr "alternative" "2") (const_string "store")]
7329 (const_string "arith")))
7333 @findex define_asm_attributes
7334 The @code{define_asm_attributes} expression provides a mechanism to
7335 specify the attributes assigned to insns produced from an @code{asm}
7336 statement. It has the form:
7339 (define_asm_attributes [@var{attr-sets}])
7343 where @var{attr-sets} is specified the same as for both the
7344 @code{define_insn} and the @code{define_peephole} expressions.
7346 These values will typically be the ``worst case'' attribute values. For
7347 example, they might indicate that the condition code will be clobbered.
7349 A specification for a @code{length} attribute is handled specially. The
7350 way to compute the length of an @code{asm} insn is to multiply the
7351 length specified in the expression @code{define_asm_attributes} by the
7352 number of machine instructions specified in the @code{asm} statement,
7353 determined by counting the number of semicolons and newlines in the
7354 string. Therefore, the value of the @code{length} attribute specified
7355 in a @code{define_asm_attributes} should be the maximum possible length
7356 of a single machine instruction.
7361 @subsection Example of Attribute Specifications
7362 @cindex attribute specifications example
7363 @cindex attribute specifications
7365 The judicious use of defaulting is important in the efficient use of
7366 insn attributes. Typically, insns are divided into @dfn{types} and an
7367 attribute, customarily called @code{type}, is used to represent this
7368 value. This attribute is normally used only to define the default value
7369 for other attributes. An example will clarify this usage.
7371 Assume we have a RISC machine with a condition code and in which only
7372 full-word operations are performed in registers. Let us assume that we
7373 can divide all insns into loads, stores, (integer) arithmetic
7374 operations, floating point operations, and branches.
7376 Here we will concern ourselves with determining the effect of an insn on
7377 the condition code and will limit ourselves to the following possible
7378 effects: The condition code can be set unpredictably (clobbered), not
7379 be changed, be set to agree with the results of the operation, or only
7380 changed if the item previously set into the condition code has been
7383 Here is part of a sample @file{md} file for such a machine:
7386 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
7388 (define_attr "cc" "clobber,unchanged,set,change0"
7389 (cond [(eq_attr "type" "load")
7390 (const_string "change0")
7391 (eq_attr "type" "store,branch")
7392 (const_string "unchanged")
7393 (eq_attr "type" "arith")
7394 (if_then_else (match_operand:SI 0 "" "")
7395 (const_string "set")
7396 (const_string "clobber"))]
7397 (const_string "clobber")))
7400 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
7401 (match_operand:SI 1 "general_operand" "r,m,r"))]
7407 [(set_attr "type" "arith,load,store")])
7410 Note that we assume in the above example that arithmetic operations
7411 performed on quantities smaller than a machine word clobber the condition
7412 code since they will set the condition code to a value corresponding to the
7418 @subsection Computing the Length of an Insn
7419 @cindex insn lengths, computing
7420 @cindex computing the length of an insn
7422 For many machines, multiple types of branch instructions are provided, each
7423 for different length branch displacements. In most cases, the assembler
7424 will choose the correct instruction to use. However, when the assembler
7425 cannot do so, GCC can when a special attribute, the @code{length}
7426 attribute, is defined. This attribute must be defined to have numeric
7427 values by specifying a null string in its @code{define_attr}.
7429 In the case of the @code{length} attribute, two additional forms of
7430 arithmetic terms are allowed in test expressions:
7433 @cindex @code{match_dup} and attributes
7434 @item (match_dup @var{n})
7435 This refers to the address of operand @var{n} of the current insn, which
7436 must be a @code{label_ref}.
7438 @cindex @code{pc} and attributes
7440 This refers to the address of the @emph{current} insn. It might have
7441 been more consistent with other usage to make this the address of the
7442 @emph{next} insn but this would be confusing because the length of the
7443 current insn is to be computed.
7446 @cindex @code{addr_vec}, length of
7447 @cindex @code{addr_diff_vec}, length of
7448 For normal insns, the length will be determined by value of the
7449 @code{length} attribute. In the case of @code{addr_vec} and
7450 @code{addr_diff_vec} insn patterns, the length is computed as
7451 the number of vectors multiplied by the size of each vector.
7453 Lengths are measured in addressable storage units (bytes).
7455 The following macros can be used to refine the length computation:
7458 @findex ADJUST_INSN_LENGTH
7459 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
7460 If defined, modifies the length assigned to instruction @var{insn} as a
7461 function of the context in which it is used. @var{length} is an lvalue
7462 that contains the initially computed length of the insn and should be
7463 updated with the correct length of the insn.
7465 This macro will normally not be required. A case in which it is
7466 required is the ROMP@. On this machine, the size of an @code{addr_vec}
7467 insn must be increased by two to compensate for the fact that alignment
7471 @findex get_attr_length
7472 The routine that returns @code{get_attr_length} (the value of the
7473 @code{length} attribute) can be used by the output routine to
7474 determine the form of the branch instruction to be written, as the
7475 example below illustrates.
7477 As an example of the specification of variable-length branches, consider
7478 the IBM 360. If we adopt the convention that a register will be set to
7479 the starting address of a function, we can jump to labels within 4k of
7480 the start using a four-byte instruction. Otherwise, we need a six-byte
7481 sequence to load the address from memory and then branch to it.
7483 On such a machine, a pattern for a branch instruction might be specified
7489 (label_ref (match_operand 0 "" "")))]
7492 return (get_attr_length (insn) == 4
7493 ? "b %l0" : "l r15,=a(%l0); br r15");
7495 [(set (attr "length")
7496 (if_then_else (lt (match_dup 0) (const_int 4096))
7503 @node Constant Attributes
7504 @subsection Constant Attributes
7505 @cindex constant attributes
7507 A special form of @code{define_attr}, where the expression for the
7508 default value is a @code{const} expression, indicates an attribute that
7509 is constant for a given run of the compiler. Constant attributes may be
7510 used to specify which variety of processor is used. For example,
7513 (define_attr "cpu" "m88100,m88110,m88000"
7515 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
7516 (symbol_ref "TARGET_88110") (const_string "m88110")]
7517 (const_string "m88000"))))
7519 (define_attr "memory" "fast,slow"
7521 (if_then_else (symbol_ref "TARGET_FAST_MEM")
7522 (const_string "fast")
7523 (const_string "slow"))))
7526 The routine generated for constant attributes has no parameters as it
7527 does not depend on any particular insn. RTL expressions used to define
7528 the value of a constant attribute may use the @code{symbol_ref} form,
7529 but may not use either the @code{match_operand} form or @code{eq_attr}
7530 forms involving insn attributes.
7535 @subsection Delay Slot Scheduling
7536 @cindex delay slots, defining
7538 The insn attribute mechanism can be used to specify the requirements for
7539 delay slots, if any, on a target machine. An instruction is said to
7540 require a @dfn{delay slot} if some instructions that are physically
7541 after the instruction are executed as if they were located before it.
7542 Classic examples are branch and call instructions, which often execute
7543 the following instruction before the branch or call is performed.
7545 On some machines, conditional branch instructions can optionally
7546 @dfn{annul} instructions in the delay slot. This means that the
7547 instruction will not be executed for certain branch outcomes. Both
7548 instructions that annul if the branch is true and instructions that
7549 annul if the branch is false are supported.
7551 Delay slot scheduling differs from instruction scheduling in that
7552 determining whether an instruction needs a delay slot is dependent only
7553 on the type of instruction being generated, not on data flow between the
7554 instructions. See the next section for a discussion of data-dependent
7555 instruction scheduling.
7557 @findex define_delay
7558 The requirement of an insn needing one or more delay slots is indicated
7559 via the @code{define_delay} expression. It has the following form:
7562 (define_delay @var{test}
7563 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
7564 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
7568 @var{test} is an attribute test that indicates whether this
7569 @code{define_delay} applies to a particular insn. If so, the number of
7570 required delay slots is determined by the length of the vector specified
7571 as the second argument. An insn placed in delay slot @var{n} must
7572 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
7573 attribute test that specifies which insns may be annulled if the branch
7574 is true. Similarly, @var{annul-false-n} specifies which insns in the
7575 delay slot may be annulled if the branch is false. If annulling is not
7576 supported for that delay slot, @code{(nil)} should be coded.
7578 For example, in the common case where branch and call insns require
7579 a single delay slot, which may contain any insn other than a branch or
7580 call, the following would be placed in the @file{md} file:
7583 (define_delay (eq_attr "type" "branch,call")
7584 [(eq_attr "type" "!branch,call") (nil) (nil)])
7587 Multiple @code{define_delay} expressions may be specified. In this
7588 case, each such expression specifies different delay slot requirements
7589 and there must be no insn for which tests in two @code{define_delay}
7590 expressions are both true.
7592 For example, if we have a machine that requires one delay slot for branches
7593 but two for calls, no delay slot can contain a branch or call insn,
7594 and any valid insn in the delay slot for the branch can be annulled if the
7595 branch is true, we might represent this as follows:
7598 (define_delay (eq_attr "type" "branch")
7599 [(eq_attr "type" "!branch,call")
7600 (eq_attr "type" "!branch,call")
7603 (define_delay (eq_attr "type" "call")
7604 [(eq_attr "type" "!branch,call") (nil) (nil)
7605 (eq_attr "type" "!branch,call") (nil) (nil)])
7607 @c the above is *still* too long. --mew 4feb93
7611 @node Processor pipeline description
7612 @subsection Specifying processor pipeline description
7613 @cindex processor pipeline description
7614 @cindex processor functional units
7615 @cindex instruction latency time
7616 @cindex interlock delays
7617 @cindex data dependence delays
7618 @cindex reservation delays
7619 @cindex pipeline hazard recognizer
7620 @cindex automaton based pipeline description
7621 @cindex regular expressions
7622 @cindex deterministic finite state automaton
7623 @cindex automaton based scheduler
7627 To achieve better performance, most modern processors
7628 (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW}
7629 processors) have many @dfn{functional units} on which several
7630 instructions can be executed simultaneously. An instruction starts
7631 execution if its issue conditions are satisfied. If not, the
7632 instruction is stalled until its conditions are satisfied. Such
7633 @dfn{interlock (pipeline) delay} causes interruption of the fetching
7634 of successor instructions (or demands nop instructions, e.g.@: for some
7637 There are two major kinds of interlock delays in modern processors.
7638 The first one is a data dependence delay determining @dfn{instruction
7639 latency time}. The instruction execution is not started until all
7640 source data have been evaluated by prior instructions (there are more
7641 complex cases when the instruction execution starts even when the data
7642 are not available but will be ready in given time after the
7643 instruction execution start). Taking the data dependence delays into
7644 account is simple. The data dependence (true, output, and
7645 anti-dependence) delay between two instructions is given by a
7646 constant. In most cases this approach is adequate. The second kind
7647 of interlock delays is a reservation delay. The reservation delay
7648 means that two instructions under execution will be in need of shared
7649 processors resources, i.e.@: buses, internal registers, and/or
7650 functional units, which are reserved for some time. Taking this kind
7651 of delay into account is complex especially for modern @acronym{RISC}
7654 The task of exploiting more processor parallelism is solved by an
7655 instruction scheduler. For a better solution to this problem, the
7656 instruction scheduler has to have an adequate description of the
7657 processor parallelism (or @dfn{pipeline description}). GCC
7658 machine descriptions describe processor parallelism and functional
7659 unit reservations for groups of instructions with the aid of
7660 @dfn{regular expressions}.
7662 The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to
7663 figure out the possibility of the instruction issue by the processor
7664 on a given simulated processor cycle. The pipeline hazard recognizer is
7665 automatically generated from the processor pipeline description. The
7666 pipeline hazard recognizer generated from the machine description
7667 is based on a deterministic finite state automaton (@acronym{DFA}):
7668 the instruction issue is possible if there is a transition from one
7669 automaton state to another one. This algorithm is very fast, and
7670 furthermore, its speed is not dependent on processor
7671 complexity@footnote{However, the size of the automaton depends on
7672 processor complexity. To limit this effect, machine descriptions
7673 can split orthogonal parts of the machine description among several
7674 automata: but then, since each of these must be stepped independently,
7675 this does cause a small decrease in the algorithm's performance.}.
7677 @cindex automaton based pipeline description
7678 The rest of this section describes the directives that constitute
7679 an automaton-based processor pipeline description. The order of
7680 these constructions within the machine description file is not
7683 @findex define_automaton
7684 @cindex pipeline hazard recognizer
7685 The following optional construction describes names of automata
7686 generated and used for the pipeline hazards recognition. Sometimes
7687 the generated finite state automaton used by the pipeline hazard
7688 recognizer is large. If we use more than one automaton and bind functional
7689 units to the automata, the total size of the automata is usually
7690 less than the size of the single automaton. If there is no one such
7691 construction, only one finite state automaton is generated.
7694 (define_automaton @var{automata-names})
7697 @var{automata-names} is a string giving names of the automata. The
7698 names are separated by commas. All the automata should have unique names.
7699 The automaton name is used in the constructions @code{define_cpu_unit} and
7700 @code{define_query_cpu_unit}.
7702 @findex define_cpu_unit
7703 @cindex processor functional units
7704 Each processor functional unit used in the description of instruction
7705 reservations should be described by the following construction.
7708 (define_cpu_unit @var{unit-names} [@var{automaton-name}])
7711 @var{unit-names} is a string giving the names of the functional units
7712 separated by commas. Don't use name @samp{nothing}, it is reserved
7715 @var{automaton-name} is a string giving the name of the automaton with
7716 which the unit is bound. The automaton should be described in
7717 construction @code{define_automaton}. You should give
7718 @dfn{automaton-name}, if there is a defined automaton.
7720 The assignment of units to automata are constrained by the uses of the
7721 units in insn reservations. The most important constraint is: if a
7722 unit reservation is present on a particular cycle of an alternative
7723 for an insn reservation, then some unit from the same automaton must
7724 be present on the same cycle for the other alternatives of the insn
7725 reservation. The rest of the constraints are mentioned in the
7726 description of the subsequent constructions.
7728 @findex define_query_cpu_unit
7729 @cindex querying function unit reservations
7730 The following construction describes CPU functional units analogously
7731 to @code{define_cpu_unit}. The reservation of such units can be
7732 queried for an automaton state. The instruction scheduler never
7733 queries reservation of functional units for given automaton state. So
7734 as a rule, you don't need this construction. This construction could
7735 be used for future code generation goals (e.g.@: to generate
7736 @acronym{VLIW} insn templates).
7739 (define_query_cpu_unit @var{unit-names} [@var{automaton-name}])
7742 @var{unit-names} is a string giving names of the functional units
7743 separated by commas.
7745 @var{automaton-name} is a string giving the name of the automaton with
7746 which the unit is bound.
7748 @findex define_insn_reservation
7749 @cindex instruction latency time
7750 @cindex regular expressions
7752 The following construction is the major one to describe pipeline
7753 characteristics of an instruction.
7756 (define_insn_reservation @var{insn-name} @var{default_latency}
7757 @var{condition} @var{regexp})
7760 @var{default_latency} is a number giving latency time of the
7761 instruction. There is an important difference between the old
7762 description and the automaton based pipeline description. The latency
7763 time is used for all dependencies when we use the old description. In
7764 the automaton based pipeline description, the given latency time is only
7765 used for true dependencies. The cost of anti-dependencies is always
7766 zero and the cost of output dependencies is the difference between
7767 latency times of the producing and consuming insns (if the difference
7768 is negative, the cost is considered to be zero). You can always
7769 change the default costs for any description by using the target hook
7770 @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}).
7772 @var{insn-name} is a string giving the internal name of the insn. The
7773 internal names are used in constructions @code{define_bypass} and in
7774 the automaton description file generated for debugging. The internal
7775 name has nothing in common with the names in @code{define_insn}. It is a
7776 good practice to use insn classes described in the processor manual.
7778 @var{condition} defines what RTL insns are described by this
7779 construction. You should remember that you will be in trouble if
7780 @var{condition} for two or more different
7781 @code{define_insn_reservation} constructions is TRUE for an insn. In
7782 this case what reservation will be used for the insn is not defined.
7783 Such cases are not checked during generation of the pipeline hazards
7784 recognizer because in general recognizing that two conditions may have
7785 the same value is quite difficult (especially if the conditions
7786 contain @code{symbol_ref}). It is also not checked during the
7787 pipeline hazard recognizer work because it would slow down the
7788 recognizer considerably.
7790 @var{regexp} is a string describing the reservation of the cpu's functional
7791 units by the instruction. The reservations are described by a regular
7792 expression according to the following syntax:
7795 regexp = regexp "," oneof
7798 oneof = oneof "|" allof
7801 allof = allof "+" repeat
7804 repeat = element "*" number
7807 element = cpu_function_unit_name
7816 @samp{,} is used for describing the start of the next cycle in
7820 @samp{|} is used for describing a reservation described by the first
7821 regular expression @strong{or} a reservation described by the second
7822 regular expression @strong{or} etc.
7825 @samp{+} is used for describing a reservation described by the first
7826 regular expression @strong{and} a reservation described by the
7827 second regular expression @strong{and} etc.
7830 @samp{*} is used for convenience and simply means a sequence in which
7831 the regular expression are repeated @var{number} times with cycle
7832 advancing (see @samp{,}).
7835 @samp{cpu_function_unit_name} denotes reservation of the named
7839 @samp{reservation_name} --- see description of construction
7840 @samp{define_reservation}.
7843 @samp{nothing} denotes no unit reservations.
7846 @findex define_reservation
7847 Sometimes unit reservations for different insns contain common parts.
7848 In such case, you can simplify the pipeline description by describing
7849 the common part by the following construction
7852 (define_reservation @var{reservation-name} @var{regexp})
7855 @var{reservation-name} is a string giving name of @var{regexp}.
7856 Functional unit names and reservation names are in the same name
7857 space. So the reservation names should be different from the
7858 functional unit names and can not be the reserved name @samp{nothing}.
7860 @findex define_bypass
7861 @cindex instruction latency time
7863 The following construction is used to describe exceptions in the
7864 latency time for given instruction pair. This is so called bypasses.
7867 (define_bypass @var{number} @var{out_insn_names} @var{in_insn_names}
7871 @var{number} defines when the result generated by the instructions
7872 given in string @var{out_insn_names} will be ready for the
7873 instructions given in string @var{in_insn_names}. Each of these
7874 strings is a comma-separated list of filename-style globs and
7875 they refer to the names of @code{define_insn_reservation}s.
7878 (define_bypass 1 "cpu1_load_*, cpu1_store_*" "cpu1_load_*")
7880 defines a bypass between instructions that start with
7881 @samp{cpu1_load_} or @samp{cpu1_store_} and those that start with
7884 @var{guard} is an optional string giving the name of a C function which
7885 defines an additional guard for the bypass. The function will get the
7886 two insns as parameters. If the function returns zero the bypass will
7887 be ignored for this case. The additional guard is necessary to
7888 recognize complicated bypasses, e.g.@: when the consumer is only an address
7889 of insn @samp{store} (not a stored value).
7891 If there are more one bypass with the same output and input insns, the
7892 chosen bypass is the first bypass with a guard in description whose
7893 guard function returns nonzero. If there is no such bypass, then
7894 bypass without the guard function is chosen.
7896 @findex exclusion_set
7897 @findex presence_set
7898 @findex final_presence_set
7900 @findex final_absence_set
7903 The following five constructions are usually used to describe
7904 @acronym{VLIW} processors, or more precisely, to describe a placement
7905 of small instructions into @acronym{VLIW} instruction slots. They
7906 can be used for @acronym{RISC} processors, too.
7909 (exclusion_set @var{unit-names} @var{unit-names})
7910 (presence_set @var{unit-names} @var{patterns})
7911 (final_presence_set @var{unit-names} @var{patterns})
7912 (absence_set @var{unit-names} @var{patterns})
7913 (final_absence_set @var{unit-names} @var{patterns})
7916 @var{unit-names} is a string giving names of functional units
7917 separated by commas.
7919 @var{patterns} is a string giving patterns of functional units
7920 separated by comma. Currently pattern is one unit or units
7921 separated by white-spaces.
7923 The first construction (@samp{exclusion_set}) means that each
7924 functional unit in the first string can not be reserved simultaneously
7925 with a unit whose name is in the second string and vice versa. For
7926 example, the construction is useful for describing processors
7927 (e.g.@: some SPARC processors) with a fully pipelined floating point
7928 functional unit which can execute simultaneously only single floating
7929 point insns or only double floating point insns.
7931 The second construction (@samp{presence_set}) means that each
7932 functional unit in the first string can not be reserved unless at
7933 least one of pattern of units whose names are in the second string is
7934 reserved. This is an asymmetric relation. For example, it is useful
7935 for description that @acronym{VLIW} @samp{slot1} is reserved after
7936 @samp{slot0} reservation. We could describe it by the following
7940 (presence_set "slot1" "slot0")
7943 Or @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0}
7944 reservation. In this case we could write
7947 (presence_set "slot1" "slot0 b0")
7950 The third construction (@samp{final_presence_set}) is analogous to
7951 @samp{presence_set}. The difference between them is when checking is
7952 done. When an instruction is issued in given automaton state
7953 reflecting all current and planned unit reservations, the automaton
7954 state is changed. The first state is a source state, the second one
7955 is a result state. Checking for @samp{presence_set} is done on the
7956 source state reservation, checking for @samp{final_presence_set} is
7957 done on the result reservation. This construction is useful to
7958 describe a reservation which is actually two subsequent reservations.
7959 For example, if we use
7962 (presence_set "slot1" "slot0")
7965 the following insn will be never issued (because @samp{slot1} requires
7966 @samp{slot0} which is absent in the source state).
7969 (define_reservation "insn_and_nop" "slot0 + slot1")
7972 but it can be issued if we use analogous @samp{final_presence_set}.
7974 The forth construction (@samp{absence_set}) means that each functional
7975 unit in the first string can be reserved only if each pattern of units
7976 whose names are in the second string is not reserved. This is an
7977 asymmetric relation (actually @samp{exclusion_set} is analogous to
7978 this one but it is symmetric). For example it might be useful in a
7979 @acronym{VLIW} description to say that @samp{slot0} cannot be reserved
7980 after either @samp{slot1} or @samp{slot2} have been reserved. This
7981 can be described as:
7984 (absence_set "slot0" "slot1, slot2")
7987 Or @samp{slot2} can not be reserved if @samp{slot0} and unit @samp{b0}
7988 are reserved or @samp{slot1} and unit @samp{b1} are reserved. In
7989 this case we could write
7992 (absence_set "slot2" "slot0 b0, slot1 b1")
7995 All functional units mentioned in a set should belong to the same
7998 The last construction (@samp{final_absence_set}) is analogous to
7999 @samp{absence_set} but checking is done on the result (state)
8000 reservation. See comments for @samp{final_presence_set}.
8002 @findex automata_option
8003 @cindex deterministic finite state automaton
8004 @cindex nondeterministic finite state automaton
8005 @cindex finite state automaton minimization
8006 You can control the generator of the pipeline hazard recognizer with
8007 the following construction.
8010 (automata_option @var{options})
8013 @var{options} is a string giving options which affect the generated
8014 code. Currently there are the following options:
8018 @dfn{no-minimization} makes no minimization of the automaton. This is
8019 only worth to do when we are debugging the description and need to
8020 look more accurately at reservations of states.
8023 @dfn{time} means printing time statistics about the generation of
8027 @dfn{stats} means printing statistics about the generated automata
8028 such as the number of DFA states, NDFA states and arcs.
8031 @dfn{v} means a generation of the file describing the result automata.
8032 The file has suffix @samp{.dfa} and can be used for the description
8033 verification and debugging.
8036 @dfn{w} means a generation of warning instead of error for
8037 non-critical errors.
8040 @dfn{no-comb-vect} prevents the automaton generator from generating
8041 two data structures and comparing them for space efficiency. Using
8042 a comb vector to represent transitions may be better, but it can be
8043 very expensive to construct. This option is useful if the build
8044 process spends an unacceptably long time in genautomata.
8047 @dfn{ndfa} makes nondeterministic finite state automata. This affects
8048 the treatment of operator @samp{|} in the regular expressions. The
8049 usual treatment of the operator is to try the first alternative and,
8050 if the reservation is not possible, the second alternative. The
8051 nondeterministic treatment means trying all alternatives, some of them
8052 may be rejected by reservations in the subsequent insns.
8055 @dfn{collapse-ndfa} modifies the behaviour of the generator when
8056 producing an automaton. An additional state transition to collapse a
8057 nondeterministic @acronym{NDFA} state to a deterministic @acronym{DFA}
8058 state is generated. It can be triggered by passing @code{const0_rtx} to
8059 state_transition. In such an automaton, cycle advance transitions are
8060 available only for these collapsed states. This option is useful for
8061 ports that want to use the @code{ndfa} option, but also want to use
8062 @code{define_query_cpu_unit} to assign units to insns issued in a cycle.
8065 @dfn{progress} means output of a progress bar showing how many states
8066 were generated so far for automaton being processed. This is useful
8067 during debugging a @acronym{DFA} description. If you see too many
8068 generated states, you could interrupt the generator of the pipeline
8069 hazard recognizer and try to figure out a reason for generation of the
8073 As an example, consider a superscalar @acronym{RISC} machine which can
8074 issue three insns (two integer insns and one floating point insn) on
8075 the cycle but can finish only two insns. To describe this, we define
8076 the following functional units.
8079 (define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline")
8080 (define_cpu_unit "port0, port1")
8083 All simple integer insns can be executed in any integer pipeline and
8084 their result is ready in two cycles. The simple integer insns are
8085 issued into the first pipeline unless it is reserved, otherwise they
8086 are issued into the second pipeline. Integer division and
8087 multiplication insns can be executed only in the second integer
8088 pipeline and their results are ready correspondingly in 8 and 4
8089 cycles. The integer division is not pipelined, i.e.@: the subsequent
8090 integer division insn can not be issued until the current division
8091 insn finished. Floating point insns are fully pipelined and their
8092 results are ready in 3 cycles. Where the result of a floating point
8093 insn is used by an integer insn, an additional delay of one cycle is
8094 incurred. To describe all of this we could specify
8097 (define_cpu_unit "div")
8099 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
8100 "(i0_pipeline | i1_pipeline), (port0 | port1)")
8102 (define_insn_reservation "mult" 4 (eq_attr "type" "mult")
8103 "i1_pipeline, nothing*2, (port0 | port1)")
8105 (define_insn_reservation "div" 8 (eq_attr "type" "div")
8106 "i1_pipeline, div*7, div + (port0 | port1)")
8108 (define_insn_reservation "float" 3 (eq_attr "type" "float")
8109 "f_pipeline, nothing, (port0 | port1))
8111 (define_bypass 4 "float" "simple,mult,div")
8114 To simplify the description we could describe the following reservation
8117 (define_reservation "finish" "port0|port1")
8120 and use it in all @code{define_insn_reservation} as in the following
8124 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
8125 "(i0_pipeline | i1_pipeline), finish")
8131 @node Conditional Execution
8132 @section Conditional Execution
8133 @cindex conditional execution
8136 A number of architectures provide for some form of conditional
8137 execution, or predication. The hallmark of this feature is the
8138 ability to nullify most of the instructions in the instruction set.
8139 When the instruction set is large and not entirely symmetric, it
8140 can be quite tedious to describe these forms directly in the
8141 @file{.md} file. An alternative is the @code{define_cond_exec} template.
8143 @findex define_cond_exec
8146 [@var{predicate-pattern}]
8148 "@var{output-template}")
8151 @var{predicate-pattern} is the condition that must be true for the
8152 insn to be executed at runtime and should match a relational operator.
8153 One can use @code{match_operator} to match several relational operators
8154 at once. Any @code{match_operand} operands must have no more than one
8157 @var{condition} is a C expression that must be true for the generated
8160 @findex current_insn_predicate
8161 @var{output-template} is a string similar to the @code{define_insn}
8162 output template (@pxref{Output Template}), except that the @samp{*}
8163 and @samp{@@} special cases do not apply. This is only useful if the
8164 assembly text for the predicate is a simple prefix to the main insn.
8165 In order to handle the general case, there is a global variable
8166 @code{current_insn_predicate} that will contain the entire predicate
8167 if the current insn is predicated, and will otherwise be @code{NULL}.
8169 When @code{define_cond_exec} is used, an implicit reference to
8170 the @code{predicable} instruction attribute is made.
8171 @xref{Insn Attributes}. This attribute must be a boolean (i.e.@: have
8172 exactly two elements in its @var{list-of-values}), with the possible
8173 values being @code{no} and @code{yes}. The default and all uses in
8174 the insns must be a simple constant, not a complex expressions. It
8175 may, however, depend on the alternative, by using a comma-separated
8176 list of values. If that is the case, the port should also define an
8177 @code{enabled} attribute (@pxref{Disable Insn Alternatives}), which
8178 should also allow only @code{no} and @code{yes} as its values.
8180 For each @code{define_insn} for which the @code{predicable}
8181 attribute is true, a new @code{define_insn} pattern will be
8182 generated that matches a predicated version of the instruction.
8186 (define_insn "addsi"
8187 [(set (match_operand:SI 0 "register_operand" "r")
8188 (plus:SI (match_operand:SI 1 "register_operand" "r")
8189 (match_operand:SI 2 "register_operand" "r")))]
8194 [(ne (match_operand:CC 0 "register_operand" "c")
8201 generates a new pattern
8206 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
8207 (set (match_operand:SI 0 "register_operand" "r")
8208 (plus:SI (match_operand:SI 1 "register_operand" "r")
8209 (match_operand:SI 2 "register_operand" "r"))))]
8210 "(@var{test2}) && (@var{test1})"
8211 "(%3) add %2,%1,%0")
8216 @node Constant Definitions
8217 @section Constant Definitions
8218 @cindex constant definitions
8219 @findex define_constants
8221 Using literal constants inside instruction patterns reduces legibility and
8222 can be a maintenance problem.
8224 To overcome this problem, you may use the @code{define_constants}
8225 expression. It contains a vector of name-value pairs. From that
8226 point on, wherever any of the names appears in the MD file, it is as
8227 if the corresponding value had been written instead. You may use
8228 @code{define_constants} multiple times; each appearance adds more
8229 constants to the table. It is an error to redefine a constant with
8232 To come back to the a29k load multiple example, instead of
8236 [(match_parallel 0 "load_multiple_operation"
8237 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
8238 (match_operand:SI 2 "memory_operand" "m"))
8240 (clobber (reg:SI 179))])]
8256 [(match_parallel 0 "load_multiple_operation"
8257 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
8258 (match_operand:SI 2 "memory_operand" "m"))
8260 (clobber (reg:SI R_CR))])]
8265 The constants that are defined with a define_constant are also output
8266 in the insn-codes.h header file as #defines.
8268 @cindex enumerations
8269 @findex define_c_enum
8270 You can also use the machine description file to define enumerations.
8271 Like the constants defined by @code{define_constant}, these enumerations
8272 are visible to both the machine description file and the main C code.
8274 The syntax is as follows:
8277 (define_c_enum "@var{name}" [
8285 This definition causes the equivalent of the following C code to appear
8286 in @file{insn-constants.h}:
8293 @var{valuen} = @var{n}
8295 #define NUM_@var{cname}_VALUES (@var{n} + 1)
8298 where @var{cname} is the capitalized form of @var{name}.
8299 It also makes each @var{valuei} available in the machine description
8300 file, just as if it had been declared with:
8303 (define_constants [(@var{valuei} @var{i})])
8306 Each @var{valuei} is usually an upper-case identifier and usually
8307 begins with @var{cname}.
8309 You can split the enumeration definition into as many statements as
8310 you like. The above example is directly equivalent to:
8313 (define_c_enum "@var{name}" [@var{value0}])
8314 (define_c_enum "@var{name}" [@var{value1}])
8316 (define_c_enum "@var{name}" [@var{valuen}])
8319 Splitting the enumeration helps to improve the modularity of each
8320 individual @code{.md} file. For example, if a port defines its
8321 synchronization instructions in a separate @file{sync.md} file,
8322 it is convenient to define all synchronization-specific enumeration
8323 values in @file{sync.md} rather than in the main @file{.md} file.
8325 Some enumeration names have special significance to GCC:
8329 @findex unspec_volatile
8330 If an enumeration called @code{unspecv} is defined, GCC will use it
8331 when printing out @code{unspec_volatile} expressions. For example:
8334 (define_c_enum "unspecv" [
8339 causes GCC to print @samp{(unspec_volatile @dots{} 0)} as:
8342 (unspec_volatile ... UNSPECV_BLOCKAGE)
8347 If an enumeration called @code{unspec} is defined, GCC will use
8348 it when printing out @code{unspec} expressions. GCC will also use
8349 it when printing out @code{unspec_volatile} expressions unless an
8350 @code{unspecv} enumeration is also defined. You can therefore
8351 decide whether to keep separate enumerations for volatile and
8352 non-volatile expressions or whether to use the same enumeration
8357 @anchor{define_enum}
8358 Another way of defining an enumeration is to use @code{define_enum}:
8361 (define_enum "@var{name}" [
8369 This directive implies:
8372 (define_c_enum "@var{name}" [
8373 @var{cname}_@var{cvalue0}
8374 @var{cname}_@var{cvalue1}
8376 @var{cname}_@var{cvaluen}
8380 @findex define_enum_attr
8381 where @var{cvaluei} is the capitalized form of @var{valuei}.
8382 However, unlike @code{define_c_enum}, the enumerations defined
8383 by @code{define_enum} can be used in attribute specifications
8384 (@pxref{define_enum_attr}).
8389 @cindex iterators in @file{.md} files
8391 Ports often need to define similar patterns for more than one machine
8392 mode or for more than one rtx code. GCC provides some simple iterator
8393 facilities to make this process easier.
8396 * Mode Iterators:: Generating variations of patterns for different modes.
8397 * Code Iterators:: Doing the same for codes.
8400 @node Mode Iterators
8401 @subsection Mode Iterators
8402 @cindex mode iterators in @file{.md} files
8404 Ports often need to define similar patterns for two or more different modes.
8409 If a processor has hardware support for both single and double
8410 floating-point arithmetic, the @code{SFmode} patterns tend to be
8411 very similar to the @code{DFmode} ones.
8414 If a port uses @code{SImode} pointers in one configuration and
8415 @code{DImode} pointers in another, it will usually have very similar
8416 @code{SImode} and @code{DImode} patterns for manipulating pointers.
8419 Mode iterators allow several patterns to be instantiated from one
8420 @file{.md} file template. They can be used with any type of
8421 rtx-based construct, such as a @code{define_insn},
8422 @code{define_split}, or @code{define_peephole2}.
8425 * Defining Mode Iterators:: Defining a new mode iterator.
8426 * Substitutions:: Combining mode iterators with substitutions
8427 * Examples:: Examples
8430 @node Defining Mode Iterators
8431 @subsubsection Defining Mode Iterators
8432 @findex define_mode_iterator
8434 The syntax for defining a mode iterator is:
8437 (define_mode_iterator @var{name} [(@var{mode1} "@var{cond1}") @dots{} (@var{moden} "@var{condn}")])
8440 This allows subsequent @file{.md} file constructs to use the mode suffix
8441 @code{:@var{name}}. Every construct that does so will be expanded
8442 @var{n} times, once with every use of @code{:@var{name}} replaced by
8443 @code{:@var{mode1}}, once with every use replaced by @code{:@var{mode2}},
8444 and so on. In the expansion for a particular @var{modei}, every
8445 C condition will also require that @var{condi} be true.
8450 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
8453 defines a new mode suffix @code{:P}. Every construct that uses
8454 @code{:P} will be expanded twice, once with every @code{:P} replaced
8455 by @code{:SI} and once with every @code{:P} replaced by @code{:DI}.
8456 The @code{:SI} version will only apply if @code{Pmode == SImode} and
8457 the @code{:DI} version will only apply if @code{Pmode == DImode}.
8459 As with other @file{.md} conditions, an empty string is treated
8460 as ``always true''. @code{(@var{mode} "")} can also be abbreviated
8461 to @code{@var{mode}}. For example:
8464 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
8467 means that the @code{:DI} expansion only applies if @code{TARGET_64BIT}
8468 but that the @code{:SI} expansion has no such constraint.
8470 Iterators are applied in the order they are defined. This can be
8471 significant if two iterators are used in a construct that requires
8472 substitutions. @xref{Substitutions}.
8475 @subsubsection Substitution in Mode Iterators
8476 @findex define_mode_attr
8478 If an @file{.md} file construct uses mode iterators, each version of the
8479 construct will often need slightly different strings or modes. For
8484 When a @code{define_expand} defines several @code{add@var{m}3} patterns
8485 (@pxref{Standard Names}), each expander will need to use the
8486 appropriate mode name for @var{m}.
8489 When a @code{define_insn} defines several instruction patterns,
8490 each instruction will often use a different assembler mnemonic.
8493 When a @code{define_insn} requires operands with different modes,
8494 using an iterator for one of the operand modes usually requires a specific
8495 mode for the other operand(s).
8498 GCC supports such variations through a system of ``mode attributes''.
8499 There are two standard attributes: @code{mode}, which is the name of
8500 the mode in lower case, and @code{MODE}, which is the same thing in
8501 upper case. You can define other attributes using:
8504 (define_mode_attr @var{name} [(@var{mode1} "@var{value1}") @dots{} (@var{moden} "@var{valuen}")])
8507 where @var{name} is the name of the attribute and @var{valuei}
8508 is the value associated with @var{modei}.
8510 When GCC replaces some @var{:iterator} with @var{:mode}, it will scan
8511 each string and mode in the pattern for sequences of the form
8512 @code{<@var{iterator}:@var{attr}>}, where @var{attr} is the name of a
8513 mode attribute. If the attribute is defined for @var{mode}, the whole
8514 @code{<@dots{}>} sequence will be replaced by the appropriate attribute
8517 For example, suppose an @file{.md} file has:
8520 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
8521 (define_mode_attr load [(SI "lw") (DI "ld")])
8524 If one of the patterns that uses @code{:P} contains the string
8525 @code{"<P:load>\t%0,%1"}, the @code{SI} version of that pattern
8526 will use @code{"lw\t%0,%1"} and the @code{DI} version will use
8529 Here is an example of using an attribute for a mode:
8532 (define_mode_iterator LONG [SI DI])
8533 (define_mode_attr SHORT [(SI "HI") (DI "SI")])
8534 (define_insn @dots{}
8535 (sign_extend:LONG (match_operand:<LONG:SHORT> @dots{})) @dots{})
8538 The @code{@var{iterator}:} prefix may be omitted, in which case the
8539 substitution will be attempted for every iterator expansion.
8542 @subsubsection Mode Iterator Examples
8544 Here is an example from the MIPS port. It defines the following
8545 modes and attributes (among others):
8548 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
8549 (define_mode_attr d [(SI "") (DI "d")])
8552 and uses the following template to define both @code{subsi3}
8556 (define_insn "sub<mode>3"
8557 [(set (match_operand:GPR 0 "register_operand" "=d")
8558 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
8559 (match_operand:GPR 2 "register_operand" "d")))]
8562 [(set_attr "type" "arith")
8563 (set_attr "mode" "<MODE>")])
8566 This is exactly equivalent to:
8569 (define_insn "subsi3"
8570 [(set (match_operand:SI 0 "register_operand" "=d")
8571 (minus:SI (match_operand:SI 1 "register_operand" "d")
8572 (match_operand:SI 2 "register_operand" "d")))]
8575 [(set_attr "type" "arith")
8576 (set_attr "mode" "SI")])
8578 (define_insn "subdi3"
8579 [(set (match_operand:DI 0 "register_operand" "=d")
8580 (minus:DI (match_operand:DI 1 "register_operand" "d")
8581 (match_operand:DI 2 "register_operand" "d")))]
8584 [(set_attr "type" "arith")
8585 (set_attr "mode" "DI")])
8588 @node Code Iterators
8589 @subsection Code Iterators
8590 @cindex code iterators in @file{.md} files
8591 @findex define_code_iterator
8592 @findex define_code_attr
8594 Code iterators operate in a similar way to mode iterators. @xref{Mode Iterators}.
8599 (define_code_iterator @var{name} [(@var{code1} "@var{cond1}") @dots{} (@var{coden} "@var{condn}")])
8602 defines a pseudo rtx code @var{name} that can be instantiated as
8603 @var{codei} if condition @var{condi} is true. Each @var{codei}
8604 must have the same rtx format. @xref{RTL Classes}.
8606 As with mode iterators, each pattern that uses @var{name} will be
8607 expanded @var{n} times, once with all uses of @var{name} replaced by
8608 @var{code1}, once with all uses replaced by @var{code2}, and so on.
8609 @xref{Defining Mode Iterators}.
8611 It is possible to define attributes for codes as well as for modes.
8612 There are two standard code attributes: @code{code}, the name of the
8613 code in lower case, and @code{CODE}, the name of the code in upper case.
8614 Other attributes are defined using:
8617 (define_code_attr @var{name} [(@var{code1} "@var{value1}") @dots{} (@var{coden} "@var{valuen}")])
8620 Here's an example of code iterators in action, taken from the MIPS port:
8623 (define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
8624 eq ne gt ge lt le gtu geu ltu leu])
8626 (define_expand "b<code>"
8628 (if_then_else (any_cond:CC (cc0)
8630 (label_ref (match_operand 0 ""))
8634 gen_conditional_branch (operands, <CODE>);
8639 This is equivalent to:
8642 (define_expand "bunordered"
8644 (if_then_else (unordered:CC (cc0)
8646 (label_ref (match_operand 0 ""))
8650 gen_conditional_branch (operands, UNORDERED);
8654 (define_expand "bordered"
8656 (if_then_else (ordered:CC (cc0)
8658 (label_ref (match_operand 0 ""))
8662 gen_conditional_branch (operands, ORDERED);