1 @c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 1999, 2000, 2001,
2 @c 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
3 @c Free Software Foundation, Inc.
4 @c This is part of the GCC manual.
5 @c For copying conditions, see the file gcc.texi.
9 @chapter Machine Descriptions
10 @cindex machine descriptions
12 A machine description has two parts: a file of instruction patterns
13 (@file{.md} file) and a C header file of macro definitions.
15 The @file{.md} file for a target machine contains a pattern for each
16 instruction that the target machine supports (or at least each instruction
17 that is worth telling the compiler about). It may also contain comments.
18 A semicolon causes the rest of the line to be a comment, unless the semicolon
19 is inside a quoted string.
21 See the next chapter for information on the C header file.
24 * Overview:: How the machine description is used.
25 * Patterns:: How to write instruction patterns.
26 * Example:: An explained example of a @code{define_insn} pattern.
27 * RTL Template:: The RTL template defines what insns match a pattern.
28 * Output Template:: The output template says how to make assembler code
30 * Output Statement:: For more generality, write C code to output
32 * Predicates:: Controlling what kinds of operands can be used
34 * Constraints:: Fine-tuning operand selection.
35 * Standard Names:: Names mark patterns to use for code generation.
36 * Pattern Ordering:: When the order of patterns makes a difference.
37 * Dependent Patterns:: Having one pattern may make you need another.
38 * Jump Patterns:: Special considerations for patterns for jump insns.
39 * Looping Patterns:: How to define patterns for special looping insns.
40 * Insn Canonicalizations::Canonicalization of Instructions
41 * Expander Definitions::Generating a sequence of several RTL insns
42 for a standard operation.
43 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
44 * Including Patterns:: Including Patterns in Machine Descriptions.
45 * Peephole Definitions::Defining machine-specific peephole optimizations.
46 * Insn Attributes:: Specifying the value of attributes for generated insns.
47 * Conditional Execution::Generating @code{define_insn} patterns for
49 * Constant Definitions::Defining symbolic constants that can be used in the
51 * Iterators:: Using iterators to generate patterns from a template.
55 @section Overview of How the Machine Description is Used
57 There are three main conversions that happen in the compiler:
62 The front end reads the source code and builds a parse tree.
65 The parse tree is used to generate an RTL insn list based on named
69 The insn list is matched against the RTL templates to produce assembler
74 For the generate pass, only the names of the insns matter, from either a
75 named @code{define_insn} or a @code{define_expand}. The compiler will
76 choose the pattern with the right name and apply the operands according
77 to the documentation later in this chapter, without regard for the RTL
78 template or operand constraints. Note that the names the compiler looks
79 for are hard-coded in the compiler---it will ignore unnamed patterns and
80 patterns with names it doesn't know about, but if you don't provide a
81 named pattern it needs, it will abort.
83 If a @code{define_insn} is used, the template given is inserted into the
84 insn list. If a @code{define_expand} is used, one of three things
85 happens, based on the condition logic. The condition logic may manually
86 create new insns for the insn list, say via @code{emit_insn()}, and
87 invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
88 compiler to use an alternate way of performing that task. If it invokes
89 neither @code{DONE} nor @code{FAIL}, the template given in the pattern
90 is inserted, as if the @code{define_expand} were a @code{define_insn}.
92 Once the insn list is generated, various optimization passes convert,
93 replace, and rearrange the insns in the insn list. This is where the
94 @code{define_split} and @code{define_peephole} patterns get used, for
97 Finally, the insn list's RTL is matched up with the RTL templates in the
98 @code{define_insn} patterns, and those patterns are used to emit the
99 final assembly code. For this purpose, each named @code{define_insn}
100 acts like it's unnamed, since the names are ignored.
103 @section Everything about Instruction Patterns
105 @cindex instruction patterns
108 Each instruction pattern contains an incomplete RTL expression, with pieces
109 to be filled in later, operand constraints that restrict how the pieces can
110 be filled in, and an output pattern or C code to generate the assembler
111 output, all wrapped up in a @code{define_insn} expression.
113 A @code{define_insn} is an RTL expression containing four or five operands:
117 An optional name. The presence of a name indicate that this instruction
118 pattern can perform a certain standard job for the RTL-generation
119 pass of the compiler. This pass knows certain names and will use
120 the instruction patterns with those names, if the names are defined
121 in the machine description.
123 The absence of a name is indicated by writing an empty string
124 where the name should go. Nameless instruction patterns are never
125 used for generating RTL code, but they may permit several simpler insns
126 to be combined later on.
128 Names that are not thus known and used in RTL-generation have no
129 effect; they are equivalent to no name at all.
131 For the purpose of debugging the compiler, you may also specify a
132 name beginning with the @samp{*} character. Such a name is used only
133 for identifying the instruction in RTL dumps; it is entirely equivalent
134 to having a nameless pattern for all other purposes.
137 The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete
138 RTL expressions which show what the instruction should look like. It is
139 incomplete because it may contain @code{match_operand},
140 @code{match_operator}, and @code{match_dup} expressions that stand for
141 operands of the instruction.
143 If the vector has only one element, that element is the template for the
144 instruction pattern. If the vector has multiple elements, then the
145 instruction pattern is a @code{parallel} expression containing the
149 @cindex pattern conditions
150 @cindex conditions, in patterns
151 A condition. This is a string which contains a C expression that is
152 the final test to decide whether an insn body matches this pattern.
154 @cindex named patterns and conditions
155 For a named pattern, the condition (if present) may not depend on
156 the data in the insn being matched, but only the target-machine-type
157 flags. The compiler needs to test these conditions during
158 initialization in order to learn exactly which named instructions are
159 available in a particular run.
162 For nameless patterns, the condition is applied only when matching an
163 individual insn, and only after the insn has matched the pattern's
164 recognition template. The insn's operands may be found in the vector
165 @code{operands}. For an insn where the condition has once matched, it
166 can't be used to control register allocation, for example by excluding
167 certain hard registers or hard register combinations.
170 The @dfn{output template}: a string that says how to output matching
171 insns as assembler code. @samp{%} in this string specifies where
172 to substitute the value of an operand. @xref{Output Template}.
174 When simple substitution isn't general enough, you can specify a piece
175 of C code to compute the output. @xref{Output Statement}.
178 Optionally, a vector containing the values of attributes for insns matching
179 this pattern. @xref{Insn Attributes}.
183 @section Example of @code{define_insn}
184 @cindex @code{define_insn} example
186 Here is an actual example of an instruction pattern, for the 68000/68020.
191 (match_operand:SI 0 "general_operand" "rm"))]
195 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
197 return \"cmpl #0,%0\";
202 This can also be written using braced strings:
207 (match_operand:SI 0 "general_operand" "rm"))]
210 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
216 This is an instruction that sets the condition codes based on the value of
217 a general operand. It has no condition, so any insn whose RTL description
218 has the form shown may be handled according to this pattern. The name
219 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation
220 pass that, when it is necessary to test such a value, an insn to do so
221 can be constructed using this pattern.
223 The output control string is a piece of C code which chooses which
224 output template to return based on the kind of operand and the specific
225 type of CPU for which code is being generated.
227 @samp{"rm"} is an operand constraint. Its meaning is explained below.
230 @section RTL Template
231 @cindex RTL insn template
232 @cindex generating insns
233 @cindex insns, generating
234 @cindex recognizing insns
235 @cindex insns, recognizing
237 The RTL template is used to define which insns match the particular pattern
238 and how to find their operands. For named patterns, the RTL template also
239 says how to construct an insn from specified operands.
241 Construction involves substituting specified operands into a copy of the
242 template. Matching involves determining the values that serve as the
243 operands in the insn being matched. Both of these activities are
244 controlled by special expression types that direct matching and
245 substitution of the operands.
248 @findex match_operand
249 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
250 This expression is a placeholder for operand number @var{n} of
251 the insn. When constructing an insn, operand number @var{n}
252 will be substituted at this point. When matching an insn, whatever
253 appears at this position in the insn will be taken as operand
254 number @var{n}; but it must satisfy @var{predicate} or this instruction
255 pattern will not match at all.
257 Operand numbers must be chosen consecutively counting from zero in
258 each instruction pattern. There may be only one @code{match_operand}
259 expression in the pattern for each operand number. Usually operands
260 are numbered in the order of appearance in @code{match_operand}
261 expressions. In the case of a @code{define_expand}, any operand numbers
262 used only in @code{match_dup} expressions have higher values than all
263 other operand numbers.
265 @var{predicate} is a string that is the name of a function that
266 accepts two arguments, an expression and a machine mode.
267 @xref{Predicates}. During matching, the function will be called with
268 the putative operand as the expression and @var{m} as the mode
269 argument (if @var{m} is not specified, @code{VOIDmode} will be used,
270 which normally causes @var{predicate} to accept any mode). If it
271 returns zero, this instruction pattern fails to match.
272 @var{predicate} may be an empty string; then it means no test is to be
273 done on the operand, so anything which occurs in this position is
276 Most of the time, @var{predicate} will reject modes other than @var{m}---but
277 not always. For example, the predicate @code{address_operand} uses
278 @var{m} as the mode of memory ref that the address should be valid for.
279 Many predicates accept @code{const_int} nodes even though their mode is
282 @var{constraint} controls reloading and the choice of the best register
283 class to use for a value, as explained later (@pxref{Constraints}).
284 If the constraint would be an empty string, it can be omitted.
286 People are often unclear on the difference between the constraint and the
287 predicate. The predicate helps decide whether a given insn matches the
288 pattern. The constraint plays no role in this decision; instead, it
289 controls various decisions in the case of an insn which does match.
291 @findex match_scratch
292 @item (match_scratch:@var{m} @var{n} @var{constraint})
293 This expression is also a placeholder for operand number @var{n}
294 and indicates that operand must be a @code{scratch} or @code{reg}
297 When matching patterns, this is equivalent to
300 (match_operand:@var{m} @var{n} "scratch_operand" @var{pred})
303 but, when generating RTL, it produces a (@code{scratch}:@var{m})
306 If the last few expressions in a @code{parallel} are @code{clobber}
307 expressions whose operands are either a hard register or
308 @code{match_scratch}, the combiner can add or delete them when
309 necessary. @xref{Side Effects}.
312 @item (match_dup @var{n})
313 This expression is also a placeholder for operand number @var{n}.
314 It is used when the operand needs to appear more than once in the
317 In construction, @code{match_dup} acts just like @code{match_operand}:
318 the operand is substituted into the insn being constructed. But in
319 matching, @code{match_dup} behaves differently. It assumes that operand
320 number @var{n} has already been determined by a @code{match_operand}
321 appearing earlier in the recognition template, and it matches only an
322 identical-looking expression.
324 Note that @code{match_dup} should not be used to tell the compiler that
325 a particular register is being used for two operands (example:
326 @code{add} that adds one register to another; the second register is
327 both an input operand and the output operand). Use a matching
328 constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
329 operand is used in two places in the template, such as an instruction
330 that computes both a quotient and a remainder, where the opcode takes
331 two input operands but the RTL template has to refer to each of those
332 twice; once for the quotient pattern and once for the remainder pattern.
334 @findex match_operator
335 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
336 This pattern is a kind of placeholder for a variable RTL expression
339 When constructing an insn, it stands for an RTL expression whose
340 expression code is taken from that of operand @var{n}, and whose
341 operands are constructed from the patterns @var{operands}.
343 When matching an expression, it matches an expression if the function
344 @var{predicate} returns nonzero on that expression @emph{and} the
345 patterns @var{operands} match the operands of the expression.
347 Suppose that the function @code{commutative_operator} is defined as
348 follows, to match any expression whose operator is one of the
349 commutative arithmetic operators of RTL and whose mode is @var{mode}:
353 commutative_integer_operator (x, mode)
355 enum machine_mode mode;
357 enum rtx_code code = GET_CODE (x);
358 if (GET_MODE (x) != mode)
360 return (GET_RTX_CLASS (code) == RTX_COMM_ARITH
361 || code == EQ || code == NE);
365 Then the following pattern will match any RTL expression consisting
366 of a commutative operator applied to two general operands:
369 (match_operator:SI 3 "commutative_operator"
370 [(match_operand:SI 1 "general_operand" "g")
371 (match_operand:SI 2 "general_operand" "g")])
374 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
375 because the expressions to be matched all contain two operands.
377 When this pattern does match, the two operands of the commutative
378 operator are recorded as operands 1 and 2 of the insn. (This is done
379 by the two instances of @code{match_operand}.) Operand 3 of the insn
380 will be the entire commutative expression: use @code{GET_CODE
381 (operands[3])} to see which commutative operator was used.
383 The machine mode @var{m} of @code{match_operator} works like that of
384 @code{match_operand}: it is passed as the second argument to the
385 predicate function, and that function is solely responsible for
386 deciding whether the expression to be matched ``has'' that mode.
388 When constructing an insn, argument 3 of the gen-function will specify
389 the operation (i.e.@: the expression code) for the expression to be
390 made. It should be an RTL expression, whose expression code is copied
391 into a new expression whose operands are arguments 1 and 2 of the
392 gen-function. The subexpressions of argument 3 are not used;
393 only its expression code matters.
395 When @code{match_operator} is used in a pattern for matching an insn,
396 it usually best if the operand number of the @code{match_operator}
397 is higher than that of the actual operands of the insn. This improves
398 register allocation because the register allocator often looks at
399 operands 1 and 2 of insns to see if it can do register tying.
401 There is no way to specify constraints in @code{match_operator}. The
402 operand of the insn which corresponds to the @code{match_operator}
403 never has any constraints because it is never reloaded as a whole.
404 However, if parts of its @var{operands} are matched by
405 @code{match_operand} patterns, those parts may have constraints of
409 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
410 Like @code{match_dup}, except that it applies to operators instead of
411 operands. When constructing an insn, operand number @var{n} will be
412 substituted at this point. But in matching, @code{match_op_dup} behaves
413 differently. It assumes that operand number @var{n} has already been
414 determined by a @code{match_operator} appearing earlier in the
415 recognition template, and it matches only an identical-looking
418 @findex match_parallel
419 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
420 This pattern is a placeholder for an insn that consists of a
421 @code{parallel} expression with a variable number of elements. This
422 expression should only appear at the top level of an insn pattern.
424 When constructing an insn, operand number @var{n} will be substituted at
425 this point. When matching an insn, it matches if the body of the insn
426 is a @code{parallel} expression with at least as many elements as the
427 vector of @var{subpat} expressions in the @code{match_parallel}, if each
428 @var{subpat} matches the corresponding element of the @code{parallel},
429 @emph{and} the function @var{predicate} returns nonzero on the
430 @code{parallel} that is the body of the insn. It is the responsibility
431 of the predicate to validate elements of the @code{parallel} beyond
432 those listed in the @code{match_parallel}.
434 A typical use of @code{match_parallel} is to match load and store
435 multiple expressions, which can contain a variable number of elements
436 in a @code{parallel}. For example,
440 [(match_parallel 0 "load_multiple_operation"
441 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
442 (match_operand:SI 2 "memory_operand" "m"))
444 (clobber (reg:SI 179))])]
449 This example comes from @file{a29k.md}. The function
450 @code{load_multiple_operation} is defined in @file{a29k.c} and checks
451 that subsequent elements in the @code{parallel} are the same as the
452 @code{set} in the pattern, except that they are referencing subsequent
453 registers and memory locations.
455 An insn that matches this pattern might look like:
459 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
461 (clobber (reg:SI 179))
463 (mem:SI (plus:SI (reg:SI 100)
466 (mem:SI (plus:SI (reg:SI 100)
470 @findex match_par_dup
471 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
472 Like @code{match_op_dup}, but for @code{match_parallel} instead of
473 @code{match_operator}.
477 @node Output Template
478 @section Output Templates and Operand Substitution
479 @cindex output templates
480 @cindex operand substitution
482 @cindex @samp{%} in template
484 The @dfn{output template} is a string which specifies how to output the
485 assembler code for an instruction pattern. Most of the template is a
486 fixed string which is output literally. The character @samp{%} is used
487 to specify where to substitute an operand; it can also be used to
488 identify places where different variants of the assembler require
491 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
492 operand @var{n} at that point in the string.
494 @samp{%} followed by a letter and a digit says to output an operand in an
495 alternate fashion. Four letters have standard, built-in meanings described
496 below. The machine description macro @code{PRINT_OPERAND} can define
497 additional letters with nonstandard meanings.
499 @samp{%c@var{digit}} can be used to substitute an operand that is a
500 constant value without the syntax that normally indicates an immediate
503 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
504 the constant is negated before printing.
506 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
507 memory reference, with the actual operand treated as the address. This may
508 be useful when outputting a ``load address'' instruction, because often the
509 assembler syntax for such an instruction requires you to write the operand
510 as if it were a memory reference.
512 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
515 @samp{%=} outputs a number which is unique to each instruction in the
516 entire compilation. This is useful for making local labels to be
517 referred to more than once in a single template that generates multiple
518 assembler instructions.
520 @samp{%} followed by a punctuation character specifies a substitution that
521 does not use an operand. Only one case is standard: @samp{%%} outputs a
522 @samp{%} into the assembler code. Other nonstandard cases can be
523 defined in the @code{PRINT_OPERAND} macro. You must also define
524 which punctuation characters are valid with the
525 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
529 The template may generate multiple assembler instructions. Write the text
530 for the instructions, with @samp{\;} between them.
532 @cindex matching operands
533 When the RTL contains two operands which are required by constraint to match
534 each other, the output template must refer only to the lower-numbered operand.
535 Matching operands are not always identical, and the rest of the compiler
536 arranges to put the proper RTL expression for printing into the lower-numbered
539 One use of nonstandard letters or punctuation following @samp{%} is to
540 distinguish between different assembler languages for the same machine; for
541 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
542 requires periods in most opcode names, while MIT syntax does not. For
543 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
544 syntax. The same file of patterns is used for both kinds of output syntax,
545 but the character sequence @samp{%.} is used in each place where Motorola
546 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
547 defines the sequence to output a period; the macro for MIT syntax defines
550 @cindex @code{#} in template
551 As a special case, a template consisting of the single character @code{#}
552 instructs the compiler to first split the insn, and then output the
553 resulting instructions separately. This helps eliminate redundancy in the
554 output templates. If you have a @code{define_insn} that needs to emit
555 multiple assembler instructions, and there is a matching @code{define_split}
556 already defined, then you can simply use @code{#} as the output template
557 instead of writing an output template that emits the multiple assembler
560 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
561 of the form @samp{@{option0|option1|option2@}} in the templates. These
562 describe multiple variants of assembler language syntax.
563 @xref{Instruction Output}.
565 @node Output Statement
566 @section C Statements for Assembler Output
567 @cindex output statements
568 @cindex C statements for assembler output
569 @cindex generating assembler output
571 Often a single fixed template string cannot produce correct and efficient
572 assembler code for all the cases that are recognized by a single
573 instruction pattern. For example, the opcodes may depend on the kinds of
574 operands; or some unfortunate combinations of operands may require extra
575 machine instructions.
577 If the output control string starts with a @samp{@@}, then it is actually
578 a series of templates, each on a separate line. (Blank lines and
579 leading spaces and tabs are ignored.) The templates correspond to the
580 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
581 if a target machine has a two-address add instruction @samp{addr} to add
582 into a register and another @samp{addm} to add a register to memory, you
583 might write this pattern:
586 (define_insn "addsi3"
587 [(set (match_operand:SI 0 "general_operand" "=r,m")
588 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
589 (match_operand:SI 2 "general_operand" "g,r")))]
596 @cindex @code{*} in template
597 @cindex asterisk in template
598 If the output control string starts with a @samp{*}, then it is not an
599 output template but rather a piece of C program that should compute a
600 template. It should execute a @code{return} statement to return the
601 template-string you want. Most such templates use C string literals, which
602 require doublequote characters to delimit them. To include these
603 doublequote characters in the string, prefix each one with @samp{\}.
605 If the output control string is written as a brace block instead of a
606 double-quoted string, it is automatically assumed to be C code. In that
607 case, it is not necessary to put in a leading asterisk, or to escape the
608 doublequotes surrounding C string literals.
610 The operands may be found in the array @code{operands}, whose C data type
613 It is very common to select different ways of generating assembler code
614 based on whether an immediate operand is within a certain range. Be
615 careful when doing this, because the result of @code{INTVAL} is an
616 integer on the host machine. If the host machine has more bits in an
617 @code{int} than the target machine has in the mode in which the constant
618 will be used, then some of the bits you get from @code{INTVAL} will be
619 superfluous. For proper results, you must carefully disregard the
620 values of those bits.
622 @findex output_asm_insn
623 It is possible to output an assembler instruction and then go on to output
624 or compute more of them, using the subroutine @code{output_asm_insn}. This
625 receives two arguments: a template-string and a vector of operands. The
626 vector may be @code{operands}, or it may be another array of @code{rtx}
627 that you declare locally and initialize yourself.
629 @findex which_alternative
630 When an insn pattern has multiple alternatives in its constraints, often
631 the appearance of the assembler code is determined mostly by which alternative
632 was matched. When this is so, the C code can test the variable
633 @code{which_alternative}, which is the ordinal number of the alternative
634 that was actually satisfied (0 for the first, 1 for the second alternative,
637 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
638 for registers and @samp{clrmem} for memory locations. Here is how
639 a pattern could use @code{which_alternative} to choose between them:
643 [(set (match_operand:SI 0 "general_operand" "=r,m")
647 return (which_alternative == 0
648 ? "clrreg %0" : "clrmem %0");
652 The example above, where the assembler code to generate was
653 @emph{solely} determined by the alternative, could also have been specified
654 as follows, having the output control string start with a @samp{@@}:
659 [(set (match_operand:SI 0 "general_operand" "=r,m")
671 @cindex operand predicates
672 @cindex operator predicates
674 A predicate determines whether a @code{match_operand} or
675 @code{match_operator} expression matches, and therefore whether the
676 surrounding instruction pattern will be used for that combination of
677 operands. GCC has a number of machine-independent predicates, and you
678 can define machine-specific predicates as needed. By convention,
679 predicates used with @code{match_operand} have names that end in
680 @samp{_operand}, and those used with @code{match_operator} have names
681 that end in @samp{_operator}.
683 All predicates are Boolean functions (in the mathematical sense) of
684 two arguments: the RTL expression that is being considered at that
685 position in the instruction pattern, and the machine mode that the
686 @code{match_operand} or @code{match_operator} specifies. In this
687 section, the first argument is called @var{op} and the second argument
688 @var{mode}. Predicates can be called from C as ordinary two-argument
689 functions; this can be useful in output templates or other
690 machine-specific code.
692 Operand predicates can allow operands that are not actually acceptable
693 to the hardware, as long as the constraints give reload the ability to
694 fix them up (@pxref{Constraints}). However, GCC will usually generate
695 better code if the predicates specify the requirements of the machine
696 instructions as closely as possible. Reload cannot fix up operands
697 that must be constants (``immediate operands''); you must use a
698 predicate that allows only constants, or else enforce the requirement
699 in the extra condition.
701 @cindex predicates and machine modes
702 @cindex normal predicates
703 @cindex special predicates
704 Most predicates handle their @var{mode} argument in a uniform manner.
705 If @var{mode} is @code{VOIDmode} (unspecified), then @var{op} can have
706 any mode. If @var{mode} is anything else, then @var{op} must have the
707 same mode, unless @var{op} is a @code{CONST_INT} or integer
708 @code{CONST_DOUBLE}. These RTL expressions always have
709 @code{VOIDmode}, so it would be counterproductive to check that their
710 mode matches. Instead, predicates that accept @code{CONST_INT} and/or
711 integer @code{CONST_DOUBLE} check that the value stored in the
712 constant will fit in the requested mode.
714 Predicates with this behavior are called @dfn{normal}.
715 @command{genrecog} can optimize the instruction recognizer based on
716 knowledge of how normal predicates treat modes. It can also diagnose
717 certain kinds of common errors in the use of normal predicates; for
718 instance, it is almost always an error to use a normal predicate
719 without specifying a mode.
721 Predicates that do something different with their @var{mode} argument
722 are called @dfn{special}. The generic predicates
723 @code{address_operand} and @code{pmode_register_operand} are special
724 predicates. @command{genrecog} does not do any optimizations or
725 diagnosis when special predicates are used.
728 * Machine-Independent Predicates:: Predicates available to all back ends.
729 * Defining Predicates:: How to write machine-specific predicate
733 @node Machine-Independent Predicates
734 @subsection Machine-Independent Predicates
735 @cindex machine-independent predicates
736 @cindex generic predicates
738 These are the generic predicates available to all back ends. They are
739 defined in @file{recog.c}. The first category of predicates allow
740 only constant, or @dfn{immediate}, operands.
742 @defun immediate_operand
743 This predicate allows any sort of constant that fits in @var{mode}.
744 It is an appropriate choice for instructions that take operands that
748 @defun const_int_operand
749 This predicate allows any @code{CONST_INT} expression that fits in
750 @var{mode}. It is an appropriate choice for an immediate operand that
751 does not allow a symbol or label.
754 @defun const_double_operand
755 This predicate accepts any @code{CONST_DOUBLE} expression that has
756 exactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also
757 accept @code{CONST_INT}. It is intended for immediate floating point
762 The second category of predicates allow only some kind of machine
765 @defun register_operand
766 This predicate allows any @code{REG} or @code{SUBREG} expression that
767 is valid for @var{mode}. It is often suitable for arithmetic
768 instruction operands on a RISC machine.
771 @defun pmode_register_operand
772 This is a slight variant on @code{register_operand} which works around
773 a limitation in the machine-description reader.
776 (match_operand @var{n} "pmode_register_operand" @var{constraint})
783 (match_operand:P @var{n} "register_operand" @var{constraint})
787 would mean, if the machine-description reader accepted @samp{:P}
788 mode suffixes. Unfortunately, it cannot, because @code{Pmode} is an
789 alias for some other mode, and might vary with machine-specific
790 options. @xref{Misc}.
793 @defun scratch_operand
794 This predicate allows hard registers and @code{SCRATCH} expressions,
795 but not pseudo-registers. It is used internally by @code{match_scratch};
796 it should not be used directly.
800 The third category of predicates allow only some kind of memory reference.
802 @defun memory_operand
803 This predicate allows any valid reference to a quantity of mode
804 @var{mode} in memory, as determined by the weak form of
805 @code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}).
808 @defun address_operand
809 This predicate is a little unusual; it allows any operand that is a
810 valid expression for the @emph{address} of a quantity of mode
811 @var{mode}, again determined by the weak form of
812 @code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if
813 @samp{@w{(mem:@var{mode} (@var{exp}))}} is acceptable to
814 @code{memory_operand}, then @var{exp} is acceptable to
815 @code{address_operand}. Note that @var{exp} does not necessarily have
819 @defun indirect_operand
820 This is a stricter form of @code{memory_operand} which allows only
821 memory references with a @code{general_operand} as the address
822 expression. New uses of this predicate are discouraged, because
823 @code{general_operand} is very permissive, so it's hard to tell what
824 an @code{indirect_operand} does or does not allow. If a target has
825 different requirements for memory operands for different instructions,
826 it is better to define target-specific predicates which enforce the
827 hardware's requirements explicitly.
831 This predicate allows a memory reference suitable for pushing a value
832 onto the stack. This will be a @code{MEM} which refers to
833 @code{stack_pointer_rtx}, with a side-effect in its address expression
834 (@pxref{Incdec}); which one is determined by the
835 @code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}).
839 This predicate allows a memory reference suitable for popping a value
840 off the stack. Again, this will be a @code{MEM} referring to
841 @code{stack_pointer_rtx}, with a side-effect in its address
842 expression. However, this time @code{STACK_POP_CODE} is expected.
846 The fourth category of predicates allow some combination of the above
849 @defun nonmemory_operand
850 This predicate allows any immediate or register operand valid for @var{mode}.
853 @defun nonimmediate_operand
854 This predicate allows any register or memory operand valid for @var{mode}.
857 @defun general_operand
858 This predicate allows any immediate, register, or memory operand
859 valid for @var{mode}.
863 Finally, there are two generic operator predicates.
865 @defun comparison_operator
866 This predicate matches any expression which performs an arithmetic
867 comparison in @var{mode}; that is, @code{COMPARISON_P} is true for the
871 @defun ordered_comparison_operator
872 This predicate matches any expression which performs an arithmetic
873 comparison in @var{mode} and whose expression code is valid for integer
874 modes; that is, the expression code will be one of @code{eq}, @code{ne},
875 @code{lt}, @code{ltu}, @code{le}, @code{leu}, @code{gt}, @code{gtu},
876 @code{ge}, @code{geu}.
879 @node Defining Predicates
880 @subsection Defining Machine-Specific Predicates
881 @cindex defining predicates
882 @findex define_predicate
883 @findex define_special_predicate
885 Many machines have requirements for their operands that cannot be
886 expressed precisely using the generic predicates. You can define
887 additional predicates using @code{define_predicate} and
888 @code{define_special_predicate} expressions. These expressions have
893 The name of the predicate, as it will be referred to in
894 @code{match_operand} or @code{match_operator} expressions.
897 An RTL expression which evaluates to true if the predicate allows the
898 operand @var{op}, false if it does not. This expression can only use
899 the following RTL codes:
903 When written inside a predicate expression, a @code{MATCH_OPERAND}
904 expression evaluates to true if the predicate it names would allow
905 @var{op}. The operand number and constraint are ignored. Due to
906 limitations in @command{genrecog}, you can only refer to generic
907 predicates and predicates that have already been defined.
910 This expression evaluates to true if @var{op} or a specified
911 subexpression of @var{op} has one of a given list of RTX codes.
913 The first operand of this expression is a string constant containing a
914 comma-separated list of RTX code names (in lower case). These are the
915 codes for which the @code{MATCH_CODE} will be true.
917 The second operand is a string constant which indicates what
918 subexpression of @var{op} to examine. If it is absent or the empty
919 string, @var{op} itself is examined. Otherwise, the string constant
920 must be a sequence of digits and/or lowercase letters. Each character
921 indicates a subexpression to extract from the current expression; for
922 the first character this is @var{op}, for the second and subsequent
923 characters it is the result of the previous character. A digit
924 @var{n} extracts @samp{@w{XEXP (@var{e}, @var{n})}}; a letter @var{l}
925 extracts @samp{@w{XVECEXP (@var{e}, 0, @var{n})}} where @var{n} is the
926 alphabetic ordinal of @var{l} (0 for `a', 1 for 'b', and so on). The
927 @code{MATCH_CODE} then examines the RTX code of the subexpression
928 extracted by the complete string. It is not possible to extract
929 components of an @code{rtvec} that is not at position 0 within its RTX
933 This expression has one operand, a string constant containing a C
934 expression. The predicate's arguments, @var{op} and @var{mode}, are
935 available with those names in the C expression. The @code{MATCH_TEST}
936 evaluates to true if the C expression evaluates to a nonzero value.
937 @code{MATCH_TEST} expressions must not have side effects.
943 The basic @samp{MATCH_} expressions can be combined using these
944 logical operators, which have the semantics of the C operators
945 @samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively. As
946 in Common Lisp, you may give an @code{AND} or @code{IOR} expression an
947 arbitrary number of arguments; this has exactly the same effect as
948 writing a chain of two-argument @code{AND} or @code{IOR} expressions.
952 An optional block of C code, which should execute
953 @samp{@w{return true}} if the predicate is found to match and
954 @samp{@w{return false}} if it does not. It must not have any side
955 effects. The predicate arguments, @var{op} and @var{mode}, are
956 available with those names.
958 If a code block is present in a predicate definition, then the RTL
959 expression must evaluate to true @emph{and} the code block must
960 execute @samp{@w{return true}} for the predicate to allow the operand.
961 The RTL expression is evaluated first; do not re-check anything in the
962 code block that was checked in the RTL expression.
965 The program @command{genrecog} scans @code{define_predicate} and
966 @code{define_special_predicate} expressions to determine which RTX
967 codes are possibly allowed. You should always make this explicit in
968 the RTL predicate expression, using @code{MATCH_OPERAND} and
971 Here is an example of a simple predicate definition, from the IA64
976 ;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.}
977 (define_predicate "small_addr_symbolic_operand"
978 (and (match_code "symbol_ref")
979 (match_test "SYMBOL_REF_SMALL_ADDR_P (op)")))
984 And here is another, showing the use of the C block.
988 ;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.}
989 (define_predicate "gr_register_operand"
990 (match_operand 0 "register_operand")
993 if (GET_CODE (op) == SUBREG)
994 op = SUBREG_REG (op);
997 return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno));
1002 Predicates written with @code{define_predicate} automatically include
1003 a test that @var{mode} is @code{VOIDmode}, or @var{op} has the same
1004 mode as @var{mode}, or @var{op} is a @code{CONST_INT} or
1005 @code{CONST_DOUBLE}. They do @emph{not} check specifically for
1006 integer @code{CONST_DOUBLE}, nor do they test that the value of either
1007 kind of constant fits in the requested mode. This is because
1008 target-specific predicates that take constants usually have to do more
1009 stringent value checks anyway. If you need the exact same treatment
1010 of @code{CONST_INT} or @code{CONST_DOUBLE} that the generic predicates
1011 provide, use a @code{MATCH_OPERAND} subexpression to call
1012 @code{const_int_operand}, @code{const_double_operand}, or
1013 @code{immediate_operand}.
1015 Predicates written with @code{define_special_predicate} do not get any
1016 automatic mode checks, and are treated as having special mode handling
1017 by @command{genrecog}.
1019 The program @command{genpreds} is responsible for generating code to
1020 test predicates. It also writes a header file containing function
1021 declarations for all machine-specific predicates. It is not necessary
1022 to declare these predicates in @file{@var{cpu}-protos.h}.
1025 @c Most of this node appears by itself (in a different place) even
1026 @c when the INTERNALS flag is clear. Passages that require the internals
1027 @c manual's context are conditionalized to appear only in the internals manual.
1030 @section Operand Constraints
1031 @cindex operand constraints
1034 Each @code{match_operand} in an instruction pattern can specify
1035 constraints for the operands allowed. The constraints allow you to
1036 fine-tune matching within the set of operands allowed by the
1042 @section Constraints for @code{asm} Operands
1043 @cindex operand constraints, @code{asm}
1044 @cindex constraints, @code{asm}
1045 @cindex @code{asm} constraints
1047 Here are specific details on what constraint letters you can use with
1048 @code{asm} operands.
1050 Constraints can say whether
1051 an operand may be in a register, and which kinds of register; whether the
1052 operand can be a memory reference, and which kinds of address; whether the
1053 operand may be an immediate constant, and which possible values it may
1054 have. Constraints can also require two operands to match.
1058 * Simple Constraints:: Basic use of constraints.
1059 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1060 * Class Preferences:: Constraints guide which hard register to put things in.
1061 * Modifiers:: More precise control over effects of constraints.
1062 * Disable Insn Alternatives:: Disable insn alternatives using the @code{enabled} attribute.
1063 * Machine Constraints:: Existing constraints for some particular machines.
1064 * Define Constraints:: How to define machine-specific constraints.
1065 * C Constraint Interface:: How to test constraints from C code.
1071 * Simple Constraints:: Basic use of constraints.
1072 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1073 * Modifiers:: More precise control over effects of constraints.
1074 * Machine Constraints:: Special constraints for some particular machines.
1078 @node Simple Constraints
1079 @subsection Simple Constraints
1080 @cindex simple constraints
1082 The simplest kind of constraint is a string full of letters, each of
1083 which describes one kind of operand that is permitted. Here are
1084 the letters that are allowed:
1088 Whitespace characters are ignored and can be inserted at any position
1089 except the first. This enables each alternative for different operands to
1090 be visually aligned in the machine description even if they have different
1091 number of constraints and modifiers.
1093 @cindex @samp{m} in constraint
1094 @cindex memory references in constraints
1096 A memory operand is allowed, with any kind of address that the machine
1097 supports in general.
1098 Note that the letter used for the general memory constraint can be
1099 re-defined by a back end using the @code{TARGET_MEM_CONSTRAINT} macro.
1101 @cindex offsettable address
1102 @cindex @samp{o} in constraint
1104 A memory operand is allowed, but only if the address is
1105 @dfn{offsettable}. This means that adding a small integer (actually,
1106 the width in bytes of the operand, as determined by its machine mode)
1107 may be added to the address and the result is also a valid memory
1110 @cindex autoincrement/decrement addressing
1111 For example, an address which is constant is offsettable; so is an
1112 address that is the sum of a register and a constant (as long as a
1113 slightly larger constant is also within the range of address-offsets
1114 supported by the machine); but an autoincrement or autodecrement
1115 address is not offsettable. More complicated indirect/indexed
1116 addresses may or may not be offsettable depending on the other
1117 addressing modes that the machine supports.
1119 Note that in an output operand which can be matched by another
1120 operand, the constraint letter @samp{o} is valid only when accompanied
1121 by both @samp{<} (if the target machine has predecrement addressing)
1122 and @samp{>} (if the target machine has preincrement addressing).
1124 @cindex @samp{V} in constraint
1126 A memory operand that is not offsettable. In other words, anything that
1127 would fit the @samp{m} constraint but not the @samp{o} constraint.
1129 @cindex @samp{<} in constraint
1131 A memory operand with autodecrement addressing (either predecrement or
1132 postdecrement) is allowed.
1134 @cindex @samp{>} in constraint
1136 A memory operand with autoincrement addressing (either preincrement or
1137 postincrement) is allowed.
1139 @cindex @samp{r} in constraint
1140 @cindex registers in constraints
1142 A register operand is allowed provided that it is in a general
1145 @cindex constants in constraints
1146 @cindex @samp{i} in constraint
1148 An immediate integer operand (one with constant value) is allowed.
1149 This includes symbolic constants whose values will be known only at
1150 assembly time or later.
1152 @cindex @samp{n} in constraint
1154 An immediate integer operand with a known numeric value is allowed.
1155 Many systems cannot support assembly-time constants for operands less
1156 than a word wide. Constraints for these operands should use @samp{n}
1157 rather than @samp{i}.
1159 @cindex @samp{I} in constraint
1160 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
1161 Other letters in the range @samp{I} through @samp{P} may be defined in
1162 a machine-dependent fashion to permit immediate integer operands with
1163 explicit integer values in specified ranges. For example, on the
1164 68000, @samp{I} is defined to stand for the range of values 1 to 8.
1165 This is the range permitted as a shift count in the shift
1168 @cindex @samp{E} in constraint
1170 An immediate floating operand (expression code @code{const_double}) is
1171 allowed, but only if the target floating point format is the same as
1172 that of the host machine (on which the compiler is running).
1174 @cindex @samp{F} in constraint
1176 An immediate floating operand (expression code @code{const_double} or
1177 @code{const_vector}) is allowed.
1179 @cindex @samp{G} in constraint
1180 @cindex @samp{H} in constraint
1181 @item @samp{G}, @samp{H}
1182 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
1183 permit immediate floating operands in particular ranges of values.
1185 @cindex @samp{s} in constraint
1187 An immediate integer operand whose value is not an explicit integer is
1190 This might appear strange; if an insn allows a constant operand with a
1191 value not known at compile time, it certainly must allow any known
1192 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
1193 better code to be generated.
1195 For example, on the 68000 in a fullword instruction it is possible to
1196 use an immediate operand; but if the immediate value is between @minus{}128
1197 and 127, better code results from loading the value into a register and
1198 using the register. This is because the load into the register can be
1199 done with a @samp{moveq} instruction. We arrange for this to happen
1200 by defining the letter @samp{K} to mean ``any integer outside the
1201 range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand
1204 @cindex @samp{g} in constraint
1206 Any register, memory or immediate integer operand is allowed, except for
1207 registers that are not general registers.
1209 @cindex @samp{X} in constraint
1212 Any operand whatsoever is allowed, even if it does not satisfy
1213 @code{general_operand}. This is normally used in the constraint of
1214 a @code{match_scratch} when certain alternatives will not actually
1215 require a scratch register.
1218 Any operand whatsoever is allowed.
1221 @cindex @samp{0} in constraint
1222 @cindex digits in constraint
1223 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
1224 An operand that matches the specified operand number is allowed. If a
1225 digit is used together with letters within the same alternative, the
1226 digit should come last.
1228 This number is allowed to be more than a single digit. If multiple
1229 digits are encountered consecutively, they are interpreted as a single
1230 decimal integer. There is scant chance for ambiguity, since to-date
1231 it has never been desirable that @samp{10} be interpreted as matching
1232 either operand 1 @emph{or} operand 0. Should this be desired, one
1233 can use multiple alternatives instead.
1235 @cindex matching constraint
1236 @cindex constraint, matching
1237 This is called a @dfn{matching constraint} and what it really means is
1238 that the assembler has only a single operand that fills two roles
1240 considered separate in the RTL insn. For example, an add insn has two
1241 input operands and one output operand in the RTL, but on most CISC
1244 which @code{asm} distinguishes. For example, an add instruction uses
1245 two input operands and an output operand, but on most CISC
1247 machines an add instruction really has only two operands, one of them an
1248 input-output operand:
1254 Matching constraints are used in these circumstances.
1255 More precisely, the two operands that match must include one input-only
1256 operand and one output-only operand. Moreover, the digit must be a
1257 smaller number than the number of the operand that uses it in the
1261 For operands to match in a particular case usually means that they
1262 are identical-looking RTL expressions. But in a few special cases
1263 specific kinds of dissimilarity are allowed. For example, @code{*x}
1264 as an input operand will match @code{*x++} as an output operand.
1265 For proper results in such cases, the output template should always
1266 use the output-operand's number when printing the operand.
1269 @cindex load address instruction
1270 @cindex push address instruction
1271 @cindex address constraints
1272 @cindex @samp{p} in constraint
1274 An operand that is a valid memory address is allowed. This is
1275 for ``load address'' and ``push address'' instructions.
1277 @findex address_operand
1278 @samp{p} in the constraint must be accompanied by @code{address_operand}
1279 as the predicate in the @code{match_operand}. This predicate interprets
1280 the mode specified in the @code{match_operand} as the mode of the memory
1281 reference for which the address would be valid.
1283 @cindex other register constraints
1284 @cindex extensible constraints
1285 @item @var{other-letters}
1286 Other letters can be defined in machine-dependent fashion to stand for
1287 particular classes of registers or other arbitrary operand types.
1288 @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
1289 for data, address and floating point registers.
1293 In order to have valid assembler code, each operand must satisfy
1294 its constraint. But a failure to do so does not prevent the pattern
1295 from applying to an insn. Instead, it directs the compiler to modify
1296 the code so that the constraint will be satisfied. Usually this is
1297 done by copying an operand into a register.
1299 Contrast, therefore, the two instruction patterns that follow:
1303 [(set (match_operand:SI 0 "general_operand" "=r")
1304 (plus:SI (match_dup 0)
1305 (match_operand:SI 1 "general_operand" "r")))]
1311 which has two operands, one of which must appear in two places, and
1315 [(set (match_operand:SI 0 "general_operand" "=r")
1316 (plus:SI (match_operand:SI 1 "general_operand" "0")
1317 (match_operand:SI 2 "general_operand" "r")))]
1323 which has three operands, two of which are required by a constraint to be
1324 identical. If we are considering an insn of the form
1327 (insn @var{n} @var{prev} @var{next}
1329 (plus:SI (reg:SI 6) (reg:SI 109)))
1334 the first pattern would not apply at all, because this insn does not
1335 contain two identical subexpressions in the right place. The pattern would
1336 say, ``That does not look like an add instruction; try other patterns''.
1337 The second pattern would say, ``Yes, that's an add instruction, but there
1338 is something wrong with it''. It would direct the reload pass of the
1339 compiler to generate additional insns to make the constraint true. The
1340 results might look like this:
1343 (insn @var{n2} @var{prev} @var{n}
1344 (set (reg:SI 3) (reg:SI 6))
1347 (insn @var{n} @var{n2} @var{next}
1349 (plus:SI (reg:SI 3) (reg:SI 109)))
1353 It is up to you to make sure that each operand, in each pattern, has
1354 constraints that can handle any RTL expression that could be present for
1355 that operand. (When multiple alternatives are in use, each pattern must,
1356 for each possible combination of operand expressions, have at least one
1357 alternative which can handle that combination of operands.) The
1358 constraints don't need to @emph{allow} any possible operand---when this is
1359 the case, they do not constrain---but they must at least point the way to
1360 reloading any possible operand so that it will fit.
1364 If the constraint accepts whatever operands the predicate permits,
1365 there is no problem: reloading is never necessary for this operand.
1367 For example, an operand whose constraints permit everything except
1368 registers is safe provided its predicate rejects registers.
1370 An operand whose predicate accepts only constant values is safe
1371 provided its constraints include the letter @samp{i}. If any possible
1372 constant value is accepted, then nothing less than @samp{i} will do;
1373 if the predicate is more selective, then the constraints may also be
1377 Any operand expression can be reloaded by copying it into a register.
1378 So if an operand's constraints allow some kind of register, it is
1379 certain to be safe. It need not permit all classes of registers; the
1380 compiler knows how to copy a register into another register of the
1381 proper class in order to make an instruction valid.
1383 @cindex nonoffsettable memory reference
1384 @cindex memory reference, nonoffsettable
1386 A nonoffsettable memory reference can be reloaded by copying the
1387 address into a register. So if the constraint uses the letter
1388 @samp{o}, all memory references are taken care of.
1391 A constant operand can be reloaded by allocating space in memory to
1392 hold it as preinitialized data. Then the memory reference can be used
1393 in place of the constant. So if the constraint uses the letters
1394 @samp{o} or @samp{m}, constant operands are not a problem.
1397 If the constraint permits a constant and a pseudo register used in an insn
1398 was not allocated to a hard register and is equivalent to a constant,
1399 the register will be replaced with the constant. If the predicate does
1400 not permit a constant and the insn is re-recognized for some reason, the
1401 compiler will crash. Thus the predicate must always recognize any
1402 objects allowed by the constraint.
1405 If the operand's predicate can recognize registers, but the constraint does
1406 not permit them, it can make the compiler crash. When this operand happens
1407 to be a register, the reload pass will be stymied, because it does not know
1408 how to copy a register temporarily into memory.
1410 If the predicate accepts a unary operator, the constraint applies to the
1411 operand. For example, the MIPS processor at ISA level 3 supports an
1412 instruction which adds two registers in @code{SImode} to produce a
1413 @code{DImode} result, but only if the registers are correctly sign
1414 extended. This predicate for the input operands accepts a
1415 @code{sign_extend} of an @code{SImode} register. Write the constraint
1416 to indicate the type of register that is required for the operand of the
1420 @node Multi-Alternative
1421 @subsection Multiple Alternative Constraints
1422 @cindex multiple alternative constraints
1424 Sometimes a single instruction has multiple alternative sets of possible
1425 operands. For example, on the 68000, a logical-or instruction can combine
1426 register or an immediate value into memory, or it can combine any kind of
1427 operand into a register; but it cannot combine one memory location into
1430 These constraints are represented as multiple alternatives. An alternative
1431 can be described by a series of letters for each operand. The overall
1432 constraint for an operand is made from the letters for this operand
1433 from the first alternative, a comma, the letters for this operand from
1434 the second alternative, a comma, and so on until the last alternative.
1436 Here is how it is done for fullword logical-or on the 68000:
1439 (define_insn "iorsi3"
1440 [(set (match_operand:SI 0 "general_operand" "=m,d")
1441 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1442 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1446 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1447 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1448 2. The second alternative has @samp{d} (data register) for operand 0,
1449 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1450 @samp{%} in the constraints apply to all the alternatives; their
1451 meaning is explained in the next section (@pxref{Class Preferences}).
1454 @c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL
1455 If all the operands fit any one alternative, the instruction is valid.
1456 Otherwise, for each alternative, the compiler counts how many instructions
1457 must be added to copy the operands so that that alternative applies.
1458 The alternative requiring the least copying is chosen. If two alternatives
1459 need the same amount of copying, the one that comes first is chosen.
1460 These choices can be altered with the @samp{?} and @samp{!} characters:
1463 @cindex @samp{?} in constraint
1464 @cindex question mark
1466 Disparage slightly the alternative that the @samp{?} appears in,
1467 as a choice when no alternative applies exactly. The compiler regards
1468 this alternative as one unit more costly for each @samp{?} that appears
1471 @cindex @samp{!} in constraint
1472 @cindex exclamation point
1474 Disparage severely the alternative that the @samp{!} appears in.
1475 This alternative can still be used if it fits without reloading,
1476 but if reloading is needed, some other alternative will be used.
1480 When an insn pattern has multiple alternatives in its constraints, often
1481 the appearance of the assembler code is determined mostly by which
1482 alternative was matched. When this is so, the C code for writing the
1483 assembler code can use the variable @code{which_alternative}, which is
1484 the ordinal number of the alternative that was actually satisfied (0 for
1485 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1489 @node Class Preferences
1490 @subsection Register Class Preferences
1491 @cindex class preference constraints
1492 @cindex register class preference constraints
1494 @cindex voting between constraint alternatives
1495 The operand constraints have another function: they enable the compiler
1496 to decide which kind of hardware register a pseudo register is best
1497 allocated to. The compiler examines the constraints that apply to the
1498 insns that use the pseudo register, looking for the machine-dependent
1499 letters such as @samp{d} and @samp{a} that specify classes of registers.
1500 The pseudo register is put in whichever class gets the most ``votes''.
1501 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1502 favor of a general register. The machine description says which registers
1503 are considered general.
1505 Of course, on some machines all registers are equivalent, and no register
1506 classes are defined. Then none of this complexity is relevant.
1510 @subsection Constraint Modifier Characters
1511 @cindex modifiers in constraints
1512 @cindex constraint modifier characters
1514 @c prevent bad page break with this line
1515 Here are constraint modifier characters.
1518 @cindex @samp{=} in constraint
1520 Means that this operand is write-only for this instruction: the previous
1521 value is discarded and replaced by output data.
1523 @cindex @samp{+} in constraint
1525 Means that this operand is both read and written by the instruction.
1527 When the compiler fixes up the operands to satisfy the constraints,
1528 it needs to know which operands are inputs to the instruction and
1529 which are outputs from it. @samp{=} identifies an output; @samp{+}
1530 identifies an operand that is both input and output; all other operands
1531 are assumed to be input only.
1533 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1534 first character of the constraint string.
1536 @cindex @samp{&} in constraint
1537 @cindex earlyclobber operand
1539 Means (in a particular alternative) that this operand is an
1540 @dfn{earlyclobber} operand, which is modified before the instruction is
1541 finished using the input operands. Therefore, this operand may not lie
1542 in a register that is used as an input operand or as part of any memory
1545 @samp{&} applies only to the alternative in which it is written. In
1546 constraints with multiple alternatives, sometimes one alternative
1547 requires @samp{&} while others do not. See, for example, the
1548 @samp{movdf} insn of the 68000.
1550 An input operand can be tied to an earlyclobber operand if its only
1551 use as an input occurs before the early result is written. Adding
1552 alternatives of this form often allows GCC to produce better code
1553 when only some of the inputs can be affected by the earlyclobber.
1554 See, for example, the @samp{mulsi3} insn of the ARM@.
1556 @samp{&} does not obviate the need to write @samp{=}.
1558 @cindex @samp{%} in constraint
1560 Declares the instruction to be commutative for this operand and the
1561 following operand. This means that the compiler may interchange the
1562 two operands if that is the cheapest way to make all operands fit the
1565 This is often used in patterns for addition instructions
1566 that really have only two operands: the result must go in one of the
1567 arguments. Here for example, is how the 68000 halfword-add
1568 instruction is defined:
1571 (define_insn "addhi3"
1572 [(set (match_operand:HI 0 "general_operand" "=m,r")
1573 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1574 (match_operand:HI 2 "general_operand" "di,g")))]
1578 GCC can only handle one commutative pair in an asm; if you use more,
1579 the compiler may fail. Note that you need not use the modifier if
1580 the two alternatives are strictly identical; this would only waste
1581 time in the reload pass. The modifier is not operational after
1582 register allocation, so the result of @code{define_peephole2}
1583 and @code{define_split}s performed after reload cannot rely on
1584 @samp{%} to make the intended insn match.
1586 @cindex @samp{#} in constraint
1588 Says that all following characters, up to the next comma, are to be
1589 ignored as a constraint. They are significant only for choosing
1590 register preferences.
1592 @cindex @samp{*} in constraint
1594 Says that the following character should be ignored when choosing
1595 register preferences. @samp{*} has no effect on the meaning of the
1596 constraint as a constraint, and no effect on reloading.
1599 Here is an example: the 68000 has an instruction to sign-extend a
1600 halfword in a data register, and can also sign-extend a value by
1601 copying it into an address register. While either kind of register is
1602 acceptable, the constraints on an address-register destination are
1603 less strict, so it is best if register allocation makes an address
1604 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1605 constraint letter (for data register) is ignored when computing
1606 register preferences.
1609 (define_insn "extendhisi2"
1610 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1612 (match_operand:HI 1 "general_operand" "0,g")))]
1618 @node Machine Constraints
1619 @subsection Constraints for Particular Machines
1620 @cindex machine specific constraints
1621 @cindex constraints, machine specific
1623 Whenever possible, you should use the general-purpose constraint letters
1624 in @code{asm} arguments, since they will convey meaning more readily to
1625 people reading your code. Failing that, use the constraint letters
1626 that usually have very similar meanings across architectures. The most
1627 commonly used constraints are @samp{m} and @samp{r} (for memory and
1628 general-purpose registers respectively; @pxref{Simple Constraints}), and
1629 @samp{I}, usually the letter indicating the most common
1630 immediate-constant format.
1632 Each architecture defines additional constraints. These constraints
1633 are used by the compiler itself for instruction generation, as well as
1634 for @code{asm} statements; therefore, some of the constraints are not
1635 particularly useful for @code{asm}. Here is a summary of some of the
1636 machine-dependent constraints available on some particular machines;
1637 it includes both constraints that are useful for @code{asm} and
1638 constraints that aren't. The compiler source file mentioned in the
1639 table heading for each architecture is the definitive reference for
1640 the meanings of that architecture's constraints.
1643 @item ARM family---@file{config/arm/arm.h}
1646 Floating-point register
1649 VFP floating-point register
1652 One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0
1656 Floating-point constant that would satisfy the constraint @samp{F} if it
1660 Integer that is valid as an immediate operand in a data processing
1661 instruction. That is, an integer in the range 0 to 255 rotated by a
1665 Integer in the range @minus{}4095 to 4095
1668 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1671 Integer that satisfies constraint @samp{I} when negated (twos complement)
1674 Integer in the range 0 to 32
1677 A memory reference where the exact address is in a single register
1678 (`@samp{m}' is preferable for @code{asm} statements)
1681 An item in the constant pool
1684 A symbol in the text segment of the current file
1687 A memory reference suitable for VFP load/store insns (reg+constant offset)
1690 A memory reference suitable for iWMMXt load/store instructions.
1693 A memory reference suitable for the ARMv4 ldrsb instruction.
1696 @item AVR family---@file{config/avr/constraints.md}
1699 Registers from r0 to r15
1702 Registers from r16 to r23
1705 Registers from r16 to r31
1708 Registers from r24 to r31. These registers can be used in @samp{adiw} command
1711 Pointer register (r26--r31)
1714 Base pointer register (r28--r31)
1717 Stack pointer register (SPH:SPL)
1720 Temporary register r0
1723 Register pair X (r27:r26)
1726 Register pair Y (r29:r28)
1729 Register pair Z (r31:r30)
1732 Constant greater than @minus{}1, less than 64
1735 Constant greater than @minus{}64, less than 1
1744 Constant that fits in 8 bits
1747 Constant integer @minus{}1
1750 Constant integer 8, 16, or 24
1756 A floating point constant 0.0
1759 Integer constant in the range -6 @dots{} 5.
1762 A memory address based on Y or Z pointer with displacement.
1765 @item CRX Architecture---@file{config/crx/crx.h}
1769 Registers from r0 to r14 (registers without stack pointer)
1772 Register r16 (64-bit accumulator lo register)
1775 Register r17 (64-bit accumulator hi register)
1778 Register pair r16-r17. (64-bit accumulator lo-hi pair)
1781 Constant that fits in 3 bits
1784 Constant that fits in 4 bits
1787 Constant that fits in 5 bits
1790 Constant that is one of -1, 4, -4, 7, 8, 12, 16, 20, 32, 48
1793 Floating point constant that is legal for store immediate
1796 @item Hewlett-Packard PA-RISC---@file{config/pa/pa.h}
1802 Floating point register
1805 Shift amount register
1808 Floating point register (deprecated)
1811 Upper floating point register (32-bit), floating point register (64-bit)
1817 Signed 11-bit integer constant
1820 Signed 14-bit integer constant
1823 Integer constant that can be deposited with a @code{zdepi} instruction
1826 Signed 5-bit integer constant
1832 Integer constant that can be loaded with a @code{ldil} instruction
1835 Integer constant whose value plus one is a power of 2
1838 Integer constant that can be used for @code{and} operations in @code{depi}
1839 and @code{extru} instructions
1848 Floating-point constant 0.0
1851 A @code{lo_sum} data-linkage-table memory operand
1854 A memory operand that can be used as the destination operand of an
1855 integer store instruction
1858 A scaled or unscaled indexed memory operand
1861 A memory operand for floating-point loads and stores
1864 A register indirect memory operand
1867 @item picoChip family---@file{picochip.h}
1873 Pointer register. A register which can be used to access memory without
1874 supplying an offset. Any other register can be used to access memory,
1875 but will need a constant offset. In the case of the offset being zero,
1876 it is more efficient to use a pointer register, since this reduces code
1880 A twin register. A register which may be paired with an adjacent
1881 register to create a 32-bit register.
1884 Any absolute memory address (e.g., symbolic constant, symbolic
1888 4-bit signed integer.
1891 4-bit unsigned integer.
1894 8-bit signed integer.
1897 Any constant whose absolute value is no greater than 4-bits.
1900 10-bit signed integer
1903 16-bit signed integer.
1907 @item PowerPC and IBM RS6000---@file{config/rs6000/rs6000.h}
1910 Address base register
1913 Floating point register
1919 @samp{MQ}, @samp{CTR}, or @samp{LINK} register
1928 @samp{LINK} register
1931 @samp{CR} register (condition register) number 0
1934 @samp{CR} register (condition register)
1937 @samp{FPMEM} stack memory for FPR-GPR transfers
1940 Signed 16-bit constant
1943 Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for
1944 @code{SImode} constants)
1947 Unsigned 16-bit constant
1950 Signed 16-bit constant shifted left 16 bits
1953 Constant larger than 31
1962 Constant whose negation is a signed 16-bit constant
1965 Floating point constant that can be loaded into a register with one
1966 instruction per word
1969 Integer/Floating point constant that can be loaded into a register using
1973 Memory operand that is an offset from a register (@samp{m} is preferable
1974 for @code{asm} statements)
1977 Memory operand that is an indexed or indirect from a register (@samp{m} is
1978 preferable for @code{asm} statements)
1984 Address operand that is an indexed or indirect from a register (@samp{p} is
1985 preferable for @code{asm} statements)
1988 Constant suitable as a 64-bit mask operand
1991 Constant suitable as a 32-bit mask operand
1994 System V Release 4 small data area reference
1997 AND masks that can be performed by two rldic@{l, r@} instructions
2000 Vector constant that does not require memory
2004 @item Intel 386---@file{config/i386/constraints.md}
2007 Legacy register---the eight integer registers available on all
2008 i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
2009 @code{si}, @code{di}, @code{bp}, @code{sp}).
2012 Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a},
2013 @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.
2016 Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
2017 @code{c}, and @code{d}.
2021 Any register that can be used as the index in a base+index memory
2022 access: that is, any general register except the stack pointer.
2026 The @code{a} register.
2029 The @code{b} register.
2032 The @code{c} register.
2035 The @code{d} register.
2038 The @code{si} register.
2041 The @code{di} register.
2044 The @code{a} and @code{d} registers, as a pair (for instructions that
2045 return half the result in one and half in the other).
2048 Any 80387 floating-point (stack) register.
2051 Top of 80387 floating-point stack (@code{%st(0)}).
2054 Second from top of 80387 floating-point stack (@code{%st(1)}).
2063 First SSE register (@code{%xmm0}).
2067 Any SSE register, when SSE2 is enabled.
2070 Any SSE register, when SSE2 and inter-unit moves are enabled.
2073 Any MMX register, when inter-unit moves are enabled.
2077 Integer constant in the range 0 @dots{} 31, for 32-bit shifts.
2080 Integer constant in the range 0 @dots{} 63, for 64-bit shifts.
2083 Signed 8-bit integer constant.
2086 @code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move.
2089 0, 1, 2, or 3 (shifts for the @code{lea} instruction).
2092 Unsigned 8-bit integer constant (for @code{in} and @code{out}
2097 Integer constant in the range 0 @dots{} 127, for 128-bit shifts.
2101 Standard 80387 floating point constant.
2104 Standard SSE floating point constant.
2107 32-bit signed integer constant, or a symbolic reference known
2108 to fit that range (for immediate operands in sign-extending x86-64
2112 32-bit unsigned integer constant, or a symbolic reference known
2113 to fit that range (for immediate operands in zero-extending x86-64
2118 @item Intel IA-64---@file{config/ia64/ia64.h}
2121 General register @code{r0} to @code{r3} for @code{addl} instruction
2127 Predicate register (@samp{c} as in ``conditional'')
2130 Application register residing in M-unit
2133 Application register residing in I-unit
2136 Floating-point register
2140 Remember that @samp{m} allows postincrement and postdecrement which
2141 require printing with @samp{%Pn} on IA-64.
2142 Use @samp{S} to disallow postincrement and postdecrement.
2145 Floating-point constant 0.0 or 1.0
2148 14-bit signed integer constant
2151 22-bit signed integer constant
2154 8-bit signed integer constant for logical instructions
2157 8-bit adjusted signed integer constant for compare pseudo-ops
2160 6-bit unsigned integer constant for shift counts
2163 9-bit signed integer constant for load and store postincrements
2169 0 or @minus{}1 for @code{dep} instruction
2172 Non-volatile memory for floating-point loads and stores
2175 Integer constant in the range 1 to 4 for @code{shladd} instruction
2178 Memory operand except postincrement and postdecrement
2181 @item FRV---@file{config/frv/frv.h}
2184 Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}).
2187 Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}).
2190 Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and
2191 @code{icc0} to @code{icc3}).
2194 Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}).
2197 Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}).
2198 Odd registers are excluded not in the class but through the use of a machine
2199 mode larger than 4 bytes.
2202 Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}).
2205 Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}).
2206 Odd registers are excluded not in the class but through the use of a machine
2207 mode larger than 4 bytes.
2210 Register in the class @code{LR_REG} (the @code{lr} register).
2213 Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}).
2214 Register numbers not divisible by 4 are excluded not in the class but through
2215 the use of a machine mode larger than 8 bytes.
2218 Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}).
2221 Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}).
2224 Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}).
2227 Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}).
2230 Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}).
2231 Register numbers not divisible by 4 are excluded not in the class but through
2232 the use of a machine mode larger than 8 bytes.
2235 Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}).
2238 Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}).
2241 Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}).
2244 Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}).
2247 Floating point constant zero
2250 6-bit signed integer constant
2253 10-bit signed integer constant
2256 16-bit signed integer constant
2259 16-bit unsigned integer constant
2262 12-bit signed integer constant that is negative---i.e.@: in the
2263 range of @minus{}2048 to @minus{}1
2269 12-bit signed integer constant that is greater than zero---i.e.@: in the
2274 @item Blackfin family---@file{config/bfin/constraints.md}
2283 A call clobbered P register.
2286 A single register. If @var{n} is in the range 0 to 7, the corresponding D
2287 register. If it is @code{A}, then the register P0.
2290 Even-numbered D register
2293 Odd-numbered D register
2296 Accumulator register.
2299 Even-numbered accumulator register.
2302 Odd-numbered accumulator register.
2314 Registers used for circular buffering, i.e. I, B, or L registers.
2329 Any D, P, B, M, I or L register.
2332 Additional registers typically used only in prologues and epilogues: RETS,
2333 RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.
2336 Any register except accumulators or CC.
2339 Signed 16 bit integer (in the range -32768 to 32767)
2342 Unsigned 16 bit integer (in the range 0 to 65535)
2345 Signed 7 bit integer (in the range -64 to 63)
2348 Unsigned 7 bit integer (in the range 0 to 127)
2351 Unsigned 5 bit integer (in the range 0 to 31)
2354 Signed 4 bit integer (in the range -8 to 7)
2357 Signed 3 bit integer (in the range -3 to 4)
2360 Unsigned 3 bit integer (in the range 0 to 7)
2363 Constant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4.
2366 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2367 use with either accumulator.
2370 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2371 use only with accumulator A1.
2380 An integer constant with exactly a single bit set.
2383 An integer constant with all bits set except exactly one.
2391 @item M32C---@file{config/m32c/m32c.c}
2396 @samp{$sp}, @samp{$fb}, @samp{$sb}.
2399 Any control register, when they're 16 bits wide (nothing if control
2400 registers are 24 bits wide)
2403 Any control register, when they're 24 bits wide.
2412 $r0 or $r2, or $r2r0 for 32 bit values.
2415 $r1 or $r3, or $r3r1 for 32 bit values.
2418 A register that can hold a 64 bit value.
2421 $r0 or $r1 (registers with addressable high/low bytes)
2430 Address registers when they're 16 bits wide.
2433 Address registers when they're 24 bits wide.
2436 Registers that can hold QI values.
2439 Registers that can be used with displacements ($a0, $a1, $sb).
2442 Registers that can hold 32 bit values.
2445 Registers that can hold 16 bit values.
2448 Registers chat can hold 16 bit values, including all control
2452 $r0 through R1, plus $a0 and $a1.
2458 The memory-based pseudo-registers $mem0 through $mem15.
2461 Registers that can hold pointers (16 bit registers for r8c, m16c; 24
2462 bit registers for m32cm, m32c).
2465 Matches multiple registers in a PARALLEL to form a larger register.
2466 Used to match function return values.
2475 -32768 @dots{} 32767
2481 -8 @dots{} -1 or 1 @dots{} 8
2484 -16 @dots{} -1 or 1 @dots{} 16
2487 -32 @dots{} -1 or 1 @dots{} 32
2493 An 8 bit value with exactly one bit set.
2496 A 16 bit value with exactly one bit set.
2499 The common src/dest memory addressing modes.
2502 Memory addressed using $a0 or $a1.
2505 Memory addressed with immediate addresses.
2508 Memory addressed using the stack pointer ($sp).
2511 Memory addressed using the frame base register ($fb).
2514 Memory addressed using the small base register ($sb).
2520 @item MIPS---@file{config/mips/constraints.md}
2523 An address register. This is equivalent to @code{r} unless
2524 generating MIPS16 code.
2527 A floating-point register (if available).
2530 Formerly the @code{hi} register. This constraint is no longer supported.
2533 The @code{lo} register. Use this register to store values that are
2534 no bigger than a word.
2537 The concatenated @code{hi} and @code{lo} registers. Use this register
2538 to store doubleword values.
2541 A register suitable for use in an indirect jump. This will always be
2542 @code{$25} for @option{-mabicalls}.
2545 Register @code{$3}. Do not use this constraint in new code;
2546 it is retained only for compatibility with glibc.
2549 Equivalent to @code{r}; retained for backwards compatibility.
2552 A floating-point condition code register.
2555 A signed 16-bit constant (for arithmetic instructions).
2561 An unsigned 16-bit constant (for logic instructions).
2564 A signed 32-bit constant in which the lower 16 bits are zero.
2565 Such constants can be loaded using @code{lui}.
2568 A constant that cannot be loaded using @code{lui}, @code{addiu}
2572 A constant in the range -65535 to -1 (inclusive).
2575 A signed 15-bit constant.
2578 A constant in the range 1 to 65535 (inclusive).
2581 Floating-point zero.
2584 An address that can be used in a non-macro load or store.
2587 @item Motorola 680x0---@file{config/m68k/constraints.md}
2596 68881 floating-point register, if available
2599 Integer in the range 1 to 8
2602 16-bit signed number
2605 Signed number whose magnitude is greater than 0x80
2608 Integer in the range @minus{}8 to @minus{}1
2611 Signed number whose magnitude is greater than 0x100
2614 Range 24 to 31, rotatert:SI 8 to 1 expressed as rotate
2617 16 (for rotate using swap)
2620 Range 8 to 15, rotatert:HI 8 to 1 expressed as rotate
2623 Numbers that mov3q can handle
2626 Floating point constant that is not a 68881 constant
2629 Operands that satisfy 'm' when -mpcrel is in effect
2632 Operands that satisfy 's' when -mpcrel is not in effect
2635 Address register indirect addressing mode
2638 Register offset addressing
2653 Range of signed numbers that don't fit in 16 bits
2656 Integers valid for mvq
2659 Integers valid for a moveq followed by a swap
2662 Integers valid for mvz
2665 Integers valid for mvs
2671 Non-register operands allowed in clr
2675 @item Motorola 68HC11 & 68HC12 families---@file{config/m68hc11/m68hc11.h}
2690 Temporary soft register _.tmp
2693 A soft register _.d1 to _.d31
2696 Stack pointer register
2705 Pseudo register `z' (replaced by `x' or `y' at the end)
2708 An address register: x, y or z
2711 An address register: x or y
2714 Register pair (x:d) to form a 32-bit value
2717 Constants in the range @minus{}65536 to 65535
2720 Constants whose 16-bit low part is zero
2723 Constant integer 1 or @minus{}1
2729 Constants in the range @minus{}8 to 2
2733 @item Moxie---@file{config/moxie/constraints.md}
2742 A register indirect memory operand
2745 A constant in the range of 0 to 255.
2748 A constant in the range of 0 to -255.
2753 @item SPARC---@file{config/sparc/sparc.h}
2756 Floating-point register on the SPARC-V8 architecture and
2757 lower floating-point register on the SPARC-V9 architecture.
2760 Floating-point register. It is equivalent to @samp{f} on the
2761 SPARC-V8 architecture and contains both lower and upper
2762 floating-point registers on the SPARC-V9 architecture.
2765 Floating-point condition code register.
2768 Lower floating-point register. It is only valid on the SPARC-V9
2769 architecture when the Visual Instruction Set is available.
2772 Floating-point register. It is only valid on the SPARC-V9 architecture
2773 when the Visual Instruction Set is available.
2776 64-bit global or out register for the SPARC-V8+ architecture.
2782 Signed 13-bit constant
2788 32-bit constant with the low 12 bits clear (a constant that can be
2789 loaded with the @code{sethi} instruction)
2792 A constant in the range supported by @code{movcc} instructions
2795 A constant in the range supported by @code{movrcc} instructions
2798 Same as @samp{K}, except that it verifies that bits that are not in the
2799 lower 32-bit range are all zero. Must be used instead of @samp{K} for
2800 modes wider than @code{SImode}
2809 Signed 13-bit constant, sign-extended to 32 or 64 bits
2812 Floating-point constant whose integral representation can
2813 be moved into an integer register using a single sethi
2817 Floating-point constant whose integral representation can
2818 be moved into an integer register using a single mov
2822 Floating-point constant whose integral representation can
2823 be moved into an integer register using a high/lo_sum
2824 instruction sequence
2827 Memory address aligned to an 8-byte boundary
2833 Memory address for @samp{e} constraint registers
2840 @item SPU---@file{config/spu/spu.h}
2843 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value.
2846 An immediate for and/xor/or instructions. const_int is treated as a 64 bit value.
2849 An immediate for the @code{iohl} instruction. const_int is treated as a 64 bit value.
2852 An immediate which can be loaded with @code{fsmbi}.
2855 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value.
2858 An immediate for most arithmetic instructions. const_int is treated as a 32 bit value.
2861 An immediate for and/xor/or instructions. const_int is treated as a 32 bit value.
2864 An immediate for the @code{iohl} instruction. const_int is treated as a 32 bit value.
2867 A constant in the range [-64, 63] for shift/rotate instructions.
2870 An unsigned 7-bit constant for conversion/nop/channel instructions.
2873 A signed 10-bit constant for most arithmetic instructions.
2876 A signed 16 bit immediate for @code{stop}.
2879 An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}.
2882 An unsigned 7-bit constant whose 3 least significant bits are 0.
2885 An unsigned 3-bit constant for 16-byte rotates and shifts
2888 Call operand, reg, for indirect calls
2891 Call operand, symbol, for relative calls.
2894 Call operand, const_int, for absolute calls.
2897 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit.
2900 An immediate for shift and rotate instructions. const_int is treated as a 32 bit value.
2903 An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit.
2906 An immediate for the @code{iohl} instruction. const_int is sign extended to 128 bit.
2910 @item S/390 and zSeries---@file{config/s390/s390.h}
2913 Address register (general purpose register except r0)
2916 Condition code register
2919 Data register (arbitrary general purpose register)
2922 Floating-point register
2925 Unsigned 8-bit constant (0--255)
2928 Unsigned 12-bit constant (0--4095)
2931 Signed 16-bit constant (@minus{}32768--32767)
2934 Value appropriate as displacement.
2937 for short displacement
2938 @item (-524288..524287)
2939 for long displacement
2943 Constant integer with a value of 0x7fffffff.
2946 Multiple letter constraint followed by 4 parameter letters.
2949 number of the part counting from most to least significant
2953 mode of the containing operand
2955 value of the other parts (F---all bits set)
2957 The constraint matches if the specified part of a constant
2958 has a value different from its other parts.
2961 Memory reference without index register and with short displacement.
2964 Memory reference with index register and short displacement.
2967 Memory reference without index register but with long displacement.
2970 Memory reference with index register and long displacement.
2973 Pointer with short displacement.
2976 Pointer with long displacement.
2979 Shift count operand.
2983 @item Score family---@file{config/score/score.h}
2986 Registers from r0 to r32.
2989 Registers from r0 to r16.
2992 r8---r11 or r22---r27 registers.
3013 cnt + lcb + scb register.
3016 cr0---cr15 register.
3028 cp1 + cp2 + cp3 registers.
3031 High 16-bit constant (32-bit constant with 16 LSBs zero).
3034 Unsigned 5 bit integer (in the range 0 to 31).
3037 Unsigned 16 bit integer (in the range 0 to 65535).
3040 Signed 16 bit integer (in the range @minus{}32768 to 32767).
3043 Unsigned 14 bit integer (in the range 0 to 16383).
3046 Signed 14 bit integer (in the range @minus{}8192 to 8191).
3052 @item Xstormy16---@file{config/stormy16/stormy16.h}
3067 Registers r0 through r7.
3070 Registers r0 and r1.
3076 Registers r8 and r9.
3079 A constant between 0 and 3 inclusive.
3082 A constant that has exactly one bit set.
3085 A constant that has exactly one bit clear.
3088 A constant between 0 and 255 inclusive.
3091 A constant between @minus{}255 and 0 inclusive.
3094 A constant between @minus{}3 and 0 inclusive.
3097 A constant between 1 and 4 inclusive.
3100 A constant between @minus{}4 and @minus{}1 inclusive.
3103 A memory reference that is a stack push.
3106 A memory reference that is a stack pop.
3109 A memory reference that refers to a constant address of known value.
3112 The register indicated by Rx (not implemented yet).
3115 A constant that is not between 2 and 15 inclusive.
3122 @item Xtensa---@file{config/xtensa/constraints.md}
3125 General-purpose 32-bit register
3128 One-bit boolean register
3131 MAC16 40-bit accumulator register
3134 Signed 12-bit integer constant, for use in MOVI instructions
3137 Signed 8-bit integer constant, for use in ADDI instructions
3140 Integer constant valid for BccI instructions
3143 Unsigned constant valid for BccUI instructions
3150 @node Disable Insn Alternatives
3151 @subsection Disable insn alternatives using the @code{enabled} attribute
3154 The @code{enabled} insn attribute may be used to disable certain insn
3155 alternatives for machine-specific reasons. This is useful when adding
3156 new instructions to an existing pattern which are only available for
3157 certain cpu architecture levels as specified with the @code{-march=}
3160 If an insn alternative is disabled, then it will never be used. The
3161 compiler treats the constraints for the disabled alternative as
3164 In order to make use of the @code{enabled} attribute a back end has to add
3165 in the machine description files:
3169 A definition of the @code{enabled} insn attribute. The attribute is
3170 defined as usual using the @code{define_attr} command. This
3171 definition should be based on other insn attributes and/or target flags.
3172 The @code{enabled} attribute is a numeric attribute and should evaluate to
3173 @code{(const_int 1)} for an enabled alternative and to
3174 @code{(const_int 0)} otherwise.
3176 A definition of another insn attribute used to describe for what
3177 reason an insn alternative might be available or
3178 not. E.g. @code{cpu_facility} as in the example below.
3180 An assignment for the second attribute to each insn definition
3181 combining instructions which are not all available under the same
3182 circumstances. (Note: It obviously only makes sense for definitions
3183 with more than one alternative. Otherwise the insn pattern should be
3184 disabled or enabled using the insn condition.)
3187 E.g. the following two patterns could easily be merged using the @code{enabled}
3192 (define_insn "*movdi_old"
3193 [(set (match_operand:DI 0 "register_operand" "=d")
3194 (match_operand:DI 1 "register_operand" " d"))]
3198 (define_insn "*movdi_new"
3199 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
3200 (match_operand:DI 1 "register_operand" " d,d,f"))]
3213 (define_insn "*movdi_combined"
3214 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
3215 (match_operand:DI 1 "register_operand" " d,d,f"))]
3221 [(set_attr "cpu_facility" "*,new,new")])
3225 with the @code{enabled} attribute defined like this:
3229 (define_attr "cpu_facility" "standard,new" (const_string "standard"))
3231 (define_attr "enabled" ""
3232 (cond [(eq_attr "cpu_facility" "standard") (const_int 1)
3233 (and (eq_attr "cpu_facility" "new")
3234 (ne (symbol_ref "TARGET_NEW") (const_int 0)))
3243 @node Define Constraints
3244 @subsection Defining Machine-Specific Constraints
3245 @cindex defining constraints
3246 @cindex constraints, defining
3248 Machine-specific constraints fall into two categories: register and
3249 non-register constraints. Within the latter category, constraints
3250 which allow subsets of all possible memory or address operands should
3251 be specially marked, to give @code{reload} more information.
3253 Machine-specific constraints can be given names of arbitrary length,
3254 but they must be entirely composed of letters, digits, underscores
3255 (@samp{_}), and angle brackets (@samp{< >}). Like C identifiers, they
3256 must begin with a letter or underscore.
3258 In order to avoid ambiguity in operand constraint strings, no
3259 constraint can have a name that begins with any other constraint's
3260 name. For example, if @code{x} is defined as a constraint name,
3261 @code{xy} may not be, and vice versa. As a consequence of this rule,
3262 no constraint may begin with one of the generic constraint letters:
3263 @samp{E F V X g i m n o p r s}.
3265 Register constraints correspond directly to register classes.
3266 @xref{Register Classes}. There is thus not much flexibility in their
3269 @deffn {MD Expression} define_register_constraint name regclass docstring
3270 All three arguments are string constants.
3271 @var{name} is the name of the constraint, as it will appear in
3272 @code{match_operand} expressions. If @var{name} is a multi-letter
3273 constraint its length shall be the same for all constraints starting
3274 with the same letter. @var{regclass} can be either the
3275 name of the corresponding register class (@pxref{Register Classes}),
3276 or a C expression which evaluates to the appropriate register class.
3277 If it is an expression, it must have no side effects, and it cannot
3278 look at the operand. The usual use of expressions is to map some
3279 register constraints to @code{NO_REGS} when the register class
3280 is not available on a given subarchitecture.
3282 @var{docstring} is a sentence documenting the meaning of the
3283 constraint. Docstrings are explained further below.
3286 Non-register constraints are more like predicates: the constraint
3287 definition gives a Boolean expression which indicates whether the
3290 @deffn {MD Expression} define_constraint name docstring exp
3291 The @var{name} and @var{docstring} arguments are the same as for
3292 @code{define_register_constraint}, but note that the docstring comes
3293 immediately after the name for these expressions. @var{exp} is an RTL
3294 expression, obeying the same rules as the RTL expressions in predicate
3295 definitions. @xref{Defining Predicates}, for details. If it
3296 evaluates true, the constraint matches; if it evaluates false, it
3297 doesn't. Constraint expressions should indicate which RTL codes they
3298 might match, just like predicate expressions.
3300 @code{match_test} C expressions have access to the
3301 following variables:
3305 The RTL object defining the operand.
3307 The machine mode of @var{op}.
3309 @samp{INTVAL (@var{op})}, if @var{op} is a @code{const_int}.
3311 @samp{CONST_DOUBLE_HIGH (@var{op})}, if @var{op} is an integer
3312 @code{const_double}.
3314 @samp{CONST_DOUBLE_LOW (@var{op})}, if @var{op} is an integer
3315 @code{const_double}.
3317 @samp{CONST_DOUBLE_REAL_VALUE (@var{op})}, if @var{op} is a floating-point
3318 @code{const_double}.
3321 The @var{*val} variables should only be used once another piece of the
3322 expression has verified that @var{op} is the appropriate kind of RTL
3326 Most non-register constraints should be defined with
3327 @code{define_constraint}. The remaining two definition expressions
3328 are only appropriate for constraints that should be handled specially
3329 by @code{reload} if they fail to match.
3331 @deffn {MD Expression} define_memory_constraint name docstring exp
3332 Use this expression for constraints that match a subset of all memory
3333 operands: that is, @code{reload} can make them match by converting the
3334 operand to the form @samp{@w{(mem (reg @var{X}))}}, where @var{X} is a
3335 base register (from the register class specified by
3336 @code{BASE_REG_CLASS}, @pxref{Register Classes}).
3338 For example, on the S/390, some instructions do not accept arbitrary
3339 memory references, but only those that do not make use of an index
3340 register. The constraint letter @samp{Q} is defined to represent a
3341 memory address of this type. If @samp{Q} is defined with
3342 @code{define_memory_constraint}, a @samp{Q} constraint can handle any
3343 memory operand, because @code{reload} knows it can simply copy the
3344 memory address into a base register if required. This is analogous to
3345 the way an @samp{o} constraint can handle any memory operand.
3347 The syntax and semantics are otherwise identical to
3348 @code{define_constraint}.
3351 @deffn {MD Expression} define_address_constraint name docstring exp
3352 Use this expression for constraints that match a subset of all address
3353 operands: that is, @code{reload} can make the constraint match by
3354 converting the operand to the form @samp{@w{(reg @var{X})}}, again
3355 with @var{X} a base register.
3357 Constraints defined with @code{define_address_constraint} can only be
3358 used with the @code{address_operand} predicate, or machine-specific
3359 predicates that work the same way. They are treated analogously to
3360 the generic @samp{p} constraint.
3362 The syntax and semantics are otherwise identical to
3363 @code{define_constraint}.
3366 For historical reasons, names beginning with the letters @samp{G H}
3367 are reserved for constraints that match only @code{const_double}s, and
3368 names beginning with the letters @samp{I J K L M N O P} are reserved
3369 for constraints that match only @code{const_int}s. This may change in
3370 the future. For the time being, constraints with these names must be
3371 written in a stylized form, so that @code{genpreds} can tell you did
3376 (define_constraint "[@var{GHIJKLMNOP}]@dots{}"
3378 (and (match_code "const_int") ; @r{@code{const_double} for G/H}
3379 @var{condition}@dots{})) ; @r{usually a @code{match_test}}
3382 @c the semicolons line up in the formatted manual
3384 It is fine to use names beginning with other letters for constraints
3385 that match @code{const_double}s or @code{const_int}s.
3387 Each docstring in a constraint definition should be one or more complete
3388 sentences, marked up in Texinfo format. @emph{They are currently unused.}
3389 In the future they will be copied into the GCC manual, in @ref{Machine
3390 Constraints}, replacing the hand-maintained tables currently found in
3391 that section. Also, in the future the compiler may use this to give
3392 more helpful diagnostics when poor choice of @code{asm} constraints
3393 causes a reload failure.
3395 If you put the pseudo-Texinfo directive @samp{@@internal} at the
3396 beginning of a docstring, then (in the future) it will appear only in
3397 the internals manual's version of the machine-specific constraint tables.
3398 Use this for constraints that should not appear in @code{asm} statements.
3400 @node C Constraint Interface
3401 @subsection Testing constraints from C
3402 @cindex testing constraints
3403 @cindex constraints, testing
3405 It is occasionally useful to test a constraint from C code rather than
3406 implicitly via the constraint string in a @code{match_operand}. The
3407 generated file @file{tm_p.h} declares a few interfaces for working
3408 with machine-specific constraints. None of these interfaces work with
3409 the generic constraints described in @ref{Simple Constraints}. This
3410 may change in the future.
3412 @strong{Warning:} @file{tm_p.h} may declare other functions that
3413 operate on constraints, besides the ones documented here. Do not use
3414 those functions from machine-dependent code. They exist to implement
3415 the old constraint interface that machine-independent components of
3416 the compiler still expect. They will change or disappear in the
3419 Some valid constraint names are not valid C identifiers, so there is a
3420 mangling scheme for referring to them from C@. Constraint names that
3421 do not contain angle brackets or underscores are left unchanged.
3422 Underscores are doubled, each @samp{<} is replaced with @samp{_l}, and
3423 each @samp{>} with @samp{_g}. Here are some examples:
3425 @c the @c's prevent double blank lines in the printed manual.
3427 @multitable {Original} {Mangled}
3428 @item @strong{Original} @tab @strong{Mangled} @c
3429 @item @code{x} @tab @code{x} @c
3430 @item @code{P42x} @tab @code{P42x} @c
3431 @item @code{P4_x} @tab @code{P4__x} @c
3432 @item @code{P4>x} @tab @code{P4_gx} @c
3433 @item @code{P4>>} @tab @code{P4_g_g} @c
3434 @item @code{P4_g>} @tab @code{P4__g_g} @c
3438 Throughout this section, the variable @var{c} is either a constraint
3439 in the abstract sense, or a constant from @code{enum constraint_num};
3440 the variable @var{m} is a mangled constraint name (usually as part of
3441 a larger identifier).
3443 @deftp Enum constraint_num
3444 For each machine-specific constraint, there is a corresponding
3445 enumeration constant: @samp{CONSTRAINT_} plus the mangled name of the
3446 constraint. Functions that take an @code{enum constraint_num} as an
3447 argument expect one of these constants.
3449 Machine-independent constraints do not have associated constants.
3450 This may change in the future.
3453 @deftypefun {inline bool} satisfies_constraint_@var{m} (rtx @var{exp})
3454 For each machine-specific, non-register constraint @var{m}, there is
3455 one of these functions; it returns @code{true} if @var{exp} satisfies the
3456 constraint. These functions are only visible if @file{rtl.h} was included
3457 before @file{tm_p.h}.
3460 @deftypefun bool constraint_satisfied_p (rtx @var{exp}, enum constraint_num @var{c})
3461 Like the @code{satisfies_constraint_@var{m}} functions, but the
3462 constraint to test is given as an argument, @var{c}. If @var{c}
3463 specifies a register constraint, this function will always return
3467 @deftypefun {enum reg_class} regclass_for_constraint (enum constraint_num @var{c})
3468 Returns the register class associated with @var{c}. If @var{c} is not
3469 a register constraint, or those registers are not available for the
3470 currently selected subtarget, returns @code{NO_REGS}.
3473 Here is an example use of @code{satisfies_constraint_@var{m}}. In
3474 peephole optimizations (@pxref{Peephole Definitions}), operand
3475 constraint strings are ignored, so if there are relevant constraints,
3476 they must be tested in the C condition. In the example, the
3477 optimization is applied if operand 2 does @emph{not} satisfy the
3478 @samp{K} constraint. (This is a simplified version of a peephole
3479 definition from the i386 machine description.)
3483 [(match_scratch:SI 3 "r")
3484 (set (match_operand:SI 0 "register_operand" "")
3485 (mult:SI (match_operand:SI 1 "memory_operand" "")
3486 (match_operand:SI 2 "immediate_operand" "")))]
3488 "!satisfies_constraint_K (operands[2])"
3490 [(set (match_dup 3) (match_dup 1))
3491 (set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))]
3496 @node Standard Names
3497 @section Standard Pattern Names For Generation
3498 @cindex standard pattern names
3499 @cindex pattern names
3500 @cindex names, pattern
3502 Here is a table of the instruction names that are meaningful in the RTL
3503 generation pass of the compiler. Giving one of these names to an
3504 instruction pattern tells the RTL generation pass that it can use the
3505 pattern to accomplish a certain task.
3508 @cindex @code{mov@var{m}} instruction pattern
3509 @item @samp{mov@var{m}}
3510 Here @var{m} stands for a two-letter machine mode name, in lowercase.
3511 This instruction pattern moves data with that machine mode from operand
3512 1 to operand 0. For example, @samp{movsi} moves full-word data.
3514 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
3515 own mode is wider than @var{m}, the effect of this instruction is
3516 to store the specified value in the part of the register that corresponds
3517 to mode @var{m}. Bits outside of @var{m}, but which are within the
3518 same target word as the @code{subreg} are undefined. Bits which are
3519 outside the target word are left unchanged.
3521 This class of patterns is special in several ways. First of all, each
3522 of these names up to and including full word size @emph{must} be defined,
3523 because there is no other way to copy a datum from one place to another.
3524 If there are patterns accepting operands in larger modes,
3525 @samp{mov@var{m}} must be defined for integer modes of those sizes.
3527 Second, these patterns are not used solely in the RTL generation pass.
3528 Even the reload pass can generate move insns to copy values from stack
3529 slots into temporary registers. When it does so, one of the operands is
3530 a hard register and the other is an operand that can need to be reloaded
3534 Therefore, when given such a pair of operands, the pattern must generate
3535 RTL which needs no reloading and needs no temporary registers---no
3536 registers other than the operands. For example, if you support the
3537 pattern with a @code{define_expand}, then in such a case the
3538 @code{define_expand} mustn't call @code{force_reg} or any other such
3539 function which might generate new pseudo registers.
3541 This requirement exists even for subword modes on a RISC machine where
3542 fetching those modes from memory normally requires several insns and
3543 some temporary registers.
3545 @findex change_address
3546 During reload a memory reference with an invalid address may be passed
3547 as an operand. Such an address will be replaced with a valid address
3548 later in the reload pass. In this case, nothing may be done with the
3549 address except to use it as it stands. If it is copied, it will not be
3550 replaced with a valid address. No attempt should be made to make such
3551 an address into a valid address and no routine (such as
3552 @code{change_address}) that will do so may be called. Note that
3553 @code{general_operand} will fail when applied to such an address.
3555 @findex reload_in_progress
3556 The global variable @code{reload_in_progress} (which must be explicitly
3557 declared if required) can be used to determine whether such special
3558 handling is required.
3560 The variety of operands that have reloads depends on the rest of the
3561 machine description, but typically on a RISC machine these can only be
3562 pseudo registers that did not get hard registers, while on other
3563 machines explicit memory references will get optional reloads.
3565 If a scratch register is required to move an object to or from memory,
3566 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
3568 If there are cases which need scratch registers during or after reload,
3569 you must provide an appropriate secondary_reload target hook.
3571 @findex can_create_pseudo_p
3572 The macro @code{can_create_pseudo_p} can be used to determine if it
3573 is unsafe to create new pseudo registers. If this variable is nonzero, then
3574 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
3576 The constraints on a @samp{mov@var{m}} must permit moving any hard
3577 register to any other hard register provided that
3578 @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
3579 @code{REGISTER_MOVE_COST} applied to their classes returns a value of 2.
3581 It is obligatory to support floating point @samp{mov@var{m}}
3582 instructions into and out of any registers that can hold fixed point
3583 values, because unions and structures (which have modes @code{SImode} or
3584 @code{DImode}) can be in those registers and they may have floating
3587 There may also be a need to support fixed point @samp{mov@var{m}}
3588 instructions in and out of floating point registers. Unfortunately, I
3589 have forgotten why this was so, and I don't know whether it is still
3590 true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
3591 floating point registers, then the constraints of the fixed point
3592 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
3593 reload into a floating point register.
3595 @cindex @code{reload_in} instruction pattern
3596 @cindex @code{reload_out} instruction pattern
3597 @item @samp{reload_in@var{m}}
3598 @itemx @samp{reload_out@var{m}}
3599 These named patterns have been obsoleted by the target hook
3600 @code{secondary_reload}.
3602 Like @samp{mov@var{m}}, but used when a scratch register is required to
3603 move between operand 0 and operand 1. Operand 2 describes the scratch
3604 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
3605 macro in @pxref{Register Classes}.
3607 There are special restrictions on the form of the @code{match_operand}s
3608 used in these patterns. First, only the predicate for the reload
3609 operand is examined, i.e., @code{reload_in} examines operand 1, but not
3610 the predicates for operand 0 or 2. Second, there may be only one
3611 alternative in the constraints. Third, only a single register class
3612 letter may be used for the constraint; subsequent constraint letters
3613 are ignored. As a special exception, an empty constraint string
3614 matches the @code{ALL_REGS} register class. This may relieve ports
3615 of the burden of defining an @code{ALL_REGS} constraint letter just
3618 @cindex @code{movstrict@var{m}} instruction pattern
3619 @item @samp{movstrict@var{m}}
3620 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
3621 with mode @var{m} of a register whose natural mode is wider,
3622 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
3623 any of the register except the part which belongs to mode @var{m}.
3625 @cindex @code{movmisalign@var{m}} instruction pattern
3626 @item @samp{movmisalign@var{m}}
3627 This variant of a move pattern is designed to load or store a value
3628 from a memory address that is not naturally aligned for its mode.
3629 For a store, the memory will be in operand 0; for a load, the memory
3630 will be in operand 1. The other operand is guaranteed not to be a
3631 memory, so that it's easy to tell whether this is a load or store.
3633 This pattern is used by the autovectorizer, and when expanding a
3634 @code{MISALIGNED_INDIRECT_REF} expression.
3636 @cindex @code{load_multiple} instruction pattern
3637 @item @samp{load_multiple}
3638 Load several consecutive memory locations into consecutive registers.
3639 Operand 0 is the first of the consecutive registers, operand 1
3640 is the first memory location, and operand 2 is a constant: the
3641 number of consecutive registers.
3643 Define this only if the target machine really has such an instruction;
3644 do not define this if the most efficient way of loading consecutive
3645 registers from memory is to do them one at a time.
3647 On some machines, there are restrictions as to which consecutive
3648 registers can be stored into memory, such as particular starting or
3649 ending register numbers or only a range of valid counts. For those
3650 machines, use a @code{define_expand} (@pxref{Expander Definitions})
3651 and make the pattern fail if the restrictions are not met.
3653 Write the generated insn as a @code{parallel} with elements being a
3654 @code{set} of one register from the appropriate memory location (you may
3655 also need @code{use} or @code{clobber} elements). Use a
3656 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
3657 @file{rs6000.md} for examples of the use of this insn pattern.
3659 @cindex @samp{store_multiple} instruction pattern
3660 @item @samp{store_multiple}
3661 Similar to @samp{load_multiple}, but store several consecutive registers
3662 into consecutive memory locations. Operand 0 is the first of the
3663 consecutive memory locations, operand 1 is the first register, and
3664 operand 2 is a constant: the number of consecutive registers.
3666 @cindex @code{vec_set@var{m}} instruction pattern
3667 @item @samp{vec_set@var{m}}
3668 Set given field in the vector value. Operand 0 is the vector to modify,
3669 operand 1 is new value of field and operand 2 specify the field index.
3671 @cindex @code{vec_extract@var{m}} instruction pattern
3672 @item @samp{vec_extract@var{m}}
3673 Extract given field from the vector value. Operand 1 is the vector, operand 2
3674 specify field index and operand 0 place to store value into.
3676 @cindex @code{vec_extract_even@var{m}} instruction pattern
3677 @item @samp{vec_extract_even@var{m}}
3678 Extract even elements from the input vectors (operand 1 and operand 2).
3679 The even elements of operand 2 are concatenated to the even elements of operand
3680 1 in their original order. The result is stored in operand 0.
3681 The output and input vectors should have the same modes.
3683 @cindex @code{vec_extract_odd@var{m}} instruction pattern
3684 @item @samp{vec_extract_odd@var{m}}
3685 Extract odd elements from the input vectors (operand 1 and operand 2).
3686 The odd elements of operand 2 are concatenated to the odd elements of operand
3687 1 in their original order. The result is stored in operand 0.
3688 The output and input vectors should have the same modes.
3690 @cindex @code{vec_interleave_high@var{m}} instruction pattern
3691 @item @samp{vec_interleave_high@var{m}}
3692 Merge high elements of the two input vectors into the output vector. The output
3693 and input vectors should have the same modes (@code{N} elements). The high
3694 @code{N/2} elements of the first input vector are interleaved with the high
3695 @code{N/2} elements of the second input vector.
3697 @cindex @code{vec_interleave_low@var{m}} instruction pattern
3698 @item @samp{vec_interleave_low@var{m}}
3699 Merge low elements of the two input vectors into the output vector. The output
3700 and input vectors should have the same modes (@code{N} elements). The low
3701 @code{N/2} elements of the first input vector are interleaved with the low
3702 @code{N/2} elements of the second input vector.
3704 @cindex @code{vec_init@var{m}} instruction pattern
3705 @item @samp{vec_init@var{m}}
3706 Initialize the vector to given values. Operand 0 is the vector to initialize
3707 and operand 1 is parallel containing values for individual fields.
3709 @cindex @code{push@var{m}1} instruction pattern
3710 @item @samp{push@var{m}1}
3711 Output a push instruction. Operand 0 is value to push. Used only when
3712 @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be
3713 missing and in such case an @code{mov} expander is used instead, with a
3714 @code{MEM} expression forming the push operation. The @code{mov} expander
3715 method is deprecated.
3717 @cindex @code{add@var{m}3} instruction pattern
3718 @item @samp{add@var{m}3}
3719 Add operand 2 and operand 1, storing the result in operand 0. All operands
3720 must have mode @var{m}. This can be used even on two-address machines, by
3721 means of constraints requiring operands 1 and 0 to be the same location.
3723 @cindex @code{ssadd@var{m}3} instruction pattern
3724 @cindex @code{usadd@var{m}3} instruction pattern
3725 @cindex @code{sub@var{m}3} instruction pattern
3726 @cindex @code{sssub@var{m}3} instruction pattern
3727 @cindex @code{ussub@var{m}3} instruction pattern
3728 @cindex @code{mul@var{m}3} instruction pattern
3729 @cindex @code{ssmul@var{m}3} instruction pattern
3730 @cindex @code{usmul@var{m}3} instruction pattern
3731 @cindex @code{div@var{m}3} instruction pattern
3732 @cindex @code{ssdiv@var{m}3} instruction pattern
3733 @cindex @code{udiv@var{m}3} instruction pattern
3734 @cindex @code{usdiv@var{m}3} instruction pattern
3735 @cindex @code{mod@var{m}3} instruction pattern
3736 @cindex @code{umod@var{m}3} instruction pattern
3737 @cindex @code{umin@var{m}3} instruction pattern
3738 @cindex @code{umax@var{m}3} instruction pattern
3739 @cindex @code{and@var{m}3} instruction pattern
3740 @cindex @code{ior@var{m}3} instruction pattern
3741 @cindex @code{xor@var{m}3} instruction pattern
3742 @item @samp{ssadd@var{m}3}, @samp{usadd@var{m}3}
3743 @item @samp{sub@var{m}3}, @samp{sssub@var{m}3}, @samp{ussub@var{m}3}
3744 @item @samp{mul@var{m}3}, @samp{ssmul@var{m}3}, @samp{usmul@var{m}3}
3745 @itemx @samp{div@var{m}3}, @samp{ssdiv@var{m}3}
3746 @itemx @samp{udiv@var{m}3}, @samp{usdiv@var{m}3}
3747 @itemx @samp{mod@var{m}3}, @samp{umod@var{m}3}
3748 @itemx @samp{umin@var{m}3}, @samp{umax@var{m}3}
3749 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
3750 Similar, for other arithmetic operations.
3752 @cindex @code{min@var{m}3} instruction pattern
3753 @cindex @code{max@var{m}3} instruction pattern
3754 @item @samp{smin@var{m}3}, @samp{smax@var{m}3}
3755 Signed minimum and maximum operations. When used with floating point,
3756 if both operands are zeros, or if either operand is @code{NaN}, then
3757 it is unspecified which of the two operands is returned as the result.
3759 @cindex @code{reduc_smin_@var{m}} instruction pattern
3760 @cindex @code{reduc_smax_@var{m}} instruction pattern
3761 @item @samp{reduc_smin_@var{m}}, @samp{reduc_smax_@var{m}}
3762 Find the signed minimum/maximum of the elements of a vector. The vector is
3763 operand 1, and the scalar result is stored in the least significant bits of
3764 operand 0 (also a vector). The output and input vector should have the same
3767 @cindex @code{reduc_umin_@var{m}} instruction pattern
3768 @cindex @code{reduc_umax_@var{m}} instruction pattern
3769 @item @samp{reduc_umin_@var{m}}, @samp{reduc_umax_@var{m}}
3770 Find the unsigned minimum/maximum of the elements of a vector. The vector is
3771 operand 1, and the scalar result is stored in the least significant bits of
3772 operand 0 (also a vector). The output and input vector should have the same
3775 @cindex @code{reduc_splus_@var{m}} instruction pattern
3776 @item @samp{reduc_splus_@var{m}}
3777 Compute the sum of the signed elements of a vector. The vector is operand 1,
3778 and the scalar result is stored in the least significant bits of operand 0
3779 (also a vector). The output and input vector should have the same modes.
3781 @cindex @code{reduc_uplus_@var{m}} instruction pattern
3782 @item @samp{reduc_uplus_@var{m}}
3783 Compute the sum of the unsigned elements of a vector. The vector is operand 1,
3784 and the scalar result is stored in the least significant bits of operand 0
3785 (also a vector). The output and input vector should have the same modes.
3787 @cindex @code{sdot_prod@var{m}} instruction pattern
3788 @item @samp{sdot_prod@var{m}}
3789 @cindex @code{udot_prod@var{m}} instruction pattern
3790 @item @samp{udot_prod@var{m}}
3791 Compute the sum of the products of two signed/unsigned elements.
3792 Operand 1 and operand 2 are of the same mode. Their product, which is of a
3793 wider mode, is computed and added to operand 3. Operand 3 is of a mode equal or
3794 wider than the mode of the product. The result is placed in operand 0, which
3795 is of the same mode as operand 3.
3797 @cindex @code{ssum_widen@var{m3}} instruction pattern
3798 @item @samp{ssum_widen@var{m3}}
3799 @cindex @code{usum_widen@var{m3}} instruction pattern
3800 @item @samp{usum_widen@var{m3}}
3801 Operands 0 and 2 are of the same mode, which is wider than the mode of
3802 operand 1. Add operand 1 to operand 2 and place the widened result in
3803 operand 0. (This is used express accumulation of elements into an accumulator
3806 @cindex @code{vec_shl_@var{m}} instruction pattern
3807 @cindex @code{vec_shr_@var{m}} instruction pattern
3808 @item @samp{vec_shl_@var{m}}, @samp{vec_shr_@var{m}}
3809 Whole vector left/right shift in bits.
3810 Operand 1 is a vector to be shifted.
3811 Operand 2 is an integer shift amount in bits.
3812 Operand 0 is where the resulting shifted vector is stored.
3813 The output and input vectors should have the same modes.
3815 @cindex @code{vec_pack_trunc_@var{m}} instruction pattern
3816 @item @samp{vec_pack_trunc_@var{m}}
3817 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
3818 are vectors of the same mode having N integral or floating point elements
3819 of size S@. Operand 0 is the resulting vector in which 2*N elements of
3820 size N/2 are concatenated after narrowing them down using truncation.
3822 @cindex @code{vec_pack_ssat_@var{m}} instruction pattern
3823 @cindex @code{vec_pack_usat_@var{m}} instruction pattern
3824 @item @samp{vec_pack_ssat_@var{m}}, @samp{vec_pack_usat_@var{m}}
3825 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
3826 are vectors of the same mode having N integral elements of size S.
3827 Operand 0 is the resulting vector in which the elements of the two input
3828 vectors are concatenated after narrowing them down using signed/unsigned
3829 saturating arithmetic.
3831 @cindex @code{vec_pack_sfix_trunc_@var{m}} instruction pattern
3832 @cindex @code{vec_pack_ufix_trunc_@var{m}} instruction pattern
3833 @item @samp{vec_pack_sfix_trunc_@var{m}}, @samp{vec_pack_ufix_trunc_@var{m}}
3834 Narrow, convert to signed/unsigned integral type and merge the elements
3835 of two vectors. Operands 1 and 2 are vectors of the same mode having N
3836 floating point elements of size S@. Operand 0 is the resulting vector
3837 in which 2*N elements of size N/2 are concatenated.
3839 @cindex @code{vec_unpacks_hi_@var{m}} instruction pattern
3840 @cindex @code{vec_unpacks_lo_@var{m}} instruction pattern
3841 @item @samp{vec_unpacks_hi_@var{m}}, @samp{vec_unpacks_lo_@var{m}}
3842 Extract and widen (promote) the high/low part of a vector of signed
3843 integral or floating point elements. The input vector (operand 1) has N
3844 elements of size S@. Widen (promote) the high/low elements of the vector
3845 using signed or floating point extension and place the resulting N/2
3846 values of size 2*S in the output vector (operand 0).
3848 @cindex @code{vec_unpacku_hi_@var{m}} instruction pattern
3849 @cindex @code{vec_unpacku_lo_@var{m}} instruction pattern
3850 @item @samp{vec_unpacku_hi_@var{m}}, @samp{vec_unpacku_lo_@var{m}}
3851 Extract and widen (promote) the high/low part of a vector of unsigned
3852 integral elements. The input vector (operand 1) has N elements of size S.
3853 Widen (promote) the high/low elements of the vector using zero extension and
3854 place the resulting N/2 values of size 2*S in the output vector (operand 0).
3856 @cindex @code{vec_unpacks_float_hi_@var{m}} instruction pattern
3857 @cindex @code{vec_unpacks_float_lo_@var{m}} instruction pattern
3858 @cindex @code{vec_unpacku_float_hi_@var{m}} instruction pattern
3859 @cindex @code{vec_unpacku_float_lo_@var{m}} instruction pattern
3860 @item @samp{vec_unpacks_float_hi_@var{m}}, @samp{vec_unpacks_float_lo_@var{m}}
3861 @itemx @samp{vec_unpacku_float_hi_@var{m}}, @samp{vec_unpacku_float_lo_@var{m}}
3862 Extract, convert to floating point type and widen the high/low part of a
3863 vector of signed/unsigned integral elements. The input vector (operand 1)
3864 has N elements of size S@. Convert the high/low elements of the vector using
3865 floating point conversion and place the resulting N/2 values of size 2*S in
3866 the output vector (operand 0).
3868 @cindex @code{vec_widen_umult_hi_@var{m}} instruction pattern
3869 @cindex @code{vec_widen_umult_lo__@var{m}} instruction pattern
3870 @cindex @code{vec_widen_smult_hi_@var{m}} instruction pattern
3871 @cindex @code{vec_widen_smult_lo_@var{m}} instruction pattern
3872 @item @samp{vec_widen_umult_hi_@var{m}}, @samp{vec_widen_umult_lo_@var{m}}
3873 @itemx @samp{vec_widen_smult_hi_@var{m}}, @samp{vec_widen_smult_lo_@var{m}}
3874 Signed/Unsigned widening multiplication. The two inputs (operands 1 and 2)
3875 are vectors with N signed/unsigned elements of size S@. Multiply the high/low
3876 elements of the two vectors, and put the N/2 products of size 2*S in the
3877 output vector (operand 0).
3879 @cindex @code{mulhisi3} instruction pattern
3880 @item @samp{mulhisi3}
3881 Multiply operands 1 and 2, which have mode @code{HImode}, and store
3882 a @code{SImode} product in operand 0.
3884 @cindex @code{mulqihi3} instruction pattern
3885 @cindex @code{mulsidi3} instruction pattern
3886 @item @samp{mulqihi3}, @samp{mulsidi3}
3887 Similar widening-multiplication instructions of other widths.
3889 @cindex @code{umulqihi3} instruction pattern
3890 @cindex @code{umulhisi3} instruction pattern
3891 @cindex @code{umulsidi3} instruction pattern
3892 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
3893 Similar widening-multiplication instructions that do unsigned
3896 @cindex @code{usmulqihi3} instruction pattern
3897 @cindex @code{usmulhisi3} instruction pattern
3898 @cindex @code{usmulsidi3} instruction pattern
3899 @item @samp{usmulqihi3}, @samp{usmulhisi3}, @samp{usmulsidi3}
3900 Similar widening-multiplication instructions that interpret the first
3901 operand as unsigned and the second operand as signed, then do a signed
3904 @cindex @code{smul@var{m}3_highpart} instruction pattern
3905 @item @samp{smul@var{m}3_highpart}
3906 Perform a signed multiplication of operands 1 and 2, which have mode
3907 @var{m}, and store the most significant half of the product in operand 0.
3908 The least significant half of the product is discarded.
3910 @cindex @code{umul@var{m}3_highpart} instruction pattern
3911 @item @samp{umul@var{m}3_highpart}
3912 Similar, but the multiplication is unsigned.
3914 @cindex @code{madd@var{m}@var{n}4} instruction pattern
3915 @item @samp{madd@var{m}@var{n}4}
3916 Multiply operands 1 and 2, sign-extend them to mode @var{n}, add
3917 operand 3, and store the result in operand 0. Operands 1 and 2
3918 have mode @var{m} and operands 0 and 3 have mode @var{n}.
3919 Both modes must be integer or fixed-point modes and @var{n} must be twice
3920 the size of @var{m}.
3922 In other words, @code{madd@var{m}@var{n}4} is like
3923 @code{mul@var{m}@var{n}3} except that it also adds operand 3.
3925 These instructions are not allowed to @code{FAIL}.
3927 @cindex @code{umadd@var{m}@var{n}4} instruction pattern
3928 @item @samp{umadd@var{m}@var{n}4}
3929 Like @code{madd@var{m}@var{n}4}, but zero-extend the multiplication
3930 operands instead of sign-extending them.
3932 @cindex @code{ssmadd@var{m}@var{n}4} instruction pattern
3933 @item @samp{ssmadd@var{m}@var{n}4}
3934 Like @code{madd@var{m}@var{n}4}, but all involved operations must be
3937 @cindex @code{usmadd@var{m}@var{n}4} instruction pattern
3938 @item @samp{usmadd@var{m}@var{n}4}
3939 Like @code{umadd@var{m}@var{n}4}, but all involved operations must be
3940 unsigned-saturating.
3942 @cindex @code{msub@var{m}@var{n}4} instruction pattern
3943 @item @samp{msub@var{m}@var{n}4}
3944 Multiply operands 1 and 2, sign-extend them to mode @var{n}, subtract the
3945 result from operand 3, and store the result in operand 0. Operands 1 and 2
3946 have mode @var{m} and operands 0 and 3 have mode @var{n}.
3947 Both modes must be integer or fixed-point modes and @var{n} must be twice
3948 the size of @var{m}.
3950 In other words, @code{msub@var{m}@var{n}4} is like
3951 @code{mul@var{m}@var{n}3} except that it also subtracts the result
3954 These instructions are not allowed to @code{FAIL}.
3956 @cindex @code{umsub@var{m}@var{n}4} instruction pattern
3957 @item @samp{umsub@var{m}@var{n}4}
3958 Like @code{msub@var{m}@var{n}4}, but zero-extend the multiplication
3959 operands instead of sign-extending them.
3961 @cindex @code{ssmsub@var{m}@var{n}4} instruction pattern
3962 @item @samp{ssmsub@var{m}@var{n}4}
3963 Like @code{msub@var{m}@var{n}4}, but all involved operations must be
3966 @cindex @code{usmsub@var{m}@var{n}4} instruction pattern
3967 @item @samp{usmsub@var{m}@var{n}4}
3968 Like @code{umsub@var{m}@var{n}4}, but all involved operations must be
3969 unsigned-saturating.
3971 @cindex @code{divmod@var{m}4} instruction pattern
3972 @item @samp{divmod@var{m}4}
3973 Signed division that produces both a quotient and a remainder.
3974 Operand 1 is divided by operand 2 to produce a quotient stored
3975 in operand 0 and a remainder stored in operand 3.
3977 For machines with an instruction that produces both a quotient and a
3978 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
3979 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
3980 allows optimization in the relatively common case when both the quotient
3981 and remainder are computed.
3983 If an instruction that just produces a quotient or just a remainder
3984 exists and is more efficient than the instruction that produces both,
3985 write the output routine of @samp{divmod@var{m}4} to call
3986 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
3987 quotient or remainder and generate the appropriate instruction.
3989 @cindex @code{udivmod@var{m}4} instruction pattern
3990 @item @samp{udivmod@var{m}4}
3991 Similar, but does unsigned division.
3993 @anchor{shift patterns}
3994 @cindex @code{ashl@var{m}3} instruction pattern
3995 @cindex @code{ssashl@var{m}3} instruction pattern
3996 @cindex @code{usashl@var{m}3} instruction pattern
3997 @item @samp{ashl@var{m}3}, @samp{ssashl@var{m}3}, @samp{usashl@var{m}3}
3998 Arithmetic-shift operand 1 left by a number of bits specified by operand
3999 2, and store the result in operand 0. Here @var{m} is the mode of
4000 operand 0 and operand 1; operand 2's mode is specified by the
4001 instruction pattern, and the compiler will convert the operand to that
4002 mode before generating the instruction. The meaning of out-of-range shift
4003 counts can optionally be specified by @code{TARGET_SHIFT_TRUNCATION_MASK}.
4004 @xref{TARGET_SHIFT_TRUNCATION_MASK}. Operand 2 is always a scalar type.
4006 @cindex @code{ashr@var{m}3} instruction pattern
4007 @cindex @code{lshr@var{m}3} instruction pattern
4008 @cindex @code{rotl@var{m}3} instruction pattern
4009 @cindex @code{rotr@var{m}3} instruction pattern
4010 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
4011 Other shift and rotate instructions, analogous to the
4012 @code{ashl@var{m}3} instructions. Operand 2 is always a scalar type.
4014 @cindex @code{vashl@var{m}3} instruction pattern
4015 @cindex @code{vashr@var{m}3} instruction pattern
4016 @cindex @code{vlshr@var{m}3} instruction pattern
4017 @cindex @code{vrotl@var{m}3} instruction pattern
4018 @cindex @code{vrotr@var{m}3} instruction pattern
4019 @item @samp{vashl@var{m}3}, @samp{vashr@var{m}3}, @samp{vlshr@var{m}3}, @samp{vrotl@var{m}3}, @samp{vrotr@var{m}3}
4020 Vector shift and rotate instructions that take vectors as operand 2
4021 instead of a scalar type.
4023 @cindex @code{neg@var{m}2} instruction pattern
4024 @cindex @code{ssneg@var{m}2} instruction pattern
4025 @cindex @code{usneg@var{m}2} instruction pattern
4026 @item @samp{neg@var{m}2}, @samp{ssneg@var{m}2}, @samp{usneg@var{m}2}
4027 Negate operand 1 and store the result in operand 0.
4029 @cindex @code{abs@var{m}2} instruction pattern
4030 @item @samp{abs@var{m}2}
4031 Store the absolute value of operand 1 into operand 0.
4033 @cindex @code{sqrt@var{m}2} instruction pattern
4034 @item @samp{sqrt@var{m}2}
4035 Store the square root of operand 1 into operand 0.
4037 The @code{sqrt} built-in function of C always uses the mode which
4038 corresponds to the C data type @code{double} and the @code{sqrtf}
4039 built-in function uses the mode which corresponds to the C data
4042 @cindex @code{fmod@var{m}3} instruction pattern
4043 @item @samp{fmod@var{m}3}
4044 Store the remainder of dividing operand 1 by operand 2 into
4045 operand 0, rounded towards zero to an integer.
4047 The @code{fmod} built-in function of C always uses the mode which
4048 corresponds to the C data type @code{double} and the @code{fmodf}
4049 built-in function uses the mode which corresponds to the C data
4052 @cindex @code{remainder@var{m}3} instruction pattern
4053 @item @samp{remainder@var{m}3}
4054 Store the remainder of dividing operand 1 by operand 2 into
4055 operand 0, rounded to the nearest integer.
4057 The @code{remainder} built-in function of C always uses the mode
4058 which corresponds to the C data type @code{double} and the
4059 @code{remainderf} built-in function uses the mode which corresponds
4060 to the C data type @code{float}.
4062 @cindex @code{cos@var{m}2} instruction pattern
4063 @item @samp{cos@var{m}2}
4064 Store the cosine of operand 1 into operand 0.
4066 The @code{cos} built-in function of C always uses the mode which
4067 corresponds to the C data type @code{double} and the @code{cosf}
4068 built-in function uses the mode which corresponds to the C data
4071 @cindex @code{sin@var{m}2} instruction pattern
4072 @item @samp{sin@var{m}2}
4073 Store the sine of operand 1 into operand 0.
4075 The @code{sin} built-in function of C always uses the mode which
4076 corresponds to the C data type @code{double} and the @code{sinf}
4077 built-in function uses the mode which corresponds to the C data
4080 @cindex @code{exp@var{m}2} instruction pattern
4081 @item @samp{exp@var{m}2}
4082 Store the exponential of operand 1 into operand 0.
4084 The @code{exp} built-in function of C always uses the mode which
4085 corresponds to the C data type @code{double} and the @code{expf}
4086 built-in function uses the mode which corresponds to the C data
4089 @cindex @code{log@var{m}2} instruction pattern
4090 @item @samp{log@var{m}2}
4091 Store the natural logarithm of operand 1 into operand 0.
4093 The @code{log} built-in function of C always uses the mode which
4094 corresponds to the C data type @code{double} and the @code{logf}
4095 built-in function uses the mode which corresponds to the C data
4098 @cindex @code{pow@var{m}3} instruction pattern
4099 @item @samp{pow@var{m}3}
4100 Store the value of operand 1 raised to the exponent operand 2
4103 The @code{pow} built-in function of C always uses the mode which
4104 corresponds to the C data type @code{double} and the @code{powf}
4105 built-in function uses the mode which corresponds to the C data
4108 @cindex @code{atan2@var{m}3} instruction pattern
4109 @item @samp{atan2@var{m}3}
4110 Store the arc tangent (inverse tangent) of operand 1 divided by
4111 operand 2 into operand 0, using the signs of both arguments to
4112 determine the quadrant of the result.
4114 The @code{atan2} built-in function of C always uses the mode which
4115 corresponds to the C data type @code{double} and the @code{atan2f}
4116 built-in function uses the mode which corresponds to the C data
4119 @cindex @code{floor@var{m}2} instruction pattern
4120 @item @samp{floor@var{m}2}
4121 Store the largest integral value not greater than argument.
4123 The @code{floor} built-in function of C always uses the mode which
4124 corresponds to the C data type @code{double} and the @code{floorf}
4125 built-in function uses the mode which corresponds to the C data
4128 @cindex @code{btrunc@var{m}2} instruction pattern
4129 @item @samp{btrunc@var{m}2}
4130 Store the argument rounded to integer towards zero.
4132 The @code{trunc} built-in function of C always uses the mode which
4133 corresponds to the C data type @code{double} and the @code{truncf}
4134 built-in function uses the mode which corresponds to the C data
4137 @cindex @code{round@var{m}2} instruction pattern
4138 @item @samp{round@var{m}2}
4139 Store the argument rounded to integer away from zero.
4141 The @code{round} built-in function of C always uses the mode which
4142 corresponds to the C data type @code{double} and the @code{roundf}
4143 built-in function uses the mode which corresponds to the C data
4146 @cindex @code{ceil@var{m}2} instruction pattern
4147 @item @samp{ceil@var{m}2}
4148 Store the argument rounded to integer away from zero.
4150 The @code{ceil} built-in function of C always uses the mode which
4151 corresponds to the C data type @code{double} and the @code{ceilf}
4152 built-in function uses the mode which corresponds to the C data
4155 @cindex @code{nearbyint@var{m}2} instruction pattern
4156 @item @samp{nearbyint@var{m}2}
4157 Store the argument rounded according to the default rounding mode
4159 The @code{nearbyint} built-in function of C always uses the mode which
4160 corresponds to the C data type @code{double} and the @code{nearbyintf}
4161 built-in function uses the mode which corresponds to the C data
4164 @cindex @code{rint@var{m}2} instruction pattern
4165 @item @samp{rint@var{m}2}
4166 Store the argument rounded according to the default rounding mode and
4167 raise the inexact exception when the result differs in value from
4170 The @code{rint} built-in function of C always uses the mode which
4171 corresponds to the C data type @code{double} and the @code{rintf}
4172 built-in function uses the mode which corresponds to the C data
4175 @cindex @code{lrint@var{m}@var{n}2}
4176 @item @samp{lrint@var{m}@var{n}2}
4177 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4178 point mode @var{n} as a signed number according to the current
4179 rounding mode and store in operand 0 (which has mode @var{n}).
4181 @cindex @code{lround@var{m}@var{n}2}
4182 @item @samp{lround@var{m}2}
4183 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4184 point mode @var{n} as a signed number rounding to nearest and away
4185 from zero and store in operand 0 (which has mode @var{n}).
4187 @cindex @code{lfloor@var{m}@var{n}2}
4188 @item @samp{lfloor@var{m}2}
4189 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4190 point mode @var{n} as a signed number rounding down and store in
4191 operand 0 (which has mode @var{n}).
4193 @cindex @code{lceil@var{m}@var{n}2}
4194 @item @samp{lceil@var{m}2}
4195 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4196 point mode @var{n} as a signed number rounding up and store in
4197 operand 0 (which has mode @var{n}).
4199 @cindex @code{copysign@var{m}3} instruction pattern
4200 @item @samp{copysign@var{m}3}
4201 Store a value with the magnitude of operand 1 and the sign of operand
4204 The @code{copysign} built-in function of C always uses the mode which
4205 corresponds to the C data type @code{double} and the @code{copysignf}
4206 built-in function uses the mode which corresponds to the C data
4209 @cindex @code{ffs@var{m}2} instruction pattern
4210 @item @samp{ffs@var{m}2}
4211 Store into operand 0 one plus the index of the least significant 1-bit
4212 of operand 1. If operand 1 is zero, store zero. @var{m} is the mode
4213 of operand 0; operand 1's mode is specified by the instruction
4214 pattern, and the compiler will convert the operand to that mode before
4215 generating the instruction.
4217 The @code{ffs} built-in function of C always uses the mode which
4218 corresponds to the C data type @code{int}.
4220 @cindex @code{clz@var{m}2} instruction pattern
4221 @item @samp{clz@var{m}2}
4222 Store into operand 0 the number of leading 0-bits in @var{x}, starting
4223 at the most significant bit position. If @var{x} is 0, the
4224 @code{CLZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
4225 the result is undefined or has a useful value.
4226 @var{m} is the mode of operand 0; operand 1's mode is
4227 specified by the instruction pattern, and the compiler will convert the
4228 operand to that mode before generating the instruction.
4230 @cindex @code{ctz@var{m}2} instruction pattern
4231 @item @samp{ctz@var{m}2}
4232 Store into operand 0 the number of trailing 0-bits in @var{x}, starting
4233 at the least significant bit position. If @var{x} is 0, the
4234 @code{CTZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
4235 the result is undefined or has a useful value.
4236 @var{m} is the mode of operand 0; operand 1's mode is
4237 specified by the instruction pattern, and the compiler will convert the
4238 operand to that mode before generating the instruction.
4240 @cindex @code{popcount@var{m}2} instruction pattern
4241 @item @samp{popcount@var{m}2}
4242 Store into operand 0 the number of 1-bits in @var{x}. @var{m} is the
4243 mode of operand 0; operand 1's mode is specified by the instruction
4244 pattern, and the compiler will convert the operand to that mode before
4245 generating the instruction.
4247 @cindex @code{parity@var{m}2} instruction pattern
4248 @item @samp{parity@var{m}2}
4249 Store into operand 0 the parity of @var{x}, i.e.@: the number of 1-bits
4250 in @var{x} modulo 2. @var{m} is the mode of operand 0; operand 1's mode
4251 is specified by the instruction pattern, and the compiler will convert
4252 the operand to that mode before generating the instruction.
4254 @cindex @code{one_cmpl@var{m}2} instruction pattern
4255 @item @samp{one_cmpl@var{m}2}
4256 Store the bitwise-complement of operand 1 into operand 0.
4258 @cindex @code{movmem@var{m}} instruction pattern
4259 @item @samp{movmem@var{m}}
4260 Block move instruction. The destination and source blocks of memory
4261 are the first two operands, and both are @code{mem:BLK}s with an
4262 address in mode @code{Pmode}.
4264 The number of bytes to move is the third operand, in mode @var{m}.
4265 Usually, you specify @code{word_mode} for @var{m}. However, if you can
4266 generate better code knowing the range of valid lengths is smaller than
4267 those representable in a full word, you should provide a pattern with a
4268 mode corresponding to the range of values you can handle efficiently
4269 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
4270 that appear negative) and also a pattern with @code{word_mode}.
4272 The fourth operand is the known shared alignment of the source and
4273 destination, in the form of a @code{const_int} rtx. Thus, if the
4274 compiler knows that both source and destination are word-aligned,
4275 it may provide the value 4 for this operand.
4277 Optional operands 5 and 6 specify expected alignment and size of block
4278 respectively. The expected alignment differs from alignment in operand 4
4279 in a way that the blocks are not required to be aligned according to it in
4280 all cases. This expected alignment is also in bytes, just like operand 4.
4281 Expected size, when unknown, is set to @code{(const_int -1)}.
4283 Descriptions of multiple @code{movmem@var{m}} patterns can only be
4284 beneficial if the patterns for smaller modes have fewer restrictions
4285 on their first, second and fourth operands. Note that the mode @var{m}
4286 in @code{movmem@var{m}} does not impose any restriction on the mode of
4287 individually moved data units in the block.
4289 These patterns need not give special consideration to the possibility
4290 that the source and destination strings might overlap.
4292 @cindex @code{movstr} instruction pattern
4294 String copy instruction, with @code{stpcpy} semantics. Operand 0 is
4295 an output operand in mode @code{Pmode}. The addresses of the
4296 destination and source strings are operands 1 and 2, and both are
4297 @code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of
4298 the expansion of this pattern should store in operand 0 the address in
4299 which the @code{NUL} terminator was stored in the destination string.
4301 @cindex @code{setmem@var{m}} instruction pattern
4302 @item @samp{setmem@var{m}}
4303 Block set instruction. The destination string is the first operand,
4304 given as a @code{mem:BLK} whose address is in mode @code{Pmode}. The
4305 number of bytes to set is the second operand, in mode @var{m}. The value to
4306 initialize the memory with is the third operand. Targets that only support the
4307 clearing of memory should reject any value that is not the constant 0. See
4308 @samp{movmem@var{m}} for a discussion of the choice of mode.
4310 The fourth operand is the known alignment of the destination, in the form
4311 of a @code{const_int} rtx. Thus, if the compiler knows that the
4312 destination is word-aligned, it may provide the value 4 for this
4315 Optional operands 5 and 6 specify expected alignment and size of block
4316 respectively. The expected alignment differs from alignment in operand 4
4317 in a way that the blocks are not required to be aligned according to it in
4318 all cases. This expected alignment is also in bytes, just like operand 4.
4319 Expected size, when unknown, is set to @code{(const_int -1)}.
4321 The use for multiple @code{setmem@var{m}} is as for @code{movmem@var{m}}.
4323 @cindex @code{cmpstrn@var{m}} instruction pattern
4324 @item @samp{cmpstrn@var{m}}
4325 String compare instruction, with five operands. Operand 0 is the output;
4326 it has mode @var{m}. The remaining four operands are like the operands
4327 of @samp{movmem@var{m}}. The two memory blocks specified are compared
4328 byte by byte in lexicographic order starting at the beginning of each
4329 string. The instruction is not allowed to prefetch more than one byte
4330 at a time since either string may end in the first byte and reading past
4331 that may access an invalid page or segment and cause a fault. The
4332 effect of the instruction is to store a value in operand 0 whose sign
4333 indicates the result of the comparison.
4335 @cindex @code{cmpstr@var{m}} instruction pattern
4336 @item @samp{cmpstr@var{m}}
4337 String compare instruction, without known maximum length. Operand 0 is the
4338 output; it has mode @var{m}. The second and third operand are the blocks of
4339 memory to be compared; both are @code{mem:BLK} with an address in mode
4342 The fourth operand is the known shared alignment of the source and
4343 destination, in the form of a @code{const_int} rtx. Thus, if the
4344 compiler knows that both source and destination are word-aligned,
4345 it may provide the value 4 for this operand.
4347 The two memory blocks specified are compared byte by byte in lexicographic
4348 order starting at the beginning of each string. The instruction is not allowed
4349 to prefetch more than one byte at a time since either string may end in the
4350 first byte and reading past that may access an invalid page or segment and
4351 cause a fault. The effect of the instruction is to store a value in operand 0
4352 whose sign indicates the result of the comparison.
4354 @cindex @code{cmpmem@var{m}} instruction pattern
4355 @item @samp{cmpmem@var{m}}
4356 Block compare instruction, with five operands like the operands
4357 of @samp{cmpstr@var{m}}. The two memory blocks specified are compared
4358 byte by byte in lexicographic order starting at the beginning of each
4359 block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch
4360 any bytes in the two memory blocks. The effect of the instruction is
4361 to store a value in operand 0 whose sign indicates the result of the
4364 @cindex @code{strlen@var{m}} instruction pattern
4365 @item @samp{strlen@var{m}}
4366 Compute the length of a string, with three operands.
4367 Operand 0 is the result (of mode @var{m}), operand 1 is
4368 a @code{mem} referring to the first character of the string,
4369 operand 2 is the character to search for (normally zero),
4370 and operand 3 is a constant describing the known alignment
4371 of the beginning of the string.
4373 @cindex @code{float@var{mn}2} instruction pattern
4374 @item @samp{float@var{m}@var{n}2}
4375 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
4376 floating point mode @var{n} and store in operand 0 (which has mode
4379 @cindex @code{floatuns@var{mn}2} instruction pattern
4380 @item @samp{floatuns@var{m}@var{n}2}
4381 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
4382 to floating point mode @var{n} and store in operand 0 (which has mode
4385 @cindex @code{fix@var{mn}2} instruction pattern
4386 @item @samp{fix@var{m}@var{n}2}
4387 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4388 point mode @var{n} as a signed number and store in operand 0 (which
4389 has mode @var{n}). This instruction's result is defined only when
4390 the value of operand 1 is an integer.
4392 If the machine description defines this pattern, it also needs to
4393 define the @code{ftrunc} pattern.
4395 @cindex @code{fixuns@var{mn}2} instruction pattern
4396 @item @samp{fixuns@var{m}@var{n}2}
4397 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4398 point mode @var{n} as an unsigned number and store in operand 0 (which
4399 has mode @var{n}). This instruction's result is defined only when the
4400 value of operand 1 is an integer.
4402 @cindex @code{ftrunc@var{m}2} instruction pattern
4403 @item @samp{ftrunc@var{m}2}
4404 Convert operand 1 (valid for floating point mode @var{m}) to an
4405 integer value, still represented in floating point mode @var{m}, and
4406 store it in operand 0 (valid for floating point mode @var{m}).
4408 @cindex @code{fix_trunc@var{mn}2} instruction pattern
4409 @item @samp{fix_trunc@var{m}@var{n}2}
4410 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
4411 of mode @var{m} by converting the value to an integer.
4413 @cindex @code{fixuns_trunc@var{mn}2} instruction pattern
4414 @item @samp{fixuns_trunc@var{m}@var{n}2}
4415 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
4416 value of mode @var{m} by converting the value to an integer.
4418 @cindex @code{trunc@var{mn}2} instruction pattern
4419 @item @samp{trunc@var{m}@var{n}2}
4420 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
4421 store in operand 0 (which has mode @var{n}). Both modes must be fixed
4422 point or both floating point.
4424 @cindex @code{extend@var{mn}2} instruction pattern
4425 @item @samp{extend@var{m}@var{n}2}
4426 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
4427 store in operand 0 (which has mode @var{n}). Both modes must be fixed
4428 point or both floating point.
4430 @cindex @code{zero_extend@var{mn}2} instruction pattern
4431 @item @samp{zero_extend@var{m}@var{n}2}
4432 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
4433 store in operand 0 (which has mode @var{n}). Both modes must be fixed
4436 @cindex @code{fract@var{mn}2} instruction pattern
4437 @item @samp{fract@var{m}@var{n}2}
4438 Convert operand 1 of mode @var{m} to mode @var{n} and store in
4439 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
4440 could be fixed-point to fixed-point, signed integer to fixed-point,
4441 fixed-point to signed integer, floating-point to fixed-point,
4442 or fixed-point to floating-point.
4443 When overflows or underflows happen, the results are undefined.
4445 @cindex @code{satfract@var{mn}2} instruction pattern
4446 @item @samp{satfract@var{m}@var{n}2}
4447 Convert operand 1 of mode @var{m} to mode @var{n} and store in
4448 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
4449 could be fixed-point to fixed-point, signed integer to fixed-point,
4450 or floating-point to fixed-point.
4451 When overflows or underflows happen, the instruction saturates the
4452 results to the maximum or the minimum.
4454 @cindex @code{fractuns@var{mn}2} instruction pattern
4455 @item @samp{fractuns@var{m}@var{n}2}
4456 Convert operand 1 of mode @var{m} to mode @var{n} and store in
4457 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
4458 could be unsigned integer to fixed-point, or
4459 fixed-point to unsigned integer.
4460 When overflows or underflows happen, the results are undefined.
4462 @cindex @code{satfractuns@var{mn}2} instruction pattern
4463 @item @samp{satfractuns@var{m}@var{n}2}
4464 Convert unsigned integer operand 1 of mode @var{m} to fixed-point mode
4465 @var{n} and store in operand 0 (which has mode @var{n}).
4466 When overflows or underflows happen, the instruction saturates the
4467 results to the maximum or the minimum.
4469 @cindex @code{extv} instruction pattern
4471 Extract a bit-field from operand 1 (a register or memory operand), where
4472 operand 2 specifies the width in bits and operand 3 the starting bit,
4473 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
4474 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
4475 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
4476 be valid for @code{word_mode}.
4478 The RTL generation pass generates this instruction only with constants
4479 for operands 2 and 3 and the constant is never zero for operand 2.
4481 The bit-field value is sign-extended to a full word integer
4482 before it is stored in operand 0.
4484 @cindex @code{extzv} instruction pattern
4486 Like @samp{extv} except that the bit-field value is zero-extended.
4488 @cindex @code{insv} instruction pattern
4490 Store operand 3 (which must be valid for @code{word_mode}) into a
4491 bit-field in operand 0, where operand 1 specifies the width in bits and
4492 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
4493 @code{word_mode}; often @code{word_mode} is allowed only for registers.
4494 Operands 1 and 2 must be valid for @code{word_mode}.
4496 The RTL generation pass generates this instruction only with constants
4497 for operands 1 and 2 and the constant is never zero for operand 1.
4499 @cindex @code{mov@var{mode}cc} instruction pattern
4500 @item @samp{mov@var{mode}cc}
4501 Conditionally move operand 2 or operand 3 into operand 0 according to the
4502 comparison in operand 1. If the comparison is true, operand 2 is moved
4503 into operand 0, otherwise operand 3 is moved.
4505 The mode of the operands being compared need not be the same as the operands
4506 being moved. Some machines, sparc64 for example, have instructions that
4507 conditionally move an integer value based on the floating point condition
4508 codes and vice versa.
4510 If the machine does not have conditional move instructions, do not
4511 define these patterns.
4513 @cindex @code{add@var{mode}cc} instruction pattern
4514 @item @samp{add@var{mode}cc}
4515 Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally
4516 move operand 2 or (operands 2 + operand 3) into operand 0 according to the
4517 comparison in operand 1. If the comparison is true, operand 2 is moved into
4518 operand 0, otherwise (operand 2 + operand 3) is moved.
4520 @cindex @code{cstore@var{mode}4} instruction pattern
4521 @item @samp{cstore@var{mode}4}
4522 Store zero or nonzero in operand 0 according to whether a comparison
4523 is true. Operand 1 is a comparison operator. Operand 2 and operand 3
4524 are the first and second operand of the comparison, respectively.
4525 You specify the mode that operand 0 must have when you write the
4526 @code{match_operand} expression. The compiler automatically sees which
4527 mode you have used and supplies an operand of that mode.
4529 The value stored for a true condition must have 1 as its low bit, or
4530 else must be negative. Otherwise the instruction is not suitable and
4531 you should omit it from the machine description. You describe to the
4532 compiler exactly which value is stored by defining the macro
4533 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
4534 found that can be used for all the @samp{s@var{cond}} patterns, you
4535 should omit those operations from the machine description.
4537 These operations may fail, but should do so only in relatively
4538 uncommon cases; if they would fail for common cases involving
4539 integer comparisons, it is best to omit these patterns.
4541 If these operations are omitted, the compiler will usually generate code
4542 that copies the constant one to the target and branches around an
4543 assignment of zero to the target. If this code is more efficient than
4544 the potential instructions used for the @samp{cstore@var{mode}4} pattern
4545 followed by those required to convert the result into a 1 or a zero in
4546 @code{SImode}, you should omit the @samp{cstore@var{mode}4} operations from
4547 the machine description.
4549 @cindex @code{cbranch@var{mode}4} instruction pattern
4550 @item @samp{cbranch@var{mode}4}
4551 Conditional branch instruction combined with a compare instruction.
4552 Operand 0 is a comparison operator. Operand 1 and operand 2 are the
4553 first and second operands of the comparison, respectively. Operand 3
4554 is a @code{label_ref} that refers to the label to jump to.
4556 @cindex @code{jump} instruction pattern
4558 A jump inside a function; an unconditional branch. Operand 0 is the
4559 @code{label_ref} of the label to jump to. This pattern name is mandatory
4562 @cindex @code{call} instruction pattern
4564 Subroutine call instruction returning no value. Operand 0 is the
4565 function to call; operand 1 is the number of bytes of arguments pushed
4566 as a @code{const_int}; operand 2 is the number of registers used as
4569 On most machines, operand 2 is not actually stored into the RTL
4570 pattern. It is supplied for the sake of some RISC machines which need
4571 to put this information into the assembler code; they can put it in
4572 the RTL instead of operand 1.
4574 Operand 0 should be a @code{mem} RTX whose address is the address of the
4575 function. Note, however, that this address can be a @code{symbol_ref}
4576 expression even if it would not be a legitimate memory address on the
4577 target machine. If it is also not a valid argument for a call
4578 instruction, the pattern for this operation should be a
4579 @code{define_expand} (@pxref{Expander Definitions}) that places the
4580 address into a register and uses that register in the call instruction.
4582 @cindex @code{call_value} instruction pattern
4583 @item @samp{call_value}
4584 Subroutine call instruction returning a value. Operand 0 is the hard
4585 register in which the value is returned. There are three more
4586 operands, the same as the three operands of the @samp{call}
4587 instruction (but with numbers increased by one).
4589 Subroutines that return @code{BLKmode} objects use the @samp{call}
4592 @cindex @code{call_pop} instruction pattern
4593 @cindex @code{call_value_pop} instruction pattern
4594 @item @samp{call_pop}, @samp{call_value_pop}
4595 Similar to @samp{call} and @samp{call_value}, except used if defined and
4596 if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel}
4597 that contains both the function call and a @code{set} to indicate the
4598 adjustment made to the frame pointer.
4600 For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these
4601 patterns increases the number of functions for which the frame pointer
4602 can be eliminated, if desired.
4604 @cindex @code{untyped_call} instruction pattern
4605 @item @samp{untyped_call}
4606 Subroutine call instruction returning a value of any type. Operand 0 is
4607 the function to call; operand 1 is a memory location where the result of
4608 calling the function is to be stored; operand 2 is a @code{parallel}
4609 expression where each element is a @code{set} expression that indicates
4610 the saving of a function return value into the result block.
4612 This instruction pattern should be defined to support
4613 @code{__builtin_apply} on machines where special instructions are needed
4614 to call a subroutine with arbitrary arguments or to save the value
4615 returned. This instruction pattern is required on machines that have
4616 multiple registers that can hold a return value
4617 (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
4619 @cindex @code{return} instruction pattern
4621 Subroutine return instruction. This instruction pattern name should be
4622 defined only if a single instruction can do all the work of returning
4625 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
4626 RTL generation phase. In this case it is to support machines where
4627 multiple instructions are usually needed to return from a function, but
4628 some class of functions only requires one instruction to implement a
4629 return. Normally, the applicable functions are those which do not need
4630 to save any registers or allocate stack space.
4632 @findex reload_completed
4633 @findex leaf_function_p
4634 For such machines, the condition specified in this pattern should only
4635 be true when @code{reload_completed} is nonzero and the function's
4636 epilogue would only be a single instruction. For machines with register
4637 windows, the routine @code{leaf_function_p} may be used to determine if
4638 a register window push is required.
4640 Machines that have conditional return instructions should define patterns
4646 (if_then_else (match_operator
4647 0 "comparison_operator"
4648 [(cc0) (const_int 0)])
4655 where @var{condition} would normally be the same condition specified on the
4656 named @samp{return} pattern.
4658 @cindex @code{untyped_return} instruction pattern
4659 @item @samp{untyped_return}
4660 Untyped subroutine return instruction. This instruction pattern should
4661 be defined to support @code{__builtin_return} on machines where special
4662 instructions are needed to return a value of any type.
4664 Operand 0 is a memory location where the result of calling a function
4665 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
4666 expression where each element is a @code{set} expression that indicates
4667 the restoring of a function return value from the result block.
4669 @cindex @code{nop} instruction pattern
4671 No-op instruction. This instruction pattern name should always be defined
4672 to output a no-op in assembler code. @code{(const_int 0)} will do as an
4675 @cindex @code{indirect_jump} instruction pattern
4676 @item @samp{indirect_jump}
4677 An instruction to jump to an address which is operand zero.
4678 This pattern name is mandatory on all machines.
4680 @cindex @code{casesi} instruction pattern
4682 Instruction to jump through a dispatch table, including bounds checking.
4683 This instruction takes five operands:
4687 The index to dispatch on, which has mode @code{SImode}.
4690 The lower bound for indices in the table, an integer constant.
4693 The total range of indices in the table---the largest index
4694 minus the smallest one (both inclusive).
4697 A label that precedes the table itself.
4700 A label to jump to if the index has a value outside the bounds.
4703 The table is an @code{addr_vec} or @code{addr_diff_vec} inside of a
4704 @code{jump_insn}. The number of elements in the table is one plus the
4705 difference between the upper bound and the lower bound.
4707 @cindex @code{tablejump} instruction pattern
4708 @item @samp{tablejump}
4709 Instruction to jump to a variable address. This is a low-level
4710 capability which can be used to implement a dispatch table when there
4711 is no @samp{casesi} pattern.
4713 This pattern requires two operands: the address or offset, and a label
4714 which should immediately precede the jump table. If the macro
4715 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
4716 operand is an offset which counts from the address of the table; otherwise,
4717 it is an absolute address to jump to. In either case, the first operand has
4720 The @samp{tablejump} insn is always the last insn before the jump
4721 table it uses. Its assembler code normally has no need to use the
4722 second operand, but you should incorporate it in the RTL pattern so
4723 that the jump optimizer will not delete the table as unreachable code.
4726 @cindex @code{decrement_and_branch_until_zero} instruction pattern
4727 @item @samp{decrement_and_branch_until_zero}
4728 Conditional branch instruction that decrements a register and
4729 jumps if the register is nonzero. Operand 0 is the register to
4730 decrement and test; operand 1 is the label to jump to if the
4731 register is nonzero. @xref{Looping Patterns}.
4733 This optional instruction pattern is only used by the combiner,
4734 typically for loops reversed by the loop optimizer when strength
4735 reduction is enabled.
4737 @cindex @code{doloop_end} instruction pattern
4738 @item @samp{doloop_end}
4739 Conditional branch instruction that decrements a register and jumps if
4740 the register is nonzero. This instruction takes five operands: Operand
4741 0 is the register to decrement and test; operand 1 is the number of loop
4742 iterations as a @code{const_int} or @code{const0_rtx} if this cannot be
4743 determined until run-time; operand 2 is the actual or estimated maximum
4744 number of iterations as a @code{const_int}; operand 3 is the number of
4745 enclosed loops as a @code{const_int} (an innermost loop has a value of
4746 1); operand 4 is the label to jump to if the register is nonzero.
4747 @xref{Looping Patterns}.
4749 This optional instruction pattern should be defined for machines with
4750 low-overhead looping instructions as the loop optimizer will try to
4751 modify suitable loops to utilize it. If nested low-overhead looping is
4752 not supported, use a @code{define_expand} (@pxref{Expander Definitions})
4753 and make the pattern fail if operand 3 is not @code{const1_rtx}.
4754 Similarly, if the actual or estimated maximum number of iterations is
4755 too large for this instruction, make it fail.
4757 @cindex @code{doloop_begin} instruction pattern
4758 @item @samp{doloop_begin}
4759 Companion instruction to @code{doloop_end} required for machines that
4760 need to perform some initialization, such as loading special registers
4761 used by a low-overhead looping instruction. If initialization insns do
4762 not always need to be emitted, use a @code{define_expand}
4763 (@pxref{Expander Definitions}) and make it fail.
4766 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
4767 @item @samp{canonicalize_funcptr_for_compare}
4768 Canonicalize the function pointer in operand 1 and store the result
4771 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
4772 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
4773 and also has mode @code{Pmode}.
4775 Canonicalization of a function pointer usually involves computing
4776 the address of the function which would be called if the function
4777 pointer were used in an indirect call.
4779 Only define this pattern if function pointers on the target machine
4780 can have different values but still call the same function when
4781 used in an indirect call.
4783 @cindex @code{save_stack_block} instruction pattern
4784 @cindex @code{save_stack_function} instruction pattern
4785 @cindex @code{save_stack_nonlocal} instruction pattern
4786 @cindex @code{restore_stack_block} instruction pattern
4787 @cindex @code{restore_stack_function} instruction pattern
4788 @cindex @code{restore_stack_nonlocal} instruction pattern
4789 @item @samp{save_stack_block}
4790 @itemx @samp{save_stack_function}
4791 @itemx @samp{save_stack_nonlocal}
4792 @itemx @samp{restore_stack_block}
4793 @itemx @samp{restore_stack_function}
4794 @itemx @samp{restore_stack_nonlocal}
4795 Most machines save and restore the stack pointer by copying it to or
4796 from an object of mode @code{Pmode}. Do not define these patterns on
4799 Some machines require special handling for stack pointer saves and
4800 restores. On those machines, define the patterns corresponding to the
4801 non-standard cases by using a @code{define_expand} (@pxref{Expander
4802 Definitions}) that produces the required insns. The three types of
4803 saves and restores are:
4807 @samp{save_stack_block} saves the stack pointer at the start of a block
4808 that allocates a variable-sized object, and @samp{restore_stack_block}
4809 restores the stack pointer when the block is exited.
4812 @samp{save_stack_function} and @samp{restore_stack_function} do a
4813 similar job for the outermost block of a function and are used when the
4814 function allocates variable-sized objects or calls @code{alloca}. Only
4815 the epilogue uses the restored stack pointer, allowing a simpler save or
4816 restore sequence on some machines.
4819 @samp{save_stack_nonlocal} is used in functions that contain labels
4820 branched to by nested functions. It saves the stack pointer in such a
4821 way that the inner function can use @samp{restore_stack_nonlocal} to
4822 restore the stack pointer. The compiler generates code to restore the
4823 frame and argument pointer registers, but some machines require saving
4824 and restoring additional data such as register window information or
4825 stack backchains. Place insns in these patterns to save and restore any
4829 When saving the stack pointer, operand 0 is the save area and operand 1
4830 is the stack pointer. The mode used to allocate the save area defaults
4831 to @code{Pmode} but you can override that choice by defining the
4832 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
4833 specify an integral mode, or @code{VOIDmode} if no save area is needed
4834 for a particular type of save (either because no save is needed or
4835 because a machine-specific save area can be used). Operand 0 is the
4836 stack pointer and operand 1 is the save area for restore operations. If
4837 @samp{save_stack_block} is defined, operand 0 must not be
4838 @code{VOIDmode} since these saves can be arbitrarily nested.
4840 A save area is a @code{mem} that is at a constant offset from
4841 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
4842 nonlocal gotos and a @code{reg} in the other two cases.
4844 @cindex @code{allocate_stack} instruction pattern
4845 @item @samp{allocate_stack}
4846 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
4847 the stack pointer to create space for dynamically allocated data.
4849 Store the resultant pointer to this space into operand 0. If you
4850 are allocating space from the main stack, do this by emitting a
4851 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
4852 If you are allocating the space elsewhere, generate code to copy the
4853 location of the space to operand 0. In the latter case, you must
4854 ensure this space gets freed when the corresponding space on the main
4857 Do not define this pattern if all that must be done is the subtraction.
4858 Some machines require other operations such as stack probes or
4859 maintaining the back chain. Define this pattern to emit those
4860 operations in addition to updating the stack pointer.
4862 @cindex @code{check_stack} instruction pattern
4863 @item @samp{check_stack}
4864 If stack checking cannot be done on your system by probing the stack with
4865 a load or store instruction (@pxref{Stack Checking}), define this pattern
4866 to perform the needed check and signaling an error if the stack
4867 has overflowed. The single operand is the location in the stack furthest
4868 from the current stack pointer that you need to validate. Normally,
4869 on machines where this pattern is needed, you would obtain the stack
4870 limit from a global or thread-specific variable or register.
4872 @cindex @code{nonlocal_goto} instruction pattern
4873 @item @samp{nonlocal_goto}
4874 Emit code to generate a non-local goto, e.g., a jump from one function
4875 to a label in an outer function. This pattern has four arguments,
4876 each representing a value to be used in the jump. The first
4877 argument is to be loaded into the frame pointer, the second is
4878 the address to branch to (code to dispatch to the actual label),
4879 the third is the address of a location where the stack is saved,
4880 and the last is the address of the label, to be placed in the
4881 location for the incoming static chain.
4883 On most machines you need not define this pattern, since GCC will
4884 already generate the correct code, which is to load the frame pointer
4885 and static chain, restore the stack (using the
4886 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
4887 to the dispatcher. You need only define this pattern if this code will
4888 not work on your machine.
4890 @cindex @code{nonlocal_goto_receiver} instruction pattern
4891 @item @samp{nonlocal_goto_receiver}
4892 This pattern, if defined, contains code needed at the target of a
4893 nonlocal goto after the code already generated by GCC@. You will not
4894 normally need to define this pattern. A typical reason why you might
4895 need this pattern is if some value, such as a pointer to a global table,
4896 must be restored when the frame pointer is restored. Note that a nonlocal
4897 goto only occurs within a unit-of-translation, so a global table pointer
4898 that is shared by all functions of a given module need not be restored.
4899 There are no arguments.
4901 @cindex @code{exception_receiver} instruction pattern
4902 @item @samp{exception_receiver}
4903 This pattern, if defined, contains code needed at the site of an
4904 exception handler that isn't needed at the site of a nonlocal goto. You
4905 will not normally need to define this pattern. A typical reason why you
4906 might need this pattern is if some value, such as a pointer to a global
4907 table, must be restored after control flow is branched to the handler of
4908 an exception. There are no arguments.
4910 @cindex @code{builtin_setjmp_setup} instruction pattern
4911 @item @samp{builtin_setjmp_setup}
4912 This pattern, if defined, contains additional code needed to initialize
4913 the @code{jmp_buf}. You will not normally need to define this pattern.
4914 A typical reason why you might need this pattern is if some value, such
4915 as a pointer to a global table, must be restored. Though it is
4916 preferred that the pointer value be recalculated if possible (given the
4917 address of a label for instance). The single argument is a pointer to
4918 the @code{jmp_buf}. Note that the buffer is five words long and that
4919 the first three are normally used by the generic mechanism.
4921 @cindex @code{builtin_setjmp_receiver} instruction pattern
4922 @item @samp{builtin_setjmp_receiver}
4923 This pattern, if defined, contains code needed at the site of a
4924 built-in setjmp that isn't needed at the site of a nonlocal goto. You
4925 will not normally need to define this pattern. A typical reason why you
4926 might need this pattern is if some value, such as a pointer to a global
4927 table, must be restored. It takes one argument, which is the label
4928 to which builtin_longjmp transfered control; this pattern may be emitted
4929 at a small offset from that label.
4931 @cindex @code{builtin_longjmp} instruction pattern
4932 @item @samp{builtin_longjmp}
4933 This pattern, if defined, performs the entire action of the longjmp.
4934 You will not normally need to define this pattern unless you also define
4935 @code{builtin_setjmp_setup}. The single argument is a pointer to the
4938 @cindex @code{eh_return} instruction pattern
4939 @item @samp{eh_return}
4940 This pattern, if defined, affects the way @code{__builtin_eh_return},
4941 and thence the call frame exception handling library routines, are
4942 built. It is intended to handle non-trivial actions needed along
4943 the abnormal return path.
4945 The address of the exception handler to which the function should return
4946 is passed as operand to this pattern. It will normally need to copied by
4947 the pattern to some special register or memory location.
4948 If the pattern needs to determine the location of the target call
4949 frame in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX},
4950 if defined; it will have already been assigned.
4952 If this pattern is not defined, the default action will be to simply
4953 copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either
4954 that macro or this pattern needs to be defined if call frame exception
4955 handling is to be used.
4957 @cindex @code{prologue} instruction pattern
4958 @anchor{prologue instruction pattern}
4959 @item @samp{prologue}
4960 This pattern, if defined, emits RTL for entry to a function. The function
4961 entry is responsible for setting up the stack frame, initializing the frame
4962 pointer register, saving callee saved registers, etc.
4964 Using a prologue pattern is generally preferred over defining
4965 @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue.
4967 The @code{prologue} pattern is particularly useful for targets which perform
4968 instruction scheduling.
4970 @cindex @code{epilogue} instruction pattern
4971 @anchor{epilogue instruction pattern}
4972 @item @samp{epilogue}
4973 This pattern emits RTL for exit from a function. The function
4974 exit is responsible for deallocating the stack frame, restoring callee saved
4975 registers and emitting the return instruction.
4977 Using an epilogue pattern is generally preferred over defining
4978 @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue.
4980 The @code{epilogue} pattern is particularly useful for targets which perform
4981 instruction scheduling or which have delay slots for their return instruction.
4983 @cindex @code{sibcall_epilogue} instruction pattern
4984 @item @samp{sibcall_epilogue}
4985 This pattern, if defined, emits RTL for exit from a function without the final
4986 branch back to the calling function. This pattern will be emitted before any
4987 sibling call (aka tail call) sites.
4989 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
4990 parameter passing or any stack slots for arguments passed to the current
4993 @cindex @code{trap} instruction pattern
4995 This pattern, if defined, signals an error, typically by causing some
4996 kind of signal to be raised. Among other places, it is used by the Java
4997 front end to signal `invalid array index' exceptions.
4999 @cindex @code{ctrap@var{MM}4} instruction pattern
5000 @item @samp{ctrap@var{MM}4}
5001 Conditional trap instruction. Operand 0 is a piece of RTL which
5002 performs a comparison, and operands 1 and 2 are the arms of the
5003 comparison. Operand 3 is the trap code, an integer.
5005 A typical @code{ctrap} pattern looks like
5008 (define_insn "ctrapsi4"
5009 [(trap_if (match_operator 0 "trap_operator"
5010 [(match_operand 1 "register_operand")
5011 (match_operand 2 "immediate_operand")])
5012 (match_operand 3 "const_int_operand" "i"))]
5017 @cindex @code{prefetch} instruction pattern
5018 @item @samp{prefetch}
5020 This pattern, if defined, emits code for a non-faulting data prefetch
5021 instruction. Operand 0 is the address of the memory to prefetch. Operand 1
5022 is a constant 1 if the prefetch is preparing for a write to the memory
5023 address, or a constant 0 otherwise. Operand 2 is the expected degree of
5024 temporal locality of the data and is a value between 0 and 3, inclusive; 0
5025 means that the data has no temporal locality, so it need not be left in the
5026 cache after the access; 3 means that the data has a high degree of temporal
5027 locality and should be left in all levels of cache possible; 1 and 2 mean,
5028 respectively, a low or moderate degree of temporal locality.
5030 Targets that do not support write prefetches or locality hints can ignore
5031 the values of operands 1 and 2.
5033 @cindex @code{blockage} instruction pattern
5034 @item @samp{blockage}
5036 This pattern defines a pseudo insn that prevents the instruction
5037 scheduler from moving instructions across the boundary defined by the
5038 blockage insn. Normally an UNSPEC_VOLATILE pattern.
5040 @cindex @code{memory_barrier} instruction pattern
5041 @item @samp{memory_barrier}
5043 If the target memory model is not fully synchronous, then this pattern
5044 should be defined to an instruction that orders both loads and stores
5045 before the instruction with respect to loads and stores after the instruction.
5046 This pattern has no operands.
5048 @cindex @code{sync_compare_and_swap@var{mode}} instruction pattern
5049 @item @samp{sync_compare_and_swap@var{mode}}
5051 This pattern, if defined, emits code for an atomic compare-and-swap
5052 operation. Operand 1 is the memory on which the atomic operation is
5053 performed. Operand 2 is the ``old'' value to be compared against the
5054 current contents of the memory location. Operand 3 is the ``new'' value
5055 to store in the memory if the compare succeeds. Operand 0 is the result
5056 of the operation; it should contain the contents of the memory
5057 before the operation. If the compare succeeds, this should obviously be
5058 a copy of operand 2.
5060 This pattern must show that both operand 0 and operand 1 are modified.
5062 This pattern must issue any memory barrier instructions such that all
5063 memory operations before the atomic operation occur before the atomic
5064 operation and all memory operations after the atomic operation occur
5065 after the atomic operation.
5067 For targets where the success or failure of the compare-and-swap
5068 operation is available via the status flags, it is possible to
5069 avoid a separate compare operation and issue the subsequent
5070 branch or store-flag operation immediately after the compare-and-swap.
5071 To this end, GCC will look for a @code{MODE_CC} set in the
5072 output of @code{sync_compare_and_swap@var{mode}}; if the machine
5073 description includes such a set, the target should also define special
5074 @code{cbranchcc4} and/or @code{cstorecc4} instructions. GCC will then
5075 be able to take the destination of the @code{MODE_CC} set and pass it
5076 to the @code{cbranchcc4} or @code{cstorecc4} pattern as the first
5077 operand of the comparison (the second will be @code{(const_int 0)}).
5079 @cindex @code{sync_add@var{mode}} instruction pattern
5080 @cindex @code{sync_sub@var{mode}} instruction pattern
5081 @cindex @code{sync_ior@var{mode}} instruction pattern
5082 @cindex @code{sync_and@var{mode}} instruction pattern
5083 @cindex @code{sync_xor@var{mode}} instruction pattern
5084 @cindex @code{sync_nand@var{mode}} instruction pattern
5085 @item @samp{sync_add@var{mode}}, @samp{sync_sub@var{mode}}
5086 @itemx @samp{sync_ior@var{mode}}, @samp{sync_and@var{mode}}
5087 @itemx @samp{sync_xor@var{mode}}, @samp{sync_nand@var{mode}}
5089 These patterns emit code for an atomic operation on memory.
5090 Operand 0 is the memory on which the atomic operation is performed.
5091 Operand 1 is the second operand to the binary operator.
5093 This pattern must issue any memory barrier instructions such that all
5094 memory operations before the atomic operation occur before the atomic
5095 operation and all memory operations after the atomic operation occur
5096 after the atomic operation.
5098 If these patterns are not defined, the operation will be constructed
5099 from a compare-and-swap operation, if defined.
5101 @cindex @code{sync_old_add@var{mode}} instruction pattern
5102 @cindex @code{sync_old_sub@var{mode}} instruction pattern
5103 @cindex @code{sync_old_ior@var{mode}} instruction pattern
5104 @cindex @code{sync_old_and@var{mode}} instruction pattern
5105 @cindex @code{sync_old_xor@var{mode}} instruction pattern
5106 @cindex @code{sync_old_nand@var{mode}} instruction pattern
5107 @item @samp{sync_old_add@var{mode}}, @samp{sync_old_sub@var{mode}}
5108 @itemx @samp{sync_old_ior@var{mode}}, @samp{sync_old_and@var{mode}}
5109 @itemx @samp{sync_old_xor@var{mode}}, @samp{sync_old_nand@var{mode}}
5111 These patterns are emit code for an atomic operation on memory,
5112 and return the value that the memory contained before the operation.
5113 Operand 0 is the result value, operand 1 is the memory on which the
5114 atomic operation is performed, and operand 2 is the second operand
5115 to the binary operator.
5117 This pattern must issue any memory barrier instructions such that all
5118 memory operations before the atomic operation occur before the atomic
5119 operation and all memory operations after the atomic operation occur
5120 after the atomic operation.
5122 If these patterns are not defined, the operation will be constructed
5123 from a compare-and-swap operation, if defined.
5125 @cindex @code{sync_new_add@var{mode}} instruction pattern
5126 @cindex @code{sync_new_sub@var{mode}} instruction pattern
5127 @cindex @code{sync_new_ior@var{mode}} instruction pattern
5128 @cindex @code{sync_new_and@var{mode}} instruction pattern
5129 @cindex @code{sync_new_xor@var{mode}} instruction pattern
5130 @cindex @code{sync_new_nand@var{mode}} instruction pattern
5131 @item @samp{sync_new_add@var{mode}}, @samp{sync_new_sub@var{mode}}
5132 @itemx @samp{sync_new_ior@var{mode}}, @samp{sync_new_and@var{mode}}
5133 @itemx @samp{sync_new_xor@var{mode}}, @samp{sync_new_nand@var{mode}}
5135 These patterns are like their @code{sync_old_@var{op}} counterparts,
5136 except that they return the value that exists in the memory location
5137 after the operation, rather than before the operation.
5139 @cindex @code{sync_lock_test_and_set@var{mode}} instruction pattern
5140 @item @samp{sync_lock_test_and_set@var{mode}}
5142 This pattern takes two forms, based on the capabilities of the target.
5143 In either case, operand 0 is the result of the operand, operand 1 is
5144 the memory on which the atomic operation is performed, and operand 2
5145 is the value to set in the lock.
5147 In the ideal case, this operation is an atomic exchange operation, in
5148 which the previous value in memory operand is copied into the result
5149 operand, and the value operand is stored in the memory operand.
5151 For less capable targets, any value operand that is not the constant 1
5152 should be rejected with @code{FAIL}. In this case the target may use
5153 an atomic test-and-set bit operation. The result operand should contain
5154 1 if the bit was previously set and 0 if the bit was previously clear.
5155 The true contents of the memory operand are implementation defined.
5157 This pattern must issue any memory barrier instructions such that the
5158 pattern as a whole acts as an acquire barrier, that is all memory
5159 operations after the pattern do not occur until the lock is acquired.
5161 If this pattern is not defined, the operation will be constructed from
5162 a compare-and-swap operation, if defined.
5164 @cindex @code{sync_lock_release@var{mode}} instruction pattern
5165 @item @samp{sync_lock_release@var{mode}}
5167 This pattern, if defined, releases a lock set by
5168 @code{sync_lock_test_and_set@var{mode}}. Operand 0 is the memory
5169 that contains the lock; operand 1 is the value to store in the lock.
5171 If the target doesn't implement full semantics for
5172 @code{sync_lock_test_and_set@var{mode}}, any value operand which is not
5173 the constant 0 should be rejected with @code{FAIL}, and the true contents
5174 of the memory operand are implementation defined.
5176 This pattern must issue any memory barrier instructions such that the
5177 pattern as a whole acts as a release barrier, that is the lock is
5178 released only after all previous memory operations have completed.
5180 If this pattern is not defined, then a @code{memory_barrier} pattern
5181 will be emitted, followed by a store of the value to the memory operand.
5183 @cindex @code{stack_protect_set} instruction pattern
5184 @item @samp{stack_protect_set}
5186 This pattern, if defined, moves a @code{Pmode} value from the memory
5187 in operand 1 to the memory in operand 0 without leaving the value in
5188 a register afterward. This is to avoid leaking the value some place
5189 that an attacker might use to rewrite the stack guard slot after
5190 having clobbered it.
5192 If this pattern is not defined, then a plain move pattern is generated.
5194 @cindex @code{stack_protect_test} instruction pattern
5195 @item @samp{stack_protect_test}
5197 This pattern, if defined, compares a @code{Pmode} value from the
5198 memory in operand 1 with the memory in operand 0 without leaving the
5199 value in a register afterward and branches to operand 2 if the values
5202 If this pattern is not defined, then a plain compare pattern and
5203 conditional branch pattern is used.
5205 @cindex @code{clear_cache} instruction pattern
5206 @item @samp{clear_cache}
5208 This pattern, if defined, flushes the instruction cache for a region of
5209 memory. The region is bounded to by the Pmode pointers in operand 0
5210 inclusive and operand 1 exclusive.
5212 If this pattern is not defined, a call to the library function
5213 @code{__clear_cache} is used.
5218 @c Each of the following nodes are wrapped in separate
5219 @c "@ifset INTERNALS" to work around memory limits for the default
5220 @c configuration in older tetex distributions. Known to not work:
5221 @c tetex-1.0.7, known to work: tetex-2.0.2.
5223 @node Pattern Ordering
5224 @section When the Order of Patterns Matters
5225 @cindex Pattern Ordering
5226 @cindex Ordering of Patterns
5228 Sometimes an insn can match more than one instruction pattern. Then the
5229 pattern that appears first in the machine description is the one used.
5230 Therefore, more specific patterns (patterns that will match fewer things)
5231 and faster instructions (those that will produce better code when they
5232 do match) should usually go first in the description.
5234 In some cases the effect of ordering the patterns can be used to hide
5235 a pattern when it is not valid. For example, the 68000 has an
5236 instruction for converting a fullword to floating point and another
5237 for converting a byte to floating point. An instruction converting
5238 an integer to floating point could match either one. We put the
5239 pattern to convert the fullword first to make sure that one will
5240 be used rather than the other. (Otherwise a large integer might
5241 be generated as a single-byte immediate quantity, which would not work.)
5242 Instead of using this pattern ordering it would be possible to make the
5243 pattern for convert-a-byte smart enough to deal properly with any
5248 @node Dependent Patterns
5249 @section Interdependence of Patterns
5250 @cindex Dependent Patterns
5251 @cindex Interdependence of Patterns
5253 In some cases machines support instructions identical except for the
5254 machine mode of one or more operands. For example, there may be
5255 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
5259 (set (match_operand:SI 0 @dots{})
5260 (extend:SI (match_operand:HI 1 @dots{})))
5262 (set (match_operand:SI 0 @dots{})
5263 (extend:SI (match_operand:QI 1 @dots{})))
5267 Constant integers do not specify a machine mode, so an instruction to
5268 extend a constant value could match either pattern. The pattern it
5269 actually will match is the one that appears first in the file. For correct
5270 results, this must be the one for the widest possible mode (@code{HImode},
5271 here). If the pattern matches the @code{QImode} instruction, the results
5272 will be incorrect if the constant value does not actually fit that mode.
5274 Such instructions to extend constants are rarely generated because they are
5275 optimized away, but they do occasionally happen in nonoptimized
5278 If a constraint in a pattern allows a constant, the reload pass may
5279 replace a register with a constant permitted by the constraint in some
5280 cases. Similarly for memory references. Because of this substitution,
5281 you should not provide separate patterns for increment and decrement
5282 instructions. Instead, they should be generated from the same pattern
5283 that supports register-register add insns by examining the operands and
5284 generating the appropriate machine instruction.
5289 @section Defining Jump Instruction Patterns
5290 @cindex jump instruction patterns
5291 @cindex defining jump instruction patterns
5293 GCC does not assume anything about how the machine realizes jumps.
5294 The machine description should define a single pattern, usually
5295 a @code{define_expand}, which expands to all the required insns.
5297 Usually, this would be a comparison insn to set the condition code
5298 and a separate branch insn testing the condition code and branching
5299 or not according to its value. For many machines, however,
5300 separating compares and branches is limiting, which is why the
5301 more flexible approach with one @code{define_expand} is used in GCC.
5302 The machine description becomes clearer for architectures that
5303 have compare-and-branch instructions but no condition code. It also
5304 works better when different sets of comparison operators are supported
5305 by different kinds of conditional branches (e.g. integer vs. floating-point),
5306 or by conditional branches with respect to conditional stores.
5308 Two separate insns are always used if the machine description represents
5309 a condition code register using the legacy RTL expression @code{(cc0)},
5310 and on most machines that use a separate condition code register
5311 (@pxref{Condition Code}). For machines that use @code{(cc0)}, in
5312 fact, the set and use of the condition code must be separate and
5313 adjacent@footnote{@code{note} insns can separate them, though.}, thus
5314 allowing flags in @code{cc_status} to be used (@pxref{Condition Code}) and
5315 so that the comparison and branch insns could be located from each other
5316 by using the functions @code{prev_cc0_setter} and @code{next_cc0_user}.
5318 Even in this case having a single entry point for conditional branches
5319 is advantageous, because it handles equally well the case where a single
5320 comparison instruction records the results of both signed and unsigned
5321 comparison of the given operands (with the branch insns coming in distinct
5322 signed and unsigned flavors) as in the x86 or SPARC, and the case where
5323 there are distinct signed and unsigned compare instructions and only
5324 one set of conditional branch instructions as in the PowerPC.
5328 @node Looping Patterns
5329 @section Defining Looping Instruction Patterns
5330 @cindex looping instruction patterns
5331 @cindex defining looping instruction patterns
5333 Some machines have special jump instructions that can be utilized to
5334 make loops more efficient. A common example is the 68000 @samp{dbra}
5335 instruction which performs a decrement of a register and a branch if the
5336 result was greater than zero. Other machines, in particular digital
5337 signal processors (DSPs), have special block repeat instructions to
5338 provide low-overhead loop support. For example, the TI TMS320C3x/C4x
5339 DSPs have a block repeat instruction that loads special registers to
5340 mark the top and end of a loop and to count the number of loop
5341 iterations. This avoids the need for fetching and executing a
5342 @samp{dbra}-like instruction and avoids pipeline stalls associated with
5345 GCC has three special named patterns to support low overhead looping.
5346 They are @samp{decrement_and_branch_until_zero}, @samp{doloop_begin},
5347 and @samp{doloop_end}. The first pattern,
5348 @samp{decrement_and_branch_until_zero}, is not emitted during RTL
5349 generation but may be emitted during the instruction combination phase.
5350 This requires the assistance of the loop optimizer, using information
5351 collected during strength reduction, to reverse a loop to count down to
5352 zero. Some targets also require the loop optimizer to add a
5353 @code{REG_NONNEG} note to indicate that the iteration count is always
5354 positive. This is needed if the target performs a signed loop
5355 termination test. For example, the 68000 uses a pattern similar to the
5356 following for its @code{dbra} instruction:
5360 (define_insn "decrement_and_branch_until_zero"
5363 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
5366 (label_ref (match_operand 1 "" ""))
5369 (plus:SI (match_dup 0)
5371 "find_reg_note (insn, REG_NONNEG, 0)"
5376 Note that since the insn is both a jump insn and has an output, it must
5377 deal with its own reloads, hence the `m' constraints. Also note that
5378 since this insn is generated by the instruction combination phase
5379 combining two sequential insns together into an implicit parallel insn,
5380 the iteration counter needs to be biased by the same amount as the
5381 decrement operation, in this case @minus{}1. Note that the following similar
5382 pattern will not be matched by the combiner.
5386 (define_insn "decrement_and_branch_until_zero"
5389 (ge (match_operand:SI 0 "general_operand" "+d*am")
5391 (label_ref (match_operand 1 "" ""))
5394 (plus:SI (match_dup 0)
5396 "find_reg_note (insn, REG_NONNEG, 0)"
5401 The other two special looping patterns, @samp{doloop_begin} and
5402 @samp{doloop_end}, are emitted by the loop optimizer for certain
5403 well-behaved loops with a finite number of loop iterations using
5404 information collected during strength reduction.
5406 The @samp{doloop_end} pattern describes the actual looping instruction
5407 (or the implicit looping operation) and the @samp{doloop_begin} pattern
5408 is an optional companion pattern that can be used for initialization
5409 needed for some low-overhead looping instructions.
5411 Note that some machines require the actual looping instruction to be
5412 emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
5413 the true RTL for a looping instruction at the top of the loop can cause
5414 problems with flow analysis. So instead, a dummy @code{doloop} insn is
5415 emitted at the end of the loop. The machine dependent reorg pass checks
5416 for the presence of this @code{doloop} insn and then searches back to
5417 the top of the loop, where it inserts the true looping insn (provided
5418 there are no instructions in the loop which would cause problems). Any
5419 additional labels can be emitted at this point. In addition, if the
5420 desired special iteration counter register was not allocated, this
5421 machine dependent reorg pass could emit a traditional compare and jump
5424 The essential difference between the
5425 @samp{decrement_and_branch_until_zero} and the @samp{doloop_end}
5426 patterns is that the loop optimizer allocates an additional pseudo
5427 register for the latter as an iteration counter. This pseudo register
5428 cannot be used within the loop (i.e., general induction variables cannot
5429 be derived from it), however, in many cases the loop induction variable
5430 may become redundant and removed by the flow pass.
5435 @node Insn Canonicalizations
5436 @section Canonicalization of Instructions
5437 @cindex canonicalization of instructions
5438 @cindex insn canonicalization
5440 There are often cases where multiple RTL expressions could represent an
5441 operation performed by a single machine instruction. This situation is
5442 most commonly encountered with logical, branch, and multiply-accumulate
5443 instructions. In such cases, the compiler attempts to convert these
5444 multiple RTL expressions into a single canonical form to reduce the
5445 number of insn patterns required.
5447 In addition to algebraic simplifications, following canonicalizations
5452 For commutative and comparison operators, a constant is always made the
5453 second operand. If a machine only supports a constant as the second
5454 operand, only patterns that match a constant in the second operand need
5458 For associative operators, a sequence of operators will always chain
5459 to the left; for instance, only the left operand of an integer @code{plus}
5460 can itself be a @code{plus}. @code{and}, @code{ior}, @code{xor},
5461 @code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and
5462 @code{umax} are associative when applied to integers, and sometimes to
5466 @cindex @code{neg}, canonicalization of
5467 @cindex @code{not}, canonicalization of
5468 @cindex @code{mult}, canonicalization of
5469 @cindex @code{plus}, canonicalization of
5470 @cindex @code{minus}, canonicalization of
5471 For these operators, if only one operand is a @code{neg}, @code{not},
5472 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
5476 In combinations of @code{neg}, @code{mult}, @code{plus}, and
5477 @code{minus}, the @code{neg} operations (if any) will be moved inside
5478 the operations as far as possible. For instance,
5479 @code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but
5480 @code{(plus (mult (neg A) B) C)} is canonicalized as
5481 @code{(minus A (mult B C))}.
5483 @cindex @code{compare}, canonicalization of
5485 For the @code{compare} operator, a constant is always the second operand
5486 if the first argument is a condition code register or @code{(cc0)}.
5489 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
5490 @code{minus} is made the first operand under the same conditions as
5494 @code{(ltu (plus @var{a} @var{b}) @var{b})} is converted to
5495 @code{(ltu (plus @var{a} @var{b}) @var{a})}. Likewise with @code{geu} instead
5499 @code{(minus @var{x} (const_int @var{n}))} is converted to
5500 @code{(plus @var{x} (const_int @var{-n}))}.
5503 Within address computations (i.e., inside @code{mem}), a left shift is
5504 converted into the appropriate multiplication by a power of two.
5506 @cindex @code{ior}, canonicalization of
5507 @cindex @code{and}, canonicalization of
5508 @cindex De Morgan's law
5510 De Morgan's Law is used to move bitwise negation inside a bitwise
5511 logical-and or logical-or operation. If this results in only one
5512 operand being a @code{not} expression, it will be the first one.
5514 A machine that has an instruction that performs a bitwise logical-and of one
5515 operand with the bitwise negation of the other should specify the pattern
5516 for that instruction as
5520 [(set (match_operand:@var{m} 0 @dots{})
5521 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
5522 (match_operand:@var{m} 2 @dots{})))]
5528 Similarly, a pattern for a ``NAND'' instruction should be written
5532 [(set (match_operand:@var{m} 0 @dots{})
5533 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
5534 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
5539 In both cases, it is not necessary to include patterns for the many
5540 logically equivalent RTL expressions.
5542 @cindex @code{xor}, canonicalization of
5544 The only possible RTL expressions involving both bitwise exclusive-or
5545 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
5546 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
5549 The sum of three items, one of which is a constant, will only appear in
5553 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
5556 @cindex @code{zero_extract}, canonicalization of
5557 @cindex @code{sign_extract}, canonicalization of
5559 Equality comparisons of a group of bits (usually a single bit) with zero
5560 will be written using @code{zero_extract} rather than the equivalent
5561 @code{and} or @code{sign_extract} operations.
5565 Further canonicalization rules are defined in the function
5566 @code{commutative_operand_precedence} in @file{gcc/rtlanal.c}.
5570 @node Expander Definitions
5571 @section Defining RTL Sequences for Code Generation
5572 @cindex expander definitions
5573 @cindex code generation RTL sequences
5574 @cindex defining RTL sequences for code generation
5576 On some target machines, some standard pattern names for RTL generation
5577 cannot be handled with single insn, but a sequence of RTL insns can
5578 represent them. For these target machines, you can write a
5579 @code{define_expand} to specify how to generate the sequence of RTL@.
5581 @findex define_expand
5582 A @code{define_expand} is an RTL expression that looks almost like a
5583 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
5584 only for RTL generation and it can produce more than one RTL insn.
5586 A @code{define_expand} RTX has four operands:
5590 The name. Each @code{define_expand} must have a name, since the only
5591 use for it is to refer to it by name.
5594 The RTL template. This is a vector of RTL expressions representing
5595 a sequence of separate instructions. Unlike @code{define_insn}, there
5596 is no implicit surrounding @code{PARALLEL}.
5599 The condition, a string containing a C expression. This expression is
5600 used to express how the availability of this pattern depends on
5601 subclasses of target machine, selected by command-line options when GCC
5602 is run. This is just like the condition of a @code{define_insn} that
5603 has a standard name. Therefore, the condition (if present) may not
5604 depend on the data in the insn being matched, but only the
5605 target-machine-type flags. The compiler needs to test these conditions
5606 during initialization in order to learn exactly which named instructions
5607 are available in a particular run.
5610 The preparation statements, a string containing zero or more C
5611 statements which are to be executed before RTL code is generated from
5614 Usually these statements prepare temporary registers for use as
5615 internal operands in the RTL template, but they can also generate RTL
5616 insns directly by calling routines such as @code{emit_insn}, etc.
5617 Any such insns precede the ones that come from the RTL template.
5620 Every RTL insn emitted by a @code{define_expand} must match some
5621 @code{define_insn} in the machine description. Otherwise, the compiler
5622 will crash when trying to generate code for the insn or trying to optimize
5625 The RTL template, in addition to controlling generation of RTL insns,
5626 also describes the operands that need to be specified when this pattern
5627 is used. In particular, it gives a predicate for each operand.
5629 A true operand, which needs to be specified in order to generate RTL from
5630 the pattern, should be described with a @code{match_operand} in its first
5631 occurrence in the RTL template. This enters information on the operand's
5632 predicate into the tables that record such things. GCC uses the
5633 information to preload the operand into a register if that is required for
5634 valid RTL code. If the operand is referred to more than once, subsequent
5635 references should use @code{match_dup}.
5637 The RTL template may also refer to internal ``operands'' which are
5638 temporary registers or labels used only within the sequence made by the
5639 @code{define_expand}. Internal operands are substituted into the RTL
5640 template with @code{match_dup}, never with @code{match_operand}. The
5641 values of the internal operands are not passed in as arguments by the
5642 compiler when it requests use of this pattern. Instead, they are computed
5643 within the pattern, in the preparation statements. These statements
5644 compute the values and store them into the appropriate elements of
5645 @code{operands} so that @code{match_dup} can find them.
5647 There are two special macros defined for use in the preparation statements:
5648 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
5655 Use the @code{DONE} macro to end RTL generation for the pattern. The
5656 only RTL insns resulting from the pattern on this occasion will be
5657 those already emitted by explicit calls to @code{emit_insn} within the
5658 preparation statements; the RTL template will not be generated.
5662 Make the pattern fail on this occasion. When a pattern fails, it means
5663 that the pattern was not truly available. The calling routines in the
5664 compiler will try other strategies for code generation using other patterns.
5666 Failure is currently supported only for binary (addition, multiplication,
5667 shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv})
5671 If the preparation falls through (invokes neither @code{DONE} nor
5672 @code{FAIL}), then the @code{define_expand} acts like a
5673 @code{define_insn} in that the RTL template is used to generate the
5676 The RTL template is not used for matching, only for generating the
5677 initial insn list. If the preparation statement always invokes
5678 @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple
5679 list of operands, such as this example:
5683 (define_expand "addsi3"
5684 [(match_operand:SI 0 "register_operand" "")
5685 (match_operand:SI 1 "register_operand" "")
5686 (match_operand:SI 2 "register_operand" "")]
5692 handle_add (operands[0], operands[1], operands[2]);
5698 Here is an example, the definition of left-shift for the SPUR chip:
5702 (define_expand "ashlsi3"
5703 [(set (match_operand:SI 0 "register_operand" "")
5707 (match_operand:SI 1 "register_operand" "")
5708 (match_operand:SI 2 "nonmemory_operand" "")))]
5717 if (GET_CODE (operands[2]) != CONST_INT
5718 || (unsigned) INTVAL (operands[2]) > 3)
5725 This example uses @code{define_expand} so that it can generate an RTL insn
5726 for shifting when the shift-count is in the supported range of 0 to 3 but
5727 fail in other cases where machine insns aren't available. When it fails,
5728 the compiler tries another strategy using different patterns (such as, a
5731 If the compiler were able to handle nontrivial condition-strings in
5732 patterns with names, then it would be possible to use a
5733 @code{define_insn} in that case. Here is another case (zero-extension
5734 on the 68000) which makes more use of the power of @code{define_expand}:
5737 (define_expand "zero_extendhisi2"
5738 [(set (match_operand:SI 0 "general_operand" "")
5740 (set (strict_low_part
5744 (match_operand:HI 1 "general_operand" ""))]
5746 "operands[1] = make_safe_from (operands[1], operands[0]);")
5750 @findex make_safe_from
5751 Here two RTL insns are generated, one to clear the entire output operand
5752 and the other to copy the input operand into its low half. This sequence
5753 is incorrect if the input operand refers to [the old value of] the output
5754 operand, so the preparation statement makes sure this isn't so. The
5755 function @code{make_safe_from} copies the @code{operands[1]} into a
5756 temporary register if it refers to @code{operands[0]}. It does this
5757 by emitting another RTL insn.
5759 Finally, a third example shows the use of an internal operand.
5760 Zero-extension on the SPUR chip is done by @code{and}-ing the result
5761 against a halfword mask. But this mask cannot be represented by a
5762 @code{const_int} because the constant value is too large to be legitimate
5763 on this machine. So it must be copied into a register with
5764 @code{force_reg} and then the register used in the @code{and}.
5767 (define_expand "zero_extendhisi2"
5768 [(set (match_operand:SI 0 "register_operand" "")
5770 (match_operand:HI 1 "register_operand" "")
5775 = force_reg (SImode, GEN_INT (65535)); ")
5778 @emph{Note:} If the @code{define_expand} is used to serve a
5779 standard binary or unary arithmetic operation or a bit-field operation,
5780 then the last insn it generates must not be a @code{code_label},
5781 @code{barrier} or @code{note}. It must be an @code{insn},
5782 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
5783 at the end, emit an insn to copy the result of the operation into
5784 itself. Such an insn will generate no code, but it can avoid problems
5789 @node Insn Splitting
5790 @section Defining How to Split Instructions
5791 @cindex insn splitting
5792 @cindex instruction splitting
5793 @cindex splitting instructions
5795 There are two cases where you should specify how to split a pattern
5796 into multiple insns. On machines that have instructions requiring
5797 delay slots (@pxref{Delay Slots}) or that have instructions whose
5798 output is not available for multiple cycles (@pxref{Processor pipeline
5799 description}), the compiler phases that optimize these cases need to
5800 be able to move insns into one-instruction delay slots. However, some
5801 insns may generate more than one machine instruction. These insns
5802 cannot be placed into a delay slot.
5804 Often you can rewrite the single insn as a list of individual insns,
5805 each corresponding to one machine instruction. The disadvantage of
5806 doing so is that it will cause the compilation to be slower and require
5807 more space. If the resulting insns are too complex, it may also
5808 suppress some optimizations. The compiler splits the insn if there is a
5809 reason to believe that it might improve instruction or delay slot
5812 The insn combiner phase also splits putative insns. If three insns are
5813 merged into one insn with a complex expression that cannot be matched by
5814 some @code{define_insn} pattern, the combiner phase attempts to split
5815 the complex pattern into two insns that are recognized. Usually it can
5816 break the complex pattern into two patterns by splitting out some
5817 subexpression. However, in some other cases, such as performing an
5818 addition of a large constant in two insns on a RISC machine, the way to
5819 split the addition into two insns is machine-dependent.
5821 @findex define_split
5822 The @code{define_split} definition tells the compiler how to split a
5823 complex insn into several simpler insns. It looks like this:
5827 [@var{insn-pattern}]
5829 [@var{new-insn-pattern-1}
5830 @var{new-insn-pattern-2}
5832 "@var{preparation-statements}")
5835 @var{insn-pattern} is a pattern that needs to be split and
5836 @var{condition} is the final condition to be tested, as in a
5837 @code{define_insn}. When an insn matching @var{insn-pattern} and
5838 satisfying @var{condition} is found, it is replaced in the insn list
5839 with the insns given by @var{new-insn-pattern-1},
5840 @var{new-insn-pattern-2}, etc.
5842 The @var{preparation-statements} are similar to those statements that
5843 are specified for @code{define_expand} (@pxref{Expander Definitions})
5844 and are executed before the new RTL is generated to prepare for the
5845 generated code or emit some insns whose pattern is not fixed. Unlike
5846 those in @code{define_expand}, however, these statements must not
5847 generate any new pseudo-registers. Once reload has completed, they also
5848 must not allocate any space in the stack frame.
5850 Patterns are matched against @var{insn-pattern} in two different
5851 circumstances. If an insn needs to be split for delay slot scheduling
5852 or insn scheduling, the insn is already known to be valid, which means
5853 that it must have been matched by some @code{define_insn} and, if
5854 @code{reload_completed} is nonzero, is known to satisfy the constraints
5855 of that @code{define_insn}. In that case, the new insn patterns must
5856 also be insns that are matched by some @code{define_insn} and, if
5857 @code{reload_completed} is nonzero, must also satisfy the constraints
5858 of those definitions.
5860 As an example of this usage of @code{define_split}, consider the following
5861 example from @file{a29k.md}, which splits a @code{sign_extend} from
5862 @code{HImode} to @code{SImode} into a pair of shift insns:
5866 [(set (match_operand:SI 0 "gen_reg_operand" "")
5867 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
5870 (ashift:SI (match_dup 1)
5873 (ashiftrt:SI (match_dup 0)
5876 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
5879 When the combiner phase tries to split an insn pattern, it is always the
5880 case that the pattern is @emph{not} matched by any @code{define_insn}.
5881 The combiner pass first tries to split a single @code{set} expression
5882 and then the same @code{set} expression inside a @code{parallel}, but
5883 followed by a @code{clobber} of a pseudo-reg to use as a scratch
5884 register. In these cases, the combiner expects exactly two new insn
5885 patterns to be generated. It will verify that these patterns match some
5886 @code{define_insn} definitions, so you need not do this test in the
5887 @code{define_split} (of course, there is no point in writing a
5888 @code{define_split} that will never produce insns that match).
5890 Here is an example of this use of @code{define_split}, taken from
5895 [(set (match_operand:SI 0 "gen_reg_operand" "")
5896 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
5897 (match_operand:SI 2 "non_add_cint_operand" "")))]
5899 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
5900 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
5903 int low = INTVAL (operands[2]) & 0xffff;
5904 int high = (unsigned) INTVAL (operands[2]) >> 16;
5907 high++, low |= 0xffff0000;
5909 operands[3] = GEN_INT (high << 16);
5910 operands[4] = GEN_INT (low);
5914 Here the predicate @code{non_add_cint_operand} matches any
5915 @code{const_int} that is @emph{not} a valid operand of a single add
5916 insn. The add with the smaller displacement is written so that it
5917 can be substituted into the address of a subsequent operation.
5919 An example that uses a scratch register, from the same file, generates
5920 an equality comparison of a register and a large constant:
5924 [(set (match_operand:CC 0 "cc_reg_operand" "")
5925 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
5926 (match_operand:SI 2 "non_short_cint_operand" "")))
5927 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
5928 "find_single_use (operands[0], insn, 0)
5929 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
5930 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
5931 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
5932 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
5935 /* @r{Get the constant we are comparing against, C, and see what it
5936 looks like sign-extended to 16 bits. Then see what constant
5937 could be XOR'ed with C to get the sign-extended value.} */
5939 int c = INTVAL (operands[2]);
5940 int sextc = (c << 16) >> 16;
5941 int xorv = c ^ sextc;
5943 operands[4] = GEN_INT (xorv);
5944 operands[5] = GEN_INT (sextc);
5948 To avoid confusion, don't write a single @code{define_split} that
5949 accepts some insns that match some @code{define_insn} as well as some
5950 insns that don't. Instead, write two separate @code{define_split}
5951 definitions, one for the insns that are valid and one for the insns that
5954 The splitter is allowed to split jump instructions into sequence of
5955 jumps or create new jumps in while splitting non-jump instructions. As
5956 the central flowgraph and branch prediction information needs to be updated,
5957 several restriction apply.
5959 Splitting of jump instruction into sequence that over by another jump
5960 instruction is always valid, as compiler expect identical behavior of new
5961 jump. When new sequence contains multiple jump instructions or new labels,
5962 more assistance is needed. Splitter is required to create only unconditional
5963 jumps, or simple conditional jump instructions. Additionally it must attach a
5964 @code{REG_BR_PROB} note to each conditional jump. A global variable
5965 @code{split_branch_probability} holds the probability of the original branch in case
5966 it was a simple conditional jump, @minus{}1 otherwise. To simplify
5967 recomputing of edge frequencies, the new sequence is required to have only
5968 forward jumps to the newly created labels.
5970 @findex define_insn_and_split
5971 For the common case where the pattern of a define_split exactly matches the
5972 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
5976 (define_insn_and_split
5977 [@var{insn-pattern}]
5979 "@var{output-template}"
5980 "@var{split-condition}"
5981 [@var{new-insn-pattern-1}
5982 @var{new-insn-pattern-2}
5984 "@var{preparation-statements}"
5985 [@var{insn-attributes}])
5989 @var{insn-pattern}, @var{condition}, @var{output-template}, and
5990 @var{insn-attributes} are used as in @code{define_insn}. The
5991 @var{new-insn-pattern} vector and the @var{preparation-statements} are used as
5992 in a @code{define_split}. The @var{split-condition} is also used as in
5993 @code{define_split}, with the additional behavior that if the condition starts
5994 with @samp{&&}, the condition used for the split will be the constructed as a
5995 logical ``and'' of the split condition with the insn condition. For example,
5999 (define_insn_and_split "zero_extendhisi2_and"
6000 [(set (match_operand:SI 0 "register_operand" "=r")
6001 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
6002 (clobber (reg:CC 17))]
6003 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
6005 "&& reload_completed"
6006 [(parallel [(set (match_dup 0)
6007 (and:SI (match_dup 0) (const_int 65535)))
6008 (clobber (reg:CC 17))])]
6010 [(set_attr "type" "alu1")])
6014 In this case, the actual split condition will be
6015 @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
6017 The @code{define_insn_and_split} construction provides exactly the same
6018 functionality as two separate @code{define_insn} and @code{define_split}
6019 patterns. It exists for compactness, and as a maintenance tool to prevent
6020 having to ensure the two patterns' templates match.
6024 @node Including Patterns
6025 @section Including Patterns in Machine Descriptions.
6026 @cindex insn includes
6029 The @code{include} pattern tells the compiler tools where to
6030 look for patterns that are in files other than in the file
6031 @file{.md}. This is used only at build time and there is no preprocessing allowed.
6045 (include "filestuff")
6049 Where @var{pathname} is a string that specifies the location of the file,
6050 specifies the include file to be in @file{gcc/config/target/filestuff}. The
6051 directory @file{gcc/config/target} is regarded as the default directory.
6054 Machine descriptions may be split up into smaller more manageable subsections
6055 and placed into subdirectories.
6061 (include "BOGUS/filestuff")
6065 the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}.
6067 Specifying an absolute path for the include file such as;
6070 (include "/u2/BOGUS/filestuff")
6073 is permitted but is not encouraged.
6075 @subsection RTL Generation Tool Options for Directory Search
6076 @cindex directory options .md
6077 @cindex options, directory search
6078 @cindex search options
6080 The @option{-I@var{dir}} option specifies directories to search for machine descriptions.
6085 genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md
6090 Add the directory @var{dir} to the head of the list of directories to be
6091 searched for header files. This can be used to override a system machine definition
6092 file, substituting your own version, since these directories are
6093 searched before the default machine description file directories. If you use more than
6094 one @option{-I} option, the directories are scanned in left-to-right
6095 order; the standard default directory come after.
6100 @node Peephole Definitions
6101 @section Machine-Specific Peephole Optimizers
6102 @cindex peephole optimizer definitions
6103 @cindex defining peephole optimizers
6105 In addition to instruction patterns the @file{md} file may contain
6106 definitions of machine-specific peephole optimizations.
6108 The combiner does not notice certain peephole optimizations when the data
6109 flow in the program does not suggest that it should try them. For example,
6110 sometimes two consecutive insns related in purpose can be combined even
6111 though the second one does not appear to use a register computed in the
6112 first one. A machine-specific peephole optimizer can detect such
6115 There are two forms of peephole definitions that may be used. The
6116 original @code{define_peephole} is run at assembly output time to
6117 match insns and substitute assembly text. Use of @code{define_peephole}
6120 A newer @code{define_peephole2} matches insns and substitutes new
6121 insns. The @code{peephole2} pass is run after register allocation
6122 but before scheduling, which may result in much better code for
6123 targets that do scheduling.
6126 * define_peephole:: RTL to Text Peephole Optimizers
6127 * define_peephole2:: RTL to RTL Peephole Optimizers
6132 @node define_peephole
6133 @subsection RTL to Text Peephole Optimizers
6134 @findex define_peephole
6137 A definition looks like this:
6141 [@var{insn-pattern-1}
6142 @var{insn-pattern-2}
6146 "@var{optional-insn-attributes}")
6150 The last string operand may be omitted if you are not using any
6151 machine-specific information in this machine description. If present,
6152 it must obey the same rules as in a @code{define_insn}.
6154 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
6155 consecutive insns. The optimization applies to a sequence of insns when
6156 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
6157 the next, and so on.
6159 Each of the insns matched by a peephole must also match a
6160 @code{define_insn}. Peepholes are checked only at the last stage just
6161 before code generation, and only optionally. Therefore, any insn which
6162 would match a peephole but no @code{define_insn} will cause a crash in code
6163 generation in an unoptimized compilation, or at various optimization
6166 The operands of the insns are matched with @code{match_operands},
6167 @code{match_operator}, and @code{match_dup}, as usual. What is not
6168 usual is that the operand numbers apply to all the insn patterns in the
6169 definition. So, you can check for identical operands in two insns by
6170 using @code{match_operand} in one insn and @code{match_dup} in the
6173 The operand constraints used in @code{match_operand} patterns do not have
6174 any direct effect on the applicability of the peephole, but they will
6175 be validated afterward, so make sure your constraints are general enough
6176 to apply whenever the peephole matches. If the peephole matches
6177 but the constraints are not satisfied, the compiler will crash.
6179 It is safe to omit constraints in all the operands of the peephole; or
6180 you can write constraints which serve as a double-check on the criteria
6183 Once a sequence of insns matches the patterns, the @var{condition} is
6184 checked. This is a C expression which makes the final decision whether to
6185 perform the optimization (we do so if the expression is nonzero). If
6186 @var{condition} is omitted (in other words, the string is empty) then the
6187 optimization is applied to every sequence of insns that matches the
6190 The defined peephole optimizations are applied after register allocation
6191 is complete. Therefore, the peephole definition can check which
6192 operands have ended up in which kinds of registers, just by looking at
6195 @findex prev_active_insn
6196 The way to refer to the operands in @var{condition} is to write
6197 @code{operands[@var{i}]} for operand number @var{i} (as matched by
6198 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
6199 to refer to the last of the insns being matched; use
6200 @code{prev_active_insn} to find the preceding insns.
6202 @findex dead_or_set_p
6203 When optimizing computations with intermediate results, you can use
6204 @var{condition} to match only when the intermediate results are not used
6205 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
6206 @var{op})}, where @var{insn} is the insn in which you expect the value
6207 to be used for the last time (from the value of @code{insn}, together
6208 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
6209 value (from @code{operands[@var{i}]}).
6211 Applying the optimization means replacing the sequence of insns with one
6212 new insn. The @var{template} controls ultimate output of assembler code
6213 for this combined insn. It works exactly like the template of a
6214 @code{define_insn}. Operand numbers in this template are the same ones
6215 used in matching the original sequence of insns.
6217 The result of a defined peephole optimizer does not need to match any of
6218 the insn patterns in the machine description; it does not even have an
6219 opportunity to match them. The peephole optimizer definition itself serves
6220 as the insn pattern to control how the insn is output.
6222 Defined peephole optimizers are run as assembler code is being output,
6223 so the insns they produce are never combined or rearranged in any way.
6225 Here is an example, taken from the 68000 machine description:
6229 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
6230 (set (match_operand:DF 0 "register_operand" "=f")
6231 (match_operand:DF 1 "register_operand" "ad"))]
6232 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
6235 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
6237 output_asm_insn ("move.l %1,(sp)", xoperands);
6238 output_asm_insn ("move.l %1,-(sp)", operands);
6239 return "fmove.d (sp)+,%0";
6241 output_asm_insn ("movel %1,sp@@", xoperands);
6242 output_asm_insn ("movel %1,sp@@-", operands);
6243 return "fmoved sp@@+,%0";
6249 The effect of this optimization is to change
6275 If a peephole matches a sequence including one or more jump insns, you must
6276 take account of the flags such as @code{CC_REVERSED} which specify that the
6277 condition codes are represented in an unusual manner. The compiler
6278 automatically alters any ordinary conditional jumps which occur in such
6279 situations, but the compiler cannot alter jumps which have been replaced by
6280 peephole optimizations. So it is up to you to alter the assembler code
6281 that the peephole produces. Supply C code to write the assembler output,
6282 and in this C code check the condition code status flags and change the
6283 assembler code as appropriate.
6286 @var{insn-pattern-1} and so on look @emph{almost} like the second
6287 operand of @code{define_insn}. There is one important difference: the
6288 second operand of @code{define_insn} consists of one or more RTX's
6289 enclosed in square brackets. Usually, there is only one: then the same
6290 action can be written as an element of a @code{define_peephole}. But
6291 when there are multiple actions in a @code{define_insn}, they are
6292 implicitly enclosed in a @code{parallel}. Then you must explicitly
6293 write the @code{parallel}, and the square brackets within it, in the
6294 @code{define_peephole}. Thus, if an insn pattern looks like this,
6297 (define_insn "divmodsi4"
6298 [(set (match_operand:SI 0 "general_operand" "=d")
6299 (div:SI (match_operand:SI 1 "general_operand" "0")
6300 (match_operand:SI 2 "general_operand" "dmsK")))
6301 (set (match_operand:SI 3 "general_operand" "=d")
6302 (mod:SI (match_dup 1) (match_dup 2)))]
6304 "divsl%.l %2,%3:%0")
6308 then the way to mention this insn in a peephole is as follows:
6314 [(set (match_operand:SI 0 "general_operand" "=d")
6315 (div:SI (match_operand:SI 1 "general_operand" "0")
6316 (match_operand:SI 2 "general_operand" "dmsK")))
6317 (set (match_operand:SI 3 "general_operand" "=d")
6318 (mod:SI (match_dup 1) (match_dup 2)))])
6325 @node define_peephole2
6326 @subsection RTL to RTL Peephole Optimizers
6327 @findex define_peephole2
6329 The @code{define_peephole2} definition tells the compiler how to
6330 substitute one sequence of instructions for another sequence,
6331 what additional scratch registers may be needed and what their
6336 [@var{insn-pattern-1}
6337 @var{insn-pattern-2}
6340 [@var{new-insn-pattern-1}
6341 @var{new-insn-pattern-2}
6343 "@var{preparation-statements}")
6346 The definition is almost identical to @code{define_split}
6347 (@pxref{Insn Splitting}) except that the pattern to match is not a
6348 single instruction, but a sequence of instructions.
6350 It is possible to request additional scratch registers for use in the
6351 output template. If appropriate registers are not free, the pattern
6352 will simply not match.
6354 @findex match_scratch
6356 Scratch registers are requested with a @code{match_scratch} pattern at
6357 the top level of the input pattern. The allocated register (initially) will
6358 be dead at the point requested within the original sequence. If the scratch
6359 is used at more than a single point, a @code{match_dup} pattern at the
6360 top level of the input pattern marks the last position in the input sequence
6361 at which the register must be available.
6363 Here is an example from the IA-32 machine description:
6367 [(match_scratch:SI 2 "r")
6368 (parallel [(set (match_operand:SI 0 "register_operand" "")
6369 (match_operator:SI 3 "arith_or_logical_operator"
6371 (match_operand:SI 1 "memory_operand" "")]))
6372 (clobber (reg:CC 17))])]
6373 "! optimize_size && ! TARGET_READ_MODIFY"
6374 [(set (match_dup 2) (match_dup 1))
6375 (parallel [(set (match_dup 0)
6376 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
6377 (clobber (reg:CC 17))])]
6382 This pattern tries to split a load from its use in the hopes that we'll be
6383 able to schedule around the memory load latency. It allocates a single
6384 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
6385 to be live only at the point just before the arithmetic.
6387 A real example requiring extended scratch lifetimes is harder to come by,
6388 so here's a silly made-up example:
6392 [(match_scratch:SI 4 "r")
6393 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
6394 (set (match_operand:SI 2 "" "") (match_dup 1))
6396 (set (match_operand:SI 3 "" "") (match_dup 1))]
6397 "/* @r{determine 1 does not overlap 0 and 2} */"
6398 [(set (match_dup 4) (match_dup 1))
6399 (set (match_dup 0) (match_dup 4))
6400 (set (match_dup 2) (match_dup 4))]
6401 (set (match_dup 3) (match_dup 4))]
6406 If we had not added the @code{(match_dup 4)} in the middle of the input
6407 sequence, it might have been the case that the register we chose at the
6408 beginning of the sequence is killed by the first or second @code{set}.
6412 @node Insn Attributes
6413 @section Instruction Attributes
6414 @cindex insn attributes
6415 @cindex instruction attributes
6417 In addition to describing the instruction supported by the target machine,
6418 the @file{md} file also defines a group of @dfn{attributes} and a set of
6419 values for each. Every generated insn is assigned a value for each attribute.
6420 One possible attribute would be the effect that the insn has on the machine's
6421 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
6422 to track the condition codes.
6425 * Defining Attributes:: Specifying attributes and their values.
6426 * Expressions:: Valid expressions for attribute values.
6427 * Tagging Insns:: Assigning attribute values to insns.
6428 * Attr Example:: An example of assigning attributes.
6429 * Insn Lengths:: Computing the length of insns.
6430 * Constant Attributes:: Defining attributes that are constant.
6431 * Delay Slots:: Defining delay slots required for a machine.
6432 * Processor pipeline description:: Specifying information for insn scheduling.
6437 @node Defining Attributes
6438 @subsection Defining Attributes and their Values
6439 @cindex defining attributes and their values
6440 @cindex attributes, defining
6443 The @code{define_attr} expression is used to define each attribute required
6444 by the target machine. It looks like:
6447 (define_attr @var{name} @var{list-of-values} @var{default})
6450 @var{name} is a string specifying the name of the attribute being defined.
6452 @var{list-of-values} is either a string that specifies a comma-separated
6453 list of values that can be assigned to the attribute, or a null string to
6454 indicate that the attribute takes numeric values.
6456 @var{default} is an attribute expression that gives the value of this
6457 attribute for insns that match patterns whose definition does not include
6458 an explicit value for this attribute. @xref{Attr Example}, for more
6459 information on the handling of defaults. @xref{Constant Attributes},
6460 for information on attributes that do not depend on any particular insn.
6463 For each defined attribute, a number of definitions are written to the
6464 @file{insn-attr.h} file. For cases where an explicit set of values is
6465 specified for an attribute, the following are defined:
6469 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
6472 An enumerated class is defined for @samp{attr_@var{name}} with
6473 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
6474 the attribute name and value are first converted to uppercase.
6477 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
6478 returns the attribute value for that insn.
6481 For example, if the following is present in the @file{md} file:
6484 (define_attr "type" "branch,fp,load,store,arith" @dots{})
6488 the following lines will be written to the file @file{insn-attr.h}.
6491 #define HAVE_ATTR_type
6492 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
6493 TYPE_STORE, TYPE_ARITH@};
6494 extern enum attr_type get_attr_type ();
6497 If the attribute takes numeric values, no @code{enum} type will be
6498 defined and the function to obtain the attribute's value will return
6501 There are attributes which are tied to a specific meaning. These
6502 attributes are not free to use for other purposes:
6506 The @code{length} attribute is used to calculate the length of emitted
6507 code chunks. This is especially important when verifying branch
6508 distances. @xref{Insn Lengths}.
6511 The @code{enabled} attribute can be defined to prevent certain
6512 alternatives of an insn definition from being used during code
6513 generation. @xref{Disable Insn Alternatives}.
6520 @subsection Attribute Expressions
6521 @cindex attribute expressions
6523 RTL expressions used to define attributes use the codes described above
6524 plus a few specific to attribute definitions, to be discussed below.
6525 Attribute value expressions must have one of the following forms:
6528 @cindex @code{const_int} and attributes
6529 @item (const_int @var{i})
6530 The integer @var{i} specifies the value of a numeric attribute. @var{i}
6531 must be non-negative.
6533 The value of a numeric attribute can be specified either with a
6534 @code{const_int}, or as an integer represented as a string in
6535 @code{const_string}, @code{eq_attr} (see below), @code{attr},
6536 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
6537 overrides on specific instructions (@pxref{Tagging Insns}).
6539 @cindex @code{const_string} and attributes
6540 @item (const_string @var{value})
6541 The string @var{value} specifies a constant attribute value.
6542 If @var{value} is specified as @samp{"*"}, it means that the default value of
6543 the attribute is to be used for the insn containing this expression.
6544 @samp{"*"} obviously cannot be used in the @var{default} expression
6545 of a @code{define_attr}.
6547 If the attribute whose value is being specified is numeric, @var{value}
6548 must be a string containing a non-negative integer (normally
6549 @code{const_int} would be used in this case). Otherwise, it must
6550 contain one of the valid values for the attribute.
6552 @cindex @code{if_then_else} and attributes
6553 @item (if_then_else @var{test} @var{true-value} @var{false-value})
6554 @var{test} specifies an attribute test, whose format is defined below.
6555 The value of this expression is @var{true-value} if @var{test} is true,
6556 otherwise it is @var{false-value}.
6558 @cindex @code{cond} and attributes
6559 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
6560 The first operand of this expression is a vector containing an even
6561 number of expressions and consisting of pairs of @var{test} and @var{value}
6562 expressions. The value of the @code{cond} expression is that of the
6563 @var{value} corresponding to the first true @var{test} expression. If
6564 none of the @var{test} expressions are true, the value of the @code{cond}
6565 expression is that of the @var{default} expression.
6568 @var{test} expressions can have one of the following forms:
6571 @cindex @code{const_int} and attribute tests
6572 @item (const_int @var{i})
6573 This test is true if @var{i} is nonzero and false otherwise.
6575 @cindex @code{not} and attributes
6576 @cindex @code{ior} and attributes
6577 @cindex @code{and} and attributes
6578 @item (not @var{test})
6579 @itemx (ior @var{test1} @var{test2})
6580 @itemx (and @var{test1} @var{test2})
6581 These tests are true if the indicated logical function is true.
6583 @cindex @code{match_operand} and attributes
6584 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
6585 This test is true if operand @var{n} of the insn whose attribute value
6586 is being determined has mode @var{m} (this part of the test is ignored
6587 if @var{m} is @code{VOIDmode}) and the function specified by the string
6588 @var{pred} returns a nonzero value when passed operand @var{n} and mode
6589 @var{m} (this part of the test is ignored if @var{pred} is the null
6592 The @var{constraints} operand is ignored and should be the null string.
6594 @cindex @code{le} and attributes
6595 @cindex @code{leu} and attributes
6596 @cindex @code{lt} and attributes
6597 @cindex @code{gt} and attributes
6598 @cindex @code{gtu} and attributes
6599 @cindex @code{ge} and attributes
6600 @cindex @code{geu} and attributes
6601 @cindex @code{ne} and attributes
6602 @cindex @code{eq} and attributes
6603 @cindex @code{plus} and attributes
6604 @cindex @code{minus} and attributes
6605 @cindex @code{mult} and attributes
6606 @cindex @code{div} and attributes
6607 @cindex @code{mod} and attributes
6608 @cindex @code{abs} and attributes
6609 @cindex @code{neg} and attributes
6610 @cindex @code{ashift} and attributes
6611 @cindex @code{lshiftrt} and attributes
6612 @cindex @code{ashiftrt} and attributes
6613 @item (le @var{arith1} @var{arith2})
6614 @itemx (leu @var{arith1} @var{arith2})
6615 @itemx (lt @var{arith1} @var{arith2})
6616 @itemx (ltu @var{arith1} @var{arith2})
6617 @itemx (gt @var{arith1} @var{arith2})
6618 @itemx (gtu @var{arith1} @var{arith2})
6619 @itemx (ge @var{arith1} @var{arith2})
6620 @itemx (geu @var{arith1} @var{arith2})
6621 @itemx (ne @var{arith1} @var{arith2})
6622 @itemx (eq @var{arith1} @var{arith2})
6623 These tests are true if the indicated comparison of the two arithmetic
6624 expressions is true. Arithmetic expressions are formed with
6625 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
6626 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
6627 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
6630 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
6631 Lengths},for additional forms). @code{symbol_ref} is a string
6632 denoting a C expression that yields an @code{int} when evaluated by the
6633 @samp{get_attr_@dots{}} routine. It should normally be a global
6637 @item (eq_attr @var{name} @var{value})
6638 @var{name} is a string specifying the name of an attribute.
6640 @var{value} is a string that is either a valid value for attribute
6641 @var{name}, a comma-separated list of values, or @samp{!} followed by a
6642 value or list. If @var{value} does not begin with a @samp{!}, this
6643 test is true if the value of the @var{name} attribute of the current
6644 insn is in the list specified by @var{value}. If @var{value} begins
6645 with a @samp{!}, this test is true if the attribute's value is
6646 @emph{not} in the specified list.
6651 (eq_attr "type" "load,store")
6658 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
6661 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
6662 value of the compiler variable @code{which_alternative}
6663 (@pxref{Output Statement}) and the values must be small integers. For
6667 (eq_attr "alternative" "2,3")
6674 (ior (eq (symbol_ref "which_alternative") (const_int 2))
6675 (eq (symbol_ref "which_alternative") (const_int 3)))
6678 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
6679 where the value of the attribute being tested is known for all insns matching
6680 a particular pattern. This is by far the most common case.
6683 @item (attr_flag @var{name})
6684 The value of an @code{attr_flag} expression is true if the flag
6685 specified by @var{name} is true for the @code{insn} currently being
6688 @var{name} is a string specifying one of a fixed set of flags to test.
6689 Test the flags @code{forward} and @code{backward} to determine the
6690 direction of a conditional branch. Test the flags @code{very_likely},
6691 @code{likely}, @code{very_unlikely}, and @code{unlikely} to determine
6692 if a conditional branch is expected to be taken.
6694 If the @code{very_likely} flag is true, then the @code{likely} flag is also
6695 true. Likewise for the @code{very_unlikely} and @code{unlikely} flags.
6697 This example describes a conditional branch delay slot which
6698 can be nullified for forward branches that are taken (annul-true) or
6699 for backward branches which are not taken (annul-false).
6702 (define_delay (eq_attr "type" "cbranch")
6703 [(eq_attr "in_branch_delay" "true")
6704 (and (eq_attr "in_branch_delay" "true")
6705 (attr_flag "forward"))
6706 (and (eq_attr "in_branch_delay" "true")
6707 (attr_flag "backward"))])
6710 The @code{forward} and @code{backward} flags are false if the current
6711 @code{insn} being scheduled is not a conditional branch.
6713 The @code{very_likely} and @code{likely} flags are true if the
6714 @code{insn} being scheduled is not a conditional branch.
6715 The @code{very_unlikely} and @code{unlikely} flags are false if the
6716 @code{insn} being scheduled is not a conditional branch.
6718 @code{attr_flag} is only used during delay slot scheduling and has no
6719 meaning to other passes of the compiler.
6722 @item (attr @var{name})
6723 The value of another attribute is returned. This is most useful
6724 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
6725 produce more efficient code for non-numeric attributes.
6731 @subsection Assigning Attribute Values to Insns
6732 @cindex tagging insns
6733 @cindex assigning attribute values to insns
6735 The value assigned to an attribute of an insn is primarily determined by
6736 which pattern is matched by that insn (or which @code{define_peephole}
6737 generated it). Every @code{define_insn} and @code{define_peephole} can
6738 have an optional last argument to specify the values of attributes for
6739 matching insns. The value of any attribute not specified in a particular
6740 insn is set to the default value for that attribute, as specified in its
6741 @code{define_attr}. Extensive use of default values for attributes
6742 permits the specification of the values for only one or two attributes
6743 in the definition of most insn patterns, as seen in the example in the
6746 The optional last argument of @code{define_insn} and
6747 @code{define_peephole} is a vector of expressions, each of which defines
6748 the value for a single attribute. The most general way of assigning an
6749 attribute's value is to use a @code{set} expression whose first operand is an
6750 @code{attr} expression giving the name of the attribute being set. The
6751 second operand of the @code{set} is an attribute expression
6752 (@pxref{Expressions}) giving the value of the attribute.
6754 When the attribute value depends on the @samp{alternative} attribute
6755 (i.e., which is the applicable alternative in the constraint of the
6756 insn), the @code{set_attr_alternative} expression can be used. It
6757 allows the specification of a vector of attribute expressions, one for
6761 When the generality of arbitrary attribute expressions is not required,
6762 the simpler @code{set_attr} expression can be used, which allows
6763 specifying a string giving either a single attribute value or a list
6764 of attribute values, one for each alternative.
6766 The form of each of the above specifications is shown below. In each case,
6767 @var{name} is a string specifying the attribute to be set.
6770 @item (set_attr @var{name} @var{value-string})
6771 @var{value-string} is either a string giving the desired attribute value,
6772 or a string containing a comma-separated list giving the values for
6773 succeeding alternatives. The number of elements must match the number
6774 of alternatives in the constraint of the insn pattern.
6776 Note that it may be useful to specify @samp{*} for some alternative, in
6777 which case the attribute will assume its default value for insns matching
6780 @findex set_attr_alternative
6781 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
6782 Depending on the alternative of the insn, the value will be one of the
6783 specified values. This is a shorthand for using a @code{cond} with
6784 tests on the @samp{alternative} attribute.
6787 @item (set (attr @var{name}) @var{value})
6788 The first operand of this @code{set} must be the special RTL expression
6789 @code{attr}, whose sole operand is a string giving the name of the
6790 attribute being set. @var{value} is the value of the attribute.
6793 The following shows three different ways of representing the same
6794 attribute value specification:
6797 (set_attr "type" "load,store,arith")
6799 (set_attr_alternative "type"
6800 [(const_string "load") (const_string "store")
6801 (const_string "arith")])
6804 (cond [(eq_attr "alternative" "1") (const_string "load")
6805 (eq_attr "alternative" "2") (const_string "store")]
6806 (const_string "arith")))
6810 @findex define_asm_attributes
6811 The @code{define_asm_attributes} expression provides a mechanism to
6812 specify the attributes assigned to insns produced from an @code{asm}
6813 statement. It has the form:
6816 (define_asm_attributes [@var{attr-sets}])
6820 where @var{attr-sets} is specified the same as for both the
6821 @code{define_insn} and the @code{define_peephole} expressions.
6823 These values will typically be the ``worst case'' attribute values. For
6824 example, they might indicate that the condition code will be clobbered.
6826 A specification for a @code{length} attribute is handled specially. The
6827 way to compute the length of an @code{asm} insn is to multiply the
6828 length specified in the expression @code{define_asm_attributes} by the
6829 number of machine instructions specified in the @code{asm} statement,
6830 determined by counting the number of semicolons and newlines in the
6831 string. Therefore, the value of the @code{length} attribute specified
6832 in a @code{define_asm_attributes} should be the maximum possible length
6833 of a single machine instruction.
6838 @subsection Example of Attribute Specifications
6839 @cindex attribute specifications example
6840 @cindex attribute specifications
6842 The judicious use of defaulting is important in the efficient use of
6843 insn attributes. Typically, insns are divided into @dfn{types} and an
6844 attribute, customarily called @code{type}, is used to represent this
6845 value. This attribute is normally used only to define the default value
6846 for other attributes. An example will clarify this usage.
6848 Assume we have a RISC machine with a condition code and in which only
6849 full-word operations are performed in registers. Let us assume that we
6850 can divide all insns into loads, stores, (integer) arithmetic
6851 operations, floating point operations, and branches.
6853 Here we will concern ourselves with determining the effect of an insn on
6854 the condition code and will limit ourselves to the following possible
6855 effects: The condition code can be set unpredictably (clobbered), not
6856 be changed, be set to agree with the results of the operation, or only
6857 changed if the item previously set into the condition code has been
6860 Here is part of a sample @file{md} file for such a machine:
6863 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
6865 (define_attr "cc" "clobber,unchanged,set,change0"
6866 (cond [(eq_attr "type" "load")
6867 (const_string "change0")
6868 (eq_attr "type" "store,branch")
6869 (const_string "unchanged")
6870 (eq_attr "type" "arith")
6871 (if_then_else (match_operand:SI 0 "" "")
6872 (const_string "set")
6873 (const_string "clobber"))]
6874 (const_string "clobber")))
6877 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
6878 (match_operand:SI 1 "general_operand" "r,m,r"))]
6884 [(set_attr "type" "arith,load,store")])
6887 Note that we assume in the above example that arithmetic operations
6888 performed on quantities smaller than a machine word clobber the condition
6889 code since they will set the condition code to a value corresponding to the
6895 @subsection Computing the Length of an Insn
6896 @cindex insn lengths, computing
6897 @cindex computing the length of an insn
6899 For many machines, multiple types of branch instructions are provided, each
6900 for different length branch displacements. In most cases, the assembler
6901 will choose the correct instruction to use. However, when the assembler
6902 cannot do so, GCC can when a special attribute, the @code{length}
6903 attribute, is defined. This attribute must be defined to have numeric
6904 values by specifying a null string in its @code{define_attr}.
6906 In the case of the @code{length} attribute, two additional forms of
6907 arithmetic terms are allowed in test expressions:
6910 @cindex @code{match_dup} and attributes
6911 @item (match_dup @var{n})
6912 This refers to the address of operand @var{n} of the current insn, which
6913 must be a @code{label_ref}.
6915 @cindex @code{pc} and attributes
6917 This refers to the address of the @emph{current} insn. It might have
6918 been more consistent with other usage to make this the address of the
6919 @emph{next} insn but this would be confusing because the length of the
6920 current insn is to be computed.
6923 @cindex @code{addr_vec}, length of
6924 @cindex @code{addr_diff_vec}, length of
6925 For normal insns, the length will be determined by value of the
6926 @code{length} attribute. In the case of @code{addr_vec} and
6927 @code{addr_diff_vec} insn patterns, the length is computed as
6928 the number of vectors multiplied by the size of each vector.
6930 Lengths are measured in addressable storage units (bytes).
6932 The following macros can be used to refine the length computation:
6935 @findex ADJUST_INSN_LENGTH
6936 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
6937 If defined, modifies the length assigned to instruction @var{insn} as a
6938 function of the context in which it is used. @var{length} is an lvalue
6939 that contains the initially computed length of the insn and should be
6940 updated with the correct length of the insn.
6942 This macro will normally not be required. A case in which it is
6943 required is the ROMP@. On this machine, the size of an @code{addr_vec}
6944 insn must be increased by two to compensate for the fact that alignment
6948 @findex get_attr_length
6949 The routine that returns @code{get_attr_length} (the value of the
6950 @code{length} attribute) can be used by the output routine to
6951 determine the form of the branch instruction to be written, as the
6952 example below illustrates.
6954 As an example of the specification of variable-length branches, consider
6955 the IBM 360. If we adopt the convention that a register will be set to
6956 the starting address of a function, we can jump to labels within 4k of
6957 the start using a four-byte instruction. Otherwise, we need a six-byte
6958 sequence to load the address from memory and then branch to it.
6960 On such a machine, a pattern for a branch instruction might be specified
6966 (label_ref (match_operand 0 "" "")))]
6969 return (get_attr_length (insn) == 4
6970 ? "b %l0" : "l r15,=a(%l0); br r15");
6972 [(set (attr "length")
6973 (if_then_else (lt (match_dup 0) (const_int 4096))
6980 @node Constant Attributes
6981 @subsection Constant Attributes
6982 @cindex constant attributes
6984 A special form of @code{define_attr}, where the expression for the
6985 default value is a @code{const} expression, indicates an attribute that
6986 is constant for a given run of the compiler. Constant attributes may be
6987 used to specify which variety of processor is used. For example,
6990 (define_attr "cpu" "m88100,m88110,m88000"
6992 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
6993 (symbol_ref "TARGET_88110") (const_string "m88110")]
6994 (const_string "m88000"))))
6996 (define_attr "memory" "fast,slow"
6998 (if_then_else (symbol_ref "TARGET_FAST_MEM")
6999 (const_string "fast")
7000 (const_string "slow"))))
7003 The routine generated for constant attributes has no parameters as it
7004 does not depend on any particular insn. RTL expressions used to define
7005 the value of a constant attribute may use the @code{symbol_ref} form,
7006 but may not use either the @code{match_operand} form or @code{eq_attr}
7007 forms involving insn attributes.
7012 @subsection Delay Slot Scheduling
7013 @cindex delay slots, defining
7015 The insn attribute mechanism can be used to specify the requirements for
7016 delay slots, if any, on a target machine. An instruction is said to
7017 require a @dfn{delay slot} if some instructions that are physically
7018 after the instruction are executed as if they were located before it.
7019 Classic examples are branch and call instructions, which often execute
7020 the following instruction before the branch or call is performed.
7022 On some machines, conditional branch instructions can optionally
7023 @dfn{annul} instructions in the delay slot. This means that the
7024 instruction will not be executed for certain branch outcomes. Both
7025 instructions that annul if the branch is true and instructions that
7026 annul if the branch is false are supported.
7028 Delay slot scheduling differs from instruction scheduling in that
7029 determining whether an instruction needs a delay slot is dependent only
7030 on the type of instruction being generated, not on data flow between the
7031 instructions. See the next section for a discussion of data-dependent
7032 instruction scheduling.
7034 @findex define_delay
7035 The requirement of an insn needing one or more delay slots is indicated
7036 via the @code{define_delay} expression. It has the following form:
7039 (define_delay @var{test}
7040 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
7041 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
7045 @var{test} is an attribute test that indicates whether this
7046 @code{define_delay} applies to a particular insn. If so, the number of
7047 required delay slots is determined by the length of the vector specified
7048 as the second argument. An insn placed in delay slot @var{n} must
7049 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
7050 attribute test that specifies which insns may be annulled if the branch
7051 is true. Similarly, @var{annul-false-n} specifies which insns in the
7052 delay slot may be annulled if the branch is false. If annulling is not
7053 supported for that delay slot, @code{(nil)} should be coded.
7055 For example, in the common case where branch and call insns require
7056 a single delay slot, which may contain any insn other than a branch or
7057 call, the following would be placed in the @file{md} file:
7060 (define_delay (eq_attr "type" "branch,call")
7061 [(eq_attr "type" "!branch,call") (nil) (nil)])
7064 Multiple @code{define_delay} expressions may be specified. In this
7065 case, each such expression specifies different delay slot requirements
7066 and there must be no insn for which tests in two @code{define_delay}
7067 expressions are both true.
7069 For example, if we have a machine that requires one delay slot for branches
7070 but two for calls, no delay slot can contain a branch or call insn,
7071 and any valid insn in the delay slot for the branch can be annulled if the
7072 branch is true, we might represent this as follows:
7075 (define_delay (eq_attr "type" "branch")
7076 [(eq_attr "type" "!branch,call")
7077 (eq_attr "type" "!branch,call")
7080 (define_delay (eq_attr "type" "call")
7081 [(eq_attr "type" "!branch,call") (nil) (nil)
7082 (eq_attr "type" "!branch,call") (nil) (nil)])
7084 @c the above is *still* too long. --mew 4feb93
7088 @node Processor pipeline description
7089 @subsection Specifying processor pipeline description
7090 @cindex processor pipeline description
7091 @cindex processor functional units
7092 @cindex instruction latency time
7093 @cindex interlock delays
7094 @cindex data dependence delays
7095 @cindex reservation delays
7096 @cindex pipeline hazard recognizer
7097 @cindex automaton based pipeline description
7098 @cindex regular expressions
7099 @cindex deterministic finite state automaton
7100 @cindex automaton based scheduler
7104 To achieve better performance, most modern processors
7105 (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW}
7106 processors) have many @dfn{functional units} on which several
7107 instructions can be executed simultaneously. An instruction starts
7108 execution if its issue conditions are satisfied. If not, the
7109 instruction is stalled until its conditions are satisfied. Such
7110 @dfn{interlock (pipeline) delay} causes interruption of the fetching
7111 of successor instructions (or demands nop instructions, e.g.@: for some
7114 There are two major kinds of interlock delays in modern processors.
7115 The first one is a data dependence delay determining @dfn{instruction
7116 latency time}. The instruction execution is not started until all
7117 source data have been evaluated by prior instructions (there are more
7118 complex cases when the instruction execution starts even when the data
7119 are not available but will be ready in given time after the
7120 instruction execution start). Taking the data dependence delays into
7121 account is simple. The data dependence (true, output, and
7122 anti-dependence) delay between two instructions is given by a
7123 constant. In most cases this approach is adequate. The second kind
7124 of interlock delays is a reservation delay. The reservation delay
7125 means that two instructions under execution will be in need of shared
7126 processors resources, i.e.@: buses, internal registers, and/or
7127 functional units, which are reserved for some time. Taking this kind
7128 of delay into account is complex especially for modern @acronym{RISC}
7131 The task of exploiting more processor parallelism is solved by an
7132 instruction scheduler. For a better solution to this problem, the
7133 instruction scheduler has to have an adequate description of the
7134 processor parallelism (or @dfn{pipeline description}). GCC
7135 machine descriptions describe processor parallelism and functional
7136 unit reservations for groups of instructions with the aid of
7137 @dfn{regular expressions}.
7139 The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to
7140 figure out the possibility of the instruction issue by the processor
7141 on a given simulated processor cycle. The pipeline hazard recognizer is
7142 automatically generated from the processor pipeline description. The
7143 pipeline hazard recognizer generated from the machine description
7144 is based on a deterministic finite state automaton (@acronym{DFA}):
7145 the instruction issue is possible if there is a transition from one
7146 automaton state to another one. This algorithm is very fast, and
7147 furthermore, its speed is not dependent on processor
7148 complexity@footnote{However, the size of the automaton depends on
7149 processor complexity. To limit this effect, machine descriptions
7150 can split orthogonal parts of the machine description among several
7151 automata: but then, since each of these must be stepped independently,
7152 this does cause a small decrease in the algorithm's performance.}.
7154 @cindex automaton based pipeline description
7155 The rest of this section describes the directives that constitute
7156 an automaton-based processor pipeline description. The order of
7157 these constructions within the machine description file is not
7160 @findex define_automaton
7161 @cindex pipeline hazard recognizer
7162 The following optional construction describes names of automata
7163 generated and used for the pipeline hazards recognition. Sometimes
7164 the generated finite state automaton used by the pipeline hazard
7165 recognizer is large. If we use more than one automaton and bind functional
7166 units to the automata, the total size of the automata is usually
7167 less than the size of the single automaton. If there is no one such
7168 construction, only one finite state automaton is generated.
7171 (define_automaton @var{automata-names})
7174 @var{automata-names} is a string giving names of the automata. The
7175 names are separated by commas. All the automata should have unique names.
7176 The automaton name is used in the constructions @code{define_cpu_unit} and
7177 @code{define_query_cpu_unit}.
7179 @findex define_cpu_unit
7180 @cindex processor functional units
7181 Each processor functional unit used in the description of instruction
7182 reservations should be described by the following construction.
7185 (define_cpu_unit @var{unit-names} [@var{automaton-name}])
7188 @var{unit-names} is a string giving the names of the functional units
7189 separated by commas. Don't use name @samp{nothing}, it is reserved
7192 @var{automaton-name} is a string giving the name of the automaton with
7193 which the unit is bound. The automaton should be described in
7194 construction @code{define_automaton}. You should give
7195 @dfn{automaton-name}, if there is a defined automaton.
7197 The assignment of units to automata are constrained by the uses of the
7198 units in insn reservations. The most important constraint is: if a
7199 unit reservation is present on a particular cycle of an alternative
7200 for an insn reservation, then some unit from the same automaton must
7201 be present on the same cycle for the other alternatives of the insn
7202 reservation. The rest of the constraints are mentioned in the
7203 description of the subsequent constructions.
7205 @findex define_query_cpu_unit
7206 @cindex querying function unit reservations
7207 The following construction describes CPU functional units analogously
7208 to @code{define_cpu_unit}. The reservation of such units can be
7209 queried for an automaton state. The instruction scheduler never
7210 queries reservation of functional units for given automaton state. So
7211 as a rule, you don't need this construction. This construction could
7212 be used for future code generation goals (e.g.@: to generate
7213 @acronym{VLIW} insn templates).
7216 (define_query_cpu_unit @var{unit-names} [@var{automaton-name}])
7219 @var{unit-names} is a string giving names of the functional units
7220 separated by commas.
7222 @var{automaton-name} is a string giving the name of the automaton with
7223 which the unit is bound.
7225 @findex define_insn_reservation
7226 @cindex instruction latency time
7227 @cindex regular expressions
7229 The following construction is the major one to describe pipeline
7230 characteristics of an instruction.
7233 (define_insn_reservation @var{insn-name} @var{default_latency}
7234 @var{condition} @var{regexp})
7237 @var{default_latency} is a number giving latency time of the
7238 instruction. There is an important difference between the old
7239 description and the automaton based pipeline description. The latency
7240 time is used for all dependencies when we use the old description. In
7241 the automaton based pipeline description, the given latency time is only
7242 used for true dependencies. The cost of anti-dependencies is always
7243 zero and the cost of output dependencies is the difference between
7244 latency times of the producing and consuming insns (if the difference
7245 is negative, the cost is considered to be zero). You can always
7246 change the default costs for any description by using the target hook
7247 @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}).
7249 @var{insn-name} is a string giving the internal name of the insn. The
7250 internal names are used in constructions @code{define_bypass} and in
7251 the automaton description file generated for debugging. The internal
7252 name has nothing in common with the names in @code{define_insn}. It is a
7253 good practice to use insn classes described in the processor manual.
7255 @var{condition} defines what RTL insns are described by this
7256 construction. You should remember that you will be in trouble if
7257 @var{condition} for two or more different
7258 @code{define_insn_reservation} constructions is TRUE for an insn. In
7259 this case what reservation will be used for the insn is not defined.
7260 Such cases are not checked during generation of the pipeline hazards
7261 recognizer because in general recognizing that two conditions may have
7262 the same value is quite difficult (especially if the conditions
7263 contain @code{symbol_ref}). It is also not checked during the
7264 pipeline hazard recognizer work because it would slow down the
7265 recognizer considerably.
7267 @var{regexp} is a string describing the reservation of the cpu's functional
7268 units by the instruction. The reservations are described by a regular
7269 expression according to the following syntax:
7272 regexp = regexp "," oneof
7275 oneof = oneof "|" allof
7278 allof = allof "+" repeat
7281 repeat = element "*" number
7284 element = cpu_function_unit_name
7293 @samp{,} is used for describing the start of the next cycle in
7297 @samp{|} is used for describing a reservation described by the first
7298 regular expression @strong{or} a reservation described by the second
7299 regular expression @strong{or} etc.
7302 @samp{+} is used for describing a reservation described by the first
7303 regular expression @strong{and} a reservation described by the
7304 second regular expression @strong{and} etc.
7307 @samp{*} is used for convenience and simply means a sequence in which
7308 the regular expression are repeated @var{number} times with cycle
7309 advancing (see @samp{,}).
7312 @samp{cpu_function_unit_name} denotes reservation of the named
7316 @samp{reservation_name} --- see description of construction
7317 @samp{define_reservation}.
7320 @samp{nothing} denotes no unit reservations.
7323 @findex define_reservation
7324 Sometimes unit reservations for different insns contain common parts.
7325 In such case, you can simplify the pipeline description by describing
7326 the common part by the following construction
7329 (define_reservation @var{reservation-name} @var{regexp})
7332 @var{reservation-name} is a string giving name of @var{regexp}.
7333 Functional unit names and reservation names are in the same name
7334 space. So the reservation names should be different from the
7335 functional unit names and can not be the reserved name @samp{nothing}.
7337 @findex define_bypass
7338 @cindex instruction latency time
7340 The following construction is used to describe exceptions in the
7341 latency time for given instruction pair. This is so called bypasses.
7344 (define_bypass @var{number} @var{out_insn_names} @var{in_insn_names}
7348 @var{number} defines when the result generated by the instructions
7349 given in string @var{out_insn_names} will be ready for the
7350 instructions given in string @var{in_insn_names}. The instructions in
7351 the string are separated by commas.
7353 @var{guard} is an optional string giving the name of a C function which
7354 defines an additional guard for the bypass. The function will get the
7355 two insns as parameters. If the function returns zero the bypass will
7356 be ignored for this case. The additional guard is necessary to
7357 recognize complicated bypasses, e.g.@: when the consumer is only an address
7358 of insn @samp{store} (not a stored value).
7360 If there are more one bypass with the same output and input insns, the
7361 chosen bypass is the first bypass with a guard in description whose
7362 guard function returns nonzero. If there is no such bypass, then
7363 bypass without the guard function is chosen.
7365 @findex exclusion_set
7366 @findex presence_set
7367 @findex final_presence_set
7369 @findex final_absence_set
7372 The following five constructions are usually used to describe
7373 @acronym{VLIW} processors, or more precisely, to describe a placement
7374 of small instructions into @acronym{VLIW} instruction slots. They
7375 can be used for @acronym{RISC} processors, too.
7378 (exclusion_set @var{unit-names} @var{unit-names})
7379 (presence_set @var{unit-names} @var{patterns})
7380 (final_presence_set @var{unit-names} @var{patterns})
7381 (absence_set @var{unit-names} @var{patterns})
7382 (final_absence_set @var{unit-names} @var{patterns})
7385 @var{unit-names} is a string giving names of functional units
7386 separated by commas.
7388 @var{patterns} is a string giving patterns of functional units
7389 separated by comma. Currently pattern is one unit or units
7390 separated by white-spaces.
7392 The first construction (@samp{exclusion_set}) means that each
7393 functional unit in the first string can not be reserved simultaneously
7394 with a unit whose name is in the second string and vice versa. For
7395 example, the construction is useful for describing processors
7396 (e.g.@: some SPARC processors) with a fully pipelined floating point
7397 functional unit which can execute simultaneously only single floating
7398 point insns or only double floating point insns.
7400 The second construction (@samp{presence_set}) means that each
7401 functional unit in the first string can not be reserved unless at
7402 least one of pattern of units whose names are in the second string is
7403 reserved. This is an asymmetric relation. For example, it is useful
7404 for description that @acronym{VLIW} @samp{slot1} is reserved after
7405 @samp{slot0} reservation. We could describe it by the following
7409 (presence_set "slot1" "slot0")
7412 Or @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0}
7413 reservation. In this case we could write
7416 (presence_set "slot1" "slot0 b0")
7419 The third construction (@samp{final_presence_set}) is analogous to
7420 @samp{presence_set}. The difference between them is when checking is
7421 done. When an instruction is issued in given automaton state
7422 reflecting all current and planned unit reservations, the automaton
7423 state is changed. The first state is a source state, the second one
7424 is a result state. Checking for @samp{presence_set} is done on the
7425 source state reservation, checking for @samp{final_presence_set} is
7426 done on the result reservation. This construction is useful to
7427 describe a reservation which is actually two subsequent reservations.
7428 For example, if we use
7431 (presence_set "slot1" "slot0")
7434 the following insn will be never issued (because @samp{slot1} requires
7435 @samp{slot0} which is absent in the source state).
7438 (define_reservation "insn_and_nop" "slot0 + slot1")
7441 but it can be issued if we use analogous @samp{final_presence_set}.
7443 The forth construction (@samp{absence_set}) means that each functional
7444 unit in the first string can be reserved only if each pattern of units
7445 whose names are in the second string is not reserved. This is an
7446 asymmetric relation (actually @samp{exclusion_set} is analogous to
7447 this one but it is symmetric). For example it might be useful in a
7448 @acronym{VLIW} description to say that @samp{slot0} cannot be reserved
7449 after either @samp{slot1} or @samp{slot2} have been reserved. This
7450 can be described as:
7453 (absence_set "slot0" "slot1, slot2")
7456 Or @samp{slot2} can not be reserved if @samp{slot0} and unit @samp{b0}
7457 are reserved or @samp{slot1} and unit @samp{b1} are reserved. In
7458 this case we could write
7461 (absence_set "slot2" "slot0 b0, slot1 b1")
7464 All functional units mentioned in a set should belong to the same
7467 The last construction (@samp{final_absence_set}) is analogous to
7468 @samp{absence_set} but checking is done on the result (state)
7469 reservation. See comments for @samp{final_presence_set}.
7471 @findex automata_option
7472 @cindex deterministic finite state automaton
7473 @cindex nondeterministic finite state automaton
7474 @cindex finite state automaton minimization
7475 You can control the generator of the pipeline hazard recognizer with
7476 the following construction.
7479 (automata_option @var{options})
7482 @var{options} is a string giving options which affect the generated
7483 code. Currently there are the following options:
7487 @dfn{no-minimization} makes no minimization of the automaton. This is
7488 only worth to do when we are debugging the description and need to
7489 look more accurately at reservations of states.
7492 @dfn{time} means printing time statistics about the generation of
7496 @dfn{stats} means printing statistics about the generated automata
7497 such as the number of DFA states, NDFA states and arcs.
7500 @dfn{v} means a generation of the file describing the result automata.
7501 The file has suffix @samp{.dfa} and can be used for the description
7502 verification and debugging.
7505 @dfn{w} means a generation of warning instead of error for
7506 non-critical errors.
7509 @dfn{ndfa} makes nondeterministic finite state automata. This affects
7510 the treatment of operator @samp{|} in the regular expressions. The
7511 usual treatment of the operator is to try the first alternative and,
7512 if the reservation is not possible, the second alternative. The
7513 nondeterministic treatment means trying all alternatives, some of them
7514 may be rejected by reservations in the subsequent insns.
7517 @dfn{progress} means output of a progress bar showing how many states
7518 were generated so far for automaton being processed. This is useful
7519 during debugging a @acronym{DFA} description. If you see too many
7520 generated states, you could interrupt the generator of the pipeline
7521 hazard recognizer and try to figure out a reason for generation of the
7525 As an example, consider a superscalar @acronym{RISC} machine which can
7526 issue three insns (two integer insns and one floating point insn) on
7527 the cycle but can finish only two insns. To describe this, we define
7528 the following functional units.
7531 (define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline")
7532 (define_cpu_unit "port0, port1")
7535 All simple integer insns can be executed in any integer pipeline and
7536 their result is ready in two cycles. The simple integer insns are
7537 issued into the first pipeline unless it is reserved, otherwise they
7538 are issued into the second pipeline. Integer division and
7539 multiplication insns can be executed only in the second integer
7540 pipeline and their results are ready correspondingly in 8 and 4
7541 cycles. The integer division is not pipelined, i.e.@: the subsequent
7542 integer division insn can not be issued until the current division
7543 insn finished. Floating point insns are fully pipelined and their
7544 results are ready in 3 cycles. Where the result of a floating point
7545 insn is used by an integer insn, an additional delay of one cycle is
7546 incurred. To describe all of this we could specify
7549 (define_cpu_unit "div")
7551 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
7552 "(i0_pipeline | i1_pipeline), (port0 | port1)")
7554 (define_insn_reservation "mult" 4 (eq_attr "type" "mult")
7555 "i1_pipeline, nothing*2, (port0 | port1)")
7557 (define_insn_reservation "div" 8 (eq_attr "type" "div")
7558 "i1_pipeline, div*7, div + (port0 | port1)")
7560 (define_insn_reservation "float" 3 (eq_attr "type" "float")
7561 "f_pipeline, nothing, (port0 | port1))
7563 (define_bypass 4 "float" "simple,mult,div")
7566 To simplify the description we could describe the following reservation
7569 (define_reservation "finish" "port0|port1")
7572 and use it in all @code{define_insn_reservation} as in the following
7576 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
7577 "(i0_pipeline | i1_pipeline), finish")
7583 @node Conditional Execution
7584 @section Conditional Execution
7585 @cindex conditional execution
7588 A number of architectures provide for some form of conditional
7589 execution, or predication. The hallmark of this feature is the
7590 ability to nullify most of the instructions in the instruction set.
7591 When the instruction set is large and not entirely symmetric, it
7592 can be quite tedious to describe these forms directly in the
7593 @file{.md} file. An alternative is the @code{define_cond_exec} template.
7595 @findex define_cond_exec
7598 [@var{predicate-pattern}]
7600 "@var{output-template}")
7603 @var{predicate-pattern} is the condition that must be true for the
7604 insn to be executed at runtime and should match a relational operator.
7605 One can use @code{match_operator} to match several relational operators
7606 at once. Any @code{match_operand} operands must have no more than one
7609 @var{condition} is a C expression that must be true for the generated
7612 @findex current_insn_predicate
7613 @var{output-template} is a string similar to the @code{define_insn}
7614 output template (@pxref{Output Template}), except that the @samp{*}
7615 and @samp{@@} special cases do not apply. This is only useful if the
7616 assembly text for the predicate is a simple prefix to the main insn.
7617 In order to handle the general case, there is a global variable
7618 @code{current_insn_predicate} that will contain the entire predicate
7619 if the current insn is predicated, and will otherwise be @code{NULL}.
7621 When @code{define_cond_exec} is used, an implicit reference to
7622 the @code{predicable} instruction attribute is made.
7623 @xref{Insn Attributes}. This attribute must be boolean (i.e.@: have
7624 exactly two elements in its @var{list-of-values}). Further, it must
7625 not be used with complex expressions. That is, the default and all
7626 uses in the insns must be a simple constant, not dependent on the
7627 alternative or anything else.
7629 For each @code{define_insn} for which the @code{predicable}
7630 attribute is true, a new @code{define_insn} pattern will be
7631 generated that matches a predicated version of the instruction.
7635 (define_insn "addsi"
7636 [(set (match_operand:SI 0 "register_operand" "r")
7637 (plus:SI (match_operand:SI 1 "register_operand" "r")
7638 (match_operand:SI 2 "register_operand" "r")))]
7643 [(ne (match_operand:CC 0 "register_operand" "c")
7650 generates a new pattern
7655 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
7656 (set (match_operand:SI 0 "register_operand" "r")
7657 (plus:SI (match_operand:SI 1 "register_operand" "r")
7658 (match_operand:SI 2 "register_operand" "r"))))]
7659 "(@var{test2}) && (@var{test1})"
7660 "(%3) add %2,%1,%0")
7665 @node Constant Definitions
7666 @section Constant Definitions
7667 @cindex constant definitions
7668 @findex define_constants
7670 Using literal constants inside instruction patterns reduces legibility and
7671 can be a maintenance problem.
7673 To overcome this problem, you may use the @code{define_constants}
7674 expression. It contains a vector of name-value pairs. From that
7675 point on, wherever any of the names appears in the MD file, it is as
7676 if the corresponding value had been written instead. You may use
7677 @code{define_constants} multiple times; each appearance adds more
7678 constants to the table. It is an error to redefine a constant with
7681 To come back to the a29k load multiple example, instead of
7685 [(match_parallel 0 "load_multiple_operation"
7686 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
7687 (match_operand:SI 2 "memory_operand" "m"))
7689 (clobber (reg:SI 179))])]
7705 [(match_parallel 0 "load_multiple_operation"
7706 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
7707 (match_operand:SI 2 "memory_operand" "m"))
7709 (clobber (reg:SI R_CR))])]
7714 The constants that are defined with a define_constant are also output
7715 in the insn-codes.h header file as #defines.
7720 @cindex iterators in @file{.md} files
7722 Ports often need to define similar patterns for more than one machine
7723 mode or for more than one rtx code. GCC provides some simple iterator
7724 facilities to make this process easier.
7727 * Mode Iterators:: Generating variations of patterns for different modes.
7728 * Code Iterators:: Doing the same for codes.
7731 @node Mode Iterators
7732 @subsection Mode Iterators
7733 @cindex mode iterators in @file{.md} files
7735 Ports often need to define similar patterns for two or more different modes.
7740 If a processor has hardware support for both single and double
7741 floating-point arithmetic, the @code{SFmode} patterns tend to be
7742 very similar to the @code{DFmode} ones.
7745 If a port uses @code{SImode} pointers in one configuration and
7746 @code{DImode} pointers in another, it will usually have very similar
7747 @code{SImode} and @code{DImode} patterns for manipulating pointers.
7750 Mode iterators allow several patterns to be instantiated from one
7751 @file{.md} file template. They can be used with any type of
7752 rtx-based construct, such as a @code{define_insn},
7753 @code{define_split}, or @code{define_peephole2}.
7756 * Defining Mode Iterators:: Defining a new mode iterator.
7757 * Substitutions:: Combining mode iterators with substitutions
7758 * Examples:: Examples
7761 @node Defining Mode Iterators
7762 @subsubsection Defining Mode Iterators
7763 @findex define_mode_iterator
7765 The syntax for defining a mode iterator is:
7768 (define_mode_iterator @var{name} [(@var{mode1} "@var{cond1}") @dots{} (@var{moden} "@var{condn}")])
7771 This allows subsequent @file{.md} file constructs to use the mode suffix
7772 @code{:@var{name}}. Every construct that does so will be expanded
7773 @var{n} times, once with every use of @code{:@var{name}} replaced by
7774 @code{:@var{mode1}}, once with every use replaced by @code{:@var{mode2}},
7775 and so on. In the expansion for a particular @var{modei}, every
7776 C condition will also require that @var{condi} be true.
7781 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
7784 defines a new mode suffix @code{:P}. Every construct that uses
7785 @code{:P} will be expanded twice, once with every @code{:P} replaced
7786 by @code{:SI} and once with every @code{:P} replaced by @code{:DI}.
7787 The @code{:SI} version will only apply if @code{Pmode == SImode} and
7788 the @code{:DI} version will only apply if @code{Pmode == DImode}.
7790 As with other @file{.md} conditions, an empty string is treated
7791 as ``always true''. @code{(@var{mode} "")} can also be abbreviated
7792 to @code{@var{mode}}. For example:
7795 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
7798 means that the @code{:DI} expansion only applies if @code{TARGET_64BIT}
7799 but that the @code{:SI} expansion has no such constraint.
7801 Iterators are applied in the order they are defined. This can be
7802 significant if two iterators are used in a construct that requires
7803 substitutions. @xref{Substitutions}.
7806 @subsubsection Substitution in Mode Iterators
7807 @findex define_mode_attr
7809 If an @file{.md} file construct uses mode iterators, each version of the
7810 construct will often need slightly different strings or modes. For
7815 When a @code{define_expand} defines several @code{add@var{m}3} patterns
7816 (@pxref{Standard Names}), each expander will need to use the
7817 appropriate mode name for @var{m}.
7820 When a @code{define_insn} defines several instruction patterns,
7821 each instruction will often use a different assembler mnemonic.
7824 When a @code{define_insn} requires operands with different modes,
7825 using an iterator for one of the operand modes usually requires a specific
7826 mode for the other operand(s).
7829 GCC supports such variations through a system of ``mode attributes''.
7830 There are two standard attributes: @code{mode}, which is the name of
7831 the mode in lower case, and @code{MODE}, which is the same thing in
7832 upper case. You can define other attributes using:
7835 (define_mode_attr @var{name} [(@var{mode1} "@var{value1}") @dots{} (@var{moden} "@var{valuen}")])
7838 where @var{name} is the name of the attribute and @var{valuei}
7839 is the value associated with @var{modei}.
7841 When GCC replaces some @var{:iterator} with @var{:mode}, it will scan
7842 each string and mode in the pattern for sequences of the form
7843 @code{<@var{iterator}:@var{attr}>}, where @var{attr} is the name of a
7844 mode attribute. If the attribute is defined for @var{mode}, the whole
7845 @code{<@dots{}>} sequence will be replaced by the appropriate attribute
7848 For example, suppose an @file{.md} file has:
7851 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
7852 (define_mode_attr load [(SI "lw") (DI "ld")])
7855 If one of the patterns that uses @code{:P} contains the string
7856 @code{"<P:load>\t%0,%1"}, the @code{SI} version of that pattern
7857 will use @code{"lw\t%0,%1"} and the @code{DI} version will use
7860 Here is an example of using an attribute for a mode:
7863 (define_mode_iterator LONG [SI DI])
7864 (define_mode_attr SHORT [(SI "HI") (DI "SI")])
7865 (define_insn @dots{}
7866 (sign_extend:LONG (match_operand:<LONG:SHORT> @dots{})) @dots{})
7869 The @code{@var{iterator}:} prefix may be omitted, in which case the
7870 substitution will be attempted for every iterator expansion.
7873 @subsubsection Mode Iterator Examples
7875 Here is an example from the MIPS port. It defines the following
7876 modes and attributes (among others):
7879 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
7880 (define_mode_attr d [(SI "") (DI "d")])
7883 and uses the following template to define both @code{subsi3}
7887 (define_insn "sub<mode>3"
7888 [(set (match_operand:GPR 0 "register_operand" "=d")
7889 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
7890 (match_operand:GPR 2 "register_operand" "d")))]
7893 [(set_attr "type" "arith")
7894 (set_attr "mode" "<MODE>")])
7897 This is exactly equivalent to:
7900 (define_insn "subsi3"
7901 [(set (match_operand:SI 0 "register_operand" "=d")
7902 (minus:SI (match_operand:SI 1 "register_operand" "d")
7903 (match_operand:SI 2 "register_operand" "d")))]
7906 [(set_attr "type" "arith")
7907 (set_attr "mode" "SI")])
7909 (define_insn "subdi3"
7910 [(set (match_operand:DI 0 "register_operand" "=d")
7911 (minus:DI (match_operand:DI 1 "register_operand" "d")
7912 (match_operand:DI 2 "register_operand" "d")))]
7915 [(set_attr "type" "arith")
7916 (set_attr "mode" "DI")])
7919 @node Code Iterators
7920 @subsection Code Iterators
7921 @cindex code iterators in @file{.md} files
7922 @findex define_code_iterator
7923 @findex define_code_attr
7925 Code iterators operate in a similar way to mode iterators. @xref{Mode Iterators}.
7930 (define_code_iterator @var{name} [(@var{code1} "@var{cond1}") @dots{} (@var{coden} "@var{condn}")])
7933 defines a pseudo rtx code @var{name} that can be instantiated as
7934 @var{codei} if condition @var{condi} is true. Each @var{codei}
7935 must have the same rtx format. @xref{RTL Classes}.
7937 As with mode iterators, each pattern that uses @var{name} will be
7938 expanded @var{n} times, once with all uses of @var{name} replaced by
7939 @var{code1}, once with all uses replaced by @var{code2}, and so on.
7940 @xref{Defining Mode Iterators}.
7942 It is possible to define attributes for codes as well as for modes.
7943 There are two standard code attributes: @code{code}, the name of the
7944 code in lower case, and @code{CODE}, the name of the code in upper case.
7945 Other attributes are defined using:
7948 (define_code_attr @var{name} [(@var{code1} "@var{value1}") @dots{} (@var{coden} "@var{valuen}")])
7951 Here's an example of code iterators in action, taken from the MIPS port:
7954 (define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
7955 eq ne gt ge lt le gtu geu ltu leu])
7957 (define_expand "b<code>"
7959 (if_then_else (any_cond:CC (cc0)
7961 (label_ref (match_operand 0 ""))
7965 gen_conditional_branch (operands, <CODE>);
7970 This is equivalent to:
7973 (define_expand "bunordered"
7975 (if_then_else (unordered:CC (cc0)
7977 (label_ref (match_operand 0 ""))
7981 gen_conditional_branch (operands, UNORDERED);
7985 (define_expand "bordered"
7987 (if_then_else (ordered:CC (cc0)
7989 (label_ref (match_operand 0 ""))
7993 gen_conditional_branch (operands, ORDERED);