1 ;; GCC machine description for Tensilica's Xtensa architecture.
2 ;; Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
40 ;; This code iterator allows signed and unsigned widening multiplications
41 ;; to use the same template.
42 (define_code_iterator any_extend [sign_extend zero_extend])
44 ;; <u> expands to an empty string when doing a signed operation and
45 ;; "u" when doing an unsigned operation.
46 (define_code_attr u [(sign_extend "") (zero_extend "u")])
48 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
49 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
51 ;; This code iterator allows four integer min/max operations to be
52 ;; generated from one template.
53 (define_code_iterator any_minmax [smin umin smax umax])
55 ;; <minmax> expands to the opcode name for any_minmax operations.
56 (define_code_attr minmax [(smin "min") (umin "minu")
57 (smax "max") (umax "maxu")])
59 ;; This code iterator allows all branch instructions to be generated from
60 ;; a single define_expand template.
61 (define_code_iterator any_cond [eq ne gt ge lt le gtu geu ltu leu])
63 ;; This code iterator is for setting a register from a comparison.
64 (define_code_iterator any_scc [eq ne gt ge lt le])
66 ;; This code iterator is for floating-point comparisons.
67 (define_code_iterator any_scc_sf [eq lt le])
69 ;; This iterator and attribute allow to combine most atomic operations.
70 (define_code_iterator ATOMIC [and ior xor plus minus mult])
71 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
72 (plus "add") (minus "sub") (mult "nand")])
74 ;; This mode iterator allows the HI and QI patterns to be defined from
76 (define_mode_iterator HQI [HI QI])
82 "unknown,jump,call,load,store,move,arith,multi,nop,farith,fmadd,fdiv,fsqrt,fconv,fload,fstore,mul16,mul32,div32,mac16,rsr,wsr,entry"
83 (const_string "unknown"))
86 "unknown,none,QI,HI,SI,DI,SF,DF,BL"
87 (const_string "unknown"))
89 (define_attr "length" "" (const_int 1))
91 ;; Describe a user's asm statement.
92 (define_asm_attributes
93 [(set_attr "type" "multi")])
98 ;; The Xtensa basically has simple 5-stage RISC pipeline.
99 ;; Most instructions complete in 1 cycle, and it is OK to assume that
100 ;; everything is fully pipelined. The exceptions have special insn
101 ;; reservations in the pipeline description below. The Xtensa can
102 ;; issue one instruction per cycle, so defining CPU units is unnecessary.
104 (define_insn_reservation "xtensa_any_insn" 1
105 (eq_attr "type" "!load,fload,rsr,mul16,mul32,fmadd,fconv")
108 (define_insn_reservation "xtensa_memory" 2
109 (eq_attr "type" "load,fload")
112 (define_insn_reservation "xtensa_sreg" 2
113 (eq_attr "type" "rsr")
116 (define_insn_reservation "xtensa_mul16" 2
117 (eq_attr "type" "mul16")
120 (define_insn_reservation "xtensa_mul32" 2
121 (eq_attr "type" "mul32")
124 (define_insn_reservation "xtensa_fmadd" 4
125 (eq_attr "type" "fmadd")
128 (define_insn_reservation "xtensa_fconv" 2
129 (eq_attr "type" "fconv")
132 ;; Include predicates and constraints.
134 (include "predicates.md")
135 (include "constraints.md")
140 (define_insn "addsi3"
141 [(set (match_operand:SI 0 "register_operand" "=D,D,a,a,a")
142 (plus:SI (match_operand:SI 1 "register_operand" "%d,d,r,r,r")
143 (match_operand:SI 2 "add_operand" "d,O,r,J,N")))]
151 [(set_attr "type" "arith,arith,arith,arith,arith")
152 (set_attr "mode" "SI")
153 (set_attr "length" "2,2,3,3,3")])
156 [(set (match_operand:SI 0 "register_operand" "=a")
157 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
158 (match_operand:SI 3 "addsubx_operand" "i"))
159 (match_operand:SI 2 "register_operand" "r")))]
162 [(set_attr "type" "arith")
163 (set_attr "mode" "SI")
164 (set_attr "length" "3")])
166 (define_insn "addsf3"
167 [(set (match_operand:SF 0 "register_operand" "=f")
168 (plus:SF (match_operand:SF 1 "register_operand" "%f")
169 (match_operand:SF 2 "register_operand" "f")))]
172 [(set_attr "type" "fmadd")
173 (set_attr "mode" "SF")
174 (set_attr "length" "3")])
179 (define_insn "subsi3"
180 [(set (match_operand:SI 0 "register_operand" "=a")
181 (minus:SI (match_operand:SI 1 "register_operand" "r")
182 (match_operand:SI 2 "register_operand" "r")))]
185 [(set_attr "type" "arith")
186 (set_attr "mode" "SI")
187 (set_attr "length" "3")])
190 [(set (match_operand:SI 0 "register_operand" "=a")
191 (minus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
192 (match_operand:SI 3 "addsubx_operand" "i"))
193 (match_operand:SI 2 "register_operand" "r")))]
196 [(set_attr "type" "arith")
197 (set_attr "mode" "SI")
198 (set_attr "length" "3")])
200 (define_insn "subsf3"
201 [(set (match_operand:SF 0 "register_operand" "=f")
202 (minus:SF (match_operand:SF 1 "register_operand" "f")
203 (match_operand:SF 2 "register_operand" "f")))]
206 [(set_attr "type" "fmadd")
207 (set_attr "mode" "SF")
208 (set_attr "length" "3")])
213 (define_expand "<u>mulsidi3"
214 [(set (match_operand:DI 0 "register_operand")
215 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
216 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
219 emit_insn (gen_mulsi3 (gen_lowpart (SImode, operands[0]),
220 operands[1], operands[2]));
221 emit_insn (gen_<u>mulsi3_highpart (gen_highpart (SImode, operands[0]),
222 operands[1], operands[2]));
226 (define_insn "<u>mulsi3_highpart"
227 [(set (match_operand:SI 0 "register_operand" "=a")
230 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "%r"))
231 (any_extend:DI (match_operand:SI 2 "register_operand" "r")))
234 "mul<su>h\t%0, %1, %2"
235 [(set_attr "type" "mul32")
236 (set_attr "mode" "SI")
237 (set_attr "length" "3")])
239 (define_insn "mulsi3"
240 [(set (match_operand:SI 0 "register_operand" "=a")
241 (mult:SI (match_operand:SI 1 "register_operand" "%r")
242 (match_operand:SI 2 "register_operand" "r")))]
245 [(set_attr "type" "mul32")
246 (set_attr "mode" "SI")
247 (set_attr "length" "3")])
249 (define_insn "mulhisi3"
250 [(set (match_operand:SI 0 "register_operand" "=C,A")
251 (mult:SI (sign_extend:SI
252 (match_operand:HI 1 "register_operand" "%r,r"))
254 (match_operand:HI 2 "register_operand" "r,r"))))]
255 "TARGET_MUL16 || TARGET_MAC16"
259 [(set_attr "type" "mul16,mac16")
260 (set_attr "mode" "SI")
261 (set_attr "length" "3,3")])
263 (define_insn "umulhisi3"
264 [(set (match_operand:SI 0 "register_operand" "=C,A")
265 (mult:SI (zero_extend:SI
266 (match_operand:HI 1 "register_operand" "%r,r"))
268 (match_operand:HI 2 "register_operand" "r,r"))))]
269 "TARGET_MUL16 || TARGET_MAC16"
273 [(set_attr "type" "mul16,mac16")
274 (set_attr "mode" "SI")
275 (set_attr "length" "3,3")])
277 (define_insn "muladdhisi"
278 [(set (match_operand:SI 0 "register_operand" "=A")
279 (plus:SI (mult:SI (sign_extend:SI
280 (match_operand:HI 1 "register_operand" "%r"))
282 (match_operand:HI 2 "register_operand" "r")))
283 (match_operand:SI 3 "register_operand" "0")))]
286 [(set_attr "type" "mac16")
287 (set_attr "mode" "SI")
288 (set_attr "length" "3")])
290 (define_insn "mulsubhisi"
291 [(set (match_operand:SI 0 "register_operand" "=A")
292 (minus:SI (match_operand:SI 1 "register_operand" "0")
293 (mult:SI (sign_extend:SI
294 (match_operand:HI 2 "register_operand" "%r"))
296 (match_operand:HI 3 "register_operand" "r")))))]
299 [(set_attr "type" "mac16")
300 (set_attr "mode" "SI")
301 (set_attr "length" "3")])
303 (define_insn "mulsf3"
304 [(set (match_operand:SF 0 "register_operand" "=f")
305 (mult:SF (match_operand:SF 1 "register_operand" "%f")
306 (match_operand:SF 2 "register_operand" "f")))]
309 [(set_attr "type" "fmadd")
310 (set_attr "mode" "SF")
311 (set_attr "length" "3")])
313 (define_insn "muladdsf3"
314 [(set (match_operand:SF 0 "register_operand" "=f")
315 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%f")
316 (match_operand:SF 2 "register_operand" "f"))
317 (match_operand:SF 3 "register_operand" "0")))]
318 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
320 [(set_attr "type" "fmadd")
321 (set_attr "mode" "SF")
322 (set_attr "length" "3")])
324 (define_insn "mulsubsf3"
325 [(set (match_operand:SF 0 "register_operand" "=f")
326 (minus:SF (match_operand:SF 1 "register_operand" "0")
327 (mult:SF (match_operand:SF 2 "register_operand" "%f")
328 (match_operand:SF 3 "register_operand" "f"))))]
329 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
331 [(set_attr "type" "fmadd")
332 (set_attr "mode" "SF")
333 (set_attr "length" "3")])
338 (define_insn "divsi3"
339 [(set (match_operand:SI 0 "register_operand" "=a")
340 (div:SI (match_operand:SI 1 "register_operand" "r")
341 (match_operand:SI 2 "register_operand" "r")))]
344 [(set_attr "type" "div32")
345 (set_attr "mode" "SI")
346 (set_attr "length" "3")])
348 (define_insn "udivsi3"
349 [(set (match_operand:SI 0 "register_operand" "=a")
350 (udiv:SI (match_operand:SI 1 "register_operand" "r")
351 (match_operand:SI 2 "register_operand" "r")))]
354 [(set_attr "type" "div32")
355 (set_attr "mode" "SI")
356 (set_attr "length" "3")])
358 (define_insn "divsf3"
359 [(set (match_operand:SF 0 "register_operand" "=f")
360 (div:SF (match_operand:SF 1 "register_operand" "f")
361 (match_operand:SF 2 "register_operand" "f")))]
362 "TARGET_HARD_FLOAT_DIV"
364 [(set_attr "type" "fdiv")
365 (set_attr "mode" "SF")
366 (set_attr "length" "3")])
368 (define_insn "*recipsf2"
369 [(set (match_operand:SF 0 "register_operand" "=f")
370 (div:SF (match_operand:SF 1 "const_float_1_operand" "")
371 (match_operand:SF 2 "register_operand" "f")))]
372 "TARGET_HARD_FLOAT_RECIP && flag_unsafe_math_optimizations"
374 [(set_attr "type" "fdiv")
375 (set_attr "mode" "SF")
376 (set_attr "length" "3")])
381 (define_insn "modsi3"
382 [(set (match_operand:SI 0 "register_operand" "=a")
383 (mod:SI (match_operand:SI 1 "register_operand" "r")
384 (match_operand:SI 2 "register_operand" "r")))]
387 [(set_attr "type" "div32")
388 (set_attr "mode" "SI")
389 (set_attr "length" "3")])
391 (define_insn "umodsi3"
392 [(set (match_operand:SI 0 "register_operand" "=a")
393 (umod:SI (match_operand:SI 1 "register_operand" "r")
394 (match_operand:SI 2 "register_operand" "r")))]
397 [(set_attr "type" "div32")
398 (set_attr "mode" "SI")
399 (set_attr "length" "3")])
404 (define_insn "sqrtsf2"
405 [(set (match_operand:SF 0 "register_operand" "=f")
406 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
407 "TARGET_HARD_FLOAT_SQRT"
409 [(set_attr "type" "fsqrt")
410 (set_attr "mode" "SF")
411 (set_attr "length" "3")])
413 (define_insn "*rsqrtsf2"
414 [(set (match_operand:SF 0 "register_operand" "=f")
415 (div:SF (match_operand:SF 1 "const_float_1_operand" "")
416 (sqrt:SF (match_operand:SF 2 "register_operand" "f"))))]
417 "TARGET_HARD_FLOAT_RSQRT && flag_unsafe_math_optimizations"
419 [(set_attr "type" "fsqrt")
420 (set_attr "mode" "SF")
421 (set_attr "length" "3")])
426 (define_insn "abssi2"
427 [(set (match_operand:SI 0 "register_operand" "=a")
428 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
431 [(set_attr "type" "arith")
432 (set_attr "mode" "SI")
433 (set_attr "length" "3")])
435 (define_insn "abssf2"
436 [(set (match_operand:SF 0 "register_operand" "=f")
437 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
440 [(set_attr "type" "farith")
441 (set_attr "mode" "SF")
442 (set_attr "length" "3")])
447 (define_insn "<code>si3"
448 [(set (match_operand:SI 0 "register_operand" "=a")
449 (any_minmax:SI (match_operand:SI 1 "register_operand" "%r")
450 (match_operand:SI 2 "register_operand" "r")))]
452 "<minmax>\t%0, %1, %2"
453 [(set_attr "type" "arith")
454 (set_attr "mode" "SI")
455 (set_attr "length" "3")])
458 ;; Count leading/trailing zeros and find first bit.
460 (define_insn "clzsi2"
461 [(set (match_operand:SI 0 "register_operand" "=a")
462 (clz:SI (match_operand:SI 1 "register_operand" "r")))]
465 [(set_attr "type" "arith")
466 (set_attr "mode" "SI")
467 (set_attr "length" "3")])
469 (define_expand "ctzsi2"
470 [(set (match_operand:SI 0 "register_operand" "")
471 (ctz:SI (match_operand:SI 1 "register_operand" "")))]
474 rtx temp = gen_reg_rtx (SImode);
475 emit_insn (gen_negsi2 (temp, operands[1]));
476 emit_insn (gen_andsi3 (temp, temp, operands[1]));
477 emit_insn (gen_clzsi2 (temp, temp));
478 emit_insn (gen_negsi2 (temp, temp));
479 emit_insn (gen_addsi3 (operands[0], temp, GEN_INT (31)));
483 (define_expand "ffssi2"
484 [(set (match_operand:SI 0 "register_operand" "")
485 (ffs:SI (match_operand:SI 1 "register_operand" "")))]
488 rtx temp = gen_reg_rtx (SImode);
489 emit_insn (gen_negsi2 (temp, operands[1]));
490 emit_insn (gen_andsi3 (temp, temp, operands[1]));
491 emit_insn (gen_clzsi2 (temp, temp));
492 emit_insn (gen_negsi2 (temp, temp));
493 emit_insn (gen_addsi3 (operands[0], temp, GEN_INT (32)));
498 ;; Negation and one's complement.
500 (define_insn "negsi2"
501 [(set (match_operand:SI 0 "register_operand" "=a")
502 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
505 [(set_attr "type" "arith")
506 (set_attr "mode" "SI")
507 (set_attr "length" "3")])
509 (define_expand "one_cmplsi2"
510 [(set (match_operand:SI 0 "register_operand" "")
511 (not:SI (match_operand:SI 1 "register_operand" "")))]
514 rtx temp = gen_reg_rtx (SImode);
515 emit_insn (gen_movsi (temp, constm1_rtx));
516 emit_insn (gen_xorsi3 (operands[0], temp, operands[1]));
520 (define_insn "negsf2"
521 [(set (match_operand:SF 0 "register_operand" "=f")
522 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
525 [(set_attr "type" "farith")
526 (set_attr "mode" "SF")
527 (set_attr "length" "3")])
530 ;; Logical instructions.
532 (define_insn "andsi3"
533 [(set (match_operand:SI 0 "register_operand" "=a,a")
534 (and:SI (match_operand:SI 1 "register_operand" "%r,r")
535 (match_operand:SI 2 "mask_operand" "P,r")))]
538 extui\t%0, %1, 0, %K2
540 [(set_attr "type" "arith,arith")
541 (set_attr "mode" "SI")
542 (set_attr "length" "3,3")])
544 (define_insn "iorsi3"
545 [(set (match_operand:SI 0 "register_operand" "=a")
546 (ior:SI (match_operand:SI 1 "register_operand" "%r")
547 (match_operand:SI 2 "register_operand" "r")))]
550 [(set_attr "type" "arith")
551 (set_attr "mode" "SI")
552 (set_attr "length" "3")])
554 (define_insn "xorsi3"
555 [(set (match_operand:SI 0 "register_operand" "=a")
556 (xor:SI (match_operand:SI 1 "register_operand" "%r")
557 (match_operand:SI 2 "register_operand" "r")))]
560 [(set_attr "type" "arith")
561 (set_attr "mode" "SI")
562 (set_attr "length" "3")])
565 ;; Zero-extend instructions.
567 (define_insn "zero_extendhisi2"
568 [(set (match_operand:SI 0 "register_operand" "=a,a")
569 (zero_extend:SI (match_operand:HI 1 "nonimmed_operand" "r,U")))]
574 [(set_attr "type" "arith,load")
575 (set_attr "mode" "SI")
576 (set_attr "length" "3,3")])
578 (define_insn "zero_extendqisi2"
579 [(set (match_operand:SI 0 "register_operand" "=a,a")
580 (zero_extend:SI (match_operand:QI 1 "nonimmed_operand" "r,U")))]
585 [(set_attr "type" "arith,load")
586 (set_attr "mode" "SI")
587 (set_attr "length" "3,3")])
590 ;; Sign-extend instructions.
592 (define_expand "extendhisi2"
593 [(set (match_operand:SI 0 "register_operand" "")
594 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
597 if (sext_operand (operands[1], HImode))
598 emit_insn (gen_extendhisi2_internal (operands[0], operands[1]));
600 xtensa_extend_reg (operands[0], operands[1]);
604 (define_insn "extendhisi2_internal"
605 [(set (match_operand:SI 0 "register_operand" "=B,a")
606 (sign_extend:SI (match_operand:HI 1 "sext_operand" "r,U")))]
611 [(set_attr "type" "arith,load")
612 (set_attr "mode" "SI")
613 (set_attr "length" "3,3")])
615 (define_expand "extendqisi2"
616 [(set (match_operand:SI 0 "register_operand" "")
617 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
621 emit_insn (gen_extendqisi2_internal (operands[0], operands[1]));
623 xtensa_extend_reg (operands[0], operands[1]);
627 (define_insn "extendqisi2_internal"
628 [(set (match_operand:SI 0 "register_operand" "=B")
629 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
632 [(set_attr "type" "arith")
633 (set_attr "mode" "SI")
634 (set_attr "length" "3")])
637 ;; Field extract instructions.
639 (define_expand "extv"
640 [(set (match_operand:SI 0 "register_operand" "")
641 (sign_extract:SI (match_operand:SI 1 "register_operand" "")
642 (match_operand:SI 2 "const_int_operand" "")
643 (match_operand:SI 3 "const_int_operand" "")))]
646 if (!sext_fldsz_operand (operands[2], SImode))
649 /* We could expand to a right shift followed by SEXT but that's
650 no better than the standard left and right shift sequence. */
651 if (!lsbitnum_operand (operands[3], SImode))
654 emit_insn (gen_extv_internal (operands[0], operands[1],
655 operands[2], operands[3]));
659 (define_insn "extv_internal"
660 [(set (match_operand:SI 0 "register_operand" "=a")
661 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
662 (match_operand:SI 2 "sext_fldsz_operand" "i")
663 (match_operand:SI 3 "lsbitnum_operand" "i")))]
666 int fldsz = INTVAL (operands[2]);
667 operands[2] = GEN_INT (fldsz - 1);
668 return "sext\t%0, %1, %2";
670 [(set_attr "type" "arith")
671 (set_attr "mode" "SI")
672 (set_attr "length" "3")])
674 (define_expand "extzv"
675 [(set (match_operand:SI 0 "register_operand" "")
676 (zero_extract:SI (match_operand:SI 1 "register_operand" "")
677 (match_operand:SI 2 "const_int_operand" "")
678 (match_operand:SI 3 "const_int_operand" "")))]
681 if (!extui_fldsz_operand (operands[2], SImode))
683 emit_insn (gen_extzv_internal (operands[0], operands[1],
684 operands[2], operands[3]));
688 (define_insn "extzv_internal"
689 [(set (match_operand:SI 0 "register_operand" "=a")
690 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
691 (match_operand:SI 2 "extui_fldsz_operand" "i")
692 (match_operand:SI 3 "const_int_operand" "i")))]
697 shift = (32 - (INTVAL (operands[2]) + INTVAL (operands[3]))) & 0x1f;
699 shift = INTVAL (operands[3]) & 0x1f;
700 operands[3] = GEN_INT (shift);
701 return "extui\t%0, %1, %3, %2";
703 [(set_attr "type" "arith")
704 (set_attr "mode" "SI")
705 (set_attr "length" "3")])
710 (define_insn "fix_truncsfsi2"
711 [(set (match_operand:SI 0 "register_operand" "=a")
712 (fix:SI (match_operand:SF 1 "register_operand" "f")))]
715 [(set_attr "type" "fconv")
716 (set_attr "mode" "SF")
717 (set_attr "length" "3")])
719 (define_insn "fixuns_truncsfsi2"
720 [(set (match_operand:SI 0 "register_operand" "=a")
721 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "f")))]
723 "utrunc.s\t%0, %1, 0"
724 [(set_attr "type" "fconv")
725 (set_attr "mode" "SF")
726 (set_attr "length" "3")])
728 (define_insn "floatsisf2"
729 [(set (match_operand:SF 0 "register_operand" "=f")
730 (float:SF (match_operand:SI 1 "register_operand" "a")))]
733 [(set_attr "type" "fconv")
734 (set_attr "mode" "SF")
735 (set_attr "length" "3")])
737 (define_insn "floatunssisf2"
738 [(set (match_operand:SF 0 "register_operand" "=f")
739 (unsigned_float:SF (match_operand:SI 1 "register_operand" "a")))]
741 "ufloat.s\t%0, %1, 0"
742 [(set_attr "type" "fconv")
743 (set_attr "mode" "SF")
744 (set_attr "length" "3")])
747 ;; Data movement instructions.
749 ;; 64-bit Integer moves
751 (define_expand "movdi"
752 [(set (match_operand:DI 0 "nonimmed_operand" "")
753 (match_operand:DI 1 "general_operand" ""))]
756 if (CONSTANT_P (operands[1]) && !TARGET_CONST16)
757 operands[1] = force_const_mem (DImode, operands[1]);
759 if (!register_operand (operands[0], DImode)
760 && !register_operand (operands[1], DImode))
761 operands[1] = force_reg (DImode, operands[1]);
763 operands[1] = xtensa_copy_incoming_a7 (operands[1]);
766 (define_insn_and_split "movdi_internal"
767 [(set (match_operand:DI 0 "nonimmed_operand" "=a,W,a,a,U")
768 (match_operand:DI 1 "move_operand" "r,i,T,U,r"))]
769 "register_operand (operands[0], DImode)
770 || register_operand (operands[1], DImode)"
773 [(set (match_dup 0) (match_dup 2))
774 (set (match_dup 1) (match_dup 3))]
776 xtensa_split_operand_pair (operands, SImode);
777 if (reg_overlap_mentioned_p (operands[0], operands[3]))
780 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
781 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
785 ;; 32-bit Integer moves
787 (define_expand "movsi"
788 [(set (match_operand:SI 0 "nonimmed_operand" "")
789 (match_operand:SI 1 "general_operand" ""))]
792 if (xtensa_emit_move_sequence (operands, SImode))
796 (define_insn "movsi_internal"
797 [(set (match_operand:SI 0 "nonimmed_operand" "=D,D,D,D,R,R,a,q,a,W,a,a,U,*a,*A")
798 (match_operand:SI 1 "move_operand" "M,D,d,R,D,d,r,r,I,i,T,U,r,*A,*r"))]
799 "xtensa_valid_move (SImode, operands)"
810 const16\t%0, %t1\;const16\t%0, %b1
816 [(set_attr "type" "move,move,move,load,store,store,move,move,move,move,load,load,store,rsr,wsr")
817 (set_attr "mode" "SI")
818 (set_attr "length" "2,2,2,2,2,2,3,3,3,6,3,3,3,3,3")])
820 ;; 16-bit Integer moves
822 (define_expand "movhi"
823 [(set (match_operand:HI 0 "nonimmed_operand" "")
824 (match_operand:HI 1 "general_operand" ""))]
827 if (xtensa_emit_move_sequence (operands, HImode))
831 (define_insn "movhi_internal"
832 [(set (match_operand:HI 0 "nonimmed_operand" "=D,D,a,a,a,U,*a,*A")
833 (match_operand:HI 1 "move_operand" "M,d,r,I,U,r,*A,*r"))]
834 "xtensa_valid_move (HImode, operands)"
844 [(set_attr "type" "move,move,move,move,load,store,rsr,wsr")
845 (set_attr "mode" "HI")
846 (set_attr "length" "2,2,3,3,3,3,3,3")])
848 ;; 8-bit Integer moves
850 (define_expand "movqi"
851 [(set (match_operand:QI 0 "nonimmed_operand" "")
852 (match_operand:QI 1 "general_operand" ""))]
855 if (xtensa_emit_move_sequence (operands, QImode))
859 (define_insn "movqi_internal"
860 [(set (match_operand:QI 0 "nonimmed_operand" "=D,D,a,a,a,U,*a,*A")
861 (match_operand:QI 1 "move_operand" "M,d,r,I,U,r,*A,*r"))]
862 "xtensa_valid_move (QImode, operands)"
872 [(set_attr "type" "move,move,move,move,load,store,rsr,wsr")
873 (set_attr "mode" "QI")
874 (set_attr "length" "2,2,3,3,3,3,3,3")])
876 ;; 32-bit floating point moves
878 (define_expand "movsf"
879 [(set (match_operand:SF 0 "nonimmed_operand" "")
880 (match_operand:SF 1 "general_operand" ""))]
883 if (!TARGET_CONST16 && CONSTANT_P (operands[1]))
884 operands[1] = force_const_mem (SFmode, operands[1]);
886 if ((!register_operand (operands[0], SFmode)
887 && !register_operand (operands[1], SFmode))
888 || (FP_REG_P (xt_true_regnum (operands[0]))
889 && !(reload_in_progress | reload_completed)
890 && (constantpool_mem_p (operands[1])
891 || CONSTANT_P (operands[1]))))
892 operands[1] = force_reg (SFmode, operands[1]);
894 operands[1] = xtensa_copy_incoming_a7 (operands[1]);
897 (define_insn "movsf_internal"
898 [(set (match_operand:SF 0 "nonimmed_operand" "=f,f,U,D,D,R,a,f,a,W,a,a,U")
899 (match_operand:SF 1 "move_operand" "f,U,f,d,R,d,r,r,f,iF,T,U,r"))]
900 "((register_operand (operands[0], SFmode)
901 || register_operand (operands[1], SFmode))
902 && !(FP_REG_P (xt_true_regnum (operands[0]))
903 && (constantpool_mem_p (operands[1]) || CONSTANT_P (operands[1]))))"
914 const16\t%0, %t1\;const16\t%0, %b1
918 [(set_attr "type" "farith,fload,fstore,move,load,store,move,farith,farith,move,load,load,store")
919 (set_attr "mode" "SF")
920 (set_attr "length" "3,3,3,2,2,2,3,3,3,6,3,3,3")])
923 [(set (match_operand:SF 0 "register_operand" "=f")
924 (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "+a")
925 (match_operand:SI 2 "fpmem_offset_operand" "i"))))
927 (plus:SI (match_dup 1) (match_dup 2)))]
930 if (volatile_refs_p (PATTERN (insn)))
931 output_asm_insn ("memw", operands);
932 return "lsiu\t%0, %1, %2";
934 [(set_attr "type" "fload")
935 (set_attr "mode" "SF")
936 (set_attr "length" "3")])
939 [(set (mem:SF (plus:SI (match_operand:SI 0 "register_operand" "+a")
940 (match_operand:SI 1 "fpmem_offset_operand" "i")))
941 (match_operand:SF 2 "register_operand" "f"))
943 (plus:SI (match_dup 0) (match_dup 1)))]
946 if (volatile_refs_p (PATTERN (insn)))
947 output_asm_insn ("memw", operands);
948 return "ssiu\t%2, %0, %1";
950 [(set_attr "type" "fstore")
951 (set_attr "mode" "SF")
952 (set_attr "length" "3")])
954 ;; 64-bit floating point moves
956 (define_expand "movdf"
957 [(set (match_operand:DF 0 "nonimmed_operand" "")
958 (match_operand:DF 1 "general_operand" ""))]
961 if (CONSTANT_P (operands[1]) && !TARGET_CONST16)
962 operands[1] = force_const_mem (DFmode, operands[1]);
964 if (!register_operand (operands[0], DFmode)
965 && !register_operand (operands[1], DFmode))
966 operands[1] = force_reg (DFmode, operands[1]);
968 operands[1] = xtensa_copy_incoming_a7 (operands[1]);
971 (define_insn_and_split "movdf_internal"
972 [(set (match_operand:DF 0 "nonimmed_operand" "=a,W,a,a,U")
973 (match_operand:DF 1 "move_operand" "r,iF,T,U,r"))]
974 "register_operand (operands[0], DFmode)
975 || register_operand (operands[1], DFmode)"
978 [(set (match_dup 0) (match_dup 2))
979 (set (match_dup 1) (match_dup 3))]
981 xtensa_split_operand_pair (operands, SFmode);
982 if (reg_overlap_mentioned_p (operands[0], operands[3]))
985 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
986 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
992 (define_expand "movmemsi"
993 [(parallel [(set (match_operand:BLK 0 "" "")
994 (match_operand:BLK 1 "" ""))
995 (use (match_operand:SI 2 "arith_operand" ""))
996 (use (match_operand:SI 3 "const_int_operand" ""))])]
999 if (!xtensa_expand_block_move (operands))
1005 ;; Shift instructions.
1007 (define_expand "ashlsi3"
1008 [(set (match_operand:SI 0 "register_operand" "")
1009 (ashift:SI (match_operand:SI 1 "register_operand" "")
1010 (match_operand:SI 2 "arith_operand" "")))]
1013 operands[1] = xtensa_copy_incoming_a7 (operands[1]);
1016 (define_insn "ashlsi3_internal"
1017 [(set (match_operand:SI 0 "register_operand" "=a,a")
1018 (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
1019 (match_operand:SI 2 "arith_operand" "J,r")))]
1023 ssl\t%2\;sll\t%0, %1"
1024 [(set_attr "type" "arith,arith")
1025 (set_attr "mode" "SI")
1026 (set_attr "length" "3,6")])
1028 (define_insn "ashrsi3"
1029 [(set (match_operand:SI 0 "register_operand" "=a,a")
1030 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
1031 (match_operand:SI 2 "arith_operand" "J,r")))]
1035 ssr\t%2\;sra\t%0, %1"
1036 [(set_attr "type" "arith,arith")
1037 (set_attr "mode" "SI")
1038 (set_attr "length" "3,6")])
1040 (define_insn "lshrsi3"
1041 [(set (match_operand:SI 0 "register_operand" "=a,a")
1042 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
1043 (match_operand:SI 2 "arith_operand" "J,r")))]
1046 if (which_alternative == 0)
1048 if ((INTVAL (operands[2]) & 0x1f) < 16)
1049 return "srli\t%0, %1, %R2";
1051 return "extui\t%0, %1, %R2, %L2";
1053 return "ssr\t%2\;srl\t%0, %1";
1055 [(set_attr "type" "arith,arith")
1056 (set_attr "mode" "SI")
1057 (set_attr "length" "3,6")])
1059 (define_insn "rotlsi3"
1060 [(set (match_operand:SI 0 "register_operand" "=a,a")
1061 (rotate:SI (match_operand:SI 1 "register_operand" "r,r")
1062 (match_operand:SI 2 "arith_operand" "J,r")))]
1065 ssai\t%L2\;src\t%0, %1, %1
1066 ssl\t%2\;src\t%0, %1, %1"
1067 [(set_attr "type" "multi,multi")
1068 (set_attr "mode" "SI")
1069 (set_attr "length" "6,6")])
1071 (define_insn "rotrsi3"
1072 [(set (match_operand:SI 0 "register_operand" "=a,a")
1073 (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
1074 (match_operand:SI 2 "arith_operand" "J,r")))]
1077 ssai\t%R2\;src\t%0, %1, %1
1078 ssr\t%2\;src\t%0, %1, %1"
1079 [(set_attr "type" "multi,multi")
1080 (set_attr "mode" "SI")
1081 (set_attr "length" "6,6")])
1086 ;; Handle comparisons by stashing away the operands and then using that
1087 ;; information in the subsequent conditional branch.
1089 (define_expand "cmpsi"
1091 (compare:CC (match_operand:SI 0 "register_operand" "")
1092 (match_operand:SI 1 "nonmemory_operand" "")))]
1095 branch_cmp[0] = operands[0];
1096 branch_cmp[1] = operands[1];
1097 branch_type = CMP_SI;
1101 (define_expand "cmpsf"
1103 (compare:CC (match_operand:SF 0 "register_operand" "")
1104 (match_operand:SF 1 "register_operand" "")))]
1107 branch_cmp[0] = operands[0];
1108 branch_cmp[1] = operands[1];
1109 branch_type = CMP_SF;
1114 ;; Conditional branches.
1116 (define_expand "b<code>"
1118 (if_then_else (any_cond (cc0) (const_int 0))
1119 (label_ref (match_operand 0 "" ""))
1123 xtensa_expand_conditional_branch (operands, <CODE>);
1127 ;; Branch patterns for standard integer comparisons
1129 (define_insn "*btrue"
1131 (if_then_else (match_operator 3 "branch_operator"
1132 [(match_operand:SI 0 "register_operand" "r,r")
1133 (match_operand:SI 1 "branch_operand" "K,r")])
1134 (label_ref (match_operand 2 "" ""))
1138 return xtensa_emit_branch (false, which_alternative == 0, operands);
1140 [(set_attr "type" "jump,jump")
1141 (set_attr "mode" "none")
1142 (set_attr "length" "3,3")])
1144 (define_insn "*bfalse"
1146 (if_then_else (match_operator 3 "branch_operator"
1147 [(match_operand:SI 0 "register_operand" "r,r")
1148 (match_operand:SI 1 "branch_operand" "K,r")])
1150 (label_ref (match_operand 2 "" ""))))]
1153 return xtensa_emit_branch (true, which_alternative == 0, operands);
1155 [(set_attr "type" "jump,jump")
1156 (set_attr "mode" "none")
1157 (set_attr "length" "3,3")])
1159 (define_insn "*ubtrue"
1161 (if_then_else (match_operator 3 "ubranch_operator"
1162 [(match_operand:SI 0 "register_operand" "r,r")
1163 (match_operand:SI 1 "ubranch_operand" "L,r")])
1164 (label_ref (match_operand 2 "" ""))
1168 return xtensa_emit_branch (false, which_alternative == 0, operands);
1170 [(set_attr "type" "jump,jump")
1171 (set_attr "mode" "none")
1172 (set_attr "length" "3,3")])
1174 (define_insn "*ubfalse"
1176 (if_then_else (match_operator 3 "ubranch_operator"
1177 [(match_operand:SI 0 "register_operand" "r,r")
1178 (match_operand:SI 1 "ubranch_operand" "L,r")])
1180 (label_ref (match_operand 2 "" ""))))]
1183 return xtensa_emit_branch (true, which_alternative == 0, operands);
1185 [(set_attr "type" "jump,jump")
1186 (set_attr "mode" "none")
1187 (set_attr "length" "3,3")])
1189 ;; Branch patterns for bit testing
1191 (define_insn "*bittrue"
1193 (if_then_else (match_operator 3 "boolean_operator"
1195 (match_operand:SI 0 "register_operand" "r,r")
1197 (match_operand:SI 1 "arith_operand" "J,r"))
1199 (label_ref (match_operand 2 "" ""))
1203 return xtensa_emit_bit_branch (false, which_alternative == 0, operands);
1205 [(set_attr "type" "jump")
1206 (set_attr "mode" "none")
1207 (set_attr "length" "3")])
1209 (define_insn "*bitfalse"
1211 (if_then_else (match_operator 3 "boolean_operator"
1213 (match_operand:SI 0 "register_operand" "r,r")
1215 (match_operand:SI 1 "arith_operand" "J,r"))
1218 (label_ref (match_operand 2 "" ""))))]
1221 return xtensa_emit_bit_branch (true, which_alternative == 0, operands);
1223 [(set_attr "type" "jump")
1224 (set_attr "mode" "none")
1225 (set_attr "length" "3")])
1227 (define_insn "*masktrue"
1229 (if_then_else (match_operator 3 "boolean_operator"
1230 [(and:SI (match_operand:SI 0 "register_operand" "r")
1231 (match_operand:SI 1 "register_operand" "r"))
1233 (label_ref (match_operand 2 "" ""))
1237 switch (GET_CODE (operands[3]))
1239 case EQ: return "bnone\t%0, %1, %2";
1240 case NE: return "bany\t%0, %1, %2";
1241 default: gcc_unreachable ();
1244 [(set_attr "type" "jump")
1245 (set_attr "mode" "none")
1246 (set_attr "length" "3")])
1248 (define_insn "*maskfalse"
1250 (if_then_else (match_operator 3 "boolean_operator"
1251 [(and:SI (match_operand:SI 0 "register_operand" "r")
1252 (match_operand:SI 1 "register_operand" "r"))
1255 (label_ref (match_operand 2 "" ""))))]
1258 switch (GET_CODE (operands[3]))
1260 case EQ: return "bany\t%0, %1, %2";
1261 case NE: return "bnone\t%0, %1, %2";
1262 default: gcc_unreachable ();
1265 [(set_attr "type" "jump")
1266 (set_attr "mode" "none")
1267 (set_attr "length" "3")])
1270 ;; Define the loop insns used by bct optimization to represent the
1271 ;; start and end of a zero-overhead loop (in loop.c). This start
1272 ;; template generates the loop insn; the end template doesn't generate
1273 ;; any instructions since loop end is handled in hardware.
1275 (define_insn "zero_cost_loop_start"
1277 (if_then_else (eq (match_operand:SI 0 "register_operand" "a")
1279 (label_ref (match_operand 1 "" ""))
1282 (plus:SI (match_dup 0) (const_int -1)))]
1285 [(set_attr "type" "jump")
1286 (set_attr "mode" "none")
1287 (set_attr "length" "3")])
1289 (define_insn "zero_cost_loop_end"
1291 (if_then_else (ne (reg:SI 19) (const_int 0))
1292 (label_ref (match_operand 0 "" ""))
1295 (plus:SI (reg:SI 19) (const_int -1)))]
1298 xtensa_emit_loop_end (insn, operands);
1301 [(set_attr "type" "jump")
1302 (set_attr "mode" "none")
1303 (set_attr "length" "0")])
1306 ;; Setting a register from a comparison.
1308 (define_expand "s<code>"
1309 [(set (match_operand:SI 0 "register_operand" "")
1310 (any_scc:SI (match_dup 1)
1314 operands[1] = gen_rtx_<CODE> (SImode, branch_cmp[0], branch_cmp[1]);
1315 if (!xtensa_expand_scc (operands))
1321 ;; Conditional moves.
1323 (define_expand "movsicc"
1324 [(set (match_operand:SI 0 "register_operand" "")
1325 (if_then_else:SI (match_operand 1 "comparison_operator" "")
1326 (match_operand:SI 2 "register_operand" "")
1327 (match_operand:SI 3 "register_operand" "")))]
1330 if (!xtensa_expand_conditional_move (operands, 0))
1335 (define_expand "movsfcc"
1336 [(set (match_operand:SF 0 "register_operand" "")
1337 (if_then_else:SF (match_operand 1 "comparison_operator" "")
1338 (match_operand:SF 2 "register_operand" "")
1339 (match_operand:SF 3 "register_operand" "")))]
1342 if (!xtensa_expand_conditional_move (operands, 1))
1347 (define_insn "movsicc_internal0"
1348 [(set (match_operand:SI 0 "register_operand" "=a,a")
1349 (if_then_else:SI (match_operator 4 "branch_operator"
1350 [(match_operand:SI 1 "register_operand" "r,r")
1352 (match_operand:SI 2 "register_operand" "r,0")
1353 (match_operand:SI 3 "register_operand" "0,r")))]
1356 return xtensa_emit_movcc (which_alternative == 1, false, false, operands);
1358 [(set_attr "type" "move,move")
1359 (set_attr "mode" "SI")
1360 (set_attr "length" "3,3")])
1362 (define_insn "movsicc_internal1"
1363 [(set (match_operand:SI 0 "register_operand" "=a,a")
1364 (if_then_else:SI (match_operator 4 "boolean_operator"
1365 [(match_operand:CC 1 "register_operand" "b,b")
1367 (match_operand:SI 2 "register_operand" "r,0")
1368 (match_operand:SI 3 "register_operand" "0,r")))]
1371 return xtensa_emit_movcc (which_alternative == 1, false, true, operands);
1373 [(set_attr "type" "move,move")
1374 (set_attr "mode" "SI")
1375 (set_attr "length" "3,3")])
1377 (define_insn "movsfcc_internal0"
1378 [(set (match_operand:SF 0 "register_operand" "=a,a,f,f")
1379 (if_then_else:SF (match_operator 4 "branch_operator"
1380 [(match_operand:SI 1 "register_operand" "r,r,r,r")
1382 (match_operand:SF 2 "register_operand" "r,0,f,0")
1383 (match_operand:SF 3 "register_operand" "0,r,0,f")))]
1386 return xtensa_emit_movcc ((which_alternative & 1) == 1,
1387 which_alternative >= 2, false, operands);
1389 [(set_attr "type" "move,move,move,move")
1390 (set_attr "mode" "SF")
1391 (set_attr "length" "3,3,3,3")])
1393 (define_insn "movsfcc_internal1"
1394 [(set (match_operand:SF 0 "register_operand" "=a,a,f,f")
1395 (if_then_else:SF (match_operator 4 "boolean_operator"
1396 [(match_operand:CC 1 "register_operand" "b,b,b,b")
1398 (match_operand:SF 2 "register_operand" "r,0,f,0")
1399 (match_operand:SF 3 "register_operand" "0,r,0,f")))]
1402 return xtensa_emit_movcc ((which_alternative & 1) == 1,
1403 which_alternative >= 2, true, operands);
1405 [(set_attr "type" "move,move,move,move")
1406 (set_attr "mode" "SF")
1407 (set_attr "length" "3,3,3,3")])
1410 ;; Floating-point comparisons.
1412 (define_insn "s<code>_sf"
1413 [(set (match_operand:CC 0 "register_operand" "=b")
1414 (any_scc_sf:CC (match_operand:SF 1 "register_operand" "f")
1415 (match_operand:SF 2 "register_operand" "f")))]
1417 "o<code>.s\t%0, %1, %2"
1418 [(set_attr "type" "farith")
1419 (set_attr "mode" "BL")
1420 (set_attr "length" "3")])
1423 ;; Unconditional branches.
1427 (label_ref (match_operand 0 "" "")))]
1430 [(set_attr "type" "jump")
1431 (set_attr "mode" "none")
1432 (set_attr "length" "3")])
1434 (define_expand "indirect_jump"
1436 (match_operand 0 "register_operand" ""))]
1439 rtx dest = operands[0];
1440 if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode)
1441 operands[0] = copy_to_mode_reg (Pmode, dest);
1443 emit_jump_insn (gen_indirect_jump_internal (dest));
1447 (define_insn "indirect_jump_internal"
1448 [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
1451 [(set_attr "type" "jump")
1452 (set_attr "mode" "none")
1453 (set_attr "length" "3")])
1456 (define_expand "tablejump"
1457 [(use (match_operand:SI 0 "register_operand" ""))
1458 (use (label_ref (match_operand 1 "" "")))]
1461 rtx target = operands[0];
1464 /* For PIC, the table entry is relative to the start of the table. */
1465 rtx label = gen_reg_rtx (SImode);
1466 target = gen_reg_rtx (SImode);
1467 emit_move_insn (label, gen_rtx_LABEL_REF (SImode, operands[1]));
1468 emit_insn (gen_addsi3 (target, operands[0], label));
1470 emit_jump_insn (gen_tablejump_internal (target, operands[1]));
1474 (define_insn "tablejump_internal"
1476 (match_operand:SI 0 "register_operand" "r"))
1477 (use (label_ref (match_operand 1 "" "")))]
1480 [(set_attr "type" "jump")
1481 (set_attr "mode" "none")
1482 (set_attr "length" "3")])
1487 (define_expand "sym_PLT"
1488 [(const (unspec [(match_operand:SI 0 "" "")] UNSPEC_PLT))]
1492 (define_expand "call"
1493 [(call (match_operand 0 "memory_operand" "")
1494 (match_operand 1 "" ""))]
1497 rtx addr = XEXP (operands[0], 0);
1498 if (flag_pic && GET_CODE (addr) == SYMBOL_REF
1499 && (!SYMBOL_REF_LOCAL_P (addr) || SYMBOL_REF_EXTERNAL_P (addr)))
1500 addr = gen_sym_PLT (addr);
1501 if (!call_insn_operand (addr, VOIDmode))
1502 XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, addr);
1505 (define_insn "call_internal"
1506 [(call (mem (match_operand:SI 0 "call_insn_operand" "nir"))
1507 (match_operand 1 "" "i"))]
1510 return xtensa_emit_call (0, operands);
1512 [(set_attr "type" "call")
1513 (set_attr "mode" "none")
1514 (set_attr "length" "3")])
1516 (define_expand "call_value"
1517 [(set (match_operand 0 "register_operand" "")
1518 (call (match_operand 1 "memory_operand" "")
1519 (match_operand 2 "" "")))]
1522 rtx addr = XEXP (operands[1], 0);
1523 if (flag_pic && GET_CODE (addr) == SYMBOL_REF
1524 && (!SYMBOL_REF_LOCAL_P (addr) || SYMBOL_REF_EXTERNAL_P (addr)))
1525 addr = gen_sym_PLT (addr);
1526 if (!call_insn_operand (addr, VOIDmode))
1527 XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, addr);
1530 (define_insn "call_value_internal"
1531 [(set (match_operand 0 "register_operand" "=a")
1532 (call (mem (match_operand:SI 1 "call_insn_operand" "nir"))
1533 (match_operand 2 "" "i")))]
1536 return xtensa_emit_call (1, operands);
1538 [(set_attr "type" "call")
1539 (set_attr "mode" "none")
1540 (set_attr "length" "3")])
1542 (define_insn "entry"
1543 [(set (reg:SI A1_REG)
1544 (unspec_volatile:SI [(match_operand:SI 0 "const_int_operand" "i")]
1548 [(set_attr "type" "entry")
1549 (set_attr "mode" "SI")
1550 (set_attr "length" "3")])
1552 (define_insn "return"
1554 (use (reg:SI A0_REG))]
1557 return (TARGET_DENSITY ? "retw.n" : "retw");
1559 [(set_attr "type" "jump")
1560 (set_attr "mode" "none")
1561 (set_attr "length" "2")])
1564 ;; Miscellaneous instructions.
1566 (define_expand "prologue"
1570 xtensa_expand_prologue ();
1574 (define_expand "epilogue"
1578 emit_jump_insn (gen_return ());
1586 return (TARGET_DENSITY ? "nop.n" : "nop");
1588 [(set_attr "type" "nop")
1589 (set_attr "mode" "none")
1590 (set_attr "length" "3")])
1592 (define_expand "nonlocal_goto"
1593 [(match_operand:SI 0 "general_operand" "")
1594 (match_operand:SI 1 "general_operand" "")
1595 (match_operand:SI 2 "general_operand" "")
1596 (match_operand:SI 3 "" "")]
1599 xtensa_expand_nonlocal_goto (operands);
1603 ;; Setting up a frame pointer is tricky for Xtensa because GCC doesn't
1604 ;; know if a frame pointer is required until the reload pass, and
1605 ;; because there may be an incoming argument value in the hard frame
1606 ;; pointer register (a7). If there is an incoming argument in that
1607 ;; register, the "set_frame_ptr" insn gets inserted immediately after
1608 ;; the insn that copies the incoming argument to a pseudo or to the
1609 ;; stack. This serves several purposes here: (1) it keeps the
1610 ;; optimizer from copy-propagating or scheduling the use of a7 as an
1611 ;; incoming argument away from the beginning of the function; (2) we
1612 ;; can use a post-reload splitter to expand away the insn if a frame
1613 ;; pointer is not required, so that the post-reload scheduler can do
1614 ;; the right thing; and (3) it makes it easy for the prologue expander
1615 ;; to search for this insn to determine whether it should add a new insn
1616 ;; to set up the frame pointer.
1618 (define_insn "set_frame_ptr"
1619 [(set (reg:SI A7_REG) (unspec_volatile:SI [(const_int 0)] UNSPECV_SET_FP))]
1622 if (frame_pointer_needed)
1623 return "mov\ta7, sp";
1626 [(set_attr "type" "move")
1627 (set_attr "mode" "SI")
1628 (set_attr "length" "3")])
1630 ;; Post-reload splitter to remove fp assignment when it's not needed.
1632 [(set (reg:SI A7_REG) (unspec_volatile:SI [(const_int 0)] UNSPECV_SET_FP))]
1633 "reload_completed && !frame_pointer_needed"
1634 [(unspec [(const_int 0)] UNSPEC_NOP)]
1637 ;; The preceding splitter needs something to split the insn into;
1638 ;; things start breaking if the result is just a "use" so instead we
1639 ;; generate the following insn.
1640 (define_insn "*unspec_nop"
1641 [(unspec [(const_int 0)] UNSPEC_NOP)]
1644 [(set_attr "type" "nop")
1645 (set_attr "mode" "none")
1646 (set_attr "length" "0")])
1648 ;; The fix_return_addr pattern sets the high 2 bits of an address in a
1649 ;; register to match the high bits of the current PC.
1650 (define_insn "fix_return_addr"
1651 [(set (match_operand:SI 0 "register_operand" "=a")
1652 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
1654 (clobber (match_scratch:SI 2 "=r"))
1655 (clobber (match_scratch:SI 3 "=r"))]
1657 "mov\t%2, a0\;call0\t0f\;.align\t4\;0:\;mov\t%3, a0\;mov\ta0, %2\;\
1658 srli\t%3, %3, 30\;slli\t%0, %1, 2\;ssai\t2\;src\t%0, %3, %0"
1659 [(set_attr "type" "multi")
1660 (set_attr "mode" "SI")
1661 (set_attr "length" "24")])
1664 ;; Instructions for the Xtensa "boolean" option.
1666 (define_insn "*booltrue"
1668 (if_then_else (match_operator 2 "boolean_operator"
1669 [(match_operand:CC 0 "register_operand" "b")
1671 (label_ref (match_operand 1 "" ""))
1675 if (GET_CODE (operands[2]) == EQ)
1676 return "bf\t%0, %1";
1678 return "bt\t%0, %1";
1680 [(set_attr "type" "jump")
1681 (set_attr "mode" "none")
1682 (set_attr "length" "3")])
1684 (define_insn "*boolfalse"
1686 (if_then_else (match_operator 2 "boolean_operator"
1687 [(match_operand:CC 0 "register_operand" "b")
1690 (label_ref (match_operand 1 "" ""))))]
1693 if (GET_CODE (operands[2]) == EQ)
1694 return "bt\t%0, %1";
1696 return "bf\t%0, %1";
1698 [(set_attr "type" "jump")
1699 (set_attr "mode" "none")
1700 (set_attr "length" "3")])
1703 ;; Atomic operations
1705 (define_expand "memory_barrier"
1706 [(set (mem:BLK (match_dup 0))
1707 (unspec_volatile:BLK [(mem:BLK (match_dup 0))] UNSPECV_MEMW))]
1710 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (SImode));
1711 MEM_VOLATILE_P (operands[0]) = 1;
1714 (define_insn "*memory_barrier"
1715 [(set (match_operand:BLK 0 "" "")
1716 (unspec_volatile:BLK [(match_operand:BLK 1 "" "")] UNSPECV_MEMW))]
1719 [(set_attr "type" "unknown")
1720 (set_attr "mode" "none")
1721 (set_attr "length" "3")])
1723 ;; sync_lock_release is only implemented for SImode.
1724 ;; For other modes, just use the default of a store with a memory_barrier.
1725 (define_insn "sync_lock_releasesi"
1726 [(set (match_operand:SI 0 "mem_operand" "=U")
1728 [(match_operand:SI 1 "register_operand" "r")]
1730 "TARGET_RELEASE_SYNC"
1732 [(set_attr "type" "store")
1733 (set_attr "mode" "SI")
1734 (set_attr "length" "3")])
1736 (define_insn "sync_compare_and_swapsi"
1738 [(set (match_operand:SI 0 "register_operand" "=a")
1739 (match_operand:SI 1 "mem_operand" "+U"))
1743 (match_operand:SI 2 "register_operand" "r")
1744 (match_operand:SI 3 "register_operand" "0")]
1747 "wsr\t%2, SCOMPARE1\;s32c1i\t%3, %1"
1748 [(set_attr "type" "multi")
1749 (set_attr "mode" "SI")
1750 (set_attr "length" "6")])
1752 (define_expand "sync_compare_and_swap<mode>"
1754 [(set (match_operand:HQI 0 "register_operand" "")
1755 (match_operand:HQI 1 "mem_operand" ""))
1757 (unspec_volatile:HQI
1759 (match_operand:HQI 2 "register_operand" "")
1760 (match_operand:HQI 3 "register_operand" "")]
1764 xtensa_expand_compare_and_swap (operands[0], operands[1],
1765 operands[2], operands[3]);
1769 (define_expand "sync_lock_test_and_set<mode>"
1770 [(match_operand:HQI 0 "register_operand")
1771 (match_operand:HQI 1 "memory_operand")
1772 (match_operand:HQI 2 "register_operand")]
1775 xtensa_expand_atomic (SET, operands[0], operands[1], operands[2], false);
1779 (define_expand "sync_<atomic><mode>"
1780 [(set (match_operand:HQI 0 "memory_operand")
1781 (ATOMIC:HQI (match_dup 0)
1782 (match_operand:HQI 1 "register_operand")))]
1785 xtensa_expand_atomic (<CODE>, NULL_RTX, operands[0], operands[1], false);
1789 (define_expand "sync_old_<atomic><mode>"
1790 [(set (match_operand:HQI 0 "register_operand")
1791 (match_operand:HQI 1 "memory_operand"))
1793 (ATOMIC:HQI (match_dup 1)
1794 (match_operand:HQI 2 "register_operand")))]
1797 xtensa_expand_atomic (<CODE>, operands[0], operands[1], operands[2], false);
1801 (define_expand "sync_new_<atomic><mode>"
1802 [(set (match_operand:HQI 0 "register_operand")
1803 (ATOMIC:HQI (match_operand:HQI 1 "memory_operand")
1804 (match_operand:HQI 2 "register_operand")))
1805 (set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))]
1808 xtensa_expand_atomic (<CODE>, operands[0], operands[1], operands[2], true);