1 /* Definitions of Tensilica's Xtensa target machine for GNU compiler.
2 Copyright 2001,2002,2003 Free Software Foundation, Inc.
3 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* Get Xtensa configuration settings */
23 #include "xtensa-config.h"
25 /* Standard GCC variables that we reference. */
26 extern int current_function_calls_alloca;
27 extern int target_flags;
30 /* External variables defined in xtensa.c. */
34 CMP_SI, /* four byte integers */
35 CMP_DI, /* eight byte integers */
36 CMP_SF, /* single precision floats */
37 CMP_DF, /* double precision floats */
38 CMP_MAX /* max comparison type */
41 extern struct rtx_def * branch_cmp[2]; /* operands for compare */
42 extern enum cmp_type branch_type; /* what type of branch to use */
43 extern unsigned xtensa_current_frame_size;
45 /* Masks for the -m switches */
46 #define MASK_NO_FUSED_MADD 0x00000001 /* avoid f-p mul/add */
47 #define MASK_CONST16 0x00000002 /* use CONST16 instruction */
49 /* Macros used in the machine description to select various Xtensa
50 configuration options. */
51 #define TARGET_BIG_ENDIAN XCHAL_HAVE_BE
52 #define TARGET_DENSITY XCHAL_HAVE_DENSITY
53 #define TARGET_MAC16 XCHAL_HAVE_MAC16
54 #define TARGET_MUL16 XCHAL_HAVE_MUL16
55 #define TARGET_MUL32 XCHAL_HAVE_MUL32
56 #define TARGET_DIV32 XCHAL_HAVE_DIV32
57 #define TARGET_NSA XCHAL_HAVE_NSA
58 #define TARGET_MINMAX XCHAL_HAVE_MINMAX
59 #define TARGET_SEXT XCHAL_HAVE_SEXT
60 #define TARGET_BOOLEANS XCHAL_HAVE_BOOLEANS
61 #define TARGET_HARD_FLOAT XCHAL_HAVE_FP
62 #define TARGET_HARD_FLOAT_DIV XCHAL_HAVE_FP_DIV
63 #define TARGET_HARD_FLOAT_RECIP XCHAL_HAVE_FP_RECIP
64 #define TARGET_HARD_FLOAT_SQRT XCHAL_HAVE_FP_SQRT
65 #define TARGET_HARD_FLOAT_RSQRT XCHAL_HAVE_FP_RSQRT
66 #define TARGET_ABS XCHAL_HAVE_ABS
67 #define TARGET_ADDX XCHAL_HAVE_ADDX
69 /* Macros controlled by command-line options. */
70 #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD)
71 #define TARGET_CONST16 (target_flags & MASK_CONST16)
73 #define TARGET_DEFAULT ( \
74 (XCHAL_HAVE_L32R ? 0 : MASK_CONST16))
76 #define TARGET_SWITCHES \
78 {"const16", MASK_CONST16, \
79 N_("Use CONST16 instruction to load constants")}, \
80 {"no-const16", -MASK_CONST16, \
81 N_("Use PC-relative L32R instruction to load constants")}, \
82 {"no-fused-madd", MASK_NO_FUSED_MADD, \
83 N_("Disable fused multiply/add and multiply/subtract FP instructions")}, \
84 {"fused-madd", -MASK_NO_FUSED_MADD, \
85 N_("Enable fused multiply/add and multiply/subtract FP instructions")}, \
86 {"text-section-literals", 0, \
87 N_("Intersperse literal pools with code in the text section")}, \
88 {"no-text-section-literals", 0, \
89 N_("Put literal pools in a separate literal section")}, \
91 N_("Automatically align branch targets to reduce branch penalties")}, \
92 {"no-target-align", 0, \
93 N_("Do not automatically align branch targets")}, \
95 N_("Use indirect CALLXn instructions for large programs")}, \
97 N_("Use direct CALLn instructions for fast calls")}, \
98 {"", TARGET_DEFAULT, 0} \
102 #define OVERRIDE_OPTIONS override_options ()
104 /* Target CPU builtins. */
105 #define TARGET_CPU_CPP_BUILTINS() \
107 builtin_assert ("cpu=xtensa"); \
108 builtin_assert ("machine=xtensa"); \
109 builtin_define ("__XTENSA__"); \
110 builtin_define (TARGET_BIG_ENDIAN ? "__XTENSA_EB__" : "__XTENSA_EL__"); \
111 if (!TARGET_HARD_FLOAT) \
112 builtin_define ("__XTENSA_SOFT_FLOAT__"); \
115 builtin_define ("__PIC__"); \
116 builtin_define ("__pic__"); \
120 #define CPP_SPEC " %(subtarget_cpp_spec) "
122 #ifndef SUBTARGET_CPP_SPEC
123 #define SUBTARGET_CPP_SPEC ""
126 #define EXTRA_SPECS \
127 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC },
130 #define LIBGCC2_WORDS_BIG_ENDIAN 1
132 #define LIBGCC2_WORDS_BIG_ENDIAN 0
135 /* Show we can debug even without a frame pointer. */
136 #define CAN_DEBUG_WITHOUT_FP
139 /* Target machine storage layout */
141 /* Define this if most significant bit is lowest numbered
142 in instructions that operate on numbered bit-fields. */
143 #define BITS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
145 /* Define this if most significant byte of a word is the lowest numbered. */
146 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
148 /* Define this if most significant word of a multiword number is the lowest. */
149 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
151 #define MAX_BITS_PER_WORD 32
153 /* Width of a word, in units (bytes). */
154 #define UNITS_PER_WORD 4
155 #define MIN_UNITS_PER_WORD 4
157 /* Width of a floating point register. */
158 #define UNITS_PER_FPREG 4
160 /* Size in bits of various types on the target machine. */
161 #define INT_TYPE_SIZE 32
162 #define SHORT_TYPE_SIZE 16
163 #define LONG_TYPE_SIZE 32
164 #define MAX_LONG_TYPE_SIZE 32
165 #define LONG_LONG_TYPE_SIZE 64
166 #define FLOAT_TYPE_SIZE 32
167 #define DOUBLE_TYPE_SIZE 64
168 #define LONG_DOUBLE_TYPE_SIZE 64
170 /* Allocation boundary (in *bits*) for storing pointers in memory. */
171 #define POINTER_BOUNDARY 32
173 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
174 #define PARM_BOUNDARY 32
176 /* Allocation boundary (in *bits*) for the code of a function. */
177 #define FUNCTION_BOUNDARY 32
179 /* Alignment of field after 'int : 0' in a structure. */
180 #define EMPTY_FIELD_BOUNDARY 32
182 /* Every structure's size must be a multiple of this. */
183 #define STRUCTURE_SIZE_BOUNDARY 8
185 /* There is no point aligning anything to a rounder boundary than this. */
186 #define BIGGEST_ALIGNMENT 128
188 /* Set this nonzero if move instructions will actually fail to work
189 when given unaligned data. */
190 #define STRICT_ALIGNMENT 1
192 /* Promote integer modes smaller than a word to SImode. Set UNSIGNEDP
193 for QImode, because there is no 8-bit load from memory with sign
194 extension. Otherwise, leave UNSIGNEDP alone, since Xtensa has 16-bit
195 loads both with and without sign extension. */
196 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
198 if (GET_MODE_CLASS (MODE) == MODE_INT \
199 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
201 if ((MODE) == QImode) \
207 /* The promotion described by `PROMOTE_MODE' should also be done for
208 outgoing function arguments. */
209 #define PROMOTE_FUNCTION_ARGS
211 /* The promotion described by `PROMOTE_MODE' should also be done for
212 the return value of functions. Note: `FUNCTION_VALUE' must perform
213 the same promotions done by `PROMOTE_MODE'. */
214 #define PROMOTE_FUNCTION_RETURN
216 /* Imitate the way many other C compilers handle alignment of
217 bitfields and the structures that contain them. */
218 #define PCC_BITFIELD_TYPE_MATTERS 1
220 /* Align string constants and constructors to at least a word boundary.
221 The typical use of this macro is to increase alignment for string
222 constants to be word aligned so that 'strcpy' calls that copy
223 constants can be done inline. */
224 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
225 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
226 && (ALIGN) < BITS_PER_WORD \
230 /* Align arrays, unions and records to at least a word boundary.
231 One use of this macro is to increase alignment of medium-size
232 data to make it all fit in fewer cache lines. Another is to
233 cause character arrays to be word-aligned so that 'strcpy' calls
234 that copy constants to character arrays can be done inline. */
235 #undef DATA_ALIGNMENT
236 #define DATA_ALIGNMENT(TYPE, ALIGN) \
237 ((((ALIGN) < BITS_PER_WORD) \
238 && (TREE_CODE (TYPE) == ARRAY_TYPE \
239 || TREE_CODE (TYPE) == UNION_TYPE \
240 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
242 /* An argument declared as 'char' or 'short' in a prototype should
243 actually be passed as an 'int'. */
244 #define PROMOTE_PROTOTYPES 1
246 /* Operations between registers always perform the operation
247 on the full register even if a narrower mode is specified. */
248 #define WORD_REGISTER_OPERATIONS
250 /* Xtensa loads are zero-extended by default. */
251 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
253 /* Standard register usage. */
255 /* Number of actual hardware registers.
256 The hardware registers are assigned numbers for the compiler
257 from 0 to just below FIRST_PSEUDO_REGISTER.
258 All registers that the compiler knows about must be given numbers,
259 even those that are not normally considered general registers.
261 The fake frame pointer and argument pointer will never appear in
262 the generated code, since they will always be eliminated and replaced
263 by either the stack pointer or the hard frame pointer.
265 0 - 15 AR[0] - AR[15]
266 16 FRAME_POINTER (fake = initial sp)
267 17 ARG_POINTER (fake = initial sp + framesize)
268 18 BR[0] for floating-point CC
269 19 - 34 FR[0] - FR[15]
270 35 MAC16 accumulator */
272 #define FIRST_PSEUDO_REGISTER 36
274 /* Return the stabs register number to use for REGNO. */
275 #define DBX_REGISTER_NUMBER(REGNO) xtensa_dbx_register_number (REGNO)
277 /* 1 for registers that have pervasive standard uses
278 and are not available for the register allocator. */
279 #define FIXED_REGISTERS \
281 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
283 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
287 /* 1 for registers not available across function calls.
288 These must include the FIXED_REGISTERS and also any
289 registers that can be used without being saved.
290 The latter must include the registers where values are returned
291 and the register where structure-value addresses are passed.
292 Aside from that, you can include as many other registers as you like. */
293 #define CALL_USED_REGISTERS \
295 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
297 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
301 /* For non-leaf procedures on Xtensa processors, the allocation order
302 is as specified below by REG_ALLOC_ORDER. For leaf procedures, we
303 want to use the lowest numbered registers first to minimize
304 register window overflows. However, local-alloc is not smart
305 enough to consider conflicts with incoming arguments. If an
306 incoming argument in a2 is live throughout the function and
307 local-alloc decides to use a2, then the incoming argument must
308 either be spilled or copied to another register. To get around
309 this, we define ORDER_REGS_FOR_LOCAL_ALLOC to redefine
310 reg_alloc_order for leaf functions such that lowest numbered
311 registers are used first with the exception that the incoming
312 argument registers are not used until after other register choices
313 have been exhausted. */
315 #define REG_ALLOC_ORDER \
316 { 8, 9, 10, 11, 12, 13, 14, 15, 7, 6, 5, 4, 3, 2, \
318 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, \
323 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
325 /* For Xtensa, the only point of this is to prevent GCC from otherwise
326 giving preference to call-used registers. To minimize window
327 overflows for the AR registers, we want to give preference to the
328 lower-numbered AR registers. For other register files, which are
329 not windowed, we still prefer call-used registers, if there are any. */
330 extern const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER];
331 #define LEAF_REGISTERS xtensa_leaf_regs
333 /* For Xtensa, no remapping is necessary, but this macro must be
334 defined if LEAF_REGISTERS is defined. */
335 #define LEAF_REG_REMAP(REGNO) (REGNO)
337 /* this must be declared if LEAF_REGISTERS is set */
338 extern int leaf_function;
340 /* Internal macros to classify a register number. */
342 /* 16 address registers + fake registers */
343 #define GP_REG_FIRST 0
344 #define GP_REG_LAST 17
345 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
347 /* Coprocessor registers */
348 #define BR_REG_FIRST 18
349 #define BR_REG_LAST 18
350 #define BR_REG_NUM (BR_REG_LAST - BR_REG_FIRST + 1)
352 /* 16 floating-point registers */
353 #define FP_REG_FIRST 19
354 #define FP_REG_LAST 34
355 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
357 /* MAC16 accumulator */
358 #define ACC_REG_FIRST 35
359 #define ACC_REG_LAST 35
360 #define ACC_REG_NUM (ACC_REG_LAST - ACC_REG_FIRST + 1)
362 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
363 #define BR_REG_P(REGNO) ((unsigned) ((REGNO) - BR_REG_FIRST) < BR_REG_NUM)
364 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
365 #define ACC_REG_P(REGNO) ((unsigned) ((REGNO) - ACC_REG_FIRST) < ACC_REG_NUM)
367 /* Return number of consecutive hard regs needed starting at reg REGNO
368 to hold something of mode MODE. */
369 #define HARD_REGNO_NREGS(REGNO, MODE) \
370 (FP_REG_P (REGNO) ? \
371 ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG) : \
372 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
374 /* Value is 1 if hard register REGNO can hold a value of machine-mode
376 extern char xtensa_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
378 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
379 xtensa_hard_regno_mode_ok[(int) (MODE)][(REGNO)]
381 /* Value is 1 if it is a good idea to tie two pseudo registers
382 when one has mode MODE1 and one has mode MODE2.
383 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
384 for any hard reg, then this must be 0 for correct output. */
385 #define MODES_TIEABLE_P(MODE1, MODE2) \
386 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
387 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
388 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
389 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
391 /* Register to use for pushing function arguments. */
392 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 1)
394 /* Base register for access to local variables of the function. */
395 #define HARD_FRAME_POINTER_REGNUM (GP_REG_FIRST + 7)
397 /* The register number of the frame pointer register, which is used to
398 access automatic variables in the stack frame. For Xtensa, this
399 register never appears in the output. It is always eliminated to
400 either the stack pointer or the hard frame pointer. */
401 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 16)
403 /* Value should be nonzero if functions must have frame pointers.
404 Zero means the frame pointer need not be set up (and parms
405 may be accessed via the stack pointer) in functions that seem suitable.
406 This is computed in 'reload', in reload1.c. */
407 #define FRAME_POINTER_REQUIRED xtensa_frame_pointer_required ()
409 /* Base register for access to arguments of the function. */
410 #define ARG_POINTER_REGNUM (GP_REG_FIRST + 17)
412 /* If the static chain is passed in memory, these macros provide rtx
413 giving 'mem' expressions that denote where they are stored.
414 'STATIC_CHAIN' and 'STATIC_CHAIN_INCOMING' give the locations as
415 seen by the calling and called functions, respectively. */
417 #define STATIC_CHAIN \
418 gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, -5 * UNITS_PER_WORD))
420 #define STATIC_CHAIN_INCOMING \
421 gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -5 * UNITS_PER_WORD))
423 /* For now we don't try to use the full set of boolean registers. Without
424 software pipelining of FP operations, there's not much to gain and it's
425 a real pain to get them reloaded. */
426 #define FPCC_REGNUM (BR_REG_FIRST + 0)
428 /* Pass structure value address as an "invisible" first argument. */
429 #define STRUCT_VALUE 0
431 /* It is as good or better to call a constant function address than to
432 call an address kept in a register. */
433 #define NO_FUNCTION_CSE 1
435 /* It is as good or better for a function to call itself with an
436 explicit address than to call an address kept in a register. */
437 #define NO_RECURSIVE_FUNCTION_CSE 1
439 /* Xtensa processors have "register windows". GCC does not currently
440 take advantage of the possibility for variable-sized windows; instead,
441 we use a fixed window size of 8. */
443 #define INCOMING_REGNO(OUT) \
444 ((GP_REG_P (OUT) && \
445 ((unsigned) ((OUT) - GP_REG_FIRST) >= WINDOW_SIZE)) ? \
446 (OUT) - WINDOW_SIZE : (OUT))
448 #define OUTGOING_REGNO(IN) \
450 ((unsigned) ((IN) - GP_REG_FIRST) < WINDOW_SIZE)) ? \
451 (IN) + WINDOW_SIZE : (IN))
454 /* Define the classes of registers for register constraints in the
455 machine description. */
458 NO_REGS, /* no registers in set */
459 BR_REGS, /* coprocessor boolean registers */
460 FP_REGS, /* floating point registers */
461 ACC_REG, /* MAC16 accumulator */
462 SP_REG, /* sp register (aka a1) */
463 RL_REGS, /* preferred reload regs (not sp or fp) */
464 GR_REGS, /* integer registers except sp */
465 AR_REGS, /* all integer registers */
466 ALL_REGS, /* all registers */
467 LIM_REG_CLASSES /* max value + 1 */
470 #define N_REG_CLASSES (int) LIM_REG_CLASSES
472 #define GENERAL_REGS AR_REGS
474 /* An initializer containing the names of the register classes as C
475 string constants. These names are used in writing some of the
477 #define REG_CLASS_NAMES \
490 /* Contents of the register classes. The Nth integer specifies the
491 contents of class N. The way the integer MASK is interpreted is
492 that register R is in the class if 'MASK & (1 << R)' is 1. */
493 #define REG_CLASS_CONTENTS \
495 { 0x00000000, 0x00000000 }, /* no registers */ \
496 { 0x00040000, 0x00000000 }, /* coprocessor boolean registers */ \
497 { 0xfff80000, 0x00000007 }, /* floating-point registers */ \
498 { 0x00000000, 0x00000008 }, /* MAC16 accumulator */ \
499 { 0x00000002, 0x00000000 }, /* stack pointer register */ \
500 { 0x0000ff7d, 0x00000000 }, /* preferred reload registers */ \
501 { 0x0000fffd, 0x00000000 }, /* general-purpose registers */ \
502 { 0x0003ffff, 0x00000000 }, /* integer registers */ \
503 { 0xffffffff, 0x0000000f } /* all registers */ \
506 /* A C expression whose value is a register class containing hard
507 register REGNO. In general there is more that one such class;
508 choose a class which is "minimal", meaning that no smaller class
509 also contains the register. */
510 extern const enum reg_class xtensa_regno_to_class[FIRST_PSEUDO_REGISTER];
512 #define REGNO_REG_CLASS(REGNO) xtensa_regno_to_class[ (REGNO) ]
514 /* Use the Xtensa AR register file for base registers.
515 No index registers. */
516 #define BASE_REG_CLASS AR_REGS
517 #define INDEX_REG_CLASS NO_REGS
519 /* SMALL_REGISTER_CLASSES is required for Xtensa, because all of the
520 16 AR registers may be explicitly used in the RTL, as either
521 incoming or outgoing arguments. */
522 #define SMALL_REGISTER_CLASSES 1
525 /* REGISTER AND CONSTANT CLASSES */
527 /* Get reg_class from a letter such as appears in the machine
530 Available letters: a-f,h,j-l,q,t-z,A-D,W,Y-Z
532 DEFINED REGISTER CLASSES:
534 'a' general-purpose registers except sp
536 'D' general-purpose registers (only if density option enabled)
537 'd' general-purpose registers, including sp (only if density enabled)
538 'A' MAC16 accumulator (only if MAC16 option enabled)
539 'B' general-purpose registers (only if sext instruction enabled)
540 'C' general-purpose registers (only if mul16 option enabled)
541 'W' general-purpose registers (only if const16 option enabled)
542 'b' coprocessor boolean registers
543 'f' floating-point registers
546 extern enum reg_class xtensa_char_to_class[256];
548 #define REG_CLASS_FROM_LETTER(C) xtensa_char_to_class[ (int) (C) ]
550 /* The letters I, J, K, L, M, N, O, and P in a register constraint
551 string can be used to stand for particular ranges of immediate
552 operands. This macro defines what the ranges are. C is the
553 letter, and VALUE is a constant value. Return 1 if VALUE is
554 in the range specified by C.
558 I = 12-bit signed immediate for movi
559 J = 8-bit signed immediate for addi
560 K = 4-bit value in (b4const U {0})
561 L = 4-bit value in b4constu
562 M = 7-bit value in simm7
563 N = 8-bit unsigned immediate shifted left by 8 bits for addmi
564 O = 4-bit value in ai4const
565 P = valid immediate mask value for extui */
567 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
568 ((C) == 'I' ? (xtensa_simm12b (VALUE)) \
569 : (C) == 'J' ? (xtensa_simm8 (VALUE)) \
570 : (C) == 'K' ? (((VALUE) == 0) || xtensa_b4const (VALUE)) \
571 : (C) == 'L' ? (xtensa_b4constu (VALUE)) \
572 : (C) == 'M' ? (xtensa_simm7 (VALUE)) \
573 : (C) == 'N' ? (xtensa_simm8x256 (VALUE)) \
574 : (C) == 'O' ? (xtensa_ai4const (VALUE)) \
575 : (C) == 'P' ? (xtensa_mask_immediate (VALUE)) \
579 /* Similar, but for floating constants, and defining letters G and H.
580 Here VALUE is the CONST_DOUBLE rtx itself. */
581 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) (0)
584 /* Other letters can be defined in a machine-dependent fashion to
585 stand for particular classes of registers or other arbitrary
588 R = memory that can be accessed with a 4-bit unsigned offset
589 T = memory in a constant pool (addressable with a pc-relative load)
590 U = memory *NOT* in a constant pool
592 The offset range should not be checked here (except to distinguish
593 denser versions of the instructions for which more general versions
594 are available). Doing so leads to problems in reloading: an
595 argptr-relative address may become invalid when the phony argptr is
596 eliminated in favor of the stack pointer (the offset becomes too
597 large to fit in the instruction's immediate field); a reload is
598 generated to fix this but the RTL is not immediately updated; in
599 the meantime, the constraints are checked and none match. The
600 solution seems to be to simply skip the offset check here. The
601 address will be checked anyway because of the code in
602 GO_IF_LEGITIMATE_ADDRESS. */
604 #define EXTRA_CONSTRAINT(OP, CODE) \
605 ((GET_CODE (OP) != MEM) ? \
606 ((CODE) >= 'R' && (CODE) <= 'U' \
607 && reload_in_progress && GET_CODE (OP) == REG \
608 && REGNO (OP) >= FIRST_PSEUDO_REGISTER) \
609 : ((CODE) == 'R') ? smalloffset_mem_p (OP) \
610 : ((CODE) == 'T') ? !TARGET_CONST16 && constantpool_mem_p (OP) \
611 : ((CODE) == 'U') ? !constantpool_mem_p (OP) \
614 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
615 xtensa_preferred_reload_class (X, CLASS, 0)
617 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
618 xtensa_preferred_reload_class (X, CLASS, 1)
620 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
621 xtensa_secondary_reload_class (CLASS, MODE, X, 0)
623 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
624 xtensa_secondary_reload_class (CLASS, MODE, X, 1)
626 /* Return the maximum number of consecutive registers
627 needed to represent mode MODE in a register of class CLASS. */
628 #define CLASS_UNITS(mode, size) \
629 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
631 #define CLASS_MAX_NREGS(CLASS, MODE) \
632 (CLASS_UNITS (MODE, UNITS_PER_WORD))
635 /* Stack layout; function entry, exit and calling. */
637 #define STACK_GROWS_DOWNWARD
639 /* Offset within stack frame to start allocating local variables at. */
640 #define STARTING_FRAME_OFFSET \
641 current_function_outgoing_args_size
643 /* The ARG_POINTER and FRAME_POINTER are not real Xtensa registers, so
644 they are eliminated to either the stack pointer or hard frame pointer. */
645 #define ELIMINABLE_REGS \
646 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
647 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
648 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
649 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
651 #define CAN_ELIMINATE(FROM, TO) 1
653 /* Specify the initial difference between the specified pair of registers. */
654 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
656 compute_frame_size (get_frame_size ()); \
657 if ((FROM) == FRAME_POINTER_REGNUM) \
659 else if ((FROM) == ARG_POINTER_REGNUM) \
660 (OFFSET) = xtensa_current_frame_size; \
665 /* If defined, the maximum amount of space required for outgoing
666 arguments will be computed and placed into the variable
667 'current_function_outgoing_args_size'. No space will be pushed
668 onto the stack for each call; instead, the function prologue
669 should increase the stack frame size by this amount. */
670 #define ACCUMULATE_OUTGOING_ARGS 1
672 /* Offset from the argument pointer register to the first argument's
673 address. On some machines it may depend on the data type of the
674 function. If 'ARGS_GROW_DOWNWARD', this is the offset to the
675 location above the first argument's address. */
676 #define FIRST_PARM_OFFSET(FNDECL) 0
678 /* Align stack frames on 128 bits for Xtensa. This is necessary for
679 128-bit datatypes defined in TIE (e.g., for Vectra). */
680 #define STACK_BOUNDARY 128
682 /* Functions do not pop arguments off the stack. */
683 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
685 /* Use a fixed register window size of 8. */
686 #define WINDOW_SIZE 8
688 /* Symbolic macros for the registers used to return integer, floating
689 point, and values of coprocessor and user-defined modes. */
690 #define GP_RETURN (GP_REG_FIRST + 2 + WINDOW_SIZE)
691 #define GP_OUTGOING_RETURN (GP_REG_FIRST + 2)
693 /* Symbolic macros for the first/last argument registers. */
694 #define GP_ARG_FIRST (GP_REG_FIRST + 2)
695 #define GP_ARG_LAST (GP_REG_FIRST + 7)
696 #define GP_OUTGOING_ARG_FIRST (GP_REG_FIRST + 2 + WINDOW_SIZE)
697 #define GP_OUTGOING_ARG_LAST (GP_REG_FIRST + 7 + WINDOW_SIZE)
699 #define MAX_ARGS_IN_REGISTERS 6
701 /* Don't worry about compatibility with PCC. */
702 #define DEFAULT_PCC_STRUCT_RETURN 0
704 /* For Xtensa, up to 4 words can be returned in registers. (It would
705 have been nice to allow up to 6 words in registers but GCC cannot
706 support that. The return value must be given one of the standard
707 MODE_INT modes, and there is no 6 word mode. Instead, if we try to
708 return a 6 word structure, GCC selects the next biggest mode
709 (OImode, 8 words) and then the register allocator fails because
710 there is no 8-register group beginning with a10.) */
711 #define RETURN_IN_MEMORY(TYPE) \
712 ((unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) > 4 * UNITS_PER_WORD)
714 /* Define how to find the value returned by a library function
715 assuming the value has mode MODE. Because we have defined
716 PROMOTE_FUNCTION_RETURN, we have to perform the same promotions as
718 #define XTENSA_LIBCALL_VALUE(MODE, OUTGOINGP) \
719 gen_rtx_REG ((GET_MODE_CLASS (MODE) == MODE_INT \
720 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
722 OUTGOINGP ? GP_OUTGOING_RETURN : GP_RETURN)
724 #define LIBCALL_VALUE(MODE) \
725 XTENSA_LIBCALL_VALUE ((MODE), 0)
727 #define LIBCALL_OUTGOING_VALUE(MODE) \
728 XTENSA_LIBCALL_VALUE ((MODE), 1)
730 /* Define how to find the value returned by a function.
731 VALTYPE is the data type of the value (as a tree).
732 If the precise function being called is known, FUNC is its FUNCTION_DECL;
733 otherwise, FUNC is 0. */
734 #define XTENSA_FUNCTION_VALUE(VALTYPE, FUNC, OUTGOINGP) \
735 gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \
736 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
737 ? SImode: TYPE_MODE (VALTYPE), \
738 OUTGOINGP ? GP_OUTGOING_RETURN : GP_RETURN)
740 #define FUNCTION_VALUE(VALTYPE, FUNC) \
741 XTENSA_FUNCTION_VALUE (VALTYPE, FUNC, 0)
743 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
744 XTENSA_FUNCTION_VALUE (VALTYPE, FUNC, 1)
746 /* A C expression that is nonzero if REGNO is the number of a hard
747 register in which the values of called function may come back. A
748 register whose use for returning values is limited to serving as
749 the second of a pair (for a value of type 'double', say) need not
750 be recognized by this macro. If the machine has register windows,
751 so that the caller and the called function use different registers
752 for the return value, this macro should recognize only the caller's
754 #define FUNCTION_VALUE_REGNO_P(N) \
757 /* A C expression that is nonzero if REGNO is the number of a hard
758 register in which function arguments are sometimes passed. This
759 does *not* include implicit arguments such as the static chain and
760 the structure-value address. On many machines, no registers can be
761 used for this purpose since all function arguments are pushed on
763 #define FUNCTION_ARG_REGNO_P(N) \
764 ((N) >= GP_OUTGOING_ARG_FIRST && (N) <= GP_OUTGOING_ARG_LAST)
766 /* Define a data type for recording info about an argument list
767 during the scan of that argument list. This data type should
768 hold all necessary information about the function itself
769 and about the args processed so far, enough to enable macros
770 such as FUNCTION_ARG to determine where the next arg should go. */
771 typedef struct xtensa_args {
772 int arg_words; /* # total words the arguments take */
775 /* Initialize a variable CUM of type CUMULATIVE_ARGS
776 for a call to a function whose data type is FNTYPE.
777 For a library call, FNTYPE is 0. */
778 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
779 init_cumulative_args (&CUM, FNTYPE, LIBNAME)
781 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
782 init_cumulative_args (&CUM, FNTYPE, LIBNAME)
784 /* Update the data in CUM to advance over an argument
785 of mode MODE and data type TYPE.
786 (TYPE is null for libcalls where that information may not be available.) */
787 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
788 function_arg_advance (&CUM, MODE, TYPE)
790 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
791 function_arg (&CUM, MODE, TYPE, FALSE)
793 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
794 function_arg (&CUM, MODE, TYPE, TRUE)
796 /* Arguments are never passed partly in memory and partly in registers. */
797 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) (0)
799 /* Specify function argument alignment. */
800 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
802 ? (TYPE_ALIGN (TYPE) <= PARM_BOUNDARY \
804 : TYPE_ALIGN (TYPE)) \
805 : (GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY \
807 : GET_MODE_ALIGNMENT (MODE)))
810 /* Nonzero if we do not know how to pass TYPE solely in registers.
811 We cannot do so in the following cases:
813 - if the type has variable size
814 - if the type is marked as addressable (it is required to be constructed
817 This differs from the default in that it does not check if the padding
818 and mode of the type are such that a copy into a register would put it
819 into the wrong part of the register. */
821 #define MUST_PASS_IN_STACK(MODE, TYPE) \
823 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
824 || TREE_ADDRESSABLE (TYPE)))
826 /* Profiling Xtensa code is typically done with the built-in profiling
827 feature of Tensilica's instruction set simulator, which does not
828 require any compiler support. Profiling code on a real (i.e.,
829 non-simulated) Xtensa processor is currently only supported by
830 GNU/Linux with glibc. The glibc version of _mcount doesn't require
831 counter variables. The _mcount function needs the current PC and
832 the current return address to identify an arc in the call graph.
833 Pass the current return address as the first argument; the current
834 PC is available as a0 in _mcount's register window. Both of these
835 values contain window size information in the two most significant
836 bits; we assume that _mcount will mask off those bits. The call to
837 _mcount uses a window size of 8 to make sure that it doesn't clobber
838 any incoming argument values. */
840 #define NO_PROFILE_COUNTERS 1
842 #define FUNCTION_PROFILER(FILE, LABELNO) \
844 fprintf (FILE, "\t%s\ta10, a0\n", TARGET_DENSITY ? "mov.n" : "mov"); \
847 fprintf (FILE, "\tmovi\ta8, _mcount@PLT\n"); \
848 fprintf (FILE, "\tcallx8\ta8\n"); \
851 fprintf (FILE, "\tcall8\t_mcount\n"); \
854 /* Stack pointer value doesn't matter at exit. */
855 #define EXIT_IGNORE_STACK 1
857 /* A C statement to output, on the stream FILE, assembler code for a
858 block of data that contains the constant parts of a trampoline.
859 This code should not include a label--the label is taken care of
862 For Xtensa, the trampoline must perform an entry instruction with a
863 minimal stack frame in order to get some free registers. Once the
864 actual call target is known, the proper stack frame size is extracted
865 from the entry instruction at the target and the current frame is
866 adjusted to match. The trampoline then transfers control to the
867 instruction following the entry at the target. Note: this assumes
868 that the target begins with an entry instruction. */
870 /* minimum frame = reg save area (4 words) plus static chain (1 word)
871 and the total number of words must be a multiple of 128 bits */
872 #define MIN_FRAME_SIZE (8 * UNITS_PER_WORD)
874 #define TRAMPOLINE_TEMPLATE(STREAM) \
876 fprintf (STREAM, "\t.begin no-generics\n"); \
877 fprintf (STREAM, "\tentry\tsp, %d\n", MIN_FRAME_SIZE); \
879 /* save the return address */ \
880 fprintf (STREAM, "\tmov\ta10, a0\n"); \
882 /* Use a CALL0 instruction to skip past the constants and in the \
883 process get the PC into A0. This allows PC-relative access to \
884 the constants without relying on L32R, which may not always be \
887 fprintf (STREAM, "\tcall0\t.Lskipconsts\n"); \
888 fprintf (STREAM, "\t.align\t4\n"); \
889 fprintf (STREAM, ".Lchainval:%s0\n", integer_asm_op (4, TRUE)); \
890 fprintf (STREAM, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE)); \
891 fprintf (STREAM, ".Lskipconsts:\n"); \
893 /* store the static chain */ \
894 fprintf (STREAM, "\taddi\ta0, a0, 3\n"); \
895 fprintf (STREAM, "\tl32i\ta8, a0, 0\n"); \
896 fprintf (STREAM, "\ts32i\ta8, sp, %d\n", MIN_FRAME_SIZE - 20); \
898 /* set the proper stack pointer value */ \
899 fprintf (STREAM, "\tl32i\ta8, a0, 4\n"); \
900 fprintf (STREAM, "\tl32i\ta9, a8, 0\n"); \
901 fprintf (STREAM, "\textui\ta9, a9, %d, 12\n", \
902 TARGET_BIG_ENDIAN ? 8 : 12); \
903 fprintf (STREAM, "\tslli\ta9, a9, 3\n"); \
904 fprintf (STREAM, "\taddi\ta9, a9, %d\n", -MIN_FRAME_SIZE); \
905 fprintf (STREAM, "\tsub\ta9, sp, a9\n"); \
906 fprintf (STREAM, "\tmovsp\tsp, a9\n"); \
908 /* restore the return address */ \
909 fprintf (STREAM, "\tmov\ta0, a10\n"); \
911 /* jump to the instruction following the entry */ \
912 fprintf (STREAM, "\taddi\ta8, a8, 3\n"); \
913 fprintf (STREAM, "\tjx\ta8\n"); \
914 fprintf (STREAM, "\t.end no-generics\n"); \
917 /* Size in bytes of the trampoline, as an integer. */
918 #define TRAMPOLINE_SIZE 59
920 /* Alignment required for trampolines, in bits. */
921 #define TRAMPOLINE_ALIGNMENT (32)
923 /* A C statement to initialize the variable parts of a trampoline. */
924 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
927 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 12)), CHAIN); \
928 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 16)), FUNC); \
929 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__xtensa_sync_caches"), \
930 0, VOIDmode, 1, addr, Pmode); \
933 /* Define the `__builtin_va_list' type for the ABI. */
934 #define BUILD_VA_LIST_TYPE(VALIST) \
935 (VALIST) = xtensa_build_va_list ()
937 /* If defined, is a C expression that produces the machine-specific
938 code for a call to '__builtin_saveregs'. This code will be moved
939 to the very beginning of the function, before any parameter access
940 are made. The return value of this function should be an RTX that
941 contains the value to use as the return of '__builtin_saveregs'. */
942 #define EXPAND_BUILTIN_SAVEREGS \
943 xtensa_builtin_saveregs
945 /* Implement `va_start' for varargs and stdarg. */
946 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
947 xtensa_va_start (valist, nextarg)
949 /* Implement `va_arg'. */
950 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
951 xtensa_va_arg (valist, type)
953 /* If defined, a C expression that produces the machine-specific code
954 to setup the stack so that arbitrary frames can be accessed.
956 On Xtensa, a stack back-trace must always begin from the stack pointer,
957 so that the register overflow save area can be located. However, the
958 stack-walking code in GCC always begins from the hard_frame_pointer
959 register, not the stack pointer. The frame pointer is usually equal
960 to the stack pointer, but the __builtin_return_address and
961 __builtin_frame_address functions will not work if count > 0 and
962 they are called from a routine that uses alloca. These functions
963 are not guaranteed to work at all if count > 0 so maybe that is OK.
965 A nicer solution would be to allow the architecture-specific files to
966 specify whether to start from the stack pointer or frame pointer. That
967 would also allow us to skip the machine->accesses_prev_frame stuff that
968 we currently need to ensure that there is a frame pointer when these
969 builtin functions are used. */
971 #define SETUP_FRAME_ADDRESSES xtensa_setup_frame_addresses
973 /* A C expression whose value is RTL representing the address in a
974 stack frame where the pointer to the caller's frame is stored.
975 Assume that FRAMEADDR is an RTL expression for the address of the
978 For Xtensa, there is no easy way to get the frame pointer if it is
979 not equivalent to the stack pointer. Moreover, the result of this
980 macro is used for continuing to walk back up the stack, so it must
981 return the stack pointer address. Thus, there is some inconsistency
982 here in that __builtin_frame_address will return the frame pointer
983 when count == 0 and the stack pointer when count > 0. */
985 #define DYNAMIC_CHAIN_ADDRESS(frame) \
986 gen_rtx (PLUS, Pmode, frame, \
987 gen_rtx_CONST_INT (VOIDmode, -3 * UNITS_PER_WORD))
989 /* Define this if the return address of a particular stack frame is
990 accessed from the frame pointer of the previous stack frame. */
991 #define RETURN_ADDR_IN_PREVIOUS_FRAME
993 /* A C expression whose value is RTL representing the value of the
994 return address for the frame COUNT steps up from the current
995 frame, after the prologue. */
996 #define RETURN_ADDR_RTX xtensa_return_addr
998 /* Addressing modes, and classification of registers for them. */
1000 /* C expressions which are nonzero if register number NUM is suitable
1001 for use as a base or index register in operand addresses. It may
1002 be either a suitable hard register or a pseudo register that has
1003 been allocated such a hard register. The difference between an
1004 index register and a base register is that the index register may
1007 #define REGNO_OK_FOR_BASE_P(NUM) \
1008 (GP_REG_P (NUM) || GP_REG_P ((unsigned) reg_renumber[NUM]))
1010 #define REGNO_OK_FOR_INDEX_P(NUM) 0
1012 /* C expressions that are nonzero if X (assumed to be a `reg' RTX) is
1013 valid for use as a base or index register. For hard registers, it
1014 should always accept those which the hardware permits and reject
1015 the others. Whether the macro accepts or rejects pseudo registers
1016 must be controlled by `REG_OK_STRICT'. This usually requires two
1017 variant definitions, of which `REG_OK_STRICT' controls the one
1018 actually used. The difference between an index register and a base
1019 register is that the index register may be scaled. */
1021 #ifdef REG_OK_STRICT
1023 #define REG_OK_FOR_INDEX_P(X) 0
1024 #define REG_OK_FOR_BASE_P(X) \
1025 REGNO_OK_FOR_BASE_P (REGNO (X))
1027 #else /* !REG_OK_STRICT */
1029 #define REG_OK_FOR_INDEX_P(X) 0
1030 #define REG_OK_FOR_BASE_P(X) \
1031 ((REGNO (X) >= FIRST_PSEUDO_REGISTER) || (GP_REG_P (REGNO (X))))
1033 #endif /* !REG_OK_STRICT */
1035 /* Maximum number of registers that can appear in a valid memory address. */
1036 #define MAX_REGS_PER_ADDRESS 1
1038 /* Identify valid Xtensa addresses. */
1039 #define GO_IF_LEGITIMATE_ADDRESS(MODE, ADDR, LABEL) \
1041 rtx xinsn = (ADDR); \
1043 /* allow constant pool addresses */ \
1044 if ((MODE) != BLKmode && GET_MODE_SIZE (MODE) >= UNITS_PER_WORD \
1045 && !TARGET_CONST16 && constantpool_address_p (xinsn)) \
1048 while (GET_CODE (xinsn) == SUBREG) \
1049 xinsn = SUBREG_REG (xinsn); \
1051 /* allow base registers */ \
1052 if (GET_CODE (xinsn) == REG && REG_OK_FOR_BASE_P (xinsn)) \
1055 /* check for "register + offset" addressing */ \
1056 if (GET_CODE (xinsn) == PLUS) \
1058 rtx xplus0 = XEXP (xinsn, 0); \
1059 rtx xplus1 = XEXP (xinsn, 1); \
1060 enum rtx_code code0; \
1061 enum rtx_code code1; \
1063 while (GET_CODE (xplus0) == SUBREG) \
1064 xplus0 = SUBREG_REG (xplus0); \
1065 code0 = GET_CODE (xplus0); \
1067 while (GET_CODE (xplus1) == SUBREG) \
1068 xplus1 = SUBREG_REG (xplus1); \
1069 code1 = GET_CODE (xplus1); \
1071 /* swap operands if necessary so the register is first */ \
1072 if (code0 != REG && code1 == REG) \
1074 xplus0 = XEXP (xinsn, 1); \
1075 xplus1 = XEXP (xinsn, 0); \
1076 code0 = GET_CODE (xplus0); \
1077 code1 = GET_CODE (xplus1); \
1080 if (code0 == REG && REG_OK_FOR_BASE_P (xplus0) \
1081 && code1 == CONST_INT \
1082 && xtensa_mem_offset (INTVAL (xplus1), (MODE))) \
1089 /* A C expression that is 1 if the RTX X is a constant which is a
1090 valid address. This is defined to be the same as 'CONSTANT_P (X)',
1091 but rejecting CONST_DOUBLE. */
1092 #define CONSTANT_ADDRESS_P(X) \
1093 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1094 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
1095 || (GET_CODE (X) == CONST)))
1097 /* Nonzero if the constant value X is a legitimate general operand.
1098 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1099 #define LEGITIMATE_CONSTANT_P(X) 1
1101 /* A C expression that is nonzero if X is a legitimate immediate
1102 operand on the target machine when generating position independent
1104 #define LEGITIMATE_PIC_OPERAND_P(X) \
1105 ((GET_CODE (X) != SYMBOL_REF || SYMBOL_REF_FLAG (X)) \
1106 && GET_CODE (X) != LABEL_REF \
1107 && GET_CODE (X) != CONST)
1109 /* Tell GCC how to use ADDMI to generate addresses. */
1110 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1113 if (GET_CODE (xinsn) == PLUS) \
1115 rtx plus0 = XEXP (xinsn, 0); \
1116 rtx plus1 = XEXP (xinsn, 1); \
1118 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG) \
1120 plus0 = XEXP (xinsn, 1); \
1121 plus1 = XEXP (xinsn, 0); \
1124 if (GET_CODE (plus0) == REG \
1125 && GET_CODE (plus1) == CONST_INT \
1126 && !xtensa_mem_offset (INTVAL (plus1), MODE) \
1127 && !xtensa_simm8 (INTVAL (plus1)) \
1128 && xtensa_mem_offset (INTVAL (plus1) & 0xff, MODE) \
1129 && xtensa_simm8x256 (INTVAL (plus1) & ~0xff)) \
1131 rtx temp = gen_reg_rtx (Pmode); \
1132 emit_insn (gen_rtx (SET, Pmode, temp, \
1133 gen_rtx (PLUS, Pmode, plus0, \
1134 GEN_INT (INTVAL (plus1) & ~0xff)))); \
1135 (X) = gen_rtx (PLUS, Pmode, temp, \
1136 GEN_INT (INTVAL (plus1) & 0xff)); \
1143 /* Treat constant-pool references as "mode dependent" since they can
1144 only be accessed with SImode loads. This works around a bug in the
1145 combiner where a constant pool reference is temporarily converted
1146 to an HImode load, which is then assumed to zero-extend based on
1147 our definition of LOAD_EXTEND_OP. This is wrong because the high
1148 bits of a 16-bit value in the constant pool are now sign-extended
1151 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1153 if (constantpool_address_p (ADDR)) \
1157 /* Specify the machine mode that this machine uses
1158 for the index in the tablejump instruction. */
1159 #define CASE_VECTOR_MODE (SImode)
1161 /* Define this if the tablejump instruction expects the table
1162 to contain offsets from the address of the table.
1163 Do not define this if the table should contain absolute addresses. */
1164 /* #define CASE_VECTOR_PC_RELATIVE */
1166 /* Define this as 1 if 'char' should by default be signed; else as 0. */
1167 #define DEFAULT_SIGNED_CHAR 0
1169 /* Max number of bytes we can move from memory to memory
1170 in one reasonably fast instruction. */
1172 #define MAX_MOVE_MAX 4
1174 /* Prefer word-sized loads. */
1175 #define SLOW_BYTE_ACCESS 1
1177 /* ??? Xtensa doesn't have any instructions that set integer values
1178 based on the results of comparisons, but the simplification code in
1179 the combiner also uses STORE_FLAG_VALUE. The default value (1) is
1180 fine for us, but (-1) might be better. */
1182 /* Shift instructions ignore all but the low-order few bits. */
1183 #define SHIFT_COUNT_TRUNCATED 1
1185 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1186 is done just by pretending it is already truncated. */
1187 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1189 /* Specify the machine mode that pointers have.
1190 After generation of rtl, the compiler makes no further distinction
1191 between pointers and any other objects of this machine mode. */
1192 #define Pmode SImode
1194 /* A function address in a call instruction is a word address (for
1195 indexing purposes) so give the MEM rtx a words's mode. */
1196 #define FUNCTION_MODE SImode
1198 /* A C expression for the cost of moving data from a register in
1199 class FROM to one in class TO. The classes are expressed using
1200 the enumeration values such as 'GENERAL_REGS'. A value of 2 is
1201 the default; other values are interpreted relative to that. */
1202 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1203 (((FROM) == (TO) && (FROM) != BR_REGS && (TO) != BR_REGS) \
1205 : (reg_class_subset_p ((FROM), AR_REGS) \
1206 && reg_class_subset_p ((TO), AR_REGS) \
1208 : (reg_class_subset_p ((FROM), AR_REGS) \
1209 && (TO) == ACC_REG \
1211 : ((FROM) == ACC_REG \
1212 && reg_class_subset_p ((TO), AR_REGS) \
1216 #define MEMORY_MOVE_COST(MODE, CLASS, IN) 4
1218 #define BRANCH_COST 3
1220 /* Optionally define this if you have added predicates to
1221 'MACHINE.c'. This macro is called within an initializer of an
1222 array of structures. The first field in the structure is the
1223 name of a predicate and the second field is an array of rtl
1224 codes. For each predicate, list all rtl codes that can be in
1225 expressions matched by the predicate. The list should have a
1228 #define PREDICATE_CODES \
1229 {"add_operand", { REG, CONST_INT, SUBREG }}, \
1230 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
1231 {"nonimmed_operand", { REG, SUBREG, MEM }}, \
1232 {"mem_operand", { MEM }}, \
1233 {"mask_operand", { REG, CONST_INT, SUBREG }}, \
1234 {"extui_fldsz_operand", { CONST_INT }}, \
1235 {"sext_fldsz_operand", { CONST_INT }}, \
1236 {"lsbitnum_operand", { CONST_INT }}, \
1237 {"fpmem_offset_operand", { CONST_INT }}, \
1238 {"sext_operand", { REG, SUBREG, MEM }}, \
1239 {"branch_operand", { REG, CONST_INT, SUBREG }}, \
1240 {"ubranch_operand", { REG, CONST_INT, SUBREG }}, \
1241 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG }}, \
1242 {"move_operand", { REG, SUBREG, MEM, CONST_INT, CONST_DOUBLE, \
1243 CONST, SYMBOL_REF, LABEL_REF }}, \
1244 {"const_float_1_operand", { CONST_DOUBLE }}, \
1245 {"branch_operator", { EQ, NE, LT, GE }}, \
1246 {"ubranch_operator", { LTU, GEU }}, \
1247 {"boolean_operator", { EQ, NE }},
1249 /* Control the assembler format that we output. */
1251 /* How to refer to registers in assembler output.
1252 This sequence is indexed by compiler's hard-register-number (see above). */
1253 #define REGISTER_NAMES \
1255 "a0", "sp", "a2", "a3", "a4", "a5", "a6", "a7", \
1256 "a8", "a9", "a10", "a11", "a12", "a13", "a14", "a15", \
1257 "fp", "argp", "b0", \
1258 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
1259 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
1263 /* If defined, a C initializer for an array of structures containing a
1264 name and a register number. This macro defines additional names
1265 for hard registers, thus allowing the 'asm' option in declarations
1266 to refer to registers using alternate names. */
1267 #define ADDITIONAL_REGISTER_NAMES \
1269 { "a1", 1 + GP_REG_FIRST } \
1272 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1273 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1275 /* Recognize machine-specific patterns that may appear within
1276 constants. Used for PIC-specific UNSPECs. */
1277 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
1279 if (flag_pic && GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
1281 switch (XINT ((X), 1)) \
1284 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
1285 fputs ("@PLT", (STREAM)); \
1296 /* Globalizing directive for a label. */
1297 #define GLOBAL_ASM_OP "\t.global\t"
1299 /* Declare an uninitialized external linkage data object. */
1300 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1301 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
1303 /* This is how to output an element of a case-vector that is absolute. */
1304 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
1305 fprintf (STREAM, "%s%sL%u\n", integer_asm_op (4, TRUE), \
1306 LOCAL_LABEL_PREFIX, VALUE)
1308 /* This is how to output an element of a case-vector that is relative.
1309 This is used for pc-relative code. */
1310 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
1312 fprintf (STREAM, "%s%sL%u-%sL%u\n", integer_asm_op (4, TRUE), \
1313 LOCAL_LABEL_PREFIX, (VALUE), \
1314 LOCAL_LABEL_PREFIX, (REL)); \
1317 /* This is how to output an assembler line that says to advance the
1318 location counter to a multiple of 2**LOG bytes. */
1319 #define ASM_OUTPUT_ALIGN(STREAM, LOG) \
1322 fprintf (STREAM, "\t.align\t%d\n", 1 << (LOG)); \
1325 /* Indicate that jump tables go in the text section. This is
1326 necessary when compiling PIC code. */
1327 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
1330 /* Define the strings to put out for each section in the object file. */
1331 #define TEXT_SECTION_ASM_OP "\t.text"
1332 #define DATA_SECTION_ASM_OP "\t.data"
1333 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
1336 /* Define output to appear before the constant pool. If the function
1337 has been assigned to a specific ELF section, or if it goes into a
1338 unique section, set the name of that section to be the literal
1340 #define ASM_OUTPUT_POOL_PROLOGUE(FILE, FUNNAME, FUNDECL, SIZE) \
1343 resolve_unique_section ((FUNDECL), 0, flag_function_sections); \
1344 fnsection = DECL_SECTION_NAME (FUNDECL); \
1345 if (fnsection != NULL_TREE) \
1347 const char *fnsectname = TREE_STRING_POINTER (fnsection); \
1348 fprintf (FILE, "\t.begin\tliteral_prefix %s\n", \
1349 strcmp (fnsectname, ".text") ? fnsectname : ""); \
1353 function_section (FUNDECL); \
1354 fprintf (FILE, "\t.literal_position\n"); \
1359 /* Define code to write out the ".end literal_prefix" directive for a
1360 function in a special section. This is appended to the standard ELF
1361 code for ASM_DECLARE_FUNCTION_SIZE. */
1362 #define XTENSA_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \
1363 if (DECL_SECTION_NAME (DECL) != NULL_TREE) \
1364 fprintf (FILE, "\t.end\tliteral_prefix\n")
1366 /* A C statement (with or without semicolon) to output a constant in
1367 the constant pool, if it needs special treatment. */
1368 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, JUMPTO) \
1370 xtensa_output_literal (FILE, X, MODE, LABELNO); \
1374 /* How to start an assembler comment. */
1375 #define ASM_COMMENT_START "#"
1377 /* Exception handling TODO!! */
1378 #define DWARF_UNWIND_INFO 0
1380 /* Xtensa constant pool breaks the devices in crtstuff.c to control
1381 section in where code resides. We have to write it as asm code. Use
1382 a MOVI and let the assembler relax it -- for the .init and .fini
1383 sections, the assembler knows to put the literal in the right
1385 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
1386 asm (SECTION_OP "\n\
1387 movi\ta8, " USER_LABEL_PREFIX #FUNC "\n\
1389 TEXT_SECTION_ASM_OP);
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